From 168a4cafc6c99e6a9e00d757b4231d3e5f50e0c4 Mon Sep 17 00:00:00 2001 From: Nathan Hartman <59230071+hartmannathan@users.noreply.github.com> Date: Fri, 22 May 2020 11:51:18 -0400 Subject: [PATCH] Add support for STM32G474: Modify existing files Add support for the STM32G474 family of microcontrollers and the B-G474E-DPOW1 Discovery Board, which features a STM32G474RET6. This is a major pull request as it adds support for an entirely new family of STM32. This support is implemented in arch/arm/src/stm32 and shares implementation with other STM32 families supported by that code, such as the 'L15xx, 'F10xx, 'F20xx, 'F3xxx, and 'F4xxx. arch/arm/Kconfig: arch/arm/include/stm32/chip.h: arch/arm/include/stm32/irq.h: arch/arm/src/stm32/Kconfig: arch/arm/src/stm32/hardware/stm32_adc.h: arch/arm/src/stm32/hardware/stm32_adc_v2.h: arch/arm/src/stm32/hardware/stm32_dma.h: arch/arm/src/stm32/hardware/stm32_dma_v1.h: arch/arm/src/stm32/hardware/stm32_flash.h: arch/arm/src/stm32/hardware/stm32_i2c.h: arch/arm/src/stm32/hardware/stm32_i2c_v2.h: arch/arm/src/stm32/hardware/stm32_memorymap.h: arch/arm/src/stm32/hardware/stm32_pinmap.h: arch/arm/src/stm32/hardware/stm32_tim.h: arch/arm/src/stm32/stm32_allocateheap.c: arch/arm/src/stm32/stm32_dma.c: arch/arm/src/stm32/stm32_dma_v1.c: arch/arm/src/stm32/stm32_dumpgpio.c: arch/arm/src/stm32/stm32_gpio.c: arch/arm/src/stm32/stm32_gpio.h: arch/arm/src/stm32/stm32_lowputc.c: arch/arm/src/stm32/stm32_rcc.c: arch/arm/src/stm32/stm32_rcc.h: arch/arm/src/stm32/stm32_serial.c: arch/arm/src/stm32/stm32_syscfg.h: arch/arm/src/stm32/stm32_uart.h: * Add architectural support to existing NuttX files. This makes the STM32G474 family parts accessible to the system. With big thanks for detailed code review: David Sidrane (davids5) Mateusz Szafoni (raiden00) Abdelatif Guettouche (Ouss4) --- arch/arm/Kconfig | 2 +- arch/arm/include/stm32/chip.h | 142 ++- arch/arm/include/stm32/irq.h | 2 + arch/arm/src/stm32/Kconfig | 358 ++++++- arch/arm/src/stm32/hardware/stm32_adc.h | 2 +- arch/arm/src/stm32/hardware/stm32_adc_v2.h | 889 ++++++++++-------- arch/arm/src/stm32/hardware/stm32_dma.h | 2 +- arch/arm/src/stm32/hardware/stm32_dma_v1.h | 96 +- arch/arm/src/stm32/hardware/stm32_flash.h | 281 +++++- arch/arm/src/stm32/hardware/stm32_i2c.h | 2 +- arch/arm/src/stm32/hardware/stm32_i2c_v2.h | 4 +- arch/arm/src/stm32/hardware/stm32_memorymap.h | 2 + arch/arm/src/stm32/hardware/stm32_pinmap.h | 6 + arch/arm/src/stm32/hardware/stm32_tim.h | 12 +- arch/arm/src/stm32/stm32_allocateheap.c | 88 ++ arch/arm/src/stm32/stm32_dma.c | 2 +- arch/arm/src/stm32/stm32_dma_v1.c | 141 ++- arch/arm/src/stm32/stm32_dumpgpio.c | 30 + arch/arm/src/stm32/stm32_gpio.c | 43 +- arch/arm/src/stm32/stm32_gpio.h | 27 +- arch/arm/src/stm32/stm32_lowputc.c | 11 +- arch/arm/src/stm32/stm32_rcc.c | 2 + arch/arm/src/stm32/stm32_rcc.h | 4 + arch/arm/src/stm32/stm32_serial.c | 12 +- arch/arm/src/stm32/stm32_syscfg.h | 2 + arch/arm/src/stm32/stm32_uart.h | 2 + 26 files changed, 1685 insertions(+), 479 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 23e90bef8e4..c43f252aac6 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -292,7 +292,7 @@ config ARCH_CHIP_SIMPLELINK TI SimpleLink CCxxx architectures (ARM Cortex-M3 or M4) config ARCH_CHIP_STM32 - bool "STMicro STM32 F1/F2/F3/F4/L1" + bool "STMicro STM32 F1/F2/F3/F4/G4/L1" select ARCH_HAVE_MPU select ARCH_HAVE_FETCHADD select ARCH_HAVE_I2CRESET diff --git a/arch/arm/include/stm32/chip.h b/arch/arm/include/stm32/chip.h index c8ae4fae806..1a39d6a2698 100644 --- a/arch/arm/include/stm32/chip.h +++ b/arch/arm/include/stm32/chip.h @@ -80,6 +80,11 @@ #else # define __HAVE_F4 0 #endif +#ifdef CONFIG_STM32_STM32G47XX +# define __HAVE_G47 1 +#else +# define __HAVE_G47 0 +#endif #ifdef CONFIG_STM32_STM32L15XX # define __HAVE_L1 1 #else @@ -87,7 +92,7 @@ #endif #if ((__HAVE_F1 + __HAVE_F2 + __HAVE_F30 + __HAVE_F33 + __HAVE_F37 + __HAVE_F4 + \ - __HAVE_L1) != 1) + __HAVE_G47 + __HAVE_L1) != 1) # error "Only one STM32 family must be selected !" #endif @@ -2267,6 +2272,141 @@ # define STM32_NRNG 1 /* Random number generator (RNG) */ # define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ +#elif defined (CONFIG_ARCH_CHIP_STM32G474C) +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 3 /* (3) Advanced motor control timers TIM1, 8, and 20 with DMA */ +# define STM32_NGTIM 7 /* (2) 16-bit general timers TIM3 and 4 with DMA + * (2) 32-bit general timers TIM2 and 5 with DMA + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NI2C 4 /* I2C1-4 */ +# define STM32_NCAN 3 /* FDCAN1-3 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed + * with LPM and BCD support) */ +# define STM32_NGPIO 42 /* GPIOA-C, F-G */ +# define STM32_NADC 5 /* 12-bit ADC1-5 */ +# define STM32_NDAC 4 /* 12-bit DAC1-4, 7 channels (3 external, 4 internal) */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined (CONFIG_ARCH_CHIP_STM32G474M) +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 3 /* (3) Advanced motor control timers TIM1, 8, and 20 with DMA */ +# define STM32_NGTIM 7 /* (2) 16-bit general timers TIM3 and 4 with DMA + * (2) 32-bit general timers TIM2 and 5 with DMA + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 4 /* SPI1-4 */ +# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ +# define STM32_NUSART 5 /* USART1-3 and UART 4-5 */ +# define STM32_NI2C 4 /* I2C1-4 */ +# define STM32_NCAN 3 /* FDCAN1-3 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed + * with LPM and BCD support) */ +# define STM32_NGPIO 67 /* GPIOA-G */ +# define STM32_NADC 5 /* 12-bit ADC1-5 */ +# define STM32_NDAC 4 /* 12-bit DAC1-4, 7 channels (3 external, 4 internal) */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined (CONFIG_ARCH_CHIP_STM32G474R) +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 3 /* (3) Advanced motor control timers TIM1, 8, and 20 with DMA */ +# define STM32_NGTIM 7 /* (2) 16-bit general timers TIM3 and 4 with DMA + * (2) 32-bit general timers TIM2 and 5 with DMA + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ +# define STM32_NUSART 5 /* USART1-3 and UART 4-5 */ +# define STM32_NI2C 4 /* I2C1-4 */ +# define STM32_NCAN 3 /* FDCAN1-3 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed + * with LPM and BCD support) */ +# define STM32_NGPIO 52 /* GPIOA-D, F-G */ +# define STM32_NADC 5 /* 12-bit ADC1-5 */ +# define STM32_NDAC 4 /* 12-bit DAC1-4, 7 channels (3 external, 4 internal) */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined (CONFIG_ARCH_CHIP_STM32G474Q) +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 3 /* (3) Advanced motor control timers TIM1, 8, and 20 with DMA */ +# define STM32_NGTIM 7 /* (2) 16-bit general timers TIM3 and 4 with DMA + * (2) 32-bit general timers TIM2 and 5 with DMA + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 4 /* SPI1-4 */ +# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ +# define STM32_NUSART 5 /* USART1-3 and UART 4-5 */ +# define STM32_NI2C 4 /* I2C1-4 */ +# define STM32_NCAN 3 /* FDCAN1-3 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD parallel interface possible via FMC */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed + * with LPM and BCD support) */ +# define STM32_NGPIO 107 /* GPIOA-G */ +# define STM32_NADC 5 /* 12-bit ADC1-5 */ +# define STM32_NDAC 4 /* 12-bit DAC1-4, 7 channels (3 external, 4 internal) */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined (CONFIG_ARCH_CHIP_STM32G474V) +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 3 /* (3) Advanced motor control timers TIM1, 8, and 20 with DMA */ +# define STM32_NGTIM 7 /* (2) 16-bit general timers TIM3 and 4 with DMA + * (2) 32-bit general timers TIM2 and 5 with DMA + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 4 /* SPI1-4 */ +# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ +# define STM32_NUSART 5 /* USART1-3 and UART 4-5 */ +# define STM32_NI2C 4 /* I2C1-4 */ +# define STM32_NCAN 3 /* FDCAN1-3 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD parallel interface possible via FMC */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed + * with LPM and BCD support) */ +# define STM32_NGPIO 86 /* GPIOA-G */ +# define STM32_NADC 5 /* 12-bit ADC1-5 */ +# define STM32_NDAC 4 /* 12-bit DAC1-4, 7 channels (3 external, 4 internal) */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + #else # error "Unsupported STM32 chip" #endif diff --git a/arch/arm/include/stm32/irq.h b/arch/arm/include/stm32/irq.h index 4e2f114d4af..892c6f059d4 100644 --- a/arch/arm/include/stm32/irq.h +++ b/arch/arm/include/stm32/irq.h @@ -95,6 +95,8 @@ # include #elif defined(CONFIG_STM32_STM32F4XXX) # include +#elif defined(CONFIG_STM32_STM32G47XX) +# include #else # error "Unsupported STM32 chip" #endif diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig index 6c2e9ad7343..00e5d3bfbd7 100644 --- a/arch/arm/src/stm32/Kconfig +++ b/arch/arm/src/stm32/Kconfig @@ -1129,6 +1129,31 @@ config ARCH_CHIP_STM32F469N select STM32_STM32F469 select STM32_HAVE_ETHMAC +config ARCH_CHIP_STM32G474C + bool "STM32G474C" + select STM32_STM32G47XX + select STM32_STM32G474C + +config ARCH_CHIP_STM32G474M + bool "STM32G474M" + select STM32_STM32G47XX + select STM32_STM32G474M + +config ARCH_CHIP_STM32G474R + bool "STM32G474R" + select STM32_STM32G47XX + select STM32_STM32G474R + +config ARCH_CHIP_STM32G474Q + bool "STM32G474Q" + select STM32_STM32G47XX + select STM32_STM32G474Q + +config ARCH_CHIP_STM32G474V + bool "STM32G474V" + select STM32_STM32G47XX + select STM32_STM32G474V + endchoice choice @@ -1136,8 +1161,8 @@ choice default STM32_FLASH_CONFIG_DEFAULT depends on ARCH_CHIP_STM32 ---help--- - STM32F/STM32L series parts numbering (sans the package type) ends with a number or letter - that designates the FLASH size. + STM32F/STM32G/STM32L series parts numbering (sans the package type) + ends with a number or letter that designates the FLASH size. Designator Size in KiB 4 16 @@ -1152,17 +1177,18 @@ choice G 1024 I 2048 - This configuration option defaults to using the configuration based on that designator - or the default smaller size if there is no last character designator is present in the - STM32 Chip Selection. + This configuration option defaults to using the configuration based + on that designator or the default smaller size if there is no last + character designator is present in the STM32 Chip Selection. Examples: - If the STM32F407VE is chosen, the Flash configuration would be 'E', if a variant of - the part with a 2048 KiB Flash is released in the future one could simply select - the 'I' designator here. + If the STM32F407VE is chosen, the Flash configuration would be + 'E', if a variant of the part with a 2048 KiB Flash is released + in the future one could simply select the 'I' designator here. - If an STM32F42xxx or Series parts is chosen the default Flash configuration will be 'G' - and can be set herein to 'I' to choose the larger FLASH part. + If an STM32F42xxx or Series parts is chosen the default Flash + configuration will be 'G' and can be set herein to 'I' to choose + the larger FLASH part. config STM32_FLASH_CONFIG_DEFAULT bool "Default" @@ -1810,6 +1836,108 @@ config STM32_STM32F469 select STM32_HAVE_I2S3 select STM32_HAVE_I2C3 +config STM32_STM32G47XX + bool + default n + select ARCH_CORTEXM4 + select ARCH_HAVE_FPU + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_ADC4 + select STM32_HAVE_ADC5 + select STM32_HAVE_CCM + select STM32_HAVE_COMP1 + select STM32_HAVE_COMP2 + select STM32_HAVE_COMP3 + select STM32_HAVE_COMP4 + select STM32_HAVE_COMP5 + select STM32_HAVE_COMP6 + select STM32_HAVE_COMP7 + select STM32_HAVE_CORDIC + select STM32_HAVE_CRS + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 + select STM32_HAVE_DAC3 + select STM32_HAVE_DAC4 + select STM32_HAVE_DMA1_CHAN8 + select STM32_HAVE_DMA2_CHAN678 + select STM32_HAVE_FSMC + select STM32_HAVE_FMAC + select STM32_HAVE_FDCAN1 + select STM32_HAVE_FDCAN2 + select STM32_HAVE_HRTIM1 + select STM32_HAVE_I2C2 + select STM32_HAVE_I2C3 + select STM32_HAVE_I2C4 + select STM32_HAVE_I2S3 + select STM32_HAVE_LPTIM1 + select STM32_HAVE_LPUART1 + select STM32_HAVE_OPAMP1 + select STM32_HAVE_OPAMP2 + select STM32_HAVE_OPAMP3 + select STM32_HAVE_OPAMP4 + select STM32_HAVE_OPAMP5 + select STM32_HAVE_OPAMP6 + select STM32_HAVE_QSPI + select STM32_HAVE_RNG + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM20 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM8 + select STM32_HAVE_USART3 + select STM32_HAVE_UCPD + select STM32_HAVE_USBDEV + select STM32_HAVE_IP_ADC_V2 + select STM32_HAVE_IP_DMA_V1 + select STM32_HAVE_IP_I2C_V2 + select STM32_HAVE_IP_TIMERS_V1 + +config STM32_STM32G474C + bool + default n + select STM32_HAVE_FDCAN3 + +config STM32_STM32G474M + bool + default n + select STM32_HAVE_FDCAN3 + select STM32_HAVE_SPI4 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + +config STM32_STM32G474R + bool + default n + select STM32_HAVE_FDCAN3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + +config STM32_STM32G474Q + bool + default n + select STM32_HAVE_FDCAN3 + select STM32_HAVE_FMC + select STM32_HAVE_SPI4 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + +config STM32_STM32G474V + bool + default n + select STM32_HAVE_FDCAN3 + select STM32_HAVE_FMC + select STM32_HAVE_SPI4 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + config STM32_DFU bool "DFU bootloader" default n @@ -1835,6 +1963,18 @@ config STM32_HAVE_CCM bool default n +config STM32_HAVE_DMA1_CHAN8 + bool + default n + +config STM32_HAVE_DMA2_CHAN678 + bool + default n + +config STM32_HAVE_UCPD + bool + default n + config STM32_HAVE_USBDEV bool default n @@ -1847,10 +1987,26 @@ config STM32_HAVE_FMC bool default n +config STM32_HAVE_FMAC + bool + default n + config STM32_HAVE_FSMC bool default n +config STM32_HAVE_FDCAN1 + bool + default n + +config STM32_HAVE_FDCAN2 + bool + default n + +config STM32_HAVE_FDCAN3 + bool + default n + config STM32_HAVE_IOCOMPENSATION bool default n @@ -1955,6 +2111,18 @@ config STM32_HAVE_TIM17 bool default n +config STM32_HAVE_TIM18 + bool + default n + +config STM32_HAVE_TIM19 + bool + default n + +config STM32_HAVE_TIM20 + bool + default n + config STM32_HAVE_TSC bool default n @@ -1971,6 +2139,10 @@ config STM32_HAVE_ADC4 bool default n +config STM32_HAVE_ADC5 + bool + default n + config STM32_HAVE_ADC1_DMA bool default n @@ -1987,6 +2159,10 @@ config STM32_HAVE_ADC4_DMA bool default n +config STM32_HAVE_ADC5_DMA + bool + default n + config STM32_HAVE_SDADC1 bool default n @@ -2047,6 +2223,14 @@ config STM32_HAVE_COMP7 bool default n +config STM32_HAVE_CORDIC + bool + default n + +config STM32_HAVE_CRS + bool + default n + config STM32_HAVE_DAC1 bool default n @@ -2055,6 +2239,18 @@ config STM32_HAVE_DAC2 bool default n +config STM32_HAVE_DAC3 + bool + default n + +config STM32_HAVE_DAC4 + bool + default n + +config STM32_HAVE_QSPI + bool + default n + config STM32_HAVE_RNG bool default n @@ -2071,6 +2267,18 @@ config STM32_HAVE_I2C3 bool default n +config STM32_HAVE_I2C4 + bool + default n + +config STM32_HAVE_LPTIM1 + bool + default n + +config STM32_HAVE_LPUART1 + bool + default n + config STM32_HAVE_SPI2 bool default n @@ -2119,6 +2327,14 @@ config STM32_HAVE_OPAMP4 bool default n +config STM32_HAVE_OPAMP5 + bool + default n + +config STM32_HAVE_OPAMP6 + bool + default n + # These are STM32 peripherals IP blocks config STM32_HAVE_IP_I2C_V1 @@ -2194,6 +2410,13 @@ config STM32_ADC4 depends on STM32_HAVE_ADC4 select STM32_HAVE_ADC4_DMA if STM32_DMA2 +config STM32_ADC5 + bool "ADC5" + default n + select STM32_ADC + depends on STM32_HAVE_ADC5 + select STM32_HAVE_ADC5_DMA if STM32_DMA2 + config STM32_SDADC1 bool "SDADC1" default n @@ -2257,6 +2480,11 @@ config STM32_COMP7 select STM32_COMP depends on STM32_HAVE_COMP7 +config STM32_CORDIC + bool "CORDIC Accelerator" + default n + depends on STM32_HAVE_CORDIC + config STM32_BKP bool "BKP" default n @@ -2302,6 +2530,11 @@ config STM32_CRC bool "CRC" default n +config STM32_CRS + bool "CRS (Clock Recovery System)" + default n + depends on STM32_HAVE_CRS + config STM32_CRYP bool "CRYP" default n @@ -2350,6 +2583,18 @@ config STM32_DAC2CH1 endif #STM32_DAC2 +config STM32_DAC3 + bool "DAC3" + default n + depends on STM32_HAVE_DAC3 + select STM32_DAC + +config STM32_DAC4 + bool "DAC4" + default n + depends on STM32_HAVE_DAC4 + select STM32_DAC + config STM32_DCMI bool "DCMI" default n @@ -2362,6 +2607,21 @@ config STM32_ETHMAC select NETDEVICES select ARCH_HAVE_PHY +config STM32_FDCAN1 + bool "FDCAN1" + default n + depends on STM32_HAVE_FDCAN1 + +config STM32_FDCAN2 + bool "FDCAN2" + default n + depends on STM32_HAVE_FDCAN2 + +config STM32_FDCAN3 + bool "FDCAN3" + default n + depends on STM32_HAVE_FDCAN3 + config STM32_FSMC bool "FSMC" default n @@ -2372,6 +2632,11 @@ config STM32_FMC default n depends on STM32_HAVE_FMC +config STM32_FMAC + bool "FMAC (Filter Math Accelerator)" + default n + depends on STM32_HAVE_FMAC + config STM32_HASH bool "HASH" default n @@ -2444,6 +2709,16 @@ config STM32_I2C3 depends on STM32_HAVE_I2C3 select STM32_I2C +config STM32_LPTIM1 + bool "LPTIM1" + default n + depends on STM32_HAVE_LPTIM1 + +config STM32_LPUART1 + bool "LPUART1" + default n + depends on STM32_HAVE_LPUART1 + config STM32_LTDC bool "LTDC" default n @@ -2510,6 +2785,11 @@ config STM32_PWR bool "PWR" default n +config STM32_QSPI + bool "QSPI (QUADSPI)" + depends on STM32_HAVE_QSPI + default n + config STM32_RNG bool "RNG" default n @@ -2577,7 +2857,7 @@ config STM32_SPI6 config STM32_SYSCFG bool "SYSCFG" default y - depends on STM32_STM32L15XX || STM32_STM32F30XX || STM32_STM32F33XX || STM32_STM32F37XX || STM32_STM32F20XX || STM32_STM32F4XXX || STM32_CONNECTIVITYLINE + depends on STM32_STM32L15XX || STM32_STM32F30XX || STM32_STM32F33XX || STM32_STM32F37XX || STM32_STM32F20XX || STM32_STM32F4XXX || STM32_STM32G47XX || STM32_CONNECTIVITYLINE config STM32_TIM1 bool "TIM1" @@ -2737,6 +3017,12 @@ config STM32_USB depends on STM32_HAVE_USBDEV select USBDEV +config STM32_UCPD + bool "UCPD (USB Type C Power Delivery)" + default n + depends on STM32_HAVE_UCPD + select USBDEV + config STM32_LCD bool "Segment LCD" default n @@ -5645,6 +5931,9 @@ config STM32_HAVE_ADC3_TIMER config STM32_HAVE_ADC4_TIMER bool +config STM32_HAVE_ADC5_TIMER + bool + config STM32_ADC1_SAMPLE_FREQUENCY int "ADC1 Sampling Frequency" default 100 @@ -7633,6 +7922,14 @@ config STM32_ADC4_RESOLUTION ---help--- ADC4 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit +config STM32_ADC5_RESOLUTION + int "ADC5 resolution" + depends on STM32_ADC5 && !STM32_HAVE_IP_ADC_V1_BASIC + default 0 + range 0 3 + ---help--- + ADC5 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit + config STM32_ADC_NO_STARTUP_CONV bool "Do not start conversion when opening ADC device" default n @@ -7726,6 +8023,23 @@ config STM32_ADC4_DMA_CFG ---help--- 0 - ADC4 DMA in One Shot Mode, 1 - ADC4 DMA in Circular Mode +config STM32_ADC5_DMA + bool "ADC5 DMA" + depends on STM32_ADC5 && STM32_HAVE_ADC5_DMA + default n + ---help--- + If DMA is selected, then the ADC may be configured to support + DMA transfer, which is necessary if multiple channels are read + or if very high trigger frequencies are used. + +config STM32_ADC5_DMA_CFG + int "ADC5 DMA configuration" + depends on STM32_ADC5_DMA && !STM32_HAVE_IP_ADC_V1_BASIC + range 0 1 + default 0 + ---help--- + 0 - ADC5 DMA in One Shot Mode, 1 - ADC5 DMA in Circular Mode + config STM32_ADC1_INJECTED_CHAN int "ADC1 injected channels" depends on STM32_ADC1 @@ -7758,6 +8072,14 @@ config STM32_ADC4_INJECTED_CHAN ---help--- Support for ADC4 injected channels. +config STM32_ADC5_INJECTED_CHAN + int "ADC5 injected channels" + depends on STM32_ADC5 + range 0 4 + default 0 + ---help--- + Support for ADC5 injected channels. + config STM32_ADC1_EXTSEL bool "ADC1 external trigger for regular group" depends on STM32_ADC1 && !STM32_HAVE_ADC1_TIMER @@ -7786,6 +8108,13 @@ config STM32_ADC4_EXTSEL ---help--- Enable EXTSEL for ADC4. +config STM32_ADC5_EXTSEL + bool "ADC5 external trigger for regular group" + depends on STM32_ADC5 && !STM32_HAVE_ADC5_TIMER + default n + ---help--- + Enable EXTSEL for ADC5. + config STM32_ADC1_JEXTSEL bool "ADC1 external trigger for injected group" depends on STM32_ADC1 @@ -7814,6 +8143,13 @@ config STM32_ADC4_JEXTSEL ---help--- Enable JEXTSEL for ADC4. +config STM32_ADC5_JEXTSEL + bool "ADC5 external trigger for injected group" + depends on STM32_ADC5 + default n + ---help--- + Enable JEXTSEL for ADC5. + endmenu menu "SDADC Configuration" diff --git a/arch/arm/src/stm32/hardware/stm32_adc.h b/arch/arm/src/stm32/hardware/stm32_adc.h index af4c7d5dedc..4622ab5b936 100644 --- a/arch/arm/src/stm32/hardware/stm32_adc.h +++ b/arch/arm/src/stm32/hardware/stm32_adc.h @@ -50,7 +50,7 @@ * b) extended version for F2, F4, F7, L1: * 2. STM32 ADC IPv2: * a) basic version for F0 and L0 - * b) extended version for F3 (without F37x), H7, L4, L4+ + * b) extended version for F3 (without F37x), G4, H7, L4, L4+ * * We also distinguish the modified STM32 ADC IPv1 core for the L1 family, * which differs too much to keep it in the same file as ADC IPv1. diff --git a/arch/arm/src/stm32/hardware/stm32_adc_v2.h b/arch/arm/src/stm32/hardware/stm32_adc_v2.h index d108fd9467d..e625435258b 100644 --- a/arch/arm/src/stm32/hardware/stm32_adc_v2.h +++ b/arch/arm/src/stm32/hardware/stm32_adc_v2.h @@ -51,7 +51,7 @@ /* Configuration ************************************************************************************/ -/* This is implementation for STM32 ADC IPv2 - F0, F3 (without F37x), H7, L0, L4, L4+ */ +/* This is implementation for STM32 ADC IPv2 - F0, F3 (without F37x), G4, H7, L0, L4, L4+ */ #define HAVE_IP_ADC_V2 #undef HAVE_IP_ADC_V1 /* No ADC IPv1 */ @@ -86,219 +86,219 @@ /* Base addresses ***********************************************************************************/ -#define STM32_ADC1_OFFSET 0x0000 -#define STM32_ADC2_OFFSET 0x0100 -#define STM32_ADC3_OFFSET 0x0000 -#define STM32_ADC4_OFFSET 0x0100 -#define STM32_ADCCMN_OFFSET 0x0300 +#define STM32_ADC1_OFFSET 0x0000 +#define STM32_ADC2_OFFSET 0x0100 +#define STM32_ADC3_OFFSET 0x0000 +#define STM32_ADC4_OFFSET 0x0100 +#define STM32_ADCCMN_OFFSET 0x0300 -#define STM32_ADC1_BASE (STM32_ADC1_OFFSET + STM32_ADC12_BASE) /* ADC1 Master ADC */ -#define STM32_ADC2_BASE (STM32_ADC2_OFFSET + STM32_ADC12_BASE) /* ADC2 Slave ADC */ -#define STM32_ADC3_BASE (STM32_ADC3_OFFSET + STM32_ADC34_BASE) /* ADC3 Master ADC */ -#define STM32_ADC4_BASE (STM32_ADC4_OFFSET + STM32_ADC34_BASE) /* ADC4 Slave ADC */ -#define STM32_ADC12CMN_BASE (STM32_ADCCMN_OFFSET + STM32_ADC12_BASE) /* ADC1, ADC2 common */ -#define STM32_ADC34CMN_BASE (STM32_ADCCMN_OFFSET + STM32_ADC34_BASE) /* ADC3, ADC4 common */ +#define STM32_ADC1_BASE (STM32_ADC1_OFFSET + STM32_ADC12_BASE) /* ADC1 Master ADC */ +#define STM32_ADC2_BASE (STM32_ADC2_OFFSET + STM32_ADC12_BASE) /* ADC2 Slave ADC */ +#define STM32_ADC3_BASE (STM32_ADC3_OFFSET + STM32_ADC34_BASE) /* ADC3 Master ADC */ +#define STM32_ADC4_BASE (STM32_ADC4_OFFSET + STM32_ADC34_BASE) /* ADC4 Slave ADC */ +#define STM32_ADC12CMN_BASE (STM32_ADCCMN_OFFSET + STM32_ADC12_BASE) /* ADC1, ADC2 common */ +#define STM32_ADC34CMN_BASE (STM32_ADCCMN_OFFSET + STM32_ADC34_BASE) /* ADC3, ADC4 common */ /* Register Offsets *********************************************************************************/ -#define STM32_ADC_ISR_OFFSET 0x0000 /* ADC interrupt and status register */ -#define STM32_ADC_IER_OFFSET 0x0004 /* ADC interrupt enable register */ -#define STM32_ADC_CR_OFFSET 0x0008 /* ADC control register */ -#define STM32_ADC_CFGR1_OFFSET 0x000c /* ADC configuration register 1 */ +#define STM32_ADC_ISR_OFFSET 0x0000 /* ADC interrupt and status register */ +#define STM32_ADC_IER_OFFSET 0x0004 /* ADC interrupt enable register */ +#define STM32_ADC_CR_OFFSET 0x0008 /* ADC control register */ +#define STM32_ADC_CFGR1_OFFSET 0x000c /* ADC configuration register 1 */ #ifdef HAVE_ADC_CFGR2 -# define STM32_ADC_CFGR2_OFFSET 0x0010 /* ADC configuration register 2 */ +# define STM32_ADC_CFGR2_OFFSET 0x0010 /* ADC configuration register 2 */ #endif -#define STM32_ADC_SMPR1_OFFSET 0x0014 /* ADC sample time register 1 */ -#define STM32_ADC_SMPR2_OFFSET 0x0018 /* ADC sample time register 2 */ -#define STM32_ADC_TR1_OFFSET 0x0020 /* ADC watchdog threshold register 1 */ -#define STM32_ADC_TR2_OFFSET 0x0024 /* ADC watchdog threshold register 2 */ -#define STM32_ADC_TR3_OFFSET 0x0028 /* ADC watchdog threshold register 3 */ -#define STM32_ADC_SQR1_OFFSET 0x0030 /* ADC regular sequence register 1 */ -#define STM32_ADC_SQR2_OFFSET 0x0034 /* ADC regular sequence register 2 */ -#define STM32_ADC_SQR3_OFFSET 0x0038 /* ADC regular sequence register 3 */ -#define STM32_ADC_SQR4_OFFSET 0x003c /* ADC regular sequence register 4 */ -#define STM32_ADC_DR_OFFSET 0x0040 /* ADC regular data register */ -#define STM32_ADC_JSQR_OFFSET 0x004c /* ADC injected sequence register */ -#define STM32_ADC_OFR1_OFFSET 0x0060 /* ADC offset register 1 */ -#define STM32_ADC_OFR2_OFFSET 0x0064 /* ADC offset register 2 */ -#define STM32_ADC_OFR3_OFFSET 0x0068 /* ADC offset register 3 */ -#define STM32_ADC_OFR4_OFFSET 0x006c /* ADC data offset register 4 */ -#define STM32_ADC_JDR1_OFFSET 0x0080 /* ADC injected data register 1 */ -#define STM32_ADC_JDR2_OFFSET 0x0084 /* ADC injected data register 2 */ -#define STM32_ADC_JDR3_OFFSET 0x0088 /* ADC injected data register 3 */ -#define STM32_ADC_JDR4_OFFSET 0x008c /* ADC injected data register 4 */ -#define STM32_ADC_AWD2CR_OFFSET 0x00a0 /* ADC analog watchdog 2 configuration register */ -#define STM32_ADC_AWD3CR_OFFSET 0x00a4 /* ADC analog watchdog 3 configuration register */ -#define STM32_ADC_DIFSEL_OFFSET 0x00b0 /* ADC differential mode selection register */ -#define STM32_ADC_CALFACT_OFFSET 0x00b4 /* ADC calibration factors */ +#define STM32_ADC_SMPR1_OFFSET 0x0014 /* ADC sample time register 1 */ +#define STM32_ADC_SMPR2_OFFSET 0x0018 /* ADC sample time register 2 */ +#define STM32_ADC_TR1_OFFSET 0x0020 /* ADC watchdog threshold register 1 */ +#define STM32_ADC_TR2_OFFSET 0x0024 /* ADC watchdog threshold register 2 */ +#define STM32_ADC_TR3_OFFSET 0x0028 /* ADC watchdog threshold register 3 */ +#define STM32_ADC_SQR1_OFFSET 0x0030 /* ADC regular sequence register 1 */ +#define STM32_ADC_SQR2_OFFSET 0x0034 /* ADC regular sequence register 2 */ +#define STM32_ADC_SQR3_OFFSET 0x0038 /* ADC regular sequence register 3 */ +#define STM32_ADC_SQR4_OFFSET 0x003c /* ADC regular sequence register 4 */ +#define STM32_ADC_DR_OFFSET 0x0040 /* ADC regular data register */ +#define STM32_ADC_JSQR_OFFSET 0x004c /* ADC injected sequence register */ +#define STM32_ADC_OFR1_OFFSET 0x0060 /* ADC offset register 1 */ +#define STM32_ADC_OFR2_OFFSET 0x0064 /* ADC offset register 2 */ +#define STM32_ADC_OFR3_OFFSET 0x0068 /* ADC offset register 3 */ +#define STM32_ADC_OFR4_OFFSET 0x006c /* ADC data offset register 4 */ +#define STM32_ADC_JDR1_OFFSET 0x0080 /* ADC injected data register 1 */ +#define STM32_ADC_JDR2_OFFSET 0x0084 /* ADC injected data register 2 */ +#define STM32_ADC_JDR3_OFFSET 0x0088 /* ADC injected data register 3 */ +#define STM32_ADC_JDR4_OFFSET 0x008c /* ADC injected data register 4 */ +#define STM32_ADC_AWD2CR_OFFSET 0x00a0 /* ADC analog watchdog 2 configuration register */ +#define STM32_ADC_AWD3CR_OFFSET 0x00a4 /* ADC analog watchdog 3 configuration register */ +#define STM32_ADC_DIFSEL_OFFSET 0x00b0 /* ADC differential mode selection register */ +#define STM32_ADC_CALFACT_OFFSET 0x00b4 /* ADC calibration factors */ /* Master and Slave ADC Common Registers */ -#define STM32_ADC_CSR_OFFSET 0x0000 /* Common status register */ -#define STM32_ADC_CCR_OFFSET 0x0008 /* Common control register */ -#define STM32_ADC_CDR_OFFSET 0x000c /* Common regular data register for dual mode */ +#define STM32_ADC_CSR_OFFSET 0x0000 /* Common status register */ +#define STM32_ADC_CCR_OFFSET 0x0008 /* Common control register */ +#define STM32_ADC_CDR_OFFSET 0x000c /* Common regular data register for dual mode */ /* Register Addresses *******************************************************************************/ #if STM32_NADC > 0 -# define STM32_ADC1_ISR (STM32_ADC1_BASE + STM32_ADC_ISR_OFFSET) -# define STM32_ADC1_IER (STM32_ADC1_BASE + STM32_ADC_IER_OFFSET) -# define STM32_ADC1_CR (STM32_ADC1_BASE + STM32_ADC_CR_OFFSET) -# define STM32_ADC1_CFGR1 (STM32_ADC1_BASE + STM32_ADC_CFGR1_OFFSET) +# define STM32_ADC1_ISR (STM32_ADC1_BASE + STM32_ADC_ISR_OFFSET) +# define STM32_ADC1_IER (STM32_ADC1_BASE + STM32_ADC_IER_OFFSET) +# define STM32_ADC1_CR (STM32_ADC1_BASE + STM32_ADC_CR_OFFSET) +# define STM32_ADC1_CFGR1 (STM32_ADC1_BASE + STM32_ADC_CFGR1_OFFSET) # ifdef HAVE_ADC_CFGR2 -# define STM32_ADC1_CFGR2 (STM32_ADC1_BASE + STM32_ADC_CFGR2_OFFSET) +# define STM32_ADC1_CFGR2 (STM32_ADC1_BASE + STM32_ADC_CFGR2_OFFSET) # endif -# define STM32_ADC1_SMPR1 (STM32_ADC1_BASE + STM32_ADC_SMPR1_OFFSET) -# define STM32_ADC1_SMPR2 (STM32_ADC1_BASE + STM32_ADC_SMPR2_OFFSET) -# define STM32_ADC1_TR1 (STM32_ADC1_BASE + STM32_ADC_TR1_OFFSET) -# define STM32_ADC1_TR2 (STM32_ADC1_BASE + STM32_ADC_TR2_OFFSET) -# define STM32_ADC1_TR3 (STM32_ADC1_BASE + STM32_ADC_TR3_OFFSET) -# define STM32_ADC1_SQR1 (STM32_ADC1_BASE + STM32_ADC_SQR1_OFFSET) -# define STM32_ADC1_SQR2 (STM32_ADC1_BASE + STM32_ADC_SQR2_OFFSET) -# define STM32_ADC1_SQR3 (STM32_ADC1_BASE + STM32_ADC_SQR3_OFFSET) -# define STM32_ADC1_SQR4 (STM32_ADC1_BASE + STM32_ADC_SQR4_OFFSET) -# define STM32_ADC1_DR (STM32_ADC1_BASE + STM32_ADC_DR_OFFSET) -# define STM32_ADC1_JSQR (STM32_ADC1_BASE + STM32_ADC_JSQR_OFFSET) -# define STM32_ADC1_OFR1 (STM32_ADC1_BASE + STM32_ADC_OFR1_OFFSET) -# define STM32_ADC1_OFR2 (STM32_ADC1_BASE + STM32_ADC_OFR2_OFFSET) -# define STM32_ADC1_OFR3 (STM32_ADC1_BASE + STM32_ADC_OFR3_OFFSET) -# define STM32_ADC1_OFR4 (STM32_ADC1_BASE + STM32_ADC_OFR4_OFFSET) -# define STM32_ADC1_JDR1 (STM32_ADC1_BASE + STM32_ADC_JDR1_OFFSET) -# define STM32_ADC1_JDR2 (STM32_ADC1_BASE + STM32_ADC_JDR2_OFFSET) -# define STM32_ADC1_JDR3 (STM32_ADC1_BASE + STM32_ADC_JDR3_OFFSET) -# define STM32_ADC1_JDR4 (STM32_ADC1_BASE + STM32_ADC_JDR4_OFFSET) -# define STM32_ADC1_AWD2CR (STM32_ADC1_BASE + STM32_ADC_AWD2CR_OFFSET) -# define STM32_ADC1_AWD3CR (STM32_ADC1_BASE + STM32_ADC_AWD3CR_OFFSET) -# define STM32_ADC1_DIFSEL (STM32_ADC1_BASE + STM32_ADC_DIFSEL_OFFSET) -# define STM32_ADC1_CALFACT (STM32_ADC1_BASE + STM32_ADC_CALFACT_OFFSET) +# define STM32_ADC1_SMPR1 (STM32_ADC1_BASE + STM32_ADC_SMPR1_OFFSET) +# define STM32_ADC1_SMPR2 (STM32_ADC1_BASE + STM32_ADC_SMPR2_OFFSET) +# define STM32_ADC1_TR1 (STM32_ADC1_BASE + STM32_ADC_TR1_OFFSET) +# define STM32_ADC1_TR2 (STM32_ADC1_BASE + STM32_ADC_TR2_OFFSET) +# define STM32_ADC1_TR3 (STM32_ADC1_BASE + STM32_ADC_TR3_OFFSET) +# define STM32_ADC1_SQR1 (STM32_ADC1_BASE + STM32_ADC_SQR1_OFFSET) +# define STM32_ADC1_SQR2 (STM32_ADC1_BASE + STM32_ADC_SQR2_OFFSET) +# define STM32_ADC1_SQR3 (STM32_ADC1_BASE + STM32_ADC_SQR3_OFFSET) +# define STM32_ADC1_SQR4 (STM32_ADC1_BASE + STM32_ADC_SQR4_OFFSET) +# define STM32_ADC1_DR (STM32_ADC1_BASE + STM32_ADC_DR_OFFSET) +# define STM32_ADC1_JSQR (STM32_ADC1_BASE + STM32_ADC_JSQR_OFFSET) +# define STM32_ADC1_OFR1 (STM32_ADC1_BASE + STM32_ADC_OFR1_OFFSET) +# define STM32_ADC1_OFR2 (STM32_ADC1_BASE + STM32_ADC_OFR2_OFFSET) +# define STM32_ADC1_OFR3 (STM32_ADC1_BASE + STM32_ADC_OFR3_OFFSET) +# define STM32_ADC1_OFR4 (STM32_ADC1_BASE + STM32_ADC_OFR4_OFFSET) +# define STM32_ADC1_JDR1 (STM32_ADC1_BASE + STM32_ADC_JDR1_OFFSET) +# define STM32_ADC1_JDR2 (STM32_ADC1_BASE + STM32_ADC_JDR2_OFFSET) +# define STM32_ADC1_JDR3 (STM32_ADC1_BASE + STM32_ADC_JDR3_OFFSET) +# define STM32_ADC1_JDR4 (STM32_ADC1_BASE + STM32_ADC_JDR4_OFFSET) +# define STM32_ADC1_AWD2CR (STM32_ADC1_BASE + STM32_ADC_AWD2CR_OFFSET) +# define STM32_ADC1_AWD3CR (STM32_ADC1_BASE + STM32_ADC_AWD3CR_OFFSET) +# define STM32_ADC1_DIFSEL (STM32_ADC1_BASE + STM32_ADC_DIFSEL_OFFSET) +# define STM32_ADC1_CALFACT (STM32_ADC1_BASE + STM32_ADC_CALFACT_OFFSET) #endif #if STM32_NADC > 1 -# define STM32_ADC2_ISR (STM32_ADC2_BASE + STM32_ADC_ISR_OFFSET) -# define STM32_ADC2_IER (STM32_ADC2_BASE + STM32_ADC_IER_OFFSET) -# define STM32_ADC2_CR (STM32_ADC2_BASE + STM32_ADC_CR_OFFSET) -# define STM32_ADC2_CFGR1 (STM32_ADC2_BASE + STM32_ADC_CFGR1_OFFSET) +# define STM32_ADC2_ISR (STM32_ADC2_BASE + STM32_ADC_ISR_OFFSET) +# define STM32_ADC2_IER (STM32_ADC2_BASE + STM32_ADC_IER_OFFSET) +# define STM32_ADC2_CR (STM32_ADC2_BASE + STM32_ADC_CR_OFFSET) +# define STM32_ADC2_CFGR1 (STM32_ADC2_BASE + STM32_ADC_CFGR1_OFFSET) # ifdef HAVE_ADC_CFGR2 -# define STM32_ADC2_CFGR2 (STM32_ADC2_BASE + STM32_ADC_CFGR2_OFFSET) +# define STM32_ADC2_CFGR2 (STM32_ADC2_BASE + STM32_ADC_CFGR2_OFFSET) # endif -# define STM32_ADC2_SMPR1 (STM32_ADC2_BASE + STM32_ADC_SMPR1_OFFSET) -# define STM32_ADC2_SMPR2 (STM32_ADC2_BASE + STM32_ADC_SMPR2_OFFSET) -# define STM32_ADC2_TR1 (STM32_ADC2_BASE + STM32_ADC_TR1_OFFSET) -# define STM32_ADC2_TR2 (STM32_ADC2_BASE + STM32_ADC_TR2_OFFSET) -# define STM32_ADC2_TR3 (STM32_ADC2_BASE + STM32_ADC_TR3_OFFSET) -# define STM32_ADC2_SQR1 (STM32_ADC2_BASE + STM32_ADC_SQR1_OFFSET) -# define STM32_ADC2_SQR2 (STM32_ADC2_BASE + STM32_ADC_SQR2_OFFSET) -# define STM32_ADC2_SQR3 (STM32_ADC2_BASE + STM32_ADC_SQR3_OFFSET) -# define STM32_ADC2_SQR4 (STM32_ADC2_BASE + STM32_ADC_SQR4_OFFSET) -# define STM32_ADC2_DR (STM32_ADC2_BASE + STM32_ADC_DR_OFFSET) -# define STM32_ADC2_JSQR (STM32_ADC2_BASE + STM32_ADC_JSQR_OFFSET) -# define STM32_ADC2_OFR1 (STM32_ADC2_BASE + STM32_ADC_OFR1_OFFSET) -# define STM32_ADC2_OFR2 (STM32_ADC2_BASE + STM32_ADC_OFR2_OFFSET) -# define STM32_ADC2_OFR3 (STM32_ADC2_BASE + STM32_ADC_OFR3_OFFSET) -# define STM32_ADC2_OFR4 (STM32_ADC2_BASE + STM32_ADC_OFR4_OFFSET) -# define STM32_ADC2_JDR1 (STM32_ADC2_BASE + STM32_ADC_JDR1_OFFSET) -# define STM32_ADC2_JDR2 (STM32_ADC2_BASE + STM32_ADC_JDR2_OFFSET) -# define STM32_ADC2_JDR3 (STM32_ADC2_BASE + STM32_ADC_JDR3_OFFSET) -# define STM32_ADC2_JDR4 (STM32_ADC2_BASE + STM32_ADC_JDR4_OFFSET) -# define STM32_ADC2_AWD2CR (STM32_ADC2_BASE + STM32_ADC_AWD2CR_OFFSET) -# define STM32_ADC2_AWD3CR (STM32_ADC2_BASE + STM32_ADC_AWD3CR_OFFSET) -# define STM32_ADC2_DIFSEL (STM32_ADC2_BASE + STM32_ADC_DIFSEL_OFFSET) -# define STM32_ADC2_CALFACT (STM32_ADC2_BASE + STM32_ADC_CALFACT_OFFSET) +# define STM32_ADC2_SMPR1 (STM32_ADC2_BASE + STM32_ADC_SMPR1_OFFSET) +# define STM32_ADC2_SMPR2 (STM32_ADC2_BASE + STM32_ADC_SMPR2_OFFSET) +# define STM32_ADC2_TR1 (STM32_ADC2_BASE + STM32_ADC_TR1_OFFSET) +# define STM32_ADC2_TR2 (STM32_ADC2_BASE + STM32_ADC_TR2_OFFSET) +# define STM32_ADC2_TR3 (STM32_ADC2_BASE + STM32_ADC_TR3_OFFSET) +# define STM32_ADC2_SQR1 (STM32_ADC2_BASE + STM32_ADC_SQR1_OFFSET) +# define STM32_ADC2_SQR2 (STM32_ADC2_BASE + STM32_ADC_SQR2_OFFSET) +# define STM32_ADC2_SQR3 (STM32_ADC2_BASE + STM32_ADC_SQR3_OFFSET) +# define STM32_ADC2_SQR4 (STM32_ADC2_BASE + STM32_ADC_SQR4_OFFSET) +# define STM32_ADC2_DR (STM32_ADC2_BASE + STM32_ADC_DR_OFFSET) +# define STM32_ADC2_JSQR (STM32_ADC2_BASE + STM32_ADC_JSQR_OFFSET) +# define STM32_ADC2_OFR1 (STM32_ADC2_BASE + STM32_ADC_OFR1_OFFSET) +# define STM32_ADC2_OFR2 (STM32_ADC2_BASE + STM32_ADC_OFR2_OFFSET) +# define STM32_ADC2_OFR3 (STM32_ADC2_BASE + STM32_ADC_OFR3_OFFSET) +# define STM32_ADC2_OFR4 (STM32_ADC2_BASE + STM32_ADC_OFR4_OFFSET) +# define STM32_ADC2_JDR1 (STM32_ADC2_BASE + STM32_ADC_JDR1_OFFSET) +# define STM32_ADC2_JDR2 (STM32_ADC2_BASE + STM32_ADC_JDR2_OFFSET) +# define STM32_ADC2_JDR3 (STM32_ADC2_BASE + STM32_ADC_JDR3_OFFSET) +# define STM32_ADC2_JDR4 (STM32_ADC2_BASE + STM32_ADC_JDR4_OFFSET) +# define STM32_ADC2_AWD2CR (STM32_ADC2_BASE + STM32_ADC_AWD2CR_OFFSET) +# define STM32_ADC2_AWD3CR (STM32_ADC2_BASE + STM32_ADC_AWD3CR_OFFSET) +# define STM32_ADC2_DIFSEL (STM32_ADC2_BASE + STM32_ADC_DIFSEL_OFFSET) +# define STM32_ADC2_CALFACT (STM32_ADC2_BASE + STM32_ADC_CALFACT_OFFSET) #endif #if STM32_NADC > 2 -# define STM32_ADC3_ISR (STM32_ADC3_BASE + STM32_ADC_ISR_OFFSET) -# define STM32_ADC3_IER (STM32_ADC3_BASE + STM32_ADC_IER_OFFSET) -# define STM32_ADC3_CR (STM32_ADC3_BASE + STM32_ADC_CR_OFFSET) -# define STM32_ADC3_CFGR1 (STM32_ADC3_BASE + STM32_ADC_CFGR1_OFFSET) +# define STM32_ADC3_ISR (STM32_ADC3_BASE + STM32_ADC_ISR_OFFSET) +# define STM32_ADC3_IER (STM32_ADC3_BASE + STM32_ADC_IER_OFFSET) +# define STM32_ADC3_CR (STM32_ADC3_BASE + STM32_ADC_CR_OFFSET) +# define STM32_ADC3_CFGR1 (STM32_ADC3_BASE + STM32_ADC_CFGR1_OFFSET) # ifdef HAVE_ADC_CFGR2 -# define STM32_ADC3_CFGR2 (STM32_ADC3_BASE + STM32_ADC_CFGR2_OFFSET) +# define STM32_ADC3_CFGR2 (STM32_ADC3_BASE + STM32_ADC_CFGR2_OFFSET) # endif -# define STM32_ADC3_SMPR1 (STM32_ADC3_BASE + STM32_ADC_SMPR1_OFFSET) -# define STM32_ADC3_SMPR2 (STM32_ADC3_BASE + STM32_ADC_SMPR2_OFFSET) -# define STM32_ADC3_TR1 (STM32_ADC3_BASE + STM32_ADC_TR1_OFFSET) -# define STM32_ADC3_TR2 (STM32_ADC3_BASE + STM32_ADC_TR2_OFFSET) -# define STM32_ADC3_TR3 (STM32_ADC3_BASE + STM32_ADC_TR3_OFFSET) -# define STM32_ADC3_SQR1 (STM32_ADC3_BASE + STM32_ADC_SQR1_OFFSET) -# define STM32_ADC3_SQR2 (STM32_ADC3_BASE + STM32_ADC_SQR2_OFFSET) -# define STM32_ADC3_SQR3 (STM32_ADC3_BASE + STM32_ADC_SQR3_OFFSET) -# define STM32_ADC3_SQR4 (STM32_ADC3_BASE + STM32_ADC_SQR4_OFFSET) -# define STM32_ADC3_DR (STM32_ADC3_BASE + STM32_ADC_DR_OFFSET) -# define STM32_ADC3_JSQR (STM32_ADC3_BASE + STM32_ADC_JSQR_OFFSET) -# define STM32_ADC3_OFR1 (STM32_ADC3_BASE + STM32_ADC_OFR1_OFFSET) -# define STM32_ADC3_OFR2 (STM32_ADC3_BASE + STM32_ADC_OFR2_OFFSET) -# define STM32_ADC3_OFR3 (STM32_ADC3_BASE + STM32_ADC_OFR3_OFFSET) -# define STM32_ADC3_OFR4 (STM32_ADC3_BASE + STM32_ADC_OFR4_OFFSET) -# define STM32_ADC3_JDR1 (STM32_ADC3_BASE + STM32_ADC_JDR1_OFFSET) -# define STM32_ADC3_JDR2 (STM32_ADC3_BASE + STM32_ADC_JDR2_OFFSET) -# define STM32_ADC3_JDR3 (STM32_ADC3_BASE + STM32_ADC_JDR3_OFFSET) -# define STM32_ADC3_JDR4 (STM32_ADC3_BASE + STM32_ADC_JDR4_OFFSET) -# define STM32_ADC3_AWD2CR (STM32_ADC3_BASE + STM32_ADC_AWD2CR_OFFSET) -# define STM32_ADC3_AWD3CR (STM32_ADC3_BASE + STM32_ADC_AWD3CR_OFFSET) -# define STM32_ADC3_DIFSEL (STM32_ADC3_BASE + STM32_ADC_DIFSEL_OFFSET) -# define STM32_ADC3_CALFACT (STM32_ADC3_BASE + STM32_ADC_CALFACT_OFFSET) +# define STM32_ADC3_SMPR1 (STM32_ADC3_BASE + STM32_ADC_SMPR1_OFFSET) +# define STM32_ADC3_SMPR2 (STM32_ADC3_BASE + STM32_ADC_SMPR2_OFFSET) +# define STM32_ADC3_TR1 (STM32_ADC3_BASE + STM32_ADC_TR1_OFFSET) +# define STM32_ADC3_TR2 (STM32_ADC3_BASE + STM32_ADC_TR2_OFFSET) +# define STM32_ADC3_TR3 (STM32_ADC3_BASE + STM32_ADC_TR3_OFFSET) +# define STM32_ADC3_SQR1 (STM32_ADC3_BASE + STM32_ADC_SQR1_OFFSET) +# define STM32_ADC3_SQR2 (STM32_ADC3_BASE + STM32_ADC_SQR2_OFFSET) +# define STM32_ADC3_SQR3 (STM32_ADC3_BASE + STM32_ADC_SQR3_OFFSET) +# define STM32_ADC3_SQR4 (STM32_ADC3_BASE + STM32_ADC_SQR4_OFFSET) +# define STM32_ADC3_DR (STM32_ADC3_BASE + STM32_ADC_DR_OFFSET) +# define STM32_ADC3_JSQR (STM32_ADC3_BASE + STM32_ADC_JSQR_OFFSET) +# define STM32_ADC3_OFR1 (STM32_ADC3_BASE + STM32_ADC_OFR1_OFFSET) +# define STM32_ADC3_OFR2 (STM32_ADC3_BASE + STM32_ADC_OFR2_OFFSET) +# define STM32_ADC3_OFR3 (STM32_ADC3_BASE + STM32_ADC_OFR3_OFFSET) +# define STM32_ADC3_OFR4 (STM32_ADC3_BASE + STM32_ADC_OFR4_OFFSET) +# define STM32_ADC3_JDR1 (STM32_ADC3_BASE + STM32_ADC_JDR1_OFFSET) +# define STM32_ADC3_JDR2 (STM32_ADC3_BASE + STM32_ADC_JDR2_OFFSET) +# define STM32_ADC3_JDR3 (STM32_ADC3_BASE + STM32_ADC_JDR3_OFFSET) +# define STM32_ADC3_JDR4 (STM32_ADC3_BASE + STM32_ADC_JDR4_OFFSET) +# define STM32_ADC3_AWD2CR (STM32_ADC3_BASE + STM32_ADC_AWD2CR_OFFSET) +# define STM32_ADC3_AWD3CR (STM32_ADC3_BASE + STM32_ADC_AWD3CR_OFFSET) +# define STM32_ADC3_DIFSEL (STM32_ADC3_BASE + STM32_ADC_DIFSEL_OFFSET) +# define STM32_ADC3_CALFACT (STM32_ADC3_BASE + STM32_ADC_CALFACT_OFFSET) #endif #if STM32_NADC > 3 -# define STM32_ADC4_ISR (STM32_ADC4_BASE + STM32_ADC_ISR_OFFSET) -# define STM32_ADC4_IER (STM32_ADC4_BASE + STM32_ADC_IER_OFFSET) -# define STM32_ADC4_CR (STM32_ADC4_BASE + STM32_ADC_CR_OFFSET) -# define STM32_ADC4_CFGR1 (STM32_ADC4_BASE + STM32_ADC_CFGR1_OFFSET) +# define STM32_ADC4_ISR (STM32_ADC4_BASE + STM32_ADC_ISR_OFFSET) +# define STM32_ADC4_IER (STM32_ADC4_BASE + STM32_ADC_IER_OFFSET) +# define STM32_ADC4_CR (STM32_ADC4_BASE + STM32_ADC_CR_OFFSET) +# define STM32_ADC4_CFGR1 (STM32_ADC4_BASE + STM32_ADC_CFGR1_OFFSET) # ifdef HAVE_ADC_CFGR2 -# define STM32_ADC4_CFGR2 (STM32_ADC4_BASE + STM32_ADC_CFGR2_OFFSET) +# define STM32_ADC4_CFGR2 (STM32_ADC4_BASE + STM32_ADC_CFGR2_OFFSET) # endif -# define STM32_ADC4_SMPR1 (STM32_ADC4_BASE + STM32_ADC_SMPR1_OFFSET) -# define STM32_ADC4_SMPR2 (STM32_ADC4_BASE + STM32_ADC_SMPR2_OFFSET) -# define STM32_ADC4_TR1 (STM32_ADC4_BASE + STM32_ADC_TR1_OFFSET) -# define STM32_ADC4_TR2 (STM32_ADC4_BASE + STM32_ADC_TR2_OFFSET) -# define STM32_ADC4_TR3 (STM32_ADC4_BASE + STM32_ADC_TR3_OFFSET) -# define STM32_ADC4_SQR1 (STM32_ADC4_BASE + STM32_ADC_SQR1_OFFSET) -# define STM32_ADC4_SQR2 (STM32_ADC4_BASE + STM32_ADC_SQR2_OFFSET) -# define STM32_ADC4_SQR3 (STM32_ADC4_BASE + STM32_ADC_SQR3_OFFSET) -# define STM32_ADC4_SQR4 (STM32_ADC4_BASE + STM32_ADC_SQR4_OFFSET) -# define STM32_ADC4_DR (STM32_ADC4_BASE + STM32_ADC_DR_OFFSET) -# define STM32_ADC4_JSQR (STM32_ADC4_BASE + STM32_ADC_JSQR_OFFSET) -# define STM32_ADC4_OFR1 (STM32_ADC4_BASE + STM32_ADC_OFR1_OFFSET) -# define STM32_ADC4_OFR2 (STM32_ADC4_BASE + STM32_ADC_OFR2_OFFSET) -# define STM32_ADC4_OFR3 (STM32_ADC4_BASE + STM32_ADC_OFR3_OFFSET) -# define STM32_ADC4_OFR4 (STM32_ADC4_BASE + STM32_ADC_OFR4_OFFSET) -# define STM32_ADC4_JDR1 (STM32_ADC4_BASE + STM32_ADC_JDR1_OFFSET) -# define STM32_ADC4_JDR2 (STM32_ADC4_BASE + STM32_ADC_JDR2_OFFSET) -# define STM32_ADC4_JDR3 (STM32_ADC4_BASE + STM32_ADC_JDR3_OFFSET) -# define STM32_ADC4_JDR4 (STM32_ADC4_BASE + STM32_ADC_JDR4_OFFSET) -# define STM32_ADC4_AWD2CR (STM32_ADC4_BASE + STM32_ADC_AWD2CR_OFFSET) -# define STM32_ADC4_AWD3CR (STM32_ADC4_BASE + STM32_ADC_AWD3CR_OFFSET) -# define STM32_ADC4_DIFSEL (STM32_ADC4_BASE + STM32_ADC_DIFSEL_OFFSET) -# define STM32_ADC4_CALFACT (STM32_ADC4_BASE + STM32_ADC_CALFACT_OFFSET) +# define STM32_ADC4_SMPR1 (STM32_ADC4_BASE + STM32_ADC_SMPR1_OFFSET) +# define STM32_ADC4_SMPR2 (STM32_ADC4_BASE + STM32_ADC_SMPR2_OFFSET) +# define STM32_ADC4_TR1 (STM32_ADC4_BASE + STM32_ADC_TR1_OFFSET) +# define STM32_ADC4_TR2 (STM32_ADC4_BASE + STM32_ADC_TR2_OFFSET) +# define STM32_ADC4_TR3 (STM32_ADC4_BASE + STM32_ADC_TR3_OFFSET) +# define STM32_ADC4_SQR1 (STM32_ADC4_BASE + STM32_ADC_SQR1_OFFSET) +# define STM32_ADC4_SQR2 (STM32_ADC4_BASE + STM32_ADC_SQR2_OFFSET) +# define STM32_ADC4_SQR3 (STM32_ADC4_BASE + STM32_ADC_SQR3_OFFSET) +# define STM32_ADC4_SQR4 (STM32_ADC4_BASE + STM32_ADC_SQR4_OFFSET) +# define STM32_ADC4_DR (STM32_ADC4_BASE + STM32_ADC_DR_OFFSET) +# define STM32_ADC4_JSQR (STM32_ADC4_BASE + STM32_ADC_JSQR_OFFSET) +# define STM32_ADC4_OFR1 (STM32_ADC4_BASE + STM32_ADC_OFR1_OFFSET) +# define STM32_ADC4_OFR2 (STM32_ADC4_BASE + STM32_ADC_OFR2_OFFSET) +# define STM32_ADC4_OFR3 (STM32_ADC4_BASE + STM32_ADC_OFR3_OFFSET) +# define STM32_ADC4_OFR4 (STM32_ADC4_BASE + STM32_ADC_OFR4_OFFSET) +# define STM32_ADC4_JDR1 (STM32_ADC4_BASE + STM32_ADC_JDR1_OFFSET) +# define STM32_ADC4_JDR2 (STM32_ADC4_BASE + STM32_ADC_JDR2_OFFSET) +# define STM32_ADC4_JDR3 (STM32_ADC4_BASE + STM32_ADC_JDR3_OFFSET) +# define STM32_ADC4_JDR4 (STM32_ADC4_BASE + STM32_ADC_JDR4_OFFSET) +# define STM32_ADC4_AWD2CR (STM32_ADC4_BASE + STM32_ADC_AWD2CR_OFFSET) +# define STM32_ADC4_AWD3CR (STM32_ADC4_BASE + STM32_ADC_AWD3CR_OFFSET) +# define STM32_ADC4_DIFSEL (STM32_ADC4_BASE + STM32_ADC_DIFSEL_OFFSET) +# define STM32_ADC4_CALFACT (STM32_ADC4_BASE + STM32_ADC_CALFACT_OFFSET) #endif #if STM32_NADC > 0 -# define STM32_ADC12_CSR (STM32_ADC12CMN_BASE + STM32_ADC_CSR_OFFSET) -# define STM32_ADC12_CCR (STM32_ADC12CMN_BASE + STM32_ADC_CCR_OFFSET) -# define STM32_ADC12_CDR (STM32_ADC12CMN_BASE + STM32_ADC_CDR_OFFSET) +# define STM32_ADC12_CSR (STM32_ADC12CMN_BASE + STM32_ADC_CSR_OFFSET) +# define STM32_ADC12_CCR (STM32_ADC12CMN_BASE + STM32_ADC_CCR_OFFSET) +# define STM32_ADC12_CDR (STM32_ADC12CMN_BASE + STM32_ADC_CDR_OFFSET) #endif #if STM32_NADC > 2 -# define STM32_ADC34_CSR (STM32_ADC34CMN_BASE + STM32_ADC_CSR_OFFSET) -# define STM32_ADC34_CCR (STM32_ADC34CMN_BASE + STM32_ADC_CCR_OFFSET) -# define STM32_ADC34_CDR (STM32_ADC34CMN_BASE + STM32_ADC_CDR_OFFSET) +# define STM32_ADC34_CSR (STM32_ADC34CMN_BASE + STM32_ADC_CSR_OFFSET) +# define STM32_ADC34_CCR (STM32_ADC34CMN_BASE + STM32_ADC_CCR_OFFSET) +# define STM32_ADC34_CDR (STM32_ADC34CMN_BASE + STM32_ADC_CDR_OFFSET) #endif /* Register Bitfield Definitions ********************************************************************/ /* ADC interrupt and status register (ISR) and ADC interrupt enable register (IER) */ -#define ADC_INT_ARDY (1 << 0) /* Bit 0: ADC ready */ -#define ADC_INT_EOSMP (1 << 1) /* Bit 1: End of sampling flag */ -#define ADC_INT_EOC (1 << 2) /* Bit 2: End of conversion */ -#define ADC_INT_EOS (1 << 3) /* Bit 3: End of regular sequence flag */ -#define ADC_INT_OVR (1 << 4) /* Bit 4: Overrun */ -#define ADC_INT_JEOC (1 << 5) /* Bit 5: Injected channel end of conversion */ -#define ADC_INT_JEOS (1 << 6) /* Bit 6: Injected channel end of sequence flag */ -#define ADC_INT_AWD1 (1 << 7) /* Bit 7: Analog watchdog 1 flag */ -#define ADC_INT_AWD2 (1 << 8) /* Bit 8: Analog watchdog 2 flag */ -#define ADC_INT_AWD3 (1 << 9) /* Bit 9: Analog watchdog 3 flag */ -#define ADC_INT_JQOVF (1 << 10) /* Bit 10: Injected context queue overflow */ +#define ADC_INT_ARDY (1 << 0) /* Bit 0: ADC ready */ +#define ADC_INT_EOSMP (1 << 1) /* Bit 1: End of sampling flag */ +#define ADC_INT_EOC (1 << 2) /* Bit 2: End of conversion */ +#define ADC_INT_EOS (1 << 3) /* Bit 3: End of regular sequence flag */ +#define ADC_INT_OVR (1 << 4) /* Bit 4: Overrun */ +#define ADC_INT_JEOC (1 << 5) /* Bit 5: Injected channel end of conversion */ +#define ADC_INT_JEOS (1 << 6) /* Bit 6: Injected channel end of sequence flag */ +#define ADC_INT_AWD1 (1 << 7) /* Bit 7: Analog watchdog 1 flag */ +#define ADC_INT_AWD2 (1 << 8) /* Bit 8: Analog watchdog 2 flag */ +#define ADC_INT_AWD3 (1 << 9) /* Bit 9: Analog watchdog 3 flag */ +#define ADC_INT_JQOVF (1 << 10) /* Bit 10: Injected context queue overflow */ /* ADC control register */ @@ -375,6 +375,71 @@ # define ADC34_CFGR1_EXTSEL_T7TRGO (13 << ADC_CFGR1_EXTSEL_SHIFT) # define ADC34_CFGR1_EXTSEL_T15TRGO (14 << ADC_CFGR1_EXTSEL_SHIFT) # define ADC34_CFGR1_EXTSEL_T2CC1 (15 << ADC_CFGR1_EXTSEL_SHIFT) +#elif defined(CONFIG_STM32_STM32G47XX) +# define ADC12_CFGR1_EXTSEL_T1CC1 (0 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T1CC2 (1 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T1CC3 (2 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T2CC2 (3 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T3TRGO (4 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T4CC4 (5 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_EXTI11 (6 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T8TRGO (7 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T8TRGO2 (8 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T1TRGO (9 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T1TRGO2 (10 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T2TRGO (11 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T4TRGO (12 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T6TRGO (13 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T15TRGO (14 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T3CC4 (15 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T20TRGO (16 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T20TRGO2 (17 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T20CC1 (18 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T20CC2 (19 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T20CC3 (20 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_HRT1TRG1 (21 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_HRT1TRG3 (22 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_HRT1TRG5 (23 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_HRT1TRG6 (24 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_HRT1TRG7 (25 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_HRT1TRG8 (26 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_HRT1TRG9 (27 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_HRT1TRG10 (28 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_LPTIMOUT (29 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T7TRGO (30 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_RSVD1 (31 << ADC_CFGR1_EXTSEL_SHIFT) /* 11111: Reserved */ +# define ADC34_CFGR1_EXTSEL_T3CC1 (0 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T2CC3 (1 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T1CC3 (2 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T8CC1 (3 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T3TRGO (4 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_EXTI2 (5 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T4CC1 (6 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T8TRGO (7 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T8TRGO2 (8 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T1TRGO (9 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T1TRGO2 (10 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T2TRGO (11 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T4TRGO (12 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T6TRGO (13 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T15TRGO (14 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T2CC1 (15 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T20TRGO (16 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T20TRGO2 (17 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T20CC1 (18 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_HRT1TRG2 (19 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_HRT1TRG4 (20 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_HRT1TRG1 (21 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_HRT1TRG3 (22 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_HRT1TRG5 (23 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_HRT1TRG6 (24 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_HRT1TRG7 (25 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_HRT1TRG8 (26 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_HRT1TRG9 (27 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_HRT1TRG10 (28 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_LPTIMOUT (29 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T7TRGO (30 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_RSVD1 (31 << ADC_CFGR1_EXTSEL_SHIFT) /* 11111: Reserved */ #else # error TODO EXTSEL #endif @@ -406,201 +471,267 @@ /* ADC sample time register 1 */ -#define ADC_SMPR_1p5 0 /* 000: 1.5 cycles */ -#define ADC_SMPR_2p5 1 /* 001: 2.5 cycles */ -#define ADC_SMPR_4p5 2 /* 010: 4.5 cycles */ -#define ADC_SMPR_7p5 3 /* 011: 7.5 cycles */ -#define ADC_SMPR_19p5 4 /* 100: 19.5 cycles */ -#define ADC_SMPR_61p5 5 /* 101: 61.5 cycles */ -#define ADC_SMPR_181p5 6 /* 110: 181.5 cycles */ -#define ADC_SMPR_601p5 7 /* 111: 601.5 cycles */ +#define ADC_SMPR_1p5 0 /* 000: 1.5 cycles */ +#define ADC_SMPR_2p5 1 /* 001: 2.5 cycles */ +#define ADC_SMPR_4p5 2 /* 010: 4.5 cycles */ +#define ADC_SMPR_7p5 3 /* 011: 7.5 cycles */ +#define ADC_SMPR_19p5 4 /* 100: 19.5 cycles */ +#define ADC_SMPR_61p5 5 /* 101: 61.5 cycles */ +#define ADC_SMPR_181p5 6 /* 110: 181.5 cycles */ +#define ADC_SMPR_601p5 7 /* 111: 601.5 cycles */ -#define ADC_SMPR1_SMP1_SHIFT (3) /* Bits 5-3: Channel 1 Sample time selection */ -#define ADC_SMPR1_SMP1_MASK (7 << ADC_SMPR1_SMP1_SHIFT) -#define ADC_SMPR1_SMP2_SHIFT (6) /* Bits 8-6: Channel 2 Sample time selection */ -#define ADC_SMPR1_SMP2_MASK (7 << ADC_SMPR1_SMP2_SHIFT) -#define ADC_SMPR1_SMP3_SHIFT (9) /* Bits 11-9: Channel 3 Sample time selection */ -#define ADC_SMPR1_SMP3_MASK (7 << ADC_SMPR1_SMP3_SHIFT) -#define ADC_SMPR1_SMP4_SHIFT (12) /* Bits 14-12: Channel 4 Sample time selection */ -#define ADC_SMPR1_SMP4_MASK (7 << ADC_SMPR1_SMP4_SHIFT) -#define ADC_SMPR1_SMP5_SHIFT (15) /* Bits 17-15: Channel 5 Sample time selection */ -#define ADC_SMPR1_SMP5_MASK (7 << ADC_SMPR1_SMP5_SHIFT) -#define ADC_SMPR1_SMP6_SHIFT (18) /* Bits 20-18: Channel 6 Sample time selection */ -#define ADC_SMPR1_SMP6_MASK (7 << ADC_SMPR1_SMP6_SHIFT) -#define ADC_SMPR1_SMP7_SHIFT (21) /* Bits 23-21: Channel 7 Sample time selection */ -#define ADC_SMPR1_SMP7_MASK (7 << ADC_SMPR1_SMP7_SHIFT) -#define ADC_SMPR1_SMP8_SHIFT (24) /* Bits 26-24: Channel 8 Sample time selection */ -#define ADC_SMPR1_SMP8_MASK (7 << ADC_SMPR1_SMP8_SHIFT) -#define ADC_SMPR1_SMP9_SHIFT (27) /* Bits 29-27: Channel 9 Sample time selection */ -#define ADC_SMPR1_SMP9_MASK (7 << ADC_SMPR1_SMP9_SHIFT) +#define ADC_SMPR1_SMP1_SHIFT (3) /* Bits 5-3: Channel 1 Sample time selection */ +#define ADC_SMPR1_SMP1_MASK (7 << ADC_SMPR1_SMP1_SHIFT) +#define ADC_SMPR1_SMP2_SHIFT (6) /* Bits 8-6: Channel 2 Sample time selection */ +#define ADC_SMPR1_SMP2_MASK (7 << ADC_SMPR1_SMP2_SHIFT) +#define ADC_SMPR1_SMP3_SHIFT (9) /* Bits 11-9: Channel 3 Sample time selection */ +#define ADC_SMPR1_SMP3_MASK (7 << ADC_SMPR1_SMP3_SHIFT) +#define ADC_SMPR1_SMP4_SHIFT (12) /* Bits 14-12: Channel 4 Sample time selection */ +#define ADC_SMPR1_SMP4_MASK (7 << ADC_SMPR1_SMP4_SHIFT) +#define ADC_SMPR1_SMP5_SHIFT (15) /* Bits 17-15: Channel 5 Sample time selection */ +#define ADC_SMPR1_SMP5_MASK (7 << ADC_SMPR1_SMP5_SHIFT) +#define ADC_SMPR1_SMP6_SHIFT (18) /* Bits 20-18: Channel 6 Sample time selection */ +#define ADC_SMPR1_SMP6_MASK (7 << ADC_SMPR1_SMP6_SHIFT) +#define ADC_SMPR1_SMP7_SHIFT (21) /* Bits 23-21: Channel 7 Sample time selection */ +#define ADC_SMPR1_SMP7_MASK (7 << ADC_SMPR1_SMP7_SHIFT) +#define ADC_SMPR1_SMP8_SHIFT (24) /* Bits 26-24: Channel 8 Sample time selection */ +#define ADC_SMPR1_SMP8_MASK (7 << ADC_SMPR1_SMP8_SHIFT) +#define ADC_SMPR1_SMP9_SHIFT (27) /* Bits 29-27: Channel 9 Sample time selection */ +#define ADC_SMPR1_SMP9_MASK (7 << ADC_SMPR1_SMP9_SHIFT) /* ADC sample time register 2 */ -#define ADC_SMPR2_SMP10_SHIFT (0) /* Bits 0-2: Channel 10 Sample time selection */ -#define ADC_SMPR2_SMP10_MASK (7 << ADC_SMPR2_SMP10_SHIFT) -#define ADC_SMPR2_SMP11_SHIFT (3) /* Bits 3-5: Channel 11 Sample time selection */ -#define ADC_SMPR2_SMP11_MASK (7 << ADC_SMPR2_SMP11_SHIFT) -#define ADC_SMPR2_SMP12_SHIFT (6) /* Bits 6-8: Channel 12 Sample time selection */ -#define ADC_SMPR2_SMP12_MASK (7 << ADC_SMPR2_SMP12_SHIFT) -#define ADC_SMPR2_SMP13_SHIFT (9) /* Bits 9-11: Channel 13 Sample time selection */ -#define ADC_SMPR2_SMP13_MASK (7 << ADC_SMPR2_SMP13_SHIFT) -#define ADC_SMPR2_SMP14_SHIFT (12) /* Bits 12-14: Channel 14 Sample time selection */ -#define ADC_SMPR2_SMP14_MASK (7 << ADC_SMPR2_SMP14_SHIFT) -#define ADC_SMPR2_SMP15_SHIFT (15) /* Bits 15-17: Channel 15 Sample time selection */ -#define ADC_SMPR2_SMP15_MASK (7 << ADC_SMPR2_SMP15_SHIFT) -#define ADC_SMPR2_SMP16_SHIFT (18) /* Bits 18-20: Channel 16 Sample time selection */ -#define ADC_SMPR2_SMP16_MASK (7 << ADC_SMPR2_SMP16_SHIFT) -#define ADC_SMPR2_SMP17_SHIFT (21) /* Bits 21-23: Channel 17 Sample time selection */ -#define ADC_SMPR2_SMP17_MASK (7 << ADC_SMPR2_SMP17_SHIFT) -#define ADC_SMPR2_SMP18_SHIFT (24) /* Bits 24-26: Channel 18 Sample time selection */ -#define ADC_SMPR2_SMP18_MASK (7 << ADC_SMPR2_SMP18_SHIFT) +#define ADC_SMPR2_SMP10_SHIFT (0) /* Bits 0-2: Channel 10 Sample time selection */ +#define ADC_SMPR2_SMP10_MASK (7 << ADC_SMPR2_SMP10_SHIFT) +#define ADC_SMPR2_SMP11_SHIFT (3) /* Bits 3-5: Channel 11 Sample time selection */ +#define ADC_SMPR2_SMP11_MASK (7 << ADC_SMPR2_SMP11_SHIFT) +#define ADC_SMPR2_SMP12_SHIFT (6) /* Bits 6-8: Channel 12 Sample time selection */ +#define ADC_SMPR2_SMP12_MASK (7 << ADC_SMPR2_SMP12_SHIFT) +#define ADC_SMPR2_SMP13_SHIFT (9) /* Bits 9-11: Channel 13 Sample time selection */ +#define ADC_SMPR2_SMP13_MASK (7 << ADC_SMPR2_SMP13_SHIFT) +#define ADC_SMPR2_SMP14_SHIFT (12) /* Bits 12-14: Channel 14 Sample time selection */ +#define ADC_SMPR2_SMP14_MASK (7 << ADC_SMPR2_SMP14_SHIFT) +#define ADC_SMPR2_SMP15_SHIFT (15) /* Bits 15-17: Channel 15 Sample time selection */ +#define ADC_SMPR2_SMP15_MASK (7 << ADC_SMPR2_SMP15_SHIFT) +#define ADC_SMPR2_SMP16_SHIFT (18) /* Bits 18-20: Channel 16 Sample time selection */ +#define ADC_SMPR2_SMP16_MASK (7 << ADC_SMPR2_SMP16_SHIFT) +#define ADC_SMPR2_SMP17_SHIFT (21) /* Bits 21-23: Channel 17 Sample time selection */ +#define ADC_SMPR2_SMP17_MASK (7 << ADC_SMPR2_SMP17_SHIFT) +#define ADC_SMPR2_SMP18_SHIFT (24) /* Bits 24-26: Channel 18 Sample time selection */ +#define ADC_SMPR2_SMP18_MASK (7 << ADC_SMPR2_SMP18_SHIFT) /* ADC watchdog threshold register 1 */ -#define ADC_TR1_LT_SHIFT (0) /* Bits 0-11: Analog watchdog 1 lower threshold */ -#define ADC_TR1_LT_MASK (0x0fff << ADC_TR1_LT_SHIFT) -#define ADC_TR1_HT_SHIFT (16) /* Bits 16-27: Analog watchdog 1 higher threshold */ -#define ADC_TR1_HT_MASK (0x0fff << ADC_TR1_HT_SHIFT) +#define ADC_TR1_LT_SHIFT (0) /* Bits 0-11: Analog watchdog 1 lower threshold */ +#define ADC_TR1_LT_MASK (0x0fff << ADC_TR1_LT_SHIFT) +#define ADC_TR1_HT_SHIFT (16) /* Bits 16-27: Analog watchdog 1 higher threshold */ +#define ADC_TR1_HT_MASK (0x0fff << ADC_TR1_HT_SHIFT) /* ADC watchdog threshold register 2 */ -#define ADC_TR2_LT_SHIFT (0) /* Bits 0-7: Analog watchdog 2 lower threshold */ -#define ADC_TR2_LT_MASK (0xff << ADC_TR2_LT_SHIFT) -#define ADC_TR2_HT_SHIFT (16) /* Bits 16-23: Analog watchdog 2 higher threshold */ -#define ADC_TR2_HT_MASK (0xff << ADC_TR2_HT_SHIFT) +#define ADC_TR2_LT_SHIFT (0) /* Bits 0-7: Analog watchdog 2 lower threshold */ +#define ADC_TR2_LT_MASK (0xff << ADC_TR2_LT_SHIFT) +#define ADC_TR2_HT_SHIFT (16) /* Bits 16-23: Analog watchdog 2 higher threshold */ +#define ADC_TR2_HT_MASK (0xff << ADC_TR2_HT_SHIFT) /* ADC watchdog threshold register 3 */ -#define ADC_TR3_LT_SHIFT (0) /* Bits 0-7: Analog watchdog 3 lower threshold */ -#define ADC_TR3_LT_MASK (0xff << ADC_TR3_LT_SHIFT) -#define ADC_TR3_HT_SHIFT (16) /* Bits 16-23: Analog watchdog 3 higher threshold */ -#define ADC_TR3_HT_MASK (0xff << ADC_TR3_HT_SHIFT) +#define ADC_TR3_LT_SHIFT (0) /* Bits 0-7: Analog watchdog 3 lower threshold */ +#define ADC_TR3_LT_MASK (0xff << ADC_TR3_LT_SHIFT) +#define ADC_TR3_HT_SHIFT (16) /* Bits 16-23: Analog watchdog 3 higher threshold */ +#define ADC_TR3_HT_MASK (0xff << ADC_TR3_HT_SHIFT) /* Offset between SQ bits */ -#define ADC_SQ_OFFSET (6) +#define ADC_SQ_OFFSET (6) /* ADC regular sequence register 1 */ -#define ADC_SQR1_L_SHIFT (0) /* Bits 0-3: Regular channel sequence length */ -#define ADC_SQR1_L_MASK (0x0f << ADC_SQR1_L_SHIFT) -#define ADC_SQR1_SQ1_SHIFT (6) /* Bits 6-10: 13th conversion in regular sequence */ -#define ADC_SQR1_SQ1_MASK (0x1f << ADC_SQR1_SQ1_SHIFT) -#define ADC_SQR1_SQ2_SHIFT (12) /* Bits 12-16: 2nd conversion in regular sequence */ -#define ADC_SQR1_SQ2_MASK (0x1f << ADC_SQR1_SQ2_SHIFT) -#define ADC_SQR1_SQ3_SHIFT (18) /* Bits 18-22: 3rd conversion in regular sequence */ -#define ADC_SQR1_SQ3_MASK (0x1f << ADC_SQR1_SQ3_SHIFT) -#define ADC_SQR1_SQ4_SHIFT (24) /* Bits 24-28: 4th conversion in regular sequence */ -#define ADC_SQR1_SQ4_MASK (0x1f << ADC_SQR1_SQ4_SHIFT) -#define ADC_SQR1_RESERVED (0xe0820830) -#define ADC_SQR1_FIRST (1) -#define ADC_SQR1_LAST (4) -#define ADC_SQR1_SQ_OFFSET (1*ADC_SQ_OFFSET) +#define ADC_SQR1_L_SHIFT (0) /* Bits 0-3: Regular channel sequence length */ +#define ADC_SQR1_L_MASK (0x0f << ADC_SQR1_L_SHIFT) +#define ADC_SQR1_SQ1_SHIFT (6) /* Bits 6-10: 13th conversion in regular sequence */ +#define ADC_SQR1_SQ1_MASK (0x1f << ADC_SQR1_SQ1_SHIFT) +#define ADC_SQR1_SQ2_SHIFT (12) /* Bits 12-16: 2nd conversion in regular sequence */ +#define ADC_SQR1_SQ2_MASK (0x1f << ADC_SQR1_SQ2_SHIFT) +#define ADC_SQR1_SQ3_SHIFT (18) /* Bits 18-22: 3rd conversion in regular sequence */ +#define ADC_SQR1_SQ3_MASK (0x1f << ADC_SQR1_SQ3_SHIFT) +#define ADC_SQR1_SQ4_SHIFT (24) /* Bits 24-28: 4th conversion in regular sequence */ +#define ADC_SQR1_SQ4_MASK (0x1f << ADC_SQR1_SQ4_SHIFT) +#define ADC_SQR1_RESERVED (0xe0820830) +#define ADC_SQR1_FIRST (1) +#define ADC_SQR1_LAST (4) +#define ADC_SQR1_SQ_OFFSET (1*ADC_SQ_OFFSET) /* ADC regular sequence register 2 */ -#define ADC_SQR2_SQ5_SHIFT (0) /* Bits 4-0: 5th conversion in regular sequence */ -#define ADC_SQR2_SQ5_MASK (0x1f << ADC_SQR2_SQ5_SHIFT) -#define ADC_SQR2_SQ6_SHIFT (6) /* Bits 6-10: 6th conversion in regular sequence */ -#define ADC_SQR2_SQ6_MASK (0x1f << ADC_SQR2_SQ6_SHIFT) -#define ADC_SQR2_SQ7_SHIFT (12) /* Bits 12-16: 7th conversion in regular sequence */ -#define ADC_SQR2_SQ7_MASK (0x1f << ADC_SQR2_SQ7_SHIFT) -#define ADC_SQR2_SQ8_SHIFT (18) /* Bits 18-22: 8th conversion in regular sequence */ -#define ADC_SQR2_SQ8_MASK (0x1f << ADC_SQR2_SQ8_SHIFT) -#define ADC_SQR2_SQ9_SHIFT (24) /* Bits 24-28: 9th conversion in regular sequence */ -#define ADC_SQR2_SQ9_MASK (0x1f << ADC_SQR2_SQ9_SHIFT) -#define ADC_SQR2_RESERVED (0xe0820820) -#define ADC_SQR2_FIRST (5) -#define ADC_SQR2_LAST (9) -#define ADC_SQR2_SQ_OFFSET (0) +#define ADC_SQR2_SQ5_SHIFT (0) /* Bits 4-0: 5th conversion in regular sequence */ +#define ADC_SQR2_SQ5_MASK (0x1f << ADC_SQR2_SQ5_SHIFT) +#define ADC_SQR2_SQ6_SHIFT (6) /* Bits 6-10: 6th conversion in regular sequence */ +#define ADC_SQR2_SQ6_MASK (0x1f << ADC_SQR2_SQ6_SHIFT) +#define ADC_SQR2_SQ7_SHIFT (12) /* Bits 12-16: 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_MASK (0x1f << ADC_SQR2_SQ7_SHIFT) +#define ADC_SQR2_SQ8_SHIFT (18) /* Bits 18-22: 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_MASK (0x1f << ADC_SQR2_SQ8_SHIFT) +#define ADC_SQR2_SQ9_SHIFT (24) /* Bits 24-28: 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_MASK (0x1f << ADC_SQR2_SQ9_SHIFT) +#define ADC_SQR2_RESERVED (0xe0820820) +#define ADC_SQR2_FIRST (5) +#define ADC_SQR2_LAST (9) +#define ADC_SQR2_SQ_OFFSET (0) /* ADC regular sequence register 3 */ -#define ADC_SQR3_SQ10_SHIFT (0) /* Bits 4-0: 10th conversion in regular sequence */ -#define ADC_SQR3_SQ10_MASK (0x1f << ADC_SQR3_SQ10_SHIFT) -#define ADC_SQR3_SQ11_SHIFT (6) /* Bits 6-10: 11th conversion in regular sequence */ -#define ADC_SQR3_SQ11_MASK (0x1f << ADC_SQR3_SQ11_SHIFT) -#define ADC_SQR3_SQ12_SHIFT (12) /* Bits 12-16: 12th conversion in regular sequence */ -#define ADC_SQR3_SQ12_MASK (0x1f << ADC_SQR3_SQ12_SHIFT) -#define ADC_SQR3_SQ13_SHIFT (18) /* Bits 18-22: 13th conversion in regular sequence */ -#define ADC_SQR3_SQ13_MASK (0x1f << ADC_SQR3_SQ13_SHIFT) -#define ADC_SQR3_SQ14_SHIFT (24) /* Bits 24-28: 14th conversion in regular sequence */ -#define ADC_SQR3_SQ14_MASK (0x1f << ADC_SQR3_SQ14_SHIFT) -#define ADC_SQR3_RESERVED (0xe0820820) -#define ADC_SQR3_FIRST (10) -#define ADC_SQR3_LAST (14) -#define ADC_SQR3_SQ_OFFSET (0) +#define ADC_SQR3_SQ10_SHIFT (0) /* Bits 4-0: 10th conversion in regular sequence */ +#define ADC_SQR3_SQ10_MASK (0x1f << ADC_SQR3_SQ10_SHIFT) +#define ADC_SQR3_SQ11_SHIFT (6) /* Bits 6-10: 11th conversion in regular sequence */ +#define ADC_SQR3_SQ11_MASK (0x1f << ADC_SQR3_SQ11_SHIFT) +#define ADC_SQR3_SQ12_SHIFT (12) /* Bits 12-16: 12th conversion in regular sequence */ +#define ADC_SQR3_SQ12_MASK (0x1f << ADC_SQR3_SQ12_SHIFT) +#define ADC_SQR3_SQ13_SHIFT (18) /* Bits 18-22: 13th conversion in regular sequence */ +#define ADC_SQR3_SQ13_MASK (0x1f << ADC_SQR3_SQ13_SHIFT) +#define ADC_SQR3_SQ14_SHIFT (24) /* Bits 24-28: 14th conversion in regular sequence */ +#define ADC_SQR3_SQ14_MASK (0x1f << ADC_SQR3_SQ14_SHIFT) +#define ADC_SQR3_RESERVED (0xe0820820) +#define ADC_SQR3_FIRST (10) +#define ADC_SQR3_LAST (14) +#define ADC_SQR3_SQ_OFFSET (0) /* ADC regular sequence register 4 */ -#define ADC_SQR4_SQ15_SHIFT (0) /* Bits 4-0: 15th conversion in regular sequence */ -#define ADC_SQR4_SQ15_MASK (0x1f << ADC_SQR4_SQ15_SHIFT) -#define ADC_SQR4_SQ16_SHIFT (6) /* Bits 6-10: 16th conversion in regular sequence */ -#define ADC_SQR4_SQ16_MASK (0x1f << ADC_SQR4_SQ16_SHIFT) -#define ADC_SQR4_RESERVED (0xfffff820) -#define ADC_SQR4_FIRST (15) -#define ADC_SQR4_LAST (16) -#define ADC_SQR4_SQ_OFFSET (0) +#define ADC_SQR4_SQ15_SHIFT (0) /* Bits 4-0: 15th conversion in regular sequence */ +#define ADC_SQR4_SQ15_MASK (0x1f << ADC_SQR4_SQ15_SHIFT) +#define ADC_SQR4_SQ16_SHIFT (6) /* Bits 6-10: 16th conversion in regular sequence */ +#define ADC_SQR4_SQ16_MASK (0x1f << ADC_SQR4_SQ16_SHIFT) +#define ADC_SQR4_RESERVED (0xfffff820) +#define ADC_SQR4_FIRST (15) +#define ADC_SQR4_LAST (16) +#define ADC_SQR4_SQ_OFFSET (0) /* ADC regular data register */ -#define ADC_DR_RDATA_SHIFT (0) -#define ADC_DR_RDATA_MASK (0xffff << ADC_DR_RDATA_SHIFT) +#define ADC_DR_RDATA_SHIFT (0) +#define ADC_DR_RDATA_MASK (0xffff << ADC_DR_RDATA_SHIFT) /* ADC injected sequence register */ -#define ADC_JSQR_JL_SHIFT (0) /* Bits 0-1: Injected Sequence length */ -#define ADC_JSQR_JL_MASK (2 << ADC_JSQR_JL_SHIFT) -# define ADC_JSQR_JL(n) (((n)-1) << ADC_JSQR_JL_SHIFT) /* n=1..4 */ -#define ADC_JSQR_JEXTSEL_SHIFT (2) /* Bits 2-5: External Trigger Selection for injected group */ -#define ADC_JSQR_JEXTSEL_MASK (15 << ADC_JSQR_JEXTSEL_SHIFT) +#define ADC_JSQR_JL_SHIFT (0) /* Bits 0-1: Injected Sequence length */ +#define ADC_JSQR_JL_MASK (2 << ADC_JSQR_JL_SHIFT) +# define ADC_JSQR_JL(n) (((n)-1) << ADC_JSQR_JL_SHIFT) /* n=1..4 */ +#define ADC_JSQR_JEXTSEL_SHIFT (2) /* Bits 2-5: External Trigger Selection for injected group */ +#define ADC_JSQR_JEXTSEL_MASK (15 << ADC_JSQR_JEXTSEL_SHIFT) #if defined(CONFIG_STM32_STM32F33XX) -# define ADC12_JSQR_JEXTSEL_T1TRGO (0 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T1CC4 (1 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T2TRGO (2 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T2CC1 (3 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T3CC4 (4 << ADC_JSQR_JEXTSEL_SHIFT) - /* 0101: Reserved */ -# define ADC12_JSQR_JEXTSEL_EXTI15 (6 << ADC_JSQR_JEXTSEL_SHIFT) /* 0110: EXTI line 15 */ - /* 0111: Reserved */ -# define ADC12_JSQR_JEXTSEL_T1TRGO2 (8 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_HRT1TRG2 (9 << ADC_JSQR_JEXTSEL_SHIFT) /* 1001: HRTIM1 ADCTRG2 event */ -# define ADC12_JSQR_JEXTSEL_HRT1TRG4 (10 << ADC_JSQR_JEXTSEL_SHIFT) /* 1010: HRTIM1 ADCTRG4 event */ -# define ADC12_JSQR_JEXTSEL_T3CC3 (11 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T3TRGO (12 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T3CC1 (13 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T6TRGO (14 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T15TRGO (15 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T1TRGO (0 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T1CC4 (1 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T2TRGO (2 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T2CC1 (3 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T3CC4 (4 << ADC_JSQR_JEXTSEL_SHIFT) + /* 0101: Reserved */ +# define ADC12_JSQR_JEXTSEL_EXTI15 (6 << ADC_JSQR_JEXTSEL_SHIFT) /* 0110: EXTI line 15 */ + /* 0111: Reserved */ +# define ADC12_JSQR_JEXTSEL_T1TRGO2 (8 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_HRT1TRG2 (9 << ADC_JSQR_JEXTSEL_SHIFT) /* 1001: HRTIM1 ADCTRG2 event */ +# define ADC12_JSQR_JEXTSEL_HRT1TRG4 (10 << ADC_JSQR_JEXTSEL_SHIFT) /* 1010: HRTIM1 ADCTRG4 event */ +# define ADC12_JSQR_JEXTSEL_T3CC3 (11 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T3TRGO (12 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T3CC1 (13 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T6TRGO (14 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T15TRGO (15 << ADC_JSQR_JEXTSEL_SHIFT) #elif defined(CONFIG_STM32_STM32F30XX) -# define ADC12_JSQR_JEXTSEL_T1TRGO (0 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T1CC4 (1 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T2TRGO (2 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T2CC1 (3 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T3CC4 (4 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T4TRGO (5 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T20TRGO (6 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T8CC4 (7 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T1TRGO2 (8 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T8TRGO (9 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T3CC3 (11 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T3TRGO (12 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T3CC1 (13 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T6TRGO (14 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T15TRGO (15 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T1TRGO (0 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T1CC4 (1 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T4CC3 (2 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T8CC2 (3 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T8CC4 (4 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T20TRGO (5 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T4CC4 (6 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T4TRGO (7 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T8TRGO (9 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T1CC3 (11 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T3TRGO (12 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T2TRGO (13 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T7TRGO (14 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T15TRGO (15 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T1TRGO (0 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T1CC4 (1 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T2TRGO (2 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T2CC1 (3 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T3CC4 (4 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T4TRGO (5 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T20TRGO (6 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T8CC4 (7 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T1TRGO2 (8 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T8TRGO (9 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T3CC3 (11 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T3TRGO (12 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T3CC1 (13 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T6TRGO (14 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T15TRGO (15 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T1TRGO (0 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T1CC4 (1 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T4CC3 (2 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T8CC2 (3 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T8CC4 (4 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T20TRGO (5 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T4CC4 (6 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T4TRGO (7 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T8TRGO (9 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T1CC3 (11 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T3TRGO (12 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T2TRGO (13 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T7TRGO (14 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T15TRGO (15 << ADC_JSQR_JEXTSEL_SHIFT) +#elif defined(CONFIG_STM32_STM32G47XX) +# define ADC12_JSQR_JEXTSEL_T1TRGO (0 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T1CC4 (1 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T2TRGO (2 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T2CC1 (3 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T3CC4 (4 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T4TRGO (5 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_EXTI15 (6 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T8CC4 (7 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T1TRGO2 (8 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T8TRGO (9 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T8TRGO2 (10 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T3CC3 (11 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T3TRGO (12 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T3CC1 (13 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T6TRGO (14 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T15TRGO (15 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T20TRGO (16 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T20TRGO2 (17 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T20CC4 (18 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_HRT1TRG2 (19 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_HRT1TRG4 (20 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_HRT1TRG5 (21 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_HRT1TRG6 (22 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_HRT1TRG7 (23 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_HRT1TRG8 (24 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_HRT1TRG9 (25 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_HRT1TRG10 (26 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T16CC1 (27 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_RSVD1 (28 << ADC_JSQR_JEXTSEL_SHIFT) /* 11100: Reserved */ +# define ADC12_JSQR_JEXTSEL_LPTIMOUT (29 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T7TRGO (30 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_RSVD2 (31 << ADC_JSQR_JEXTSEL_SHIFT) /* 11111: Reserved */ + +# define ADC34_JSQR_JEXTSEL_T1TRGO (0 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T1CC4 (1 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T2TRGO (2 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T8CC2 (3 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T4CC3 (4 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T4TRGO (5 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T4CC4 (6 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T8CC4 (7 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T1TRGO2 (8 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T8TRGO (9 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T8TRGO2 (10 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T1CC3 (11 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T3TRGO (12 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_EXTI3 (13 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T6TRGO (14 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T15TRGO (15 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T20TRGO (16 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T20TRGO2 (17 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T20CC2 (18 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_HRT1TRG2 (19 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_HRT1TRG4 (20 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_HRT1TRG5 (21 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_HRT1TRG6 (22 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_HRT1TRG7 (23 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_HRT1TRG8 (24 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_HRT1TRG9 (25 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_HRT1TRG10 (26 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_HRT1TRG1 (27 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_HRT1TRG3 (28 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_LPTIMOUT (29 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T7TRGO (30 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_RSVD1 (31 << ADC_JSQR_JEXTSEL_SHIFT) /* 11111: Reserved */ #else # error TODO JEXTSEL #endif @@ -626,69 +757,69 @@ /* ADC offset register 1 and 2 */ -#define ADC_OFR_OFFSETY_SHIFT (0) /* Bits 0-11: Data offset y for channel OFFSETY_CH */ -#define ADC_OFR_OFFSETY_MASK (0x0fff << ADC_OFR_OFFSETY_SHIFT) -# define ADC_OFR_OFFSETY(offset) ((offset) << ADC_OFR_OFFSETY_SHIFT) -#define ADC_OFR_OFFSETY_CH_SHIFT (26) /* Bits 26-30: Channel selection for data offset y */ -#define ADC_OFR_OFFSETY_CH_MASK (31 << ADC_OFR_OFFSETY_CH_SHIFT) -# define ADC_OFR_OFFSETY_CH(ch) ((ch) << ADC_OFR_OFFSETY_CH_SHIFT) -#define ADC_OFR_OFFSETY_EN (1 << 31) /* Bit 31: Offset y enable */ +#define ADC_OFR_OFFSETY_SHIFT (0) /* Bits 0-11: Data offset y for channel OFFSETY_CH */ +#define ADC_OFR_OFFSETY_MASK (0x0fff << ADC_OFR_OFFSETY_SHIFT) +# define ADC_OFR_OFFSETY(offset) ((offset) << ADC_OFR_OFFSETY_SHIFT) +#define ADC_OFR_OFFSETY_CH_SHIFT (26) /* Bits 26-30: Channel selection for data offset y */ +#define ADC_OFR_OFFSETY_CH_MASK (31 << ADC_OFR_OFFSETY_CH_SHIFT) +# define ADC_OFR_OFFSETY_CH(ch) ((ch) << ADC_OFR_OFFSETY_CH_SHIFT) +#define ADC_OFR_OFFSETY_EN (1 << 31) /* Bit 31: Offset y enable */ /* ADC injected data register 1 and 2 */ -#define ADC_JDR_JDATA_SHIFT (0) -#define ADC_JDR_JDATA_MASK (0xffff << ADC_JDR_JDATA_SHIFT) +#define ADC_JDR_JDATA_SHIFT (0) +#define ADC_JDR_JDATA_MASK (0xffff << ADC_JDR_JDATA_SHIFT) /* ADC analog watchdog 2 configuration register */ -#define ADC_AWD2CR_CH_SHIFT (1) /* Bits 1-18: Analog watchdog 2 channel selection */ -#define ADC_AWD2CR_CH_MASK (0x3ffff << ADC_AWD2CR_CH_SHIFT) -# define ADC_AWD2CR_CH(n) (1 << (n)) /* Channel n=1..18 */ +#define ADC_AWD2CR_CH_SHIFT (1) /* Bits 1-18: Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_CH_MASK (0x3ffff << ADC_AWD2CR_CH_SHIFT) +# define ADC_AWD2CR_CH(n) (1 << (n)) /* Channel n=1..18 */ /* ADC analog watchdog 3 configuration register */ -#define ADC_AWD3CR_CH_SHIFT (1) /* Bits 1-18: Analog watchdog 2 channel selection */ -#define ADC_AWD3CR_CH_MASK (0x3ffff << ADC_AWD3CR_CH_SHIFT) -# define ADC_AWD3CR_CH(n) (1 << (n)) /* Channel n=1..18 */ +#define ADC_AWD3CR_CH_SHIFT (1) /* Bits 1-18: Analog watchdog 2 channel selection */ +#define ADC_AWD3CR_CH_MASK (0x3ffff << ADC_AWD3CR_CH_SHIFT) +# define ADC_AWD3CR_CH(n) (1 << (n)) /* Channel n=1..18 */ /* ADC differential mode selection register 2 */ #define ADC_DIFSEL_ -#define ADC_DIFSEL_CH_SHIFT (1) /* Bits 1-18: Analog watchdog 2 channel selection */ -#define ADC_DIFSEL_CH_MASK (0x3ffff << ADC_DIFSEL_CH_SHIFT) -# define ADC_DIFSEL_CH(n) (1 << (n)) /* Channel n=1..18 */ +#define ADC_DIFSEL_CH_SHIFT (1) /* Bits 1-18: Analog watchdog 2 channel selection */ +#define ADC_DIFSEL_CH_MASK (0x3ffff << ADC_DIFSEL_CH_SHIFT) +# define ADC_DIFSEL_CH(n) (1 << (n)) /* Channel n=1..18 */ /* ADC calibration factors */ -#define ADC_CALFACT_S_SHIFT (0) /* Bits 0-6: Calibration factors in single-ended mode */ -#define ADC_CALFACT_S_MASK (0x7f << ADC_CALFACT_S_SHIFT) -#define ADC_CALFACT_D_SHIFT (16) /* Bits 16-22: Calibration Factors indifferential mode */ -#define ADC_CALFACT_D_MASK (0x7f << ADC_CALFACT_D_SHIFT) +#define ADC_CALFACT_S_SHIFT (0) /* Bits 0-6: Calibration factors in single-ended mode */ +#define ADC_CALFACT_S_MASK (0x7f << ADC_CALFACT_S_SHIFT) +#define ADC_CALFACT_D_SHIFT (16) /* Bits 16-22: Calibration Factors indifferential mode */ +#define ADC_CALFACT_D_MASK (0x7f << ADC_CALFACT_D_SHIFT) /* Common status register */ -#define ADC_CSR_ADRDY_MST (1 << 0) /* Bit 0: Master ADC ready */ -#define ADC_CSR_EOSMP_MST (1 << 1) /* Bit 1: End of Sampling phase flag (master ADC) */ -#define ADC_CSR_EOC_MST (1 << 2) /* Bit 2: End of regular conversion (master ADC) */ -#define ADC_CSR_EOS_MST (1 << 3) /* Bit 3: End of regular sequence flag (master ADC) */ -#define ADC_CSR_OVR_MST (1 << 4) /* Bit 4: Overrun flag (master ADC) */ -#define ADC_CSR_JEOC_MST (1 << 5) /* Bit 5: End of injected conversion flag (master ADC) */ -#define ADC_CSR_JEOS_MST (1 << 6) /* Bit 6: End of injected sequence flag (master ADC) */ -#define ADC_CSR_AWD1_MST (1 << 7) /* Bit 7: Analog watchdog 1 flag (master ADC) */ -#define ADC_CSR_AWD2_MST (1 << 8) /* Bit 8: Analog watchdog 2 flag (master ADC) */ -#define ADC_CSR_AWD3_MST (1 << 9) /* Bit 9: Analog watchdog 3 flag (master ADC) */ -#define ADC_CSR_JQOVF_MST (1 << 10) /* Bit 10: Injected Context Queue Overflow flag (master ADC) */ -#define ADC_CSR_ADRDY_SLV (1 << 16) /* Bit 16: Slave ADC ready */ -#define ADC_CSR_EOSMP_SLV (1 << 17) /* Bit 17: End of Sampling phase flag (slave ADC) */ -#define ADC_CSR_EOC_SLV (1 << 18) /* Bit 18: End of regular conversion (slave ADC) */ -#define ADC_CSR_EOS_SLV (1 << 19) /* Bit 19: End of regular sequence flag (slave ADC) */ -#define ADC_CSR_OVR_SLV (1 << 20) /* Bit 20: Overrun flag (slave ADC) */ -#define ADC_CSR_JEOC_SLV (1 << 21) /* Bit 21: End of injected conversion flag (slave ADC) */ -#define ADC_CSR_JEOS_SLV (1 << 22) /* Bit 22: End of injected sequence flag (slave ADC) */ -#define ADC_CSR_AWD1_SLV (1 << 23) /* Bit 23: Analog watchdog 1 flag (slave ADC) */ -#define ADC_CSR_AWD2_SLV (1 << 24) /* Bit 24: Analog watchdog 2 flag (slave ADC) */ -#define ADC_CSR_AWD3_SLV (1 << 25) /* Bit 25: Analog watchdog 3 flag (slave ADC) */ -#define ADC_CSR_JQOVF_SLV (1 << 26) /* Bit 26: Injected Context Queue Overflow flag (slave ADC) */ +#define ADC_CSR_ADRDY_MST (1 << 0) /* Bit 0: Master ADC ready */ +#define ADC_CSR_EOSMP_MST (1 << 1) /* Bit 1: End of Sampling phase flag (master ADC) */ +#define ADC_CSR_EOC_MST (1 << 2) /* Bit 2: End of regular conversion (master ADC) */ +#define ADC_CSR_EOS_MST (1 << 3) /* Bit 3: End of regular sequence flag (master ADC) */ +#define ADC_CSR_OVR_MST (1 << 4) /* Bit 4: Overrun flag (master ADC) */ +#define ADC_CSR_JEOC_MST (1 << 5) /* Bit 5: End of injected conversion flag (master ADC) */ +#define ADC_CSR_JEOS_MST (1 << 6) /* Bit 6: End of injected sequence flag (master ADC) */ +#define ADC_CSR_AWD1_MST (1 << 7) /* Bit 7: Analog watchdog 1 flag (master ADC) */ +#define ADC_CSR_AWD2_MST (1 << 8) /* Bit 8: Analog watchdog 2 flag (master ADC) */ +#define ADC_CSR_AWD3_MST (1 << 9) /* Bit 9: Analog watchdog 3 flag (master ADC) */ +#define ADC_CSR_JQOVF_MST (1 << 10) /* Bit 10: Injected Context Queue Overflow flag (master ADC) */ +#define ADC_CSR_ADRDY_SLV (1 << 16) /* Bit 16: Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV (1 << 17) /* Bit 17: End of Sampling phase flag (slave ADC) */ +#define ADC_CSR_EOC_SLV (1 << 18) /* Bit 18: End of regular conversion (slave ADC) */ +#define ADC_CSR_EOS_SLV (1 << 19) /* Bit 19: End of regular sequence flag (slave ADC) */ +#define ADC_CSR_OVR_SLV (1 << 20) /* Bit 20: Overrun flag (slave ADC) */ +#define ADC_CSR_JEOC_SLV (1 << 21) /* Bit 21: End of injected conversion flag (slave ADC) */ +#define ADC_CSR_JEOS_SLV (1 << 22) /* Bit 22: End of injected sequence flag (slave ADC) */ +#define ADC_CSR_AWD1_SLV (1 << 23) /* Bit 23: Analog watchdog 1 flag (slave ADC) */ +#define ADC_CSR_AWD2_SLV (1 << 24) /* Bit 24: Analog watchdog 2 flag (slave ADC) */ +#define ADC_CSR_AWD3_SLV (1 << 25) /* Bit 25: Analog watchdog 3 flag (slave ADC) */ +#define ADC_CSR_JQOVF_SLV (1 << 26) /* Bit 26: Injected Context Queue Overflow flag (slave ADC) */ /* Common control register */ @@ -724,10 +855,10 @@ /* Common regular data register for dual mode */ -#define ADC_CDR_RDATA_MST_SHIFT (0) /* Bits 0-15: Regular data of the master ADC */ -#define ADC_CDR_RDATA_MST_MASK (0xffff << ADC_CDR_RDATA_MST_SHIFT) -#define ADC_CDR_RDATA_SLV_SHIFT (16) /* Bits 16-31: Regular data of the slave ADC */ -#define ADC_CDR_RDATA_SLV_MASK (0xffff << ADC_CDR_RDATA_SLV_SHIFT) +#define ADC_CDR_RDATA_MST_SHIFT (0) /* Bits 0-15: Regular data of the master ADC */ +#define ADC_CDR_RDATA_MST_MASK (0xffff << ADC_CDR_RDATA_MST_SHIFT) +#define ADC_CDR_RDATA_SLV_SHIFT (16) /* Bits 16-31: Regular data of the slave ADC */ +#define ADC_CDR_RDATA_SLV_MASK (0xffff << ADC_CDR_RDATA_SLV_SHIFT) /**************************************************************************************************** * Public Types diff --git a/arch/arm/src/stm32/hardware/stm32_dma.h b/arch/arm/src/stm32/hardware/stm32_dma.h index a823068e603..0994af54db5 100644 --- a/arch/arm/src/stm32/hardware/stm32_dma.h +++ b/arch/arm/src/stm32/hardware/stm32_dma.h @@ -45,7 +45,7 @@ #include "chip.h" /* Include the correct DMA register definitions for selected STM32 DMA IP core: - * - STM32 DMA IP version 1 - F0, F1, F3, L0, L1, L4 + * - STM32 DMA IP version 1 - F0, F1, F3, G4, L0, L1, L4 * - STM32 DMA IP version 2 - F2, F4, F7, H7 */ diff --git a/arch/arm/src/stm32/hardware/stm32_dma_v1.h b/arch/arm/src/stm32/hardware/stm32_dma_v1.h index 0065b5d8a91..50759edd15e 100644 --- a/arch/arm/src/stm32/hardware/stm32_dma_v1.h +++ b/arch/arm/src/stm32/hardware/stm32_dma_v1.h @@ -40,7 +40,7 @@ * Pre-processor Definitions ************************************************************************************/ -/* This is implementation for STM32 DMA IP version 1 - F0, F1, F3, L0, L1, L4 */ +/* This is implementation for STM32 DMA IP version 1 - F0, F1, F3, G4, L0, L1, L4 */ #define HAVE_IP_DMA_V1 1 #undef HAVE_IP_DMA_V2 @@ -54,8 +54,13 @@ #define DMA1 (0) #define DMA2 (1) -/* These definitions apply to both the STM32 F1 and F3 families - * 12 Channels Total: 7 DMA1 Channels(1-7) and 5 DMA2 channels (1-5) +/* These definitions apply to multiple STM32 families. + * + * The STM32 F1 and F3 families have 12 channels total: + * 7 DMA1 channels(1-7) and 5 DMA2 channels (1-5). + * + * The STM32 G4 family has 16 channels total: + * 8 DMA1 channels(1-8) and 8 DMA2 channels (1-8). */ #define DMA_CHAN1 (0) @@ -65,6 +70,7 @@ #define DMA_CHAN5 (4) #define DMA_CHAN6 (5) #define DMA_CHAN7 (6) +#define DMA_CHAN8 (7) /* Register Offsets *****************************************************************/ @@ -79,6 +85,7 @@ #define STM32_DMACHAN5_OFFSET 0x0050 #define STM32_DMACHAN6_OFFSET 0x0064 #define STM32_DMACHAN7_OFFSET 0x0078 +#define STM32_DMACHAN8_OFFSET 0x008c #define STM32_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */ #define STM32_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */ @@ -97,6 +104,7 @@ #define STM32_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */ #define STM32_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */ #define STM32_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */ +#define STM32_DMA_CCR8_OFFSET 0x0094 /* DMA channel 8 configuration register */ #define STM32_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */ #define STM32_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */ @@ -105,6 +113,7 @@ #define STM32_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */ #define STM32_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */ #define STM32_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */ +#define STM32_DMA_CNDTR8_OFFSET 0x0098 /* DMA channel 8 number of data register */ #define STM32_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */ #define STM32_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */ @@ -113,6 +122,7 @@ #define STM32_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */ #define STM32_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */ #define STM32_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */ +#define STM32_DMA_CPAR8_OFFSET 0x009c /* DMA channel 8 peripheral address register */ #define STM32_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */ #define STM32_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */ @@ -121,6 +131,7 @@ #define STM32_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */ #define STM32_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */ #define STM32_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */ +#define STM32_DMA_CMAR8_OFFSET 0x00a0 /* DMA channel 8 memory address register */ #ifdef DMA_HAVE_CSELR # define STM32_DMA_CSELR_OFFSET 0x00a8 /* DMA channel selection register */ @@ -139,6 +150,9 @@ #define STM32_DMA1_CCR5 (STM32_DMA1_BASE+STM32_DMA_CCR5_OFFSET) #define STM32_DMA1_CCR6 (STM32_DMA1_BASE+STM32_DMA_CCR6_OFFSET) #define STM32_DMA1_CCR7 (STM32_DMA1_BASE+STM32_DMA_CCR7_OFFSET) +#if defined(CONFIG_STM32_HAVE_DMA1_CHAN8) +# define STM32_DMA1_CCR8 (STM32_DMA1_BASE+STM32_DMA_CCR8_OFFSET) +#endif #define STM32_DMA1_CNDTR(n) (STM32_DMA1_BASE+STM32_DMA_CNDTR_OFFSET(n)) #define STM32_DMA1_CNDTR1 (STM32_DMA1_BASE+STM32_DMA_CNDTR1_OFFSET) @@ -148,6 +162,9 @@ #define STM32_DMA1_CNDTR5 (STM32_DMA1_BASE+STM32_DMA_CNDTR5_OFFSET) #define STM32_DMA1_CNDTR6 (STM32_DMA1_BASE+STM32_DMA_CNDTR6_OFFSET) #define STM32_DMA1_CNDTR7 (STM32_DMA1_BASE+STM32_DMA_CNDTR7_OFFSET) +#if defined(CONFIG_STM32_HAVE_DMA1_CHAN8) +# define STM32_DMA1_CNDTR8 (STM32_DMA1_BASE+STM32_DMA_CNDTR8_OFFSET) +#endif #define STM32_DMA1_CPAR(n) (STM32_DMA1_BASE+STM32_DMA_CPAR_OFFSET(n)) #define STM32_DMA1_CPAR1 (STM32_DMA1_BASE+STM32_DMA_CPAR1_OFFSET) @@ -157,6 +174,9 @@ #define STM32_DMA1_CPAR5 (STM32_DMA1_BASE+STM32_DMA_CPAR5_OFFSET) #define STM32_DMA1_CPAR6 (STM32_DMA1_BASE+STM32_DMA_CPAR6_OFFSET) #define STM32_DMA1_CPAR7 (STM32_DMA1_BASE+STM32_DMA_CPAR7_OFFSET) +#if defined(CONFIG_STM32_HAVE_DMA1_CHAN8) +# define STM32_DMA1_CPAR8 (STM32_DMA1_BASE+STM32_DMA_CPAR8_OFFSET) +#endif #define STM32_DMA1_CMAR(n) (STM32_DMA1_BASE+STM32_DMA_CMAR_OFFSET(n)) #define STM32_DMA1_CMAR1 (STM32_DMA1_BASE+STM32_DMA_CMAR1_OFFSET) @@ -166,6 +186,9 @@ #define STM32_DMA1_CMAR5 (STM32_DMA1_BASE+STM32_DMA_CMAR5_OFFSET) #define STM32_DMA1_CMAR6 (STM32_DMA1_BASE+STM32_DMA_CMAR6_OFFSET) #define STM32_DMA1_CMAR7 (STM32_DMA1_BASE+STM32_DMA_CMAR7_OFFSET) +#if defined(CONFIG_STM32_HAVE_DMA1_CHAN8) +# define STM32_DMA1_CMAR8 (STM32_DMA1_BASE+STM32_DMA_CMAR8_OFFSET) +#endif #define STM32_DMA2_ISRC (STM32_DMA2_BASE+STM32_DMA_ISR_OFFSET) #define STM32_DMA2_IFCR (STM32_DMA2_BASE+STM32_DMA_IFCR_OFFSET) @@ -176,6 +199,11 @@ #define STM32_DMA2_CCR3 (STM32_DMA2_BASE+STM32_DMA_CCR3_OFFSET) #define STM32_DMA2_CCR4 (STM32_DMA2_BASE+STM32_DMA_CCR4_OFFSET) #define STM32_DMA2_CCR5 (STM32_DMA2_BASE+STM32_DMA_CCR5_OFFSET) +#if defined(CONFIG_STM32_HAVE_DMA2_CHAN678) +# define STM32_DMA2_CCR6 (STM32_DMA2_BASE+STM32_DMA_CCR6_OFFSET) +# define STM32_DMA2_CCR7 (STM32_DMA2_BASE+STM32_DMA_CCR7_OFFSET) +# define STM32_DMA2_CCR8 (STM32_DMA2_BASE+STM32_DMA_CCR8_OFFSET) +#endif #define STM32_DMA2_CNDTR(n) (STM32_DMA2_BASE+STM32_DMA_CNDTR_OFFSET(n)) #define STM32_DMA2_CNDTR1 (STM32_DMA2_BASE+STM32_DMA_CNDTR1_OFFSET) @@ -183,6 +211,11 @@ #define STM32_DMA2_CNDTR3 (STM32_DMA2_BASE+STM32_DMA_CNDTR3_OFFSET) #define STM32_DMA2_CNDTR4 (STM32_DMA2_BASE+STM32_DMA_CNDTR4_OFFSET) #define STM32_DMA2_CNDTR5 (STM32_DMA2_BASE+STM32_DMA_CNDTR5_OFFSET) +#if defined(CONFIG_STM32_HAVE_DMA2_CHAN678) +# define STM32_DMA2_CNDTR6 (STM32_DMA2_BASE+STM32_DMA_CNDTR6_OFFSET) +# define STM32_DMA2_CNDTR7 (STM32_DMA2_BASE+STM32_DMA_CNDTR7_OFFSET) +# define STM32_DMA2_CNDTR8 (STM32_DMA2_BASE+STM32_DMA_CNDTR8_OFFSET) +#endif #define STM32_DMA2_CPAR(n) (STM32_DMA2_BASE+STM32_DMA_CPAR_OFFSET(n)) #define STM32_DMA2_CPAR1 (STM32_DMA2_BASE+STM32_DMA_CPAR1_OFFSET) @@ -190,6 +223,11 @@ #define STM32_DMA2_CPAR3 (STM32_DMA2_BASE+STM32_DMA_CPAR3_OFFSET) #define STM32_DMA2_CPAR4 (STM32_DMA2_BASE+STM32_DMA_CPAR4_OFFSET) #define STM32_DMA2_CPAR5 (STM32_DMA2_BASE+STM32_DMA_CPAR5_OFFSET) +#if defined(CONFIG_STM32_HAVE_DMA2_CHAN678) +# define STM32_DMA2_CPAR6 (STM32_DMA2_BASE+STM32_DMA_CPAR6_OFFSET) +# define STM32_DMA2_CPAR7 (STM32_DMA2_BASE+STM32_DMA_CPAR7_OFFSET) +# define STM32_DMA2_CPAR8 (STM32_DMA2_BASE+STM32_DMA_CPAR8_OFFSET) +#endif #define STM32_DMA2_CMAR(n) (STM32_DMA2_BASE+STM32_DMA_CMAR_OFFSET(n)) #define STM32_DMA2_CMAR1 (STM32_DMA2_BASE+STM32_DMA_CMAR1_OFFSET) @@ -197,6 +235,11 @@ #define STM32_DMA2_CMAR3 (STM32_DMA2_BASE+STM32_DMA_CMAR3_OFFSET) #define STM32_DMA2_CMAR4 (STM32_DMA2_BASE+STM32_DMA_CMAR4_OFFSET) #define STM32_DMA2_CMAR5 (STM32_DMA2_BASE+STM32_DMA_CMAR5_OFFSET) +#if defined(CONFIG_STM32_HAVE_DMA2_CHAN678) +# define STM32_DMA2_CMAR6 (STM32_DMA2_BASE+STM32_DMA_CMAR6_OFFSET) +# define STM32_DMA2_CMAR7 (STM32_DMA2_BASE+STM32_DMA_CMAR7_OFFSET) +# define STM32_DMA2_CMAR8 (STM32_DMA2_BASE+STM32_DMA_CMAR8_OFFSET) +#endif /* Register Bitfield Definitions ****************************************************/ @@ -225,6 +268,8 @@ #define DMA_ISR_CHAN6_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN6_SHIFT) #define DMA_ISR_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt status */ #define DMA_ISR_CHAN7_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN7_SHIFT) +#define DMA_ISR_CHAN8_SHIFT (28) /* Bits 31-28: DMA Channel 8 interrupt status */ +#define DMA_ISR_CHAN8_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN8_SHIFT) #define DMA_ISR_GIF(n) (DMA_CHAN_GIF_BIT << DMA_ISR_CHAN_SHIFT(n)) #define DMA_ISR_TCIF(n) (DMA_CHAN_TCIF_BIT << DMA_ISR_CHAN_SHIFT(n)) @@ -249,7 +294,14 @@ #define DMA_IFCR_CHAN6_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN6_SHIFT) #define DMA_IFCR_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt flag clear */ #define DMA_IFCR_CHAN7_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN7_SHIFT) -#define DMA_IFCR_ALLCHANNELS (0x0fffffff) +#define DMA_IFCR_CHAN8_SHIFT (28) /* Bits 31-28: DMA Channel 8 interrupt flag clear */ +#define DMA_IFCR_CHAN8_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN8_SHIFT) + +#if defined(CONFIG_STM32_HAVE_DMA1_CHAN8) || defined(CONFIG_STM32_HAVE_DMA2_CHAN678) +# define DMA_IFCR_ALLCHANNELS (0xffffffff) +#else +# define DMA_IFCR_ALLCHANNELS (0x0fffffff) +#endif #define DMA_IFCR_CGIF(n) (DMA_CHAN_GIF_BIT << DMA_IFCR_CHAN_SHIFT(n)) #define DMA_IFCR_CTCIF(n) (DMA_CHAN_TCIF_BIT << DMA_IFCR_CHAN_SHIFT(n)) @@ -308,12 +360,30 @@ #define STM32_DMA1_CHAN5 (4) #define STM32_DMA1_CHAN6 (5) #define STM32_DMA1_CHAN7 (6) - -#define STM32_DMA2_CHAN1 (7) -#define STM32_DMA2_CHAN2 (8) -#define STM32_DMA2_CHAN3 (9) -#define STM32_DMA2_CHAN4 (10) -#define STM32_DMA2_CHAN5 (11) +#if defined(CONFIG_STM32_HAVE_DMA1_CHAN8) +# define STM32_DMA1_CHAN8 (7) +# define STM32_DMA2_CHAN1 (8) +# define STM32_DMA2_CHAN2 (9) +# define STM32_DMA2_CHAN3 (10) +# define STM32_DMA2_CHAN4 (11) +# define STM32_DMA2_CHAN5 (12) +# if defined(CONFIG_STM32_HAVE_DMA2_CHAN678) +# define STM32_DMA2_CHAN6 (13) +# define STM32_DMA2_CHAN7 (14) +# define STM32_DMA2_CHAN8 (15) +# endif +#else +# define STM32_DMA2_CHAN1 (7) +# define STM32_DMA2_CHAN2 (8) +# define STM32_DMA2_CHAN3 (9) +# define STM32_DMA2_CHAN4 (10) +# define STM32_DMA2_CHAN5 (11) +# if defined(CONFIG_STM32_HAVE_DMA2_CHAN678) +# define STM32_DMA2_CHAN6 (12) +# define STM32_DMA2_CHAN7 (13) +# define STM32_DMA2_CHAN8 (14) +# endif +#endif #ifdef DMA_HAVE_CSELR # define DMACHAN_SETTING(chan, sel) ((((sel) & 0xff) << 8) | ((chan) & 0xff)) @@ -700,6 +770,12 @@ # define DMACHAN_TIM18_UP_2 STM32_DMA2_CHAN5 # define DMACHAN_DAC2_CH1_2 STM32_DMA2_CHAN5 +#elif defined(CONFIG_STM32_STM32G47XX) + + /* This family uses a DMAMUX. The code to support this needs to be ported + * to this family from STM32L4R. + */ + #else # error "Unknown DMA channel assignments" #endif diff --git a/arch/arm/src/stm32/hardware/stm32_flash.h b/arch/arm/src/stm32/hardware/stm32_flash.h index 1248aabbb8a..bd2371557f0 100644 --- a/arch/arm/src/stm32/hardware/stm32_flash.h +++ b/arch/arm/src/stm32/hardware/stm32_flash.h @@ -125,6 +125,11 @@ /* STM32F4 has mixed page size */ # undef STM32_FLASH_PAGESIZE + +# elif defined(CONFIG_STM32_STM32G47XX) +# define STM32_FLASH_NPAGES 32 +# define STM32_FLASH_PAGESIZE 4096 + # endif #endif /* CONFIG_STM32_FLASH_CONFIG_DEFAULT */ @@ -186,6 +191,22 @@ _K(128), _K(128), _K(128), _K(128)} # endif +/* Define the Valid Configuration the G4 */ + +# elif defined(CONFIG_STM32_STM32G47XX) +# if defined(CONFIG_STM32_FLASH_CONFIG_B) +# define STM32_FLASH_NPAGES 32 +# define STM32_FLASH_PAGESIZE 4096 + +# elif defined(CONFIG_STM32_FLASH_CONFIG_C) +# define STM32_FLASH_NPAGES 64 +# define STM32_FLASH_PAGESIZE 4096 + +# elif defined(CONFIG_STM32_FLASH_CONFIG_E) +# define STM32_FLASH_NPAGES 128 +# define STM32_FLASH_PAGESIZE 4096 +# endif + /* Define the Valid Configuration the F1 and F3 */ # else @@ -253,6 +274,24 @@ # define STM32_FLASH_WRPR2_OFFSET 0x0080 # define STM32_FLASH_WRPR3_OFFSET 0x0084 # define STM32_FLASH_WRPR4_OFFSET 0x0088 +#elif defined(CONFIG_STM32_STM32G47XX) +# define STM32_FLASH_PDKEYR_OFFSET 0x0004 +# define STM32_FLASH_KEYR_OFFSET 0x0008 +# define STM32_FLASH_OPT_KEYR_OFFSET 0x000c +# define STM32_FLASH_SR_OFFSET 0x0010 +# define STM32_FLASH_CR_OFFSET 0x0014 +# define STM32_FLASH_ECCR_OFFSET 0x0018 +# define STM32_FLASH_OPTR_OFFSET 0x0020 +# define STM32_FLASH_PCROP1SR_OFFSET 0x0024 +# define STM32_FLASH_PCROP1ER_OFFSET 0x0028 +# define STM32_FLASH_WRP1AR_OFFSET 0x002c +# define STM32_FLASH_WRP1BR_OFFSET 0x0030 +# define STM32_FLASH_PCROP2SR_OFFSET 0x0044 +# define STM32_FLASH_PCROP2ER_OFFSET 0x0048 +# define STM32_FLASH_WRP2AR_OFFSET 0x004c +# define STM32_FLASH_WRP2BR_OFFSET 0x0050 +# define STM32_FLASH_SEC1R_OFFSET 0x0070 +# define STM32_FLASH_SEC2R_OFFSET 0x0074 #else # define STM32_FLASH_KEYR_OFFSET 0x0004 # define STM32_FLASH_OPTKEYR_OFFSET 0x0008 @@ -298,6 +337,24 @@ # define STM32_FLASH_WRPR2 (STM32_FLASHIF_BASE+STM32_FLASH_WRPR2_OFFSET) # define STM32_FLASH_WRPR3 (STM32_FLASHIF_BASE+STM32_FLASH_WRPR3_OFFSET) # define STM32_FLASH_WRPR4 (STM32_FLASHIF_BASE+STM32_FLASH_WRPR4_OFFSET) +#elif defined(CONFIG_STM32_STM32G47XX) +# define STM32_FLASH_PDKEYR (STM32_FLASHIF_BASE+STM32_FLASH_PDKEYR_OFFSET) +# define STM32_FLASH_KEYR (STM32_FLASHIF_BASE+STM32_FLASH_KEYR_OFFSET) +# define STM32_FLASH_OPT_KEYR (STM32_FLASHIF_BASE+STM32_FLASH_OPT_KEYR_OFFSET) +# define STM32_FLASH_SR (STM32_FLASHIF_BASE+STM32_FLASH_SR_OFFSET) +# define STM32_FLASH_CR (STM32_FLASHIF_BASE+STM32_FLASH_CR_OFFSET) +# define STM32_FLASH_ECCR (STM32_FLASHIF_BASE+STM32_FLASH_ECCR_OFFSET) +# define STM32_FLASH_OPTR (STM32_FLASHIF_BASE+STM32_FLASH_OPTR_OFFSET) +# define STM32_FLASH_PCROP1SR (STM32_FLASHIF_BASE+STM32_FLASH_PCROP1SR_OFFSET) +# define STM32_FLASH_PCROP1ER (STM32_FLASHIF_BASE+STM32_FLASH_PCROP1ER_OFFSET) +# define STM32_FLASH_WRP1AR (STM32_FLASHIF_BASE+STM32_FLASH_WRP1AR_OFFSET) +# define STM32_FLASH_WRP1BR (STM32_FLASHIF_BASE+STM32_FLASH_WRP1BR_OFFSET) +# define STM32_FLASH_PCROP2SR (STM32_FLASHIF_BASE+STM32_FLASH_PCROP2SR_OFFSET) +# define STM32_FLASH_PCROP2ER (STM32_FLASHIF_BASE+STM32_FLASH_PCROP2ER_OFFSET) +# define STM32_FLASH_WRP2AR (STM32_FLASHIF_BASE+STM32_FLASH_WRP2AR_OFFSET) +# define STM32_FLASH_WRP2BR (STM32_FLASHIF_BASE+STM32_FLASH_WRP2BR_OFFSET) +# define STM32_FLASH_SEC1R (STM32_FLASHIF_BASE+STM32_FLASH_SEC1R_OFFSET) +# define STM32_FLASH_SEC2R (STM32_FLASHIF_BASE+STM32_FLASH_SEC2R_OFFSET) #else # define STM32_FLASH_KEYR (STM32_FLASHIF_BASE+STM32_FLASH_KEYR_OFFSET) # define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE+STM32_FLASH_OPTKEYR_OFFSET) @@ -335,6 +392,34 @@ # define FLASH_ACR_ACC64 (1 << 2) /* Bit 2: 64-bit access */ # define FLASH_ACR_SLEEP_PD (1 << 3) /* Bit 3: Flash mode during Sleep */ # define FLASH_ACR_RUN_PD (1 << 4) /* Bit 4: Flash mode during Run */ +#elif defined(CONFIG_STM32_STM32G47XX) +# define FLASH_ACR_LATENCY_SHIFT (0) +# define FLASH_ACR_LATENCY_MASK (0xf << FLASH_ACR_LATENCY_SHIFT) +# define FLASH_ACR_LATENCY(n) ((n) << FLASH_ACR_LATENCY_SHIFT) /* n wait states = 0..15 */ +# define FLASH_ACR_LATENCY_0 (0 << FLASH_ACR_LATENCY_SHIFT) /* 0000: Zero wait states */ +# define FLASH_ACR_LATENCY_1 (1 << FLASH_ACR_LATENCY_SHIFT) /* 0001: One wait state */ +# define FLASH_ACR_LATENCY_2 (2 << FLASH_ACR_LATENCY_SHIFT) /* 0010: Two wait states */ +# define FLASH_ACR_LATENCY_3 (3 << FLASH_ACR_LATENCY_SHIFT) /* 0011: Three wait states */ +# define FLASH_ACR_LATENCY_4 (4 << FLASH_ACR_LATENCY_SHIFT) /* 0100: Four wait states */ +# define FLASH_ACR_LATENCY_5 (5 << FLASH_ACR_LATENCY_SHIFT) /* 0101: Five wait states */ +# define FLASH_ACR_LATENCY_6 (6 << FLASH_ACR_LATENCY_SHIFT) /* 0110: Six wait states */ +# define FLASH_ACR_LATENCY_7 (7 << FLASH_ACR_LATENCY_SHIFT) /* 0111: Seven wait states */ +# define FLASH_ACR_LATENCY_8 (8 << FLASH_ACR_LATENCY_SHIFT) /* 1000: Eight wait states */ +# define FLASH_ACR_LATENCY_9 (9 << FLASH_ACR_LATENCY_SHIFT) /* 1001: Nine wait state */ +# define FLASH_ACR_LATENCY_10 (10 << FLASH_ACR_LATENCY_SHIFT) /* 1010: Ten wait states */ +# define FLASH_ACR_LATENCY_11 (11 << FLASH_ACR_LATENCY_SHIFT) /* 1011: Eleven wait states */ +# define FLASH_ACR_LATENCY_12 (12 << FLASH_ACR_LATENCY_SHIFT) /* 1100: Twelve wait states */ +# define FLASH_ACR_LATENCY_13 (13 << FLASH_ACR_LATENCY_SHIFT) /* 1101: Thirteen wait states */ +# define FLASH_ACR_LATENCY_14 (14 << FLASH_ACR_LATENCY_SHIFT) /* 1110: Fourteen wait states */ +# define FLASH_ACR_LATENCY_15 (15 << FLASH_ACR_LATENCY_SHIFT) /* 1111: Fifteen wait states */ +# define FLASH_ACR_PRFTEN (1 << 8) /* Bit 8: FLASH prefetch enable */ +# define FLASH_ACR_ICEN (1 << 9) /* Bit 9: Instruction cache enable */ +# define FLASH_ACR_DCEN (1 << 10) /* Bit 10: Data cache enable */ +# define FLASH_ACR_ICRST (1 << 11) /* Bit 11: Instruction cache reset */ +# define FLASH_ACR_DCRST (1 << 12) /* Bit 12: Data cache reset */ +# define FLASH_ACR_RUNPD (1 << 13) /* Bit 13: Flash Power Down Mode During Run or Low Power Run */ +# define FLASH_ACR_SLEEPPD (1 << 14) /* Bit 14: Flash Power Down Mode During Sleep or Low Power Sleep */ +# define FLASH_ACR_DBG_SWEN (1 << 18) /* Bit 18: Debug Software Enable */ #else # define FLASH_ACR_LATENCY_SHIFT (0) # define FLASH_ACR_LATENCY_MASK (7 << FLASH_ACR_LATENCY_SHIFT) @@ -392,6 +477,19 @@ # define FLASH_SR_OPTVERR (1 << 11) /* Bit 11: Option validity error */ # define FLASH_SR_OPTVERRUSR (1 << 12) /* Bit 12: Option UserValidity Error */ # define FLASH_SR_RDERR (1 << 13) /* Bit 13: Read protected error */ +#elif defined(CONFIG_STM32_STM32G47XX) +# define FLASH_SR_EOP (1 << 0) /* Bit 0: End of operation */ +# define FLASH_SR_OPERR (1 << 1) /* Bit 1: Operation error */ +# define FLASH_SR_PROGERR (1 << 3) /* Bit 3: Programming error */ +# define FLASH_SR_WRPERR (1 << 4) /* Bit 4: Write protection error */ +# define FLASH_SR_PGAERR (1 << 5) /* Bit 5: Programming alignment error */ +# define FLASH_SR_SIZERR (1 << 6) /* Bit 6: Size error */ +# define FLASH_SR_PGSERR (1 << 7) /* Bit 7: Programming sequence error */ +# define FLASH_SR_MISERR (1 << 8) /* Bit 8: Fast programming data miss error */ +# define FLASH_SR_FASTERR (1 << 9) /* Bit 9: Fast programming error */ +# define FLASH_SR_RDERR (1 << 14) /* Bit 14: PCROP read error */ +# define FLASH_SR_OPTVERR (1 << 15) /* Bit 15: Option validity error */ +# define FLASH_SR_BSY (1 << 16) /* Bit 16: Busy */ #endif /* Program/Erase Control Register (PECR) */ @@ -434,13 +532,13 @@ # define FLASH_CR_SER (1 << 1) /* Bit 1: Sector Erase */ # define FLASH_CR_MER (1 << 2) /* Bit 2: Mass Erase sectors 0..11 */ # define FLASH_CR_SNB_SHIFT (3) /* Bits 3-6: Sector number */ -#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) +# if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) # define FLASH_CR_SNB_MASK (31 << FLASH_CR_SNB_SHIFT) # define FLASH_CR_SNB(n) (((n % 12) << FLASH_CR_SNB_SHIFT) | ((n / 12) << 7)) /* Sector n, n=0..23 */ -#else +# else # define FLASH_CR_SNB_MASK (15 << FLASH_CR_SNB_SHIFT) # define FLASH_CR_SNB(n) ((n) << FLASH_CR_SNB_SHIFT) /* Sector n, n=0..11 */ -#endif +# endif # define FLASH_CR_PSIZE_SHIFT (8) /* Bits 8-9: Program size */ # define FLASH_CR_PSIZE_MASK (3 << FLASH_CR_PSIZE_SHIFT) # define FLASH_CR_PSIZE_X8 (0 << FLASH_CR_PSIZE_SHIFT) /* 00 program x8 */ @@ -451,11 +549,47 @@ # define FLASH_CR_EOPIE (1 << 24) /* Bit 24: End of operation interrupt enable */ # define FLASH_CR_ERRIE (1 << 25) /* Bit 25: Error interrupt enable */ # define FLASH_CR_LOCK (1 << 31) /* Bit 31: Lock */ +#elif defined(CONFIG_STM32_STM32G47XX) +# define FLASH_CR_PG (1 << 0) +# define FLASH_CR_PER (1 << 1) +# define FLASH_CR_MER1 (1 << 2) +# define FLASH_CR_PNB_SHIFT (3) +# define FLASH_CR_PNB_MASK (0x7f << FLASH_CR_PNB_SHIFT) +# define FLASH_CR_PNB(n) (((n) << FLASH_CR_PNB_SHIFT) & FLASH_CR_PNB_MASK) +# define FLASH_CR_BKER (1 << 11) +# define FLASH_CR_MER2 (1 << 15) +# define FLASH_CR_START (1 << 16) +# define FLASH_CR_OPTSTRT (1 << 17) +# define FLASH_CR_FSTPG (1 << 18) +# define FLASH_CR_EOPIE (1 << 24) +# define FLASH_CR_ERRIE (1 << 25) +# define FLASH_CR_RDERRIE (1 << 26) +# define FLASH_CR_OBL_LAUNCH (1 << 27) +# define FLASH_CR_SEC_PROT1 (1 << 28) +# define FLASH_CR_SEC_PROT2 (1 << 29) +# define FLASH_CR_OPTLOCK (1 << 30) +# define FLASH_CR_LOCK (1 << 31) #endif #if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) # define FLASH_CR_MER1 (1 << 15) /* Bit 15: Mass Erase sectors 12..23 */ #endif +/* Flash ECC register (ECCR) */ + +#if defined(CONFIG_STM32_STM32G47XX) +# define FLASH_ECCR_ADDR_ECC_SHIFT (0) +# define FLASH_ECCR_ADDR_ECC_MASK (0x7ffff << FLASH_ECCR_ADDR_ECC_SHIFT) +# define FLASH_ECCR_ADDR_ECC(n) (((n) << FLASH_ECCR_ADDR_ECC_SHIFT) & FLASH_ECCR_ADDR_ECC_MASK) + +# define FLASH_ECCR_BK_ECC (1 << 21) +# define FLASH_ECCR_SYSF_ECC (1 << 22) +# define FLASH_ECCR_ECCIE (1 << 24) +# define FLASH_ECCR_ECCC2 (1 << 28) +# define FLASH_ECCR_ECCD2 (1 << 29) +# define FLASH_ECCR_ECCC (1 << 30) +# define FLASH_ECCR_ECCD (1 << 31) +#endif + /* Flash Option Control Register (OPTCR) */ #if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) @@ -481,16 +615,145 @@ /* Flash Option Control Register (OPTCR1) */ #if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) -# define FLASH_OPTCR1_NWRP_SHIFT (16) /* Bits 16-27: Not write protect (high bank) */ -# define FLASH_OPTCR1_NWRP_MASK (0xfff << FLASH_OPTCR_NWRP_SHIFT) +# define FLASH_OPTCR1_NWRP_SHIFT (16) /* Bits 16-27: Not write protect (high bank) */ +# define FLASH_OPTCR1_NWRP_MASK (0xfff << FLASH_OPTCR_NWRP_SHIFT) -# define FLASH_OPTCR1_BFB2_SHIFT (4) /* Bits 4: Dual-bank Boot option byte */ -# define FLASH_OPTCR1_BFB2_MASK (1 << FLASH_OPTCR_NWRP_SHIFT) +# define FLASH_OPTCR1_BFB2_SHIFT (4) /* Bits 4: Dual-bank Boot option byte */ +# define FLASH_OPTCR1_BFB2_MASK (1 << FLASH_OPTCR_NWRP_SHIFT) #endif #if defined(CONFIG_STM32_STM32F446) -# define FLASH_OPTCR1_NWRP_SHIFT (16) /* Bits 16-23: Not write protect (high bank) */ -# define FLASH_OPTCR1_NWRP_MASK (0xff << FLASH_OPTCR_NWRP_SHIFT) +# define FLASH_OPTCR1_NWRP_SHIFT (16) /* Bits 16-23: Not write protect (high bank) */ +# define FLASH_OPTCR1_NWRP_MASK (0xff << FLASH_OPTCR_NWRP_SHIFT) +#endif + +/* Flash option register (OPTR) */ + +#if defined(CONFIG_STM32_STM32G47XX) +# define FLASH_OPTR_RDP_SHIFT (0) +# define FLASH_OPTR_RDP_MASK (0xff << FLASH_OPTR_RDP_SHIFT) +# define FLASH_OPTR_RDP (((n) << FLASH_OPTR_RDP_SHIFT) & FLASH_OPTR_RDP_MASK) +# define FLASH_OPTR_BOR_LEV_SHIFT (8) +# define FLASH_OPTR_BOR_LEV_MASK (0x7 << FLASH_OPTR_BOR_LEV_SHIFT) +# define FLASH_OPTR_BOR_LEV_1_7V (0x0 << FLASH_OPTR_BOR_LEV_SHIFT) +# define FLASH_OPTR_BOR_LEV_2_0V (0x1 << FLASH_OPTR_BOR_LEV_SHIFT) +# define FLASH_OPTR_BOR_LEV_2_2V (0x2 << FLASH_OPTR_BOR_LEV_SHIFT) +# define FLASH_OPTR_BOR_LEV_2_5V (0x3 << FLASH_OPTR_BOR_LEV_SHIFT) +# define FLASH_OPTR_BOR_LEV_2_8V (0x4 << FLASH_OPTR_BOR_LEV_SHIFT) +# define FLASH_OPTR_NRST_STOP (1 << 12) +# define FLASH_OPTR_NRST_STDBY (1 << 13) +# define FLASH_OPTR_NRST_SHDW (1 << 14) +# define FLASH_OPTR_IWDG_SW (1 << 16) +# define FLASH_OPTR_IWDG_STOP (1 << 17) +# define FLASH_OPTR_IWDG_STDBY (1 << 18) +# define FLASH_OPTR_WWDG_SW (1 << 19) +# define FLASH_OPTR_BFB2 (1 << 20) +# define FLASH_OPTR_DBANK (1 << 22) +# define FLASH_OPTR_NBOOT1 (1 << 23) +# define FLASH_OPTR_SRAM_PE (1 << 24) +# define FLASH_OPTR_CCMSRAM_RST (1 << 25) +# define FLASH_OPTR_NSWBOOT0 (1 << 26) +# define FLASH_OPTR_NBOOT0 (1 << 27) +# define FLASH_OPTR_NRST_MODE_SHIFT (28) +# define FLASH_OPTR_NRST_MODE_MASK (0x3 << FLASH_OPTR_NRST_MODE_SHIFT) +# define FLASH_OPTR_NRST_MODE_NRST (0x1 << FLASH_OPTR_NRST_MODE_SHIFT) +# define FLASH_OPTR_NRST_MODE_GPIO (0x2 << FLASH_OPTR_NRST_MODE_SHIFT) +# define FLASH_OPTR_NRST_MODE_BIDI_NRST (0x3 << FLASH_OPTR_NRST_MODE_SHIFT) +# define FLASH_OPTR_IRHEN (1 << 30) +#endif + +/* Flash PCROP1 Start Address Register (PCROP1SR) */ + +#if defined(CONFIG_STM32_STM32G47XX) +# define FLASH_PCROP1SR_PCROP1_STRT_SHIFT (0) +# define FLASH_PCROP1SR_PCROP1_STRT_MASK (0x7fff << FLASH_PCROP1SR_PCROP1_STRT_SHIFT) +# define FLASH_PCROP1SR_PCROP1_STRT(n) (((n) << FLASH_PCROP1SR_PCROP1_STRT_SHIFT) & FLASH_PCROP1SR_PCROP1_STRT_MASK) +#endif + +/* Flash PCROP1 End Address Register (PCROP1ER) */ + +#if defined(CONFIG_STM32_STM32G47XX) +# define FLASH_PCROP1ER_PCROP1_END_SHIFT (0) +# define FLASH_PCROP1ER_PCROP1_END_MASK (0x7fff << FLASH_PCROP1ER_PCROP1_END_SHIFT) +# define FLASH_PCROP1ER_PCROP1_END(n) (((n) << FLASH_PCROP1ER_PCROP1_END_SHIFT) & FLASH_PCROP1ER_PCROP1_END_MASK) +# define FLASH_PCROP1ER_PCROP_RDP (1 << 31) +#endif + +/* Flash Bank 1 WRP Area A Address Register (WRP1AR) */ + +#if defined(CONFIG_STM32_STM32G47XX) +# define FLASH_WRP1AR_WRP1A_STRT_SHIFT (0) +# define FLASH_WRP1AR_WRP1A_STRT_MASK (0x7f << FLASH_WRP1AR_WRP1A_STRT_SHIFT) +# define FLASH_WRP1AR_WRP1A_STRT(n) (((n) << FLASH_WRP1AR_WRP1A_STRT_SHIFT) & FLASH_WRP1AR_WRP1A_STRT_MASK) +# define FLASH_WRP1AR_WRP1A_END_SHIFT (16) +# define FLASH_WRP1AR_WRP1A_END_MASK (0x7f << FLASH_WRP1AR_WRP1A_END_SHIFT) +# define FLASH_WRP1AR_WRP1A_END(n) (((n) << FLASH_WRP1AR_WRP1A_END_SHIFT) & FLASH_WRP1AR_WRP1A_END_MASK) +#endif + +/* Flash Bank 1 WRP Area B Address Register (WRPB1R) */ + +#if defined(CONFIG_STM32_STM32G47XX) +# define FLASH_WRP1BR_WRP1B_STRT_SHIFT (0) +# define FLASH_WRP1BR_WRP1B_STRT_MASK (0x7f << FLASH_WRP1BR_WRP1B_STRT_SHIFT) +# define FLASH_WRP1BR_WRP1B_STRT(n) (((n) << FLASH_WRP1BR_WRP1B_STRT_SHIFT) & FLASH_WRP1BR_WRP1B_STRT_MASK) +# define FLASH_WRP1BR_WRP1B_END_SHIFT (16) +# define FLASH_WRP1BR_WRP1B_END_MASK (0x7f << FLASH_WRP1BR_WRP1B_END_SHIFT) +# define FLASH_WRP1BR_WRP1B_END(n) (((n) << FLASH_WRP1BR_WRP1B_END_SHIFT) & FLASH_WRP1BR_WRP1B_END_MASK) +#endif + +/* Flash PCROP2 Start Address Register (PCROP2SR) */ + +#if defined(CONFIG_STM32_STM32G47XX) +# define FLASH_PCROP2SR_PCROP2_STRT_SHIFT (0) +# define FLASH_PCROP2SR_PCROP2_STRT_MASK (0x7fff << FLASH_PCROP2SR_PCROP2_STRT_SHIFT) +# define FLASH_PCROP2SR_PCROP2_STRT(n) (((n) << FLASH_PCROP2SR_PCROP2_STRT_SHIFT) & FLASH_PCROP2SR_PCROP2_STRT_MASK) +#endif + +/* Flash PCROP2 End Address Register (PCROP2ER) */ + +#if defined(CONFIG_STM32_STM32G47XX) +# define FLASH_PCROP2ER_PCROP2_END_SHIFT (0) +# define FLASH_PCROP2ER_PCROP2_END_MASK (0x7fff << FLASH_PCROP2ER_PCROP2_END_SHIFT) +# define FLASH_PCROP2ER_PCROP2_END(n) (((n) << FLASH_PCROP2ER_PCROP2_END_SHIFT) & FLASH_PCROP2ER_PCROP2_END_MASK) +#endif + +/* Flash Bank 2 WRP Area A Address Register (WRP2AR) */ + +#if defined(CONFIG_STM32_STM32G47XX) +# define FLASH_WRP2AR_WRP2A_STRT_SHIFT (0) +# define FLASH_WRP2AR_WRP2A_STRT_MASK (0x7f << FLASH_WRP2AR_WRP2A_STRT_SHIFT) +# define FLASH_WRP2AR_WRP2A_STRT(n) (((n) << FLASH_WRP2AR_WRP2A_STRT_SHIFT) & FLASH_WRP2AR_WRP2A_STRT_MASK) +# define FLASH_WRP2AR_WRP2A_END_SHIFT (16) +# define FLASH_WRP2AR_WRP2A_END_MASK (0x7f << FLASH_WRP2AR_WRP2A_END_SHIFT) +# define FLASH_WRP2AR_WRP2A_END(n) (((n) << FLASH_WRP2AR_WRP2A_END_SHIFT) & FLASH_WRP2AR_WRP2A_END_MASK) +#endif + +/* Flash Bank 2 WRP Area B Address Register (WRP2BR) */ + +#if defined(CONFIG_STM32_STM32G47XX) +# define FLASH_WRP2BR_WRP2B_STRT_SHIFT (0) +# define FLASH_WRP2BR_WRP2B_STRT_MASK (0x7f << FLASH_WRP2BR_WRP2B_STRT_SHIFT) +# define FLASH_WRP2BR_WRP2B_STRT(n) (((n) << FLASH_WRP2BR_WRP2B_STRT_SHIFT) & FLASH_WRP2BR_WRP2B_STRT_SHIFT) +# define FLASH_WRP2BR_WRP2B_END_SHIFT (16) +# define FLASH_WRP2BR_WRP2B_END_MASK (0x7f << FLASH_WRP2BR_WRP2B_END_SHIFT) +# define FLASH_WRP2BR_WRP2B_END(n) (((n) << FLASH_WRP2BR_WRP2B_END_SHIFT) & FLASH_WRP2BR_WRP2B_END_MASK) +#endif + +/* Flash Securable Area Bank 1 Register (SEC1R) */ + +#if defined(CONFIG_STM32_STM32G47XX) +# define FLASH_SEC1R_SEC_SIZE1_SHIFT (0) +# define FLASH_SEC1R_SEC_SIZE1_MASK (0xff << FLASH_SEC1R_SEC_SIZE1_SHIFT) +# define FLASH_SEC1R_SEC_SIZE1(n) (((n) << FLASH_SEC1R_SEC_SIZE1_SHIFT) & FLASH_SEC1R_SEC_SIZE1_MASK) +# define FLASH_SEC1R_BOOT_LOCK (1 << 16) +#endif + +/* Flash Securable Area Bank 2 Register (SEC2R) */ + +#if defined(CONFIG_STM32_STM32G47XX) +# define FLASH_SEC2R_SEC_SIZE2_SHIFT (0) +# define FLASH_SEC2R_SEC_SIZE2_MASK (0xff << FLASH_SEC2R_SEC_SIZE2_SHIFT) +# define FLASH_SEC2R_SEC_SIZE2(n) (((n) << FLASH_SEC2R_SEC_SIZE2_SHIFT) & FLASH_SEC2R_SEC_SIZE2_MASK) #endif /************************************************************************************ diff --git a/arch/arm/src/stm32/hardware/stm32_i2c.h b/arch/arm/src/stm32/hardware/stm32_i2c.h index d1778c5628f..899de922b52 100644 --- a/arch/arm/src/stm32/hardware/stm32_i2c.h +++ b/arch/arm/src/stm32/hardware/stm32_i2c.h @@ -42,7 +42,7 @@ /* There are 2 main types of I2C IP cores among STM32 chips: * 1. STM32 I2C IPv1 - F1, F2, F4 and L1 - * 2. STM32 I2C IPv2 - G0, L0, F0, F3, F7, H7 and L4 + * 2. STM32 I2C IPv2 - F0, F3, F7, G0, G4, H7, L0 and L4 */ #if defined(CONFIG_STM32_HAVE_IP_I2C_V1) diff --git a/arch/arm/src/stm32/hardware/stm32_i2c_v2.h b/arch/arm/src/stm32/hardware/stm32_i2c_v2.h index cc3d3aef3c0..7bf118e07de 100644 --- a/arch/arm/src/stm32/hardware/stm32_i2c_v2.h +++ b/arch/arm/src/stm32/hardware/stm32_i2c_v2.h @@ -36,8 +36,8 @@ #ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_V2_H #define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_V2_H -/* This file provide definitions for the STM32 I2C IP core 2 (G0, L0, F0, F3, F7, - * H7, and L4). +/* This file provide definitions for the STM32 I2C IP core 2 (F0, F3, F7, G0, + * G4, H7, L0 and L4). */ /************************************************************************************ diff --git a/arch/arm/src/stm32/hardware/stm32_memorymap.h b/arch/arm/src/stm32/hardware/stm32_memorymap.h index b24bb4f937b..e97b60111c2 100644 --- a/arch/arm/src/stm32/hardware/stm32_memorymap.h +++ b/arch/arm/src/stm32/hardware/stm32_memorymap.h @@ -57,6 +57,8 @@ # include "hardware/stm32f37xxx_memorymap.h" #elif defined(CONFIG_STM32_STM32F4XXX) # include "hardware/stm32f40xxx_memorymap.h" +#elif defined(CONFIG_STM32_STM32G47XX) +# include "hardware/stm32g47xxx_memorymap.h" #else # error "Unsupported STM32 memory map" #endif diff --git a/arch/arm/src/stm32/hardware/stm32_pinmap.h b/arch/arm/src/stm32/hardware/stm32_pinmap.h index c945de75854..e41fed5368b 100644 --- a/arch/arm/src/stm32/hardware/stm32_pinmap.h +++ b/arch/arm/src/stm32/hardware/stm32_pinmap.h @@ -131,6 +131,12 @@ #elif defined(CONFIG_STM32_STM32F4XXX) # include "hardware/stm32f40xxx_pinmap.h" + +/* STM32 G4 Family ******************************************************************/ + +#elif defined(CONFIG_STM32_STM32G47XX) +# include "hardware/stm32g47xxx_pinmap.h" + #else # error "No pinmap file for this STM32 chip" #endif diff --git a/arch/arm/src/stm32/hardware/stm32_tim.h b/arch/arm/src/stm32/hardware/stm32_tim.h index c46805526f9..70dda13d87d 100644 --- a/arch/arm/src/stm32/hardware/stm32_tim.h +++ b/arch/arm/src/stm32/hardware/stm32_tim.h @@ -100,6 +100,10 @@ * For the STM32F20xx and STM32F40xx, TIM2 and 5 are 32-bit * The STM32 F1 Value Line and the STM32 F3 have variant general purpose registers * that are not yet fully covered in this header file. + * The STM32 G47x also have variant registers that are not yet covered. Check + * whether those are similar to the F1 and F3 mentioned above. In + * particular, the DCR and DMAR offsets are 0x3dc and 0x3e0, respectively, + * as opposed to the values below: */ #define STM32_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ @@ -129,7 +133,13 @@ #define STM32_GTIM_OR_OFFSET 0x0050 /* Timer 2/5/11/16 option register */ -/* Advanced Timers - TIM1 and TIM8 */ +/* Advanced Timers - TIM1 and TIM8 + * + * The STM32 G47x have variant registers that are not yet covered. In + * particular, the DCR and DMAR offsets are 0x3dc and 0x3e0, respectively, + * as opposed to the values below, and there are several additional + * registers that are not mentioned below at all. + */ #define STM32_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ #define STM32_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit*) */ diff --git a/arch/arm/src/stm32/stm32_allocateheap.c b/arch/arm/src/stm32/stm32_allocateheap.c index 6b2834000b6..1998e07b2f0 100644 --- a/arch/arm/src/stm32/stm32_allocateheap.c +++ b/arch/arm/src/stm32/stm32_allocateheap.c @@ -493,6 +493,94 @@ # endif # endif +/* STM32G47xxx family P/Ns have 96KiB of internal RAM in 2 banks, plus 32 KiB + * of CCM SRAM (Routine Booster), and the possibility of external RAM via + * FSMC: + * + * All internal RAM is contiguous from address 0x2000:0000 thru 0x2001:FFFF, + * but consists of these separate regions: + * + * SRAM: + * + * 1) 80 KiB SRAM1 mapped at 0x2000:0000 thru 0x2001:3FFF. + * 2) 16 KiB SRAM2 mapped at 0x2001:4000 thru 0x2001:7FFF. + * + * CCM SRAM: + * + * 3) 32 KiB CCM SRAM mapped at 0x1000:0000 thru 0x1000:7FFF + * but also aliased at at 0x2001:8000 thru 0x2001:FFFF to be contiguous + * with the SRAM1 and SRAM2. + * + * Because SRAM1 and SRAM2 are contiguous, they are treated as one region + * by this logic. + * + * REVISIT: I believe that unlike other parts mentioned in this file, the + * CCM SRAM *is* accessible to DMA. See Reference Manual (RM0440 Rev 2) + * section 2.1.3, DMA-Bus: "This bus connects the AHB master interface of + * the DMA to the BusMatrix. The targets of this bus are the SRAM1, SRAM2 + * and CCM SRAM..." Then, should we exclude CCM SRAM from the heap? + * + * In addition, external FSMC SRAM may be available. + */ + +#elif defined(CONFIG_STM32_STM32G47XX) + +/* Set the end of system SRAM */ + +# define SRAM1_END 0x20020000 + +/* Set the range of CCM SRAM as well (although we may not use it) */ + +# define SRAM2_START 0x10000000 +# define SRAM2_END 0x10008000 + +/* There are 4 possible SRAM configurations: + * + * Configuration 1. System SRAM (only) + * CONFIG_MM_REGIONS == 1 + * CONFIG_STM32_EXTERNAL_RAM NOT defined + * CONFIG_STM32_CCMEXCLUDE defined + * Configuration 2. System SRAM and CCM SRAM + * CONFIG_MM_REGIONS == 2 + * CONFIG_STM32_EXTERNAL_RAM NOT defined + * CONFIG_STM32_CCMEXCLUDE NOT defined + * Configuration 3. System SRAM and FSMC SRAM + * CONFIG_MM_REGIONS == 2 + * CONFIG_STM32_EXTERNAL_RAM defined + * CONFIG_STM32_CCMEXCLUDE defined + * Configuration 4. System SRAM, CCM SRAM, and FSMC SRAM + * CONFIG_MM_REGIONS == 3 + * CONFIG_STM32_EXTERNAL_RAM defined + * CONFIG_STM32_CCMEXCLUDE NOT defined + * + * Let's make sure that all definitions are consistent before doing + * anything else + */ + +# if defined(CONFIG_STM32_EXTERNAL_RAM) +# if (CONFIG_MM_REGIONS == 2) +/* OK: This is Configuration 3: SRAM and FSMC */ + +# elif (CONFIG_MM_REGIONS == 3) +/* OK: This is Configuration 3: SRAM, CCM, and FSMC */ + +# else +# error "Expected CONFIG_MM_REGIONS to be either 2 (SRAM + FSMC) or 3 (SRAM + CCM + FSMC)!" + +# endif +# else +# if (CONFIG_MM_REGIONS == 1) +/* OK: Configuration 1: SRAM only. */ + +# elif (CONFIG_MM_REGIONS == 2) +/* OK: Configuration 2: SRAM and CCM SRAM. */ + +# else +# error "Expected CONFIG_MM_REGIONS to be either 1 (SRAM) or 2 (SRAM + CCM)!" + +# endif +# endif + #else # error "Unsupported STM32 chip" #endif diff --git a/arch/arm/src/stm32/stm32_dma.c b/arch/arm/src/stm32/stm32_dma.c index 3f0cae3b417..77d5066f612 100644 --- a/arch/arm/src/stm32/stm32_dma.c +++ b/arch/arm/src/stm32/stm32_dma.c @@ -43,7 +43,7 @@ /* This file is only a thin shell that includes the correct DMA * implementation for the selected STM32 IP core: - * - STM32 DMA IP version 1 - F0, F1, F3, L0, L1, L4 + * - STM32 DMA IP version 1 - F0, F1, F3, G4, L0, L1, L4 * - STM32 DMA IP version 2 - F2, F4, F7, H7 * * The STM32 DMA IPv2 differs from the STM32 DMA IPv1 primarily in that it diff --git a/arch/arm/src/stm32/stm32_dma_v1.c b/arch/arm/src/stm32/stm32_dma_v1.c index d269dd64ea4..d40ddca3445 100644 --- a/arch/arm/src/stm32/stm32_dma_v1.c +++ b/arch/arm/src/stm32/stm32_dma_v1.c @@ -56,23 +56,34 @@ #include "stm32_dma.h" #include "stm32.h" -/* This file supports the STM32 DMA IP core version 1 - F0, F1, F3, L0, L1, - * L4. +/* This file supports the STM32 DMA IP core version 1 - F0, F1, F3, G4, L0, + * L1, L4. * * F0, L0 and L4 have the additional CSELR register which is used to remap * the DMA requests for each channel. + * + * G4 has additional channels in DMA1 and DMA2. */ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#define DMA1_NCHANNELS 7 -#if STM32_NDMA > 1 -# define DMA2_NCHANNELS 5 -# define DMA_NCHANNELS (DMA1_NCHANNELS+DMA2_NCHANNELS) +#if defined(CONFIG_STM32_HAVE_DMA1_CHAN8) +# define DMA1_NCHANNELS 8 #else -# define DMA_NCHANNELS DMA1_NCHANNELS +# define DMA1_NCHANNELS 7 +#endif + +#if STM32_NDMA > 1 +# if defined(CONFIG_STM32_HAVE_DMA2_CHAN678) +# define DMA2_NCHANNELS 8 +# else +# define DMA2_NCHANNELS 5 +# endif +# define DMA_NCHANNELS (DMA1_NCHANNELS + DMA2_NCHANNELS) +#else +# define DMA_NCHANNELS DMA1_NCHANNELS #endif /* Convert the DMA channel base address to the DMA register block address */ @@ -106,80 +117,132 @@ struct stm32_dma_s static struct stm32_dma_s g_dma[DMA_NCHANNELS] = { +#if DMA1_NCHANNELS > 0 { .chan = 0, .irq = STM32_IRQ_DMA1CH1, .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(0), }, +#endif /* DMA1_NCHANNELS > 0 */ +#if DMA1_NCHANNELS > 1 { .chan = 1, .irq = STM32_IRQ_DMA1CH2, .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(1), }, +#endif /* DMA1_NCHANNELS > 1 */ +#if DMA1_NCHANNELS > 2 { .chan = 2, .irq = STM32_IRQ_DMA1CH3, .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(2), }, +#endif /* DMA1_NCHANNELS > 2 */ +#if DMA1_NCHANNELS > 3 { .chan = 3, .irq = STM32_IRQ_DMA1CH4, .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(3), }, +#endif /* DMA1_NCHANNELS > 3 */ +#if DMA1_NCHANNELS > 4 { .chan = 4, .irq = STM32_IRQ_DMA1CH5, .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(4), }, +#endif /* DMA1_NCHANNELS > 4 */ +#if DMA1_NCHANNELS > 5 { .chan = 5, .irq = STM32_IRQ_DMA1CH6, .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(5), }, +#endif /* DMA1_NCHANNELS > 5 */ +#if DMA1_NCHANNELS > 6 { .chan = 6, .irq = STM32_IRQ_DMA1CH7, .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(6), }, +#endif /* DMA1_NCHANNELS > 6 */ +#if DMA1_NCHANNELS > 7 + { + .chan = 7, + .irq = STM32_IRQ_DMA1CH8, + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(7), + }, +#endif /* DMA1_NCHANNELS > 7 */ #if STM32_NDMA > 1 +#if DMA2_NCHANNELS > 0 { .chan = 0, .irq = STM32_IRQ_DMA2CH1, .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(0), }, +#endif /* DMA2_NCHANNELS > 0 */ +#if DMA2_NCHANNELS > 1 { .chan = 1, .irq = STM32_IRQ_DMA2CH2, .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(1), }, +#endif /* DMA2_NCHANNELS > 1 */ +#if DMA2_NCHANNELS > 2 { .chan = 2, .irq = STM32_IRQ_DMA2CH3, .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(2), }, +#endif /* DMA2_NCHANNELS > 2 */ +#if DMA2_NCHANNELS > 3 { .chan = 3, #if defined(CONFIG_STM32_CONNECTIVITYLINE) || \ - defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32L15XX) + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \ + defined(CONFIG_STM32_STM32G47XX) || defined(CONFIG_STM32_STM32L15XX) .irq = STM32_IRQ_DMA2CH4, #else .irq = STM32_IRQ_DMA2CH45, #endif .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(3), }, +#endif /* DMA2_NCHANNELS > 3 */ +#if DMA2_NCHANNELS > 4 { .chan = 4, #if defined(CONFIG_STM32_CONNECTIVITYLINE) || \ - defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32L15XX) + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \ + defined(CONFIG_STM32_STM32G47XX) || defined(CONFIG_STM32_STM32L15XX) .irq = STM32_IRQ_DMA2CH5, #else .irq = STM32_IRQ_DMA2CH45, #endif .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(4), }, -#endif +#endif /* DMA2_NCHANNELS > 4 */ +#if DMA2_NCHANNELS > 5 + { + .chan = 5, + .irq = STM32_IRQ_DMA2CH5, + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(5), + }, +#endif /* DMA2_NCHANNELS > 5 */ +#if DMA2_NCHANNELS > 6 + { + .chan = 6, + .irq = STM32_IRQ_DMA2CH6, + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(6), + }, +#endif /* DMA2_NCHANNELS > 6 */ +#if DMA2_NCHANNELS > 7 + { + .chan = 7, + .irq = STM32_IRQ_DMA2CH7, + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(7), + }, +#endif /* DMA2_NCHANNELS > 7 */ +#endif /* STM32_NDMA > 1 */ }; /**************************************************************************** @@ -268,6 +331,41 @@ static void stm32_dmachandisable(struct stm32_dma_s *dmach) DMA_ISR_CHAN_MASK(dmach->chan)); } +/**************************************************************************** + * Name: irq_to_channel_index + * + * Description: + * Given an IRQ number, find the channel index in the g_dma array. + * + * Parameters: + * irq: IRQ number as passed to stm32_dmainterrupt. + * + * Returned Value: + * On success (IRQ matches a DMA channel), returns index in the g_dma + * array from 0 to DMA_NCHANNELS - 1. On failure (IRQ does not match + * a DMA channel), returns -1. + * + ****************************************************************************/ + +static int irq_to_channel_index(int irq) +{ + int chndx; + + /* Find the DMA channel that matches this IRQ */ + + for (chndx = 0; chndx < DMA_NCHANNELS; chndx++) + { + if (irq == g_dma[chndx].irq) + { + return chndx; + } + } + + /* Failed to find the DMA channel for this IRQ */ + + return -1; +} + /**************************************************************************** * Name: stm32_dmainterrupt * @@ -284,23 +382,8 @@ static int stm32_dmainterrupt(int irq, void *context, FAR void *arg) /* Get the channel structure from the interrupt number */ - if (irq >= STM32_IRQ_DMA1CH1 && irq <= STM32_IRQ_DMA1CH7) - { - chndx = irq - STM32_IRQ_DMA1CH1; - } - else -#if STM32_NDMA > 1 -#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32L15XX) - if (irq >= STM32_IRQ_DMA2CH1 && irq <= STM32_IRQ_DMA2CH5) -#else - if (irq >= STM32_IRQ_DMA2CH1 && irq <= STM32_IRQ_DMA2CH45) -#endif - { - chndx = irq - STM32_IRQ_DMA2CH1 + DMA1_NCHANNELS; - } - else -#endif + chndx = irq_to_channel_index(irq); + if (chndx < 0) { DEBUGPANIC(); } diff --git a/arch/arm/src/stm32/stm32_dumpgpio.c b/arch/arm/src/stm32/stm32_dumpgpio.c index d2ec8805338..3fa5157a430 100644 --- a/arch/arm/src/stm32/stm32_dumpgpio.c +++ b/arch/arm/src/stm32/stm32_dumpgpio.c @@ -224,6 +224,36 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg) _info(" GPIO%c not enabled: AHB1ENR: %08x\n", g_portchar[port], getreg32(STM32_RCC_AHB1ENR)); } + +#elif defined(CONFIG_STM32_STM32G47XX) + DEBUGASSERT(port < STM32_NGPIO_PORTS); + + _info("GPIO%c pinset: %08x base: %08x -- %s\n", + g_portchar[port], pinset, base, msg); + + if ((getreg32(STM32_RCC_AHB2ENR) & RCC_AHB2ENR_GPIOEN(port)) != 0) + { + _info(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n", + getreg32(base + STM32_GPIO_MODER_OFFSET), + getreg32(base + STM32_GPIO_OTYPER_OFFSET), + getreg32(base + STM32_GPIO_OSPEED_OFFSET), + getreg32(base + STM32_GPIO_PUPDR_OFFSET)); + _info(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n", + getreg32(base + STM32_GPIO_IDR_OFFSET), + getreg32(base + STM32_GPIO_ODR_OFFSET), + getreg32(base + STM32_GPIO_BSRR_OFFSET), + getreg32(base + STM32_GPIO_LCKR_OFFSET)); + _info(" AFRH: %08x AFRL: %08x BRR: %04x\n", + getreg32(base + STM32_GPIO_AFRH_OFFSET), + getreg32(base + STM32_GPIO_AFRL_OFFSET), + getreg32(base + STM32_GPIO_BRR_OFFSET)); + } + else + { + _info(" GPIO%c not enabled: AHB2ENR: %08x\n", + g_portchar[port], getreg32(STM32_RCC_AHB2ENR)); + } + #else # error "Unsupported STM32 chip" #endif diff --git a/arch/arm/src/stm32/stm32_gpio.c b/arch/arm/src/stm32/stm32_gpio.c index 332e89d6fdc..70f44746a7d 100644 --- a/arch/arm/src/stm32/stm32_gpio.c +++ b/arch/arm/src/stm32/stm32_gpio.c @@ -410,13 +410,14 @@ int stm32_configgpio(uint32_t cfgset) #endif /**************************************************************************** - * Name: stm32_configgpio (for the STM32L15xxx, STM32F20xxx and STM32F40xxx - * family) + * Name: stm32_configgpio (for the STM32L15xxx, STM32F20xxx, STM32F40xxx, + * and STM32G47XX families). ****************************************************************************/ #if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \ defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ - defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX) + defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX) || \ + defined(CONFIG_STM32_STM32G47XX) int stm32_configgpio(uint32_t cfgset) { uintptr_t base; @@ -547,11 +548,11 @@ int stm32_configgpio(uint32_t cfgset) { #if defined(CONFIG_STM32_STM32L15XX) default: - case GPIO_SPEED_400KHz: /* 400 kHz Very low speed output */ + case GPIO_SPEED_400KHz: /* 400 kHz Very low speed output */ setting = GPIO_OSPEED_400KHz; break; - case GPIO_SPEED_2MHz: /* 2 MHz Low speed output */ + case GPIO_SPEED_2MHz: /* 2 MHz Low speed output */ setting = GPIO_OSPEED_2MHz; break; @@ -562,6 +563,23 @@ int stm32_configgpio(uint32_t cfgset) case GPIO_SPEED_40MHz: /* 40 MHz High speed output */ setting = GPIO_OSPEED_40MHz; break; +#elif defined(CONFIG_STM32_STM32G47XX) + default: + case GPIO_SPEED_5MHz: /* 5 MHz Low speed output */ + setting = GPIO_OSPEED_5MHz; + break; + + case GPIO_SPEED_25MHz: /* 25 MHz Medium speed output */ + setting = GPIO_OSPEED_25MHz; + break; + + case GPIO_SPEED_50MHz: /* 50 MHz Fast speed output */ + setting = GPIO_OSPEED_50MHz; + break; + + case GPIO_SPEED_120MHz: /* 120 MHz High speed output */ + setting = GPIO_OSPEED_120MHz; + break; #else default: case GPIO_SPEED_2MHz: /* 2 MHz Low speed output */ @@ -655,10 +673,10 @@ int stm32_configgpio(uint32_t cfgset) * Description: * Unconfigure a GPIO pin based on bit-encoded description of the pin, set * it into default HiZ state (and possibly mark it's unused) and unlock it - * whether it was previously selected as alternative function - * (GPIO_ALT|GPIO_CNF_AFPP|...). + * whether it was previously selected as an alternative function + * (GPIO_ALT | GPIO_CNF_AFPP | ...). * - * This is a safety function and prevents hardware from schocks, as + * This is a safety function and prevents hardware from shocks, as * unexpected write to the Timer Channel Output GPIO to fixed '1' or '0' * while it should operate in PWM mode could produce excessive on-board * currents and trigger over-current/alarm function. @@ -679,7 +697,8 @@ int stm32_unconfiggpio(uint32_t cfgset) cfgset |= GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT; #elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \ defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ - defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX) + defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX) || \ + defined(CONFIG_STM32_STM32G47XX) cfgset |= GPIO_INPUT | GPIO_FLOAT; #else # error "Unsupported STM32 chip" @@ -705,7 +724,8 @@ void stm32_gpiowrite(uint32_t pinset, bool value) uint32_t offset; #elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \ defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ - defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX) + defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX) || \ + defined(CONFIG_STM32_STM32G47XX) uint32_t bit; #endif unsigned int port; @@ -739,7 +759,8 @@ void stm32_gpiowrite(uint32_t pinset, bool value) #elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \ defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ - defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX) + defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX) || \ + defined(CONFIG_STM32_STM32G47XX) if (value) { diff --git a/arch/arm/src/stm32/stm32_gpio.h b/arch/arm/src/stm32/stm32_gpio.h index 65ee437cf9d..498be9f4446 100644 --- a/arch/arm/src/stm32/stm32_gpio.h +++ b/arch/arm/src/stm32/stm32_gpio.h @@ -64,6 +64,8 @@ # include "hardware/stm32f30xxx_gpio.h" #elif defined(CONFIG_STM32_STM32F4XXX) # include "hardware/stm32f40xxx_gpio.h" +#elif defined(CONFIG_STM32_STM32G47XX) +# include "hardware/stm32g47xxx_gpio.h" #else # error "Unrecognized STM32 chip" #endif @@ -204,8 +206,8 @@ #elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \ defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ - defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX) - + defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX) || \ + defined(CONFIG_STM32_STM32G47XX) /* Each port bit of the general-purpose I/O (GPIO) ports can be * individually configured by software in several modes: * @@ -295,16 +297,21 @@ #define GPIO_SPEED_SHIFT (10) /* Bits 10-11: GPIO frequency selection */ #define GPIO_SPEED_MASK (3 << GPIO_SPEED_SHIFT) #if defined(CONFIG_STM32_STM32L15XX) -# define GPIO_SPEED_400KHz (0 << GPIO_SPEED_SHIFT) /* 400 kHz Very low speed output */ -# define GPIO_SPEED_2MHz (1 << GPIO_SPEED_SHIFT) /* 2 MHz Low speed output */ -# define GPIO_SPEED_10MHz (2 << GPIO_SPEED_SHIFT) /* 10 MHz Medium speed output */ -# define GPIO_SPEED_40MHz (3 << GPIO_SPEED_SHIFT) /* 40 MHz High speed output */ +# define GPIO_SPEED_400KHz (0 << GPIO_SPEED_SHIFT) /* 400 kHz Very low speed output */ +# define GPIO_SPEED_2MHz (1 << GPIO_SPEED_SHIFT) /* 2 MHz Low speed output */ +# define GPIO_SPEED_10MHz (2 << GPIO_SPEED_SHIFT) /* 10 MHz Medium speed output */ +# define GPIO_SPEED_40MHz (3 << GPIO_SPEED_SHIFT) /* 40 MHz High speed output */ +#elif defined(CONFIG_STM32_STM32G47XX) /* With C=50pF, 2.7priv; #if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ - defined(CONFIG_STM32_STM32F37XX) + defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32G47XX) uint32_t usartdiv8; #else uint32_t usartdiv32; @@ -1192,7 +1192,7 @@ static void up_set_format(struct uart_dev_s *dev) regval = up_serialin(priv, STM32_USART_CR1_OFFSET); #if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)|| \ - defined(CONFIG_STM32_STM32F37XX) + defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32G47XX) /* This first implementation is for U[S]ARTs that support oversampling * by 8 in additional to the standard oversampling by 16. * With baud rate of fCK / Divider for oversampling by 16. @@ -1882,7 +1882,7 @@ static int up_interrupt(int irq, void *context, void *arg) else if ((priv->sr & (USART_SR_ORE | USART_SR_NE | USART_SR_FE)) != 0) { #if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ - defined(CONFIG_STM32_STM32F37XX) + defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32G47XX) /* These errors are cleared by writing the corresponding bit to the * interrupt clear register (ICR). */ diff --git a/arch/arm/src/stm32/stm32_syscfg.h b/arch/arm/src/stm32/stm32_syscfg.h index 83005fd9568..feb363ddb32 100644 --- a/arch/arm/src/stm32/stm32_syscfg.h +++ b/arch/arm/src/stm32/stm32_syscfg.h @@ -55,6 +55,8 @@ # include "hardware/stm32f37xxx_syscfg.h" #elif defined(CONFIG_STM32_STM32F4XXX) # include "hardware/stm32f40xxx_syscfg.h" +#elif defined(CONFIG_STM32_STM32G47XX) +# include "hardware/stm32g47xxx_syscfg.h" #endif /**************************************************************************************************** diff --git a/arch/arm/src/stm32/stm32_uart.h b/arch/arm/src/stm32/stm32_uart.h index 8695a80ab82..1a87544e616 100644 --- a/arch/arm/src/stm32/stm32_uart.h +++ b/arch/arm/src/stm32/stm32_uart.h @@ -56,6 +56,8 @@ # include "hardware/stm32f30xxx_uart.h" #elif defined(CONFIG_STM32_STM32F4XXX) # include "hardware/stm32f40xxx_uart.h" +#elif defined(CONFIG_STM32_STM32G47XX) +# include "hardware/stm32g47xxx_uart.h" #else # error "Unsupported STM32 UART" #endif