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Add support for STM32G474: New files
Add support for the STM32G474 family of microcontrollers and the
B-G474E-DPOW1 Discovery Board, which features a STM32G474RET6.
This is a major pull request as it adds support for an entirely
new family of STM32. This support is implemented in
arch/arm/src/stm32 and shares implementation with other STM32
families supported by that code, such as the 'L15xx, 'F10xx,
'F20xx, 'F3xxx, and 'F4xxx.
arch/arm/include/stm32/stm32g47xxx_irq.h:
arch/arm/src/stm32/hardware/stm32g474cxx_pinmap.h:
arch/arm/src/stm32/hardware/stm32g474mxx_pinmap.h:
arch/arm/src/stm32/hardware/stm32g474qxx_pinmap.h:
arch/arm/src/stm32/hardware/stm32g474rxx_pinmap.h:
arch/arm/src/stm32/hardware/stm32g474vxx_pinmap.h:
arch/arm/src/stm32/hardware/stm32g47xxx_gpio.h:
arch/arm/src/stm32/hardware/stm32g47xxx_memorymap.h:
arch/arm/src/stm32/hardware/stm32g47xxx_pinmap.h:
arch/arm/src/stm32/hardware/stm32g47xxx_pwr.h:
arch/arm/src/stm32/hardware/stm32g47xxx_rcc.h:
arch/arm/src/stm32/hardware/stm32g47xxx_syscfg.h:
arch/arm/src/stm32/hardware/stm32g47xxx_uart.h:
arch/arm/src/stm32/stm32g47xxx_rcc.c:
* New files required for architectural support. Note that
existing NuttX files are not modified. As such, in this
revision, the system is unaffected by their addition.
With big thanks for detailed code review:
David Sidrane (davids5)
Mateusz Szafoni (raiden00)
Abdelatif Guettouche (Ouss4)
This commit is contained in:
Nathan Hartman
committed by
Alan Carvalho de Assis
Alan Carvalho de Assis
parent
31bb58548d
commit
3b4e4c603f
@@ -0,0 +1,200 @@
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/****************************************************************************************************
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* arch/arm/include/stm32/stm32g47xxx_irq.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************************************/
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/* This file should never be included directly but, rather, only indirectly
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* through nuttx/irq.h
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*/
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#ifndef __ARCH_ARM_INCLUDE_STM32_STM32G47XXX_IRQ_H
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#define __ARCH_ARM_INCLUDE_STM32_STM32G47XXX_IRQ_H
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/****************************************************************************************************
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* Included Files
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****************************************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/irq.h>
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/****************************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************************/
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/* IRQ numbers. The IRQ numbers correspond to the vector numbers and hence
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* map directly to bits in the NVIC. This does, however, waste several words
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* of memory in the IRQ to handle mapping tables.
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*
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* Processor Exceptions (vectors 0-15) are common to all STM32 parts and are
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* found in nuttx/arch/arm/include/stm32/irq.h. They are not repeated here.
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*
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* Other interrupts (vectors >= 16) are defined below.
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*/
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#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */
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#define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */
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#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper interrupt, or Time Stamp (shared with STM32_IRQ_TIMESTAMP) */
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#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Time stamp interrupt (shared with STM32_IRQ_TAMPER) */
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#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC global interrupt */
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#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */
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#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */
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#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */
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#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */
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#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt, or */
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#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */
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#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */
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#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 channel 1 global interrupt */
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#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 channel 2 global interrupt */
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#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 channel 3 global interrupt */
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#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 channel 4 global interrupt */
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#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 channel 5 global interrupt */
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#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 channel 6 global interrupt */
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#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 channel 7 global interrupt */
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#define STM32_IRQ_ADC12 (STM32_IRQ_FIRST + 18) /* 18: ADC1 and ADC2 shared global interrupt */
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#define STM32_IRQ_USBHP (STM32_IRQ_FIRST + 19) /* 19: USB High priority interrupt */
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#define STM32_IRQ_USBLP (STM32_IRQ_FIRST + 20) /* 20: USB Low priority interrupt */
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#define STM32_IRQ_FDCAN1_0 (STM32_IRQ_FIRST + 21) /* 21: FDCAN1 interrupt 0 */
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#define STM32_IRQ_FDCAN1_1 (STM32_IRQ_FIRST + 22) /* 22: FDCAN1 interrupt 1 */
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#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */
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#define STM32_IRQ_TIM15 (STM32_IRQ_FIRST + 24) /* 24: TIM15 global interrupt (shared with STM32_IRQ_TIM1BRK) */
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#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 24) /* 24: TIM1 Break, Transition error, Index error (shared with STM32_IRQ_TIM15) */
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#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 25) /* 25: TIM16 global interrupt (shared with STM32_IRQ_TIM1UP) */
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#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt (shared with STM32_IRQ_TIM16) */
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#define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 26) /* 26: TIM17 global interrupt (shared with STM32_IRQ_TIM1TRGCOM) */
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#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 26) /* 26: TIM1 Trigger, Commutation, Direction Change, and Index interrupt (shared with STM32_IRQ_TIM17) */
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#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */
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#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */
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#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */
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#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */
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#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */
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#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */
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#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */
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#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */
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#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */
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#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */
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#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global interrupt */
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#define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global interrupt */
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#define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global interrupt */
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#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */
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#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */
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#define STM32_IRQ_USBWKUP (STM32_IRQ_FIRST + 42) /* 42: 42: USB wakeup from suspend through EXTI line interrupt */
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#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 43) /* 43: TIM8 Break, Transition error, Index error */
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#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */
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#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 45) /* 45: TIM8 Trigger, Commutation, Direction Change, and Index interrupt */
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#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */
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#define STM32_IRQ_ADC3 (STM32_IRQ_FIRST + 47) /* 47: ADC3 global interrupt */
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#define STM32_IRQ_FMC (STM32_IRQ_FIRST + 48) /* 48: FMC global interrupt */
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#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 49) /* 49: LPTIM1 interrupt */
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#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */
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#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */
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#define STM32_IRQ_UART4 (STM32_IRQ_FIRST + 52) /* 52: UART4 global interrupt */
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#define STM32_IRQ_UART5 (STM32_IRQ_FIRST + 53) /* 53: UART5 global interrupt */
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#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 54) /* 54: TIM6 global interrupt (shared with STM32_IRQ_DAC1, STM32_IRQ_DAC3) */
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#define STM32_IRQ_DAC1 (STM32_IRQ_FIRST + 54) /* 54: DAC1 underrun error interrupt (shared with STM32_IRQ_TIM6, STM32_IRQ_DAC3) */
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#define STM32_IRQ_DAC3 (STM32_IRQ_FIRST + 54) /* 54: DAC3 underrun error interrupt (shared with STM32_IRQ_TIM6, STM32_IRQ_DAC1) */
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#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 55) /* 55: TIM7 global interrupt (shared with STM32_IRQ_DAC2, STM32_IRQ_DAC4) */
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#define STM32_IRQ_DAC2 (STM32_IRQ_FIRST + 55) /* 55: DAC2 underrun error interrupt (shared with STM32_IRQ_TIM7) */
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#define STM32_IRQ_DAC4 (STM32_IRQ_FIRST + 55) /* 55: DAC4 underrun error interrupt (shared with STM32_IRQ_TIM7) */
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#define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 56) /* 56: DMA2 channel 1 global interrupt */
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#define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 57) /* 57: DMA2 channel 2 global interrupt */
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#define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 58) /* 58: DMA2 channel 3 global interrupt */
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#define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 59) /* 59: DMA2 channel 4 global interrupt */
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#define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 60) /* 60: DMA2 channel 5 global interrupt */
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#define STM32_IRQ_ADC4 (STM32_IRQ_FIRST + 61) /* 61: ADC4 global interrupt */
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#define STM32_IRQ_ADC5 (STM32_IRQ_FIRST + 62) /* 62: ADC5 global interrupt */
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#define STM32_IRQ_UCPD (STM32_IRQ_FIRST + 63) /* 63: UCPD global interrupt */
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#define STM32_IRQ_COMP123 (STM32_IRQ_FIRST + 64) /* 64: COMP1, COMP2, and COMP3 interrupts */
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#define STM32_IRQ_COMP456 (STM32_IRQ_FIRST + 65) /* 65: COMP4, COMP5, and COMP6 interrupts */
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#define STM32_IRQ_COMP7 (STM32_IRQ_FIRST + 66) /* 66: COMPP7 interrupt */
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#define STM32_IRQ_HRTIM1MST (STM32_IRQ_FIRST + 67) /* 67: HRTIM1 master timer interrupt */
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#define STM32_IRQ_HRTIM1TIMA (STM32_IRQ_FIRST + 68) /* 68: HRTIM1 timer A interrupt */
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#define STM32_IRQ_HRTIM1TIMB (STM32_IRQ_FIRST + 69) /* 69: HRTIM1 timer B interrupt */
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#define STM32_IRQ_HRTIM1TIMC (STM32_IRQ_FIRST + 70) /* 70: HRTIM1 timer C interrupt */
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#define STM32_IRQ_HRTIM1TIMD (STM32_IRQ_FIRST + 71) /* 71: HRTIM1 timer D interrupt */
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#define STM32_IRQ_HRTIM1TIME (STM32_IRQ_FIRST + 72) /* 72: HRTIM1 timer E interrupt */
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#define STM32_IRQ_HRTIM1FLT (STM32_IRQ_FIRST + 73) /* 73: HRTIM1 fault interrupt */
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#define STM32_IRQ_HRTIM1TIMF (STM32_IRQ_FIRST + 74) /* 74: HRTIM1 timer E interrupt */
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#define STM32_IRQ_CRS (STM32_IRQ_FIRST + 75) /* 75: CRS (Clock Recovery System) global interrupt */
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#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 76) /* 76: SAI4 global interrupt */
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#define STM32_IRQ_TIM20BRK (STM32_IRQ_FIRST + 77) /* 77: TIM20 Break, Transition error, Index error interrupt */
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#define STM32_IRQ_TIM20UP (STM32_IRQ_FIRST + 78) /* 78: TIM20 Update interrupt */
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#define STM32_IRQ_TIM20TRGCOM (STM32_IRQ_FIRST + 79) /* 79: TIM20 Trigger, Commutation, Direction Change, and Index interrupt */
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#define STM32_IRQ_TIM20CC (STM32_IRQ_FIRST + 80) /* 80: TIM20 Capture Compare interrupt */
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#define STM32_IRQ_FPU (STM32_IRQ_FIRST + 81) /* 81: FPU global interrupt */
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#define STM32_IRQ_I2C4EV (STM32_IRQ_FIRST + 82) /* 82: I2C4 event interrupt */
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#define STM32_IRQ_I2C4ER (STM32_IRQ_FIRST + 83) /* 83: I2C4 error interrupt */
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#define STM32_IRQ_SPI4 (STM32_IRQ_FIRST + 84) /* 84: SPI4 global interrupt */
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#define STM32_IRQ_AES (STM32_IRQ_FIRST + 85) /* 85: AES global interrupt */
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#define STM32_IRQ_FDCAN2_0 (STM32_IRQ_FIRST + 86) /* 86: FDCAN2 interrupt 0 */
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#define STM32_IRQ_FDCAN2_1 (STM32_IRQ_FIRST + 87) /* 87: FDCAN2 interrupt 1 */
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#define STM32_IRQ_FDCAN3_0 (STM32_IRQ_FIRST + 88) /* 88: FDCAN3 interrupt 0 */
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#define STM32_IRQ_FDCAN3_1 (STM32_IRQ_FIRST + 89) /* 89: FDCAN3 interrupt 1 */
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#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 90) /* 90: RNG global interrupt */
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#define STM32_IRQ_LPUART (STM32_IRQ_FIRST + 91) /* 91: LPUART global interrupt */
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#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 92) /* 92: I2C3 event interrupt */
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#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 93) /* 93: I2C3 error interrupt */
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#define STM32_IRQ_DMAMUXOV (STM32_IRQ_FIRST + 94) /* 94: DMAMUX overrun interrupt */
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#define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST + 95) /* 95: QuadSPI global interrupt */
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#define STM32_IRQ_DMA1CH8 (STM32_IRQ_FIRST + 96) /* 96: DMA1 channel 8 global interrupt */
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#define STM32_IRQ_DMA2CH6 (STM32_IRQ_FIRST + 97) /* 97: DMA2 channel 6 global interrupt */
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#define STM32_IRQ_DMA2CH7 (STM32_IRQ_FIRST + 98) /* 98: DMA2 channel 7 global interrupt */
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#define STM32_IRQ_DMA2CH8 (STM32_IRQ_FIRST + 99) /* 99: DMA2 channel 8 global interrupt */
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#define STM32_IRQ_CORDIC (STM32_IRQ_FIRST + 100) /* 100: CORDIC trigonometric accelerator interrupt */
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#define STM32_IRQ_FMAC (STM32_IRQ_FIRST + 101) /* 101: FMAC filter math acclerator interrupt */
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#define STM32_IRQ_NEXTINT (102)
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#define NR_IRQS (STM32_IRQ_FIRST + 102)
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/****************************************************************************************************
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* Public Types
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****************************************************************************************************/
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/****************************************************************************************************
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* Public Data
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****************************************************************************************************/
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************************************
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* Public Function Prototypes
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****************************************************************************************************/
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif
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#endif /* __ARCH_ARM_INCLUDE_STM32F30XXX_IRQ_H */
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
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Load Diff
@@ -0,0 +1,340 @@
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/****************************************************************************
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* arch/arm/src/stm32/hardware/stm32g47xxx_gpio.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
|
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* contributor license agreements. See the NOTICE file distributed with
|
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
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* "License"); you may not use this file except in compliance with the
|
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* License. You may obtain a copy of the License at
|
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_GPIO_H
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#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_GPIO_H
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define STM32_NGPIO_PORTS (7) /* GPIOA-G */
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/* Register Offsets *********************************************************/
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#define STM32_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */
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#define STM32_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */
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#define STM32_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */
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#define STM32_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */
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#define STM32_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */
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#define STM32_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */
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#define STM32_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */
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#define STM32_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */
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#define STM32_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */
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#define STM32_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */
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#define STM32_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */
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/* Register Addresses *******************************************************/
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#if (STM32_NGPIO_PORTS > 0)
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# define STM32_GPIOA_MODER (STM32_GPIOA_BASE + STM32_GPIO_MODER_OFFSET)
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# define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE + STM32_GPIO_OTYPER_OFFSET)
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# define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE + STM32_GPIO_OSPEED_OFFSET)
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# define STM32_GPIOA_PUPDR (STM32_GPIOA_BASE + STM32_GPIO_PUPDR_OFFSET)
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# define STM32_GPIOA_IDR (STM32_GPIOA_BASE + STM32_GPIO_IDR_OFFSET)
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# define STM32_GPIOA_ODR (STM32_GPIOA_BASE + STM32_GPIO_ODR_OFFSET)
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# define STM32_GPIOA_BSRR (STM32_GPIOA_BASE + STM32_GPIO_BSRR_OFFSET)
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# define STM32_GPIOA_LCKR (STM32_GPIOA_BASE + STM32_GPIO_LCKR_OFFSET)
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# define STM32_GPIOA_AFRL (STM32_GPIOA_BASE + STM32_GPIO_AFRL_OFFSET)
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# define STM32_GPIOA_AFRH (STM32_GPIOA_BASE + STM32_GPIO_AFRH_OFFSET)
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# define STM32_GPIOA_BRR (STM32_GPIOA_BASE + STM32_GPIO_BRR_OFFSET)
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#endif
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#if (STM32_NGPIO_PORTS > 1)
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# define STM32_GPIOB_MODER (STM32_GPIOB_BASE + STM32_GPIO_MODER_OFFSET)
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# define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE + STM32_GPIO_OTYPER_OFFSET)
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# define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE + STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOB_PUPDR (STM32_GPIOB_BASE + STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOB_IDR (STM32_GPIOB_BASE + STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOB_ODR (STM32_GPIOB_BASE + STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOB_BSRR (STM32_GPIOB_BASE + STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOB_LCKR (STM32_GPIOB_BASE + STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOB_AFRL (STM32_GPIOB_BASE + STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOB_AFRH (STM32_GPIOB_BASE + STM32_GPIO_AFRH_OFFSET)
|
||||
# define STM32_GPIOB_BRR (STM32_GPIOB_BASE + STM32_GPIO_BRR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if (STM32_NGPIO_PORTS > 2)
|
||||
# define STM32_GPIOC_MODER (STM32_GPIOC_BASE + STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE + STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE + STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOC_PUPDR (STM32_GPIOC_BASE + STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOC_IDR (STM32_GPIOC_BASE + STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOC_ODR (STM32_GPIOC_BASE + STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOC_BSRR (STM32_GPIOC_BASE + STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOC_LCKR (STM32_GPIOC_BASE + STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOC_AFRL (STM32_GPIOC_BASE + STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOC_AFRH (STM32_GPIOC_BASE + STM32_GPIO_AFRH_OFFSET)
|
||||
# define STM32_GPIOC_BRR (STM32_GPIOC_BASE + STM32_GPIO_BRR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if (STM32_NGPIO_PORTS > 3)
|
||||
# define STM32_GPIOD_MODER (STM32_GPIOD_BASE + STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE + STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE + STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOD_PUPDR (STM32_GPIOD_BASE + STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOD_IDR (STM32_GPIOD_BASE + STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOD_ODR (STM32_GPIOD_BASE + STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOD_BSRR (STM32_GPIOD_BASE + STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOD_LCKR (STM32_GPIOD_BASE + STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOD_AFRL (STM32_GPIOD_BASE + STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOD_AFRH (STM32_GPIOD_BASE + STM32_GPIO_AFRH_OFFSET)
|
||||
# define STM32_GPIOD_BRR (STM32_GPIOD_BASE + STM32_GPIO_BRR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if (STM32_NGPIO_PORTS > 4)
|
||||
# define STM32_GPIOE_MODER (STM32_GPIOE_BASE + STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE + STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE + STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOE_PUPDR (STM32_GPIOE_BASE + STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOE_IDR (STM32_GPIOE_BASE + STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOE_ODR (STM32_GPIOE_BASE + STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOE_BSRR (STM32_GPIOE_BASE + STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOE_LCKR (STM32_GPIOE_BASE + STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOE_AFRL (STM32_GPIOE_BASE + STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOE_AFRH (STM32_GPIOE_BASE + STM32_GPIO_AFRH_OFFSET)
|
||||
# define STM32_GPIOE_BRR (STM32_GPIOE_BASE + STM32_GPIO_BRR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if (STM32_NGPIO_PORTS > 5)
|
||||
# define STM32_GPIOF_MODER (STM32_GPIOF_BASE + STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE + STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE + STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOF_PUPDR (STM32_GPIOF_BASE + STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOF_IDR (STM32_GPIOF_BASE + STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOF_ODR (STM32_GPIOF_BASE + STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOF_BSRR (STM32_GPIOF_BASE + STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOF_LCKR (STM32_GPIOF_BASE + STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOF_AFRL (STM32_GPIOF_BASE + STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOF_AFRH (STM32_GPIOF_BASE + STM32_GPIO_AFRH_OFFSET)
|
||||
# define STM32_GPIOF_BRR (STM32_GPIOF_BASE + STM32_GPIO_BRR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if (STM32_NGPIO_PORTS > 6)
|
||||
# define STM32_GPIOG_MODER (STM32_GPIOG_BASE + STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE + STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE + STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOG_PUPDR (STM32_GPIOG_BASE + STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOG_IDR (STM32_GPIOG_BASE + STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOG_ODR (STM32_GPIOG_BASE + STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOG_BSRR (STM32_GPIOG_BASE + STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOG_LCKR (STM32_GPIOG_BASE + STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOG_AFRL (STM32_GPIOG_BASE + STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOG_AFRH (STM32_GPIOG_BASE + STM32_GPIO_AFRH_OFFSET)
|
||||
# define STM32_GPIOG_BRR (STM32_GPIOG_BASE + STM32_GPIO_BRR_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
/* GPIO port mode register */
|
||||
|
||||
#define GPIO_MODER_INPUT (0x0) /* Input mode */
|
||||
#define GPIO_MODER_OUTPUT (0x1) /* General purpose output mode */
|
||||
#define GPIO_MODER_ALT (0x2) /* Alternate mode */
|
||||
#define GPIO_MODER_ANALOG (0x3) /* Analog mode (reset state) */
|
||||
|
||||
#define GPIO_MODER_SHIFT(n) ((n) << 1)
|
||||
#define GPIO_MODER_MASK(n) (0x3 << GPIO_MODER_SHIFT(n))
|
||||
|
||||
#define GPIO_MODER0_SHIFT (0)
|
||||
#define GPIO_MODER0_MASK (3 << GPIO_MODER0_SHIFT)
|
||||
#define GPIO_MODER1_SHIFT (2)
|
||||
#define GPIO_MODER1_MASK (3 << GPIO_MODER1_SHIFT)
|
||||
#define GPIO_MODER2_SHIFT (4)
|
||||
#define GPIO_MODER2_MASK (3 << GPIO_MODER2_SHIFT)
|
||||
#define GPIO_MODER3_SHIFT (6)
|
||||
#define GPIO_MODER3_MASK (3 << GPIO_MODER3_SHIFT)
|
||||
#define GPIO_MODER4_SHIFT (8)
|
||||
#define GPIO_MODER4_MASK (3 << GPIO_MODER4_SHIFT)
|
||||
#define GPIO_MODER5_SHIFT (10)
|
||||
#define GPIO_MODER5_MASK (3 << GPIO_MODER5_SHIFT)
|
||||
#define GPIO_MODER6_SHIFT (12)
|
||||
#define GPIO_MODER6_MASK (3 << GPIO_MODER6_SHIFT)
|
||||
#define GPIO_MODER7_SHIFT (14)
|
||||
#define GPIO_MODER7_MASK (3 << GPIO_MODER7_SHIFT)
|
||||
#define GPIO_MODER8_SHIFT (16)
|
||||
#define GPIO_MODER8_MASK (3 << GPIO_MODER8_SHIFT)
|
||||
#define GPIO_MODER9_SHIFT (18)
|
||||
#define GPIO_MODER9_MASK (3 << GPIO_MODER9_SHIFT)
|
||||
#define GPIO_MODER10_SHIFT (20)
|
||||
#define GPIO_MODER10_MASK (3 << GPIO_MODER10_SHIFT)
|
||||
#define GPIO_MODER11_SHIFT (22)
|
||||
#define GPIO_MODER11_MASK (3 << GPIO_MODER11_SHIFT)
|
||||
#define GPIO_MODER12_SHIFT (24)
|
||||
#define GPIO_MODER12_MASK (3 << GPIO_MODER12_SHIFT)
|
||||
#define GPIO_MODER13_SHIFT (26)
|
||||
#define GPIO_MODER13_MASK (3 << GPIO_MODER13_SHIFT)
|
||||
#define GPIO_MODER14_SHIFT (28)
|
||||
#define GPIO_MODER14_MASK (3 << GPIO_MODER14_SHIFT)
|
||||
#define GPIO_MODER15_SHIFT (30)
|
||||
#define GPIO_MODER15_MASK (3 << GPIO_MODER15_SHIFT)
|
||||
|
||||
/* GPIO port output type register */
|
||||
|
||||
#define GPIO_OTYPER_PP(n) (0) /* 0=Output push-pull (reset state) */
|
||||
#define GPIO_OTYPER_OD(n) (1 << (n)) /* 1=Output open-drain */
|
||||
|
||||
/* GPIO port output speed register */
|
||||
|
||||
#define GPIO_OSPEED_5MHz (0x0) /* 5 MHz Low speed output */
|
||||
#define GPIO_OSPEED_25MHz (0x1) /* 25 MHz Medium speed output */
|
||||
#define GPIO_OSPEED_50MHz (0x2) /* 50 MHz Fast speed output */
|
||||
#define GPIO_OSPEED_120MHz (0x3) /* 120 MHz High speed output */
|
||||
|
||||
#define GPIO_OSPEED_SHIFT(n) ((n) << 1)
|
||||
#define GPIO_OSPEED_MASK(n) (0x3 << GPIO_OSPEED_SHIFT(n))
|
||||
|
||||
#define GPIO_OSPEED0_SHIFT (GPIO_OSPEED_SHIFT(0))
|
||||
#define GPIO_OSPEED0_MASK (GPIO_OSPEED_MASK(0))
|
||||
#define GPIO_OSPEED1_SHIFT (GPIO_OSPEED_SHIFT(1))
|
||||
#define GPIO_OSPEED1_MASK (GPIO_OSPEED_MASK(1))
|
||||
#define GPIO_OSPEED2_SHIFT (GPIO_OSPEED_SHIFT(2))
|
||||
#define GPIO_OSPEED2_MASK (GPIO_OSPEED_MASK(2))
|
||||
#define GPIO_OSPEED3_SHIFT (GPIO_OSPEED_SHIFT(3))
|
||||
#define GPIO_OSPEED3_MASK (GPIO_OSPEED_MASK(3))
|
||||
#define GPIO_OSPEED4_SHIFT (GPIO_OSPEED_SHIFT(4))
|
||||
#define GPIO_OSPEED4_MASK (GPIO_OSPEED_MASK(4))
|
||||
#define GPIO_OSPEED5_SHIFT (GPIO_OSPEED_SHIFT(5))
|
||||
#define GPIO_OSPEED5_MASK (GPIO_OSPEED_MASK(5))
|
||||
#define GPIO_OSPEED6_SHIFT (GPIO_OSPEED_SHIFT(6))
|
||||
#define GPIO_OSPEED6_MASK (GPIO_OSPEED_MASK(6))
|
||||
#define GPIO_OSPEED7_SHIFT (GPIO_OSPEED_SHIFT(7))
|
||||
#define GPIO_OSPEED7_MASK (GPIO_OSPEED_MASK(7))
|
||||
#define GPIO_OSPEED8_SHIFT (GPIO_OSPEED_SHIFT(8))
|
||||
#define GPIO_OSPEED8_MASK (GPIO_OSPEED_MASK(8))
|
||||
#define GPIO_OSPEED9_SHIFT (GPIO_OSPEED_SHIFT(9))
|
||||
#define GPIO_OSPEED9_MASK (GPIO_OSPEED_MASK(9))
|
||||
#define GPIO_OSPEED10_SHIFT (GPIO_OSPEED_SHIFT(10))
|
||||
#define GPIO_OSPEED10_MASK (GPIO_OSPEED_MASK(10))
|
||||
#define GPIO_OSPEED11_SHIFT (GPIO_OSPEED_SHIFT(11))
|
||||
#define GPIO_OSPEED11_MASK (GPIO_OSPEED_MASK(11))
|
||||
#define GPIO_OSPEED12_SHIFT (GPIO_OSPEED_SHIFT(12))
|
||||
#define GPIO_OSPEED12_MASK (GPIO_OSPEED_MASK(12))
|
||||
#define GPIO_OSPEED13_SHIFT (GPIO_OSPEED_SHIFT(13))
|
||||
#define GPIO_OSPEED13_MASK (GPIO_OSPEED_MASK(13))
|
||||
#define GPIO_OSPEED14_SHIFT (GPIO_OSPEED_SHIFT(14))
|
||||
#define GPIO_OSPEED14_MASK (GPIO_OSPEED_MASK(14))
|
||||
#define GPIO_OSPEED15_SHIFT (GPIO_OSPEED_SHIFT(15))
|
||||
#define GPIO_OSPEED15_MASK (GPIO_OSPEED_MASK(15))
|
||||
|
||||
/* GPIO port pull-up/pull-down register */
|
||||
|
||||
#define GPIO_PUPDR_NONE (0x0) /* No pull-up, pull-down */
|
||||
#define GPIO_PUPDR_PULLUP (0x1) /* Pull-up */
|
||||
#define GPIO_PUPDR_PULLDOWN (0x2) /* Pull-down */
|
||||
|
||||
#define GPIO_PUPDR_SHIFT(n) ((n) << 1)
|
||||
#define GPIO_PUPDR_MASK(n) (0x3 << GPIO_PUPDR_SHIFT(n))
|
||||
|
||||
#define GPIO_PUPDR0_SHIFT GPIO_PUPDR_SHIFT(0)
|
||||
#define GPIO_PUPDR0_MASK GPIO_PUPDR_MASK(0)
|
||||
#define GPIO_PUPDR1_SHIFT GPIO_PUPDR_SHIFT(1)
|
||||
#define GPIO_PUPDR1_MASK GPIO_PUPDR_MASK(1)
|
||||
#define GPIO_PUPDR2_SHIFT GPIO_PUPDR_SHIFT(2)
|
||||
#define GPIO_PUPDR2_MASK GPIO_PUPDR_MASK(2)
|
||||
#define GPIO_PUPDR3_SHIFT GPIO_PUPDR_SHIFT(3)
|
||||
#define GPIO_PUPDR3_MASK GPIO_PUPDR_MASK(3)
|
||||
#define GPIO_PUPDR4_SHIFT GPIO_PUPDR_SHIFT(4)
|
||||
#define GPIO_PUPDR4_MASK GPIO_PUPDR_MASK(4)
|
||||
#define GPIO_PUPDR5_SHIFT GPIO_PUPDR_SHIFT(5)
|
||||
#define GPIO_PUPDR5_MASK GPIO_PUPDR_MASK(5)
|
||||
#define GPIO_PUPDR6_SHIFT GPIO_PUPDR_SHIFT(6)
|
||||
#define GPIO_PUPDR6_MASK GPIO_PUPDR_MASK(6)
|
||||
#define GPIO_PUPDR7_SHIFT GPIO_PUPDR_SHIFT(7)
|
||||
#define GPIO_PUPDR7_MASK GPIO_PUPDR_MASK(7)
|
||||
#define GPIO_PUPDR8_SHIFT GPIO_PUPDR_SHIFT(8)
|
||||
#define GPIO_PUPDR8_MASK GPIO_PUPDR_MASK(8)
|
||||
#define GPIO_PUPDR9_SHIFT GPIO_PUPDR_SHIFT(9)
|
||||
#define GPIO_PUPDR9_MASK GPIO_PUPDR_MASK(9)
|
||||
#define GPIO_PUPDR10_SHIFT GPIO_PUPDR_SHIFT(10)
|
||||
#define GPIO_PUPDR10_MASK GPIO_PUPDR_MASK(10)
|
||||
#define GPIO_PUPDR11_SHIFT GPIO_PUPDR_SHIFT(11)
|
||||
#define GPIO_PUPDR11_MASK GPIO_PUPDR_MASK(11)
|
||||
#define GPIO_PUPDR12_SHIFT GPIO_PUPDR_SHIFT(12)
|
||||
#define GPIO_PUPDR12_MASK GPIO_PUPDR_MASK(12)
|
||||
#define GPIO_PUPDR13_SHIFT GPIO_PUPDR_SHIFT(13)
|
||||
#define GPIO_PUPDR13_MASK GPIO_PUPDR_MASK(13)
|
||||
#define GPIO_PUPDR14_SHIFT GPIO_PUPDR_SHIFT(14)
|
||||
#define GPIO_PUPDR14_MASK GPIO_PUPDR_MASK(14)
|
||||
#define GPIO_PUPDR15_SHIFT GPIO_PUPDR_SHIFT(15)
|
||||
#define GPIO_PUPDR15_MASK GPIO_PUPDR_MASK(15)
|
||||
|
||||
/* GPIO port input data register */
|
||||
|
||||
#define GPIO_IDR(n) (1 << (n))
|
||||
|
||||
/* GPIO port output data register */
|
||||
|
||||
#define GPIO_ODR(n) (1 << (n))
|
||||
|
||||
/* GPIO port bit set/reset register */
|
||||
|
||||
#define GPIO_BSRR_SET(n) (1 << (n))
|
||||
#define GPIO_BSRR_RESET(n) (1 << ((n) + 16))
|
||||
|
||||
/* GPIO port configuration lock register */
|
||||
|
||||
#define GPIO_LCKR(n) (1 << (n))
|
||||
#define GPIO_LCKK (1 << 16) /* Lock key */
|
||||
|
||||
/* GPIO alternate function low/high register */
|
||||
|
||||
#define GPIO_AFR_SHIFT(n) ((n) << 2)
|
||||
#define GPIO_AFR_MASK(n) (0xf << GPIO_AFR_SHIFT(n))
|
||||
|
||||
#define GPIO_AFRL0_SHIFT (0)
|
||||
#define GPIO_AFRL0_MASK (0xf << GPIO_AFRL0_SHIFT)
|
||||
#define GPIO_AFRL1_SHIFT (4)
|
||||
#define GPIO_AFRL1_MASK (0xf << GPIO_AFRL1_SHIFT)
|
||||
#define GPIO_AFRL2_SHIFT (8)
|
||||
#define GPIO_AFRL2_MASK (0xf << GPIO_AFRL2_SHIFT)
|
||||
#define GPIO_AFRL3_SHIFT (12)
|
||||
#define GPIO_AFRL3_MASK (0xf << GPIO_AFRL3_SHIFT)
|
||||
#define GPIO_AFRL4_SHIFT (16)
|
||||
#define GPIO_AFRL4_MASK (0xf << GPIO_AFRL4_SHIFT)
|
||||
#define GPIO_AFRL5_SHIFT (20)
|
||||
#define GPIO_AFRL5_MASK (0xf << GPIO_AFRL5_SHIFT)
|
||||
#define GPIO_AFRL6_SHIFT (24)
|
||||
#define GPIO_AFRL6_MASK (0xf << GPIO_AFRL6_SHIFT)
|
||||
#define GPIO_AFRL7_SHIFT (28)
|
||||
#define GPIO_AFRL7_MASK (0xf << GPIO_AFRL7_SHIFT)
|
||||
|
||||
#define GPIO_AFRH8_SHIFT (0)
|
||||
#define GPIO_AFRH8_MASK (0xf << GPIO_AFRH8_SHIFT)
|
||||
#define GPIO_AFRH9_SHIFT (4)
|
||||
#define GPIO_AFRH9_MASK (0xf << GPIO_AFRH9_SHIFT)
|
||||
#define GPIO_AFRH10_SHIFT (8)
|
||||
#define GPIO_AFRH10_MASK (0xf << GPIO_AFRH10_SHIFT)
|
||||
#define GPIO_AFRH11_SHIFT (12)
|
||||
#define GPIO_AFRH11_MASK (0xf << GPIO_AFRH11_SHIFT)
|
||||
#define GPIO_AFRH12_SHIFT (16)
|
||||
#define GPIO_AFRH12_MASK (0xf << GPIO_AFRH12_SHIFT)
|
||||
#define GPIO_AFRH13_SHIFT (20)
|
||||
#define GPIO_AFRH13_MASK (0xf << GPIO_AFRH13_SHIFT)
|
||||
#define GPIO_AFRH14_SHIFT (24)
|
||||
#define GPIO_AFRH14_MASK (0xf << GPIO_AFRH14_SHIFT)
|
||||
#define GPIO_AFRH15_SHIFT (28)
|
||||
#define GPIO_AFRH15_MASK (0xf << GPIO_AFRH15_SHIFT)
|
||||
|
||||
/* GPIO port bit reset register */
|
||||
|
||||
#define GPIO_BRR_RESET(n) (1 << (n))
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_GPIO_H */
|
||||
@@ -0,0 +1,188 @@
|
||||
/****************************************************************************************************
|
||||
* arch/arm/src/stm32/hardware/stm32g47xxx_memorymap.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_MEMORYMAP_H
|
||||
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_MEMORYMAP_H
|
||||
|
||||
/****************************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************************************/
|
||||
|
||||
/* STM32G47xxx Address Blocks ***********************************************************************/
|
||||
|
||||
#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */
|
||||
#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block */
|
||||
#define STM32_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */
|
||||
#define STM32_FMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/PSRMA/SRAM */
|
||||
/* 0x70000000-0x7fffffff: Reserved */
|
||||
#define STM32_FMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */
|
||||
#define STM32_QSPI_BANK1 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QUADSPI */
|
||||
|
||||
#define STM32_FMC_QSPI_BASE 0xa0000000 /* 0xa0000000-0xbfffffff: 256Mb FMC and QUADSPI registers */
|
||||
/* 0xc0000000-0xdfffffff: Reserved */
|
||||
#define STM32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */
|
||||
|
||||
#define STM32_REGION_MASK 0xf0000000
|
||||
#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE)
|
||||
|
||||
/* Code Base Addresses ******************************************************************************/
|
||||
|
||||
#define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x0007ffff: Aliased boot memory */
|
||||
/* 0x00080000-0x07ffffff: Reserved */
|
||||
#define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x807ffff: Up to 512Kb FLASH memory */
|
||||
/* 0x08080000-0xfffffff: Reserved */
|
||||
#define STM32_CCMRAM_BASE 0x10000000 /* 0x10000000-0x10007fff: 32Kb CCM data SRAM */
|
||||
/* 0x10008000-0x1ffeffff: Reserved */
|
||||
#define STM32_SYSMEM_BASE 0x1fff0000 /* 0x1fff0000-0x1fff6fff: 28Kb System memory */
|
||||
#define STM32_OTP_AREA_BASE 0x1fff7000 /* 0x1fff7000-0x1fff73ff: 1Kb OTP area */
|
||||
/* 0x1fff7400-0x1fff77ff: Reserved */
|
||||
#define STM32_OPTION_BASE 0x1fff7800 /* 0x1fff7800-0x1fff780f: 16 Option bytes */
|
||||
/* 0x1fff7810-0x1fff7fff: Reserved */
|
||||
#define STM32_SYSMEM_BASE2 0x1fff8000 /* 0x1fff8000-0x1fffefff: 28Kb System memory */
|
||||
/* 0x1ffff000-0x1ffff7ff: Reserved */
|
||||
#define STM32_OPTION_BASE2 0x1ffff800 /* 0x1ffff800-0x1ffff80f: 16 Option bytes */
|
||||
/* 0x1fff7810-0x1fff7fff: Reserved */
|
||||
|
||||
/* System Memory Addresses **************************************************************************/
|
||||
|
||||
#define STM32_PACKAGE_INFO 0x1fff7500 /* Package data register */
|
||||
#define STM32_SYSMEM_UID 0x1fff7590 /* The 96-bit unique device identifier */
|
||||
#define STM32_SYSMEM_FSIZE 0x1fff75e0 /* This bitfield indicates the size of
|
||||
* the device Flash memory expressed in
|
||||
* Kbytes. Example: 0x040 corresponds
|
||||
* to 64 Kbytes
|
||||
*/
|
||||
|
||||
/* Peripheral Base Addresses ************************************************************************/
|
||||
|
||||
#define STM32_APB1_BASE 0x40000000 /* 0x40000000-0x400097ff: APB1 */
|
||||
/* 0x40009800-0x4000ffff: Reserved */
|
||||
#define STM32_APB2_BASE 0x40010000 /* 0x40010000-0x400163ff: APB2 */
|
||||
/* 0x40016400-0x4001ffff: Reserved */
|
||||
#define STM32_AHB1_BASE 0x40020000 /* 0x40020000-0x400243ff: APB1 */
|
||||
/* 0x40024400-0x47ffffff: Reserved */
|
||||
#define STM32_AHB2_BASE 0x48000000 /* 0x48000000-0x50060bff: AHB2 */
|
||||
/* 0x50060c00-0x5fffffff: Reserved */
|
||||
|
||||
/* APB1 Base Addresses ******************************************************************************/
|
||||
|
||||
#define STM32_TIM2_BASE 0x40000000 /* 0x40000000-0x400003ff: TIM2 */
|
||||
#define STM32_TIM3_BASE 0x40000400 /* 0x40000400-0x400007ff: TIM3 */
|
||||
#define STM32_TIM4_BASE 0x40000800 /* 0x40000800-0x40000bff: TIM4 */
|
||||
#define STM32_TIM5_BASE 0x40000c00 /* 0x40000c00-0x40000fff: TIM5 */
|
||||
#define STM32_TIM6_BASE 0x40001000 /* 0x40001000-0x400013ff: TIM6 */
|
||||
#define STM32_TIM7_BASE 0x40001400 /* 0x40001400-0x400017ff: TIM7 */
|
||||
#define STM32_CRS_BASE 0x40002000 /* 0x40002000-0x400023ff: CRS */
|
||||
#define STM32_TAMP_BASE 0x40002400 /* 0x40002400-0x400027ff: TAMP */
|
||||
#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff: RTC */
|
||||
#define STM32_WWDG_BASE 0x40002c00 /* 0x40002c00-0x40002fff: WWDG */
|
||||
#define STM32_IWDG_BASE 0x40003000 /* 0x40003000-0x400033ff: IWDG */
|
||||
#define STM32_SPI2_BASE 0x40003800 /* 0x40003800-0x40003bff: SPI2 */
|
||||
#define STM32_SPI3_BASE 0x40003c00 /* 0x40003c00-0x40003fff: SPI3 */
|
||||
#define STM32_USART2_BASE 0x40004400 /* 0x40004400-0x400047ff: USART2 */
|
||||
#define STM32_USART3_BASE 0x40004800 /* 0x40004800-0x40004bff: USART3 */
|
||||
#define STM32_UART4_BASE 0x40004c00 /* 0x40004c00-0x40004fff: UART4 */
|
||||
#define STM32_UART5_BASE 0x40005000 /* 0x40005000-0x400053ff: UART5 */
|
||||
#define STM32_I2C1_BASE 0x40005400 /* 0x40005400-0x400057ff: I2C1 */
|
||||
#define STM32_I2C2_BASE 0x40005800 /* 0x40005800-0x40005bff: I2C2 */
|
||||
#define STM32_USB_BASE 0x40005c00 /* 0x40005c00-0x400063ff: USB and USB SRAM */
|
||||
#define STM32_FDCAN1_BASE 0x40006400 /* 0x40006400-0x400067ff: FDCAN1 */
|
||||
#define STM32_FDCAN2_BASE 0x40006800 /* 0x40006800-0x40006bff: FDCAN2 */
|
||||
#define STM32_FDCAN3_BASE 0x40006c00 /* 0x40006c00-0x40006fff: FDCAN3 */
|
||||
#define STM32_PWR_BASE 0x40007000 /* 0x40007000-0x400073ff: PWR */
|
||||
#define STM32_I2C3_BASE 0x40007800 /* 0x40007800-0x40007bff: I2C3 */
|
||||
#define STM32_LPTIM1_BASE 0x40007c00 /* 0x40007c00-0x40007fff: LPTIM1 */
|
||||
#define STM32_LPUART1_BASE 0x40008000 /* 0x40008000-0x400083ff: LPUART1 */
|
||||
#define STM32_I2C4_BASE 0x40008400 /* 0x40008400-0x400087ff: I2C4 */
|
||||
#define STM32_UCPD1_BASE 0x4000a000 /* 0x4000a000-0x4000a3ff: UCPD1 */
|
||||
#define STM32_SRAMCAN_BASE 0x4000a400 /* 0x4000a400-0x4000afff: FDCANs Message RAM */
|
||||
|
||||
/* APB2 Base Addresses ******************************************************************************/
|
||||
|
||||
#define STM32_SYSCFG_BASE 0x40010000 /* 0x40010000-0x40010029: SYSCFG */
|
||||
#define STM32_VREFBUF_BASE 0x40010030 /* 0x40010030-0x400101ff: VREFBUF */
|
||||
#define STM32_COMP1_BASE 0x40010200 /* 0x40010200-0x40010203: COMP1 */
|
||||
#define STM32_COMP2_BASE 0x40010204 /* 0x40010204-0x40010207: COMP2 */
|
||||
#define STM32_COMP3_BASE 0x40010208 /* 0x40010208-0x4001020b: COMP3 */
|
||||
#define STM32_COMP4_BASE 0x4001020c /* 0x4001020c-0x4001020f: COMP4 */
|
||||
#define STM32_COMP5_BASE 0x40010210 /* 0x40010210-0x40010213: COMP5 */
|
||||
#define STM32_COMP6_BASE 0x40010214 /* 0x40010214-0x40010217: COMP6 */
|
||||
#define STM32_COMP7_BASE 0x40010218 /* 0x40010218-0x400102ff: COMP7 */
|
||||
#define STM32_OPAMP_BASE 0x40010300 /* 0x40010300-0x40010303: OPAMP */
|
||||
#define STM32_OPAMP1_BASE 0x40010300 /* 0x40010300-0x40010303: OPAMP1 */
|
||||
#define STM32_OPAMP2_BASE 0x40010304 /* 0x40010304-0x40010307: OPAMP2 */
|
||||
#define STM32_OPAMP3_BASE 0x40010308 /* 0x40010308-0x4001030b: OPAMP3 */
|
||||
#define STM32_OPAMP4_BASE 0x4001030c /* 0x4001030c-0x4001030f: OPAMP4 */
|
||||
#define STM32_OPAMP5_BASE 0x40010310 /* 0x40010310-0x40010313: OPAMP5 */
|
||||
#define STM32_OPAMP6_BASE 0x40010314 /* 0x40010314-0x400103ff: OPAMP6 */
|
||||
#define STM32_EXTI_BASE 0x40010400 /* 0x40010400-0x400107ff: EXTI */
|
||||
#define STM32_TIM1_BASE 0x40012c00 /* 0x40012c00-0x40012fff: TIM1 */
|
||||
#define STM32_SPI1_BASE 0x40013000 /* 0x40013000-0x400133ff: SPI1 */
|
||||
#define STM32_TIM8_BASE 0x40013400 /* 0x40013400-0x400137ff: TIM8 */
|
||||
#define STM32_USART1_BASE 0x40013800 /* 0x40013800-0x40013bff: USART1 */
|
||||
#define STM32_SPI4_BASE 0x40013c00 /* 0x40013c00-0x40013fff: SPI4 */
|
||||
#define STM32_TIM15_BASE 0x40014000 /* 0x40014000-0x400143ff: TIM15 */
|
||||
#define STM32_TIM16_BASE 0x40014400 /* 0x40014400-0x400147ff: TIM16 */
|
||||
#define STM32_TIM17_BASE 0x40014800 /* 0x40014800-0x40014bff: TIM17 */
|
||||
#define STM32_TIM20_BASE 0x40015000 /* 0x40015000-0x400153ff: TIM20 */
|
||||
#define STM32_SAI1_BASE 0x40015400 /* 0x40015400-0x400157ff: SAI1 */
|
||||
#define STM32_HRTIM1_BASE 0x40016800 /* 0x40016800-0x400167ff: HRTIM1 */
|
||||
|
||||
/* AHB1 Base Addresses ******************************************************************************/
|
||||
|
||||
#define STM32_DMA1_BASE 0x40020000 /* 0x40020000-0x400203ff: DMA1 */
|
||||
#define STM32_DMA2_BASE 0x40020400 /* 0x40020400-0x400207ff: DMA2 */
|
||||
#define STM32_DMAMUX1_BASE 0x40020800 /* 0x40020800-0x40020bff: DMAMUX1 */
|
||||
#define STM32_CORDIC_BASE 0x40020c00 /* 0x40020c00-0x40020fff: CORDIC */
|
||||
#define STM32_RCC_BASE 0x40021000 /* 0x40021000-0x400213ff: Reset and Clock Control (RCC) */
|
||||
#define STM32_FMAC_BASE 0x40021400 /* 0x40021400-0x40021fff: FMAC */
|
||||
#define STM32_FLASHIF_BASE 0x40022000 /* 0x40022000-0x400223ff: Flash memory I/F */
|
||||
#define STM32_CRC_BASE 0x40023000 /* 0x40023000-0x400233ff: CRC */
|
||||
|
||||
/* AHB2 Base Addresses ******************************************************************************/
|
||||
|
||||
#define STM32_GPIOA_BASE 0x48000000 /* 0x48000000-0x480003ff: GPIO Port A */
|
||||
#define STM32_GPIOB_BASE 0x48000400 /* 0x48000400-0x480007ff: GPIO Port B */
|
||||
#define STM32_GPIOC_BASE 0x48000800 /* 0x48000800-0x48000bff: GPIO Port C */
|
||||
#define STM32_GPIOD_BASE 0x48000c00 /* 0X48000C00-0x48000fff: GPIO Port D */
|
||||
#define STM32_GPIOE_BASE 0x48001000 /* 0X48001000-0x480013ff: GPIO Port E */
|
||||
#define STM32_GPIOF_BASE 0x48001400 /* 0x48001400-0x480017ff: GPIO Port F */
|
||||
#define STM32_GPIOG_BASE 0x48001800 /* 0x48001800-0x48001bff: GPIO Port G */
|
||||
#define STM32_ADC12_BASE 0x50000000 /* 0x50000000-0x500003ff: ADC12 */
|
||||
#define STM32_ADC345_BASE 0x50000400 /* 0x50000400-0x500007ff: ADC345 */
|
||||
#define STM32_DAC_BASE 0x50000800 /* 0x50000800-0x50000bff: DAC */
|
||||
#define STM32_DAC1_BASE 0x50000800 /* 0x50000800-0x50000bff: DAC1 */
|
||||
#define STM32_DAC2_BASE 0x50000c00 /* 0x50000c00-0x50000fff: DAC2 */
|
||||
#define STM32_DAC3_BASE 0x50001000 /* 0x50001000-0x500013ff: DAC3 */
|
||||
#define STM32_DAC4_BASE 0x50001400 /* 0x50001400-0x500017ff: DAC4 */
|
||||
|
||||
/* Compatibility defines */
|
||||
|
||||
#define STM32_ADC34_BASE STM32_ADC345_BASE
|
||||
|
||||
/* Cortex-M4 Base Addresses *************************************************************************/
|
||||
|
||||
/* Other registers -- see armv7-m/nvic.h for standard Cortex-M4 registers in
|
||||
* this address range
|
||||
*/
|
||||
|
||||
#define STM32_DEBUGMCU_BASE 0xe0042000
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_MEMORYMAP_H */
|
||||
@@ -0,0 +1,46 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32/hardware/stm32g47xxx_pinmap.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_PINMAP_H
|
||||
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_PINMAP_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "stm32_gpio.h"
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_STM32G474C)
|
||||
# include "stm32g474cxx_pinmap.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32G474M)
|
||||
# include "stm32g474mxx_pinmap.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32G474Q)
|
||||
# include "stm32g474qxx_pinmap.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32G474R)
|
||||
# include "stm32g474rxx_pinmap.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32G474V)
|
||||
# include "stm32g474vxx_pinmap.h"
|
||||
#else
|
||||
# error "Unknown STM32G47xxx chip!"
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_PINMAP_H */
|
||||
@@ -0,0 +1,453 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32/hardware/stm32g47xxx_pwr.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_PWR_H
|
||||
#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_PWR_H
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32_PWR_CR1_OFFSET 0x0000 /* PWR Power Control Register 1 */
|
||||
#define STM32_PWR_CR2_OFFSET 0x0004 /* PWR Power Control Register 2 */
|
||||
#define STM32_PWR_CR3_OFFSET 0x0008 /* PWR Power Control Register 3 */
|
||||
#define STM32_PWR_CR4_OFFSET 0x000c /* PWR Power Control Register 4 */
|
||||
#define STM32_PWR_SR1_OFFSET 0x0010 /* PWR Power Status Register 1 */
|
||||
#define STM32_PWR_SR2_OFFSET 0x0014 /* PWR Power Status Register 2 */
|
||||
#define STM32_PWR_SCR_OFFSET 0x0018 /* PWR Power Status Reset Register */
|
||||
/* Offset 0x001c Reserved */
|
||||
#define STM32_PWR_PUCRA_OFFSET 0x0020 /* Power Port A Pull Up Control Register */
|
||||
#define STM32_PWR_PDCRA_OFFSET 0x0024 /* Power Port A Pull Down Control Register */
|
||||
#define STM32_PWR_PUCRB_OFFSET 0x0028 /* Power Port B Pull Up Control Register */
|
||||
#define STM32_PWR_PDCRB_OFFSET 0x002c /* Power Port B Pull Down Control Register */
|
||||
#define STM32_PWR_PUCRC_OFFSET 0x0030 /* Power Port C Pull Up Control Register */
|
||||
#define STM32_PWR_PDCRC_OFFSET 0x0034 /* Power Port C Pull Down Control Register */
|
||||
#define STM32_PWR_PUCRD_OFFSET 0x0038 /* Power Port D Pull Up Control Register */
|
||||
#define STM32_PWR_PDCRD_OFFSET 0x003c /* Power Port D Pull Down Control Register */
|
||||
#define STM32_PWR_PUCRE_OFFSET 0x0040 /* Power Port E Pull Up Control Register */
|
||||
#define STM32_PWR_PDCRE_OFFSET 0x0044 /* Power Port E Pull Down Control Register */
|
||||
#define STM32_PWR_PUCRF_OFFSET 0x0048 /* Power Port F Pull Up Control Register */
|
||||
#define STM32_PWR_PDCRF_OFFSET 0x004c /* Power Port F Pull Down Control Register */
|
||||
#define STM32_PWR_PUCRG_OFFSET 0x0050 /* Power Port G Pull Up Control Register */
|
||||
#define STM32_PWR_PDCRG_OFFSET 0x0054 /* Power Port G Pull Down Control Register */
|
||||
/* Offset 0x0058 Reserved */
|
||||
/* Offset 0x005C Reserved */
|
||||
/* Offset 0x0060 Reserved */
|
||||
/* Offset 0x0064 Reserved */
|
||||
/* Offset 0x0068 Reserved */
|
||||
/* Offset 0x006C Reserved */
|
||||
/* Offset 0x0070 Reserved */
|
||||
/* Offset 0x0074 Reserved */
|
||||
/* Offset 0x0078 Reserved */
|
||||
/* Offset 0x007C Reserved */
|
||||
#define STM32_PWR_CR5_OFFSET 0x0080 /* PWR Power Control Register 5 */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32_PWR_CR1 (STM32_PWR_BASE + STM32_PWR_CR1_OFFSET)
|
||||
#define STM32_PWR_CR2 (STM32_PWR_BASE + STM32_PWR_CR2_OFFSET)
|
||||
#define STM32_PWR_CR3 (STM32_PWR_BASE + STM32_PWR_CR3_OFFSET)
|
||||
#define STM32_PWR_CR4 (STM32_PWR_BASE + STM32_PWR_CR4_OFFSET)
|
||||
#define STM32_PWR_SR1 (STM32_PWR_BASE + STM32_PWR_SR1_OFFSET)
|
||||
#define STM32_PWR_SR2 (STM32_PWR_BASE + STM32_PWR_SR2_OFFSET)
|
||||
#define STM32_PWR_SCR (STM32_PWR_BASE + STM32_PWR_SCR_OFFSET)
|
||||
#define STM32_PWR_PUCRA (STM32_PWR_BASE + STM32_PWR_PUCRA_OFFSET)
|
||||
#define STM32_PWR_PDCRA (STM32_PWR_BASE + STM32_PWR_PDCRA_OFFSET)
|
||||
#define STM32_PWR_PUCRB (STM32_PWR_BASE + STM32_PWR_PUCRB_OFFSET)
|
||||
#define STM32_PWR_PDCRB (STM32_PWR_BASE + STM32_PWR_PDCRB_OFFSET)
|
||||
#define STM32_PWR_PUCRC (STM32_PWR_BASE + STM32_PWR_PUCRC_OFFSET)
|
||||
#define STM32_PWR_PDCRC (STM32_PWR_BASE + STM32_PWR_PDCRC_OFFSET)
|
||||
#define STM32_PWR_PUCRD (STM32_PWR_BASE + STM32_PWR_PUCRD_OFFSET)
|
||||
#define STM32_PWR_PDCRD (STM32_PWR_BASE + STM32_PWR_PDCRD_OFFSET)
|
||||
#define STM32_PWR_PUCRE (STM32_PWR_BASE + STM32_PWR_PUCRE_OFFSET)
|
||||
#define STM32_PWR_PDCRE (STM32_PWR_BASE + STM32_PWR_PDCRE_OFFSET)
|
||||
#define STM32_PWR_PUCRF (STM32_PWR_BASE + STM32_PWR_PUCRF_OFFSET)
|
||||
#define STM32_PWR_PDCRF (STM32_PWR_BASE + STM32_PWR_PDCRF_OFFSET)
|
||||
#define STM32_PWR_PUCRG (STM32_PWR_BASE + STM32_PWR_PUCRG_OFFSET)
|
||||
#define STM32_PWR_PDCRG (STM32_PWR_BASE + STM32_PWR_PDCRG_OFFSET)
|
||||
#define STM32_PWR_CR5 (STM32_PWR_BASE + STM32_PWR_CR5_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
/* PWR Power Control Register 1 (CR1) */
|
||||
|
||||
#define PWR_CR1_LPR_SHIFT (14) /* Low Power Run */
|
||||
#define PWR_CR1_LPR (0x1 << PWR_CR1_LPR_SHIFT)
|
||||
#define PWR_CR1_VOS_SHIFT (9) /* Voltage Scaling Range Selection */
|
||||
#define PWR_CR1_VOS_MASK (0x3 << PWR_CR1_VOS_SHIFT)
|
||||
# define PWR_CR1_VOS_RANGE_1 (0x1 << PWR_CR1_VOS_SHIFT)
|
||||
# define PWR_CR1_VOS_RANGE_2 (0x2 << PWR_CR1_VOS_SHIFT)
|
||||
#define PWR_CR1_DBP_SHIFT (8) /* Disable Backup Domain Write Protection */
|
||||
#define PWR_CR1_DBP (0x1 << PWR_CR1_DBP_SHIFT)
|
||||
#define PWR_CR1_LPMS_SHIFT (0) /* Low Power Mode Selection */
|
||||
#define PWR_CR1_LPMS_MASK (0x7 << PWR_CR1_LPMS_SHIFT)
|
||||
# define PWR_CR1_LPMS_STOP_0 (0x0 << PWR_CR1_LPMS_SHIFT) /* Stop 0 Mode */
|
||||
# define PWR_CR1_LPMS_STOP_1 (0x1 << PWR_CR1_LPMS_SHIFT) /* Stop 1 Mode */
|
||||
# define PWR_CR1_LPMS_STANDBY (0x3 << PWR_CR1_LPMS_SHIFT) /* Standby Mode */
|
||||
# define PWR_CR1_LPMS_SHUTDOWN (0x4 << PWR_CR1_LPMS_SHIFT) /* Shutdown Mode */
|
||||
|
||||
/* PWR Power Control Register 2 (CR2) */
|
||||
|
||||
#define PWR_CR2_PVDE (1 << 0) /* Power Voltage Detector Enable */
|
||||
#define PWR_CR2_PLS_SHIFT (1) /* Power Voltage Detector Level Selection */
|
||||
#define PWR_CR2_PLS_MASK (0x7 << PWR_CR2_PLS_SHIFT)
|
||||
# define PWR_CR2_PLS_0 (0x0 << PWR_CR2_PLS_SHIFT)
|
||||
# define PWR_CR2_PLS_1 (0x1 << PWR_CR2_PLS_SHIFT)
|
||||
# define PWR_CR2_PLS_2 (0x2 << PWR_CR2_PLS_SHIFT)
|
||||
# define PWR_CR2_PLS_3 (0x3 << PWR_CR2_PLS_SHIFT)
|
||||
# define PWR_CR2_PLS_4 (0x4 << PWR_CR2_PLS_SHIFT)
|
||||
# define PWR_CR2_PLS_5 (0x5 << PWR_CR2_PLS_SHIFT)
|
||||
# define PWR_CR2_PLS_6 (0x6 << PWR_CR2_PLS_SHIFT)
|
||||
# define PWR_CR2_PLS_7 (0x7 << PWR_CR2_PLS_SHIFT)
|
||||
#define PWR_CR2_PVMEN1 (1 << 6) /* Peripheral Voltage Monitoring 3 Enable (VDDA vs ADC or COMP Minimum Voltage) */
|
||||
#define PWR_CR2_PVMEN2 (1 << 7) /* Peripheral Voltage Monitoring 4 Enable (VDDA vs DAC 1Msps or 15Msps Minimum Voltage) */
|
||||
|
||||
/* PWR Power Control Register 3 (CR3) */
|
||||
|
||||
#define PWR_CR3_EWUP1 (1 << 0) /* Enable Wake Up Pin WKUP1 */
|
||||
#define PWR_CR3_EWUP2 (1 << 1) /* Enable Wake Up Pin WKUP2 */
|
||||
#define PWR_CR3_EWUP3 (1 << 2) /* Enable Wake Up Pin WKUP3 */
|
||||
#define PWR_CR3_EWUP4 (1 << 3) /* Enable Wake Up Pin WKUP4 */
|
||||
#define PWR_CR3_EWUP5 (1 << 4) /* Enable Wake Up Pin WKUP5 */
|
||||
#define PWR_CR3_RRS (1 << 8) /* SRAM2 Retention In Standby Mode */
|
||||
#define PWR_CR3_APC (1 << 10) /* Apply Pull Up And Pull Down Configuration */
|
||||
#define PWR_CR3_UCPD1_STDBY (1 << 13) /* USB Type C And Power Delivery Standby Mode */
|
||||
#define PWR_CR3_UCPD1_DBDIS (1 << 14) /* USB Type C And Power Delivery Dead Battery Disable */
|
||||
#define PWR_CR3_EIWUL (1 << 15) /* Enable Internal Wake Up Line */
|
||||
|
||||
/* PWR Power Control Register 4 (CR4) */
|
||||
|
||||
#define PWR_CR4_WP1 (1 << 0) /* Wake Up Pin WKUP1 polarity */
|
||||
#define PWR_CR4_WP2 (1 << 1) /* Wake Up Pin WKUP2 polarity */
|
||||
#define PWR_CR4_WP3 (1 << 2) /* Wake Up Pin WKUP3 polarity */
|
||||
#define PWR_CR4_WP4 (1 << 3) /* Wake Up Pin WKUP4 polarity */
|
||||
#define PWR_CR4_WP5 (1 << 4) /* Wake Up Pin WKUP5 polarity */
|
||||
#define PWR_CR4_VBE (1 << 8) /* VBAT Battery charging Enable */
|
||||
#define PWR_CR4_VBRS (1 << 9) /* VBAT Battery charging Resistor Selection */
|
||||
|
||||
/* PWR Power Status Register 1 (SR1) */
|
||||
|
||||
#define PWR_SR1_WUF_SHIFT (0) /* Wake Up Flags */
|
||||
#define PWR_SR1_WUF_MASK (0x1f << PWR_SR1_WUF_SHIFT)
|
||||
# define PWR_SR1_WUF1 (0x1 << PWR_SR1_WUF_SHIFT) /* Wake Up Flag 1 */
|
||||
# define PWR_SR1_WUF2 (0x2 << PWR_SR1_WUF_SHIFT) /* Wake Up Flag 2 */
|
||||
# define PWR_SR1_WUF3 (0x4 << PWR_SR1_WUF_SHIFT) /* Wake Up Flag 3 */
|
||||
# define PWR_SR1_WUF4 (0x8 << PWR_SR1_WUF_SHIFT) /* Wake Up Flag 4 */
|
||||
# define PWR_SR1_WUF5 (0x10 << PWR_SR1_WUF_SHIFT) /* Wake Up Flag 5 */
|
||||
#define PWR_SR1_SBF (1 << 8) /* Stand-By Flag */
|
||||
#define PWR_SR1_WUFI (1 << 15) /* Wake Up Flag Internal */
|
||||
|
||||
/* PWR Power Status Register 2 (SR2) */
|
||||
|
||||
#define PWR_SR2_FLASHRDY (1 << 7) /* Flash Ready Flag */
|
||||
#define PWR_SR2_REGLPS (1 << 8) /* Low-power Regulator Started */
|
||||
#define PWR_SR2_REGLPF (1 << 9) /* Low-power Regulator Flag */
|
||||
#define PWR_SR2_VOSF (1 << 10) /* Voltage Scaling Flag */
|
||||
#define PWR_SR2_PVDO (1 << 11) /* Power Voltage Detector Output */
|
||||
#define PWR_SR2_PVMO1 (1 << 12) /* Peripheral Voltage Monitoring Output 1 */
|
||||
#define PWR_SR2_PVMO2 (1 << 13) /* Peripheral Voltage Monitoring Output 2 */
|
||||
#define PWR_SR2_PVMO3 (1 << 14) /* Peripheral Voltage Monitoring Output 3 */
|
||||
#define PWR_SR2_PVMO4 (1 << 15) /* Peripheral Voltage Monitoring Output 4 */
|
||||
|
||||
/* PWR Power Status Reset Register (SCR) */
|
||||
|
||||
#define PWR_SCR_CWUF_SHIFT (0) /* Clear Wake Up Flags */
|
||||
#define PWR_SCR_CWUF (0x1f << PWR_SCR_CWUF_SHIFT)
|
||||
# define PWR_SCR_CWUF1 (0x1 << PWR_SCR_CWUF_SHIFT) /* Clear Wake Up Flag 1 */
|
||||
# define PWR_SCR_CWUF2 (0x2 << PWR_SCR_CWUF_SHIFT) /* Clear Wake Up Flag 2 */
|
||||
# define PWR_SCR_CWUF3 (0x4 << PWR_SCR_CWUF_SHIFT) /* Clear Wake Up Flag 3 */
|
||||
# define PWR_SCR_CWUF4 (0x8 << PWR_SCR_CWUF_SHIFT) /* Clear Wake Up Flag 4 */
|
||||
# define PWR_SCR_CWUF5 (0x10 << PWR_SCR_CWUF_SHIFT) /* Clear Wake Up Flag 5 */
|
||||
#define PWR_SCR_CSBF (1 << 8) /* Clear Standby Flag */
|
||||
|
||||
/* Power Port A Pull Up Control Register (PUCRA) */
|
||||
|
||||
#define PWR_PUCRA_PA0 (1 << 0) /* PA0 Pull Up Control Bit */
|
||||
#define PWR_PUCRA_PA1 (1 << 1) /* PA1 Pull Up Control Bit */
|
||||
#define PWR_PUCRA_PA2 (1 << 2) /* PA2 Pull Up Control Bit */
|
||||
#define PWR_PUCRA_PA3 (1 << 3) /* PA3 Pull Up Control Bit */
|
||||
#define PWR_PUCRA_PA4 (1 << 4) /* PA4 Pull Up Control Bit */
|
||||
#define PWR_PUCRA_PA5 (1 << 5) /* PA5 Pull Up Control Bit */
|
||||
#define PWR_PUCRA_PA6 (1 << 6) /* PA6 Pull Up Control Bit */
|
||||
#define PWR_PUCRA_PA7 (1 << 7) /* PA7 Pull Up Control Bit */
|
||||
#define PWR_PUCRA_PA8 (1 << 8) /* PA8 Pull Up Control Bit */
|
||||
#define PWR_PUCRA_PA9 (1 << 9) /* PA9 Pull Up Control Bit */
|
||||
#define PWR_PUCRA_PA10 (1 << 10) /* PA10 Pull Up Control Bit */
|
||||
#define PWR_PUCRA_PA11 (1 << 11) /* PA11 Pull Up Control Bit */
|
||||
#define PWR_PUCRA_PA12 (1 << 12) /* PA12 Pull Up Control Bit */
|
||||
#define PWR_PUCRA_PA13 (1 << 13) /* PA13 Pull Up Control Bit */
|
||||
#define PWR_PUCRA_PA14 (1 << 14) /* PA14 Pull Up Control Bit */
|
||||
#define PWR_PUCRA_PA15 (1 << 15) /* PA15 Pull Up Control Bit */
|
||||
|
||||
/* Power Port A Pull Down Control Register (PDCRA) */
|
||||
|
||||
#define PWR_PDCRA_PA0 (1 << 0) /* PA0 Pull Down Control Bit */
|
||||
#define PWR_PDCRA_PA1 (1 << 1) /* PA1 Pull Down Control Bit */
|
||||
#define PWR_PDCRA_PA2 (1 << 2) /* PA2 Pull Down Control Bit */
|
||||
#define PWR_PDCRA_PA3 (1 << 3) /* PA3 Pull Down Control Bit */
|
||||
#define PWR_PDCRA_PA4 (1 << 4) /* PA4 Pull Down Control Bit */
|
||||
#define PWR_PDCRA_PA5 (1 << 5) /* PA5 Pull Down Control Bit */
|
||||
#define PWR_PDCRA_PA6 (1 << 6) /* PA6 Pull Down Control Bit */
|
||||
#define PWR_PDCRA_PA7 (1 << 7) /* PA7 Pull Down Control Bit */
|
||||
#define PWR_PDCRA_PA8 (1 << 8) /* PA8 Pull Down Control Bit */
|
||||
#define PWR_PDCRA_PA9 (1 << 9) /* PA9 Pull Down Control Bit */
|
||||
#define PWR_PDCRA_PA10 (1 << 10) /* PA10 Pull Down Control Bit */
|
||||
#define PWR_PDCRA_PA11 (1 << 11) /* PA11 Pull Down Control Bit */
|
||||
#define PWR_PDCRA_PA12 (1 << 12) /* PA12 Pull Down Control Bit */
|
||||
#define PWR_PDCRA_PA13 (1 << 13) /* PA13 Pull Down Control Bit */
|
||||
#define PWR_PDCRA_PA14 (1 << 14) /* PA14 Pull Down Control Bit */
|
||||
#define PWR_PDCRA_PA15 (1 << 15) /* PA15 Pull Down Control Bit */
|
||||
|
||||
/* Power Port B Pull Up Control Register (PUCRB) */
|
||||
|
||||
#define PWR_PUCRB_PB0 (1 << 0) /* PB0 Pull Up Control Bit */
|
||||
#define PWR_PUCRB_PB1 (1 << 1) /* PB1 Pull Up Control Bit */
|
||||
#define PWR_PUCRB_PB2 (1 << 2) /* PB2 Pull Up Control Bit */
|
||||
#define PWR_PUCRB_PB3 (1 << 3) /* PB3 Pull Up Control Bit */
|
||||
#define PWR_PUCRB_PB4 (1 << 4) /* PB4 Pull Up Control Bit */
|
||||
#define PWR_PUCRB_PB5 (1 << 5) /* PB5 Pull Up Control Bit */
|
||||
#define PWR_PUCRB_PB6 (1 << 6) /* PB6 Pull Up Control Bit */
|
||||
#define PWR_PUCRB_PB7 (1 << 7) /* PB7 Pull Up Control Bit */
|
||||
#define PWR_PUCRB_PB8 (1 << 8) /* PB8 Pull Up Control Bit */
|
||||
#define PWR_PUCRB_PB9 (1 << 9) /* PB9 Pull Up Control Bit */
|
||||
#define PWR_PUCRB_PB10 (1 << 10) /* PB10 Pull Up Control Bit */
|
||||
#define PWR_PUCRB_PB11 (1 << 11) /* PB11 Pull Up Control Bit */
|
||||
#define PWR_PUCRB_PB12 (1 << 12) /* PB12 Pull Up Control Bit */
|
||||
#define PWR_PUCRB_PB13 (1 << 13) /* PB13 Pull Up Control Bit */
|
||||
#define PWR_PUCRB_PB14 (1 << 14) /* PB14 Pull Up Control Bit */
|
||||
#define PWR_PUCRB_PB15 (1 << 15) /* PB15 Pull Up Control Bit */
|
||||
|
||||
/* Power Port B Pull Down Control Register (PDCRB) */
|
||||
|
||||
#define PWR_PDCRB_PB0 (1 << 0) /* PB0 Pull Down Control Bit */
|
||||
#define PWR_PDCRB_PB1 (1 << 1) /* PB1 Pull Down Control Bit */
|
||||
#define PWR_PDCRB_PB2 (1 << 2) /* PB2 Pull Down Control Bit */
|
||||
#define PWR_PDCRB_PB3 (1 << 3) /* PB3 Pull Down Control Bit */
|
||||
#define PWR_PDCRB_PB4 (1 << 4) /* PB4 Pull Down Control Bit */
|
||||
#define PWR_PDCRB_PB5 (1 << 5) /* PB5 Pull Down Control Bit */
|
||||
#define PWR_PDCRB_PB6 (1 << 6) /* PB6 Pull Down Control Bit */
|
||||
#define PWR_PDCRB_PB7 (1 << 7) /* PB7 Pull Down Control Bit */
|
||||
#define PWR_PDCRB_PB8 (1 << 8) /* PB8 Pull Down Control Bit */
|
||||
#define PWR_PDCRB_PB9 (1 << 9) /* PB9 Pull Down Control Bit */
|
||||
#define PWR_PDCRB_PB10 (1 << 10) /* PB10 Pull Down Control Bit */
|
||||
#define PWR_PDCRB_PB11 (1 << 11) /* PB11 Pull Down Control Bit */
|
||||
#define PWR_PDCRB_PB12 (1 << 12) /* PB12 Pull Down Control Bit */
|
||||
#define PWR_PDCRB_PB13 (1 << 13) /* PB13 Pull Down Control Bit */
|
||||
#define PWR_PDCRB_PB14 (1 << 14) /* PB14 Pull Down Control Bit */
|
||||
#define PWR_PDCRB_PB15 (1 << 15) /* PB15 Pull Down Control Bit */
|
||||
|
||||
/* Power Port C Pull Up Control Register (PUCRC) */
|
||||
|
||||
#define PWR_PUCRC_PC0 (1 << 0) /* PC0 Pull Up Control Bit */
|
||||
#define PWR_PUCRC_PC1 (1 << 1) /* PC1 Pull Up Control Bit */
|
||||
#define PWR_PUCRC_PC2 (1 << 2) /* PC2 Pull Up Control Bit */
|
||||
#define PWR_PUCRC_PC3 (1 << 3) /* PC3 Pull Up Control Bit */
|
||||
#define PWR_PUCRC_PC4 (1 << 4) /* PC4 Pull Up Control Bit */
|
||||
#define PWR_PUCRC_PC5 (1 << 5) /* PC5 Pull Up Control Bit */
|
||||
#define PWR_PUCRC_PC6 (1 << 6) /* PC6 Pull Up Control Bit */
|
||||
#define PWR_PUCRC_PC7 (1 << 7) /* PC7 Pull Up Control Bit */
|
||||
#define PWR_PUCRC_PC8 (1 << 8) /* PC8 Pull Up Control Bit */
|
||||
#define PWR_PUCRC_PC9 (1 << 9) /* PC9 Pull Up Control Bit */
|
||||
#define PWR_PUCRC_PC10 (1 << 10) /* PC10 Pull Up Control Bit */
|
||||
#define PWR_PUCRC_PC11 (1 << 11) /* PC11 Pull Up Control Bit */
|
||||
#define PWR_PUCRC_PC12 (1 << 12) /* PC12 Pull Up Control Bit */
|
||||
#define PWR_PUCRC_PC13 (1 << 13) /* PC13 Pull Up Control Bit */
|
||||
#define PWR_PUCRC_PC14 (1 << 14) /* PC14 Pull Up Control Bit */
|
||||
#define PWR_PUCRC_PC15 (1 << 15) /* PC15 Pull Up Control Bit */
|
||||
|
||||
/* Power Port C Pull Down Control Register (PDCRC) */
|
||||
|
||||
#define PWR_PDCRC_PC0 (1 << 0) /* PC0 Pull Down Control Bit */
|
||||
#define PWR_PDCRC_PC1 (1 << 1) /* PC1 Pull Down Control Bit */
|
||||
#define PWR_PDCRC_PC2 (1 << 2) /* PC2 Pull Down Control Bit */
|
||||
#define PWR_PDCRC_PC3 (1 << 3) /* PC3 Pull Down Control Bit */
|
||||
#define PWR_PDCRC_PC4 (1 << 4) /* PC4 Pull Down Control Bit */
|
||||
#define PWR_PDCRC_PC5 (1 << 5) /* PC5 Pull Down Control Bit */
|
||||
#define PWR_PDCRC_PC6 (1 << 6) /* PC6 Pull Down Control Bit */
|
||||
#define PWR_PDCRC_PC7 (1 << 7) /* PC7 Pull Down Control Bit */
|
||||
#define PWR_PDCRC_PC8 (1 << 8) /* PC8 Pull Down Control Bit */
|
||||
#define PWR_PDCRC_PC9 (1 << 9) /* PC9 Pull Down Control Bit */
|
||||
#define PWR_PDCRC_PC10 (1 << 10) /* PC10 Pull Down Control Bit */
|
||||
#define PWR_PDCRC_PC11 (1 << 11) /* PC11 Pull Down Control Bit */
|
||||
#define PWR_PDCRC_PC12 (1 << 12) /* PC12 Pull Down Control Bit */
|
||||
#define PWR_PDCRC_PC13 (1 << 13) /* PC13 Pull Down Control Bit */
|
||||
#define PWR_PDCRC_PC14 (1 << 14) /* PC14 Pull Down Control Bit */
|
||||
#define PWR_PDCRC_PC15 (1 << 15) /* PC15 Pull Down Control Bit */
|
||||
|
||||
/* Power Port D Pull Up Control Register (PUCRD) */
|
||||
|
||||
#define PWR_PUCRD_PD0 (1 << 0) /* PD0 Pull Up Control Bit */
|
||||
#define PWR_PUCRD_PD1 (1 << 1) /* PD1 Pull Up Control Bit */
|
||||
#define PWR_PUCRD_PD2 (1 << 2) /* PD2 Pull Up Control Bit */
|
||||
#define PWR_PUCRD_PD3 (1 << 3) /* PD3 Pull Up Control Bit */
|
||||
#define PWR_PUCRD_PD4 (1 << 4) /* PD4 Pull Up Control Bit */
|
||||
#define PWR_PUCRD_PD5 (1 << 5) /* PD5 Pull Up Control Bit */
|
||||
#define PWR_PUCRD_PD6 (1 << 6) /* PD6 Pull Up Control Bit */
|
||||
#define PWR_PUCRD_PD7 (1 << 7) /* PD7 Pull Up Control Bit */
|
||||
#define PWR_PUCRD_PD8 (1 << 8) /* PD8 Pull Up Control Bit */
|
||||
#define PWR_PUCRD_PD9 (1 << 9) /* PD9 Pull Up Control Bit */
|
||||
#define PWR_PUCRD_PD10 (1 << 10) /* PD10 Pull Up Control Bit */
|
||||
#define PWR_PUCRD_PD11 (1 << 11) /* PD11 Pull Up Control Bit */
|
||||
#define PWR_PUCRD_PD12 (1 << 12) /* PD12 Pull Up Control Bit */
|
||||
#define PWR_PUCRD_PD13 (1 << 13) /* PD13 Pull Up Control Bit */
|
||||
#define PWR_PUCRD_PD14 (1 << 14) /* PD14 Pull Up Control Bit */
|
||||
#define PWR_PUCRD_PD15 (1 << 15) /* PD15 Pull Up Control Bit */
|
||||
|
||||
/* Power Port D Pull Down Control Register (PDCRD) */
|
||||
|
||||
#define PWR_PDCRD_PD0 (1 << 0) /* PD0 Pull Down Control Bit */
|
||||
#define PWR_PDCRD_PD1 (1 << 1) /* PD1 Pull Down Control Bit */
|
||||
#define PWR_PDCRD_PD2 (1 << 2) /* PD2 Pull Down Control Bit */
|
||||
#define PWR_PDCRD_PD3 (1 << 3) /* PD3 Pull Down Control Bit */
|
||||
#define PWR_PDCRD_PD4 (1 << 4) /* PD4 Pull Down Control Bit */
|
||||
#define PWR_PDCRD_PD5 (1 << 5) /* PD5 Pull Down Control Bit */
|
||||
#define PWR_PDCRD_PD6 (1 << 6) /* PD6 Pull Down Control Bit */
|
||||
#define PWR_PDCRD_PD7 (1 << 7) /* PD7 Pull Down Control Bit */
|
||||
#define PWR_PDCRD_PD8 (1 << 8) /* PD8 Pull Down Control Bit */
|
||||
#define PWR_PDCRD_PD9 (1 << 9) /* PD9 Pull Down Control Bit */
|
||||
#define PWR_PDCRD_PD10 (1 << 10) /* PD10 Pull Down Control Bit */
|
||||
#define PWR_PDCRD_PD11 (1 << 11) /* PD11 Pull Down Control Bit */
|
||||
#define PWR_PDCRD_PD12 (1 << 12) /* PD12 Pull Down Control Bit */
|
||||
#define PWR_PDCRD_PD13 (1 << 13) /* PD13 Pull Down Control Bit */
|
||||
#define PWR_PDCRD_PD14 (1 << 14) /* PD14 Pull Down Control Bit */
|
||||
#define PWR_PDCRD_PD15 (1 << 15) /* PD15 Pull Down Control Bit */
|
||||
|
||||
/* Power Port E Pull Up Control Register (PUCRE) */
|
||||
|
||||
#define PWR_PUCRE_PE0 (1 << 0) /* PE0 Pull Up Control Bit */
|
||||
#define PWR_PUCRE_PE1 (1 << 1) /* PE1 Pull Up Control Bit */
|
||||
#define PWR_PUCRE_PE2 (1 << 2) /* PE2 Pull Up Control Bit */
|
||||
#define PWR_PUCRE_PE3 (1 << 3) /* PE3 Pull Up Control Bit */
|
||||
#define PWR_PUCRE_PE4 (1 << 4) /* PE4 Pull Up Control Bit */
|
||||
#define PWR_PUCRE_PE5 (1 << 5) /* PE5 Pull Up Control Bit */
|
||||
#define PWR_PUCRE_PE6 (1 << 6) /* PE6 Pull Up Control Bit */
|
||||
#define PWR_PUCRE_PE7 (1 << 7) /* PE7 Pull Up Control Bit */
|
||||
#define PWR_PUCRE_PE8 (1 << 8) /* PE8 Pull Up Control Bit */
|
||||
#define PWR_PUCRE_PE9 (1 << 9) /* PE9 Pull Up Control Bit */
|
||||
#define PWR_PUCRE_PE10 (1 << 10) /* PE10 Pull Up Control Bit */
|
||||
#define PWR_PUCRE_PE11 (1 << 11) /* PE11 Pull Up Control Bit */
|
||||
#define PWR_PUCRE_PE12 (1 << 12) /* PE12 Pull Up Control Bit */
|
||||
#define PWR_PUCRE_PE13 (1 << 13) /* PE13 Pull Up Control Bit */
|
||||
#define PWR_PUCRE_PE14 (1 << 14) /* PE14 Pull Up Control Bit */
|
||||
#define PWR_PUCRE_PE15 (1 << 15) /* PE15 Pull Up Control Bit */
|
||||
|
||||
/* Power Port E Pull Down Control Register (PDCRE) */
|
||||
|
||||
#define PWR_PDCRE_PE0 (1 << 0) /* PE0 Pull Down Control Bit */
|
||||
#define PWR_PDCRE_PE1 (1 << 1) /* PE1 Pull Down Control Bit */
|
||||
#define PWR_PDCRE_PE2 (1 << 2) /* PE2 Pull Down Control Bit */
|
||||
#define PWR_PDCRE_PE3 (1 << 3) /* PE3 Pull Down Control Bit */
|
||||
#define PWR_PDCRE_PE4 (1 << 4) /* PE4 Pull Down Control Bit */
|
||||
#define PWR_PDCRE_PE5 (1 << 5) /* PE5 Pull Down Control Bit */
|
||||
#define PWR_PDCRE_PE6 (1 << 6) /* PE6 Pull Down Control Bit */
|
||||
#define PWR_PDCRE_PE7 (1 << 7) /* PE7 Pull Down Control Bit */
|
||||
#define PWR_PDCRE_PE8 (1 << 8) /* PE8 Pull Down Control Bit */
|
||||
#define PWR_PDCRE_PE9 (1 << 9) /* PE9 Pull Down Control Bit */
|
||||
#define PWR_PDCRE_PE10 (1 << 10) /* PE10 Pull Down Control Bit */
|
||||
#define PWR_PDCRE_PE11 (1 << 11) /* PE11 Pull Down Control Bit */
|
||||
#define PWR_PDCRE_PE12 (1 << 12) /* PE12 Pull Down Control Bit */
|
||||
#define PWR_PDCRE_PE13 (1 << 13) /* PE13 Pull Down Control Bit */
|
||||
#define PWR_PDCRE_PE14 (1 << 14) /* PE14 Pull Down Control Bit */
|
||||
#define PWR_PDCRE_PE15 (1 << 15) /* PE15 Pull Down Control Bit */
|
||||
|
||||
/* Power Port F Pull Up Control Register (PUCRF) */
|
||||
|
||||
#define PWR_PUCRF_PF0 (1 << 0) /* PF0 Pull Up Control Bit */
|
||||
#define PWR_PUCRF_PF1 (1 << 1) /* PF1 Pull Up Control Bit */
|
||||
#define PWR_PUCRF_PF2 (1 << 2) /* PF2 Pull Up Control Bit */
|
||||
#define PWR_PUCRF_PF3 (1 << 3) /* PF3 Pull Up Control Bit */
|
||||
#define PWR_PUCRF_PF4 (1 << 4) /* PF4 Pull Up Control Bit */
|
||||
#define PWR_PUCRF_PF5 (1 << 5) /* PF5 Pull Up Control Bit */
|
||||
#define PWR_PUCRF_PF6 (1 << 6) /* PF6 Pull Up Control Bit */
|
||||
#define PWR_PUCRF_PF7 (1 << 7) /* PF7 Pull Up Control Bit */
|
||||
#define PWR_PUCRF_PF8 (1 << 8) /* PF8 Pull Up Control Bit */
|
||||
#define PWR_PUCRF_PF9 (1 << 9) /* PF9 Pull Up Control Bit */
|
||||
#define PWR_PUCRF_PF10 (1 << 10) /* PF10 Pull Up Control Bit */
|
||||
#define PWR_PUCRF_PF11 (1 << 11) /* PF11 Pull Up Control Bit */
|
||||
#define PWR_PUCRF_PF12 (1 << 12) /* PF12 Pull Up Control Bit */
|
||||
#define PWR_PUCRF_PF13 (1 << 13) /* PF13 Pull Up Control Bit */
|
||||
#define PWR_PUCRF_PF14 (1 << 14) /* PF14 Pull Up Control Bit */
|
||||
#define PWR_PUCRF_PF15 (1 << 15) /* PF15 Pull Up Control Bit */
|
||||
|
||||
/* Power Port F Pull Down Control Register (PDCRF) */
|
||||
|
||||
#define PWR_PDCRF_PF0 (1 << 0) /* PF0 Pull Down Control Bit */
|
||||
#define PWR_PDCRF_PF1 (1 << 1) /* PF1 Pull Down Control Bit */
|
||||
#define PWR_PDCRF_PF2 (1 << 2) /* PF2 Pull Down Control Bit */
|
||||
#define PWR_PDCRF_PF3 (1 << 3) /* PF3 Pull Down Control Bit */
|
||||
#define PWR_PDCRF_PF4 (1 << 4) /* PF4 Pull Down Control Bit */
|
||||
#define PWR_PDCRF_PF5 (1 << 5) /* PF5 Pull Down Control Bit */
|
||||
#define PWR_PDCRF_PF6 (1 << 6) /* PF6 Pull Down Control Bit */
|
||||
#define PWR_PDCRF_PF7 (1 << 7) /* PF7 Pull Down Control Bit */
|
||||
#define PWR_PDCRF_PF8 (1 << 8) /* PF8 Pull Down Control Bit */
|
||||
#define PWR_PDCRF_PF9 (1 << 9) /* PF9 Pull Down Control Bit */
|
||||
#define PWR_PDCRF_PF10 (1 << 10) /* PF10 Pull Down Control Bit */
|
||||
#define PWR_PDCRF_PF11 (1 << 11) /* PF11 Pull Down Control Bit */
|
||||
#define PWR_PDCRF_PF12 (1 << 12) /* PF12 Pull Down Control Bit */
|
||||
#define PWR_PDCRF_PF13 (1 << 13) /* PF13 Pull Down Control Bit */
|
||||
#define PWR_PDCRF_PF14 (1 << 14) /* PF14 Pull Down Control Bit */
|
||||
#define PWR_PDCRF_PF15 (1 << 15) /* PF15 Pull Down Control Bit */
|
||||
|
||||
/* Power Port G Pull Up Control Register (PUCRG) */
|
||||
|
||||
#define PWR_PUCRG_PG0 (1 << 0) /* PG0 Pull Up Control Bit */
|
||||
#define PWR_PUCRG_PG1 (1 << 1) /* PG1 Pull Up Control Bit */
|
||||
#define PWR_PUCRG_PG2 (1 << 2) /* PG2 Pull Up Control Bit */
|
||||
#define PWR_PUCRG_PG3 (1 << 3) /* PG3 Pull Up Control Bit */
|
||||
#define PWR_PUCRG_PG4 (1 << 4) /* PG4 Pull Up Control Bit */
|
||||
#define PWR_PUCRG_PG5 (1 << 5) /* PG5 Pull Up Control Bit */
|
||||
#define PWR_PUCRG_PG6 (1 << 6) /* PG6 Pull Up Control Bit */
|
||||
#define PWR_PUCRG_PG7 (1 << 7) /* PG7 Pull Up Control Bit */
|
||||
#define PWR_PUCRG_PG8 (1 << 8) /* PG8 Pull Up Control Bit */
|
||||
#define PWR_PUCRG_PG9 (1 << 9) /* PG9 Pull Up Control Bit */
|
||||
#define PWR_PUCRG_PG10 (1 << 10) /* PG10 Pull Up Control Bit */
|
||||
#define PWR_PUCRG_PG11 (1 << 11) /* PG11 Pull Up Control Bit */
|
||||
#define PWR_PUCRG_PG12 (1 << 12) /* PG12 Pull Up Control Bit */
|
||||
#define PWR_PUCRG_PG13 (1 << 13) /* PG13 Pull Up Control Bit */
|
||||
#define PWR_PUCRG_PG14 (1 << 14) /* PG14 Pull Up Control Bit */
|
||||
#define PWR_PUCRG_PG15 (1 << 15) /* PG15 Pull Up Control Bit */
|
||||
|
||||
/* Power Port G Pull Down Control Register (PDCRG) */
|
||||
|
||||
#define PWR_PDCRG_PG0 (1 << 0) /* PG0 Pull Down Control Bit */
|
||||
#define PWR_PDCRG_PG1 (1 << 1) /* PG1 Pull Down Control Bit */
|
||||
#define PWR_PDCRG_PG2 (1 << 2) /* PG2 Pull Down Control Bit */
|
||||
#define PWR_PDCRG_PG3 (1 << 3) /* PG3 Pull Down Control Bit */
|
||||
#define PWR_PDCRG_PG4 (1 << 4) /* PG4 Pull Down Control Bit */
|
||||
#define PWR_PDCRG_PG5 (1 << 5) /* PG5 Pull Down Control Bit */
|
||||
#define PWR_PDCRG_PG6 (1 << 6) /* PG6 Pull Down Control Bit */
|
||||
#define PWR_PDCRG_PG7 (1 << 7) /* PG7 Pull Down Control Bit */
|
||||
#define PWR_PDCRG_PG8 (1 << 8) /* PG8 Pull Down Control Bit */
|
||||
#define PWR_PDCRG_PG9 (1 << 9) /* PG9 Pull Down Control Bit */
|
||||
#define PWR_PDCRG_PG10 (1 << 10) /* PG10 Pull Down Control Bit */
|
||||
#define PWR_PDCRG_PG11 (1 << 11) /* PG11 Pull Down Control Bit */
|
||||
#define PWR_PDCRG_PG12 (1 << 12) /* PG12 Pull Down Control Bit */
|
||||
#define PWR_PDCRG_PG13 (1 << 13) /* PG13 Pull Down Control Bit */
|
||||
#define PWR_PDCRG_PG14 (1 << 14) /* PG14 Pull Down Control Bit */
|
||||
#define PWR_PDCRG_PG15 (1 << 15) /* PG15 Pull Down Control Bit */
|
||||
|
||||
/* PWR power control register 5 (CR5) */
|
||||
|
||||
#define PWR_CR5_R1MODE_SHIFT (8)
|
||||
#define PWR_CR5_R1MODE (0x1 << PWR_CR5_R1MODE_SHIFT) /* Main Regulator Range 1 Mode */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_PWR_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,171 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32/hardware/stm32g47xxx_syscfg.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_SYSCFG_H
|
||||
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_SYSCFG_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
#ifdef CONFIG_STM32_STM32G47XX
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */
|
||||
#define STM32_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */
|
||||
#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */
|
||||
# define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */
|
||||
# define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */
|
||||
# define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */
|
||||
# define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */
|
||||
#define STM32_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG CCMSRAM control and status register */
|
||||
#define STM32_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */
|
||||
#define STM32_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG CCMSRAM write protection register */
|
||||
#define STM32_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG CCMSRAM key register */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32_SYSCFG_MEMRMP (STM32_SYSCFG_BASE + STM32_SYSCFG_MEMRMP_OFFSET)
|
||||
#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE + STM32_SYSCFG_CFGR1_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR_OFFSET(p))
|
||||
# define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR1_OFFSET)
|
||||
# define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR2_OFFSET)
|
||||
# define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR3_OFFSET)
|
||||
# define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR4_OFFSET)
|
||||
#define STM32_SYSCFG_SCSR (STM32_SYSCFG_BASE + STM32_SYSCFG_SCSR_OFFSET)
|
||||
#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_CFGR2_OFFSET)
|
||||
#define STM32_SYSCFG_SWPR (STM32_SYSCFG_BASE + STM32_SYSCFG_SWPR_OFFSET)
|
||||
#define STM32_SYSCFG_SKR (STM32_SYSCFG_BASE + STM32_SYSCFG_SKR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
/* Memory remap register (MEMRMP) */
|
||||
|
||||
#define SYSCFG_MEMRMP_MEM_MODE_SHIFT (0)
|
||||
#define SYSCFG_MEMRMP_MEM_MODE_MASK (0x7 << SYSCFG_MEMRMP_MEM_MODE_SHIFT)
|
||||
# define SYSCFG_MEMRMP_MEM_MODE_FLASH (0x0 << SYSCFG_MEMRMP_MEM_MODE_SHIFT) /* Main Flash memory mapped at 0x00000000 */
|
||||
# define SYSCFG_MEMRMP_MEM_MODE_SYSTEM (0x1 << SYSCFG_MEMRMP_MEM_MODE_SHIFT) /* System Flash memory mapped at 0x00000000 */
|
||||
# define SYSCFG_MEMRMP_MEM_MODE_FSMC (0x2 << SYSCFG_MEMRMP_MEM_MODE_SHIFT) /* FSMC memory */
|
||||
# define SYSCFG_MEMRMP_MEM_MODE_SRAM1 (0x3 << SYSCFG_MEMRMP_MEM_MODE_SHIFT) /* SRAM1 mapped at 0x00000000 */
|
||||
# define SYSCFG_MEMRMP_MEM_MODE_QSPI (0x4 << SYSCFG_MEMRMP_MEM_MODE_SHIFT) /* QUADSPI memory mapped at 0x00000000 */
|
||||
#define SYSCFG_MEMRMP_FB_MODE_MASK (1 << 8) /* User Flash Bank mode selection */
|
||||
|
||||
/* Configuration register 1 (CFGR1) */
|
||||
|
||||
#define SYSCFG_CFGR1_BOOSTEN_MASK (1 << 8) /* I/O analog switch voltage booster enable */
|
||||
#define SYSCFG_CFGR1_ANASWVDD_MASK (1 << 9) /* GPIO analog switch control voltage selection */
|
||||
#define SYSCFG_CFGR1_I2C_PB6_FMP_MASK (1 << 16) /* I2C PB6 fast mode plus */
|
||||
#define SYSCFG_CFGR1_I2C_PB7_FMP_MASK (1 << 17) /* I2C PB7 fast mode plus */
|
||||
#define SYSCFG_CFGR1_I2C_PB8_FMP_MASK (1 << 18) /* I2C PB8 fast mode plus */
|
||||
#define SYSCFG_CFGR1_I2C_PB9_FMP_MASK (1 << 19) /* I2C PB9 fast mode plus */
|
||||
#define SYSCFG_CFGR1_I2C1_FMP_MASK (1 << 20) /* I2C1 fast mode plus */
|
||||
#define SYSCFG_CFGR1_I2C2_FMP_MASK (1 << 21) /* I2C2 fast mode plus */
|
||||
#define SYSCFG_CFGR1_I2C3_FMP_MASK (1 << 22) /* I2C3 fast mode plus */
|
||||
#define SYSCFG_CFGR1_I2C4_FMP_MASK (1 << 23) /* I2C4 fast mode plus */
|
||||
#define SYSCFG_CFGR1_FPUIE_INVALIDOP (1 << 26) /* Invalid operation interrupt enable */
|
||||
#define SYSCFG_CFGR1_FPUIE_DIVZERO (1 << 27) /* Divide by zero interrupt enable */
|
||||
#define SYSCFG_CFGR1_FPUIE_UNDERFLOW (1 << 28) /* Underflow interrupt enable */
|
||||
#define SYSCFG_CFGR1_FPUIE_OVERFLOW (1 << 29) /* Overflow interrupt enable */
|
||||
#define SYSCFG_CFGR1_FPUIE_DENORMAL (1 << 30) /* Input denormal interrupt enable */
|
||||
#define SYSCFG_CFGR1_FPUIE_INEXACT (1 << 31) /* Inexact interrupt enable */
|
||||
|
||||
/* External interrupt (EXTI) configuration registers 1-4 (EXTICR1..4) */
|
||||
|
||||
#define SYSCFG_EXTICR_PORTA (0) /* 0000: PA[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTB (1) /* 0001: PB[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTC (2) /* 0010: PC[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTD (3) /* 0011: PD[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTE (4) /* 0100: PE[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTF (5) /* 0101: PF[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTG (6) /* 0110: PG[x] pin */
|
||||
|
||||
#define SYSCFG_EXTICR_PORT_MASK (15)
|
||||
#define SYSCFG_EXTICR_EXTI_SHIFT(g) (((g) & 3) << 2)
|
||||
#define SYSCFG_EXTICR_EXTI_MASK(g) (SYSCFG_EXTICR_PORT_MASK << (SYSCFG_EXTICR_EXTI_SHIFT(g)))
|
||||
|
||||
#define SYSCFG_EXTICR1_EXTI0_SHIFT (0) /* Bits 0-3: EXTI 0 configuration */
|
||||
#define SYSCFG_EXTICR1_EXTI0_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI0_SHIFT)
|
||||
#define SYSCFG_EXTICR1_EXTI1_SHIFT (4) /* Bits 4-7: EXTI 1 configuration */
|
||||
#define SYSCFG_EXTICR1_EXTI1_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI1_SHIFT)
|
||||
#define SYSCFG_EXTICR1_EXTI2_SHIFT (8) /* Bits 8-11: EXTI 2 configuration */
|
||||
#define SYSCFG_EXTICR1_EXTI2_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI2_SHIFT)
|
||||
#define SYSCFG_EXTICR1_EXTI3_SHIFT (12) /* Bits 12-15: EXTI 3 configuration */
|
||||
#define SYSCFG_EXTICR1_EXTI3_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI3_SHIFT)
|
||||
|
||||
#define SYSCFG_EXTICR2_EXTI4_SHIFT (0) /* Bits 0-3: EXTI 4 configuration */
|
||||
#define SYSCFG_EXTICR2_EXTI4_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI4_SHIFT)
|
||||
#define SYSCFG_EXTICR2_EXTI5_SHIFT (4) /* Bits 4-7: EXTI 5 configuration */
|
||||
#define SYSCFG_EXTICR2_EXTI5_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI5_SHIFT)
|
||||
#define SYSCFG_EXTICR2_EXTI6_SHIFT (8) /* Bits 8-11: EXTI 6 configuration */
|
||||
#define SYSCFG_EXTICR2_EXTI6_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI6_SHIFT)
|
||||
#define SYSCFG_EXTICR2_EXTI7_SHIFT (12) /* Bits 12-15: EXTI 7 configuration */
|
||||
#define SYSCFG_EXTICR2_EXTI7_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI7_SHIFT)
|
||||
|
||||
#define SYSCFG_EXTICR3_EXTI8_SHIFT (0) /* Bits 0-3: EXTI 8 configuration */
|
||||
#define SYSCFG_EXTICR3_EXTI8_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI8_SHIFT)
|
||||
#define SYSCFG_EXTICR3_EXTI9_SHIFT (4) /* Bits 4-7: EXTI 9 configuration */
|
||||
#define SYSCFG_EXTICR3_EXTI9_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI9_SHIFT)
|
||||
#define SYSCFG_EXTICR3_EXTI10_SHIFT (8) /* Bits 8-11: EXTI 10 configuration */
|
||||
#define SYSCFG_EXTICR3_EXTI10_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI10_SHIFT)
|
||||
#define SYSCFG_EXTICR3_EXTI11_SHIFT (12) /* Bits 12-15: EXTI 11 configuration */
|
||||
#define SYSCFG_EXTICR3_EXTI11_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI11_SHIFT)
|
||||
|
||||
#define SYSCFG_EXTICR4_EXTI12_SHIFT (0) /* Bits 0-3: EXTI 12 configuration */
|
||||
#define SYSCFG_EXTICR4_EXTI12_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI12_SHIFT)
|
||||
#define SYSCFG_EXTICR4_EXTI13_SHIFT (4) /* Bits 4-7: EXTI 13 configuration */
|
||||
#define SYSCFG_EXTICR4_EXTI13_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI13_SHIFT)
|
||||
#define SYSCFG_EXTICR4_EXTI14_SHIFT (8) /* Bits 8-11: EXTI 14 configuration */
|
||||
#define SYSCFG_EXTICR4_EXTI14_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI14_SHIFT)
|
||||
#define SYSCFG_EXTICR4_EXTI15_SHIFT (12) /* Bits 12-15: EXTI 15 configuration */
|
||||
#define SYSCFG_EXTICR4_EXTI15_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI15_SHIFT)
|
||||
|
||||
/* CCM SRAM control and status register (SCSR) */
|
||||
|
||||
#define SYSCFG_SCSR_CCMER (1 << 0) /* CCMSRAM Erase Request */
|
||||
#define SYSCFG_SCSR_CCMBSY (1 << 1) /* CCMSRAM Erase In Progress */
|
||||
|
||||
/* Configuration register 2 (CFGR2) */
|
||||
|
||||
#define SYSCFG_CFGR2_CLL (1 << 0) /* Cortex M4 lockup (HARDFAULT) output enable bit */
|
||||
#define SYSCFG_CFGR2_SPL (1 << 1) /* SRAM1 and CCM SRAM parity lock */
|
||||
#define SYSCFG_CFGR2_PVDL (1 << 2) /* PVD lock enable bit */
|
||||
#define SYSCFG_CFGR2_ECCL (1 << 3) /* ECC lock */
|
||||
#define SYSCFG_CFGR2_SPF (1 << 8) /* SRAM1 and CCM STAM parity error flag */
|
||||
|
||||
/* CCM SRAM write protection register (SWPR) */
|
||||
|
||||
#define SYSCFG_SWPR_PWP(n) (1 << (n)) /* CCMSRAM Write protection for page n=0..31 */
|
||||
|
||||
/* CCM SRAM key register (SKR) */
|
||||
|
||||
#define SYSCFG_SKR_KEY_SHIFT (0) /* CCMSRAM write protection key for software erase */
|
||||
#define SYSCFG_SKR_KEY_MASK (0xff << SYSCFG_SKR_KEY_SHIFT)
|
||||
# define SYSCFG_SKR_KEY(n) (((n) << SYSCFG_SKR_KEY_SHIFT) & SYSCFG_SKR_KEY_MASK)
|
||||
|
||||
#endif /* CONFIG_STM32_STM32G47XX */
|
||||
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_SYSCFG_H */
|
||||
@@ -0,0 +1,420 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32/hardware/stm32g47xxx_uart.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_UART_H
|
||||
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_UART_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32_USART_CR1_OFFSET 0x0000 /* Control Register 1 */
|
||||
#define STM32_USART_CR2_OFFSET 0x0004 /* Control Register 2 */
|
||||
#define STM32_USART_CR3_OFFSET 0x0008 /* Control Register 3 */
|
||||
#define STM32_USART_BRR_OFFSET 0x000c /* BAUD Rate Register */
|
||||
#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard Time and Prescaler Register */
|
||||
#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver Timeout Register */
|
||||
#define STM32_USART_RQR_OFFSET 0x0018 /* Request Register */
|
||||
#define STM32_USART_ISR_OFFSET 0x001c /* Interrupt and Status Register */
|
||||
#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt Flag Clear Register */
|
||||
#define STM32_USART_RDR_OFFSET 0x0024 /* Receive Data Register */
|
||||
#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit Data Register */
|
||||
#define STM32_USART_PRESC_OFFSET 0x002c /* Prescaler Register */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#if (STM32_NUSART > 0)
|
||||
# define STM32_USART1_CR1 (STM32_USART1_BASE + STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART1_CR2 (STM32_USART1_BASE + STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART1_CR3 (STM32_USART1_BASE + STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART1_BRR (STM32_USART1_BASE + STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART1_GTPR (STM32_USART1_BASE + STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART1_RTOR (STM32_USART1_BASE + STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_USART1_RQR (STM32_USART1_BASE + STM32_USART_RQR_OFFSET)
|
||||
# define STM32_USART1_ISR (STM32_USART1_BASE + STM32_USART_ISR_OFFSET)
|
||||
# define STM32_USART1_ICR (STM32_USART1_BASE + STM32_USART_ICR_OFFSET)
|
||||
# define STM32_USART1_RDR (STM32_USART1_BASE + STM32_USART_RDR_OFFSET)
|
||||
# define STM32_USART1_TDR (STM32_USART1_BASE + STM32_USART_TDR_OFFSET)
|
||||
# define STM32_USART1_PRESC (STM32_USART1_BASE + STM32_USART_PRESC_OFFSET)
|
||||
#endif
|
||||
|
||||
#if (STM32_NUSART > 1)
|
||||
# define STM32_USART2_CR1 (STM32_USART2_BASE + STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART2_CR2 (STM32_USART2_BASE + STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART2_CR3 (STM32_USART2_BASE + STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART2_BRR (STM32_USART2_BASE + STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART2_GTPR (STM32_USART2_BASE + STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART2_RTOR (STM32_USART2_BASE + STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_USART2_RQR (STM32_USART2_BASE + STM32_USART_RQR_OFFSET)
|
||||
# define STM32_USART2_ISR (STM32_USART2_BASE + STM32_USART_ISR_OFFSET)
|
||||
# define STM32_USART2_ICR (STM32_USART2_BASE + STM32_USART_ICR_OFFSET)
|
||||
# define STM32_USART2_RDR (STM32_USART2_BASE + STM32_USART_RDR_OFFSET)
|
||||
# define STM32_USART2_TDR (STM32_USART2_BASE + STM32_USART_TDR_OFFSET)
|
||||
# define STM32_USART2_PRESC (STM32_USART2_BASE + STM32_USART_PRESC_OFFSET)
|
||||
#endif
|
||||
|
||||
#if (STM32_NUSART > 2)
|
||||
# define STM32_USART3_CR1 (STM32_USART3_BASE + STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART3_CR2 (STM32_USART3_BASE + STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART3_CR3 (STM32_USART3_BASE + STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART3_BRR (STM32_USART3_BASE + STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART3_GTPR (STM32_USART3_BASE + STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART3_RTOR (STM32_USART3_BASE + STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_USART3_RQR (STM32_USART3_BASE + STM32_USART_RQR_OFFSET)
|
||||
# define STM32_USART3_ISR (STM32_USART3_BASE + STM32_USART_ISR_OFFSET)
|
||||
# define STM32_USART3_ICR (STM32_USART3_BASE + STM32_USART_ICR_OFFSET)
|
||||
# define STM32_USART3_RDR (STM32_USART3_BASE + STM32_USART_RDR_OFFSET)
|
||||
# define STM32_USART3_TDR (STM32_USART3_BASE + STM32_USART_TDR_OFFSET)
|
||||
# define STM32_USART3_PRESC (STM32_USART3_BASE + STM32_USART_PRESC_OFFSET)
|
||||
#endif
|
||||
|
||||
#if (STM32_NUSART > 3)
|
||||
# define STM32_UART4_CR1 (STM32_UART4_BASE + STM32_USART_CR1_OFFSET)
|
||||
# define STM32_UART4_CR2 (STM32_UART4_BASE + STM32_USART_CR2_OFFSET)
|
||||
# define STM32_UART4_CR3 (STM32_UART4_BASE + STM32_USART_CR3_OFFSET)
|
||||
# define STM32_UART4_BRR (STM32_UART4_BASE + STM32_USART_BRR_OFFSET)
|
||||
# define STM32_UART4_GTPR (STM32_UART4_BASE + STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_UART4_RTOR (STM32_UART4_BASE + STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_UART4_RQR (STM32_UART4_BASE + STM32_USART_RQR_OFFSET)
|
||||
# define STM32_UART4_ISR (STM32_UART4_BASE + STM32_USART_ISR_OFFSET)
|
||||
# define STM32_UART4_ICR (STM32_UART4_BASE + STM32_USART_ICR_OFFSET)
|
||||
# define STM32_UART4_RDR (STM32_UART4_BASE + STM32_USART_RDR_OFFSET)
|
||||
# define STM32_UART4_TDR (STM32_UART4_BASE + STM32_USART_TDR_OFFSET)
|
||||
# define STM32_UART4_PRESC (STM32_UART4_BASE + STM32_USART_PRESC_OFFSET)
|
||||
#endif
|
||||
|
||||
#if (STM32_NUSART > 4)
|
||||
# define STM32_UART5_CR1 (STM32_UART5_BASE + STM32_USART_CR1_OFFSET)
|
||||
# define STM32_UART5_CR2 (STM32_UART5_BASE + STM32_USART_CR2_OFFSET)
|
||||
# define STM32_UART5_CR3 (STM32_UART5_BASE + STM32_USART_CR3_OFFSET)
|
||||
# define STM32_UART5_BRR (STM32_UART5_BASE + STM32_USART_BRR_OFFSET)
|
||||
# define STM32_UART5_GTPR (STM32_UART5_BASE + STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_UART5_RTOR (STM32_UART5_BASE + STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_UART5_RQR (STM32_UART5_BASE + STM32_USART_RQR_OFFSET)
|
||||
# define STM32_UART5_ISR (STM32_UART5_BASE + STM32_USART_ISR_OFFSET)
|
||||
# define STM32_UART5_ICR (STM32_UART5_BASE + STM32_USART_ICR_OFFSET)
|
||||
# define STM32_UART5_RDR (STM32_UART5_BASE + STM32_USART_RDR_OFFSET)
|
||||
# define STM32_UART5_TDR (STM32_UART5_BASE + STM32_USART_TDR_OFFSET)
|
||||
# define STM32_UART5_PRESC (STM32_UART5_BASE + STM32_USART_PRESC_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
/* Control Register 1 */
|
||||
|
||||
#define USART_CR1_UE (1 << 0) /* Bit 0 - USART Enable */
|
||||
#define USART_CR1_UESM (1 << 1) /* Bit 1 - USART Enable in low power Mode */
|
||||
#define USART_CR1_RE (1 << 2) /* Bit 2 - Receiver Enable */
|
||||
#define USART_CR1_TE (1 << 3) /* Bit 3 - Transmitter Enable */
|
||||
#define USART_CR1_IDLEIE (1 << 4) /* Bit 4 - IDLE Interrupt Enable */
|
||||
#define USART_CR1_RXFNEIE (1 << 5) /* Bit 5 in FIFO mode - Rx FIFO Not Empty Interrupt Enable */
|
||||
#define USART_CR1_RXNEIE (1 << 5) /* Bit 5 in Non-FIFO mode - Rx Data Register Not Empty Interrupt Enable */
|
||||
#define USART_CR1_TCIE (1 << 6) /* Bit 6 - Transmission Complete Interrupt Enable */
|
||||
#define USART_CR1_TXFNFIE (1 << 7) /* Bit 7 in FIFO mode - Tx FIFO Not Full Interrupt Enable */
|
||||
#define USART_CR1_TXEIE (1 << 7) /* Bit 7 in Non-FIFO mode - Tx Data Register Empty Interrupt Enable */
|
||||
#define USART_CR1_PEIE (1 << 8) /* Bit 8 - PE Interrupt Enable */
|
||||
#define USART_CR1_PS (1 << 9) /* Bit 9 - Parity Selection */
|
||||
#define USART_CR1_PCE (1 << 10) /* Bit 10 - Parity Control Enable */
|
||||
#define USART_CR1_WAKE (1 << 11) /* Bit 11 - Receiver Wakeup method */
|
||||
#define USART_CR1_M0 (1 << 12) /* Bit 12 - Word length - Bit 0 */
|
||||
#define USART_CR1_MME (1 << 13) /* Bit 13 - Mute Mode Enable */
|
||||
#define USART_CR1_CMIE (1 << 14) /* Bit 14 - Character match interrupt enable */
|
||||
#define USART_CR1_OVER8 (1 << 15) /* Bit 15 - Oversampling by 8-bit or 16-bit mode */
|
||||
#define USART_CR1_DEDT_SHIFT (16) /* Bits 20:16 - Driver Enable Deassertion Time, in 1/16ths or 1/8ths bit time */
|
||||
#define USART_CR1_DEDT_MASK (0x1f << USART_CR1_DEDT_SHIFT)
|
||||
# define USART_CR1_DEDT(n) (((n) << USART_CR1_DEDT_SHIFT) & USART_CR1_DEDT_MASK)
|
||||
#define USART_CR1_DEAT_SHIFT (21) /* Bits 25:21 - Driver Enable Assertion Time, in 1/16ths or 1/8ths bit time */
|
||||
#define USART_CR1_DEAT_MASK (0x1f << USART_CR1_DEAT_SHIFT)
|
||||
# define USART_CR1_DEAT(n) (((n) << USART_CR1_DEAT_SHIFT) & USART_CR1_DEAT_MASK)
|
||||
#define USART_CR1_RTOIE (1 << 26) /* Bit 26 - Receive Time Out interrupt enable */
|
||||
#define USART_CR1_EOBIE (1 << 27) /* Bit 27 - End of Block interrupt enable */
|
||||
#define USART_CR1_M1 (1 << 28) /* Bit 28 - Word length - Bit 1 */
|
||||
#define USART_CR1_FIFOEN (1 << 29) /* Bit 29 - FIFO mode enable */
|
||||
#define USART_CR1_TXFEIE (1 << 30) /* Bit 30 - TXFIFO empty interrupt enable */
|
||||
#define USART_CR1_RXFFIE (1 << 31) /* Bit 31 - RXFIFO Full interrupt enable */
|
||||
|
||||
#define USART_CR1_M_MASK (USART_CR1_M0 | USART_CR1_M1)
|
||||
|
||||
#define USART_CR1_ALLINTS \
|
||||
(USART_CR1_IDLEIE | USART_CR1_RXNEIE | USART_CR1_TCIE | \
|
||||
USART_CR1_TXEIE | USART_CR1_PEIE | USART_CR1_CMIE | USART_CR1_RTOIE | \
|
||||
USART_CR1_EOBIE | USART_CR1_TXFEIE | USART_CR1_RXFFIE)
|
||||
|
||||
/* Control Register 2 */
|
||||
|
||||
#define USART_CR2_SLVEN (1 << 0) /* Synchronous Slave Mode Enable */
|
||||
#define USART_CR2_DIS_NSS (1 << 3) /* Slave Select (NSS) Pin Ignore For SPI */
|
||||
#define USART_CR2_ADDM7 (1 << 4) /* 7-Bit / 4-Bit Address Detection */
|
||||
#define USART_CR2_LBDL (1 << 5) /* LIN Break Detection Length */
|
||||
#define USART_CR2_LBDIE (1 << 6) /* LIN Break Detection Interrupt Enable */
|
||||
#define USART_CR2_LBCL (1 << 8) /* Last Bit Clock pulse */
|
||||
#define USART_CR2_CPHA (1 << 9) /* Clock Phase */
|
||||
#define USART_CR2_CPOL (1 << 10) /* Clock Polarity */
|
||||
#define USART_CR2_CLKEN (1 << 11) /* Clock Enable */
|
||||
#define USART_CR2_STOP_SHIFT (12) /* Stop Bit Mode */
|
||||
#define USART_CR2_STOP_MASK (0x3 << USART_CR2_STOP_SHIFT)
|
||||
# define USART_CR2_STOP1 (0x0 << USART_CR2_STOP_SHIFT) /* 1 Stop Bit */
|
||||
# define USART_CR2_STOP0p5 (0x1 << USART_CR2_STOP_SHIFT) /* 0.5 Stop Bit */
|
||||
# define USART_CR2_STOP2 (0x2 << USART_CR2_STOP_SHIFT) /* 2 Stop Bits */
|
||||
# define USART_CR2_STOP1p5 (0x3 << USART_CR2_STOP_SHIFT) /* 1.5 Stop Bits */
|
||||
#define USART_CR2_LINEN (1 << 14) /* LIN Mode Enable */
|
||||
#define USART_CR2_SWAP (1 << 15) /* Swap TX/RX Pins */
|
||||
#define USART_CR2_RXINV (1 << 16) /* RX Pin Active Level Inversion */
|
||||
#define USART_CR2_TXINV (1 << 17) /* TX Pin Active Level Inversion */
|
||||
#define USART_CR2_DATAINV (1 << 18) /* Binary Data Inversion */
|
||||
#define USART_CR2_MSBFIRST (1 << 19) /* MSB First */
|
||||
#define USART_CR2_ABREN (1 << 20) /* Auto BAUD-Rate Enable */
|
||||
#define USART_CR2_ABRMOD_SHIFT (21) /* Auto BAUD-Rate Detection Mode */
|
||||
#define USART_CR2_ABRMOD_MASK (0x3 << USART_CR2_ABRMOD_SHIFT)
|
||||
# define USART_CR2_ABRMOD_STARTBIT (0x0 << USART_CR2_ABRMOD_SHIFT) /* Measurement of Start Bit */
|
||||
# define USART_CR2_ABRMOD_FALLEDGE (0x1 << USART_CR2_ABRMOD_SHIFT) /* Falling Edge To Falling Edge */
|
||||
# define USART_CR2_ABRMOD_7F_FRAME (0x2 << USART_CR2_ABRMOD_SHIFT) /* 0X7F Frame Detection */
|
||||
# define USART_CR2_ABRMOD_55_FRAME (0x3 << USART_CR2_ABRMOD_SHIFT) /* 0X55 Frame Detection */
|
||||
#define USART_CR2_RTOEN (1 << 23) /* Receiver Time-Out Enable */
|
||||
#define USART_CR2_ADD8_SHIFT (24) /* Address of the USART Node */
|
||||
#define USART_CR2_ADD8_MASK (0xff << USART_CR2_ADD8_SHIFT)
|
||||
|
||||
/* Control Register 3 */
|
||||
|
||||
#define USART_CR3_EIE (1 << 0) /* Error Interrupt Enable */
|
||||
#define USART_CR3_IREN (1 << 1) /* IrDA Mode Enable */
|
||||
#define USART_CR3_IRLP (1 << 2) /* IrDA Low-Power */
|
||||
#define USART_CR3_HDSEL (1 << 3) /* Half-Duplex Selection */
|
||||
#define USART_CR3_NACK (1 << 4) /* SmartCard NACK Enable */
|
||||
#define USART_CR3_SCEN (1 << 5) /* SmartCard Mode Enable */
|
||||
#define USART_CR3_DMAR (1 << 6) /* DMA Enable Receiver */
|
||||
#define USART_CR3_DMAT (1 << 7) /* DMA Enable Transmitter */
|
||||
#define USART_CR3_RTSE (1 << 8) /* RTS Enable */
|
||||
#define USART_CR3_CTSE (1 << 9) /* CTS Enable */
|
||||
#define USART_CR3_CTSIE (1 << 10) /* CTS Interrupt Enable */
|
||||
#define USART_CR3_ONEBIT (1 << 11) /* One Sample Bit Method Enable */
|
||||
#define USART_CR3_OVRDIS (1 << 12) /* Overrun Disable */
|
||||
#define USART_CR3_DDRE (1 << 13) /* DMA Disable on Reception Error */
|
||||
#define USART_CR3_DEM (1 << 14) /* Driver Enable Mode */
|
||||
#define USART_CR3_DEP (1 << 15)
|
||||
#define USART_CR3_SCARCNT_SHIFT (17) /* SmartCard Auto-Retry Count */
|
||||
#define USART_CR3_SCARCNT_MASK (0x7 << USART_CR3_SCARCNT_SHIFT)
|
||||
# define USART_CR3_SCARCNT(n) (((n) << USART_CR3_SCARCNT_SHIFT) & USART_CR3_SCARCNT_MASK)
|
||||
#define USART_CR3_WUS_SHIFT (20) /* Wake Up From Low Power Mode Interrupt Flag Selection) */
|
||||
#define USART_CR3_WUS_MASK (0x3 << USART_CR3_WUS_SHIFT)
|
||||
# define USART_CR3_WUS_ADDR (0x0 << USART_CR3_WUS_SHIFT) /* On Address Match */
|
||||
# define USART_CR3_WUS_STARTBIT (0x2 << USART_CR3_WUS_SHIFT) /* On Start Bit Detection */
|
||||
# define USART_CR3_WUS_RXFNE (0x3 << USART_CR3_WUS_SHIFT) /* On RXNE/RXFNE */
|
||||
#define USART_CR3_WUFIE (1 << 22) /* Wake Up From Low Power Mode Interrupt Enable */
|
||||
#define USART_CR3_TXFTIE (1 << 23) /* Transmit FIFO Threshold Interrupt Enable */
|
||||
#define USART_CR3_TCBGTIE (1 << 24) /* Transmit Complete Before Guard Time Interrupt Enable */
|
||||
#define USART_CR3_RXFTCFG_SHIFT (25) /* Receive FIFO Threshold Configuration */
|
||||
#define USART_CR3_RXFTCFG_MASK (0x7 << USART_CR3_RXFTCFG_SHIFT)
|
||||
# define USART_CR3_RXFTCFG_1_8 (0x0 << USART_CR3_RXFTCFG_SHIFT) /* When Rx FIFO Reaches 1/8Th Depth */
|
||||
# define USART_CR3_RXFTCFG_1_4 (0x1 << USART_CR3_RXFTCFG_SHIFT) /* When Rx FIFO Reaches 1/4Th Depth */
|
||||
# define USART_CR3_RXFTCFG_1_2 (0x2 << USART_CR3_RXFTCFG_SHIFT) /* When Rx FIFO Reaches 1/2 Depth */
|
||||
# define USART_CR3_RXFTCFG_3_4 (0x3 << USART_CR3_RXFTCFG_SHIFT) /* When Rx FIFO Reaches 3/4Ths Depth */
|
||||
# define USART_CR3_RXFTCFG_7_8 (0x4 << USART_CR3_RXFTCFG_SHIFT) /* When Rx FIFO Reaches 7/8Ths Depth */
|
||||
# define USART_CR3_RXFTCFG_FULL (0x5 << USART_CR3_RXFTCFG_SHIFT) /* When Rx FIFO Is Full */
|
||||
#define USART_CR3_RXFTIE (1 << 28) /* Receive FIFO Threshold Interrupt Enable */
|
||||
#define USART_CR3_TXFTCFG_SHIFT (29) /* Transmit FIFO Threshold Configuration */
|
||||
#define USART_CR3_TXFTCFG_MASK (0x7 << USART_CR3_TXFTCFG_SHIFT)
|
||||
# define USART_CR3_TXFTCFG_1_8 (0x0 << USART_CR3_TXFTCFG_SHIFT) /* When Tx FIFO Reaches 1/8Th Depth */
|
||||
# define USART_CR3_TXFTCFG_1_4 (0x1 << USART_CR3_TXFTCFG_SHIFT) /* When Tx FIFO Reaches 1/4Th Depth */
|
||||
# define USART_CR3_TXFTCFG_1_2 (0x2 << USART_CR3_TXFTCFG_SHIFT) /* When Tx FIFO Reaches 1/2 Depth */
|
||||
# define USART_CR3_TXFTCFG_3_4 (0x3 << USART_CR3_TXFTCFG_SHIFT) /* When Tx FIFO Reaches 3/4Ths Depth */
|
||||
# define USART_CR3_TXFTCFG_7_8 (0x4 << USART_CR3_TXFTCFG_SHIFT) /* When Tx FIFO Reaches 7/8Ths Depth */
|
||||
# define USART_CR3_TXFTCFG_FULL (0x5 << USART_CR3_TXFTCFG_SHIFT) /* When Tx FIFO Is Full */
|
||||
|
||||
/* BAUD Rate Register */
|
||||
|
||||
/* Full BRR field */
|
||||
|
||||
#define USART_BRR_SHIFT (0)
|
||||
#define USART_BRR_MASK (0xffff << USART_BRR_BRR_SHIFT)
|
||||
# define USART_BRR(n) (((n) << USART_BRR_BRR_SHIFT) & USART_BRR_BRR_MASK)
|
||||
|
||||
/* Partial BRR field BRR[3:0]:
|
||||
*
|
||||
* When OVER8 = 0: BRR[3:0] = USARTDIV[3:0]
|
||||
*
|
||||
* When OVER8 = 1: BRR[2:0] = (USARTDIV[3:0] >> 1) and
|
||||
* BRR[3] must be kept cleared.
|
||||
*/
|
||||
|
||||
#define USART_BRR_0_3_SHIFT (0)
|
||||
#define USART_BRR_0_3_MASK (0xf << USART_BRR_0_3_SHIFT)
|
||||
# define USART_BRR_0_3(n) (((n) << USART_BRR_0_3_SHIFT) & USART_BRR_0_3_MASK)
|
||||
|
||||
/* Partial BRR field BRR[15:4]:
|
||||
* BRR[15:4] = USARTDIV[15:4]
|
||||
*/
|
||||
|
||||
#define USART_BRR_4_15_SHIFT (4)
|
||||
#define USART_BRR_4_15_MASK (0xfff << USART_BRR_4_15_SHIFT)
|
||||
# define USART_BRR_4_15(n) (((n) << USART_BRR_4_15_SHIFT) & USART_BRR_4_15_MASK)
|
||||
|
||||
/* Guard Time and Prescaler Register */
|
||||
|
||||
#define USART_GTPR_PSC_SHIFT (0) /* Prescaler Value */
|
||||
#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT)
|
||||
# define USART_GTPR_PSC(n) (((n) << USART_GTPR_PSC_SHIFT) & USART_GTPR_PSC_MASK)
|
||||
#define USART_GTPR_GT_SHIFT (8) /* Guard Time Value */
|
||||
#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT)
|
||||
# define USART_GTPR_GT(n) (((n) << USART_GTPR_GT_SHIFT) & USART_GTPR_GT_MASK)
|
||||
|
||||
/* Receiver Timeout Register */
|
||||
|
||||
#define USART_RTOR_RTO_SHIFT (0) /* Receiver Time Out Value */
|
||||
#define USART_RTOR_RTO_MASK (0xffffff << USART_RTOR_RTO_SHIFT)
|
||||
# define USART_RTOR_RTO(n) (((n) << USART_RTOR_RTO_SHIFT) & USART_RTOR_RTO_MASK)
|
||||
#define USART_RTOR_BLEN_SHIFT (24) /* Block Length */
|
||||
#define USART_RTOR_BLEN_MASK (0xff << USART_RTOR_BLEN_SHIFT)
|
||||
# define USART_RTOR_BLEN(n) (((n) << USART_RTOR_BLEN_SHIFT) & USART_RTOR_BLEN_MASK)
|
||||
|
||||
/* Request Register */
|
||||
|
||||
#define USART_RQR_ABRRQ (1 << 0) /* Bit 0 - Auto-Baud Rate Request */
|
||||
#define USART_RQR_SBKRQ (1 << 1) /* Bit 1 - Send Break Request */
|
||||
#define USART_RQR_MMRQ (1 << 2) /* Bit 2 - Mute Mode Request */
|
||||
#define USART_RQR_RXFRQ (1 << 3) /* Bit 3 - Receive Data Flush Request */
|
||||
#define USART_RQR_TXFRQ (1 << 4) /* Bit 4 - Transmit Data Flush Request */
|
||||
|
||||
/* Interrupt and Status Register */
|
||||
|
||||
#define USART_ISR_PE (1 << 0) /* Bit 0 - Parity Error */
|
||||
#define USART_ISR_FE (1 << 1) /* Bit 1 - Framing Error */
|
||||
#define USART_ISR_NE (1 << 2) /* Bit 2 - Noise Detected Flag */
|
||||
#define USART_ISR_ORE (1 << 3) /* Bit 3 - Overrun Error */
|
||||
#define USART_ISR_IDLE (1 << 4) /* Bit 4 - Idle Line Detected */
|
||||
#define USART_ISR_RXFNE (1 << 5) /* Bit 5 (When FIFO in use) - Rx FIFO Not Empty */
|
||||
#define USART_ISR_RXNE (1 << 5) /* Bit 5 (When FIFO not in use) - Rx Data Register Not Empty */
|
||||
#define USART_ISR_TC (1 << 6) /* Bit 6 - Transmission Complete */
|
||||
#define USART_ISR_TXFNF (1 << 7) /* Bit 7 (When FIFO in use) - Tx FIFO Not Full */
|
||||
#define USART_ISR_TXE (1 << 7) /* Bit 7 (When FIFO not in use) - Tx Data Register Empty */
|
||||
#define USART_ISR_LBDF (1 << 8) /* Bit 8 - LIN Break Detection Flag */
|
||||
#define USART_ISR_CTSIF (1 << 9) /* Bit 9 - CTS Interrupt Flag */
|
||||
#define USART_ISR_CTS (1 << 10) /* Bit 10 - CTS Flag */
|
||||
#define USART_ISR_RTOF (1 << 11) /* Bit 11 - Receiver Time Out */
|
||||
#define USART_ISR_EOBF (1 << 12) /* Bit 12 - End of Block Flag */
|
||||
#define USART_ISR_UDR (1 << 13) /* Bit 13 - SPI Slave Underrun Error Flag */
|
||||
#define USART_ISR_ABRE (1 << 14) /* Bit 14 - Auto BAUD Rate Error */
|
||||
#define USART_ISR_ABRF (1 << 15) /* Bit 15 - Auto BAUD Rate Flag */
|
||||
#define USART_ISR_BUSY (1 << 16) /* Bit 16 - Busy Flag */
|
||||
#define USART_ISR_CMF (1 << 17) /* Bit 17 - Character Match Flag */
|
||||
#define USART_ISR_SBKF (1 << 18) /* Bit 18 - Send Break Flag */
|
||||
#define USART_ISR_RWU (1 << 19) /* Bit 19 - Receive Wake Up From Mute Mode Flag */
|
||||
#define USART_ISR_WUF (1 << 20) /* Bit 20 - Wake Up From Stop Mode Flag */
|
||||
#define USART_ISR_TEACK (1 << 21) /* Bit 21 - Transmit Enable Acknowledge Flag */
|
||||
#define USART_ISR_REACK (1 << 22) /* Bit 22 - Receive Enable Acknowledge Flag */
|
||||
#define USART_ISR_TXFE (1 << 23) /* Bit 23 (When FIFO in use) - Tx FIFO Empty */
|
||||
#define USART_ISR_RXFF (1 << 24) /* Bit 24 (When FIFO in use) - Rx FIFO Full */
|
||||
#define USART_ISR_TCBGT (1 << 25) /* Bit 25 - Transmission Complete Before Guard Time Completion */
|
||||
#define USART_ISR_RXFT (1 << 26) /* Bit 26 (When FIFO in use) - Rx FIFO Threshold Flag */
|
||||
#define USART_ISR_TXFT (1 << 27) /* Bit 27 (When FIFO in use) - Tx FIFO Threshold Flag */
|
||||
|
||||
#define USART_ISR_ALLBITS (0x0fffffff)
|
||||
|
||||
/* Interrupt Flag Clear Register */
|
||||
|
||||
#define USART_ICR_PECF (1 << 0) /* Bit 0 - Parity Error Clear Flag */
|
||||
#define USART_ICR_FECF (1 << 1) /* Bit 1 - Framing Error Clear Flag */
|
||||
#define USART_ICR_NCF (1 << 2) /* Bit 2 - Noise detected Clear Flag */
|
||||
#define USART_ICR_ORECF (1 << 3) /* Bit 3 - OverRun Error Clear Flag */
|
||||
#define USART_ICR_IDLECF (1 << 4) /* Bit 4 - Idle Line Detected Clear Flag */
|
||||
#define USART_ICR_TXFECF (1 << 5) /* Bit 5 - Tx FIFO Empty Clear Flag */
|
||||
#define USART_ICR_TCCF (1 << 6) /* Bit 6 - Transmission Complete Clear Flag */
|
||||
#define USART_ICR_TCBGTCF (1 << 7) /* Bit 7 - Transmission Complete Before Guard Time Clear Flag */
|
||||
#define USART_ICR_LBDCF (1 << 8) /* Bit 8 - LIN Break Detection Clear Flag */
|
||||
#define USART_ICR_CTSCF (1 << 9) /* Bit 9 - CTS Interrupt Clear Flag */
|
||||
#define USART_ICR_RTOCF (1 << 11) /* Bit 11 - Receiver Timeout Clear Flag */
|
||||
#define USART_ICR_EOBCF (1 << 12) /* Bit 12 - End of Block Clear Flag */
|
||||
#define USART_ICR_UDRCF (1 << 13) /* Bit 13 - SPI Slave Underrun Clear Flag */
|
||||
#define USART_ICR_CMCF (1 << 17) /* Bit 17 - Character Match Clear Flag */
|
||||
#define USART_ICR_WUCF (1 << 20) /* Bit 20 - Wake Up From Stop Mode Clear Flag */
|
||||
|
||||
/* Receive Data Register */
|
||||
|
||||
#define USART_RDR_SHIFT (0)
|
||||
#define USART_RDR_MASK (0x1ff << USART_RDR_SHIFT)
|
||||
# define USART_RDR(n) (((n) << USART_RDR_SHIFT) & USART_RDR_MASK)
|
||||
|
||||
/* Transmit Data Register */
|
||||
|
||||
#define USART_TDR_SHIFT (0)
|
||||
#define USART_TDR_MASK (0x1ff << USART_TDR_SHIFT)
|
||||
# define USART_TDR(n) (((n) << USART_TDR_SHIFT) & USART_TDR_MASK)
|
||||
|
||||
/* Prescaler Register */
|
||||
|
||||
#define USART_PRESC_PRESCALER_SHIFT (0)
|
||||
#define USART_PRESC_PRESCALER_MASK (0xf << USART_PRESC_PRESCALER_SHIFT)
|
||||
#define USART_PRESC_PRESCALER_1 (0x0 << USART_PRESC_PRESCALER_SHIFT)
|
||||
#define USART_PRESC_PRESCALER_2 (0x1 << USART_PRESC_PRESCALER_SHIFT)
|
||||
#define USART_PRESC_PRESCALER_4 (0x2 << USART_PRESC_PRESCALER_SHIFT)
|
||||
#define USART_PRESC_PRESCALER_6 (0x3 << USART_PRESC_PRESCALER_SHIFT)
|
||||
#define USART_PRESC_PRESCALER_8 (0x4 << USART_PRESC_PRESCALER_SHIFT)
|
||||
#define USART_PRESC_PRESCALER_10 (0x5 << USART_PRESC_PRESCALER_SHIFT)
|
||||
#define USART_PRESC_PRESCALER_12 (0x6 << USART_PRESC_PRESCALER_SHIFT)
|
||||
#define USART_PRESC_PRESCALER_16 (0x7 << USART_PRESC_PRESCALER_SHIFT)
|
||||
#define USART_PRESC_PRESCALER_32 (0x8 << USART_PRESC_PRESCALER_SHIFT)
|
||||
#define USART_PRESC_PRESCALER_64 (0x9 << USART_PRESC_PRESCALER_SHIFT)
|
||||
#define USART_PRESC_PRESCALER_128 (0xa << USART_PRESC_PRESCALER_SHIFT)
|
||||
#define USART_PRESC_PRESCALER_256 (0xb << USART_PRESC_PRESCALER_SHIFT)
|
||||
|
||||
/* Compatibility definitions ************************************************/
|
||||
|
||||
/* Compatibility with F1/F2/F4 Status Register names */
|
||||
|
||||
#define STM32_USART_SR_OFFSET STM32_USART_ISR_OFFSET
|
||||
|
||||
#define USART_SR_PE USART_ISR_PE /* Parity Error */
|
||||
#define USART_SR_FE USART_ISR_FE /* Framing error */
|
||||
#define USART_SR_NE USART_ISR_NE /* Noise detected flag */
|
||||
#define USART_SR_ORE USART_ISR_ORE /* Overrun error */
|
||||
#define USART_SR_IDLE USART_ISR_IDLE /* IDLE line detected */
|
||||
#define USART_SR_RXNE USART_ISR_RXNE /* Read Data Register Not Empty */
|
||||
#define USART_SR_TC USART_ISR_TC /* Transmission Complete */
|
||||
#define USART_SR_TXE USART_ISR_TXE /* Transmit Data Register Empty */
|
||||
#define USART_SR_LBD USART_ISR_LBDF /* LIN Break Detection Flag */
|
||||
#define USART_SR_CTS USART_ISR_CTS /* CTS Flag */
|
||||
|
||||
#define USART_SR_ALLBITS USART_ISR_ALLBITS
|
||||
|
||||
#define USART_CR1_M USART_CR1_M0
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_UART_H */
|
||||
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user