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Rename arch/arm/src/imxrt/chip to arch/arm/src/imxrt/hardware.

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This commit is contained in:
Gregory Nutt
2019-05-24 18:25:44 -06:00
parent 50d18f9774
commit 159dbb9ff1
79 changed files with 56 additions and 26135 deletions
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arch/arm/src/imxrt/chip.h
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@@ -48,7 +48,7 @@
#include <arch/irq.h>
#include <arch/imxrt/chip.h>
#include "chip/imxrt_memorymap.h"
#include "hardware/imxrt_memorymap.h"
/* If the common ARMv7-M vector handling logic is used, then it expects the following
* definition in this file that provides the number of supported vectors external
arch/arm/src/imxrt/chip/imxrt_adc.h
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@@ -1,263 +0,0 @@
/************************************************************************************
* arch/arm/src/imxrt/chip/imxrt_adc.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_ADC_H
#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_ADC_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip/imxrt_memorymap.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register Offsets *****************************************************************/
#define IMXRT_ADC_HC0_OFFSET 0x0000 /* Control register for hardware triggers */
#define IMXRT_ADC_HC1_OFFSET 0x0004 /* Control register for hardware triggers */
#define IMXRT_ADC_HC2_OFFSET 0x0008 /* Control register for hardware triggers */
#define IMXRT_ADC_HC3_OFFSET 0x000c /* Control register for hardware triggers */
#define IMXRT_ADC_HC4_OFFSET 0x0010 /* Control register for hardware triggers */
#define IMXRT_ADC_HC5_OFFSET 0x0014 /* Control register for hardware triggers */
#define IMXRT_ADC_HC6_OFFSET 0x0018 /* Control register for hardware triggers */
#define IMXRT_ADC_HC7_OFFSET 0x001c /* Control register for hardware triggers */
#define IMXRT_ADC_HS_OFFSET 0x0020 /* Status register for HW triggers */
#define IMXRT_ADC_R0_OFFSET 0x0024 /* Data result register for HW triggers */
#define IMXRT_ADC_R1_OFFSET 0x0028 /* Data result register for HW triggers */
#define IMXRT_ADC_R2_OFFSET 0x002c /* Data result register for HW triggers */
#define IMXRT_ADC_R3_OFFSET 0x0030 /* Data result register for HW triggers */
#define IMXRT_ADC_R4_OFFSET 0x0034 /* Data result register for HW triggers */
#define IMXRT_ADC_R5_OFFSET 0x0038 /* Data result register for HW triggers */
#define IMXRT_ADC_R6_OFFSET 0x003c /* Data result register for HW triggers */
#define IMXRT_ADC_R7_OFFSET 0x0040 /* Data result register for HW triggers */
#define IMXRT_ADC_CFG_OFFSET 0x0044 /* Configuration register */
#define IMXRT_ADC_GC_OFFSET 0x0048 /* General control register */
#define IMXRT_ADC_GS_OFFSET 0x004c /* General status register */
#define IMXRT_ADC_CV_OFFSET 0x0050 /* Compare value register */
#define IMXRT_ADC_OFS_OFFSET 0x0054 /* Offset correction value register */
#define IMXRT_ADC_CAL_OFFSET 0x0058 /* Calibration value register */
/* Register addresses ***********************************************************************/
/* ADC1 Register Addresses */
#define IMXRT_ADC1_HC0 (IMXRT_ADC1_BASE + IMXRT_ADC_HC_OFFSET) /* ADC1 Control register for hardware triggers */
#define IMXRT_ADC1_HC1 (IMXRT_ADC1_BASE + IMXRT_ADC_HC1_OFFSET) /* ADC1 Control register for hardware triggers */
#define IMXRT_ADC1_HC2 (IMXRT_ADC1_BASE + IMXRT_ADC_HC2_OFFSET) /* ADC1 Control register for hardware triggers */
#define IMXRT_ADC1_HC3 (IMXRT_ADC1_BASE + IMXRT_ADC_HC3_OFFSET) /* ADC1 Control register for hardware triggers */
#define IMXRT_ADC1_HC4 (IMXRT_ADC1_BASE + IMXRT_ADC_HC4_OFFSET) /* ADC1 Control register for hardware triggers */
#define IMXRT_ADC1_HC5 (IMXRT_ADC1_BASE + IMXRT_ADC_HC5_OFFSET) /* ADC1 Control register for hardware triggers */
#define IMXRT_ADC1_HC6 (IMXRT_ADC1_BASE + IMXRT_ADC_HC6_OFFSET) /* ADC1 Control register for hardware triggers */
#define IMXRT_ADC1_HC7 (IMXRT_ADC1_BASE + IMXRT_ADC_HC7_OFFSET) /* ADC1 Control register for hardware triggers */
#define IMXRT_ADC1_HS (IMXRT_ADC1_BASE + IMXRT_ADC_HS_OFFSET) /* ADC1 Status register for HW triggers */
#define IMXRT_ADC1_R0 (IMXRT_ADC1_BASE + IMXRT_ADC_R0_OFFSET) /* ADC1 Data result register for HW triggers */
#define IMXRT_ADC1_R1 (IMXRT_ADC1_BASE + IMXRT_ADC_R1_OFFSET) /* ADC1 Data result register for HW triggers */
#define IMXRT_ADC1_R2 (IMXRT_ADC1_BASE + IMXRT_ADC_R2_OFFSET) /* ADC1 Data result register for HW triggers */
#define IMXRT_ADC1_R3 (IMXRT_ADC1_BASE + IMXRT_ADC_R3_OFFSET) /* ADC1 Data result register for HW triggers */
#define IMXRT_ADC1_R4 (IMXRT_ADC1_BASE + IMXRT_ADC_R4_OFFSET) /* ADC1 Data result register for HW triggers */
#define IMXRT_ADC1_R5 (IMXRT_ADC1_BASE + IMXRT_ADC_R5_OFFSET) /* ADC1 Data result register for HW triggers */
#define IMXRT_ADC1_R6 (IMXRT_ADC1_BASE + IMXRT_ADC_R6_OFFSET) /* ADC1 Data result register for HW triggers */
#define IMXRT_ADC1_R7 (IMXRT_ADC1_BASE + IMXRT_ADC_R7_OFFSET) /* ADC1 Data result register for HW triggers */
#define IMXRT_ADC1_CFG (IMXRT_ADC1_BASE + IMXRT_ADC_CFG_OFFSET) /* ADC1 Configuration register */
#define IMXRT_ADC1_GC (IMXRT_ADC1_BASE + IMXRT_ADC_GC_OFFSET) /* ADC1 General control register */
#define IMXRT_ADC1_GS (IMXRT_ADC1_BASE + IMXRT_ADC_GS_OFFSET) /* ADC1 General status register */
#define IMXRT_ADC1_CV (IMXRT_ADC1_BASE + IMXRT_ADC_CV_OFFSET) /* ADC1 Compare value register */
#define IMXRT_ADC1_OFS (IMXRT_ADC1_BASE + IMXRT_ADC_OFS_OFFSET) /* ADC1 Offset correction value register */
#define IMXRT_ADC1_CAL (IMXRT_ADC1_BASE + IMXRT_ADC_CAL_OFFSET) /* ADC1 Calibration value register */
/* ADC2 Register Addresses */
#define IMXRT_ADC2_HC0 (IMXRT_ADC2_BASE + IMXRT_ADC_HC_OFFSET) /* ADC2 Control register for hardware triggers */
#define IMXRT_ADC2_HC1 (IMXRT_ADC2_BASE + IMXRT_ADC_HC1_OFFSET) /* ADC2 Control register for hardware triggers */
#define IMXRT_ADC2_HC2 (IMXRT_ADC2_BASE + IMXRT_ADC_HC2_OFFSET) /* ADC2 Control register for hardware triggers */
#define IMXRT_ADC2_HC3 (IMXRT_ADC2_BASE + IMXRT_ADC_HC3_OFFSET) /* ADC2 Control register for hardware triggers */
#define IMXRT_ADC2_HC4 (IMXRT_ADC2_BASE + IMXRT_ADC_HC4_OFFSET) /* ADC2 Control register for hardware triggers */
#define IMXRT_ADC2_HC5 (IMXRT_ADC2_BASE + IMXRT_ADC_HC5_OFFSET) /* ADC2 Control register for hardware triggers */
#define IMXRT_ADC2_HC6 (IMXRT_ADC2_BASE + IMXRT_ADC_HC6_OFFSET) /* ADC2 Control register for hardware triggers */
#define IMXRT_ADC2_HC7 (IMXRT_ADC2_BASE + IMXRT_ADC_HC7_OFFSET) /* ADC2 Control register for hardware triggers */
#define IMXRT_ADC2_HS (IMXRT_ADC2_BASE + IMXRT_ADC_HS_OFFSET) /* ADC2 Status register for HW triggers */
#define IMXRT_ADC2_R0 (IMXRT_ADC2_BASE + IMXRT_ADC_R0_OFFSET) /* ADC2 Data result register for HW triggers */
#define IMXRT_ADC2_R1 (IMXRT_ADC2_BASE + IMXRT_ADC_R1_OFFSET) /* ADC2 Data result register for HW triggers */
#define IMXRT_ADC2_R2 (IMXRT_ADC2_BASE + IMXRT_ADC_R2_OFFSET) /* ADC2 Data result register for HW triggers */
#define IMXRT_ADC2_R3 (IMXRT_ADC2_BASE + IMXRT_ADC_R3_OFFSET) /* ADC2 Data result register for HW triggers */
#define IMXRT_ADC2_R4 (IMXRT_ADC2_BASE + IMXRT_ADC_R4_OFFSET) /* ADC2 Data result register for HW triggers */
#define IMXRT_ADC2_R5 (IMXRT_ADC2_BASE + IMXRT_ADC_R5_OFFSET) /* ADC2 Data result register for HW triggers */
#define IMXRT_ADC2_R6 (IMXRT_ADC2_BASE + IMXRT_ADC_R6_OFFSET) /* ADC2 Data result register for HW triggers */
#define IMXRT_ADC2_R7 (IMXRT_ADC2_BASE + IMXRT_ADC_R7_OFFSET) /* ADC2 Data result register for HW triggers */
#define IMXRT_ADC2_CFG (IMXRT_ADC2_BASE + IMXRT_ADC_CFG_OFFSET) /* ADC2 Configuration register */
#define IMXRT_ADC2_GC (IMXRT_ADC2_BASE + IMXRT_ADC_GC_OFFSET) /* ADC2 General control register */
#define IMXRT_ADC2_GS (IMXRT_ADC2_BASE + IMXRT_ADC_GS_OFFSET) /* ADC2 General status register */
#define IMXRT_ADC2_CV (IMXRT_ADC2_BASE + IMXRT_ADC_CV_OFFSET) /* ADC2 Compare value register */
#define IMXRT_ADC2_OFS (IMXRT_ADC2_BASE + IMXRT_ADC_OFS_OFFSET) /* ADC2 Offset correction value register */
#define IMXRT_ADC2_CAL (IMXRT_ADC2_BASE + IMXRT_ADC_CAL_OFFSET) /* ADC2 Calibration value register */
/* Register Bit Definitions *********************************************************/
/* Control register for hardware & SW triggers for n=0,1..7 */
#define ADC_HC_ADCH_SHIFT (0) /* Bits: 0-4 Input Channel Select */
#define ADC_HC_ADCH_MASK (31 << ADC_HC_ADCH_SHIFT)
# define ADC_HC_ADCH(n) ((uint32_t)(n) << ADC_HC_ADCH_SHIFT)
# define ADC_HC_ADCH_EXT_0 (0 << ADC_HC_ADCH_SHIFT) /* External channels 0 */
# define ADC_HC_ADCH_EXT_1 (1 << ADC_HC_ADCH_SHIFT) /* External channels 1 */
# define ADC_HC_ADCH_EXT_2 (2 << ADC_HC_ADCH_SHIFT) /* External channels 2 */
# define ADC_HC_ADCH_EXT_3 (3 << ADC_HC_ADCH_SHIFT) /* External channels 3 */
# define ADC_HC_ADCH_EXT_4 (4 << ADC_HC_ADCH_SHIFT) /* External channels 4 */
# define ADC_HC_ADCH_EXT_5 (5 << ADC_HC_ADCH_SHIFT) /* External channels 5 */
# define ADC_HC_ADCH_EXT_6 (6 << ADC_HC_ADCH_SHIFT) /* External channels 6 */
# define ADC_HC_ADCH_EXT_7 (7 << ADC_HC_ADCH_SHIFT) /* External channels 7 */
# define ADC_HC_ADCH_EXT_8 (8 << ADC_HC_ADCH_SHIFT) /* External channels 8 */
# define ADC_HC_ADCH_EXT_9 (9 << ADC_HC_ADCH_SHIFT) /* External channels 9 */
# define ADC_HC_ADCH_EXT_10 (10 << ADC_HC_ADCH_SHIFT) /* External channels 10 */
# define ADC_HC_ADCH_EXT_11 (11 << ADC_HC_ADCH_SHIFT) /* External channels 11 */
# define ADC_HC_ADCH_EXT_12 (12 << ADC_HC_ADCH_SHIFT) /* External channels 12 */
# define ADC_HC_ADCH_EXT_13 (13 << ADC_HC_ADCH_SHIFT) /* External channels 13 */
# define ADC_HC_ADCH_EXT_14 (14 << ADC_HC_ADCH_SHIFT) /* External channels 14 */
# define ADC_HC_ADCH_EXT_15 (15 << ADC_HC_ADCH_SHIFT) /* External channels 15 */
# define ADC_HC_ADCH_EXT_ADC_ETC (16 << ADC_HC_ADCH_SHIFT) /* External channel selection from ADC_ETC */
# define ADC_HC_ADCH_VREFSH (25 << ADC_HC_ADCH_SHIFT) /* internal channel, for ADC self-test, hard connected to VRH internally */
# define ADC_HC_ADCH_DIS (31 << ADC_HC_ADCH_SHIFT) /* */
/* Bits: 5-6 Reserved */
#define ADC_HC_AIEN (1 << 7) /* Bit: 7 Conversion Complete Interrupt Enable/Disable Control */
/* Bits: 8-31 Reserved */
/* Status register for HW triggers */
#define ADC_HS_COCO0 (1 << 0) /* Bit: 0 Conversion Complete Flag */
/* Bits: 1-31 Reserved */
/* Data result register for HW & SW triggers */
#define ADC_R_CDATA_SHIFT (0) /* Bits: 0-11 Data (result of an ADC conversion) */
#define ADC_R_CDATA_MASK (0xfff << ADC_R_CDATA_SHIFT)
/* Configuration register */
#define ADC_CFG_ADICLK_SHIFT (0) /* Bits: 0-1 Input Clock Select */
#define ADC_CFG_ADICLK_MASK (3 << ADC_CFG_ADICLK_SHIFT)
# define ADC_CFG_ADICLK(n) ((uint32_t)(n) << ADC_CFG_ADICLK_SHIFT)
# define ADC_CFG_ADICLK_IPG (0 << ADC_CFG_ADICLK_SHIFT) /* IPG clock */
# define ADC_CFG_ADICLK_IPGDIV2 (1 << ADC_CFG_ADICLK_SHIFT) /* IPG clock divided by 2 */
# define ADC_CFG_ADICLK_ADACK (3 << ADC_CFG_ADICLK_SHIFT) /* Asynchronous clock (ADACK) */
#define ADC_CFG_MODE_SHIFT (2) /* Bits: 2-3 Conversion Mode Selection */
#define ADC_CFG_MODE_MASK (3 << ADC_CFG_MODE_SHIFT)
# define ADC_CFG_MODE(n) ((uint32_t)(n) << ADC_CFG_MODE_SHIFT)
# define ADC_CFG_MODE_8BIT (0 << ADC_CFG_MODE_SHIFT) /* 8-bit conversion */
# define ADC_CFG_MODE_10BIT (1 << ADC_CFG_MODE_SHIFT) /* 10-bit conversion */
# define ADC_CFG_MODE_12BIT (2 << ADC_CFG_MODE_SHIFT) /* 12-bit conversion */
#define ADC_CFG_ADLSMP (1 << 4) /* Bit: 4 Long Sample Time Configuration */
#define ADC_CFG_ADIV_SHIFT (5) /* Bits: 5-6 Clock Divide Select */
#define ADC_CFG_ADIV_MASK (3 << ADC_CFG_ADIV_SHIFT)
# define ADC_CFG_ADIV(n) ((uint32_t)(n) << ADC_CFG_ADIV_SHIFT)
# define ADC_CFG_ADIV_DIV1 (0 << ADC_CFG_ADIV_SHIFT) /* Input clock */
# define ADC_CFG_ADIV_DIV2 (1 << ADC_CFG_ADIV_SHIFT) /* Input clock / 2 */
# define ADC_CFG_ADIV_DIV4 (2 << ADC_CFG_ADIV_SHIFT) /* Input clock / 4 */
# define ADC_CFG_ADIV_DIV8 (3 << ADC_CFG_ADIV_SHIFT) /* Input clock / 8 */
#define ADC_CFG_ADLPC (1 << 7) /* Bit: 7 Low-Power Configuration */
#define ADC_CFG_ADSTS_SHIFT (8) /* Bits: 8-9 Defines the sample time duration. */
#define ADC_CFG_ADSTS_MASK (3 << ADC_CFG_ADSTS_SHIFT)
# define ADC_CFG_ADSTS(n) ((uint32_t)(n) << ADC_CFG_ADSTS_SHIFT)
# define ADC_CFG_ADSTS_2_12 (0 << ADC_CFG_ADSTS_SHIFT) /* Sample period (ADC clocks) = 2 if ADLSMP=0b, 12 if ADLSMP=1b */
# define ADC_CFG_ADSTS_4_16 (1 << ADC_CFG_ADSTS_SHIFT) /* Sample period (ADC clocks) = 4 if ADLSMP=0b, 16 if ADLSMP=1b */
# define ADC_CFG_ADSTS_6_20 (2 << ADC_CFG_ADSTS_SHIFT) /* Sample period (ADC clocks) = 6 if ADLSMP=0b, 20 if ADLSMP=1b */
# define ADC_CFG_ADSTS_8_24 (3 << ADC_CFG_ADSTS_SHIFT) /* Sample period (ADC clocks) = 8 if ADLSMP=0b, 24 if ADLSMP=1b */
#define ADC_CFG_ADHSC (1 << 10) /* Bit: 10 High Speed Configuration*/
#define ADC_CFG_REFSEL_SHIFT (11) /* Bits: 11-12 Voltage Reference Selection */
#define ADC_CFG_REFSEL_MASK (3 << ADC_CFG_REFSEL_SHIFT)
# define ADC_CFG_REFSEL(n) ((uint32_t)(n) << ADC_CFG_REFSEL_SHIFT)
# define ADC_CFG_REFSEL_VREF (0 << ADC_CFG_REFSEL_SHIFT) /* Selects VREFH/VREFL as reference voltage. */
#define ADC_CFG_ADTRG (1 << 13) /* Bit: 13 Conversion Trigger Select */
# define ADC_CFG_ADTRG_SW (0 << 13) /* SW trigger selected */
# define ADC_CFG_ADTRG_HW (1 << 13) /* HW trigger selected */
#define ADC_CFG_AVGS_SHIFT (14) /* Bits: 14-15 Hardware Average select */
#define ADC_CFG_AVGS_MASK (3 << ADC_CFG_AVGS_SHIFT)
# define ADC_CFG_AVGS(n) ((uint32_t)(n) << ADC_CFG_AVGS_SHIFT)
# define ADC_CFG_AVGS_4SMPL (0 << ADC_CFG_AVGS_SHIFT) /* 4 samples averaged */
# define ADC_CFG_AVGS_8SMPL (1 << ADC_CFG_AVGS_SHIFT) /* 8 samples averaged */
# define ADC_CFG_AVGS_16SMPL (2 << ADC_CFG_AVGS_SHIFT) /* 16 samples averaged */
# define ADC_CFG_AVGS_32SMPL (3 << ADC_CFG_AVGS_SHIFT) /* 32 samples averaged */
#define ADC_CFG_OVWREN (1 << 16) /* Bit: 16 Data Overwrite Enable */
/* Bits: 17-31 Reserved */
/* General control register */
#define ADC_GC_ADACKEN (1 << 0) /* Bit: 0 Asynchronous clock output enable */
#define ADC_GC_DMAEN (1 << 1) /* Bit: 1 DMA Enable */
#define ADC_GC_ACREN (1 << 2) /* Bit: 2 Compare Function Range Enable */
#define ADC_GC_ACFGT (1 << 3) /* Bit: 3 Compare Function Greater Than Enable */
#define ADC_GC_ACFE (1 << 4) /* Bit: 4 Compare Function Enable */
#define ADC_GC_AVGE (1 << 5) /* Bit: 5 Hardware average enable */
#define ADC_GC_ADCO (1 << 6) /* Bit: 6 Continuous Conversion Enable */
#define ADC_GC_CAL (1 << 7) /* Bit: 7 Calibration */
/* Bits: 8-31 Reserved */
/* General status register */
#define ADC_GS_ADACT (1 << 0) /* Bit: 0 Conversion Active */
#define ADC_GS_CALF (1 << 1) /* Bit: 1 Calibration Failed Flag */
#define ADC_GS_AWKST (1 << 2) /* Bit: 2 Asynchronous wakeup interrupt status */
/* Bits: 3-31 Reserved */
/* Compare value register */
#define ADC_CV_CV1_SHIFT (0) /* Bits: 0-11 Compare Value 1 */
#define ADC_CV_CV1_MASK (0xfff << ADC_CV_CV1_SHIFT)
# define ADC_CV_CV1(n) ((uint32_t)(n) << ADC_CV_CV1_SHIFT)
/* Bits: 12-15 Reserved */
#define ADC_CV_CV2_SHIFT (16) /* Bits: 16-27 Compare Value 2 */
#define ADC_CV_CV2_MASK (0xfff << ADC_CV_CV2_SHIFT)
# define ADC_CV_CV2(n) ((uint32_t)(n) << ADC_CV_CV2_SHIFT)
/* Bits: 28-31 Reserved */
/* Offset correction value register */
#define ADC_OFS_OFS_SHIFT (0) /* Bits: 0-11 Offset value */
#define ADC_OFS_OFS_MASK (0xfff << ADC_OFS_OFS_SHIFT)
# define ADC_OFS_OFS(n) ((uint32_t)(n) << ADC_OFS_OFS_SHIFT)
#define ADC_OFS_SIGN (1 << 12) /* Bit: 12 Sign bit */
/* Bits: 13-31 Reserved */
/* Calibration value register */
#define ADC_CAL_CAL_CODE_SHIFT (0) /* Bits: 0-3 Calibration Result Value */
#define ADC_CAL_CAL_CODE_MASK (0xf << ADC_CAL_CAL_CODE_SHIFT)
/* Bits: 4-31 Reserved */
#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_ADC_H */
arch/arm/src/imxrt/chip/imxrt_ccm.h
-57
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@@ -1,57 +0,0 @@
/*****************************************************************************
* arch/arm/src/imxrt/imxrt_ccm.h
*
* Copyright (C) 2018-2019 Gregory Nutt. All rights reserved.
* Authors: Janne Rosberg <janne@offcode.fi>
* David Sidrane <david_s5@nscdg.com>
* Dave Marples <dave@marples.net>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_CCM_H
#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_CCM_H
/*****************************************************************************
* Included Files
*****************************************************************************/
#include <nuttx/config.h>
#include "chip/imxrt_memorymap.h"
#if defined(CONFIG_ARCH_FAMILY_IMXRT102x)
# include "chip/rt102x/imxrt102x_ccm.h"
#elif defined(CONFIG_ARCH_FAMILY_IMXRT105x)
# include "chip/rt105x/imxrt105x_ccm.h"
#elif defined(CONFIG_ARCH_FAMILY_IMXRT106x)
# include "chip/rt106x/imxrt106x_ccm.h"
#else
# error Unrecognized i.MX RT architecture
#endif
#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_CCM_H */
arch/arm/src/imxrt/chip/imxrt_daisy.h
-62
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@@ -1,62 +0,0 @@
/************************************************************************************
* arch/arm/src/imxrt/chip/imxrt_daisy.h
*
* Copyright (C) 2018-2019 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_DAISY_H
#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_DAISY_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
/************************************************************************************
* Name: imxrt_daisy_select
*
* Description:
* Initialize logic to support a daisy chain input selection for GPIO pins.
*
************************************************************************************/
void imxrt_daisy_select(unsigned int index, unsigned int alt);
#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_DAISY_H */
arch/arm/src/imxrt/chip/imxrt_dcdc.h
-152
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@@ -1,152 +0,0 @@
/****************************************************************************************************
* arch/arm/src/imxrt/imxrt_dcdc.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Janne Rosberg <janne@offcode.fi>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_DCDC_H
#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_DCDC_H
/****************************************************************************************************
* Included Files
****************************************************************************************************/
#include <nuttx/config.h>
#include "chip/imxrt_memorymap.h"
/****************************************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
/* Register offsets *********************************************************************************/
#define IMXRT_DCDC_REG0_OFFSET 0x0000 /* DCDC Register 0 */
#define IMXRT_DCDC_REG1_OFFSET 0x0004 /* DCDC Register 1 */
#define IMXRT_DCDC_REG2_OFFSET 0x0008 /* DCDC Register 2 */
#define IMXRT_DCDC_REG3_OFFSET 0x000c /* DCDC Register 3 */
/* Register addresses *******************************************************************************/
#define IMXRT_DCDC_REG0 (IMXRT_DCDC_BASE + IMXRT_DCDC_REG0_OFFSET)
#define IMXRT_DCDC_REG1 (IMXRT_DCDC_BASE + IMXRT_DCDC_REG1_OFFSET)
#define IMXRT_DCDC_REG2 (IMXRT_DCDC_BASE + IMXRT_DCDC_REG2_OFFSET)
#define IMXRT_DCDC_REG3 (IMXRT_DCDC_BASE + IMXRT_DCDC_REG3_OFFSET)
/* Register bit definitions *************************************************************************/
/* Register 0 */
#define DCDC_REG0_PWD_ZCD (1 << 0) /* Bit 0: Power down the zero cross detection */
#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH (1 << 1) /* Bit 1: Disable automatic clock switch */
#define DCDC_REG0_SEL_CLK (1 << 2) /* Bit 2: Select 24 MHz Crystal clock */
#define DCDC_REG0_PWD_OSC_INT (1 << 3) /* Bit 3: Power down internal osc */
#define DCDC_REG0_PWD_CUR_SNS_CMP (1 << 4) /* Bit 4: The power down signal of the current detector */
#define DCDC_REG0_CUR_SNS_THRSH_SHIFT (5) /* Bits 5-7: threshold of current detector */
#define DCDC_REG0_CUR_SNS_THRSH_MASK (0x7 << DCDC_REG0_CUR_SNS_THRSH_SHIFT)
# define DCDC_REG0_CUR_SNS_THRSH_150MA ((uint32_t)(0) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)
# define DCDC_REG0_CUR_SNS_THRSH_250MA ((uint32_t)(1) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)
# define DCDC_REG0_CUR_SNS_THRSH_350MA ((uint32_t)(2) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)
# define DCDC_REG0_CUR_SNS_THRSH_450MA ((uint32_t)(3) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)
# define DCDC_REG0_CUR_SNS_THRSH_550MA ((uint32_t)(4) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)
# define DCDC_REG0_CUR_SNS_THRSH_650MA ((uint32_t)(5) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)
#define DCDC_REG0_PWD_OVERCUR_DET (1 << 8) /* Bit 8: Power down overcurrent detection comparator */
#define DCDC_REG0_OVERCUR_TIRG_ADJ_SHIFT (9) /* Bits 9-10: The threshold of over current detection */
#define DCDC_REG0_OVERCUR_TIRG_ADJ_MASK (0x3 << DCDC_REG0_OVERCUR_TIRG_ADJ_SHIFT)
# define DCDC_REG0_OVERCUR_TIRG_ADJ_1A_025 ((uint32_t)(0) << DCDC_REG0_OVERCUR_TIRG_ADJ_SHIFT)
# define DCDC_REG0_OVERCUR_TIRG_ADJ_2A_025 ((uint32_t)(1) << DCDC_REG0_OVERCUR_TIRG_ADJ_SHIFT)
# define DCDC_REG0_OVERCUR_TIRG_ADJ_1A_02 ((uint32_t)(2) << DCDC_REG0_OVERCUR_TIRG_ADJ_SHIFT)
# define DCDC_REG0_OVERCUR_TIRG_ADJ_2A_02 ((uint32_t)(3) << DCDC_REG0_OVERCUR_TIRG_ADJ_SHIFT)
#define DCDC_REG0_PWD_CMP_BATT_DET (1 << 11) /* Bit 11: Power down the low voltage detection comparator */
#define DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT (12) /* Bits 12-15: Adjust value to poslimit_buck register */
#define DCDC_REG0_ADJ_POSLIMIT_BUCK_MASK (0xf << DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT)
# define DCDC_REG0_ADJ_POSLIMIT_BUCK(n) ((uint32_t)(n) << DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT)
#define DCDC_REG0_EN_LP_OVERLOAD_SNS (1 << 16) /* Bit 16: Enable the overload detection in power save mode */
#define DCDC_REG0_PWD_HIGH_VOLT_DET (1 << 17) /* Bit 17: Power down overvoltage detection comparator */
#define DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT (18) /* Bits 18-19: the threshold of the counting number */
#define DCDC_REG0_LP_OVERLOAD_THRSH_MASK (0x3 << DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT)
# define DCDC_REG0_LP_OVERLOAD_THRSH_32 ((uint32_t)(0) << DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT)
# define DCDC_REG0_LP_OVERLOAD_THRSH_64 ((uint32_t)(1) << DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT)
# define DCDC_REG0_LP_OVERLOAD_THRSH_16 ((uint32_t)(2) << DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT)
# define DCDC_REG0_LP_OVERLOAD_THRSH_8 ((uint32_t)(3) << DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT)
#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL (1 << 20) /* Bit 20: The period of counting the charging times in power save mode */
#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL_8 (0 << 20) /* Bit 20: The period of counting the charging times in power save mode */
#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL_16 (1 << 20) /* Bit 20: Fhe period of counting the charging times in power save mode */
#define DCDC_REG0_LP_HIGH_HYS (1 << 21) /* Bit 21: Adjust hysteretic value in low power from 12.5mV to 25mV */
/* Bits 22-26 Reserved */
#define DCDC_REG0_XTALOK_DISABLE (1 << 27) /* Bit 27: Disable xtalok detection circuit */
#define DCDC_REG0_CURRENT_ALERT_RESET (1 << 28) /* Bit 28: Reset current alert signal */
#define DCDC_REG0_XTAL_24M_OK (1 << 29) /* Bit 29: Set to 1 to switch internal ring osc to xtal 24M */
/* Bit 30: Reserved */
#define DCDC_REG0_STS_DC_OK (1 << 31) /* Bit 31: Status register to indicate DCDC status */
/* Register 1 */
#define DCDC_REG1_POSLIMIT_BUCK_IN_SHIFT (0) /* Bits 0-6: Upper limit duty cycle limit in DC-DC converter */
#define DCDC_REG1_POSLIMIT_BUCK_IN_MASK (0x7f << DCDC_REG1_POSLIMIT_BUCK_IN_SHIFT)
# define DCDC_REG1_POSLIMIT_BUCK_IN(n) ((uint32_t)(n) << DCDC_REG1_POSLIMIT_BUCK_IN_SHIFT)
#define DCDC_REG1_REG_FBK_SEL_SHIFT (7) /* Bits 7-8: Select the feedback point of the internal regulator */
#define DCDC_REG1_REG_FBK_SEL_MASK (0x3 << DCDC_REG1_REG_FBK_SEL_SHIFT)
# define DCDC_REG1_REG_FBK_SEL(n) ((uint32_t)(n) << DCDC_REG1_REG_FBK_SEL_SHIFT)
/* Bits 9-11: Reserved */
#define DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT (12) /* Bits 12-13: Set the current bias of low power comparator */
#define DCDC_REG1_LP_CMP_ISRC_SEL_MASK (0x3 << DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT)
# define DCDC_REG1_LP_CMP_ISRC_SEL(n) ((uint32_t)(n) << DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT)
#define DCDC_REG1_NEGLIMIT_IN_SHIFT (14) /* Bits 14-20: Set the current bias of low power comparator */
#define DCDC_REG1_NEGLIMIT_IN_MASK (0x3f << DCDC_REG1_NEGLIMIT_IN_SHIFT)
# define DCDC_REG1_NEGLIMIT_IN(n) ((uint32_t)(n) << DCDC_REG1_NEGLIMIT_IN_SHIFT)
#define DCDC_REG1_LOOPCTRL_HST_THRESH (1 << 21) /* Bit 21: Increase the threshold detection for common mode analog comparator */
/* Bit 22: Reserved */
#define DCDC_REG1_LOOPCTRL_EN_HYST (1 << 23) /* Bit 23: Enable hysteresis in switching converter */
#define DCDC_REG1_VBG_TRIM_SHIFT (24) /* Bits 24-28: Trim bandgap voltage */
#define DCDC_REG1_VBG_TRIM_MASK (0x1f << DCDC_REG1_VBG_TRIM_SHIFT)
# define DCDC_REG1_VBG_TRIM(n) ((uint32_t)(n) << DCDC_REG1_VBG_TRIM_SHIFT)
/* Bit 29-31: Reserved */
/* Register 3 */
#define DCDC_REG3_TRG_SHIFT (0) /* Bits 0-4: Target value of VDD_SOC, 25 mV each step */
#define DCDC_REG3_TRG_MASK (0x1f << DCDC_REG3_TRG_SHIFT)
# define DCDC_REG3_TRG(n) ((uint32_t)(n) << DCDC_REG3_TRG_SHIFT)
/* Bit 5-7: Reserved */
#define DCDC_REG3_TARGET_LP_SHIFT (8) /* Bits 8-10: Target value of standby (low power) mode */
#define DCDC_REG3_TARGET_LP_MASK (0x7 << DCDC_REG3_TARGET_LP_SHIFT)
# define DCDC_REG3_TARGET_LP_(n) ((uint32_t)(n) << DCDC_REG3_TARGET_LP_SHIFT)
/* Bit 11-23: Reserved */
#define DCDC_REG3_MINPWR_DC_HALFCLK (1 << 24) /* Bit 24: Set DCDC clock to half freqeuncy for continuous mode */
/* Bit 25-26: Reserved */
#define DCDC_REG3_MISC_DELAY_TIMING (1 << 27) /* Bit 27: Adjust delay to reduce ground noise */
#define DCDC_REG3_MISC_DISABLE_FET_LOGIC (1 << 28) /* Bit 28: Datasheet: reserved? */
/* Bit 29: Reserved */
#define DCDC_REG3_DISABLE_STEP (1 << 30) /* Bit 30: Disable stepping */
/* Bit 31: Reserved */
#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_DCDC_H */
arch/arm/src/imxrt/chip/imxrt_dmamux.h
-147
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@@ -1,147 +0,0 @@
/****************************************************************************
* arch/arm/src/imxrt/chip/imxrt_dmamux.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_DMAMUX_H
#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_DMAMUX_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip/imxrt_memorymap.h"
#if defined(CONFIG_ARCH_FAMILY_IMXRT102x)
# include "chip/rt102x/imxrt102x_dmamux.h"
#elif defined(CONFIG_ARCH_FAMILY_IMXRT105x)
# include "chip/rt105x/imxrt105x_dmamux.h"
#elif defined(CONFIG_ARCH_FAMILY_IMXRT106x)
# include "chip/rt106x/imxrt106x_dmamux.h"
#else
# error Unrecognized i.MX RT architecture
#endif
/****************************************************************************
* Pre-processor definitions
****************************************************************************/
#define IMXRT_DMAMUX_NCHAN 32
/* DMAMUX Register Offsets **************************************************/
#define IMXRT_DMAMUX_CHCFG_OFFSET(n) ((uintptr_t)(n) << 2)
# define IMXRT_DMAMUX_CHCFG0_OFFSET 0x0000 /* Channel configuration register 0 */
# define IMXRT_DMAMUX_CHCFG1_OFFSET 0x0004 /* Channel configuration register 1 */
# define IMXRT_DMAMUX_CHCFG2_OFFSET 0x0008 /* Channel configuration register 2 */
# define IMXRT_DMAMUX_CHCFG3_OFFSET 0x000c /* Channel configuration register 3 */
# define IMXRT_DMAMUX_CHCFG4_OFFSET 0x0010 /* Channel configuration register 4 */
# define IMXRT_DMAMUX_CHCFG5_OFFSET 0x0014 /* Channel configuration register 5 */
# define IMXRT_DMAMUX_CHCFG6_OFFSET 0x0018 /* Channel configuration register 6 */
# define IMXRT_DMAMUX_CHCFG7_OFFSET 0x001c /* Channel configuration register 7 */
# define IMXRT_DMAMUX_CHCFG8_OFFSET 0x0020 /* Channel configuration register 8 */
# define IMXRT_DMAMUX_CHCFG9_OFFSET 0x0024 /* Channel configuration register 9 */
# define IMXRT_DMAMUX_CHCFG10_OFFSET 0x0028 /* Channel configuration register 10 */
# define IMXRT_DMAMUX_CHCFG11_OFFSET 0x002c /* Channel configuration register 11 */
# define IMXRT_DMAMUX_CHCFG12_OFFSET 0x0030 /* Channel configuration register 12 */
# define IMXRT_DMAMUX_CHCFG13_OFFSET 0x0034 /* Channel configuration register 13 */
# define IMXRT_DMAMUX_CHCFG14_OFFSET 0x0038 /* Channel configuration register 14 */
# define IMXRT_DMAMUX_CHCFG15_OFFSET 0x003c /* Channel configuration register 15 */
# define IMXRT_DMAMUX_CHCFG16_OFFSET 0x0040 /* Channel configuration register 16 */
# define IMXRT_DMAMUX_CHCFG17_OFFSET 0x0044 /* Channel configuration register 17 */
# define IMXRT_DMAMUX_CHCFG18_OFFSET 0x0048 /* Channel configuration register 18 */
# define IMXRT_DMAMUX_CHCFG19_OFFSET 0x004c /* Channel configuration register 19 */
# define IMXRT_DMAMUX_CHCFG20_OFFSET 0x0050 /* Channel configuration register 20 */
# define IMXRT_DMAMUX_CHCFG21_OFFSET 0x0054 /* Channel configuration register 21 */
# define IMXRT_DMAMUX_CHCFG22_OFFSET 0x0058 /* Channel configuration register 22 */
# define IMXRT_DMAMUX_CHCFG23_OFFSET 0x005c /* Channel configuration register 23 */
# define IMXRT_DMAMUX_CHCFG24_OFFSET 0x0060 /* Channel configuration register 24 */
# define IMXRT_DMAMUX_CHCFG25_OFFSET 0x0064 /* Channel configuration register 25 */
# define IMXRT_DMAMUX_CHCFG26_OFFSET 0x0068 /* Channel configuration register 26 */
# define IMXRT_DMAMUX_CHCFG27_OFFSET 0x006c /* Channel configuration register 27 */
# define IMXRT_DMAMUX_CHCFG28_OFFSET 0x0070 /* Channel configuration register 28 */
# define IMXRT_DMAMUX_CHCFG29_OFFSET 0x0074 /* Channel configuration register 29 */
# define IMXRT_DMAMUX_CHCFG30_OFFSET 0x0078 /* Channel configuration register 30 */
# define IMXRT_DMAMUX_CHCFG31_OFFSET 0x007c /* Channel configuration register 31 */
/* DMAMUX Register Addresses ************************************************/
#define IMXRT_DMAMUX_CHCFG(n) (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG_OFFSET(n))
# define IMXRT_DMAMUX_CHCFG0 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG0_OFFSET)
# define IMXRT_DMAMUX_CHCFG1 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG1_OFFSET)
# define IMXRT_DMAMUX_CHCFG2 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG2_OFFSET)
# define IMXRT_DMAMUX_CHCFG3 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG3_OFFSET)
# define IMXRT_DMAMUX_CHCFG4 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG4_OFFSET)
# define IMXRT_DMAMUX_CHCFG5 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG5_OFFSET)
# define IMXRT_DMAMUX_CHCFG6 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG6_OFFSET)
# define IMXRT_DMAMUX_CHCFG7 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG7_OFFSET)
# define IMXRT_DMAMUX_CHCFG8 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG8_OFFSET)
# define IMXRT_DMAMUX_CHCFG9 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG9_OFFSET)
# define IMXRT_DMAMUX_CHCFG10 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG10_OFFSET)
# define IMXRT_DMAMUX_CHCFG11 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG11_OFFSET)
# define IMXRT_DMAMUX_CHCFG12 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG12_OFFSET)
# define IMXRT_DMAMUX_CHCFG13 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG13_OFFSET)
# define IMXRT_DMAMUX_CHCFG14 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG14_OFFSET)
# define IMXRT_DMAMUX_CHCFG15 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG15_OFFSET)
# define IMXRT_DMAMUX_CHCFG16 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG16_OFFSET)
# define IMXRT_DMAMUX_CHCFG17 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG17_OFFSET)
# define IMXRT_DMAMUX_CHCFG18 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG18_OFFSET)
# define IMXRT_DMAMUX_CHCFG19 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG19_OFFSET)
# define IMXRT_DMAMUX_CHCFG20 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG20_OFFSET)
# define IMXRT_DMAMUX_CHCFG21 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG21_OFFSET)
# define IMXRT_DMAMUX_CHCFG22 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG22_OFFSET)
# define IMXRT_DMAMUX_CHCFG23 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG23_OFFSET)
# define IMXRT_DMAMUX_CHCFG24 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG24_OFFSET)
# define IMXRT_DMAMUX_CHCFG25 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG25_OFFSET)
# define IMXRT_DMAMUX_CHCFG26 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG26_OFFSET)
# define IMXRT_DMAMUX_CHCFG27 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG27_OFFSET)
# define IMXRT_DMAMUX_CHCFG28 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG28_OFFSET)
# define IMXRT_DMAMUX_CHCFG29 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG29_OFFSET)
# define IMXRT_DMAMUX_CHCFG30 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG30_OFFSET)
# define IMXRT_DMAMUX_CHCFG31 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG31_OFFSET)
/* DMAMUX Bit-Field Definitions *********************************************/
/* Channel configuration registers 0-31 */
#define DMAMUX_CHCFG_SOURCE_SHIFT (0) /* Bits 0-6: Chip-specific DMA source */
#define DMAMUX_CHCFG_SOURCE_MASK (0x7e << DMAMUX_CHCFG_SOURCE_SHIFT)
# define DMAMUX_CHCFG_SOURCE(n) ((uint32_t)(n) << DMAMUX_CHCFG_SOURCE_SHIFT)
/* Bits 7-28: Reserved */
#define DMAMUX_CHCFG_AON (1 << 29) /* Bit 29: DMA Channel Always Enable */
#define DMAMUX_CHCFG_TRIG (1 << 30) /* Bit 30: DMA Channel Trigger Enable */
#define DMAMUX_CHCFG_ENBL (1 << 31) /* Bit 31: DMA Mux Channel Enable */
#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_DMAMUX_H */
arch/arm/src/imxrt/chip/imxrt_edma.h
-1302
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arch/arm/src/imxrt/chip/imxrt_enet.h
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arch/arm/src/imxrt/chip/imxrt_flexpwm.h
-1817
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arch/arm/src/imxrt/chip/imxrt_gpio.h
-93
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@@ -1,93 +0,0 @@
/********************************************************************************************
* arch/arm/src/imxrt/imxrt_gpio.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_GPIO_H
#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_GPIO_H
/********************************************************************************************
* Included Files
********************************************************************************************/
#include <nuttx/config.h>
#if defined(CONFIG_ARCH_FAMILY_IMXRT102x)
# include "chip/rt102x/imxrt102x_gpio.h"
#elif defined(CONFIG_ARCH_FAMILY_IMXRT105x)
# include "chip/rt105x/imxrt105x_gpio.h"
#elif defined(CONFIG_ARCH_FAMILY_IMXRT106x)
# include "chip/rt106x/imxrt106x_gpio.h"
#else
# error Unrecognized i.MX RT architecture
#endif
/********************************************************************************************
* Pre-processor Definitions
********************************************************************************************/
#define GPIO1 0 /* Port 1 index */
#define GPIO2 1 /* Port 2 index */
#define GPIO3 2 /* Port 3 index */
#define GPIO4 3 /* Port 4 index */
#define GPIO5 4 /* Port 5 index */
#if IMXRT_GPIO_NPORTS > 5
#define GPIO6 5 /* Port 6 index */
#define GPIO7 6 /* Port 7 index */
#define GPIO8 7 /* Port 8 index */
#define GPIO9 8 /* Port 9 index */
#endif
#define IMXRT_GPIO_NPINS 32 /* Up to 32 pins per port */
/* Register bit definitions *****************************************************************/
/* Most registers are laid out simply with one bit per pin */
#define GPIO_PIN(n) (1 << (n)) /* Bit n: Pin n, n=0-31 */
/* GPIO interrupt configuration register 1/2 */
#define GPIO_ICR_INDEX(n) (((n) >> 4) & 1)
#define GPIO_ICR_OFFSET(n) (GPIO_ICR1_OFFSET + (GPIO_ICR_INDEX(n) << 2))
#define GPIO_ICR_LOWLEVEL 0 /* Interrupt is low-level sensitive */
#define GPIO_ICR_HIGHLEVEL 1 /* Interrupt is high-level sensitive */
#define GPIO_ICR_RISINGEDGE 2 /* Interrupt is rising-edge sensitive */
#define GPIO_ICR_FALLINGEDGE 3 /* Interrupt is falling-edge sensitive */
#define GPIO_ICR_SHIFT(n) (((n) & 15) << 1)
#define GPIO_ICR_MASK(n) (3 << GPIO_ICR_SHIFT(n))
#define GPIO_ICR(i,n) ((uint32_t)(i) << GPIO_ICR_SHIFT(n))
#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_GPIO_H */
arch/arm/src/imxrt/chip/imxrt_gpt.h
-182
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@@ -1,182 +0,0 @@
/************************************************************************************
* arch/arm/src/imxrt/chip/imxrt_gpt.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_GPT_H
#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_GPT_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip/imxrt_memorymap.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register Offsets *****************************************************************/
#define IMXRT_GPT_CR_OFFSET 0x0000 /* GPT Control Register */
#define IMXRT_GPT_PR_OFFSET 0x0004 /* GPT Prescaler Register */
#define IMXRT_GPT_SR_OFFSET 0x0008 /* GPT Status Register */
#define IMXRT_GPT_IR_OFFSET 0x000c /* GPT Interrupt Register */
#define IMXRT_GPT_OCR1_OFFSET 0x0010 /* GPT Output Compare Register 1 */
#define IMXRT_GPT_OCR2_OFFSET 0x0014 /* GPT Output Compare Register 2 */
#define IMXRT_GPT_OCR3_OFFSET 0x0018 /* GPT Output Compare Register 3 */
#define IMXRT_GPT_ICR1_OFFSET 0x001c /* GPT Input Capture Register 1 */
#define IMXRT_GPT_ICR2_OFFSET 0x0020 /* GPT Input Capture Register 2 */
#define IMXRT_GPT_CNT_OFFSET 0x0024 /* GPT Counter Register */
/* Register addresses ***********************************************************************/
#define IMXRT_GPT1_CR (IMXRT_GPT1_BASE + IMXRT_GPT1_CR_OFFSET) /* GPT 1 Control Register */
#define IMXRT_GPT1_PR (IMXRT_GPT1_BASE + IMXRT_GPT1_PR_OFFSET) /* GPT 1 Prescaler Register */
#define IMXRT_GPT1_SR (IMXRT_GPT1_BASE + IMXRT_GPT1_SR_OFFSET) /* GPT 1 Status Register */
#define IMXRT_GPT1_IR (IMXRT_GPT1_BASE + IMXRT_GPT1_IR_OFFSET) /* GPT 1 Interrupt Register */
#define IMXRT_GPT1_OCR1 (IMXRT_GPT1_BASE + IMXRT_GPT1_OCR1_OFFSET) /* GPT 1 Output Compare Register 1 */
#define IMXRT_GPT1_OCR2 (IMXRT_GPT1_BASE + IMXRT_GPT1_OCR2_OFFSET) /* GPT 1 Output Compare Register 2 */
#define IMXRT_GPT1_OCR3 (IMXRT_GPT1_BASE + IMXRT_GPT1_OCR3_OFFSET) /* GPT 1 Output Compare Register 3 */
#define IMXRT_GPT1_ICR1 (IMXRT_GPT1_BASE + IMXRT_GPT1_ICR1_OFFSET) /* GPT 1 Input Capture Register 1 */
#define IMXRT_GPT1_ICR2 (IMXRT_GPT1_BASE + IMXRT_GPT1_ICR2_OFFSET) /* GPT 1 Input Capture Register 2 */
#define IMXRT_GPT1_CNT (IMXRT_GPT1_BASE + IMXRT_GPT1_CNT_OFFSET) /* GPT 1 Counter Register */
#define IMXRT_GPT2_CR (IMXRT_GPT2_BASE + IMXRT_GPT2_CR_OFFSET) /* GPT 2 Control Register */
#define IMXRT_GPT2_PR (IMXRT_GPT2_BASE + IMXRT_GPT2_PR_OFFSET) /* GPT 2 Prescaler Register */
#define IMXRT_GPT2_SR (IMXRT_GPT2_BASE + IMXRT_GPT2_SR_OFFSET) /* GPT 2 Status Register */
#define IMXRT_GPT2_IR (IMXRT_GPT2_BASE + IMXRT_GPT2_IR_OFFSET) /* GPT 2 Interrupt Register */
#define IMXRT_GPT2_OCR1 (IMXRT_GPT2_BASE + IMXRT_GPT2_OCR1_OFFSET) /* GPT 2 Output Compare Register 1 */
#define IMXRT_GPT2_OCR2 (IMXRT_GPT2_BASE + IMXRT_GPT2_OCR2_OFFSET) /* GPT 2 Output Compare Register 2 */
#define IMXRT_GPT2_OCR3 (IMXRT_GPT2_BASE + IMXRT_GPT2_OCR3_OFFSET) /* GPT 2 Output Compare Register 3 */
#define IMXRT_GPT2_ICR1 (IMXRT_GPT2_BASE + IMXRT_GPT2_ICR1_OFFSET) /* GPT 2 Input Capture Register 1 */
#define IMXRT_GPT2_ICR2 (IMXRT_GPT2_BASE + IMXRT_GPT2_ICR2_OFFSET) /* GPT 2 Input Capture Register 2 */
#define IMXRT_GPT2_CNT (IMXRT_GPT2_BASE + IMXRT_GPT2_CNT_OFFSET) /* GPT 2 Counter Register */
/* GPT Control Register */
/* Register Bit Definitions *********************************************************/
#define GPT_CR_EN (1 << 0) /* Bit: 0 GPT Enable. */
#define GPT_CR_ENMOD (1 << 1) /* Bit: 1 GPT Enable mode. */
#define GPT_CR_DBGEN (1 << 2) /* Bit: 2 GPT debug mode enable. */
#define GPT_CR_WAITEN (1 << 3) /* Bit: 3 GPT Wait Mode enable. */
#define GPT_CR_DOZEEN (1 << 4) /* Bit: 4 GPT Doze Mode Enable. */
#define GPT_CR_STOPEN (1 << 5) /* Bit: 5 GPT Stop Mode enable. */
#define GPT_CR_CLKSRC_SHIFT (6) /* Bits: 6-8 Clock Source select. */
#define GPT_CR_CLKSRC_MASK (7 << GPT_CR_CLKSRC_SHIFT)
# define GPT_CR_CLKSRC(n) ((uint32_t)(n) << GPT_CR_CLKSRC_SHIFT)
# define GPT_CR_CLKSRC_NONE (0 << GPT_CR_CLKSRC_SHIFT) /* No clock */
# define GPT_CR_CLKSRC_IPG (1 << GPT_CR_CLKSRC_SHIFT) /* Peripheral Clock (ipg_clk) */
# define GPT_CR_CLKSRC_IPG_HFR (2 << GPT_CR_CLKSRC_SHIFT) /* High Frequency Reference Clock (ipg_clk_highfreq) */
# define GPT_CR_CLKSRC_EXT (3 << GPT_CR_CLKSRC_SHIFT) /* External Clock */
# define GPT_CR_CLKSRC_IPG_LFR (4 << GPT_CR_CLKSRC_SHIFT) /* Low Frequency Reference Clock (ipg_clk_32k) */
# define GPT_CR_CLKSRC_IPG_24M (5 << GPT_CR_CLKSRC_SHIFT) /* Crystal oscillator as Reference Clock (ipg_clk_24M) */
#define GPT_CR_FRR (1 << 9) /* Bit: 9 Free-Run or Restart mode. */
#define GPT_CR_EN_24M (1 << 10) /* Bit: 10 Enable 24 MHz clock input from crystal. */
/* Bits: 11-14 Reserved */
#define GPT_CR_SWR (1 << 15) /* Bit: 15 Software reset. */
#define GPT_CR_IM1_SHIFT (16) /* Bits: 16-17 See IM2 */
#define GPT_CR_IM1_MASK (3 << GPT_CR_IM1_SHIFT)
# define GPT_CR_IM1(n) ((uint32_t)(n) << GPT_CR_IM1_SHIFT)
# define GPT_CR_IM1_DIS (0 << GPT_CR_IM1_SHIFT) /* Capture disabled */
# define GPT_CR_IM1_RISING (1 << GPT_CR_IM1_SHIFT) /* Capture on rising edge */
# define GPT_CR_IM1_FALLING (2 << GPT_CR_IM1_SHIFT) /* Capture on falling edge */
# define GPT_CR_IM1_BOTH (3 << GPT_CR_IM1_SHIFT) /* Capture on both edges */
#define GPT_CR_IM2_SHIFT (18) /* Bits: 18-19 IM2 (bits 19-18, Input Capture Channel 2 operating mode) */
#define GPT_CR_IM2_MASK (3 << GPT_CR_IM2_SHIFT)
# define GPT_CR_IM2(n) ((uint32_t)(n) << GPT_CR_IM2_SHIFT)
# define GPT_CR_IM2_DIS (0 << GPT_CR_IM2_SHIFT) /* Capture disabled */
# define GPT_CR_IM2_RISING (1 << GPT_CR_IM2_SHIFT) /* Capture on rising edge */
# define GPT_CR_IM2_FALLING (2 << GPT_CR_IM2_SHIFT) /* Capture on falling edge */
# define GPT_CR_IM2_BOTH (3 << GPT_CR_IM2_SHIFT) /* Capture on both edges */
#define GPT_CR_OM1_SHIFT (20) /* Bits: 20-22 See OM3 */
#define GPT_CR_OM1_MASK (7 << GPT_CR_OM1_SHIFT)
# define GPT_CR_OM1(n) ((uint32_t)(n) << GPT_CR_OM1_SHIFT)
# define GPT_CR_OM1_DIS (0 << GPT_CR_OM1_SHIFT) /* Output disconnected. No response on pin. */
# define GPT_CR_OM1_TOGGLE (1 << GPT_CR_OM1_SHIFT) /* Toggle output pin */
# define GPT_CR_OM1_CLEAR (2 << GPT_CR_OM1_SHIFT) /* Clear output pin */
# define GPT_CR_OM1_SET (3 << GPT_CR_OM1_SHIFT) /* Set output pin */
# define GPT_CR_OM1_PULSE (4 << GPT_CR_OM1_SHIFT) /* Generate an active low pulse */
#define GPT_CR_OM2_SHIFT (23) /* Bits: 23-25 See OM3 */
#define GPT_CR_OM2_MASK (7 << GPT_CR_OM2_SHIFT)
# define GPT_CR_OM2(n) ((uint32_t)(n) << GPT_CR_OM2_SHIFT)
# define GPT_CR_OM2_DIS (0 << GPT_CR_OM2_SHIFT) /* Output disconnected. No response on pin. */
# define GPT_CR_OM2_TOGGLE (1 << GPT_CR_OM2_SHIFT) /* Toggle output pin */
# define GPT_CR_OM2_CLEAR (2 << GPT_CR_OM2_SHIFT) /* Clear output pin */
# define GPT_CR_OM2_SET (3 << GPT_CR_OM2_SHIFT) /* Set output pin */
# define GPT_CR_OM2_PULSE (4 << GPT_CR_OM2_SHIFT) /* Generate an active low pulse */
#define GPT_CR_OM3_SHIFT (26) /* Bits: 26-28 OM3 (bits 28-26) controls the Output Compare Channel 3 operating mode. */
#define GPT_CR_OM3_MASK (7 << GPT_CR_OM3_SHIFT)
# define GPT_CR_OM3(n) ((uint32_t)(n) << GPT_CR_OM3_SHIFT)
# define GPT_CR_OM3_DIS (0 << GPT_CR_OM3_SHIFT) /* Output disconnected. No response on pin. */
# define GPT_CR_OM3_TOGGLE (1 << GPT_CR_OM3_SHIFT) /* Toggle output pin */
# define GPT_CR_OM3_CLEAR (2 << GPT_CR_OM3_SHIFT) /* Clear output pin */
# define GPT_CR_OM3_SET (3 << GPT_CR_OM3_SHIFT) /* Set output pin */
# define GPT_CR_OM3_PULSE (4 << GPT_CR_OM3_SHIFT) /* Generate an active low pulse */
#define GPT_CR_FO1 (1 << 29) /* Bit: 29 See F03 */
#define GPT_CR_FO2 (1 << 30) /* Bit: 30 See F03 */
#define GPT_CR_FO3 (1 << 31) /* Bit: 31 FO3 Force Output Compare Channel 3 */
/* GPT Prescaler Register */
#define GPT_PR_PRESCALER_SHIFT (0) /* Bits: 0-11 Prescaler bits. */
#define GPT_PR_PRESCALER_MASK (0xfff << GPT_PR_PRESCALER_SHIFT)
# define GPT_PR_PRESCALER(n) ((uint32_t)(n) << GPT_PR_PRESCALER_SHIFT)
#define GPT_PR_PRESCALER24M_SHIFT (12) /* Bits: 12-15 Prescaler bits. */
#define GPT_PR_PRESCALER24M_MASK (0xf << GPT_PR_PRESCALER24M_SHIFT)
# define GPT_PR_PRESCALER24M(n) ((uint32_t)(n) << GPT_PR_PRESCALER24M_SHIFT)
/* Bits: 16-31 Reserved */
/* GPT Status Register */
#define GPT_SR_OF1 (1 << 0) /* Bit: 0 Output Compare 1 Flag*/
#define GPT_SR_OF2 (1 << 1) /* Bit: 1 Output Compare 2 Flag*/
#define GPT_SR_OF3 (1 << 2) /* Bit: 2 Output Compare 3 Flag */
#define GPT_SR_IF1 (1 << 3) /* Bit: 3 Input capture 1 Flag */
#define GPT_SR_IF2 (1 << 4) /* Bit: 4 Input capture 2 Flag */
#define GPT_SR_ROV (1 << 5) /* Bit: 5 Rollover Flag. */
/* Bits: 6-31 Reserved */
/* GPT Interrupt Register */
#define GPT_IR_OF1IE (1 << 0) /* Bit: 0 Output Compare 1 Interrupt Enable */
#define GPT_IR_OF2IE (1 << 1) /* Bit: 1 Output Compare 2 Interrupt Enable */
#define GPT_IR_OF3IE (1 << 2) /* Bit: 2 Output Compare 3 Interrupt Enable */
#define GPT_IR_IF1IE (1 << 3) /* Bit: 3 Input capture 1 Interrupt Enable */
#define GPT_IR_IF2IE (1 << 4) /* Bit: 4 Input capture 2 Interrupt Enable */
#define GPT_IR_ROVIE (1 << 5) /* Bit: 5 Rollover Interrupt Enable. */
/* Bits: 6-31 Reserved */
#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_GPT_H */
arch/arm/src/imxrt/chip/imxrt_iomuxc.h
-124
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@@ -1,124 +0,0 @@
/************************************************************************************
* arch/arm/src/imxrt/imxrt_iomuxc.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_IOMUXC_H
#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_IOMUXC_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#if defined(CONFIG_ARCH_FAMILY_IMXRT102x)
# include "chip/rt102x/imxrt102x_iomuxc.h"
#elif defined(CONFIG_ARCH_FAMILY_IMXRT105x)
# include "chip/rt105x/imxrt105x_iomuxc.h"
#elif defined(CONFIG_ARCH_FAMILY_IMXRT106x)
# include "chip/rt106x/imxrt106x_iomuxc.h"
#else
# error Unrecognized i.MX RT architecture
#endif
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Pad Mux Registers */
#define PADMUX_MUXMODE_SHIFT (0) /* Bit 0-2: Software Input On Field */
#define PADMUX_MUXMODE_MASK (7 << PADMUX_MUXMODE_SHIFT)
# define PADMUX_MUXMODE_ALT0 (0 << PADMUX_MUXMODE_SHIFT)
# define PADMUX_MUXMODE_ALT1 (1 << PADMUX_MUXMODE_SHIFT)
# define PADMUX_MUXMODE_ALT2 (2 << PADMUX_MUXMODE_SHIFT)
# define PADMUX_MUXMODE_ALT3 (3 << PADMUX_MUXMODE_SHIFT)
# define PADMUX_MUXMODE_ALT4 (4 << PADMUX_MUXMODE_SHIFT)
# define PADMUX_MUXMODE_ALT5 (5 << PADMUX_MUXMODE_SHIFT)
# define PADMUX_MUXMODE_ALT7 (7 << PADMUX_MUXMODE_SHIFT)
#define PADMUX_SION_SHIFT (4) /* Bit 4: Software Input On Field */
# define PADMUX_SION (1 << PADMUX_SION_SHIFT)
/* Pad Control Registers */
#define DRIVE_HIZ (0) /* HI-Z */
#define DRIVE_260OHM (1) /* 150 Ohm @3.3V, 260 Ohm @1.8V */
#define DRIVE_130OHM (2) /* 75 Ohm @3.3V, 130 Ohm @1.8V */
#define DRIVE_90OHM (3) /* 50 Ohm @3.3V, 90 Ohm @1.8V */
#define DRIVE_60OHM (4) /* 37 Ohm @3.3V, 60 Ohm @1.8V */
#define DRIVE_50OHM (5) /* 30 Ohm @3.3V, 50 Ohm @1.8V */
#define DRIVE_40OHM (6) /* 25 Ohm @3.3V, 40 Ohm @1.8V */
#define DRIVE_33OHM (7) /* 20 Ohm @3.3V, 33 Ohm @1.8V */
#define SPEED_LOW (0) /* Low frequency (50 MHz) */
#define SPEED_MEDIUM (2) /* Medium frequency (100, MHz) */
#define SPEED_MAX (3) /* Maximum frequency (200 MHz) */
#define PULL_DOWN_100K (0) /* 100K Ohm Pull Down */
#define PULL_UP_47K (1) /* 47K Ohm Pull Up */
#define PULL_UP_100K (2) /* 100K Ohm Pull Up */
#define PULL_UP_22K (3) /* 22K Ohm Pull Up */
#define PADCTL_SRE (1 << 0) /* Bit 0: Slew Rate Field */
#define PADCTL_DSE_SHIFT (3) /* Bits 3-5: Drive Strength Field */
#define PADCTL_DSE_MASK (7 << PADCTL_DSE_SHIFT)
# define PADCTL_DSE(n) ((uint32_t)(n) << PADCTL_DSE_SHIFT) /* n=DRIVE_* */
# define PADCTL_DSE_HIZ (0 << PADCTL_DSE_SHIFT) /* HI-Z */
# define PADCTL_DSE_260OHM (1 << PADCTL_DSE_SHIFT) /* 150 Ohm @3.3V, 260 Ohm @1.8V */
# define PADCTL_DSE_130OHM (2 << PADCTL_DSE_SHIFT) /* 75 Ohm @3.3V, 130 Ohm @1.8V */
# define PADCTL_DSE_90OHM (3 << PADCTL_DSE_SHIFT) /* 50 Ohm @3.3V, 90 Ohm @1.8V */
# define PADCTL_DSE_60OHM (4 << PADCTL_DSE_SHIFT) /* 37 Ohm @3.3V, 60 Ohm @1.8V */
# define PADCTL_DSE_50OHM (5 << PADCTL_DSE_SHIFT) /* 30 Ohm @3.3V, 50 Ohm @1.8V */
# define PADCTL_DSE_40OHM (6 << PADCTL_DSE_SHIFT) /* 25 Ohm @3.3V, 40 Ohm @1.8V */
# define PADCTL_DSE_33OHM (7 << PADCTL_DSE_SHIFT) /* 20 Ohm @3.3V, 33 Ohm @1.8V */
#define PADCTL_SPEED_SHIFT (6) /* Bits 6-7: Speed Field */
#define PADCTL_SPEED_MASK (3 << PADCTL_SPEED_SHIFT)
# define PADCTL_SPEED(n) ((uint32_t)(n) << PADCTL_SPEED_SHIFT) /* n=SPEED_* */
# define PADCTL_SPEED_LOW (0 << PADCTL_SPEED_SHIFT) /* Low frequency (50 MHz) */
# define PADCTL_SPEED_MEDIUM (1 << PADCTL_SPEED_SHIFT) /* Medium frequency (100, 150 MHz) */
# define PADCTL_SPEED_MAX (3 << PADCTL_SPEED_SHIFT) /* Maximum frequency (100, 150, 200 MHz) */
#define PADCTL_ODE (1 << 11) /* Bit 11: Open Drain Enable Field */
#define PADCTL_PKE (1 << 12) /* Bit 12: Pull / Keep Enable Field */
#define PADCTL_PUE (1 << 13) /* Bit 13: Pull / Keep Select Field */
#define PADCTL_PUS_SHIFT (14) /* Bits 14-15: Pull Up / Down Config. Field */
#define PADCTL_PUS_MASK (3 << PADCTL_PUS_SHIFT)
# define PADCTL_PUS(n) ((uint32_t)(n) << PADCTL_PUS_SHIFT) /* n=PULL_* */
# define PADCTL_PUS_DOWN_100K (0 << PADCTL_PUS_SHIFT) /* 100K Ohm Pull Down */
# define PADCTL_PUS_UP_47K (1 << PADCTL_PUS_SHIFT) /* 47K Ohm Pull Up */
# define PADCTL_PUS_UP_100K (2 << PADCTL_PUS_SHIFT) /* 100K Ohm Pull Up */
# define PADCTL_PUS_UP_22K (3 << PADCTL_PUS_SHIFT) /* 22K Ohm Pull Up */
#define PADCTL_HYS (1 << 16) /* Bit 16: Hysteresis Enable Field */
#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_IOMUXC_H */
arch/arm/src/imxrt/chip/imxrt_lcd.h
-1709
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arch/arm/src/imxrt/chip/imxrt_lpi2c.h
-622
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arch/arm/src/imxrt/chip/imxrt_lpspi.h
-371
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@@ -1,371 +0,0 @@
/********************************************************************************************
* arch/arm/src/imxrt/imxrt_lpspi.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Pavlina Koleva <pavlinaikoleva19@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_LPSPI_H
#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_LPSPI_H
/********************************************************************************************
* Included Files
********************************************************************************************/
#include <nuttx/config.h>
#include "chip/imxrt_memorymap.h"
/********************************************************************************************
* Pre-processor Definitions
********************************************************************************************/
/* Register offsets *************************************************************************/
#define IMXRT_LPSPI_VERID_OFFSET 0x0000 /* Version ID Register offset */
#define IMXRT_LPSPI_PARAM_OFFSET 0x0004 /* Parameter Register offset */
#define IMXRT_LPSPI_CR_OFFSET 0x0010 /* Control Register offset */
#define IMXRT_LPSPI_SR_OFFSET 0x0014 /* Status Register offset */
#define IMXRT_LPSPI_IER_OFFSET 0x0018 /* Interrupt Enable Register offset */
#define IMXRT_LPSPI_DER_OFFSET 0x001C /* DMA Enable Register offset */
#define IMXRT_LPSPI_CFGR0_OFFSET 0x0020 /* Configuration Register 0 offset */
#define IMXRT_LPSPI_CFGR1_OFFSET 0x0024 /* Configuration Register 1 offset */
#define IMXRT_LPSPI_DMR0_OFFSET 0x0030 /* Data Match Register 0 offset */
#define IMXRT_LPSPI_DMR1_OFFSET 0x0034 /* Data Match Register 1 offset */
#define IMXRT_LPSPI_CCR_OFFSET 0x0040 /* Clock Configuration Register offset */
#define IMXRT_LPSPI_FCR_OFFSET 0x0058 /* FIFO Control Register offset */
#define IMXRT_LPSPI_FSR_OFFSET 0x005C /* FIFO Status Register offset */
#define IMXRT_LPSPI_TCR_OFFSET 0x0060 /* Transmit Command Register offset */
#define IMXRT_LPSPI_TDR_OFFSET 0x0064 /* Transmit Data Register offset */
#define IMXRT_LPSPI_RSR_OFFSET 0x0070 /* Receive Status Register offset */
#define IMXRT_LPSPI_RDR_OFFSET 0x0074 /* Receive Data Register offset */
/* Register addresses ***********************************************************************/
#define IMXRT_LPSPI1_VERID (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_VERID_OFFSET)
#define IMXRT_LPSPI1_PARAM (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_PARAM_OFFSET)
#define IMXRT_LPSPI1_CR (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_CR_OFFSET)
#define IMXRT_LPSPI1_SR (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_SR_OFFSET)
#define IMXRT_LPSPI1_IER (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_IER_OFFSET)
#define IMXRT_LPSPI1_DER (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_DER_OFFSET)
#define IMXRT_LPSPI1_CFGR0 (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_CFGR0_OFFSET)
#define IMXRT_LPSPI1_CFGR1 (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_CFGR1_OFFSET)
#define IMXRT_LPSPI1_DMR0 (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_DMR0_OFFSET)
#define IMXRT_LPSPI1_DMR1 (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_DMR1_OFFSET)
#define IMXRT_LPSPI1_CCR (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_CCR_OFFSET)
#define IMXRT_LPSPI1_FCR (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_FCR_OFFSET)
#define IMXRT_LPSPI1_FSR (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_FSR_OFFSET)
#define IMXRT_LPSPI1_TCR (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_TCR_OFFSET)
#define IMXRT_LPSPI1_TDR (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_TDR_OFFSET)
#define IMXRT_LPSPI1_RSR (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_RSR_OFFSET)
#define IMXRT_LPSPI1_RDR (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_RDR_OFFSET)
#define IMXRT_LPSPI2_VERID (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_VERID_OFFSET)
#define IMXRT_LPSPI2_PARAM (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_PARAM_OFFSET)
#define IMXRT_LPSPI2_CR (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_CR_OFFSET)
#define IMXRT_LPSPI2_SR (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_SR_OFFSET)
#define IMXRT_LPSPI2_IER (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_IER_OFFSET)
#define IMXRT_LPSPI2_DER (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_DER_OFFSET)
#define IMXRT_LPSPI2_CFGR0 (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_CFGR0_OFFSET)
#define IMXRT_LPSPI2_CFGR1 (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_CFGR1_OFFSET)
#define IMXRT_LPSPI2_DMR0 (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_DMR0_OFFSET)
#define IMXRT_LPSPI2_DMR1 (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_DMR1_OFFSET)
#define IMXRT_LPSPI2_CCR (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_CCR_OFFSET)
#define IMXRT_LPSPI2_FCR (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_FCR_OFFSET)
#define IMXRT_LPSPI2_FSR (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_FSR_OFFSET)
#define IMXRT_LPSPI2_TCR (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_TCR_OFFSET)
#define IMXRT_LPSPI2_TDR (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_TDR_OFFSET)
#define IMXRT_LPSPI2_RSR (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_RSR_OFFSET)
#define IMXRT_LPSPI2_RDR (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_RDR_OFFSET)
#define IMXRT_LPSPI3_VERID (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_VERID_OFFSET)
#define IMXRT_LPSPI3_PARAM (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_PARAM_OFFSET)
#define IMXRT_LPSPI3_CR (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_CR_OFFSET)
#define IMXRT_LPSPI3_SR (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_SR_OFFSET)
#define IMXRT_LPSPI3_IER (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_IER_OFFSET)
#define IMXRT_LPSPI3_DER (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_DER_OFFSET)
#define IMXRT_LPSPI3_CFGR0 (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_CFGR0_OFFSET)
#define IMXRT_LPSPI3_CFGR1 (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_CFGR1_OFFSET)
#define IMXRT_LPSPI3_DMR0 (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_DMR0_OFFSET)
#define IMXRT_LPSPI3_DMR1 (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_DMR1_OFFSET)
#define IMXRT_LPSPI3_CCR (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_CCR_OFFSET)
#define IMXRT_LPSPI3_FCR (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_FCR_OFFSET)
#define IMXRT_LPSPI3_FSR (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_FSR_OFFSET)
#define IMXRT_LPSPI3_TCR (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_TCR_OFFSET)
#define IMXRT_LPSPI3_TDR (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_TDR_OFFSET)
#define IMXRT_LPSPI3_RSR (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_RSR_OFFSET)
#define IMXRT_LPSPI3_RDR (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_RDR_OFFSET)
#define IMXRT_LPSPI4_VERID (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_VERID_OFFSET)
#define IMXRT_LPSPI4_PARAM (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_PARAM_OFFSET)
#define IMXRT_LPSPI4_CR (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_CR_OFFSET)
#define IMXRT_LPSPI4_SR (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_SR_OFFSET)
#define IMXRT_LPSPI4_IER (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_IER_OFFSET)
#define IMXRT_LPSPI4_DER (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_DER_OFFSET)
#define IMXRT_LPSPI4_CFGR0 (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_CFGR0_OFFSET)
#define IMXRT_LPSPI4_CFGR1 (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_CFGR1_OFFSET)
#define IMXRT_LPSPI4_DMR0 (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_DMR0_OFFSET)
#define IMXRT_LPSPI4_DMR1 (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_DMR1_OFFSET)
#define IMXRT_LPSPI4_CCR (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_CCR_OFFSET)
#define IMXRT_LPSPI4_FCR (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_FCR_OFFSET)
#define IMXRT_LPSPI4_FSR (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_FSR_OFFSET)
#define IMXRT_LPSPI4_TCR (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_TCR_OFFSET)
#define IMXRT_LPSPI4_TDR (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_TDR_OFFSET)
#define IMXRT_LPSPI4_RSR (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_RSR_OFFSET)
#define IMXRT_LPSPI4_RDR (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_RDR_OFFSET)
/* Register bit definitions *****************************************************************/
/* Version ID Register */
#define LPSPI_VERID_FEATURE_SHIFT (0) /* Bits 0-15: Module Identification Number */
#define LPSPI_VERID_FEATURE_MASK (0xffff << LPSPI_VERID_FEATURE_SHIFT)
#define LPSPI_VERID_MINOR_SHIFT (16) /* Bits 16-23: Minor Version Number */
#define LPSPI_VERID_MINOR_MASK (0xff << LPSPI_VERID_MINOR_SHIFT)
#define LPSPI_VERID_MAJOR_SHIFT (24) /* Bits 24-31: Major Version Number */
#define LPSPI_VERID_MAJOR_MASK (0xff << LPSPI_VERID_MAJOR_SHIFT)
/* Parameter Register */
#define LPSPI_PARAM_TXFIFO_SHIFT (0) /* Bits 0-7: Transmit FIFO Size */
#define LPSPI_PARAM_TXFIFO_MASK (0xff << LPSPI_PARAM_TXFIFO_SHIFT)
#define LPSPI_PARAM_RXFIFO_SHIFT (8) /* Bits 8-15: Receive FIFO Size */
#define LPSPI_PARAM_RXFIFO_MASK (0xff << LPSPI_PARAM_RXFIFO_SHIFT)
#define LPSPI_PARAM_PCSNUM_SHIFT (16) /* Bits 16-23: PCS Number */
#define LPSPI_PARAM_PCSNUM_MASK (0xff << LPSPI_PARAM_PCSNUM_SHIFT)
/* Bits 24-31: Reserved */
/* Control Register */
#define LPSPI_CR_MEN (1 << 0) /* Bit 0: Module Enable */
#define LPSPI_CR_RST (1 << 1) /* Bit 1: Software Reset */
#define LPSPI_CR_DOZEN (1 << 2) /* Bit 2: Doze mode enable */
# define LPSPI_CR_DOZEN_EN (0 << 2) /* Module is enabled in Doze mode */
# define LPSPI_CR_DOZEN_DIS (1 << 2) /* Module is disabled in Doze mode */
#define LPSPI_CR_DBGEN (1 << 3) /* Bit 3: Debug Enable */
/* Bits 4-7: Reserved */
#define LPSPI_CR_RTF (1 << 8) /* Bit 8: Reset Transmit FIFO */
#define LPSPI_CR_RRF (1 << 9) /* Bit 9: Reset Receive FIFO */
/* Bits 10-31: Reserved */
/* Status Register */
#define LPSPI_SR_TDF (1 << 0) /* Bit 0: Transmit Data Flag */
#define LPSPI_SR_RDF (1 << 1) /* Bit 1: Receive Data Flag */
/* Bits 2-7: Reserved */
#define LPSPI_SR_WCF (1 << 8) /* Bit 8: Word Complete Flag */
#define LPSPI_SR_FCF (1 << 9) /* Bit 9: Frame Complete Flag */
#define LPSPI_SR_TCF (1 << 10) /* Bit 10: Transfer Complete Flag */
#define LPSPI_SR_TEF (1 << 11) /* Bit 11: Transmit Error Flag */
#define LPSPI_SR_REF (1 << 12) /* Bit 12: Receive Error Flag */
#define LPSPI_SR_DMF (1 << 13) /* Bit 13: Data Match Flag */
/* Bits 14-23: Reserved */
#define LPSPI_SR_MBF (1 << 24) /* Bit 24: Module Busy Flag */
/* Bits 25-31: Reserved */
/* Interrupt Enable Register */
#define LPSPI_IER_TDIE (1 << 0) /* Bit 0: Transmit Data Interrupt Enable */
#define LPSPI_IER_RDIE (1 << 1) /* Bit 1: Receive Data Interrupt Enable */
/* Bits 2-7: Reserved */
#define LPSPI_IER_WCIE (1 << 8) /* Bit 8: Word Complete Interrupt Enable */
#define LPSPI_IER_FCIE (1 << 9) /* Bit 9: Frame Complete Interrupt Enable */
#define LPSPI_IER_TCIE (1 << 10) /* Bit 10: Transfer Complete Interrupt Enable */
#define LPSPI_IER_TEIE (1 << 11) /* Bit 11: Transmit Error Interrupt Enable */
#define LPSPI_IER_REIE (1 << 12) /* Bit 12: Receive Error Interrupt Enable */
#define LPSPI_IER_DMIE (1 << 13) /* Bit 13: Data Match Interrupt Enable */
/* Bits 14-31: Reserved */
/* DMA Enable Register */
#define LPSPI_DER_TDDE (1 << 0) /* Bit 0: Transmit Data DMA Enable */
#define LPSPI_DER_RDDE (1 << 1) /* Bit 1: Receive Data DMA Enable */
/* Bits 2-31: Reserved */
/* Configuration Register 0 */
#define LPSPI_CFGR0_HREN (1 << 0) /* Bit 0: Host Request Enable */
#define LPSPI_CFGR0_HRPOL (1 << 1) /* Bit 1: Host Request Polarity */
# define LPSPI_CFGR0_HRPOL_LOW (0 << 1) /* Active low */
# define LPSPI_CFGR0_HRPOL_HIGH (1 << 1) /* Active high */
#define LPSPI_CFGR0_HRSEL (1 << 2) /* Bit 2: Host Request Select */
# define LPSPI_CFGR0_HRSEL_HREQ (0 << 2) /* Host request input is the LPSPI_HREQ pin */
# define LPSPI_CFGR0_HRSEL_INTR (1 << 2) /* Host request input is the input trigger */
/* Bits 3-7: Reserved */
#define LPSPI_CFGR0_CIRFIFO (1 << 8) /* Bits 8: Circular FIFO Enable */
#define LPSPI_CFGR0_RDMO (1 << 9) /* Bits 9: Receive Data Match Only */
# define LPSPI_CFGR0_RDMO_FIFO (0 << 9) /* RD stored in the receive FIFO as in normal operations */
# define LPSPI_CFGR0_RDMO_DMF (1 << 9) /* RD discarded unless the Data Match Flag (DMF) is set */
/* Bits 10-31: Reserved */
/* Configuration Register 1 */
#define LPSPI_CFGR1_MASTER (1 << 0) /* Bit 0: Master Mode */
#define LPSPI_CFGR1_SAMPLE (1 << 1) /* Bit 1: Sample Point */
# define LPSPI_CFGR1_SAMPLE_SCK (0 << 1) /* Input data is sampled on SCK edge */
# define LPSPI_CFGR1_SAMPLE_DELAY (1 << 1) /* Input data is sampled on delayed SCK edge */
#define LPSPI_CFGR1_AUTOPCS (1 << 2) /* Bit 2: Automatic PCS enabled */
#define LPSPI_CFGR1_NOSTALL (1 << 3) /* Bit 3: No Stall enabled */
/* Bits 4-7: Reserved */
#define LPSPI_CFGR1_PCSPOL_SHIFT (8) /* Bits 8-11: Peripheral Chip Select Polarity */
#define LPSPI_CFGR1_PCSPOL_MASK (0xf << LPSPI_CFGR1_PCSPOL_SHIFT)
# define LPSPI_CFGR1_PCSPOL_LOW (0 << LPSPI_CFGR1_PCSPOL_SHIFT) /* The Peripheral Chip Select pin PCSx is active low */
# define LPSPI_CFGR1_PCSPOL_HIGH (1 << LPSPI_CFGR1_PCSPOL_SHIFT) /* The Peripheral Chip Select pin PCSx is active high */
/* Bits 12-15: Reserved */
#define LPSPI_CFGR1_MATCFG_SHIFT (16) /* Bits 16-18: Match Configuration */
#define LPSPI_CFGR1_MATCFG_MASK (7 << LPSPI_CFGR1_MATCFG_SHIFT)
# define LPSPI_CFGR1_MATCFG(n) ((uint32_t)(n) << LPSPI_CFGR1_MATCFG_SHIFT)
/* Bits 19-23: Reserved */
#define LPSPI_CFGR1_PINCFG_SHIFT (24) /* Bits 24-25: Pin Configuration */
#define LPSPI_CFGR1_PINCFG_MASK (3 << LPSPI_CFGR1_PINCFG_SHIFT)
# define LPSPI_CFGR1_PINCFG_SIN_SOUT (0 << LPSPI_CFGR1_PINCFG_SHIFT) /* SIN is used for input data and SOUT is used for output data */
# define LPSPI_CFGR1_PINCFG_SIN_SIN (1 << LPSPI_CFGR1_PINCFG_SHIFT) /* SIN is used for both input and output data */
# define LPSPI_CFGR1_PINCFG_SOUT_SOUT (2 << LPSPI_CFGR1_PINCFG_SHIFT) /* SOUT is used for both input and output data */
# define LPSPI_CFGR1_PINCFG_SOUT_SIN (3 << LPSPI_CFGR1_PINCFG_SHIFT) /* SOUT is used for input data and SIN is used for output data */
# define LPSPI_CFGR1_PINCFG(n) ((uint32_t)(n) << LPSPI_CFGR1_PINCFG_SHIFT)
#define LPSPI_CFGR1_OUTCFG (1 << 26) /* Bit 26: Output Config */
# define LPSPI_CFGR1_OUTCFG_RETAIN (0 << 26) /* Output data retains last value when chip select is negated */
# define LPSPI_CFGR1_OUTCFG_TRISTATE (1 << 26) /* Output data is tristated when chip select is negated */
#define LPSPI_CFGR1_PCSCFG (1 << 27) /* Bit 27: Peripheral Chip Select Configuration */
# define LPSPI_CFGR1_PCSCFG_EN (0 << 27) /* PCS[3:2] are enabled */
# define LPSPI_CFGR1_PCSCFG_DIS (1 << 27) /* PCS[3:2] are disabled */
/* Bits 28-31: Reserved */
/* Data Match Register 0 */
#define LPSPI_DMR0_MATCH0_SHIFT (0) /* Bits 0-31: Match 0 Value */
#define LPSPI_DMR0_MATCH0_MASK (0xffffffff << LPSPI_DMR0_MATCH0_SHIFT)
# define LPSPI_DMR0_MATCH0(n) ((uint32_t)(n) << LPSPI_DMR0_MATCH0_SHIFT)
/* Data Match Register 0 */
#define LPSPI_DMR1_MATCH1_SHIFT (0) /* Bits 0-31: Match 1 Value */
#define LPSPI_DMR1_MATCH1_MASK (0xffffffff << LPSPI_DMR1_MATCH1_SHIFT)
# define LPSPI_DMR1_MATCH1(n) ((uint32_t)(n) << LPSPI_DMR1_MATCH1_SHIFT)
/* Clock Configuration Register */
#define LPSPI_CCR_SCKDIV_SHIFT (0) /* Bits 0-7: SCK Divider */
#define LPSPI_CCR_SCKDIV_MASK (0xff << LPSPI_CCR_SCKDIV_SHIFT)
# define LPSPI_CCR_SCKDIV(n) ((uint32_t)(n) << LPSPI_CCR_SCKDIV_SHIFT)
#define LPSPI_CCR_DBT_SHIFT (8) /* Bits 8-15: Delay Between Transfers */
#define LPSPI_CCR_DBT_MASK (0xff << LPSPI_CCR_DBT_SHIFT)
# define LPSPI_CCR_DBT(n) ((uint32_t)(n) << LPSPI_CCR_DBT_SHIFT)
#define LPSPI_CCR_PCSSCK_SHIFT (16) /* Bits 16-23: PCS-to-SCK Delay */
#define LPSPI_CCR_PCSSCK_MASK (0xff << LPSPI_CCR_PCSSCK_SHIFT)
# define LPSPI_CCR_PCSSCK(n) ((uint32_t)(n) << LPSPI_CCR_PCSSCK_SHIFT)
#define LPSPI_CCR_SCKPCS_SHIFT (24) /* Bits 24-31: SCK-to-PCS Delay */
#define LPSPI_CCR_SCKPCS_MASK (0xff << LPSPI_CCR_SCKPCS_SHIFT)
# define LPSPI_CCR_SCKPCS(n) ((uint32_t)(n) << LPSPI_CCR_SCKPCS_SHIFT)
/* FIFO Control Register */
#define LPSPI_FCR_TXWATER_SHIFT (0) /* Bits 0-3: Transmit FIFO Watermark */
#define LPSPI_FCR_TXWATER_MASK (0xf << LPSPI_FCR_TXWATER_SHIFT)
# define LPSPI_FCR_TXWATER(n) ((uint32_t)(n) << LPSPI_FCR_TXWATER_SHIFT)
/* Bits 4-7: Reserved */
/* Bits 8-15: Reserved */
#define LPSPI_FCR_RXWATER_SHIFT (8) /* Bits 16-19: Receive FIFO Watermark */
#define LPSPI_FCR_RXWATER_MASK (0xf << LPSPI_FCR_RXWATER_SHIFT)
# define LPSPI_FCR_RXWATER(n) ((uint32_t)(n) << LPSPI_FCR_RXWATER_SHIFT)
/* Bits 20-23: Reserved */
/* Bits 24-31: Reserved */
/* FIFO Status Register */
#define LPSPI_FSR_TXCOUNT_SHIFT (0) /* Bits 0-4: Transmit FIFO Count */
#define LPSPI_FSR_TXCOUNT_MASK (0x1f << LPSPI_FSR_TXCOUNT_SHIFT)
/* Bits 5-7: Reserved */
/* Bits 8-15: Reserved */
#define LPSPI_FSR_RXCOUNT_SHIFT (16) /* Bits 16-20: Receive FIFO Count */
#define LPSPI_FSR_RXCOUNT_MASK (0x1f << LPSPI_FSR_RXCOUNT_SHIFT)
/* Bits 21-23: Reserved */
/* Bits 24-31: Reserved */
/* Transmit Command Register */
#define LPSPI_TCR_FRAMESZ_SHIFT (0) /* Bits 0-11: Frame Size */
#define LPSPI_TCR_FRAMESZ_MASK (0xfff << LPSPI_TCR_FRAMESZ_SHIFT)
# define LPSPI_TCR_FRAMESZ(n) ((uint32_t)(n) << LPSPI_TCR_FRAMESZ_SHIFT)
/* Bits 12-15: Reserved */
#define LPSPI_TCR_WIDTH_SHIFT (16) /* Bits 16-17: Transfer Width */
#define LPSPI_TCR_WIDTH_MASK (3 << LPSPI_TCR_WIDTH_SHIFT)
# define LPSPI_TCR_WIDTH_1BIT (0 << LPSPI_TCR_WIDTH_SHIFT) /* 1 bit transfer */
# define LPSPI_TCR_WIDTH_2BIT (1 << LPSPI_TCR_WIDTH_SHIFT) /* 2 bit transfer */
# define LPSPI_TCR_WIDTH_4BIT (2 << LPSPI_TCR_WIDTH_SHIFT) /* 4 bit transfer */
#define LPSPI_TCR_TXMSK (1 << 18) /* Bit 18: Transmit Data Mask */
#define LPSPI_TCR_RXMSK (1 << 19) /* Bit 19: Receive Data Mask */
#define LPSPI_TCR_CONTC (1 << 20) /* Bit 20: Continuing Command */
#define LPSPI_TCR_CONT (1 << 21) /* Bit 21: Continuous Transfer */
#define LPSPI_TCR_BYSW (1 << 22) /* Bit 22: Byte Swap */
#define LPSPI_TCR_LSBF (1 << 23) /* Bit 23: LSB First */
# define LPSPI_TCR_MSBF (0 << 23) /* MSB First */
#define LPSPI_TCR_PCS_SHIFT (24) /* Bits 24-25: Peripheral Chip Select */
#define LPSPI_TCR_PCS_MASK (3 << LPSPI_TCR_PCS_SHIFT)
# define LPSPI_TCR_PCS_0 (0 << LPSPI_TCR_PCS_SHIFT) /* Transfer using LPSPI_PCS[0] */
# define LPSPI_TCR_PCS_1 (1 << LPSPI_TCR_PCS_SHIFT) /* Transfer using LPSPI_PCS[1] */
# define LPSPI_TCR_PCS_2 (2 << LPSPI_TCR_PCS_SHIFT) /* Transfer using LPSPI_PCS[2] */
# define LPSPI_TCR_PCS_3 (3 << LPSPI_TCR_PCS_SHIFT) /* Transfer using LPSPI_PCS[3] */
/* Bit 26: Reserved */
#define LPSPI_TCR_PRESCALE_SHIFT (27) /* Bits 27-29: Prescaler Value */
#define LPSPI_TCR_PRESCALE_MASK (7 << LPSPI_TCR_PRESCALE_SHIFT)
# define LPSPI_TCR_PRESCALE_1 (0 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 1 */
# define LPSPI_TCR_PRESCALE_2 (1 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 2 */
# define LPSPI_TCR_PRESCALE_4 (2 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 4 */
# define LPSPI_TCR_PRESCALE_8 (3 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 8 */
# define LPSPI_TCR_PRESCALE_16 (4 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 16 */
# define LPSPI_TCR_PRESCALE_32 (5 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 32 */
# define LPSPI_TCR_PRESCALE_64 (6 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 64 */
# define LPSPI_TCR_PRESCALE_128 (7 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 128 */
# define LPSPI_TCR_PRESCALE(n) ((uint32_t)(n) << LPSPI_TCR_PRESCALE_SHIFT)
#define LPSPI_TCR_CPHA (1 << 30) /* Bit 30: Clock Phase */
# define LPSPI_TCR_CPHA_CPT_LEAD (0 << 30) /* Data captured - leading edge of SCK and changed - following edge of SCK */
# define LPSPI_TCR_CPHA_CPT_FOLLOW (1 << 30) /* Data changed - leading edge of SCK and captured - following edge of SCK */
#define LPSPI_TCR_CPOL (1 << 31) /* Bit 31: Clock Polarity */
# define LPSPI_TCR_CPOL_INACT_LOW (0 << 31) /* The inactive state value of SCK is low */
# define LPSPI_TCR_CPOL_INACT_HIGH (1 << 31) /* The inactive state value of SCK is high */
/* Transmit Data Register */
#define LPSPI_TDR_DATA_SHIFT (0) /* Bits 0-31: Transmit Data */
# define LPSPI_TCR_DATA(n) ((uint32_t)(n) << LPSPI_TDR_DATA_SHIFT)
/* Receive Status Register */
#define LPSPI_RSR_SOF (1 << 0) /* Bit 0: Start Of Frame */
#define LPSPI_RSR_RXEMPTY (1 << 1) /* Bit 1: RX FIFO Empty */
/* Bits 2-31: Reserved */
/* Receive Data Register */
#define LPSPI_RDR_DATA_SHIFT (0) /* Bits 0-31: Receive Data */
#define LPSPI_RDR_DATA_MASK (0xffffffff << LPSPI_RDR_DATA_SHIFT)
#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_LPSPI_H */
arch/arm/src/imxrt/chip/imxrt_lpuart.h
-416
View File
@@ -1,416 +0,0 @@
/********************************************************************************************
* arch/arm/src/imxrt/imxrt_lpuart.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_LPUART_H
#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_LPUART_H
/********************************************************************************************
* Included Files
********************************************************************************************/
#include <nuttx/config.h>
#include "chip/imxrt_memorymap.h"
/********************************************************************************************
* Pre-processor Definitions
********************************************************************************************/
/* Register offsets *************************************************************************/
#define IMXRT_LPUART_VERID_OFFSET 0x0000 /* Version ID Register */
#define IMXRT_LPUART_PARAM_OFFSET 0x0004 /* Parameter Register */
#define IMXRT_LPUART_GLOBAL_OFFSET 0x0008 /* LPUART Global Register */
#define IMXRT_LPUART_PINCFG_OFFSET 0x000c /* LPUART Pin Configuration Register */
#define IMXRT_LPUART_BAUD_OFFSET 0x0010 /* LPUART Baud Rate Register */
#define IMXRT_LPUART_STAT_OFFSET 0x0014 /* LPUART Status Register */
#define IMXRT_LPUART_CTRL_OFFSET 0x0018 /* LPUART Control Register */
#define IMXRT_LPUART_DATA_OFFSET 0x001c /* LPUART Data Register */
#define IMXRT_LPUART_MATCH_OFFSET 0x0020 /* LPUART Match Address Register */
#define IMXRT_LPUART_MODIR_OFFSET 0x0024 /* LPUART Modem IrDA Register */
#define IMXRT_LPUART_FIFO_OFFSET 0x0028 /* LPUART FIFO Register */
#define IMXRT_LPUART_WATER_OFFSET 0x002c /* LPUART Watermark Register */
/* Register addresses ***********************************************************************/
#define IMXRT_LPUART1_VERID (IMXRT_LPUART1_BASE + IMXRT_LPUART_VERID_OFFSET)
#define IMXRT_LPUART1_PARAM (IMXRT_LPUART1_BASE + IMXRT_LPUART_PARAM_OFFSET)
#define IMXRT_LPUART1_GLOBAL (IMXRT_LPUART1_BASE + IMXRT_LPUART_GLOBAL_OFFSET)
#define IMXRT_LPUART1_PINCFG (IMXRT_LPUART1_BASE + IMXRT_LPUART_PINCFG_OFFSET)
#define IMXRT_LPUART1_BAUD (IMXRT_LPUART1_BASE + IMXRT_LPUART_BAUD_OFFSET)
#define IMXRT_LPUART1_STAT (IMXRT_LPUART1_BASE + IMXRT_LPUART_STAT_OFFSET)
#define IMXRT_LPUART1_CTRL (IMXRT_LPUART1_BASE + IMXRT_LPUART_CTRL_OFFSET)
#define IMXRT_LPUART1_DATA (IMXRT_LPUART1_BASE + IMXRT_LPUART_DATA_OFFSET)
#define IMXRT_LPUART1_MATCH (IMXRT_LPUART1_BASE + IMXRT_LPUART_MATCH_OFFSET)
#define IMXRT_LPUART1_MODIR (IMXRT_LPUART1_BASE + IMXRT_LPUART_MODIR_OFFSET)
#define IMXRT_LPUART1_FIFO (IMXRT_LPUART1_BASE + IMXRT_LPUART_FIFO_OFFSET)
#define IMXRT_LPUART1_WATER (IMXRT_LPUART1_BASE + IMXRT_LPUART_WATER_OFFSET)
#define IMXRT_LPUART2_VERID (IMXRT_LPUART2_BASE + IMXRT_LPUART_VERID_OFFSET)
#define IMXRT_LPUART2_PARAM (IMXRT_LPUART2_BASE + IMXRT_LPUART_PARAM_OFFSET)
#define IMXRT_LPUART2_GLOBAL (IMXRT_LPUART2_BASE + IMXRT_LPUART_GLOBAL_OFFSET)
#define IMXRT_LPUART2_PINCFG (IMXRT_LPUART2_BASE + IMXRT_LPUART_PINCFG_OFFSET)
#define IMXRT_LPUART2_BAUD (IMXRT_LPUART2_BASE + IMXRT_LPUART_BAUD_OFFSET)
#define IMXRT_LPUART2_STAT (IMXRT_LPUART2_BASE + IMXRT_LPUART_STAT_OFFSET)
#define IMXRT_LPUART2_CTRL (IMXRT_LPUART2_BASE + IMXRT_LPUART_CTRL_OFFSET)
#define IMXRT_LPUART2_DATA (IMXRT_LPUART2_BASE + IMXRT_LPUART_DATA_OFFSET)
#define IMXRT_LPUART2_MATCH (IMXRT_LPUART2_BASE + IMXRT_LPUART_MATCH_OFFSET)
#define IMXRT_LPUART2_MODIR (IMXRT_LPUART2_BASE + IMXRT_LPUART_MODIR_OFFSET)
#define IMXRT_LPUART2_FIFO (IMXRT_LPUART2_BASE + IMXRT_LPUART_FIFO_OFFSET)
#define IMXRT_LPUART2_WATER (IMXRT_LPUART2_BASE + IMXRT_LPUART_WATER_OFFSET)
#define IMXRT_LPUART3_VERID (IMXRT_LPUART3_BASE + IMXRT_LPUART_VERID_OFFSET)
#define IMXRT_LPUART3_PARAM (IMXRT_LPUART3_BASE + IMXRT_LPUART_PARAM_OFFSET)
#define IMXRT_LPUART3_GLOBAL (IMXRT_LPUART3_BASE + IMXRT_LPUART_GLOBAL_OFFSET)
#define IMXRT_LPUART3_PINCFG (IMXRT_LPUART3_BASE + IMXRT_LPUART_PINCFG_OFFSET)
#define IMXRT_LPUART3_BAUD (IMXRT_LPUART3_BASE + IMXRT_LPUART_BAUD_OFFSET)
#define IMXRT_LPUART3_STAT (IMXRT_LPUART3_BASE + IMXRT_LPUART_STAT_OFFSET)
#define IMXRT_LPUART3_CTRL (IMXRT_LPUART3_BASE + IMXRT_LPUART_CTRL_OFFSET)
#define IMXRT_LPUART3_DATA (IMXRT_LPUART3_BASE + IMXRT_LPUART_DATA_OFFSET)
#define IMXRT_LPUART3_MATCH (IMXRT_LPUART3_BASE + IMXRT_LPUART_MATCH_OFFSET)
#define IMXRT_LPUART3_MODIR (IMXRT_LPUART3_BASE + IMXRT_LPUART_MODIR_OFFSET)
#define IMXRT_LPUART3_FIFO (IMXRT_LPUART3_BASE + IMXRT_LPUART_FIFO_OFFSET)
#define IMXRT_LPUART3_WATER (IMXRT_LPUART3_BASE + IMXRT_LPUART_WATER_OFFSET)
#define IMXRT_LPUART4_VERID (IMXRT_LPUART4_BASE + IMXRT_LPUART_VERID_OFFSET)
#define IMXRT_LPUART4_PARAM (IMXRT_LPUART4_BASE + IMXRT_LPUART_PARAM_OFFSET)
#define IMXRT_LPUART4_GLOBAL (IMXRT_LPUART4_BASE + IMXRT_LPUART_GLOBAL_OFFSET)
#define IMXRT_LPUART4_PINCFG (IMXRT_LPUART4_BASE + IMXRT_LPUART_PINCFG_OFFSET)
#define IMXRT_LPUART4_BAUD (IMXRT_LPUART4_BASE + IMXRT_LPUART_BAUD_OFFSET)
#define IMXRT_LPUART4_STAT (IMXRT_LPUART4_BASE + IMXRT_LPUART_STAT_OFFSET)
#define IMXRT_LPUART4_CTRL (IMXRT_LPUART4_BASE + IMXRT_LPUART_CTRL_OFFSET)
#define IMXRT_LPUART4_DATA (IMXRT_LPUART4_BASE + IMXRT_LPUART_DATA_OFFSET)
#define IMXRT_LPUART4_MATCH (IMXRT_LPUART4_BASE + IMXRT_LPUART_MATCH_OFFSET)
#define IMXRT_LPUART4_MODIR (IMXRT_LPUART4_BASE + IMXRT_LPUART_MODIR_OFFSET)
#define IMXRT_LPUART4_FIFO (IMXRT_LPUART4_BASE + IMXRT_LPUART_FIFO_OFFSET)
#define IMXRT_LPUART4_WATER (IMXRT_LPUART4_BASE + IMXRT_LPUART_WATER_OFFSET)
#define IMXRT_LPUART5_VERID (IMXRT_LPUART5_BASE + IMXRT_LPUART_VERID_OFFSET)
#define IMXRT_LPUART5_PARAM (IMXRT_LPUART5_BASE + IMXRT_LPUART_PARAM_OFFSET)
#define IMXRT_LPUART5_GLOBAL (IMXRT_LPUART5_BASE + IMXRT_LPUART_GLOBAL_OFFSET)
#define IMXRT_LPUART5_PINCFG (IMXRT_LPUART5_BASE + IMXRT_LPUART_PINCFG_OFFSET)
#define IMXRT_LPUART5_BAUD (IMXRT_LPUART5_BASE + IMXRT_LPUART_BAUD_OFFSET)
#define IMXRT_LPUART5_STAT (IMXRT_LPUART5_BASE + IMXRT_LPUART_STAT_OFFSET)
#define IMXRT_LPUART5_CTRL (IMXRT_LPUART5_BASE + IMXRT_LPUART_CTRL_OFFSET)
#define IMXRT_LPUART5_DATA (IMXRT_LPUART5_BASE + IMXRT_LPUART_DATA_OFFSET)
#define IMXRT_LPUART5_MATCH (IMXRT_LPUART5_BASE + IMXRT_LPUART_MATCH_OFFSET)
#define IMXRT_LPUART5_MODIR (IMXRT_LPUART5_BASE + IMXRT_LPUART_MODIR_OFFSET)
#define IMXRT_LPUART5_FIFO (IMXRT_LPUART5_BASE + IMXRT_LPUART_FIFO_OFFSET)
#define IMXRT_LPUART5_WATER (IMXRT_LPUART5_BASE + IMXRT_LPUART_WATER_OFFSET)
#define IMXRT_LPUART6_VERID (IMXRT_LPUART6_BASE + IMXRT_LPUART_VERID_OFFSET)
#define IMXRT_LPUART6_PARAM (IMXRT_LPUART6_BASE + IMXRT_LPUART_PARAM_OFFSET)
#define IMXRT_LPUART6_GLOBAL (IMXRT_LPUART6_BASE + IMXRT_LPUART_GLOBAL_OFFSET)
#define IMXRT_LPUART6_PINCFG (IMXRT_LPUART6_BASE + IMXRT_LPUART_PINCFG_OFFSET)
#define IMXRT_LPUART6_BAUD (IMXRT_LPUART6_BASE + IMXRT_LPUART_BAUD_OFFSET)
#define IMXRT_LPUART6_STAT (IMXRT_LPUART6_BASE + IMXRT_LPUART_STAT_OFFSET)
#define IMXRT_LPUART6_CTRL (IMXRT_LPUART6_BASE + IMXRT_LPUART_CTRL_OFFSET)
#define IMXRT_LPUART6_DATA (IMXRT_LPUART6_BASE + IMXRT_LPUART_DATA_OFFSET)
#define IMXRT_LPUART6_MATCH (IMXRT_LPUART6_BASE + IMXRT_LPUART_MATCH_OFFSET)
#define IMXRT_LPUART6_MODIR (IMXRT_LPUART6_BASE + IMXRT_LPUART_MODIR_OFFSET)
#define IMXRT_LPUART6_FIFO (IMXRT_LPUART6_BASE + IMXRT_LPUART_FIFO_OFFSET)
#define IMXRT_LPUART6_WATER (IMXRT_LPUART6_BASE + IMXRT_LPUART_WATER_OFFSET)
#define IMXRT_LPUART7_VERID (IMXRT_LPUART7_BASE + IMXRT_LPUART_VERID_OFFSET)
#define IMXRT_LPUART7_PARAM (IMXRT_LPUART7_BASE + IMXRT_LPUART_PARAM_OFFSET)
#define IMXRT_LPUART7_GLOBAL (IMXRT_LPUART7_BASE + IMXRT_LPUART_GLOBAL_OFFSET)
#define IMXRT_LPUART7_PINCFG (IMXRT_LPUART7_BASE + IMXRT_LPUART_PINCFG_OFFSET)
#define IMXRT_LPUART7_BAUD (IMXRT_LPUART7_BASE + IMXRT_LPUART_BAUD_OFFSET)
#define IMXRT_LPUART7_STAT (IMXRT_LPUART7_BASE + IMXRT_LPUART_STAT_OFFSET)
#define IMXRT_LPUART7_CTRL (IMXRT_LPUART7_BASE + IMXRT_LPUART_CTRL_OFFSET)
#define IMXRT_LPUART7_DATA (IMXRT_LPUART7_BASE + IMXRT_LPUART_DATA_OFFSET)
#define IMXRT_LPUART7_MATCH (IMXRT_LPUART7_BASE + IMXRT_LPUART_MATCH_OFFSET)
#define IMXRT_LPUART7_MODIR (IMXRT_LPUART7_BASE + IMXRT_LPUART_MODIR_OFFSET)
#define IMXRT_LPUART7_FIFO (IMXRT_LPUART7_BASE + IMXRT_LPUART_FIFO_OFFSET)
#define IMXRT_LPUART7_WATER (IMXRT_LPUART7_BASE + IMXRT_LPUART_WATER_OFFSET)
#define IMXRT_LPUART8_VERID (IMXRT_LPUART8_BASE + IMXRT_LPUART_VERID_OFFSET)
#define IMXRT_LPUART8_PARAM (IMXRT_LPUART8_BASE + IMXRT_LPUART_PARAM_OFFSET)
#define IMXRT_LPUART8_GLOBAL (IMXRT_LPUART8_BASE + IMXRT_LPUART_GLOBAL_OFFSET)
#define IMXRT_LPUART8_PINCFG (IMXRT_LPUART8_BASE + IMXRT_LPUART_PINCFG_OFFSET)
#define IMXRT_LPUART8_BAUD (IMXRT_LPUART8_BASE + IMXRT_LPUART_BAUD_OFFSET)
#define IMXRT_LPUART8_STAT (IMXRT_LPUART8_BASE + IMXRT_LPUART_STAT_OFFSET)
#define IMXRT_LPUART8_CTRL (IMXRT_LPUART8_BASE + IMXRT_LPUART_CTRL_OFFSET)
#define IMXRT_LPUART8_DATA (IMXRT_LPUART8_BASE + IMXRT_LPUART_DATA_OFFSET)
#define IMXRT_LPUART8_MATCH (IMXRT_LPUART8_BASE + IMXRT_LPUART_MATCH_OFFSET)
#define IMXRT_LPUART8_MODIR (IMXRT_LPUART8_BASE + IMXRT_LPUART_MODIR_OFFSET)
#define IMXRT_LPUART8_FIFO (IMXRT_LPUART8_BASE + IMXRT_LPUART_FIFO_OFFSET)
#define IMXRT_LPUART8_WATER (IMXRT_LPUART8_BASE + IMXRT_LPUART_WATER_OFFSET)
/* Register bit definitions *****************************************************************/
/* Version ID Register */
#define LPUART_VERID_FEATURE_SHIFT (0) /* Bits 0-15: Feature Identification Number */
#define LPUART_VERID_FEATURE_MASK (0xffff << LPUART_VERID_FEATURE_SHIFT)
# define LPUART_VERID_FEATURE_STD (1 << LPUART_VERID_FEATURE_SHIFT) /* Standard feature set */
# define LPUART_VERID_FEATURE_MODEM (3 << LPUART_VERID_FEATURE_SHIFT) /* MODEM/IrDA support */
#define LPUART_VERID_MINOR_SHIFT (16) /* Bits 16-23: Minor Version Number */
#define LPUART_VERID_MINOR_MASK (0xff << LPUART_VERID_MINOR_SHIFT)
#define LPUART_VERID_MAJOR_SHIFT (24) /* Bits 24-31: Major Version Number */
#define LPUART_VERID_MAJOR_MASK (0xff << LPUART_VERID_MAJOR_SHIFT)
/* Parameter Register */
#define LPUART_PARAM_TXFIFO_SHIFT (0) /* Bits 0-7: Transmit FIFO Size */
#define LPUART_PARAM_TXFIFO_MASK (0xff << LPUART_PARAM_TXFIFO_SHIFT)
#define LPUART_PARAM_RXFIFO_SHIFT (8) /* Bits 8-15: Transmit FIFO Size */
#define LPUART_PARAM_RXFIFO_MASK (0xff << LPUART_PARAM_RXFIFO_SHIFT)
/* Bits 16-31: Reserved */
/* LPUART Global Register */
/* Bit 0: Reserved */
#define LPUART_GLOBAL_RST (1 << 1) /* Bit 1: Software Reset */
/* Bits 2-31: Reserved */
/* LPUART Pin Configuration Register */
#define LPUART_PINCFG_TRGSEL_SHIFT (0) /* Bits 0-1: Trigger Select */
#define LPUART_PINCFG_TRGSEL_MASK (3 << LPUART_PINCFG_TRGSEL_SHIFT)
# define LPUART_PINCFG_TRGSEL_DISABLE (0 << LPUART_PINCFG_TRGSEL_SHIFT) /* Trigger disabled */
# define LPUART_PINCFG_TRGSEL_RXD (1 << LPUART_PINCFG_TRGSEL_SHIFT) /* Trigger used instead of RXD pin */
# define LPUART_PINCFG_TRGSEL_CTSB (2 << LPUART_PINCFG_TRGSEL_SHIFT) /* Trigger used instead of CTS_B pin */
# define LPUART_PINCFG_TRGSEL_TXDMOD (3 << LPUART_PINCFG_TRGSEL_SHIFT) /* Trigger used to modulate the TXD output */
/* Bits 2-31: Reserved */
/* LPUART Baud Rate Register */
#define LPUART_BAUD_SBR_SHIFT (0) /* Bits 0-12: Baud Rate Modulo Divisor. */
#define LPUART_BAUD_SBR_MASK (0x1fff << LPUART_BAUD_SBR_SHIFT)
# define LPUART_BAUD_SBR(n) ((uint32_t)(n) << LPUART_BAUD_SBR_SHIFT)
#define LPUART_BAUD_SBNS (1 << 13) /* Bit 13: Stop Bit Number Select */
#define LPUART_BAUD_RXEDGIE (1 << 14) /* Bit 14: RX Input Active Edge Interrupt Enable */
#define LPUART_BAUD_LBKDIE (1 << 15) /* Bit 15: LIN Break Detect Interrupt Enable */
#define LPUART_BAUD_RESYNCDIS (1 << 16) /* Bit 16: Resynchronization Disable */
#define LPUART_BAUD_BOTHEDGE (1 << 17) /* Bit 17: Both Edge Sampling */
#define LPUART_BAUD_MATCFG_SHIFT (18) /* Bits 18-19: Match Configuration */
#define LPUART_BAUD_MATCFG_MASK (3 << LPUART_BAUD_MATCFG_SHIFT)
# define LPUART_BAUD_MATCFG_ADDR (0 << LPUART_BAUD_MATCFG_SHIFT) /* Address Match Wakeup */
# define LPUART_BAUD_MATCFG_IDLE (1 << LPUART_BAUD_MATCFG_SHIFT) /* Idle Match Wakeup */
# define LPUART_BAUD_MATCFG_ONOFF (2 << LPUART_BAUD_MATCFG_SHIFT) /* Match On and Match Off */
# define LPUART_BAUD_MATCFG_RWUENAB (3 << LPUART_BAUD_MATCFG_SHIFT) /* Enables RWU on Data Match and Match
* On/Off for transmitter CTS input */
/* Bit 20: Reserved */
#define LPUART_BAUD_RDMAE (1 << 21) /* Bit 21: Receiver Full DMA Enable */
/* Bit 22: Reserved */
#define LPUART_BAUD_TDMAE (1 << 23) /* Bit 23: Transmitter DMA Enable */
#define LPUART_BAUD_OSR_SHIFT (24) /* Bits 24-28: Oversampling Ratio */
#define LPUART_BAUD_OSR_MASK (15 << LPUART_BAUD_OSR_SHIFT)
# define LPUART_BAUD_OSR(n) ((uint32_t)((n) - 1) << LPUART_BAUD_OSR_SHIFT)
#define LPUART_BAUD_M10 (1 << 29) /* Bit 20: 10-bit Mode select */
#define LPUART_BAUD_MAEN2 (1 << 30) /* Bit 30: Match Address Mode Enable 2 */
#define LPUART_BAUD_MAEN1 (1 << 31) /* Bit 31: Match Address Mode Enable 1 */
/* LPUART Status Register */
/* Bits 0-13: Reserved */
#define LPUART_STAT_MA2F (1 << 14) /* Bit 14: Match 2 Flag */
#define LPUART_STAT_MA1F (1 << 15) /* Bit 15: Match 1 Flag */
#define LPUART_STAT_PF (1 << 16) /* Bit 16: Parity Error Flag */
#define LPUART_STAT_FE (1 << 17) /* Bit 17: Framing Error Flag */
#define LPUART_STAT_NF (1 << 18) /* Bit 18: Noise Flag */
#define LPUART_STAT_OR (1 << 19) /* Bit 19: Receiver Overrun Flag */
#define LPUART_STAT_IDLE (1 << 20) /* Bit 20: Idle Line Flag */
#define LPUART_STAT_RDRF (1 << 21) /* Bit 21: Receive Data Register Full Flag */
#define LPUART_STAT_TC (1 << 22) /* Bit 22: Transmission Complete Flag */
#define LPUART_STAT_TDRE (1 << 23) /* Bit 23: Transmit Data Register Empty Flag */
#define LPUART_STAT_RAF (1 << 24) /* Bit 24: Receiver Active Flag */
#define LPUART_STAT_LBKDE (1 << 25) /* Bit 25: LIN Break Detection Enable */
#define LPUART_STAT_BRK13 (1 << 26) /* Bit 26: Break Character Generation Length */
#define LPUART_STAT_RWUID (1 << 27) /* Bit 27: Receive Wake Up Idle Detect */
#define LPUART_STAT_RXINV (1 << 28) /* Bit 28: Receive Data Inversion */
#define LPUART_STAT_MSBF (1 << 29) /* Bit 29: MSB First */
#define LPUART_STAT_RXEDGIF (1 << 30) /* Bit 30: RXD Pin Active Edge Interrupt Flag */
#define LPUART_STAT_LBKDIF (1 << 31) /* Bit 31: LIN Break Detect Interrupt Flag */
/* LPUART Control Register */
#define LPUART_CTRL_PT (1 << 0) /* Bit 0: Parity Type */
# define LPUART_CTRL_PT_EVEN (0 << 0) /* Even parity */
# define LPUART_CTRL_PT_ODD (1 << 0) /* Odd parity */
#define LPUART_CTRL_PE (1 << 1) /* Bit 1: Parity Enable */
#define LPUART_CTRL_ILT (1 << 2) /* Bit 2: Idle Line Type Select */
#define LPUART_CTRL_WAKE (1 << 3) /* Bit 3: Receiver Wakeup Method Select */
#define LPUART_CTRL_M (1 << 4) /* Bit 4: 9-Bit or 8-Bit Mode Select */
#define LPUART_CTRL_RSRC (1 << 5) /* Bit 5: Receiver Source Select */
#define LPUART_CTRL_DOZEEN (1 << 6) /* Bit 6: Doze Enable */
#define LPUART_CTRL_LOOPS (1 << 7) /* Bit 7: Loop Mode Select */
#define LPUART_CTRL_IDLECFG_SHIFT (8) /* Bits 8-10: Idle Configuration */
#define LPUART_CTRL_IDLECFG_MASK (7 << LPUART_CTRL_IDLECFG_SHIFT)
# define LPUART_CTRL_IDLECFG_1 (0 << LPUART_CTRL_IDLECFG_SHIFT) /* 1 idle character */
# define LPUART_CTRL_IDLECFG_2 (1 << LPUART_CTRL_IDLECFG_SHIFT) /* 2 idle characters */
# define LPUART_CTRL_IDLECFG_4 (2 << LPUART_CTRL_IDLECFG_SHIFT) /* 4 idle characters */
# define LPUART_CTRL_IDLECFG_8 (3 << LPUART_CTRL_IDLECFG_SHIFT) /* 8 idle characters */
# define LPUART_CTRL_IDLECFG_16 (4 << LPUART_CTRL_IDLECFG_SHIFT) /* 6 idle characters */
# define LPUART_CTRL_IDLECFG_32 (5 << LPUART_CTRL_IDLECFG_SHIFT) /* 32 idle characters */
# define LPUART_CTRL_IDLECFG_64 (6 << LPUART_CTRL_IDLECFG_SHIFT) /* 64 idle characters */
# define LPUART_CTRL_IDLECFG_128 (7 << LPUART_CTRL_IDLECFG_SHIFT) /* 128 idle characters */
#define LPUART_CTRL_M7 (1 << 11) /* Bit 11: 7-Bit Mode Select */
/* Bits 12-13: Reserved */
#define LPUART_CTRL_MA2IE (1 << 14) /* Bit 14: Match 2 Interrupt Enable */
#define LPUART_CTRL_MA1IE (1 << 15) /* Bit 15: Match 1 Interrupt Enable */
#define LPUART_CTRL_SBK (1 << 16) /* Bit 16: Send Break */
#define LPUART_CTRL_RWU (1 << 17) /* Bit 17: Receiver Wakeup Control */
#define LPUART_CTRL_RE (1 << 18) /* Bit 18: Receiver Enable */
#define LPUART_CTRL_TE (1 << 19) /* Bit 19: Transmitter Enable */
#define LPUART_CTRL_ILIE (1 << 20) /* Bit 20: Idle Line Interrupt Enable */
#define LPUART_CTRL_RIE (1 << 21) /* Bit 21: Receiver Interrupt Enable */
#define LPUART_CTRL_TCIE (1 << 22) /* Bit 22: Transmission Complete Interrupt Enable */
#define LPUART_CTRL_TIE (1 << 23) /* Bit 23: Transmit Interrupt Enable */
#define LPUART_CTRL_PEIE (1 << 24) /* Bit 24: Parity Error Interrupt Enable */
#define LPUART_CTRL_FEIE (1 << 25) /* Bit 25: Framing Error Interrupt Enable */
#define LPUART_CTRL_NEIE (1 << 26) /* Bit 26: Noise Error Interrupt Enable */
#define LPUART_CTRL_ORIE (1 << 27) /* Bit 27: Overrun Interrupt Enable */
#define LPUART_CTRL_TXINV (1 << 28) /* Bit 28: Transmit Data Inversion */
#define LPUART_CTRL_TXDIR (1 << 29) /* Bit 29: TXD Pin Direction in Single-Wire Mode */
#define LPUART_CTRL_R9T8 (1 << 30) /* Bit 30: Receive Bit 9 / Transmit Bit 8 */
#define LPUART_CTRL_R8T9 (1 << 31) /* Bit 31: Receive Bit 8 / Transmit Bit 9 */
#define LPUART_ALL_INTS (LPUART_CTRL_ORIE | LPUART_CTRL_NEIE | LPUART_CTRL_FEIE | \
LPUART_CTRL_PEIE | LPUART_CTRL_TIE | LPUART_CTRL_TCIE | \
LPUART_CTRL_RIE | LPUART_CTRL_ILIE | LPUART_CTRL_MA1IE | \
LPUART_CTRL_MA2IE)
/* LPUART Data Register */
#define LPUART_DATA_SHIFT (0) /* Bits 0-9: Data bits 0-9 */
#define LPUART_DATA_MASK (0x3ff << LPUART_DATA_SHIFT)
/* Bit 10: Reserved */
#define LPUART_DATA_STATUS_SHIFT (11) /* Bit 11: Idle Line status */
#define LPUART_DATA_IDLINE (1 << 11) /* Bit 11: Idle Line */
#define LPUART_DATA_RXEMPT (1 << 12) /* Bit 12: Receive Buffer Empty */
#define LPUART_DATA_FRETSC (1 << 13) /* Bit 13: Frame Error / Transmit Special Character */
#define LPUART_DATA_PARITYE (1 << 14) /* Bit 14: Parity Error */
#define LPUART_DATA_NOISY (1 << 15) /* Bit 15: Noisy */
/* Bits 16-31: Reserved */
/* LPUART Match Address Register */
#define LPUART_MATCH_MA1_SHIFT (0) /* Bits 0-9: Match Address 1 */
#define LPUART_MATCH_MA1_MASK (0x3ff << LPUART_MATCH_MA1_SHIFT)
# define LPUART_MATCH_MA1(n) ((uint32_t)(n) << LPUART_MATCH_MA1_SHIFT)
/* Bits 10-15: Reserved */
#define LPUART_MATCH_MA2_SHIFT (16) /* Bits 16-25: Match Address 2 */
#define LPUART_MATCH_MA2_MASK (0x3ff << LPUART_MATCH_MA2_SHIFT)
# define LPUART_MATCH_MA2(n) ((uint32_t)(n) << LPUART_MATCH_MA2_SHIFT)
/* Bits 26-31: Reserved */
/* LPUART Modem IrDA Register */
#define LPUART_MODIR_TXCTSE (1 << 0) /* Bit nn: Transmitter clear-to-send enable */
#define LPUART_MODIR_TXRTSE (1 << 1) /* Bit nn: Transmitter request-to-send enable */
#define LPUART_MODIR_TXRTSPOL (1 << 2) /* Bit nn: Transmitter request-to-send polarity */
#define LPUART_MODIR_RXRTSE (1 << 3) /* Bit nn: Receiver request-to-send enable */
#define LPUART_MODIR_TXCTSC (1 << 4) /* Bit nn: Transmit CTS Configuration */
# define LPUART_MODIR_TXCTSC_START (0 << 4) /* CTS sampled at start of character */
# define LPUART_MODIR_TXCTSC_IDLE (1 << 4) /* CTS sampled when transmitter idle */
#define LPUART_MODIR_TXCTSSRC (1 << 5) /* Bit nn: Transmit CTS Source */
# define LPUART_MODIR_TXCTSSRC_CTSB (0 << 5) /* Bit nn: CTS input is CTS_B pin */
# define LPUART_MODIR_TXCTSSRC_RXMAT (1 << 5) /* Bit nn: Transmit CTS Source */
/* Bits 6-7: Reserved */
#define LPUART_MODIR_RTSWATER (8) /* Bits 8-9: Receive RTS Configuration */
/* Bits 10-15: Reserved */
#define LPUART_MODIR_TNP_SHIFT (16) /* Bits 16-17: Transmitter narrow pulse */
#define LPUART_MODIR_TNP_MASK (3 << LPUART_MODIR_TNP_SHIFT)
# define LPUART_MODIR_TNP(n) ((uint32_t)((n) - 1) << LPUART_MODIR_TNP_SHIFT) /* n/OSR */
#define LPUART_MODIR_IREN (1 << 18) /* Bit nn: Infrared enable */
/* Bits 19-31: Reserved */
/* LPUART FIFO Register */
#define LPUART_FIFO_RXFIFOSIZE_SHIFT (0) /* Bits 0-2: Receive FIFO. Buffer Depth */
#define LPUART_FIFO_RXFIFOSIZE_MASK (7 << LPUART_FIFO_RXFIFOSIZE_SHIFT)
# define LPUART_FIFO_RXFIFOSIZE_1 (0 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 1 datawords */
# define LPUART_FIFO_RXFIFOSIZE_4 (1 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 4 datawords */
# define LPUART_FIFO_RXFIFOSIZE_8 (2 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 8 datawords */
# define LPUART_FIFO_RXFIFOSIZE_16 (3 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 16 datawords */
# define LPUART_FIFO_RXFIFOSIZE_32 (4 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 32 datawords */
# define LPUART_FIFO_RXFIFOSIZE_64 (5 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 64 datawords */
# define LPUART_FIFO_RXFIFOSIZE_128 (6 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 128 datawords */
# define LPUART_FIFO_RXFIFOSIZE_256 (7 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 256 datawords */
#define LPUART_FIFO_TXFIFOSIZE_SHIFT (4) /* Bits 4-6: Transmit FIFO. Buffer Depth */
#define LPUART_FIFO_TXFIFOSIZE_MASK (7 << LPUART_FIFO_TXFIFOSIZE_SHIFT)
# define LPUART_FIFO_TXFIFOSIZE_1 (0 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 1 datawords */
# define LPUART_FIFO_TXFIFOSIZE_4 (1 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 4 datawords */
# define LPUART_FIFO_TXFIFOSIZE_8 (2 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 8 datawords */
# define LPUART_FIFO_TXFIFOSIZE_16 (3 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 16 datawords */
# define LPUART_FIFO_TXFIFOSIZE_32 (4 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 32 datawords */
# define LPUART_FIFO_TXFIFOSIZE_64 (5 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 64 datawords */
# define LPUART_FIFO_TXFIFOSIZE_128 (6 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 128 datawords */
# define LPUART_FIFO_TXFIFOSIZE_256 (7 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 256 datawords */
#define LPUART_FIFO_TXFE (1 << 7) /* Bit 7: Transmit FIFO Enable */
#define LPUART_FIFO_RXUFE (1 << 8) /* Bit 8: Receive FIFO Underflow Interrupt Enable */
#define LPUART_FIFO_TXOFE (1 << 9) /* Bit 9: Transmit FIFO Overflow Interrupt Enable */
#define LPUART_FIFO_RXIDEN_SHIFT (10) /* Bits 10-12: Receiver Idle Empty Enable */
#define LPUART_FIFO_RXIDEN_MASK (7 << LPUART_FIFO_RXIDEN_SHIFT)
# define LPUART_FIFO_RXIDEN_DISABLE (0 << LPUART_FIFO_RXIDEN_SHIFT) /* Disable RDRF assertion when receiver is idle */
# define LPUART_FIFO_RXIDEN_1 (1 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 1 word */
# define LPUART_FIFO_RXIDEN_2 (2 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 2 words */
# define LPUART_FIFO_RXIDEN_4 (3 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 4 words */
# define LPUART_FIFO_RXIDEN_8 (4 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 8 words */
# define LPUART_FIFO_RXIDEN_16 (5 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 16 words */
# define LPUART_FIFO_RXIDEN_32 (6 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 32 words */
# define LPUART_FIFO_RXIDEN_64 (7 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 64 words */
#define LPUART_FIFO_RXFLUSH (1 << 14) /* Bit 14: Receive FIFO/Buffer Flush */
#define LPUART_FIFO_TXFLUSH (1 << 15) /* Bit 15: Transmit FIFO/Buffer Flush */
#define LPUART_FIFO_RXUF (1 << 16) /* Bit 16: Receiver Buffer Underflow Flag */
#define LPUART_FIFO_TXOF (1 << 17) /* Bit 17: Transmitter Buffer Overflow Flag */
/* Bits 18-21: Reserved */
#define LPUART_FIFO_RXEMPT (1 << 22) /* Bit 22: Receive Buffer/FIFO Empty */
#define LPUART_FIFO_TXEMPT (1 << 23) /* Bit 23: Transmit Buffer/FIFO Empty */
/* Bits 24-31: Reserved */
/* LPUART Watermark Register */
#define LPUART_WATER_TXWATER_SHIFT (0) /* Bits 0-1: Transmit Watermark */
#define LPUART_WATER_TXWATER_MASK (3 << LPUART_WATER_TXWATER_SHIFT)
# define LPUART_WATER_TXWATER(n) ((uint32_t)(n) << LPUART_WATER_TXWATER_SHIFT)
/* Bits 2-7: Reserved */
#define LPUART_WATER_TXCOUNT_SHIFT (8) /* Bits 8-10:Transmit Counter */
#define LPUART_WATER_TXCOUNT_MASK (7 << LPUART_WATER_TXCOUNT_SHIFT)
# define LPUART_WATER_TXCOUNT(n) ((uint32_t)(n) << LPUART_WATER_TXCOUNT_SHIFT)
/* Bits 11-15: Reserved */
#define LPUART_WATER_RXWATER_SHIFT (16) /* Bits 16-17: Receive Watermark */
#define LPUART_WATER_RXWATER_MASK (3 << LPUART_WATER_RXWATER_SHIFT)
# define LPUART_WATER_RXWATER(n) ((uint32_t)(n) << LPUART_WATER_RXWATER_SHIFT)
/* Bits 18-23: Reserved */
#define LPUART_WATER_RXCOUNT_SHIFT (24) /* Bits 24-26: Receive Counter */
#define LPUART_WATER_RXCOUNT_MASK (7 << LPUART_WATER_RXCOUNT_SHIFT)
# define LPUART_WATER_RXCOUNT(n) ((uint32_t)(n) << LPUART_WATER_RXCOUNT_SHIFT)
/* Bits 27-31: Reserved */
#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_LPUART_H */
arch/arm/src/imxrt/chip/imxrt_memorymap.h
-55
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@@ -1,55 +0,0 @@
/************************************************************************************
* arch/arm/src/imxrt/chip/imxrt_memorymap.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_MEMORYMAP_H
#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_MEMORYMAP_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#if defined(CONFIG_ARCH_FAMILY_IMXRT102x)
# include "chip/rt102x/imxrt102x_memorymap.h"
#elif defined(CONFIG_ARCH_FAMILY_IMXRT105x)
# include "chip/rt105x/imxrt105x_memorymap.h"
#elif defined(CONFIG_ARCH_FAMILY_IMXRT106x)
# include "chip/rt106x/imxrt106x_memorymap.h"
#else
# error Unrecognized i.MX RT architecture
#endif
#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_MEMORYMAP_H */
arch/arm/src/imxrt/chip/imxrt_ocotp.h
-429
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@@ -1,429 +0,0 @@
/************************************************************************************************************************************
* arch/arm/src/imxrt/chip/imxrt_ocotp.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_OCOTP_H
#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_OCOTP_H
/* The OCOTP IP block provides a set of register to access the On Chip OPT.
* It also provides a shadow image of the 64 OTP entries that are read only
* memory addressable (OCOTP Shadow Offsets). To read or write the actual
* OTP, OCOTP Indexes are used.
*/
/************************************************************************************************************************************
* Included Files
************************************************************************************************************************************/
#include <nuttx/config.h>
#include "chip/imxrt_memorymap.h"
/************************************************************************************************************************************
* Pre-processor Definitions
************************************************************************************************************************************/
/* Register Offsets *****************************************************************/
#define IMXRT_OCOTP_CTRL_OFFSET 0x0000 /* OTP Controller Control Register */
#define IMXRT_OCOTP_CTRL_SET_OFFSET 0x0004 /* OTP Controller Control Register */
#define IMXRT_OCOTP_CTRL_CLR_OFFSET 0x0008 /* OTP Controller Control Register */
#define IMXRT_OCOTP_CTRL_TOG_OFFSET 0x000c /* OTP Controller Control Register */
#define IMXRT_OCOTP_TIMING_OFFSET 0x0010 /* OTP Controller Timing Register */
#define IMXRT_OCOTP_DATA_OFFSET 0x0020 /* OTP Controller Write Data Register */
#define IMXRT_OCOTP_READ_CTRL_OFFSET 0x0030 /* OTP Controller Write Data Register */
#define IMXRT_OCOTP_READ_FUSE_DATA_OFFSET 0x0040 /* OTP Controller Read Data Register */
#define IMXRT_OCOTP_SW_STICKY_OFFSET 0x0050 /* Sticky bit Register */
#define IMXRT_OCOTP_SCS_OFFSET 0x0060 /* Software Controllable Signals Register */
#define IMXRT_OCOTP_SCS_SET_OFFSET 0x0064 /* Software Controllable Signals Register */
#define IMXRT_OCOTP_SCS_CLR_OFFSET 0x0068 /* Software Controllable Signals Register */
#define IMXRT_OCOTP_SCS_TOG_OFFSET 0x006c /* Software Controllable Signals Register */
#define IMXRT_OCOTP_CRC_ADDR_OFFSET 0x0070 /* OTP Controller CRC test address */
#define IMXRT_OCOTP_CRC_VALUE_OFFSET 0x0080 /* OTP Controller CRC Value Register */
#define IMXRT_OCOTP_VERSION_OFFSET 0x0090 /* OTP Controller Version Register */
#define IMXRT_OCOTP_TIMING2_OFFSET 0x0100 /* OTP Controller Timing Register */
/* OCOTP Shadow Offsets *************************************************************/
#define IMXRT_OCOTP_LOCK_OFFSET 0x0400 /* Value of OTP Bank0 Word0 (Lock controls) */
#define IMXRT_OCOTP_CFG0_OFFSET 0x0410 /* Value of OTP Bank0 Word1 (Configuration and Manufacturing */
#define IMXRT_OCOTP_CFG1_OFFSET 0x0420 /* Value of OTP Bank0 Word2 (Configuration and Manufacturing */
#define IMXRT_OCOTP_CFG2_OFFSET 0x0430 /* Value of OTP Bank0 Word3 (Configuration and Manufacturing */
#define IMXRT_OCOTP_CFG3_OFFSET 0x0440 /* Value of OTP Bank0 Word4 (Configuration and Manufacturing */
#define IMXRT_OCOTP_CFG4_OFFSET 0x0450 /* Value of OTP Bank0 Word5 (Configuration and Manufacturing */
#define IMXRT_OCOTP_CFG5_OFFSET 0x0460 /* Value of OTP Bank0 Word6 (Configuration and Manufacturing */
#define IMXRT_OCOTP_CFG6_OFFSET 0x0470 /* Value of OTP Bank0 Word7 (Configuration and Manufacturing */
#define IMXRT_OCOTP_MEM0_OFFSET 0x0480 /* Value of OTP Bank1 Word0 (Memory Related Info.) */
#define IMXRT_OCOTP_MEM1_OFFSET 0x0490 /* Value of OTP Bank1 Word1 (Memory Related Info.) */
#define IMXRT_OCOTP_MEM2_OFFSET 0x04a0 /* Value of OTP Bank1 Word2 (Memory Related Info.) */
#define IMXRT_OCOTP_MEM3_OFFSET 0x04b0 /* Value of OTP Bank1 Word3 (Memory Related Info.) */
#define IMXRT_OCOTP_MEM4_OFFSET 0x04c0 /* Value of OTP Bank1 Word4 (Memory Related Info.) */
#define IMXRT_OCOTP_ANA0_OFFSET 0x04d0 /* Value of OTP Bank1 Word5 (Analog Info.) */
#define IMXRT_OCOTP_ANA1_OFFSET 0x04e0 /* Value of OTP Bank1 Word6 (Analog Info.) */
#define IMXRT_OCOTP_ANA2_OFFSET 0x04f0 /* Value of OTP Bank1 Word7 (Analog Info.) */
#define IMXRT_OCOTP_OTPMK0_OFFSET 0x0500 /* Value of OTP Bank2 Word0 (OTPMK Key) */
#define IMXRT_OCOTP_OTPMK1_OFFSET 0x0510 /* Value of OTP Bank2 Word1 (OTPMK Key) */
#define IMXRT_OCOTP_OTPMK2_OFFSET 0x0520 /* Value of OTP Bank2 Word2 (OTPMK Key) */
#define IMXRT_OCOTP_OTPMK3_OFFSET 0x0530 /* Value of OTP Bank2 Word3 (OTPMK Key) */
#define IMXRT_OCOTP_OTPMK4_OFFSET 0x0540 /* Value of OTP Bank2 Word4 (OTPMK Key) */
#define IMXRT_OCOTP_OTPMK5_OFFSET 0x0550 /* Value of OTP Bank2 Word5 (OTPMK Key) */
#define IMXRT_OCOTP_OTPMK6_OFFSET 0x0560 /* Value of OTP Bank2 Word6 (OTPMK Key) */
#define IMXRT_OCOTP_OTPMK7_OFFSET 0x0570 /* Value of OTP Bank2 Word7 (OTPMK Key) */
#define IMXRT_OCOTP_SRK0_OFFSET 0x0580 /* Shadow Register for OTP Bank3 Word0 (SRK Hash) */
#define IMXRT_OCOTP_SRK1_OFFSET 0x0590 /* Shadow Register for OTP Bank3 Word1 (SRK Hash) */
#define IMXRT_OCOTP_SRK2_OFFSET 0x05a0 /* Shadow Register for OTP Bank3 Word2 (SRK Hash) */
#define IMXRT_OCOTP_SRK3_OFFSET 0x05b0 /* Shadow Register for OTP Bank3 Word3 (SRK Hash) */
#define IMXRT_OCOTP_SRK4_OFFSET 0x05c0 /* Shadow Register for OTP Bank3 Word4 (SRK Hash) */
#define IMXRT_OCOTP_SRK5_OFFSET 0x05d0 /* Shadow Register for OTP Bank3 Word5 (SRK Hash) */
#define IMXRT_OCOTP_SRK6_OFFSET 0x05e0 /* Shadow Register for OTP Bank3 Word6 (SRK Hash) */
#define IMXRT_OCOTP_SRK7_OFFSET 0x05f0 /* Shadow Register for OTP Bank3 Word7 (SRK Hash) */
#define IMXRT_OCOTP_SJC_RESP0_OFFSET 0x0600 /* Value of OTP Bank4 Word0 (Secure JTAG Response Field) */
#define IMXRT_OCOTP_SJC_RESP1_OFFSET 0x0610 /* Value of OTP Bank4 Word1 (Secure JTAG Response Field) */
#define IMXRT_OCOTP_MAC0_OFFSET 0x0620 /* Value of OTP Bank4 Word2 (MAC Address) */
#define IMXRT_OCOTP_MAC1_OFFSET 0x0630 /* Value of OTP Bank4 Word3 (MAC Address) */
#define IMXRT_OCOTP_MAC2_OFFSET 0x0640 /* Value of OTP Bank4 Word4 (MAC Address) */
#define IMXRT_OCOTP_OTPMK_CRC32_OFFSET 0x0650 /* Value of OTP Bank4 Word5 (CRC Key) */
#define IMXRT_OCOTP_SW_GP1_OFFSET 0x0680 /* Value of OTP Bank5 Word0 (SW GP1) */
#define IMXRT_OCOTP_SW_GP20_OFFSET 0x0690 /* Value of OTP Bank5 Word1 (SW GP2) */
#define IMXRT_OCOTP_SW_GP21_OFFSET 0x06a0 /* Value of OTP Bank5 Word2 (SW GP2) */
#define IMXRT_OCOTP_SW_GP22_OFFSET 0x06b0 /* Value of OTP Bank5 Word3 (SW GP2) */
#define IMXRT_OCOTP_SW_GP23_OFFSET 0x06c0 /* Value of OTP Bank5 Word4 (SW GP2) */
#define IMXRT_OCOTP_MISC_CONF0_OFFSET 0x06d0 /* Value of OTP Bank5 Word5 (Misc Conf) */
#define IMXRT_OCOTP_MISC_CONF1_OFFSET 0x06e0 /* Value of OTP Bank5 Word6 (Misc Conf) */
#define IMXRT_OCOTP_SRK_REVOKE_OFFSET 0x06f0 /* Value of OTP Bank5 Word7 (SRK Revoke) */
#define IMXRT_OCOTP_ROM_PATCH0_OFFSET 0x0800 /* Value of OTP Bank6 Word0 (ROM Patch) */
#define IMXRT_OCOTP_ROM_PATCH1_OFFSET 0x0810 /* Value of OTP Bank6 Word1 (ROM Patch) */
#define IMXRT_OCOTP_ROM_PATCH2_OFFSET 0x0820 /* Value of OTP Bank6 Word2 (ROM Patch) */
#define IMXRT_OCOTP_ROM_PATCH3_OFFSET 0x0830 /* Value of OTP Bank6 Word3 (ROM Patch) */
#define IMXRT_OCOTP_ROM_PATCH4_OFFSET 0x0840 /* Value of OTP Bank6 Word4 (ROM Patch) */
#define IMXRT_OCOTP_ROM_PATCH5_OFFSET 0x0850 /* Value of OTP Bank6 Word5 (ROM Patch) */
#define IMXRT_OCOTP_ROM_PATCH6_OFFSET 0x0860 /* Value of OTP Bank6 Word6 (ROM Patch) */
#define IMXRT_OCOTP_ROM_PATCH7_OFFSET 0x0870 /* Value of OTP Bank6 Word7 (ROM Patch) */
#define IMXRT_OCOTP_GP30_OFFSET 0x0880 /* Value of OTP Bank7 Word0 (GP3) */
#define IMXRT_OCOTP_GP31_OFFSET 0x0890 /* Value of OTP Bank7 Word1 (GP3) */
#define IMXRT_OCOTP_GP32_OFFSET 0x08a0 /* Value of OTP Bank7 Word2 (GP3) */
#define IMXRT_OCOTP_GP33_OFFSET 0x08b0 /* Value of OTP Bank7 Word3 (GP3) */
#define IMXRT_OCOTP_GP40_OFFSET 0x08c0 /* Value of OTP Bank7 Word4 (GP4) */
#define IMXRT_OCOTP_GP41_OFFSET 0x08d0 /* Value of OTP Bank7 Word5 (GP4) */
#define IMXRT_OCOTP_GP42_OFFSET 0x08e0 /* Value of OTP Bank7 Word6 (GP4) */
#define IMXRT_OCOTP_GP43_OFFSET 0x08f0 /* Value of OTP Bank7 Word7 (GP4) */
/* OCOTP Indexes *****************************************************************/
#define IMXRT_OCOTP_O2I(offset) (((offset) - IMXRT_OCOTP_LOCK_OFFSET) >> 4)
#define IMXRT_OCOTP_LOCK_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_LOCK_OFFSET) /* Value of OTP Bank0 Word0 (Lock controls) */
#define IMXRT_OCOTP_CFG0_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_CFG0_OFFSET) /* Value of OTP Bank0 Word1 (Configuration and Manufacturing */
#define IMXRT_OCOTP_CFG1_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_CFG1_OFFSET) /* Value of OTP Bank0 Word2 (Configuration and Manufacturing */
#define IMXRT_OCOTP_CFG2_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_CFG2_OFFSET) /* Value of OTP Bank0 Word3 (Configuration and Manufacturing */
#define IMXRT_OCOTP_CFG3_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_CFG3_OFFSET) /* Value of OTP Bank0 Word4 (Configuration and Manufacturing */
#define IMXRT_OCOTP_CFG4_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_CFG4_OFFSET) /* Value of OTP Bank0 Word5 (Configuration and Manufacturing */
#define IMXRT_OCOTP_CFG5_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_CFG5_OFFSET) /* Value of OTP Bank0 Word6 (Configuration and Manufacturing */
#define IMXRT_OCOTP_CFG6_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_CFG6_OFFSET) /* Value of OTP Bank0 Word7 (Configuration and Manufacturing */
#define IMXRT_OCOTP_MEM0_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_MEM0_OFFSET) /* Value of OTP Bank1 Word0 (Memory Related Info.) */
#define IMXRT_OCOTP_MEM1_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_MEM1_OFFSET) /* Value of OTP Bank1 Word1 (Memory Related Info.) */
#define IMXRT_OCOTP_MEM2_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_MEM2_OFFSET) /* Value of OTP Bank1 Word2 (Memory Related Info.) */
#define IMXRT_OCOTP_MEM3_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_MEM3_OFFSET) /* Value of OTP Bank1 Word3 (Memory Related Info.) */
#define IMXRT_OCOTP_MEM4_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_MEM4_OFFSET) /* Value of OTP Bank1 Word4 (Memory Related Info.) */
#define IMXRT_OCOTP_ANA0_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_ANA0_OFFSET) /* Value of OTP Bank1 Word5 (Analog Info.) */
#define IMXRT_OCOTP_ANA1_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_ANA1_OFFSET) /* Value of OTP Bank1 Word6 (Analog Info.) */
#define IMXRT_OCOTP_ANA2_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_ANA2_OFFSET) /* Value of OTP Bank1 Word7 (Analog Info.) */
#define IMXRT_OCOTP_OTPMK0_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_OTPMK0_OFFSET) /* Value of OTP Bank2 Word0 (OTPMK Key) */
#define IMXRT_OCOTP_OTPMK1_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_OTPMK1_OFFSET) /* Value of OTP Bank2 Word1 (OTPMK Key) */
#define IMXRT_OCOTP_OTPMK2_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_OTPMK2_OFFSET) /* Value of OTP Bank2 Word2 (OTPMK Key) */
#define IMXRT_OCOTP_OTPMK3_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_OTPMK3_OFFSET) /* Value of OTP Bank2 Word3 (OTPMK Key) */
#define IMXRT_OCOTP_OTPMK4_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_OTPMK4_OFFSET) /* Value of OTP Bank2 Word4 (OTPMK Key) */
#define IMXRT_OCOTP_OTPMK5_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_OTPMK5_OFFSET) /* Value of OTP Bank2 Word5 (OTPMK Key) */
#define IMXRT_OCOTP_OTPMK6_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_OTPMK6_OFFSET) /* Value of OTP Bank2 Word6 (OTPMK Key) */
#define IMXRT_OCOTP_OTPMK7_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_OTPMK7_OFFSET) /* Value of OTP Bank2 Word7 (OTPMK Key) */
#define IMXRT_OCOTP_SRK0_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_SRK0_OFFSET) /* Shadow Register for OTP Bank3 Word0 (SRK Hash) */
#define IMXRT_OCOTP_SRK1_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_SRK1_OFFSET) /* Shadow Register for OTP Bank3 Word1 (SRK Hash) */
#define IMXRT_OCOTP_SRK2_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_SRK2_OFFSET) /* Shadow Register for OTP Bank3 Word2 (SRK Hash) */
#define IMXRT_OCOTP_SRK3_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_SRK3_OFFSET) /* Shadow Register for OTP Bank3 Word3 (SRK Hash) */
#define IMXRT_OCOTP_SRK4_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_SRK4_OFFSET) /* Shadow Register for OTP Bank3 Word4 (SRK Hash) */
#define IMXRT_OCOTP_SRK5_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_SRK5_OFFSET) /* Shadow Register for OTP Bank3 Word5 (SRK Hash) */
#define IMXRT_OCOTP_SRK6_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_SRK6_OFFSET) /* Shadow Register for OTP Bank3 Word6 (SRK Hash) */
#define IMXRT_OCOTP_SRK7_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_SRK7_OFFSET) /* Shadow Register for OTP Bank3 Word7 (SRK Hash) */
#define IMXRT_OCOTP_SJC_RESP0_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_SJC_RESP0_OFFSET) /* Value of OTP Bank4 Word0 (Secure JTAG Response Field) */
#define IMXRT_OCOTP_SJC_RESP1_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_SJC_RESP1_OFFSET) /* Value of OTP Bank4 Word1 (Secure JTAG Response Field) */
#define IMXRT_OCOTP_MAC0_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_MAC0_OFFSET) /* Value of OTP Bank4 Word2 (MAC Address) */
#define IMXRT_OCOTP_MAC1_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_MAC1_OFFSET) /* Value of OTP Bank4 Word3 (MAC Address) */
#define IMXRT_OCOTP_MAC2_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_MAC2_OFFSET) /* Value of OTP Bank4 Word4 (MAC Address) */
#define IMXRT_OCOTP_OTPMK_CRC32_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_OTPMK_CRC32_OFFSET) /* Value of OTP Bank4 Word5 (CRC Key) */
#define IMXRT_OCOTP_SW_GP1_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_SW_GP1_OFFSET) /* Value of OTP Bank5 Word0 (SW GP1) */
#define IMXRT_OCOTP_SW_GP20_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_SW_GP20_OFFSET) /* Value of OTP Bank5 Word1 (SW GP2) */
#define IMXRT_OCOTP_SW_GP21_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_SW_GP21_OFFSET) /* Value of OTP Bank5 Word2 (SW GP2) */
#define IMXRT_OCOTP_SW_GP22_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_SW_GP22_OFFSET) /* Value of OTP Bank5 Word3 (SW GP2) */
#define IMXRT_OCOTP_SW_GP23_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_SW_GP23_OFFSET) /* Value of OTP Bank5 Word4 (SW GP2) */
#define IMXRT_OCOTP_MISC_CONF0_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_MISC_CONF0_OFFSET) /* Value of OTP Bank5 Word5 (Misc Conf) */
#define IMXRT_OCOTP_MISC_CONF1_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_MISC_CONF1_OFFSET) /* Value of OTP Bank5 Word6 (Misc Conf) */
#define IMXRT_OCOTP_SRK_REVOKE_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_SRK_REVOKE_OFFSET) /* Value of OTP Bank5 Word7 (SRK Revoke) */
#define IMXRT_OCOTP_O2IP(offset) (((offset) - (IMXRT_OCOTP_LOCK_OFFSET + 0x100)) >> 4)
#define IMXRT_OCOTP_ROM_PATCH0_INDEX IMXRT_OCOTP_O2IP(IMXRT_OCOTP_ROM_PATCH0_OFFSET) /* Value of OTP Bank6 Word0 (ROM Patch) */
#define IMXRT_OCOTP_ROM_PATCH1_INDEX IMXRT_OCOTP_O2IP(IMXRT_OCOTP_ROM_PATCH1_OFFSET) /* Value of OTP Bank6 Word1 (ROM Patch) */
#define IMXRT_OCOTP_ROM_PATCH2_INDEX IMXRT_OCOTP_O2IP(IMXRT_OCOTP_ROM_PATCH2_OFFSET) /* Value of OTP Bank6 Word2 (ROM Patch) */
#define IMXRT_OCOTP_ROM_PATCH3_INDEX IMXRT_OCOTP_O2IP(IMXRT_OCOTP_ROM_PATCH3_OFFSET) /* Value of OTP Bank6 Word3 (ROM Patch) */
#define IMXRT_OCOTP_ROM_PATCH4_INDEX IMXRT_OCOTP_O2IP(IMXRT_OCOTP_ROM_PATCH4_OFFSET) /* Value of OTP Bank6 Word4 (ROM Patch) */
#define IMXRT_OCOTP_ROM_PATCH5_INDEX IMXRT_OCOTP_O2IP(IMXRT_OCOTP_ROM_PATCH5_OFFSET) /* Value of OTP Bank6 Word5 (ROM Patch) */
#define IMXRT_OCOTP_ROM_PATCH6_INDEX IMXRT_OCOTP_O2IP(IMXRT_OCOTP_ROM_PATCH6_OFFSET) /* Value of OTP Bank6 Word6 (ROM Patch) */
#define IMXRT_OCOTP_ROM_PATCH7_INDEX IMXRT_OCOTP_O2IP(IMXRT_OCOTP_ROM_PATCH7_OFFSET) /* Value of OTP Bank6 Word7 (ROM Patch) */
#define IMXRT_OCOTP_GP30_INDEX IMXRT_OCOTP_O2IP(IMXRT_OCOTP_GP30_OFFSET) /* Value of OTP Bank7 Word0 (GP3) */
#define IMXRT_OCOTP_GP31_INDEX IMXRT_OCOTP_O2IP(IMXRT_OCOTP_GP31_OFFSET) /* Value of OTP Bank7 Word1 (GP3) */
#define IMXRT_OCOTP_GP32_INDEX IMXRT_OCOTP_O2IP(IMXRT_OCOTP_GP32_OFFSET) /* Value of OTP Bank7 Word2 (GP3) */
#define IMXRT_OCOTP_GP33_INDEX IMXRT_OCOTP_O2IP(IMXRT_OCOTP_GP33_OFFSET) /* Value of OTP Bank7 Word3 (GP3) */
#define IMXRT_OCOTP_GP40_INDEX IMXRT_OCOTP_O2IP(IMXRT_OCOTP_GP40_OFFSET) /* Value of OTP Bank7 Word4 (GP4) */
#define IMXRT_OCOTP_GP41_INDEX IMXRT_OCOTP_O2IP(IMXRT_OCOTP_GP41_OFFSET) /* Value of OTP Bank7 Word5 (GP4) */
#define IMXRT_OCOTP_GP42_INDEX IMXRT_OCOTP_O2IP(IMXRT_OCOTP_GP42_OFFSET) /* Value of OTP Bank7 Word6 (GP4) */
#define IMXRT_OCOTP_GP43_INDEX IMXRT_OCOTP_O2IP(IMXRT_OCOTP_GP43_OFFSET) /* Value of OTP Bank7 Word7 (GP4) */
/* Register addresses ***********************************************************************************************************************/
#define IMXRT_OCOTP_CTRL (IMXRT_OCOTP_BASE + IMXRT_OCOTP_CTRL_OFFSET) /* OTP Controller Control Register */
#define IMXRT_OCOTP_CTRL_SET (IMXRT_OCOTP_BASE + IMXRT_OCOTP_CTRL_SET_OFFSET) /* OTP Controller Control Register */
#define IMXRT_OCOTP_CTRL_CLR (IMXRT_OCOTP_BASE + IMXRT_OCOTP_CTRL_CLR_OFFSET) /* OTP Controller Control Register */
#define IMXRT_OCOTP_CTRL_TOG (IMXRT_OCOTP_BASE + IMXRT_OCOTP_CTRL_TOG_OFFSET) /* OTP Controller Control Register */
#define IMXRT_OCOTP_TIMING (IMXRT_OCOTP_BASE + IMXRT_OCOTP_TIMING_OFFSET) /* OTP Controller Timing Register */
#define IMXRT_OCOTP_DATA (IMXRT_OCOTP_BASE + IMXRT_OCOTP_DATA_OFFSET) /* OTP Controller Write Data Register */
#define IMXRT_OCOTP_READ_CTRL (IMXRT_OCOTP_BASE + IMXRT_OCOTP_READ_CTRL_OFFSET) /* OTP Controller Write Data Register */
#define IMXRT_OCOTP_READ_FUSE_DATA (IMXRT_OCOTP_BASE + IMXRT_OCOTP_READ_FUSE_DATA_OFFSET) /* OTP Controller Read Data Register */
#define IMXRT_OCOTP_SW_STICKY (IMXRT_OCOTP_BASE + IMXRT_OCOTP_SW_STICKY_OFFSET) /* Sticky bit Register */
#define IMXRT_OCOTP_SCS (IMXRT_OCOTP_BASE + IMXRT_OCOTP_SCS_OFFSET) /* Software Controllable Signals Register */
#define IMXRT_OCOTP_SCS_SET (IMXRT_OCOTP_BASE + IMXRT_OCOTP_SCS_SET_OFFSET) /* Software Controllable Signals Register */
#define IMXRT_OCOTP_SCS_CLR (IMXRT_OCOTP_BASE + IMXRT_OCOTP_SCS_CLR_OFFSET) /* Software Controllable Signals Register */
#define IMXRT_OCOTP_SCS_TOG (IMXRT_OCOTP_BASE + IMXRT_OCOTP_SCS_TOG_OFFSET) /* Software Controllable Signals Register */
#define IMXRT_OCOTP_CRC_ADDR (IMXRT_OCOTP_BASE + IMXRT_OCOTP_CRC_ADDR_OFFSET) /* OTP Controller CRC test address */
#define IMXRT_OCOTP_CRC_VALUE (IMXRT_OCOTP_BASE + IMXRT_OCOTP_CRC_VALUE_OFFSET) /* OTP Controller CRC Value Register */
#define IMXRT_OCOTP_VERSION (IMXRT_OCOTP_BASE + IMXRT_OCOTP_VERSION_OFFSET) /* OTP Controller Version Register */
#define IMXRT_OCOTP_TIMING2 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_TIMING2_OFFSET) /* OTP Controller Timing Register */
#define IMXRT_OCOTP_LOCK (IMXRT_OCOTP_BASE + IMXRT_OCOTP_LOCK_OFFSET) /* Value of OTP Bank0 Word0 (Lock controls) */
#define IMXRT_OCOTP_CFG0 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_CFG0_OFFSET) /* Value of OTP Bank0 Word1 (Configuration and Manufacturing */
#define IMXRT_OCOTP_CFG1 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_CFG1_OFFSET) /* Value of OTP Bank0 Word2 (Configuration and Manufacturing */
#define IMXRT_OCOTP_CFG2 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_CFG2_OFFSET) /* Value of OTP Bank0 Word3 (Configuration and Manufacturing */
#define IMXRT_OCOTP_CFG3 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_CFG3_OFFSET) /* Value of OTP Bank0 Word4 (Configuration and Manufacturing */
#define IMXRT_OCOTP_CFG4 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_CFG4_OFFSET) /* Value of OTP Bank0 Word5 (Configuration and Manufacturing */
#define IMXRT_OCOTP_CFG5 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_CFG5_OFFSET) /* Value of OTP Bank0 Word6 (Configuration and Manufacturing */
#define IMXRT_OCOTP_CFG6 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_CFG6_OFFSET) /* Value of OTP Bank0 Word7 (Configuration and Manufacturing */
#define IMXRT_OCOTP_MEM0 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_MEM0_OFFSET) /* Value of OTP Bank1 Word0 (Memory Related Info.) */
#define IMXRT_OCOTP_MEM1 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_MEM1_OFFSET) /* Value of OTP Bank1 Word1 (Memory Related Info.) */
#define IMXRT_OCOTP_MEM2 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_MEM2_OFFSET) /* Value of OTP Bank1 Word2 (Memory Related Info.) */
#define IMXRT_OCOTP_MEM3 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_MEM3_OFFSET) /* Value of OTP Bank1 Word3 (Memory Related Info.) */
#define IMXRT_OCOTP_MEM4 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_MEM4_OFFSET) /* Value of OTP Bank1 Word4 (Memory Related Info.) */
#define IMXRT_OCOTP_ANA0 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_ANA0_OFFSET) /* Value of OTP Bank1 Word5 (Analog Info.) */
#define IMXRT_OCOTP_ANA1 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_ANA1_OFFSET) /* Value of OTP Bank1 Word6 (Analog Info.) */
#define IMXRT_OCOTP_ANA2 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_ANA2_OFFSET) /* Value of OTP Bank1 Word7 (Analog Info.) */
#define IMXRT_OCOTP_OTPMK0 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_OTPMK0_OFFSET) /* Value of OTP Bank2 Word0 (OTPMK Key) */
#define IMXRT_OCOTP_OTPMK1 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_OTPMK1_OFFSET) /* Value of OTP Bank2 Word1 (OTPMK Key) */
#define IMXRT_OCOTP_OTPMK2 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_OTPMK2_OFFSET) /* Value of OTP Bank2 Word2 (OTPMK Key) */
#define IMXRT_OCOTP_OTPMK3 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_OTPMK3_OFFSET) /* Value of OTP Bank2 Word3 (OTPMK Key) */
#define IMXRT_OCOTP_OTPMK4 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_OTPMK4_OFFSET) /* Value of OTP Bank2 Word4 (OTPMK Key) */
#define IMXRT_OCOTP_OTPMK5 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_OTPMK5_OFFSET) /* Value of OTP Bank2 Word5 (OTPMK Key) */
#define IMXRT_OCOTP_OTPMK6 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_OTPMK6_OFFSET) /* Value of OTP Bank2 Word6 (OTPMK Key) */
#define IMXRT_OCOTP_OTPMK7 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_OTPMK7_OFFSET) /* Value of OTP Bank2 Word7 (OTPMK Key) */
#define IMXRT_OCOTP_SRK0 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_SRK0_OFFSET) /* Shadow Register for OTP Bank3 Word0 (SRK Hash) */
#define IMXRT_OCOTP_SRK1 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_SRK1_OFFSET) /* Shadow Register for OTP Bank3 Word1 (SRK Hash) */
#define IMXRT_OCOTP_SRK2 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_SRK2_OFFSET) /* Shadow Register for OTP Bank3 Word2 (SRK Hash) */
#define IMXRT_OCOTP_SRK3 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_SRK3_OFFSET) /* Shadow Register for OTP Bank3 Word3 (SRK Hash) */
#define IMXRT_OCOTP_SRK4 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_SRK4_OFFSET) /* Shadow Register for OTP Bank3 Word4 (SRK Hash) */
#define IMXRT_OCOTP_SRK5 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_SRK5_OFFSET) /* Shadow Register for OTP Bank3 Word5 (SRK Hash) */
#define IMXRT_OCOTP_SRK6 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_SRK6_OFFSET) /* Shadow Register for OTP Bank3 Word6 (SRK Hash) */
#define IMXRT_OCOTP_SRK7 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_SRK7_OFFSET) /* Shadow Register for OTP Bank3 Word7 (SRK Hash) */
#define IMXRT_OCOTP_SJC_RESP0 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_SJC_RESP0_OFFSET) /* Value of OTP Bank4 Word0 (Secure JTAG Response Field) */
#define IMXRT_OCOTP_SJC_RESP1 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_SJC_RESP1_OFFSET) /* Value of OTP Bank4 Word1 (Secure JTAG Response Field) */
#define IMXRT_OCOTP_MAC0 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_MAC0_OFFSET) /* Value of OTP Bank4 Word2 (MAC Address) */
#define IMXRT_OCOTP_MAC1 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_MAC1_OFFSET) /* Value of OTP Bank4 Word3 (MAC Address) */
#define IMXRT_OCOTP_MAC2 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_MAC2_OFFSET) /* Value of OTP Bank4 Word4 (MAC Address) */
#define IMXRT_OCOTP_OTPMK_CRC32 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_OTPMK_CRC32_OFFSET) /* Value of OTP Bank4 Word5 (CRC Key) */
#define IMXRT_OCOTP_SW_GP1 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_SW_GP1_OFFSET) /* Value of OTP Bank5 Word0 (SW GP1) */
#define IMXRT_OCOTP_SW_GP20 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_SW_GP20_OFFSET) /* Value of OTP Bank5 Word1 (SW GP2) */
#define IMXRT_OCOTP_SW_GP21 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_SW_GP21_OFFSET) /* Value of OTP Bank5 Word2 (SW GP2) */
#define IMXRT_OCOTP_SW_GP22 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_SW_GP22_OFFSET) /* Value of OTP Bank5 Word3 (SW GP2) */
#define IMXRT_OCOTP_SW_GP23 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_SW_GP23_OFFSET) /* Value of OTP Bank5 Word4 (SW GP2) */
#define IMXRT_OCOTP_MISC_CONF0 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_MISC_CONF0_OFFSET) /* Value of OTP Bank5 Word5 (Misc Conf) */
#define IMXRT_OCOTP_MISC_CONF1 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_MISC_CONF1_OFFSET) /* Value of OTP Bank5 Word6 (Misc Conf) */
#define IMXRT_OCOTP_SRK_REVOKE (IMXRT_OCOTP_BASE + IMXRT_OCOTP_SRK_REVOKE_OFFSET) /* Value of OTP Bank5 Word7 (SRK Revoke) */
#define IMXRT_OCOTP_ROM_PATCH0 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_ROM_PATCH0_OFFSET) /* Value of OTP Bank6 Word0 (ROM Patch) */
#define IMXRT_OCOTP_ROM_PATCH1 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_ROM_PATCH1_OFFSET) /* Value of OTP Bank6 Word1 (ROM Patch) */
#define IMXRT_OCOTP_ROM_PATCH2 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_ROM_PATCH2_OFFSET) /* Value of OTP Bank6 Word2 (ROM Patch) */
#define IMXRT_OCOTP_ROM_PATCH3 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_ROM_PATCH3_OFFSET) /* Value of OTP Bank6 Word3 (ROM Patch) */
#define IMXRT_OCOTP_ROM_PATCH4 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_ROM_PATCH4_OFFSET) /* Value of OTP Bank6 Word4 (ROM Patch) */
#define IMXRT_OCOTP_ROM_PATCH5 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_ROM_PATCH5_OFFSET) /* Value of OTP Bank6 Word5 (ROM Patch) */
#define IMXRT_OCOTP_ROM_PATCH6 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_ROM_PATCH6_OFFSET) /* Value of OTP Bank6 Word6 (ROM Patch) */
#define IMXRT_OCOTP_ROM_PATCH7 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_ROM_PATCH7_OFFSET) /* Value of OTP Bank6 Word7 (ROM Patch) */
#define IMXRT_OCOTP_GP30 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_GP30_OFFSET) /* Value of OTP Bank7 Word0 (GP3) */
#define IMXRT_OCOTP_GP31 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_GP31_OFFSET) /* Value of OTP Bank7 Word1 (GP3) */
#define IMXRT_OCOTP_GP32 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_GP32_OFFSET) /* Value of OTP Bank7 Word2 (GP3) */
#define IMXRT_OCOTP_GP33 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_GP33_OFFSET) /* Value of OTP Bank7 Word3 (GP3) */
#define IMXRT_OCOTP_GP40 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_GP40_OFFSET) /* Value of OTP Bank7 Word4 (GP4) */
#define IMXRT_OCOTP_GP41 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_GP41_OFFSET) /* Value of OTP Bank7 Word5 (GP4) */
#define IMXRT_OCOTP_GP42 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_GP42_OFFSET) /* Value of OTP Bank7 Word6 (GP4) */
#define IMXRT_OCOTP_GP43 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_GP43_OFFSET) /* Value of OTP Bank7 Word7 (GP4) */
/* Register Bit Definitions *********************************************************************************************************/
/* OTP Controller Control Register */
#define OCOTP_CTRL_ADDR_SHIFT (0) /* Bits: 0-5 ADDR */
#define OCOTP_CTRL_ADDR_MASK (0x3f << OCOTP_CTRL_ADDR_SHIFT)
# define OCOTP_CTRL_ADDR(n) ((uint32_t)(n) << OCOTP_CTRL_ADDR_SHIFT)
/* Bits: 6-7 Reserved */
#define OCOTP_CTRL_BUSY (1 << 8) /* Bit: 8 BUSY */
#define OCOTP_CTRL_ERROR (1 << 9) /* Bit: 9 ERROR */
#define OCOTP_CTRL_RELOAD_SHADOWS (1 << 10) /* Bit: 10 OWS */
#define OCOTP_CTRL_CRC_TEST (1 << 11) /* Bit: 11 CRC_TEST */
#define OCOTP_CTRL_CRC_FAIL (1 << 12) /* Bit: 12 CRC_FAIL */
/* Bits: 13-15 Reserved */
#define OCOTP_CTRL_WR_UNLOCK_SHIFT (16) /* Bits: 16-31 WR_UNLOCK */
#define OCOTP_CTRL_WR_UNLOCK_MASK (0xffff << OCOTP_CTRL_WR_UNLOCK_SHIFT)
# define OCOTP_CTRL_WR_UNLOCK (0x3e77 << OCOTP_CTRL_WR_UNLOCK_SHIFT)
/* OTP Controller Timing Register */
#define OCOTP_TIMING_STROBE_PROG_SHIFT (0) /* Bits: 0-11 Specifies the strobe period in one time write OTP */
#define OCOTP_TIMING_STROBE_PROG_MASK (0xfff << OCOTP_TIMING_STROBE_PROG_SHIFT)
# define OCOTP_TIMING_STROBE_PROG(n) ((uint32_t)(n) << OCOTP_TIMING_STROBE_PROG_SHIFT)
#define OCOTP_TIMING_RELAX_SHIFT (12) /* Bits: 12-15 Specifies the time to add to all default timing parameters other than the Tpgm and Trd. */
#define OCOTP_TIMING_RELAX_MASK (15 << OCOTP_TIMING_RELAX_SHIFT)
# define OCOTP_TIMING_RELAX(n) ((uint32_t)(n) << OCOTP_TIMING_RELAX_SHIFT)
#define OCOTP_TIMING_STROBE_READ_SHIFT (16) /* Bits: 16-21 Specifies the strobe period in one time read OTP. */
#define OCOTP_TIMING_STROBE_READ_MASK (0x3f << OCOTP_TIMING_STROBE_READ_SHIFT)
# define OCOTP_TIMING_STROBE_READ(n) ((uint32_t)(n) << OCOTP_TIMING_STROBE_READ_SHIFT)
#define OCOTP_TIMING_WAIT_SHIFT (22) /* Bits: 22-27 Specifies time interval between auto read and write access in one time program */
#define OCOTP_TIMING_WAIT_MASK (0x3f << OCOTP_TIMING_WAIT_SHIFT)
# define OCOTP_TIMING_WAIT(n) ((uint32_t)(n) << OCOTP_TIMING_WAIT_SHIFT)
/* Bits: 28-31 Reserved */
/* OTP Controller Write Data Register */
#define OCOTP_READ_CTRL_READ_FUSE (1 << 0) /* Bit: 0 Used to initiate a read to OTP */
/* Bits: 1-31 Reserved */
/* Sticky bit Register */
#define OCOTP_SW_STICKY_BLOCK_DTCP_KEY (1 << 0) /* Bit: 0 Shadow register read and OTP read lock for DTCP_KEY region. */
#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK (1 << 1) /* Bit: 1 Shadow register write and OTP write lock for SRK_REVOKE region. */
#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK (1 << 2) /* Bit: 2 Shadow register write and OTP write lock for FIELD_RETURN region. */
#define OCOTP_SW_STICKY_BLOCK_ROM_PART (1 << 3) /* Bit: 3 Set by ARM during Boot after DTCP is initialized and before test mode entry, if ROM_PART_LOCK=1.*/
#define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE (1 << 4) /* Bit: 4 Set by ARM during Boot after DTCP is initialized and before test mode entry. */
/* Bits: 5-31 Reserved */
/* Software Controllable Signals Register */
#define OCOTP_SCS_HAB_JDE (1 << 0) /* Bit: 0 HAB JTAG Debug Enable. */
#define OCOTP_SCS_SPARE_SHIFT (1) /* Bits: 1-30 Unallocated read/write bits for implementation specific software use. */
#define OCOTP_SCS_SPARE_MASK (0x3fffffff << OCOTP_SCS_SPARE_SHIFT)
# define OCOTP_SCS_SPARE(n) ((uint32_t)(n) << OCOTP_SCS_SPARE_SHIFT)
#define OCOTP_SCS_LOCK (1 << 31) /* Bit: 31 LOCK */
/* OTP Controller CRC test address */
#define OCOTP_CRC_ADDR_DATA_START_ADDR_SHIFT (0) /* Bits: 0-7 Start address of fuse location for CRC calculation */
#define OCOTP_CRC_ADDR_DATA_START_ADDR_MASK (0xff << OCOTP_CRC_ADDR_DATA_START_ADDR_SHIFT)
# define OCOTP_CRC_ADDR_DATA_START_ADDR(n) ((uint32_t)(n) << OCOTP_CRC_ADDR_DATA_START_ADDR_SHIFT)
#define OCOTP_CRC_ADDR_DATA_END_ADDR_SHIFT (8) /* Bits: 8-15 End address of fuse location for CRC calculation */
#define OCOTP_CRC_ADDR_DATA_END_ADDR_MASK (0xff << OCOTP_CRC_ADDR_DATA_END_ADDR_SHIFT)
# define OCOTP_CRC_ADDR_DATA_END_ADDR(n) ((uint32_t)(n) << OCOTP_CRC_ADDR_DATA_END_ADDR_SHIFT)
#define OCOTP_CRC_ADDR_CRC_ADDR_SHIFT (16) /* Bits: 16-23 Address of 32-bit CRC result for comparing */
#define OCOTP_CRC_ADDR_CRC_ADDR_MASK (0xff << OCOTP_CRC_ADDR_CRC_ADDR_SHIFT)
# define OCOTP_CRC_ADDR_CRC_ADDR(n) ((uint32_t)(n) << OCOTP_CRC_ADDR_CRC_ADDR_SHIFT)
#define OCOTP_CRC_ADDR_OTPMK_CRC (1 << 24) /* Bit: 24 Enable bit for OCOTP CRC32 calculation address. */
/* Bits: 25-31 Reserved */
/* OTP Controller Version Register */
#define OCOTP_VERSION_STEP_SHIFT (0) /* Bits: 0-15 STEP field of the RTL version.*/
#define OCOTP_VERSION_STEP_MASK (0xffff << OCOTP_VERSION_STEP_SHIFT)
# define OCOTP_VERSION_STEP(n) ((uint32_t)(n) << OCOTP_VERSION_STEP_SHIFT)
#define OCOTP_VERSION_MINOR_SHIFT (16) /* Bits: 16-23 MINOR field of the RTL version. */
#define OCOTP_VERSION_MINOR_MASK (0xff << OCOTP_VERSION_MINOR_SHIFT)
# define OCOTP_VERSION_MINOR(n) ((uint32_t)(n) << OCOTP_VERSION_MINOR_SHIFT)
#define OCOTP_VERSION_MAJOR_SHIFT (24) /* Bits: 24-31 MAJOR field of the RTL version. */
#define OCOTP_VERSION_MAJOR_MASK (0xff << OCOTP_VERSION_MAJOR_SHIFT)
# define OCOTP_VERSION_MAJOR(n) ((uint32_t)(n) << OCOTP_VERSION_MAJOR_SHIFT)
/* OTP Controller Timing Register */
#define OCOTP_TIMING2_RELAX_PROG_SHIFT (0) /* Bits: 0-11 Specifies the strobe period in one time write OTP. */
#define OCOTP_TIMING2_RELAX_PROG_MASK (0xfff << OCOTP_TIMING2_RELAX_PROG_SHIFT)
# define OCOTP_TIMING2_RELAX_PROG(n) ((uint32_t)(n) << OCOTP_TIMING2_RELAX_PROG_SHIFT)
/* Bits: 12-15 Reserved. These bits always read back zero. */
#define OCOTP_TIMING2_RELAX_READ_SHIFT (16) /* Bits: 16-21 Specifies the strobe period in one time read OTP. */
#define OCOTP_TIMING2_RELAX_READ_MASK (0x3f << OCOTP_TIMING2_RELAX_READ_SHIFT)
# define OCOTP_TIMING2_RELAX_READ(n) ((uint32_t)(n) << OCOTP_TIMING2_RELAX_READ_SHIFT)
/* Bits: 22-31 Reserved. These bits always read back zero. */
/* Value of OTP Bank0 Word0 (Lock controls) */
#define OCOTP_LOCK_TESTER_SHIFT (0) /* Bits: 0-1 Chapter 22 On-Chip OTP Controller (OCOTP_CTRL) */
#define OCOTP_LOCK_TESTER_MASK (3 << OCOTP_LOCK_TESTER_SHIFT)
# define OCOTP_LOCK_TESTER(n) ((uint32_t)(n) << OCOTP_LOCK_TESTER_SHIFT)
#define OCOTP_LOCK_BOOT_CFG_SHIFT (2) /* Bits: 2-3 Status of shadow register and OTP write lock for boot_cfg region. */
#define OCOTP_LOCK_BOOT_CFG_MASK (3 << OCOTP_LOCK_BOOT_CFG_SHIFT)
# define OCOTP_LOCK_BOOT_CFG(n) ((uint32_t)(n) << OCOTP_LOCK_BOOT_CFG_SHIFT)
#define OCOTP_LOCK_MEM_TRIM_SHIFT (4) /* Bits: 4-5 Status of shadow register and OTP write lock for mem_trim region. */
#define OCOTP_LOCK_MEM_TRIM_MASK (3 << OCOTP_LOCK_MEM_TRIM_SHIFT)
# define OCOTP_LOCK_MEM_TRIM(n) ((uint32_t)(n) << OCOTP_LOCK_MEM_TRIM_SHIFT)
#define OCOTP_LOCK_SJC_RESP (1 << 6) /* Bit: 6 Status of shadow register read and write, OTP read and write lock for sjc_resp region. */
#define OCOTP_LOCK_GP4_RLOCK (1 << 7) /* Bit: 7 Status of shadow register and OTP read lock for gp4 region. */
#define OCOTP_LOCK_MAC_ADDR_SHIFT (8) /* Bits: 8-9 Status of shadow register and OTP write lock for mac_addr region. */
#define OCOTP_LOCK_MAC_ADDR_MASK (3 << OCOTP_LOCK_MAC_ADDR_SHIFT)
# define OCOTP_LOCK_MAC_ADDR(n) ((uint32_t)(n) << OCOTP_LOCK_MAC_ADDR_SHIFT)
#define OCOTP_LOCK_GP1_SHIFT (10) /* Bits: 10-11 Status of shadow register and OTP write lock for gp2 region. */
#define OCOTP_LOCK_GP1_MASK (3 << OCOTP_LOCK_GP1_SHIFT)
# define OCOTP_LOCK_GP1(n) ((uint32_t)(n) << OCOTP_LOCK_GP1_SHIFT)
#define OCOTP_LOCK_GP2_SHIFT (12) /* Bits: 12-13 Status of shadow register and OTP write lock for gp2 region.*/
#define OCOTP_LOCK_GP2_MASK (3 << OCOTP_LOCK_GP2_SHIFT)
# define OCOTP_LOCK_GP2(n) ((uint32_t)(n) << OCOTP_LOCK_GP2_SHIFT)
#define OCOTP_LOCK_SRK (1 << 14) /* Bit: 14 Status of shadow register and OTP write lock for srk region. */
#define OCOTP_LOCK_ROM_PATCH (1 << 15) /* Bit: 15 Status of shadow register and OTP write lock for rom_patch region. */
#define OCOTP_LOCK_SW_GP1 (1 << 16) /* Bit: 16 Status of shadow register and OTP write lock for sw_gp1 region.*/
#define OCOTP_LOCK_OTPMK (1 << 17) /* Bit: 17 Status of shadow register and OTP write lock for OTPMK region. */
#define OCOTP_LOCK_ANALOG_SHIFT (18) /* Bits: 18-19 Status of shadow register and OTP write lock for analog region. */
#define OCOTP_LOCK_ANALOG_MASK (3 << OCOTP_LOCK_ANALOG_SHIFT)
#define OCOTP_LOCK_SW_GP2_LOCK (1 << 21) /* Bit: 21 Status of shadow register and OTP write lock for sw_gp2 region.*/
#define OCOTP_LOCK_MISC_CONF (1 << 22) /* Bit: 22 Status of shadow register and OTP write lock for misc_conf region.*/
#define OCOTP_LOCK_SW_GP2_RLOCK (1 << 23) /* Bit: 23 Status of shadow register and OTP read lock for sw_gp2 region. */
#define OCOTP_LOCK_GP4_SHIFT (24) /* Bits: 24-25 Status of shadow register and OTP write lock for GP4 region. */
#define OCOTP_LOCK_GP4_MASK (3 << OCOTP_LOCK_GP4_SHIFT)
# define OCOTP_LOCK_GP4(n) ((uint32_t)(n) << OCOTP_LOCK_GP4_SHIFT)
#define OCOTP_LOCK_GP3_SHIFT (26) /* Bits: 26-27 Status of shadow register and OTP write lock for GP3 region. */
#define OCOTP_LOCK_GP3_MASK (3 << OCOTP_LOCK_GP3_SHIFT)
# define OCOTP_LOCK_GP3(n) ((uint32_t)(n) << OCOTP_LOCK_GP3_SHIFT)
#define OCOTP_LOCK_FIELD_RETURN_SHIFT (28) /* Bits: 28-31 When write field_return shadow register(only highest 4bits valid), the bits[27:0] must be kept as 0. */
#define OCOTP_LOCK_FIELD_RETURN_MASK (15 << OCOTP_LOCK_FIELD_RETURN_SHIFT)
# define OCOTP_LOCK_FIELD_RETURN(n) ((uint32_t)(n) << OCOTP_LOCK_FIELD_RETURN_SHIFT)
#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_OCOTP_H */
arch/arm/src/imxrt/chip/imxrt_pinmux.h
-56
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@@ -1,56 +0,0 @@
/************************************************************************************
* arch/arm/src/imxrt/chip/imxrt_pinmux.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_PINMUX_H
#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_PINMUX_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#if defined(CONFIG_ARCH_FAMILY_IMXRT102x)
# include "chip/rt102x/imxrt102x_pinmux.h"
#elif defined(CONFIG_ARCH_FAMILY_IMXRT105x)
# include "chip/rt105x/imxrt105x_pinmux.h"
#elif defined(CONFIG_ARCH_FAMILY_IMXRT106x)
# include "chip/rt106x/imxrt106x_pinmux.h"
#else
# error Unrecognized i.MX RT architecture
#endif
#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_PINMUX_H */
arch/arm/src/imxrt/chip/imxrt_pit.h
-131
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@@ -1,131 +0,0 @@
/************************************************************************************
* arch/arm/src/imxrt/chip/imxrt_pit.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_PIT_H
#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_PIT_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip/imxrt_memorymap.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register Offsets *****************************************************************/
#define IMXRT_PIT_MCR_OFFSET 0x0000 /* PIT Module Control Register */
#define IMXRT_PIT_LTMR64H_OFFSET 0x00e0 /* PIT Upper Lifetime Timer Register */
#define IMXRT_PIT_LTMR64L_OFFSET 0x00e4 /* PIT Lower Lifetime Timer Register */
#define IMXRT_PIT_LDVAL0_OFFSET 0x0100 /* Timer Load Value Register */
#define IMXRT_PIT_CVAL0_OFFSET 0x0104 /* Current Timer Value Register */
#define IMXRT_PIT_TCTRL0_OFFSET 0x0108 /* Timer Control Register */
#define IMXRT_PIT_TFLG0_OFFSET 0x010c /* Timer Flag Register */
#define IMXRT_PIT_LDVAL1_OFFSET 0x0110 /* Timer Load Value Register */
#define IMXRT_PIT_CVAL1_OFFSET 0x0114 /* Current Timer Value Register */
#define IMXRT_PIT_TCTRL1_OFFSET 0x0118 /* Timer Control Register */
#define IMXRT_PIT_TFLG1_OFFSET 0x011c /* Timer Flag Register */
#define IMXRT_PIT_LDVAL2_OFFSET 0x0120 /* Timer Load Value Register */
#define IMXRT_PIT_CVAL2_OFFSET 0x0124 /* Current Timer Value Register */
#define IMXRT_PIT_TCTRL2_OFFSET 0x0128 /* Timer Control Register */
#define IMXRT_PIT_TFLG2_OFFSET 0x012c /* Timer Flag Register */
#define IMXRT_PIT_LDVAL3_OFFSET 0x0130 /* Timer Load Value Register */
#define IMXRT_PIT_CVAL3_OFFSET 0x0134 /* Current Timer Value Register */
#define IMXRT_PIT_TCTRL3_OFFSET 0x0138 /* Timer Control Register */
#define IMXRT_PIT_TFLG3_OFFSET 0x013c /* Timer Flag Register */
/* Register Addresses ***************************************************************/
#define IMXRT_PIT_MCR (IMXRT_PIT_BASE+IMXRT_PIT_MCR_OFFSET)
#define IMXRT_PIT_LTMR64H (IMXRT_PIT_BASE+IMXRT_PIT_LTMR64H_OFFSET)
#define IMXRT_PIT_LTMR64L (IMXRT_PIT_BASE+IMXRT_PIT_LTMR64L_OFFSET)
#define IMXRT_PIT_LDVAL0 (IMXRT_PIT_BASE+IMXRT_PIT_LDVAL0_OFFSET)
#define IMXRT_PIT_CVAL0 (IMXRT_PIT_BASE+IMXRT_PIT_CVAL0_OFFSET)
#define IMXRT_PIT_TCTRL0 (IMXRT_PIT_BASE+IMXRT_PIT_TCTRL0_OFFSET)
#define IMXRT_PIT_TFLG0 (IMXRT_PIT_BASE+IMXRT_PIT_TFLG0_OFFSET)
#define IMXRT_PIT_LDVAL1 (IMXRT_PIT_BASE+IMXRT_PIT_LDVAL1_OFFSET)
#define IMXRT_PIT_CVAL1 (IMXRT_PIT_BASE+IMXRT_PIT_CVAL1_OFFSET)
#define IMXRT_PIT_TCTRL1 (IMXRT_PIT_BASE+IMXRT_PIT_TCTRL1_OFFSET)
#define IMXRT_PIT_TFLG1 (IMXRT_PIT_BASE+IMXRT_PIT_TFLG1_OFFSET)
#define IMXRT_PIT_LDVAL2 (IMXRT_PIT_BASE+IMXRT_PIT_LDVAL2_OFFSET)
#define IMXRT_PIT_CVAL2 (IMXRT_PIT_BASE+IMXRT_PIT_CVAL2_OFFSET)
#define IMXRT_PIT_TCTRL2 (IMXRT_PIT_BASE+IMXRT_PIT_TCTRL2_OFFSET)
#define IMXRT_PIT_TFLG2 (IMXRT_PIT_BASE+IMXRT_PIT_TFLG2_OFFSET)
#define IMXRT_PIT_LDVAL3 (IMXRT_PIT_BASE+IMXRT_PIT_LDVAL3_OFFSET)
#define IMXRT_PIT_CVAL3 (IMXRT_PIT_BASE+IMXRT_PIT_CVAL3_OFFSET)
#define IMXRT_PIT_TCTRL3 (IMXRT_PIT_BASE+IMXRT_PIT_TCTRL3_OFFSET)
#define IMXRT_PIT_TFLG3 (IMXRT_PIT_BASE+IMXRT_PIT_TFLG3_OFFSET)
/* Register Bit Definitions *********************************************************/
/* PIT Module Control Register */
#define PIT_MCR_FRZ (1 << 0) /* Bit 0: Freeze */
#define PIT_MCR_MDIS (1 << 1) /* Bit 1: Module Disable */
/* Bits 2-31: Reserved */
/* Timer Load Value Register (32-bit Timer Start Value Bits) */
/* Current Timer Value Register (32-bit Current Timer Value) */
/* Timer Control Register */
#define PIT_TCTRL_TEN (1 << 0) /* Bit 0: Timer Enable Bit */
#define PIT_TCTRL_TIE (1 << 1) /* Bit 1: Timer Interrupt Enable Bit */
/* Bits 2-31: Reserved */
#define PIT_TCTRL_CHN (1 << 2) /* Bit 2: Chain Mode */
/* Bits 3-31: Reserved */
/* Timer Flag Register */
#define PIT_TFLG_TIF (1 << 0) /* Bit 0: Timer Interrupt Flag */
/* Bits 1-31: Reserved */
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_PIT_H */
arch/arm/src/imxrt/chip/imxrt_snvs.h
-297
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/********************************************************************************************
* arch/arm/src/imxrt/imxrt_snvs.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_SNVS_H
#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_SNVS_H
/********************************************************************************************
* Included Files
********************************************************************************************/
#include <nuttx/config.h>
#include "chip/imxrt_memorymap.h"
/********************************************************************************************
* Pre-processor Definitions
********************************************************************************************/
#define IMXRT_SNVS_LP_MAXTAMPER 10
/* Register offsets *************************************************************************/
#define IMXRT_SNVS_HPLR_OFFSET 0x0000 /* SNVS_HP Lock Register */
#define IMXRT_SNVS_HPCOMR_OFFSET 0x0004 /* SNVS_HP Command Register */
#define IMXRT_SNVS_HPCR_OFFSET 0x0008 /* SNVS_HP Control Register */
#define IMXRT_SNVS_HPSR_OFFSET 0x0014 /* SNVS_HP Status Register */
#define IMXRT_SNVS_HPRTCMR_OFFSET 0x0024 /* SNVS_HP Real Time Counter MSB Register */
#define IMXRT_SNVS_HPRTCLR_OFFSET 0x0028 /* SNVS_HP Real Time Counter LSB Register */
#define IMXRT_SNVS_HPTAMR_OFFSET 0x002c /* SNVS_HP Time Alarm MSB Register */
#define IMXRT_SNVS_HPTALR_OFFSET 0x0030 /* SNVS_HP Time Alarm LSB Register */
#define IMXRT_SNVS_LPLR_OFFSET 0x0034 /* SNVS_LP Lock Register */
#define IMXRT_SNVS_LPCR_OFFSET 0x0038 /* SNVS_LP Control Register */
#define IMXRT_SNVS_LPSR_OFFSET 0x004c /* SNVS_LP Status Register */
#define IMXRT_SNVS_LPSMCMR_OFFSET 0x005c /* SNVS_LP Secure Monotonic Counter MSB Register */
#define IMXRT_SNVS_LPSMCLR_OFFSET 0x0060 /* SNVS_LP Secure Monotonic Counter LSB Register */
#define IMXRT_SNVS_LPGPR0L_OFFSET 0x0068 /* SNVS_LP General Purpose Register 0 (legacy alias) */
#define IMXRT_SNVS_LPGPRA_OFFSET(n) (0x0090 + ((n) << 2))
#define IMXRT_SNVS_LPGPR0A_OFFSET 0x0090 /* NVS_LP General Purpose Registers 0 LPGPR0_alias */
#define IMXRT_SNVS_LPGPR1A_OFFSET 0x0094 /* NVS_LP General Purpose Registers 1 LPGPR1_alias */
#define IMXRT_SNVS_LPGPR2A_OFFSET 0x0098 /* NVS_LP General Purpose Registers 2 LPGPR2_alias */
#define IMXRT_SNVS_LPGPR3A_OFFSET 0x009c /* NVS_LP General Purpose Registers 3 LPGPR3_alias */
#define IMXRT_SNVS_LPGPR_OFFSET(n) (0x0100 + ((n) << 2))
#define IMXRT_SNVS_LPGPR0_OFFSET 0x0100 /* SNVS_LP General Purpose Registers 0 */
#define IMXRT_SNVS_LPGPR1_OFFSET 0x0104 /* SNVS_LP General Purpose Registers 1 */
#define IMXRT_SNVS_LPGPR2_OFFSET 0x0108 /* SNVS_LP General Purpose Registers 2 */
#define IMXRT_SNVS_LPGPR3_OFFSET 0x010c /* SNVS_LP General Purpose Registers 3 */
#define IMXRT_SNVS_HPVIDR1_OFFSET 0x0bf8 /* SNVS_HP Version ID Register 1 */
#define IMXRT_SNVS_HPVIDR2_OFFSET 0x0bfc /* SNVS_HP Version ID Register 2 */
/* Register addresses ***********************************************************************/
#define IMXRT_SNVS_HPLR (IMXRT_SNVSHP_BASE + IMXRT_SNVS_HPLR_OFFSET)
#define IMXRT_SNVS_HPCOMR (IMXRT_SNVSHP_BASE + IMXRT_SNVS_HPCOMR_OFFSET)
#define IMXRT_SNVS_HPCR (IMXRT_SNVSHP_BASE + IMXRT_SNVS_HPCR_OFFSET)
#define IMXRT_SNVS_HPSR (IMXRT_SNVSHP_BASE + IMXRT_SNVS_HPSR_OFFSET)
#define IMXRT_SNVS_HPRTCMR (IMXRT_SNVSHP_BASE + IMXRT_SNVS_HPRTCMR_OFFSET)
#define IMXRT_SNVS_HPRTCLR (IMXRT_SNVSHP_BASE + IMXRT_SNVS_HPRTCLR_OFFSET)
#define IMXRT_SNVS_HPTAMR (IMXRT_SNVSHP_BASE + IMXRT_SNVS_HPTAMR_OFFSET)
#define IMXRT_SNVS_HPTALR (IMXRT_SNVSHP_BASE + IMXRT_SNVS_HPTALR_OFFSET)
#define IMXRT_SNVS_LPLR (IMXRT_SNVSHP_BASE + IMXRT_SNVS_LPLR_OFFSET)
#define IMXRT_SNVS_LPCR (IMXRT_SNVSHP_BASE + IMXRT_SNVS_LPCR_OFFSET)
#define IMXRT_SNVS_LPSR (IMXRT_SNVSHP_BASE + IMXRT_SNVS_LPSR_OFFSET)
#define IMXRT_SNVS_LPSMCMR (IMXRT_SNVSHP_BASE + IMXRT_SNVS_LPSMCMR_OFFSET)
#define IMXRT_SNVS_LPSMCLR (IMXRT_SNVSHP_BASE + IMXRT_SNVS_LPSMCLR_OFFSET)
#define IMXRT_SNVS_LPGPR0L (IMXRT_SNVSHP_BASE + IMXRT_SNVS_LPGPR0L_OFFSET)
#define IMXRT_SNVS_LPGPRA(n) (IMXRT_SNVSHP_BASE + IMXRT_SNVS_LPGPRA_OFFSET(n))
#define IMXRT_SNVS_LPGPR0A (IMXRT_SNVSHP_BASE + IMXRT_SNVS_LPGPR0A_OFFSET)
#define IMXRT_SNVS_LPGPR1A (IMXRT_SNVSHP_BASE + IMXRT_SNVS_LPGPR1A_OFFSET)
#define IMXRT_SNVS_LPGPR2A (IMXRT_SNVSHP_BASE + IMXRT_SNVS_LPGPR2A_OFFSET)
#define IMXRT_SNVS_LPGPR3A (IMXRT_SNVSHP_BASE + IMXRT_SNVS_LPGPR3A_OFFSET)
#define IMXRT_SNVS_LPGPR(n) (IMXRT_SNVSHP_BASE + IMXRT_SNVS_LPGPR_OFFSET(n))
#define IMXRT_SNVS_LPGPR0 (IMXRT_SNVSHP_BASE + IMXRT_SNVS_LPGPR0_OFFSET)
#define IMXRT_SNVS_LPGPR1 (IMXRT_SNVSHP_BASE + IMXRT_SNVS_LPGPR1_OFFSET)
#define IMXRT_SNVS_LPGPR2 (IMXRT_SNVSHP_BASE + IMXRT_SNVS_LPGPR2_OFFSET)
#define IMXRT_SNVS_LPGPR3 (IMXRT_SNVSHP_BASE + IMXRT_SNVS_LPGPR3_OFFSET)
#define IMXRT_SNVS_HPVIDR1 (IMXRT_SNVSHP_BASE + IMXRT_SNVS_HPVIDR1_OFFSET)
#define IMXRT_SNVS_HPVIDR2 (IMXRT_SNVSHP_BASE + IMXRT_SNVS_HPVIDR2_OFFSET)
/* Register bit definitions *****************************************************************/
/* SNVS_HP Lock Register */
/* Bits 0-3: Reserved */
#define SNVS_HPLR_MCSL (1 << 4) /* Bit 4: Monotonic Counter Soft Lock */
#define SNVS_HPLR_GPRSL (1 << 5) /* Bit 5: General Purpose Register Soft Lock */
/* Bits 6-31: Reserved */
/* SNVS_HP Command Register */
/* Bits 0-3: Reserved */
#define SNVS_HPCOMR_LPSWR (1 << 4) /* Bit 4: LP Software Reset */
#define SNVS_HPCOMR_LPSWRDIS (1 << 5) /* Bit 5: LP Software Reset Disable */
/* Bits 6-7: Reserved */
#define SNVS_HPCOMR_SWSV (1 << 8) /* Bit 8: */
/* Bits 9-30: Reserved */
#define SNVS_HPCOMR_NPSWAEN (1 << 31) /* Bit 31: Non-Privileged Software Access Enable */
/* SNVS_HP Control Register */
#define SNVS_HPCR_RTCEN (1 << 0) /* Bit 0: HP Real Time Counter Enable */
#define SNVS_HPCR_HPTAEN (1 << 1) /* Bit 1: HP Time Alarm Enable */
#define SNVS_HPCR_DISPI (1 << 2) /* Bit 2: Disable periodic interrupt in the functional interrupt */
/* Bit 2: Reserved */
#define SNVS_HPCR_PIEN (1 << 3) /* Bit 3: HP Periodic Interrupt Enable */
#define SNVS_HPCR_PIFREQ_SHIFT (4) /* Bits 4-7: Periodic Interrupt Frequency */
#define SNVS_HPCR_PIFREQ_MASK (15 << SNVS_HPCR_PIFREQ_SHIFT)
# define SNVS_HPCR_PIFREQ(n) ((uint32_t)(n) << SNVS_HPCR_PIFREQ_SHIFT)
#define SNVS_HPCR_HPCALBEN (1 << 8) /* Bit 8: HP Real Time Counter Calibration Enabled */
/* Bit 9: Reserved */
#define SNVS_HPCR_HPCALBVAL_SHIFT (10) /* Bits 10-14: HP Calibration Value */
#define SNVS_HPCR_HPCALBVAL_MASK (31 << SNVS_HPCR_HPCALBVAL_SHIFT)
# define SNVS_HPCR_HPCALBVAL(n) ((uint32_t)(n) << SNVS_HPCR_HPCALBVAL_SHIFT)
# define SNVS_HPCR_HPCALBVAL_ZERO (0 << SNVS_HPCR_HPCALBVAL_SHIFT) /* +0 counts per 32768 ticks */
# define SNVS_HPCR_HPCALBVAL_P1 (1 << SNVS_HPCR_HPCALBVAL_SHIFT) /* +1 counts per 32768 ticks */
# define SNVS_HPCR_HPCALBVAL_P2 (2 << SNVS_HPCR_HPCALBVAL_SHIFT) /* +2 counts per 32768 ticks */
# define SNVS_HPCR_HPCALBVAL_P15 (15 << SNVS_HPCR_HPCALBVAL_SHIFT) /* +15 counts per 32768 ticks */
# define SNVS_HPCR_HPCALBVAL_M16 (16 << SNVS_HPCR_HPCALBVAL_SHIFT) /* -16 counts per 32768 ticks */
# define SNVS_HPCR_HPCALBVAL_M15 (17 << SNVS_HPCR_HPCALBVAL_SHIFT) /* -15 counts per 32768 ticks */
# define SNVS_HPCR_HPCALBVAL_M2 (30 << SNVS_HPCR_HPCALBVAL_SHIFT) /* -2 counts per 32768 ticks */
# define SNVS_HPCR_HPCALBVAL_M1 (31 << SNVS_HPCR_HPCALBVAL_SHIFT) /* -1 counts per 32768 ticks */
/* Bits 15: Reserved */
#define SNVS_HPCR_HPTS (1 << 16) /* Bit 16: LPSRTC time sychronization */
/* Bits 17-23: Reserved */
#define SNVS_HPCR_BTNCONFIG_SHIFT (24) /* Bits 24-26: Button Configuration */
#define SNVS_HPCR_BTNCONFIG_MASK (7 << SNVS_HPCR_BTNCONFIG_SHIFT)
# define SNVS_HPCR_BTNCONFIG_ LOW (0 << SNVS_HPCR_BTNCONFIG_SHIFT) /* Button signal active low */
# define SNVS_HPCR_BTNCONFIG_HIGH (1 << SNVS_HPCR_BTNCONFIG_SHIFT) /* Button signal active high */
# define SNVS_HPCR_BTNCONFIG_RISING (2 << SNVS_HPCR_BTNCONFIG_SHIFT) /* Button signal active on rising edge */
# define SNVS_HPCR_BTNCONFIG_FALLING (3 << SNVS_HPCR_BTNCONFIG_SHIFT) /* Button signal active on falling edge */
# define SNVS_HPCR_BTNCONFIG_BOTH (4 << SNVS_HPCR_BTNCONFIG_SHIFT) /* Button signal active on any edge */
#define SNVS_HPCR_BTNMASK (1 << 27) /* Bit 27: Button interrupt mask */
/* Bits 28-31: Reserved */
/* SNVS_HP Status Register */
#define SNVS_HPSR_HPTA (1 << 0) /* Bit 0: HP Time Alarm */
#define SNVS_HPSR_PI (1 << 1) /* Bit 1: Periodic Interrupt */
/* Bits 2-3: Reserved */
#define SNVS_HPSR_LPDIS (1 << 4) /* Bit 4: Low Power Disable */
/* Bit 95 Reserved */
#define SNVS_HPSR_BTN (1 << 6) /* Bit 6: Button */
#define SNVS_HPSR_BI (1 << 7) /* Bit 7: Button Interrupt */
/* Bits 8-31: Reserved */
/* SNVS_HP Real Time Counter MSB Register (15-bit MSB of counter) */
/* SNVS_HP Real Time Counter LSB Register (32-bit LSB of counter) */
#define SNVS_HPRTCMR_MASK 0x00007fff /* Bits 0-14: HP Real Time Counter */
/* SNVS_HP Time Alarm MSB Register (15-bit MSB of counter) */
/* SNVS_HP Time Alarm LSB Register (32-bit LSB of counter) */
#define SNVS_HPTAMR_MASK 0x00007fff /* Bits 0-14: HP Time Alarm, most-significant 15 bits */
/* SNVS_LP Lock Register */
/* Bits 0-3: Reserved */
#define SNVS_LPLR_MCHL (1 << 4) /* Bit 4: Monotonic Counter Hard Lock */
#define SNVS_LPLR_GPRHL (1 << 5) /* Bit 5: General Purpose Register Hard Lock */
/* Bits 6-31: Reserved */
/* SNVS_LP Control Register */
#define SVNS_LPCR_SRTCENV (1 << 0) /* Bit 0: Start SVNS RTC time counter */
#define SVNS_LPCR_LPTAEN (1 << 1) /* Bit 1: Enable SVNS RTC time alarm */
#define SNVS_LPCR_MCENV (1 << 2) /* Bit 2: Monotonic Counter Enabled and Valid */
#define SNVS_LPCR_LPWUIEN (1 << 3) /* Bit 3: LP Wake-Up Interrupt Enable */
/* Bit 4: Reserved */
#define SNVS_LPCR_DPEN (1 << 5) /* Bit 5: Dumb PMIC Enabled */
#define SNVS_LPCR_TOP (1 << 6) /* Bit 6: Turn off System Power */
#define SNVS_LPCR_PWRGLITCHEN (1 << 7) /* Bit 7: Power Glitch Enable */
/* Bits 8-15: Reserved for i.MX1050 family */
#define SNVS_LPCR_LPCALBEN (1 << 8) /* Bit 8: LP Real Time Counter Calibration Enabled */
/* Bit 9: Reserved */
#define SNVS_LPCR_LPCALBVAL_SHIFT (10) /* Bits 10-14: LP Calibration Value */
#define SNVS_LPCR_LPCALBVAL_MASK (31 << SNVS_LPCR_LPCALBVAL_SHIFT)
# define SNVS_LPCR_LPCALBVAL(n) ((uint32_t)(n) << SNVS_LPCR_LPCALBVAL_SHIFT)
# define SNVS_LPCR_LPCALBVAL_ZERO (0 << SNVS_LPCR_LPCALBVAL_SHIFT) /* +0 counts per 32768 ticks */
# define SNVS_LPCR_LPCALBVAL_P1 (1 << SNVS_LPCR_LPCALBVAL_SHIFT) /* +1 counts per 32768 ticks */
# define SNVS_LPCR_LPCALBVAL_P2 (2 << SNVS_LPCR_LPCALBVAL_SHIFT) /* +2 counts per 32768 ticks */
# define SNVS_LPCR_LPCALBVAL_P15 (15 << SNVS_LPCR_LPCALBVAL_SHIFT) /* +15 counts per 32768 ticks */
# define SNVS_LPCR_LPCALBVAL_M16 (16 << SNVS_LPCR_LPCALBVAL_SHIFT) /* -16 counts per 32768 ticks */
# define SNVS_LPCR_LPCALBVAL_M15 (17 << SNVS_LPCR_LPCALBVAL_SHIFT) /* -15 counts per 32768 ticks */
# define SNVS_LPCR_LPCALBVAL_M2 (30 << SNVS_LPCR_LPCALBVAL_SHIFT) /* -2 counts per 32768 ticks */
# define SNVS_LPCR_LPCALBVAL_M1 (31 << SNVS_LPCR_LPCALBVAL_SHIFT) /* -1 counts per 32768 ticks */
/* Bit 15: Reserved */
#define SNVS_LPCR_BTNPRESSTIME_SHIFT (16) /* Bits 16-17: PMIC button press time out values */
#define SNVS_LPCR_BTNPRESSTIME_MASK (3 << SNVS_LPCR_BTNPRESSTIME_SHIFT)
# define SNVS_LPCR_BTNPRESSTIME_5SEC (0 << SNVS_LPCR_BTNPRESSTIME_SHIFT) /* 5 secs */
# define SNVS_LPCR_BTNPRESSTIME_10SEC (1 << SNVS_LPCR_BTNPRESSTIME_SHIFT) /* 10 secs */
# define SNVS_LPCR_BTNPRESSTIME_15SEC (2 << SNVS_LPCR_BTNPRESSTIME_SHIFT) /* 15 secs */
# define SNVS_LPCR_BTNPRESSTIME_DESAB (3 << SNVS_LPCR_BTNPRESSTIME_SHIFT) /* Long press disabled */
#define SNVS_LPCR_DEBOUNCE_SHIFT (18) /* Bits 18-19: Debounce time for BTN input signal */
#define SNVS_LPCR_DEBOUNCE_MASK (3 << SNVS_LPCR_DEBOUNCE_SHIFT)
# define SNVS_LPCR_DEBOUNCE_50MS (0 << SNVS_LPCR_DEBOUNCE_SHIFT) /* 50msec debounce */
# define SNVS_LPCR_DEBOUNCE_100MS (1 << SNVS_LPCR_DEBOUNCE_SHIFT) /* 100msec debounce */
# define SNVS_LPCR_DEBOUNCE_500MS (2 << SNVS_LPCR_DEBOUNCE_SHIFT) /* 500msec debounce */
# define SNVS_LPCR_DEBOUNCE_NONE (3 << SNVS_LPCR_DEBOUNCE_SHIFT) /* 0msec debounce */
#define SNVS_LPCR_ONTIME_SHIFT (20) /* Bits 20-21: ON time configuration */
#define SNVS_LPCR_ONTIME_MASK (3 << SNVS_LPCR_ONTIME_SHIFT)
# define SNVS_LPCR_ONTIME_500MS (0 << SNVS_LPCR_ONTIME_SHIFT) /* 500msec off->on transition time */
# define SNVS_LPCR_ONTIME_50MS (1 << SNVS_LPCR_ONTIME_SHIFT) /* 50msec off->on transition time */
# define SNVS_LPCR_ONTIME_100MS (2 << SNVS_LPCR_ONTIME_SHIFT) /* 100msec off->on transition time */
# define SNVS_LPCR_ONTIME_NONE (3 << SNVS_LPCR_ONTIME_SHIFT) /* 0msec off->on transition time */
#define SNVS_LPCR_PKEN (1 << 22) /* Bit 22: PMIC On Request Enable */
#define SNVS_LPCR_PKOVERRIDE (1 << 23) /* Bit 23: PMIC On Request Override */
/* Bits 24-31: Reserved */
/* SNVS_LP Status Register */
/* Bits 0-1: Reserved */
#define SNVS_LPSR_MCR (1 << 2) /* Bit 2: Monotonic Counter Rollover */
/* Bits 3-16: Reserved */
#define SNVS_LPSR_EO (1 << 17) /* Bit 17: Emergency Off */
#define SNVS_LPSR_SPO (1 << 18) /* Bit 18: Set Power Off */
/* Bits 19-31: Reserved */
/* SNVS_LP Secure Monotonic Counter MSB Register */
/* SNVS_LP Secure Monotonic Counter LSB Register (32-bit LSB counter value) */
#define SNVS_LPSMCMR_MONCOUNTER_SHIFT (0) /* Bits 0-15: Monotonic Counter most-significant 16 Bits */
#define SNVS_LPSMCMR_MONCOUNTER_MASK (0xffff << SNVS_LPSMCMR_MONCOUNTER_SHIFT)
# define SNVS_LPSMCMR_MONCOUNTER(n) ((uint32_t)(n) << SNVS_LPSMCMR_MONCOUNTER_SHIFT)
#define SNVS_LPSMCMR_MCERABITS_SHIFT (16) /* Bits 16-31: Monotonic Counter Era Bits */
#define SNVS_LPSMCMR_MCERABITS_MASK (0xffff << SNVS_LPSMCMR_MCERABITS_SHIFT)
# define SNVS_LPSMCMR_MCERABITS(n) ((uint32_t)(n) << SNVS_LPSMCMR_MCERABITS_SHIFT)
/* SNVS_LP General Purpose Register 0 (legacy alias) (32-bit value) */
/* NVS_LP General Purpose Registers 0 LPGPR0_alias (32-bit value) */
/* NVS_LP General Purpose Registers 1 LPGPR1_alias (32-bit value) */
/* NVS_LP General Purpose Registers 2 LPGPR2_alias (32-bit value) */
/* NVS_LP General Purpose Registers 3 LPGPR3_alias (32-bit value) */
/* SNVS_LP General Purpose Registers 0 (32-bit value) */
/* SNVS_LP General Purpose Registers 1 (32-bit value) */
/* SNVS_LP General Purpose Registers 2 (32-bit value) */
/* SNVS_LP General Purpose Registers 3 (32-bit value) */
/* SNVS_HP Version ID Register 1 */
#define SNVS_HPVIDR1_MINORREV_SHIFT (0) /* Bits 0-7: SNVS block minor version number */
#define SNVS_HPVIDR1_MINORREV_MASK (0xff << SNVS_HPVIDR1_MINORREV_SHIFT)
#define SNVS_HPVIDR1_MAJORREV_SHIFT (8) /* Bits 8-15: SNVS block major version number */
#define SNVS_HPVIDR1_MAJORREV_MASK (0xff << SNVS_HPVIDR1_MAJORREV_SHIFT)
#define SNVS_HPVIDR1_IPID_SHIFT (16) /* Bits 16-31: SNVS block ID */
#define SNVS_HPVIDR1_IPID_MASK (0xffff << SNVS_HPVIDR1_IPID_SHIFT)
/* SNVS_HP Version ID Register 2 */
#define SNVS_HPVIDR2_CONFIGOPT_SHIFT (0) /* Bits 0-7: SNVS Configuration Options */
#define SNVS_HPVIDR2_CONFIGOPT_MASK (0xff << SNVS_HPVIDR2_CONFIGOPT_SHIFT)
#define SNVS_HPVIDR2_ECOREV_SHIFT (8) /* Bits 8-15: SNVS ECO Revision */
#define SNVS_HPVIDR2_ECOREV_MASK (0xff << SNVS_HPVIDR2_ECOREV_SHIFT)
#define SNVS_HPVIDR2_INTGOPT_SHIFT (16) /* Bits 16-23: SNVS Integration Options */
#define SNVS_HPVIDR2_INTGOPT_MASK (0xff << SNVS_HPVIDR2_INTGOPT_SHIFT)
#define SNVS_HPVIDR2_IPERA_SHIFT (24) /* Bits 24-31: IP Era */
#define SNVS_HPVIDR2_IPERA_MASK (0xff << SNVS_HPVIDR2_IPERA_SHIFT)
#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_SNVS_H */
arch/arm/src/imxrt/chip/imxrt_src.h
-157
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/********************************************************************************************
* arch/arm/src/imxrt/imxrt_src.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_SRC_H
#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_SRC_H
/********************************************************************************************
* Included Files
********************************************************************************************/
#include <nuttx/config.h>
#include "chip/imxrt_memorymap.h"
/********************************************************************************************
* Pre-processor Definitions
********************************************************************************************/
/* Register offsets *************************************************************************/
#define IMXRT_SRC_SCR_OFFSET 0x0000 /* SRC Control Register */
#define IMXRT_SRC_SBMR1_OFFSET 0x0004 /* SRC Boot Mode Register 1 */
#define IMXRT_SRC_SRSR_OFFSET 0x0008 /* SRC Reset Status Register */
#define IMXRT_SRC_SBMR2_OFFSET 0x001c /* SRC Boot Mode Register 2 */
#define IMXRT_SRC_GPR1_OFFSET 0x0020 /* SRC General Purpose Register 1 */
#define IMXRT_SRC_GPR2_OFFSET 0x0024 /* SRC General Purpose Register 2 */
#define IMXRT_SRC_GPR3_OFFSET 0x0028 /* SRC General Purpose Register 3 */
#define IMXRT_SRC_GPR4_OFFSET 0x002c /* SRC General Purpose Register 4 */
#define IMXRT_SRC_GPR5_OFFSET 0x0030 /* SRC General Purpose Register 5 */
#define IMXRT_SRC_GPR6_OFFSET 0x0034 /* SRC General Purpose Register 6 */
#define IMXRT_SRC_GPR7_OFFSET 0x0038 /* SRC General Purpose Register 7 */
#define IMXRT_SRC_GPR8_OFFSET 0x003c /* SRC General Purpose Register 8 */
#define IMXRT_SRC_GPR9_OFFSET 0x0040 /* SRC General Purpose Register 9 */
#define IMXRT_SRC_GPR10_OFFSET 0x0044 /* SRC General Purpose Register 10 */
/* Register addresses ***********************************************************************/
#define IMXRT_SRC_SCR (IMXRT_SRC_BASE + IMXRT_SRC_SCR_OFFSET)
#define IMXRT_SRC_SBMR1 (IMXRT_SRC_BASE + IMXRT_SRC_SBMR1_OFFSET)
#define IMXRT_SRC_SRSR (IMXRT_SRC_BASE + IMXRT_SRC_SRSR_OFFSET)
#define IMXRT_SRC_SBMR2 (IMXRT_SRC_BASE + IMXRT_SRC_SBMR2_OFFSET)
#define IMXRT_SRC_GPR1 (IMXRT_SRC_BASE + IMXRT_SRC_GPR1_OFFSET)
#define IMXRT_SRC_GPR2 (IMXRT_SRC_BASE + IMXRT_SRC_GPR2_OFFSET)
#define IMXRT_SRC_GPR3 (IMXRT_SRC_BASE + IMXRT_SRC_GPR3_OFFSET)
#define IMXRT_SRC_GPR4 (IMXRT_SRC_BASE + IMXRT_SRC_GPR4_OFFSET)
#define IMXRT_SRC_GPR5 (IMXRT_SRC_BASE + IMXRT_SRC_GPR5_OFFSET)
#define IMXRT_SRC_GPR6 (IMXRT_SRC_BASE + IMXRT_SRC_GPR6_OFFSET)
#define IMXRT_SRC_GPR7 (IMXRT_SRC_BASE + IMXRT_SRC_GPR7_OFFSET)
#define IMXRT_SRC_GPR8 (IMXRT_SRC_BASE + IMXRT_SRC_GPR8_OFFSET)
#define IMXRT_SRC_GPR9 (IMXRT_SRC_BASE + IMXRT_SRC_GPR9_OFFSET)
#define IMXRT_SRC_GPR10 (IMXRT_SRC_BASE + IMXRT_SRC_GPR10_OFFSET)
/* Register bit definitions *****************************************************************/
/* SRC Control Register */
/* Bits 0-3: Reserved */
#define SRC_SCR_LOCKUP_RST (1 << 4) /* Bit 4: Lockup reset enable bit */
/* Bits 5-6: Reserved */
#define SRC_SCR_MASK_WDOG_RST_SHIFT (7) /* Bits 7-10: Mask wdog_rst_b source */
#define SRC_SCR_MASK_WDOG_RST_MASK (15 << SRC_SCR_MASK_WDOG_RST_SHIFT)
# define SRC_SCR_MASK_WDOG_RST_MASKED (5 << SRC_SCR_MASK_WDOG_RST_SHIFT)
# define SRC_SCR_MASK_WDOG_RST_UNMASKED (10 << SRC_SCR_MASK_WDOG_RST_SHIFT)
/* Bits 11-12: Reserved */
#define SRC_SCR_CORE0_RST (1 << 13) /* Bit 13: Software reset for core0 only. */
/* Bits 14-16: Reserved */
#define SRC_SCR_CORE0_DBG_RST (1 << 17) /* Bit 17: Software reset for core0 debug only */
/* Bits 18-24: Reserved */
#define SRC_SCR_DBG_RST_MSK_PG (1 << 25) /* Bit 25: Do not assert debug resets
* after power gating event of core */
/* Bits 26-27: Reserved */
#define SRC_SCR_MASK_WDOG3_RST_SHIFT (28) /* Bits 38-31: Mask wdog3_rst_b source */
#define SRC_SCR_MASK_WDOG3_RST_MASK (15 << SRC_SCR_MASK_WDOG3_RST_SHIFT)
# define SRC_SCR_MASK_WDOG3_RST_MASKED (5 << SRC_SCR_MASK_WDOG3_RST_SHIFT)
# define SRC_SCR_MASK_WDOG3_RST_UNMASKED (10 << SRC_SCR_MASK_WDOG3_RST_SHIFT)
/* SRC Boot Mode Register 1 */
#define SRC_SBMR1_BOOT_CFG_SHIFT (24) /* Bits 24-31: Refer to fusemap */
#define SRC_SBMR1_BOOT_CFG_MASK (0xff << SRC_SBMR1_BOOT_CFG_SHIFT)
#define SRC_SBMR1_BOOT_CFG2_SHIFT (16) /* Bits 16-23: Refer to fusemap */
#define SRC_SBMR1_BOOT_CFG2_MASK (0xff << SRC_SBMR1_BOOT_CFG2_SHIFT)
#define SRC_SBMR1_BOOT_CFG3_SHIFT (8) /* Bits 8-15: Refer to fusemap */
#define SRC_SBMR1_BOOT_CFG3_MASK (0xff << SRC_SBMR1_BOOT_CFG3_SHIFT)
#define SRC_SBMR1_BOOT_CFG4_SHIFT (0) /* Bits 0-7: Refer to fusemap */
#define SRC_SBMR1_BOOT_CFG4_MASK (0xff << SRC_SBMR1_BOOT_CFG4_SHIFT)
/* SRC Reset Status Register */
#define SRC_SRSR_IPP_RESET_B (1 << 0) /* Bit 0: Indicates whether reset was the
* result of ipp_reset_b pin (Power-up
* sequence) */
#define SRC_SRSR_LOCKUP_SYSRESETREQ (1 << 1) /* Bit 1: Indicates a reset has been
* caused by CPU lockup or software setting
* of SYSRESETREQ bit */
#define SRC_SRSR_CSU_RESET_B (1 << 2) /* Bit 2: Indicates whether the reset was
* the result of the csu_reset_b input */
#define SRC_SRSR_IPP_USER_RESET_B (1 << 3) /* Bit 3: Indicates whether the reset was
* the result of the ipp_user_reset_b qualified
* reset */
#define SRC_SRSR_WDOG_RST_B (1 << 4) /* Bit 4: IC Watchdog Time-out reset */
#define SRC_SRSR_JTAG_RST_B (1 << 5) /* Bit 5: HIGH - Z JTAG reset */
#define SRC_SRSR_JTAG_SW_RST (1 << 6) /* Bit 6: JTAG software reset */
#define SRC_SRSR_WDOG3_RST_B (1 << 7) /* Bit 7: IC Watchdog3 Time-out reset */
#define SRC_SRSR_TEMPSENSE_RST_B (1 << 8) /* Bit 8: Temper Sensor software reset */
/* Bits 9-31: Reserved */
/* SRC Boot Mode Register 2 */
#define SRC_SBMR2_SEC_CONFIG_SHIFT (0) /* Bits 0-1: State of the corresponding
* SECONFIG fuse */
/* Bit 2: Reserved */
#define SRC_SBMR2_DIR_BT_DIS (1 << 3) /* Bit 3: State of the DIR_BT_DIS fuse */
#define SRC_SBMR2_BT_FUSE_SEL (1 << 4) /* Bit 4: State of the BT_FUSE_SEL fuse */
/* Bits 5-23: Reserved */
#define SRC_SBMR2_BMOD_SHIFT (24) /* Bits 24-25: Latched state of the BOOT_MODE
* and BOOT_MODE0 signals on POR.
/* Bits 26-31: Reserved */
/* SRC General Purpose Register 1 (32-bit values, some have reserved bits)
* NOTE: Ald GPR registers are used by the ROM code and should not be used by application
* software.
*/
#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_SRC_H */
arch/arm/src/imxrt/chip/imxrt_tmr.h
-662
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arch/arm/src/imxrt/chip/imxrt_usb_analog.h
-209
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/************************************************************************************************************************************
* arch/arm/src/imxrt/chip/imxrt_usb_analog.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_USB_ANALOG_H
#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_USB_ANALOG_H
/************************************************************************************************************************************
* Included Files
************************************************************************************************************************************/
#include <nuttx/config.h>
#include "chip/imxrt_memorymap.h"
/************************************************************************************************************************************
* Pre-processor Definitions
************************************************************************************************************************************/
/* Register Offsets *****************************************************************************************************************/
#define IMXRT_USB_ANALOG_USB1_VBUS_DETECT_OFFSET 0x01a0 /* USB VBUS Detect Register */
#define IMXRT_USB_ANALOG_USB1_VBUS_DETECT_SET_OFFSET 0x01a4 /* USB VBUS Detect Set Register */
#define IMXRT_USB_ANALOG_USB1_VBUS_DETECT_CLR_OFFSET 0x01a8 /* USB VBUS Detect Clear Register */
#define IMXRT_USB_ANALOG_USB1_VBUS_DETECT_TOG_OFFSET 0x01ac /* USB VBUS Detect Toggle Register */
#define IMXRT_USB_ANALOG_USB1_CHRG_DETECT_OFFSET 0x01b0 /* USB Charger Detect Register */
#define IMXRT_USB_ANALOG_USB1_CHRG_DETECT_SET_OFFSET 0x01b4 /* USB Charger Detect Set Register */
#define IMXRT_USB_ANALOG_USB1_CHRG_DETECT_CLR_OFFSET 0x01b8 /* USB Charger Detect Clear Register */
#define IMXRT_USB_ANALOG_USB1_CHRG_DETECT_TOG_OFFSET 0x01bc /* USB Charger Detect Toggle Register */
#define IMXRT_USB_ANALOG_USB1_VBUS_DETECT_STAT_OFFSET 0x01c0 /* USB VBUS Detect Status Register */
#define IMXRT_USB_ANALOG_USB1_CHRG_DETECT_STAT_OFFSET 0x01d0 /* USB Charger Detect Status Register */
#define IMXRT_USB_ANALOG_USB1_MISC_OFFSET 0x01f0 /* USB Misc Register */
#define IMXRT_USB_ANALOG_USB1_MISC_SET_OFFSET 0x01f4 /* USB Misc Set Register */
#define IMXRT_USB_ANALOG_USB1_MISC_CLR_OFFSET 0x01f8 /* USB Misc Clear Register */
#define IMXRT_USB_ANALOG_USB1_MISC_TOG_OFFSET 0x01fc /* USB Misc Toggle Register */
#define IMXRT_USB_ANALOG_USB2_VBUS_DETECT_OFFSET 0x0200 /* USB VBUS Detect Register */
#define IMXRT_USB_ANALOG_USB2_VBUS_DETECT_SET_OFFSET 0x0204 /* USB VBUS Detect Set Register */
#define IMXRT_USB_ANALOG_USB2_VBUS_DETECT_CLR_OFFSET 0x0208 /* USB VBUS Detect Clear Register */
#define IMXRT_USB_ANALOG_USB2_VBUS_DETECT_TOG_OFFSET 0x020c /* USB VBUS Detect Toggle Register */
#define IMXRT_USB_ANALOG_USB2_CHRG_DETECT_OFFSET 0x0210 /* USB Charger Detect Register */
#define IMXRT_USB_ANALOG_USB2_CHRG_DETECT_SET_OFFSET 0x0214 /* USB Charger Detect Set Register */
#define IMXRT_USB_ANALOG_USB2_CHRG_DETECT_CLR_OFFSET 0x0218 /* USB Charger Detect Clear Register */
#define IMXRT_USB_ANALOG_USB2_CHRG_DETECT_TOG_OFFSET 0x021c /* USB Charger Detect Toggle Register */
#define IMXRT_USB_ANALOG_USB2_VBUS_DETECT_STAT_OFFSET 0x0220 /* USB VBUS Detect Status Register */
#define IMXRT_USB_ANALOG_USB2_CHRG_DETECT_STAT_OFFSET 0x0230 /* USB Charger Detect Status Register */
#define IMXRT_USB_ANALOG_USB2_MISC_OFFSET 0x0250 /* USB Misc Register */
#define IMXRT_USB_ANALOG_USB2_MISC_SET_OFFSET 0x0254 /* USB Misc Set Register */
#define IMXRT_USB_ANALOG_USB2_MISC_CLR_OFFSET 0x0258 /* USB Misc Clear Register */
#define IMXRT_USB_ANALOG_USB2_MISC_TOG_OFFSET 0x025c /* USB Misc Toggle Register */
#define IMXRT_USB_ANALOG_DIGPROG_OFFSET 0x0260 /* Chip Silicon Version */
/* Register addresses ***********************************************************************************************************************/
/* Analog USB1 Register Addresses */
#define IMXRT_USB_ANALOG_USB1_VBUS_DETECT (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_VBUS_DETECT_OFFSET) /* USB_ANALOG1 USB VBUS Detect Register */
#define IMXRT_USB_ANALOG_USB1_VBUS_DETECT_SET (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_VBUS_DETECT_SET_OFFSET) /* USB_ANALOG1 USB VBUS Detect Set Register */
#define IMXRT_USB_ANALOG_USB1_VBUS_DETECT_CLR (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_VBUS_DETECT_CLR_OFFSET) /* USB_ANALOG1 USB VBUS Detect Clear Register */
#define IMXRT_USB_ANALOG_USB1_VBUS_DETECT_TOG (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_VBUS_DETECT_TOG_OFFSET) /* USB_ANALOG1 USB VBUS Detect Toggle Register */
#define IMXRT_USB_ANALOG_USB1_CHRG_DETECT (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_CHRG_DETECT_OFFSET) /* USB_ANALOG1 USB Charger Detect Register */
#define IMXRT_USB_ANALOG_USB1_CHRG_DETECT_SET (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_CHRG_DETECT_SET_OFFSET) /* USB_ANALOG1 USB Charger Detect Set Register */
#define IMXRT_USB_ANALOG_USB1_CHRG_DETECT_CLR (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_CHRG_DETECT_CLR_OFFSET) /* USB_ANALOG1 USB Charger Detect Clear Register */
#define IMXRT_USB_ANALOG_USB1_CHRG_DETECT_TOG (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_CHRG_DETECT_TOG_OFFSET) /* USB_ANALOG1 USB Charger Detect Toggle Register */
#define IMXRT_USB_ANALOG_USB1_VBUS_DETECT_STAT (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_VBUS_DETECT_STAT_OFFSET) /* USB_ANALOG1 USB VBUS Detect Status Register */
#define IMXRT_USB_ANALOG_USB1_CHRG_DETECT_STAT (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_CHRG_DETECT_STAT_OFFSET) /* USB_ANALOG1 USB Charger Detect Status Register */
#define IMXRT_USB_ANALOG_USB1_MISC (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_MISC_OFFSET) /* USB_ANALOG1 USB Misc Register */
#define IMXRT_USB_ANALOG_USB1_MISC_SET (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_MISC_SET_OFFSET) /* USB_ANALOG1 USB Misc Set Register */
#define IMXRT_USB_ANALOG_USB1_MISC_CLR (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_MISC_CLR_OFFSET) /* USB_ANALOG1 USB Misc Clear Register */
#define IMXRT_USB_ANALOG_USB1_MISC_TOG (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_MISC_TOG_OFFSET) /* USB_ANALOG1 USB Misc Toggle Register */
#define IMXRT_USB_ANALOG_USB2_VBUS_DETECT (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_VBUS_DETECT_OFFSET) /* USB_ANALOG1 USB VBUS Detect Register */
#define IMXRT_USB_ANALOG_USB2_VBUS_DETECT_SET (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_VBUS_DETECT_SET_OFFSET) /* USB_ANALOG1 USB VBUS Detect Set Register */
#define IMXRT_USB_ANALOG_USB2_VBUS_DETECT_CLR (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_VBUS_DETECT_CLR_OFFSET) /* USB_ANALOG1 USB VBUS Detect Clear Register */
#define IMXRT_USB_ANALOG_USB2_VBUS_DETECT_TOG (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_VBUS_DETECT_TOG_OFFSET) /* USB_ANALOG1 USB VBUS Detect Toggle Register */
#define IMXRT_USB_ANALOG_USB2_CHRG_DETECT (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_CHRG_DETECT_OFFSET) /* USB_ANALOG1 USB Charger Detect Register */
#define IMXRT_USB_ANALOG_USB2_CHRG_DETECT_SET (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_CHRG_DETECT_SET_OFFSET) /* USB_ANALOG1 USB Charger Detect Set Register */
#define IMXRT_USB_ANALOG_USB2_CHRG_DETECT_CLR (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_CHRG_DETECT_CLR_OFFSET) /* USB_ANALOG1 USB Charger Detect Clear Register */
#define IMXRT_USB_ANALOG_USB2_CHRG_DETECT_TOG (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_CHRG_DETECT_TOG_OFFSET) /* USB_ANALOG1 USB Charger Detect Toggle Register */
#define IMXRT_USB_ANALOG_USB2_VBUS_DETECT_STAT (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_VBUS_DETECT_STAT_OFFSET) /* USB_ANALOG1 USB VBUS Detect Status Register */
#define IMXRT_USB_ANALOG_USB2_CHRG_DETECT_STAT (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_CHRG_DETECT_STAT_OFFSET) /* USB_ANALOG1 USB Charger Detect Status Register */
#define IMXRT_USB_ANALOG_USB2_MISC (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_MISC_OFFSET) /* USB_ANALOG1 USB Misc Register */
#define IMXRT_USB_ANALOG_USB2_MISC_SET (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_MISC_SET_OFFSET) /* USB_ANALOG1 USB Misc Set Register */
#define IMXRT_USB_ANALOG_USB2_MISC_CLR (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_MISC_CLR_OFFSET) /* USB_ANALOG1 USB Misc Clear Register */
#define IMXRT_USB_ANALOG_USB2_MISC_TOG (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_MISC_TOG_OFFSET) /* USB_ANALOG1 USB Misc Toggle Register */
#define IMXRT_USB_ANALOG_DIGPROG (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_DIGPROG_OFFSET) /* USB_ANALOG1 Chip Silicon Version */
/* Analog USB2 Register Addresses */
#define IMXRT_USB_ANALOG_USB1_VBUS_DETECT (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_VBUS_DETECT_OFFSET) /* USB_ANALOG2 USB VBUS Detect Register */
#define IMXRT_USB_ANALOG_USB1_VBUS_DETECT_SET (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_VBUS_DETECT_SET_OFFSET) /* USB_ANALOG2 USB VBUS Detect Set Register */
#define IMXRT_USB_ANALOG_USB1_VBUS_DETECT_CLR (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_VBUS_DETECT_CLR_OFFSET) /* USB_ANALOG2 USB VBUS Detect Clear Register */
#define IMXRT_USB_ANALOG_USB1_VBUS_DETECT_TOG (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_VBUS_DETECT_TOG_OFFSET) /* USB_ANALOG2 USB VBUS Detect Toggle Register */
#define IMXRT_USB_ANALOG_USB1_CHRG_DETECT (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_CHRG_DETECT_OFFSET) /* USB_ANALOG2 USB Charger Detect Register */
#define IMXRT_USB_ANALOG_USB1_CHRG_DETECT_SET (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_CHRG_DETECT_SET_OFFSET) /* USB_ANALOG2 USB Charger Detect Set Register */
#define IMXRT_USB_ANALOG_USB1_CHRG_DETECT_CLR (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_CHRG_DETECT_CLR_OFFSET) /* USB_ANALOG2 USB Charger Detect Clear Register */
#define IMXRT_USB_ANALOG_USB1_CHRG_DETECT_TOG (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_CHRG_DETECT_TOG_OFFSET) /* USB_ANALOG2 USB Charger Detect Toggle Register */
#define IMXRT_USB_ANALOG_USB1_VBUS_DETECT_STAT (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_VBUS_DETECT_STAT_OFFSET) /* USB_ANALOG2 USB VBUS Detect Status Register */
#define IMXRT_USB_ANALOG_USB1_CHRG_DETECT_STAT (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_CHRG_DETECT_STAT_OFFSET) /* USB_ANALOG2 USB Charger Detect Status Register */
#define IMXRT_USB_ANALOG_USB1_MISC (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_MISC_OFFSET) /* USB_ANALOG2 USB Misc Register */
#define IMXRT_USB_ANALOG_USB1_MISC_SET (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_MISC_SET_OFFSET) /* USB_ANALOG2 USB Misc Set Register */
#define IMXRT_USB_ANALOG_USB1_MISC_CLR (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_MISC_CLR_OFFSET) /* USB_ANALOG2 USB Misc Clear Register */
#define IMXRT_USB_ANALOG_USB1_MISC_TOG (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_MISC_TOG_OFFSET) /* USB_ANALOG2 USB Misc Toggle Register */
#define IMXRT_USB_ANALOG_USB2_VBUS_DETECT (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_VBUS_DETECT_OFFSET) /* USB_ANALOG2 USB VBUS Detect Register */
#define IMXRT_USB_ANALOG_USB2_VBUS_DETECT_SET (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_VBUS_DETECT_SET_OFFSET) /* USB_ANALOG2 USB VBUS Detect Set Register */
#define IMXRT_USB_ANALOG_USB2_VBUS_DETECT_CLR (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_VBUS_DETECT_CLR_OFFSET) /* USB_ANALOG2 USB VBUS Detect Clear Register */
#define IMXRT_USB_ANALOG_USB2_VBUS_DETECT_TOG (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_VBUS_DETECT_TOG_OFFSET) /* USB_ANALOG2 USB VBUS Detect Toggle Register */
#define IMXRT_USB_ANALOG_USB2_CHRG_DETECT (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_CHRG_DETECT_OFFSET) /* USB_ANALOG2 USB Charger Detect Register */
#define IMXRT_USB_ANALOG_USB2_CHRG_DETECT_SET (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_CHRG_DETECT_SET_OFFSET) /* USB_ANALOG2 USB Charger Detect Set Register */
#define IMXRT_USB_ANALOG_USB2_CHRG_DETECT_CLR (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_CHRG_DETECT_CLR_OFFSET) /* USB_ANALOG2 USB Charger Detect Clear Register */
#define IMXRT_USB_ANALOG_USB2_CHRG_DETECT_TOG (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_CHRG_DETECT_TOG_OFFSET) /* USB_ANALOG2 USB Charger Detect Toggle Register */
#define IMXRT_USB_ANALOG_USB2_VBUS_DETECT_STAT (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_VBUS_DETECT_STAT_OFFSET) /* USB_ANALOG2 USB VBUS Detect Status Register */
#define IMXRT_USB_ANALOG_USB2_CHRG_DETECT_STAT (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_CHRG_DETECT_STAT_OFFSET) /* USB_ANALOG2 USB Charger Detect Status Register */
#define IMXRT_USB_ANALOG_USB2_MISC (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_MISC_OFFSET) /* USB_ANALOG2 USB Misc Register */
#define IMXRT_USB_ANALOG_USB2_MISC_SET (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_MISC_SET_OFFSET) /* USB_ANALOG2 USB Misc Set Register */
#define IMXRT_USB_ANALOG_USB2_MISC_CLR (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_MISC_CLR_OFFSET) /* USB_ANALOG2 USB Misc Clear Register */
#define IMXRT_USB_ANALOG_USB2_MISC_TOG (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_MISC_TOG_OFFSET) /* USB_ANALOG2 USB Misc Toggle Register */
#define IMXRT_USB_ANALOG_DIGPROG (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_DIGPROG_OFFSET) /* USB_ANALOG2 Chip Silicon Version */
/* Register Bit Definitions *********************************************************************************************************/
/* USB VBUS Detect Register */
#define USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0) /* Bits: 0-2 Set the threshold for the VBUSVALID comparator. */
#define USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_MASK (7 << USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)
# define USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH(n) ((uint32_t)(n) << USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)
# define USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_4V0 (0 << USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_SHIFT) /* 4V0 — 4.0V */
# define USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_4V1 (1 << USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_SHIFT) /* 4V1 — 4.1V */
# define USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_4V2 (2 << USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_SHIFT) /* 4V2 — 4.2V */
# define USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_4V3 (3 << USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_SHIFT) /* 4V3 — 4.3V */
# define USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_4V4 (4 << USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_SHIFT) /* 4V4 — 4.4V (default) */
# define USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_4V5 (5 << USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_SHIFT) /* 4V5 — 4.5V */
# define USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_4V6 (6 << USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_SHIFT) /* 4V6 — 4.6V */
# define USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_4V7 (7 << USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_SHIFT) /* 4V7 — 4.7V */
/* Bits: 3-19 Reserved */
#define USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_PWRUP_CMPS (1 << 20) /* Bit: 20 Powers up comparators for vbus_valid detector. */
/* Bits: 21-25 Reserved */
#define USB_ANALOG_USB_VBUS_DETECT_DISCHARGE_VBUS (1 << 26) /* Bit: 26 USB OTG discharge VBUS. */
#define USB_ANALOG_USB_VBUS_DETECT_CHARGE_VBUS (1 << 27) /* Bit: 27 USB OTG charge VBUS. */
/* Bits: 28-31 Reserved */
/* USB Charger Detect Register */
/* Bits: 0-17 Reserved */
#define USB_ANALOG_USB_CHRG_DETECT_CHK_CONTACT (1 << 18) /* Bit: 18 Check the contact of USB plug */
#define USB_ANALOG_USB_CHRG_DETECT_CHK_CHRG_B (1 << 19) /* Bit: 19 Check the charger connection */
#define USB_ANALOG_USB_CHRG_DETECT_EN_B (1 << 20) /* Bit: 20 Control the charger detector. */
/* Bits: 21-22 Reserved */
/* Bit: 23 Reserved */
/* Bits: 24-31 Reserved */
/* USB VBUS Detect Status Register */
#define USB_ANALOG_USB_VBUS_DETECT_STAT_SESSEND (1 << 0) /* Bit: 0 Session End for USB OTG. */
#define USB_ANALOG_USB_VBUS_DETECT_STAT_BVALID (1 << 1) /* Bit: 1 Indicates VBus is valid for a B-peripheral. */
#define USB_ANALOG_USB_VBUS_DETECT_STAT_AVALID (1 << 2) /* Bit: 2 Indicates VBus is valid for a A-peripheral. */
#define USB_ANALOG_USB_VBUS_DETECT_STAT_VBUS_VALID (1 << 3) /* Bit: 3 VBus valid for USB OTG. */
/* Bits: 4-31 Reserved */
/* USB Charger Detect Status Register */
#define USB_ANALOG_USB_CHRG_DETECT_STAT_PLUG_CONTACT (1 << 0) /* Bit: 0 State of the USB plug contact detector. */
#define USB_ANALOG_USB_CHRG_DETECT_STAT_CHRG_ (1 << 1) /* Bit: 1 DETECTED */
#define USB_ANALOG_USB_CHRG_DETECT_STAT_DM_STATE (1 << 2) /* Bit: 2 DM line state output of the charger detector. */
#define USB_ANALOG_USB_CHRG_DETECT_STAT_DP_STATE (1 << 3) /* Bit: 3 DP line state output of the charger detector. */
/* Bits: 4-31 Reserved */
/* USB Misc Register */
#define USB_ANALOG_USB_MISC_HS_USE_EXTERNAL_R (1 << 0) /* Bit: 0 Use external resistor to generate the current bias for the high speed transmitter. */
#define USB_ANALOG_USB_MISC_EN_DEGLITCH (1 << 1) /* Bit: 1 Enable the deglitching circuit of the USB PLL output. */
/* Bits: 2-29 Reserved */
#define USB_ANALOG_USB_MISC_EN_CLK_UTMI (1 << 30) /* Bit: 30 Enables the clk to the UTMI block. */
/* Bit: 31 Reserved */
/* Chip Silicon Version */
#define USB_ANALOG_DIGPROG_SILICON_REVISION 0x006C0000 /* Silicon revision 1.0 */
#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_USB_ANALOG_H */
arch/arm/src/imxrt/chip/imxrt_usdhc.h
-555
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arch/arm/src/imxrt/chip/imxrt_wdog.h
-142
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/************************************************************************************
* arch/arm/src/imxrt/imxrt_wdog.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Janne Rosberg <janne@offcode.fi>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_WDOG_H
#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_WDOG_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip/imxrt_memorymap.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register offsets *****************************************************************/
#define IMXRT_WDOG_WCR_OFFSET 0x0000 /* Watchdog control register */
#define IMXRT_WDOG_WSR_OFFSET 0x0002 /* Watchdog service register */
#define IMXRT_WDOG_WRSR_OFFSET 0x0004 /* Watchdog reset status */
#define IMXRT_WDOG_WICR_OFFSET 0x0006 /* Watchdog interrupt control */
#define IMXRT_WDOG_WMCR_OFFSET 0x0008 /* Watchdog misc control */
#define IMXRT_RTWDOG_CS_OFFSET 0x0000 /* Watchdog control and status register */
#define IMXRT_RTWDOG_CNT_OFFSET 0x0004 /* Watchdog counter register */
#define IMXRT_RTWDOG_TOVAL_OFFSET 0x0008 /* Watchdog timeout value register */
#define IMXRT_RTWDOG_WIN_OFFSET 0x000c /* Watchdog window register */
/* Register addresses ***************************************************************/
#define IMXRT_WDOG1_WCR (IMXRT_WDOG1_BASE + IMXRT_WDOG_WCR_OFFSET)
#define IMXRT_WDOG1_WSR (IMXRT_WDOG1_BASE + IMXRT_WDOG_WSR_OFFSET)
#define IMXRT_WDOG1_WRSR (IMXRT_WDOG1_BASE + IMXRT_WDOG_WRSR_OFFSET)
#define IMXRT_WDOG1_WICR (IMXRT_WDOG1_BASE + IMXRT_WDOG_WICR_OFFSET)
#define IMXRT_WDOG1_WMCR (IMXRT_WDOG1_BASE + IMXRT_WDOG_WMCR_OFFSET)
#define IMXRT_WDOG2_WCR (IMXRT_WDOG2_BASE + IMXRT_WDOG_WCR_OFFSET)
#define IMXRT_WDOG2_WSR (IMXRT_WDOG2_BASE + IMXRT_WDOG_WSR_OFFSET)
#define IMXRT_WDOG2_WRSR (IMXRT_WDOG2_BASE + IMXRT_WDOG_WRSR_OFFSET)
#define IMXRT_WDOG2_WMCR (IMXRT_WDOG2_BASE + IMXRT_WDOG_WMCR_OFFSET)
#define IMXRT_RTWDOG_CS (IMXRT_WDOG3_BASE + IMXRT_RTWDOG_CS_OFFSET)
#define IMXRT_RTWDOG_CNT (IMXRT_WDOG3_BASE + IMXRT_RTWDOG_CNT_OFFSET)
#define IMXRT_RTWDOG_TOVAL (IMXRT_WDOG3_BASE + IMXRT_RTWDOG_TOVAL_OFFSET)
#define IMXRT_RTWDOG_WIN (IMXRT_WDOG3_BASE + IMXRT_RTWDOG_WIN_OFFSET)
/* Register bit definitions *********************************************************/
/* Watchdog control and status register */
#define WDOG_WCR_WDZST (1 << 0) /* Bit 0: Watchdog Low Power */
#define WDOG_WCR_WDBG (1 << 1) /* Bit 1: Watchdog DEBUG Enable */
#define WDOG_WCR_WDE (1 << 2) /* Bit 2: Watchdog Enable */
#define WDOG_WCR_WDT (1 << 3) /* Bit 3: WDOG_B Time-out assertion */
#define WDOG_WCR_SRS (1 << 4) /* Bit 4: Software Reset Signal */
#define WDOG_WCR_WDA (1 << 5) /* Bit 5: WDOG_B assertion */
#define WDOG_WCR_SRE (1 << 6) /* Bit 6: Software reset extension */
#define WDOG_WCR_WDW (1 << 7) /* Bit 7: Watchdog Disable for Wait */
#define WDOG_WCR_WT_SHIFT (8) /* Bits 8-15: Watchdog time-out value */
#define WDOG_WCR_WT_MASK (0xff << WDOG_WCR_WT_SHIFT)
# define WDOG_WCR_WT(n) ((uint16_t)((n)) << WDOG_WCR_WT_SHIFT)
/* Watchdog reset status */
#define WDOG_WRSR_SFTW (1 << 0) /* Bit 0: Software Reset */
#define WDOG_WRSR_TOUT (1 << 1) /* Bit 1: Timeout */
/* Bits 2-3: reserved */
#define WDOG_WRSR_POR (1 << 4) /* Bit 4: Power on reset */
/* Bits 5-15: Reserved */
/* Watchdog interrupt control */
#define WDOG_WICR_WICT_SHIFT (0) /* Bits 0-7: Watchdog Interrupt Count Time-out */
#define WDOG_WICR_WICT_MASK (0xff << WDOG_WCR_WT_SHIFT)
# define WDOG_WICR_WICT(n) ((uint16_t)((n)) << WDOG_WICR_WICT_SHIFT)
/* Bits 8-13: Reserved */
#define WDOG_WICR_WTIS (1 << 14) /* Bit 14: Watchdog Timer Interrupt Status */
#define WDOG_WICR_WIE (1 << 15) /* Bit 15: Watchdog Timer Interrupt enable */
/* Watchdog misc control */
#define WDOG_WMCR_PDE (1 << 0) /* Bit 0: Power Down Enable */
/* Bits 1-15: Reserved */
/* RT Watchdog Control and Status Register */
#define RTWDOG_CS_STOP (1 << 0) /* Bit 0: Stop enable */
#define RTWDOG_CS_WAIT (1 << 1) /* Bit 1: Wait enable */
#define RTWDOG_CS_DBG (1 << 2) /* Bit 2: Debug Enable */
#define RTWDOG_CS_TST_SHIFT (3) /* Bits 3-4: Enables the fast test mode */
#define RTWDOG_CS_TST_MASK (0x03 << RTWDOG_CS_TST_SHIFT)
# define RTWDOG_CS_TST(n) ((uint32_t)((n)) << RTWDOG_CS_TST_SHIFT)
#define RTWDOG_CS_UPDATE (1 << 5) /* Bit 5: Update */
#define RTWDOG_CS_INT (1 << 6) /* Bit 6: Interrupt */
#define RTWDOG_CS_EN (1 << 7) /* Bit 7: Enable */
#define RTWDOG_CS_CLK_SHIFT (8) /* Bits 8-9: Clock */
#define RTWDOG_CS_CLK_MASK (0x03 << RTWDOG_CS_CLK_SHIFT)
# define RTWDOG_CS_CLK(n) ((uint32_t)((n)) << RTWDOG_CS_CLK_SHIFT)
#define RTWDOG_CS_RCS (1 << 10) /* Bit 10: Reconfiguration Success */
#define RTWDOG_CS_ULK (1 << 11) /* Bit 11: Unlock status */
#define RTWDOG_CS_PRES (1 << 12) /* Bit 12: Watchdog prescaler */
#define RTWDOG_CS_CMD32EN (1 << 13) /* Bit 13: WDOG support for 32-bit */
#define RTWDOG_CS_FLG (1 << 14) /* Bit 14: Interrupt Flag */
#define RTWDOG_CS_WIN (1 << 15) /* Bit 15: Watchdog Window */
#define RTWDOG_UPDATE_KEY (0xd928c520)
#define RTWDOG_REFRESH_KEY (0xb480a602)
#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_WDOG_H */
arch/arm/src/imxrt/chip/imxrt_xbar.h
-74
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/************************************************************************************
* arch/arm/src/imxrt/chip/imxrt_abar.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_XBAR_H
#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_XBAR_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include "chip/imxrt_memorymap.h"
#if defined(CONFIG_ARCH_FAMILY_IMXRT102x)
# include "chip/rt102x/imxrt102x_xbar.h"
#elif defined(CONFIG_ARCH_FAMILY_IMXRT105x)
# include "chip/rt105x/imxrt105x_xbar.h"
#elif defined(CONFIG_ARCH_FAMILY_IMXRT106x)
# include "chip/rt106x/imxrt106x_xbar.h"
#else
# error Unrecognized i.MX RT architecture
#endif
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
#define IMXRT_SEL_PER_REG 2
#define IMXRT_SEL0_SHIFTS 0 /* Bits 0-6: Input (XBARA_INn) to be muxed to
* XBARA_OUTm */
#define IMXRT_SEL0_MASK (0x7f << IMXRT_SEL0_SHIFTS)
/* Bit 7: Reserved */
#define IMXRT_SEL1_SHIFTS 8 /* Bits 8-14: Input (XBARA_INn) to be muxed to
* XBARA_OUTm */
#define IMXRT_SEL1_MASK (0x7f << IMXRT_SEL1_SHIFTS)
/* Bit 15 Reserved */
#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_XBAR_H */
arch/arm/src/imxrt/chip/rt102x/imxrt102x_ccm.h
-970
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arch/arm/src/imxrt/chip/rt102x/imxrt102x_dmamux.h
-143
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@@ -1,143 +0,0 @@
/*****************************************************************************
* arch/arm/src/imxrt/chip/rt102x/imxrt102x_dmamux.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Dave Marples <dave@marples.net>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_DMAMUX_H
#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_DMAMUX_H
/*****************************************************************************
* Included Files
*****************************************************************************/
#include <nuttx/config.h>
/*****************************************************************************
* Preprocessor Definitions
*****************************************************************************/
/* Peripheral DMA request channels */
#define IMXRT_DMACHAN_FLEXIO1_01 0 /* FlexIO1 DMA 0/1, Async DMA 0/1 */
#define IMXRT_DMACHAN_FLEXIO1_45 1 /* FlexIO1 DMA 4/5, Async DMA 4/5 */
#define IMXRT_DMACHAN_LPUART1_TX 2 /* LPUART1 TX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPUART1_RX 3 /* LPUART1 RX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPUART3_TX 4 /* LPUART3 RX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPUART3_RX 5 /* LPUART3 RX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPUART5_TX 6 /* LPUART5 TX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPUART5_RX 7 /* LPUART5 RX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPUART7_TX 8 /* LPUART7 TX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPUART7_RX 9 /* LPUART7 RX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPSPI1_RX 13 /* LPSPI1 RX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPSPI1_TX 14 /* LPSPI1 TX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPSPI3_RX 15 /* LPSPI3 RX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPSPI3_TX 16 /* LPSPI3 TX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPI2C1 17 /* LPI2C1 Master/Slave RX/TX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPI2C3 18 /* LPI2C3 Master/Slave RX/TX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_SAI1_RX 19 /* SAI1 RX FIFO DMA */
#define IMXRT_DMACHAN_SAI1_TX 20 /* SAI1 TX FIFO DMA */
#define IMXRT_DMACHAN_SAI2_RX 21 /* SAI2 RX FIFO DMA */
#define IMXRT_DMACHAN_SAI2_TX 22 /* SAI2 TX FIFO DMA */
#define IMXRT_DMACHAN_ADC_ETC 23 /* ADC ETC DMA */
#define IMXRT_DMACHAN_ADC1 24 /* ADC1 DMA */
#define IMXRT_DMACHAN_ACMP1 25 /* ACMP1 DMA */
#define IMXRT_DMACHAN_ACMP3 26 /* ACMP3 DMA */
#define IMXRT_DMACHAN_FLEXSPI_RX 28 /* FlexSPI RX FIFO DMA */
#define IMXRT_DMACHAN_FLEXSPI_TX 29 /* FlexSPI TX FIFO DMA */
#define IMXRT_DMACHAN_XBAR1_0 30 /* XBAR1 DMA 0 */
#define IMXRT_DMACHAN_XBAR1_1 31 /* XBAR1 DMA 1 */
#define IMXRT_DMACHAN_FLEXPWM1_RX0 32 /* FlexPWM1 RX sub-module0 capture */
#define IMXRT_DMACHAN_FLEXPWM1_RX1 33 /* FlexPWM1 RX sub-module1 capture */
#define IMXRT_DMACHAN_FLEXPWM1_RX2 34 /* FlexPWM1 RX sub-module2 capture */
#define IMXRT_DMACHAN_FLEXPWM1_RX3 35 /* FlexPWM1 RX sub-module3 capture */
#define IMXRT_DMACHAN_FLEXPWM1_TX0 36 /* FlexPWM1 TX sub-module0 value */
#define IMXRT_DMACHAN_FLEXPWM1_TX1 37 /* FlexPWM1 TX sub-module1 value */
#define IMXRT_DMACHAN_FLEXPWM1_TX2 38 /* FlexPWM1 TX sub-module2 value */
#define IMXRT_DMACHAN_FLEXPWM1_TX3 39 /* FlexPWM1 TX sub-module3 value */
#define IMXRT_DMACHAN_QTIMER1_RX0 48 /* QTimer1 RX capture timer 0 */
#define IMXRT_DMACHAN_QTIMER1_RX1 49 /* QTimer1 RX capture timer 1 */
#define IMXRT_DMACHAN_QTIMER1_RX2 50 /* QTimer1 RX capture timer 2 */
#define IMXRT_DMACHAN_QTIMER1_RX3 51 /* QTimer1 RX capture timer 3 */
#define IMXRT_DMACHAN_QTIMER1_TX0 52 /* QTimer1 TX cmpld1 timer 0 / cmld2 timer 1 */
#define IMXRT_DMACHAN_QTIMER1_TX1 53 /* QTimer1 TX cmpld1 timer 1 / cmld2 timer 0 */
#define IMXRT_DMACHAN_QTIMER1_TX2 54 /* QTimer1 TX cmpld1 timer 2 / cmld2 timer 3 */
#define IMXRT_DMACHAN_QTIMER1_TX3 55 /* QTimer1 TX cmpld1 timer 3 / cmld2 timer 2 */
#define IMXRT_DMACHAN_FLEXIO1_23 64 /* FlexIO1 DMA 2 / Async DMA 2 / DMA 3 / Async DMA 3 */
#define IMXRT_DMACHAN_FLEXIO1_67 65 /* FlexIO1 DMA 6 / Async DMA 6 / DMA 7 / Async DMA 7 */
#define IMXRT_DMACHAN_LPUART2_TX 66 /* LPUART2 TX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPUART2_RX 67 /* LPUART2 RX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPUART4_TX 68 /* LPUART4 TX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPUART4_RX 69 /* LPUART4 RX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPUART6_TX 70 /* LPUART6 TX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPUART6_RX 71 /* LPUART6 RX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPUART8_TX 72 /* LPUART8 TX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPUART8_RX 73 /* LPUART8 RX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPSPI2_RX 77 /* LPSPI2 RX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPSPI2_TX 78 /* LPSPI2 TX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPSPI4_RX 79 /* LPSPI4 RX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPSPI4_TX 80 /* LPSPI4 TX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPI2C2 81 /* LPI2C2 Master/Slave RX/TX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPI2C4 82 /* LPI2C4 Master/Slave RX/TX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_SAI3_RX 83 /* SAI3 RX FIFO DMA */
#define IMXRT_DMACHAN_SAI3_TX 84 /* SAI3 RX FIFO DMA */
#define IMXRT_DMACHAN_SPDIF_RX 85 /* SPDIF RX DMA */
#define IMXRT_DMACHAN_SPDIF_TX 86 /* SPDIF TX DMA */
#define IMXRT_DMACHAN_ADC2 88 /* ADC2 DMA */
#define IMXRT_DMACHAN_ACMP2 89 /* ACMP2 DMA */
#define IMXRT_DMACHAN_ACMP4 90 /* ACMP4 DMA */
#define IMXRT_DMACHAN_ENET_0 92 /* ENET Timer DMA 0 */
#define IMXRT_DMACHAN_ENET_1 93 /* ENET Timer DMA 1 */
#define IMXRT_DMACHAN_XBAR1_2 94 /* XBAR1 DMA 2 */
#define IMXRT_DMACHAN_XBAR1_3 95 /* XBAR1 DMA 3 */
#define IMXRT_DMACHAN_FLEXPWM2_RX0 96 /* FlexPWM2 RX sub-module0 capture */
#define IMXRT_DMACHAN_FLEXPWM2_RX1 97 /* FlexPWM2 RX sub-module1 capture */
#define IMXRT_DMACHAN_FLEXPWM2_RX2 98 /* FlexPWM2 RX sub-module2 capture */
#define IMXRT_DMACHAN_FLEXPWM2_RX3 99 /* FlexPWM2 RX sub-module3 capture */
#define IMXRT_DMACHAN_FLEXPWM2_TX0 100 /* FlexPWM2 TX sub-module0 value */
#define IMXRT_DMACHAN_FLEXPWM2_TX1 101 /* FlexPWM2 TX sub-module1 value */
#define IMXRT_DMACHAN_FLEXPWM2_TX2 102 /* FlexPWM2 TX sub-module2 value */
#define IMXRT_DMACHAN_FLEXPWM2_TX3 103 /* FlexPWM2 TX sub-module3 value */
#define IMXRT_DMACHAN_QTIMER2_RX0 112 /* QTimer2 RX capture timer 0 */
#define IMXRT_DMACHAN_QTIMER2_RX1 113 /* QTimer2 RX capture timer 1 */
#define IMXRT_DMACHAN_QTIMER2_RX2 114 /* QTimer2 RX capture timer 2 */
#define IMXRT_DMACHAN_QTIMER2_RX3 115 /* QTimer2 RX capture timer 3 */
#define IMXRT_DMACHAN_QTIMER2_TX0 116 /* QTimer2 TX cmpld1 timer 0 / cmld2 timer 1 */
#define IMXRT_DMACHAN_QTIMER2_TX1 117 /* QTimer2 TX cmpld1 timer 1 / cmld2 timer 0 */
#define IMXRT_DMACHAN_QTIMER2_TX2 118 /* QTimer2 TX cmpld1 timer 2 / cmld2 timer 3 */
#define IMXRT_DMACHAN_QTIMER2_TX3 119 /* QTimer2 TX cmpld1 timer 3 / cmld2 timer 2 */
#define IMXRT_DMA_NCHANNELS 128 /* Includes reserved channels */
#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_DMAMUX_H */
arch/arm/src/imxrt/chip/rt102x/imxrt102x_gpio.h
-116
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@@ -1,116 +0,0 @@
/*****************************************************************************
* arch/arm/src/imxrt/chip/rt102x/imxrt105x_gpio.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
* Dave Marples <dave@marples.net>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_GPIO_H
#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_GPIO_H
/*****************************************************************************
* Included Files
*****************************************************************************/
#include <nuttx/config.h>
#include "chip/imxrt_memorymap.h"
/*****************************************************************************
* Pre-processor Definitions
*****************************************************************************/
/* Register offsets **********************************************************/
#define IMXRT_GPIO_DR_OFFSET 0x0000 /* GPIO data register */
#define IMXRT_GPIO_GDIR_OFFSET 0x0004 /* GPIO direction register */
#define IMXRT_GPIO_PSR_OFFSET 0x0008 /* GPIO pad status register */
#define IMXRT_GPIO_ICR1_OFFSET 0x000c /* GPIO interrupt configuration register1 */
#define IMXRT_GPIO_ICR2_OFFSET 0x0010 /* GPIO interrupt configuration register2 */
#define IMXRT_GPIO_IMR_OFFSET 0x0014 /* GPIO interrupt mask register */
#define IMXRT_GPIO_ISR_OFFSET 0x0018 /* GPIO interrupt status register */
#define IMXRT_GPIO_EDGE_OFFSET 0x001c /* GPIO edge select register */
#define IMXRT_GPIO_SET_OFFSET 0x0084 /* GPIO data register SET */
#define IMXRT_GPIO_CLEAR_OFFSET 0x0088 /* GPIO data register CLEAR */
#define IMXRT_GPIO_TOGGLE_OFFSET 0x008c /* GPIO data register TOGGLE */
/* Register addresses ********************************************************/
#define IMXRT_GPIO1_DR (IMXRT_GPIO1_BASE + IMXRT_GPIO_DR_OFFSET)
#define IMXRT_GPIO1_GDIR (IMXRT_GPIO1_BASE + IMXRT_GPIO_GDIR_OFFSET)
#define IMXRT_GPIO1_PSR (IMXRT_GPIO1_BASE + IMXRT_GPIO_PSR_OFFSET)
#define IMXRT_GPIO1_ICR1 (IMXRT_GPIO1_BASE + IMXRT_GPIO_ICR1_OFFSET)
#define IMXRT_GPIO1_ICR2 (IMXRT_GPIO1_BASE + IMXRT_GPIO_ICR2_OFFSET)
#define IMXRT_GPIO1_IMR (IMXRT_GPIO1_BASE + IMXRT_GPIO_IMR_OFFSET)
#define IMXRT_GPIO1_ISR (IMXRT_GPIO1_BASE + IMXRT_GPIO_ISR_OFFSET)
#define IMXRT_GPIO1_EDGE (IMXRT_GPIO1_BASE + IMXRT_GPIO_EDGE_OFFSET)
#define IMXRT_GPIO1_SET (IMXRT_GPIO1_BASE + IMXRT_GPIO_SET_OFFSET)
#define IMXRT_GPIO1_CLEAR (IMXRT_GPIO1_BASE + IMXRT_GPIO_CLEAR_OFFSET)
#define IMXRT_GPIO1_TOGGLE (IMXRT_GPIO1_BASE + IMXRT_GPIO_TOGGLE_OFFSET)
#define IMXRT_GPIO2_DR (IMXRT_GPIO2_BASE + IMXRT_GPIO_DR_OFFSET)
#define IMXRT_GPIO2_GDIR (IMXRT_GPIO2_BASE + IMXRT_GPIO_GDIR_OFFSET)
#define IMXRT_GPIO2_PSR (IMXRT_GPIO2_BASE + IMXRT_GPIO_PSR_OFFSET)
#define IMXRT_GPIO2_ICR1 (IMXRT_GPIO2_BASE + IMXRT_GPIO_ICR1_OFFSET)
#define IMXRT_GPIO2_ICR2 (IMXRT_GPIO2_BASE + IMXRT_GPIO_ICR2_OFFSET)
#define IMXRT_GPIO2_IMR (IMXRT_GPIO2_BASE + IMXRT_GPIO_IMR_OFFSET)
#define IMXRT_GPIO2_ISR (IMXRT_GPIO2_BASE + IMXRT_GPIO_ISR_OFFSET)
#define IMXRT_GPIO2_EDGE (IMXRT_GPIO2_BASE + IMXRT_GPIO_EDGE_OFFSET)
#define IMXRT_GPIO2_SET (IMXRT_GPIO2_BASE + IMXRT_GPIO_SET_OFFSET)
#define IMXRT_GPIO2_CLEAR (IMXRT_GPIO2_BASE + IMXRT_GPIO_CLEAR_OFFSET)
#define IMXRT_GPIO2_TOGGLE (IMXRT_GPIO2_BASE + IMXRT_GPIO_TOGGLE_OFFSET)
#define IMXRT_GPIO3_DR (IMXRT_GPIO3_BASE + IMXRT_GPIO_DR_OFFSET)
#define IMXRT_GPIO3_GDIR (IMXRT_GPIO3_BASE + IMXRT_GPIO_GDIR_OFFSET)
#define IMXRT_GPIO3_PSR (IMXRT_GPIO3_BASE + IMXRT_GPIO_PSR_OFFSET)
#define IMXRT_GPIO3_ICR1 (IMXRT_GPIO3_BASE + IMXRT_GPIO_ICR1_OFFSET)
#define IMXRT_GPIO3_ICR2 (IMXRT_GPIO3_BASE + IMXRT_GPIO_ICR2_OFFSET)
#define IMXRT_GPIO3_IMR (IMXRT_GPIO3_BASE + IMXRT_GPIO_IMR_OFFSET)
#define IMXRT_GPIO3_ISR (IMXRT_GPIO3_BASE + IMXRT_GPIO_ISR_OFFSET)
#define IMXRT_GPIO3_EDGE (IMXRT_GPIO3_BASE + IMXRT_GPIO_EDGE_OFFSET)
#define IMXRT_GPIO3_SET (IMXRT_GPIO3_BASE + IMXRT_GPIO_SET_OFFSET)
#define IMXRT_GPIO3_CLEAR (IMXRT_GPIO3_BASE + IMXRT_GPIO_CLEAR_OFFSET)
#define IMXRT_GPIO3_TOGGLE (IMXRT_GPIO3_BASE + IMXRT_GPIO_TOGGLE_OFFSET)
#define IMXRT_GPIO5_DR (IMXRT_GPIO5_BASE + IMXRT_GPIO_DR_OFFSET)
#define IMXRT_GPIO5_GDIR (IMXRT_GPIO5_BASE + IMXRT_GPIO_GDIR_OFFSET)
#define IMXRT_GPIO5_PSR (IMXRT_GPIO5_BASE + IMXRT_GPIO_PSR_OFFSET)
#define IMXRT_GPIO5_ICR1 (IMXRT_GPIO5_BASE + IMXRT_GPIO_ICR1_OFFSET)
#define IMXRT_GPIO5_ICR2 (IMXRT_GPIO5_BASE + IMXRT_GPIO_ICR2_OFFSET)
#define IMXRT_GPIO5_IMR (IMXRT_GPIO5_BASE + IMXRT_GPIO_IMR_OFFSET)
#define IMXRT_GPIO5_ISR (IMXRT_GPIO5_BASE + IMXRT_GPIO_ISR_OFFSET)
#define IMXRT_GPIO5_EDGE (IMXRT_GPIO5_BASE + IMXRT_GPIO_EDGE_OFFSET)
#define IMXRT_GPIO5_SET (IMXRT_GPIO5_BASE + IMXRT_GPIO_SET_OFFSET)
#define IMXRT_GPIO5_CLEAR (IMXRT_GPIO5_BASE + IMXRT_GPIO_CLEAR_OFFSET)
#define IMXRT_GPIO5_TOGGLE (IMXRT_GPIO5_BASE + IMXRT_GPIO_TOGGLE_OFFSET)
#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_GPIO_H */
arch/arm/src/imxrt/chip/rt102x/imxrt102x_iomuxc.h
-1606
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arch/arm/src/imxrt/chip/rt102x/imxrt102x_memorymap.h
-261
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@@ -1,261 +0,0 @@
/****************************************************************************
* arch/arm/src/imxrt/chip/rt102x/imxrt102x_memorymap.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Dave Marples <dave@marples.net>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_MEMORYMAP_H
#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_MEMORYMAP_H
/*****************************************************************************
* Included Files
*****************************************************************************/
#include <nuttx/config.h>
/*****************************************************************************
* Pre-processor Definitions
*****************************************************************************/
/* System memory map */
#define IMXRT_ITCM_BASE 0x00000000 /* 256KB ITCM */
/* 0x00040000 768KB ITCM Reserved */
/* 0x00100000 1MB ITCM Reserved */
#define IMXRT_ROMCP_BASE 0x00200000 /* 96KB ROMCP */
/* 0x00218000 416KB ROMCP Reserved */
/* 0x00280000 1536KB Reserved */
/* 0x00400000 124MB Reserved */
/* 0x00800000 1527MB Reserved */
#define IMXRT_FLEXSPI_BASE 0x06000000 /* 128MB FlexSPI (Aliased) */
#define IMXRT_SEMCA_BASE 0x06800000 /* 639MB SEMC (Aliased) */
/* 0x90000000 256MB SEMC (Aliased) */
#define IMXRT_DTCM_BASE 0x20000000 /* 256KB DTCM */
/* 0x20040000 768KB DTCM Reserved */
/* 0x20100000 1MB Reserved */
#define IMXRT_OCRAM_BASE 0x20200000 /* 256KB OCRAM */
/* 0x20240000 1792KB OCRAM Reserved */
/* 0x20400000 252MB Reserved */
/* 0x30000000 256MB Reserved */
#define IMXRT_AIPS1_BASE 0x40000000 /* 1MB AIPS-1 */
#define IMXRT_AIPS2_BASE 0x40100000 /* 1MB AIPS-2 */
#define IMXRT_AIPS3_BASE 0x40200000 /* 1MB AIPS-3 */
#define IMXRT_AIPS4_BASE 0x40300000 /* 1MB AIPS-4 */
/* 0x40400000 12MB Reserved */
/* 0x41000000 1MB Reserved */
#define IMXRT_MCNF_BASE 0x41100000 /* 1MB "m" configuration port */
/* 41200000 1MB Reserved for "per" GPV */
/* 41300000 1MB Reserved for "ems" GPV */
#define IMXRT_CPUCNF_BASE 0x41400000 /* 1MB "cpu" configuration port */
/* 0x41500000 1MB GPV Reserved */
/* 0x41600000 1MB GPV Reserved */
/* 0x41700000 1MB GPV Reserved */
/* 0x41800000 8MB Reserved */
/* 0x42000000 32MB Reserved */
/* 0x44000000 64MB Reserved */
/* 0x48000000 384MB Reserved */
#define IMXRT_FLEXCIPHER_BASE 0x60000000 /* 504MB FlexSPI/ FlexSPI ciphertext */
#define IMXRT_FLEXSPITX_BASE 0x7f800000 /* 4MB FlexSPI TX FIFO */
#define IMXRT_FLEXSPIRX_BASE 0x7fc00000 /* 4MB FlexSPI RX FIFO */
#define IMXRT_EXTMEM_BASE 0x80000000 /* 1.5GB SEMC external memories shared memory space */
#define IMXRT_CM7_BASE 0xe0000000 /* 1MB CM7 PPB */
/* 0xe0100000 511MB Reserved */
/* AIPS-1 memory map */
/* 0x40000000 256KB Reserved */
/* 0x40040000 240KB Reserved */
#define IMXRT_AIPS1CNF_BASE 0x4007c000 /* 16KB AIPS-1 Configuration */
#define IMXRT_DCDC_BASE 0x40080000 /* 16KB DCDC */
#define IMXRT_PIT_BASE 0x40084000 /* 16KB PIT */
/* 0x40088000 16KB Reserved */
/* 0x4008c000 16KB Reserved */
/* 0x40090000 16KB Reserved */
#define IMXRT_ACMP_BASE 0x40094000 /* 16KB ACMP */
/* 0x40098000 16KB Reserved */
/* 0x4009c000 16KB Reserved */
/* 0x400a0000 16KB Reserved */
#define IMXRT_IOMUXCSNVSGPR_BASE 0x400a4000 /* 16KB IOMUXC_SNVS_GPR */
#define IMXRT_IOMUXCSNVS_BASE 0x400a8000 /* 16KB IOMUXC_SNVS */
#define IMXRT_IOMUXCGPR_BASE 0x400ac000 /* 16KB IOMUXC_GPR */
#define IMXRT_FLEXRAM_BASE 0x400b0000 /* 16KB CM7_MXRT(FLEXRAM) */
#define IMXRT_EWM_BASE 0x400b4000 /* 16KB EWM */
#define IMXRT_WDOG1_BASE 0x400b8000 /* 16KB WDOG1 */
#define IMXRT_WDOG3_BASE 0x400bc000 /* 16KB WDOG3 */
#define IMXRT_GPIO5_BASE 0x400c0000 /* 16KB GPIO5 */
#define IMXRT_ADC1_BASE 0x400c4000 /* 16KB ADC1 */
#define IMXRT_ADC2_BASE 0x400c8000 /* 16KB ADC2 */
#define IMXRT_TRNG_BASE 0x400cc000 /* 16KB TRNG */
#define IMXRT_WDOG2_BASE 0x400d0000 /* 16KB WDOG2 */
#define IMXRT_SNVSHP_BASE 0x400d4000 /* 16KB SNVS_HP */
#define IMXRT_ANATOP_BASE 0x400d8000 /* 16KB ANATOP */
#define IMXRT_CSU_BASE 0x400dc000 /* 16KB CSU */
/* 0x400e0000 16KB Reserved */
/* 0x400e4000 16KB Reserved */
#define IMXRT_EDMA_BASE 0x400e8000 /* 16KB EDMA */
#define IMXRT_DMAMUX_BASE 0x400ec000 /* 16KB DMA_CH_MUX */
/* 400f0000 16KB Reserved */
#define IMXRT_GPC_BASE 0x400f4000 /* 16KB GPC */
#define IMXRT_SRC_BASE 0x400f8000 /* 16KB SRC */
#define IMXRT_CCM_BASE 0x400fc000 /* 16KB CCM */
/* AIPS-2 memory map */
/* 0x40100000 256KB Reserved */
/* 0x40140000 240KB Reserved */
#define IMXRT_AIPS2CNF_BASE 0x4017c000 /* 16KB AIPS-2 Configuration */
#define IMXRT_ROMCPC_BASE 0x40180000 /* 16KB ROMCP controller*/
#define IMXRT_LPUART1_BASE 0x40184000 /* 16KB LPUART1 */
#define IMXRT_LPUART2_BASE 0x40188000 /* 16KB LPUART2 */
#define IMXRT_LPUART3_BASE 0x4018c000 /* 16KB LPUART3 */
#define IMXRT_LPUART4_BASE 0x40190000 /* 16KB LPUART4 */
#define IMXRT_LPUART5_BASE 0x40194000 /* 16KB LPUART5 */
#define IMXRT_LPUART6_BASE 0x40198000 /* 16KB LPUART6 */
#define IMXRT_LPUART7_BASE 0x4019c000 /* 16KB LPUART7 */
#define IMXRT_LPUART8_BASE 0x401a0000 /* 16KB LPUART8 */
/* 0x401a4000 16KB Reserved */
/* 0x401a8000 16KB Reserved */
#define IMXRT_FLEXIO1_BASE 0x401ac000 /* 16KB FlexIO1 */
/* 0x401b0000 16KB Reserved */
/* 0x401b4000 16KB Reserved */
#define IMXRT_GPIO1_BASE 0x401b8000 /* 16KB GPIO1 */
#define IMXRT_GPIO2_BASE 0x401bc000 /* 16KB GPIO2 */
#define IMXRT_GPIO3_BASE 0x401c0000 /* 16KB GPIO3 */
/* 0x401c4000 16KB Reserved */
/* 0x401c8000 16KB Reserved */
/* 0x401cc000 16KB Reserved */
#define IMXRT_CAN1_BASE 0x401d0000 /* 16KB CAN1 */
#define IMXRT_CAN2_BASE 0x401d4000 /* 16KB CAN2 */
/* 0x401d8000 16KB Reserved */
#define IMXRT_QTIMER1_BASE 0x401dc000 /* 16KB QTimer1 */
#define IMXRT_QTIMER2_BASE 0x401e0000 /* 16KB QTimer2 */
/* 0x401e4000 16KB Reserved */
/* 0x401e8000 16KB Reserved */
#define IMXRT_GPT1_BASE 0x401ec000 /* 16KB GPT1 */
#define IMXRT_GPT2_BASE 0x401f0000 /* 16KB GPT2 */
#define IMXRT_OCOTP_BASE 0x401f4000 /* 16KB OCOTP */
#define IMXRT_IOMUXC_BASE 0x401f8000 /* 16KB IOMUXC */
#define IMXRT_KPP_BASE 0x401fc000 /* 16KB KPP */
/* AIPS-3 memory map */
/* 0x40200000 256KB Reserved */
/* 0x40240000 240KB Reserved */
#define IMXRT_AIOS3CNF_BASE 0x4027c000 /* 16KB AIPS-3 Configuration */
/* 0x40280000 16KB Reserved */
/* 0x40284000 16KB Reserved */
/* 0x40288000 16KB Reserved */
/* 0x4028c000 16KB Reserved */
/* 0x40290000 16KB Reserved */
/* 0x40294000 16KB Reserved */
/* 0x40298000 16KB Reserved */
/* 0x4029c000 16KB Reserved */
/* 0x402a0000 16KB Reserved */
/* 0x402a4000 16KB Reserved */
#define IMXRT_FLEXSPIC_BASE 0x402a8000 /* 16KB FlexSPI controller */
/* 0x402ac000 16KB Reserved */
/* 0x402b0000 16KB Reserved */
/* 0x402b4000 16KB Reserved */
/* 0x402b8000 16KB Reserved */
/* 0x402bc000 16KB Reserved */
#define IMXRT_USDHC1_BASE 0x402c0000 /* 16KB USDHC1 */
#define IMXRT_USDHC2_BASE 0x402c4000 /* 16KB USDHC2 */
/* 0x402c8000 16KB Reserved */
/* 0x402cc000 16KB Reserved */
/* 0x402d0000 16KB Reserved */
/* 0x402d4000 16KB Reserved */
#define IMXRT_ENET_BASE 0x402d8000 /* 16KB ENET */
/* 0x402dc000 16KB Reserved */
#define IMXRT_USB_BASE 0x402e0000 /* 16KB USB(USB) */
/* 0x402e4000 16KB Reserved */
/* 0x402e8000 16KB Reserved */
/* 0x402ec000 16KB Reserved */
#define IMXRT_SEMC_BASE 0x402f0000 /* 16KB SEMC */
/* 0x402f4000 16KB Reserved */
/* 0x402f8000 16KB Reserved */
#define IMXRT_DCP_BASE 0x402fc000 /* 16KB DCP */
/* AIPS-4 memory map */
/* 0x40300000 256KB Reserved */
/* 0x40340000 240KB Reserved */
#define IMXRT_AIPS4CNF_BASE 0x4037c000 /* 16KB AIPS-4 Configuration */
#define IMXRT_SPDIF_BASE 0x40380000 /* 16KB SPDIF */
#define IMXRT_SAI1_BASE 0x40384000 /* 16KB SAI1 */
#define IMXRT_SAI2_BASE 0x40388000 /* 16KB SAI2 */
#define IMXRT_SAI3_BASE 0x4038c000 /* 16KB SAI3 */
/* 0x40390000 16KB Reserved */
#define IMXRT_LPSPI1_BASE 0x40394000 /* 16KB LPSPI1 */
#define IMXRT_LPSPI2_BASE 0x40398000 /* 16KB LPSPI2 */
#define IMXRT_LPSPI3_BASE 0x4039c000 /* 16KB LPSPI3 */
#define IMXRT_LPSPI4_BASE 0x403a0000 /* 16KB LPSPI4 */
/* 0x403a4000 16KB Reserved */
/* 0x403a8000 16KB Reserved */
/* 0x403ac000 16KB Reserved */
#define IMXRT_ADCETC_BASE 0x403b0000 /* 16KB ADC_ETC */
#define IMXRT_AOI1_BASE 0x403b4000 /* 16KB AOI1 */
/* 0x403b8000 16KB Reserved */
#define IMXRT_XBAR1_BASE 0x403bc000 /* 16KB XBAR1 */
#define IMXRT_XBAR2_BASE 0x403c0000 /* 16KB XBAR2 */
/* 0x403c4000 16KB Reserved */
#define IMXRT_ENC1_BASE 0x403c8000 /* 16KB ENC1 */
#define IMXRT_ENC2_BASE 0x403cc000 /* 16KB ENC2 */
/* 0x403d0000 16KB Reserved */
/* 0x403d4000 16KB Reserved */
/* 0x403d8000 16KB Reserved */
#define IMXRT_FLEXPWM1_BASE 0x403dc000 /* 16KB FLEXPWM1 */
#define IMXRT_FLEXPWM2_BASE 0x403e0000 /* 16KB FLEXPWM2 */
/* 0x403e4000 16KB Reserved */
/* 0x403e8000 16KB Reserved */
#define IMXRT_BEE_BASE 0x403ec000 /* 16KB BEE */
#define IMXRT_LPI2C1_BASE 0x403f0000 /* 16KB */
#define IMXRT_LPI2C2_BASE 0x403f4000 /* 16KB LPI2C2 */
#define IMXRT_LPI2C3_BASE 0x403f8000 /* 16KB LPI2C3 */
#define IMXRT_LPI2C4_BASE 0x403fc000 /* 16KB LPI2C4 */
/* PPB memory map */
#define IMXRT_TPIU_BASE 0xe0040000 /* 4KB TPIU */
#define IMXRT_ETM_BASE 0xe0041000 /* 4KB ETM */
#define IMXRT_CTI_BASE 0xe0042000 /* 4KB CTI */
#define IMXRT_TSGEN_BASE 0xe0043000 /* 4KB TSGEN */
#define IMXRT_PPBRES_BASE 0xe0044000 /* 4KB PPB RES */
/* 0xe0045000 236KB PPB Reserved */
#define IMXRT_MCM_BASE 0xe0080000 /* 4KB MCM */
/* 0xe0081000 444KB PPB Reserved */
/* 0xe00f0000 52KB PPB Reserved */
#define IMXRT_SYSROM_BASE 0xe00fd000 /* 4KB SYS ROM */
#define IMXRT_PROCROM_BASE 0xe00fe000 /* 4KB Processor ROM */
#define IMXRT_PPBROM_BASE 0xe00ff000 /* 4KB PPB ROM */
#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_MEMORYMAP_H */
arch/arm/src/imxrt/chip/rt102x/imxrt102x_pinmux.h
-914
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File diff suppressed because it is too large Load Diff
arch/arm/src/imxrt/chip/rt102x/imxrt102x_xbar.h
-324
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@@ -1,324 +0,0 @@
/* XBAR Defines for IMXRT102x */
/* XBARA1 Mux inputs (I values) ***************************************************************************************************************************************/
#define IMXRT_XBARA1_IN_LOGIC_LOW IMXRT_XBARA1(XBAR_INPUT, 0) /* LOGIC_LOW output assigned to XBARA1_IN0 input. */
#define IMXRT_XBARA1_IN_LOGIC_HIGH IMXRT_XBARA1(XBAR_INPUT, 1) /* LOGIC_HIGH output assigned to XBARA1_IN1 input. */
/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 2) RESERVED */
/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 3) RESERVED */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO04 IMXRT_XBARA1(XBAR_INPUT, 4) /* IOMUX_XBAR_INOUT04 output assigned to XBARA1_IN4 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO05 IMXRT_XBARA1(XBAR_INPUT, 5) /* IOMUX_XBAR_INOUT05 output assigned to XBARA1_IN5 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO06 IMXRT_XBARA1(XBAR_INPUT, 6) /* IOMUX_XBAR_INOUT06 output assigned to XBARA1_IN6 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO07 IMXRT_XBARA1(XBAR_INPUT, 7) /* IOMUX_XBAR_INOUT07 output assigned to XBARA1_IN7 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO08 IMXRT_XBARA1(XBAR_INPUT, 8) /* IOMUX_XBAR_INOUT08 output assigned to XBARA1_IN8 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO09 IMXRT_XBARA1(XBAR_INPUT, 9) /* IOMUX_XBAR_INOUT09 output assigned to XBARA1_IN9 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO10 IMXRT_XBARA1(XBAR_INPUT, 10) /* IOMUX_XBAR_INOUT10 output assigned to XBARA1_IN10 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO11 IMXRT_XBARA1(XBAR_INPUT, 11) /* IOMUX_XBAR_INOUT11 output assigned to XBARA1_IN11 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO12 IMXRT_XBARA1(XBAR_INPUT, 12) /* IOMUX_XBAR_INOUT12 output assigned to XBARA1_IN12 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO13 IMXRT_XBARA1(XBAR_INPUT, 13) /* IOMUX_XBAR_INOUT13 output assigned to XBARA1_IN13 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO14 IMXRT_XBARA1(XBAR_INPUT, 14) /* IOMUX_XBAR_INOUT14 output assigned to XBARA1_IN14 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO15 IMXRT_XBARA1(XBAR_INPUT, 15) /* IOMUX_XBAR_INOUT15 output assigned to XBARA1_IN15 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO16 IMXRT_XBARA1(XBAR_INPUT, 16) /* IOMUX_XBAR_INOUT16 output assigned to XBARA1_IN16 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO17 IMXRT_XBARA1(XBAR_INPUT, 17) /* IOMUX_XBAR_INOUT17 output assigned to XBARA1_IN17 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO18 IMXRT_XBARA1(XBAR_INPUT, 18) /* IOMUX_XBAR_INOUT18 output assigned to XBARA1_IN18 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO19 IMXRT_XBARA1(XBAR_INPUT, 19) /* IOMUX_XBAR_INOUT19 output assigned to XBARA1_IN19 input. */
/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 20) RESERVED */
/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 21) RESERVED */
/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 22) RESERVED */
/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 23) RESERVED */
/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 24) RESERVED */
/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 25) RESERVED */
#define IMXRT_XBARA1_IN_ACMP1_OUT IMXRT_XBARA1(XBAR_INPUT, 26) /* ACMP1_OUT output assigned to XBARA1_IN26 input. */
#define IMXRT_XBARA1_IN_ACMP2_OUT IMXRT_XBARA1(XBAR_INPUT, 27) /* ACMP2_OUT output assigned to XBARA1_IN27 input. */
#define IMXRT_XBARA1_IN_ACMP3_OUT IMXRT_XBARA1(XBAR_INPUT, 28) /* ACMP3_OUT output assigned to XBARA1_IN28 input. */
#define IMXRT_XBARA1_IN_ACMP4_OUT IMXRT_XBARA1(XBAR_INPUT, 29) /* ACMP4_OUT output assigned to XBARA1_IN29 input. */
/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 30) RESERVED */
/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 31) RESERVED */
#define IMXRT_XBARA1_IN_QTIMER1_TMR0_OUT IMXRT_XBARA1(XBAR_INPUT, 32) /* QTIMER3_TMR0_OUTPUT output assigned to XBARA1_IN32 input. */
#define IMXRT_XBARA1_IN_QTIMER1_TMR1_OUT IMXRT_XBARA1(XBAR_INPUT, 33) /* QTIMER3_TMR1_OUTPUT output assigned to XBARA1_IN33 input. */
#define IMXRT_XBARA1_IN_QTIMER1_TMR2_OUT IMXRT_XBARA1(XBAR_INPUT, 34) /* QTIMER3_TMR2_OUTPUT output assigned to XBARA1_IN34 input. */
#define IMXRT_XBARA1_IN_QTIMER1_TMR3_OUT IMXRT_XBARA1(XBAR_INPUT, 35) /* QTIMER3_TMR3_OUTPUT output assigned to XBARA1_IN35 input. */
#define IMXRT_XBARA1_IN_QTIMER2_TMR0_OUT IMXRT_XBARA1(XBAR_INPUT, 36) /* QTIMER4_TMR0_OUTPUT output assigned to XBARA1_IN36 input. */
#define IMXRT_XBARA1_IN_QTIMER2_TMR1_OUT IMXRT_XBARA1(XBAR_INPUT, 37) /* QTIMER4_TMR1_OUTPUT output assigned to XBARA1_IN37 input. */
#define IMXRT_XBARA1_IN_QTIMER2_TMR2_OUT IMXRT_XBARA1(XBAR_INPUT, 38) /* QTIMER4_TMR2_OUTPUT output assigned to XBARA1_IN38 input. */
#define IMXRT_XBARA1_IN_QTIMER2_TMR3_OUT IMXRT_XBARA1(XBAR_INPUT, 39) /* QTIMER4_TMR3_OUTPUT output assigned to XBARA1_IN39 input. */
#define IMXRT_XBARA1_IN_FLEXPWM1_PWM1_OUT_TRIG0 IMXRT_XBARA1(XBAR_INPUT, 40) /* FLEXPWM1_PWM1_OUT_TRIG0 output OR assigned to XBARA1_IN40 input. */
#define IMXRT_XBARA1_IN_FLEXPWM1_PWM1_OUT_TRIG1 IMXRT_XBARA1(XBAR_INPUT, 40) /* FLEXPWM1_PWM1_OUT_TRIG1 output OR assigned to XBARA1_IN40 input. */
#define IMXRT_XBARA1_IN_FLEXPWM1_PWM2_OUT_TRIG0 IMXRT_XBARA1(XBAR_INPUT, 41) /* FLEXPWM1_PWM2_OUT_TRIG0 output OR assigned to XBARA1_IN41 input. */
#define IMXRT_XBARA1_IN_FLEXPWM1_PWM2_OUT_TRIG1 IMXRT_XBARA1(XBAR_INPUT, 41) /* FLEXPWM1_PWM2_OUT_TRIG1 output OR assigned to XBARA1_IN41 input. */
#define IMXRT_XBARA1_IN_FLEXPWM1_PWM3_OUT_TRIG0 IMXRT_XBARA1(XBAR_INPUT, 42) /* FLEXPWM1_PWM3_OUT_TRIG0 output OR assigned to XBARA1_IN42 input. */
#define IMXRT_XBARA1_IN_FLEXPWM1_PWM3_OUT_TRIG1 IMXRT_XBARA1(XBAR_INPUT, 42) /* FLEXPWM1_PWM3_OUT_TRIG1 output OR assigned to XBARA1_IN42 input. */
#define IMXRT_XBARA1_IN_FLEXPWM1_PWM4_OUT_TRIG0 IMXRT_XBARA1(XBAR_INPUT, 43) /* FLEXPWM1_PWM4_OUT_TRIG0 output OR assigned to XBARA1_IN43 input. */
#define IMXRT_XBARA1_IN_FLEXPWM1_PWM4_OUT_TRIG1 IMXRT_XBARA1(XBAR_INPUT, 43) /* FLEXPWM1_PWM4_OUT_TRIG1 output OR assigned to XBARA1_IN43 input. */
#define IMXRT_XBARA1_IN_FLEXPWM2_PWM1_OUT_TRIG0 IMXRT_XBARA1(XBAR_INPUT, 44) /* FLEXPWM2_PWM1_OUT_TRIG0 output OR assigned to XBARA1_IN44 input. */
#define IMXRT_XBARA1_IN_FLEXPWM2_PWM1_OUT_TRIG1 IMXRT_XBARA1(XBAR_INPUT, 44) /* FLEXPWM2_PWM1_OUT_TRIG1 output OR assigned to XBARA1_IN44 input. */
#define IMXRT_XBARA1_IN_FLEXPWM2_PWM2_OUT_TRIG0 IMXRT_XBARA1(XBAR_INPUT, 45) /* FLEXPWM2_PWM2_OUT_TRIG0 output OR assigned to XBARA1_IN45 input. */
#define IMXRT_XBARA1_IN_FLEXPWM2_PWM2_OUT_TRIG1 IMXRT_XBARA1(XBAR_INPUT, 45) /* FLEXPWM2_PWM2_OUT_TRIG1 output OR assigned to XBARA1_IN45 input. */
#define IMXRT_XBARA1_IN_FLEXPWM2_PWM3_OUT_TRIG0 IMXRT_XBARA1(XBAR_INPUT, 46) /* FLEXPWM2_PWM3_OUT_TRIG0 output OR assigned to XBARA1_IN46 input. */
#define IMXRT_XBARA1_IN_FLEXPWM2_PWM3_OUT_TRIG1 IMXRT_XBARA1(XBAR_INPUT, 46) /* FLEXPWM2_PWM3_OUT_TRIG1 output OR assigned to XBARA1_IN46 input. */
#define IMXRT_XBARA1_IN_FLEXPWM2_PWM4_OUT_TRIG0 IMXRT_XBARA1(XBAR_INPUT, 47) /* FLEXPWM2_PWM4_OUT_TRIG0 output OR assigned to XBARA1_IN47 input. */
#define IMXRT_XBARA1_IN_FLEXPWM2_PWM4_OUT_TRIG1 IMXRT_XBARA1(XBAR_INPUT, 47) /* FLEXPWM2_PWM4_OUT_TRIG1 output OR assigned to XBARA1_IN47 input. */
/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 48) RESERVED */
/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 49) RESERVED */
/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 50) RESERVED */
/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 51) RESERVED */
/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 52) RESERVED */
/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 53) RESERVED */
/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 54) RESERVED */
/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 55) RESERVED */
#define IMXRT_XBARA1_IN_PIT_TRIGGER0 IMXRT_XBARA1(XBAR_INPUT, 56) /* PIT_TRIGGER0 output assigned to XBARA1_IN56 input. */
#define IMXRT_XBARA1_IN_PIT_TRIGGER1 IMXRT_XBARA1(XBAR_INPUT, 57) /* PIT_TRIGGER1 output assigned to XBARA1_IN57 input. */
#define IMXRT_XBARA1_IN_PIT_TRIGGER2 IMXRT_XBARA1(XBAR_INPUT, 58) /* PIT_TRIGGER2 output assigned to XBARA1_IN58 input. */
#define IMXRT_XBARA1_IN_PIT_TRIGGER3 IMXRT_XBARA1(XBAR_INPUT, 59) /* PIT_TRIGGER3 output assigned to XBARA1_IN59 input. */
#define IMXRT_XBARA1_IN_ENC1_POS_MATCH IMXRT_XBARA1(XBAR_INPUT, 60) /* ENC1_POS_MATCH output assigned to XBARA1_IN60 input. */
#define IMXRT_XBARA1_IN_ENC2_POS_MATCH IMXRT_XBARA1(XBAR_INPUT, 61) /* ENC2_POS_MATCH output assigned to XBARA1_IN61 input. */
/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 62) RESERVED */
/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 63) RESERVED */
#define IMXRT_XBARA1_IN_DMA_DONE0 IMXRT_XBARA1(XBAR_INPUT, 64) /* DMA_DONE0 output assigned to XBARA1_IN64 input. */
#define IMXRT_XBARA1_IN_DMA_DONE1 IMXRT_XBARA1(XBAR_INPUT, 65) /* DMA_DONE1 output assigned to XBARA1_IN65 input. */
#define IMXRT_XBARA1_IN_DMA_DONE2 IMXRT_XBARA1(XBAR_INPUT, 66) /* DMA_DONE2 output assigned to XBARA1_IN66 input. */
#define IMXRT_XBARA1_IN_DMA_DONE3 IMXRT_XBARA1(XBAR_INPUT, 67) /* DMA_DONE3 output assigned to XBARA1_IN67 input. */
#define IMXRT_XBARA1_IN_DMA_DONE4 IMXRT_XBARA1(XBAR_INPUT, 68) /* DMA_DONE4 output assigned to XBARA1_IN68 input. */
#define IMXRT_XBARA1_IN_DMA_DONE5 IMXRT_XBARA1(XBAR_INPUT, 69) /* DMA_DONE5 output assigned to XBARA1_IN69 input. */
#define IMXRT_XBARA1_IN_DMA_DONE6 IMXRT_XBARA1(XBAR_INPUT, 70) /* DMA_DONE6 output assigned to XBARA1_IN70 input. */
#define IMXRT_XBARA1_IN_DMA_DONE7 IMXRT_XBARA1(XBAR_INPUT, 71) /* DMA_DONE7 output assigned to XBARA1_IN71 input. */
#define IMXRT_XBARA1_IN_AOI1_OUT0 IMXRT_XBARA1(XBAR_INPUT, 72) /* AOI1_OUT0 output assigned to XBARA1_IN72 input. */
#define IMXRT_XBARA1_IN_AOI1_OUT1 IMXRT_XBARA1(XBAR_INPUT, 73) /* AOI1_OUT1 output assigned to XBARA1_IN73 input. */
#define IMXRT_XBARA1_IN_AOI1_OUT2 IMXRT_XBARA1(XBAR_INPUT, 74) /* AOI1_OUT2 output assigned to XBARA1_IN74 input. */
#define IMXRT_XBARA1_IN_AOI1_OUT3 IMXRT_XBARA1(XBAR_INPUT, 75) /* AOI1_OUT3 output assigned to XBARA1_IN75 input. */
/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 76) RESERVED */
/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 77) RESERVED */
/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 78) RESERVED */
/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 79) RESERVED */
#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO0 IMXRT_XBARA1(XBAR_INPUT, 80) /* ADC_ETC_XBAR0_COCO0 output assigned to XBARA1_IN80 input. */
#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO1 IMXRT_XBARA1(XBAR_INPUT, 81) /* ADC_ETC_XBAR0_COCO1 output assigned to XBARA1_IN81 input. */
#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO2 IMXRT_XBARA1(XBAR_INPUT, 82) /* ADC_ETC_XBAR0_COCO2 output assigned to XBARA1_IN82 input. */
#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO3 IMXRT_XBARA1(XBAR_INPUT, 83) /* ADC_ETC_XBAR0_COCO3 output assigned to XBARA1_IN83 input. */
#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO0 IMXRT_XBARA1(XBAR_INPUT, 84) /* ADC_ETC_XBAR1_COCO0 output assigned to XBARA1_IN84 input. */
#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO1 IMXRT_XBARA1(XBAR_INPUT, 85) /* ADC_ETC_XBAR1_COCO1 output assigned to XBARA1_IN85 input. */
#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO2 IMXRT_XBARA1(XBAR_INPUT, 86) /* ADC_ETC_XBAR1_COCO2 output assigned to XBARA1_IN86 input. */
#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO3 IMXRT_XBARA1(XBAR_INPUT, 87) /* ADC_ETC_XBAR1_COCO3 output assigned to XBARA1_IN87 input. */
/* XBARA1 Mux Output (M Muxes) ***************************************************************************************************************/
#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ30_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 0) /* XBARA1_OUT0 output assigned to DMA_CH_MUX_REQ30 */
#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ31_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 1) /* XBARA1_OUT1 output assigned to DMA_CH_MUX_REQ31 */
#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ94_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 2) /* XBARA1_OUT2 output assigned to DMA_CH_MUX_REQ94 */
#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ95_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 3) /* XBARA1_OUT3 output assigned to DMA_CH_MUX_REQ95 */
#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO04_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 4) /* XBARA1_OUT4 output assigned to IOMUX_XBAR_INOUT04 */
#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO05_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 5) /* XBARA1_OUT5 output assigned to IOMUX_XBAR_INOUT05 */
#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO06_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 6) /* XBARA1_OUT6 output assigned to IOMUX_XBAR_INOUT06 */
#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO07_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 7) /* XBARA1_OUT7 output assigned to IOMUX_XBAR_INOUT07 */
#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO08_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 8) /* XBARA1_OUT8 output assigned to IOMUX_XBAR_INOUT08 */
#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO09_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 9) /* XBARA1_OUT9 output assigned to IOMUX_XBAR_INOUT09 */
#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO10_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 10) /* XBARA1_OUT10 output assigned to IOMUX_XBAR_INOUT10 */
#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO11_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 11) /* XBARA1_OUT11 output assigned to IOMUX_XBAR_INOUT11 */
#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO12_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 12) /* XBARA1_OUT12 output assigned to IOMUX_XBAR_INOUT12 */
#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO13_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 13) /* XBARA1_OUT13 output assigned to IOMUX_XBAR_INOUT13 */
#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO14_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 14) /* XBARA1_OUT14 output assigned to IOMUX_XBAR_INOUT14 */
#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO15_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 15) /* XBARA1_OUT15 output assigned to IOMUX_XBAR_INOUT15 */
#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO16_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 16) /* XBARA1_OUT16 output assigned to IOMUX_XBAR_INOUT16 */
#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO17_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 17) /* XBARA1_OUT17 output assigned to IOMUX_XBAR_INOUT17 */
#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO18_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 18) /* XBARA1_OUT18 output assigned to IOMUX_XBAR_INOUT18 */
#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO19_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 19) /* XBARA1_OUT19 output assigned to IOMUX_XBAR_INOUT19 */
#define IMXRT_XBARA1_OUT_ACMP1_SAMPLE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 20) /* XBARA1_OUT20 output assigned to ACMP1_SAMPLE */
#define IMXRT_XBARA1_OUT_ACMP2_SAMPLE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 21) /* XBARA1_OUT21 output assigned to ACMP2_SAMPLE */
#define IMXRT_XBARA1_OUT_ACMP3_SAMPLE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 22) /* XBARA1_OUT22 output assigned to ACMP3_SAMPLE */
#define IMXRT_XBARA1_OUT_ACMP4_SAMPLE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 23) /* XBARA1_OUT23 output assigned to ACMP4_SAMPLE */
/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 24) RESERVED */
/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 25) RESERVED */
#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 26) /* XBARA1_OUT26 output assigned to FLEXPWM1_EXTA0 */
#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 27) /* XBARA1_OUT27 output assigned to FLEXPWM1_EXTA1 */
#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 28) /* XBARA1_OUT28 output assigned to FLEXPWM1_EXTA2 */
#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 29) /* XBARA1_OUT29 output assigned to FLEXPWM1_EXTA3 */
#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 30) /* XBARA1_OUT30 output assigned to FLEXPWM1_EXT_SYNC0 */
#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 31) /* XBARA1_OUT31 output assigned to FLEXPWM1_EXT_SYNC1 */
#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 32) /* XBARA1_OUT32 output assigned to FLEXPWM1_EXT_SYNC2 */
#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 33) /* XBARA1_OUT33 output assigned to FLEXPWM1_EXT_SYNC3 */
#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_CLK_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 34) /* XBARA1_OUT34 output assigned to FLEXPWM1_EXT_CLK */
#define IMXRT_XBARA1_OUT_FLEXPWM1_FAULT0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 35) /* XBARA1_OUT35 output assigned to FLEXPWM1_FAULT0 */
#define IMXRT_XBARA1_OUT_FLEXPWM1_FAULT1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 36) /* XBARA1_OUT36 output assigned to FLEXPWM1_FAULT1 */
#define IMXRT_XBARA1_OUT_FLEXPWM12_FAULT2_SEL_OFFSET IMXXRT_XBARA1(XBAR_OUTPUT,37) /* XBARA1_OUT37 output assigned to FLEXPWM1_2_FAULT2 */
#define IMXRT_XBARA1_OUT_FLEXPWM12_FAULT3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 38) /* XBARA1_OUT38 output assigned to FLEXPWM1_2_FAULT3 */
#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_FORCE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 39) /* XBARA1_OUT39 output assigned to FLEXPWM1_EXT_FORCE */
#define IMXRT_XBARA1_OUT_FLEXPWM2_EXTA0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 40) /* XBARA1_OUT40 output assigned to FLEXPWM2_EXTA0 */
#define IMXRT_XBARA1_OUT_FLEXPWM2_EXTA1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 41) /* XBARA1_OUT41 output assigned to FLEXPWM2_EXTA1 */
#define IMXRT_XBARA1_OUT_FLEXPWM2_EXTA2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 42) /* XBARA1_OUT42 output assigned to FLEXPWM2_EXTA2 */
#define IMXRT_XBARA1_OUT_FLEXPWM2_EXTA3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 43) /* XBARA1_OUT43 output assigned to FLEXPWM2_EXTA3 */
#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 44) /* XBARA1_OUT44 output assigned to FLEXPWM2_EXT_SYNC0 */
#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 45) /* XBARA1_OUT45 output assigned to FLEXPWM2_EXT_SYNC1 */
#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 46) /* XBARA1_OUT46 output assigned to FLEXPWM2_EXT_SYNC2 */
#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 47) /* XBARA1_OUT47 output assigned to FLEXPWM2_EXT_SYNC3 */
#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_CLK_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 48) /* XBARA1_OUT48 output assigned to FLEXPWM2_EXT_CLK */
#define IMXRT_XBARA1_OUT_FLEXPWM2_FAULT0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 49) /* XBARA1_OUT49 output assigned to FLEXPWM2_FAULT0 */
#define IMXRT_XBARA1_OUT_FLEXPWM2_FAULT1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 50) /* XBARA1_OUT50 output assigned to FLEXPWM2_FAULT1 */
#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_FORCE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 51) /* XBARA1_OUT51 output assigned to FLEXPWM2_EXT_FORCE */
/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 52) RESERVED */
/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 53) RESERVED */
/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 54) RESERVED */
/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 55) RESERVED */
/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 56) RESERVED */
/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 57) RESERVED */
/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 58) RESERVED */
/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 59) RESERVED */
/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 60) RESERVED */
/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 61) RESERVED */
/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 62) RESERVED */
/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 63) RESERVED */
/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 64) RESERVED */
/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 65) RESERVED */
#define IMXRT_XBARA1_OUT_ENC1_PHASE_AIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 66) /* XBARA1_OUT66 output assigned to ENC1_PHASE_A_IN */
#define IMXRT_XBARA1_OUT_ENC1_PHASE_BIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 67) /* XBARA1_OUT67 output assigned to ENC1_PHASE_B_IN */
#define IMXRT_XBARA1_OUT_ENC1_INDEX_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 68) /* XBARA1_OUT68 output assigned to ENC1_INDEX */
#define IMXRT_XBARA1_OUT_ENC1_HOME_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 69) /* XBARA1_OUT69 output assigned to ENC1_HOME */
#define IMXRT_XBARA1_OUT_ENC1_TRIGGER_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 70) /* XBARA1_OUT70 output assigned to ENC1_TRIGGER */
#define IMXRT_XBARA1_OUT_ENC2_PHASE_AIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 71) /* XBARA1_OUT71 output assigned to ENC2_PHASE_A_IN */
#define IMXRT_XBARA1_OUT_ENC2_PHASE_BIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 72) /* XBARA1_OUT72 output assigned to ENC2_PHASE_B_IN */
#define IMXRT_XBARA1_OUT_ENC2_INDEX_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 73) /* XBARA1_OUT73 output assigned to ENC2_INDEX */
#define IMXRT_XBARA1_OUT_ENC2_HOME_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 74) /* XBARA1_OUT74 output assigned to ENC2_HOME */
#define IMXRT_XBARA1_OUT_ENC2_TRIGGER_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 75) /* XBARA1_OUT75 output assigned to ENC2_TRIGGER */
/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 76) RESERVED */
/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 77) RESERVED */
/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 78) RESERVED */
/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 79) RESERVED */
/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 80) RESERVED */
/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 81) RESERVED */
/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 82) RESERVED */
/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 83) RESERVED */
/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 84) RESERVED */
/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 85) RESERVED */
#define IMXRT_XBARA1_OUT_QTIMER1_TMR0_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 86) /* XBARA1_OUT86 output assigned to QTIMER1_TMR0_IN_ */
#define IMXRT_XBARA1_OUT_QTIMER1_TMR1_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 87) /* XBARA1_OUT87 output assigned to QTIMER1_TMR1_IN_ */
#define IMXRT_XBARA1_OUT_QTIMER1_TMR2_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 88) /* XBARA1_OUT88 output assigned to QTIMER1_TMR2_IN_ */
#define IMXRT_XBARA1_OUT_QTIMER1_TMR3_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 89) /* XBARA1_OUT89 output assigned to QTIMER1_TMR3_IN_ */
#define IMXRT_XBARA1_OUT_QTIMER2_TMR0_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 90) /* XBARA1_OUT90 output assigned to QTIMER2_TMR0_IN_ */
#define IMXRT_XBARA1_OUT_QTIMER2_TMR1_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 91) /* XBARA1_OUT91 output assigned to QTIMER2_TMR1_IN_ */
#define IMXRT_XBARA1_OUT_QTIMER2_TMR2_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 92) /* XBARA1_OUT92 output assigned to QTIMER2_TMR2_IN_ */
#define IMXRT_XBARA1_OUT_QTIMER2_TMR3_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 93) /* XBARA1_OUT93 output assigned to QTIMER2_TMR3_IN_ */
#define IMXRT_XBARA1_OUT_QTIMER3_TMR0_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 94) /* XBARA1_OUT94 output assigned to QTIMER3_TMR0_IN_ */
/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 95) RESERVED */
/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 96) RESERVED */
/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 97) RESERVED */
/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 98) RESERVED */
/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 99) RESERVED */
/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 100) RESERVED */
/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 101) RESERVED */
#define IMXRT_XBARA1_OUT_EWM_EWM_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 102) /* XBARA1_OUT102 output assigned to EWM_EWM_IN */
#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 103) /* XBARA1_OUT103 output assigned to ADC_ETC_XBAR0_TRIG0 */
#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 104) /* XBARA1_OUT104 output assigned to ADC_ETC_XBAR0_TRIG1 */
#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 105) /* XBARA1_OUT105 output assigned to ADC_ETC_XBAR0_TRIG2 */
#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 106) /* XBARA1_OUT106 output assigned to ADC_ETC_XBAR0_TRIG3 */
#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG10_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 107) /* XBARA1_OUT107 output assigned to ADC_ETC_XBAR1_TRIG10 */
#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG11_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 108) /* XBARA1_OUT108 output assigned to ADC_ETC_XBAR1_TRIG11 */
#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG12_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 109) /* XBARA1_OUT109 output assigned to ADC_ETC_XBAR1_TRIG12 */
#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG13_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 110) /* XBARA1_OUT110 output assigned to ADC_ETC_XBAR1_TRIG13 */
#define IMXRT_XBARA1_OUT_LPI2C1_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 111) /* XBARA1_OUT111 output assigned to LPI2C1_TRG_IN */
#define IMXRT_XBARA1_OUT_LPI2C2_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 112) /* XBARA1_OUT112 output assigned to LPI2C2_TRG_IN */
#define IMXRT_XBARA1_OUT_LPI2C3_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 113) /* XBARA1_OUT113 output assigned to LPI2C3_TRG_IN */
#define IMXRT_XBARA1_OUT_LPI2C4_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 114) /* XBARA1_OUT114 output assigned to LPI2C4_TRG_IN */
#define IMXRT_XBARA1_OUT_LPSPI1_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 115) /* XBARA1_OUT115 output assigned to LPSPI1_TRG_IN */
#define IMXRT_XBARA1_OUT_LPSPI2_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 116) /* XBARA1_OUT116 output assigned to LPSPI2_TRG_IN */
#define IMXRT_XBARA1_OUT_LPSPI3_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 117) /* XBARA1_OUT117 output assigned to LPSPI3_TRG_IN */
#define IMXRT_XBARA1_OUT_LPSPI4_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 118) /* XBARA1_OUT118 output assigned to LPSPI4_TRG_IN */
#define IMXRT_XBARA1_OUT_LPUART1_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 119) /* XBARA1_OUT119 output assigned to LPUART1_TRG_IN */
#define IMXRT_XBARA1_OUT_LPUART2_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 120) /* XBARA1_OUT120 output assigned to LPUART2_TRG_IN */
#define IMXRT_XBARA1_OUT_LPUART3_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 121) /* XBARA1_OUT121 output assigned to LPUART3_TRG_IN */
#define IMXRT_XBARA1_OUT_LPUART4_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 122) /* XBARA1_OUT122 output assigned to LPUART4_TRG_IN */
#define IMXRT_XBARA1_OUT_LPUART5_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 123) /* XBARA1_OUT123 output assigned to LPUART5_TRG_IN */
#define IMXRT_XBARA1_OUT_LPUART6_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 124) /* XBARA1_OUT124 output assigned to LPUART6_TRG_IN */
#define IMXRT_XBARA1_OUT_LPUART7_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 125) /* XBARA1_OUT125 output assigned to LPUART7_TRG_IN */
#define IMXRT_XBARA1_OUT_LPUART8_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 126) /* XBARA1_OUT126 output assigned to LPUART8_TRG_IN */
#define IMXRT_XBARA1_OUT_FLEXIO1_TRIGGER_IN0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 127) /* XBARA1_OUT127 output assigned to FLEXIO1_TRIGGER_IN0 */
#define IMXRT_XBARA1_OUT_FLEXIO1_TRIGGER_IN1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 128) /* XBARA1_OUT128 output assigned to FLEXIO1_TRIGGER_IN1 */
/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 129) RESERVED */
/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 130) RESERVED */
/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 131) RESERVED */
/* XBARB2 Mux inputs (I values) *******************************************************************************************************************/
#define IMXRT_XBARB2_IN_LOGIC_LOW IMXRT_XBARB2(XBAR_INPUT, 0) /* LOGIC_LOW output assigned to XBARB2_IN0 input. */
#define IMXRT_XBARB2_IN_LOGIC_HIGH IMXRT_XBARB2(XBAR_INPUT, 1) /* LOGIC_HIGH output assigned to XBARB2_IN1 input. */
/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 2) RESERVED */
/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 3) RESERVED */
/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 4) RESERVED */
/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 5) RESERVED */
#define IMXRT_XBARB2_IN_ACMP1_OUT IMXRT_XBARB2(XBAR_INPUT, 6) /* ACMP1_OUT output assigned to XBARB2_IN6 input. */
#define IMXRT_XBARB2_IN_ACMP2_OUT IMXRT_XBARB2(XBAR_INPUT, 7) /* ACMP2_OUT output assigned to XBARB2_IN7 input. */
#define IMXRT_XBARB2_IN_ACMP3_OUT IMXRT_XBARB2(XBAR_INPUT, 8) /* ACMP3_OUT output assigned to XBARB2_IN8 input. */
#define IMXRT_XBARB2_IN_ACMP4_OUT IMXRT_XBARB2(XBAR_INPUT, 9) /* ACMP4_OUT output assigned to XBARB2_IN9 input. */
/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 10) RESERVED */
/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 11) RESERVED */
#define IMXRT_XBARB2_IN_QTIMER1_TMR0_OUT IMXRT_XBARB2(XBAR_INPUT, 12) /* QTIMER3_TMR0_OUTPUT output assigned to XBARB2_IN12 input. */
#define IMXRT_XBARB2_IN_QTIMER1_TMR1_OUT IMXRT_XBARB2(XBAR_INPUT, 13) /* QTIMER3_TMR1_OUTPUT output assigned to XBARB2_IN13 input. */
#define IMXRT_XBARB2_IN_QTIMER1_TMR2_OUT IMXRT_XBARB2(XBAR_INPUT, 14) /* QTIMER3_TMR2_OUTPUT output assigned to XBARB2_IN14 input. */
#define IMXRT_XBARB2_IN_QTIMER1_TMR3_OUT IMXRT_XBARB2(XBAR_INPUT, 15) /* QTIMER3_TMR3_OUTPUT output assigned to XBARB2_IN15 input. */
#define IMXRT_XBARB2_IN_QTIMER2_TMR0_OUT IMXRT_XBARB2(XBAR_INPUT, 16) /* QTIMER4_TMR0_OUTPUT output assigned to XBARB2_IN16 input. */
#define IMXRT_XBARB2_IN_QTIMER2_TMR1_OUT IMXRT_XBARB2(XBAR_INPUT, 17) /* QTIMER4_TMR1_OUTPUT output assigned to XBARB2_IN17 input. */
#define IMXRT_XBARB2_IN_QTIMER2_TMR2_OUT IMXRT_XBARB2(XBAR_INPUT, 18) /* QTIMER4_TMR2_OUTPUT output assigned to XBARB2_IN18 input. */
#define IMXRT_XBARB2_IN_QTIMER2_TMR3_OUT IMXRT_XBARB2(XBAR_INPUT, 19) /* QTIMER4_TMR3_OUTPUT output assigned to XBARB2_IN19 input. */
#define IMXRT_XBARB2_IN_FLEXPWM1_PWM1_OUT_TRIG0 IMXRT_XBARB2(XBAR_INPUT, 20) /* FLEXPWM1_PWM1_OUT_TRIG0 output OR assigned to XBARB2_IN20 input. */
#define IMXRT_XBARB2_IN_FLEXPWM1_PWM1_OUT_TRIG1 IMXRT_XBARB2(XBAR_INPUT, 20) /* FLEXPWM1_PWM1_OUT_TRIG1 output OR assigned to XBARB2_IN20 input. */
#define IMXRT_XBARB2_IN_FLEXPWM1_PWM2_OUT_TRIG0 IMXRT_XBARB2(XBAR_INPUT, 21) /* FLEXPWM1_PWM2_OUT_TRIG0 output OR assigned to XBARB2_IN21 input. */
#define IMXRT_XBARB2_IN_FLEXPWM1_PWM2_OUT_TRIG1 IMXRT_XBARB2(XBAR_INPUT, 21) /* FLEXPWM1_PWM2_OUT_TRIG1 output OR assigned to XBARB2_IN21 input. */
#define IMXRT_XBARB2_IN_FLEXPWM1_PWM3_OUT_TRIG0 IMXRT_XBARB2(XBAR_INPUT, 22) /* FLEXPWM1_PWM3_OUT_TRIG0 output OR assigned to XBARB2_IN22 input. */
#define IMXRT_XBARB2_IN_FLEXPWM1_PWM3_OUT_TRIG1 IMXRT_XBARB2(XBAR_INPUT, 22) /* FLEXPWM1_PWM3_OUT_TRIG1 output OR assigned to XBARB2_IN22 input. */
#define IMXRT_XBARB2_IN_FLEXPWM1_PWM4_OUT_TRIG0 IMXRT_XBARB2(XBAR_INPUT, 23) /* FLEXPWM1_PWM4_OUT_TRIG0 output OR assigned to XBARB2_IN23 input. */
#define IMXRT_XBARB2_IN_FLEXPWM1_PWM4_OUT_TRIG1 IMXRT_XBARB2(XBAR_INPUT, 23) /* FLEXPWM1_PWM4_OUT_TRIG1 output OR assigned to XBARB2_IN23 input. */
#define IMXRT_XBARB2_IN_FLEXPWM2_PWM1_OUT_TRIG0 IMXRT_XBARB2(XBAR_INPUT, 24) /* FLEXPWM2_PWM1_OUT_TRIG0 output OR assigned to XBARB2_IN24 input. */
#define IMXRT_XBARB2_IN_FLEXPWM2_PWM1_OUT_TRIG1 IMXRT_XBARB2(XBAR_INPUT, 24) /* FLEXPWM2_PWM1_OUT_TRIG1 output OR assigned to XBARB2_IN24 input. */
#define IMXRT_XBARB2_IN_FLEXPWM2_PWM2_OUT_TRIG0 IMXRT_XBARB2(XBAR_INPUT, 25) /* FLEXPWM2_PWM2_OUT_TRIG0 output OR assigned to XBARB2_IN25 input. */
#define IMXRT_XBARB2_IN_FLEXPWM2_PWM2_OUT_TRIG1 IMXRT_XBARB2(XBAR_INPUT, 25) /* FLEXPWM2_PWM2_OUT_TRIG1 output OR assigned to XBARB2_IN25 input. */
#define IMXRT_XBARB2_IN_FLEXPWM2_PWM3_OUT_TRIG0 IMXRT_XBARB2(XBAR_INPUT, 26) /* FLEXPWM2_PWM3_OUT_TRIG0 output OR assigned to XBARB2_IN26 input. */
#define IMXRT_XBARB2_IN_FLEXPWM2_PWM3_OUT_TRIG1 IMXRT_XBARB2(XBAR_INPUT, 26) /* FLEXPWM2_PWM3_OUT_TRIG1 output OR assigned to XBARB2_IN26 input. */
#define IMXRT_XBARB2_IN_FLEXPWM2_PWM4_OUT_TRIG0 IMXRT_XBARB2(XBAR_INPUT, 27) /* FLEXPWM2_PWM4_OUT_TRIG0 output OR assigned to XBARB2_IN27 input. */
#define IMXRT_XBARB2_IN_FLEXPWM2_PWM4_OUT_TRIG1 IMXRT_XBARB2(XBAR_INPUT, 27) /* FLEXPWM2_PWM4_OUT_TRIG1 output OR assigned to XBARB2_IN27 input. */
/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 28) RESERVED */
/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 29) RESERVED */
/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 30) RESERVED */
/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 31) RESERVED */
/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 32) RESERVED */
/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 33) RESERVED */
/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 34) RESERVED */
/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 35) RESERVED */
#define IMXRT_XBARB2_IN_PIT_TRIGGER0 IMXRT_XBARB2(XBAR_INPUT, 36) /* PIT_TRIGGER0 output assigned to XBARB2_IN36 input. */
#define IMXRT_XBARB2_IN_PIT_TRIGGER1 IMXRT_XBARB2(XBAR_INPUT, 37) /* PIT_TRIGGER1 output assigned to XBARB2_IN37 input. */
#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO0 IMXRT_XBARB2(XBAR_INPUT, 38) /* ADC_ETC_XBAR0_COCO0 output assigned to XBARB2_IN38 input. */
#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO1 IMXRT_XBARB2(XBAR_INPUT, 39) /* ADC_ETC_XBAR0_COCO1 output assigned to XBARB2_IN39 input. */
#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO2 IMXRT_XBARB2(XBAR_INPUT, 40) /* ADC_ETC_XBAR0_COCO2 output assigned to XBARB2_IN40 input. */
#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO3 IMXRT_XBARB2(XBAR_INPUT, 41) /* ADC_ETC_XBAR0_COCO3 output assigned to XBARB2_IN41 input. */
#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO0 IMXRT_XBARB2(XBAR_INPUT, 42) /* ADC_ETC_XBAR1_COCO0 output assigned to XBARB2_IN42 input. */
#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO1 IMXRT_XBARB2(XBAR_INPUT, 43) /* ADC_ETC_XBAR1_COCO1 output assigned to XBARB2_IN43 input. */
#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO2 IMXRT_XBARB2(XBAR_INPUT, 44) /* ADC_ETC_XBAR1_COCO2 output assigned to XBARB2_IN44 input. */
#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO3 IMXRT_XBARB2(XBAR_INPUT, 45) /* ADC_ETC_XBAR1_COCO3 output assigned to XBARB2_IN45 input. */
#define IMXRT_XBARB2_IN_ENC1_POS_MATCH IMXRT_XBARB2(XBAR_INPUT, 46) /* ENC1_POS_MATCH output assigned to XBARB2_IN46 input. */
#define IMXRT_XBARB2_IN_ENC2_POS_MATCH IMXRT_XBARB2(XBAR_INPUT, 47) /* ENC2_POS_MATCH output assigned to XBARB2_IN47 input. */
/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 48) RESERVED */
/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 49) RESERVED */
#define IMXRT_XBARB2_IN_DMA_DONE0 IMXRT_XBARB2(XBAR_INPUT, 50) /* DMA_DONE0 output assigned to XBARB2_IN50 input. */
#define IMXRT_XBARB2_IN_DMA_DONE1 IMXRT_XBARB2(XBAR_INPUT, 51) /* DMA_DONE1 output assigned to XBARB2_IN51 input. */
#define IMXRT_XBARB2_IN_DMA_DONE2 IMXRT_XBARB2(XBAR_INPUT, 52) /* DMA_DONE2 output assigned to XBARB2_IN52 input. */
#define IMXRT_XBARB2_IN_DMA_DONE3 IMXRT_XBARB2(XBAR_INPUT, 53) /* DMA_DONE3 output assigned to XBARB2_IN53 input. */
#define IMXRT_XBARB2_IN_DMA_DONE4 IMXRT_XBARB2(XBAR_INPUT, 54) /* DMA_DONE4 output assigned to XBARB2_IN54 input. */
#define IMXRT_XBARB2_IN_DMA_DONE5 IMXRT_XBARB2(XBAR_INPUT, 55) /* DMA_DONE5 output assigned to XBARB2_IN55 input. */
#define IMXRT_XBARB2_IN_DMA_DONE6 IMXRT_XBARB2(XBAR_INPUT, 56) /* DMA_DONE6 output assigned to XBARB2_IN56 input. */
#define IMXRT_XBARB2_IN_DMA_DONE7 IMXRT_XBARB2(XBAR_INPUT, 57) /* DMA_DONE7 output assigned to XBARB2_IN57 input. */
/* XBARB2 Mux Output (M Muxes) ********************************************************************************************************************/
#define IMXRT_XBARB2_OUT_AOI1_IN00_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 0) /* XBARB2_OUT0 output assigned to AOI1_IN00 */
#define IMXRT_XBARB2_OUT_AOI1_IN01_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 1) /* XBARB2_OUT1 output assigned to AOI1_IN01 */
#define IMXRT_XBARB2_OUT_AOI1_IN02_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 2) /* XBARB2_OUT2 output assigned to AOI1_IN02 */
#define IMXRT_XBARB2_OUT_AOI1_IN03_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 3) /* XBARB2_OUT3 output assigned to AOI1_IN03 */
#define IMXRT_XBARB2_OUT_AOI1_IN04_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 4) /* XBARB2_OUT4 output assigned to AOI1_IN04 */
#define IMXRT_XBARB2_OUT_AOI1_IN05_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 5) /* XBARB2_OUT5 output assigned to AOI1_IN05 */
#define IMXRT_XBARB2_OUT_AOI1_IN06_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 6) /* XBARB2_OUT6 output assigned to AOI1_IN06 */
#define IMXRT_XBARB2_OUT_AOI1_IN07_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 7) /* XBARB2_OUT7 output assigned to AOI1_IN07 */
#define IMXRT_XBARB2_OUT_AOI1_IN08_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 8) /* XBARB2_OUT8 output assigned to AOI1_IN08 */
#define IMXRT_XBARB2_OUT_AOI1_IN09_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 9) /* XBARB2_OUT9 output assigned to AOI1_IN09 */
#define IMXRT_XBARB2_OUT_AOI1_IN10_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 10) /* XBARB2_OUT10 output assigned to AOI1_IN10 */
#define IMXRT_XBARB2_OUT_AOI1_IN11_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 11) /* XBARB2_OUT11 output assigned to AOI1_IN11 */
#define IMXRT_XBARB2_OUT_AOI1_IN12_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 12) /* XBARB2_OUT12 output assigned to AOI1_IN12 */
#define IMXRT_XBARB2_OUT_AOI1_IN13_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 13) /* XBARB2_OUT13 output assigned to AOI1_IN13 */
#define IMXRT_XBARB2_OUT_AOI1_IN14_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 14) /* XBARB2_OUT14 output assigned to AOI1_IN14 */
#define IMXRT_XBARB2_OUT_AOI1_IN15_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 15) /* XBARB2_OUT15 output assigned to AOI1_IN15 */
arch/arm/src/imxrt/chip/rt105x/imxrt105x_ccm.h
-1145
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arch/arm/src/imxrt/chip/rt105x/imxrt105x_dmamux.h
-168
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@@ -1,168 +0,0 @@
/************************************************************************************
* arch/arm/src/imxrt/chip/imxrt105x_dmamux.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_DMAMUX_H
#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_DMAMUX_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Preprocessor Definitions
************************************************************************************/
/* Peripheral DMA request channels */
#define IMXRT_DMACHAN_FLEXIO1 0 /* FlexIO1 DMA 0/1, Async DMA 0/1 */
#define IMXRT_DMACHAN_FLEXIO2 1 /* FlexIO1 DMA 0/1, Async DMA 0/1 */
#define IMXRT_DMACHAN_LPUART1_TX 2 /* LPUART1 TX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPUART1_RX 3 /* LPUART1 RX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPUART3_TX 4 /* LPUART3 RX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPUART3_RX 5 /* LPUART3 RX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPUART5_TX 6 /* LPUART5 TX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPUART5_RX 7 /* LPUART5 RX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPUART7_TX 8 /* LPUART7 TX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPUART7_RX 9 /* LPUART7 RX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_CSI 12 /* CSI Write DMA */
#define IMXRT_DMACHAN_LPSPI1_RX 13 /* LPSPI1 RX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPSPI1_TX 14 /* LPSPI1 TX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPSPI3_RX 15 /* LPSPI3 RX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPSPI3_TX 16 /* LPSPI3 TX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPI2C1 17 /* LPI2C1 Master/Slave RX/TX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPI2C3 18 /* LPI2C3 Master/Slave RX/TX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_SAI1_RX 19 /* SAI1 RX FIFO DMA */
#define IMXRT_DMACHAN_SAI1_TX 20 /* SAI1 TX FIFO DMA */
#define IMXRT_DMACHAN_SAI2_RX 21 /* SAI2 RX FIFO DMA */
#define IMXRT_DMACHAN_SAI2_TX 22 /* SAI2 TX FIFO DMA */
#define IMXRT_DMACHAN_ADC_ETC 23 /* ADC ETC DMA */
#define IMXRT_DMACHAN_ADC1 24 /* ADC1 DMA */
#define IMXRT_DMACHAN_ACMP1 25 /* ACMP1 DMA */
#define IMXRT_DMACHAN_ACMP2 26 /* ACMP2 DMA */
#define IMXRT_DMACHAN_FLEXSPI_RX 28 /* FlexSPI RX FIFO DMA */
#define IMXRT_DMACHAN_FLEXSPI_TX 29 /* FlexSPI TX FIFO DMA */
#define IMXRT_DMACHAN_XBAR1_0 30 /* XBAR1 DMA 0 */
#define IMXRT_DMACHAN_XBAR1_1 31 /* XBAR1 DMA 1 */
#define IMXRT_DMACHAN_FLEXPWM1_RX0 32 /* FlexPWM1 RX sub-module0 capture */
#define IMXRT_DMACHAN_FLEXPWM1_RX1 33 /* FlexPWM1 RX sub-module1 capture */
#define IMXRT_DMACHAN_FLEXPWM1_RX2 34 /* FlexPWM1 RX sub-module2 capture */
#define IMXRT_DMACHAN_FLEXPWM1_RX3 35 /* FlexPWM1 RX sub-module3 capture */
#define IMXRT_DMACHAN_FLEXPWM1_TX0 36 /* FlexPWM1 TX sub-module0 value */
#define IMXRT_DMACHAN_FLEXPWM1_TX1 37 /* FlexPWM1 TX sub-module1 value */
#define IMXRT_DMACHAN_FLEXPWM1_TX2 38 /* FlexPWM1 TX sub-module2 value */
#define IMXRT_DMACHAN_FLEXPWM1_TX3 39 /* FlexPWM1 TX sub-module3 value */
#define IMXRT_DMACHAN_FLEXPWM3_RX0 40 /* FlexPWM3 RX sub-module0 capture */
#define IMXRT_DMACHAN_FLEXPWM3_RX1 41 /* FlexPWM3 RX sub-module1 capture */
#define IMXRT_DMACHAN_FLEXPWM3_RX2 42 /* FlexPWM3 RX sub-module2 capture */
#define IMXRT_DMACHAN_FLEXPWM3_RX3 43 /* FlexPWM3 RX sub-module3 capture */
#define IMXRT_DMACHAN_FLEXPWM3_TX0 44 /* FlexPWM3 TX sub-module0 value */
#define IMXRT_DMACHAN_FLEXPWM3_TX1 45 /* FlexPWM3 TX sub-module1 value */
#define IMXRT_DMACHAN_FLEXPWM3_TX2 46 /* FlexPWM3 TX sub-module2 value */
#define IMXRT_DMACHAN_FLEXPWM3_TX3 47 /* FlexPWM3 TX sub-module3 value */
#define IMXRT_DMACHAN_QTIMER1_RX0 48 /* QTimer1 RX capture timer 0 */
#define IMXRT_DMACHAN_QTIMER1_RX1 49 /* QTimer1 RX capture timer 1 */
#define IMXRT_DMACHAN_QTIMER1_RX2 50 /* QTimer1 RX capture timer 2 */
#define IMXRT_DMACHAN_QTIMER1_RX3 51 /* QTimer1 RX capture timer 3 */
#define IMXRT_DMACHAN_QTIMER1_TX0 52 /* QTimer1 TX cmpld1 timer 0 / cmld2 timer 1 */
#define IMXRT_DMACHAN_QTIMER1_TX1 53 /* QTimer1 TX cmpld1 timer 1 / cmld2 timer 0 */
#define IMXRT_DMACHAN_QTIMER1_TX2 54 /* QTimer1 TX cmpld1 timer 2 / cmld2 timer 3 */
#define IMXRT_DMACHAN_QTIMER1_TX3 55 /* QTimer1 TX cmpld1 timer 3 / cmld2 timer 2 */
#define IMXRT_DMACHAN_QTIMER3_RXTX0 56 /* QTimer1 RX capture timer 0 / TX cmpld1 timer 0 / cmld2 timer 1 */
#define IMXRT_DMACHAN_QTIMER3_RXTX1 57 /* QTimer1 RX capture timer 1 / TX cmpld1 timer 1 / cmld2 timer 0 */
#define IMXRT_DMACHAN_QTIMER3_RXTX2 58 /* QTimer1 RX capture timer 2 / TX cmpld1 timer 2 / cmld2 timer 3 */
#define IMXRT_DMACHAN_QTIMER3_RXTX3 59 /* QTimer1 RX capture timer 3 / TX cmpld1 timer 3 / cmld2 timer 2 */
#define IMXRT_DMACHAN_FLEXIO1_01 64 /* FlexIO1 DMA 0 / Async DMA 0 / DMA 1 / Async DMA 1 */
#define IMXRT_DMACHAN_FLEXIO2_23 65 /* FlexIO1 DMA 2 / Async DMA 2 / DMA 3 / Async DMA 3 */
#define IMXRT_DMACHAN_LPUART2_TX 66 /* LPUART2 TX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPUART2_RX 67 /* LPUART2 RX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPUART4_TX 68 /* LPUART4 TX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPUART4_RX 69 /* LPUART4 RX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPUART6_TX 70 /* LPUART6 TX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPUART6_RX 71 /* LPUART6 RX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPUART8_TX 72 /* LPUART8 TX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPUART8_RX 73 /* LPUART8 RX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_PXP 75 /* PXP DMA Event */
#define IMXRT_DMACHAN_LCDIF 76 /* LCDIF DMA Event */
#define IMXRT_DMACHAN_LPSPI2_RX 77 /* LPSPI2 RX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPSPI2_TX 78 /* LPSPI2 TX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPSPI4_RX 79 /* LPSPI4 RX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPSPI4_TX 80 /* LPSPI4 TX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPI2C2 81 /* LPI2C2 Master/Slave RX/TX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPI2C4 82 /* LPI2C4 Master/Slave RX/TX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_SAI3_RX 83 /* SAI3 RX FIFO DMA */
#define IMXRT_DMACHAN_SAI3_TX 84 /* SAI3 RX FIFO DMA */
#define IMXRT_DMACHAN_SPDIF_RX 85 /* SPDIF RX DMA */
#define IMXRT_DMACHAN_SPDIF_TX 86 /* SPDIF TX DMA */
#define IMXRT_DMACHAN_ADC2 88 /* ADC2 DMA */
#define IMXRT_DMACHAN_ACMP3 89 /* ACMP3 DMA */
#define IMXRT_DMACHAN_ACMP4 90 /* ACMP4 DMA */
#define IMXRT_DMACHAN_ENET_0 92 /* ENET Timer DMA 0 */
#define IMXRT_DMACHAN_ENET_1 93 /* ENET Timer DMA 1 */
#define IMXRT_DMACHAN_XBAR1_2 94 /* XBAR1 DMA 2 */
#define IMXRT_DMACHAN_XBAR1_3 95 /* XBAR1 DMA 3 */
#define IMXRT_DMACHAN_FLEXPWM2_RX0 96 /* FlexPWM2 RX sub-module0 capture */
#define IMXRT_DMACHAN_FLEXPWM2_RX1 97 /* FlexPWM2 RX sub-module1 capture */
#define IMXRT_DMACHAN_FLEXPWM2_RX2 98 /* FlexPWM2 RX sub-module2 capture */
#define IMXRT_DMACHAN_FLEXPWM2_RX3 99 /* FlexPWM2 RX sub-module3 capture */
#define IMXRT_DMACHAN_FLEXPWM2_TX0 100 /* FlexPWM2 TX sub-module0 value */
#define IMXRT_DMACHAN_FLEXPWM2_TX1 101 /* FlexPWM2 TX sub-module1 value */
#define IMXRT_DMACHAN_FLEXPWM2_TX2 102 /* FlexPWM2 TX sub-module2 value */
#define IMXRT_DMACHAN_FLEXPWM2_TX3 103 /* FlexPWM2 TX sub-module3 value */
#define IMXRT_DMACHAN_FLEXPWM4_RX0 104 /* FlexPWM4 RX sub-module0 capture */
#define IMXRT_DMACHAN_FLEXPWM4_RX1 105 /* FlexPWM4 RX sub-module1 capture */
#define IMXRT_DMACHAN_FLEXPWM4_RX2 106 /* FlexPWM4 RX sub-module2 capture */
#define IMXRT_DMACHAN_FLEXPWM4_RX3 107 /* FlexPWM4 RX sub-module3 capture */
#define IMXRT_DMACHAN_FLEXPWM4_TX0 108 /* FlexPWM4 TX sub-module0 value */
#define IMXRT_DMACHAN_FLEXPWM4_TX1 109 /* FlexPWM4 TX sub-module1 value */
#define IMXRT_DMACHAN_FLEXPWM4_TX2 110 /* FlexPWM4 TX sub-module2 value */
#define IMXRT_DMACHAN_FLEXPWM4_TX3 111 /* FlexPWM4 TX sub-module3 value */
#define IMXRT_DMACHAN_QTIMER2_RX0 112 /* QTimer2 RX capture timer 0 */
#define IMXRT_DMACHAN_QTIMER2_RX1 113 /* QTimer2 RX capture timer 1 */
#define IMXRT_DMACHAN_QTIMER2_RX2 114 /* QTimer2 RX capture timer 2 */
#define IMXRT_DMACHAN_QTIMER2_RX3 115 /* QTimer2 RX capture timer 3 */
#define IMXRT_DMACHAN_QTIMER2_TX0 116 /* QTimer2 TX cmpld1 timer 0 / cmld2 timer 1 */
#define IMXRT_DMACHAN_QTIMER2_TX1 117 /* QTimer2 TX cmpld1 timer 1 / cmld2 timer 0 */
#define IMXRT_DMACHAN_QTIMER2_TX2 118 /* QTimer2 TX cmpld1 timer 2 / cmld2 timer 3 */
#define IMXRT_DMACHAN_QTIMER2_TX3 119 /* QTimer2 TX cmpld1 timer 3 / cmld2 timer 2 */
#define IMXRT_DMACHAN_QTIMER4_RXTX0 120 /* QTimer4 RX capture timer 0 / TX cmpld1 timer 0 / cmld2 timer 1 */
#define IMXRT_DMACHAN_QTIMER4_RXTX1 121 /* QTimer4 RX capture timer 1 / TX cmpld1 timer 1 / cmld2 timer 0 */
#define IMXRT_DMACHAN_QTIMER4_RXTX2 122 /* QTimer4 RX capture timer 2 / TX cmpld1 timer 2 / cmld2 timer 3 */
#define IMXRT_DMACHAN_QTIMER4_RXTX3 123 /* QTimer4 RX capture timer 3 / TX cmpld1 timer 3 / cmld2 timer 2 */
#define IMXRT_DMA_NCHANNLES 128 /* Includes reserved channels */
#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_DMAMUX_H */
arch/arm/src/imxrt/chip/rt105x/imxrt105x_gpio.h
-127
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/********************************************************************************************
* arch/arm/src/imxrt/rt105x/imxrt105x_gpio.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_GPIO_H
#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_GPIO_H
/********************************************************************************************
* Included Files
********************************************************************************************/
#include <nuttx/config.h>
#include "chip/imxrt_memorymap.h"
/********************************************************************************************
* Pre-processor Definitions
********************************************************************************************/
/* Register offsets *************************************************************************/
#define IMXRT_GPIO_DR_OFFSET 0x0000 /* GPIO data register */
#define IMXRT_GPIO_GDIR_OFFSET 0x0004 /* GPIO direction register */
#define IMXRT_GPIO_PSR_OFFSET 0x0008 /* GPIO pad status register */
#define IMXRT_GPIO_ICR1_OFFSET 0x000c /* GPIO interrupt configuration register1 */
#define IMXRT_GPIO_ICR2_OFFSET 0x0010 /* GPIO interrupt configuration register2 */
#define IMXRT_GPIO_IMR_OFFSET 0x0014 /* GPIO interrupt mask register */
#define IMXRT_GPIO_ISR_OFFSET 0x0018 /* GPIO interrupt status register */
#define IMXRT_GPIO_EDGE_OFFSET 0x001c /* GPIO edge select register */
#define IMXRT_GPIO_SET_OFFSET 0x0084 /* GPIO data register SET */
#define IMXRT_GPIO_CLEAR_OFFSET 0x0088 /* GPIO data register CLEAR */
#define IMXRT_GPIO_TOGGLE_OFFSET 0x008c /* GPIO data register TOGGLE */
/* Register addresses ***********************************************************************/
#define IMXRT_GPIO1_DR (IMXRT_GPIO1_BASE + IMXRT_GPIO_DR_OFFSET)
#define IMXRT_GPIO1_GDIR (IMXRT_GPIO1_BASE + IMXRT_GPIO_GDIR_OFFSET)
#define IMXRT_GPIO1_PSR (IMXRT_GPIO1_BASE + IMXRT_GPIO_PSR_OFFSET)
#define IMXRT_GPIO1_ICR1 (IMXRT_GPIO1_BASE + IMXRT_GPIO_ICR1_OFFSET)
#define IMXRT_GPIO1_ICR2 (IMXRT_GPIO1_BASE + IMXRT_GPIO_ICR2_OFFSET)
#define IMXRT_GPIO1_IMR (IMXRT_GPIO1_BASE + IMXRT_GPIO_IMR_OFFSET)
#define IMXRT_GPIO1_ISR (IMXRT_GPIO1_BASE + IMXRT_GPIO_ISR_OFFSET)
#define IMXRT_GPIO1_EDGE (IMXRT_GPIO1_BASE + IMXRT_GPIO_EDGE_OFFSET)
#define IMXRT_GPIO1_SET (IMXRT_GPIO1_BASE + IMXRT_GPIO_SET_OFFSET)
#define IMXRT_GPIO1_CLEAR (IMXRT_GPIO1_BASE + IMXRT_GPIO_CLEAR_OFFSET)
#define IMXRT_GPIO1_TOGGLE (IMXRT_GPIO1_BASE + IMXRT_GPIO_TOGGLE_OFFSET)
#define IMXRT_GPIO2_DR (IMXRT_GPIO2_BASE + IMXRT_GPIO_DR_OFFSET)
#define IMXRT_GPIO2_GDIR (IMXRT_GPIO2_BASE + IMXRT_GPIO_GDIR_OFFSET)
#define IMXRT_GPIO2_PSR (IMXRT_GPIO2_BASE + IMXRT_GPIO_PSR_OFFSET)
#define IMXRT_GPIO2_ICR1 (IMXRT_GPIO2_BASE + IMXRT_GPIO_ICR1_OFFSET)
#define IMXRT_GPIO2_ICR2 (IMXRT_GPIO2_BASE + IMXRT_GPIO_ICR2_OFFSET)
#define IMXRT_GPIO2_IMR (IMXRT_GPIO2_BASE + IMXRT_GPIO_IMR_OFFSET)
#define IMXRT_GPIO2_ISR (IMXRT_GPIO2_BASE + IMXRT_GPIO_ISR_OFFSET)
#define IMXRT_GPIO2_EDGE (IMXRT_GPIO2_BASE + IMXRT_GPIO_EDGE_OFFSET)
#define IMXRT_GPIO2_SET (IMXRT_GPIO2_BASE + IMXRT_GPIO_SET_OFFSET)
#define IMXRT_GPIO2_CLEAR (IMXRT_GPIO2_BASE + IMXRT_GPIO_CLEAR_OFFSET)
#define IMXRT_GPIO2_TOGGLE (IMXRT_GPIO2_BASE + IMXRT_GPIO_TOGGLE_OFFSET)
#define IMXRT_GPIO3_DR (IMXRT_GPIO3_BASE + IMXRT_GPIO_DR_OFFSET)
#define IMXRT_GPIO3_GDIR (IMXRT_GPIO3_BASE + IMXRT_GPIO_GDIR_OFFSET)
#define IMXRT_GPIO3_PSR (IMXRT_GPIO3_BASE + IMXRT_GPIO_PSR_OFFSET)
#define IMXRT_GPIO3_ICR1 (IMXRT_GPIO3_BASE + IMXRT_GPIO_ICR1_OFFSET)
#define IMXRT_GPIO3_ICR2 (IMXRT_GPIO3_BASE + IMXRT_GPIO_ICR2_OFFSET)
#define IMXRT_GPIO3_IMR (IMXRT_GPIO3_BASE + IMXRT_GPIO_IMR_OFFSET)
#define IMXRT_GPIO3_ISR (IMXRT_GPIO3_BASE + IMXRT_GPIO_ISR_OFFSET)
#define IMXRT_GPIO3_EDGE (IMXRT_GPIO3_BASE + IMXRT_GPIO_EDGE_OFFSET)
#define IMXRT_GPIO3_SET (IMXRT_GPIO3_BASE + IMXRT_GPIO_SET_OFFSET)
#define IMXRT_GPIO3_CLEAR (IMXRT_GPIO3_BASE + IMXRT_GPIO_CLEAR_OFFSET)
#define IMXRT_GPIO3_TOGGLE (IMXRT_GPIO3_BASE + IMXRT_GPIO_TOGGLE_OFFSET)
#define IMXRT_GPIO4_DR (IMXRT_GPIO4_BASE + IMXRT_GPIO_DR_OFFSET)
#define IMXRT_GPIO4_GDIR (IMXRT_GPIO4_BASE + IMXRT_GPIO_GDIR_OFFSET)
#define IMXRT_GPIO4_PSR (IMXRT_GPIO4_BASE + IMXRT_GPIO_PSR_OFFSET)
#define IMXRT_GPIO4_ICR1 (IMXRT_GPIO4_BASE + IMXRT_GPIO_ICR1_OFFSET)
#define IMXRT_GPIO4_ICR2 (IMXRT_GPIO4_BASE + IMXRT_GPIO_ICR2_OFFSET)
#define IMXRT_GPIO4_IMR (IMXRT_GPIO4_BASE + IMXRT_GPIO_IMR_OFFSET)
#define IMXRT_GPIO4_ISR (IMXRT_GPIO4_BASE + IMXRT_GPIO_ISR_OFFSET)
#define IMXRT_GPIO4_EDGE (IMXRT_GPIO4_BASE + IMXRT_GPIO_EDGE_OFFSET)
#define IMXRT_GPIO4_SET (IMXRT_GPIO4_BASE + IMXRT_GPIO_SET_OFFSET)
#define IMXRT_GPIO4_CLEAR (IMXRT_GPIO4_BASE + IMXRT_GPIO_CLEAR_OFFSET)
#define IMXRT_GPIO4_TOGGLE (IMXRT_GPIO4_BASE + IMXRT_GPIO_TOGGLE_OFFSET)
#define IMXRT_GPIO5_DR (IMXRT_GPIO5_BASE + IMXRT_GPIO_DR_OFFSET)
#define IMXRT_GPIO5_GDIR (IMXRT_GPIO5_BASE + IMXRT_GPIO_GDIR_OFFSET)
#define IMXRT_GPIO5_PSR (IMXRT_GPIO5_BASE + IMXRT_GPIO_PSR_OFFSET)
#define IMXRT_GPIO5_ICR1 (IMXRT_GPIO5_BASE + IMXRT_GPIO_ICR1_OFFSET)
#define IMXRT_GPIO5_ICR2 (IMXRT_GPIO5_BASE + IMXRT_GPIO_ICR2_OFFSET)
#define IMXRT_GPIO5_IMR (IMXRT_GPIO5_BASE + IMXRT_GPIO_IMR_OFFSET)
#define IMXRT_GPIO5_ISR (IMXRT_GPIO5_BASE + IMXRT_GPIO_ISR_OFFSET)
#define IMXRT_GPIO5_EDGE (IMXRT_GPIO5_BASE + IMXRT_GPIO_EDGE_OFFSET)
#define IMXRT_GPIO5_SET (IMXRT_GPIO5_BASE + IMXRT_GPIO_SET_OFFSET)
#define IMXRT_GPIO5_CLEAR (IMXRT_GPIO5_BASE + IMXRT_GPIO_CLEAR_OFFSET)
#define IMXRT_GPIO5_TOGGLE (IMXRT_GPIO5_BASE + IMXRT_GPIO_TOGGLE_OFFSET)
#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_GPIO_H */
arch/arm/src/imxrt/chip/rt105x/imxrt105x_iomuxc.h
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arch/arm/src/imxrt/chip/rt105x/imxrt105x_memorymap.h
-258
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/************************************************************************************
* arch/arm/src/imxrt/chip/rt105x/imxrt105x_memorymap.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_MEMORYMAP_H
#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_MEMORYMAP_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* System memory map */
#define IMXRT_ITCM_BASE 0x00000000 /* 512KB ITCM */
/* 0x00080000 512KB ITCM Reserved */
/* 0x00100000 1MB ITCM Reserved */
#define IMXRT_ROMCP_BASE 0x00200000 /* 96KB ROMCP */
/* 0x00218000 416KB ROMCP Reserved */
/* 0x00280000 1536KB Reserved */
/* 0x00400000 124MB Reserved */
#define IMXRT_FLEXSPI_BASE 0x08000000 /* 128MB FlexSPI (Aliased) */
#define IMXRT_SEMCA_BASE 0x10000000 /* 256MB SEMC (Aliased) */
#define IMXRT_DTCM_BASE 0x20000000 /* 512KB DTCM */
/* 0x20080000 512KB DTCM Reserved */
/* 0x20100000 1MB Reserved */
#define IMXRT_OCRAM_BASE 0x20200000 /* 512KB OCRAM */
/* 0x20280000 1536KB OCRAM Reserved */
/* 0x20400000 252MB Reserved */
/* 0x30000000 256MB Reserved */
#define IMXRT_AIPS1_BASE 0x40000000 /* 1MB AIPS-1 */
#define IMXRT_AIPS2_BASE 0x40100000 /* 1MB AIPS-2 */
#define IMXRT_AIPS3_BASE 0x40200000 /* 1MB AIPS-3 */
#define IMXRT_AIPS4_BASE 0x40300000 /* 1MB AIPS-4 */
/* 40400000 12MB Reserved */
#define IMXRT_MAINCNF_BASE 0x41000000 /* 1MB "main" configuration port */
#define IMXRT_MCNF_BASE 0x41100000 /* 1MB "m" configuration port */
/* 41200000 1MB Reserved for "per" GPV */
/* 41300000 1MB Reserved for "ems" GPV */
#define IMXRT_CPUCNF_BASE 0x41400000 /* 1MB "cpu" configuration port */
/* 0x41500000 1MB GPV Reserved */
/* 0x41600000 1MB GPV Reserved */
/* 0x41700000 1MB GPV Reserved */
/* 0x41800000 8MB Reserved */
/* 0x42000000 32MB Reserved */
/* 0x44000000 64MB Reserved */
/* 0x48000000 384MB Reserved */
#define IMXRT_FLEXCIPHER_BASE 0x60000000 /* 504MB FlexSPI/ FlexSPI ciphertext */
#define IMXRT_FLEXSPITX_BASE 0x7f800000 /* 4MB FlexSPI TX FIFO */
#define IMXRT_FLEXSPIRX_BASE 0x7fc00000 /* 4MB FlexSPI RX FIFO */
#define IMXRT_EXTMEM_BASE 0x80000000 /* 1.5GB SEMC external memories shared memory space */
#define IMXRT_CM7_BASE 0xe0000000 /* 1MB CM7 PPB */
/* 0xe0100000 511MB Reserved */
/* AIPS-1 memory map */
/* 0x40000000 256KB Reserved */
/* 0x40040000 240KB Reserved */
#define IMXRT_AIPS1CNF_BASE 0x4007c000 /* 6KB AIPS-1 Configuration */
#define IMXRT_DCDC_BASE 0x40080000 /* 16KB DCDC */
#define IMXRT_PIT_BASE 0x40084000 /* 16KB PIT */
/* 0x40088000 16KB Reserved */
/* 0x4008c000 16KB Reserved */
#define IMXRT_MTR_BASE 0x40090000 /* 16KB MTR */
#define IMXRT_ACMP_BASE 0x40094000 /* 16KB ACMP */
/* 0x40098000 16KB Reserved */
/* 0x4009c000 16KB Reserved */
/* 0x400a0000 16KB Reserved */
#define IMXRT_IOMUXCSNVSGPR_BASE 0x400a4000 /* 16KB IOMUXC_SNVS_GPR */
#define IMXRT_IOMUXCSNVS_BASE 0x400a8000 /* 16KB IOMUXC_SNVS */
#define IMXRT_IOMUXCGPR_BASE 0x400ac000 /* 16KB IOMUXC_GPR */
#define IMXRT_FLEXRAM_BASE 0x400b0000 /* 16KB CM7_MX6RT(FLEXRAM) */
#define IMXRT_EWM_BASE 0x400b4000 /* 16KB EWM */
#define IMXRT_WDOG1_BASE 0x400b8000 /* 16KB WDOG1 */
#define IMXRT_WDOG3_BASE 0x400bc000 /* 16KB WDOG3 */
#define IMXRT_GPIO5_BASE 0x400c0000 /* 16KB GPIO5 */
#define IMXRT_ADC1_BASE 0x400c4000 /* 16KB ADC1 */
#define IMXRT_ADC2_BASE 0x400c8000 /* 16KB ADC2 */
#define IMXRT_TRNG_BASE 0x400cc000 /* 16KB TRNG */
#define IMXRT_WDOG2_BASE 0x400d0000 /* 16KB WDOG2 */
#define IMXRT_SNVSHP_BASE 0x400d4000 /* 16KB SNVS_HP */
#define IMXRT_ANATOP_BASE 0x400d8000 /* 16KB ANATOP */
#define IMXRT_CSU_BASE 0x400dc000 /* 16KB CSU */
/* 0x400e0000 16KB Reserved */
/* 0x400e4000 16KB Reserved */
#define IMXRT_EDMA_BASE 0x400e8000 /* 16KB EDMA */
#define IMXRT_DMAMUX_BASE 0x400ec000 /* 16KB DMA_CH_MUX */
/* 400f0000 16KB Reserved */
#define IMXRT_GPC_BASE 0x400f4000 /* 16KB GPC */
#define IMXRT_SRC_BASE 0x400f8000 /* 16KB SRC */
#define IMXRT_CCM_BASE 0x400fc000 /* 16KB CCM */
/* AIPS-2 memory map */
/* 0x40100000 256KB Reserved */
/* 0x40140000 240KB Reserved */
#define IMXRT_AIPS2CNF_BASE 0x4017c000 /* 16KB AIPS-2 Configuration */
#define IMXRT_ROMCPC_BASE 0x40180000 /* 16KB ROMCP controller*/
#define IMXRT_LPUART1_BASE 0x40184000 /* 16KB LPUART1 */
#define IMXRT_LPUART2_BASE 0x40188000 /* 16KB LPUART2 */
#define IMXRT_LPUART3_BASE 0x4018c000 /* 16KB LPUART3 */
#define IMXRT_LPUART4_BASE 0x40190000 /* 16KB LPUART4 */
#define IMXRT_LPUART5_BASE 0x40194000 /* 16KB LPUART5 */
#define IMXRT_LPUART6_BASE 0x40198000 /* 16KB LPUART6 */
#define IMXRT_LPUART7_BASE 0x4019c000 /* 16KB LPUART7 */
#define IMXRT_LPUART8_BASE 0x401a0000 /* 16KB LPUART8 */
/* 0x401a4000 16KB Reserved */
/* 0x401a8000 16KB Reserved */
#define IMXRT_FLEXIO1_BASE 0x401ac000 /* 16KB FlexIO1 */
#define IMXRT_FLEXIO2_BASE 0x401b0000 /* 16KB FlexIO2 */
/* 0x401b4000 16KB Reserved */
#define IMXRT_GPIO1_BASE 0x401b8000 /* 16KB GPIO1 */
#define IMXRT_GPIO2_BASE 0x401bc000 /* 16KB GPIO2 */
#define IMXRT_GPIO3_BASE 0x401c0000 /* 16KB GPIO3 */
#define IMXRT_GPIO4_BASE 0x401c4000 /* 16KB GPIO4 */
/* 0x401c8000 16KB Reserved */
/* 0x401cc000 16KB Reserved */
#define IMXRT_CAN1_BASE 0x401d0000 /* 16KB CAN1 */
#define IMXRT_CAN2_BASE 0x401d4000 /* 16KB CAN2 */
/* 0x401d8000 16KB Reserved */
#define IMXRT_QTIMER1_BASE 0x401dc000 /* 16KB QTimer1 */
#define IMXRT_QTIMER2_BASE 0x401e0000 /* 16KB QTimer2 */
#define IMXRT_QTIMER3_BASE 0x401e4000 /* 16KB QTimer3 */
#define IMXRT_QTIMER4_BASE 0x401e8000 /* 16KB QTimer4 */
#define IMXRT_GPT1_BASE 0x401ec000 /* 16KB GPT1 */
#define IMXRT_GPT2_BASE 0x401f0000 /* 16KB GPT2 */
#define IMXRT_OCOTP_BASE 0x401f4000 /* 16KB OCOTP */
#define IMXRT_IOMUXC_BASE 0x401f8000 /* 16KB IOMUXC */
#define IMXRT_KPP_BASE 0x401fc000 /* 16KB KPP */
/* AIPS-3 memory map */
/* 0x40200000 256KB Reserved */
/* 0x40240000 240KB Reserved */
#define IMXRT_AIOS3CNF_BASE 0x4027c000 /* 16KB AIPS-3 Configuration */
/* 0x40280000 16KB Reserved */
/* 0x40284000 16KB Reserved */
/* 0x40288000 16KB Reserved */
/* 0x4028c000 16KB Reserved */
/* 0x40290000 16KB Reserved */
/* 0x40294000 16KB Reserved */
/* 0x40298000 16KB Reserved */
/* 0x4029c000 16KB Reserved */
/* 0x402a0000 16KB Reserved */
/* 0x402a4000 16KB Reserved */
#define IMXRT_FLEXSPIC_BASE 0x402a8000 /* 16KB FlexSPI controller */
/* 0x402ac000 16KB Reserved */
/* 0x402b0000 16KB Reserved */
#define IMXRT_PXP_BASE 0x402b4000 /* 16KB PXP */
#define IMXRT_LCDIF_BASE 0x402b8000 /* 16KB LCDIF */
#define IMXRT_CSI_BASE 0x402bc000 /* 16KB CSI */
#define IMXRT_USDHC1_BASE 0x402c0000 /* 16KB USDHC1 */
#define IMXRT_USDHC2_BASE 0x402c4000 /* 16KB USDHC2 */
/* 0x402c8000 16KB Reserved */
/* 0x402cc000 16KB Reserved */
/* 0x402d0000 16KB Reserved */
/* 0x402d4000 16KB Reserved */
#define IMXRT_ENET_BASE 0x402d8000 /* 16KB ENET */
#define IMXRT_USBPL301_BASE 0x402dc000 /* 16KB USB(PL301) */
#define IMXRT_USB_BASE 0x402e0000 /* 16KB USB(USB) */
/* 0x402e4000 16KB Reserved */
/* 0x402e8000 16KB Reserved */
/* 0x402ec000 16KB Reserved */
#define IMXRT_SEMC_BASE 0x402f0000 /* 16KB SEMC */
/* 0x402f4000 16KB Reserved */
/* 0x402f8000 16KB Reserved */
#define IMXRT_DCP_BASE 0x402fc000 /* 16KB DCP */
/* AIPS-4 memory map */
/* 0x40300000 256KB Reserved */
/* 0x40340000 240KB Reserved */
#define IMXRT_AIPS4CNF_BASE 0x4037c000 /* 16KB AIPS-4 Configuration */
#define IMXRT_SPDIF_BASE 0x40380000 /* 16KB SPDIF */
#define IMXRT_SAI1_BASE 0x40384000 /* 16KB SAI1 */
#define IMXRT_SAI2_BASE 0x40388000 /* 16KB SAI2 */
#define IMXRT_SAI3_BASE 0x4038c000 /* 16KB SAI3 */
/* 0x40390000 16KB Reserved */
#define IMXRT_LPSPI1_BASE 0x40394000 /* 16KB LPSPI1 */
#define IMXRT_LPSPI2_BASE 0x40398000 /* 16KB LPSPI2 */
#define IMXRT_LPSPI3_BASE 0x4039c000 /* 16KB LPSPI3 */
#define IMXRT_LPSPI4_BASE 0x403a0000 /* 16KB LPSPI4 */
/* 0x403a4000 16KB Reserved */
/* 0x403a8000 16KB Reserved */
/* 0x403ac000 16KB Reserved */
#define IMXRT_ADCETC_BASE 0x403b0000 /* 16KB ADC_ETC */
#define IMXRT_AOI1_BASE 0x403b4000 /* 16KB AOI1 */
#define IMXRT_AOI2_BASE 0x403b8000 /* 16KB AOI2 */
#define IMXRT_XBAR1_BASE 0x403bc000 /* 16KB XBAR1 */
#define IMXRT_XBAR2_BASE 0x403c0000 /* 16KB XBAR2 */
#define IMXRT_XBAR3_BASE 0x403c4000 /* 16KB XBAR3 */
#define IMXRT_ENC1_BASE 0x403c8000 /* 16KB ENC1 */
#define IMXRT_ENC2_BASE 0x403cc000 /* 16KB ENC2 */
#define IMXRT_ENC3_BASE 0x403d0000 /* 16KB ENC3 */
#define IMXRT_ENC4_BASE 0x403d4000 /* 16KB ENC4 */
/* 0x403d8000 16KB Reserved */
#define IMXRT_FLEXPWM1_BASE 0x403dc000 /* 16KB FLEXPWM1 */
#define IMXRT_FLEXPWM2_BASE 0x403e0000 /* 16KB FLEXPWM2 */
#define IMXRT_FLEXPWM3_BASE 0x403e4000 /* 16KB FLEXPWM3 */
#define IMXRT_FLEXPWM4_BASE 0x403e8000 /* 16KB FLEXPWM4 */
#define IMXRT_BEE_BASE 0x403ec000 /* 16KB BEE */
#define IMXRT_LPI2C1_BASE 0x403f0000 /* 16KB */
#define IMXRT_LPI2C2_BASE 0x403f4000 /* 16KB LPI2C2 */
#define IMXRT_LPI2C3_BASE 0x403f8000 /* 16KB LPI2C3 */
#define IMXRT_LPI2C4_BASE 0x403fc000 /* 16KB LPI2C4 */
/* PPB memory map */
#define IMXRT_TPIU_BASE 0xe0040000 /* 4KB TPIU */
#define IMXRT_ETM_BASE 0xe0041000 /* 4KB ETM */
#define IMXRT_CTI_BASE 0xe0042000 /* 4KB CTI */
#define IMXRT_TSGEN_BASE 0xe0043000 /* 4KB TSGEN */
#define IMXRT_PPBRES_BASE 0xe0044000 /* 4KB PPB RES */
/* 0xe0045000 236KB PPB Reserved */
#define IMXRT_MCM_BASE 0xe0080000 /* 4KB MCM */
/* 0xe0081000 444KB PPB Reserved */
/* 0xe00f0000 52KB PPB Reserved */
#define IMXRT_SYSROM_BASE 0xe00fd000 /* 4KB SYS ROM */
#define IMXRT_PROCROM_BASE 0xe00fe000 /* 4KB Processor ROM */
#define IMXRT_PPBROM_BASE 0xe00ff000 /* 4KB PPB ROM */
#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_MEMORYMAP_H */
arch/arm/src/imxrt/chip/rt105x/imxrt105x_pinmux.h
-1090
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arch/arm/src/imxrt/chip/rt105x/imxrt105x_xbar.h
-386
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/* XBAR Defines for IMXRT1050 */
/* XBARA1 Mux inputs (I values) ***************************************************************************************************************************************/
#define IMXRT_XBARA1_IN_LOGIC_LOW IMXRT_XBARA1(XBAR_INPUT, 0) /* LOGIC_LOW output assigned to XBARA1_IN0 input. */
#define IMXRT_XBARA1_IN_LOGIC_HIGH IMXRT_XBARA1(XBAR_INPUT, 1) /* LOGIC_HIGH output assigned to XBARA1_IN1 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN02 IMXRT_XBARA1(XBAR_INPUT, 2) /* IOMUX_XBAR_IN02 output assigned to XBARA1_IN2 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN03 IMXRT_XBARA1(XBAR_INPUT, 3) /* IOMUX_XBAR_IN03 output assigned to XBARA1_IN3 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO04 IMXRT_XBARA1(XBAR_INPUT, 4) /* IOMUX_XBAR_INOUT04 output assigned to XBARA1_IN4 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO05 IMXRT_XBARA1(XBAR_INPUT, 5) /* IOMUX_XBAR_INOUT05 output assigned to XBARA1_IN5 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO06 IMXRT_XBARA1(XBAR_INPUT, 6) /* IOMUX_XBAR_INOUT06 output assigned to XBARA1_IN6 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO07 IMXRT_XBARA1(XBAR_INPUT, 7) /* IOMUX_XBAR_INOUT07 output assigned to XBARA1_IN7 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO08 IMXRT_XBARA1(XBAR_INPUT, 8) /* IOMUX_XBAR_INOUT08 output assigned to XBARA1_IN8 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO09 IMXRT_XBARA1(XBAR_INPUT, 9) /* IOMUX_XBAR_INOUT09 output assigned to XBARA1_IN9 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO10 IMXRT_XBARA1(XBAR_INPUT, 10) /* IOMUX_XBAR_INOUT10 output assigned to XBARA1_IN10 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO11 IMXRT_XBARA1(XBAR_INPUT, 11) /* IOMUX_XBAR_INOUT11 output assigned to XBARA1_IN11 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO12 IMXRT_XBARA1(XBAR_INPUT, 12) /* IOMUX_XBAR_INOUT12 output assigned to XBARA1_IN12 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO13 IMXRT_XBARA1(XBAR_INPUT, 13) /* IOMUX_XBAR_INOUT13 output assigned to XBARA1_IN13 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO14 IMXRT_XBARA1(XBAR_INPUT, 14) /* IOMUX_XBAR_INOUT14 output assigned to XBARA1_IN14 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO15 IMXRT_XBARA1(XBAR_INPUT, 15) /* IOMUX_XBAR_INOUT15 output assigned to XBARA1_IN15 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO16 IMXRT_XBARA1(XBAR_INPUT, 16) /* IOMUX_XBAR_INOUT16 output assigned to XBARA1_IN16 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO17 IMXRT_XBARA1(XBAR_INPUT, 17) /* IOMUX_XBAR_INOUT17 output assigned to XBARA1_IN17 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO18 IMXRT_XBARA1(XBAR_INPUT, 18) /* IOMUX_XBAR_INOUT18 output assigned to XBARA1_IN18 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO19 IMXRT_XBARA1(XBAR_INPUT, 19) /* IOMUX_XBAR_INOUT19 output assigned to XBARA1_IN19 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN20 IMXRT_XBARA1(XBAR_INPUT, 20) /* IOMUX_XBAR_IN20 output assigned to XBARA1_IN20 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN21 IMXRT_XBARA1(XBAR_INPUT, 21) /* IOMUX_XBAR_IN21 output assigned to XBARA1_IN21 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN22 IMXRT_XBARA1(XBAR_INPUT, 22) /* IOMUX_XBAR_IN22 output assigned to XBARA1_IN22 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN23 IMXRT_XBARA1(XBAR_INPUT, 23) /* IOMUX_XBAR_IN23 output assigned to XBARA1_IN23 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN24 IMXRT_XBARA1(XBAR_INPUT, 24) /* IOMUX_XBAR_IN24 output assigned to XBARA1_IN24 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN25 IMXRT_XBARA1(XBAR_INPUT, 25) /* IOMUX_XBAR_IN25 output assigned to XBARA1_IN25 input. */
#define IMXRT_XBARA1_IN_ACMP1_OUT IMXRT_XBARA1(XBAR_INPUT, 26) /* ACMP1_OUT output assigned to XBARA1_IN26 input. */
#define IMXRT_XBARA1_IN_ACMP2_OUT IMXRT_XBARA1(XBAR_INPUT, 27) /* ACMP2_OUT output assigned to XBARA1_IN27 input. */
#define IMXRT_XBARA1_IN_ACMP3_OUT IMXRT_XBARA1(XBAR_INPUT, 28) /* ACMP3_OUT output assigned to XBARA1_IN28 input. */
#define IMXRT_XBARA1_IN_ACMP4_OUT IMXRT_XBARA1(XBAR_INPUT, 29) /* ACMP4_OUT output assigned to XBARA1_IN29 input. */
#define IMXRT_XBARA1_IN_RESERVED30 IMXRT_XBARA1(XBAR_INPUT, 30) /* XBARA1_IN30 input is reserved. */
#define IMXRT_XBARA1_IN_RESERVED31 IMXRT_XBARA1(XBAR_INPUT, 31) /* XBARA1_IN31 input is reserved. */
#define IMXRT_XBARA1_IN_QTIMER3_TMR0_OUT IMXRT_XBARA1(XBAR_INPUT, 32) /* QTIMER3_TMR0_OUTPUT output assigned to XBARA1_IN32 input. */
#define IMXRT_XBARA1_IN_QTIMER3_TMR1_OUT IMXRT_XBARA1(XBAR_INPUT, 33) /* QTIMER3_TMR1_OUTPUT output assigned to XBARA1_IN33 input. */
#define IMXRT_XBARA1_IN_QTIMER3_TMR2_OUT IMXRT_XBARA1(XBAR_INPUT, 34) /* QTIMER3_TMR2_OUTPUT output assigned to XBARA1_IN34 input. */
#define IMXRT_XBARA1_IN_QTIMER3_TMR3_OUT IMXRT_XBARA1(XBAR_INPUT, 35) /* QTIMER3_TMR3_OUTPUT output assigned to XBARA1_IN35 input. */
#define IMXRT_XBARA1_IN_QTIMER4_TMR0_OUT IMXRT_XBARA1(XBAR_INPUT, 36) /* QTIMER4_TMR0_OUTPUT output assigned to XBARA1_IN36 input. */
#define IMXRT_XBARA1_IN_QTIMER4_TMR1_OUT IMXRT_XBARA1(XBAR_INPUT, 37) /* QTIMER4_TMR1_OUTPUT output assigned to XBARA1_IN37 input. */
#define IMXRT_XBARA1_IN_QTIMER4_TMR2_OUT IMXRT_XBARA1(XBAR_INPUT, 38) /* QTIMER4_TMR2_OUTPUT output assigned to XBARA1_IN38 input. */
#define IMXRT_XBARA1_IN_QTIMER4_TMR3_OUT IMXRT_XBARA1(XBAR_INPUT, 39) /* QTIMER4_TMR3_OUTPUT output assigned to XBARA1_IN39 input. */
#define IMXRT_XBARA1_IN_FLEXPWM1_PWM1_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 40) /* FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN40 input. */
#define IMXRT_XBARA1_IN_FLEXPWM1_PWM2_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 41) /* FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN41 input. */
#define IMXRT_XBARA1_IN_FLEXPWM1_PWM3_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 42) /* FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN42 input. */
#define IMXRT_XBARA1_IN_FLEXPWM1_PWM4_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 43) /* FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN43 input. */
#define IMXRT_XBARA1_IN_FLEXPWM2_PWM1_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 44) /* FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN44 input. */
#define IMXRT_XBARA1_IN_FLEXPWM2_PWM2_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 45) /* FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN45 input. */
#define IMXRT_XBARA1_IN_FLEXPWM2_PWM3_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 46) /* FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN46 input. */
#define IMXRT_XBARA1_IN_FLEXPWM2_PWM4_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 47) /* FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN47 input. */
#define IMXRT_XBARA1_IN_FLEXPWM3_PWM1_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 48) /* FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN48 input. */
#define IMXRT_XBARA1_IN_FLEXPWM3_PWM2_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 49) /* FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN49 input. */
#define IMXRT_XBARA1_IN_FLEXPWM3_PWM3_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 50) /* FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN50 input. */
#define IMXRT_XBARA1_IN_FLEXPWM3_PWM4_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 51) /* FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN51 input. */
#define IMXRT_XBARA1_IN_FLEXPWM4_PWM1_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 52) /* FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN52 input. */
#define IMXRT_XBARA1_IN_FLEXPWM4_PWM2_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 53) /* FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN53 input. */
#define IMXRT_XBARA1_IN_FLEXPWM4_PWM3_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 54) /* FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN54 input. */
#define IMXRT_XBARA1_IN_FLEXPWM4_PWM4_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 55) /* FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN55 input. */
#define IMXRT_XBARA1_IN_PIT_TRIGGER0 IMXRT_XBARA1(XBAR_INPUT, 56) /* PIT_TRIGGER0 output assigned to XBARA1_IN56 input. */
#define IMXRT_XBARA1_IN_PIT_TRIGGER1 IMXRT_XBARA1(XBAR_INPUT, 57) /* PIT_TRIGGER1 output assigned to XBARA1_IN57 input. */
#define IMXRT_XBARA1_IN_PIT_TRIGGER2 IMXRT_XBARA1(XBAR_INPUT, 58) /* PIT_TRIGGER2 output assigned to XBARA1_IN58 input. */
#define IMXRT_XBARA1_IN_PIT_TRIGGER3 IMXRT_XBARA1(XBAR_INPUT, 59) /* PIT_TRIGGER3 output assigned to XBARA1_IN59 input. */
#define IMXRT_XBARA1_IN_ENC1_POS_MATCH IMXRT_XBARA1(XBAR_INPUT, 60) /* ENC1_POS_MATCH output assigned to XBARA1_IN60 input. */
#define IMXRT_XBARA1_IN_ENC2_POS_MATCH IMXRT_XBARA1(XBAR_INPUT, 61) /* ENC2_POS_MATCH output assigned to XBARA1_IN61 input. */
#define IMXRT_XBARA1_IN_ENC3_POS_MATCH IMXRT_XBARA1(XBAR_INPUT, 62) /* ENC3_POS_MATCH output assigned to XBARA1_IN62 input. */
#define IMXRT_XBARA1_IN_ENC4_POS_MATCH IMXRT_XBARA1(XBAR_INPUT, 63) /* ENC4_POS_MATCH output assigned to XBARA1_IN63 input. */
#define IMXRT_XBARA1_IN_DMA_DONE0 IMXRT_XBARA1(XBAR_INPUT, 64) /* DMA_DONE0 output assigned to XBARA1_IN64 input. */
#define IMXRT_XBARA1_IN_DMA_DONE1 IMXRT_XBARA1(XBAR_INPUT, 65) /* DMA_DONE1 output assigned to XBARA1_IN65 input. */
#define IMXRT_XBARA1_IN_DMA_DONE2 IMXRT_XBARA1(XBAR_INPUT, 66) /* DMA_DONE2 output assigned to XBARA1_IN66 input. */
#define IMXRT_XBARA1_IN_DMA_DONE3 IMXRT_XBARA1(XBAR_INPUT, 67) /* DMA_DONE3 output assigned to XBARA1_IN67 input. */
#define IMXRT_XBARA1_IN_DMA_DONE4 IMXRT_XBARA1(XBAR_INPUT, 68) /* DMA_DONE4 output assigned to XBARA1_IN68 input. */
#define IMXRT_XBARA1_IN_DMA_DONE5 IMXRT_XBARA1(XBAR_INPUT, 69) /* DMA_DONE5 output assigned to XBARA1_IN69 input. */
#define IMXRT_XBARA1_IN_DMA_DONE6 IMXRT_XBARA1(XBAR_INPUT, 70) /* DMA_DONE6 output assigned to XBARA1_IN70 input. */
#define IMXRT_XBARA1_IN_DMA_DONE7 IMXRT_XBARA1(XBAR_INPUT, 71) /* DMA_DONE7 output assigned to XBARA1_IN71 input. */
#define IMXRT_XBARA1_IN_AOI1_OUT0 IMXRT_XBARA1(XBAR_INPUT, 72) /* AOI1_OUT0 output assigned to XBARA1_IN72 input. */
#define IMXRT_XBARA1_IN_AOI1_OUT1 IMXRT_XBARA1(XBAR_INPUT, 73) /* AOI1_OUT1 output assigned to XBARA1_IN73 input. */
#define IMXRT_XBARA1_IN_AOI1_OUT2 IMXRT_XBARA1(XBAR_INPUT, 74) /* AOI1_OUT2 output assigned to XBARA1_IN74 input. */
#define IMXRT_XBARA1_IN_AOI1_OUT3 IMXRT_XBARA1(XBAR_INPUT, 75) /* AOI1_OUT3 output assigned to XBARA1_IN75 input. */
#define IMXRT_XBARA1_IN_AOI2_OUT0 IMXRT_XBARA1(XBAR_INPUT, 76) /* AOI2_OUT0 output assigned to XBARA1_IN76 input. */
#define IMXRT_XBARA1_IN_AOI2_OUT1 IMXRT_XBARA1(XBAR_INPUT, 77) /* AOI2_OUT1 output assigned to XBARA1_IN77 input. */
#define IMXRT_XBARA1_IN_AOI2_OUT2 IMXRT_XBARA1(XBAR_INPUT, 78) /* AOI2_OUT2 output assigned to XBARA1_IN78 input. */
#define IMXRT_XBARA1_IN_AOI2_OUT3 IMXRT_XBARA1(XBAR_INPUT, 79) /* AOI2_OUT3 output assigned to XBARA1_IN79 input. */
#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO0 IMXRT_XBARA1(XBAR_INPUT, 80) /* ADC_ETC_XBAR0_COCO0 output assigned to XBARA1_IN80 input. */
#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO1 IMXRT_XBARA1(XBAR_INPUT, 81) /* ADC_ETC_XBAR0_COCO1 output assigned to XBARA1_IN81 input. */
#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO2 IMXRT_XBARA1(XBAR_INPUT, 82) /* ADC_ETC_XBAR0_COCO2 output assigned to XBARA1_IN82 input. */
#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO3 IMXRT_XBARA1(XBAR_INPUT, 83) /* ADC_ETC_XBAR0_COCO3 output assigned to XBARA1_IN83 input. */
#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO0 IMXRT_XBARA1(XBAR_INPUT, 84) /* ADC_ETC_XBAR1_COCO0 output assigned to XBARA1_IN84 input. */
#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO1 IMXRT_XBARA1(XBAR_INPUT, 85) /* ADC_ETC_XBAR1_COCO1 output assigned to XBARA1_IN85 input. */
#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO2 IMXRT_XBARA1(XBAR_INPUT, 86) /* ADC_ETC_XBAR1_COCO2 output assigned to XBARA1_IN86 input. */
#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO3 IMXRT_XBARA1(XBAR_INPUT, 87) /* ADC_ETC_XBAR1_COCO3 output assigned to XBARA1_IN87 input. */
/* XBARA1 Mux Output (M Muxes) ***************************************************************************************************************/
#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ30_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 0) /* XBARA1_OUT0 output assigned to DMA_CH_MUX_REQ30 */
#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ31_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 1) /* XBARA1_OUT1 output assigned to DMA_CH_MUX_REQ31 */
#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ94_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 2) /* XBARA1_OUT2 output assigned to DMA_CH_MUX_REQ94 */
#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ95_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 3) /* XBARA1_OUT3 output assigned to DMA_CH_MUX_REQ95 */
#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO04_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 4) /* XBARA1_OUT4 output assigned to IOMUX_XBAR_INOUT04 */
#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO05_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 5) /* XBARA1_OUT5 output assigned to IOMUX_XBAR_INOUT05 */
#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO06_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 6) /* XBARA1_OUT6 output assigned to IOMUX_XBAR_INOUT06 */
#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO07_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 7) /* XBARA1_OUT7 output assigned to IOMUX_XBAR_INOUT07 */
#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO08_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 8) /* XBARA1_OUT8 output assigned to IOMUX_XBAR_INOUT08 */
#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO09_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 9) /* XBARA1_OUT9 output assigned to IOMUX_XBAR_INOUT09 */
#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO10_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 10) /* XBARA1_OUT10 output assigned to IOMUX_XBAR_INOUT10 */
#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO11_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 11) /* XBARA1_OUT11 output assigned to IOMUX_XBAR_INOUT11 */
#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO12_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 12) /* XBARA1_OUT12 output assigned to IOMUX_XBAR_INOUT12 */
#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO13_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 13) /* XBARA1_OUT13 output assigned to IOMUX_XBAR_INOUT13 */
#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO14_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 14) /* XBARA1_OUT14 output assigned to IOMUX_XBAR_INOUT14 */
#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO15_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 15) /* XBARA1_OUT15 output assigned to IOMUX_XBAR_INOUT15 */
#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO16_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 16) /* XBARA1_OUT16 output assigned to IOMUX_XBAR_INOUT16 */
#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO17_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 17) /* XBARA1_OUT17 output assigned to IOMUX_XBAR_INOUT17 */
#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO18_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 18) /* XBARA1_OUT18 output assigned to IOMUX_XBAR_INOUT18 */
#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO19_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 19) /* XBARA1_OUT19 output assigned to IOMUX_XBAR_INOUT19 */
#define IMXRT_XBARA1_OUT_ACMP1_SAMPLE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 20) /* XBARA1_OUT20 output assigned to ACMP1_SAMPLE */
#define IMXRT_XBARA1_OUT_ACMP2_SAMPLE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 21) /* XBARA1_OUT21 output assigned to ACMP2_SAMPLE */
#define IMXRT_XBARA1_OUT_ACMP3_SAMPLE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 22) /* XBARA1_OUT22 output assigned to ACMP3_SAMPLE */
#define IMXRT_XBARA1_OUT_ACMP4_SAMPLE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 23) /* XBARA1_OUT23 output assigned to ACMP4_SAMPLE */
#define IMXRT_XBARA1_OUT_RESERVED24_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 24) /* XBARA1_OUT24 output is reserved. */
#define IMXRT_XBARA1_OUT_RESERVED25_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 25) /* XBARA1_OUT25 output is reserved. */
#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 26) /* XBARA1_OUT26 output assigned to FLEXPWM1_EXTA0 */
#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 27) /* XBARA1_OUT27 output assigned to FLEXPWM1_EXTA1 */
#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 28) /* XBARA1_OUT28 output assigned to FLEXPWM1_EXTA2 */
#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 29) /* XBARA1_OUT29 output assigned to FLEXPWM1_EXTA3 */
#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 30) /* XBARA1_OUT30 output assigned to FLEXPWM1_EXT_SYNC0 */
#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 31) /* XBARA1_OUT31 output assigned to FLEXPWM1_EXT_SYNC1 */
#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 32) /* XBARA1_OUT32 output assigned to FLEXPWM1_EXT_SYNC2 */
#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 33) /* XBARA1_OUT33 output assigned to FLEXPWM1_EXT_SYNC3 */
#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_CLK_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 34) /* XBARA1_OUT34 output assigned to FLEXPWM1_EXT_CLK */
#define IMXRT_XBARA1_OUT_FLEXPWM1_FAULT0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 35) /* XBARA1_OUT35 output assigned to FLEXPWM1_FAULT0 */
#define IMXRT_XBARA1_OUT_FLEXPWM1_FAULT1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 36) /* XBARA1_OUT36 output assigned to FLEXPWM1_FAULT1 */
#define IMXRT_XBARA1_OUT_FLEXPWM1234_FAULT2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 37) /* XBARA1_OUT37 output assigned to FLEXPWM1_2_3_4_FAULT2 */
#define IMXRT_XBARA1_OUT_FLEXPWM1234_FAULT3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 38) /* XBARA1_OUT38 output assigned to FLEXPWM1_2_3_4_FAULT3 */
#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_FORCE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 39) /* XBARA1_OUT39 output assigned to FLEXPWM1_EXT_FORCE */
#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 40) /* XBARA1_OUT40 output assigned to FLEXPWM2_3_4_EXTA0 */
#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 41) /* XBARA1_OUT41 output assigned to FLEXPWM2_3_4_EXTA1 */
#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 42) /* XBARA1_OUT42 output assigned to FLEXPWM2_3_4_EXTA2 */
#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 43) /* XBARA1_OUT43 output assigned to FLEXPWM2_3_4_EXTA3 */
#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 44) /* XBARA1_OUT44 output assigned to FLEXPWM2_EXT_SYNC0 */
#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 45) /* XBARA1_OUT45 output assigned to FLEXPWM2_EXT_SYNC1 */
#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 46) /* XBARA1_OUT46 output assigned to FLEXPWM2_EXT_SYNC2 */
#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 47) /* XBARA1_OUT47 output assigned to FLEXPWM2_EXT_SYNC3 */
#define IMXRT_XBARA1_OUT_FLEXPWM234_EXT_CLK_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 48) /* XBARA1_OUT48 output assigned to FLEXPWM2_3_4_EXT_CLK */
#define IMXRT_XBARA1_OUT_FLEXPWM2_FAULT0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 49) /* XBARA1_OUT49 output assigned to FLEXPWM2_FAULT0 */
#define IMXRT_XBARA1_OUT_FLEXPWM2_FAULT1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 50) /* XBARA1_OUT50 output assigned to FLEXPWM2_FAULT1 */
#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_FORCE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 51) /* XBARA1_OUT51 output assigned to FLEXPWM2_EXT_FORCE */
#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 52) /* XBARA1_OUT52 output assigned to FLEXPWM3_EXT_SYNC0 */
#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 53) /* XBARA1_OUT53 output assigned to FLEXPWM3_EXT_SYNC1 */
#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 54) /* XBARA1_OUT54 output assigned to FLEXPWM3_EXT_SYNC2 */
#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 55) /* XBARA1_OUT55 output assigned to FLEXPWM3_EXT_SYNC3 */
#define IMXRT_XBARA1_OUT_FLEXPWM3_FAULT0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 56) /* XBARA1_OUT56 output assigned to FLEXPWM3_FAULT0 */
#define IMXRT_XBARA1_OUT_FLEXPWM3_FAULT1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 57) /* XBARA1_OUT57 output assigned to FLEXPWM3_FAULT1 */
#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_FORCE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 58) /* XBARA1_OUT58 output assigned to FLEXPWM3_EXT_FORCE */
#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 59) /* XBARA1_OUT59 output assigned to FLEXPWM4_EXT_SYNC0 */
#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 60) /* XBARA1_OUT60 output assigned to FLEXPWM4_EXT_SYNC1 */
#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 61) /* XBARA1_OUT61 output assigned to FLEXPWM4_EXT_SYNC2 */
#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 62) /* XBARA1_OUT62 output assigned to FLEXPWM4_EXT_SYNC3 */
#define IMXRT_XBARA1_OUT_FLEXPWM4_FAULT0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 63) /* XBARA1_OUT63 output assigned to FLEXPWM4_FAULT0 */
#define IMXRT_XBARA1_OUT_FLEXPWM4_FAULT1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 64) /* XBARA1_OUT64 output assigned to FLEXPWM4_FAULT1 */
#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_FORCE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 65) /* XBARA1_OUT65 output assigned to FLEXPWM4_EXT_FORCE */
#define IMXRT_XBARA1_OUT_ENC1_PHASE_AIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 66) /* XBARA1_OUT66 output assigned to ENC1_PHASE_A_IN_ */
#define IMXRT_XBARA1_OUT_ENC1_PHASE_BIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 67) /* XBARA1_OUT67 output assigned to ENC1_PHASE_B_IN_ */
#define IMXRT_XBARA1_OUT_ENC1_INDEX_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 68) /* XBARA1_OUT68 output assigned to ENC1_INDEX */
#define IMXRT_XBARA1_OUT_ENC1_HOME_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 69) /* XBARA1_OUT69 output assigned to ENC1_HOME */
#define IMXRT_XBARA1_OUT_ENC1_TRIGGER_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 70) /* XBARA1_OUT70 output assigned to ENC1_TRIGGER */
#define IMXRT_XBARA1_OUT_ENC2_PHASE_AIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 71) /* XBARA1_OUT71 output assigned to ENC2_PHASE_A_IN_ */
#define IMXRT_XBARA1_OUT_ENC2_PHASE_BIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 72) /* XBARA1_OUT72 output assigned to ENC2_PHASE_B_IN_ */
#define IMXRT_XBARA1_OUT_ENC2_INDEX_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 73) /* XBARA1_OUT73 output assigned to ENC2_INDEX */
#define IMXRT_XBARA1_OUT_ENC2_HOME_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 74) /* XBARA1_OUT74 output assigned to ENC2_HOME */
#define IMXRT_XBARA1_OUT_ENC2_TRIGGER_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 75) /* XBARA1_OUT75 output assigned to ENC2_TRIGGER */
#define IMXRT_XBARA1_OUT_ENC3_PHASE_AIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 76) /* XBARA1_OUT76 output assigned to ENC3_PHASE_A_IN_ */
#define IMXRT_XBARA1_OUT_ENC3_PHASE_BIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 77) /* XBARA1_OUT77 output assigned to ENC3_PHASE_B_IN_ */
#define IMXRT_XBARA1_OUT_ENC3_INDEX_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 78) /* XBARA1_OUT78 output assigned to ENC3_INDEX */
#define IMXRT_XBARA1_OUT_ENC3_HOME_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 79) /* XBARA1_OUT79 output assigned to ENC3_HOME */
#define IMXRT_XBARA1_OUT_ENC3_TRIGGER_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 80) /* XBARA1_OUT80 output assigned to ENC3_TRIGGER */
#define IMXRT_XBARA1_OUT_ENC4_PHASE_AIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 81) /* XBARA1_OUT81 output assigned to ENC4_PHASE_A_IN_ */
#define IMXRT_XBARA1_OUT_ENC4_PHASE_BIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 82) /* XBARA1_OUT82 output assigned to ENC4_PHASE_B_IN_ */
#define IMXRT_XBARA1_OUT_ENC4_INDEX_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 83) /* XBARA1_OUT83 output assigned to ENC4_INDEX */
#define IMXRT_XBARA1_OUT_ENC4_HOME_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 84) /* XBARA1_OUT84 output assigned to ENC4_HOME */
#define IMXRT_XBARA1_OUT_ENC4_TRIGGER_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 85) /* XBARA1_OUT85 output assigned to ENC4_TRIGGER */
#define IMXRT_XBARA1_OUT_QTIMER1_TMR0_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 86) /* XBARA1_OUT86 output assigned to QTIMER1_TMR0_IN_ */
#define IMXRT_XBARA1_OUT_QTIMER1_TMR1_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 87) /* XBARA1_OUT87 output assigned to QTIMER1_TMR1_IN_ */
#define IMXRT_XBARA1_OUT_QTIMER1_TMR2_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 88) /* XBARA1_OUT88 output assigned to QTIMER1_TMR2_IN_ */
#define IMXRT_XBARA1_OUT_QTIMER1_TMR3_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 89) /* XBARA1_OUT89 output assigned to QTIMER1_TMR3_IN_ */
#define IMXRT_XBARA1_OUT_QTIMER2_TMR0_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 90) /* XBARA1_OUT90 output assigned to QTIMER2_TMR0_IN_ */
#define IMXRT_XBARA1_OUT_QTIMER2_TMR1_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 91) /* XBARA1_OUT91 output assigned to QTIMER2_TMR1_IN_ */
#define IMXRT_XBARA1_OUT_QTIMER2_TMR2_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 92) /* XBARA1_OUT92 output assigned to QTIMER2_TMR2_IN_ */
#define IMXRT_XBARA1_OUT_QTIMER2_TMR3_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 93) /* XBARA1_OUT93 output assigned to QTIMER2_TMR3_IN_ */
#define IMXRT_XBARA1_OUT_QTIMER3_TMR0_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 94) /* XBARA1_OUT94 output assigned to QTIMER3_TMR0_IN_ */
#define IMXRT_XBARA1_OUT_QTIMER3_TMR1_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 95) /* XBARA1_OUT95 output assigned to QTIMER3_TMR1_IN_ */
#define IMXRT_XBARA1_OUT_QTIMER3_TMR2_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 96) /* XBARA1_OUT96 output assigned to QTIMER3_TMR2_IN_ */
#define IMXRT_XBARA1_OUT_QTIMER3_TMR3_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 97) /* XBARA1_OUT97 output assigned to QTIMER3_TMR3_IN_ */
#define IMXRT_XBARA1_OUT_QTIMER4_TMR0_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 98) /* XBARA1_OUT98 output assigned to QTIMER4_TMR0_IN_ */
#define IMXRT_XBARA1_OUT_QTIMER4_TMR1_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 99) /* XBARA1_OUT99 output assigned to QTIMER4_TMR1_IN_ */
#define IMXRT_XBARA1_OUT_QTIMER4_TMR2_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 100) /* XBARA1_OUT100 output assigned to QTIMER4_TMR2_IN_ */
#define IMXRT_XBARA1_OUT_QTIMER4_TMR3_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 101) /* XBARA1_OUT101 output assigned to QTIMER4_TMR3_IN_ */
#define IMXRT_XBARA1_OUT_EWM_EWM_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 102) /* XBARA1_OUT102 output assigned to EWM_EWM_IN */
#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 103) /* XBARA1_OUT103 output assigned to ADC_ETC_XBAR0_TRIG0 */
#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 104) /* XBARA1_OUT104 output assigned to ADC_ETC_XBAR0_TRIG1 */
#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 105) /* XBARA1_OUT105 output assigned to ADC_ETC_XBAR0_TRIG2 */
#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 106) /* XBARA1_OUT106 output assigned to ADC_ETC_XBAR0_TRIG3 */
#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 107) /* XBARA1_OUT107 output assigned to ADC_ETC_XBAR1_TRIG0 */
#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 108) /* XBARA1_OUT108 output assigned to ADC_ETC_XBAR1_TRIG1 */
#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 109) /* XBARA1_OUT109 output assigned to ADC_ETC_XBAR1_TRIG2 */
#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 110) /* XBARA1_OUT110 output assigned to ADC_ETC_XBAR1_TRIG3 */
#define IMXRT_XBARA1_OUT_LPI2C1_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 111) /* XBARA1_OUT111 output assigned to LPI2C1_TRG_IN_ */
#define IMXRT_XBARA1_OUT_LPI2C2_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 112) /* XBARA1_OUT112 output assigned to LPI2C2_TRG_IN_ */
#define IMXRT_XBARA1_OUT_LPI2C3_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 113) /* XBARA1_OUT113 output assigned to LPI2C3_TRG_IN_ */
#define IMXRT_XBARA1_OUT_LPI2C4_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 114) /* XBARA1_OUT114 output assigned to LPI2C4_TRG_IN_ */
#define IMXRT_XBARA1_OUT_LPSPI1_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 115) /* XBARA1_OUT115 output assigned to LPSPI1_TRG_IN_ */
#define IMXRT_XBARA1_OUT_LPSPI2_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 116) /* XBARA1_OUT116 output assigned to LPSPI2_TRG_IN_ */
#define IMXRT_XBARA1_OUT_LPSPI3_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 117) /* XBARA1_OUT117 output assigned to LPSPI3_TRG_IN_ */
#define IMXRT_XBARA1_OUT_LPSPI4_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 118) /* XBARA1_OUT118 output assigned to LPSPI4_TRG_IN_ */
#define IMXRT_XBARA1_OUT_LPUART1_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 119) /* XBARA1_OUT119 output assigned to LPUART1_TRG_IN_ */
#define IMXRT_XBARA1_OUT_LPUART2_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 120) /* XBARA1_OUT120 output assigned to LPUART2_TRG_IN_ */
#define IMXRT_XBARA1_OUT_LPUART3_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 121) /* XBARA1_OUT121 output assigned to LPUART3_TRG_IN_ */
#define IMXRT_XBARA1_OUT_LPUART4_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 122) /* XBARA1_OUT122 output assigned to LPUART4_TRG_IN_ */
#define IMXRT_XBARA1_OUT_LPUART5_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 123) /* XBARA1_OUT123 output assigned to LPUART5_TRG_IN_ */
#define IMXRT_XBARA1_OUT_LPUART6_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 124) /* XBARA1_OUT124 output assigned to LPUART6_TRG_IN_ */
#define IMXRT_XBARA1_OUT_LPUART7_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 125) /* XBARA1_OUT125 output assigned to LPUART7_TRG_IN_ */
#define IMXRT_XBARA1_OUT_LPUART8_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 126) /* XBARA1_OUT126 output assigned to LPUART8_TRG_IN_ */
#define IMXRT_XBARA1_OUT_FLEXIO1_TRIGGER_IN0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 127) /* XBARA1_OUT127 output assigned to FLEXIO1_TRIGGER_IN0 */
#define IMXRT_XBARA1_OUT_FLEXIO1_TRIGGER_IN1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 128) /* XBARA1_OUT128 output assigned to FLEXIO1_TRIGGER_IN1 */
#define IMXRT_XBARA1_OUT_FLEXIO2_TRIGGER_IN0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 129) /* XBARA1_OUT129 output assigned to FLEXIO2_TRIGGER_IN0 */
#define IMXRT_XBARA1_OUT_FLEXIO2_TRIGGER_IN1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 130) /* XBARA1_OUT130 output assigned to FLEXIO2_TRIGGER_IN1 */
/* XBARB2 Mux inputs (I values) *******************************************************************************************************************/
#define IMXRT_XBARB2_IN_LOGIC_LOW IMXRT_XBARB2(XBAR_INPUT, 0) /* LOGIC_LOW output assigned to XBARB2_IN0 input. */
#define IMXRT_XBARB2_IN_LOGIC_HIGH IMXRT_XBARB2(XBAR_INPUT, 1) /* LOGIC_HIGH output assigned to XBARB2_IN1 input. */
#define IMXRT_XBARB2_IN_RESERVED2 IMXRT_XBARB2(XBAR_INPUT, 2) /* XBARB2_IN2 input is reserved. */
#define IMXRT_XBARB2_IN_RESERVED3 IMXRT_XBARB2(XBAR_INPUT, 3) /* XBARB2_IN3 input is reserved. */
#define IMXRT_XBARB2_IN_RESERVED4 IMXRT_XBARB2(XBAR_INPUT, 4) /* XBARB2_IN4 input is reserved. */
#define IMXRT_XBARB2_IN_RESERVED5 IMXRT_XBARB2(XBAR_INPUT, 5) /* XBARB2_IN5 input is reserved. */
#define IMXRT_XBARB2_IN_ACMP1_OUT IMXRT_XBARB2(XBAR_INPUT, 6) /* ACMP1_OUT output assigned to XBARB2_IN6 input. */
#define IMXRT_XBARB2_IN_ACMP2_OUT IMXRT_XBARB2(XBAR_INPUT, 7) /* ACMP2_OUT output assigned to XBARB2_IN7 input. */
#define IMXRT_XBARB2_IN_ACMP3_OUT IMXRT_XBARB2(XBAR_INPUT, 8) /* ACMP3_OUT output assigned to XBARB2_IN8 input. */
#define IMXRT_XBARB2_IN_ACMP4_OUT IMXRT_XBARB2(XBAR_INPUT, 9) /* ACMP4_OUT output assigned to XBARB2_IN9 input. */
#define IMXRT_XBARB2_IN_RESERVED10 IMXRT_XBARB2(XBAR_INPUT, 10) /* XBARB2_IN10 input is reserved. */
#define IMXRT_XBARB2_IN_RESERVED11 IMXRT_XBARB2(XBAR_INPUT, 11) /* XBARB2_IN11 input is reserved. */
#define IMXRT_XBARB2_IN_QTIMER3_TMR0_OUT IMXRT_XBARB2(XBAR_INPUT, 12) /* QTIMER3_TMR0_OUTPUT output assigned to XBARB2_IN12 input. */
#define IMXRT_XBARB2_IN_QTIMER3_TMR1_OUT IMXRT_XBARB2(XBAR_INPUT, 13) /* QTIMER3_TMR1_OUTPUT output assigned to XBARB2_IN13 input. */
#define IMXRT_XBARB2_IN_QTIMER3_TMR2_OUT IMXRT_XBARB2(XBAR_INPUT, 14) /* QTIMER3_TMR2_OUTPUT output assigned to XBARB2_IN14 input. */
#define IMXRT_XBARB2_IN_QTIMER3_TMR3_OUT IMXRT_XBARB2(XBAR_INPUT, 15) /* QTIMER3_TMR3_OUTPUT output assigned to XBARB2_IN15 input. */
#define IMXRT_XBARB2_IN_QTIMER4_TMR0_OUT IMXRT_XBARB2(XBAR_INPUT, 16) /* QTIMER4_TMR0_OUTPUT output assigned to XBARB2_IN16 input. */
#define IMXRT_XBARB2_IN_QTIMER4_TMR1_OUT IMXRT_XBARB2(XBAR_INPUT, 17) /* QTIMER4_TMR1_OUTPUT output assigned to XBARB2_IN17 input. */
#define IMXRT_XBARB2_IN_QTIMER4_TMR2_OUT IMXRT_XBARB2(XBAR_INPUT, 18) /* QTIMER4_TMR2_OUTPUT output assigned to XBARB2_IN18 input. */
#define IMXRT_XBARB2_IN_QTIMER4_TMR3_OUT IMXRT_XBARB2(XBAR_INPUT, 19) /* QTIMER4_TMR3_OUTPUT output assigned to XBARB2_IN19 input. */
#define IMXRT_XBARB2_IN_FLEXPWM1_PWM1_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 20) /* FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN20 input. */
#define IMXRT_XBARB2_IN_FLEXPWM1_PWM2_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 21) /* FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN21 input. */
#define IMXRT_XBARB2_IN_FLEXPWM1_PWM3_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 22) /* FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN22 input. */
#define IMXRT_XBARB2_IN_FLEXPWM1_PWM4_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 23) /* FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN23 input. */
#define IMXRT_XBARB2_IN_FLEXPWM2_PWM1_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 24) /* FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN24 input. */
#define IMXRT_XBARB2_IN_FLEXPWM2_PWM2_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 25) /* FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN25 input. */
#define IMXRT_XBARB2_IN_FLEXPWM2_PWM3_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 26) /* FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN26 input. */
#define IMXRT_XBARB2_IN_FLEXPWM2_PWM4_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 27) /* FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN27 input. */
#define IMXRT_XBARB2_IN_FLEXPWM3_PWM1_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 28) /* FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN28 input. */
#define IMXRT_XBARB2_IN_FLEXPWM3_PWM2_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 29) /* FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN29 input. */
#define IMXRT_XBARB2_IN_FLEXPWM3_PWM3_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 30) /* FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN30 input. */
#define IMXRT_XBARB2_IN_FLEXPWM3_PWM4_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 31) /* FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN31 input. */
#define IMXRT_XBARB2_IN_FLEXPWM4_PWM1_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 32) /* FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN32 input. */
#define IMXRT_XBARB2_IN_FLEXPWM4_PWM2_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 33) /* FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN33 input. */
#define IMXRT_XBARB2_IN_FLEXPWM4_PWM3_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 34) /* FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN34 input. */
#define IMXRT_XBARB2_IN_FLEXPWM4_PWM4_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 35) /* FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN35 input. */
#define IMXRT_XBARB2_IN_PIT_TRIGGER0 IMXRT_XBARB2(XBAR_INPUT, 36) /* PIT_TRIGGER0 output assigned to XBARB2_IN36 input. */
#define IMXRT_XBARB2_IN_PIT_TRIGGER1 IMXRT_XBARB2(XBAR_INPUT, 37) /* PIT_TRIGGER1 output assigned to XBARB2_IN37 input. */
#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO0 IMXRT_XBARB2(XBAR_INPUT, 38) /* ADC_ETC_XBAR0_COCO0 output assigned to XBARB2_IN38 input. */
#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO1 IMXRT_XBARB2(XBAR_INPUT, 39) /* ADC_ETC_XBAR0_COCO1 output assigned to XBARB2_IN39 input. */
#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO2 IMXRT_XBARB2(XBAR_INPUT, 40) /* ADC_ETC_XBAR0_COCO2 output assigned to XBARB2_IN40 input. */
#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO3 IMXRT_XBARB2(XBAR_INPUT, 41) /* ADC_ETC_XBAR0_COCO3 output assigned to XBARB2_IN41 input. */
#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO0 IMXRT_XBARB2(XBAR_INPUT, 42) /* ADC_ETC_XBAR1_COCO0 output assigned to XBARB2_IN42 input. */
#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO1 IMXRT_XBARB2(XBAR_INPUT, 43) /* ADC_ETC_XBAR1_COCO1 output assigned to XBARB2_IN43 input. */
#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO2 IMXRT_XBARB2(XBAR_INPUT, 44) /* ADC_ETC_XBAR1_COCO2 output assigned to XBARB2_IN44 input. */
#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO3 IMXRT_XBARB2(XBAR_INPUT, 45) /* ADC_ETC_XBAR1_COCO3 output assigned to XBARB2_IN45 input. */
#define IMXRT_XBARB2_IN_ENC1_POS_MATCH IMXRT_XBARB2(XBAR_INPUT, 46) /* ENC1_POS_MATCH output assigned to XBARB2_IN46 input. */
#define IMXRT_XBARB2_IN_ENC2_POS_MATCH IMXRT_XBARB2(XBAR_INPUT, 47) /* ENC2_POS_MATCH output assigned to XBARB2_IN47 input. */
#define IMXRT_XBARB2_IN_ENC3_POS_MATCH IMXRT_XBARB2(XBAR_INPUT, 48) /* ENC3_POS_MATCH output assigned to XBARB2_IN48 input. */
#define IMXRT_XBARB2_IN_ENC4_POS_MATCH IMXRT_XBARB2(XBAR_INPUT, 49) /* ENC4_POS_MATCH output assigned to XBARB2_IN49 input. */
#define IMXRT_XBARB2_IN_DMA_DONE0 IMXRT_XBARB2(XBAR_INPUT, 50) /* DMA_DONE0 output assigned to XBARB2_IN50 input. */
#define IMXRT_XBARB2_IN_DMA_DONE1 IMXRT_XBARB2(XBAR_INPUT, 51) /* DMA_DONE1 output assigned to XBARB2_IN51 input. */
#define IMXRT_XBARB2_IN_DMA_DONE2 IMXRT_XBARB2(XBAR_INPUT, 52) /* DMA_DONE2 output assigned to XBARB2_IN52 input. */
#define IMXRT_XBARB2_IN_DMA_DONE3 IMXRT_XBARB2(XBAR_INPUT, 53) /* DMA_DONE3 output assigned to XBARB2_IN53 input. */
#define IMXRT_XBARB2_IN_DMA_DONE4 IMXRT_XBARB2(XBAR_INPUT, 54) /* DMA_DONE4 output assigned to XBARB2_IN54 input. */
#define IMXRT_XBARB2_IN_DMA_DONE5 IMXRT_XBARB2(XBAR_INPUT, 55) /* DMA_DONE5 output assigned to XBARB2_IN55 input. */
#define IMXRT_XBARB2_IN_DMA_DONE6 IMXRT_XBARB2(XBAR_INPUT, 56) /* DMA_DONE6 output assigned to XBARB2_IN56 input. */
#define IMXRT_XBARB2_IN_DMA_DONE7 IMXRT_XBARB2(XBAR_INPUT, 57) /* DMA_DONE7 output assigned to XBARB2_IN57 input. */
/* XBARB2 Mux Output (M Muxes) ********************************************************************************************************************/
#define IMXRT_XBARB2_OUT_AOI1_IN00_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 0) /* XBARB2_OUT0 output assigned to AOI1_IN00 */
#define IMXRT_XBARB2_OUT_AOI1_IN01_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 1) /* XBARB2_OUT1 output assigned to AOI1_IN01 */
#define IMXRT_XBARB2_OUT_AOI1_IN02_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 2) /* XBARB2_OUT2 output assigned to AOI1_IN02 */
#define IMXRT_XBARB2_OUT_AOI1_IN03_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 3) /* XBARB2_OUT3 output assigned to AOI1_IN03 */
#define IMXRT_XBARB2_OUT_AOI1_IN04_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 4) /* XBARB2_OUT4 output assigned to AOI1_IN04 */
#define IMXRT_XBARB2_OUT_AOI1_IN05_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 5) /* XBARB2_OUT5 output assigned to AOI1_IN05 */
#define IMXRT_XBARB2_OUT_AOI1_IN06_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 6) /* XBARB2_OUT6 output assigned to AOI1_IN06 */
#define IMXRT_XBARB2_OUT_AOI1_IN07_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 7) /* XBARB2_OUT7 output assigned to AOI1_IN07 */
#define IMXRT_XBARB2_OUT_AOI1_IN08_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 8) /* XBARB2_OUT8 output assigned to AOI1_IN08 */
#define IMXRT_XBARB2_OUT_AOI1_IN09_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 9) /* XBARB2_OUT9 output assigned to AOI1_IN09 */
#define IMXRT_XBARB2_OUT_AOI1_IN10_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 10) /* XBARB2_OUT10 output assigned to AOI1_IN10 */
#define IMXRT_XBARB2_OUT_AOI1_IN11_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 11) /* XBARB2_OUT11 output assigned to AOI1_IN11 */
#define IMXRT_XBARB2_OUT_AOI1_IN12_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 12) /* XBARB2_OUT12 output assigned to AOI1_IN12 */
#define IMXRT_XBARB2_OUT_AOI1_IN13_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 13) /* XBARB2_OUT13 output assigned to AOI1_IN13 */
#define IMXRT_XBARB2_OUT_AOI1_IN14_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 14) /* XBARB2_OUT14 output assigned to AOI1_IN14 */
#define IMXRT_XBARB2_OUT_AOI1_IN15_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 15) /* XBARB2_OUT15 output assigned to AOI1_IN15 */
/* XBARB3 Mux inputs (I values) *******************************************************************************************************************/
#define IMXRT_XBARB3_IN_LOGIC_LOW IMXRT_XBARB3(XBAR_INPUT, 0) /* LOGIC_LOW output assigned to XBARB3_IN0 input. */
#define IMXRT_XBARB3_IN_LOGIC_HIGH IMXRT_XBARB3(XBAR_INPUT, 1) /* LOGIC_HIGH output assigned to XBARB3_IN1 input. */
#define IMXRT_XBARB3_IN_RESERVED2 IMXRT_XBARB3(XBAR_INPUT, 2) /* XBARB3_IN2 input is reserved. */
#define IMXRT_XBARB3_IN_RESERVED3 IMXRT_XBARB3(XBAR_INPUT, 3) /* XBARB3_IN3 input is reserved. */
#define IMXRT_XBARB3_IN_RESERVED4 IMXRT_XBARB3(XBAR_INPUT, 4) /* XBARB3_IN4 input is reserved. */
#define IMXRT_XBARB3_IN_RESERVED5 IMXRT_XBARB3(XBAR_INPUT, 5) /* XBARB3_IN5 input is reserved. */
#define IMXRT_XBARB3_IN_ACMP1_OUT IMXRT_XBARB3(XBAR_INPUT, 6) /* ACMP1_OUT output assigned to XBARB3_IN6 input. */
#define IMXRT_XBARB3_IN_ACMP2_OUT IMXRT_XBARB3(XBAR_INPUT, 7) /* ACMP2_OUT output assigned to XBARB3_IN7 input. */
#define IMXRT_XBARB3_IN_ACMP3_OUT IMXRT_XBARB3(XBAR_INPUT, 8) /* ACMP3_OUT output assigned to XBARB3_IN8 input. */
#define IMXRT_XBARB3_IN_ACMP4_OUT IMXRT_XBARB3(XBAR_INPUT, 9) /* ACMP4_OUT output assigned to XBARB3_IN9 input. */
#define IMXRT_XBARB3_IN_RESERVED10 IMXRT_XBARB3(XBAR_INPUT, 10) /* XBARB3_IN10 input is reserved. */
#define IMXRT_XBARB3_IN_RESERVED11 IMXRT_XBARB3(XBAR_INPUT, 11) /* XBARB3_IN11 input is reserved. */
#define IMXRT_XBARB3_IN_QTIMER3_TMR0_OUT IMXRT_XBARB3(XBAR_INPUT, 12) /* QTIMER3_TMR0_OUTPUT output assigned to XBARB3_IN12 input. */
#define IMXRT_XBARB3_IN_QTIMER3_TMR1_OUT IMXRT_XBARB3(XBAR_INPUT, 13) /* QTIMER3_TMR1_OUTPUT output assigned to XBARB3_IN13 input. */
#define IMXRT_XBARB3_IN_QTIMER3_TMR2_OUT IMXRT_XBARB3(XBAR_INPUT, 14) /* QTIMER3_TMR2_OUTPUT output assigned to XBARB3_IN14 input. */
#define IMXRT_XBARB3_IN_QTIMER3_TMR3_OUT IMXRT_XBARB3(XBAR_INPUT, 15) /* QTIMER3_TMR3_OUTPUT output assigned to XBARB3_IN15 input. */
#define IMXRT_XBARB3_IN_QTIMER4_TMR0_OUT IMXRT_XBARB3(XBAR_INPUT, 16) /* QTIMER4_TMR0_OUTPUT output assigned to XBARB3_IN16 input. */
#define IMXRT_XBARB3_IN_QTIMER4_TMR1_OUT IMXRT_XBARB3(XBAR_INPUT, 17) /* QTIMER4_TMR1_OUTPUT output assigned to XBARB3_IN17 input. */
#define IMXRT_XBARB3_IN_QTIMER4_TMR2_OUT IMXRT_XBARB3(XBAR_INPUT, 18) /* QTIMER4_TMR2_OUTPUT output assigned to XBARB3_IN18 input. */
#define IMXRT_XBARB3_IN_QTIMER4_TMR3_OUT IMXRT_XBARB3(XBAR_INPUT, 19) /* QTIMER4_TMR3_OUTPUT output assigned to XBARB3_IN19 input. */
#define IMXRT_XBARB3_IN_FLEXPWM1_PWM1_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 20) /* FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN20 input. */
#define IMXRT_XBARB3_IN_FLEXPWM1_PWM2_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 21) /* FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN21 input. */
#define IMXRT_XBARB3_IN_FLEXPWM1_PWM3_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 22) /* FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN22 input. */
#define IMXRT_XBARB3_IN_FLEXPWM1_PWM4_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 23) /* FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN23 input. */
#define IMXRT_XBARB3_IN_FLEXPWM2_PWM1_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 24) /* FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN24 input. */
#define IMXRT_XBARB3_IN_FLEXPWM2_PWM2_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 25) /* FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN25 input. */
#define IMXRT_XBARB3_IN_FLEXPWM2_PWM3_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 26) /* FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN26 input. */
#define IMXRT_XBARB3_IN_FLEXPWM2_PWM4_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 27) /* FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN27 input. */
#define IMXRT_XBARB3_IN_FLEXPWM3_PWM1_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 28) /* FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN28 input. */
#define IMXRT_XBARB3_IN_FLEXPWM3_PWM2_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 29) /* FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN29 input. */
#define IMXRT_XBARB3_IN_FLEXPWM3_PWM3_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 30) /* FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN30 input. */
#define IMXRT_XBARB3_IN_FLEXPWM3_PWM4_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 31) /* FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN31 input. */
#define IMXRT_XBARB3_IN_FLEXPWM4_PWM1_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 32) /* FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN32 input. */
#define IMXRT_XBARB3_IN_FLEXPWM4_PWM2_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 33) /* FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN33 input. */
#define IMXRT_XBARB3_IN_FLEXPWM4_PWM3_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 34) /* FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN34 input. */
#define IMXRT_XBARB3_IN_FLEXPWM4_PWM4_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 35) /* FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN35 input. */
#define IMXRT_XBARB3_IN_PIT_TRIGGER0 IMXRT_XBARB3(XBAR_INPUT, 36) /* PIT_TRIGGER0 output assigned to XBARB3_IN36 input. */
#define IMXRT_XBARB3_IN_PIT_TRIGGER1 IMXRT_XBARB3(XBAR_INPUT, 37) /* PIT_TRIGGER1 output assigned to XBARB3_IN37 input. */
#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO0 IMXRT_XBARB3(XBAR_INPUT, 38) /* ADC_ETC_XBAR0_COCO0 output assigned to XBARB3_IN38 input. */
#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO1 IMXRT_XBARB3(XBAR_INPUT, 39) /* ADC_ETC_XBAR0_COCO1 output assigned to XBARB3_IN39 input. */
#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO2 IMXRT_XBARB3(XBAR_INPUT, 40) /* ADC_ETC_XBAR0_COCO2 output assigned to XBARB3_IN40 input. */
#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO3 IMXRT_XBARB3(XBAR_INPUT, 41) /* ADC_ETC_XBAR0_COCO3 output assigned to XBARB3_IN41 input. */
#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO0 IMXRT_XBARB3(XBAR_INPUT, 42) /* ADC_ETC_XBAR1_COCO0 output assigned to XBARB3_IN42 input. */
#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO1 IMXRT_XBARB3(XBAR_INPUT, 43) /* ADC_ETC_XBAR1_COCO1 output assigned to XBARB3_IN43 input. */
#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO2 IMXRT_XBARB3(XBAR_INPUT, 44) /* ADC_ETC_XBAR1_COCO2 output assigned to XBARB3_IN44 input. */
#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO3 IMXRT_XBARB3(XBAR_INPUT, 45) /* ADC_ETC_XBAR1_COCO3 output assigned to XBARB3_IN45 input. */
#define IMXRT_XBARB3_IN_ENC1_POS_MATCH IMXRT_XBARB3(XBAR_INPUT, 46) /* ENC1_POS_MATCH output assigned to XBARB3_IN46 input. */
#define IMXRT_XBARB3_IN_ENC2_POS_MATCH IMXRT_XBARB3(XBAR_INPUT, 47) /* ENC2_POS_MATCH output assigned to XBARB3_IN47 input. */
#define IMXRT_XBARB3_IN_ENC3_POS_MATCH IMXRT_XBARB3(XBAR_INPUT, 48) /* ENC3_POS_MATCH output assigned to XBARB3_IN48 input. */
#define IMXRT_XBARB3_IN_ENC4_POS_MATCH IMXRT_XBARB3(XBAR_INPUT, 49) /* ENC4_POS_MATCH output assigned to XBARB3_IN49 input. */
#define IMXRT_XBARB3_IN_DMA_DONE0 IMXRT_XBARB3(XBAR_INPUT, 50) /* DMA_DONE0 output assigned to XBARB3_IN50 input. */
#define IMXRT_XBARB3_IN_DMA_DONE1 IMXRT_XBARB3(XBAR_INPUT, 51) /* DMA_DONE1 output assigned to XBARB3_IN51 input. */
#define IMXRT_XBARB3_IN_DMA_DONE2 IMXRT_XBARB3(XBAR_INPUT, 52) /* DMA_DONE2 output assigned to XBARB3_IN52 input. */
#define IMXRT_XBARB3_IN_DMA_DONE3 IMXRT_XBARB3(XBAR_INPUT, 53) /* DMA_DONE3 output assigned to XBARB3_IN53 input. */
#define IMXRT_XBARB3_IN_DMA_DONE4 IMXRT_XBARB3(XBAR_INPUT, 54) /* DMA_DONE4 output assigned to XBARB3_IN54 input. */
#define IMXRT_XBARB3_IN_DMA_DONE5 IMXRT_XBARB3(XBAR_INPUT, 55) /* DMA_DONE5 output assigned to XBARB3_IN55 input. */
#define IMXRT_XBARB3_IN_DMA_DONE6 IMXRT_XBARB3(XBAR_INPUT, 56) /* DMA_DONE6 output assigned to XBARB3_IN56 input. */
#define IMXRT_XBARB3_IN_DMA_DONE7 IMXRT_XBARB3(XBAR_INPUT, 57) /* DMA_DONE7 output assigned to XBARB3_IN57 input. */
/* XBARB3 Mux Output (M Muxes) ********************************************************************************************************************/
#define IMXRT_XBARB3_OUT_AOI2_IN00_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 0) /* XBARB3_OUT0 output assigned to AOI2_IN00 */
#define IMXRT_XBARB3_OUT_AOI2_IN01_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 1) /* XBARB3_OUT1 output assigned to AOI2_IN01 */
#define IMXRT_XBARB3_OUT_AOI2_IN02_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 2) /* XBARB3_OUT2 output assigned to AOI2_IN02 */
#define IMXRT_XBARB3_OUT_AOI2_IN03_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 3) /* XBARB3_OUT3 output assigned to AOI2_IN03 */
#define IMXRT_XBARB3_OUT_AOI2_IN04_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 4) /* XBARB3_OUT4 output assigned to AOI2_IN04 */
#define IMXRT_XBARB3_OUT_AOI2_IN05_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 5) /* XBARB3_OUT5 output assigned to AOI2_IN05 */
#define IMXRT_XBARB3_OUT_AOI2_IN06_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 6) /* XBARB3_OUT6 output assigned to AOI2_IN06 */
#define IMXRT_XBARB3_OUT_AOI2_IN07_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 7) /* XBARB3_OUT7 output assigned to AOI2_IN07 */
#define IMXRT_XBARB3_OUT_AOI2_IN08_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 8) /* XBARB3_OUT8 output assigned to AOI2_IN08 */
#define IMXRT_XBARB3_OUT_AOI2_IN09_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 9) /* XBARB3_OUT9 output assigned to AOI2_IN09 */
#define IMXRT_XBARB3_OUT_AOI2_IN10_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 10) /* XBARB3_OUT10 output assigned to AOI2_IN10 */
#define IMXRT_XBARB3_OUT_AOI2_IN11_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 11) /* XBARB3_OUT11 output assigned to AOI2_IN11 */
#define IMXRT_XBARB3_OUT_AOI2_IN12_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 12) /* XBARB3_OUT12 output assigned to AOI2_IN12 */
#define IMXRT_XBARB3_OUT_AOI2_IN13_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 13) /* XBARB3_OUT13 output assigned to AOI2_IN13 */
#define IMXRT_XBARB3_OUT_AOI2_IN14_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 14) /* XBARB3_OUT14 output assigned to AOI2_IN14 */
#define IMXRT_XBARB3_OUT_AOI2_IN15_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 15) /* XBARB3_OUT15 output assigned to AOI2_IN15 */
arch/arm/src/imxrt/chip/rt106x/imxrt106x_ccm.h
-1144
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arch/arm/src/imxrt/chip/rt106x/imxrt106x_dmamux.h
-174
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@@ -1,174 +0,0 @@
/************************************************************************************
* arch/arm/src/imxrt/chip/rt106x/imxrt106x_dmamux.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_DMAMUX_H
#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_DMAMUX_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Preprocessor Definitions
************************************************************************************/
/* Peripheral DMA request channels */
#define IMXRT_DMACHAN_FLEXIO1 0 /* FlexIO1 DMA 0/1, Async DMA 0/1 */
#define IMXRT_DMACHAN_FLEXIO2 1 /* FlexIO1 DMA 0/1, Async DMA 0/1 */
#define IMXRT_DMACHAN_LPUART1_TX 2 /* LPUART1 TX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPUART1_RX 3 /* LPUART1 RX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPUART3_TX 4 /* LPUART3 RX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPUART3_RX 5 /* LPUART3 RX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPUART5_TX 6 /* LPUART5 TX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPUART5_RX 7 /* LPUART5 RX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPUART7_TX 8 /* LPUART7 TX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPUART7_RX 9 /* LPUART7 RX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_CAN3 11 /* FLEXCAN3 DMA */
#define IMXRT_DMACHAN_CSI 12 /* CSI Write DMA */
#define IMXRT_DMACHAN_LPSPI1_RX 13 /* LPSPI1 RX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPSPI1_TX 14 /* LPSPI1 TX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPSPI3_RX 15 /* LPSPI3 RX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPSPI3_TX 16 /* LPSPI3 TX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPI2C1 17 /* LPI2C1 Master/Slave RX/TX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPI2C3 18 /* LPI2C3 Master/Slave RX/TX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_SAI1_RX 19 /* SAI1 RX FIFO DMA */
#define IMXRT_DMACHAN_SAI1_TX 20 /* SAI1 TX FIFO DMA */
#define IMXRT_DMACHAN_SAI2_RX 21 /* SAI2 RX FIFO DMA */
#define IMXRT_DMACHAN_SAI2_TX 22 /* SAI2 TX FIFO DMA */
#define IMXRT_DMACHAN_ADC_ETC 23 /* ADC ETC DMA */
#define IMXRT_DMACHAN_ADC1 24 /* ADC1 DMA */
#define IMXRT_DMACHAN_ACMP1 25 /* ACMP1 DMA */
#define IMXRT_DMACHAN_ACMP3 26 /* ACMP3 DMA */
#define IMXRT_DMACHAN_FLEXSPI_RX 28 /* FlexSPI RX FIFO DMA */
#define IMXRT_DMACHAN_FLEXSPI_TX 29 /* FlexSPI TX FIFO DMA */
#define IMXRT_DMACHAN_XBAR1_0 30 /* XBAR1 DMA 0 */
#define IMXRT_DMACHAN_XBAR1_1 31 /* XBAR1 DMA 1 */
#define IMXRT_DMACHAN_FLEXPWM1_RX0 32 /* FlexPWM1 RX sub-module0 capture */
#define IMXRT_DMACHAN_FLEXPWM1_RX1 33 /* FlexPWM1 RX sub-module1 capture */
#define IMXRT_DMACHAN_FLEXPWM1_RX2 34 /* FlexPWM1 RX sub-module2 capture */
#define IMXRT_DMACHAN_FLEXPWM1_RX3 35 /* FlexPWM1 RX sub-module3 capture */
#define IMXRT_DMACHAN_FLEXPWM1_TX0 36 /* FlexPWM1 TX sub-module0 value */
#define IMXRT_DMACHAN_FLEXPWM1_TX1 37 /* FlexPWM1 TX sub-module1 value */
#define IMXRT_DMACHAN_FLEXPWM1_TX2 38 /* FlexPWM1 TX sub-module2 value */
#define IMXRT_DMACHAN_FLEXPWM1_TX3 39 /* FlexPWM1 TX sub-module3 value */
#define IMXRT_DMACHAN_FLEXPWM3_RX0 40 /* FlexPWM3 RX sub-module0 capture */
#define IMXRT_DMACHAN_FLEXPWM3_RX1 41 /* FlexPWM3 RX sub-module1 capture */
#define IMXRT_DMACHAN_FLEXPWM3_RX2 42 /* FlexPWM3 RX sub-module2 capture */
#define IMXRT_DMACHAN_FLEXPWM3_RX3 43 /* FlexPWM3 RX sub-module3 capture */
#define IMXRT_DMACHAN_FLEXPWM3_TX0 44 /* FlexPWM3 TX sub-module0 value */
#define IMXRT_DMACHAN_FLEXPWM3_TX1 45 /* FlexPWM3 TX sub-module1 value */
#define IMXRT_DMACHAN_FLEXPWM3_TX2 46 /* FlexPWM3 TX sub-module2 value */
#define IMXRT_DMACHAN_FLEXPWM3_TX3 47 /* FlexPWM3 TX sub-module3 value */
#define IMXRT_DMACHAN_QTIMER1_RX0 48 /* QTimer1 RX capture timer 0 */
#define IMXRT_DMACHAN_QTIMER1_RX1 49 /* QTimer1 RX capture timer 1 */
#define IMXRT_DMACHAN_QTIMER1_RX2 50 /* QTimer1 RX capture timer 2 */
#define IMXRT_DMACHAN_QTIMER1_RX3 51 /* QTimer1 RX capture timer 3 */
#define IMXRT_DMACHAN_QTIMER1_TX0 52 /* QTimer1 TX cmpld1 timer 0 / cmld2 timer 1 */
#define IMXRT_DMACHAN_QTIMER1_TX1 53 /* QTimer1 TX cmpld1 timer 1 / cmld2 timer 0 */
#define IMXRT_DMACHAN_QTIMER1_TX2 54 /* QTimer1 TX cmpld1 timer 2 / cmld2 timer 3 */
#define IMXRT_DMACHAN_QTIMER1_TX3 55 /* QTimer1 TX cmpld1 timer 3 / cmld2 timer 2 */
#define IMXRT_DMACHAN_QTIMER3_RXTX0 56 /* QTimer1 RX capture timer 0 / TX cmpld1 timer 0 / cmld2 timer 1 */
#define IMXRT_DMACHAN_QTIMER3_RXTX1 57 /* QTimer1 RX capture timer 1 / TX cmpld1 timer 1 / cmld2 timer 0 */
#define IMXRT_DMACHAN_QTIMER3_RXTX2 58 /* QTimer1 RX capture timer 2 / TX cmpld1 timer 2 / cmld2 timer 3 */
#define IMXRT_DMACHAN_QTIMER3_RXTX3 59 /* QTimer1 RX capture timer 3 / TX cmpld1 timer 3 / cmld2 timer 2 */
#define IMXRT_DMACHAN_FLEXSPI2_RX 60 /* FlexSPI2 RX FIFO DMA */
#define IMXRT_DMACHAN_FLEXSPI2_TX 61 /* FlexSPI2 TX FIFO DMA */
#define IMXRT_DMACHAN_FLEXIO1_01 64 /* FlexIO1 DMA 0 / Async DMA 0 / DMA 1 / Async DMA 1 */
#define IMXRT_DMACHAN_FLEXIO2_23 65 /* FlexIO1 DMA 2 / Async DMA 2 / DMA 3 / Async DMA 3 */
#define IMXRT_DMACHAN_LPUART2_TX 66 /* LPUART2 TX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPUART2_RX 67 /* LPUART2 RX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPUART4_TX 68 /* LPUART4 TX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPUART4_RX 69 /* LPUART4 RX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPUART6_TX 70 /* LPUART6 TX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPUART6_RX 71 /* LPUART6 RX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPUART8_TX 72 /* LPUART8 TX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPUART8_RX 73 /* LPUART8 RX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_PXP 75 /* PXP DMA Event */
#define IMXRT_DMACHAN_LCDIF 76 /* LCDIF DMA Event */
#define IMXRT_DMACHAN_LPSPI2_RX 77 /* LPSPI2 RX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPSPI2_TX 78 /* LPSPI2 TX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPSPI4_RX 79 /* LPSPI4 RX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPSPI4_TX 80 /* LPSPI4 TX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPI2C2 81 /* LPI2C2 Master/Slave RX/TX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_LPI2C4 82 /* LPI2C4 Master/Slave RX/TX FIFO DMA / Async DMA */
#define IMXRT_DMACHAN_SAI3_RX 83 /* SAI3 RX FIFO DMA */
#define IMXRT_DMACHAN_SAI3_TX 84 /* SAI3 RX FIFO DMA */
#define IMXRT_DMACHAN_SPDIF_RX 85 /* SPDIF RX DMA */
#define IMXRT_DMACHAN_SPDIF_TX 86 /* SPDIF TX DMA */
#define IMXRT_DMACHAN_ADC2 88 /* ADC2 DMA */
#define IMXRT_DMACHAN_ACMP2 89 /* ACMP2 DMA */
#define IMXRT_DMACHAN_ACMP4 90 /* ACMP4 DMA */
#define IMXRT_DMACHAN_ENET_0 92 /* ENET Timer DMA 0 */
#define IMXRT_DMACHAN_ENET_1 93 /* ENET Timer DMA 1 */
#define IMXRT_DMACHAN_XBAR1_2 94 /* XBAR1 DMA 2 */
#define IMXRT_DMACHAN_XBAR1_3 95 /* XBAR1 DMA 3 */
#define IMXRT_DMACHAN_FLEXPWM2_RX0 96 /* FlexPWM2 RX sub-module0 capture */
#define IMXRT_DMACHAN_FLEXPWM2_RX1 97 /* FlexPWM2 RX sub-module1 capture */
#define IMXRT_DMACHAN_FLEXPWM2_RX2 98 /* FlexPWM2 RX sub-module2 capture */
#define IMXRT_DMACHAN_FLEXPWM2_RX3 99 /* FlexPWM2 RX sub-module3 capture */
#define IMXRT_DMACHAN_FLEXPWM2_TX0 100 /* FlexPWM2 TX sub-module0 value */
#define IMXRT_DMACHAN_FLEXPWM2_TX1 101 /* FlexPWM2 TX sub-module1 value */
#define IMXRT_DMACHAN_FLEXPWM2_TX2 102 /* FlexPWM2 TX sub-module2 value */
#define IMXRT_DMACHAN_FLEXPWM2_TX3 103 /* FlexPWM2 TX sub-module3 value */
#define IMXRT_DMACHAN_FLEXPWM4_RX0 104 /* FlexPWM4 RX sub-module0 capture */
#define IMXRT_DMACHAN_FLEXPWM4_RX1 105 /* FlexPWM4 RX sub-module1 capture */
#define IMXRT_DMACHAN_FLEXPWM4_RX2 106 /* FlexPWM4 RX sub-module2 capture */
#define IMXRT_DMACHAN_FLEXPWM4_RX3 107 /* FlexPWM4 RX sub-module3 capture */
#define IMXRT_DMACHAN_FLEXPWM4_TX0 108 /* FlexPWM4 TX sub-module0 value */
#define IMXRT_DMACHAN_FLEXPWM4_TX1 109 /* FlexPWM4 TX sub-module1 value */
#define IMXRT_DMACHAN_FLEXPWM4_TX2 110 /* FlexPWM4 TX sub-module2 value */
#define IMXRT_DMACHAN_FLEXPWM4_TX3 111 /* FlexPWM4 TX sub-module3 value */
#define IMXRT_DMACHAN_QTIMER2_RX0 112 /* QTimer2 RX capture timer 0 */
#define IMXRT_DMACHAN_QTIMER2_RX1 113 /* QTimer2 RX capture timer 1 */
#define IMXRT_DMACHAN_QTIMER2_RX2 114 /* QTimer2 RX capture timer 2 */
#define IMXRT_DMACHAN_QTIMER2_RX3 115 /* QTimer2 RX capture timer 3 */
#define IMXRT_DMACHAN_QTIMER2_TX0 116 /* QTimer2 TX cmpld1 timer 0 / cmld2 timer 1 */
#define IMXRT_DMACHAN_QTIMER2_TX1 117 /* QTimer2 TX cmpld1 timer 1 / cmld2 timer 0 */
#define IMXRT_DMACHAN_QTIMER2_TX2 118 /* QTimer2 TX cmpld1 timer 2 / cmld2 timer 3 */
#define IMXRT_DMACHAN_QTIMER2_TX3 119 /* QTimer2 TX cmpld1 timer 3 / cmld2 timer 2 */
#define IMXRT_DMACHAN_QTIMER4_RXTX0 120 /* QTimer4 RX capture timer 0 / TX cmpld1 timer 0 / cmld2 timer 1 */
#define IMXRT_DMACHAN_QTIMER4_RXTX1 121 /* QTimer4 RX capture timer 1 / TX cmpld1 timer 1 / cmld2 timer 0 */
#define IMXRT_DMACHAN_QTIMER4_RXTX2 122 /* QTimer4 RX capture timer 2 / TX cmpld1 timer 2 / cmld2 timer 3 */
#define IMXRT_DMACHAN_QTIMER4_RXTX3 123 /* QTimer4 RX capture timer 3 / TX cmpld1 timer 3 / cmld2 timer 2 */
#define IMXRT_DMACHAN_ENET2_0 124 /* ENET2 Timer DMA 0 */
#define IMXRT_DMACHAN_ENET2_1 125 /* ENET2 Timer DMA 1 */
#define IMXRT_DMA_NCHANNLES 128 /* Includes reserved channels */
#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_DMAMUX_H */
arch/arm/src/imxrt/chip/rt106x/imxrt106x_gpio.h
-175
View File
@@ -1,175 +0,0 @@
/********************************************************************************************
* arch/arm/src/imxrt/rt106x/imxrt106x_gpio.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_GPIO_H
#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_GPIO_H
/********************************************************************************************
* Included Files
********************************************************************************************/
#include <nuttx/config.h>
#include "chip/imxrt_memorymap.h"
/********************************************************************************************
* Pre-processor Definitions
********************************************************************************************/
/* Register offsets *************************************************************************/
#define IMXRT_GPIO_DR_OFFSET 0x0000 /* GPIO data register */
#define IMXRT_GPIO_GDIR_OFFSET 0x0004 /* GPIO direction register */
#define IMXRT_GPIO_PSR_OFFSET 0x0008 /* GPIO pad status register */
#define IMXRT_GPIO_ICR1_OFFSET 0x000c /* GPIO interrupt configuration register1 */
#define IMXRT_GPIO_ICR2_OFFSET 0x0010 /* GPIO interrupt configuration register2 */
#define IMXRT_GPIO_IMR_OFFSET 0x0014 /* GPIO interrupt mask register */
#define IMXRT_GPIO_ISR_OFFSET 0x0018 /* GPIO interrupt status register */
#define IMXRT_GPIO_EDGE_OFFSET 0x001c /* GPIO edge select register */
#define IMXRT_GPIO_SET_OFFSET 0x0084 /* GPIO data register SET */
#define IMXRT_GPIO_CLEAR_OFFSET 0x0088 /* GPIO data register CLEAR */
#define IMXRT_GPIO_TOGGLE_OFFSET 0x008c /* GPIO data register TOGGLE */
/* Register addresses ***********************************************************************/
#define IMXRT_GPIO1_DR (IMXRT_GPIO1_BASE + IMXRT_GPIO_DR_OFFSET)
#define IMXRT_GPIO1_GDIR (IMXRT_GPIO1_BASE + IMXRT_GPIO_GDIR_OFFSET)
#define IMXRT_GPIO1_PSR (IMXRT_GPIO1_BASE + IMXRT_GPIO_PSR_OFFSET)
#define IMXRT_GPIO1_ICR1 (IMXRT_GPIO1_BASE + IMXRT_GPIO_ICR1_OFFSET)
#define IMXRT_GPIO1_ICR2 (IMXRT_GPIO1_BASE + IMXRT_GPIO_ICR2_OFFSET)
#define IMXRT_GPIO1_IMR (IMXRT_GPIO1_BASE + IMXRT_GPIO_IMR_OFFSET)
#define IMXRT_GPIO1_ISR (IMXRT_GPIO1_BASE + IMXRT_GPIO_ISR_OFFSET)
#define IMXRT_GPIO1_EDGE (IMXRT_GPIO1_BASE + IMXRT_GPIO_EDGE_OFFSET)
#define IMXRT_GPIO1_SET (IMXRT_GPIO1_BASE + IMXRT_GPIO_SET_OFFSET)
#define IMXRT_GPIO1_CLEAR (IMXRT_GPIO1_BASE + IMXRT_GPIO_CLEAR_OFFSET)
#define IMXRT_GPIO1_TOGGLE (IMXRT_GPIO1_BASE + IMXRT_GPIO_TOGGLE_OFFSET)
#define IMXRT_GPIO2_DR (IMXRT_GPIO2_BASE + IMXRT_GPIO_DR_OFFSET)
#define IMXRT_GPIO2_GDIR (IMXRT_GPIO2_BASE + IMXRT_GPIO_GDIR_OFFSET)
#define IMXRT_GPIO2_PSR (IMXRT_GPIO2_BASE + IMXRT_GPIO_PSR_OFFSET)
#define IMXRT_GPIO2_ICR1 (IMXRT_GPIO2_BASE + IMXRT_GPIO_ICR1_OFFSET)
#define IMXRT_GPIO2_ICR2 (IMXRT_GPIO2_BASE + IMXRT_GPIO_ICR2_OFFSET)
#define IMXRT_GPIO2_IMR (IMXRT_GPIO2_BASE + IMXRT_GPIO_IMR_OFFSET)
#define IMXRT_GPIO2_ISR (IMXRT_GPIO2_BASE + IMXRT_GPIO_ISR_OFFSET)
#define IMXRT_GPIO2_EDGE (IMXRT_GPIO2_BASE + IMXRT_GPIO_EDGE_OFFSET)
#define IMXRT_GPIO2_SET (IMXRT_GPIO2_BASE + IMXRT_GPIO_SET_OFFSET)
#define IMXRT_GPIO2_CLEAR (IMXRT_GPIO2_BASE + IMXRT_GPIO_CLEAR_OFFSET)
#define IMXRT_GPIO2_TOGGLE (IMXRT_GPIO2_BASE + IMXRT_GPIO_TOGGLE_OFFSET)
#define IMXRT_GPIO3_DR (IMXRT_GPIO3_BASE + IMXRT_GPIO_DR_OFFSET)
#define IMXRT_GPIO3_GDIR (IMXRT_GPIO3_BASE + IMXRT_GPIO_GDIR_OFFSET)
#define IMXRT_GPIO3_PSR (IMXRT_GPIO3_BASE + IMXRT_GPIO_PSR_OFFSET)
#define IMXRT_GPIO3_ICR1 (IMXRT_GPIO3_BASE + IMXRT_GPIO_ICR1_OFFSET)
#define IMXRT_GPIO3_ICR2 (IMXRT_GPIO3_BASE + IMXRT_GPIO_ICR2_OFFSET)
#define IMXRT_GPIO3_IMR (IMXRT_GPIO3_BASE + IMXRT_GPIO_IMR_OFFSET)
#define IMXRT_GPIO3_ISR (IMXRT_GPIO3_BASE + IMXRT_GPIO_ISR_OFFSET)
#define IMXRT_GPIO3_EDGE (IMXRT_GPIO3_BASE + IMXRT_GPIO_EDGE_OFFSET)
#define IMXRT_GPIO3_SET (IMXRT_GPIO3_BASE + IMXRT_GPIO_SET_OFFSET)
#define IMXRT_GPIO3_CLEAR (IMXRT_GPIO3_BASE + IMXRT_GPIO_CLEAR_OFFSET)
#define IMXRT_GPIO3_TOGGLE (IMXRT_GPIO3_BASE + IMXRT_GPIO_TOGGLE_OFFSET)
#define IMXRT_GPIO4_DR (IMXRT_GPIO4_BASE + IMXRT_GPIO_DR_OFFSET)
#define IMXRT_GPIO4_GDIR (IMXRT_GPIO4_BASE + IMXRT_GPIO_GDIR_OFFSET)
#define IMXRT_GPIO4_PSR (IMXRT_GPIO4_BASE + IMXRT_GPIO_PSR_OFFSET)
#define IMXRT_GPIO4_ICR1 (IMXRT_GPIO4_BASE + IMXRT_GPIO_ICR1_OFFSET)
#define IMXRT_GPIO4_ICR2 (IMXRT_GPIO4_BASE + IMXRT_GPIO_ICR2_OFFSET)
#define IMXRT_GPIO4_IMR (IMXRT_GPIO4_BASE + IMXRT_GPIO_IMR_OFFSET)
#define IMXRT_GPIO4_ISR (IMXRT_GPIO4_BASE + IMXRT_GPIO_ISR_OFFSET)
#define IMXRT_GPIO4_EDGE (IMXRT_GPIO4_BASE + IMXRT_GPIO_EDGE_OFFSET)
#define IMXRT_GPIO4_SET (IMXRT_GPIO4_BASE + IMXRT_GPIO_SET_OFFSET)
#define IMXRT_GPIO4_CLEAR (IMXRT_GPIO4_BASE + IMXRT_GPIO_CLEAR_OFFSET)
#define IMXRT_GPIO4_TOGGLE (IMXRT_GPIO4_BASE + IMXRT_GPIO_TOGGLE_OFFSET)
#define IMXRT_GPIO5_DR (IMXRT_GPIO5_BASE + IMXRT_GPIO_DR_OFFSET)
#define IMXRT_GPIO5_GDIR (IMXRT_GPIO5_BASE + IMXRT_GPIO_GDIR_OFFSET)
#define IMXRT_GPIO5_PSR (IMXRT_GPIO5_BASE + IMXRT_GPIO_PSR_OFFSET)
#define IMXRT_GPIO5_ICR1 (IMXRT_GPIO5_BASE + IMXRT_GPIO_ICR1_OFFSET)
#define IMXRT_GPIO5_ICR2 (IMXRT_GPIO5_BASE + IMXRT_GPIO_ICR2_OFFSET)
#define IMXRT_GPIO5_IMR (IMXRT_GPIO5_BASE + IMXRT_GPIO_IMR_OFFSET)
#define IMXRT_GPIO5_ISR (IMXRT_GPIO5_BASE + IMXRT_GPIO_ISR_OFFSET)
#define IMXRT_GPIO5_EDGE (IMXRT_GPIO5_BASE + IMXRT_GPIO_EDGE_OFFSET)
#define IMXRT_GPIO5_SET (IMXRT_GPIO5_BASE + IMXRT_GPIO_SET_OFFSET)
#define IMXRT_GPIO5_CLEAR (IMXRT_GPIO5_BASE + IMXRT_GPIO_CLEAR_OFFSET)
#define IMXRT_GPIO5_TOGGLE (IMXRT_GPIO5_BASE + IMXRT_GPIO_TOGGLE_OFFSET)
# define IMXRT_GPIO6_DR (IMXRT_GPIO6_BASE + IMXRT_GPIO_DR_OFFSET)
# define IMXRT_GPIO6_GDIR (IMXRT_GPIO6_BASE + IMXRT_GPIO_GDIR_OFFSET)
# define IMXRT_GPIO6_PSR (IMXRT_GPIO6_BASE + IMXRT_GPIO_PSR_OFFSET)
# define IMXRT_GPIO6_ICR1 (IMXRT_GPIO6_BASE + IMXRT_GPIO_ICR1_OFFSET)
# define IMXRT_GPIO6_ICR2 (IMXRT_GPIO6_BASE + IMXRT_GPIO_ICR2_OFFSET)
# define IMXRT_GPIO6_IMR (IMXRT_GPIO6_BASE + IMXRT_GPIO_IMR_OFFSET)
# define IMXRT_GPIO6_ISR (IMXRT_GPIO6_BASE + IMXRT_GPIO_ISR_OFFSET)
# define IMXRT_GPIO6_EDGE (IMXRT_GPIO6_BASE + IMXRT_GPIO_EDGE_OFFSET)
# define IMXRT_GPIO6_SET (IMXRT_GPIO6_BASE + IMXRT_GPIO_SET_OFFSET)
# define IMXRT_GPIO6_CLEAR (IMXRT_GPIO6_BASE + IMXRT_GPIO_CLEAR_OFFSET)
# define IMXRT_GPIO6_TOGGLE (IMXRT_GPIO6_BASE + IMXRT_GPIO_TOGGLE_OFFSET)
# define IMXRT_GPIO7_DR (IMXRT_GPIO7_BASE + IMXRT_GPIO_DR_OFFSET)
# define IMXRT_GPIO7_GDIR (IMXRT_GPIO7_BASE + IMXRT_GPIO_GDIR_OFFSET)
# define IMXRT_GPIO7_PSR (IMXRT_GPIO7_BASE + IMXRT_GPIO_PSR_OFFSET)
# define IMXRT_GPIO7_ICR1 (IMXRT_GPIO7_BASE + IMXRT_GPIO_ICR1_OFFSET)
# define IMXRT_GPIO7_ICR2 (IMXRT_GPIO7_BASE + IMXRT_GPIO_ICR2_OFFSET)
# define IMXRT_GPIO7_IMR (IMXRT_GPIO7_BASE + IMXRT_GPIO_IMR_OFFSET)
# define IMXRT_GPIO7_ISR (IMXRT_GPIO7_BASE + IMXRT_GPIO_ISR_OFFSET)
# define IMXRT_GPIO7_EDGE (IMXRT_GPIO7_BASE + IMXRT_GPIO_EDGE_OFFSET)
# define IMXRT_GPIO7_SET (IMXRT_GPIO7_BASE + IMXRT_GPIO_SET_OFFSET)
# define IMXRT_GPIO7_CLEAR (IMXRT_GPIO7_BASE + IMXRT_GPIO_CLEAR_OFFSET)
# define IMXRT_GPIO7_TOGGLE (IMXRT_GPIO7_BASE + IMXRT_GPIO_TOGGLE_OFFSET)
# define IMXRT_GPIO8_DR (IMXRT_GPIO8_BASE + IMXRT_GPIO_DR_OFFSET)
# define IMXRT_GPIO8_GDIR (IMXRT_GPIO8_BASE + IMXRT_GPIO_GDIR_OFFSET)
# define IMXRT_GPIO8_PSR (IMXRT_GPIO8_BASE + IMXRT_GPIO_PSR_OFFSET)
# define IMXRT_GPIO8_ICR1 (IMXRT_GPIO8_BASE + IMXRT_GPIO_ICR1_OFFSET)
# define IMXRT_GPIO8_ICR2 (IMXRT_GPIO8_BASE + IMXRT_GPIO_ICR2_OFFSET)
# define IMXRT_GPIO8_IMR (IMXRT_GPIO8_BASE + IMXRT_GPIO_IMR_OFFSET)
# define IMXRT_GPIO8_ISR (IMXRT_GPIO8_BASE + IMXRT_GPIO_ISR_OFFSET)
# define IMXRT_GPIO8_EDGE (IMXRT_GPIO8_BASE + IMXRT_GPIO_EDGE_OFFSET)
# define IMXRT_GPIO8_SET (IMXRT_GPIO8_BASE + IMXRT_GPIO_SET_OFFSET)
# define IMXRT_GPIO8_CLEAR (IMXRT_GPIO8_BASE + IMXRT_GPIO_CLEAR_OFFSET)
# define IMXRT_GPIO8_TOGGLE (IMXRT_GPIO8_BASE + IMXRT_GPIO_TOGGLE_OFFSET)
# define IMXRT_GPIO9_DR (IMXRT_GPIO9_BASE + IMXRT_GPIO_DR_OFFSET)
# define IMXRT_GPIO9_GDIR (IMXRT_GPIO9_BASE + IMXRT_GPIO_GDIR_OFFSET)
# define IMXRT_GPIO9_PSR (IMXRT_GPIO9_BASE + IMXRT_GPIO_PSR_OFFSET)
# define IMXRT_GPIO9_ICR1 (IMXRT_GPIO9_BASE + IMXRT_GPIO_ICR1_OFFSET)
# define IMXRT_GPIO9_ICR2 (IMXRT_GPIO9_BASE + IMXRT_GPIO_ICR2_OFFSET)
# define IMXRT_GPIO9_IMR (IMXRT_GPIO9_BASE + IMXRT_GPIO_IMR_OFFSET)
# define IMXRT_GPIO9_ISR (IMXRT_GPIO9_BASE + IMXRT_GPIO_ISR_OFFSET)
# define IMXRT_GPIO9_EDGE (IMXRT_GPIO9_BASE + IMXRT_GPIO_EDGE_OFFSET)
# define IMXRT_GPIO9_SET (IMXRT_GPIO9_BASE + IMXRT_GPIO_SET_OFFSET)
# define IMXRT_GPIO9_CLEAR (IMXRT_GPIO9_BASE + IMXRT_GPIO_CLEAR_OFFSET)
# define IMXRT_GPIO9_TOGGLE (IMXRT_GPIO9_BASE + IMXRT_GPIO_TOGGLE_OFFSET)
#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_GPIO_H */
arch/arm/src/imxrt/chip/rt106x/imxrt106x_iomuxc.h
-2546
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arch/arm/src/imxrt/chip/rt106x/imxrt106x_memorymap.h
-301
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@@ -1,301 +0,0 @@
/************************************************************************************
* arch/arm/src/imxrt/chip/rt106x/imxrt106x_memorymap.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_MEMORYMAP_H
#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_MEMORYMAP_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* System memory map */
#define IMXRT_ITCM_BASE 0x00000000 /* 512KB ITCM */
/* 0x00080000 512KB ITCM Reserved */
/* 0x00100000 1MB ITCM Reserved */
#define IMXRT_ROMCP_BASE 0x00200000 /* 128KB ROMCP */
/* 0x00220000 384KB ROMCP Reserved */
/* 0x00280000 1536KB Reserved */
/* 0x00400000 124MB Reserved */
#define IMXRT_FLEXSPI_BASE 0x08000000 /* 128MB FlexSPI (Aliased) */
#define IMXRT_SEMCA_BASE 0x10000000 /* 256MB SEMC (Aliased) */
#define IMXRT_DTCM_BASE 0x20000000 /* 512KB DTCM */
/* 0x20080000 512KB DTCM Reserved */
/* 0x20100000 1MB Reserved */
#define IMXRT_OCRAM2_BASE 0x20200000 /* 512KB OCRAM2 */
#define IMXRT_OCRAM_BASE 0x20280000 /* 512KB OCRAM FlexRAM */
/* 0x20300000 512KB OCRAM Reserved */
/* 0x20400000 252MB Reserved */
/* 0x30000000 256MB Reserved */
#define IMXRT_AIPS1_BASE 0x40000000 /* 1MB AIPS-1 */
#define IMXRT_AIPS2_BASE 0x40100000 /* 1MB AIPS-2 */
#define IMXRT_AIPS3_BASE 0x40200000 /* 1MB AIPS-3 */
#define IMXRT_AIPS4_BASE 0x40300000 /* 1MB AIPS-4 */
/* 40400000 12MB Reserved */
#define IMXRT_MAINCNF_BASE 0x41000000 /* 1MB "main" configuration port */
#define IMXRT_MCNF_BASE 0x41100000 /* 1MB "m" configuration port */
/* 41200000 1MB Reserved for "per" GPV */
/* 41300000 1MB Reserved for "ems" GPV */
#define IMXRT_CPUCNF_BASE 0x41400000 /* 1MB "cpu" configuration port */
/* 0x41500000 1MB GPV Reserved */
/* 0x41600000 1MB GPV Reserved */
/* 0x41700000 1MB GPV Reserved */
/* 0x41800000 8MB Reserved */
#define IMXRT_AIPS5_BASE 0x42000000 /* 1MB AIPS-5 */
/* 0x42100000 31MB Reserved */
/* 0x44000000 64MB Reserved */
/* 0x48000000 384MB Reserved */
#define IMXRT_FLEXCIPHER_BASE 0x60000000 /* 256MB FlexSPI/ FlexSPI ciphertext */
#define IMXRT_FLEX2CIPHER_BASE 0x70000000 /* 240MB FlexSPI2/ FlexSPI ciphertext */
#define IMXRT_FLEXSPI2TX_BASE 0x7f000000 /* 4MB FlexSPI2 TX FIFO */
#define IMXRT_FLEXSPI2RX_BASE 0x7f400000 /* 4MB FlexSPI2 RX FIFO */
#define IMXRT_FLEXSPITX_BASE 0x7f800000 /* 4MB FlexSPI TX FIFO */
#define IMXRT_FLEXSPIRX_BASE 0x7fc00000 /* 4MB FlexSPI RX FIFO */
#define IMXRT_EXTMEM_BASE 0x80000000 /* 1.5GB SEMC external memories shared memory space */
#define IMXRT_CM7_BASE 0xe0000000 /* 1MB CM7 PPB */
/* 0xe0100000 511MB Reserved */
/* AIPS-1 memory map */
/* 0x40000000 256KB Reserved */
/* 0x40040000 240KB Reserved */
#define IMXRT_AIPS1CNF_BASE 0x4007c000 /* 6KB AIPS-1 Configuration */
#define IMXRT_DCDC_BASE 0x40080000 /* 16KB DCDC */
#define IMXRT_PIT_BASE 0x40084000 /* 16KB PIT */
/* 0x40088000 16KB Reserved */
/* 0x4008c000 16KB Reserved */
#define IMXRT_MTR_BASE 0x40090000 /* 16KB MTR */
#define IMXRT_ACMP_BASE 0x40094000 /* 16KB ACMP */
/* 0x40098000 16KB Reserved */
/* 0x4009c000 16KB Reserved */
/* 0x400a0000 16KB Reserved */
#define IMXRT_IOMUXCSNVSGPR_BASE 0x400a4000 /* 16KB IOMUXC_SNVS_GPR */
#define IMXRT_IOMUXCSNVS_BASE 0x400a8000 /* 16KB IOMUXC_SNVS */
#define IMXRT_IOMUXCGPR_BASE 0x400ac000 /* 16KB IOMUXC_GPR */
#define IMXRT_FLEXRAM_BASE 0x400b0000 /* 16KB CM7_MX6RT(FLEXRAM) */
#define IMXRT_EWM_BASE 0x400b4000 /* 16KB EWM */
#define IMXRT_WDOG1_BASE 0x400b8000 /* 16KB WDOG1 */
#define IMXRT_WDOG3_BASE 0x400bc000 /* 16KB WDOG3 */
#define IMXRT_GPIO5_BASE 0x400c0000 /* 16KB GPIO5 */
#define IMXRT_ADC1_BASE 0x400c4000 /* 16KB ADC1 */
#define IMXRT_ADC2_BASE 0x400c8000 /* 16KB ADC2 */
#define IMXRT_TRNG_BASE 0x400cc000 /* 16KB TRNG */
#define IMXRT_WDOG2_BASE 0x400d0000 /* 16KB WDOG2 */
#define IMXRT_SNVSHP_BASE 0x400d4000 /* 16KB SNVS_HP */
#define IMXRT_ANATOP_BASE 0x400d8000 /* 16KB ANATOP */
#define IMXRT_CSU_BASE 0x400dc000 /* 16KB CSU */
/* 0x400e0000 16KB Reserved */
/* 0x400e4000 16KB Reserved */
#define IMXRT_EDMA_BASE 0x400e8000 /* 16KB EDMA */
#define IMXRT_DMAMUX_BASE 0x400ec000 /* 16KB DMA_CH_MUX */
/* 400f0000 16KB Reserved */
#define IMXRT_GPC_BASE 0x400f4000 /* 16KB GPC */
#define IMXRT_SRC_BASE 0x400f8000 /* 16KB SRC */
#define IMXRT_CCM_BASE 0x400fc000 /* 16KB CCM */
/* AIPS-2 memory map */
/* 0x40100000 256KB Reserved */
/* 0x40140000 240KB Reserved */
#define IMXRT_AIPS2CNF_BASE 0x4017c000 /* 16KB AIPS-2 Configuration */
#define IMXRT_ROMCPC_BASE 0x40180000 /* 16KB ROMCP controller*/
#define IMXRT_LPUART1_BASE 0x40184000 /* 16KB LPUART1 */
#define IMXRT_LPUART2_BASE 0x40188000 /* 16KB LPUART2 */
#define IMXRT_LPUART3_BASE 0x4018c000 /* 16KB LPUART3 */
#define IMXRT_LPUART4_BASE 0x40190000 /* 16KB LPUART4 */
#define IMXRT_LPUART5_BASE 0x40194000 /* 16KB LPUART5 */
#define IMXRT_LPUART6_BASE 0x40198000 /* 16KB LPUART6 */
#define IMXRT_LPUART7_BASE 0x4019c000 /* 16KB LPUART7 */
#define IMXRT_LPUART8_BASE 0x401a0000 /* 16KB LPUART8 */
/* 0x401a4000 16KB Reserved */
/* 0x401a8000 16KB Reserved */
#define IMXRT_FLEXIO1_BASE 0x401ac000 /* 16KB FlexIO1 */
#define IMXRT_FLEXIO2_BASE 0x401b0000 /* 16KB FlexIO2 */
/* 0x401b4000 16KB Reserved */
#define IMXRT_GPIO1_BASE 0x401b8000 /* 16KB GPIO1 */
#define IMXRT_GPIO2_BASE 0x401bc000 /* 16KB GPIO2 */
#define IMXRT_GPIO3_BASE 0x401c0000 /* 16KB GPIO3 */
#define IMXRT_GPIO4_BASE 0x401c4000 /* 16KB GPIO4 */
/* 0x401c8000 16KB Reserved */
/* 0x401cc000 16KB Reserved */
#define IMXRT_CAN1_BASE 0x401d0000 /* 16KB CAN1 */
#define IMXRT_CAN2_BASE 0x401d4000 /* 16KB CAN2 */
#define IMXRT_CAN3_BASE 0x401d8000 /* 16KB CAN3 */
#define IMXRT_QTIMER1_BASE 0x401dc000 /* 16KB QTimer1 */
#define IMXRT_QTIMER2_BASE 0x401e0000 /* 16KB QTimer2 */
#define IMXRT_QTIMER3_BASE 0x401e4000 /* 16KB QTimer3 */
#define IMXRT_QTIMER4_BASE 0x401e8000 /* 16KB QTimer4 */
#define IMXRT_GPT1_BASE 0x401ec000 /* 16KB GPT1 */
#define IMXRT_GPT2_BASE 0x401f0000 /* 16KB GPT2 */
#define IMXRT_OCOTP_BASE 0x401f4000 /* 16KB OCOTP */
#define IMXRT_IOMUXC_BASE 0x401f8000 /* 16KB IOMUXC */
#define IMXRT_KPP_BASE 0x401fc000 /* 16KB KPP */
/* AIPS-3 memory map */
/* 0x40200000 256KB Reserved */
/* 0x40240000 240KB Reserved */
#define IMXRT_AIOS3CNF_BASE 0x4027c000 /* 16KB AIPS-3 Configuration */
/* 0x40280000 16KB Reserved */
/* 0x40284000 16KB Reserved */
/* 0x40288000 16KB Reserved */
/* 0x4028c000 16KB Reserved */
/* 0x40290000 16KB Reserved */
/* 0x40294000 16KB Reserved */
/* 0x40298000 16KB Reserved */
/* 0x4029c000 16KB Reserved */
/* 0x402a0000 16KB Reserved */
#define IMXRT_FLEXSPI2C_BASE 0x402a4000 /* 16KB FlexSPI2 */
#define IMXRT_FLEXSPIC_BASE 0x402a8000 /* 16KB FlexSPI */
/* 0x402ac000 16KB Reserved */
/* 0x402b0000 16KB Reserved */
#define IMXRT_PXP_BASE 0x402b4000 /* 16KB PXP */
#define IMXRT_LCDIF_BASE 0x402b8000 /* 16KB LCDIF */
#define IMXRT_CSI_BASE 0x402bc000 /* 16KB CSI */
#define IMXRT_USDHC1_BASE 0x402c0000 /* 16KB USDHC1 */
#define IMXRT_USDHC2_BASE 0x402c4000 /* 16KB USDHC2 */
/* 0x402c8000 16KB Reserved */
/* 0x402cc000 16KB Reserved */
/* 0x402d0000 16KB Reserved */
/* 0x402d4000 16KB Reserved */
#define IMXRT_ENET2_BASE 0x402d4000 /* 16KB ENET2 */
#define IMXRT_ENET_BASE 0x402d8000 /* 16KB ENET */
#define IMXRT_USBPL301_BASE 0x402dc000 /* 16KB USB(PL301) */
#define IMXRT_USB_BASE 0x402e0000 /* 16KB USB(USB) */
/* 0x402e4000 16KB Reserved */
/* 0x402e8000 16KB Reserved */
/* 0x402ec000 16KB Reserved */
#define IMXRT_SEMC_BASE 0x402f0000 /* 16KB SEMC */
/* 0x402f4000 16KB Reserved */
/* 0x402f8000 16KB Reserved */
#define IMXRT_DCP_BASE 0x402fc000 /* 16KB DCP */
/* AIPS-4 memory map */
/* 0x40300000 256KB Reserved */
/* 0x40340000 240KB Reserved */
#define IMXRT_AIPS4CNF_BASE 0x4037c000 /* 16KB AIPS-4 Configuration */
#define IMXRT_SPDIF_BASE 0x40380000 /* 16KB SPDIF */
#define IMXRT_SAI1_BASE 0x40384000 /* 16KB SAI1 */
#define IMXRT_SAI2_BASE 0x40388000 /* 16KB SAI2 */
#define IMXRT_SAI3_BASE 0x4038c000 /* 16KB SAI3 */
/* 0x40390000 16KB Reserved */
#define IMXRT_LPSPI1_BASE 0x40394000 /* 16KB LPSPI1 */
#define IMXRT_LPSPI2_BASE 0x40398000 /* 16KB LPSPI2 */
#define IMXRT_LPSPI3_BASE 0x4039c000 /* 16KB LPSPI3 */
#define IMXRT_LPSPI4_BASE 0x403a0000 /* 16KB LPSPI4 */
/* 0x403a4000 16KB Reserved */
/* 0x403a8000 16KB Reserved */
/* 0x403ac000 16KB Reserved */
#define IMXRT_ADCETC_BASE 0x403b0000 /* 16KB ADC_ETC */
#define IMXRT_AOI1_BASE 0x403b4000 /* 16KB AOI1 */
#define IMXRT_AOI2_BASE 0x403b8000 /* 16KB AOI2 */
#define IMXRT_XBAR1_BASE 0x403bc000 /* 16KB XBAR1 */
#define IMXRT_XBAR2_BASE 0x403c0000 /* 16KB XBAR2 */
#define IMXRT_XBAR3_BASE 0x403c4000 /* 16KB XBAR3 */
#define IMXRT_ENC1_BASE 0x403c8000 /* 16KB ENC1 */
#define IMXRT_ENC2_BASE 0x403cc000 /* 16KB ENC2 */
#define IMXRT_ENC3_BASE 0x403d0000 /* 16KB ENC3 */
#define IMXRT_ENC4_BASE 0x403d4000 /* 16KB ENC4 */
/* 0x403d8000 16KB Reserved */
#define IMXRT_FLEXPWM1_BASE 0x403dc000 /* 16KB FLEXPWM1 */
#define IMXRT_FLEXPWM2_BASE 0x403e0000 /* 16KB FLEXPWM2 */
#define IMXRT_FLEXPWM3_BASE 0x403e4000 /* 16KB FLEXPWM3 */
#define IMXRT_FLEXPWM4_BASE 0x403e8000 /* 16KB FLEXPWM4 */
#define IMXRT_BEE_BASE 0x403ec000 /* 16KB BEE */
#define IMXRT_LPI2C1_BASE 0x403f0000 /* 16KB */
#define IMXRT_LPI2C2_BASE 0x403f4000 /* 16KB LPI2C2 */
#define IMXRT_LPI2C3_BASE 0x403f8000 /* 16KB LPI2C3 */
#define IMXRT_LPI2C4_BASE 0x403fc000 /* 16KB LPI2C4 */
/* AIPS-5 memory map */
#define IMXRT_GPIO6_BASE 0x42000000 /* 16KB GPIO6 */
#define IMXRT_GPIO7_BASE 0x42004000 /* 16KB GPIO7 */
#define IMXRT_GPIO8_BASE 0x42008000 /* 16KB GPIO8 */
#define IMXRT_GPIO9_BASE 0x4200c000 /* 16KB GPIO9 */
/* 0x42010000 16KB Reserved */
/* 0x42014000 16KB Reserved */
/* 0x42018000 16KB Reserved */
/* 0x4201c000 16KB Reserved */
#define IMXRT_FLEXIO3_BASE 0x42020000 /* 16KB FlexIO3 */
/* 0x42024000 16KB Reserved */
/* 0x42028000 16KB Reserved */
/* 0x4202c000 16KB Reserved */
/* 0x42030000 16KB Reserved */
/* 0x42034000 16KB Reserved */
/* 0x42038000 16KB Reserved */
/* 0x4203c000 16KB Reserved */
/* 0x42040000 16KB Reserved */
/* 0x42044000 16KB Reserved */
/* 0x42048000 16KB Reserved */
/* 0x4204c000 16KB Reserved */
/* 0x42050000 16KB Reserved */
/* 0x42054000 16KB Reserved */
/* 0x42058000 16KB Reserved */
/* 0x4205c000 16KB Reserved */
/* 0x42060000 16KB Reserved */
/* 0x42064000 16KB Reserved */
/* 0x42068000 16KB Reserved */
/* 0x4206c000 16KB Reserved */
/* 0x42070000 16KB Reserved */
/* 0x42074000 16KB Reserved */
/* 0x42078000 16KB Reserved */
/* 0x4207c000 16KB Reserved */
/* 0x42080000 512KB Reserved Off Platform */
/* PPB memory map */
#define IMXRT_TPIU_BASE 0xe0040000 /* 4KB TPIU */
#define IMXRT_ETM_BASE 0xe0041000 /* 4KB ETM */
#define IMXRT_CTI_BASE 0xe0042000 /* 4KB CTI */
#define IMXRT_TSGEN_BASE 0xe0043000 /* 4KB TSGEN */
#define IMXRT_PPBRES_BASE 0xe0044000 /* 4KB PPB RES */
/* 0xe0045000 236KB PPB Reserved */
#define IMXRT_MCM_BASE 0xe0080000 /* 4KB MCM */
/* 0xe0081000 444KB PPB Reserved */
/* 0xe00f0000 52KB PPB Reserved */
#define IMXRT_SYSROM_BASE 0xe00fd000 /* 4KB SYS ROM */
#define IMXRT_PROCROM_BASE 0xe00fe000 /* 4KB Processor ROM */
#define IMXRT_PPBROM_BASE 0xe00ff000 /* 4KB PPB ROM */
#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_MEMORYMAP_H */
arch/arm/src/imxrt/chip/rt106x/imxrt106x_pinmux.h
-1095
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arch/arm/src/imxrt/chip/rt106x/imxrt106x_xbar.h
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/* XBAR Defines for IMXRT1060 */
/* XBARA1 Mux inputs (I values) ***************************************************************************************************************************************/
#define IMXRT_XBARA1_IN_LOGIC_LOW IMXRT_XBARA1(XBAR_INPUT, 0) /* LOGIC_LOW output assigned to XBARA1_IN0 input. */
#define IMXRT_XBARA1_IN_LOGIC_HIGH IMXRT_XBARA1(XBAR_INPUT, 1) /* LOGIC_HIGH output assigned to XBARA1_IN1 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN02 IMXRT_XBARA1(XBAR_INPUT, 2) /* IOMUX_XBAR_IN02 output assigned to XBARA1_IN2 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN03 IMXRT_XBARA1(XBAR_INPUT, 3) /* IOMUX_XBAR_IN03 output assigned to XBARA1_IN3 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO04 IMXRT_XBARA1(XBAR_INPUT, 4) /* IOMUX_XBAR_INOUT04 output assigned to XBARA1_IN4 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO05 IMXRT_XBARA1(XBAR_INPUT, 5) /* IOMUX_XBAR_INOUT05 output assigned to XBARA1_IN5 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO06 IMXRT_XBARA1(XBAR_INPUT, 6) /* IOMUX_XBAR_INOUT06 output assigned to XBARA1_IN6 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO07 IMXRT_XBARA1(XBAR_INPUT, 7) /* IOMUX_XBAR_INOUT07 output assigned to XBARA1_IN7 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO08 IMXRT_XBARA1(XBAR_INPUT, 8) /* IOMUX_XBAR_INOUT08 output assigned to XBARA1_IN8 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO09 IMXRT_XBARA1(XBAR_INPUT, 9) /* IOMUX_XBAR_INOUT09 output assigned to XBARA1_IN9 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO10 IMXRT_XBARA1(XBAR_INPUT, 10) /* IOMUX_XBAR_INOUT10 output assigned to XBARA1_IN10 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO11 IMXRT_XBARA1(XBAR_INPUT, 11) /* IOMUX_XBAR_INOUT11 output assigned to XBARA1_IN11 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO12 IMXRT_XBARA1(XBAR_INPUT, 12) /* IOMUX_XBAR_INOUT12 output assigned to XBARA1_IN12 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO13 IMXRT_XBARA1(XBAR_INPUT, 13) /* IOMUX_XBAR_INOUT13 output assigned to XBARA1_IN13 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO14 IMXRT_XBARA1(XBAR_INPUT, 14) /* IOMUX_XBAR_INOUT14 output assigned to XBARA1_IN14 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO15 IMXRT_XBARA1(XBAR_INPUT, 15) /* IOMUX_XBAR_INOUT15 output assigned to XBARA1_IN15 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO16 IMXRT_XBARA1(XBAR_INPUT, 16) /* IOMUX_XBAR_INOUT16 output assigned to XBARA1_IN16 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO17 IMXRT_XBARA1(XBAR_INPUT, 17) /* IOMUX_XBAR_INOUT17 output assigned to XBARA1_IN17 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO18 IMXRT_XBARA1(XBAR_INPUT, 18) /* IOMUX_XBAR_INOUT18 output assigned to XBARA1_IN18 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO19 IMXRT_XBARA1(XBAR_INPUT, 19) /* IOMUX_XBAR_INOUT19 output assigned to XBARA1_IN19 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN20 IMXRT_XBARA1(XBAR_INPUT, 20) /* IOMUX_XBAR_IN20 output assigned to XBARA1_IN20 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN21 IMXRT_XBARA1(XBAR_INPUT, 21) /* IOMUX_XBAR_IN21 output assigned to XBARA1_IN21 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN22 IMXRT_XBARA1(XBAR_INPUT, 22) /* IOMUX_XBAR_IN22 output assigned to XBARA1_IN22 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN23 IMXRT_XBARA1(XBAR_INPUT, 23) /* IOMUX_XBAR_IN23 output assigned to XBARA1_IN23 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN24 IMXRT_XBARA1(XBAR_INPUT, 24) /* IOMUX_XBAR_IN24 output assigned to XBARA1_IN24 input. */
#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN25 IMXRT_XBARA1(XBAR_INPUT, 25) /* IOMUX_XBAR_IN25 output assigned to XBARA1_IN25 input. */
#define IMXRT_XBARA1_IN_ACMP1_OUT IMXRT_XBARA1(XBAR_INPUT, 26) /* ACMP1_OUT output assigned to XBARA1_IN26 input. */
#define IMXRT_XBARA1_IN_ACMP2_OUT IMXRT_XBARA1(XBAR_INPUT, 27) /* ACMP2_OUT output assigned to XBARA1_IN27 input. */
#define IMXRT_XBARA1_IN_ACMP3_OUT IMXRT_XBARA1(XBAR_INPUT, 28) /* ACMP3_OUT output assigned to XBARA1_IN28 input. */
#define IMXRT_XBARA1_IN_ACMP4_OUT IMXRT_XBARA1(XBAR_INPUT, 29) /* ACMP4_OUT output assigned to XBARA1_IN29 input. */
#define IMXRT_XBARA1_IN_RESERVED30 IMXRT_XBARA1(XBAR_INPUT, 30) /* XBARA1_IN30 input is reserved. */
#define IMXRT_XBARA1_IN_RESERVED31 IMXRT_XBARA1(XBAR_INPUT, 31) /* XBARA1_IN31 input is reserved. */
#define IMXRT_XBARA1_IN_QTIMER3_TMR0_OUT IMXRT_XBARA1(XBAR_INPUT, 32) /* QTIMER3_TMR0_OUTPUT output assigned to XBARA1_IN32 input. */
#define IMXRT_XBARA1_IN_QTIMER3_TMR1_OUT IMXRT_XBARA1(XBAR_INPUT, 33) /* QTIMER3_TMR1_OUTPUT output assigned to XBARA1_IN33 input. */
#define IMXRT_XBARA1_IN_QTIMER3_TMR2_OUT IMXRT_XBARA1(XBAR_INPUT, 34) /* QTIMER3_TMR2_OUTPUT output assigned to XBARA1_IN34 input. */
#define IMXRT_XBARA1_IN_QTIMER3_TMR3_OUT IMXRT_XBARA1(XBAR_INPUT, 35) /* QTIMER3_TMR3_OUTPUT output assigned to XBARA1_IN35 input. */
#define IMXRT_XBARA1_IN_QTIMER4_TMR0_OUT IMXRT_XBARA1(XBAR_INPUT, 36) /* QTIMER4_TMR0_OUTPUT output assigned to XBARA1_IN36 input. */
#define IMXRT_XBARA1_IN_QTIMER4_TMR1_OUT IMXRT_XBARA1(XBAR_INPUT, 37) /* QTIMER4_TMR1_OUTPUT output assigned to XBARA1_IN37 input. */
#define IMXRT_XBARA1_IN_QTIMER4_TMR2_OUT IMXRT_XBARA1(XBAR_INPUT, 38) /* QTIMER4_TMR2_OUTPUT output assigned to XBARA1_IN38 input. */
#define IMXRT_XBARA1_IN_QTIMER4_TMR3_OUT IMXRT_XBARA1(XBAR_INPUT, 39) /* QTIMER4_TMR3_OUTPUT output assigned to XBARA1_IN39 input. */
#define IMXRT_XBARA1_IN_FLEXPWM1_PWM1_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 40) /* FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN40 input. */
#define IMXRT_XBARA1_IN_FLEXPWM1_PWM2_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 41) /* FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN41 input. */
#define IMXRT_XBARA1_IN_FLEXPWM1_PWM3_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 42) /* FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN42 input. */
#define IMXRT_XBARA1_IN_FLEXPWM1_PWM4_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 43) /* FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN43 input. */
#define IMXRT_XBARA1_IN_FLEXPWM2_PWM1_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 44) /* FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN44 input. */
#define IMXRT_XBARA1_IN_FLEXPWM2_PWM2_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 45) /* FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN45 input. */
#define IMXRT_XBARA1_IN_FLEXPWM2_PWM3_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 46) /* FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN46 input. */
#define IMXRT_XBARA1_IN_FLEXPWM2_PWM4_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 47) /* FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN47 input. */
#define IMXRT_XBARA1_IN_FLEXPWM3_PWM1_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 48) /* FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN48 input. */
#define IMXRT_XBARA1_IN_FLEXPWM3_PWM2_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 49) /* FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN49 input. */
#define IMXRT_XBARA1_IN_FLEXPWM3_PWM3_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 50) /* FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN50 input. */
#define IMXRT_XBARA1_IN_FLEXPWM3_PWM4_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 51) /* FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN51 input. */
#define IMXRT_XBARA1_IN_FLEXPWM4_PWM1_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 52) /* FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN52 input. */
#define IMXRT_XBARA1_IN_FLEXPWM4_PWM2_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 53) /* FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN53 input. */
#define IMXRT_XBARA1_IN_FLEXPWM4_PWM3_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 54) /* FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN54 input. */
#define IMXRT_XBARA1_IN_FLEXPWM4_PWM4_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 55) /* FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN55 input. */
#define IMXRT_XBARA1_IN_PIT_TRIGGER0 IMXRT_XBARA1(XBAR_INPUT, 56) /* PIT_TRIGGER0 output assigned to XBARA1_IN56 input. */
#define IMXRT_XBARA1_IN_PIT_TRIGGER1 IMXRT_XBARA1(XBAR_INPUT, 57) /* PIT_TRIGGER1 output assigned to XBARA1_IN57 input. */
#define IMXRT_XBARA1_IN_PIT_TRIGGER2 IMXRT_XBARA1(XBAR_INPUT, 58) /* PIT_TRIGGER2 output assigned to XBARA1_IN58 input. */
#define IMXRT_XBARA1_IN_PIT_TRIGGER3 IMXRT_XBARA1(XBAR_INPUT, 59) /* PIT_TRIGGER3 output assigned to XBARA1_IN59 input. */
#define IMXRT_XBARA1_IN_ENC1_POS_MATCH IMXRT_XBARA1(XBAR_INPUT, 60) /* ENC1_POS_MATCH output assigned to XBARA1_IN60 input. */
#define IMXRT_XBARA1_IN_ENC2_POS_MATCH IMXRT_XBARA1(XBAR_INPUT, 61) /* ENC2_POS_MATCH output assigned to XBARA1_IN61 input. */
#define IMXRT_XBARA1_IN_ENC3_POS_MATCH IMXRT_XBARA1(XBAR_INPUT, 62) /* ENC3_POS_MATCH output assigned to XBARA1_IN62 input. */
#define IMXRT_XBARA1_IN_ENC4_POS_MATCH IMXRT_XBARA1(XBAR_INPUT, 63) /* ENC4_POS_MATCH output assigned to XBARA1_IN63 input. */
#define IMXRT_XBARA1_IN_DMA_DONE0 IMXRT_XBARA1(XBAR_INPUT, 64) /* DMA_DONE0 output assigned to XBARA1_IN64 input. */
#define IMXRT_XBARA1_IN_DMA_DONE1 IMXRT_XBARA1(XBAR_INPUT, 65) /* DMA_DONE1 output assigned to XBARA1_IN65 input. */
#define IMXRT_XBARA1_IN_DMA_DONE2 IMXRT_XBARA1(XBAR_INPUT, 66) /* DMA_DONE2 output assigned to XBARA1_IN66 input. */
#define IMXRT_XBARA1_IN_DMA_DONE3 IMXRT_XBARA1(XBAR_INPUT, 67) /* DMA_DONE3 output assigned to XBARA1_IN67 input. */
#define IMXRT_XBARA1_IN_DMA_DONE4 IMXRT_XBARA1(XBAR_INPUT, 68) /* DMA_DONE4 output assigned to XBARA1_IN68 input. */
#define IMXRT_XBARA1_IN_DMA_DONE5 IMXRT_XBARA1(XBAR_INPUT, 69) /* DMA_DONE5 output assigned to XBARA1_IN69 input. */
#define IMXRT_XBARA1_IN_DMA_DONE6 IMXRT_XBARA1(XBAR_INPUT, 70) /* DMA_DONE6 output assigned to XBARA1_IN70 input. */
#define IMXRT_XBARA1_IN_DMA_DONE7 IMXRT_XBARA1(XBAR_INPUT, 71) /* DMA_DONE7 output assigned to XBARA1_IN71 input. */
#define IMXRT_XBARA1_IN_AOI1_OUT0 IMXRT_XBARA1(XBAR_INPUT, 72) /* AOI1_OUT0 output assigned to XBARA1_IN72 input. */
#define IMXRT_XBARA1_IN_AOI1_OUT1 IMXRT_XBARA1(XBAR_INPUT, 73) /* AOI1_OUT1 output assigned to XBARA1_IN73 input. */
#define IMXRT_XBARA1_IN_AOI1_OUT2 IMXRT_XBARA1(XBAR_INPUT, 74) /* AOI1_OUT2 output assigned to XBARA1_IN74 input. */
#define IMXRT_XBARA1_IN_AOI1_OUT3 IMXRT_XBARA1(XBAR_INPUT, 75) /* AOI1_OUT3 output assigned to XBARA1_IN75 input. */
#define IMXRT_XBARA1_IN_AOI2_OUT0 IMXRT_XBARA1(XBAR_INPUT, 76) /* AOI2_OUT0 output assigned to XBARA1_IN76 input. */
#define IMXRT_XBARA1_IN_AOI2_OUT1 IMXRT_XBARA1(XBAR_INPUT, 77) /* AOI2_OUT1 output assigned to XBARA1_IN77 input. */
#define IMXRT_XBARA1_IN_AOI2_OUT2 IMXRT_XBARA1(XBAR_INPUT, 78) /* AOI2_OUT2 output assigned to XBARA1_IN78 input. */
#define IMXRT_XBARA1_IN_AOI2_OUT3 IMXRT_XBARA1(XBAR_INPUT, 79) /* AOI2_OUT3 output assigned to XBARA1_IN79 input. */
#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO0 IMXRT_XBARA1(XBAR_INPUT, 80) /* ADC_ETC_XBAR0_COCO0 output assigned to XBARA1_IN80 input. */
#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO1 IMXRT_XBARA1(XBAR_INPUT, 81) /* ADC_ETC_XBAR0_COCO1 output assigned to XBARA1_IN81 input. */
#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO2 IMXRT_XBARA1(XBAR_INPUT, 82) /* ADC_ETC_XBAR0_COCO2 output assigned to XBARA1_IN82 input. */
#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO3 IMXRT_XBARA1(XBAR_INPUT, 83) /* ADC_ETC_XBAR0_COCO3 output assigned to XBARA1_IN83 input. */
#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO0 IMXRT_XBARA1(XBAR_INPUT, 84) /* ADC_ETC_XBAR1_COCO0 output assigned to XBARA1_IN84 input. */
#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO1 IMXRT_XBARA1(XBAR_INPUT, 85) /* ADC_ETC_XBAR1_COCO1 output assigned to XBARA1_IN85 input. */
#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO2 IMXRT_XBARA1(XBAR_INPUT, 86) /* ADC_ETC_XBAR1_COCO2 output assigned to XBARA1_IN86 input. */
#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO3 IMXRT_XBARA1(XBAR_INPUT, 87) /* ADC_ETC_XBAR1_COCO3 output assigned to XBARA1_IN87 input. */
/* XBARA1 Mux Output (M Muxes) ***************************************************************************************************************/
#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ30_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 0) /* XBARA1_OUT0 output assigned to DMA_CH_MUX_REQ30 */
#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ31_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 1) /* XBARA1_OUT1 output assigned to DMA_CH_MUX_REQ31 */
#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ94_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 2) /* XBARA1_OUT2 output assigned to DMA_CH_MUX_REQ94 */
#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ95_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 3) /* XBARA1_OUT3 output assigned to DMA_CH_MUX_REQ95 */
#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO04_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 4) /* XBARA1_OUT4 output assigned to IOMUX_XBAR_INOUT04 */
#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO05_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 5) /* XBARA1_OUT5 output assigned to IOMUX_XBAR_INOUT05 */
#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO06_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 6) /* XBARA1_OUT6 output assigned to IOMUX_XBAR_INOUT06 */
#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO07_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 7) /* XBARA1_OUT7 output assigned to IOMUX_XBAR_INOUT07 */
#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO08_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 8) /* XBARA1_OUT8 output assigned to IOMUX_XBAR_INOUT08 */
#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO09_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 9) /* XBARA1_OUT9 output assigned to IOMUX_XBAR_INOUT09 */
#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO10_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 10) /* XBARA1_OUT10 output assigned to IOMUX_XBAR_INOUT10 */
#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO11_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 11) /* XBARA1_OUT11 output assigned to IOMUX_XBAR_INOUT11 */
#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO12_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 12) /* XBARA1_OUT12 output assigned to IOMUX_XBAR_INOUT12 */
#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO13_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 13) /* XBARA1_OUT13 output assigned to IOMUX_XBAR_INOUT13 */
#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO14_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 14) /* XBARA1_OUT14 output assigned to IOMUX_XBAR_INOUT14 */
#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO15_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 15) /* XBARA1_OUT15 output assigned to IOMUX_XBAR_INOUT15 */
#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO16_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 16) /* XBARA1_OUT16 output assigned to IOMUX_XBAR_INOUT16 */
#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO17_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 17) /* XBARA1_OUT17 output assigned to IOMUX_XBAR_INOUT17 */
#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO18_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 18) /* XBARA1_OUT18 output assigned to IOMUX_XBAR_INOUT18 */
#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO19_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 19) /* XBARA1_OUT19 output assigned to IOMUX_XBAR_INOUT19 */
#define IMXRT_XBARA1_OUT_ACMP1_SAMPLE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 20) /* XBARA1_OUT20 output assigned to ACMP1_SAMPLE */
#define IMXRT_XBARA1_OUT_ACMP2_SAMPLE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 21) /* XBARA1_OUT21 output assigned to ACMP2_SAMPLE */
#define IMXRT_XBARA1_OUT_ACMP3_SAMPLE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 22) /* XBARA1_OUT22 output assigned to ACMP3_SAMPLE */
#define IMXRT_XBARA1_OUT_ACMP4_SAMPLE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 23) /* XBARA1_OUT23 output assigned to ACMP4_SAMPLE */
#define IMXRT_XBARA1_OUT_RESERVED24_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 24) /* XBARA1_OUT24 output is reserved. */
#define IMXRT_XBARA1_OUT_RESERVED25_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 25) /* XBARA1_OUT25 output is reserved. */
#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 26) /* XBARA1_OUT26 output assigned to FLEXPWM1_EXTA0 */
#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 27) /* XBARA1_OUT27 output assigned to FLEXPWM1_EXTA1 */
#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 28) /* XBARA1_OUT28 output assigned to FLEXPWM1_EXTA2 */
#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 29) /* XBARA1_OUT29 output assigned to FLEXPWM1_EXTA3 */
#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 30) /* XBARA1_OUT30 output assigned to FLEXPWM1_EXT_SYNC0 */
#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 31) /* XBARA1_OUT31 output assigned to FLEXPWM1_EXT_SYNC1 */
#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 32) /* XBARA1_OUT32 output assigned to FLEXPWM1_EXT_SYNC2 */
#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 33) /* XBARA1_OUT33 output assigned to FLEXPWM1_EXT_SYNC3 */
#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_CLK_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 34) /* XBARA1_OUT34 output assigned to FLEXPWM1_EXT_CLK */
#define IMXRT_XBARA1_OUT_FLEXPWM1_FAULT0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 35) /* XBARA1_OUT35 output assigned to FLEXPWM1_FAULT0 */
#define IMXRT_XBARA1_OUT_FLEXPWM1_FAULT1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 36) /* XBARA1_OUT36 output assigned to FLEXPWM1_FAULT1 */
#define IMXRT_XBARA1_OUT_FLEXPWM1234_FAULT2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 37) /* XBARA1_OUT37 output assigned to FLEXPWM1_2_3_4_FAULT2 */
#define IMXRT_XBARA1_OUT_FLEXPWM1234_FAULT3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 38) /* XBARA1_OUT38 output assigned to FLEXPWM1_2_3_4_FAULT3 */
#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_FORCE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 39) /* XBARA1_OUT39 output assigned to FLEXPWM1_EXT_FORCE */
#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 40) /* XBARA1_OUT40 output assigned to FLEXPWM2_3_4_EXTA0 */
#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 41) /* XBARA1_OUT41 output assigned to FLEXPWM2_3_4_EXTA1 */
#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 42) /* XBARA1_OUT42 output assigned to FLEXPWM2_3_4_EXTA2 */
#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 43) /* XBARA1_OUT43 output assigned to FLEXPWM2_3_4_EXTA3 */
#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 44) /* XBARA1_OUT44 output assigned to FLEXPWM2_EXT_SYNC0 */
#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 45) /* XBARA1_OUT45 output assigned to FLEXPWM2_EXT_SYNC1 */
#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 46) /* XBARA1_OUT46 output assigned to FLEXPWM2_EXT_SYNC2 */
#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 47) /* XBARA1_OUT47 output assigned to FLEXPWM2_EXT_SYNC3 */
#define IMXRT_XBARA1_OUT_FLEXPWM234_EXT_CLK_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 48) /* XBARA1_OUT48 output assigned to FLEXPWM2_3_4_EXT_CLK */
#define IMXRT_XBARA1_OUT_FLEXPWM2_FAULT0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 49) /* XBARA1_OUT49 output assigned to FLEXPWM2_FAULT0 */
#define IMXRT_XBARA1_OUT_FLEXPWM2_FAULT1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 50) /* XBARA1_OUT50 output assigned to FLEXPWM2_FAULT1 */
#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_FORCE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 51) /* XBARA1_OUT51 output assigned to FLEXPWM2_EXT_FORCE */
#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 52) /* XBARA1_OUT52 output assigned to FLEXPWM3_EXT_SYNC0 */
#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 53) /* XBARA1_OUT53 output assigned to FLEXPWM3_EXT_SYNC1 */
#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 54) /* XBARA1_OUT54 output assigned to FLEXPWM3_EXT_SYNC2 */
#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 55) /* XBARA1_OUT55 output assigned to FLEXPWM3_EXT_SYNC3 */
#define IMXRT_XBARA1_OUT_FLEXPWM3_FAULT0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 56) /* XBARA1_OUT56 output assigned to FLEXPWM3_FAULT0 */
#define IMXRT_XBARA1_OUT_FLEXPWM3_FAULT1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 57) /* XBARA1_OUT57 output assigned to FLEXPWM3_FAULT1 */
#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_FORCE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 58) /* XBARA1_OUT58 output assigned to FLEXPWM3_EXT_FORCE */
#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 59) /* XBARA1_OUT59 output assigned to FLEXPWM4_EXT_SYNC0 */
#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 60) /* XBARA1_OUT60 output assigned to FLEXPWM4_EXT_SYNC1 */
#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 61) /* XBARA1_OUT61 output assigned to FLEXPWM4_EXT_SYNC2 */
#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 62) /* XBARA1_OUT62 output assigned to FLEXPWM4_EXT_SYNC3 */
#define IMXRT_XBARA1_OUT_FLEXPWM4_FAULT0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 63) /* XBARA1_OUT63 output assigned to FLEXPWM4_FAULT0 */
#define IMXRT_XBARA1_OUT_FLEXPWM4_FAULT1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 64) /* XBARA1_OUT64 output assigned to FLEXPWM4_FAULT1 */
#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_FORCE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 65) /* XBARA1_OUT65 output assigned to FLEXPWM4_EXT_FORCE */
#define IMXRT_XBARA1_OUT_ENC1_PHASE_AIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 66) /* XBARA1_OUT66 output assigned to ENC1_PHASE_A_IN_ */
#define IMXRT_XBARA1_OUT_ENC1_PHASE_BIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 67) /* XBARA1_OUT67 output assigned to ENC1_PHASE_B_IN_ */
#define IMXRT_XBARA1_OUT_ENC1_INDEX_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 68) /* XBARA1_OUT68 output assigned to ENC1_INDEX */
#define IMXRT_XBARA1_OUT_ENC1_HOME_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 69) /* XBARA1_OUT69 output assigned to ENC1_HOME */
#define IMXRT_XBARA1_OUT_ENC1_TRIGGER_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 70) /* XBARA1_OUT70 output assigned to ENC1_TRIGGER */
#define IMXRT_XBARA1_OUT_ENC2_PHASE_AIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 71) /* XBARA1_OUT71 output assigned to ENC2_PHASE_A_IN_ */
#define IMXRT_XBARA1_OUT_ENC2_PHASE_BIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 72) /* XBARA1_OUT72 output assigned to ENC2_PHASE_B_IN_ */
#define IMXRT_XBARA1_OUT_ENC2_INDEX_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 73) /* XBARA1_OUT73 output assigned to ENC2_INDEX */
#define IMXRT_XBARA1_OUT_ENC2_HOME_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 74) /* XBARA1_OUT74 output assigned to ENC2_HOME */
#define IMXRT_XBARA1_OUT_ENC2_TRIGGER_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 75) /* XBARA1_OUT75 output assigned to ENC2_TRIGGER */
#define IMXRT_XBARA1_OUT_ENC3_PHASE_AIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 76) /* XBARA1_OUT76 output assigned to ENC3_PHASE_A_IN_ */
#define IMXRT_XBARA1_OUT_ENC3_PHASE_BIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 77) /* XBARA1_OUT77 output assigned to ENC3_PHASE_B_IN_ */
#define IMXRT_XBARA1_OUT_ENC3_INDEX_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 78) /* XBARA1_OUT78 output assigned to ENC3_INDEX */
#define IMXRT_XBARA1_OUT_ENC3_HOME_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 79) /* XBARA1_OUT79 output assigned to ENC3_HOME */
#define IMXRT_XBARA1_OUT_ENC3_TRIGGER_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 80) /* XBARA1_OUT80 output assigned to ENC3_TRIGGER */
#define IMXRT_XBARA1_OUT_ENC4_PHASE_AIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 81) /* XBARA1_OUT81 output assigned to ENC4_PHASE_A_IN_ */
#define IMXRT_XBARA1_OUT_ENC4_PHASE_BIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 82) /* XBARA1_OUT82 output assigned to ENC4_PHASE_B_IN_ */
#define IMXRT_XBARA1_OUT_ENC4_INDEX_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 83) /* XBARA1_OUT83 output assigned to ENC4_INDEX */
#define IMXRT_XBARA1_OUT_ENC4_HOME_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 84) /* XBARA1_OUT84 output assigned to ENC4_HOME */
#define IMXRT_XBARA1_OUT_ENC4_TRIGGER_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 85) /* XBARA1_OUT85 output assigned to ENC4_TRIGGER */
#define IMXRT_XBARA1_OUT_QTIMER1_TMR0_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 86) /* XBARA1_OUT86 output assigned to QTIMER1_TMR0_IN_ */
#define IMXRT_XBARA1_OUT_QTIMER1_TMR1_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 87) /* XBARA1_OUT87 output assigned to QTIMER1_TMR1_IN_ */
#define IMXRT_XBARA1_OUT_QTIMER1_TMR2_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 88) /* XBARA1_OUT88 output assigned to QTIMER1_TMR2_IN_ */
#define IMXRT_XBARA1_OUT_QTIMER1_TMR3_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 89) /* XBARA1_OUT89 output assigned to QTIMER1_TMR3_IN_ */
#define IMXRT_XBARA1_OUT_QTIMER2_TMR0_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 90) /* XBARA1_OUT90 output assigned to QTIMER2_TMR0_IN_ */
#define IMXRT_XBARA1_OUT_QTIMER2_TMR1_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 91) /* XBARA1_OUT91 output assigned to QTIMER2_TMR1_IN_ */
#define IMXRT_XBARA1_OUT_QTIMER2_TMR2_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 92) /* XBARA1_OUT92 output assigned to QTIMER2_TMR2_IN_ */
#define IMXRT_XBARA1_OUT_QTIMER2_TMR3_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 93) /* XBARA1_OUT93 output assigned to QTIMER2_TMR3_IN_ */
#define IMXRT_XBARA1_OUT_QTIMER3_TMR0_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 94) /* XBARA1_OUT94 output assigned to QTIMER3_TMR0_IN_ */
#define IMXRT_XBARA1_OUT_QTIMER3_TMR1_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 95) /* XBARA1_OUT95 output assigned to QTIMER3_TMR1_IN_ */
#define IMXRT_XBARA1_OUT_QTIMER3_TMR2_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 96) /* XBARA1_OUT96 output assigned to QTIMER3_TMR2_IN_ */
#define IMXRT_XBARA1_OUT_QTIMER3_TMR3_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 97) /* XBARA1_OUT97 output assigned to QTIMER3_TMR3_IN_ */
#define IMXRT_XBARA1_OUT_QTIMER4_TMR0_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 98) /* XBARA1_OUT98 output assigned to QTIMER4_TMR0_IN_ */
#define IMXRT_XBARA1_OUT_QTIMER4_TMR1_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 99) /* XBARA1_OUT99 output assigned to QTIMER4_TMR1_IN_ */
#define IMXRT_XBARA1_OUT_QTIMER4_TMR2_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 100) /* XBARA1_OUT100 output assigned to QTIMER4_TMR2_IN_ */
#define IMXRT_XBARA1_OUT_QTIMER4_TMR3_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 101) /* XBARA1_OUT101 output assigned to QTIMER4_TMR3_IN_ */
#define IMXRT_XBARA1_OUT_EWM_EWM_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 102) /* XBARA1_OUT102 output assigned to EWM_EWM_IN */
#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 103) /* XBARA1_OUT103 output assigned to ADC_ETC_XBAR0_TRIG0 */
#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 104) /* XBARA1_OUT104 output assigned to ADC_ETC_XBAR0_TRIG1 */
#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 105) /* XBARA1_OUT105 output assigned to ADC_ETC_XBAR0_TRIG2 */
#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 106) /* XBARA1_OUT106 output assigned to ADC_ETC_XBAR0_TRIG3 */
#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 107) /* XBARA1_OUT107 output assigned to ADC_ETC_XBAR1_TRIG0 */
#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 108) /* XBARA1_OUT108 output assigned to ADC_ETC_XBAR1_TRIG1 */
#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 109) /* XBARA1_OUT109 output assigned to ADC_ETC_XBAR1_TRIG2 */
#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 110) /* XBARA1_OUT110 output assigned to ADC_ETC_XBAR1_TRIG3 */
#define IMXRT_XBARA1_OUT_LPI2C1_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 111) /* XBARA1_OUT111 output assigned to LPI2C1_TRG_IN_ */
#define IMXRT_XBARA1_OUT_LPI2C2_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 112) /* XBARA1_OUT112 output assigned to LPI2C2_TRG_IN_ */
#define IMXRT_XBARA1_OUT_LPI2C3_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 113) /* XBARA1_OUT113 output assigned to LPI2C3_TRG_IN_ */
#define IMXRT_XBARA1_OUT_LPI2C4_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 114) /* XBARA1_OUT114 output assigned to LPI2C4_TRG_IN_ */
#define IMXRT_XBARA1_OUT_LPSPI1_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 115) /* XBARA1_OUT115 output assigned to LPSPI1_TRG_IN_ */
#define IMXRT_XBARA1_OUT_LPSPI2_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 116) /* XBARA1_OUT116 output assigned to LPSPI2_TRG_IN_ */
#define IMXRT_XBARA1_OUT_LPSPI3_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 117) /* XBARA1_OUT117 output assigned to LPSPI3_TRG_IN_ */
#define IMXRT_XBARA1_OUT_LPSPI4_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 118) /* XBARA1_OUT118 output assigned to LPSPI4_TRG_IN_ */
#define IMXRT_XBARA1_OUT_LPUART1_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 119) /* XBARA1_OUT119 output assigned to LPUART1_TRG_IN_ */
#define IMXRT_XBARA1_OUT_LPUART2_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 120) /* XBARA1_OUT120 output assigned to LPUART2_TRG_IN_ */
#define IMXRT_XBARA1_OUT_LPUART3_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 121) /* XBARA1_OUT121 output assigned to LPUART3_TRG_IN_ */
#define IMXRT_XBARA1_OUT_LPUART4_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 122) /* XBARA1_OUT122 output assigned to LPUART4_TRG_IN_ */
#define IMXRT_XBARA1_OUT_LPUART5_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 123) /* XBARA1_OUT123 output assigned to LPUART5_TRG_IN_ */
#define IMXRT_XBARA1_OUT_LPUART6_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 124) /* XBARA1_OUT124 output assigned to LPUART6_TRG_IN_ */
#define IMXRT_XBARA1_OUT_LPUART7_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 125) /* XBARA1_OUT125 output assigned to LPUART7_TRG_IN_ */
#define IMXRT_XBARA1_OUT_LPUART8_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 126) /* XBARA1_OUT126 output assigned to LPUART8_TRG_IN_ */
#define IMXRT_XBARA1_OUT_FLEXIO1_TRIGGER_IN0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 127) /* XBARA1_OUT127 output assigned to FLEXIO1_TRIGGER_IN0 */
#define IMXRT_XBARA1_OUT_FLEXIO1_TRIGGER_IN1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 128) /* XBARA1_OUT128 output assigned to FLEXIO1_TRIGGER_IN1 */
#define IMXRT_XBARA1_OUT_FLEXIO2_TRIGGER_IN0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 129) /* XBARA1_OUT129 output assigned to FLEXIO2_TRIGGER_IN0 */
#define IMXRT_XBARA1_OUT_FLEXIO2_TRIGGER_IN1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 130) /* XBARA1_OUT130 output assigned to FLEXIO2_TRIGGER_IN1 */
/* XBARB2 Mux inputs (I values) *******************************************************************************************************************/
#define IMXRT_XBARB2_IN_LOGIC_LOW IMXRT_XBARB2(XBAR_INPUT, 0) /* LOGIC_LOW output assigned to XBARB2_IN0 input. */
#define IMXRT_XBARB2_IN_LOGIC_HIGH IMXRT_XBARB2(XBAR_INPUT, 1) /* LOGIC_HIGH output assigned to XBARB2_IN1 input. */
#define IMXRT_XBARB2_IN_RESERVED2 IMXRT_XBARB2(XBAR_INPUT, 2) /* XBARB2_IN2 input is reserved. */
#define IMXRT_XBARB2_IN_RESERVED3 IMXRT_XBARB2(XBAR_INPUT, 3) /* XBARB2_IN3 input is reserved. */
#define IMXRT_XBARB2_IN_RESERVED4 IMXRT_XBARB2(XBAR_INPUT, 4) /* XBARB2_IN4 input is reserved. */
#define IMXRT_XBARB2_IN_RESERVED5 IMXRT_XBARB2(XBAR_INPUT, 5) /* XBARB2_IN5 input is reserved. */
#define IMXRT_XBARB2_IN_ACMP1_OUT IMXRT_XBARB2(XBAR_INPUT, 6) /* ACMP1_OUT output assigned to XBARB2_IN6 input. */
#define IMXRT_XBARB2_IN_ACMP2_OUT IMXRT_XBARB2(XBAR_INPUT, 7) /* ACMP2_OUT output assigned to XBARB2_IN7 input. */
#define IMXRT_XBARB2_IN_ACMP3_OUT IMXRT_XBARB2(XBAR_INPUT, 8) /* ACMP3_OUT output assigned to XBARB2_IN8 input. */
#define IMXRT_XBARB2_IN_ACMP4_OUT IMXRT_XBARB2(XBAR_INPUT, 9) /* ACMP4_OUT output assigned to XBARB2_IN9 input. */
#define IMXRT_XBARB2_IN_RESERVED10 IMXRT_XBARB2(XBAR_INPUT, 10) /* XBARB2_IN10 input is reserved. */
#define IMXRT_XBARB2_IN_RESERVED11 IMXRT_XBARB2(XBAR_INPUT, 11) /* XBARB2_IN11 input is reserved. */
#define IMXRT_XBARB2_IN_QTIMER3_TMR0_OUT IMXRT_XBARB2(XBAR_INPUT, 12) /* QTIMER3_TMR0_OUTPUT output assigned to XBARB2_IN12 input. */
#define IMXRT_XBARB2_IN_QTIMER3_TMR1_OUT IMXRT_XBARB2(XBAR_INPUT, 13) /* QTIMER3_TMR1_OUTPUT output assigned to XBARB2_IN13 input. */
#define IMXRT_XBARB2_IN_QTIMER3_TMR2_OUT IMXRT_XBARB2(XBAR_INPUT, 14) /* QTIMER3_TMR2_OUTPUT output assigned to XBARB2_IN14 input. */
#define IMXRT_XBARB2_IN_QTIMER3_TMR3_OUT IMXRT_XBARB2(XBAR_INPUT, 15) /* QTIMER3_TMR3_OUTPUT output assigned to XBARB2_IN15 input. */
#define IMXRT_XBARB2_IN_QTIMER4_TMR0_OUT IMXRT_XBARB2(XBAR_INPUT, 16) /* QTIMER4_TMR0_OUTPUT output assigned to XBARB2_IN16 input. */
#define IMXRT_XBARB2_IN_QTIMER4_TMR1_OUT IMXRT_XBARB2(XBAR_INPUT, 17) /* QTIMER4_TMR1_OUTPUT output assigned to XBARB2_IN17 input. */
#define IMXRT_XBARB2_IN_QTIMER4_TMR2_OUT IMXRT_XBARB2(XBAR_INPUT, 18) /* QTIMER4_TMR2_OUTPUT output assigned to XBARB2_IN18 input. */
#define IMXRT_XBARB2_IN_QTIMER4_TMR3_OUT IMXRT_XBARB2(XBAR_INPUT, 19) /* QTIMER4_TMR3_OUTPUT output assigned to XBARB2_IN19 input. */
#define IMXRT_XBARB2_IN_FLEXPWM1_PWM1_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 20) /* FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN20 input. */
#define IMXRT_XBARB2_IN_FLEXPWM1_PWM2_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 21) /* FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN21 input. */
#define IMXRT_XBARB2_IN_FLEXPWM1_PWM3_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 22) /* FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN22 input. */
#define IMXRT_XBARB2_IN_FLEXPWM1_PWM4_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 23) /* FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN23 input. */
#define IMXRT_XBARB2_IN_FLEXPWM2_PWM1_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 24) /* FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN24 input. */
#define IMXRT_XBARB2_IN_FLEXPWM2_PWM2_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 25) /* FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN25 input. */
#define IMXRT_XBARB2_IN_FLEXPWM2_PWM3_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 26) /* FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN26 input. */
#define IMXRT_XBARB2_IN_FLEXPWM2_PWM4_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 27) /* FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN27 input. */
#define IMXRT_XBARB2_IN_FLEXPWM3_PWM1_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 28) /* FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN28 input. */
#define IMXRT_XBARB2_IN_FLEXPWM3_PWM2_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 29) /* FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN29 input. */
#define IMXRT_XBARB2_IN_FLEXPWM3_PWM3_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 30) /* FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN30 input. */
#define IMXRT_XBARB2_IN_FLEXPWM3_PWM4_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 31) /* FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN31 input. */
#define IMXRT_XBARB2_IN_FLEXPWM4_PWM1_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 32) /* FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN32 input. */
#define IMXRT_XBARB2_IN_FLEXPWM4_PWM2_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 33) /* FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN33 input. */
#define IMXRT_XBARB2_IN_FLEXPWM4_PWM3_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 34) /* FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN34 input. */
#define IMXRT_XBARB2_IN_FLEXPWM4_PWM4_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 35) /* FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN35 input. */
#define IMXRT_XBARB2_IN_PIT_TRIGGER0 IMXRT_XBARB2(XBAR_INPUT, 36) /* PIT_TRIGGER0 output assigned to XBARB2_IN36 input. */
#define IMXRT_XBARB2_IN_PIT_TRIGGER1 IMXRT_XBARB2(XBAR_INPUT, 37) /* PIT_TRIGGER1 output assigned to XBARB2_IN37 input. */
#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO0 IMXRT_XBARB2(XBAR_INPUT, 38) /* ADC_ETC_XBAR0_COCO0 output assigned to XBARB2_IN38 input. */
#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO1 IMXRT_XBARB2(XBAR_INPUT, 39) /* ADC_ETC_XBAR0_COCO1 output assigned to XBARB2_IN39 input. */
#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO2 IMXRT_XBARB2(XBAR_INPUT, 40) /* ADC_ETC_XBAR0_COCO2 output assigned to XBARB2_IN40 input. */
#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO3 IMXRT_XBARB2(XBAR_INPUT, 41) /* ADC_ETC_XBAR0_COCO3 output assigned to XBARB2_IN41 input. */
#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO0 IMXRT_XBARB2(XBAR_INPUT, 42) /* ADC_ETC_XBAR1_COCO0 output assigned to XBARB2_IN42 input. */
#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO1 IMXRT_XBARB2(XBAR_INPUT, 43) /* ADC_ETC_XBAR1_COCO1 output assigned to XBARB2_IN43 input. */
#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO2 IMXRT_XBARB2(XBAR_INPUT, 44) /* ADC_ETC_XBAR1_COCO2 output assigned to XBARB2_IN44 input. */
#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO3 IMXRT_XBARB2(XBAR_INPUT, 45) /* ADC_ETC_XBAR1_COCO3 output assigned to XBARB2_IN45 input. */
#define IMXRT_XBARB2_IN_ENC1_POS_MATCH IMXRT_XBARB2(XBAR_INPUT, 46) /* ENC1_POS_MATCH output assigned to XBARB2_IN46 input. */
#define IMXRT_XBARB2_IN_ENC2_POS_MATCH IMXRT_XBARB2(XBAR_INPUT, 47) /* ENC2_POS_MATCH output assigned to XBARB2_IN47 input. */
#define IMXRT_XBARB2_IN_ENC3_POS_MATCH IMXRT_XBARB2(XBAR_INPUT, 48) /* ENC3_POS_MATCH output assigned to XBARB2_IN48 input. */
#define IMXRT_XBARB2_IN_ENC4_POS_MATCH IMXRT_XBARB2(XBAR_INPUT, 49) /* ENC4_POS_MATCH output assigned to XBARB2_IN49 input. */
#define IMXRT_XBARB2_IN_DMA_DONE0 IMXRT_XBARB2(XBAR_INPUT, 50) /* DMA_DONE0 output assigned to XBARB2_IN50 input. */
#define IMXRT_XBARB2_IN_DMA_DONE1 IMXRT_XBARB2(XBAR_INPUT, 51) /* DMA_DONE1 output assigned to XBARB2_IN51 input. */
#define IMXRT_XBARB2_IN_DMA_DONE2 IMXRT_XBARB2(XBAR_INPUT, 52) /* DMA_DONE2 output assigned to XBARB2_IN52 input. */
#define IMXRT_XBARB2_IN_DMA_DONE3 IMXRT_XBARB2(XBAR_INPUT, 53) /* DMA_DONE3 output assigned to XBARB2_IN53 input. */
#define IMXRT_XBARB2_IN_DMA_DONE4 IMXRT_XBARB2(XBAR_INPUT, 54) /* DMA_DONE4 output assigned to XBARB2_IN54 input. */
#define IMXRT_XBARB2_IN_DMA_DONE5 IMXRT_XBARB2(XBAR_INPUT, 55) /* DMA_DONE5 output assigned to XBARB2_IN55 input. */
#define IMXRT_XBARB2_IN_DMA_DONE6 IMXRT_XBARB2(XBAR_INPUT, 56) /* DMA_DONE6 output assigned to XBARB2_IN56 input. */
#define IMXRT_XBARB2_IN_DMA_DONE7 IMXRT_XBARB2(XBAR_INPUT, 57) /* DMA_DONE7 output assigned to XBARB2_IN57 input. */
/* XBARB2 Mux Output (M Muxes) ********************************************************************************************************************/
#define IMXRT_XBARB2_OUT_AOI1_IN00_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 0) /* XBARB2_OUT0 output assigned to AOI1_IN00 */
#define IMXRT_XBARB2_OUT_AOI1_IN01_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 1) /* XBARB2_OUT1 output assigned to AOI1_IN01 */
#define IMXRT_XBARB2_OUT_AOI1_IN02_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 2) /* XBARB2_OUT2 output assigned to AOI1_IN02 */
#define IMXRT_XBARB2_OUT_AOI1_IN03_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 3) /* XBARB2_OUT3 output assigned to AOI1_IN03 */
#define IMXRT_XBARB2_OUT_AOI1_IN04_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 4) /* XBARB2_OUT4 output assigned to AOI1_IN04 */
#define IMXRT_XBARB2_OUT_AOI1_IN05_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 5) /* XBARB2_OUT5 output assigned to AOI1_IN05 */
#define IMXRT_XBARB2_OUT_AOI1_IN06_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 6) /* XBARB2_OUT6 output assigned to AOI1_IN06 */
#define IMXRT_XBARB2_OUT_AOI1_IN07_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 7) /* XBARB2_OUT7 output assigned to AOI1_IN07 */
#define IMXRT_XBARB2_OUT_AOI1_IN08_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 8) /* XBARB2_OUT8 output assigned to AOI1_IN08 */
#define IMXRT_XBARB2_OUT_AOI1_IN09_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 9) /* XBARB2_OUT9 output assigned to AOI1_IN09 */
#define IMXRT_XBARB2_OUT_AOI1_IN10_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 10) /* XBARB2_OUT10 output assigned to AOI1_IN10 */
#define IMXRT_XBARB2_OUT_AOI1_IN11_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 11) /* XBARB2_OUT11 output assigned to AOI1_IN11 */
#define IMXRT_XBARB2_OUT_AOI1_IN12_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 12) /* XBARB2_OUT12 output assigned to AOI1_IN12 */
#define IMXRT_XBARB2_OUT_AOI1_IN13_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 13) /* XBARB2_OUT13 output assigned to AOI1_IN13 */
#define IMXRT_XBARB2_OUT_AOI1_IN14_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 14) /* XBARB2_OUT14 output assigned to AOI1_IN14 */
#define IMXRT_XBARB2_OUT_AOI1_IN15_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 15) /* XBARB2_OUT15 output assigned to AOI1_IN15 */
/* XBARB3 Mux inputs (I values) *******************************************************************************************************************/
#define IMXRT_XBARB3_IN_LOGIC_LOW IMXRT_XBARB3(XBAR_INPUT, 0) /* LOGIC_LOW output assigned to XBARB3_IN0 input. */
#define IMXRT_XBARB3_IN_LOGIC_HIGH IMXRT_XBARB3(XBAR_INPUT, 1) /* LOGIC_HIGH output assigned to XBARB3_IN1 input. */
#define IMXRT_XBARB3_IN_RESERVED2 IMXRT_XBARB3(XBAR_INPUT, 2) /* XBARB3_IN2 input is reserved. */
#define IMXRT_XBARB3_IN_RESERVED3 IMXRT_XBARB3(XBAR_INPUT, 3) /* XBARB3_IN3 input is reserved. */
#define IMXRT_XBARB3_IN_RESERVED4 IMXRT_XBARB3(XBAR_INPUT, 4) /* XBARB3_IN4 input is reserved. */
#define IMXRT_XBARB3_IN_RESERVED5 IMXRT_XBARB3(XBAR_INPUT, 5) /* XBARB3_IN5 input is reserved. */
#define IMXRT_XBARB3_IN_ACMP1_OUT IMXRT_XBARB3(XBAR_INPUT, 6) /* ACMP1_OUT output assigned to XBARB3_IN6 input. */
#define IMXRT_XBARB3_IN_ACMP2_OUT IMXRT_XBARB3(XBAR_INPUT, 7) /* ACMP2_OUT output assigned to XBARB3_IN7 input. */
#define IMXRT_XBARB3_IN_ACMP3_OUT IMXRT_XBARB3(XBAR_INPUT, 8) /* ACMP3_OUT output assigned to XBARB3_IN8 input. */
#define IMXRT_XBARB3_IN_ACMP4_OUT IMXRT_XBARB3(XBAR_INPUT, 9) /* ACMP4_OUT output assigned to XBARB3_IN9 input. */
#define IMXRT_XBARB3_IN_RESERVED10 IMXRT_XBARB3(XBAR_INPUT, 10) /* XBARB3_IN10 input is reserved. */
#define IMXRT_XBARB3_IN_RESERVED11 IMXRT_XBARB3(XBAR_INPUT, 11) /* XBARB3_IN11 input is reserved. */
#define IMXRT_XBARB3_IN_QTIMER3_TMR0_OUT IMXRT_XBARB3(XBAR_INPUT, 12) /* QTIMER3_TMR0_OUTPUT output assigned to XBARB3_IN12 input. */
#define IMXRT_XBARB3_IN_QTIMER3_TMR1_OUT IMXRT_XBARB3(XBAR_INPUT, 13) /* QTIMER3_TMR1_OUTPUT output assigned to XBARB3_IN13 input. */
#define IMXRT_XBARB3_IN_QTIMER3_TMR2_OUT IMXRT_XBARB3(XBAR_INPUT, 14) /* QTIMER3_TMR2_OUTPUT output assigned to XBARB3_IN14 input. */
#define IMXRT_XBARB3_IN_QTIMER3_TMR3_OUT IMXRT_XBARB3(XBAR_INPUT, 15) /* QTIMER3_TMR3_OUTPUT output assigned to XBARB3_IN15 input. */
#define IMXRT_XBARB3_IN_QTIMER4_TMR0_OUT IMXRT_XBARB3(XBAR_INPUT, 16) /* QTIMER4_TMR0_OUTPUT output assigned to XBARB3_IN16 input. */
#define IMXRT_XBARB3_IN_QTIMER4_TMR1_OUT IMXRT_XBARB3(XBAR_INPUT, 17) /* QTIMER4_TMR1_OUTPUT output assigned to XBARB3_IN17 input. */
#define IMXRT_XBARB3_IN_QTIMER4_TMR2_OUT IMXRT_XBARB3(XBAR_INPUT, 18) /* QTIMER4_TMR2_OUTPUT output assigned to XBARB3_IN18 input. */
#define IMXRT_XBARB3_IN_QTIMER4_TMR3_OUT IMXRT_XBARB3(XBAR_INPUT, 19) /* QTIMER4_TMR3_OUTPUT output assigned to XBARB3_IN19 input. */
#define IMXRT_XBARB3_IN_FLEXPWM1_PWM1_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 20) /* FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN20 input. */
#define IMXRT_XBARB3_IN_FLEXPWM1_PWM2_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 21) /* FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN21 input. */
#define IMXRT_XBARB3_IN_FLEXPWM1_PWM3_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 22) /* FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN22 input. */
#define IMXRT_XBARB3_IN_FLEXPWM1_PWM4_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 23) /* FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN23 input. */
#define IMXRT_XBARB3_IN_FLEXPWM2_PWM1_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 24) /* FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN24 input. */
#define IMXRT_XBARB3_IN_FLEXPWM2_PWM2_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 25) /* FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN25 input. */
#define IMXRT_XBARB3_IN_FLEXPWM2_PWM3_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 26) /* FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN26 input. */
#define IMXRT_XBARB3_IN_FLEXPWM2_PWM4_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 27) /* FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN27 input. */
#define IMXRT_XBARB3_IN_FLEXPWM3_PWM1_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 28) /* FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN28 input. */
#define IMXRT_XBARB3_IN_FLEXPWM3_PWM2_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 29) /* FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN29 input. */
#define IMXRT_XBARB3_IN_FLEXPWM3_PWM3_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 30) /* FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN30 input. */
#define IMXRT_XBARB3_IN_FLEXPWM3_PWM4_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 31) /* FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN31 input. */
#define IMXRT_XBARB3_IN_FLEXPWM4_PWM1_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 32) /* FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN32 input. */
#define IMXRT_XBARB3_IN_FLEXPWM4_PWM2_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 33) /* FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN33 input. */
#define IMXRT_XBARB3_IN_FLEXPWM4_PWM3_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 34) /* FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN34 input. */
#define IMXRT_XBARB3_IN_FLEXPWM4_PWM4_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 35) /* FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN35 input. */
#define IMXRT_XBARB3_IN_PIT_TRIGGER0 IMXRT_XBARB3(XBAR_INPUT, 36) /* PIT_TRIGGER0 output assigned to XBARB3_IN36 input. */
#define IMXRT_XBARB3_IN_PIT_TRIGGER1 IMXRT_XBARB3(XBAR_INPUT, 37) /* PIT_TRIGGER1 output assigned to XBARB3_IN37 input. */
#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO0 IMXRT_XBARB3(XBAR_INPUT, 38) /* ADC_ETC_XBAR0_COCO0 output assigned to XBARB3_IN38 input. */
#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO1 IMXRT_XBARB3(XBAR_INPUT, 39) /* ADC_ETC_XBAR0_COCO1 output assigned to XBARB3_IN39 input. */
#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO2 IMXRT_XBARB3(XBAR_INPUT, 40) /* ADC_ETC_XBAR0_COCO2 output assigned to XBARB3_IN40 input. */
#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO3 IMXRT_XBARB3(XBAR_INPUT, 41) /* ADC_ETC_XBAR0_COCO3 output assigned to XBARB3_IN41 input. */
#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO0 IMXRT_XBARB3(XBAR_INPUT, 42) /* ADC_ETC_XBAR1_COCO0 output assigned to XBARB3_IN42 input. */
#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO1 IMXRT_XBARB3(XBAR_INPUT, 43) /* ADC_ETC_XBAR1_COCO1 output assigned to XBARB3_IN43 input. */
#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO2 IMXRT_XBARB3(XBAR_INPUT, 44) /* ADC_ETC_XBAR1_COCO2 output assigned to XBARB3_IN44 input. */
#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO3 IMXRT_XBARB3(XBAR_INPUT, 45) /* ADC_ETC_XBAR1_COCO3 output assigned to XBARB3_IN45 input. */
#define IMXRT_XBARB3_IN_ENC1_POS_MATCH IMXRT_XBARB3(XBAR_INPUT, 46) /* ENC1_POS_MATCH output assigned to XBARB3_IN46 input. */
#define IMXRT_XBARB3_IN_ENC2_POS_MATCH IMXRT_XBARB3(XBAR_INPUT, 47) /* ENC2_POS_MATCH output assigned to XBARB3_IN47 input. */
#define IMXRT_XBARB3_IN_ENC3_POS_MATCH IMXRT_XBARB3(XBAR_INPUT, 48) /* ENC3_POS_MATCH output assigned to XBARB3_IN48 input. */
#define IMXRT_XBARB3_IN_ENC4_POS_MATCH IMXRT_XBARB3(XBAR_INPUT, 49) /* ENC4_POS_MATCH output assigned to XBARB3_IN49 input. */
#define IMXRT_XBARB3_IN_DMA_DONE0 IMXRT_XBARB3(XBAR_INPUT, 50) /* DMA_DONE0 output assigned to XBARB3_IN50 input. */
#define IMXRT_XBARB3_IN_DMA_DONE1 IMXRT_XBARB3(XBAR_INPUT, 51) /* DMA_DONE1 output assigned to XBARB3_IN51 input. */
#define IMXRT_XBARB3_IN_DMA_DONE2 IMXRT_XBARB3(XBAR_INPUT, 52) /* DMA_DONE2 output assigned to XBARB3_IN52 input. */
#define IMXRT_XBARB3_IN_DMA_DONE3 IMXRT_XBARB3(XBAR_INPUT, 53) /* DMA_DONE3 output assigned to XBARB3_IN53 input. */
#define IMXRT_XBARB3_IN_DMA_DONE4 IMXRT_XBARB3(XBAR_INPUT, 54) /* DMA_DONE4 output assigned to XBARB3_IN54 input. */
#define IMXRT_XBARB3_IN_DMA_DONE5 IMXRT_XBARB3(XBAR_INPUT, 55) /* DMA_DONE5 output assigned to XBARB3_IN55 input. */
#define IMXRT_XBARB3_IN_DMA_DONE6 IMXRT_XBARB3(XBAR_INPUT, 56) /* DMA_DONE6 output assigned to XBARB3_IN56 input. */
#define IMXRT_XBARB3_IN_DMA_DONE7 IMXRT_XBARB3(XBAR_INPUT, 57) /* DMA_DONE7 output assigned to XBARB3_IN57 input. */
/* XBARB3 Mux Output (M Muxes) ********************************************************************************************************************/
#define IMXRT_XBARB3_OUT_AOI2_IN00_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 0) /* XBARB3_OUT0 output assigned to AOI2_IN00 */
#define IMXRT_XBARB3_OUT_AOI2_IN01_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 1) /* XBARB3_OUT1 output assigned to AOI2_IN01 */
#define IMXRT_XBARB3_OUT_AOI2_IN02_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 2) /* XBARB3_OUT2 output assigned to AOI2_IN02 */
#define IMXRT_XBARB3_OUT_AOI2_IN03_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 3) /* XBARB3_OUT3 output assigned to AOI2_IN03 */
#define IMXRT_XBARB3_OUT_AOI2_IN04_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 4) /* XBARB3_OUT4 output assigned to AOI2_IN04 */
#define IMXRT_XBARB3_OUT_AOI2_IN05_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 5) /* XBARB3_OUT5 output assigned to AOI2_IN05 */
#define IMXRT_XBARB3_OUT_AOI2_IN06_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 6) /* XBARB3_OUT6 output assigned to AOI2_IN06 */
#define IMXRT_XBARB3_OUT_AOI2_IN07_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 7) /* XBARB3_OUT7 output assigned to AOI2_IN07 */
#define IMXRT_XBARB3_OUT_AOI2_IN08_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 8) /* XBARB3_OUT8 output assigned to AOI2_IN08 */
#define IMXRT_XBARB3_OUT_AOI2_IN09_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 9) /* XBARB3_OUT9 output assigned to AOI2_IN09 */
#define IMXRT_XBARB3_OUT_AOI2_IN10_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 10) /* XBARB3_OUT10 output assigned to AOI2_IN10 */
#define IMXRT_XBARB3_OUT_AOI2_IN11_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 11) /* XBARB3_OUT11 output assigned to AOI2_IN11 */
#define IMXRT_XBARB3_OUT_AOI2_IN12_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 12) /* XBARB3_OUT12 output assigned to AOI2_IN12 */
#define IMXRT_XBARB3_OUT_AOI2_IN13_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 13) /* XBARB3_OUT13 output assigned to AOI2_IN13 */
#define IMXRT_XBARB3_OUT_AOI2_IN14_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 14) /* XBARB3_OUT14 output assigned to AOI2_IN14 */
#define IMXRT_XBARB3_OUT_AOI2_IN15_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 15) /* XBARB3_OUT15 output assigned to AOI2_IN15 */
arch/arm/src/imxrt/imxrt_allocateheap.c
+1 -1
View File
@@ -54,7 +54,7 @@
#include "up_arch.h"
#include "up_internal.h"
#include "chip/imxrt_memorymap.h"
#include "hardware/imxrt_memorymap.h"
#include "imxrt_mpuinit.h"
#include <arch/board/board.h>
arch/arm/src/imxrt/imxrt_clockconfig.c
+3 -3
View File
@@ -44,11 +44,11 @@
#include "up_arch.h"
#include <arch/board/board.h>
#include "chip/imxrt_ccm.h"
#include "chip/imxrt_dcdc.h"
#include "hardware/imxrt_ccm.h"
#include "hardware/imxrt_dcdc.h"
#include "imxrt_clockconfig.h"
#include "imxrt_lcd.h"
#include "chip/imxrt_memorymap.h"
#include "hardware/imxrt_memorymap.h"
#include <stdlib.h>

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