diff --git a/arch/arm/src/imxrt/chip.h b/arch/arm/src/imxrt/chip.h index 9b2f23236e4..ed94fc67228 100644 --- a/arch/arm/src/imxrt/chip.h +++ b/arch/arm/src/imxrt/chip.h @@ -48,7 +48,7 @@ #include #include -#include "chip/imxrt_memorymap.h" +#include "hardware/imxrt_memorymap.h" /* If the common ARMv7-M vector handling logic is used, then it expects the following * definition in this file that provides the number of supported vectors external diff --git a/arch/arm/src/imxrt/chip/imxrt_adc.h b/arch/arm/src/imxrt/chip/imxrt_adc.h deleted file mode 100644 index 6b22c151290..00000000000 --- a/arch/arm/src/imxrt/chip/imxrt_adc.h +++ /dev/null @@ -1,263 +0,0 @@ -/************************************************************************************ - * arch/arm/src/imxrt/chip/imxrt_adc.h - * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * David Sidrane - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_ADC_H -#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_ADC_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include -#include "chip/imxrt_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register Offsets *****************************************************************/ - -#define IMXRT_ADC_HC0_OFFSET 0x0000 /* Control register for hardware triggers */ -#define IMXRT_ADC_HC1_OFFSET 0x0004 /* Control register for hardware triggers */ -#define IMXRT_ADC_HC2_OFFSET 0x0008 /* Control register for hardware triggers */ -#define IMXRT_ADC_HC3_OFFSET 0x000c /* Control register for hardware triggers */ -#define IMXRT_ADC_HC4_OFFSET 0x0010 /* Control register for hardware triggers */ -#define IMXRT_ADC_HC5_OFFSET 0x0014 /* Control register for hardware triggers */ -#define IMXRT_ADC_HC6_OFFSET 0x0018 /* Control register for hardware triggers */ -#define IMXRT_ADC_HC7_OFFSET 0x001c /* Control register for hardware triggers */ -#define IMXRT_ADC_HS_OFFSET 0x0020 /* Status register for HW triggers */ -#define IMXRT_ADC_R0_OFFSET 0x0024 /* Data result register for HW triggers */ -#define IMXRT_ADC_R1_OFFSET 0x0028 /* Data result register for HW triggers */ -#define IMXRT_ADC_R2_OFFSET 0x002c /* Data result register for HW triggers */ -#define IMXRT_ADC_R3_OFFSET 0x0030 /* Data result register for HW triggers */ -#define IMXRT_ADC_R4_OFFSET 0x0034 /* Data result register for HW triggers */ -#define IMXRT_ADC_R5_OFFSET 0x0038 /* Data result register for HW triggers */ -#define IMXRT_ADC_R6_OFFSET 0x003c /* Data result register for HW triggers */ -#define IMXRT_ADC_R7_OFFSET 0x0040 /* Data result register for HW triggers */ -#define IMXRT_ADC_CFG_OFFSET 0x0044 /* Configuration register */ -#define IMXRT_ADC_GC_OFFSET 0x0048 /* General control register */ -#define IMXRT_ADC_GS_OFFSET 0x004c /* General status register */ -#define IMXRT_ADC_CV_OFFSET 0x0050 /* Compare value register */ -#define IMXRT_ADC_OFS_OFFSET 0x0054 /* Offset correction value register */ -#define IMXRT_ADC_CAL_OFFSET 0x0058 /* Calibration value register */ - -/* Register addresses ***********************************************************************/ - -/* ADC1 Register Addresses */ - -#define IMXRT_ADC1_HC0 (IMXRT_ADC1_BASE + IMXRT_ADC_HC_OFFSET) /* ADC1 Control register for hardware triggers */ -#define IMXRT_ADC1_HC1 (IMXRT_ADC1_BASE + IMXRT_ADC_HC1_OFFSET) /* ADC1 Control register for hardware triggers */ -#define IMXRT_ADC1_HC2 (IMXRT_ADC1_BASE + IMXRT_ADC_HC2_OFFSET) /* ADC1 Control register for hardware triggers */ -#define IMXRT_ADC1_HC3 (IMXRT_ADC1_BASE + IMXRT_ADC_HC3_OFFSET) /* ADC1 Control register for hardware triggers */ -#define IMXRT_ADC1_HC4 (IMXRT_ADC1_BASE + IMXRT_ADC_HC4_OFFSET) /* ADC1 Control register for hardware triggers */ -#define IMXRT_ADC1_HC5 (IMXRT_ADC1_BASE + IMXRT_ADC_HC5_OFFSET) /* ADC1 Control register for hardware triggers */ -#define IMXRT_ADC1_HC6 (IMXRT_ADC1_BASE + IMXRT_ADC_HC6_OFFSET) /* ADC1 Control register for hardware triggers */ -#define IMXRT_ADC1_HC7 (IMXRT_ADC1_BASE + IMXRT_ADC_HC7_OFFSET) /* ADC1 Control register for hardware triggers */ -#define IMXRT_ADC1_HS (IMXRT_ADC1_BASE + IMXRT_ADC_HS_OFFSET) /* ADC1 Status register for HW triggers */ -#define IMXRT_ADC1_R0 (IMXRT_ADC1_BASE + IMXRT_ADC_R0_OFFSET) /* ADC1 Data result register for HW triggers */ -#define IMXRT_ADC1_R1 (IMXRT_ADC1_BASE + IMXRT_ADC_R1_OFFSET) /* ADC1 Data result register for HW triggers */ -#define IMXRT_ADC1_R2 (IMXRT_ADC1_BASE + IMXRT_ADC_R2_OFFSET) /* ADC1 Data result register for HW triggers */ -#define IMXRT_ADC1_R3 (IMXRT_ADC1_BASE + IMXRT_ADC_R3_OFFSET) /* ADC1 Data result register for HW triggers */ -#define IMXRT_ADC1_R4 (IMXRT_ADC1_BASE + IMXRT_ADC_R4_OFFSET) /* ADC1 Data result register for HW triggers */ -#define IMXRT_ADC1_R5 (IMXRT_ADC1_BASE + IMXRT_ADC_R5_OFFSET) /* ADC1 Data result register for HW triggers */ -#define IMXRT_ADC1_R6 (IMXRT_ADC1_BASE + IMXRT_ADC_R6_OFFSET) /* ADC1 Data result register for HW triggers */ -#define IMXRT_ADC1_R7 (IMXRT_ADC1_BASE + IMXRT_ADC_R7_OFFSET) /* ADC1 Data result register for HW triggers */ -#define IMXRT_ADC1_CFG (IMXRT_ADC1_BASE + IMXRT_ADC_CFG_OFFSET) /* ADC1 Configuration register */ -#define IMXRT_ADC1_GC (IMXRT_ADC1_BASE + IMXRT_ADC_GC_OFFSET) /* ADC1 General control register */ -#define IMXRT_ADC1_GS (IMXRT_ADC1_BASE + IMXRT_ADC_GS_OFFSET) /* ADC1 General status register */ -#define IMXRT_ADC1_CV (IMXRT_ADC1_BASE + IMXRT_ADC_CV_OFFSET) /* ADC1 Compare value register */ -#define IMXRT_ADC1_OFS (IMXRT_ADC1_BASE + IMXRT_ADC_OFS_OFFSET) /* ADC1 Offset correction value register */ -#define IMXRT_ADC1_CAL (IMXRT_ADC1_BASE + IMXRT_ADC_CAL_OFFSET) /* ADC1 Calibration value register */ - -/* ADC2 Register Addresses */ - -#define IMXRT_ADC2_HC0 (IMXRT_ADC2_BASE + IMXRT_ADC_HC_OFFSET) /* ADC2 Control register for hardware triggers */ -#define IMXRT_ADC2_HC1 (IMXRT_ADC2_BASE + IMXRT_ADC_HC1_OFFSET) /* ADC2 Control register for hardware triggers */ -#define IMXRT_ADC2_HC2 (IMXRT_ADC2_BASE + IMXRT_ADC_HC2_OFFSET) /* ADC2 Control register for hardware triggers */ -#define IMXRT_ADC2_HC3 (IMXRT_ADC2_BASE + IMXRT_ADC_HC3_OFFSET) /* ADC2 Control register for hardware triggers */ -#define IMXRT_ADC2_HC4 (IMXRT_ADC2_BASE + IMXRT_ADC_HC4_OFFSET) /* ADC2 Control register for hardware triggers */ -#define IMXRT_ADC2_HC5 (IMXRT_ADC2_BASE + IMXRT_ADC_HC5_OFFSET) /* ADC2 Control register for hardware triggers */ -#define IMXRT_ADC2_HC6 (IMXRT_ADC2_BASE + IMXRT_ADC_HC6_OFFSET) /* ADC2 Control register for hardware triggers */ -#define IMXRT_ADC2_HC7 (IMXRT_ADC2_BASE + IMXRT_ADC_HC7_OFFSET) /* ADC2 Control register for hardware triggers */ -#define IMXRT_ADC2_HS (IMXRT_ADC2_BASE + IMXRT_ADC_HS_OFFSET) /* ADC2 Status register for HW triggers */ -#define IMXRT_ADC2_R0 (IMXRT_ADC2_BASE + IMXRT_ADC_R0_OFFSET) /* ADC2 Data result register for HW triggers */ -#define IMXRT_ADC2_R1 (IMXRT_ADC2_BASE + IMXRT_ADC_R1_OFFSET) /* ADC2 Data result register for HW triggers */ -#define IMXRT_ADC2_R2 (IMXRT_ADC2_BASE + IMXRT_ADC_R2_OFFSET) /* ADC2 Data result register for HW triggers */ -#define IMXRT_ADC2_R3 (IMXRT_ADC2_BASE + IMXRT_ADC_R3_OFFSET) /* ADC2 Data result register for HW triggers */ -#define IMXRT_ADC2_R4 (IMXRT_ADC2_BASE + IMXRT_ADC_R4_OFFSET) /* ADC2 Data result register for HW triggers */ -#define IMXRT_ADC2_R5 (IMXRT_ADC2_BASE + IMXRT_ADC_R5_OFFSET) /* ADC2 Data result register for HW triggers */ -#define IMXRT_ADC2_R6 (IMXRT_ADC2_BASE + IMXRT_ADC_R6_OFFSET) /* ADC2 Data result register for HW triggers */ -#define IMXRT_ADC2_R7 (IMXRT_ADC2_BASE + IMXRT_ADC_R7_OFFSET) /* ADC2 Data result register for HW triggers */ -#define IMXRT_ADC2_CFG (IMXRT_ADC2_BASE + IMXRT_ADC_CFG_OFFSET) /* ADC2 Configuration register */ -#define IMXRT_ADC2_GC (IMXRT_ADC2_BASE + IMXRT_ADC_GC_OFFSET) /* ADC2 General control register */ -#define IMXRT_ADC2_GS (IMXRT_ADC2_BASE + IMXRT_ADC_GS_OFFSET) /* ADC2 General status register */ -#define IMXRT_ADC2_CV (IMXRT_ADC2_BASE + IMXRT_ADC_CV_OFFSET) /* ADC2 Compare value register */ -#define IMXRT_ADC2_OFS (IMXRT_ADC2_BASE + IMXRT_ADC_OFS_OFFSET) /* ADC2 Offset correction value register */ -#define IMXRT_ADC2_CAL (IMXRT_ADC2_BASE + IMXRT_ADC_CAL_OFFSET) /* ADC2 Calibration value register */ - -/* Register Bit Definitions *********************************************************/ - -/* Control register for hardware & SW triggers for n=0,1..7 */ - -#define ADC_HC_ADCH_SHIFT (0) /* Bits: 0-4 Input Channel Select */ -#define ADC_HC_ADCH_MASK (31 << ADC_HC_ADCH_SHIFT) -# define ADC_HC_ADCH(n) ((uint32_t)(n) << ADC_HC_ADCH_SHIFT) -# define ADC_HC_ADCH_EXT_0 (0 << ADC_HC_ADCH_SHIFT) /* External channels 0 */ -# define ADC_HC_ADCH_EXT_1 (1 << ADC_HC_ADCH_SHIFT) /* External channels 1 */ -# define ADC_HC_ADCH_EXT_2 (2 << ADC_HC_ADCH_SHIFT) /* External channels 2 */ -# define ADC_HC_ADCH_EXT_3 (3 << ADC_HC_ADCH_SHIFT) /* External channels 3 */ -# define ADC_HC_ADCH_EXT_4 (4 << ADC_HC_ADCH_SHIFT) /* External channels 4 */ -# define ADC_HC_ADCH_EXT_5 (5 << ADC_HC_ADCH_SHIFT) /* External channels 5 */ -# define ADC_HC_ADCH_EXT_6 (6 << ADC_HC_ADCH_SHIFT) /* External channels 6 */ -# define ADC_HC_ADCH_EXT_7 (7 << ADC_HC_ADCH_SHIFT) /* External channels 7 */ -# define ADC_HC_ADCH_EXT_8 (8 << ADC_HC_ADCH_SHIFT) /* External channels 8 */ -# define ADC_HC_ADCH_EXT_9 (9 << ADC_HC_ADCH_SHIFT) /* External channels 9 */ -# define ADC_HC_ADCH_EXT_10 (10 << ADC_HC_ADCH_SHIFT) /* External channels 10 */ -# define ADC_HC_ADCH_EXT_11 (11 << ADC_HC_ADCH_SHIFT) /* External channels 11 */ -# define ADC_HC_ADCH_EXT_12 (12 << ADC_HC_ADCH_SHIFT) /* External channels 12 */ -# define ADC_HC_ADCH_EXT_13 (13 << ADC_HC_ADCH_SHIFT) /* External channels 13 */ -# define ADC_HC_ADCH_EXT_14 (14 << ADC_HC_ADCH_SHIFT) /* External channels 14 */ -# define ADC_HC_ADCH_EXT_15 (15 << ADC_HC_ADCH_SHIFT) /* External channels 15 */ -# define ADC_HC_ADCH_EXT_ADC_ETC (16 << ADC_HC_ADCH_SHIFT) /* External channel selection from ADC_ETC */ -# define ADC_HC_ADCH_VREFSH (25 << ADC_HC_ADCH_SHIFT) /* internal channel, for ADC self-test, hard connected to VRH internally */ -# define ADC_HC_ADCH_DIS (31 << ADC_HC_ADCH_SHIFT) /* */ - /* Bits: 5-6 Reserved */ -#define ADC_HC_AIEN (1 << 7) /* Bit: 7 Conversion Complete Interrupt Enable/Disable Control */ - /* Bits: 8-31 Reserved */ - -/* Status register for HW triggers */ - -#define ADC_HS_COCO0 (1 << 0) /* Bit: 0 Conversion Complete Flag */ - /* Bits: 1-31 Reserved */ - -/* Data result register for HW & SW triggers */ - -#define ADC_R_CDATA_SHIFT (0) /* Bits: 0-11 Data (result of an ADC conversion) */ -#define ADC_R_CDATA_MASK (0xfff << ADC_R_CDATA_SHIFT) - -/* Configuration register */ - -#define ADC_CFG_ADICLK_SHIFT (0) /* Bits: 0-1 Input Clock Select */ -#define ADC_CFG_ADICLK_MASK (3 << ADC_CFG_ADICLK_SHIFT) -# define ADC_CFG_ADICLK(n) ((uint32_t)(n) << ADC_CFG_ADICLK_SHIFT) -# define ADC_CFG_ADICLK_IPG (0 << ADC_CFG_ADICLK_SHIFT) /* IPG clock */ -# define ADC_CFG_ADICLK_IPGDIV2 (1 << ADC_CFG_ADICLK_SHIFT) /* IPG clock divided by 2 */ -# define ADC_CFG_ADICLK_ADACK (3 << ADC_CFG_ADICLK_SHIFT) /* Asynchronous clock (ADACK) */ -#define ADC_CFG_MODE_SHIFT (2) /* Bits: 2-3 Conversion Mode Selection */ -#define ADC_CFG_MODE_MASK (3 << ADC_CFG_MODE_SHIFT) -# define ADC_CFG_MODE(n) ((uint32_t)(n) << ADC_CFG_MODE_SHIFT) -# define ADC_CFG_MODE_8BIT (0 << ADC_CFG_MODE_SHIFT) /* 8-bit conversion */ -# define ADC_CFG_MODE_10BIT (1 << ADC_CFG_MODE_SHIFT) /* 10-bit conversion */ -# define ADC_CFG_MODE_12BIT (2 << ADC_CFG_MODE_SHIFT) /* 12-bit conversion */ -#define ADC_CFG_ADLSMP (1 << 4) /* Bit: 4 Long Sample Time Configuration */ -#define ADC_CFG_ADIV_SHIFT (5) /* Bits: 5-6 Clock Divide Select */ -#define ADC_CFG_ADIV_MASK (3 << ADC_CFG_ADIV_SHIFT) -# define ADC_CFG_ADIV(n) ((uint32_t)(n) << ADC_CFG_ADIV_SHIFT) -# define ADC_CFG_ADIV_DIV1 (0 << ADC_CFG_ADIV_SHIFT) /* Input clock */ -# define ADC_CFG_ADIV_DIV2 (1 << ADC_CFG_ADIV_SHIFT) /* Input clock / 2 */ -# define ADC_CFG_ADIV_DIV4 (2 << ADC_CFG_ADIV_SHIFT) /* Input clock / 4 */ -# define ADC_CFG_ADIV_DIV8 (3 << ADC_CFG_ADIV_SHIFT) /* Input clock / 8 */ -#define ADC_CFG_ADLPC (1 << 7) /* Bit: 7 Low-Power Configuration */ -#define ADC_CFG_ADSTS_SHIFT (8) /* Bits: 8-9 Defines the sample time duration. */ -#define ADC_CFG_ADSTS_MASK (3 << ADC_CFG_ADSTS_SHIFT) -# define ADC_CFG_ADSTS(n) ((uint32_t)(n) << ADC_CFG_ADSTS_SHIFT) -# define ADC_CFG_ADSTS_2_12 (0 << ADC_CFG_ADSTS_SHIFT) /* Sample period (ADC clocks) = 2 if ADLSMP=0b, 12 if ADLSMP=1b */ -# define ADC_CFG_ADSTS_4_16 (1 << ADC_CFG_ADSTS_SHIFT) /* Sample period (ADC clocks) = 4 if ADLSMP=0b, 16 if ADLSMP=1b */ -# define ADC_CFG_ADSTS_6_20 (2 << ADC_CFG_ADSTS_SHIFT) /* Sample period (ADC clocks) = 6 if ADLSMP=0b, 20 if ADLSMP=1b */ -# define ADC_CFG_ADSTS_8_24 (3 << ADC_CFG_ADSTS_SHIFT) /* Sample period (ADC clocks) = 8 if ADLSMP=0b, 24 if ADLSMP=1b */ -#define ADC_CFG_ADHSC (1 << 10) /* Bit: 10 High Speed Configuration*/ -#define ADC_CFG_REFSEL_SHIFT (11) /* Bits: 11-12 Voltage Reference Selection */ -#define ADC_CFG_REFSEL_MASK (3 << ADC_CFG_REFSEL_SHIFT) -# define ADC_CFG_REFSEL(n) ((uint32_t)(n) << ADC_CFG_REFSEL_SHIFT) -# define ADC_CFG_REFSEL_VREF (0 << ADC_CFG_REFSEL_SHIFT) /* Selects VREFH/VREFL as reference voltage. */ -#define ADC_CFG_ADTRG (1 << 13) /* Bit: 13 Conversion Trigger Select */ -# define ADC_CFG_ADTRG_SW (0 << 13) /* SW trigger selected */ -# define ADC_CFG_ADTRG_HW (1 << 13) /* HW trigger selected */ -#define ADC_CFG_AVGS_SHIFT (14) /* Bits: 14-15 Hardware Average select */ -#define ADC_CFG_AVGS_MASK (3 << ADC_CFG_AVGS_SHIFT) -# define ADC_CFG_AVGS(n) ((uint32_t)(n) << ADC_CFG_AVGS_SHIFT) -# define ADC_CFG_AVGS_4SMPL (0 << ADC_CFG_AVGS_SHIFT) /* 4 samples averaged */ -# define ADC_CFG_AVGS_8SMPL (1 << ADC_CFG_AVGS_SHIFT) /* 8 samples averaged */ -# define ADC_CFG_AVGS_16SMPL (2 << ADC_CFG_AVGS_SHIFT) /* 16 samples averaged */ -# define ADC_CFG_AVGS_32SMPL (3 << ADC_CFG_AVGS_SHIFT) /* 32 samples averaged */ -#define ADC_CFG_OVWREN (1 << 16) /* Bit: 16 Data Overwrite Enable */ - /* Bits: 17-31 Reserved */ - -/* General control register */ - -#define ADC_GC_ADACKEN (1 << 0) /* Bit: 0 Asynchronous clock output enable */ -#define ADC_GC_DMAEN (1 << 1) /* Bit: 1 DMA Enable */ -#define ADC_GC_ACREN (1 << 2) /* Bit: 2 Compare Function Range Enable */ -#define ADC_GC_ACFGT (1 << 3) /* Bit: 3 Compare Function Greater Than Enable */ -#define ADC_GC_ACFE (1 << 4) /* Bit: 4 Compare Function Enable */ -#define ADC_GC_AVGE (1 << 5) /* Bit: 5 Hardware average enable */ -#define ADC_GC_ADCO (1 << 6) /* Bit: 6 Continuous Conversion Enable */ -#define ADC_GC_CAL (1 << 7) /* Bit: 7 Calibration */ - /* Bits: 8-31 Reserved */ - -/* General status register */ - -#define ADC_GS_ADACT (1 << 0) /* Bit: 0 Conversion Active */ -#define ADC_GS_CALF (1 << 1) /* Bit: 1 Calibration Failed Flag */ -#define ADC_GS_AWKST (1 << 2) /* Bit: 2 Asynchronous wakeup interrupt status */ - /* Bits: 3-31 Reserved */ - -/* Compare value register */ - -#define ADC_CV_CV1_SHIFT (0) /* Bits: 0-11 Compare Value 1 */ -#define ADC_CV_CV1_MASK (0xfff << ADC_CV_CV1_SHIFT) -# define ADC_CV_CV1(n) ((uint32_t)(n) << ADC_CV_CV1_SHIFT) - /* Bits: 12-15 Reserved */ -#define ADC_CV_CV2_SHIFT (16) /* Bits: 16-27 Compare Value 2 */ -#define ADC_CV_CV2_MASK (0xfff << ADC_CV_CV2_SHIFT) -# define ADC_CV_CV2(n) ((uint32_t)(n) << ADC_CV_CV2_SHIFT) - /* Bits: 28-31 Reserved */ - -/* Offset correction value register */ - -#define ADC_OFS_OFS_SHIFT (0) /* Bits: 0-11 Offset value */ -#define ADC_OFS_OFS_MASK (0xfff << ADC_OFS_OFS_SHIFT) -# define ADC_OFS_OFS(n) ((uint32_t)(n) << ADC_OFS_OFS_SHIFT) -#define ADC_OFS_SIGN (1 << 12) /* Bit: 12 Sign bit */ - /* Bits: 13-31 Reserved */ - -/* Calibration value register */ - -#define ADC_CAL_CAL_CODE_SHIFT (0) /* Bits: 0-3 Calibration Result Value */ -#define ADC_CAL_CAL_CODE_MASK (0xf << ADC_CAL_CAL_CODE_SHIFT) - /* Bits: 4-31 Reserved */ - -#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_ADC_H */ diff --git a/arch/arm/src/imxrt/chip/imxrt_ccm.h b/arch/arm/src/imxrt/chip/imxrt_ccm.h deleted file mode 100644 index ce5206e08e1..00000000000 --- a/arch/arm/src/imxrt/chip/imxrt_ccm.h +++ /dev/null @@ -1,57 +0,0 @@ -/***************************************************************************** - * arch/arm/src/imxrt/imxrt_ccm.h - * - * Copyright (C) 2018-2019 Gregory Nutt. All rights reserved. - * Authors: Janne Rosberg - * David Sidrane - * Dave Marples - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_CCM_H -#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_CCM_H - -/***************************************************************************** - * Included Files - *****************************************************************************/ - -#include -#include "chip/imxrt_memorymap.h" - -#if defined(CONFIG_ARCH_FAMILY_IMXRT102x) -# include "chip/rt102x/imxrt102x_ccm.h" -#elif defined(CONFIG_ARCH_FAMILY_IMXRT105x) -# include "chip/rt105x/imxrt105x_ccm.h" -#elif defined(CONFIG_ARCH_FAMILY_IMXRT106x) -# include "chip/rt106x/imxrt106x_ccm.h" -#else -# error Unrecognized i.MX RT architecture -#endif -#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_CCM_H */ diff --git a/arch/arm/src/imxrt/chip/imxrt_daisy.h b/arch/arm/src/imxrt/chip/imxrt_daisy.h deleted file mode 100644 index 4ff29fc52df..00000000000 --- a/arch/arm/src/imxrt/chip/imxrt_daisy.h +++ /dev/null @@ -1,62 +0,0 @@ -/************************************************************************************ - * arch/arm/src/imxrt/chip/imxrt_daisy.h - * - * Copyright (C) 2018-2019 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * David Sidrane - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_DAISY_H -#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_DAISY_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include -#include - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -/************************************************************************************ - * Name: imxrt_daisy_select - * - * Description: - * Initialize logic to support a daisy chain input selection for GPIO pins. - * - ************************************************************************************/ - -void imxrt_daisy_select(unsigned int index, unsigned int alt); - -#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_DAISY_H */ - diff --git a/arch/arm/src/imxrt/chip/imxrt_dcdc.h b/arch/arm/src/imxrt/chip/imxrt_dcdc.h deleted file mode 100644 index 28d3c758adb..00000000000 --- a/arch/arm/src/imxrt/chip/imxrt_dcdc.h +++ /dev/null @@ -1,152 +0,0 @@ -/**************************************************************************************************** - * arch/arm/src/imxrt/imxrt_dcdc.h - * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Janne Rosberg - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_DCDC_H -#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_DCDC_H - -/**************************************************************************************************** - * Included Files - ****************************************************************************************************/ - -#include -#include "chip/imxrt_memorymap.h" - -/**************************************************************************************************** - * Pre-processor Definitions - ****************************************************************************************************/ - -/* Register offsets *********************************************************************************/ - -#define IMXRT_DCDC_REG0_OFFSET 0x0000 /* DCDC Register 0 */ -#define IMXRT_DCDC_REG1_OFFSET 0x0004 /* DCDC Register 1 */ -#define IMXRT_DCDC_REG2_OFFSET 0x0008 /* DCDC Register 2 */ -#define IMXRT_DCDC_REG3_OFFSET 0x000c /* DCDC Register 3 */ - -/* Register addresses *******************************************************************************/ - -#define IMXRT_DCDC_REG0 (IMXRT_DCDC_BASE + IMXRT_DCDC_REG0_OFFSET) -#define IMXRT_DCDC_REG1 (IMXRT_DCDC_BASE + IMXRT_DCDC_REG1_OFFSET) -#define IMXRT_DCDC_REG2 (IMXRT_DCDC_BASE + IMXRT_DCDC_REG2_OFFSET) -#define IMXRT_DCDC_REG3 (IMXRT_DCDC_BASE + IMXRT_DCDC_REG3_OFFSET) - -/* Register bit definitions *************************************************************************/ - -/* Register 0 */ - -#define DCDC_REG0_PWD_ZCD (1 << 0) /* Bit 0: Power down the zero cross detection */ -#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH (1 << 1) /* Bit 1: Disable automatic clock switch */ -#define DCDC_REG0_SEL_CLK (1 << 2) /* Bit 2: Select 24 MHz Crystal clock */ -#define DCDC_REG0_PWD_OSC_INT (1 << 3) /* Bit 3: Power down internal osc */ -#define DCDC_REG0_PWD_CUR_SNS_CMP (1 << 4) /* Bit 4: The power down signal of the current detector */ -#define DCDC_REG0_CUR_SNS_THRSH_SHIFT (5) /* Bits 5-7: threshold of current detector */ -#define DCDC_REG0_CUR_SNS_THRSH_MASK (0x7 << DCDC_REG0_CUR_SNS_THRSH_SHIFT) -# define DCDC_REG0_CUR_SNS_THRSH_150MA ((uint32_t)(0) << DCDC_REG0_CUR_SNS_THRSH_SHIFT) -# define DCDC_REG0_CUR_SNS_THRSH_250MA ((uint32_t)(1) << DCDC_REG0_CUR_SNS_THRSH_SHIFT) -# define DCDC_REG0_CUR_SNS_THRSH_350MA ((uint32_t)(2) << DCDC_REG0_CUR_SNS_THRSH_SHIFT) -# define DCDC_REG0_CUR_SNS_THRSH_450MA ((uint32_t)(3) << DCDC_REG0_CUR_SNS_THRSH_SHIFT) -# define DCDC_REG0_CUR_SNS_THRSH_550MA ((uint32_t)(4) << DCDC_REG0_CUR_SNS_THRSH_SHIFT) -# define DCDC_REG0_CUR_SNS_THRSH_650MA ((uint32_t)(5) << DCDC_REG0_CUR_SNS_THRSH_SHIFT) -#define DCDC_REG0_PWD_OVERCUR_DET (1 << 8) /* Bit 8: Power down overcurrent detection comparator */ -#define DCDC_REG0_OVERCUR_TIRG_ADJ_SHIFT (9) /* Bits 9-10: The threshold of over current detection */ -#define DCDC_REG0_OVERCUR_TIRG_ADJ_MASK (0x3 << DCDC_REG0_OVERCUR_TIRG_ADJ_SHIFT) -# define DCDC_REG0_OVERCUR_TIRG_ADJ_1A_025 ((uint32_t)(0) << DCDC_REG0_OVERCUR_TIRG_ADJ_SHIFT) -# define DCDC_REG0_OVERCUR_TIRG_ADJ_2A_025 ((uint32_t)(1) << DCDC_REG0_OVERCUR_TIRG_ADJ_SHIFT) -# define DCDC_REG0_OVERCUR_TIRG_ADJ_1A_02 ((uint32_t)(2) << DCDC_REG0_OVERCUR_TIRG_ADJ_SHIFT) -# define DCDC_REG0_OVERCUR_TIRG_ADJ_2A_02 ((uint32_t)(3) << DCDC_REG0_OVERCUR_TIRG_ADJ_SHIFT) -#define DCDC_REG0_PWD_CMP_BATT_DET (1 << 11) /* Bit 11: Power down the low voltage detection comparator */ -#define DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT (12) /* Bits 12-15: Adjust value to poslimit_buck register */ -#define DCDC_REG0_ADJ_POSLIMIT_BUCK_MASK (0xf << DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT) -# define DCDC_REG0_ADJ_POSLIMIT_BUCK(n) ((uint32_t)(n) << DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT) -#define DCDC_REG0_EN_LP_OVERLOAD_SNS (1 << 16) /* Bit 16: Enable the overload detection in power save mode */ -#define DCDC_REG0_PWD_HIGH_VOLT_DET (1 << 17) /* Bit 17: Power down overvoltage detection comparator */ -#define DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT (18) /* Bits 18-19: the threshold of the counting number */ -#define DCDC_REG0_LP_OVERLOAD_THRSH_MASK (0x3 << DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT) -# define DCDC_REG0_LP_OVERLOAD_THRSH_32 ((uint32_t)(0) << DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT) -# define DCDC_REG0_LP_OVERLOAD_THRSH_64 ((uint32_t)(1) << DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT) -# define DCDC_REG0_LP_OVERLOAD_THRSH_16 ((uint32_t)(2) << DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT) -# define DCDC_REG0_LP_OVERLOAD_THRSH_8 ((uint32_t)(3) << DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT) -#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL (1 << 20) /* Bit 20: The period of counting the charging times in power save mode */ -#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL_8 (0 << 20) /* Bit 20: The period of counting the charging times in power save mode */ -#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL_16 (1 << 20) /* Bit 20: Fhe period of counting the charging times in power save mode */ -#define DCDC_REG0_LP_HIGH_HYS (1 << 21) /* Bit 21: Adjust hysteretic value in low power from 12.5mV to 25mV */ - /* Bits 22-26 Reserved */ -#define DCDC_REG0_XTALOK_DISABLE (1 << 27) /* Bit 27: Disable xtalok detection circuit */ -#define DCDC_REG0_CURRENT_ALERT_RESET (1 << 28) /* Bit 28: Reset current alert signal */ -#define DCDC_REG0_XTAL_24M_OK (1 << 29) /* Bit 29: Set to 1 to switch internal ring osc to xtal 24M */ - /* Bit 30: Reserved */ -#define DCDC_REG0_STS_DC_OK (1 << 31) /* Bit 31: Status register to indicate DCDC status */ - -/* Register 1 */ - -#define DCDC_REG1_POSLIMIT_BUCK_IN_SHIFT (0) /* Bits 0-6: Upper limit duty cycle limit in DC-DC converter */ -#define DCDC_REG1_POSLIMIT_BUCK_IN_MASK (0x7f << DCDC_REG1_POSLIMIT_BUCK_IN_SHIFT) -# define DCDC_REG1_POSLIMIT_BUCK_IN(n) ((uint32_t)(n) << DCDC_REG1_POSLIMIT_BUCK_IN_SHIFT) -#define DCDC_REG1_REG_FBK_SEL_SHIFT (7) /* Bits 7-8: Select the feedback point of the internal regulator */ -#define DCDC_REG1_REG_FBK_SEL_MASK (0x3 << DCDC_REG1_REG_FBK_SEL_SHIFT) -# define DCDC_REG1_REG_FBK_SEL(n) ((uint32_t)(n) << DCDC_REG1_REG_FBK_SEL_SHIFT) - /* Bits 9-11: Reserved */ -#define DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT (12) /* Bits 12-13: Set the current bias of low power comparator */ -#define DCDC_REG1_LP_CMP_ISRC_SEL_MASK (0x3 << DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT) -# define DCDC_REG1_LP_CMP_ISRC_SEL(n) ((uint32_t)(n) << DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT) -#define DCDC_REG1_NEGLIMIT_IN_SHIFT (14) /* Bits 14-20: Set the current bias of low power comparator */ -#define DCDC_REG1_NEGLIMIT_IN_MASK (0x3f << DCDC_REG1_NEGLIMIT_IN_SHIFT) -# define DCDC_REG1_NEGLIMIT_IN(n) ((uint32_t)(n) << DCDC_REG1_NEGLIMIT_IN_SHIFT) -#define DCDC_REG1_LOOPCTRL_HST_THRESH (1 << 21) /* Bit 21: Increase the threshold detection for common mode analog comparator */ - /* Bit 22: Reserved */ -#define DCDC_REG1_LOOPCTRL_EN_HYST (1 << 23) /* Bit 23: Enable hysteresis in switching converter */ -#define DCDC_REG1_VBG_TRIM_SHIFT (24) /* Bits 24-28: Trim bandgap voltage */ -#define DCDC_REG1_VBG_TRIM_MASK (0x1f << DCDC_REG1_VBG_TRIM_SHIFT) -# define DCDC_REG1_VBG_TRIM(n) ((uint32_t)(n) << DCDC_REG1_VBG_TRIM_SHIFT) - /* Bit 29-31: Reserved */ - -/* Register 3 */ - -#define DCDC_REG3_TRG_SHIFT (0) /* Bits 0-4: Target value of VDD_SOC, 25 mV each step */ -#define DCDC_REG3_TRG_MASK (0x1f << DCDC_REG3_TRG_SHIFT) -# define DCDC_REG3_TRG(n) ((uint32_t)(n) << DCDC_REG3_TRG_SHIFT) - /* Bit 5-7: Reserved */ -#define DCDC_REG3_TARGET_LP_SHIFT (8) /* Bits 8-10: Target value of standby (low power) mode */ -#define DCDC_REG3_TARGET_LP_MASK (0x7 << DCDC_REG3_TARGET_LP_SHIFT) -# define DCDC_REG3_TARGET_LP_(n) ((uint32_t)(n) << DCDC_REG3_TARGET_LP_SHIFT) - /* Bit 11-23: Reserved */ -#define DCDC_REG3_MINPWR_DC_HALFCLK (1 << 24) /* Bit 24: Set DCDC clock to half freqeuncy for continuous mode */ - /* Bit 25-26: Reserved */ -#define DCDC_REG3_MISC_DELAY_TIMING (1 << 27) /* Bit 27: Adjust delay to reduce ground noise */ -#define DCDC_REG3_MISC_DISABLE_FET_LOGIC (1 << 28) /* Bit 28: Datasheet: reserved? */ - /* Bit 29: Reserved */ -#define DCDC_REG3_DISABLE_STEP (1 << 30) /* Bit 30: Disable stepping */ - /* Bit 31: Reserved */ - -#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_DCDC_H */ diff --git a/arch/arm/src/imxrt/chip/imxrt_dmamux.h b/arch/arm/src/imxrt/chip/imxrt_dmamux.h deleted file mode 100644 index 6bbde542aac..00000000000 --- a/arch/arm/src/imxrt/chip/imxrt_dmamux.h +++ /dev/null @@ -1,147 +0,0 @@ -/**************************************************************************** - * arch/arm/src/imxrt/chip/imxrt_dmamux.h - * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * David Sidrane - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_DMAMUX_H -#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_DMAMUX_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip/imxrt_memorymap.h" - -#if defined(CONFIG_ARCH_FAMILY_IMXRT102x) -# include "chip/rt102x/imxrt102x_dmamux.h" -#elif defined(CONFIG_ARCH_FAMILY_IMXRT105x) -# include "chip/rt105x/imxrt105x_dmamux.h" -#elif defined(CONFIG_ARCH_FAMILY_IMXRT106x) -# include "chip/rt106x/imxrt106x_dmamux.h" -#else -# error Unrecognized i.MX RT architecture -#endif - -/**************************************************************************** - * Pre-processor definitions - ****************************************************************************/ - -#define IMXRT_DMAMUX_NCHAN 32 - -/* DMAMUX Register Offsets **************************************************/ - -#define IMXRT_DMAMUX_CHCFG_OFFSET(n) ((uintptr_t)(n) << 2) -# define IMXRT_DMAMUX_CHCFG0_OFFSET 0x0000 /* Channel configuration register 0 */ -# define IMXRT_DMAMUX_CHCFG1_OFFSET 0x0004 /* Channel configuration register 1 */ -# define IMXRT_DMAMUX_CHCFG2_OFFSET 0x0008 /* Channel configuration register 2 */ -# define IMXRT_DMAMUX_CHCFG3_OFFSET 0x000c /* Channel configuration register 3 */ -# define IMXRT_DMAMUX_CHCFG4_OFFSET 0x0010 /* Channel configuration register 4 */ -# define IMXRT_DMAMUX_CHCFG5_OFFSET 0x0014 /* Channel configuration register 5 */ -# define IMXRT_DMAMUX_CHCFG6_OFFSET 0x0018 /* Channel configuration register 6 */ -# define IMXRT_DMAMUX_CHCFG7_OFFSET 0x001c /* Channel configuration register 7 */ -# define IMXRT_DMAMUX_CHCFG8_OFFSET 0x0020 /* Channel configuration register 8 */ -# define IMXRT_DMAMUX_CHCFG9_OFFSET 0x0024 /* Channel configuration register 9 */ -# define IMXRT_DMAMUX_CHCFG10_OFFSET 0x0028 /* Channel configuration register 10 */ -# define IMXRT_DMAMUX_CHCFG11_OFFSET 0x002c /* Channel configuration register 11 */ -# define IMXRT_DMAMUX_CHCFG12_OFFSET 0x0030 /* Channel configuration register 12 */ -# define IMXRT_DMAMUX_CHCFG13_OFFSET 0x0034 /* Channel configuration register 13 */ -# define IMXRT_DMAMUX_CHCFG14_OFFSET 0x0038 /* Channel configuration register 14 */ -# define IMXRT_DMAMUX_CHCFG15_OFFSET 0x003c /* Channel configuration register 15 */ -# define IMXRT_DMAMUX_CHCFG16_OFFSET 0x0040 /* Channel configuration register 16 */ -# define IMXRT_DMAMUX_CHCFG17_OFFSET 0x0044 /* Channel configuration register 17 */ -# define IMXRT_DMAMUX_CHCFG18_OFFSET 0x0048 /* Channel configuration register 18 */ -# define IMXRT_DMAMUX_CHCFG19_OFFSET 0x004c /* Channel configuration register 19 */ -# define IMXRT_DMAMUX_CHCFG20_OFFSET 0x0050 /* Channel configuration register 20 */ -# define IMXRT_DMAMUX_CHCFG21_OFFSET 0x0054 /* Channel configuration register 21 */ -# define IMXRT_DMAMUX_CHCFG22_OFFSET 0x0058 /* Channel configuration register 22 */ -# define IMXRT_DMAMUX_CHCFG23_OFFSET 0x005c /* Channel configuration register 23 */ -# define IMXRT_DMAMUX_CHCFG24_OFFSET 0x0060 /* Channel configuration register 24 */ -# define IMXRT_DMAMUX_CHCFG25_OFFSET 0x0064 /* Channel configuration register 25 */ -# define IMXRT_DMAMUX_CHCFG26_OFFSET 0x0068 /* Channel configuration register 26 */ -# define IMXRT_DMAMUX_CHCFG27_OFFSET 0x006c /* Channel configuration register 27 */ -# define IMXRT_DMAMUX_CHCFG28_OFFSET 0x0070 /* Channel configuration register 28 */ -# define IMXRT_DMAMUX_CHCFG29_OFFSET 0x0074 /* Channel configuration register 29 */ -# define IMXRT_DMAMUX_CHCFG30_OFFSET 0x0078 /* Channel configuration register 30 */ -# define IMXRT_DMAMUX_CHCFG31_OFFSET 0x007c /* Channel configuration register 31 */ - -/* DMAMUX Register Addresses ************************************************/ - -#define IMXRT_DMAMUX_CHCFG(n) (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG_OFFSET(n)) -# define IMXRT_DMAMUX_CHCFG0 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG0_OFFSET) -# define IMXRT_DMAMUX_CHCFG1 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG1_OFFSET) -# define IMXRT_DMAMUX_CHCFG2 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG2_OFFSET) -# define IMXRT_DMAMUX_CHCFG3 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG3_OFFSET) -# define IMXRT_DMAMUX_CHCFG4 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG4_OFFSET) -# define IMXRT_DMAMUX_CHCFG5 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG5_OFFSET) -# define IMXRT_DMAMUX_CHCFG6 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG6_OFFSET) -# define IMXRT_DMAMUX_CHCFG7 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG7_OFFSET) -# define IMXRT_DMAMUX_CHCFG8 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG8_OFFSET) -# define IMXRT_DMAMUX_CHCFG9 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG9_OFFSET) -# define IMXRT_DMAMUX_CHCFG10 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG10_OFFSET) -# define IMXRT_DMAMUX_CHCFG11 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG11_OFFSET) -# define IMXRT_DMAMUX_CHCFG12 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG12_OFFSET) -# define IMXRT_DMAMUX_CHCFG13 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG13_OFFSET) -# define IMXRT_DMAMUX_CHCFG14 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG14_OFFSET) -# define IMXRT_DMAMUX_CHCFG15 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG15_OFFSET) -# define IMXRT_DMAMUX_CHCFG16 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG16_OFFSET) -# define IMXRT_DMAMUX_CHCFG17 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG17_OFFSET) -# define IMXRT_DMAMUX_CHCFG18 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG18_OFFSET) -# define IMXRT_DMAMUX_CHCFG19 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG19_OFFSET) -# define IMXRT_DMAMUX_CHCFG20 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG20_OFFSET) -# define IMXRT_DMAMUX_CHCFG21 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG21_OFFSET) -# define IMXRT_DMAMUX_CHCFG22 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG22_OFFSET) -# define IMXRT_DMAMUX_CHCFG23 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG23_OFFSET) -# define IMXRT_DMAMUX_CHCFG24 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG24_OFFSET) -# define IMXRT_DMAMUX_CHCFG25 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG25_OFFSET) -# define IMXRT_DMAMUX_CHCFG26 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG26_OFFSET) -# define IMXRT_DMAMUX_CHCFG27 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG27_OFFSET) -# define IMXRT_DMAMUX_CHCFG28 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG28_OFFSET) -# define IMXRT_DMAMUX_CHCFG29 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG29_OFFSET) -# define IMXRT_DMAMUX_CHCFG30 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG30_OFFSET) -# define IMXRT_DMAMUX_CHCFG31 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG31_OFFSET) - -/* DMAMUX Bit-Field Definitions *********************************************/ - -/* Channel configuration registers 0-31 */ - -#define DMAMUX_CHCFG_SOURCE_SHIFT (0) /* Bits 0-6: Chip-specific DMA source */ -#define DMAMUX_CHCFG_SOURCE_MASK (0x7e << DMAMUX_CHCFG_SOURCE_SHIFT) -# define DMAMUX_CHCFG_SOURCE(n) ((uint32_t)(n) << DMAMUX_CHCFG_SOURCE_SHIFT) - /* Bits 7-28: Reserved */ -#define DMAMUX_CHCFG_AON (1 << 29) /* Bit 29: DMA Channel Always Enable */ -#define DMAMUX_CHCFG_TRIG (1 << 30) /* Bit 30: DMA Channel Trigger Enable */ -#define DMAMUX_CHCFG_ENBL (1 << 31) /* Bit 31: DMA Mux Channel Enable */ - -#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_DMAMUX_H */ diff --git a/arch/arm/src/imxrt/chip/imxrt_edma.h b/arch/arm/src/imxrt/chip/imxrt_edma.h deleted file mode 100644 index 46c809e045a..00000000000 --- a/arch/arm/src/imxrt/chip/imxrt_edma.h +++ /dev/null @@ -1,1302 +0,0 @@ -/**************************************************************************************************** - * arch/arm/src/imxrt/chip/imxrt_edma.h - * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_EDMA_H -#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_EDMA_H - -/**************************************************************************************************** - * Included Files - ****************************************************************************************************/ - -#include -#include "chip/imxrt_memorymap.h" - -/**************************************************************************************************** - * Pre-processor Definitions - ****************************************************************************************************/ - -#define IMXRT_EDMA_NCHANNELS 32 - -/* eDMA Register Offsets ****************************************************************************/ - -#define IMXRT_EDMA_CR_OFFSET 0x0000 /* Control */ -#define IMXRT_EDMA_ES_OFFSET 0x0004 /* Error Status */ -#define IMXRT_EDMA_ERQ_OFFSET 0x000c /* Enable Request */ -#define IMXRT_EDMA_EEI_OFFSET 0x0014 /* Enable Error Interrupt */ -#define IMXRT_EDMA_CEEI_OFFSET 0x0018 /* Clear Enable Error Interrupt */ -#define IMXRT_EDMA_SEEI_OFFSET 0x0019 /* Set Enable Error Interrupt */ -#define IMXRT_EDMA_CERQ_OFFSET 0x001a /* Clear Enable Request */ -#define IMXRT_EDMA_SERQ_OFFSET 0x001b /* Set Enable Request */ -#define IMXRT_EDMA_CDNE_OFFSET 0x001c /* Clear DONE Status Bit */ -#define IMXRT_EDMA_SSRT_OFFSET 0x001d /* Set START Bit */ -#define IMXRT_EDMA_CERR_OFFSET 0x001e /* Clear Error */ -#define IMXRT_EDMA_CINT_OFFSET 0x001f /* Clear Interrupt Request */ -#define IMXRT_EDMA_INT_OFFSET 0x0024 /* Interrupt Request */ -#define IMXRT_EDMA_ERR_OFFSET 0x002c /* Error */ -#define IMXRT_EDMA_HRS_OFFSET 0x0034 /* Hardware Request Status */ -#define IMXRT_EDMA_EARS_OFFSET 0x0044 /* Enable Asynchronous Request in Stop */ - -#define IMXRT_EDMA_DCHPRI_OFFSET(n) (0x0100 + ((n) & ~3) + (3 - ((n) & 3))) - -#define IMXRT_EDMA_DCHPRI3_OFFSET 0x0100 /* Channel 3 Priority */ -#define IMXRT_EDMA_DCHPRI2_OFFSET 0x0101 /* Channel 2 Priority */ -#define IMXRT_EDMA_DCHPRI1_OFFSET 0x0102 /* Channel 1 Priority */ -#define IMXRT_EDMA_DCHPRI0_OFFSET 0x0103 /* Channel 0 Priority */ -#define IMXRT_EDMA_DCHPRI7_OFFSET 0x0104 /* Channel 7 Priority */ -#define IMXRT_EDMA_DCHPRI6_OFFSET 0x0105 /* Channel 6 Priority */ -#define IMXRT_EDMA_DCHPRI5_OFFSET 0x0106 /* Channel 5 Priority */ -#define IMXRT_EDMA_DCHPRI4_OFFSET 0x0107 /* Channel 4 Priority */ -#define IMXRT_EDMA_DCHPRI11_OFFSET 0x0108 /* Channel 11 Priority */ -#define IMXRT_EDMA_DCHPRI10_OFFSET 0x0109 /* Channel 10 Priority */ -#define IMXRT_EDMA_DCHPRI9_OFFSET 0x010a /* Channel 9 Priority */ -#define IMXRT_EDMA_DCHPRI8_OFFSET 0x010b /* Channel 8 Priority */ -#define IMXRT_EDMA_DCHPRI15_OFFSET 0x010c /* Channel 15 Priority */ -#define IMXRT_EDMA_DCHPRI14_OFFSET 0x010d /* Channel 14 Priority */ -#define IMXRT_EDMA_DCHPRI13_OFFSET 0x010e /* Channel 13 Priority */ -#define IMXRT_EDMA_DCHPRI12_OFFSET 0x010f /* Channel 12 Priority */ -#define IMXRT_EDMA_DCHPRI19_OFFSET 0x0110 /* Channel 19 Priority */ -#define IMXRT_EDMA_DCHPRI18_OFFSET 0x0111 /* Channel 18 Priority */ -#define IMXRT_EDMA_DCHPRI17_OFFSET 0x0112 /* Channel 17 Priority */ -#define IMXRT_EDMA_DCHPRI16_OFFSET 0x0113 /* Channel 16 Priority */ -#define IMXRT_EDMA_DCHPRI23_OFFSET 0x0114 /* Channel 23 Priority */ -#define IMXRT_EDMA_DCHPRI22_OFFSET 0x0115 /* Channel 22 Priority */ -#define IMXRT_EDMA_DCHPRI21_OFFSET 0x0116 /* Channel 21 Priority */ -#define IMXRT_EDMA_DCHPRI20_OFFSET 0x0117 /* Channel 20 Priority */ -#define IMXRT_EDMA_DCHPRI27_OFFSET 0x0118 /* Channel 27 Priority */ -#define IMXRT_EDMA_DCHPRI26_OFFSET 0x0119 /* Channel 26 Priority */ -#define IMXRT_EDMA_DCHPRI25_OFFSET 0x011a /* Channel 25 Priority */ -#define IMXRT_EDMA_DCHPRI24_OFFSET 0x011b /* Channel 24 Priority */ -#define IMXRT_EDMA_DCHPRI31_OFFSET 0x011c /* Channel 31 Priority */ -#define IMXRT_EDMA_DCHPRI30_OFFSET 0x011d /* Channel 30 Priority */ -#define IMXRT_EDMA_DCHPRI29_OFFSET 0x011e /* Channel 29 Priority */ -#define IMXRT_EDMA_DCHPRI28_OFFSET 0x011f /* Channel 28 Priority */ - -/* Transfer Control Descriptor (TCD) */ - -#define IMXRT_EDMA_TCD_OFFSET(n) (0x1000 + ((n) << 5)) -#define IMXRT_EDMA_TCD_SADDR_OFFSET 0x0000 /* TCD Source Address */ -#define IMXRT_EDMA_TCD_SOFF_OFFSET 0x0004 /* TCD Signed Source Address Offset */ -#define IMXRT_EDMA_TCD_ATTR_OFFSET 0x0006 /* TCD Transfer Attributes */ -#define IMXRT_EDMA_TCD_NBYTES_ML_OFFSET 0x0008 /* TCD Signed Minor Loop Offset / Byte Count */ -#define IMXRT_EDMA_TCD_SLAST_OFFSET 0x000c /* TCD Last Source Address Adjustment */ -#define IMXRT_EDMA_TCD_DADDR_OFFSET 0x0010 /* TCD Destination Address */ -#define IMXRT_EDMA_TCD_DOFF_OFFSET 0x0014 /* TCD Signed Destination Address Offset */ -#define IMXRT_EDMA_TCD_CITER_ELINK_OFFSET 0x0016 /* TCD Current Minor Loop Link, Major Loop Count */ -#define IMXRT_EDMA_TCD_DLASTSGA_OFFSET 0x0018 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define IMXRT_EDMA_TCD_CSR_OFFSET 0x001c /* TCD Control and Status */ -#define IMXRT_EDMA_TCD_BITER_ELINK_OFFSET 0x001e /* TCD Beginning Minor Loop Link, Major Loop Count */ - -#define IMXRT_EDMA_TCD0_SADDR_OFFSET 0x1000 /* TCD Source Address */ -#define IMXRT_EDMA_TCD0_SOFF_OFFSET 0x1004 /* TCD Signed Source Address Offset */ -#define IMXRT_EDMA_TCD0_ATTR_OFFSET 0x1006 /* TCD Transfer Attributes */ -#define IMXRT_EDMA_TCD0_NBYTES_ML_OFFSET 0x1008 /* TCD Signed Minor Loop Offset / Byte Count */ -#define IMXRT_EDMA_TCD0_SLAST_OFFSET 0x100c /* TCD Last Source Address Adjustment */ -#define IMXRT_EDMA_TCD0_DADDR_OFFSET 0x1010 /* TCD Destination Address */ -#define IMXRT_EDMA_TCD0_DOFF_OFFSET 0x1014 /* TCD Signed Destination Address Offset */ -#define IMXRT_EDMA_TCD0_CITER_ELINK_OFFSET 0x1016 /* TCD Current Minor Loop Link, Major Loop Count */ -#define IMXRT_EDMA_TCD0_DLASTSGA_OFFSET 0x1018 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define IMXRT_EDMA_TCD0_CSR_OFFSET 0x101c /* TCD Control and Status */ -#define IMXRT_EDMA_TCD0_BITER_ELINK_OFFSET 0x101e /* TCD Beginning Minor Loop Link, Major Loop Count */ - -#define IMXRT_EDMA_TCD1_SADDR_OFFSET 0x1020 /* TCD Source Address */ -#define IMXRT_EDMA_TCD1_SOFF_OFFSET 0x1024 /* TCD Signed Source Address Offset */ -#define IMXRT_EDMA_TCD1_ATTR_OFFSET 0x1026 /* TCD Transfer Attributes */ -#define IMXRT_EDMA_TCD1_NBYTES_ML_OFFSET 0x1028 /* TCD Signed Minor Loop Offset / Byte Count */ -#define IMXRT_EDMA_TCD1_SLAST_OFFSET 0x102c /* TCD Last Source Address Adjustment */ -#define IMXRT_EDMA_TCD1_DADDR_OFFSET 0x1030 /* TCD Destination Address */ -#define IMXRT_EDMA_TCD1_DOFF_OFFSET 0x1034 /* TCD Signed Destination Address Offset */ -#define IMXRT_EDMA_TCD1_CITER_ELINK_OFFSET 0x1036 /* TCD Current Minor Loop Link, Major Loop Count */ -#define IMXRT_EDMA_TCD1_DLASTSGA_OFFSET 0x1038 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define IMXRT_EDMA_TCD1_CSR_OFFSET 0x103c /* TCD Control and Status */ -#define IMXRT_EDMA_TCD1_BITER_ELINK_OFFSET 0x103e /* TCD Beginning Minor Loop Link, Major Loop Count */ - -#define IMXRT_EDMA_TCD1_SADDR_OFFSET 0x1020 /* TCD Source Address */ -#define IMXRT_EDMA_TCD1_SOFF_OFFSET 0x1024 /* TCD Signed Source Address Offset */ -#define IMXRT_EDMA_TCD1_ATTR_OFFSET 0x1026 /* TCD Transfer Attributes */ -#define IMXRT_EDMA_TCD1_NBYTES_ML_OFFSET 0x1028 /* TCD Signed Minor Loop Offset / Byte Count */ -#define IMXRT_EDMA_TCD1_SLAST_OFFSET 0x102c /* TCD Last Source Address Adjustment */ -#define IMXRT_EDMA_TCD1_DADDR_OFFSET 0x1030 /* TCD Destination Address */ -#define IMXRT_EDMA_TCD1_DOFF_OFFSET 0x1034 /* TCD Signed Destination Address Offset */ -#define IMXRT_EDMA_TCD1_CITER_ELINK_OFFSET 0x1036 /* TCD Current Minor Loop Link, Major Loop Count */ -#define IMXRT_EDMA_TCD1_DLASTSGA_OFFSET 0x1038 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define IMXRT_EDMA_TCD1_CSR_OFFSET 0x103c /* TCD Control and Status */ -#define IMXRT_EDMA_TCD1_BITER_ELINK_OFFSET 0x103e /* TCD Beginning Minor Loop Link, Major Loop Count */ - -#define IMXRT_EDMA_TCD2_SADDR_OFFSET 0x1040 /* TCD Source Address */ -#define IMXRT_EDMA_TCD2_SOFF_OFFSET 0x1044 /* TCD Signed Source Address Offset */ -#define IMXRT_EDMA_TCD2_ATTR_OFFSET 0x1046 /* TCD Transfer Attributes */ -#define IMXRT_EDMA_TCD2_NBYTES_ML_OFFSET 0x1048 /* TCD Signed Minor Loop Offset / Byte Count */ -#define IMXRT_EDMA_TCD2_SLAST_OFFSET 0x104c /* TCD Last Source Address Adjustment */ -#define IMXRT_EDMA_TCD2_DADDR_OFFSET 0x1050 /* TCD Destination Address */ -#define IMXRT_EDMA_TCD2_DOFF_OFFSET 0x1054 /* TCD Signed Destination Address Offset */ -#define IMXRT_EDMA_TCD2_CITER_ELINK_OFFSET 0x1056 /* TCD Current Minor Loop Link, Major Loop Count */ -#define IMXRT_EDMA_TCD2_DLASTSGA_OFFSET 0x1058 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define IMXRT_EDMA_TCD2_CSR_OFFSET 0x105c /* TCD Control and Status */ -#define IMXRT_EDMA_TCD2_BITER_ELINK_OFFSET 0x105e /* TCD Beginning Minor Loop Link, Major Loop Count */ - -#define IMXRT_EDMA_TCD3_SADDR_OFFSET 0x1060 /* TCD Source Address */ -#define IMXRT_EDMA_TCD3_SOFF_OFFSET 0x1064 /* TCD Signed Source Address Offset */ -#define IMXRT_EDMA_TCD3_ATTR_OFFSET 0x1066 /* TCD Transfer Attributes */ -#define IMXRT_EDMA_TCD3_NBYTES_ML_OFFSET 0x1068 /* TCD Signed Minor Loop Offset / Byte Count */ -#define IMXRT_EDMA_TCD3_SLAST_OFFSET 0x106c /* TCD Last Source Address Adjustment */ -#define IMXRT_EDMA_TCD3_DADDR_OFFSET 0x1070 /* TCD Destination Address */ -#define IMXRT_EDMA_TCD3_DOFF_OFFSET 0x1074 /* TCD Signed Destination Address Offset */ -#define IMXRT_EDMA_TCD3_CITER_ELINK_OFFSET 0x1076 /* TCD Current Minor Loop Link, Major Loop Count */ -#define IMXRT_EDMA_TCD3_DLASTSGA_OFFSET 0x1078 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define IMXRT_EDMA_TCD3_CSR_OFFSET 0x107c /* TCD Control and Status */ -#define IMXRT_EDMA_TCD3_BITER_ELINK_OFFSET 0x107e /* TCD Beginning Minor Loop Link, Major Loop Count */ - -#define IMXRT_EDMA_TCD4_SADDR_OFFSET 0x1080 /* TCD Source Address */ -#define IMXRT_EDMA_TCD4_SOFF_OFFSET 0x1084 /* TCD Signed Source Address Offset */ -#define IMXRT_EDMA_TCD4_ATTR_OFFSET 0x1086 /* TCD Transfer Attributes */ -#define IMXRT_EDMA_TCD4_NBYTES_ML_OFFSET 0x1088 /* TCD Signed Minor Loop Offset / Byte Count */ -#define IMXRT_EDMA_TCD4_SLAST_OFFSET 0x108c /* TCD Last Source Address Adjustment */ -#define IMXRT_EDMA_TCD4_DADDR_OFFSET 0x1090 /* TCD Destination Address */ -#define IMXRT_EDMA_TCD4_DOFF_OFFSET 0x1094 /* TCD Signed Destination Address Offset */ -#define IMXRT_EDMA_TCD4_CITER_ELINK_OFFSET 0x1096 /* TCD Current Minor Loop Link, Major Loop Count */ -#define IMXRT_EDMA_TCD4_DLASTSGA_OFFSET 0x1098 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define IMXRT_EDMA_TCD4_CSR_OFFSET 0x109c /* TCD Control and Status */ -#define IMXRT_EDMA_TCD4_BITER_ELINK_OFFSET 0x109e /* TCD Beginning Minor Loop Link, Major Loop Count */ - -#define IMXRT_EDMA_TCD5_SADDR_OFFSET 0x10a0 /* TCD Source Address */ -#define IMXRT_EDMA_TCD5_SOFF_OFFSET 0x10a4 /* TCD Signed Source Address Offset */ -#define IMXRT_EDMA_TCD5_ATTR_OFFSET 0x10a6 /* TCD Transfer Attributes */ -#define IMXRT_EDMA_TCD5_NBYTES_ML_OFFSET 0x10a8 /* TCD Signed Minor Loop Offset / Byte Count */ -#define IMXRT_EDMA_TCD5_SLAST_OFFSET 0x10ac /* TCD Last Source Address Adjustment */ -#define IMXRT_EDMA_TCD5_DADDR_OFFSET 0x10b0 /* TCD Destination Address */ -#define IMXRT_EDMA_TCD5_DOFF_OFFSET 0x10b4 /* TCD Signed Destination Address Offset */ -#define IMXRT_EDMA_TCD5_CITER_ELINK_OFFSET 0x10b6 /* TCD Current Minor Loop Link, Major Loop Count */ -#define IMXRT_EDMA_TCD5_DLASTSGA_OFFSET 0x10b8 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define IMXRT_EDMA_TCD5_CSR_OFFSET 0x10bc /* TCD Control and Status */ -#define IMXRT_EDMA_TCD5_BITER_ELINK_OFFSET 0x10be /* TCD Beginning Minor Loop Link, Major Loop Count */ - -#define IMXRT_EDMA_TCD6_SADDR_OFFSET 0x10c0 /* TCD Source Address */ -#define IMXRT_EDMA_TCD6_SOFF_OFFSET 0x10c4 /* TCD Signed Source Address Offset */ -#define IMXRT_EDMA_TCD6_ATTR_OFFSET 0x10c6 /* TCD Transfer Attributes */ -#define IMXRT_EDMA_TCD6_NBYTES_ML_OFFSET 0x10c8 /* TCD Signed Minor Loop Offset / Byte Count */ -#define IMXRT_EDMA_TCD6_SLAST_OFFSET 0x10cc /* TCD Last Source Address Adjustment */ -#define IMXRT_EDMA_TCD6_DADDR_OFFSET 0x10d0 /* TCD Destination Address */ -#define IMXRT_EDMA_TCD6_DOFF_OFFSET 0x10d4 /* TCD Signed Destination Address Offset */ -#define IMXRT_EDMA_TCD6_CITER_ELINK_OFFSET 0x10d6 /* TCD Current Minor Loop Link, Major Loop Count */ -#define IMXRT_EDMA_TCD6_DLASTSGA_OFFSET 0x10d8 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define IMXRT_EDMA_TCD6_CSR_OFFSET 0x10dc /* TCD Control and Status */ -#define IMXRT_EDMA_TCD6_BITER_ELINK_OFFSET 0x10de /* TCD Beginning Minor Loop Link, Major Loop Count */ - -#define IMXRT_EDMA_TCD7_SADDR_OFFSET 0x10e0 /* TCD Source Address */ -#define IMXRT_EDMA_TCD7_SOFF_OFFSET 0x10e4 /* TCD Signed Source Address Offset */ -#define IMXRT_EDMA_TCD7_ATTR_OFFSET 0x10e6 /* TCD Transfer Attributes */ -#define IMXRT_EDMA_TCD7_NBYTES_ML_OFFSET 0x10e8 /* TCD Signed Minor Loop Offset / Byte Count */ -#define IMXRT_EDMA_TCD7_SLAST_OFFSET 0x10ec /* TCD Last Source Address Adjustment */ -#define IMXRT_EDMA_TCD7_DADDR_OFFSET 0x10f0 /* TCD Destination Address */ -#define IMXRT_EDMA_TCD7_DOFF_OFFSET 0x10f4 /* TCD Signed Destination Address Offset */ -#define IMXRT_EDMA_TCD7_CITER_ELINK_OFFSET 0x10f6 /* TCD Current Minor Loop Link, Major Loop Count */ -#define IMXRT_EDMA_TCD7_DLASTSGA_OFFSET 0x10f8 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define IMXRT_EDMA_TCD7_CSR_OFFSET 0x10fc /* TCD Control and Status */ -#define IMXRT_EDMA_TCD7_BITER_ELINK_OFFSET 0x10fe /* TCD Beginning Minor Loop Link, Major Loop Count */ - -#define IMXRT_EDMA_TCD8_SADDR_OFFSET 0x1100 /* TCD Source Address */ -#define IMXRT_EDMA_TCD8_SOFF_OFFSET 0x1104 /* TCD Signed Source Address Offset */ -#define IMXRT_EDMA_TCD8_ATTR_OFFSET 0x1106 /* TCD Transfer Attributes */ -#define IMXRT_EDMA_TCD8_NBYTES_ML_OFFSET 0x1108 /* TCD Signed Minor Loop Offset / Byte Count */ -#define IMXRT_EDMA_TCD8_SLAST_OFFSET 0x110c /* TCD Last Source Address Adjustment */ -#define IMXRT_EDMA_TCD8_DADDR_OFFSET 0x1110 /* TCD Destination Address */ -#define IMXRT_EDMA_TCD8_DOFF_OFFSET 0x1114 /* TCD Signed Destination Address Offset */ -#define IMXRT_EDMA_TCD8_CITER_ELINK_OFFSET 0x1116 /* TCD Current Minor Loop Link, Major Loop Count */ -#define IMXRT_EDMA_TCD8_DLASTSGA_OFFSET 0x1118 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define IMXRT_EDMA_TCD8_CSR_OFFSET 0x111c /* TCD Control and Status */ -#define IMXRT_EDMA_TCD8_BITER_ELINK_OFFSET 0x111e /* TCD Beginning Minor Loop Link, Major Loop Count */ - -#define IMXRT_EDMA_TCD9_SADDR_OFFSET 0x1120 /* TCD Source Address */ -#define IMXRT_EDMA_TCD9_SOFF_OFFSET 0x1124 /* TCD Signed Source Address Offset */ -#define IMXRT_EDMA_TCD9_ATTR_OFFSET 0x1126 /* TCD Transfer Attributes */ -#define IMXRT_EDMA_TCD9_NBYTES_ML_OFFSET 0x1128 /* TCD Signed Minor Loop Offset / Byte Count */ -#define IMXRT_EDMA_TCD9_SLAST_OFFSET 0x112c /* TCD Last Source Address Adjustment */ -#define IMXRT_EDMA_TCD9_DADDR_OFFSET 0x1130 /* TCD Destination Address */ -#define IMXRT_EDMA_TCD9_DOFF_OFFSET 0x1134 /* TCD Signed Destination Address Offset */ -#define IMXRT_EDMA_TCD9_CITER_ELINK_OFFSET 0x1136 /* TCD Current Minor Loop Link, Major Loop Count */ -#define IMXRT_EDMA_TCD9_DLASTSGA_OFFSET 0x1138 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define IMXRT_EDMA_TCD9_CSR_OFFSET 0x113c /* TCD Control and Status */ -#define IMXRT_EDMA_TCD9_BITER_ELINK_OFFSET 0x113e /* TCD Beginning Minor Loop Link, Major Loop Count */ - -#define IMXRT_EDMA_TCD10_SADDR_OFFSET 0x1140 /* TCD Source Address */ -#define IMXRT_EDMA_TCD10_SOFF_OFFSET 0x1144 /* TCD Signed Source Address Offset */ -#define IMXRT_EDMA_TCD10_ATTR_OFFSET 0x1146 /* TCD Transfer Attributes */ -#define IMXRT_EDMA_TCD10_NBYTES_ML_OFFSET 0x1148 /* TCD Signed Minor Loop Offset / Byte Count */ -#define IMXRT_EDMA_TCD10_SLAST_OFFSET 0x114c /* TCD Last Source Address Adjustment */ -#define IMXRT_EDMA_TCD10_DADDR_OFFSET 0x1150 /* TCD Destination Address */ -#define IMXRT_EDMA_TCD10_DOFF_OFFSET 0x1154 /* TCD Signed Destination Address Offset */ -#define IMXRT_EDMA_TCD10_CITER_ELINK_OFFSET 0x1156 /* TCD Current Minor Loop Link, Major Loop Count */ -#define IMXRT_EDMA_TCD10_DLASTSGA_OFFSET 0x1158 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define IMXRT_EDMA_TCD10_CSR_OFFSET 0x115c /* TCD Control and Status */ -#define IMXRT_EDMA_TCD10_BITER_ELINK_OFFSET 0x115e /* TCD Beginning Minor Loop Link, Major Loop Count */ - -#define IMXRT_EDMA_TCD11_SADDR_OFFSET 0x1160 /* TCD Source Address */ -#define IMXRT_EDMA_TCD11_SOFF_OFFSET 0x1164 /* TCD Signed Source Address Offset */ -#define IMXRT_EDMA_TCD11_ATTR_OFFSET 0x1166 /* TCD Transfer Attributes */ -#define IMXRT_EDMA_TCD11_NBYTES_ML_OFFSET 0x1168 /* TCD Signed Minor Loop Offset / Byte Count */ -#define IMXRT_EDMA_TCD11_SLAST_OFFSET 0x116c /* TCD Last Source Address Adjustment */ -#define IMXRT_EDMA_TCD11_DADDR_OFFSET 0x1170 /* TCD Destination Address */ -#define IMXRT_EDMA_TCD11_DOFF_OFFSET 0x1174 /* TCD Signed Destination Address Offset */ -#define IMXRT_EDMA_TCD11_CITER_ELINK_OFFSET 0x1176 /* TCD Current Minor Loop Link, Major Loop Count */ -#define IMXRT_EDMA_TCD11_DLASTSGA_OFFSET 0x1178 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define IMXRT_EDMA_TCD11_CSR_OFFSET 0x117c /* TCD Control and Status */ -#define IMXRT_EDMA_TCD11_BITER_ELINK_OFFSET 0x117e /* TCD Beginning Minor Loop Link, Major Loop Count */ - -#define IMXRT_EDMA_TCD12_SADDR_OFFSET 0x1180 /* TCD Source Address */ -#define IMXRT_EDMA_TCD12_SOFF_OFFSET 0x1184 /* TCD Signed Source Address Offset */ -#define IMXRT_EDMA_TCD12_ATTR_OFFSET 0x1186 /* TCD Transfer Attributes */ -#define IMXRT_EDMA_TCD12_NBYTES_ML_OFFSET 0x1188 /* TCD Signed Minor Loop Offset / Byte Count */ -#define IMXRT_EDMA_TCD12_SLAST_OFFSET 0x118c /* TCD Last Source Address Adjustment */ -#define IMXRT_EDMA_TCD12_DADDR_OFFSET 0x1190 /* TCD Destination Address */ -#define IMXRT_EDMA_TCD12_DOFF_OFFSET 0x1194 /* TCD Signed Destination Address Offset */ -#define IMXRT_EDMA_TCD12_CITER_ELINK_OFFSET 0x1196 /* TCD Current Minor Loop Link, Major Loop Count */ -#define IMXRT_EDMA_TCD12_DLASTSGA_OFFSET 0x1198 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define IMXRT_EDMA_TCD12_CSR_OFFSET 0x119c /* TCD Control and Status */ -#define IMXRT_EDMA_TCD12_BITER_ELINK_OFFSET 0x119e /* TCD Beginning Minor Loop Link, Major Loop Count */ - -#define IMXRT_EDMA_TCD13_SADDR_OFFSET 0x11a0 /* TCD Source Address */ -#define IMXRT_EDMA_TCD13_SOFF_OFFSET 0x11a4 /* TCD Signed Source Address Offset */ -#define IMXRT_EDMA_TCD13_ATTR_OFFSET 0x11a6 /* TCD Transfer Attributes */ -#define IMXRT_EDMA_TCD13_NBYTES_ML_OFFSET 0x11a8 /* TCD Signed Minor Loop Offset / Byte Count */ -#define IMXRT_EDMA_TCD13_SLAST_OFFSET 0x11ac /* TCD Last Source Address Adjustment */ -#define IMXRT_EDMA_TCD13_DADDR_OFFSET 0x11b0 /* TCD Destination Address */ -#define IMXRT_EDMA_TCD13_DOFF_OFFSET 0x11b4 /* TCD Signed Destination Address Offset */ -#define IMXRT_EDMA_TCD13_CITER_ELINK_OFFSET 0x11b6 /* TCD Current Minor Loop Link, Major Loop Count */ -#define IMXRT_EDMA_TCD13_DLASTSGA_OFFSET 0x11b8 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define IMXRT_EDMA_TCD13_CSR_OFFSET 0x11bc /* TCD Control and Status */ -#define IMXRT_EDMA_TCD13_BITER_ELINK_OFFSET 0x11be /* TCD Beginning Minor Loop Link, Major Loop Count */ - -#define IMXRT_EDMA_TCD14_SADDR_OFFSET 0x11c0 /* TCD Source Address */ -#define IMXRT_EDMA_TCD14_SOFF_OFFSET 0x11c4 /* TCD Signed Source Address Offset */ -#define IMXRT_EDMA_TCD14_ATTR_OFFSET 0x11c6 /* TCD Transfer Attributes */ -#define IMXRT_EDMA_TCD14_NBYTES_ML_OFFSET 0x11c8 /* TCD Signed Minor Loop Offset / Byte Count */ -#define IMXRT_EDMA_TCD14_SLAST_OFFSET 0x11cc /* TCD Last Source Address Adjustment */ -#define IMXRT_EDMA_TCD14_DADDR_OFFSET 0x11d0 /* TCD Destination Address */ -#define IMXRT_EDMA_TCD14_DOFF_OFFSET 0x11d4 /* TCD Signed Destination Address Offset */ -#define IMXRT_EDMA_TCD14_CITER_ELINK_OFFSET 0x11d6 /* TCD Current Minor Loop Link, Major Loop Count */ -#define IMXRT_EDMA_TCD14_DLASTSGA_OFFSET 0x11d8 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define IMXRT_EDMA_TCD14_CSR_OFFSET 0x11dc /* TCD Control and Status */ -#define IMXRT_EDMA_TCD14_BITER_ELINK_OFFSET 0x11de /* TCD Beginning Minor Loop Link, Major Loop Count */ - -#define IMXRT_EDMA_TCD15_SADDR_OFFSET 0x11e0 /* TCD Source Address */ -#define IMXRT_EDMA_TCD15_SOFF_OFFSET 0x11e4 /* TCD Signed Source Address Offset */ -#define IMXRT_EDMA_TCD15_ATTR_OFFSET 0x11e6 /* TCD Transfer Attributes */ -#define IMXRT_EDMA_TCD15_NBYTES_ML_OFFSET 0x11e8 /* TCD Signed Minor Loop Offset / Byte Count */ -#define IMXRT_EDMA_TCD15_SLAST_OFFSET 0x11ec /* TCD Last Source Address Adjustment */ -#define IMXRT_EDMA_TCD15_DADDR_OFFSET 0x11f0 /* TCD Destination Address */ -#define IMXRT_EDMA_TCD15_DOFF_OFFSET 0x11f4 /* TCD Signed Destination Address Offset */ -#define IMXRT_EDMA_TCD15_CITER_ELINK_OFFSET 0x11f6 /* TCD Current Minor Loop Link, Major Loop Count */ -#define IMXRT_EDMA_TCD15_DLASTSGA_OFFSET 0x11f8 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define IMXRT_EDMA_TCD15_CSR_OFFSET 0x11fc /* TCD Control and Status */ -#define IMXRT_EDMA_TCD15_BITER_ELINK_OFFSET 0x11fe /* TCD Beginning Minor Loop Link, Major Loop Count */ - -#define IMXRT_EDMA_TCD16_SADDR_OFFSET 0x1200 /* TCD Source Address */ -#define IMXRT_EDMA_TCD16_SOFF_OFFSET 0x1204 /* TCD Signed Source Address Offset */ -#define IMXRT_EDMA_TCD16_ATTR_OFFSET 0x1206 /* TCD Transfer Attributes */ -#define IMXRT_EDMA_TCD16_NBYTES_ML_OFFSET 0x1208 /* TCD Signed Minor Loop Offset / Byte Count */ -#define IMXRT_EDMA_TCD16_SLAST_OFFSET 0x120c /* TCD Last Source Address Adjustment */ -#define IMXRT_EDMA_TCD16_DADDR_OFFSET 0x1210 /* TCD Destination Address */ -#define IMXRT_EDMA_TCD16_DOFF_OFFSET 0x1214 /* TCD Signed Destination Address Offset */ -#define IMXRT_EDMA_TCD16_CITER_ELINK_OFFSET 0x1216 /* TCD Current Minor Loop Link, Major Loop Count */ -#define IMXRT_EDMA_TCD16_DLASTSGA_OFFSET 0x1218 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define IMXRT_EDMA_TCD16_CSR_OFFSET 0x121c /* TCD Control and Status */ -#define IMXRT_EDMA_TCD16_BITER_ELINK_OFFSET 0x121e /* TCD Beginning Minor Loop Link, Major Loop Count */ - -#define IMXRT_EDMA_TCD17_SADDR_OFFSET 0x1220 /* TCD Source Address */ -#define IMXRT_EDMA_TCD17_SOFF_OFFSET 0x1224 /* TCD Signed Source Address Offset */ -#define IMXRT_EDMA_TCD17_ATTR_OFFSET 0x1226 /* TCD Transfer Attributes */ -#define IMXRT_EDMA_TCD17_NBYTES_ML_OFFSET 0x1228 /* TCD Signed Minor Loop Offset / Byte Count */ -#define IMXRT_EDMA_TCD17_SLAST_OFFSET 0x122c /* TCD Last Source Address Adjustment */ -#define IMXRT_EDMA_TCD17_DADDR_OFFSET 0x1230 /* TCD Destination Address */ -#define IMXRT_EDMA_TCD17_DOFF_OFFSET 0x1234 /* TCD Signed Destination Address Offset */ -#define IMXRT_EDMA_TCD17_CITER_ELINK_OFFSET 0x1236 /* TCD Current Minor Loop Link, Major Loop Count */ -#define IMXRT_EDMA_TCD17_DLASTSGA_OFFSET 0x1238 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define IMXRT_EDMA_TCD17_CSR_OFFSET 0x123c /* TCD Control and Status */ -#define IMXRT_EDMA_TCD17_BITER_ELINK_OFFSET 0x123e /* TCD Beginning Minor Loop Link, Major Loop Count */ - -#define IMXRT_EDMA_TCD18_SADDR_OFFSET 0x1240 /* TCD Source Address */ -#define IMXRT_EDMA_TCD18_SOFF_OFFSET 0x1244 /* TCD Signed Source Address Offset */ -#define IMXRT_EDMA_TCD18_ATTR_OFFSET 0x1246 /* TCD Transfer Attributes */ -#define IMXRT_EDMA_TCD18_NBYTES_ML_OFFSET 0x1248 /* TCD Signed Minor Loop Offset / Byte Count */ -#define IMXRT_EDMA_TCD18_SLAST_OFFSET 0x124c /* TCD Last Source Address Adjustment */ -#define IMXRT_EDMA_TCD18_DADDR_OFFSET 0x1250 /* TCD Destination Address */ -#define IMXRT_EDMA_TCD18_DOFF_OFFSET 0x1254 /* TCD Signed Destination Address Offset */ -#define IMXRT_EDMA_TCD18_CITER_ELINK_OFFSET 0x1256 /* TCD Current Minor Loop Link, Major Loop Count */ -#define IMXRT_EDMA_TCD18_DLASTSGA_OFFSET 0x1258 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define IMXRT_EDMA_TCD18_CSR_OFFSET 0x125c /* TCD Control and Status */ -#define IMXRT_EDMA_TCD18_BITER_ELINK_OFFSET 0x125e /* TCD Beginning Minor Loop Link, Major Loop Count */ - -#define IMXRT_EDMA_TCD19_SADDR_OFFSET 0x1260 /* TCD Source Address */ -#define IMXRT_EDMA_TCD19_SOFF_OFFSET 0x1264 /* TCD Signed Source Address Offset */ -#define IMXRT_EDMA_TCD19_ATTR_OFFSET 0x1266 /* TCD Transfer Attributes */ -#define IMXRT_EDMA_TCD19_NBYTES_ML_OFFSET 0x1268 /* TCD Signed Minor Loop Offset / Byte Count */ -#define IMXRT_EDMA_TCD19_SLAST_OFFSET 0x126c /* TCD Last Source Address Adjustment */ -#define IMXRT_EDMA_TCD19_DADDR_OFFSET 0x1270 /* TCD Destination Address */ -#define IMXRT_EDMA_TCD19_DOFF_OFFSET 0x1274 /* TCD Signed Destination Address Offset */ -#define IMXRT_EDMA_TCD19_CITER_ELINK_OFFSET 0x1276 /* TCD Current Minor Loop Link, Major Loop Count */ -#define IMXRT_EDMA_TCD19_DLASTSGA_OFFSET 0x1278 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define IMXRT_EDMA_TCD19_CSR_OFFSET 0x127c /* TCD Control and Status */ -#define IMXRT_EDMA_TCD19_BITER_ELINK_OFFSET 0x127e /* TCD Beginning Minor Loop Link, Major Loop Count */ - -#define IMXRT_EDMA_TCD20_SADDR_OFFSET 0x1280 /* TCD Source Address */ -#define IMXRT_EDMA_TCD20_SOFF_OFFSET 0x1284 /* TCD Signed Source Address Offset */ -#define IMXRT_EDMA_TCD20_ATTR_OFFSET 0x1286 /* TCD Transfer Attributes */ -#define IMXRT_EDMA_TCD20_NBYTES_ML_OFFSET 0x1288 /* TCD Signed Minor Loop Offset / Byte Count */ -#define IMXRT_EDMA_TCD20_SLAST_OFFSET 0x128c /* TCD Last Source Address Adjustment */ -#define IMXRT_EDMA_TCD20_DADDR_OFFSET 0x1290 /* TCD Destination Address */ -#define IMXRT_EDMA_TCD20_DOFF_OFFSET 0x1294 /* TCD Signed Destination Address Offset */ -#define IMXRT_EDMA_TCD20_CITER_ELINK_OFFSET 0x1296 /* TCD Current Minor Loop Link, Major Loop Count */ -#define IMXRT_EDMA_TCD20_DLASTSGA_OFFSET 0x1298 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define IMXRT_EDMA_TCD20_CSR_OFFSET 0x129c /* TCD Control and Status */ -#define IMXRT_EDMA_TCD20_BITER_ELINK_OFFSET 0x129e /* TCD Beginning Minor Loop Link, Major Loop Count */ - -#define IMXRT_EDMA_TCD21_SADDR_OFFSET 0x12a0 /* TCD Source Address */ -#define IMXRT_EDMA_TCD21_SOFF_OFFSET 0x12a4 /* TCD Signed Source Address Offset */ -#define IMXRT_EDMA_TCD21_ATTR_OFFSET 0x12a6 /* TCD Transfer Attributes */ -#define IMXRT_EDMA_TCD21_NBYTES_ML_OFFSET 0x12a8 /* TCD Signed Minor Loop Offset / Byte Count */ -#define IMXRT_EDMA_TCD21_SLAST_OFFSET 0x12ac /* TCD Last Source Address Adjustment */ -#define IMXRT_EDMA_TCD21_DADDR_OFFSET 0x12b0 /* TCD Destination Address */ -#define IMXRT_EDMA_TCD21_DOFF_OFFSET 0x12b4 /* TCD Signed Destination Address Offset */ -#define IMXRT_EDMA_TCD21_CITER_ELINK_OFFSET 0x12b6 /* TCD Current Minor Loop Link, Major Loop Count */ -#define IMXRT_EDMA_TCD21_DLASTSGA_OFFSET 0x12b8 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define IMXRT_EDMA_TCD21_CSR_OFFSET 0x12bc /* TCD Control and Status */ -#define IMXRT_EDMA_TCD21_BITER_ELINK_OFFSET 0x12be /* TCD Beginning Minor Loop Link, Major Loop Count */ - -#define IMXRT_EDMA_TCD22_SADDR_OFFSET 0x12c0 /* TCD Source Address */ -#define IMXRT_EDMA_TCD22_SOFF_OFFSET 0x12c4 /* TCD Signed Source Address Offset */ -#define IMXRT_EDMA_TCD22_ATTR_OFFSET 0x12c6 /* TCD Transfer Attributes */ -#define IMXRT_EDMA_TCD22_NBYTES_ML_OFFSET 0x12c8 /* TCD Signed Minor Loop Offset / Byte Count */ -#define IMXRT_EDMA_TCD22_SLAST_OFFSET 0x12cc /* TCD Last Source Address Adjustment */ -#define IMXRT_EDMA_TCD22_DADDR_OFFSET 0x12d0 /* TCD Destination Address */ -#define IMXRT_EDMA_TCD22_DOFF_OFFSET 0x12d4 /* TCD Signed Destination Address Offset */ -#define IMXRT_EDMA_TCD22_CITER_ELINK_OFFSET 0x12d6 /* TCD Current Minor Loop Link, Major Loop Count */ -#define IMXRT_EDMA_TCD22_DLASTSGA_OFFSET 0x12d8 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define IMXRT_EDMA_TCD22_CSR_OFFSET 0x12dc /* TCD Control and Status */ -#define IMXRT_EDMA_TCD22_BITER_ELINK_OFFSET 0x12de /* TCD Beginning Minor Loop Link, Major Loop Count */ - -#define IMXRT_EDMA_TCD23_SADDR_OFFSET 0x12e0 /* TCD Source Address */ -#define IMXRT_EDMA_TCD23_SOFF_OFFSET 0x12e4 /* TCD Signed Source Address Offset */ -#define IMXRT_EDMA_TCD23_ATTR_OFFSET 0x12e6 /* TCD Transfer Attributes */ -#define IMXRT_EDMA_TCD23_NBYTES_ML_OFFSET 0x12e8 /* TCD Signed Minor Loop Offset / Byte Count */ -#define IMXRT_EDMA_TCD23_SLAST_OFFSET 0x12ec /* TCD Last Source Address Adjustment */ -#define IMXRT_EDMA_TCD23_DADDR_OFFSET 0x12f0 /* TCD Destination Address */ -#define IMXRT_EDMA_TCD23_DOFF_OFFSET 0x12f4 /* TCD Signed Destination Address Offset */ -#define IMXRT_EDMA_TCD23_CITER_ELINK_OFFSET 0x12f6 /* TCD Current Minor Loop Link, Major Loop Count */ -#define IMXRT_EDMA_TCD23_DLASTSGA_OFFSET 0x12f8 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define IMXRT_EDMA_TCD23_CSR_OFFSET 0x12fc /* TCD Control and Status */ -#define IMXRT_EDMA_TCD23_BITER_ELINK_OFFSET 0x12fe /* TCD Beginning Minor Loop Link, Major Loop Count */ - -#define IMXRT_EDMA_TCD24_SADDR_OFFSET 0x1300 /* TCD Source Address */ -#define IMXRT_EDMA_TCD24_SOFF_OFFSET 0x1304 /* TCD Signed Source Address Offset */ -#define IMXRT_EDMA_TCD24_ATTR_OFFSET 0x1306 /* TCD Transfer Attributes */ -#define IMXRT_EDMA_TCD24_NBYTES_ML_OFFSET 0x1308 /* TCD Signed Minor Loop Offset / Byte Count */ -#define IMXRT_EDMA_TCD24_SLAST_OFFSET 0x130c /* TCD Last Source Address Adjustment */ -#define IMXRT_EDMA_TCD24_DADDR_OFFSET 0x1310 /* TCD Destination Address */ -#define IMXRT_EDMA_TCD24_DOFF_OFFSET 0x1314 /* TCD Signed Destination Address Offset */ -#define IMXRT_EDMA_TCD24_CITER_ELINK_OFFSET 0x1316 /* TCD Current Minor Loop Link, Major Loop Count */ -#define IMXRT_EDMA_TCD24_DLASTSGA_OFFSET 0x1318 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define IMXRT_EDMA_TCD24_CSR_OFFSET 0x131c /* TCD Control and Status */ -#define IMXRT_EDMA_TCD24_BITER_ELINK_OFFSET 0x131e /* TCD Beginning Minor Loop Link, Major Loop Count */ - -#define IMXRT_EDMA_TCD25_SADDR_OFFSET 0x1320 /* TCD Source Address */ -#define IMXRT_EDMA_TCD25_SOFF_OFFSET 0x1324 /* TCD Signed Source Address Offset */ -#define IMXRT_EDMA_TCD25_ATTR_OFFSET 0x1326 /* TCD Transfer Attributes */ -#define IMXRT_EDMA_TCD25_NBYTES_ML_OFFSET 0x1328 /* TCD Signed Minor Loop Offset / Byte Count */ -#define IMXRT_EDMA_TCD25_SLAST_OFFSET 0x132c /* TCD Last Source Address Adjustment */ -#define IMXRT_EDMA_TCD25_DADDR_OFFSET 0x1330 /* TCD Destination Address */ -#define IMXRT_EDMA_TCD25_DOFF_OFFSET 0x1334 /* TCD Signed Destination Address Offset */ -#define IMXRT_EDMA_TCD25_CITER_ELINK_OFFSET 0x1336 /* TCD Current Minor Loop Link, Major Loop Count */ -#define IMXRT_EDMA_TCD25_DLASTSGA_OFFSET 0x1338 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define IMXRT_EDMA_TCD25_CSR_OFFSET 0x133c /* TCD Control and Status */ -#define IMXRT_EDMA_TCD25_BITER_ELINK_OFFSET 0x133e /* TCD Beginning Minor Loop Link, Major Loop Count */ - -#define IMXRT_EDMA_TCD26_SADDR_OFFSET 0x1340 /* TCD Source Address */ -#define IMXRT_EDMA_TCD26_SOFF_OFFSET 0x1344 /* TCD Signed Source Address Offset */ -#define IMXRT_EDMA_TCD26_ATTR_OFFSET 0x1346 /* TCD Transfer Attributes */ -#define IMXRT_EDMA_TCD26_NBYTES_ML_OFFSET 0x1348 /* TCD Signed Minor Loop Offset / Byte Count */ -#define IMXRT_EDMA_TCD26_SLAST_OFFSET 0x134c /* TCD Last Source Address Adjustment */ -#define IMXRT_EDMA_TCD26_DADDR_OFFSET 0x1350 /* TCD Destination Address */ -#define IMXRT_EDMA_TCD26_DOFF_OFFSET 0x1354 /* TCD Signed Destination Address Offset */ -#define IMXRT_EDMA_TCD26_CITER_ELINK_OFFSET 0x1356 /* TCD Current Minor Loop Link, Major Loop Count */ -#define IMXRT_EDMA_TCD26_DLASTSGA_OFFSET 0x1358 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define IMXRT_EDMA_TCD26_CSR_OFFSET 0x135c /* TCD Control and Status */ -#define IMXRT_EDMA_TCD26_BITER_ELINK_OFFSET 0x135e /* TCD Beginning Minor Loop Link, Major Loop Count */ - -#define IMXRT_EDMA_TCD27_SADDR_OFFSET 0x1360 /* TCD Source Address */ -#define IMXRT_EDMA_TCD27_SOFF_OFFSET 0x1364 /* TCD Signed Source Address Offset */ -#define IMXRT_EDMA_TCD27_ATTR_OFFSET 0x1366 /* TCD Transfer Attributes */ -#define IMXRT_EDMA_TCD27_NBYTES_ML_OFFSET 0x1368 /* TCD Signed Minor Loop Offset / Byte Count */ -#define IMXRT_EDMA_TCD27_SLAST_OFFSET 0x136c /* TCD Last Source Address Adjustment */ -#define IMXRT_EDMA_TCD27_DADDR_OFFSET 0x1370 /* TCD Destination Address */ -#define IMXRT_EDMA_TCD27_DOFF_OFFSET 0x1374 /* TCD Signed Destination Address Offset */ -#define IMXRT_EDMA_TCD27_CITER_ELINK_OFFSET 0x1376 /* TCD Current Minor Loop Link, Major Loop Count */ -#define IMXRT_EDMA_TCD27_DLASTSGA_OFFSET 0x1378 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define IMXRT_EDMA_TCD27_CSR_OFFSET 0x137c /* TCD Control and Status */ -#define IMXRT_EDMA_TCD27_BITER_ELINK_OFFSET 0x137e /* TCD Beginning Minor Loop Link, Major Loop Count */ - -#define IMXRT_EDMA_TCD28_SADDR_OFFSET 0x1380 /* TCD Source Address */ -#define IMXRT_EDMA_TCD28_SOFF_OFFSET 0x1384 /* TCD Signed Source Address Offset */ -#define IMXRT_EDMA_TCD28_ATTR_OFFSET 0x1386 /* TCD Transfer Attributes */ -#define IMXRT_EDMA_TCD28_NBYTES_ML_OFFSET 0x1388 /* TCD Signed Minor Loop Offset / Byte Count */ -#define IMXRT_EDMA_TCD28_SLAST_OFFSET 0x138c /* TCD Last Source Address Adjustment */ -#define IMXRT_EDMA_TCD28_DADDR_OFFSET 0x1390 /* TCD Destination Address */ -#define IMXRT_EDMA_TCD28_DOFF_OFFSET 0x1394 /* TCD Signed Destination Address Offset */ -#define IMXRT_EDMA_TCD28_CITER_ELINK_OFFSET 0x1396 /* TCD Current Minor Loop Link, Major Loop Count */ -#define IMXRT_EDMA_TCD28_DLASTSGA_OFFSET 0x1398 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define IMXRT_EDMA_TCD28_CSR_OFFSET 0x139c /* TCD Control and Status */ -#define IMXRT_EDMA_TCD28_BITER_ELINK_OFFSET 0x139e /* TCD Beginning Minor Loop Link, Major Loop Count */ - -#define IMXRT_EDMA_TCD29_SADDR_OFFSET 0x13a0 /* TCD Source Address */ -#define IMXRT_EDMA_TCD29_SOFF_OFFSET 0x13a4 /* TCD Signed Source Address Offset */ -#define IMXRT_EDMA_TCD29_ATTR_OFFSET 0x13a6 /* TCD Transfer Attributes */ -#define IMXRT_EDMA_TCD29_NBYTES_ML_OFFSET 0x13a8 /* TCD Signed Minor Loop Offset / Byte Count */ -#define IMXRT_EDMA_TCD29_SLAST_OFFSET 0x13ac /* TCD Last Source Address Adjustment */ -#define IMXRT_EDMA_TCD29_DADDR_OFFSET 0x13b0 /* TCD Destination Address */ -#define IMXRT_EDMA_TCD29_DOFF_OFFSET 0x13b4 /* TCD Signed Destination Address Offset */ -#define IMXRT_EDMA_TCD29_CITER_ELINK_OFFSET 0x13b6 /* TCD Current Minor Loop Link, Major Loop Count */ -#define IMXRT_EDMA_TCD29_DLASTSGA_OFFSET 0x13b8 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define IMXRT_EDMA_TCD29_CSR_OFFSET 0x13bc /* TCD Control and Status */ -#define IMXRT_EDMA_TCD29_BITER_ELINK_OFFSET 0x13be /* TCD Beginning Minor Loop Link, Major Loop Count */ - -#define IMXRT_EDMA_TCD30_SADDR_OFFSET 0x13c0 /* TCD Source Address */ -#define IMXRT_EDMA_TCD30_SOFF_OFFSET 0x13c4 /* TCD Signed Source Address Offset */ -#define IMXRT_EDMA_TCD30_ATTR_OFFSET 0x13c6 /* TCD Transfer Attributes */ -#define IMXRT_EDMA_TCD30_NBYTES_ML_OFFSET 0x13c8 /* TCD Signed Minor Loop Offset / Byte Count */ -#define IMXRT_EDMA_TCD30_SLAST_OFFSET 0x13cc /* TCD Last Source Address Adjustment */ -#define IMXRT_EDMA_TCD30_DADDR_OFFSET 0x13d0 /* TCD Destination Address */ -#define IMXRT_EDMA_TCD30_DOFF_OFFSET 0x13d4 /* TCD Signed Destination Address Offset */ -#define IMXRT_EDMA_TCD30_CITER_ELINK_OFFSET 0x13d6 /* TCD Current Minor Loop Link, Major Loop Count */ -#define IMXRT_EDMA_TCD30_DLASTSGA_OFFSET 0x13d8 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define IMXRT_EDMA_TCD30_CSR_OFFSET 0x13dc /* TCD Control and Status */ -#define IMXRT_EDMA_TCD30_BITER_ELINK_OFFSET 0x13de /* TCD Beginning Minor Loop Link, Major Loop Count */ - -#define IMXRT_EDMA_TCD31_SADDR_OFFSET 0x13e0 /* TCD Source Address */ -#define IMXRT_EDMA_TCD31_SOFF_OFFSET 0x13e4 /* TCD Signed Source Address Offset */ -#define IMXRT_EDMA_TCD31_ATTR_OFFSET 0x13e6 /* TCD Transfer Attributes */ -#define IMXRT_EDMA_TCD31_NBYTES_ML_OFFSET 0x13e8 /* TCD Signed Minor Loop Offset / Byte Count */ -#define IMXRT_EDMA_TCD31_SLAST_OFFSET 0x13ec /* TCD Last Source Address Adjustment */ -#define IMXRT_EDMA_TCD31_DADDR_OFFSET 0x13f0 /* TCD Destination Address */ -#define IMXRT_EDMA_TCD31_DOFF_OFFSET 0x13f4 /* TCD Signed Destination Address Offset */ -#define IMXRT_EDMA_TCD31_CITER_ELINK_OFFSET 0x13f6 /* TCD Current Minor Loop Link, Major Loop Count */ -#define IMXRT_EDMA_TCD31_DLASTSGA_OFFSET 0x13f8 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define IMXRT_EDMA_TCD31_CSR_OFFSET 0x13fc /* TCD Control and Status */ -#define IMXRT_EDMA_TCD31_BITER_ELINK_OFFSET 0x13fe /* TCD Beginning Minor Loop Link, Major Loop Count */ - -/* eDMA Register Addresses **************************************************************************/ - -#define IMXRT_EDMA_CR (IMXRT_EDMA_BASE + IMXRT_EDMA_CR_OFFSET) -#define IMXRT_EDMA_ES (IMXRT_EDMA_BASE + IMXRT_EDMA_ES_OFFSET) -#define IMXRT_EDMA_ERQ (IMXRT_EDMA_BASE + IMXRT_EDMA_ERQ_OFFSET) -#define IMXRT_EDMA_EEI (IMXRT_EDMA_BASE + IMXRT_EDMA_EEI_OFFSET) -#define IMXRT_EDMA_CEEI (IMXRT_EDMA_BASE + IMXRT_EDMA_CEEI_OFFSET) -#define IMXRT_EDMA_SEEI (IMXRT_EDMA_BASE + IMXRT_EDMA_SEEI_OFFSET) -#define IMXRT_EDMA_CERQ (IMXRT_EDMA_BASE + IMXRT_EDMA_CERQ_OFFSET) -#define IMXRT_EDMA_SERQ (IMXRT_EDMA_BASE + IMXRT_EDMA_SERQ_OFFSET) -#define IMXRT_EDMA_CDNE (IMXRT_EDMA_BASE + IMXRT_EDMA_CDNE_OFFSET) -#define IMXRT_EDMA_SSRT (IMXRT_EDMA_BASE + IMXRT_EDMA_SSRT_OFFSET) -#define IMXRT_EDMA_CERR (IMXRT_EDMA_BASE + IMXRT_EDMA_CERR_OFFSET) -#define IMXRT_EDMA_CINT (IMXRT_EDMA_BASE + IMXRT_EDMA_CINT_OFFSET) -#define IMXRT_EDMA_INT (IMXRT_EDMA_BASE + IMXRT_EDMA_INT_OFFSET) -#define IMXRT_EDMA_ERR (IMXRT_EDMA_BASE + IMXRT_EDMA_ERR_OFFSET) -#define IMXRT_EDMA_HRS (IMXRT_EDMA_BASE + IMXRT_EDMA_HRS_OFFSET) -#define IMXRT_EDMA_EARS (IMXRT_EDMA_BASE + IMXRT_EDMA_EARS_OFFSET) - -#define IMXRT_EDMA_DCHPRI(n) (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI_OFFSET(n)) - -#define IMXRT_EDMA_DCHPRI0 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI0_OFFSET) -#define IMXRT_EDMA_DCHPRI1 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI1_OFFSET) -#define IMXRT_EDMA_DCHPRI2 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI2_OFFSET) -#define IMXRT_EDMA_DCHPRI3 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI3_OFFSET) -#define IMXRT_EDMA_DCHPRI4 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI4_OFFSET) -#define IMXRT_EDMA_DCHPRI5 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI5_OFFSET) -#define IMXRT_EDMA_DCHPRI6 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI6_OFFSET) -#define IMXRT_EDMA_DCHPRI7 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI7_OFFSET) -#define IMXRT_EDMA_DCHPRI8 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI8_OFFSET) -#define IMXRT_EDMA_DCHPRI9 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI9_OFFSET) -#define IMXRT_EDMA_DCHPRI10 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI10_OFFSET) -#define IMXRT_EDMA_DCHPRI11 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI11_OFFSET) -#define IMXRT_EDMA_DCHPRI12 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI12_OFFSET) -#define IMXRT_EDMA_DCHPRI13 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI13_OFFSET) -#define IMXRT_EDMA_DCHPRI14 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI14_OFFSET) -#define IMXRT_EDMA_DCHPRI15 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI15_OFFSET) -#define IMXRT_EDMA_DCHPRI16 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI16_OFFSET) -#define IMXRT_EDMA_DCHPRI17 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI17_OFFSET) -#define IMXRT_EDMA_DCHPRI18 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI18_OFFSET) -#define IMXRT_EDMA_DCHPRI19 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI19_OFFSET) -#define IMXRT_EDMA_DCHPRI20 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI20_OFFSET) -#define IMXRT_EDMA_DCHPRI21 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI21_OFFSET) -#define IMXRT_EDMA_DCHPRI22 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI22_OFFSET) -#define IMXRT_EDMA_DCHPRI23 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI23_OFFSET) -#define IMXRT_EDMA_DCHPRI24 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI24_OFFSET) -#define IMXRT_EDMA_DCHPRI25 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI25_OFFSET) -#define IMXRT_EDMA_DCHPRI26 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI26_OFFSET) -#define IMXRT_EDMA_DCHPRI27 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI27_OFFSET) -#define IMXRT_EDMA_DCHPRI28 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI28_OFFSET) -#define IMXRT_EDMA_DCHPRI29 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI29_OFFSET) -#define IMXRT_EDMA_DCHPRI30 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI30_OFFSET) -#define IMXRT_EDMA_DCHPRI31 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI31_OFFSET) - -#define IMXRT_EDMA_DCHPRI3_OFFSET 0x0100 /* Channel 3 Priority */ -#define IMXRT_EDMA_DCHPRI2_OFFSET 0x0101 /* Channel 2 Priority */ -#define IMXRT_EDMA_DCHPRI1_OFFSET 0x0102 /* Channel 1 Priority */ -#define IMXRT_EDMA_DCHPRI0_OFFSET 0x0103 /* Channel 0 Priority */ -#define IMXRT_EDMA_DCHPRI7_OFFSET 0x0104 /* Channel 7 Priority */ -#define IMXRT_EDMA_DCHPRI6_OFFSET 0x0105 /* Channel 6 Priority */ -#define IMXRT_EDMA_DCHPRI5_OFFSET 0x0106 /* Channel 5 Priority */ -#define IMXRT_EDMA_DCHPRI4_OFFSET 0x0107 /* Channel 4 Priority */ -#define IMXRT_EDMA_DCHPRI11_OFFSET 0x0108 /* Channel 11 Priority */ -#define IMXRT_EDMA_DCHPRI10_OFFSET 0x0109 /* Channel 10 Priority */ -#define IMXRT_EDMA_DCHPRI9_OFFSET 0x010a /* Channel 9 Priority */ -#define IMXRT_EDMA_DCHPRI8_OFFSET 0x010b /* Channel 8 Priority */ -#define IMXRT_EDMA_DCHPRI15_OFFSET 0x010c /* Channel 15 Priority */ -#define IMXRT_EDMA_DCHPRI14_OFFSET 0x010d /* Channel 14 Priority */ -#define IMXRT_EDMA_DCHPRI13_OFFSET 0x010e /* Channel 13 Priority */ -#define IMXRT_EDMA_DCHPRI12_OFFSET 0x010f /* Channel 12 Priority */ -#define IMXRT_EDMA_DCHPRI19_OFFSET 0x0110 /* Channel 19 Priority */ -#define IMXRT_EDMA_DCHPRI18_OFFSET 0x0111 /* Channel 18 Priority */ -#define IMXRT_EDMA_DCHPRI17_OFFSET 0x0112 /* Channel 17 Priority */ -#define IMXRT_EDMA_DCHPRI16_OFFSET 0x0113 /* Channel 16 Priority */ -#define IMXRT_EDMA_DCHPRI23_OFFSET 0x0114 /* Channel 23 Priority */ -#define IMXRT_EDMA_DCHPRI22_OFFSET 0x0115 /* Channel 22 Priority */ -#define IMXRT_EDMA_DCHPRI21_OFFSET 0x0116 /* Channel 21 Priority */ -#define IMXRT_EDMA_DCHPRI20_OFFSET 0x0117 /* Channel 20 Priority */ -#define IMXRT_EDMA_DCHPRI27_OFFSET 0x0118 /* Channel 27 Priority */ -#define IMXRT_EDMA_DCHPRI26_OFFSET 0x0119 /* Channel 26 Priority */ -#define IMXRT_EDMA_DCHPRI25_OFFSET 0x011a /* Channel 25 Priority */ -#define IMXRT_EDMA_DCHPRI24_OFFSET 0x011b /* Channel 24 Priority */ -#define IMXRT_EDMA_DCHPRI31_OFFSET 0x011c /* Channel 31 Priority */ -#define IMXRT_EDMA_DCHPRI30_OFFSET 0x011d /* Channel 30 Priority */ -#define IMXRT_EDMA_DCHPRI29_OFFSET 0x011e /* Channel 29 Priority */ -#define IMXRT_EDMA_DCHPRI28_OFFSET 0x011f /* Channel 28 Priority */ - -/* Transfer Control Descriptor (TCD) */ - -#define IMXRT_EDMA_TCD_BASE(n) (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD_OFFSET(n)) -#define IMXRT_EDMA_TCD_SADDR(n) (IMXRT_EDMA_TCD_BASE(n) + IMXRT_EDMA_TCD_SADDR_OFFSET) -#define IMXRT_EDMA_TCD_SOFF(n) (IMXRT_EDMA_TCD_BASE(n) + IMXRT_EDMA_TCD_SOFF_OFFSET) -#define IMXRT_EDMA_TCD_ATTR(n) (IMXRT_EDMA_TCD_BASE(n) + IMXRT_EDMA_TCD_ATTR_OFFSET) -#define IMXRT_EDMA_TCD_NBYTES_ML(n) (IMXRT_EDMA_TCD_BASE(n) + IMXRT_EDMA_TCD_NBYTES_ML_OFFSET) -#define IMXRT_EDMA_TCD_SLAST(n) (IMXRT_EDMA_TCD_BASE(n) + IMXRT_EDMA_TCD_SLAST_OFFSET) -#define IMXRT_EDMA_TCD_DADDR(n) (IMXRT_EDMA_TCD_BASE(n) + IMXRT_EDMA_TCD_DADDR_OFFSET) -#define IMXRT_EDMA_TCD_DOFF(n) (IMXRT_EDMA_TCD_BASE(n) + IMXRT_EDMA_TCD_DOFF_OFFSET) -#define IMXRT_EDMA_TCD_CITER_ELINK(n) (IMXRT_EDMA_TCD_BASE(n) + IMXRT_EDMA_TCD_CITER_ELINK_OFFSET) -#define IMXRT_EDMA_TCD_DLASTSGA(n) (IMXRT_EDMA_TCD_BASE(n) + IMXRT_EDMA_TCD_DLASTSGA_OFFSET) -#define IMXRT_EDMA_TCD_CSR(n) (IMXRT_EDMA_TCD_BASE(n) + IMXRT_EDMA_TCD_CSR_OFFSET) -#define IMXRT_EDMA_TCD_BITER_ELINK(n) (IMXRT_EDMA_TCD_BASE(n) + IMXRT_EDMA_TCD_BITER_ELINK_OFFSET) - -#define IMXRT_EDMA_TCD0_SADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD0_SADDR_OFFSET) -#define IMXRT_EDMA_TCD0_SOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD0_SOFF_OFFSET) -#define IMXRT_EDMA_TCD0_ATTR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD0_ATTR_OFFSET) -#define IMXRT_EDMA_TCD0_NBYTES_ML (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD0_NBYTES_ML_OFFSET) -#define IMXRT_EDMA_TCD0_SLAST (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD0_SLAST_OFFSET) -#define IMXRT_EDMA_TCD0_DADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD0_DADDR_OFFSET) -#define IMXRT_EDMA_TCD0_DOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD0_DOFF_OFFSET) -#define IMXRT_EDMA_TCD0_CITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD0_CITER_ELINK_OFFSET) -#define IMXRT_EDMA_TCD0_DLASTSGA (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD0_DLASTSGA_OFFSET) -#define IMXRT_EDMA_TCD0_CSR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD0_CSR_OFFSET) -#define IMXRT_EDMA_TCD0_BITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD0_BITER_ELINK_OFFSET) - -#define IMXRT_EDMA_TCD1_SADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD1_SADDR_OFFSET) -#define IMXRT_EDMA_TCD1_SOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD1_SOFF_OFFSET) -#define IMXRT_EDMA_TCD1_ATTR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD1_ATTR_OFFSET) -#define IMXRT_EDMA_TCD1_NBYTES_ML (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD1_NBYTES_ML_OFFSET) -#define IMXRT_EDMA_TCD1_SLAST (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD1_SLAST_OFFSET) -#define IMXRT_EDMA_TCD1_DADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD1_DADDR_OFFSET) -#define IMXRT_EDMA_TCD1_DOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD1_DOFF_OFFSET) -#define IMXRT_EDMA_TCD1_CITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD1_CITER_ELINK_OFFSET) -#define IMXRT_EDMA_TCD1_DLASTSGA (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD1_DLASTSGA_OFFSET) -#define IMXRT_EDMA_TCD1_CSR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD1_CSR_OFFSET) -#define IMXRT_EDMA_TCD1_BITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD1_BITER_ELINK_OFFSET) - -#define IMXRT_EDMA_TCD2_SADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD2_SADDR_OFFSET) -#define IMXRT_EDMA_TCD2_SOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD2_SOFF_OFFSET) -#define IMXRT_EDMA_TCD2_ATTR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD2_ATTR_OFFSET) -#define IMXRT_EDMA_TCD2_NBYTES_ML (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD2_NBYTES_ML_OFFSET) -#define IMXRT_EDMA_TCD2_SLAST (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD2_SLAST_OFFSET) -#define IMXRT_EDMA_TCD2_DADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD2_DADDR_OFFSET) -#define IMXRT_EDMA_TCD2_DOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD2_DOFF_OFFSET) -#define IMXRT_EDMA_TCD2_CITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD2_CITER_ELINK_OFFSET) -#define IMXRT_EDMA_TCD2_DLASTSGA (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD2_DLASTSGA_OFFSET) -#define IMXRT_EDMA_TCD2_CSR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD2_CSR_OFFSET) -#define IMXRT_EDMA_TCD2_BITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD2_BITER_ELINK_OFFSET) - -#define IMXRT_EDMA_TCD3_SADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD3_SADDR_OFFSET) -#define IMXRT_EDMA_TCD3_SOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD3_SOFF_OFFSET) -#define IMXRT_EDMA_TCD3_ATTR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD3_ATTR_OFFSET) -#define IMXRT_EDMA_TCD3_NBYTES_ML (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD3_NBYTES_ML_OFFSET) -#define IMXRT_EDMA_TCD3_SLAST (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD3_SLAST_OFFSET) -#define IMXRT_EDMA_TCD3_DADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD3_DADDR_OFFSET) -#define IMXRT_EDMA_TCD3_DOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD3_DOFF_OFFSET) -#define IMXRT_EDMA_TCD3_CITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD3_CITER_ELINK_OFFSET) -#define IMXRT_EDMA_TCD3_DLASTSGA (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD3_DLASTSGA_OFFSET) -#define IMXRT_EDMA_TCD3_CSR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD3_CSR_OFFSET) -#define IMXRT_EDMA_TCD3_BITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD3_BITER_ELINK_OFFSET) - -#define IMXRT_EDMA_TCD4_SADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD4_SADDR_OFFSET) -#define IMXRT_EDMA_TCD4_SOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD4_SOFF_OFFSET) -#define IMXRT_EDMA_TCD4_ATTR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD4_ATTR_OFFSET) -#define IMXRT_EDMA_TCD4_NBYTES_ML (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD4_NBYTES_ML_OFFSET) -#define IMXRT_EDMA_TCD4_SLAST (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD4_SLAST_OFFSET) -#define IMXRT_EDMA_TCD4_DADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD4_DADDR_OFFSET) -#define IMXRT_EDMA_TCD4_DOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD4_DOFF_OFFSET) -#define IMXRT_EDMA_TCD4_CITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD4_CITER_ELINK_OFFSET) -#define IMXRT_EDMA_TCD4_DLASTSGA (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD4_DLASTSGA_OFFSET) -#define IMXRT_EDMA_TCD4_CSR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD4_CSR_OFFSET) -#define IMXRT_EDMA_TCD4_BITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD4_BITER_ELINK_OFFSET) - -#define IMXRT_EDMA_TCD5_SADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD5_SADDR_OFFSET) -#define IMXRT_EDMA_TCD5_SOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD5_SOFF_OFFSET) -#define IMXRT_EDMA_TCD5_ATTR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD5_ATTR_OFFSET) -#define IMXRT_EDMA_TCD5_NBYTES_ML (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD5_NBYTES_ML_OFFSET) -#define IMXRT_EDMA_TCD5_SLAST (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD5_SLAST_OFFSET) -#define IMXRT_EDMA_TCD5_DADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD5_DADDR_OFFSET) -#define IMXRT_EDMA_TCD5_DOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD5_DOFF_OFFSET) -#define IMXRT_EDMA_TCD5_CITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD5_CITER_ELINK_OFFSET) -#define IMXRT_EDMA_TCD5_DLASTSGA (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD5_DLASTSGA_OFFSET) -#define IMXRT_EDMA_TCD5_CSR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD5_CSR_OFFSET) -#define IMXRT_EDMA_TCD5_BITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD5_BITER_ELINK_OFFSET) - -#define IMXRT_EDMA_TCD6_SADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD6_SADDR_OFFSET) -#define IMXRT_EDMA_TCD6_SOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD6_SOFF_OFFSET) -#define IMXRT_EDMA_TCD6_ATTR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD6_ATTR_OFFSET) -#define IMXRT_EDMA_TCD6_NBYTES_ML (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD6_NBYTES_ML_OFFSET) -#define IMXRT_EDMA_TCD6_SLAST (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD6_SLAST_OFFSET) -#define IMXRT_EDMA_TCD6_DADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD6_DADDR_OFFSET) -#define IMXRT_EDMA_TCD6_DOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD6_DOFF_OFFSET) -#define IMXRT_EDMA_TCD6_CITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD6_CITER_ELINK_OFFSET) -#define IMXRT_EDMA_TCD6_DLASTSGA (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD6_DLASTSGA_OFFSET) -#define IMXRT_EDMA_TCD6_CSR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD6_CSR_OFFSET) -#define IMXRT_EDMA_TCD6_BITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD6_BITER_ELINK_OFFSET) - -#define IMXRT_EDMA_TCD7_SADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD7_SADDR_OFFSET) -#define IMXRT_EDMA_TCD7_SOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD7_SOFF_OFFSET) -#define IMXRT_EDMA_TCD7_ATTR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD7_ATTR_OFFSET) -#define IMXRT_EDMA_TCD7_NBYTES_ML (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD7_NBYTES_ML_OFFSET) -#define IMXRT_EDMA_TCD7_SLAST (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD7_SLAST_OFFSET) -#define IMXRT_EDMA_TCD7_DADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD7_DADDR_OFFSET) -#define IMXRT_EDMA_TCD7_DOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD7_DOFF_OFFSET) -#define IMXRT_EDMA_TCD7_CITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD7_CITER_ELINK_OFFSET) -#define IMXRT_EDMA_TCD7_DLASTSGA (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD7_DLASTSGA_OFFSET) -#define IMXRT_EDMA_TCD7_CSR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD7_CSR_OFFSET) -#define IMXRT_EDMA_TCD7_BITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD7_BITER_ELINK_OFFSET) - -#define IMXRT_EDMA_TCD8_SADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD8_SADDR_OFFSET) -#define IMXRT_EDMA_TCD8_SOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD8_SOFF_OFFSET) -#define IMXRT_EDMA_TCD8_ATTR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD8_ATTR_OFFSET) -#define IMXRT_EDMA_TCD8_NBYTES_ML (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD8_NBYTES_ML_OFFSET) -#define IMXRT_EDMA_TCD8_SLAST (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD8_SLAST_OFFSET) -#define IMXRT_EDMA_TCD8_DADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD8_DADDR_OFFSET) -#define IMXRT_EDMA_TCD8_DOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD8_DOFF_OFFSET) -#define IMXRT_EDMA_TCD8_CITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD8_CITER_ELINK_OFFSET) -#define IMXRT_EDMA_TCD8_DLASTSGA (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD8_DLASTSGA_OFFSET) -#define IMXRT_EDMA_TCD8_CSR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD8_CSR_OFFSET) -#define IMXRT_EDMA_TCD8_BITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD8_BITER_ELINK_OFFSET) - -#define IMXRT_EDMA_TCD9_SADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD9_SADDR_OFFSET) -#define IMXRT_EDMA_TCD9_SOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD9_SOFF_OFFSET) -#define IMXRT_EDMA_TCD9_ATTR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD9_ATTR_OFFSET) -#define IMXRT_EDMA_TCD9_NBYTES_ML (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD9_NBYTES_ML_OFFSET) -#define IMXRT_EDMA_TCD9_SLAST (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD9_SLAST_OFFSET) -#define IMXRT_EDMA_TCD9_DADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD9_DADDR_OFFSET) -#define IMXRT_EDMA_TCD9_DOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD9_DOFF_OFFSET) -#define IMXRT_EDMA_TCD9_CITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD9_CITER_ELINK_OFFSET) -#define IMXRT_EDMA_TCD9_DLASTSGA (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD9_DLASTSGA_OFFSET) -#define IMXRT_EDMA_TCD9_CSR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD9_CSR_OFFSET) -#define IMXRT_EDMA_TCD9_BITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD9_BITER_ELINK_OFFSET) - -#define IMXRT_EDMA_TCD10_SADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD10_SADDR_OFFSET) -#define IMXRT_EDMA_TCD10_SOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD10_SOFF_OFFSET) -#define IMXRT_EDMA_TCD10_ATTR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD10_ATTR_OFFSET) -#define IMXRT_EDMA_TCD10_NBYTES_ML (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD10_NBYTES_ML_OFFSET) -#define IMXRT_EDMA_TCD10_SLAST (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD10_SLAST_OFFSET) -#define IMXRT_EDMA_TCD10_DADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD10_DADDR_OFFSET) -#define IMXRT_EDMA_TCD10_DOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD10_DOFF_OFFSET) -#define IMXRT_EDMA_TCD10_CITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD10_CITER_ELINK_OFFSET) -#define IMXRT_EDMA_TCD10_DLASTSGA (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD10_DLASTSGA_OFFSET) -#define IMXRT_EDMA_TCD10_CSR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD10_CSR_OFFSET) -#define IMXRT_EDMA_TCD10_BITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD10_BITER_ELINK_OFFSET) - -#define IMXRT_EDMA_TCD11_SADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD11_SADDR_OFFSET) -#define IMXRT_EDMA_TCD11_SOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD11_SOFF_OFFSET) -#define IMXRT_EDMA_TCD11_ATTR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD11_ATTR_OFFSET) -#define IMXRT_EDMA_TCD11_NBYTES_ML (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD11_NBYTES_ML_OFFSET) -#define IMXRT_EDMA_TCD11_SLAST (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD11_SLAST_OFFSET) -#define IMXRT_EDMA_TCD11_DADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD11_DADDR_OFFSET) -#define IMXRT_EDMA_TCD11_DOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD11_DOFF_OFFSET) -#define IMXRT_EDMA_TCD11_CITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD11_CITER_ELINK_OFFSET) -#define IMXRT_EDMA_TCD11_DLASTSGA (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD11_DLASTSGA_OFFSET) -#define IMXRT_EDMA_TCD11_CSR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD11_CSR_OFFSET) -#define IMXRT_EDMA_TCD11_BITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD11_BITER_ELINK_OFFSET) - -#define IMXRT_EDMA_TCD12_SADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD12_SADDR_OFFSET) -#define IMXRT_EDMA_TCD12_SOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD12_SOFF_OFFSET) -#define IMXRT_EDMA_TCD12_ATTR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD12_ATTR_OFFSET) -#define IMXRT_EDMA_TCD12_NBYTES_ML (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD12_NBYTES_ML_OFFSET) -#define IMXRT_EDMA_TCD12_SLAST (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD12_SLAST_OFFSET) -#define IMXRT_EDMA_TCD12_DADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD12_DADDR_OFFSET) -#define IMXRT_EDMA_TCD12_DOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD12_DOFF_OFFSET) -#define IMXRT_EDMA_TCD12_CITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD12_CITER_ELINK_OFFSET) -#define IMXRT_EDMA_TCD12_DLASTSGA (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD12_DLASTSGA_OFFSET) -#define IMXRT_EDMA_TCD12_CSR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD12_CSR_OFFSET) -#define IMXRT_EDMA_TCD12_BITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD12_BITER_ELINK_OFFSET) - -#define IMXRT_EDMA_TCD13_SADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD13_SADDR_OFFSET) -#define IMXRT_EDMA_TCD13_SOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD13_SOFF_OFFSET) -#define IMXRT_EDMA_TCD13_ATTR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD13_ATTR_OFFSET) -#define IMXRT_EDMA_TCD13_NBYTES_ML (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD13_NBYTES_ML_OFFSET) -#define IMXRT_EDMA_TCD13_SLAST (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD13_SLAST_OFFSET) -#define IMXRT_EDMA_TCD13_DADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD13_DADDR_OFFSET) -#define IMXRT_EDMA_TCD13_DOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD13_DOFF_OFFSET) -#define IMXRT_EDMA_TCD13_CITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD13_CITER_ELINK_OFFSET) -#define IMXRT_EDMA_TCD13_DLASTSGA (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD13_DLASTSGA_OFFSET) -#define IMXRT_EDMA_TCD13_CSR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD13_CSR_OFFSET) -#define IMXRT_EDMA_TCD13_BITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD13_BITER_ELINK_OFFSET) - -#define IMXRT_EDMA_TCD14_SADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD14_SADDR_OFFSET) -#define IMXRT_EDMA_TCD14_SOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD14_SOFF_OFFSET) -#define IMXRT_EDMA_TCD14_ATTR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD14_ATTR_OFFSET) -#define IMXRT_EDMA_TCD14_NBYTES_ML (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD14_NBYTES_ML_OFFSET) -#define IMXRT_EDMA_TCD14_SLAST (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD14_SLAST_OFFSET) -#define IMXRT_EDMA_TCD14_DADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD14_DADDR_OFFSET) -#define IMXRT_EDMA_TCD14_DOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD14_DOFF_OFFSET) -#define IMXRT_EDMA_TCD14_CITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD14_CITER_ELINK_OFFSET) -#define IMXRT_EDMA_TCD14_DLASTSGA (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD14_DLASTSGA_OFFSET) -#define IMXRT_EDMA_TCD14_CSR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD14_CSR_OFFSET) -#define IMXRT_EDMA_TCD14_BITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD14_BITER_ELINK_OFFSET) - -#define IMXRT_EDMA_TCD15_SADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD15_SADDR_OFFSET) -#define IMXRT_EDMA_TCD15_SOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD15_SOFF_OFFSET) -#define IMXRT_EDMA_TCD15_ATTR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD15_ATTR_OFFSET) -#define IMXRT_EDMA_TCD15_NBYTES_ML (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD15_NBYTES_ML_OFFSET) -#define IMXRT_EDMA_TCD15_SLAST (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD15_SLAST_OFFSET) -#define IMXRT_EDMA_TCD15_DADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD15_DADDR_OFFSET) -#define IMXRT_EDMA_TCD15_DOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD15_DOFF_OFFSET) -#define IMXRT_EDMA_TCD15_CITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD15_CITER_ELINK_OFFSET) -#define IMXRT_EDMA_TCD15_DLASTSGA (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD15_DLASTSGA_OFFSET) -#define IMXRT_EDMA_TCD15_CSR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD15_CSR_OFFSET) -#define IMXRT_EDMA_TCD15_BITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD15_BITER_ELINK_OFFSET) - -#define IMXRT_EDMA_TCD16_SADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD16_SADDR_OFFSET) -#define IMXRT_EDMA_TCD16_SOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD16_SOFF_OFFSET) -#define IMXRT_EDMA_TCD16_ATTR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD16_ATTR_OFFSET) -#define IMXRT_EDMA_TCD16_NBYTES_ML (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD16_NBYTES_ML_OFFSET) -#define IMXRT_EDMA_TCD16_SLAST (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD16_SLAST_OFFSET) -#define IMXRT_EDMA_TCD16_DADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD16_DADDR_OFFSET) -#define IMXRT_EDMA_TCD16_DOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD16_DOFF_OFFSET) -#define IMXRT_EDMA_TCD16_CITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD16_CITER_ELINK_OFFSET) -#define IMXRT_EDMA_TCD16_DLASTSGA (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD16_DLASTSGA_OFFSET) -#define IMXRT_EDMA_TCD16_CSR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD16_CSR_OFFSET) -#define IMXRT_EDMA_TCD16_BITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD16_BITER_ELINK_OFFSET) - -#define IMXRT_EDMA_TCD17_SADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD17_SADDR_OFFSET) -#define IMXRT_EDMA_TCD17_SOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD17_SOFF_OFFSET) -#define IMXRT_EDMA_TCD17_ATTR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD17_ATTR_OFFSET) -#define IMXRT_EDMA_TCD17_NBYTES_ML (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD17_NBYTES_ML_OFFSET) -#define IMXRT_EDMA_TCD17_SLAST (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD17_SLAST_OFFSET) -#define IMXRT_EDMA_TCD17_DADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD17_DADDR_OFFSET) -#define IMXRT_EDMA_TCD17_DOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD17_DOFF_OFFSET) -#define IMXRT_EDMA_TCD17_CITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD17_CITER_ELINK_OFFSET) -#define IMXRT_EDMA_TCD17_DLASTSGA (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD17_DLASTSGA_OFFSET) -#define IMXRT_EDMA_TCD17_CSR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD17_CSR_OFFSET) -#define IMXRT_EDMA_TCD17_BITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD17_BITER_ELINK_OFFSET) - -#define IMXRT_EDMA_TCD18_SADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD18_SADDR_OFFSET) -#define IMXRT_EDMA_TCD18_SOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD18_SOFF_OFFSET) -#define IMXRT_EDMA_TCD18_ATTR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD18_ATTR_OFFSET) -#define IMXRT_EDMA_TCD18_NBYTES_ML (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD18_NBYTES_ML_OFFSET) -#define IMXRT_EDMA_TCD18_SLAST (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD18_SLAST_OFFSET) -#define IMXRT_EDMA_TCD18_DADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD18_DADDR_OFFSET) -#define IMXRT_EDMA_TCD18_DOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD18_DOFF_OFFSET) -#define IMXRT_EDMA_TCD18_CITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD18_CITER_ELINK_OFFSET) -#define IMXRT_EDMA_TCD18_DLASTSGA (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD18_DLASTSGA_OFFSET) -#define IMXRT_EDMA_TCD18_CSR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD18_CSR_OFFSET) -#define IMXRT_EDMA_TCD18_BITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD18_BITER_ELINK_OFFSET) - -#define IMXRT_EDMA_TCD19_SADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD19_SADDR_OFFSET) -#define IMXRT_EDMA_TCD19_SOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD19_SOFF_OFFSET) -#define IMXRT_EDMA_TCD19_ATTR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD19_ATTR_OFFSET) -#define IMXRT_EDMA_TCD19_NBYTES_ML (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD19_NBYTES_ML_OFFSET) -#define IMXRT_EDMA_TCD19_SLAST (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD19_SLAST_OFFSET) -#define IMXRT_EDMA_TCD19_DADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD19_DADDR_OFFSET) -#define IMXRT_EDMA_TCD19_DOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD19_DOFF_OFFSET) -#define IMXRT_EDMA_TCD19_CITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD19_CITER_ELINK_OFFSET) -#define IMXRT_EDMA_TCD19_DLASTSGA (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD19_DLASTSGA_OFFSET) -#define IMXRT_EDMA_TCD19_CSR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD19_CSR_OFFSET) -#define IMXRT_EDMA_TCD19_BITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD19_BITER_ELINK_OFFSET) - -#define IMXRT_EDMA_TCD20_SADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD20_SADDR_OFFSET) -#define IMXRT_EDMA_TCD20_SOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD20_SOFF_OFFSET) -#define IMXRT_EDMA_TCD20_ATTR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD20_ATTR_OFFSET) -#define IMXRT_EDMA_TCD20_NBYTES_ML (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD20_NBYTES_ML_OFFSET) -#define IMXRT_EDMA_TCD20_SLAST (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD20_SLAST_OFFSET) -#define IMXRT_EDMA_TCD20_DADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD20_DADDR_OFFSET) -#define IMXRT_EDMA_TCD20_DOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD20_DOFF_OFFSET) -#define IMXRT_EDMA_TCD20_CITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD20_CITER_ELINK_OFFSET) -#define IMXRT_EDMA_TCD20_DLASTSGA (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD20_DLASTSGA_OFFSET) -#define IMXRT_EDMA_TCD20_CSR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD20_CSR_OFFSET) -#define IMXRT_EDMA_TCD20_BITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD20_BITER_ELINK_OFFSET) - -#define IMXRT_EDMA_TCD21_SADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD21_SADDR_OFFSET) -#define IMXRT_EDMA_TCD21_SOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD21_SOFF_OFFSET) -#define IMXRT_EDMA_TCD21_ATTR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD21_ATTR_OFFSET) -#define IMXRT_EDMA_TCD21_NBYTES_ML (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD21_NBYTES_ML_OFFSET) -#define IMXRT_EDMA_TCD21_SLAST (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD21_SLAST_OFFSET) -#define IMXRT_EDMA_TCD21_DADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD21_DADDR_OFFSET) -#define IMXRT_EDMA_TCD21_DOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD21_DOFF_OFFSET) -#define IMXRT_EDMA_TCD21_CITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD21_CITER_ELINK_OFFSET) -#define IMXRT_EDMA_TCD21_DLASTSGA (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD21_DLASTSGA_OFFSET) -#define IMXRT_EDMA_TCD21_CSR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD21_CSR_OFFSET) -#define IMXRT_EDMA_TCD21_BITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD21_BITER_ELINK_OFFSET) - -#define IMXRT_EDMA_TCD22_SADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD22_SADDR_OFFSET) -#define IMXRT_EDMA_TCD22_SOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD22_SOFF_OFFSET) -#define IMXRT_EDMA_TCD22_ATTR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD22_ATTR_OFFSET) -#define IMXRT_EDMA_TCD22_NBYTES_ML (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD22_NBYTES_ML_OFFSET) -#define IMXRT_EDMA_TCD22_SLAST (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD22_SLAST_OFFSET) -#define IMXRT_EDMA_TCD22_DADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD22_DADDR_OFFSET) -#define IMXRT_EDMA_TCD22_DOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD22_DOFF_OFFSET) -#define IMXRT_EDMA_TCD22_CITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD22_CITER_ELINK_OFFSET) -#define IMXRT_EDMA_TCD22_DLASTSGA (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD22_DLASTSGA_OFFSET) -#define IMXRT_EDMA_TCD22_CSR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD22_CSR_OFFSET) -#define IMXRT_EDMA_TCD22_BITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD22_BITER_ELINK_OFFSET) - -#define IMXRT_EDMA_TCD23_SADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD23_SADDR_OFFSET) -#define IMXRT_EDMA_TCD23_SOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD23_SOFF_OFFSET) -#define IMXRT_EDMA_TCD23_ATTR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD23_ATTR_OFFSET) -#define IMXRT_EDMA_TCD23_NBYTES_ML (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD23_NBYTES_ML_OFFSET) -#define IMXRT_EDMA_TCD23_SLAST (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD23_SLAST_OFFSET) -#define IMXRT_EDMA_TCD23_DADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD23_DADDR_OFFSET) -#define IMXRT_EDMA_TCD23_DOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD23_DOFF_OFFSET) -#define IMXRT_EDMA_TCD23_CITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD23_CITER_ELINK_OFFSET) -#define IMXRT_EDMA_TCD23_DLASTSGA (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD23_DLASTSGA_OFFSET) -#define IMXRT_EDMA_TCD23_CSR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD23_CSR_OFFSET) -#define IMXRT_EDMA_TCD23_BITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD23_BITER_ELINK_OFFSET) - -#define IMXRT_EDMA_TCD24_SADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD24_SADDR_OFFSET) -#define IMXRT_EDMA_TCD24_SOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD24_SOFF_OFFSET) -#define IMXRT_EDMA_TCD24_ATTR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD24_ATTR_OFFSET) -#define IMXRT_EDMA_TCD24_NBYTES_ML (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD24_NBYTES_ML_OFFSET) -#define IMXRT_EDMA_TCD24_SLAST (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD24_SLAST_OFFSET) -#define IMXRT_EDMA_TCD24_DADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD24_DADDR_OFFSET) -#define IMXRT_EDMA_TCD24_DOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD24_DOFF_OFFSET) -#define IMXRT_EDMA_TCD24_CITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD24_CITER_ELINK_OFFSET) -#define IMXRT_EDMA_TCD24_DLASTSGA (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD24_DLASTSGA_OFFSET) -#define IMXRT_EDMA_TCD24_CSR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD24_CSR_OFFSET) -#define IMXRT_EDMA_TCD24_BITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD24_BITER_ELINK_OFFSET) - -#define IMXRT_EDMA_TCD25_SADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD25_SADDR_OFFSET) -#define IMXRT_EDMA_TCD25_SOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD25_SOFF_OFFSET) -#define IMXRT_EDMA_TCD25_ATTR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD25_ATTR_OFFSET) -#define IMXRT_EDMA_TCD25_NBYTES_ML (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD25_NBYTES_ML_OFFSET) -#define IMXRT_EDMA_TCD25_SLAST (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD25_SLAST_OFFSET) -#define IMXRT_EDMA_TCD25_DADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD25_DADDR_OFFSET) -#define IMXRT_EDMA_TCD25_DOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD25_DOFF_OFFSET) -#define IMXRT_EDMA_TCD25_CITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD25_CITER_ELINK_OFFSET) -#define IMXRT_EDMA_TCD25_DLASTSGA (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD25_DLASTSGA_OFFSET) -#define IMXRT_EDMA_TCD25_CSR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD25_CSR_OFFSET) -#define IMXRT_EDMA_TCD25_BITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD25_BITER_ELINK_OFFSET) - -#define IMXRT_EDMA_TCD26_SADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD26_SADDR_OFFSET) -#define IMXRT_EDMA_TCD26_SOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD26_SOFF_OFFSET) -#define IMXRT_EDMA_TCD26_ATTR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD26_ATTR_OFFSET) -#define IMXRT_EDMA_TCD26_NBYTES_ML (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD26_NBYTES_ML_OFFSET) -#define IMXRT_EDMA_TCD26_SLAST (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD26_SLAST_OFFSET) -#define IMXRT_EDMA_TCD26_DADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD26_DADDR_OFFSET) -#define IMXRT_EDMA_TCD26_DOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD26_DOFF_OFFSET) -#define IMXRT_EDMA_TCD26_CITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD26_CITER_ELINK_OFFSET) -#define IMXRT_EDMA_TCD26_DLASTSGA (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD26_DLASTSGA_OFFSET) -#define IMXRT_EDMA_TCD26_CSR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD26_CSR_OFFSET) -#define IMXRT_EDMA_TCD26_BITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD26_BITER_ELINK_OFFSET) - -#define IMXRT_EDMA_TCD27_SADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD27_SADDR_OFFSET) -#define IMXRT_EDMA_TCD27_SOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD27_SOFF_OFFSET) -#define IMXRT_EDMA_TCD27_ATTR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD27_ATTR_OFFSET) -#define IMXRT_EDMA_TCD27_NBYTES_ML (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD27_NBYTES_ML_OFFSET) -#define IMXRT_EDMA_TCD27_SLAST (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD27_SLAST_OFFSET) -#define IMXRT_EDMA_TCD27_DADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD27_DADDR_OFFSET) -#define IMXRT_EDMA_TCD27_DOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD27_DOFF_OFFSET) -#define IMXRT_EDMA_TCD27_CITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD27_CITER_ELINK_OFFSET) -#define IMXRT_EDMA_TCD27_DLASTSGA (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD27_DLASTSGA_OFFSET) -#define IMXRT_EDMA_TCD27_CSR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD27_CSR_OFFSET) -#define IMXRT_EDMA_TCD27_BITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD27_BITER_ELINK_OFFSET) - -#define IMXRT_EDMA_TCD28_SADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD28_SADDR_OFFSET) -#define IMXRT_EDMA_TCD28_SOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD28_SOFF_OFFSET) -#define IMXRT_EDMA_TCD28_ATTR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD28_ATTR_OFFSET) -#define IMXRT_EDMA_TCD28_NBYTES_ML (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD28_NBYTES_ML_OFFSET) -#define IMXRT_EDMA_TCD28_SLAST (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD28_SLAST_OFFSET) -#define IMXRT_EDMA_TCD28_DADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD28_DADDR_OFFSET) -#define IMXRT_EDMA_TCD28_DOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD28_DOFF_OFFSET) -#define IMXRT_EDMA_TCD28_CITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD28_CITER_ELINK_OFFSET) -#define IMXRT_EDMA_TCD28_DLASTSGA (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD28_DLASTSGA_OFFSET) -#define IMXRT_EDMA_TCD28_CSR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD28_CSR_OFFSET) -#define IMXRT_EDMA_TCD28_BITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD28_BITER_ELINK_OFFSET) - -#define IMXRT_EDMA_TCD29_SADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD29_SADDR_OFFSET) -#define IMXRT_EDMA_TCD29_SOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD29_SOFF_OFFSET) -#define IMXRT_EDMA_TCD29_ATTR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD29_ATTR_OFFSET) -#define IMXRT_EDMA_TCD29_NBYTES_ML (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD29_NBYTES_ML_OFFSET) -#define IMXRT_EDMA_TCD29_SLAST (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD29_SLAST_OFFSET) -#define IMXRT_EDMA_TCD29_DADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD29_DADDR_OFFSET) -#define IMXRT_EDMA_TCD29_DOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD29_DOFF_OFFSET) -#define IMXRT_EDMA_TCD29_CITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD29_CITER_ELINK_OFFSET) -#define IMXRT_EDMA_TCD29_DLASTSGA (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD29_DLASTSGA_OFFSET) -#define IMXRT_EDMA_TCD29_CSR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD29_CSR_OFFSET) -#define IMXRT_EDMA_TCD29_BITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD29_BITER_ELINK_OFFSET) - -#define IMXRT_EDMA_TCD30_SADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD30_SADDR_OFFSET) -#define IMXRT_EDMA_TCD30_SOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD30_SOFF_OFFSET) -#define IMXRT_EDMA_TCD30_ATTR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD30_ATTR_OFFSET) -#define IMXRT_EDMA_TCD30_NBYTES_ML (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD30_NBYTES_ML_OFFSET) -#define IMXRT_EDMA_TCD30_SLAST (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD30_SLAST_OFFSET) -#define IMXRT_EDMA_TCD30_DADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD30_DADDR_OFFSET) -#define IMXRT_EDMA_TCD30_DOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD30_DOFF_OFFSET) -#define IMXRT_EDMA_TCD30_CITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD30_CITER_ELINK_OFFSET) -#define IMXRT_EDMA_TCD30_DLASTSGA (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD30_DLASTSGA_OFFSET) -#define IMXRT_EDMA_TCD30_CSR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD30_CSR_OFFSET) -#define IMXRT_EDMA_TCD30_BITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD30_BITER_ELINK_OFFSET) - -#define IMXRT_EDMA_TCD31_SADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD31_SADDR_OFFSET) -#define IMXRT_EDMA_TCD31_SOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD31_SOFF_OFFSET) -#define IMXRT_EDMA_TCD31_ATTR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD31_ATTR_OFFSET) -#define IMXRT_EDMA_TCD31_NBYTES_ML (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD31_NBYTES_ML_OFFSET) -#define IMXRT_EDMA_TCD31_SLAST (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD31_SLAST_OFFSET) -#define IMXRT_EDMA_TCD31_DADDR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD31_DADDR_OFFSET) -#define IMXRT_EDMA_TCD31_DOFF (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD31_DOFF_OFFSET) -#define IMXRT_EDMA_TCD31_CITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD31_CITER_ELINK_OFFSET) -#define IMXRT_EDMA_TCD31_DLASTSGA (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD31_DLASTSGA_OFFSET) -#define IMXRT_EDMA_TCD31_CSR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD31_CSR_OFFSET) -#define IMXRT_EDMA_TCD31_BITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD31_BITER_ELINK_OFFSET) - -/* eDMA Bit-Field Definitions ***********************************************************************/ - -/* Control */ - /* Bit 0: Reserved */ -#define EDMA_CR_EDBG (1 << 1) /* Bit 1: Enable Debug */ -#define EDMA_CR_ERCA (1 << 2) /* Bit 2: Enable Round Robin Channel Arbitration */ -#define EDMA_CR_ERGA (1 << 3) /* Bit 3: Enable Round Robin Group Arbitration */ -#define EDMA_CR_HOE (1 << 4) /* Bit 4: Halt On Error */ -#define EDMA_CR_HALT (1 << 5) /* Bit 5: Halt DMA Operations */ -#define EDMA_CR_CLM (1 << 6) /* Bit 6: Continuous Link Mode */ -#define EDMA_CR_EMLM (1 << 7) /* Bit 7: Enable Minor Loop Mapping */ -#define EDMA_CR_GRP0PRI (1 << 8) /* Bit 8: Channel Group 0 Priority */ - /* Bit 9: Reserved */ -#define EDMA_CR_GRP1PRI (1 << 10) /* Bit 10: Channel Group 1 Priority */ - /* Bits 11-15: Reserved */ -#define EDMA_CR_ECX (1 << 16) /* Bit 16: Error Cancel Transfer */ -#define EDMA_CR_CX (1 << 17) /* Bit 17: Cancel Transfer */ - /* Bits 18-23: Reserved */ - /* Bits 24-30: eDMA version number (reserved) */ -#define EDMA_CR_ACTIVE (1 << 31) /* Bit 31: DMA Active Status */ - -/* Error Status */ - -#define EDMA_ES_DBE (1 << 0) /* Bit 0: Destination Bus Error */ -#define EDMA_ES_SBE (1 << 1) /* Bit 1: Source Bus Error */ -#define EDMA_ES_SGE (1 << 2) /* Bit 2: Scatter/Gather Configuration Error */ -#define EDMA_ES_NCE (1 << 3) /* Bit 3: NBYTES/CITER Configuration Error */ -#define EDMA_ES_DOE (1 << 4) /* Bit 4: Destination Offset Error */ -#define EDMA_ES_DAE (1 << 5) /* Bit 5: Destination Address Error */ -#define EDMA_ES_SOE (1 << 6) /* Bit 6: Source Offset Error */ -#define EDMA_ES_SAE (1 << 7) /* Bit 7: Source Address Error */ -#define EDMA_ES_ERRCHN_SHIFT (8) /* Bits 8-12: Error Channel Number or - * Canceled Channel Number */ -#define EDMA_ES_ERRCHN_MASK (0x1f << EDMA_ES_ERRCHN_SHIFT) - /* Bit 13: Reserved */ -#define EDMA_ES_CPE (1 << 14) /* Bit 14: Channel Priority Error */ -#define EDMA_ES_GPE (1 << 15) /* Bit 15: Group Priority Error */ -#define EDMA_ES_ECX (1 << 16) /* Bit 16: Transfer Canceled */ - /* Bits 17-30: Reserved */ -#define EDMA_ES_VLD (1 << 31) /* Bit 31: Logical OR of all ERR status bits */ - -/* Enable Request */ - -#define EDMA_ERQ(n) ((uint32_t)1 << (n)) /* Bit n: Enable DMA request n */ - -/* Enable Error Interrupt */ - -#define EDMA_EEI(n) ((uint32_t)1 << (n)) /* Bit n: Enable error interrupt n */ - -/* Clear Enable Error Interrupt */ - -#define EDMA_CEEI_SHIFT (0) /* Bits 0-4: Clear Enable Error Interrupt */ -#define EDMA_CEEI_MASK (0x1f << EDMA_CEEI_SHIFT) -# define EDMA_CEEI(n) ((uint32_t)(n) << EDMA_CEEI_SHIFT) - /* Bit 5: Reserved */ -#define EDMA_CEEI_CAEE (1 << 6) /* Bit 6: Clear All Enable Error Interrupts */ -#define EDMA_CEEI_NOP (1 << 7) /* Bit 7: No Op enable */ - -/* Set Enable Error Interrupt */ - -#define EDMA_SEEI_SHIFT (0) /* Bits 0-4: Set Enable Error Interrupt */ -#define EDMA_SEEI_MASK (0x1f << EDMA_SEEI_SHIFT) -# define EDMA_SEEI(n) ((uint32_t)(n) << EDMA_SEEI_SHIFT) - /* Bit 5: Reserved */ -#define EDMA_SEEI_SAEE (1 << 6) /* Bit 6: Set All Enable Error Interrupts */ -#define EDMA_SEEI_NOP (1 << 7) /* Bit 7: No Op enable */ - -/* Clear Enable Request */ - -#define EDMA_CERQ_SHIFT (0) /* Bits 0-4: Clear Enable Request */ -#define EDMA_CERQ_MASK (0x1f << EDMA_CERQ_SHIFT) -# define EDMA_CERQ(n) ((uint32_t)(n) << EDMA_CERQ_SHIFT) - /* Bit 5: Reserved */ -#define EDMA_CERQ_CAER (1 << 6) /* Bit 6: Clear All Enable Requests */ -#define EDMA_CERQ_NOP (1 << 7) /* Bit 7: No Op enable */ - -/* Set Enable Request */ - -#define EDMA_SERQ_SHIFT (0) /* Bits 0-4: Set Enable Request */ -#define EDMA_SERQ_MASK (0x1f << EDMA_SERQ_SHIFT) -# define EDMA_SERQ(n) ((uint32_t)(n) << EDMA_SERQ_SHIFT) - /* Bit 5: Reserved */ -#define EDMA_SERQ_SAER (1 << 6) /* Bit 6: Set All Enable Requests */ -#define EDMA_SERQ_NOP (1 << 7) /* Bit 7: No Op enable */ - -/* Clear DONE Status Bit */ - -#define EDMA_CDNE_SHIFT (0) /* Bits 0-4: Clear DONE Bit */ -#define EDMA_CDNE_MASK (0x1f << EDMA_CDNE_SHIFT) -# define EDMA_CDNE(n) ((uint32_t)(n) << EDMA_CDNE_SHIFT) - /* Bit 5: Reserved */ -#define EDMA_CDNE_CADN (1 << 6) /* Bit 6: Clears All DONE Bits */ -#define EDMA_CDNE_NOP (1 << 7) /* Bit 7: No Op enable */ - -/* Set START Bit */ - -#define EDMA_SSRT_SHIFT (0) /* Bits 0-4: Set START Bit */ -#define EDMA_SSRT_MASK (0x1f << EDMA_SSRT_SHIFT) -# define EDMA_SSRT(n) ((uint32_t)(n) << EDMA_SSRT_SHIFT) - /* Bit 5: Reserved */ -#define EDMA_SSRT_SAST (1 << 6) /* Bit 6: Set All START Bits (activates all channels) */ -#define EDMA_SSRT_NOP (1 << 7) /* Bit 7: No Op enable */ - -/* Clear Error */ - -#define EDMA_CERR_SHIFT (0) /* Bits 0-4: Clear Error Indicator */ -#define EDMA_CERR_MASK (0x1f << EDMA_CERR_SHIFT) -# define EDMA_CERR(n) ((uint32_t)(n) << EDMA_CERR_SHIFT) - /* Bit 5: Reserved */ -#define EDMA_CERR_CAEI (1 << 6) /* Bit 6: Clear All Error Indicators */ -#define EDMA_CERR_NOP (1 << 7) /* Bit 7: No Op enable */ - -/* Clear Interrupt Request */ -#define EDMA_CINT_ - -#define EDMA_CINT_SHIFT (0) /* Bits 0-4: Clear Interrupt Request */ -#define EDMA_CINT_MASK (0x1f << EDMA_CINT_SHIFT) -# define EDMA_CINT(n) ((uint32_t)(n) << EDMA_CINT_SHIFT) - /* Bit 5: Reserved */ -#define EDMA_CINT_CAIR (1 << 6) /* Bit 6: Clear All Interrupt Requests */ -#define EDMA_CINT_NOP (1 << 7) /* Bit 7: No Op enable */ - -/* Interrupt Request */ - -#define EDMA_INT(n) ((uint32_t)1 << (n)) /* Bit n: Interrupt Request n */ - -/* Error */ - -#define EDMA_ERR(n) ((uint32_t)1 << (n)) /* Bit n: Error In Channel n */ - -/* Hardware Request Status */ - -#define EDMA_HRS(n) ((uint32_t)1 << (n)) /* Bit n: Hardware Request Status - * Channel n */ -/* Enable Asynchronous Request in Stop */ - -#define EDMA_EARS(n) ((uint32_t)1 << (n)) /* Bit n: Enable asynchronous DMA - * request in stop mode for channel n */ -/* Channel n Priority */ - -#define EDMA_DCHPRI_CHPRI_SHIFT (0) /* Bits 0-3: Channel n Arbitration Priority */ -#define EDMA_DCHPRI_CHPRI_MASK (15 << EDMA_DCHPRI_CHPRI_SHIFT) -# define EDMA_DCHPRI_CHPRI(n) ((uint32_t)(n) << EDMA_DCHPRI_CHPRI_SHIFT) -#define EDMA_DCHPRI_GRPPRI_SHIFT (4) /* Bits 4-5: Channel n Current Group Priority */ -#define EDMA_DCHPRI_GRPPRI_MASK (3 << EDMA_DCHPRI_GRPPRI_SHIFT) -# define EDMA_DCHPRI_GRPPRI(n) ((uint32_t)(n) << EDMA_DCHPRI_GRPPRI_SHIFT) -#define EDMA_DCHPRI_DPA (1 << 6) /* Bit 6: Disable Preempt Ability */ -#define EDMA_DCHPRI_ECP (1 << 7) /* Bit 7: Enable Channel Preemption */ - -/* TCD Source Address (32-bit address) */ -/* TCD Signed Source Address Offset (16-bit offset) */ - -/* TCD Transfer Attributes */ - -#define TCD_ATTR_SIZE_8BIT (0) /* 8-bit */ -#define TCD_ATTR_SIZE_16BIT (1) /* 16-bit */ -#define TCD_ATTR_SIZE_32BIT (2) /* 32-bit */ -#define TCD_ATTR_SIZE_64BIT (3) /* 64-bit */ -#define TCD_ATTR_SIZE_256BIT (5) /* 32-byte burst (4 beats of 64 bits) */ - -#define EDMA_TCD_ATTR_DSIZE_SHIFT (0) /* Bits 0-2: Destination data transfer size */ -#define EDMA_TCD_ATTR_DSIZE_MASK (7 << EDMA_TCD_ATTR_DSIZE_SHIFT) -# define EDMA_TCD_ATTR_DSIZE(n) ((uint32_t)(n) << EDMA_TCD_ATTR_DSIZE_SHIFT) /* 8-bit */ -# define EDMA_TCD_ATTR_DSIZE_8BIT (TCD_ATTR_SIZE_8BIT << EDMA_TCD_ATTR_DSIZE_SHIFT) /* 8-bit */ -# define EDMA_TCD_ATTR_DSIZE_16BIT (TCD_ATTR_SIZE_16BIT << EDMA_TCD_ATTR_DSIZE_SHIFT) /* 16-bit */ -# define EDMA_TCD_ATTR_DSIZE_32BIT (TCD_ATTR_SIZE_32BIT << EDMA_TCD_ATTR_DSIZE_SHIFT) /* 32-bit */ -# define EDMA_TCD_ATTR_DSIZE_64BIT (TCD_ATTR_SIZE_64BIT << EDMA_TCD_ATTR_DSIZE_SHIFT) /* 64-bit */ -# define EDMA_TCD_ATTR_DSIZE_256BIT (TCD_ATTR_SIZE_256BIT << EDMA_TCD_ATTR_DSIZE_SHIFT) /* 32-byte burst */ -#define EDMA_TCD_ATTR_DMOD_SHIFT (3) /* Bits 3-7: Destination Address Modulo */ -#define EDMA_TCD_ATTR_DMOD_MASK (31 << EDMA_TCD_ATTR_DMOD_SHIFT) -# define EDMA_TCD_ATTR_DMOD(n) ((uint32_t)(n) << EDMA_TCD_ATTR_DMOD_SHIFT) -#define EDMA_TCD_ATTR_SSIZE_SHIFT (8) /* Bits 8-10: Source data transfer size */ -#define EDMA_TCD_ATTR_SSIZE_MASK (7 << EDMA_TCD_ATTR_SSIZE_SHIFT) -# define EDMA_TCD_ATTR_SSIZE(n) ((uint32_t)(n) << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 8-bit */ -# define EDMA_TCD_ATTR_SSIZE_8BIT (TCD_ATTR_SIZE_8BIT << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 8-bit */ -# define EDMA_TCD_ATTR_SSIZE_16BIT (TCD_ATTR_SIZE_16BIT << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 16-bit */ -# define EDMA_TCD_ATTR_SSIZE_32BIT (TCD_ATTR_SIZE_32BIT << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 32-bit */ -# define EDMA_TCD_ATTR_SSIZE_64BIT (TCD_ATTR_SIZE_64BIT << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 64-bit */ -# define EDMA_TCD_ATTR_SSIZE_256BIT (TCD_ATTR_SIZE_256BIT << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 32-byte burst */ -#define EDMA_TCD_ATTR_SMOD_SHIFT (11) /* Bits 11-15: Source Address Modulo */ -#define EDMA_TCD_ATTR_SMOD_MASK (31 << EDMA_TCD_ATTR_SMOD_SHIFT) -# define EDMA_TCD_ATTR_SMOD(n) ((uint32_t)(n) << EDMA_TCD_ATTR_SMOD_SHIFT) - -/* TCD Signed Minor Loop Offset / Byte Count */ -/* Minor Byte Count (Minor Loop Mapping Disabled -- 32-bit byte count) */ - -/* TCD Signed Minor Loop Offset / Byte Count */ -/* Minor Byte Count (Minor Loop Mapping Enabled, offset disabled) */ - -#define EDMA_TCD_NBYTES_ML_NBYTES_SHIFT (0) /* Bits 0-29: Minor Byte Transfer Count */ -#define EDMA_TCD_NBYTES_ML_NBYTES_MASK (0x3fffffff << EDMA_TCD_NBYTES_ML_NBYTES_SHIFT) -# define EDMA_TCD_NBYTES_ML_NBYTES(n) ((uint32_t)(n) << EDMA_TCD_NBYTES_ML_NBYTES_SHIFT) -#define EDMA_TCD_NBYTES_ML_DMLOE (1 << 30) /* Bit 30: Destination Minor Loop Offset enable */ -#define EDMA_TCD_NBYTES_ML_SMLOE (1 << 31) /* Bit 31: Source Minor Loop Offset Enable */ - -/* TCD Signed Minor Loop Offset / Byte Count */ -/* Minor Byte Count (Minor Loop Mapping Enabled, offset enabled) */ - -#define EDMA_TCD_NBYTES_MLOFF_NBYTES_SHIFT (0) /* Bits 0-9: Minor Byte Transfer Count */ -#define EDMA_TCD_NBYTES_MLOFF_NBYTES_MASK (0x3ff << EDMA_TCD_NBYTES_MLOFF_NBYTES_SHIFT) -# define EDMA_TCD_NBYTES_MLOFF_NBYTES(n) ((uint32_t)(n) << EDMA_TCD_NBYTES_MLOFF_NBYTES_SHIFT) -#define EDMA_TCD_NBYTES_MLOFF_MLOFF_SHIFT (10) /* Bits 10-29: Minor Byte Transfer Count */ -#define EDMA_TCD_NBYTES_MLOFF_MLOFF_MASK (0xfffff << EDMA_TCD_NBYTES_MLOFF_MLOFF_SHIFT) -# define EDMA_TCD_NBYTES_MLOFF_MLOFF(n) ((uint32_t)(n) << EDMA_TCD_NBYTES_MLOFF_MLOFF_SHIFT) -#define EDMA_TCD_NBYTES_MLOFF_DMLOE (1 << 30) /* Bit 30: Destination Minor Loop Offset enable */ -#define EDMA_TCD_NBYTES_MLOFF_SMLOE (1 << 31) /* Bit 31: Source Minor Loop Offset Enable */ - -/* TCD Last Source Address Adjustment (32-bit address adjustment) */ -/* TCD Destination Address (32-bit address) */ -/* TCD Signed Destination Address Offset (32-bit signed address offset) */ - -/* TCD Current Minor Loop Link, Major Loop Count (Channel linking disabled) */ - -#define EDMA_TCD_CITER_CITER_SHIFT (0) /* Bit 0-14: Starting Major Iteration Count */ -#define EDMA_TCD_CITER_CITER_MASK (0x7fff << EDMA_TCD_CITER_CITER_SHIFT) -# define EDMA_TCD_CITER_CITER(n) ((uint32_t)(n) << EDMA_TCD_CITER_CITER_SHIFT) -#define EDMA_TCD_CITER_ELINK (1 << 15) /* Bit 15: Enable channel-to-channel linking - * on minor-loop complete */ - -/* TCD Current Minor Loop Link, Major Loop Count (Channel linking enabled) */ - -#define EDMA_TCD_CITER_ELINK_CITER_SHIFT (0) /* Bit 0-8: Current major iteration count */ -#define EDMA_TCD_CITER_ELINK_CITER_MASK (0x1ff << EDMA_TCD_CITER_ELINK_CITER_SHIFT) -# define EDMA_TCD_CITER_ELINK_CITER(n) ((uint32_t)(n) << EDMA_TCD_CITER_ELINK_CITER_SHIFT) -#define EDMA_TCD_CITER_ELINK_LINKCH_SHIFT (9) /* Bit 9-13: Minor Loop Link Channel Number */ -#define EDMA_TCD_CITER_ELINK_LINKCH_MASK (31 << EDMA_TCD_CITER_ELINK_LINKCH_SHIFT) -# define EDMA_TCD_CITER_ELINK_LINKCH(n) ((uint32_t)(n) << EDMA_TCD_CITER_ELINK_LINKCH_SHIFT) - /* Bit 14: Reserved */ -#define EDMA_TCD_CITER_ELINK_ELINK (1 << 15) /* Bit 15: Enable channel-to-channel linking - * on minor-loop complete */ - -/* TCD Last Destination Address Adjustment/Scatter Gather Address (32-bit address) */ - -/* TCD Control and Status */ - -#define EDMA_TCD_CSR_START (1 << 0) /* Bit 0: Channel Start */ -#define EDMA_TCD_CSR_INTMAJOR (1 << 1) /* Bit 1: Enable an interrupt when major - * iteration count completes */ -#define EDMA_TCD_CSR_INTHALF (1 << 2) /* Bit 2: Enable an interrupt when major - * counter is half complete */ -#define EDMA_TCD_CSR_DREQ (1 << 3) /* Bit 3: Disable Request */ -#define EDMA_TCD_CSR_ESG (1 << 4) /* Bit 4: Enable Scatter/Gather Processing */ -#define EDMA_TCD_CSR_MAJORELINK (1 << 5) /* Bit 5: Enable channel-to-channel linking - * on major loop complete */ -#define EDMA_TCD_CSR_ACTIVE (1 << 6) /* Bit 6: Channel Active */ -#define EDMA_TCD_CSR_DONE (1 << 7) /* Bit 7: Channel Done */ -#define EDMA_TCD_CSR_MAJORLINKCH_SHIFT (8) /* Bits 8-12: Major Loop Link Channel Number */ -#define EDMA_TCD_CSR_MAJORLINKCH_MASK (31 << EDMA_TCD_CSR_MAJORLINKCH_SHIFT) -# define EDMA_TCD_CSR_MAJORLINKCH(n) ((uint32_t)(n) << EDMA_TCD_CSR_MAJORLINKCH_SHIFT) - /* Bit 13: Reserved */ -#define EDMA_TCD_CSR_BWC_SHIFT (14) /* Bits 14-15: Bandwidth Control */ -#define EDMA_TCD_CSR_BWC_MASK (3 << EDMA_TCD_CSR_BWC_SHIFT) -# define EDMA_TCD_CSR_BWC_NONE (0 << EDMA_TCD_CSR_BWC_SHIFT) /* No eDMA engine stalls */ -# define EDMA_TCD_CSR_BWC_4CYCLES (2 << EDMA_TCD_CSR_BWC_SHIFT) /* eDMA engine stalls for 4 - * cycles after each R/W */ -# define EDMA_TCD_CSR_BWC_8CYCLES (3 << EDMA_TCD_CSR_BWC_SHIFT) /* eDMA engine stalls for 8 - * cycles after each R/W */ - -/* TCD Beginning Minor Loop Link, Major Loop Count (Channel linking disabled) */ - -#define EDMA_TCD_BITER_BITER_SHIFT (0) /* Bit 0-14: Starting Major Iteration Count */ -#define EDMA_TCD_BITER_BITER_MASK (0x7fff << EDMA_TCD_BITER_BITER_SHIFT) -# define EDMA_TCD_BITER_BITER(n) ((uint32_t)(n) << EDMA_TCD_BITER_BITER_SHIFT) -#define EDMA_TCD_BITER_ELINK (1 << 15) /* Bit 15: Enable channel-to-channel linking - * on minor-loop complete */ - -/* TCD Beginning Minor Loop Link, Major Loop Count (Channel linking enabled) */ - -#define EDMA_TCD_BITER_ELINK_BITER_SHIFT (0) /* Bit 0-8: Current major iteration count */ -#define EDMA_TCD_BITER_ELINK_BITER_MASK (0x1ff << EDMA_TCD_BITER_ELINK_BITER_SHIFT) -# define EDMA_TCD_BITER_ELINK_BITER(n) ((uint32_t)(n) << EDMA_TCD_BITER_ELINK_BITER_SHIFT) -#define EDMA_TCD_BITER_ELINK_LINKCH_SHIFT (9) /* Bit 9-13: Link Channel Number */ -#define EDMA_TCD_BITER_ELINK_LINKCH_MASK (31 << EDMA_TCD_BITER_ELINK_LINKCH_SHIFT) -# define EDMA_TCD_BITER_ELINK_LINKCH(n) ((uint32_t)(n) << EDMA_TCD_BITER_ELINK_LINKCH_SHIFT) - /* Bit 14: Reserved */ -#define EDMA_TCD_BITER_ELINK_ELINK (1 << 15) /* Bit 15: Enable channel-to-channel linking - * on minor-loop complete */ - -/**************************************************************************************************** - * Public Types - ****************************************************************************************************/ - -/* In-memory representation of the 32-byte Transfer Control Descriptor (TCD) */ - -struct imxrt_edmatcd_s -{ - uint32_t saddr; /* Offset: 0x0000 TCD Source Address */ - uint16_t soff; /* Offset: 0x0004 TCD Signed Source Address Offset */ - uint16_t attr; /* Offset: 0x0006 TCD Transfer Attributes */ - uint32_t nbytes; /* Offset: 0x0008 TCD Signed Minor Loop Offset / Byte Count */ - uint32_t slast; /* Offset: 0x000c TCD Last Source Address Adjustment */ - uint32_t daddr; /* Offset: 0x0010 TCD Destination Address */ - uint16_t doff; /* Offset: 0x0014 TCD Signed Destination Address Offset */ - uint16_t citer; /* Offset: 0x0016 TCD Current Minor Loop Link, Major Loop Count */ - uint32_t dlastsga; /* Offset: 0x0018 TCD Last Destination Address Adjustment/Scatter Gather Address */ - uint16_t csr; /* Offset: 0x001c TCD Control and Status */ - uint16_t biter; /* Offset: 0x001e TCD Beginning Minor Loop Link, Major Loop Count */ -}; - -#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_EDMA_H */ diff --git a/arch/arm/src/imxrt/chip/imxrt_enet.h b/arch/arm/src/imxrt/chip/imxrt_enet.h deleted file mode 100644 index 4aa725475ca..00000000000 --- a/arch/arm/src/imxrt/chip/imxrt_enet.h +++ /dev/null @@ -1,672 +0,0 @@ -/***************************************************************************** - * arch/arm/src/imxrt/chip/imxrt_enet.h - * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_ENET_H -#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_ENET_H - -/***************************************************************************** - * Included Files - *****************************************************************************/ - -#include - -#include "chip.h" - -/***************************************************************************** - * Pre-processor Definitions - *****************************************************************************/ - -/* Register Offsets **********************************************************/ - -#define IMXRT_ENET_EIR_OFFSET 0x0004 /* Interrupt Event Register */ -#define IMXRT_ENET_EIMR_OFFSET 0x0008 /* Interrupt Mask Register */ -#define IMXRT_ENET_RDAR_OFFSET 0x0010 /* Receive Descriptor Active Register */ -#define IMXRT_ENET_TDAR_OFFSET 0x0014 /* Transmit Descriptor Active Register */ -#define IMXRT_ENET_ECR_OFFSET 0x0024 /* Ethernet Control Register */ -#define IMXRT_ENET_MMFR_OFFSET 0x0040 /* MII Management Frame Register */ -#define IMXRT_ENET_MSCR_OFFSET 0x0044 /* MII Speed Control Register */ -#define IMXRT_ENET_MIBC_OFFSET 0x0064 /* MIB Control Register */ -#define IMXRT_ENET_RCR_OFFSET 0x0084 /* Receive Control Register */ -#define IMXRT_ENET_TCR_OFFSET 0x00c4 /* Transmit Control Register */ -#define IMXRT_ENET_PALR_OFFSET 0x00e4 /* Physical Address Lower Register */ -#define IMXRT_ENET_PAUR_OFFSET 0x00e8 /* Physical Address Upper Register */ -#define IMXRT_ENET_OPD_OFFSET 0x00ec /* Opcode/Pause Duration Register */ -#define IMXRT_ENET_TXIC_OFFSET 0x00F0 /* Transmit Interrupt Coalescing Register */ -#define IMXRT_ENET_RXIC_OFFSET 0x0100 /* Receive Interrupt Coalescing Register */ -#define IMXRT_ENET_IAUR_OFFSET 0x0118 /* Descriptor Individual Upper Address Register */ -#define IMXRT_ENET_IALR_OFFSET 0x011c /* Descriptor Individual Lower Address Register */ -#define IMXRT_ENET_GAUR_OFFSET 0x0120 /* Descriptor Group Upper Address Register */ -#define IMXRT_ENET_GALR_OFFSET 0x0124 /* Descriptor Group Lower Address Register */ -#define IMXRT_ENET_TFWR_OFFSET 0x0144 /* Transmit FIFO Watermark Register */ -#define IMXRT_ENET_RDSR_OFFSET 0x0180 /* Receive Descriptor Ring Start Register */ -#define IMXRT_ENET_TDSR_OFFSET 0x0184 /* Transmit Buffer Descriptor Ring Start Register */ -#define IMXRT_ENET_MRBR_OFFSET 0x0188 /* Maximum Receive Buffer Size Register */ -#define IMXRT_ENET_RSFL_OFFSET 0x0190 /* Receive FIFO Section Full Threshold */ -#define IMXRT_ENET_RSEM_OFFSET 0x0194 /* Receive FIFO Section Empty Threshold */ -#define IMXRT_ENET_RAEM_OFFSET 0x0198 /* Receive FIFO Almost Empty Threshold */ -#define IMXRT_ENET_RAFL_OFFSET 0x019c /* Receive FIFO Almost Full Threshold */ -#define IMXRT_ENET_TSEM_OFFSET 0x01a0 /* Transmit FIFO Section Empty Threshold */ -#define IMXRT_ENET_TAEM_OFFSET 0x01a4 /* Transmit FIFO Almost Empty Threshold */ -#define IMXRT_ENET_TAFL_OFFSET 0x01a8 /* Transmit FIFO Almost Full Threshold */ -#define IMXRT_ENET_TIPG_OFFSET 0x01ac /* Transmit Inter-Packet Gap */ -#define IMXRT_ENET_FTRL_OFFSET 0x01b0 /* Frame Truncation Length */ -#define IMXRT_ENET_TACC_OFFSET 0x01c0 /* Transmit Accelerator Function Configuration */ -#define IMXRT_ENET_RACC_OFFSET 0x01c4 /* Receive Accelerator Function Configuration */ - -#define IMXRT_ENET_ATCR_OFFSET 0x0400 /* Timer Control Register */ -#define IMXRT_ENET_ATVR_OFFSET 0x0404 /* Timer Value Register */ -#define IMXRT_ENET_ATOFF_OFFSET 0x0408 /* Timer Offset Register */ -#define IMXRT_ENET_ATPER_OFFSET 0x040c /* Timer Period Register */ -#define IMXRT_ENET_ATCOR_OFFSET 0x0410 /* Timer Correction Register */ -#define IMXRT_ENET_ATINC_OFFSET 0x0414 /* Time-Stamping Clock Period Register */ -#define IMXRT_ENET_ATSTMP_OFFSET 0x0418 /* Timestamp of Last Transmitted Frame */ - -#define IMXRT_ENET_TGSR_OFFSET 0x0604 /* Timer Global Status Register */ -#define IMXRT_ENET_TCSR0_OFFSET 0x0608 /* Timer Control Status Register */ -#define IMXRT_ENET_TCCR0_OFFSET 0x060c /* Timer Compare Capture Register */ -#define IMXRT_ENET_TCSR1_OFFSET 0x0610 /* Timer Control Status Register */ -#define IMXRT_ENET_TCCR1_OFFSET 0x0614 /* Timer Compare Capture Register */ -#define IMXRT_ENET_TCSR2_OFFSET 0x0618 /* Timer Control Status Register */ -#define IMXRT_ENET_TCCR2_OFFSET 0x061c /* Timer Compare Capture Register */ -#define IMXRT_ENET_TCSR3_OFFSET 0x0620 /* Timer Control Status Register */ -#define IMXRT_ENET_TCCR3_OFFSET 0x0624 /* Timer Compare Capture Register */ - -/* Register Addresses ********************************************************/ - -#define IMXRT_ENET_EIR (IMXRT_ENET_BASE+IMXRT_ENET_EIR_OFFSET) -#define IMXRT_ENET_EIMR (IMXRT_ENET_BASE+IMXRT_ENET_EIMR_OFFSET) -#define IMXRT_ENET_RDAR (IMXRT_ENET_BASE+IMXRT_ENET_RDAR_OFFSET) -#define IMXRT_ENET_TDAR (IMXRT_ENET_BASE+IMXRT_ENET_TDAR_OFFSET) -#define IMXRT_ENET_ECR (IMXRT_ENET_BASE+IMXRT_ENET_ECR_OFFSET) -#define IMXRT_ENET_MMFR (IMXRT_ENET_BASE+IMXRT_ENET_MMFR_OFFSET) -#define IMXRT_ENET_MSCR (IMXRT_ENET_BASE+IMXRT_ENET_MSCR_OFFSET) -#define IMXRT_ENET_MIBC (IMXRT_ENET_BASE+IMXRT_ENET_MIBC_OFFSET) -#define IMXRT_ENET_RCR (IMXRT_ENET_BASE+IMXRT_ENET_RCR_OFFSET) -#define IMXRT_ENET_TCR (IMXRT_ENET_BASE+IMXRT_ENET_TCR_OFFSET) -#define IMXRT_ENET_PALR (IMXRT_ENET_BASE+IMXRT_ENET_PALR_OFFSET) -#define IMXRT_ENET_PAUR (IMXRT_ENET_BASE+IMXRT_ENET_PAUR_OFFSET) -#define IMXRT_ENET_OPD (IMXRT_ENET_BASE+IMXRT_ENET_OPD_OFFSET) -#define IMXRT_ENET_IAUR (IMXRT_ENET_BASE+IMXRT_ENET_IAUR_OFFSET) -#define IMXRT_ENET_IALR (IMXRT_ENET_BASE+IMXRT_ENET_IALR_OFFSET) -#define IMXRT_ENET_GAUR (IMXRT_ENET_BASE+IMXRT_ENET_GAUR_OFFSET) -#define IMXRT_ENET_GALR (IMXRT_ENET_BASE+IMXRT_ENET_GALR_OFFSET) -#define IMXRT_ENET_TFWR (IMXRT_ENET_BASE+IMXRT_ENET_TFWR_OFFSET) -#define IMXRT_ENET_RDSR (IMXRT_ENET_BASE+IMXRT_ENET_RDSR_OFFSET) -#define IMXRT_ENET_TDSR (IMXRT_ENET_BASE+IMXRT_ENET_TDSR_OFFSET) -#define IMXRT_ENET_MRBR (IMXRT_ENET_BASE+IMXRT_ENET_MRBR_OFFSET) -#define IMXRT_ENET_RSFL (IMXRT_ENET_BASE+IMXRT_ENET_RSFL_OFFSET) -#define IMXRT_ENET_RSEM (IMXRT_ENET_BASE+IMXRT_ENET_RSEM_OFFSET) -#define IMXRT_ENET_RAEM (IMXRT_ENET_BASE+IMXRT_ENET_RAEM_OFFSET) -#define IMXRT_ENET_RAFL (IMXRT_ENET_BASE+IMXRT_ENET_RAFL_OFFSET) -#define IMXRT_ENET_TSEM (IMXRT_ENET_BASE+IMXRT_ENET_TSEM_OFFSET) -#define IMXRT_ENET_TAEM (IMXRT_ENET_BASE+IMXRT_ENET_TAEM_OFFSET) -#define IMXRT_ENET_TAFL (IMXRT_ENET_BASE+IMXRT_ENET_TAFL_OFFSET) -#define IMXRT_ENET_TIPG (IMXRT_ENET_BASE+IMXRT_ENET_TIPG_OFFSET) -#define IMXRT_ENET_FTRL (IMXRT_ENET_BASE+IMXRT_ENET_FTRL_OFFSET) -#define IMXRT_ENET_TACC (IMXRT_ENET_BASE+IMXRT_ENET_TACC_OFFSET) -#define IMXRT_ENET_RACC (IMXRT_ENET_BASE+IMXRT_ENET_RACC_OFFSET) - -#define IMXRT_ENET_ATCR (IMXRT_ENET_BASE+IMXRT_ENET_ATCR_OFFSET) -#define IMXRT_ENET_ATVR (IMXRT_ENET_BASE+IMXRT_ENET_ATVR_OFFSET) -#define IMXRT_ENET_ATOFF (IMXRT_ENET_BASE+IMXRT_ENET_ATOFF_OFFSET) -#define IMXRT_ENET_ATPER (IMXRT_ENET_BASE+IMXRT_ENET_ATPER_OFFSET) -#define IMXRT_ENET_ATCOR (IMXRT_ENET_BASE+IMXRT_ENET_ATCOR_OFFSET) -#define IMXRT_ENET_ATINC (IMXRT_ENET_BASE+IMXRT_ENET_ATINC_OFFSET) -#define IMXRT_ENET_ATSTMP (IMXRT_ENET_BASE+IMXRT_ENET_ATSTMP_OFFSET) - -#define IMXRT_ENET_TGSR (IMXRT_ENET_BASE+IMXRT_ENET_TGSR_OFFSET) -#define IMXRT_ENET_TCSR0 (IMXRT_ENET_BASE+IMXRT_ENET_TCSR0_OFFSET) -#define IMXRT_ENET_TCCR0 (IMXRT_ENET_BASE+IMXRT_ENET_TCCR0_OFFSET) -#define IMXRT_ENET_TCSR1 (IMXRT_ENET_BASE+IMXRT_ENET_TCSR1_OFFSET) -#define IMXRT_ENET_TCCR1 (IMXRT_ENET_BASE+IMXRT_ENET_TCCR1_OFFSET) -#define IMXRT_ENET_TCSR2 (IMXRT_ENET_BASE+IMXRT_ENET_TCSR2_OFFSET) -#define IMXRT_ENET_TCCR2 (IMXRT_ENET_BASE+IMXRT_ENET_TCCR2_OFFSET) -#define IMXRT_ENET_TCSR3 (IMXRT_ENET_BASE+IMXRT_ENET_TCSR3_OFFSET) -#define IMXRT_ENET_TCCR3 (IMXRT_ENET_BASE+IMXRT_ENET_TCCR3_OFFSET) - -/* Register Bit Definitions **************************************************/ - -/* Interrupt Event Register, Interrupt Mask Register */ - /* Bits 0-14: Reserved */ -#define ENET_INT_TS_TIMER (1 << 15) /* Bit 15: Timestamp timer */ -#define ENET_INT_TS_AVAIL (1 << 16) /* Bit 16: Transmit timestamp available */ -#define ENET_INT_WAKEUP (1 << 17) /* Bit 17: Node wake-up request indication */ -#define ENET_INT_PLR (1 << 18) /* Bit 18: Payload receive error */ -#define ENET_INT_UN (1 << 19) /* Bit 19: Transmit FIFO underrun */ -#define ENET_INT_RL (1 << 20) /* Bit 20: Collision Retry Limit */ -#define ENET_INT_LC (1 << 21) /* Bit 21: Late Collision */ -#define ENET_INT_EBERR (1 << 22) /* Bit 22: Ethernet Bus Error */ -#define ENET_INT_MII (1 << 23) /* Bit 23: MII Interrupt */ -#define ENET_INT_RXB (1 << 24) /* Bit 24: Receive Buffer Interrupt */ -#define ENET_INT_RXF (1 << 25) /* Bit 25: Receive Frame Interrupt */ -#define ENET_INT_TXB (1 << 26) /* Bit 26: Transmit Buffer Interrupt */ -#define ENET_INT_TXF (1 << 27) /* Bit 27: Transmit Frame Interrupt */ -#define ENET_INT_GRA (1 << 28) /* Bit 28: Graceful Stop Complete */ -#define ENET_INT_BABT (1 << 29) /* Bit 29: Babbling Transmit Error */ -#define ENET_INT_BABR (1 << 30) /* Bit 30: Babbling Receive Error */ - /* Bit 31: Reserved */ -/* Receive Descriptor Active Register */ - /* Bits 0-23: Reserved */ -#define ENET_RDAR (1 << 24) /* Bit 24: Receive descriptor active */ - /* Bits 25-31: Reserved */ -/* Transmit Descriptor Active Register */ - /* Bits 0-23: Reserved */ -#define ENET_TDAR (1 << 24) /* Bit 24: Transmit descriptor active */ - /* Bits 25-31: Reserved */ -/* Ethernet Control Register */ - -#define ENET_ECR_RESET (1 << 0) /* Bit 0: Ethernet MAC reset */ -#define ENET_ECR_ETHEREN (1 << 1) /* Bit 1: Ethernet enable */ -#define ENET_ECR_MAGICEN (1 << 2) /* Bit 2: Magic packet detection enable */ -#define ENET_ECR_SLEEP (1 << 3) /* Bit 3: Sleep mode enable */ -#define ENET_ECR_EN1588 (1 << 4) /* Bit 4: EN1588 enable */ - /* Bit 5: Reserved */ -#define ENET_ECR_DBGEN (1 << 6) /* Bit 6: Debug enable */ -#define ENET_ECR_STOPEN (1 << 7) /* Bit 7: STOPEN Signal Control */ -#ifdef IMXRT_ENET_HAS_DBSWAP -#define ENET_ECR_DBSWP (1 << 8) /* Bit 8: Swap bytes */ -#endif - /* Bits 9-31: Reserved */ -#define ECR_RESV_VAL (7 << 28) /* Reserve val to write */ -/* MII Management Frame Register */ - -#define ENET_MMFR_DATA_SHIFT (0) /* Bits 0-15: Management frame data */ -#define ENET_MMFR_DATA_MASK (0xffff << ENET_MMFR_DATA_SHIFT) -#define ENET_MMFR_TA_SHIFT (16) /* Bits 16-17: Turn around */ -#define ENET_MMFR_TA_MASK (3 << ENET_MMFR_TA_SHIFT) -#define ENET_MMFR_RA_SHIFT (18) /* Bits 18-22: Register address */ -#define ENET_MMFR_RA_MASK (31 << ENET_MMFR_RA_SHIFT) -#define ENET_MMFR_PA_SHIFT (23) /* Bits 23-27: PHY address */ -#define ENET_MMFR_PA_MASK (31 << ENET_MMFR_PA_SHIFT) -#define ENET_MMFR_OP_SHIFT (28) /* Bits 28-29: Operation code */ -#define ENET_MMFR_OP_MASK (3 << ENET_MMFR_OP_SHIFT) -# define ENET_MMFR_OP_WRNOTMII (0 << ENET_MMFR_OP_SHIFT) /* Write frame, not MII compliant */ -# define ENET_MMFR_OP_WRMII (1 << ENET_MMFR_OP_SHIFT) /* Write frame, MII management frame */ -# define ENET_MMFR_OP_RDMII (2 << ENET_MMFR_OP_SHIFT) /* Read frame, MII management frame */ -# define ENET_MMFR_OP_RdNOTMII (3 << ENET_MMFR_OP_SHIFT) /* Read frame, not MII compliant */ -#define ENET_MMFR_ST_SHIFT (30) /* Bits 30-31: Start of frame delimiter */ -#define ENET_MMFR_ST_MASK (3 << ENET_MMFR_ST_SHIFT) - -/* MII Speed Control Register */ - /* Bit 0: Reserved */ -#define ENET_MSCR_MII_SPEED_SHIFT (1) /* Bits 1-6: MII speed */ -#define ENET_MSCR_MII_SPEED_MASK (63 << ENET_MSCR_MII_SPEED_SHIFT) -#define ENET_MSCR_DIS_PRE (1 << 7) /* Bit 7: Disable preamble */ -#define ENET_MSCR_HOLDTIME_SHIFT (8) /* Bits 8-10: Holdtime on MDIO output */ -#define ENET_MSCR_HOLDTIME_MASK (7 << ENET_MSCR_HOLDTIME_SHIFT) -# define ENET_MSCR_HOLDTIME_1CYCLE (0 << ENET_MSCR_HOLDTIME_SHIFT) /* 1 internal module clock cycle */ -# define ENET_MSCR_HOLDTIME_2CYCLES (1 << ENET_MSCR_HOLDTIME_SHIFT) /* 2 internal module clock cycles */ -# define ENET_MSCR_HOLDTIME_3CYCLES (2 << ENET_MSCR_HOLDTIME_SHIFT) /* 3 internal module clock cycles */ -# define ENET_MSCR_HOLDTIME_8CYCLES (7 << ENET_MSCR_HOLDTIME_SHIFT) /* 8 internal module clock cycles */ - /* Bits 11-31: Reserved */ -/* MIB Control Register */ - /* Bits 0-28: Reserved */ -#define ENET_MIBC_MIB_CLEAR (1 << 29) /* Bit 29: MIB clear */ -#define ENET_MIBC_MIB_IDLE (1 << 30) /* Bit 30: MIB idle */ -#define ENET_MIBC_MIB_DIS (1 << 31) /* Bit 31: Disable MIB logic */ - -/* Receive Control Register */ - -#define ENET_RCR_LOOP (1 << 0) /* Bit 0: Internal loopback */ -#define ENET_RCR_DRT (1 << 1) /* Bit 1: Disable receive on transmit */ -#define ENET_RCR_MII_MODE (1 << 2) /* Bit 2: Media independent interface mode */ -#define ENET_RCR_PROM (1 << 3) /* Bit 3: Promiscuous mode */ -#define ENET_RCR_BC_REJ (1 << 4) /* Bit 4: Broadcast frame reject */ -#define ENET_RCR_FCE (1 << 5) /* Bit 5: Flow control enable */ - /* Bits 6-7: Reserved */ -#define ENET_RCR_RMII_MODE (1 << 8) /* Bit 8: RMII mode enable */ -#define ENET_RCR_RMII_10T (1 << 9) /* Bit 9: Enables 10-Mbps mode of the RMII */ - /* Bits 10-11: Reserved */ -#define ENET_RCR_PADEN (1 << 12) /* Bit 12: Enable frame padding remove on receive */ -#define ENET_RCR_PAUFWD (1 << 13) /* Bit 13: Terminate/forward pause frames */ -#define ENET_RCR_CRCFWD (1 << 14) /* Bit 14: Terminate/forward received CRC */ -#define ENET_RCR_CFEN (1 << 15) /* Bit 15: MAC control frame enable */ -#define ENET_RCR_MAX_FL_SHIFT (16) /* Bits 16-29: Maximum frame length */ -#define ENET_RCR_MAX_FL_MASK (0x3fff << ENET_RCR_MAX_FL_SHIFT) -#define ENET_RCR_NLC (1 << 30) /* Bit 30: Payload length check disable */ -#define ENET_RCR_GRS (1 << 31) /* Bit 31: Graceful receive stopped */ - -/* Transmit Control Register */ - -#define ENET_TCR_GTS (1 << 0) /* Bit 0: Graceful transmit stop */ - /* Bit 1: Reserved */ -#define ENET_TCR_ADDINS (1 << 8) /* Bit 8: Set MAC address on transmit */ -#define ENET_TCR_FDEN (1 << 2) /* Bit 2: Full duplex enable */ -#define ENET_TCR_TFC_PAUSE (1 << 3) /* Bit 3: Transmit frame control pause */ -#define ENET_TCR_RFC_PAUSE (1 << 4) /* Bit 4: Receive frame control pause */ -#define ENET_TCR_ADDSEL_SHIFT (5) /* Bits 5-7: Source MAC address select on transmit */ -#define ENET_TCR_ADDSEL_MASK (7 << ENET_TCR_ADDSEL_SHIFT) -# define ENET_TCR_ADDSEL_PADDR12 (0 << ENET_TCR_ADDSEL_SHIFT) /* Node MAC address programmed on PADDR1/2 registers */ -#define ENET_TCR_CRCFWD (1 << 9) /* Bit 9: Forward frame from application with CRC */ - /* Bits 10-31: Reserved */ -/* Physical Address Lower/Upper Register (32-bits of 48-address) */ -/* Physical Address Upper Register */ - -#define ENET_PAUR_TYPE_SHIFT (0) /* Bits 0-15: Type field in PAUSE frame */ -#define ENET_PAUR_TYPE_MASK (0xffff << ENET_PAUR_TYPE_MASK) -#define ENET_PAUR_PADDR2_SHIFT (16) /* Bits 16-31: Bytes 4 and 5 of the 6-byte address */ -#define ENET_PAUR_PADDR2_MASK (0xffff << ENET_PAUR_PADDR2_SHIFT) - -/* Opcode/Pause Duration Register */ - -#define ENET_OPD_PAUSE_DUR_SHIFT (0) /* Bits 0-15: Pause duration */ -#define ENET_OPD_PAUSE_DUR_MASK (0xffff << ENET_OPD_PAUSE_DUR_SHIFT) -#define ENET_OPD_OPCODE_SHIFT (16) /* Bits 16-31: Opcode field in PAUSE frames */ -#define ENET_OPD_OPCODE_MASK (0xffff << ENET_OPD_OPCODE_SHIFT) - -/* Descriptor Individual Uupper/Lower Address Register (64-bit address in two 32-bit registers) */ -/* Descriptor Group Upper/Lower Address Register (64-bit address in two 32-bit registers) */ - -/* Transmit Interrupt Coalescing Register */ -#define ENET_TXIC_ICTT_SHIFT (0) /* Bits 0-15: Interrupt coalescing timer threshold */ -#define ENET_TXIC_ICTT_SHIFT_MASK (0xffff << ENET_TXIC_ICTT_SHIFT) - /* Bits 16-19: Reserved */ -#define ENET_TXIC_ICFT_SHIFT (20) /* Bits 0-15: Interrupt coalescing timer threshold */ -#define ENET_TXIC_ICFT_SHIFT_MASK (0xff << ENET_TXIC_ICFT_SHIFT) -#define ENET_TXIC_ICTT_ICCS (1 << 30) /* Bit 30: Interrupt Coalescing Timer Clock Source Select */ -#define ENET_TXIC_ICTT_ICEN (1 << 31) /* Bit 31: Eable/disabel Interrupt Coalescing */ - -/* Receive Interrupt Coalescing Register */ -#define ENET_RXIC_ICTT_SHIFT (0) /* Bits 0-15: Interrupt coalescing timer threshold */ -#define ENET_RXIC_ICTT_SHIFT_MASK (0xffff << ENET_TXIC_ICTT_SHIFT) - /* Bits 16-19: Reserved */ -#define ENET_RXIC_ICFT_SHIFT (20) /* Bits 0-15: Interrupt coalescing timer threshold */ -#define ENET_RXIC_ICFT_SHIFT_MASK (0xff << ENET_TXIC_ICFT_SHIFT) -#define ENET_RXIC_ICTT_ICCS (1 << 30) /* Bit 30: Interrupt Coalescing Timer Clock Source Select */ -#define ENET_RXIC_ICTT_ICEN (1 << 31) /* Bit 31: Eable/disabel Interrupt Coalescing */ - -/* Transmit FIFO Watermark Register */ - -#define ENET_TFWR_TFWR_SHIFT (0) /* Bits 0-5: Transmit FIFO write */ - /* Bits 6-7: Reserved */ -#define ENET_TFWR_TFWR_MASK (63 << ENET_TFWR_TFWR_SHIFT) -#define ENET_TFWR_STRFWD (1 << 8) /* Bit 8: Store and forward enable */ - /* Bits 9-31: Reserved */ -/* Receive Descriptor Ring Start Register */ - /* Bits 0-2: Reserved */ -#define ENET_RDSR_SHIFT (3) /* Bits 3-31: Start of the receive buffer descriptor queue */ -#define ENET_RDSR_MASK (0xfffffff8) - -/* Transmit Buffer Descriptor Ring Start Register */ - /* Bits 0-2: Reserved */ -#define ENET_TDSR_SHIFT (3) /* Bits 3-31: Start of the transmit buffer descriptor queue */ -#define ENET_TDSR_MASK (0xfffffff8) - -/* Maximum Receive Buffer Size Register */ - /* Bits 14-31: Reserved */ -#define ENET_MRBR_SHIFT (4) /* Bits 4-13: Receive buffer size in bytes */ -#define ENET_MRBR_MASK (0x3ff << ENET_MRBR_SHIFT) - /* Bits 0-3: Reserved */ -/* Receive FIFO Section Full Threshold */ - /* Bits 8-31: Reserved */ -#define ENET_RSFL_SHIFT (0) /* Bits 0-7: Value of receive FIFO section full threshold */ -#define ENET_RSFL_MASK (0xff << ENET_RSFL_SHIFT) - -/* Receive FIFO Section Empty Threshold */ - -#define ENET_RSEM_SHIFT (0) /* Bits 0-7: Value of the receive FIFO section empty threshold */ -#define ENET_RSEM_MASK (0xff << ENET_RSEM_SHIFT) - /* Bits 8-31: Reserved */ -/* Receive FIFO Almost Empty Threshold */ - -#define ENET_RAEM_SHIFT (0) /* Bits 0-7: Value of the receive FIFO almost empty threshold */ -#define ENET_RAEM_MASK (0xff << ENET_RAEM_SHIFT) - /* Bits 8-31: Reserved */ -/* Receive FIFO Almost Full Threshold */ - -#define ENET_RAFL_SHIFT (0) /* Bits 0-7: Value of the receive FIFO almost full threshold */ -#define ENET_RAFL_MASK (0xff << ENET_RAFL_SHIFT) - /* Bits 8-31: Reserved */ -/* Transmit FIFO Section Empty Threshold */ - -#define ENET_TSEM_SHIFT (0) /* Bits 0-7: Value of the transmit FIFO section empty threshold */ -#define ENET_TSEM_MASK (0xff << ENET_TSEM_SHIFT) - /* Bits 8-31: Reserved */ -/* Transmit FIFO Almost Empty Threshold */ - -#define ENET_TAEM_SHIFT (0) /* Bits 0-7: Value of the transmit FIFO section empty threshold */ -#define ENET_TAEM_MASK (0xff << ENET_TAEM_SHIFT) - /* Bits 8-31: Reserved */ -/* Transmit FIFO Almost Full Threshold */ - -#define ENET_TAFL_SHIFT (0) /* Bits 0-7: Value of the transmit FIFO section empty threshold */ -#define ENET_TAFL_MASK (0xff << ENET_TAFL_SHIFT) - /* Bits 8-31: Reserved */ -/* Transmit Inter-Packet Gap */ - -#define ENET_TIPG_SHIFT (0) /* Bits 0-4: Value of the transmit FIFO section empty threshold */ -#define ENET_TIPG_MASK (31 << ENET_TIPG_SHIFT) - /* Bits 5-31: Reserved */ -/* Frame Truncation Length */ - -#define ENET_FTRL_SHIFT (0) /* Bits 0-13: Value of the transmit FIFO section empty threshold */ -#define ENET_FTRL_MASK (0x3fff << ENET_FTRL_SHIFT) - /* Bits 14-31: Reserved */ -/* Transmit Accelerator Function Configuration */ - -#define ENET_TACC_SHIFT16 (1 << 0) /* Bit 0: TX FIFO shift-16 */ - /* Bits 1-2: Reserved */ -#define ENET_TACC_IPCHK (1 << 3) /* Bit 3: Enables insertion of IP header checksum */ -#define ENET_TACC_PROCHK (1 << 4) /* Bit 4: Enables insertion of protocol checksum */ - /* Bits 5-31: Reserved */ -/* Receive Accelerator Function Configuration */ - -#define ENET_RACC_PADREM (1 << 0) /* Bit 0: Enable padding removal for short IP frames */ -#define ENET_RACC_IPDIS (1 << 1) /* Bit 1: Enable discard of frames with wrong IPv4 header checksum */ -#define ENET_RACC_PRODIS (1 << 2) /* Bit 2: Enable discard of frames with wrong protocol checksum */ - /* Bits 3-5: Reserved */ -#define ENET_RACC_LINEDIS (1 << 6) /* Bit 6: Enable discard of frames with MAC layer errors */ -#define ENET_RACC_SHIFT16 (1 << 7) /* Bit 7: RX FIFO shift-16 */ - /* Bits 8-31: Reserved */ -/* Timer Control Register */ - -#define ENET_ATCR_EN (1 << 0) /* Bit 0: Enable timer */ - /* Bit 1: Reserved */ -#define ENET_ATCR_OFFEN (1 << 2) /* Bit 2: Enable one-shot offset event */ -#define ENET_ATCR_OFFRST (1 << 3) /* Bit 3: Reset timer on offset event */ -#define ENET_ATCR_PEREN (1 << 4) /* Bit 4: Enable periodical event */ - /* Bits 5-6: Reserved */ -#define ENET_ATCR_PINPER (1 << 7) /* Bit 7: Enables event signal output assertion on period event */ - /* Bit 8: Reserved */ -#define ENET_ATCR_RESTART (1 << 9) /* Bit 9: Reset timer */ - /* Bit 10: Reserved */ -#define ENET_ATCR_CAPTURE (1 << 11) /* Bit 11: Capture timer value */ - /* Bit 12: Reserved */ -#define ENET_ATCR_SLAVE (1 << 13) /* Bit 13: Enable timer slave mode */ - /* Bits 14-31: Reserved */ -/* Timer Value Register (32-bit timer value) */ -/* Timer Offset Register (32-bit offset value) */ -/* Timer Period Register (32-bit timer period) */ - -/* Timer Correction Register */ - -#define ENET_ATCOR_MASK (0x7fffffff) /* Bits 0-3: Correction counter wrap-around value */ - /* Bit 31: Reserved */ -/* Time-Stamping Clock Period Register */ - -#define ENET_ATINC_INC_SHIFT (0) /* Bits 0-6: Clock period of the timestamping clock (ts_clk) in nanoseconds */ -#define ENET_ATINC_INC_MASK (0x7f << ENET_ATINC_INC_SHIFT) - /* Bit 7: Reserved */ -#define ENET_ATINC_INC_CORR_SHIFT (8) /* Bits 8-14: Correction increment value */ -#define ENET_ATINC_INC_CORR_MASK (0x7f << ENET_ATINC_INC_CORR_SHIFT) - /* Bits 15-31: Reserved */ -/* Timestamp of Last Transmitted Frame (32-bit timestamp) */ - -/* Timer Global Status Register */ - -#define ENET_TGSR_TF0 (1 << 0) /* Bit 0: Copy of Timer Flag for channel 0 */ -#define ENET_TGSR_TF1 (1 << 1) /* Bit 1: Copy of Timer Flag for channel 1 */ -#define ENET_TGSR_TF2 (1 << 2) /* Bit 2: Copy of Timer Flag for channel 2 */ -#define ENET_TGSR_TF3 (1 << 3) /* Bit 3: Copy of Timer Flag for channel 3 */ - /* Bits 14-31: Reserved */ -/* Timer Control Status Register n */ - -#define ENET_TCSR_TDRE (1 << 0) /* Bit 0: Timer DMA Request Enable */ - /* Bit 1: Reserved */ -#define ENET_TCSR_TMODE_SHIFT (2) /* Bits 2-5: Timer Mode */ -#define ENET_TCSR_TMODE_MASK (15 << ENET_TCSR_TMODE_SHIFT) -# define ENET_TCSR_TMODE_DISABLED (0 << ENET_TCSR_TMODE_SHIFT) /* Disabled */ -# define ENET_TCSR_TMODE_ICRISING (1 << ENET_TCSR_TMODE_SHIFT) /* Input Capture on rising edge */ -# define ENET_TCSR_TMODE_ICFALLLING (2 << ENET_TCSR_TMODE_SHIFT) /* Input Capture on falling edge */ -# define ENET_TCSR_TMODE_ICBOTH (3 << ENET_TCSR_TMODE_SHIFT) /* Input Capture on both edges */ -# define ENET_TCSR_TMODE_OCSW (4 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, S/W only */ -# define ENET_TCSR_TMODE_OCTOGGLE (5 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, toggle on compare */ -# define ENET_TCSR_TMODE_OCCLR (6 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, clear on compare */ -# define ENET_TCSR_TMODE_OCSET (7 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, set on compare */ -# define ENET_TCSR_TMODE_OCSETCLR (9 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, set on compare, clear on overflow */ -# define ENET_TCSR_TMODE_OCCLRSET (10 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, clear on compare, set on overflow */ -# define ENET_TCSR_TMODE_PCPULSEL (14 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, pulse low on compare */ -# define ENET_TCSR_TMODE_PCPULSEH (15 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, pulse high on compare */ -#define ENET_TCSR_TIE (1 << 6) /* Bit 6: Timer interrupt enable */ -#define ENET_TCSR_TF (1 << 7) /* Bit 7: Timer Flag */ - /* Bits 8-31: Reserved */ -/* Timer Compare Capture Register (32-bit compare value) */ - -/* Buffer Descriptors ********************************************************/ -/* Endian-independent descriptor offsets */ - -#define DESC_STATUS1_OFFSET (0) -#define DESC_LENGTH_OFFSET (2) -#define DESC_DATAPTR_OFFSET (4) -#define DESC_LEGACY_LEN (8) - -#define DESC_STATUS2_OFFSET (8) -#define DESC_LENPROTO_OFFSET (12) -#define DESC_CHECKSUM_OFFSET (14) -#define DESC_BDU_OFFSET (16) -#define DESC_TIMESTAMP_OFFSET (20) -#define DESC_ENHANCED_LEN (32) - -/* Legacy/Common TX Buffer Descriptor Bit Definitions. - * - * The descriptors are represented by structures Unfortunately, when the - * structures are overlayed on the data, the bytes are reversed because - * the underlying hardware writes the data in big-endian byte order. - */ - -#ifdef IMXRT_ENET_HAS_DBSWAP -# ifndef CONFIG_ENDIAN_BIG -# define IMXRT_USE_DBSWAP -# endif -#else -# ifndef CONFIG_ENDIAN_BIG -# define IMXRT_BUFFERS_SWAP -# endif -#endif - -#ifndef IMXRT_BUFFERS_SWAP -# define TXDESC_ABC (1 << 9) /* Legacy */ -# define TXDESC_TC (1 << 10) /* Common */ -# define TXDESC_L (1 << 11) /* Common */ -# define TXDESC_TO2 (1 << 12) /* Common */ -# define TXDESC_W (1 << 13) /* Common */ -# define TXDESC_TO1 (1 << 14) /* Common */ -# define TXDESC_R (1 << 15) /* Common */ -#else -# define TXDESC_ABC (1 << 1) /* Legacy */ -# define TXDESC_TC (1 << 2) /* Common */ -# define TXDESC_L (1 << 3) /* Common */ -# define TXDESC_TO2 (1 << 4) /* Common */ -# define TXDESC_W (1 << 5) /* Common */ -# define TXDESC_TO1 (1 << 6) /* Common */ -# define TXDESC_R (1 << 7) /* Common */ -#endif - -/* Enhanced (only) TX Buffer Descriptor Bit Definitions */ - -#ifndef IMXRT_BUFFERS_SWAP -# define TXDESC_TSE (1 << 8) -# define TXDESC_OE (1 << 9) -# define TXDESC_LCE (1 << 10) -# define TXDESC_FE (1 << 11) -# define TXDESC_EE (1 << 12) -# define TXDESC_UE (1 << 13) -# define TXDESC_TXE (1 << 15) - -# define TXDESC_IINS (1 << 27) -# define TXDESC_PINS (1 << 28) -# define TXDESC_TS (1 << 29) -# define TXDESC_INT (1 << 30) - -# define TXDESC_BDU (1 << 31) -#else -# define TXDESC_IINS (1 << 3) -# define TXDESC_PINS (1 << 4) -# define TXDESC_TS (1 << 5) -# define TXDESC_INT (1 << 6) - -# define TXDESC_TSE (1 << 16) -# define TXDESC_OE (1 << 17) -# define TXDESC_LCE (1 << 18) -# define TXDESC_FE (1 << 19) -# define TXDESC_EE (1 << 20) -# define TXDESC_UE (1 << 21) -# define TXDESC_TXE (1 << 23) - -# define TXDESC_BDU (1 << 7) -#endif - -/* Legacy (and Common) RX Buffer Descriptor Bit Definitions */ - -#ifndef IMXRT_BUFFERS_SWAP -# define RXDESC_TR (1 << 0) -# define RXDESC_OV (1 << 1) -# define RXDESC_CR (1 << 2) -# define RXDESC_NO (1 << 4) -# define RXDESC_LG (1 << 5) -# define RXDESC_MC (1 << 6) -# define RXDESC_BC (1 << 7) -# define RXDESC_M (1 << 8) -# define RXDESC_L (1 << 11) -# define RXDESC_R02 (1 << 12) -# define RXDESC_W (1 << 13) -# define RXDESC_R01 (1 << 14) -# define RXDESC_E (1 << 15) -#else -# define RXDESC_M (1 << 0) -# define RXDESC_L (1 << 3) -# define RXDESC_R02 (1 << 4) -# define RXDESC_W (1 << 5) -# define RXDESC_R01 (1 << 6) -# define RXDESC_E (1 << 7) -# define RXDESC_TR (1 << 8) -# define RXDESC_OV (1 << 9) -# define RXDESC_CR (1 << 10) -# define RXDESC_NO (1 << 12) -# define RXDESC_LG (1 << 13) -# define RXDESC_MC (1 << 14) -# define RXDESC_BC (1 << 15) -#endif - -/* Enhanced (only) TX Buffer Descriptor Bit Definitions */ - -#ifndef IMXRT_BUFFERS_SWAP -# define RXDESC_FRAG (1 << 0) -# define RXDESC_IPV6 (1 << 1) -# define RXDESC_VLAN (1 << 2) -# define RXDESC_PCR (1 << 4) -# define RXDESC_ICE (1 << 5) -# define RXDESC_INT (1 << 23) -# define RXDESC_UC (1 << 24) -# define RXDESC_CE (1 << 25) -# define RXDESC_PE (1 << 26) -# define RXDESC_ME (1 << 31) - -# define RXDESC_BDU (1 << 31) -#else -# define RXDESC_UC (1 << 0) -# define RXDESC_CE (1 << 1) -# define RXDESC_PE (1 << 2) -# define RXDESC_ME (1 << 7) -# define RXDESC_INT (1 << 15) -# define RXDESC_FRAG (1 << 24) -# define RXDESC_IPV6 (1 << 25) -# define RXDESC_VLAN (1 << 26) -# define RXDESC_PCR (1 << 28) -# define RXDESC_ICE (1 << 29) - -# define RXDESC_BDU (1 << 7) -#endif - -/***************************************************************************** - * Public Types - *****************************************************************************/ - -/* Buffer Descriptors ********************************************************/ - -/* Legacy Buffer Descriptor */ - -#ifdef CONFIG_ENET_ENHANCEDBD -#ifdef IMXRT_USE_DBSWAP -/* When DBSWP is used to swap the bytes in hardware, it is done 32-bits - * at a time. Therefore, all 16 bit elements need to be swapped to - * compensate. - */ - -struct enet_desc_s -{ - uint16_t length; /* Data length */ - uint16_t status1; /* Control and status */ - uint8_t *data; /* Buffer address */ - uint32_t status2; /* Extended status */ - uint16_t checksum; /* Payload checksum */ - uint16_t lenproto; /* Header length + Protocol type */ - uint32_t bdu; /* BDU */ - uint32_t timestamp; /* Time stamp */ - uint32_t reserved1; /* unused */ - uint32_t reserved2; /* unused */ -}; -#else -struct enet_desc_s -{ - uint16_t status1; /* Control and status */ - uint16_t length; /* Data length */ - uint8_t *data; /* Buffer address */ - uint32_t status2; /* Extended status */ - uint16_t lenproto; /* Header length + Protocol type */ - uint16_t checksum; /* Payload checksum */ - uint32_t bdu; /* BDU */ - uint32_t timestamp; /* Time stamp */ - uint32_t reserved1; /* unused */ - uint32_t reserved2; /* unused */ -}; -#endif /* IMXRT_USE_DBSWAP */ -#else /* CONFIG_ENET_ENHANCEDBD */ -#ifdef IMXRT_USE_DBSWAP -struct enet_desc_s -{ - uint16_t length; /* Data length */ - uint16_t status1; /* Control and status */ - uint8_t *data; /* Buffer address */ -}; -#else -struct enet_desc_s -{ - uint16_t status1; /* Control and status */ - uint16_t length; /* Data length */ - uint8_t *data; /* Buffer address */ -}; -#endif /* IMXRT_USE_DBSWAP */ -#endif /* CONFIG_ENET_ENHANCEDBD */ - -/***************************************************************************** - * Public Data - *****************************************************************************/ - -/***************************************************************************** - * Public Functions - *****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_ENET_H */ diff --git a/arch/arm/src/imxrt/chip/imxrt_flexpwm.h b/arch/arm/src/imxrt/chip/imxrt_flexpwm.h deleted file mode 100644 index 6a3a66edd28..00000000000 --- a/arch/arm/src/imxrt/chip/imxrt_flexpwm.h +++ /dev/null @@ -1,1817 +0,0 @@ -/************************************************************************************ - * arch/arm/src/imxrt/chip/imxrt_flexpwm.h - * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * David Sidrane - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_FLEXPWM_H -#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_FLEXPWM_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include -#include "chip/imxrt_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register Offsets *****************************************************************/ - -#define IMXRT_FLEXPWM_SM0CNT_OFFSET 0x0000 /* Counter Register */ -#define IMXRT_FLEXPWM_SM0INIT_OFFSET 0x0002 /* Initial Count Register */ -#define IMXRT_FLEXPWM_SM0CTRL2_OFFSET 0x0004 /* Control 2 Register */ -#define IMXRT_FLEXPWM_SM0CTRL_OFFSET 0x0006 /* Control Register */ -#define IMXRT_FLEXPWM_SM0VAL0_OFFSET 0x000a /* Value Register 0 */ -#define IMXRT_FLEXPWM_SM0FRACVAL1_OFFSET 0x000c /* Fractional Value Register 1 */ -#define IMXRT_FLEXPWM_SM0VAL1_OFFSET 0x000e /* Value Register 1 */ -#define IMXRT_FLEXPWM_SM0FRACVAL2_OFFSET 0x0010 /* Fractional Value Register 2 */ -#define IMXRT_FLEXPWM_SM0VAL2_OFFSET 0x0012 /* Value Register 2 */ -#define IMXRT_FLEXPWM_SM0FRACVAL3_OFFSET 0x0014 /* Fractional Value Register 3 */ -#define IMXRT_FLEXPWM_SM0VAL3_OFFSET 0x0016 /* Value Register 3 */ -#define IMXRT_FLEXPWM_SM0FRACVAL4_OFFSET 0x0018 /* Fractional Value Register 4 */ -#define IMXRT_FLEXPWM_SM0VAL4_OFFSET 0x001a /* Value Register 4 */ -#define IMXRT_FLEXPWM_SM0FRACVAL5_OFFSET 0x001c /* Fractional Value Register 5 */ -#define IMXRT_FLEXPWM_SM0VAL5_OFFSET 0x001e /* Value Register 5 */ -#define IMXRT_FLEXPWM_SM0FRCTRL_OFFSET 0x0020 /* Fractional Control Register */ -#define IMXRT_FLEXPWM_SM0OCTRL_OFFSET 0x0022 /* Output Control Register */ -#define IMXRT_FLEXPWM_SM0STS_OFFSET 0x0024 /* Status Register */ -#define IMXRT_FLEXPWM_SM0INTEN_OFFSET 0x0026 /* Interrupt Enable Register */ -#define IMXRT_FLEXPWM_SM0DMAEN_OFFSET 0x0028 /* DMA Enable Register */ -#define IMXRT_FLEXPWM_SM0TCTRL_OFFSET 0x002a /* Output Trigger Control Register */ -#define IMXRT_FLEXPWM_SM0DISMAP0_OFFSET 0x002c /* Fault Disable Mapping Register 0 */ -#define IMXRT_FLEXPWM_SM0DISMAP1_OFFSET 0x002e /* Fault Disable Mapping Register 1 */ -#define IMXRT_FLEXPWM_SM0DTCNT0_OFFSET 0x0030 /* Deadtime Count Register 0 */ -#define IMXRT_FLEXPWM_SM0DTCNT1_OFFSET 0x0032 /* Deadtime Count Register 1 */ -#define IMXRT_FLEXPWM_SM0CAPTCTRLA_OFFSET 0x0034 /* Capture Control A Register */ -#define IMXRT_FLEXPWM_SM0CAPTCOMPA_OFFSET 0x0036 /* Capture Compare A Register */ -#define IMXRT_FLEXPWM_SM0CAPTCTRLB_OFFSET 0x0038 /* Capture Control B Register */ -#define IMXRT_FLEXPWM_SM0CAPTCOMPB_OFFSET 0x003a /* Capture Compare B Register */ -#define IMXRT_FLEXPWM_SM0CAPTCTRLX_OFFSET 0x003c /* Capture Control X Register */ -#define IMXRT_FLEXPWM_SM0CAPTCOMPX_OFFSET 0x003e /* Capture Compare X Register */ -#define IMXRT_FLEXPWM_SM0CVAL0_OFFSET 0x0040 /* Capture Value 0 Register */ -#define IMXRT_FLEXPWM_SM0CVAL0CYC_OFFSET 0x0042 /* Capture Value 0 Cycle Register */ -#define IMXRT_FLEXPWM_SM0CVAL1_OFFSET 0x0044 /* Capture Value 1 Register */ -#define IMXRT_FLEXPWM_SM0CVAL1CYC_OFFSET 0x0046 /* Capture Value 1 Cycle Register */ -#define IMXRT_FLEXPWM_SM0CVAL2_OFFSET 0x0048 /* Capture Value 2 Register */ -#define IMXRT_FLEXPWM_SM0CVAL2CYC_OFFSET 0x004a /* Capture Value 2 Cycle Register */ -#define IMXRT_FLEXPWM_SM0CVAL3_OFFSET 0x004c /* Capture Value 3 Register */ -#define IMXRT_FLEXPWM_SM0CVAL3CYC_OFFSET 0x004e /* Capture Value 3 Cycle Register */ -#define IMXRT_FLEXPWM_SM0CVAL4_OFFSET 0x0050 /* Capture Value 4 Register */ -#define IMXRT_FLEXPWM_SM0CVAL4CYC_OFFSET 0x0052 /* Capture Value 4 Cycle Register */ -#define IMXRT_FLEXPWM_SM0CVAL5_OFFSET 0x0054 /* Capture Value 5 Register */ -#define IMXRT_FLEXPWM_SM0CVAL5CYC_OFFSET 0x0056 /* Capture Value 5 Cycle Register */ -#define IMXRT_FLEXPWM_SM1CNT_OFFSET 0x0060 /* Counter Register */ -#define IMXRT_FLEXPWM_SM1INIT_OFFSET 0x0062 /* Initial Count Register */ -#define IMXRT_FLEXPWM_SM1CTRL2_OFFSET 0x0064 /* Control 2 Register */ -#define IMXRT_FLEXPWM_SM1CTRL_OFFSET 0x0066 /* Control Register */ -#define IMXRT_FLEXPWM_SM1VAL0_OFFSET 0x006a /* Value Register 0 */ -#define IMXRT_FLEXPWM_SM1FRACVAL1_OFFSET 0x006c /* Fractional Value Register 1 */ -#define IMXRT_FLEXPWM_SM1VAL1_OFFSET 0x006e /* Value Register 1 */ -#define IMXRT_FLEXPWM_SM1FRACVAL2_OFFSET 0x0070 /* Fractional Value Register 2 */ -#define IMXRT_FLEXPWM_SM1VAL2_OFFSET 0x0072 /* Value Register 2 */ -#define IMXRT_FLEXPWM_SM1FRACVAL3_OFFSET 0x0074 /* Fractional Value Register 3 */ -#define IMXRT_FLEXPWM_SM1VAL3_OFFSET 0x0076 /* Value Register 3 */ -#define IMXRT_FLEXPWM_SM1FRACVAL4_OFFSET 0x0078 /* Fractional Value Register 4 */ -#define IMXRT_FLEXPWM_SM1VAL4_OFFSET 0x007a /* Value Register 4 */ -#define IMXRT_FLEXPWM_SM1FRACVAL5_OFFSET 0x007c /* Fractional Value Register 5 */ -#define IMXRT_FLEXPWM_SM1VAL5_OFFSET 0x007e /* Value Register 5 */ -#define IMXRT_FLEXPWM_SM1FRCTRL_OFFSET 0x0080 /* Fractional Control Register */ -#define IMXRT_FLEXPWM_SM1OCTRL_OFFSET 0x0082 /* Output Control Register */ -#define IMXRT_FLEXPWM_SM1STS_OFFSET 0x0084 /* Status Register */ -#define IMXRT_FLEXPWM_SM1INTEN_OFFSET 0x0086 /* Interrupt Enable Register */ -#define IMXRT_FLEXPWM_SM1DMAEN_OFFSET 0x0088 /* DMA Enable Register */ -#define IMXRT_FLEXPWM_SM1TCTRL_OFFSET 0x008a /* Output Trigger Control Register */ -#define IMXRT_FLEXPWM_SM1DISMAP0_OFFSET 0x008c /* Fault Disable Mapping Register 0 */ -#define IMXRT_FLEXPWM_SM1DISMAP1_OFFSET 0x008e /* Fault Disable Mapping Register 1 */ -#define IMXRT_FLEXPWM_SM1DTCNT0_OFFSET 0x0090 /* Deadtime Count Register 0 */ -#define IMXRT_FLEXPWM_SM1DTCNT1_OFFSET 0x0092 /* Deadtime Count Register 1 */ -#define IMXRT_FLEXPWM_SM1CAPTCTRLA_OFFSET 0x0094 /* Capture Control A Register */ -#define IMXRT_FLEXPWM_SM1CAPTCOMPA_OFFSET 0x0096 /* Capture Compare A Register */ -#define IMXRT_FLEXPWM_eFlexPWM_OFFSET 0x000c /* apter 28 Enhanced Flex Pulse Width Modulator */ -#define IMXRT_FLEXPWM_SM1CAPTCTRLB_OFFSET 0x0098 /* Capture Control B Register */ -#define IMXRT_FLEXPWM_SM1CAPTCOMPB_OFFSET 0x009a /* Capture Compare B Register */ -#define IMXRT_FLEXPWM_SM1CAPTCTRLX_OFFSET 0x009c /* Capture Control X Register */ -#define IMXRT_FLEXPWM_SM1CAPTCOMPX_OFFSET 0x009e /* Capture Compare X Register */ -#define IMXRT_FLEXPWM_SM1CVAL0_OFFSET 0x00a0 /* Capture Value 0 Register */ -#define IMXRT_FLEXPWM_SM1CVAL0CYC_OFFSET 0x00a2 /* Capture Value 0 Cycle Register */ -#define IMXRT_FLEXPWM_SM1CVAL1_OFFSET 0x00a4 /* Capture Value 1 Register */ -#define IMXRT_FLEXPWM_SM1CVAL1CYC_OFFSET 0x00a6 /* Capture Value 1 Cycle Register */ -#define IMXRT_FLEXPWM_SM1CVAL2_OFFSET 0x00a8 /* Capture Value 2 Register */ -#define IMXRT_FLEXPWM_SM1CVAL2CYC_OFFSET 0x00aa /* Capture Value 2 Cycle Register */ -#define IMXRT_FLEXPWM_SM1CVAL3_OFFSET 0x00ac /* Capture Value 3 Register */ -#define IMXRT_FLEXPWM_SM1CVAL3CYC_OFFSET 0x00ae /* Capture Value 3 Cycle Register */ -#define IMXRT_FLEXPWM_SM1CVAL4_OFFSET 0x00b0 /* Capture Value 4 Register */ -#define IMXRT_FLEXPWM_SM1CVAL4CYC_OFFSET 0x00b2 /* Capture Value 4 Cycle Register */ -#define IMXRT_FLEXPWM_SM1CVAL5_OFFSET 0x00b4 /* Capture Value 5 Register */ -#define IMXRT_FLEXPWM_SM1CVAL5CYC_OFFSET 0x00b6 /* Capture Value 5 Cycle Register */ -#define IMXRT_FLEXPWM_SM2CNT_OFFSET 0x00c0 /* Counter Register */ -#define IMXRT_FLEXPWM_SM2INIT_OFFSET 0x00c2 /* Initial Count Register */ -#define IMXRT_FLEXPWM_SM2CTRL2_OFFSET 0x00c4 /* Control 2 Register */ -#define IMXRT_FLEXPWM_SM2CTRL_OFFSET 0x00c6 /* Control Register */ -#define IMXRT_FLEXPWM_SM2VAL0_OFFSET 0x00ca /* Value Register 0 */ -#define IMXRT_FLEXPWM_SM2FRACVAL1_OFFSET 0x00cc /* Fractional Value Register 1 */ -#define IMXRT_FLEXPWM_SM2VAL1_OFFSET 0x00ce /* Value Register 1 */ -#define IMXRT_FLEXPWM_SM2FRACVAL2_OFFSET 0x00d0 /* Fractional Value Register 2 */ -#define IMXRT_FLEXPWM_SM2VAL2_OFFSET 0x00d2 /* Value Register 2 */ -#define IMXRT_FLEXPWM_SM2FRACVAL3_OFFSET 0x00d4 /* Fractional Value Register 3 */ -#define IMXRT_FLEXPWM_SM2VAL3_OFFSET 0x00d6 /* Value Register 3 */ -#define IMXRT_FLEXPWM_SM2FRACVAL4_OFFSET 0x00d8 /* Fractional Value Register 4 */ -#define IMXRT_FLEXPWM_SM2VAL4_OFFSET 0x00da /* Value Register 4 */ -#define IMXRT_FLEXPWM_SM2FRACVAL5_OFFSET 0x00dc /* Fractional Value Register 5 */ -#define IMXRT_FLEXPWM_SM2VAL5_OFFSET 0x00de /* Value Register 5 */ -#define IMXRT_FLEXPWM_SM2FRCTRL_OFFSET 0x00e0 /* Fractional Control Register */ -#define IMXRT_FLEXPWM_SM2OCTRL_OFFSET 0x00e2 /* Output Control Register */ -#define IMXRT_FLEXPWM_SM2STS_OFFSET 0x00e4 /* Status Register */ -#define IMXRT_FLEXPWM_SM2INTEN_OFFSET 0x00e6 /* Interrupt Enable Register */ -#define IMXRT_FLEXPWM_SM2DMAEN_OFFSET 0x00e8 /* DMA Enable Register */ -#define IMXRT_FLEXPWM_SM2TCTRL_OFFSET 0x00ea /* Output Trigger Control Register */ -#define IMXRT_FLEXPWM_SM2DISMAP0_OFFSET 0x00ec /* Fault Disable Mapping Register 0 */ -#define IMXRT_FLEXPWM_SM2DISMAP1_OFFSET 0x00ee /* Fault Disable Mapping Register 1 */ -#define IMXRT_FLEXPWM_SM2DTCNT0_OFFSET 0x00f0 /* Deadtime Count Register 0 */ -#define IMXRT_FLEXPWM_SM2DTCNT1_OFFSET 0x00f2 /* Deadtime Count Register 1 */ -#define IMXRT_FLEXPWM_SM2CAPTCTRLA_OFFSET 0x00f4 /* Capture Control A Register */ -#define IMXRT_FLEXPWM_SM2CAPTCOMPA_OFFSET 0x00f6 /* Capture Compare A Register */ -#define IMXRT_FLEXPWM_SM2CAPTCTRLB_OFFSET 0x00f8 /* Capture Control B Register */ -#define IMXRT_FLEXPWM_SM2CAPTCOMPB_OFFSET 0x00fa /* Capture Compare B Register */ -#define IMXRT_FLEXPWM_SM2CAPTCTRLX_OFFSET 0x00fc /* Capture Control X Register */ -#define IMXRT_FLEXPWM_SM2CAPTCOMPX_OFFSET 0x00fe /* Capture Compare X Register */ -#define IMXRT_FLEXPWM_SM2CVAL0_OFFSET 0x0100 /* Capture Value 0 Register */ -#define IMXRT_FLEXPWM_SM2CVAL0CYC_OFFSET 0x0102 /* Capture Value 0 Cycle Register */ -#define IMXRT_FLEXPWM_SM2CVAL1_OFFSET 0x0104 /* Capture Value 1 Register */ -#define IMXRT_FLEXPWM_SM2CVAL1CYC_OFFSET 0x0106 /* Capture Value 1 Cycle Register */ -#define IMXRT_FLEXPWM_SM2CVAL2_OFFSET 0x0108 /* Capture Value 2 Register */ -#define IMXRT_FLEXPWM_SM2CVAL2CYC_OFFSET 0x010a /* Capture Value 2 Cycle Register */ -#define IMXRT_FLEXPWM_SM2CVAL3_OFFSET 0x010c /* Capture Value 3 Register */ -#define IMXRT_FLEXPWM_SM2CVAL3CYC_OFFSET 0x010e /* Capture Value 3 Cycle Register */ -#define IMXRT_FLEXPWM_SM2CVAL4_OFFSET 0x0110 /* Capture Value 4 Register */ -#define IMXRT_FLEXPWM_SM2CVAL4CYC_OFFSET 0x0112 /* Capture Value 4 Cycle Register */ -#define IMXRT_FLEXPWM_SM2CVAL5_OFFSET 0x0114 /* Capture Value 5 Register */ -#define IMXRT_FLEXPWM_SM2CVAL5CYC_OFFSET 0x0116 /* Capture Value 5 Cycle Register */ -#define IMXRT_FLEXPWM_SM3CNT_OFFSET 0x0120 /* Counter Register */ -#define IMXRT_FLEXPWM_SM3INIT_OFFSET 0x0122 /* Initial Count Register */ -#define IMXRT_FLEXPWM_SM3CTRL2_OFFSET 0x0124 /* Control 2 Register */ -#define IMXRT_FLEXPWM_SM3CTRL_OFFSET 0x0126 /* Control Register */ -#define IMXRT_FLEXPWM_SM3VAL0_OFFSET 0x012a /* Value Register 0 */ -#define IMXRT_FLEXPWM_SM3FRACVAL1_OFFSET 0x012c /* Fractional Value Register 1 */ -#define IMXRT_FLEXPWM_SM3VAL1_OFFSET 0x012e /* Value Register 1 */ -#define IMXRT_FLEXPWM_SM3FRACVAL2_OFFSET 0x0130 /* Fractional Value Register 2 */ -#define IMXRT_FLEXPWM_SM3VAL2_OFFSET 0x0132 /* Value Register 2 */ -#define IMXRT_FLEXPWM_SM3FRACVAL3_OFFSET 0x0134 /* Fractional Value Register 3 */ -#define IMXRT_FLEXPWM_SM3VAL3_OFFSET 0x0136 /* Value Register 3 */ -#define IMXRT_FLEXPWM_SM3FRACVAL4_OFFSET 0x0138 /* Fractional Value Register 4 */ -#define IMXRT_FLEXPWM_SM3VAL4_OFFSET 0x013a /* Value Register 4 */ -#define IMXRT_FLEXPWM_SM3FRACVAL5_OFFSET 0x013c /* Fractional Value Register 5 */ -#define IMXRT_FLEXPWM_SM3VAL5_OFFSET 0x013e /* Value Register 5 */ -#define IMXRT_FLEXPWM_SM3FRCTRL_OFFSET 0x0140 /* Fractional Control Register */ -#define IMXRT_FLEXPWM_SM3OCTRL_OFFSET 0x0142 /* Output Control Register */ -#define IMXRT_FLEXPWM_SM3STS_OFFSET 0x0144 /* Status Register */ -#define IMXRT_FLEXPWM_SM3INTEN_OFFSET 0x0146 /* Interrupt Enable Register */ -#define IMXRT_FLEXPWM_SM3DMAEN_OFFSET 0x0148 /* DMA Enable Register */ -#define IMXRT_FLEXPWM_SM3TCTRL_OFFSET 0x014a /* Output Trigger Control Register */ -#define IMXRT_FLEXPWM_SM3DISMAP0_OFFSET 0x014c /* Fault Disable Mapping Register 0 */ -#define IMXRT_FLEXPWM_SM3DISMAP1_OFFSET 0x014e /* Fault Disable Mapping Register 1 */ -#define IMXRT_FLEXPWM_SM3DTCNT0_OFFSET 0x0150 /* Deadtime Count Register 0 */ -#define IMXRT_FLEXPWM_SM3DTCNT1_OFFSET 0x0152 /* Deadtime Count Register 1 */ -#define IMXRT_FLEXPWM_SM3CAPTCTRLA_OFFSET 0x0154 /* Capture Control A Register */ -#define IMXRT_FLEXPWM_SM3CAPTCOMPA_OFFSET 0x0156 /* Capture Compare A Register */ -#define IMXRT_FLEXPWM_SM3CAPTCTRLB_OFFSET 0x0158 /* Capture Control B Register */ -#define IMXRT_FLEXPWM_SM3CAPTCOMPB_OFFSET 0x015a /* Capture Compare B Register */ -#define IMXRT_FLEXPWM_SM3CAPTCTRLX_OFFSET 0x015c /* Capture Control X Register */ -#define IMXRT_FLEXPWM_SM3CAPTCOMPX_OFFSET 0x015e /* Capture Compare X Register */ -#define IMXRT_FLEXPWM_SM3CVAL0_OFFSET 0x0160 /* Capture Value 0 Register */ -#define IMXRT_FLEXPWM_SM3CVAL0CYC_OFFSET 0x0162 /* Capture Value 0 Cycle Register */ -#define IMXRT_FLEXPWM_SM3CVAL1_OFFSET 0x0164 /* Capture Value 1 Register */ -#define IMXRT_FLEXPWM_SM3CVAL1CYC_OFFSET 0x0166 /* Capture Value 1 Cycle Register */ -#define IMXRT_FLEXPWM_SM3CVAL2_OFFSET 0x0168 /* Capture Value 2 Register */ -#define IMXRT_FLEXPWM_SM3CVAL2CYC_OFFSET 0x016a /* Capture Value 2 Cycle Register */ -#define IMXRT_FLEXPWM_SM3CVAL3_OFFSET 0x016c /* Capture Value 3 Register */ -#define IMXRT_FLEXPWM_SM3CVAL3CYC_OFFSET 0x016e /* Capture Value 3 Cycle Register */ -#define IMXRT_FLEXPWM_SM3CVAL4_OFFSET 0x0170 /* Capture Value 4 Register */ -#define IMXRT_FLEXPWM_SM3CVAL4CYC_OFFSET 0x0172 /* Capture Value 4 Cycle Register */ -#define IMXRT_FLEXPWM_SM3CVAL5_OFFSET 0x0174 /* Capture Value 5 Register */ -#define IMXRT_FLEXPWM_SM3CVAL5CYC_OFFSET 0x0176 /* Capture Value 5 Cycle Register */ -#define IMXRT_FLEXPWM_OUTEN_OFFSET 0x0180 /* Output Enable Register */ -#define IMXRT_FLEXPWM_MASK_OFFSET 0x0182 /* Mask Register */ -#define IMXRT_FLEXPWM_SWCOUT_OFFSET 0x0184 /* Software Controlled Output Register */ -#define IMXRT_FLEXPWM_DTSRCSEL_OFFSET 0x0186 /* PWM Source Select Register */ -#define IMXRT_FLEXPWM_MCTRL_OFFSET 0x0188 /* Master Control Register */ -#define IMXRT_FLEXPWM_MCTRL2_OFFSET 0x018a /* Master Control 2 Register */ -#define IMXRT_FLEXPWM_FCTRL0_OFFSET 0x018c /* Fault Control Register */ -#define IMXRT_FLEXPWM_FSTS0_OFFSET 0x018e /* Fault Status Register */ -#define IMXRT_FLEXPWM_FFILT0_OFFSET 0x0190 /* Fault Filter Register */ -#define IMXRT_FLEXPWM_FTST0_OFFSET 0x0192 /* Fault Test Register */ -#define IMXRT_FLEXPWM_FCTRL20_OFFSET 0x0194 /* Fault Control 2 Register */ - -/* Register addresses ***********************************************************************/ - -/* FLEXPWM1 Register Addresses */ - -#define IMXRT_FLEXPWM1_SM0CNT (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM0CNT_OFFSET) /* FLEXPWM1 Counter Register */ -#define IMXRT_FLEXPWM1_SM0INIT (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM0INIT_OFFSET) /* FLEXPWM1 Initial Count Register */ -#define IMXRT_FLEXPWM1_SM0CTRL2 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM0CTRL2_OFFSET) /* FLEXPWM1 Control 2 Register */ -#define IMXRT_FLEXPWM1_SM0CTRL (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM0CTRL_OFFSET) /* FLEXPWM1 Control Register */ -#define IMXRT_FLEXPWM1_SM0VAL0 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM0VAL0_OFFSET) /* FLEXPWM1 Value Register 0 */ -#define IMXRT_FLEXPWM1_SM0FRACVAL1 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM0FRACVAL1_OFFSET) /* FLEXPWM1 Fractional Value Register 1 */ -#define IMXRT_FLEXPWM1_SM0VAL1 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM0VAL1_OFFSET) /* FLEXPWM1 Value Register 1 */ -#define IMXRT_FLEXPWM1_SM0FRACVAL2 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM0FRACVAL2_OFFSET) /* FLEXPWM1 Fractional Value Register 2 */ -#define IMXRT_FLEXPWM1_SM0VAL2 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM0VAL2_OFFSET) /* FLEXPWM1 Value Register 2 */ -#define IMXRT_FLEXPWM1_SM0FRACVAL3 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM0FRACVAL3_OFFSET) /* FLEXPWM1 Fractional Value Register 3 */ -#define IMXRT_FLEXPWM1_SM0VAL3 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM0VAL3_OFFSET) /* FLEXPWM1 Value Register 3 */ -#define IMXRT_FLEXPWM1_SM0FRACVAL4 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM0FRACVAL4_OFFSET) /* FLEXPWM1 Fractional Value Register 4 */ -#define IMXRT_FLEXPWM1_SM0VAL4 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM0VAL4_OFFSET) /* FLEXPWM1 Value Register 4 */ -#define IMXRT_FLEXPWM1_SM0FRACVAL5 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM0FRACVAL5_OFFSET) /* FLEXPWM1 Fractional Value Register 5 */ -#define IMXRT_FLEXPWM1_SM0VAL5 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM0VAL5_OFFSET) /* FLEXPWM1 Value Register 5 */ -#define IMXRT_FLEXPWM1_SM0FRCTRL (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM0FRCTRL_OFFSET) /* FLEXPWM1 Fractional Control Register */ -#define IMXRT_FLEXPWM1_SM0OCTRL (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM0OCTRL_OFFSET) /* FLEXPWM1 Output Control Register */ -#define IMXRT_FLEXPWM1_SM0STS (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM0STS_OFFSET) /* FLEXPWM1 Status Register */ -#define IMXRT_FLEXPWM1_SM0INTEN (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM0INTEN_OFFSET) /* FLEXPWM1 Interrupt Enable Register */ -#define IMXRT_FLEXPWM1_SM0DMAEN (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM0DMAEN_OFFSET) /* FLEXPWM1 DMA Enable Register */ -#define IMXRT_FLEXPWM1_SM0TCTRL (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM0TCTRL_OFFSET) /* FLEXPWM1 Output Trigger Control Register */ -#define IMXRT_FLEXPWM1_SM0DISMAP0 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM0DISMAP0_OFFSET) /* FLEXPWM1 Fault Disable Mapping Register 0 */ -#define IMXRT_FLEXPWM1_SM0DISMAP1 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM0DISMAP1_OFFSET) /* FLEXPWM1 Fault Disable Mapping Register 1 */ -#define IMXRT_FLEXPWM1_SM0DTCNT0 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM0DTCNT0_OFFSET) /* FLEXPWM1 Deadtime Count Register 0 */ -#define IMXRT_FLEXPWM1_SM0DTCNT1 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM0DTCNT1_OFFSET) /* FLEXPWM1 Deadtime Count Register 1 */ -#define IMXRT_FLEXPWM1_SM0CAPTCTRLA (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM0CAPTCTRLA_OFFSET) /* FLEXPWM1 Capture Control A Register */ -#define IMXRT_FLEXPWM1_SM0CAPTCOMPA (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM0CAPTCOMPA_OFFSET) /* FLEXPWM1 Capture Compare A Register */ -#define IMXRT_FLEXPWM1_SM0CAPTCTRLB (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM0CAPTCTRLB_OFFSET) /* FLEXPWM1 Capture Control B Register */ -#define IMXRT_FLEXPWM1_SM0CAPTCOMPB (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM0CAPTCOMPB_OFFSET) /* FLEXPWM1 Capture Compare B Register */ -#define IMXRT_FLEXPWM1_SM0CAPTCTRLX (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM0CAPTCTRLX_OFFSET) /* FLEXPWM1 Capture Control X Register */ -#define IMXRT_FLEXPWM1_SM0CAPTCOMPX (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM0CAPTCOMPX_OFFSET) /* FLEXPWM1 Capture Compare X Register */ -#define IMXRT_FLEXPWM1_SM0CVAL0 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM0CVAL0_OFFSET) /* FLEXPWM1 Capture Value 0 Register */ -#define IMXRT_FLEXPWM1_SM0CVAL0CYC (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM0CVAL0CYC_OFFSET) /* FLEXPWM1 Capture Value 0 Cycle Register */ -#define IMXRT_FLEXPWM1_SM0CVAL1 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM0CVAL1_OFFSET) /* FLEXPWM1 Capture Value 1 Register */ -#define IMXRT_FLEXPWM1_SM0CVAL1CYC (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM0CVAL1CYC_OFFSET) /* FLEXPWM1 Capture Value 1 Cycle Register */ -#define IMXRT_FLEXPWM1_SM0CVAL2 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM0CVAL2_OFFSET) /* FLEXPWM1 Capture Value 2 Register */ -#define IMXRT_FLEXPWM1_SM0CVAL2CYC (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM0CVAL2CYC_OFFSET) /* FLEXPWM1 Capture Value 2 Cycle Register */ -#define IMXRT_FLEXPWM1_SM0CVAL3 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM0CVAL3_OFFSET) /* FLEXPWM1 Capture Value 3 Register */ -#define IMXRT_FLEXPWM1_SM0CVAL3CYC (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM0CVAL3CYC_OFFSET) /* FLEXPWM1 Capture Value 3 Cycle Register */ -#define IMXRT_FLEXPWM1_SM0CVAL4 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM0CVAL4_OFFSET) /* FLEXPWM1 Capture Value 4 Register */ -#define IMXRT_FLEXPWM1_SM0CVAL4CYC (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM0CVAL4CYC_OFFSET) /* FLEXPWM1 Capture Value 4 Cycle Register */ -#define IMXRT_FLEXPWM1_SM0CVAL5 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM0CVAL5_OFFSET) /* FLEXPWM1 Capture Value 5 Register */ -#define IMXRT_FLEXPWM1_SM0CVAL5CYC (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM0CVAL5CYC_OFFSET) /* FLEXPWM1 Capture Value 5 Cycle Register */ -#define IMXRT_FLEXPWM1_SM1CNT (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM1CNT_OFFSET) /* FLEXPWM1 Counter Register */ -#define IMXRT_FLEXPWM1_SM1INIT (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM1INIT_OFFSET) /* FLEXPWM1 Initial Count Register */ -#define IMXRT_FLEXPWM1_SM1CTRL2 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM1CTRL2_OFFSET) /* FLEXPWM1 Control 2 Register */ -#define IMXRT_FLEXPWM1_SM1CTRL (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM1CTRL_OFFSET) /* FLEXPWM1 Control Register */ -#define IMXRT_FLEXPWM1_SM1VAL0 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM1VAL0_OFFSET) /* FLEXPWM1 Value Register 0 */ -#define IMXRT_FLEXPWM1_SM1FRACVAL1 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM1FRACVAL1_OFFSET) /* FLEXPWM1 Fractional Value Register 1 */ -#define IMXRT_FLEXPWM1_SM1VAL1 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM1VAL1_OFFSET) /* FLEXPWM1 Value Register 1 */ -#define IMXRT_FLEXPWM1_SM1FRACVAL2 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM1FRACVAL2_OFFSET) /* FLEXPWM1 Fractional Value Register 2 */ -#define IMXRT_FLEXPWM1_SM1VAL2 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM1VAL2_OFFSET) /* FLEXPWM1 Value Register 2 */ -#define IMXRT_FLEXPWM1_SM1FRACVAL3 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM1FRACVAL3_OFFSET) /* FLEXPWM1 Fractional Value Register 3 */ -#define IMXRT_FLEXPWM1_SM1VAL3 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM1VAL3_OFFSET) /* FLEXPWM1 Value Register 3 */ -#define IMXRT_FLEXPWM1_SM1FRACVAL4 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM1FRACVAL4_OFFSET) /* FLEXPWM1 Fractional Value Register 4 */ -#define IMXRT_FLEXPWM1_SM1VAL4 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM1VAL4_OFFSET) /* FLEXPWM1 Value Register 4 */ -#define IMXRT_FLEXPWM1_SM1FRACVAL5 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM1FRACVAL5_OFFSET) /* FLEXPWM1 Fractional Value Register 5 */ -#define IMXRT_FLEXPWM1_SM1VAL5 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM1VAL5_OFFSET) /* FLEXPWM1 Value Register 5 */ -#define IMXRT_FLEXPWM1_SM1FRCTRL (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM1FRCTRL_OFFSET) /* FLEXPWM1 Fractional Control Register */ -#define IMXRT_FLEXPWM1_SM1OCTRL (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM1OCTRL_OFFSET) /* FLEXPWM1 Output Control Register */ -#define IMXRT_FLEXPWM1_SM1STS (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM1STS_OFFSET) /* FLEXPWM1 Status Register */ -#define IMXRT_FLEXPWM1_SM1INTEN (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM1INTEN_OFFSET) /* FLEXPWM1 Interrupt Enable Register */ -#define IMXRT_FLEXPWM1_SM1DMAEN (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM1DMAEN_OFFSET) /* FLEXPWM1 DMA Enable Register */ -#define IMXRT_FLEXPWM1_SM1TCTRL (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM1TCTRL_OFFSET) /* FLEXPWM1 Output Trigger Control Register */ -#define IMXRT_FLEXPWM1_SM1DISMAP0 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM1DISMAP0_OFFSET) /* FLEXPWM1 Fault Disable Mapping Register 0 */ -#define IMXRT_FLEXPWM1_SM1DISMAP1 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM1DISMAP1_OFFSET) /* FLEXPWM1 Fault Disable Mapping Register 1 */ -#define IMXRT_FLEXPWM1_SM1DTCNT0 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM1DTCNT0_OFFSET) /* FLEXPWM1 Deadtime Count Register 0 */ -#define IMXRT_FLEXPWM1_SM1DTCNT1 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM1DTCNT1_OFFSET) /* FLEXPWM1 Deadtime Count Register 1 */ -#define IMXRT_FLEXPWM1_SM1CAPTCTRLA (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM1CAPTCTRLA_OFFSET) /* FLEXPWM1 Capture Control A Register */ -#define IMXRT_FLEXPWM1_SM1CAPTCOMPA (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM1CAPTCOMPA_OFFSET) /* FLEXPWM1 Capture Compare A Register */ -#define IMXRT_FLEXPWM1_eFlexPWM (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_eFlexPWM_OFFSET) /* FLEXPWM1 apter 28 Enhanced Flex Pulse Width Modulator */ -#define IMXRT_FLEXPWM1_SM1CAPTCTRLB (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM1CAPTCTRLB_OFFSET) /* FLEXPWM1 Capture Control B Register */ -#define IMXRT_FLEXPWM1_SM1CAPTCOMPB (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM1CAPTCOMPB_OFFSET) /* FLEXPWM1 Capture Compare B Register */ -#define IMXRT_FLEXPWM1_SM1CAPTCTRLX (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM1CAPTCTRLX_OFFSET) /* FLEXPWM1 Capture Control X Register */ -#define IMXRT_FLEXPWM1_SM1CAPTCOMPX (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM1CAPTCOMPX_OFFSET) /* FLEXPWM1 Capture Compare X Register */ -#define IMXRT_FLEXPWM1_SM1CVAL0 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM1CVAL0_OFFSET) /* FLEXPWM1 Capture Value 0 Register */ -#define IMXRT_FLEXPWM1_SM1CVAL0CYC (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM1CVAL0CYC_OFFSET) /* FLEXPWM1 Capture Value 0 Cycle Register */ -#define IMXRT_FLEXPWM1_SM1CVAL1 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM1CVAL1_OFFSET) /* FLEXPWM1 Capture Value 1 Register */ -#define IMXRT_FLEXPWM1_SM1CVAL1CYC (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM1CVAL1CYC_OFFSET) /* FLEXPWM1 Capture Value 1 Cycle Register */ -#define IMXRT_FLEXPWM1_SM1CVAL2 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM1CVAL2_OFFSET) /* FLEXPWM1 Capture Value 2 Register */ -#define IMXRT_FLEXPWM1_SM1CVAL2CYC (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM1CVAL2CYC_OFFSET) /* FLEXPWM1 Capture Value 2 Cycle Register */ -#define IMXRT_FLEXPWM1_SM1CVAL3 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM1CVAL3_OFFSET) /* FLEXPWM1 Capture Value 3 Register */ -#define IMXRT_FLEXPWM1_SM1CVAL3CYC (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM1CVAL3CYC_OFFSET) /* FLEXPWM1 Capture Value 3 Cycle Register */ -#define IMXRT_FLEXPWM1_SM1CVAL4 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM1CVAL4_OFFSET) /* FLEXPWM1 Capture Value 4 Register */ -#define IMXRT_FLEXPWM1_SM1CVAL4CYC (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM1CVAL4CYC_OFFSET) /* FLEXPWM1 Capture Value 4 Cycle Register */ -#define IMXRT_FLEXPWM1_SM1CVAL5 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM1CVAL5_OFFSET) /* FLEXPWM1 Capture Value 5 Register */ -#define IMXRT_FLEXPWM1_SM1CVAL5CYC (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM1CVAL5CYC_OFFSET) /* FLEXPWM1 Capture Value 5 Cycle Register */ -#define IMXRT_FLEXPWM1_SM2CNT (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM2CNT_OFFSET) /* FLEXPWM1 Counter Register */ -#define IMXRT_FLEXPWM1_SM2INIT (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM2INIT_OFFSET) /* FLEXPWM1 Initial Count Register */ -#define IMXRT_FLEXPWM1_SM2CTRL2 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM2CTRL2_OFFSET) /* FLEXPWM1 Control 2 Register */ -#define IMXRT_FLEXPWM1_SM2CTRL (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM2CTRL_OFFSET) /* FLEXPWM1 Control Register */ -#define IMXRT_FLEXPWM1_SM2VAL0 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM2VAL0_OFFSET) /* FLEXPWM1 Value Register 0 */ -#define IMXRT_FLEXPWM1_SM2FRACVAL1 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM2FRACVAL1_OFFSET) /* FLEXPWM1 Fractional Value Register 1 */ -#define IMXRT_FLEXPWM1_SM2VAL1 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM2VAL1_OFFSET) /* FLEXPWM1 Value Register 1 */ -#define IMXRT_FLEXPWM1_SM2FRACVAL2 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM2FRACVAL2_OFFSET) /* FLEXPWM1 Fractional Value Register 2 */ -#define IMXRT_FLEXPWM1_SM2VAL2 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM2VAL2_OFFSET) /* FLEXPWM1 Value Register 2 */ -#define IMXRT_FLEXPWM1_SM2FRACVAL3 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM2FRACVAL3_OFFSET) /* FLEXPWM1 Fractional Value Register 3 */ -#define IMXRT_FLEXPWM1_SM2VAL3 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM2VAL3_OFFSET) /* FLEXPWM1 Value Register 3 */ -#define IMXRT_FLEXPWM1_SM2FRACVAL4 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM2FRACVAL4_OFFSET) /* FLEXPWM1 Fractional Value Register 4 */ -#define IMXRT_FLEXPWM1_SM2VAL4 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM2VAL4_OFFSET) /* FLEXPWM1 Value Register 4 */ -#define IMXRT_FLEXPWM1_SM2FRACVAL5 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM2FRACVAL5_OFFSET) /* FLEXPWM1 Fractional Value Register 5 */ -#define IMXRT_FLEXPWM1_SM2VAL5 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM2VAL5_OFFSET) /* FLEXPWM1 Value Register 5 */ -#define IMXRT_FLEXPWM1_SM2FRCTRL (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM2FRCTRL_OFFSET) /* FLEXPWM1 Fractional Control Register */ -#define IMXRT_FLEXPWM1_SM2OCTRL (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM2OCTRL_OFFSET) /* FLEXPWM1 Output Control Register */ -#define IMXRT_FLEXPWM1_SM2STS (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM2STS_OFFSET) /* FLEXPWM1 Status Register */ -#define IMXRT_FLEXPWM1_SM2INTEN (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM2INTEN_OFFSET) /* FLEXPWM1 Interrupt Enable Register */ -#define IMXRT_FLEXPWM1_SM2DMAEN (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM2DMAEN_OFFSET) /* FLEXPWM1 DMA Enable Register */ -#define IMXRT_FLEXPWM1_SM2TCTRL (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM2TCTRL_OFFSET) /* FLEXPWM1 Output Trigger Control Register */ -#define IMXRT_FLEXPWM1_SM2DISMAP0 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM2DISMAP0_OFFSET) /* FLEXPWM1 Fault Disable Mapping Register 0 */ -#define IMXRT_FLEXPWM1_SM2DISMAP1 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM2DISMAP1_OFFSET) /* FLEXPWM1 Fault Disable Mapping Register 1 */ -#define IMXRT_FLEXPWM1_SM2DTCNT0 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM2DTCNT0_OFFSET) /* FLEXPWM1 Deadtime Count Register 0 */ -#define IMXRT_FLEXPWM1_SM2DTCNT1 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM2DTCNT1_OFFSET) /* FLEXPWM1 Deadtime Count Register 1 */ -#define IMXRT_FLEXPWM1_SM2CAPTCTRLA (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM2CAPTCTRLA_OFFSET) /* FLEXPWM1 Capture Control A Register */ -#define IMXRT_FLEXPWM1_SM2CAPTCOMPA (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM2CAPTCOMPA_OFFSET) /* FLEXPWM1 Capture Compare A Register */ -#define IMXRT_FLEXPWM1_SM2CAPTCTRLB (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM2CAPTCTRLB_OFFSET) /* FLEXPWM1 Capture Control B Register */ -#define IMXRT_FLEXPWM1_SM2CAPTCOMPB (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM2CAPTCOMPB_OFFSET) /* FLEXPWM1 Capture Compare B Register */ -#define IMXRT_FLEXPWM1_SM2CAPTCTRLX (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM2CAPTCTRLX_OFFSET) /* FLEXPWM1 Capture Control X Register */ -#define IMXRT_FLEXPWM1_SM2CAPTCOMPX (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM2CAPTCOMPX_OFFSET) /* FLEXPWM1 Capture Compare X Register */ -#define IMXRT_FLEXPWM1_SM2CVAL0 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM2CVAL0_OFFSET) /* FLEXPWM1 Capture Value 0 Register */ -#define IMXRT_FLEXPWM1_SM2CVAL0CYC (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM2CVAL0CYC_OFFSET) /* FLEXPWM1 Capture Value 0 Cycle Register */ -#define IMXRT_FLEXPWM1_SM2CVAL1 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM2CVAL1_OFFSET) /* FLEXPWM1 Capture Value 1 Register */ -#define IMXRT_FLEXPWM1_SM2CVAL1CYC (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM2CVAL1CYC_OFFSET) /* FLEXPWM1 Capture Value 1 Cycle Register */ -#define IMXRT_FLEXPWM1_SM2CVAL2 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM2CVAL2_OFFSET) /* FLEXPWM1 Capture Value 2 Register */ -#define IMXRT_FLEXPWM1_SM2CVAL2CYC (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM2CVAL2CYC_OFFSET) /* FLEXPWM1 Capture Value 2 Cycle Register */ -#define IMXRT_FLEXPWM1_SM2CVAL3 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM2CVAL3_OFFSET) /* FLEXPWM1 Capture Value 3 Register */ -#define IMXRT_FLEXPWM1_SM2CVAL3CYC (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM2CVAL3CYC_OFFSET) /* FLEXPWM1 Capture Value 3 Cycle Register */ -#define IMXRT_FLEXPWM1_SM2CVAL4 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM2CVAL4_OFFSET) /* FLEXPWM1 Capture Value 4 Register */ -#define IMXRT_FLEXPWM1_SM2CVAL4CYC (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM2CVAL4CYC_OFFSET) /* FLEXPWM1 Capture Value 4 Cycle Register */ -#define IMXRT_FLEXPWM1_SM2CVAL5 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM2CVAL5_OFFSET) /* FLEXPWM1 Capture Value 5 Register */ -#define IMXRT_FLEXPWM1_SM2CVAL5CYC (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM2CVAL5CYC_OFFSET) /* FLEXPWM1 Capture Value 5 Cycle Register */ -#define IMXRT_FLEXPWM1_SM3CNT (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM3CNT_OFFSET) /* FLEXPWM1 Counter Register */ -#define IMXRT_FLEXPWM1_SM3INIT (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM3INIT_OFFSET) /* FLEXPWM1 Initial Count Register */ -#define IMXRT_FLEXPWM1_SM3CTRL2 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM3CTRL2_OFFSET) /* FLEXPWM1 Control 2 Register */ -#define IMXRT_FLEXPWM1_SM3CTRL (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM3CTRL_OFFSET) /* FLEXPWM1 Control Register */ -#define IMXRT_FLEXPWM1_SM3VAL0 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM3VAL0_OFFSET) /* FLEXPWM1 Value Register 0 */ -#define IMXRT_FLEXPWM1_SM3FRACVAL1 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM3FRACVAL1_OFFSET) /* FLEXPWM1 Fractional Value Register 1 */ -#define IMXRT_FLEXPWM1_SM3VAL1 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM3VAL1_OFFSET) /* FLEXPWM1 Value Register 1 */ -#define IMXRT_FLEXPWM1_SM3FRACVAL2 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM3FRACVAL2_OFFSET) /* FLEXPWM1 Fractional Value Register 2 */ -#define IMXRT_FLEXPWM1_SM3VAL2 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM3VAL2_OFFSET) /* FLEXPWM1 Value Register 2 */ -#define IMXRT_FLEXPWM1_SM3FRACVAL3 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM3FRACVAL3_OFFSET) /* FLEXPWM1 Fractional Value Register 3 */ -#define IMXRT_FLEXPWM1_SM3VAL3 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM3VAL3_OFFSET) /* FLEXPWM1 Value Register 3 */ -#define IMXRT_FLEXPWM1_SM3FRACVAL4 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM3FRACVAL4_OFFSET) /* FLEXPWM1 Fractional Value Register 4 */ -#define IMXRT_FLEXPWM1_SM3VAL4 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM3VAL4_OFFSET) /* FLEXPWM1 Value Register 4 */ -#define IMXRT_FLEXPWM1_SM3FRACVAL5 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM3FRACVAL5_OFFSET) /* FLEXPWM1 Fractional Value Register 5 */ -#define IMXRT_FLEXPWM1_SM3VAL5 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM3VAL5_OFFSET) /* FLEXPWM1 Value Register 5 */ -#define IMXRT_FLEXPWM1_SM3FRCTRL (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM3FRCTRL_OFFSET) /* FLEXPWM1 Fractional Control Register */ -#define IMXRT_FLEXPWM1_SM3OCTRL (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM3OCTRL_OFFSET) /* FLEXPWM1 Output Control Register */ -#define IMXRT_FLEXPWM1_SM3STS (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM3STS_OFFSET) /* FLEXPWM1 Status Register */ -#define IMXRT_FLEXPWM1_SM3INTEN (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM3INTEN_OFFSET) /* FLEXPWM1 Interrupt Enable Register */ -#define IMXRT_FLEXPWM1_SM3DMAEN (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM3DMAEN_OFFSET) /* FLEXPWM1 DMA Enable Register */ -#define IMXRT_FLEXPWM1_SM3TCTRL (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM3TCTRL_OFFSET) /* FLEXPWM1 Output Trigger Control Register */ -#define IMXRT_FLEXPWM1_SM3DISMAP0 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM3DISMAP0_OFFSET) /* FLEXPWM1 Fault Disable Mapping Register 0 */ -#define IMXRT_FLEXPWM1_SM3DISMAP1 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM3DISMAP1_OFFSET) /* FLEXPWM1 Fault Disable Mapping Register 1 */ -#define IMXRT_FLEXPWM1_SM3DTCNT0 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM3DTCNT0_OFFSET) /* FLEXPWM1 Deadtime Count Register 0 */ -#define IMXRT_FLEXPWM1_SM3DTCNT1 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM3DTCNT1_OFFSET) /* FLEXPWM1 Deadtime Count Register 1 */ -#define IMXRT_FLEXPWM1_SM3CAPTCTRLA (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM3CAPTCTRLA_OFFSET) /* FLEXPWM1 Capture Control A Register */ -#define IMXRT_FLEXPWM1_SM3CAPTCOMPA (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM3CAPTCOMPA_OFFSET) /* FLEXPWM1 Capture Compare A Register */ -#define IMXRT_FLEXPWM1_SM3CAPTCTRLB (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM3CAPTCTRLB_OFFSET) /* FLEXPWM1 Capture Control B Register */ -#define IMXRT_FLEXPWM1_SM3CAPTCOMPB (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM3CAPTCOMPB_OFFSET) /* FLEXPWM1 Capture Compare B Register */ -#define IMXRT_FLEXPWM1_SM3CAPTCTRLX (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM3CAPTCTRLX_OFFSET) /* FLEXPWM1 Capture Control X Register */ -#define IMXRT_FLEXPWM1_SM3CAPTCOMPX (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM3CAPTCOMPX_OFFSET) /* FLEXPWM1 Capture Compare X Register */ -#define IMXRT_FLEXPWM1_SM3CVAL0 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM3CVAL0_OFFSET) /* FLEXPWM1 Capture Value 0 Register */ -#define IMXRT_FLEXPWM1_SM3CVAL0CYC (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM3CVAL0CYC_OFFSET) /* FLEXPWM1 Capture Value 0 Cycle Register */ -#define IMXRT_FLEXPWM1_SM3CVAL1 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM3CVAL1_OFFSET) /* FLEXPWM1 Capture Value 1 Register */ -#define IMXRT_FLEXPWM1_SM3CVAL1CYC (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM3CVAL1CYC_OFFSET) /* FLEXPWM1 Capture Value 1 Cycle Register */ -#define IMXRT_FLEXPWM1_SM3CVAL2 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM3CVAL2_OFFSET) /* FLEXPWM1 Capture Value 2 Register */ -#define IMXRT_FLEXPWM1_SM3CVAL2CYC (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM3CVAL2CYC_OFFSET) /* FLEXPWM1 Capture Value 2 Cycle Register */ -#define IMXRT_FLEXPWM1_SM3CVAL3 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM3CVAL3_OFFSET) /* FLEXPWM1 Capture Value 3 Register */ -#define IMXRT_FLEXPWM1_SM3CVAL3CYC (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM3CVAL3CYC_OFFSET) /* FLEXPWM1 Capture Value 3 Cycle Register */ -#define IMXRT_FLEXPWM1_SM3CVAL4 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM3CVAL4_OFFSET) /* FLEXPWM1 Capture Value 4 Register */ -#define IMXRT_FLEXPWM1_SM3CVAL4CYC (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM3CVAL4CYC_OFFSET) /* FLEXPWM1 Capture Value 4 Cycle Register */ -#define IMXRT_FLEXPWM1_SM3CVAL5 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM3CVAL5_OFFSET) /* FLEXPWM1 Capture Value 5 Register */ -#define IMXRT_FLEXPWM1_SM3CVAL5CYC (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SM3CVAL5CYC_OFFSET) /* FLEXPWM1 Capture Value 5 Cycle Register */ -#define IMXRT_FLEXPWM1_OUTEN (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_OUTEN_OFFSET) /* FLEXPWM1 Output Enable Register */ -#define IMXRT_FLEXPWM1_MASK (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_MASK_OFFSET) /* FLEXPWM1 Mask Register */ -#define IMXRT_FLEXPWM1_SWCOUT (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_SWCOUT_OFFSET) /* FLEXPWM1 Software Controlled Output Register */ -#define IMXRT_FLEXPWM1_DTSRCSEL (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_DTSRCSEL_OFFSET) /* FLEXPWM1 PWM Source Select Register */ -#define IMXRT_FLEXPWM1_MCTRL (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_MCTRL_OFFSET) /* FLEXPWM1 Master Control Register */ -#define IMXRT_FLEXPWM1_MCTRL2 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_MCTRL2_OFFSET) /* FLEXPWM1 Master Control 2 Register */ -#define IMXRT_FLEXPWM1_FCTRL0 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_FCTRL0_OFFSET) /* FLEXPWM1 Fault Control Register */ -#define IMXRT_FLEXPWM1_FSTS0 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_FSTS0_OFFSET) /* FLEXPWM1 Fault Status Register */ -#define IMXRT_FLEXPWM1_FFILT0 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_FFILT0_OFFSET) /* FLEXPWM1 Fault Filter Register */ -#define IMXRT_FLEXPWM1_FTST0 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_FTST0_OFFSET) /* FLEXPWM1 Fault Test Register */ -#define IMXRT_FLEXPWM1_FCTRL20 (IMXRT_FLEXPWM1_BASE + IMXRT_FLEXPWM_FCTRL20_OFFSET) /* FLEXPWM1 Fault Control 2 Register */ - -/* FLEXPWM2 Register Addresses */ - -#define IMXRT_FLEXPWM2_SM0CNT (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM0CNT_OFFSET) /* FLEXPWM2 Counter Register */ -#define IMXRT_FLEXPWM2_SM0INIT (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM0INIT_OFFSET) /* FLEXPWM2 Initial Count Register */ -#define IMXRT_FLEXPWM2_SM0CTRL2 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM0CTRL2_OFFSET) /* FLEXPWM2 Control 2 Register */ -#define IMXRT_FLEXPWM2_SM0CTRL (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM0CTRL_OFFSET) /* FLEXPWM2 Control Register */ -#define IMXRT_FLEXPWM2_SM0VAL0 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM0VAL0_OFFSET) /* FLEXPWM2 Value Register 0 */ -#define IMXRT_FLEXPWM2_SM0FRACVAL1 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM0FRACVAL1_OFFSET) /* FLEXPWM2 Fractional Value Register 1 */ -#define IMXRT_FLEXPWM2_SM0VAL1 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM0VAL1_OFFSET) /* FLEXPWM2 Value Register 1 */ -#define IMXRT_FLEXPWM2_SM0FRACVAL2 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM0FRACVAL2_OFFSET) /* FLEXPWM2 Fractional Value Register 2 */ -#define IMXRT_FLEXPWM2_SM0VAL2 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM0VAL2_OFFSET) /* FLEXPWM2 Value Register 2 */ -#define IMXRT_FLEXPWM2_SM0FRACVAL3 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM0FRACVAL3_OFFSET) /* FLEXPWM2 Fractional Value Register 3 */ -#define IMXRT_FLEXPWM2_SM0VAL3 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM0VAL3_OFFSET) /* FLEXPWM2 Value Register 3 */ -#define IMXRT_FLEXPWM2_SM0FRACVAL4 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM0FRACVAL4_OFFSET) /* FLEXPWM2 Fractional Value Register 4 */ -#define IMXRT_FLEXPWM2_SM0VAL4 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM0VAL4_OFFSET) /* FLEXPWM2 Value Register 4 */ -#define IMXRT_FLEXPWM2_SM0FRACVAL5 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM0FRACVAL5_OFFSET) /* FLEXPWM2 Fractional Value Register 5 */ -#define IMXRT_FLEXPWM2_SM0VAL5 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM0VAL5_OFFSET) /* FLEXPWM2 Value Register 5 */ -#define IMXRT_FLEXPWM2_SM0FRCTRL (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM0FRCTRL_OFFSET) /* FLEXPWM2 Fractional Control Register */ -#define IMXRT_FLEXPWM2_SM0OCTRL (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM0OCTRL_OFFSET) /* FLEXPWM2 Output Control Register */ -#define IMXRT_FLEXPWM2_SM0STS (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM0STS_OFFSET) /* FLEXPWM2 Status Register */ -#define IMXRT_FLEXPWM2_SM0INTEN (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM0INTEN_OFFSET) /* FLEXPWM2 Interrupt Enable Register */ -#define IMXRT_FLEXPWM2_SM0DMAEN (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM0DMAEN_OFFSET) /* FLEXPWM2 DMA Enable Register */ -#define IMXRT_FLEXPWM2_SM0TCTRL (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM0TCTRL_OFFSET) /* FLEXPWM2 Output Trigger Control Register */ -#define IMXRT_FLEXPWM2_SM0DISMAP0 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM0DISMAP0_OFFSET) /* FLEXPWM2 Fault Disable Mapping Register 0 */ -#define IMXRT_FLEXPWM2_SM0DISMAP1 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM0DISMAP1_OFFSET) /* FLEXPWM2 Fault Disable Mapping Register 1 */ -#define IMXRT_FLEXPWM2_SM0DTCNT0 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM0DTCNT0_OFFSET) /* FLEXPWM2 Deadtime Count Register 0 */ -#define IMXRT_FLEXPWM2_SM0DTCNT1 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM0DTCNT1_OFFSET) /* FLEXPWM2 Deadtime Count Register 1 */ -#define IMXRT_FLEXPWM2_SM0CAPTCTRLA (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM0CAPTCTRLA_OFFSET) /* FLEXPWM2 Capture Control A Register */ -#define IMXRT_FLEXPWM2_SM0CAPTCOMPA (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM0CAPTCOMPA_OFFSET) /* FLEXPWM2 Capture Compare A Register */ -#define IMXRT_FLEXPWM2_SM0CAPTCTRLB (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM0CAPTCTRLB_OFFSET) /* FLEXPWM2 Capture Control B Register */ -#define IMXRT_FLEXPWM2_SM0CAPTCOMPB (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM0CAPTCOMPB_OFFSET) /* FLEXPWM2 Capture Compare B Register */ -#define IMXRT_FLEXPWM2_SM0CAPTCTRLX (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM0CAPTCTRLX_OFFSET) /* FLEXPWM2 Capture Control X Register */ -#define IMXRT_FLEXPWM2_SM0CAPTCOMPX (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM0CAPTCOMPX_OFFSET) /* FLEXPWM2 Capture Compare X Register */ -#define IMXRT_FLEXPWM2_SM0CVAL0 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM0CVAL0_OFFSET) /* FLEXPWM2 Capture Value 0 Register */ -#define IMXRT_FLEXPWM2_SM0CVAL0CYC (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM0CVAL0CYC_OFFSET) /* FLEXPWM2 Capture Value 0 Cycle Register */ -#define IMXRT_FLEXPWM2_SM0CVAL1 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM0CVAL1_OFFSET) /* FLEXPWM2 Capture Value 1 Register */ -#define IMXRT_FLEXPWM2_SM0CVAL1CYC (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM0CVAL1CYC_OFFSET) /* FLEXPWM2 Capture Value 1 Cycle Register */ -#define IMXRT_FLEXPWM2_SM0CVAL2 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM0CVAL2_OFFSET) /* FLEXPWM2 Capture Value 2 Register */ -#define IMXRT_FLEXPWM2_SM0CVAL2CYC (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM0CVAL2CYC_OFFSET) /* FLEXPWM2 Capture Value 2 Cycle Register */ -#define IMXRT_FLEXPWM2_SM0CVAL3 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM0CVAL3_OFFSET) /* FLEXPWM2 Capture Value 3 Register */ -#define IMXRT_FLEXPWM2_SM0CVAL3CYC (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM0CVAL3CYC_OFFSET) /* FLEXPWM2 Capture Value 3 Cycle Register */ -#define IMXRT_FLEXPWM2_SM0CVAL4 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM0CVAL4_OFFSET) /* FLEXPWM2 Capture Value 4 Register */ -#define IMXRT_FLEXPWM2_SM0CVAL4CYC (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM0CVAL4CYC_OFFSET) /* FLEXPWM2 Capture Value 4 Cycle Register */ -#define IMXRT_FLEXPWM2_SM0CVAL5 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM0CVAL5_OFFSET) /* FLEXPWM2 Capture Value 5 Register */ -#define IMXRT_FLEXPWM2_SM0CVAL5CYC (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM0CVAL5CYC_OFFSET) /* FLEXPWM2 Capture Value 5 Cycle Register */ -#define IMXRT_FLEXPWM2_SM1CNT (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM1CNT_OFFSET) /* FLEXPWM2 Counter Register */ -#define IMXRT_FLEXPWM2_SM1INIT (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM1INIT_OFFSET) /* FLEXPWM2 Initial Count Register */ -#define IMXRT_FLEXPWM2_SM1CTRL2 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM1CTRL2_OFFSET) /* FLEXPWM2 Control 2 Register */ -#define IMXRT_FLEXPWM2_SM1CTRL (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM1CTRL_OFFSET) /* FLEXPWM2 Control Register */ -#define IMXRT_FLEXPWM2_SM1VAL0 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM1VAL0_OFFSET) /* FLEXPWM2 Value Register 0 */ -#define IMXRT_FLEXPWM2_SM1FRACVAL1 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM1FRACVAL1_OFFSET) /* FLEXPWM2 Fractional Value Register 1 */ -#define IMXRT_FLEXPWM2_SM1VAL1 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM1VAL1_OFFSET) /* FLEXPWM2 Value Register 1 */ -#define IMXRT_FLEXPWM2_SM1FRACVAL2 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM1FRACVAL2_OFFSET) /* FLEXPWM2 Fractional Value Register 2 */ -#define IMXRT_FLEXPWM2_SM1VAL2 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM1VAL2_OFFSET) /* FLEXPWM2 Value Register 2 */ -#define IMXRT_FLEXPWM2_SM1FRACVAL3 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM1FRACVAL3_OFFSET) /* FLEXPWM2 Fractional Value Register 3 */ -#define IMXRT_FLEXPWM2_SM1VAL3 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM1VAL3_OFFSET) /* FLEXPWM2 Value Register 3 */ -#define IMXRT_FLEXPWM2_SM1FRACVAL4 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM1FRACVAL4_OFFSET) /* FLEXPWM2 Fractional Value Register 4 */ -#define IMXRT_FLEXPWM2_SM1VAL4 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM1VAL4_OFFSET) /* FLEXPWM2 Value Register 4 */ -#define IMXRT_FLEXPWM2_SM1FRACVAL5 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM1FRACVAL5_OFFSET) /* FLEXPWM2 Fractional Value Register 5 */ -#define IMXRT_FLEXPWM2_SM1VAL5 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM1VAL5_OFFSET) /* FLEXPWM2 Value Register 5 */ -#define IMXRT_FLEXPWM2_SM1FRCTRL (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM1FRCTRL_OFFSET) /* FLEXPWM2 Fractional Control Register */ -#define IMXRT_FLEXPWM2_SM1OCTRL (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM1OCTRL_OFFSET) /* FLEXPWM2 Output Control Register */ -#define IMXRT_FLEXPWM2_SM1STS (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM1STS_OFFSET) /* FLEXPWM2 Status Register */ -#define IMXRT_FLEXPWM2_SM1INTEN (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM1INTEN_OFFSET) /* FLEXPWM2 Interrupt Enable Register */ -#define IMXRT_FLEXPWM2_SM1DMAEN (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM1DMAEN_OFFSET) /* FLEXPWM2 DMA Enable Register */ -#define IMXRT_FLEXPWM2_SM1TCTRL (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM1TCTRL_OFFSET) /* FLEXPWM2 Output Trigger Control Register */ -#define IMXRT_FLEXPWM2_SM1DISMAP0 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM1DISMAP0_OFFSET) /* FLEXPWM2 Fault Disable Mapping Register 0 */ -#define IMXRT_FLEXPWM2_SM1DISMAP1 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM1DISMAP1_OFFSET) /* FLEXPWM2 Fault Disable Mapping Register 1 */ -#define IMXRT_FLEXPWM2_SM1DTCNT0 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM1DTCNT0_OFFSET) /* FLEXPWM2 Deadtime Count Register 0 */ -#define IMXRT_FLEXPWM2_SM1DTCNT1 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM1DTCNT1_OFFSET) /* FLEXPWM2 Deadtime Count Register 1 */ -#define IMXRT_FLEXPWM2_SM1CAPTCTRLA (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM1CAPTCTRLA_OFFSET) /* FLEXPWM2 Capture Control A Register */ -#define IMXRT_FLEXPWM2_SM1CAPTCOMPA (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM1CAPTCOMPA_OFFSET) /* FLEXPWM2 Capture Compare A Register */ -#define IMXRT_FLEXPWM2_eFlexPWM (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_eFlexPWM_OFFSET) /* FLEXPWM2 apter 28 Enhanced Flex Pulse Width Modulator */ -#define IMXRT_FLEXPWM2_SM1CAPTCTRLB (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM1CAPTCTRLB_OFFSET) /* FLEXPWM2 Capture Control B Register */ -#define IMXRT_FLEXPWM2_SM1CAPTCOMPB (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM1CAPTCOMPB_OFFSET) /* FLEXPWM2 Capture Compare B Register */ -#define IMXRT_FLEXPWM2_SM1CAPTCTRLX (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM1CAPTCTRLX_OFFSET) /* FLEXPWM2 Capture Control X Register */ -#define IMXRT_FLEXPWM2_SM1CAPTCOMPX (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM1CAPTCOMPX_OFFSET) /* FLEXPWM2 Capture Compare X Register */ -#define IMXRT_FLEXPWM2_SM1CVAL0 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM1CVAL0_OFFSET) /* FLEXPWM2 Capture Value 0 Register */ -#define IMXRT_FLEXPWM2_SM1CVAL0CYC (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM1CVAL0CYC_OFFSET) /* FLEXPWM2 Capture Value 0 Cycle Register */ -#define IMXRT_FLEXPWM2_SM1CVAL1 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM1CVAL1_OFFSET) /* FLEXPWM2 Capture Value 1 Register */ -#define IMXRT_FLEXPWM2_SM1CVAL1CYC (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM1CVAL1CYC_OFFSET) /* FLEXPWM2 Capture Value 1 Cycle Register */ -#define IMXRT_FLEXPWM2_SM1CVAL2 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM1CVAL2_OFFSET) /* FLEXPWM2 Capture Value 2 Register */ -#define IMXRT_FLEXPWM2_SM1CVAL2CYC (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM1CVAL2CYC_OFFSET) /* FLEXPWM2 Capture Value 2 Cycle Register */ -#define IMXRT_FLEXPWM2_SM1CVAL3 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM1CVAL3_OFFSET) /* FLEXPWM2 Capture Value 3 Register */ -#define IMXRT_FLEXPWM2_SM1CVAL3CYC (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM1CVAL3CYC_OFFSET) /* FLEXPWM2 Capture Value 3 Cycle Register */ -#define IMXRT_FLEXPWM2_SM1CVAL4 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM1CVAL4_OFFSET) /* FLEXPWM2 Capture Value 4 Register */ -#define IMXRT_FLEXPWM2_SM1CVAL4CYC (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM1CVAL4CYC_OFFSET) /* FLEXPWM2 Capture Value 4 Cycle Register */ -#define IMXRT_FLEXPWM2_SM1CVAL5 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM1CVAL5_OFFSET) /* FLEXPWM2 Capture Value 5 Register */ -#define IMXRT_FLEXPWM2_SM1CVAL5CYC (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM1CVAL5CYC_OFFSET) /* FLEXPWM2 Capture Value 5 Cycle Register */ -#define IMXRT_FLEXPWM2_SM2CNT (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM2CNT_OFFSET) /* FLEXPWM2 Counter Register */ -#define IMXRT_FLEXPWM2_SM2INIT (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM2INIT_OFFSET) /* FLEXPWM2 Initial Count Register */ -#define IMXRT_FLEXPWM2_SM2CTRL2 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM2CTRL2_OFFSET) /* FLEXPWM2 Control 2 Register */ -#define IMXRT_FLEXPWM2_SM2CTRL (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM2CTRL_OFFSET) /* FLEXPWM2 Control Register */ -#define IMXRT_FLEXPWM2_SM2VAL0 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM2VAL0_OFFSET) /* FLEXPWM2 Value Register 0 */ -#define IMXRT_FLEXPWM2_SM2FRACVAL1 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM2FRACVAL1_OFFSET) /* FLEXPWM2 Fractional Value Register 1 */ -#define IMXRT_FLEXPWM2_SM2VAL1 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM2VAL1_OFFSET) /* FLEXPWM2 Value Register 1 */ -#define IMXRT_FLEXPWM2_SM2FRACVAL2 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM2FRACVAL2_OFFSET) /* FLEXPWM2 Fractional Value Register 2 */ -#define IMXRT_FLEXPWM2_SM2VAL2 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM2VAL2_OFFSET) /* FLEXPWM2 Value Register 2 */ -#define IMXRT_FLEXPWM2_SM2FRACVAL3 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM2FRACVAL3_OFFSET) /* FLEXPWM2 Fractional Value Register 3 */ -#define IMXRT_FLEXPWM2_SM2VAL3 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM2VAL3_OFFSET) /* FLEXPWM2 Value Register 3 */ -#define IMXRT_FLEXPWM2_SM2FRACVAL4 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM2FRACVAL4_OFFSET) /* FLEXPWM2 Fractional Value Register 4 */ -#define IMXRT_FLEXPWM2_SM2VAL4 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM2VAL4_OFFSET) /* FLEXPWM2 Value Register 4 */ -#define IMXRT_FLEXPWM2_SM2FRACVAL5 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM2FRACVAL5_OFFSET) /* FLEXPWM2 Fractional Value Register 5 */ -#define IMXRT_FLEXPWM2_SM2VAL5 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM2VAL5_OFFSET) /* FLEXPWM2 Value Register 5 */ -#define IMXRT_FLEXPWM2_SM2FRCTRL (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM2FRCTRL_OFFSET) /* FLEXPWM2 Fractional Control Register */ -#define IMXRT_FLEXPWM2_SM2OCTRL (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM2OCTRL_OFFSET) /* FLEXPWM2 Output Control Register */ -#define IMXRT_FLEXPWM2_SM2STS (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM2STS_OFFSET) /* FLEXPWM2 Status Register */ -#define IMXRT_FLEXPWM2_SM2INTEN (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM2INTEN_OFFSET) /* FLEXPWM2 Interrupt Enable Register */ -#define IMXRT_FLEXPWM2_SM2DMAEN (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM2DMAEN_OFFSET) /* FLEXPWM2 DMA Enable Register */ -#define IMXRT_FLEXPWM2_SM2TCTRL (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM2TCTRL_OFFSET) /* FLEXPWM2 Output Trigger Control Register */ -#define IMXRT_FLEXPWM2_SM2DISMAP0 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM2DISMAP0_OFFSET) /* FLEXPWM2 Fault Disable Mapping Register 0 */ -#define IMXRT_FLEXPWM2_SM2DISMAP1 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM2DISMAP1_OFFSET) /* FLEXPWM2 Fault Disable Mapping Register 1 */ -#define IMXRT_FLEXPWM2_SM2DTCNT0 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM2DTCNT0_OFFSET) /* FLEXPWM2 Deadtime Count Register 0 */ -#define IMXRT_FLEXPWM2_SM2DTCNT1 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM2DTCNT1_OFFSET) /* FLEXPWM2 Deadtime Count Register 1 */ -#define IMXRT_FLEXPWM2_SM2CAPTCTRLA (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM2CAPTCTRLA_OFFSET) /* FLEXPWM2 Capture Control A Register */ -#define IMXRT_FLEXPWM2_SM2CAPTCOMPA (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM2CAPTCOMPA_OFFSET) /* FLEXPWM2 Capture Compare A Register */ -#define IMXRT_FLEXPWM2_SM2CAPTCTRLB (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM2CAPTCTRLB_OFFSET) /* FLEXPWM2 Capture Control B Register */ -#define IMXRT_FLEXPWM2_SM2CAPTCOMPB (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM2CAPTCOMPB_OFFSET) /* FLEXPWM2 Capture Compare B Register */ -#define IMXRT_FLEXPWM2_SM2CAPTCTRLX (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM2CAPTCTRLX_OFFSET) /* FLEXPWM2 Capture Control X Register */ -#define IMXRT_FLEXPWM2_SM2CAPTCOMPX (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM2CAPTCOMPX_OFFSET) /* FLEXPWM2 Capture Compare X Register */ -#define IMXRT_FLEXPWM2_SM2CVAL0 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM2CVAL0_OFFSET) /* FLEXPWM2 Capture Value 0 Register */ -#define IMXRT_FLEXPWM2_SM2CVAL0CYC (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM2CVAL0CYC_OFFSET) /* FLEXPWM2 Capture Value 0 Cycle Register */ -#define IMXRT_FLEXPWM2_SM2CVAL1 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM2CVAL1_OFFSET) /* FLEXPWM2 Capture Value 1 Register */ -#define IMXRT_FLEXPWM2_SM2CVAL1CYC (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM2CVAL1CYC_OFFSET) /* FLEXPWM2 Capture Value 1 Cycle Register */ -#define IMXRT_FLEXPWM2_SM2CVAL2 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM2CVAL2_OFFSET) /* FLEXPWM2 Capture Value 2 Register */ -#define IMXRT_FLEXPWM2_SM2CVAL2CYC (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM2CVAL2CYC_OFFSET) /* FLEXPWM2 Capture Value 2 Cycle Register */ -#define IMXRT_FLEXPWM2_SM2CVAL3 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM2CVAL3_OFFSET) /* FLEXPWM2 Capture Value 3 Register */ -#define IMXRT_FLEXPWM2_SM2CVAL3CYC (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM2CVAL3CYC_OFFSET) /* FLEXPWM2 Capture Value 3 Cycle Register */ -#define IMXRT_FLEXPWM2_SM2CVAL4 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM2CVAL4_OFFSET) /* FLEXPWM2 Capture Value 4 Register */ -#define IMXRT_FLEXPWM2_SM2CVAL4CYC (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM2CVAL4CYC_OFFSET) /* FLEXPWM2 Capture Value 4 Cycle Register */ -#define IMXRT_FLEXPWM2_SM2CVAL5 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM2CVAL5_OFFSET) /* FLEXPWM2 Capture Value 5 Register */ -#define IMXRT_FLEXPWM2_SM2CVAL5CYC (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM2CVAL5CYC_OFFSET) /* FLEXPWM2 Capture Value 5 Cycle Register */ -#define IMXRT_FLEXPWM2_SM3CNT (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM3CNT_OFFSET) /* FLEXPWM2 Counter Register */ -#define IMXRT_FLEXPWM2_SM3INIT (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM3INIT_OFFSET) /* FLEXPWM2 Initial Count Register */ -#define IMXRT_FLEXPWM2_SM3CTRL2 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM3CTRL2_OFFSET) /* FLEXPWM2 Control 2 Register */ -#define IMXRT_FLEXPWM2_SM3CTRL (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM3CTRL_OFFSET) /* FLEXPWM2 Control Register */ -#define IMXRT_FLEXPWM2_SM3VAL0 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM3VAL0_OFFSET) /* FLEXPWM2 Value Register 0 */ -#define IMXRT_FLEXPWM2_SM3FRACVAL1 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM3FRACVAL1_OFFSET) /* FLEXPWM2 Fractional Value Register 1 */ -#define IMXRT_FLEXPWM2_SM3VAL1 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM3VAL1_OFFSET) /* FLEXPWM2 Value Register 1 */ -#define IMXRT_FLEXPWM2_SM3FRACVAL2 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM3FRACVAL2_OFFSET) /* FLEXPWM2 Fractional Value Register 2 */ -#define IMXRT_FLEXPWM2_SM3VAL2 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM3VAL2_OFFSET) /* FLEXPWM2 Value Register 2 */ -#define IMXRT_FLEXPWM2_SM3FRACVAL3 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM3FRACVAL3_OFFSET) /* FLEXPWM2 Fractional Value Register 3 */ -#define IMXRT_FLEXPWM2_SM3VAL3 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM3VAL3_OFFSET) /* FLEXPWM2 Value Register 3 */ -#define IMXRT_FLEXPWM2_SM3FRACVAL4 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM3FRACVAL4_OFFSET) /* FLEXPWM2 Fractional Value Register 4 */ -#define IMXRT_FLEXPWM2_SM3VAL4 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM3VAL4_OFFSET) /* FLEXPWM2 Value Register 4 */ -#define IMXRT_FLEXPWM2_SM3FRACVAL5 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM3FRACVAL5_OFFSET) /* FLEXPWM2 Fractional Value Register 5 */ -#define IMXRT_FLEXPWM2_SM3VAL5 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM3VAL5_OFFSET) /* FLEXPWM2 Value Register 5 */ -#define IMXRT_FLEXPWM2_SM3FRCTRL (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM3FRCTRL_OFFSET) /* FLEXPWM2 Fractional Control Register */ -#define IMXRT_FLEXPWM2_SM3OCTRL (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM3OCTRL_OFFSET) /* FLEXPWM2 Output Control Register */ -#define IMXRT_FLEXPWM2_SM3STS (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM3STS_OFFSET) /* FLEXPWM2 Status Register */ -#define IMXRT_FLEXPWM2_SM3INTEN (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM3INTEN_OFFSET) /* FLEXPWM2 Interrupt Enable Register */ -#define IMXRT_FLEXPWM2_SM3DMAEN (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM3DMAEN_OFFSET) /* FLEXPWM2 DMA Enable Register */ -#define IMXRT_FLEXPWM2_SM3TCTRL (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM3TCTRL_OFFSET) /* FLEXPWM2 Output Trigger Control Register */ -#define IMXRT_FLEXPWM2_SM3DISMAP0 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM3DISMAP0_OFFSET) /* FLEXPWM2 Fault Disable Mapping Register 0 */ -#define IMXRT_FLEXPWM2_SM3DISMAP1 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM3DISMAP1_OFFSET) /* FLEXPWM2 Fault Disable Mapping Register 1 */ -#define IMXRT_FLEXPWM2_SM3DTCNT0 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM3DTCNT0_OFFSET) /* FLEXPWM2 Deadtime Count Register 0 */ -#define IMXRT_FLEXPWM2_SM3DTCNT1 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM3DTCNT1_OFFSET) /* FLEXPWM2 Deadtime Count Register 1 */ -#define IMXRT_FLEXPWM2_SM3CAPTCTRLA (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM3CAPTCTRLA_OFFSET) /* FLEXPWM2 Capture Control A Register */ -#define IMXRT_FLEXPWM2_SM3CAPTCOMPA (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM3CAPTCOMPA_OFFSET) /* FLEXPWM2 Capture Compare A Register */ -#define IMXRT_FLEXPWM2_SM3CAPTCTRLB (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM3CAPTCTRLB_OFFSET) /* FLEXPWM2 Capture Control B Register */ -#define IMXRT_FLEXPWM2_SM3CAPTCOMPB (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM3CAPTCOMPB_OFFSET) /* FLEXPWM2 Capture Compare B Register */ -#define IMXRT_FLEXPWM2_SM3CAPTCTRLX (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM3CAPTCTRLX_OFFSET) /* FLEXPWM2 Capture Control X Register */ -#define IMXRT_FLEXPWM2_SM3CAPTCOMPX (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM3CAPTCOMPX_OFFSET) /* FLEXPWM2 Capture Compare X Register */ -#define IMXRT_FLEXPWM2_SM3CVAL0 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM3CVAL0_OFFSET) /* FLEXPWM2 Capture Value 0 Register */ -#define IMXRT_FLEXPWM2_SM3CVAL0CYC (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM3CVAL0CYC_OFFSET) /* FLEXPWM2 Capture Value 0 Cycle Register */ -#define IMXRT_FLEXPWM2_SM3CVAL1 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM3CVAL1_OFFSET) /* FLEXPWM2 Capture Value 1 Register */ -#define IMXRT_FLEXPWM2_SM3CVAL1CYC (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM3CVAL1CYC_OFFSET) /* FLEXPWM2 Capture Value 1 Cycle Register */ -#define IMXRT_FLEXPWM2_SM3CVAL2 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM3CVAL2_OFFSET) /* FLEXPWM2 Capture Value 2 Register */ -#define IMXRT_FLEXPWM2_SM3CVAL2CYC (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM3CVAL2CYC_OFFSET) /* FLEXPWM2 Capture Value 2 Cycle Register */ -#define IMXRT_FLEXPWM2_SM3CVAL3 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM3CVAL3_OFFSET) /* FLEXPWM2 Capture Value 3 Register */ -#define IMXRT_FLEXPWM2_SM3CVAL3CYC (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM3CVAL3CYC_OFFSET) /* FLEXPWM2 Capture Value 3 Cycle Register */ -#define IMXRT_FLEXPWM2_SM3CVAL4 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM3CVAL4_OFFSET) /* FLEXPWM2 Capture Value 4 Register */ -#define IMXRT_FLEXPWM2_SM3CVAL4CYC (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM3CVAL4CYC_OFFSET) /* FLEXPWM2 Capture Value 4 Cycle Register */ -#define IMXRT_FLEXPWM2_SM3CVAL5 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM3CVAL5_OFFSET) /* FLEXPWM2 Capture Value 5 Register */ -#define IMXRT_FLEXPWM2_SM3CVAL5CYC (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SM3CVAL5CYC_OFFSET) /* FLEXPWM2 Capture Value 5 Cycle Register */ -#define IMXRT_FLEXPWM2_OUTEN (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_OUTEN_OFFSET) /* FLEXPWM2 Output Enable Register */ -#define IMXRT_FLEXPWM2_MASK (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_MASK_OFFSET) /* FLEXPWM2 Mask Register */ -#define IMXRT_FLEXPWM2_SWCOUT (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_SWCOUT_OFFSET) /* FLEXPWM2 Software Controlled Output Register */ -#define IMXRT_FLEXPWM2_DTSRCSEL (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_DTSRCSEL_OFFSET) /* FLEXPWM2 PWM Source Select Register */ -#define IMXRT_FLEXPWM2_MCTRL (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_MCTRL_OFFSET) /* FLEXPWM2 Master Control Register */ -#define IMXRT_FLEXPWM2_MCTRL2 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_MCTRL2_OFFSET) /* FLEXPWM2 Master Control 2 Register */ -#define IMXRT_FLEXPWM2_FCTRL0 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_FCTRL0_OFFSET) /* FLEXPWM2 Fault Control Register */ -#define IMXRT_FLEXPWM2_FSTS0 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_FSTS0_OFFSET) /* FLEXPWM2 Fault Status Register */ -#define IMXRT_FLEXPWM2_FFILT0 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_FFILT0_OFFSET) /* FLEXPWM2 Fault Filter Register */ -#define IMXRT_FLEXPWM2_FTST0 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_FTST0_OFFSET) /* FLEXPWM2 Fault Test Register */ -#define IMXRT_FLEXPWM2_FCTRL20 (IMXRT_FLEXPWM2_BASE + IMXRT_FLEXPWM_FCTRL20_OFFSET) /* FLEXPWM2 Fault Control 2 Register */ - -/* FLEXPWM3 Register Addresses */ - -#define IMXRT_FLEXPWM3_SM0CNT (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM0CNT_OFFSET) /* FLEXPWM3 Counter Register */ -#define IMXRT_FLEXPWM3_SM0INIT (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM0INIT_OFFSET) /* FLEXPWM3 Initial Count Register */ -#define IMXRT_FLEXPWM3_SM0CTRL2 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM0CTRL2_OFFSET) /* FLEXPWM3 Control 2 Register */ -#define IMXRT_FLEXPWM3_SM0CTRL (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM0CTRL_OFFSET) /* FLEXPWM3 Control Register */ -#define IMXRT_FLEXPWM3_SM0VAL0 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM0VAL0_OFFSET) /* FLEXPWM3 Value Register 0 */ -#define IMXRT_FLEXPWM3_SM0FRACVAL1 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM0FRACVAL1_OFFSET) /* FLEXPWM3 Fractional Value Register 1 */ -#define IMXRT_FLEXPWM3_SM0VAL1 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM0VAL1_OFFSET) /* FLEXPWM3 Value Register 1 */ -#define IMXRT_FLEXPWM3_SM0FRACVAL2 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM0FRACVAL2_OFFSET) /* FLEXPWM3 Fractional Value Register 2 */ -#define IMXRT_FLEXPWM3_SM0VAL2 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM0VAL2_OFFSET) /* FLEXPWM3 Value Register 2 */ -#define IMXRT_FLEXPWM3_SM0FRACVAL3 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM0FRACVAL3_OFFSET) /* FLEXPWM3 Fractional Value Register 3 */ -#define IMXRT_FLEXPWM3_SM0VAL3 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM0VAL3_OFFSET) /* FLEXPWM3 Value Register 3 */ -#define IMXRT_FLEXPWM3_SM0FRACVAL4 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM0FRACVAL4_OFFSET) /* FLEXPWM3 Fractional Value Register 4 */ -#define IMXRT_FLEXPWM3_SM0VAL4 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM0VAL4_OFFSET) /* FLEXPWM3 Value Register 4 */ -#define IMXRT_FLEXPWM3_SM0FRACVAL5 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM0FRACVAL5_OFFSET) /* FLEXPWM3 Fractional Value Register 5 */ -#define IMXRT_FLEXPWM3_SM0VAL5 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM0VAL5_OFFSET) /* FLEXPWM3 Value Register 5 */ -#define IMXRT_FLEXPWM3_SM0FRCTRL (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM0FRCTRL_OFFSET) /* FLEXPWM3 Fractional Control Register */ -#define IMXRT_FLEXPWM3_SM0OCTRL (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM0OCTRL_OFFSET) /* FLEXPWM3 Output Control Register */ -#define IMXRT_FLEXPWM3_SM0STS (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM0STS_OFFSET) /* FLEXPWM3 Status Register */ -#define IMXRT_FLEXPWM3_SM0INTEN (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM0INTEN_OFFSET) /* FLEXPWM3 Interrupt Enable Register */ -#define IMXRT_FLEXPWM3_SM0DMAEN (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM0DMAEN_OFFSET) /* FLEXPWM3 DMA Enable Register */ -#define IMXRT_FLEXPWM3_SM0TCTRL (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM0TCTRL_OFFSET) /* FLEXPWM3 Output Trigger Control Register */ -#define IMXRT_FLEXPWM3_SM0DISMAP0 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM0DISMAP0_OFFSET) /* FLEXPWM3 Fault Disable Mapping Register 0 */ -#define IMXRT_FLEXPWM3_SM0DISMAP1 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM0DISMAP1_OFFSET) /* FLEXPWM3 Fault Disable Mapping Register 1 */ -#define IMXRT_FLEXPWM3_SM0DTCNT0 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM0DTCNT0_OFFSET) /* FLEXPWM3 Deadtime Count Register 0 */ -#define IMXRT_FLEXPWM3_SM0DTCNT1 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM0DTCNT1_OFFSET) /* FLEXPWM3 Deadtime Count Register 1 */ -#define IMXRT_FLEXPWM3_SM0CAPTCTRLA (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM0CAPTCTRLA_OFFSET) /* FLEXPWM3 Capture Control A Register */ -#define IMXRT_FLEXPWM3_SM0CAPTCOMPA (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM0CAPTCOMPA_OFFSET) /* FLEXPWM3 Capture Compare A Register */ -#define IMXRT_FLEXPWM3_SM0CAPTCTRLB (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM0CAPTCTRLB_OFFSET) /* FLEXPWM3 Capture Control B Register */ -#define IMXRT_FLEXPWM3_SM0CAPTCOMPB (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM0CAPTCOMPB_OFFSET) /* FLEXPWM3 Capture Compare B Register */ -#define IMXRT_FLEXPWM3_SM0CAPTCTRLX (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM0CAPTCTRLX_OFFSET) /* FLEXPWM3 Capture Control X Register */ -#define IMXRT_FLEXPWM3_SM0CAPTCOMPX (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM0CAPTCOMPX_OFFSET) /* FLEXPWM3 Capture Compare X Register */ -#define IMXRT_FLEXPWM3_SM0CVAL0 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM0CVAL0_OFFSET) /* FLEXPWM3 Capture Value 0 Register */ -#define IMXRT_FLEXPWM3_SM0CVAL0CYC (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM0CVAL0CYC_OFFSET) /* FLEXPWM3 Capture Value 0 Cycle Register */ -#define IMXRT_FLEXPWM3_SM0CVAL1 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM0CVAL1_OFFSET) /* FLEXPWM3 Capture Value 1 Register */ -#define IMXRT_FLEXPWM3_SM0CVAL1CYC (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM0CVAL1CYC_OFFSET) /* FLEXPWM3 Capture Value 1 Cycle Register */ -#define IMXRT_FLEXPWM3_SM0CVAL2 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM0CVAL2_OFFSET) /* FLEXPWM3 Capture Value 2 Register */ -#define IMXRT_FLEXPWM3_SM0CVAL2CYC (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM0CVAL2CYC_OFFSET) /* FLEXPWM3 Capture Value 2 Cycle Register */ -#define IMXRT_FLEXPWM3_SM0CVAL3 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM0CVAL3_OFFSET) /* FLEXPWM3 Capture Value 3 Register */ -#define IMXRT_FLEXPWM3_SM0CVAL3CYC (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM0CVAL3CYC_OFFSET) /* FLEXPWM3 Capture Value 3 Cycle Register */ -#define IMXRT_FLEXPWM3_SM0CVAL4 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM0CVAL4_OFFSET) /* FLEXPWM3 Capture Value 4 Register */ -#define IMXRT_FLEXPWM3_SM0CVAL4CYC (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM0CVAL4CYC_OFFSET) /* FLEXPWM3 Capture Value 4 Cycle Register */ -#define IMXRT_FLEXPWM3_SM0CVAL5 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM0CVAL5_OFFSET) /* FLEXPWM3 Capture Value 5 Register */ -#define IMXRT_FLEXPWM3_SM0CVAL5CYC (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM0CVAL5CYC_OFFSET) /* FLEXPWM3 Capture Value 5 Cycle Register */ -#define IMXRT_FLEXPWM3_SM1CNT (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM1CNT_OFFSET) /* FLEXPWM3 Counter Register */ -#define IMXRT_FLEXPWM3_SM1INIT (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM1INIT_OFFSET) /* FLEXPWM3 Initial Count Register */ -#define IMXRT_FLEXPWM3_SM1CTRL2 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM1CTRL2_OFFSET) /* FLEXPWM3 Control 2 Register */ -#define IMXRT_FLEXPWM3_SM1CTRL (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM1CTRL_OFFSET) /* FLEXPWM3 Control Register */ -#define IMXRT_FLEXPWM3_SM1VAL0 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM1VAL0_OFFSET) /* FLEXPWM3 Value Register 0 */ -#define IMXRT_FLEXPWM3_SM1FRACVAL1 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM1FRACVAL1_OFFSET) /* FLEXPWM3 Fractional Value Register 1 */ -#define IMXRT_FLEXPWM3_SM1VAL1 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM1VAL1_OFFSET) /* FLEXPWM3 Value Register 1 */ -#define IMXRT_FLEXPWM3_SM1FRACVAL2 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM1FRACVAL2_OFFSET) /* FLEXPWM3 Fractional Value Register 2 */ -#define IMXRT_FLEXPWM3_SM1VAL2 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM1VAL2_OFFSET) /* FLEXPWM3 Value Register 2 */ -#define IMXRT_FLEXPWM3_SM1FRACVAL3 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM1FRACVAL3_OFFSET) /* FLEXPWM3 Fractional Value Register 3 */ -#define IMXRT_FLEXPWM3_SM1VAL3 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM1VAL3_OFFSET) /* FLEXPWM3 Value Register 3 */ -#define IMXRT_FLEXPWM3_SM1FRACVAL4 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM1FRACVAL4_OFFSET) /* FLEXPWM3 Fractional Value Register 4 */ -#define IMXRT_FLEXPWM3_SM1VAL4 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM1VAL4_OFFSET) /* FLEXPWM3 Value Register 4 */ -#define IMXRT_FLEXPWM3_SM1FRACVAL5 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM1FRACVAL5_OFFSET) /* FLEXPWM3 Fractional Value Register 5 */ -#define IMXRT_FLEXPWM3_SM1VAL5 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM1VAL5_OFFSET) /* FLEXPWM3 Value Register 5 */ -#define IMXRT_FLEXPWM3_SM1FRCTRL (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM1FRCTRL_OFFSET) /* FLEXPWM3 Fractional Control Register */ -#define IMXRT_FLEXPWM3_SM1OCTRL (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM1OCTRL_OFFSET) /* FLEXPWM3 Output Control Register */ -#define IMXRT_FLEXPWM3_SM1STS (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM1STS_OFFSET) /* FLEXPWM3 Status Register */ -#define IMXRT_FLEXPWM3_SM1INTEN (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM1INTEN_OFFSET) /* FLEXPWM3 Interrupt Enable Register */ -#define IMXRT_FLEXPWM3_SM1DMAEN (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM1DMAEN_OFFSET) /* FLEXPWM3 DMA Enable Register */ -#define IMXRT_FLEXPWM3_SM1TCTRL (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM1TCTRL_OFFSET) /* FLEXPWM3 Output Trigger Control Register */ -#define IMXRT_FLEXPWM3_SM1DISMAP0 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM1DISMAP0_OFFSET) /* FLEXPWM3 Fault Disable Mapping Register 0 */ -#define IMXRT_FLEXPWM3_SM1DISMAP1 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM1DISMAP1_OFFSET) /* FLEXPWM3 Fault Disable Mapping Register 1 */ -#define IMXRT_FLEXPWM3_SM1DTCNT0 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM1DTCNT0_OFFSET) /* FLEXPWM3 Deadtime Count Register 0 */ -#define IMXRT_FLEXPWM3_SM1DTCNT1 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM1DTCNT1_OFFSET) /* FLEXPWM3 Deadtime Count Register 1 */ -#define IMXRT_FLEXPWM3_SM1CAPTCTRLA (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM1CAPTCTRLA_OFFSET) /* FLEXPWM3 Capture Control A Register */ -#define IMXRT_FLEXPWM3_SM1CAPTCOMPA (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM1CAPTCOMPA_OFFSET) /* FLEXPWM3 Capture Compare A Register */ -#define IMXRT_FLEXPWM3_eFlexPWM (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_eFlexPWM_OFFSET) /* FLEXPWM3 apter 28 Enhanced Flex Pulse Width Modulator */ -#define IMXRT_FLEXPWM3_SM1CAPTCTRLB (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM1CAPTCTRLB_OFFSET) /* FLEXPWM3 Capture Control B Register */ -#define IMXRT_FLEXPWM3_SM1CAPTCOMPB (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM1CAPTCOMPB_OFFSET) /* FLEXPWM3 Capture Compare B Register */ -#define IMXRT_FLEXPWM3_SM1CAPTCTRLX (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM1CAPTCTRLX_OFFSET) /* FLEXPWM3 Capture Control X Register */ -#define IMXRT_FLEXPWM3_SM1CAPTCOMPX (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM1CAPTCOMPX_OFFSET) /* FLEXPWM3 Capture Compare X Register */ -#define IMXRT_FLEXPWM3_SM1CVAL0 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM1CVAL0_OFFSET) /* FLEXPWM3 Capture Value 0 Register */ -#define IMXRT_FLEXPWM3_SM1CVAL0CYC (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM1CVAL0CYC_OFFSET) /* FLEXPWM3 Capture Value 0 Cycle Register */ -#define IMXRT_FLEXPWM3_SM1CVAL1 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM1CVAL1_OFFSET) /* FLEXPWM3 Capture Value 1 Register */ -#define IMXRT_FLEXPWM3_SM1CVAL1CYC (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM1CVAL1CYC_OFFSET) /* FLEXPWM3 Capture Value 1 Cycle Register */ -#define IMXRT_FLEXPWM3_SM1CVAL2 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM1CVAL2_OFFSET) /* FLEXPWM3 Capture Value 2 Register */ -#define IMXRT_FLEXPWM3_SM1CVAL2CYC (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM1CVAL2CYC_OFFSET) /* FLEXPWM3 Capture Value 2 Cycle Register */ -#define IMXRT_FLEXPWM3_SM1CVAL3 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM1CVAL3_OFFSET) /* FLEXPWM3 Capture Value 3 Register */ -#define IMXRT_FLEXPWM3_SM1CVAL3CYC (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM1CVAL3CYC_OFFSET) /* FLEXPWM3 Capture Value 3 Cycle Register */ -#define IMXRT_FLEXPWM3_SM1CVAL4 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM1CVAL4_OFFSET) /* FLEXPWM3 Capture Value 4 Register */ -#define IMXRT_FLEXPWM3_SM1CVAL4CYC (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM1CVAL4CYC_OFFSET) /* FLEXPWM3 Capture Value 4 Cycle Register */ -#define IMXRT_FLEXPWM3_SM1CVAL5 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM1CVAL5_OFFSET) /* FLEXPWM3 Capture Value 5 Register */ -#define IMXRT_FLEXPWM3_SM1CVAL5CYC (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM1CVAL5CYC_OFFSET) /* FLEXPWM3 Capture Value 5 Cycle Register */ -#define IMXRT_FLEXPWM3_SM2CNT (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM2CNT_OFFSET) /* FLEXPWM3 Counter Register */ -#define IMXRT_FLEXPWM3_SM2INIT (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM2INIT_OFFSET) /* FLEXPWM3 Initial Count Register */ -#define IMXRT_FLEXPWM3_SM2CTRL2 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM2CTRL2_OFFSET) /* FLEXPWM3 Control 2 Register */ -#define IMXRT_FLEXPWM3_SM2CTRL (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM2CTRL_OFFSET) /* FLEXPWM3 Control Register */ -#define IMXRT_FLEXPWM3_SM2VAL0 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM2VAL0_OFFSET) /* FLEXPWM3 Value Register 0 */ -#define IMXRT_FLEXPWM3_SM2FRACVAL1 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM2FRACVAL1_OFFSET) /* FLEXPWM3 Fractional Value Register 1 */ -#define IMXRT_FLEXPWM3_SM2VAL1 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM2VAL1_OFFSET) /* FLEXPWM3 Value Register 1 */ -#define IMXRT_FLEXPWM3_SM2FRACVAL2 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM2FRACVAL2_OFFSET) /* FLEXPWM3 Fractional Value Register 2 */ -#define IMXRT_FLEXPWM3_SM2VAL2 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM2VAL2_OFFSET) /* FLEXPWM3 Value Register 2 */ -#define IMXRT_FLEXPWM3_SM2FRACVAL3 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM2FRACVAL3_OFFSET) /* FLEXPWM3 Fractional Value Register 3 */ -#define IMXRT_FLEXPWM3_SM2VAL3 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM2VAL3_OFFSET) /* FLEXPWM3 Value Register 3 */ -#define IMXRT_FLEXPWM3_SM2FRACVAL4 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM2FRACVAL4_OFFSET) /* FLEXPWM3 Fractional Value Register 4 */ -#define IMXRT_FLEXPWM3_SM2VAL4 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM2VAL4_OFFSET) /* FLEXPWM3 Value Register 4 */ -#define IMXRT_FLEXPWM3_SM2FRACVAL5 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM2FRACVAL5_OFFSET) /* FLEXPWM3 Fractional Value Register 5 */ -#define IMXRT_FLEXPWM3_SM2VAL5 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM2VAL5_OFFSET) /* FLEXPWM3 Value Register 5 */ -#define IMXRT_FLEXPWM3_SM2FRCTRL (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM2FRCTRL_OFFSET) /* FLEXPWM3 Fractional Control Register */ -#define IMXRT_FLEXPWM3_SM2OCTRL (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM2OCTRL_OFFSET) /* FLEXPWM3 Output Control Register */ -#define IMXRT_FLEXPWM3_SM2STS (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM2STS_OFFSET) /* FLEXPWM3 Status Register */ -#define IMXRT_FLEXPWM3_SM2INTEN (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM2INTEN_OFFSET) /* FLEXPWM3 Interrupt Enable Register */ -#define IMXRT_FLEXPWM3_SM2DMAEN (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM2DMAEN_OFFSET) /* FLEXPWM3 DMA Enable Register */ -#define IMXRT_FLEXPWM3_SM2TCTRL (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM2TCTRL_OFFSET) /* FLEXPWM3 Output Trigger Control Register */ -#define IMXRT_FLEXPWM3_SM2DISMAP0 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM2DISMAP0_OFFSET) /* FLEXPWM3 Fault Disable Mapping Register 0 */ -#define IMXRT_FLEXPWM3_SM2DISMAP1 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM2DISMAP1_OFFSET) /* FLEXPWM3 Fault Disable Mapping Register 1 */ -#define IMXRT_FLEXPWM3_SM2DTCNT0 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM2DTCNT0_OFFSET) /* FLEXPWM3 Deadtime Count Register 0 */ -#define IMXRT_FLEXPWM3_SM2DTCNT1 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM2DTCNT1_OFFSET) /* FLEXPWM3 Deadtime Count Register 1 */ -#define IMXRT_FLEXPWM3_SM2CAPTCTRLA (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM2CAPTCTRLA_OFFSET) /* FLEXPWM3 Capture Control A Register */ -#define IMXRT_FLEXPWM3_SM2CAPTCOMPA (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM2CAPTCOMPA_OFFSET) /* FLEXPWM3 Capture Compare A Register */ -#define IMXRT_FLEXPWM3_SM2CAPTCTRLB (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM2CAPTCTRLB_OFFSET) /* FLEXPWM3 Capture Control B Register */ -#define IMXRT_FLEXPWM3_SM2CAPTCOMPB (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM2CAPTCOMPB_OFFSET) /* FLEXPWM3 Capture Compare B Register */ -#define IMXRT_FLEXPWM3_SM2CAPTCTRLX (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM2CAPTCTRLX_OFFSET) /* FLEXPWM3 Capture Control X Register */ -#define IMXRT_FLEXPWM3_SM2CAPTCOMPX (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM2CAPTCOMPX_OFFSET) /* FLEXPWM3 Capture Compare X Register */ -#define IMXRT_FLEXPWM3_SM2CVAL0 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM2CVAL0_OFFSET) /* FLEXPWM3 Capture Value 0 Register */ -#define IMXRT_FLEXPWM3_SM2CVAL0CYC (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM2CVAL0CYC_OFFSET) /* FLEXPWM3 Capture Value 0 Cycle Register */ -#define IMXRT_FLEXPWM3_SM2CVAL1 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM2CVAL1_OFFSET) /* FLEXPWM3 Capture Value 1 Register */ -#define IMXRT_FLEXPWM3_SM2CVAL1CYC (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM2CVAL1CYC_OFFSET) /* FLEXPWM3 Capture Value 1 Cycle Register */ -#define IMXRT_FLEXPWM3_SM2CVAL2 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM2CVAL2_OFFSET) /* FLEXPWM3 Capture Value 2 Register */ -#define IMXRT_FLEXPWM3_SM2CVAL2CYC (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM2CVAL2CYC_OFFSET) /* FLEXPWM3 Capture Value 2 Cycle Register */ -#define IMXRT_FLEXPWM3_SM2CVAL3 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM2CVAL3_OFFSET) /* FLEXPWM3 Capture Value 3 Register */ -#define IMXRT_FLEXPWM3_SM2CVAL3CYC (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM2CVAL3CYC_OFFSET) /* FLEXPWM3 Capture Value 3 Cycle Register */ -#define IMXRT_FLEXPWM3_SM2CVAL4 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM2CVAL4_OFFSET) /* FLEXPWM3 Capture Value 4 Register */ -#define IMXRT_FLEXPWM3_SM2CVAL4CYC (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM2CVAL4CYC_OFFSET) /* FLEXPWM3 Capture Value 4 Cycle Register */ -#define IMXRT_FLEXPWM3_SM2CVAL5 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM2CVAL5_OFFSET) /* FLEXPWM3 Capture Value 5 Register */ -#define IMXRT_FLEXPWM3_SM2CVAL5CYC (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM2CVAL5CYC_OFFSET) /* FLEXPWM3 Capture Value 5 Cycle Register */ -#define IMXRT_FLEXPWM3_SM3CNT (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM3CNT_OFFSET) /* FLEXPWM3 Counter Register */ -#define IMXRT_FLEXPWM3_SM3INIT (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM3INIT_OFFSET) /* FLEXPWM3 Initial Count Register */ -#define IMXRT_FLEXPWM3_SM3CTRL2 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM3CTRL2_OFFSET) /* FLEXPWM3 Control 2 Register */ -#define IMXRT_FLEXPWM3_SM3CTRL (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM3CTRL_OFFSET) /* FLEXPWM3 Control Register */ -#define IMXRT_FLEXPWM3_SM3VAL0 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM3VAL0_OFFSET) /* FLEXPWM3 Value Register 0 */ -#define IMXRT_FLEXPWM3_SM3FRACVAL1 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM3FRACVAL1_OFFSET) /* FLEXPWM3 Fractional Value Register 1 */ -#define IMXRT_FLEXPWM3_SM3VAL1 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM3VAL1_OFFSET) /* FLEXPWM3 Value Register 1 */ -#define IMXRT_FLEXPWM3_SM3FRACVAL2 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM3FRACVAL2_OFFSET) /* FLEXPWM3 Fractional Value Register 2 */ -#define IMXRT_FLEXPWM3_SM3VAL2 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM3VAL2_OFFSET) /* FLEXPWM3 Value Register 2 */ -#define IMXRT_FLEXPWM3_SM3FRACVAL3 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM3FRACVAL3_OFFSET) /* FLEXPWM3 Fractional Value Register 3 */ -#define IMXRT_FLEXPWM3_SM3VAL3 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM3VAL3_OFFSET) /* FLEXPWM3 Value Register 3 */ -#define IMXRT_FLEXPWM3_SM3FRACVAL4 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM3FRACVAL4_OFFSET) /* FLEXPWM3 Fractional Value Register 4 */ -#define IMXRT_FLEXPWM3_SM3VAL4 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM3VAL4_OFFSET) /* FLEXPWM3 Value Register 4 */ -#define IMXRT_FLEXPWM3_SM3FRACVAL5 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM3FRACVAL5_OFFSET) /* FLEXPWM3 Fractional Value Register 5 */ -#define IMXRT_FLEXPWM3_SM3VAL5 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM3VAL5_OFFSET) /* FLEXPWM3 Value Register 5 */ -#define IMXRT_FLEXPWM3_SM3FRCTRL (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM3FRCTRL_OFFSET) /* FLEXPWM3 Fractional Control Register */ -#define IMXRT_FLEXPWM3_SM3OCTRL (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM3OCTRL_OFFSET) /* FLEXPWM3 Output Control Register */ -#define IMXRT_FLEXPWM3_SM3STS (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM3STS_OFFSET) /* FLEXPWM3 Status Register */ -#define IMXRT_FLEXPWM3_SM3INTEN (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM3INTEN_OFFSET) /* FLEXPWM3 Interrupt Enable Register */ -#define IMXRT_FLEXPWM3_SM3DMAEN (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM3DMAEN_OFFSET) /* FLEXPWM3 DMA Enable Register */ -#define IMXRT_FLEXPWM3_SM3TCTRL (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM3TCTRL_OFFSET) /* FLEXPWM3 Output Trigger Control Register */ -#define IMXRT_FLEXPWM3_SM3DISMAP0 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM3DISMAP0_OFFSET) /* FLEXPWM3 Fault Disable Mapping Register 0 */ -#define IMXRT_FLEXPWM3_SM3DISMAP1 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM3DISMAP1_OFFSET) /* FLEXPWM3 Fault Disable Mapping Register 1 */ -#define IMXRT_FLEXPWM3_SM3DTCNT0 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM3DTCNT0_OFFSET) /* FLEXPWM3 Deadtime Count Register 0 */ -#define IMXRT_FLEXPWM3_SM3DTCNT1 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM3DTCNT1_OFFSET) /* FLEXPWM3 Deadtime Count Register 1 */ -#define IMXRT_FLEXPWM3_SM3CAPTCTRLA (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM3CAPTCTRLA_OFFSET) /* FLEXPWM3 Capture Control A Register */ -#define IMXRT_FLEXPWM3_SM3CAPTCOMPA (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM3CAPTCOMPA_OFFSET) /* FLEXPWM3 Capture Compare A Register */ -#define IMXRT_FLEXPWM3_SM3CAPTCTRLB (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM3CAPTCTRLB_OFFSET) /* FLEXPWM3 Capture Control B Register */ -#define IMXRT_FLEXPWM3_SM3CAPTCOMPB (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM3CAPTCOMPB_OFFSET) /* FLEXPWM3 Capture Compare B Register */ -#define IMXRT_FLEXPWM3_SM3CAPTCTRLX (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM3CAPTCTRLX_OFFSET) /* FLEXPWM3 Capture Control X Register */ -#define IMXRT_FLEXPWM3_SM3CAPTCOMPX (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM3CAPTCOMPX_OFFSET) /* FLEXPWM3 Capture Compare X Register */ -#define IMXRT_FLEXPWM3_SM3CVAL0 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM3CVAL0_OFFSET) /* FLEXPWM3 Capture Value 0 Register */ -#define IMXRT_FLEXPWM3_SM3CVAL0CYC (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM3CVAL0CYC_OFFSET) /* FLEXPWM3 Capture Value 0 Cycle Register */ -#define IMXRT_FLEXPWM3_SM3CVAL1 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM3CVAL1_OFFSET) /* FLEXPWM3 Capture Value 1 Register */ -#define IMXRT_FLEXPWM3_SM3CVAL1CYC (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM3CVAL1CYC_OFFSET) /* FLEXPWM3 Capture Value 1 Cycle Register */ -#define IMXRT_FLEXPWM3_SM3CVAL2 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM3CVAL2_OFFSET) /* FLEXPWM3 Capture Value 2 Register */ -#define IMXRT_FLEXPWM3_SM3CVAL2CYC (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM3CVAL2CYC_OFFSET) /* FLEXPWM3 Capture Value 2 Cycle Register */ -#define IMXRT_FLEXPWM3_SM3CVAL3 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM3CVAL3_OFFSET) /* FLEXPWM3 Capture Value 3 Register */ -#define IMXRT_FLEXPWM3_SM3CVAL3CYC (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM3CVAL3CYC_OFFSET) /* FLEXPWM3 Capture Value 3 Cycle Register */ -#define IMXRT_FLEXPWM3_SM3CVAL4 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM3CVAL4_OFFSET) /* FLEXPWM3 Capture Value 4 Register */ -#define IMXRT_FLEXPWM3_SM3CVAL4CYC (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM3CVAL4CYC_OFFSET) /* FLEXPWM3 Capture Value 4 Cycle Register */ -#define IMXRT_FLEXPWM3_SM3CVAL5 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM3CVAL5_OFFSET) /* FLEXPWM3 Capture Value 5 Register */ -#define IMXRT_FLEXPWM3_SM3CVAL5CYC (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SM3CVAL5CYC_OFFSET) /* FLEXPWM3 Capture Value 5 Cycle Register */ -#define IMXRT_FLEXPWM3_OUTEN (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_OUTEN_OFFSET) /* FLEXPWM3 Output Enable Register */ -#define IMXRT_FLEXPWM3_MASK (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_MASK_OFFSET) /* FLEXPWM3 Mask Register */ -#define IMXRT_FLEXPWM3_SWCOUT (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_SWCOUT_OFFSET) /* FLEXPWM3 Software Controlled Output Register */ -#define IMXRT_FLEXPWM3_DTSRCSEL (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_DTSRCSEL_OFFSET) /* FLEXPWM3 PWM Source Select Register */ -#define IMXRT_FLEXPWM3_MCTRL (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_MCTRL_OFFSET) /* FLEXPWM3 Master Control Register */ -#define IMXRT_FLEXPWM3_MCTRL2 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_MCTRL2_OFFSET) /* FLEXPWM3 Master Control 2 Register */ -#define IMXRT_FLEXPWM3_FCTRL0 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_FCTRL0_OFFSET) /* FLEXPWM3 Fault Control Register */ -#define IMXRT_FLEXPWM3_FSTS0 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_FSTS0_OFFSET) /* FLEXPWM3 Fault Status Register */ -#define IMXRT_FLEXPWM3_FFILT0 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_FFILT0_OFFSET) /* FLEXPWM3 Fault Filter Register */ -#define IMXRT_FLEXPWM3_FTST0 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_FTST0_OFFSET) /* FLEXPWM3 Fault Test Register */ -#define IMXRT_FLEXPWM3_FCTRL20 (IMXRT_FLEXPWM3_BASE + IMXRT_FLEXPWM_FCTRL20_OFFSET) /* FLEXPWM3 Fault Control 2 Register */ - -/* FLEXPWM4 Register Addresses */ - -#define IMXRT_FLEXPWM4_SM0CNT (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM0CNT_OFFSET) /* FLEXPWM4 Counter Register */ -#define IMXRT_FLEXPWM4_SM0INIT (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM0INIT_OFFSET) /* FLEXPWM4 Initial Count Register */ -#define IMXRT_FLEXPWM4_SM0CTRL2 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM0CTRL2_OFFSET) /* FLEXPWM4 Control 2 Register */ -#define IMXRT_FLEXPWM4_SM0CTRL (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM0CTRL_OFFSET) /* FLEXPWM4 Control Register */ -#define IMXRT_FLEXPWM4_SM0VAL0 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM0VAL0_OFFSET) /* FLEXPWM4 Value Register 0 */ -#define IMXRT_FLEXPWM4_SM0FRACVAL1 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM0FRACVAL1_OFFSET) /* FLEXPWM4 Fractional Value Register 1 */ -#define IMXRT_FLEXPWM4_SM0VAL1 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM0VAL1_OFFSET) /* FLEXPWM4 Value Register 1 */ -#define IMXRT_FLEXPWM4_SM0FRACVAL2 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM0FRACVAL2_OFFSET) /* FLEXPWM4 Fractional Value Register 2 */ -#define IMXRT_FLEXPWM4_SM0VAL2 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM0VAL2_OFFSET) /* FLEXPWM4 Value Register 2 */ -#define IMXRT_FLEXPWM4_SM0FRACVAL3 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM0FRACVAL3_OFFSET) /* FLEXPWM4 Fractional Value Register 3 */ -#define IMXRT_FLEXPWM4_SM0VAL3 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM0VAL3_OFFSET) /* FLEXPWM4 Value Register 3 */ -#define IMXRT_FLEXPWM4_SM0FRACVAL4 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM0FRACVAL4_OFFSET) /* FLEXPWM4 Fractional Value Register 4 */ -#define IMXRT_FLEXPWM4_SM0VAL4 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM0VAL4_OFFSET) /* FLEXPWM4 Value Register 4 */ -#define IMXRT_FLEXPWM4_SM0FRACVAL5 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM0FRACVAL5_OFFSET) /* FLEXPWM4 Fractional Value Register 5 */ -#define IMXRT_FLEXPWM4_SM0VAL5 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM0VAL5_OFFSET) /* FLEXPWM4 Value Register 5 */ -#define IMXRT_FLEXPWM4_SM0FRCTRL (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM0FRCTRL_OFFSET) /* FLEXPWM4 Fractional Control Register */ -#define IMXRT_FLEXPWM4_SM0OCTRL (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM0OCTRL_OFFSET) /* FLEXPWM4 Output Control Register */ -#define IMXRT_FLEXPWM4_SM0STS (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM0STS_OFFSET) /* FLEXPWM4 Status Register */ -#define IMXRT_FLEXPWM4_SM0INTEN (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM0INTEN_OFFSET) /* FLEXPWM4 Interrupt Enable Register */ -#define IMXRT_FLEXPWM4_SM0DMAEN (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM0DMAEN_OFFSET) /* FLEXPWM4 DMA Enable Register */ -#define IMXRT_FLEXPWM4_SM0TCTRL (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM0TCTRL_OFFSET) /* FLEXPWM4 Output Trigger Control Register */ -#define IMXRT_FLEXPWM4_SM0DISMAP0 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM0DISMAP0_OFFSET) /* FLEXPWM4 Fault Disable Mapping Register 0 */ -#define IMXRT_FLEXPWM4_SM0DISMAP1 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM0DISMAP1_OFFSET) /* FLEXPWM4 Fault Disable Mapping Register 1 */ -#define IMXRT_FLEXPWM4_SM0DTCNT0 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM0DTCNT0_OFFSET) /* FLEXPWM4 Deadtime Count Register 0 */ -#define IMXRT_FLEXPWM4_SM0DTCNT1 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM0DTCNT1_OFFSET) /* FLEXPWM4 Deadtime Count Register 1 */ -#define IMXRT_FLEXPWM4_SM0CAPTCTRLA (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM0CAPTCTRLA_OFFSET) /* FLEXPWM4 Capture Control A Register */ -#define IMXRT_FLEXPWM4_SM0CAPTCOMPA (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM0CAPTCOMPA_OFFSET) /* FLEXPWM4 Capture Compare A Register */ -#define IMXRT_FLEXPWM4_SM0CAPTCTRLB (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM0CAPTCTRLB_OFFSET) /* FLEXPWM4 Capture Control B Register */ -#define IMXRT_FLEXPWM4_SM0CAPTCOMPB (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM0CAPTCOMPB_OFFSET) /* FLEXPWM4 Capture Compare B Register */ -#define IMXRT_FLEXPWM4_SM0CAPTCTRLX (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM0CAPTCTRLX_OFFSET) /* FLEXPWM4 Capture Control X Register */ -#define IMXRT_FLEXPWM4_SM0CAPTCOMPX (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM0CAPTCOMPX_OFFSET) /* FLEXPWM4 Capture Compare X Register */ -#define IMXRT_FLEXPWM4_SM0CVAL0 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM0CVAL0_OFFSET) /* FLEXPWM4 Capture Value 0 Register */ -#define IMXRT_FLEXPWM4_SM0CVAL0CYC (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM0CVAL0CYC_OFFSET) /* FLEXPWM4 Capture Value 0 Cycle Register */ -#define IMXRT_FLEXPWM4_SM0CVAL1 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM0CVAL1_OFFSET) /* FLEXPWM4 Capture Value 1 Register */ -#define IMXRT_FLEXPWM4_SM0CVAL1CYC (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM0CVAL1CYC_OFFSET) /* FLEXPWM4 Capture Value 1 Cycle Register */ -#define IMXRT_FLEXPWM4_SM0CVAL2 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM0CVAL2_OFFSET) /* FLEXPWM4 Capture Value 2 Register */ -#define IMXRT_FLEXPWM4_SM0CVAL2CYC (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM0CVAL2CYC_OFFSET) /* FLEXPWM4 Capture Value 2 Cycle Register */ -#define IMXRT_FLEXPWM4_SM0CVAL3 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM0CVAL3_OFFSET) /* FLEXPWM4 Capture Value 3 Register */ -#define IMXRT_FLEXPWM4_SM0CVAL3CYC (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM0CVAL3CYC_OFFSET) /* FLEXPWM4 Capture Value 3 Cycle Register */ -#define IMXRT_FLEXPWM4_SM0CVAL4 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM0CVAL4_OFFSET) /* FLEXPWM4 Capture Value 4 Register */ -#define IMXRT_FLEXPWM4_SM0CVAL4CYC (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM0CVAL4CYC_OFFSET) /* FLEXPWM4 Capture Value 4 Cycle Register */ -#define IMXRT_FLEXPWM4_SM0CVAL5 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM0CVAL5_OFFSET) /* FLEXPWM4 Capture Value 5 Register */ -#define IMXRT_FLEXPWM4_SM0CVAL5CYC (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM0CVAL5CYC_OFFSET) /* FLEXPWM4 Capture Value 5 Cycle Register */ -#define IMXRT_FLEXPWM4_SM1CNT (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM1CNT_OFFSET) /* FLEXPWM4 Counter Register */ -#define IMXRT_FLEXPWM4_SM1INIT (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM1INIT_OFFSET) /* FLEXPWM4 Initial Count Register */ -#define IMXRT_FLEXPWM4_SM1CTRL2 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM1CTRL2_OFFSET) /* FLEXPWM4 Control 2 Register */ -#define IMXRT_FLEXPWM4_SM1CTRL (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM1CTRL_OFFSET) /* FLEXPWM4 Control Register */ -#define IMXRT_FLEXPWM4_SM1VAL0 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM1VAL0_OFFSET) /* FLEXPWM4 Value Register 0 */ -#define IMXRT_FLEXPWM4_SM1FRACVAL1 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM1FRACVAL1_OFFSET) /* FLEXPWM4 Fractional Value Register 1 */ -#define IMXRT_FLEXPWM4_SM1VAL1 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM1VAL1_OFFSET) /* FLEXPWM4 Value Register 1 */ -#define IMXRT_FLEXPWM4_SM1FRACVAL2 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM1FRACVAL2_OFFSET) /* FLEXPWM4 Fractional Value Register 2 */ -#define IMXRT_FLEXPWM4_SM1VAL2 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM1VAL2_OFFSET) /* FLEXPWM4 Value Register 2 */ -#define IMXRT_FLEXPWM4_SM1FRACVAL3 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM1FRACVAL3_OFFSET) /* FLEXPWM4 Fractional Value Register 3 */ -#define IMXRT_FLEXPWM4_SM1VAL3 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM1VAL3_OFFSET) /* FLEXPWM4 Value Register 3 */ -#define IMXRT_FLEXPWM4_SM1FRACVAL4 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM1FRACVAL4_OFFSET) /* FLEXPWM4 Fractional Value Register 4 */ -#define IMXRT_FLEXPWM4_SM1VAL4 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM1VAL4_OFFSET) /* FLEXPWM4 Value Register 4 */ -#define IMXRT_FLEXPWM4_SM1FRACVAL5 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM1FRACVAL5_OFFSET) /* FLEXPWM4 Fractional Value Register 5 */ -#define IMXRT_FLEXPWM4_SM1VAL5 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM1VAL5_OFFSET) /* FLEXPWM4 Value Register 5 */ -#define IMXRT_FLEXPWM4_SM1FRCTRL (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM1FRCTRL_OFFSET) /* FLEXPWM4 Fractional Control Register */ -#define IMXRT_FLEXPWM4_SM1OCTRL (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM1OCTRL_OFFSET) /* FLEXPWM4 Output Control Register */ -#define IMXRT_FLEXPWM4_SM1STS (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM1STS_OFFSET) /* FLEXPWM4 Status Register */ -#define IMXRT_FLEXPWM4_SM1INTEN (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM1INTEN_OFFSET) /* FLEXPWM4 Interrupt Enable Register */ -#define IMXRT_FLEXPWM4_SM1DMAEN (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM1DMAEN_OFFSET) /* FLEXPWM4 DMA Enable Register */ -#define IMXRT_FLEXPWM4_SM1TCTRL (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM1TCTRL_OFFSET) /* FLEXPWM4 Output Trigger Control Register */ -#define IMXRT_FLEXPWM4_SM1DISMAP0 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM1DISMAP0_OFFSET) /* FLEXPWM4 Fault Disable Mapping Register 0 */ -#define IMXRT_FLEXPWM4_SM1DISMAP1 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM1DISMAP1_OFFSET) /* FLEXPWM4 Fault Disable Mapping Register 1 */ -#define IMXRT_FLEXPWM4_SM1DTCNT0 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM1DTCNT0_OFFSET) /* FLEXPWM4 Deadtime Count Register 0 */ -#define IMXRT_FLEXPWM4_SM1DTCNT1 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM1DTCNT1_OFFSET) /* FLEXPWM4 Deadtime Count Register 1 */ -#define IMXRT_FLEXPWM4_SM1CAPTCTRLA (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM1CAPTCTRLA_OFFSET) /* FLEXPWM4 Capture Control A Register */ -#define IMXRT_FLEXPWM4_SM1CAPTCOMPA (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM1CAPTCOMPA_OFFSET) /* FLEXPWM4 Capture Compare A Register */ -#define IMXRT_FLEXPWM4_eFlexPWM (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_eFlexPWM_OFFSET) /* FLEXPWM4 apter 28 Enhanced Flex Pulse Width Modulator */ -#define IMXRT_FLEXPWM4_SM1CAPTCTRLB (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM1CAPTCTRLB_OFFSET) /* FLEXPWM4 Capture Control B Register */ -#define IMXRT_FLEXPWM4_SM1CAPTCOMPB (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM1CAPTCOMPB_OFFSET) /* FLEXPWM4 Capture Compare B Register */ -#define IMXRT_FLEXPWM4_SM1CAPTCTRLX (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM1CAPTCTRLX_OFFSET) /* FLEXPWM4 Capture Control X Register */ -#define IMXRT_FLEXPWM4_SM1CAPTCOMPX (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM1CAPTCOMPX_OFFSET) /* FLEXPWM4 Capture Compare X Register */ -#define IMXRT_FLEXPWM4_SM1CVAL0 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM1CVAL0_OFFSET) /* FLEXPWM4 Capture Value 0 Register */ -#define IMXRT_FLEXPWM4_SM1CVAL0CYC (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM1CVAL0CYC_OFFSET) /* FLEXPWM4 Capture Value 0 Cycle Register */ -#define IMXRT_FLEXPWM4_SM1CVAL1 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM1CVAL1_OFFSET) /* FLEXPWM4 Capture Value 1 Register */ -#define IMXRT_FLEXPWM4_SM1CVAL1CYC (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM1CVAL1CYC_OFFSET) /* FLEXPWM4 Capture Value 1 Cycle Register */ -#define IMXRT_FLEXPWM4_SM1CVAL2 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM1CVAL2_OFFSET) /* FLEXPWM4 Capture Value 2 Register */ -#define IMXRT_FLEXPWM4_SM1CVAL2CYC (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM1CVAL2CYC_OFFSET) /* FLEXPWM4 Capture Value 2 Cycle Register */ -#define IMXRT_FLEXPWM4_SM1CVAL3 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM1CVAL3_OFFSET) /* FLEXPWM4 Capture Value 3 Register */ -#define IMXRT_FLEXPWM4_SM1CVAL3CYC (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM1CVAL3CYC_OFFSET) /* FLEXPWM4 Capture Value 3 Cycle Register */ -#define IMXRT_FLEXPWM4_SM1CVAL4 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM1CVAL4_OFFSET) /* FLEXPWM4 Capture Value 4 Register */ -#define IMXRT_FLEXPWM4_SM1CVAL4CYC (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM1CVAL4CYC_OFFSET) /* FLEXPWM4 Capture Value 4 Cycle Register */ -#define IMXRT_FLEXPWM4_SM1CVAL5 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM1CVAL5_OFFSET) /* FLEXPWM4 Capture Value 5 Register */ -#define IMXRT_FLEXPWM4_SM1CVAL5CYC (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM1CVAL5CYC_OFFSET) /* FLEXPWM4 Capture Value 5 Cycle Register */ -#define IMXRT_FLEXPWM4_SM2CNT (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM2CNT_OFFSET) /* FLEXPWM4 Counter Register */ -#define IMXRT_FLEXPWM4_SM2INIT (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM2INIT_OFFSET) /* FLEXPWM4 Initial Count Register */ -#define IMXRT_FLEXPWM4_SM2CTRL2 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM2CTRL2_OFFSET) /* FLEXPWM4 Control 2 Register */ -#define IMXRT_FLEXPWM4_SM2CTRL (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM2CTRL_OFFSET) /* FLEXPWM4 Control Register */ -#define IMXRT_FLEXPWM4_SM2VAL0 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM2VAL0_OFFSET) /* FLEXPWM4 Value Register 0 */ -#define IMXRT_FLEXPWM4_SM2FRACVAL1 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM2FRACVAL1_OFFSET) /* FLEXPWM4 Fractional Value Register 1 */ -#define IMXRT_FLEXPWM4_SM2VAL1 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM2VAL1_OFFSET) /* FLEXPWM4 Value Register 1 */ -#define IMXRT_FLEXPWM4_SM2FRACVAL2 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM2FRACVAL2_OFFSET) /* FLEXPWM4 Fractional Value Register 2 */ -#define IMXRT_FLEXPWM4_SM2VAL2 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM2VAL2_OFFSET) /* FLEXPWM4 Value Register 2 */ -#define IMXRT_FLEXPWM4_SM2FRACVAL3 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM2FRACVAL3_OFFSET) /* FLEXPWM4 Fractional Value Register 3 */ -#define IMXRT_FLEXPWM4_SM2VAL3 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM2VAL3_OFFSET) /* FLEXPWM4 Value Register 3 */ -#define IMXRT_FLEXPWM4_SM2FRACVAL4 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM2FRACVAL4_OFFSET) /* FLEXPWM4 Fractional Value Register 4 */ -#define IMXRT_FLEXPWM4_SM2VAL4 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM2VAL4_OFFSET) /* FLEXPWM4 Value Register 4 */ -#define IMXRT_FLEXPWM4_SM2FRACVAL5 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM2FRACVAL5_OFFSET) /* FLEXPWM4 Fractional Value Register 5 */ -#define IMXRT_FLEXPWM4_SM2VAL5 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM2VAL5_OFFSET) /* FLEXPWM4 Value Register 5 */ -#define IMXRT_FLEXPWM4_SM2FRCTRL (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM2FRCTRL_OFFSET) /* FLEXPWM4 Fractional Control Register */ -#define IMXRT_FLEXPWM4_SM2OCTRL (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM2OCTRL_OFFSET) /* FLEXPWM4 Output Control Register */ -#define IMXRT_FLEXPWM4_SM2STS (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM2STS_OFFSET) /* FLEXPWM4 Status Register */ -#define IMXRT_FLEXPWM4_SM2INTEN (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM2INTEN_OFFSET) /* FLEXPWM4 Interrupt Enable Register */ -#define IMXRT_FLEXPWM4_SM2DMAEN (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM2DMAEN_OFFSET) /* FLEXPWM4 DMA Enable Register */ -#define IMXRT_FLEXPWM4_SM2TCTRL (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM2TCTRL_OFFSET) /* FLEXPWM4 Output Trigger Control Register */ -#define IMXRT_FLEXPWM4_SM2DISMAP0 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM2DISMAP0_OFFSET) /* FLEXPWM4 Fault Disable Mapping Register 0 */ -#define IMXRT_FLEXPWM4_SM2DISMAP1 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM2DISMAP1_OFFSET) /* FLEXPWM4 Fault Disable Mapping Register 1 */ -#define IMXRT_FLEXPWM4_SM2DTCNT0 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM2DTCNT0_OFFSET) /* FLEXPWM4 Deadtime Count Register 0 */ -#define IMXRT_FLEXPWM4_SM2DTCNT1 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM2DTCNT1_OFFSET) /* FLEXPWM4 Deadtime Count Register 1 */ -#define IMXRT_FLEXPWM4_SM2CAPTCTRLA (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM2CAPTCTRLA_OFFSET) /* FLEXPWM4 Capture Control A Register */ -#define IMXRT_FLEXPWM4_SM2CAPTCOMPA (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM2CAPTCOMPA_OFFSET) /* FLEXPWM4 Capture Compare A Register */ -#define IMXRT_FLEXPWM4_SM2CAPTCTRLB (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM2CAPTCTRLB_OFFSET) /* FLEXPWM4 Capture Control B Register */ -#define IMXRT_FLEXPWM4_SM2CAPTCOMPB (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM2CAPTCOMPB_OFFSET) /* FLEXPWM4 Capture Compare B Register */ -#define IMXRT_FLEXPWM4_SM2CAPTCTRLX (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM2CAPTCTRLX_OFFSET) /* FLEXPWM4 Capture Control X Register */ -#define IMXRT_FLEXPWM4_SM2CAPTCOMPX (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM2CAPTCOMPX_OFFSET) /* FLEXPWM4 Capture Compare X Register */ -#define IMXRT_FLEXPWM4_SM2CVAL0 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM2CVAL0_OFFSET) /* FLEXPWM4 Capture Value 0 Register */ -#define IMXRT_FLEXPWM4_SM2CVAL0CYC (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM2CVAL0CYC_OFFSET) /* FLEXPWM4 Capture Value 0 Cycle Register */ -#define IMXRT_FLEXPWM4_SM2CVAL1 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM2CVAL1_OFFSET) /* FLEXPWM4 Capture Value 1 Register */ -#define IMXRT_FLEXPWM4_SM2CVAL1CYC (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM2CVAL1CYC_OFFSET) /* FLEXPWM4 Capture Value 1 Cycle Register */ -#define IMXRT_FLEXPWM4_SM2CVAL2 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM2CVAL2_OFFSET) /* FLEXPWM4 Capture Value 2 Register */ -#define IMXRT_FLEXPWM4_SM2CVAL2CYC (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM2CVAL2CYC_OFFSET) /* FLEXPWM4 Capture Value 2 Cycle Register */ -#define IMXRT_FLEXPWM4_SM2CVAL3 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM2CVAL3_OFFSET) /* FLEXPWM4 Capture Value 3 Register */ -#define IMXRT_FLEXPWM4_SM2CVAL3CYC (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM2CVAL3CYC_OFFSET) /* FLEXPWM4 Capture Value 3 Cycle Register */ -#define IMXRT_FLEXPWM4_SM2CVAL4 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM2CVAL4_OFFSET) /* FLEXPWM4 Capture Value 4 Register */ -#define IMXRT_FLEXPWM4_SM2CVAL4CYC (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM2CVAL4CYC_OFFSET) /* FLEXPWM4 Capture Value 4 Cycle Register */ -#define IMXRT_FLEXPWM4_SM2CVAL5 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM2CVAL5_OFFSET) /* FLEXPWM4 Capture Value 5 Register */ -#define IMXRT_FLEXPWM4_SM2CVAL5CYC (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM2CVAL5CYC_OFFSET) /* FLEXPWM4 Capture Value 5 Cycle Register */ -#define IMXRT_FLEXPWM4_SM3CNT (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM3CNT_OFFSET) /* FLEXPWM4 Counter Register */ -#define IMXRT_FLEXPWM4_SM3INIT (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM3INIT_OFFSET) /* FLEXPWM4 Initial Count Register */ -#define IMXRT_FLEXPWM4_SM3CTRL2 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM3CTRL2_OFFSET) /* FLEXPWM4 Control 2 Register */ -#define IMXRT_FLEXPWM4_SM3CTRL (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM3CTRL_OFFSET) /* FLEXPWM4 Control Register */ -#define IMXRT_FLEXPWM4_SM3VAL0 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM3VAL0_OFFSET) /* FLEXPWM4 Value Register 0 */ -#define IMXRT_FLEXPWM4_SM3FRACVAL1 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM3FRACVAL1_OFFSET) /* FLEXPWM4 Fractional Value Register 1 */ -#define IMXRT_FLEXPWM4_SM3VAL1 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM3VAL1_OFFSET) /* FLEXPWM4 Value Register 1 */ -#define IMXRT_FLEXPWM4_SM3FRACVAL2 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM3FRACVAL2_OFFSET) /* FLEXPWM4 Fractional Value Register 2 */ -#define IMXRT_FLEXPWM4_SM3VAL2 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM3VAL2_OFFSET) /* FLEXPWM4 Value Register 2 */ -#define IMXRT_FLEXPWM4_SM3FRACVAL3 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM3FRACVAL3_OFFSET) /* FLEXPWM4 Fractional Value Register 3 */ -#define IMXRT_FLEXPWM4_SM3VAL3 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM3VAL3_OFFSET) /* FLEXPWM4 Value Register 3 */ -#define IMXRT_FLEXPWM4_SM3FRACVAL4 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM3FRACVAL4_OFFSET) /* FLEXPWM4 Fractional Value Register 4 */ -#define IMXRT_FLEXPWM4_SM3VAL4 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM3VAL4_OFFSET) /* FLEXPWM4 Value Register 4 */ -#define IMXRT_FLEXPWM4_SM3FRACVAL5 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM3FRACVAL5_OFFSET) /* FLEXPWM4 Fractional Value Register 5 */ -#define IMXRT_FLEXPWM4_SM3VAL5 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM3VAL5_OFFSET) /* FLEXPWM4 Value Register 5 */ -#define IMXRT_FLEXPWM4_SM3FRCTRL (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM3FRCTRL_OFFSET) /* FLEXPWM4 Fractional Control Register */ -#define IMXRT_FLEXPWM4_SM3OCTRL (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM3OCTRL_OFFSET) /* FLEXPWM4 Output Control Register */ -#define IMXRT_FLEXPWM4_SM3STS (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM3STS_OFFSET) /* FLEXPWM4 Status Register */ -#define IMXRT_FLEXPWM4_SM3INTEN (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM3INTEN_OFFSET) /* FLEXPWM4 Interrupt Enable Register */ -#define IMXRT_FLEXPWM4_SM3DMAEN (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM3DMAEN_OFFSET) /* FLEXPWM4 DMA Enable Register */ -#define IMXRT_FLEXPWM4_SM3TCTRL (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM3TCTRL_OFFSET) /* FLEXPWM4 Output Trigger Control Register */ -#define IMXRT_FLEXPWM4_SM3DISMAP0 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM3DISMAP0_OFFSET) /* FLEXPWM4 Fault Disable Mapping Register 0 */ -#define IMXRT_FLEXPWM4_SM3DISMAP1 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM3DISMAP1_OFFSET) /* FLEXPWM4 Fault Disable Mapping Register 1 */ -#define IMXRT_FLEXPWM4_SM3DTCNT0 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM3DTCNT0_OFFSET) /* FLEXPWM4 Deadtime Count Register 0 */ -#define IMXRT_FLEXPWM4_SM3DTCNT1 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM3DTCNT1_OFFSET) /* FLEXPWM4 Deadtime Count Register 1 */ -#define IMXRT_FLEXPWM4_SM3CAPTCTRLA (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM3CAPTCTRLA_OFFSET) /* FLEXPWM4 Capture Control A Register */ -#define IMXRT_FLEXPWM4_SM3CAPTCOMPA (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM3CAPTCOMPA_OFFSET) /* FLEXPWM4 Capture Compare A Register */ -#define IMXRT_FLEXPWM4_SM3CAPTCTRLB (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM3CAPTCTRLB_OFFSET) /* FLEXPWM4 Capture Control B Register */ -#define IMXRT_FLEXPWM4_SM3CAPTCOMPB (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM3CAPTCOMPB_OFFSET) /* FLEXPWM4 Capture Compare B Register */ -#define IMXRT_FLEXPWM4_SM3CAPTCTRLX (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM3CAPTCTRLX_OFFSET) /* FLEXPWM4 Capture Control X Register */ -#define IMXRT_FLEXPWM4_SM3CAPTCOMPX (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM3CAPTCOMPX_OFFSET) /* FLEXPWM4 Capture Compare X Register */ -#define IMXRT_FLEXPWM4_SM3CVAL0 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM3CVAL0_OFFSET) /* FLEXPWM4 Capture Value 0 Register */ -#define IMXRT_FLEXPWM4_SM3CVAL0CYC (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM3CVAL0CYC_OFFSET) /* FLEXPWM4 Capture Value 0 Cycle Register */ -#define IMXRT_FLEXPWM4_SM3CVAL1 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM3CVAL1_OFFSET) /* FLEXPWM4 Capture Value 1 Register */ -#define IMXRT_FLEXPWM4_SM3CVAL1CYC (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM3CVAL1CYC_OFFSET) /* FLEXPWM4 Capture Value 1 Cycle Register */ -#define IMXRT_FLEXPWM4_SM3CVAL2 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM3CVAL2_OFFSET) /* FLEXPWM4 Capture Value 2 Register */ -#define IMXRT_FLEXPWM4_SM3CVAL2CYC (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM3CVAL2CYC_OFFSET) /* FLEXPWM4 Capture Value 2 Cycle Register */ -#define IMXRT_FLEXPWM4_SM3CVAL3 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM3CVAL3_OFFSET) /* FLEXPWM4 Capture Value 3 Register */ -#define IMXRT_FLEXPWM4_SM3CVAL3CYC (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM3CVAL3CYC_OFFSET) /* FLEXPWM4 Capture Value 3 Cycle Register */ -#define IMXRT_FLEXPWM4_SM3CVAL4 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM3CVAL4_OFFSET) /* FLEXPWM4 Capture Value 4 Register */ -#define IMXRT_FLEXPWM4_SM3CVAL4CYC (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM3CVAL4CYC_OFFSET) /* FLEXPWM4 Capture Value 4 Cycle Register */ -#define IMXRT_FLEXPWM4_SM3CVAL5 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM3CVAL5_OFFSET) /* FLEXPWM4 Capture Value 5 Register */ -#define IMXRT_FLEXPWM4_SM3CVAL5CYC (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SM3CVAL5CYC_OFFSET) /* FLEXPWM4 Capture Value 5 Cycle Register */ -#define IMXRT_FLEXPWM4_OUTEN (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_OUTEN_OFFSET) /* FLEXPWM4 Output Enable Register */ -#define IMXRT_FLEXPWM4_MASK (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_MASK_OFFSET) /* FLEXPWM4 Mask Register */ -#define IMXRT_FLEXPWM4_SWCOUT (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_SWCOUT_OFFSET) /* FLEXPWM4 Software Controlled Output Register */ -#define IMXRT_FLEXPWM4_DTSRCSEL (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_DTSRCSEL_OFFSET) /* FLEXPWM4 PWM Source Select Register */ -#define IMXRT_FLEXPWM4_MCTRL (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_MCTRL_OFFSET) /* FLEXPWM4 Master Control Register */ -#define IMXRT_FLEXPWM4_MCTRL2 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_MCTRL2_OFFSET) /* FLEXPWM4 Master Control 2 Register */ -#define IMXRT_FLEXPWM4_FCTRL0 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_FCTRL0_OFFSET) /* FLEXPWM4 Fault Control Register */ -#define IMXRT_FLEXPWM4_FSTS0 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_FSTS0_OFFSET) /* FLEXPWM4 Fault Status Register */ -#define IMXRT_FLEXPWM4_FFILT0 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_FFILT0_OFFSET) /* FLEXPWM4 Fault Filter Register */ -#define IMXRT_FLEXPWM4_FTST0 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_FTST0_OFFSET) /* FLEXPWM4 Fault Test Register */ -#define IMXRT_FLEXPWM4_FCTRL20 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_FCTRL20_OFFSET) /* FLEXPWM4 Fault Control 2 Register */ - -/* Register Bit Definitions ********************************************************* - * - * A single FLEXPWM[n] module (where n is 1..4) has submodules 0 - 3 - * FLEXPWM module Base addresses are spaced every 0x4000 bytes starting at - * IMXRT_FLEXPWM1_BASE. Therefore each PWM has A0-A3 and B0-B3 outputs. - * The is 8 outputs per FLEXPWM module. - * - * Each submodule instance is 0x60 bytes. - * - * The address of a register is the sum of a base address and an address offset. - * The base address is defined as the module IMXRT_FLEXPWMn_BASE (n=1..4), and - * the address offset is defined at the module level. Each PWM module has a set - * of registers for each PWM submodule, for the configuration logic, and - * for each fault channel. While the registers are 16-bits wide, they can be - * accessed in pairs as 32-bit registers. - * - * Submodule registers are repeated for each PWM submodule. To designate which - * submodule they are in, register names are prefixed with SM0, SM1, SM2, and SM3 - * Since all these register definitions are identical the defines herein drops the - * number 0-3 from the prefix. - * - * For example the 'Status Register' appears 4 times per module - * (IMXRT_FLEXPWMn_BASE) as IMXRT_FLEXPWM_SM0STS_OFFSET, IMXRT_FLEXPWM_SM1STS_OFFSET, - * IMXRT_FLEXPWM_SM2STS_OFFSET and IMXRT_FLEXPWM_SM3STS_OFFSET. But the bit - * definitions for the 'Status Register' are defined as SMSTS_xxxxx (with the number - * dropped. - * - * The base address of submodule 0 is the same as the base address for the PWM - * module as a whole. The base address of submodule 1 is offset 0x60 from the base - * address for the PWM module as a whole. This 0x60 offset is based on the number - * of registers in a submodule. The base address of submodule 2 is equal to the - * base address of submodule 1 plus this same 0x60 offset. The pattern repeats for - * the base address of submodule 3 - * . - * The base address of the module configuration registers is equal to the base - * address of the PWM module as a whole plus an offset of 0x180. - * - * Fault channel registers are repeated for each fault channel. To designate - * which fault channel they are in, register names are prefixed with F0 and F1. The - * base address of fault channel 0 is equal to the base address of the PWM module - * as a whole plus an offset of 0x18C. The base address of fault channel 1 is the - * base address of fault channel 0 + 4. This 4 offset is based on the number of - * registers in a fault channel. Each of the four fields in the fault channel - * registers corresponds to fault inputs 3-0. - */ - -/* Control 2 Register */ - -#define SMCTRL2_CLK_SEL_SHIFT (0) /* Bits: 0-1 Clock Source Select */ -#define SMCTRL2_CLK_SEL_MASK (3 << SMCTRL2_CLK_SEL_SHIFT) -# define SMCTRL2_CLK_SEL(n) ((uint32_t)(n) << SMCTRL2_CLK_SEL_SHIFT) -# define SMCTRL2_CLK_SEL_IPG_CLK (0 << SMCTRL2_CLK_SEL_SHIFT) /* The IPBus clock is used as the clock for the local prescaler and counter. */ -# define SMCTRL2_CLK_SEL_EXT_CLK (1 << SMCTRL2_CLK_SEL_SHIFT) /* EXT_CLK is used as the clock for the local prescaler and counter. */ -# define SMCTRL2_CLK_SEL_AUX_CLK (2 << SMCTRL2_CLK_SEL_SHIFT) /* Submodule 0’s clock (AUX_CLK) is used as the source clock for the local prescaler and counter. */ -#define SMCTRL2_RELOAD_SEL (1 << 2) /* Bit: 2 Reload Source Select */ -# define SMCTRL2_RELOAD_SEL_LOCAL (0 << 2) /* Reload Source is local */ -# define SMCTRL2_RELOAD_SEL_SM0 (1 << 2) /* Reload Source is submodule 0 */ -#define SMCTRL2_FORCE_SEL_SHIFT (3) /* Bits: 3-5 This read/write bit determines the source of the FORCE OUTPUT signal for this submodule. */ -#define SMCTRL2_FORCE_SEL_MASK (7 << SMCTRL2_FORCE_SEL_SHIFT) -# define SMCTRL2_FORCE_SEL(n) ((uint32_t)(n) << SMCTRL2_FORCE_SEL_SHIFT) -# define SMCTRL2_FORCE_SEL_CTRL2_FORCE (0 << SMCTRL2_FORCE_SEL_SHIFT) /* The local force signal, CTRL2[FORCE], from this submodule is used to force updates. */ -# define SMCTRL2_FORCE_SEL_SM0 (1 << SMCTRL2_FORCE_SEL_SHIFT) /* The master force signal from submodule 0 is used to force updates. */ -# define SMCTRL2_FORCE_SEL_LOCAL (2 << SMCTRL2_FORCE_SEL_SHIFT) /* The local reload signal from this submodule is used to force updates without regard to the state of LDOK. */ -# define SMCTRL2_FORCE_SEL_SM0_LDOK (3 << SMCTRL2_FORCE_SEL_SHIFT) /* The master reload signal from submodule0 is used to force updates if LDOK is set. */ -# define SMCTRL2_FORCE_SEL_LOCAL_SYNC (4 << SMCTRL2_FORCE_SEL_SHIFT) /* The local sync signal from this submodule is used to force updates. */ -# define SMCTRL2_FORCE_SEL_SM0_SYNC (5 << SMCTRL2_FORCE_SEL_SHIFT) /* The master sync signal from submodule0 is used to force updates. */ -# define SMCTRL2_FORCE_SEL_EXT_FORCE (6 << SMCTRL2_FORCE_SEL_SHIFT) /* The external force signal, EXT_FORCE, from outside the PWM module causes updates. */ -# define SMCTRL2_FORCE_SEL_EXT_SYNC (7 << SMCTRL2_FORCE_SEL_SHIFT) /* The external sync signal, EXT_SYNC, from outside the PWM module causes updates */ -#define SMCTRL2_FORCE (1 << 6) /* Bit: 6 Force Initialization */ -#define SMCTRL2_FRCEN (1 << 7) /* Bit: 7 FRCEN */ -#define SMCTRL2_INIT_SEL_SHIFT (8) /* Bits: 8-9 Initialization Control Select */ -#define SMCTRL2_INIT_SEL_MASK (3 << SMCTRL2_INIT_SEL_SHIFT) -# define SMCTRL2_INIT_SEL(n) ((uint32_t)(n) << SMCTRL2_INIT_SEL_SHIFT) -# define SMCTRL2_INIT_SEL_LOCAL (0 << SMCTRL2_INIT_SEL_SHIFT) /* Local sync (PWM_X) causes initialization. */ -# define SMCTRL2_INIT_SEL_SM0 (1 << SMCTRL2_INIT_SEL_SHIFT) /* Master reload from submodule 0 causes initialization. */ -# define SMCTRL2_INIT_SEL_SM0_SYNC (2 << SMCTRL2_INIT_SEL_SHIFT) /* Master sync from submodule 0 causes initialization. */ -# define SMCTRL2_INIT_SEL_EXT_SYNC (3 << SMCTRL2_INIT_SEL_SHIFT) /* EXT_SYNC causes initialization. */ -#define SMCTRL2_PWMX_INIT (1 << 10) /* Bit: 10 PWM_X Initial Value */ -#define SMCTRL2_PWM45_INIT (1 << 11) /* Bit: 11 PWM45 Initial Value */ -#define SMCTRL2_PWM23_INIT (1 << 12) /* Bit: 12 PWM23 Initial Value */ -#define SMCTRL2_INDEP (1 << 13) /* Bit: 13 Independent or Complementary Pair Operation */ -#define SMCTRL2_WAITEN (1 << 14) /* Bit: 14 WAIT Enable */ -#define SMCTRL2_DBGEN (1 << 15) /* Bit: 15 Debug Enable */ - -/* Control Register */ - -#define SMCTRL_DBLEN (1 << 0) /* Bit: 0 Double Switching Enable */ -#define SMCTRL_DBLX (1 << 1) /* Bit: 1 PWMX Double Switching Enable */ -#define SMCTRL_LDMOD (1 << 2) /* Bit: 2 Load Mode Select */ -#define SMCTRL_SPLIT (1 << 3) /* Bit: 3 Split the DBLPWM signal to PWMA and PWMB */ -#define SMCTRL_PRSC_SHIFT (4) /* Bits: 4-6 Prescaler */ -#define SMCTRL_PRSC_MASK (7 << SMCTRL_PRSC_SHIFT) -# define SMCTRL_PRSC(n) ((uint32_t)(n) << SMCTRL_PRSC_SHIFT) -# define SMCTRL_PRSC_DIV1 (0 << SMCTRL_PRSC_SHIFT) /* PWM clock frequency = fclk */ -# define SMCTRL_PRSC_DIV2 (1 << SMCTRL_PRSC_SHIFT) /* PWM clock frequency = fclk/2 */ -# define SMCTRL_PRSC_DIV4 (2 << SMCTRL_PRSC_SHIFT) /* PWM clock frequency = fclk/4 */ -# define SMCTRL_PRSC_DIV8 (3 << SMCTRL_PRSC_SHIFT) /* PWM clock frequency = fclk/8 */ -# define SMCTRL_PRSC_DIV16 (4 << SMCTRL_PRSC_SHIFT) /* PWM clock frequency = fclk/16 */ -# define SMCTRL_PRSC_DIV32 (5 << SMCTRL_PRSC_SHIFT) /* PWM clock frequency = fclk/32 */ -# define SMCTRL_PRSC_DIV64 (6 << SMCTRL_PRSC_SHIFT) /* PWM clock frequency = fclk/64 */ -# define SMCTRL_PRSC_DIV128 (7 << SMCTRL_PRSC_SHIFT) /* PWM clock frequency = fclk/128*/ -#define SMCTRL_COMPMODE (1 << 7) /* Bit: 7 Compare Mode */ -#define SMCTRL_DT_SHIFT (8) /* Bits: 8-9 Deadtime */ -#define SMCTRL_DT_MASK (3 << SMCTRL_DT_SHIFT) -# define SMCTRL_DT(n) ((uint32_t)(n) << SMCTRL_DT_SHIFT) -# define SMCTRL_DT0 (1 << SMCTRL_DT_SHIFT) /* Read Only. These read only bits reflect the sampled values of the PWM_X input */ -# define SMCTRL_DT1 (2 << SMCTRL_DT_SHIFT) /* Sampling occurs at the end of deadtime 0 for DT[0] and the end of deadtime 1 for DT[1]. */ -#define SMCTRL_FULL (1 << 10) /* Bit: 10 Full Cycle Reload */ -#define SMCTRL_HALF (1 << 11) /* Bit: 11 Half Cycle Reload */ -#define SMCTRL_LDFQ_SHIFT (12) /* Bits: 12-15 Load Frequency */ -#define SMCTRL_LDFQ_MASK (0xf << SMCTRL_LDFQ_SHIFT) -# define SMCTRL_LDFQ(n) ((uint32_t)(n) << SMCTRL_LDFQ_SHIFT) -# define SMCTRL_LDFQ_EVERY (0 << SMCTRL_LDFQ_SHIFT) /* Every PWM opportunity */ -# define SMCTRL_LDFQ_EVERY2 (1 << SMCTRL_LDFQ_SHIFT) /* Every 2 PWM opportunities */ -# define SMCTRL_LDFQ_EVERY3 (2 << SMCTRL_LDFQ_SHIFT) /* Every 3 PWM opportunities */ -# define SMCTRL_LDFQ_EVERY4 (3 << SMCTRL_LDFQ_SHIFT) /* Every 4 PWM opportunities */ -# define SMCTRL_LDFQ_EVERY5 (4 << SMCTRL_LDFQ_SHIFT) /* Every 5 PWM opportunities */ -# define SMCTRL_LDFQ_EVERY6 (5 << SMCTRL_LDFQ_SHIFT) /* Every 6 PWM opportunities */ -# define SMCTRL_LDFQ_EVERY7 (6 << SMCTRL_LDFQ_SHIFT) /* Every 7 PWM opportunities */ -# define SMCTRL_LDFQ_EVERY8 (7 << SMCTRL_LDFQ_SHIFT) /* Every 8 PWM opportunities */ -# define SMCTRL_LDFQ_EVERY9 (8 << SMCTRL_LDFQ_SHIFT) /* Every 9 PWM opportunities */ -# define SMCTRL_LDFQ_EVERY10 (9 << SMCTRL_LDFQ_SHIFT) /* Every 10 PWM opportunities */ -# define SMCTRL_LDFQ_EVERY11 (10 << SMCTRL_LDFQ_SHIFT) /* Every 11 PWM opportunities */ -# define SMCTRL_LDFQ_EVERY12 (11 << SMCTRL_LDFQ_SHIFT) /* Every 12 PWM opportunities */ -# define SMCTRL_LDFQ_EVERY13 (12 << SMCTRL_LDFQ_SHIFT) /* Every 13 PWM opportunities */ -# define SMCTRL_LDFQ_EVERY14 (13 << SMCTRL_LDFQ_SHIFT) /* Every 14 PWM opportunities */ -# define SMCTRL_LDFQ_EVERY15 (14 << SMCTRL_LDFQ_SHIFT) /* Every 15 PWM opportunities */ -# define SMCTRL_LDFQ_EVERY16 (0xf << SMCTRL_LDFQ_SHIFT) /* Every 16 PWM opportunities */ - -/* Fractional Value Register 1 */ - -#define SMFRACV_FRACVAL1_SHIFT (11) /* Bits: 11-15 Fractional Value 1 Register */ -#define SMFRACV_FRACVAL1_MASK (0x1f << SMFRACV_FRACVAL1_SHIFT) -# define SMFRACV_FRACVAL1(n) ((uint32_t)(n) << SMFRACV_FRACVAL1_SHIFT) - -/* Fractional Value Register 2 */ - -#define SMFRACV_FRACVAL2_SHIFT (11) /* Bits: 11-15 Fractional Value 2 Register */ -#define SMFRACV_FRACVAL2_MASK (0x1f << SMFRACV_FRACVAL2_SHIFT) -# define SMFRACV_FRACVAL2(n) ((uint32_t)(n) << SMFRACV_FRACVAL2_SHIFT) - -/* Fractional Value Register 3 */ - -#define SMFRACV_FRACVAL3_SHIFT (11) /* Bits: 11-15 Fractional Value 3 Register */ -#define SMFRACV_FRACVAL3_MASK (0x1f << SMFRACV_FRACVAL3_SHIFT) -# define SMFRACV_FRACVAL3(n) ((uint32_t)(n) << SMFRACV_FRACVAL3_SHIFT) - -/* Fractional Value Register 4 */ - -#define SMFRACV_FRACVAL4_SHIFT (11) /* Bits: 11-15 Fractional Value 4 Register */ -#define SMFRACV_FRACVAL4_MASK (0x1f << SMFRACV_FRACVAL4_SHIFT) -# define SMFRACV_FRACVAL4(n) ((uint32_t)(n) << SMFRACV_FRACVAL4_SHIFT) - -/* Fractional Value Register 5 */ - -#define SMFRACV_FRACVAL5_SHIFT (11) /* Bits: 11-15 Fractional Value 5 Register */ -#define SMFRACV_FRACVAL5_MASK (0x1f << SMFRACV_FRACVAL5_SHIFT) -# define SMFRACV_FRACVAL5(n) ((uint32_t)(n) << SMFRACV_FRACVAL5_SHIFT) - -/* Fractional Control Register */ - - /* Bit: 0 Reserved */ -#define SMFRCTRL_FRAC1_EN (1 << 1) /* Bit: 1 Fractional Cycle PWM Period Enable */ -#define SMFRCTRL_FRAC23_EN (1 << 2) /* Bit: 2 Fractional Cycle Placement Enable for PWM_A */ - /* Bit: 3 Reserved */ -#define SMFRCTRL_FRAC45_EN (1 << 4) /* Bit: 4 Fractional Cycle Placement Enable for PWM_B */ - /* Bits: 5-7 Reserved */ -#define SMFRCTRL_FRAC_PU (1 << 8) /* Bit: 8 Fractional Delay Circuit Power Up */ - /* Bits: 9-15 Reserved */ -#define SMFRCTRL_TEST (1 << 15) /* Bit: 15 Test Status Bit */ - -/* Output Control Register */ - -#define SMOCTRL_PWMXFS_SHIFT (0) /* Bits: 0-1 PWM_X Fault State */ -#define SMOCTRL_PWMXFS_MASK (3 << SMOCTRL_PWMXFS_SHIFT) -# define SMOCTRL_PWMXFS(n) ((uint32_t)(n) << SMOCTRL_PWMXFS_SHIFT) -# define SMOCTRL_PWMXFS_0 (0 << SMOCTRL_PWMXFS_SHIFT) /* Output is forced to logic 0 state prior to consideration of output polarity control. */ -# define SMOCTRL_PWMXFS_1 (1 << SMOCTRL_PWMXFS_SHIFT) /* Output is forced to logic 1 state prior to consideration of output polarity control. */ -# define SMOCTRL_PWMXFS_TRISTATE (2 << SMOCTRL_PWMXFS_SHIFT) /* Output is tristated. */ -#define SMOCTRL_PWMBFS_SHIFT (2) /* Bits: 2-3 PWM_B Fault State */ -#define SMOCTRL_PWMBFS_MASK (3 << SMOCTRL_PWMBFS_SHIFT) -# define SMOCTRL_PWMBFS(n) ((uint32_t)(n) << SMOCTRL_PWMBFS_SHIFT) -# define SMOCTRL_PWMBFS_0 (0 << SMOCTRL_PWMBFS_SHIFT) /* Output is forced to logic 0 state prior to consideration of output polarity control. */ -# define SMOCTRL_PWMBFS_1 (1 << SMOCTRL_PWMBFS_SHIFT) /* Output is forced to logic 1 state prior to consideration of output polarity control. */ -# define SMOCTRL_PWMBFS_TRISTATE (2 << SMOCTRL_PWMBFS_SHIFT) /* Output is tristated. */ -#define SMOCTRL_PWMAFS_SHIFT (4) /* Bits: 4-5 PWM_A Fault State */ -#define SMOCTRL_PWMAFS_MASK (3 << SMOCTRL_PWMAFS_SHIFT) -# define SMOCTRL_PWMAFS(n) ((uint32_t)(n) << SMOCTRL_PWMAFS_SHIFT) -# define SMOCTRL_PWMAFS_0 (0 << SMOCTRL_PWMAFS_SHIFT) /* Output is forced to logic 0 state prior to consideration of output polarity control. */ -# define SMOCTRL_PWMAFS_1 (1 << SMOCTRL_PWMAFS_SHIFT) /* Output is forced to logic 1 state prior to consideration of output polarity control. */ -# define SMOCTRL_PWMAFS_TRISTATE (2 << SMOCTRL_PWMAFS_SHIFT) /* Output is tristated. */ - /* Bits: 6-7 Reserved */ -#define SMOCTRL_POLX (1 << 8) /* Bit: 8 PWM_X Output Polarity */ -#define SMOCTRL_POLB (1 << 9) /* Bit: 9 PWM_B Output Polarity */ -#define SMOCTRL_POLA (1 << 10) /* Bit: 10 PWM_A Output Polarity */ - /* Bits: 11-12 Reserved */ -#define SMOCTRL_PWMX_IN (1 << 13) /* Bit: 13 PWM_X Input */ -#define SMOCTRL_PWMB_IN (1 << 14) /* Bit: 14 PWM_B Input */ -#define SMOCTRL_PWMA_IN (1 << 15) /* Bit: 15 PWM_A Input */ - -/* Status Register */ - -#define SMSTS_CMPF_SHIFT (0) /* Bits: 0-5 Compare Flags */ -#define SMSTS_CMPF_MASK (0x3f << SMSTS_CMPF_SHIFT) -# define SMSTS_CMPF(n) ((uint32_t)(n) << SMSTS_CMPF_SHIFT) -# define SMSTS_CMPF_VAL0 (1 << SMSTS_CMPF_SHIFT) /* A compare event has occurred for VAL0 value */ -# define SMSTS_CMPF_VAL1 (2 << SMSTS_CMPF_SHIFT) /* A compare event has occurred for VAL1 value */ -# define SMSTS_CMPF_VAL2 (4 << SMSTS_CMPF_SHIFT) /* A compare event has occurred for VAL2 value */ -# define SMSTS_CMPF_VAL3 (8 << SMSTS_CMPF_SHIFT) /* A compare event has occurred for VAL3 value */ -# define SMSTS_CMPF_VAL4 (16 << SMSTS_CMPF_SHIFT) /* A compare event has occurred for VAL4 value */ -# define SMSTS_CMPF_VAL5 (32 << SMSTS_CMPF_SHIFT) /* A compare event has occurred for VAL5 value */ -#define SMSTS_CFX0 (1 << 6) /* Bit: 6 Capture Flag X0 */ -#define SMSTS_CFX1 (1 << 7) /* Bit: 7 Capture Flag X1 */ -#define SMSTS_CFB0 (1 << 8) /* Bit: 8 Capture Flag B0 */ -#define SMSTS_CFB1 (1 << 9) /* Bit: 9 Capture Flag B1 */ -#define SMSTS_CFA0 (1 << 10) /* Bit: 10 Capture Flag A0 */ -#define SMSTS_CFA1 (1 << 11) /* Bit: 11 Capture Flag A1 */ -#define SMSTS_RF (1 << 12) /* Bit: 12 Reload Flag */ -#define SMSTS_REF (1 << 13) /* Bit: 13 Reload Error Flag */ -#define SMSTS_RUF (1 << 14) /* Bit: 14 This read-only flag is set when one of the INIT, VALx,FRACVALx, or CTRL[PRSC] is written */ - /* Bit: 15 Reserved */ - -/* Interrupt Enable Register */ - -#define SMINTEN_CMPIE_SHIFT (0) /* Bits: 0-5 Compare Interrupt Enables */ -#define SMINTEN_CMPIE_MASK (0x3f << SMINTEN_CMPIE_SHIFT) -# define SMINTEN_CMPIE(n) ((uint32_t)(n) << SMINTEN_CMPIE_SHIFT) -# define SMINTEN_CMPIE_VAL0 (1 << SMINTEN_CMPIE_SHIFT) /* A compare event for VAL0 value will generate an interrupt */ -# define SMINTEN_CMPIE_VAL1 (2 << SMINTEN_CMPIE_SHIFT) /* A compare event for VAL1 value will generate an interrupt */ -# define SMINTEN_CMPIE_VAL2 (4 << SMINTEN_CMPIE_SHIFT) /* A compare event for VAL2 value will generate an interrupt */ -# define SMINTEN_CMPIE_VAL3 (8 << SMINTEN_CMPIE_SHIFT) /* A compare event for VAL3 value will generate an interrupt */ -# define SMINTEN_CMPIE_VAL4 (16 << SMINTEN_CMPIE_SHIFT) /* A compare event for VAL4 value will generate an interrupt */ -# define SMINTEN_CMPIE_VAL5 (32 << SMINTEN_CMPIE_SHIFT) /* A compare event for VAL5 value will generate an interrupt */ -#define SMINTEN_CX0IE (1 << 6) /* Bit: 6 Capture X 0 Interrupt Enable */ -#define SMINTEN_CX1IE (1 << 7) /* Bit: 7 Capture X 1 Interrupt Enable */ -#define SMINTEN_CB0IE (1 << 8) /* Bit: 8 Capture B 0 Interrupt Enable */ -#define SMINTEN_CB1IE (1 << 9) /* Bit: 9 Capture B 1 Interrupt Enable */ -#define SMINTEN_CA0IE (1 << 10) /* Bit: 10 Capture A 0 Interrupt Enable */ -#define SMINTEN_CA1IE (1 << 11) /* Bit: 11 Capture A 1 Interrupt Enable */ -#define SMINTEN_RIE (1 << 12) /* Bit: 12 Reload Interrupt Enable */ -#define SMINTEN_REIE (1 << 13) /* Bit: 13 Reload Error Interrupt Enable */ - /* Bits: 14-15 Reserved */ - -/* DMA Enable Register */ - -#define SMDMAEN_CX0DE (1 << 0) /* Bit: 0 Capture X0 FIFO DMA Enable */ -#define SMDMAEN_CX1DE (1 << 1) /* Bit: 1 Capture X1 FIFO DMA Enable */ -#define SMDMAEN_CB0DE (1 << 2) /* Bit: 2 Capture B0 FIFO DMA Enable */ -#define SMDMAEN_CB1DE (1 << 3) /* Bit: 3 Capture B1 FIFO DMA Enable */ -#define SMDMAEN_CA0DE (1 << 4) /* Bit: 4 Capture A0 FIFO DMA Enable */ -#define SMDMAEN_CA1DE (1 << 5) /* Bit: 5 Capture A1 FIFO DMA Enable */ -#define SMDMAEN_CAPTDE_SHIFT (6) /* Bits: 6-7 Capture DMA Enable Source Select */ -#define SMDMAEN_CAPTDE_MASK (3 << SMDMAEN_CAPTDE_SHIFT) -# define SMDMAEN_CAPTDE(n) ((uint32_t)(n) << SMDMAEN_CAPTDE_SHIFT) -# define SMDMAEN_CAPTDE_DIS (0 << SMDMAEN_CAPTDE_SHIFT) /* Read DMA requests disabled. */ -# define SMDMAEN_CAPTDE_WMT (1 << SMDMAEN_CAPTDE_SHIFT) /* Exceeding a FIFO watermark sets the DMA read request. */ -# define SMDMAEN_CAPTDE_SYNC (2 << SMDMAEN_CAPTDE_SHIFT) /* A local sync (VAL1 matches counter) sets the read DMA request. */ -# define SMDMAEN_CAPTDE_RELOAD (3 << SMDMAEN_CAPTDE_SHIFT) /* A local reload (STS[RF] being set) sets the read DMA request. */ -#define SMDMAEN_FAND (1 << 8) /* Bit: 8 FIFO Watermark AND Control */ -#define SMDMAEN_VALDE (1 << 9) /* Bit: 9 Value Registers DMA Enable */ - /* Bits: 10-15 Reserved */ - -/* Output Trigger Control Register */ - -#define SMT_OUT_TRIG_EN_SHIFT (0) /* Bits: 0-5 Output Trigger Enables */ -#define SMT_OUT_TRIG_EN_MASK (0x3f << SMT_OUT_TRIG_EN_SHIFT) -# define SMT_OUT_TRIG_EN(n) ((uint32_t)(n) << SMT_OUT_TRIG_EN_SHIFT) -# define SMT_OUT_TRIG_EN_VAL0 (1 << SMT_OUT_TRIG_EN_SHIFT) /* PWM_OUT_TRIGx will set when the counter value matches the VAL0 value */ -# define SMT_OUT_TRIG_EN_VAL1 (2 << SMT_OUT_TRIG_EN_SHIFT) /* PWM_OUT_TRIGx will set when the counter value matches the VAL1 value */ -# define SMT_OUT_TRIG_EN_VAL2 (4 << SMT_OUT_TRIG_EN_SHIFT) /* PWM_OUT_TRIGx will set when the counter value matches the VAL2 value */ -# define SMT_OUT_TRIG_EN_VAL3 (8 << SMT_OUT_TRIG_EN_SHIFT) /* PWM_OUT_TRIGx will set when the counter value matches the VAL3 value */ -# define SMT_OUT_TRIG_EN_VAL4 (16 << SMT_OUT_TRIG_EN_SHIFT) /* PWM_OUT_TRIGx will set when the counter value matches the VAL4 value */ -# define SMT_OUT_TRIG_EN_VAL5 (32 << SMT_OUT_TRIG_EN_SHIFT) /* PWM_OUT_TRIGx will set when the counter value matches the VAL5 value */ - /* Bits: 6-11 Reserved */ -#define SMT_TRGFRQ (1 << 12) /* Bit: 12 Trigger frequency */ - /* Bit: 13 Reserved */ -#define SMT_PWBOT1 (1 << 14) /* Bit: 14 Output Trigger 1 Source Select */ -# define SMT_PWBOT1_OUT_TRIG1 (0 << 14) /* Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port */ -# define SMT_PWBOT1_PWMMB (1 << 14) /* Route the PWMB output to the PWM_OUT_TRIG1 port */ -#define SMT_PWBOT0 (1 << 15) /* Bit: 15 Output Trigger 0 Source Select */ -# define SMT_PWBOT0_OUT_TRIG0 (0 << 15) /* Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port */ -# define SMT_PWBOT0_PWMMB (1 << 15) /* Route the PWMA output to the PWM_OUT_TRIG0 port */ - -/* Fault Disable Mapping Register 0 */ - -#define SMD_DIS0A_SHIFT (0) /* Bits: 0-3 PWM_A Fault Disable Mask 0 */ -#define SMD_DIS0A_MASK (0xf << SMD_DIS0A_SHIFT) -# define SMD_DIS0A(n) ((uint32_t)(n) << SMD_DIS0A_SHIFT) -# define SMD_DIS0A_FAULT0 (1 << SMD_DIS0A_SHIFT) /* FAULT0 inputs of fault channel 0. */ -# define SMD_DIS0A_FAULT1 (2 << SMD_DIS0A_SHIFT) /* FAULT1 inputs of fault channel 0. */ -# define SMD_DIS0A_FAULT2 (4 << SMD_DIS0A_SHIFT) /* FAULT2 inputs of fault channel 0. */ -# define SMD_DIS0A_FAULT3 (8 << SMD_DIS0A_SHIFT) /* FAULT3 inputs of fault channel 0. */ -#define SMD_DIS0B_SHIFT (4) /* Bits: 4-7 PWM_B Fault Disable Mask 0 */ -#define SMD_DIS0B_MASK (0xf << SMD_DIS0B_SHIFT) -# define SMD_DIS0B(n) ((uint32_t)(n) << SMD_DIS0B_SHIFT) -# define SMD_DIS0B_FAULT0 (1 << SMD_DIS0B_SHIFT) /* FAULT0 inputs of fault channel 0. */ -# define SMD_DIS0B_FAULT1 (2 << SMD_DIS0B_SHIFT) /* FAULT1 inputs of fault channel 0. */ -# define SMD_DIS0B_FAULT2 (4 << SMD_DIS0B_SHIFT) /* FAULT2 inputs of fault channel 0. */ -# define SMD_DIS0B_FAULT3 (8 << SMD_DIS0B_SHIFT) /* FAULT3 inputs of fault channel 0. */ -#define SMD_DIS0X_SHIFT (8) /* Bits: 8-11 PWM_X Fault Disable Mask 0 */ -#define SMD_DIS0X_MASK (0xf << SMD_DIS0X_SHIFT) -# define SMD_DIS0X(n) ((uint32_t)(n) << SMD_DIS0X_SHIFT) -# define SMD_DIS0X_FAULT0 (1 << SMD_DIS0X_SHIFT) /* FAULT0 inputs of fault channel 0. */ -# define SMD_DIS0X_FAULT1 (2 << SMD_DIS0X_SHIFT) /* FAULT1 inputs of fault channel 0. */ -# define SMD_DIS0X_FAULT2 (4 << SMD_DIS0X_SHIFT) /* FAULT2 inputs of fault channel 0. */ -# define SMD_DIS0X_FAULT3 (8 << SMD_DIS0X_SHIFT) /* FAULT3 inputs of fault channel 0. */ - /* Bits: 12-15 Reserved */ - -/* Fault Disable Mapping Register 1 */ - -#define SMD_DIS1A_SHIFT (0) /* Bits: 0-3 PWM_A Fault Disable Mask 1 */ -#define SMD_DIS1A_MASK (0xf << SMD_DIS1A_SHIFT) -# define SMD_DIS1A(n) ((uint32_t)(n) << SMD_DIS1A_SHIFT) -# define SMD_DIS1A_FAULT0 (1 << SMD_DIS1A_SHIFT) /* FAULT0 inputs of fault channel 1. */ -# define SMD_DIS1A_FAULT1 (2 << SMD_DIS1A_SHIFT) /* FAULT1 inputs of fault channel 1. */ -# define SMD_DIS1A_FAULT2 (4 << SMD_DIS1A_SHIFT) /* FAULT2 inputs of fault channel 1. */ -# define SMD_DIS1A_FAULT3 (8 << SMD_DIS1A_SHIFT) /* FAULT3 inputs of fault channel 1. */ -#define SMD_DIS1B_SHIFT (4) /* Bits: 4-7 PWM_B Fault Disable Mask 1 */ -#define SMD_DIS1B_MASK (0xf << SMD_DIS1B_SHIFT) -# define SMD_DIS1B(n) ((uint32_t)(n) << SMD_DIS1B_SHIFT) -# define SMD_DIS1B_FAULT0 (1 << SMD_DIS1B_SHIFT) /* FAULT0 inputs of fault channel 1. */ -# define SMD_DIS1B_FAULT1 (2 << SMD_DIS1B_SHIFT) /* FAULT1 inputs of fault channel 1. */ -# define SMD_DIS1B_FAULT2 (4 << SMD_DIS1B_SHIFT) /* FAULT2 inputs of fault channel 1. */ -# define SMD_DIS1B_FAULT3 (8 << SMD_DIS1B_SHIFT) /* FAULT3 inputs of fault channel 1. */ -#define SMD_DIS1X_SHIFT (8) /* Bits: 8-11 PWM_X Fault Disable Mask 1 */ -#define SMD_DIS1X_MASK (0xf << SMD_DIS1X_SHIFT) -# define SMD_DIS1X(n) ((uint32_t)(n) << SMD_DIS1X_SHIFT) -# define SMD_DIS1X_FAULT0 (1 << SMD_DIS1X_SHIFT) /* FAULT0 inputs of fault channel 1. */ -# define SMD_DIS1X_FAULT1 (2 << SMD_DIS1X_SHIFT) /* FAULT1 inputs of fault channel 1. */ -# define SMD_DIS1X_FAULT2 (4 << SMD_DIS1X_SHIFT) /* FAULT2 inputs of fault channel 1. */ -# define SMD_DIS1X_FAULT3 (8 << SMD_DIS1X_SHIFT) /* FAULT3 inputs of fault channel 1. */ - /* Bits: 12-15 Reserved */ - -/* Capture Control A Register */ - -#define SMC_ARMA (1 << 0) /* Bit: 0 Arm A */ -#define SMC_ONESHOTA (1 << 1) /* Bit: 1 One Shot Mode A */ -#define SMC_EDGA0_SHIFT (2) /* Bits: 2-3 Edge A 0 */ -#define SMC_EDGA0_MASK (3 << SMC_EDGA0_SHIFT) -# define SMC_EDGA0(n) ((uint32_t)(n) << SMC_EDGA0_SHIFT) -# define SMC_EDGA0_DIS (0 << SMC_EDGA0_SHIFT) /* Disabled */ -# define SMC_EDGA0_FALLING (1 << SMC_EDGA0_SHIFT) /* Capture falling edges */ -# define SMC_EDGA0_RISING (2 << SMC_EDGA0_SHIFT) /* Capture rising edges */ -# define SMC_EDGA0_BOTH (3 << SMC_EDGA0_SHIFT) /* Capture any edge */ -#define SMC_EDGA1_SHIFT (4) /* Bits: 4-5 Edge A 1 */ -#define SMC_EDGA1_MASK (3 << SMC_EDGA1_SHIFT) -# define SMC_EDGA1(n) ((uint32_t)(n) << SMC_EDGA1_SHIFT) -# define SMC_EDGA1_DIS (0 << SMC_EDGA1_SHIFT) /* Disabled */ -# define SMC_EDGA1_FALLING (1 << SMC_EDGA1_SHIFT) /* Capture falling edges */ -# define SMC_EDGA1_RISING (2 << SMC_EDGA1_SHIFT) /* Capture rising edges */ -# define SMC_EDGA1_BOTH (3 << SMC_EDGA1_SHIFT) /* Capture any edge */ -#define SMC_INP_SELA (1 << 6) /* Bit: 6 Input Select A */ -#define SMC_EDGCNTA_EN (1 << 7) /* Bit: 7 Edge Counter A Enable */ -#define SMC_CFAWM_SHIFT (8) /* Bits: 8-9 Capture A FIFOs Water Mark */ -#define SMC_CFAWM_MASK (3 << SMC_CFAWM_SHIFT) -# define SMC_CFAWM(n) ((uint32_t)(n) << SMC_CFAWM_SHIFT) -# define SMC_CFAWM_1 (0 << SMC_CFAWM_SHIFT) /* Water mark level of 1 for capture A FIFOs */ -# define SMC_CFAWM_2 (1 << SMC_CFAWM_SHIFT) /* Water mark level of 2 for capture A FIFOs */ -# define SMC_CFAWM_3 (2 << SMC_CFAWM_SHIFT) /* Water mark level of 3 for capture A FIFOs */ -# define SMC_CFAWM_4 (3 << SMC_CFAWM_SHIFT) /* Water mark level of 4 for capture A FIFOs */ -#define SMC_CA0CNT_SHIFT (10) /* Bits: 10-12 Capture A0 FIFO Word Count */ -#define SMC_CA0CNT_MASK (7 << SMC_CA0CNT_SHIFT) -# define SMC_CA0CNT(n) ((uint32_t)(n) << SMC_CA0CNT_SHIFT) -# define SMC_CA0CNT_00 (0 << SMC_CA0CNT_SHIFT) /* 0 words in the Capture A0 FIFO. */ -# define SMC_CA0CNT_01 (1 << SMC_CA0CNT_SHIFT) /* 1 word in the Capture A0 FIFO. */ -# define SMC_CA0CNT_02 (2 << SMC_CA0CNT_SHIFT) /* 2 words in the Capture A0 FIFO. */ -# define SMC_CA0CNT_03 (3 << SMC_CA0CNT_SHIFT) /* 3 words in the Capture A0 FIFO. */ -# define SMC_CA0CNT_04 (4 << SMC_CA0CNT_SHIFT) /* 4 words in the Capture A0 FIFO. */ -# define SMC_CA0CNT_05 (5 << SMC_CA0CNT_SHIFT) /* 5 words in the Capture A0 FIFO. */ -# define SMC_CA0CNT_06 (6 << SMC_CA0CNT_SHIFT) /* 6 words in the Capture A0 FIFO. */ -# define SMC_CA0CNT_07 (7 << SMC_CA0CNT_SHIFT) /* 7 words in the Capture A0 FIFO. */ -#define SMC_CA1CNT_SHIFT (13) /* Bits: 13-15 Capture A1 FIFO Word Count */ -#define SMC_CA1CNT_MASK (7 << SMC_CA1CNT_SHIFT) -# define SMC_CA1CNT(n) ((uint32_t)(n) << SMC_CA1CNT_SHIFT) -# define SMC_CA1CNT_00 (0 << SMC_CA1CNT_SHIFT) /* 1 word in the Capture A1 FIFO. */ -# define SMC_CA1CNT_01 (1 << SMC_CA1CNT_SHIFT) /* 2 words in the Capture A1 FIFO. */ -# define SMC_CA1CNT_02 (2 << SMC_CA1CNT_SHIFT) /* 3 words in the Capture A1 FIFO. */ -# define SMC_CA1CNT_03 (3 << SMC_CA1CNT_SHIFT) /* 4 words in the Capture A1 FIFO. */ -# define SMC_CA1CNT_04 (4 << SMC_CA1CNT_SHIFT) /* 5 words in the Capture A1 FIFO. */ -# define SMC_CA1CNT_05 (5 << SMC_CA1CNT_SHIFT) /* 6 words in the Capture A1 FIFO. */ -# define SMC_CA1CNT_06 (6 << SMC_CA1CNT_SHIFT) /* 7 words in the Capture A1 FIFO. */ -# define SMC_CA1CNT_07 (7 << SMC_CA1CNT_SHIFT) /* 8 words in the Capture A1 FIFO. */ - -/* Capture Compare A Register */ - -#define SMC_EDGCMPA_SHIFT (0) /* Bits: 0-7 Edge Compare A */ -#define SMC_EDGCMPA_MASK (0xff << SMC_EDGCMPA_SHIFT) -# define SMC_EDGCMPA(n) ((uint32_t)(n) << SMC_EDGCMPA_SHIFT) -#define SMC_EDGCNTA_SHIFT (8) /* Bits: 8-15 Edge Counter A */ -#define SMC_EDGCNTA_MASK (0xff << SMC_EDGCNTA_SHIFT) -# define SMC_EDGCNTA(n) ((uint32_t)(n) << SMC_EDGCNTA_SHIFT) - -/* Capture Control B Register */ - -#define SMC_ARMB (1 << 0) /* Bit: 0 Arm B */ -#define SMC_ONESHOTB (1 << 1) /* Bit: 1 One Shot Mode B */ -#define SMC_EDGB0_SHIFT (2) /* Bits: 2-3 Edge B 0 */ -#define SMC_EDGB0_MASK (3 << SMC_EDGB0_SHIFT) -# define SMC_EDGB0(n) ((uint32_t)(n) << SMC_EDGB0_SHIFT) -# define SMC_EDGB0_DIS (0 << SMC_EDGB0_SHIFT) /* Disabled */ -# define SMC_EDGB0_FALLING (1 << SMC_EDGB0_SHIFT) /* Capture falling edges */ -# define SMC_EDGB0_RISING (2 << SMC_EDGB0_SHIFT) /* Capture rising edges */ -# define SMC_EDGB0_BOTH (3 << SMC_EDGB0_SHIFT) /* Capture any edge */ -#define SMC_EDGB1_SHIFT (4) /* Bits: 4-5 Edge B 1 */ -#define SMC_EDGB1_MASK (3 << SMC_EDGB1_SHIFT) -# define SMC_EDGB1(n) ((uint32_t)(n) << SMC_EDGB1_SHIFT) -# define SMC_EDGB1_DIS (0 << SMC_EDGB1_SHIFT) /* Disabled */ -# define SMC_EDGB1_FALLING (1 << SMC_EDGB1_SHIFT) /* Capture falling edges */ -# define SMC_EDGB1_RISING (2 << SMC_EDGB1_SHIFT) /* Capture rising edges */ -# define SMC_EDGB1_BOTH (3 << SMC_EDGB1_SHIFT) /* Capture any edge */ -#define SMC_INP_SELB (1 << 6) /* Bit: 6 Input Select B */ -#define SMC_EDGCNTB_EN (1 << 7) /* Bit: 7 Edge Counter B Enable */ -#define SMC_CFBWM_SHIFT (8) /* Bits: 8-9 Capture B FIFOs Water Mark */ -#define SMC_CFBWM_MASK (3 << SMC_CFBWM_SHIFT) -# define SMC_CFBWM(n) ((uint32_t)(n) << SMC_CFBWM_SHIFT) -# define SMC_CFBWM_0 (0 << SMC_CFBWM_SHIFT) /* Water mark level of 1 for capture B FIFOs */ -# define SMC_CFBWM_1 (1 << SMC_CFBWM_SHIFT) /* Water mark level of 2 for capture B FIFOs */ -# define SMC_CFBWM_2 (2 << SMC_CFBWM_SHIFT) /* Water mark level of 3 for capture B FIFOs */ -# define SMC_CFBWM_3 (3 << SMC_CFBWM_SHIFT) /* Water mark level of 4 for capture B FIFOs */ -#define SMC_CB0CNT_SHIFT (10) /* Bits: 10-12 Capture B0 FIFO Word Count */ -#define SMC_CB0CNT_MASK (7 << SMC_CB0CNT_SHIFT) -# define SMC_CB0CNT(n) ((uint32_t)(n) << SMC_CB0CNT_SHIFT) -# define SMC_CB0CNT_00 (0 << SMC_CB0CNT_SHIFT) /* 0 words in the Capture B0 FIFO. */ -# define SMC_CB0CNT_01 (1 << SMC_CB0CNT_SHIFT) /* 1 words in the Capture B0 FIFO. */ -# define SMC_CB0CNT_02 (2 << SMC_CB0CNT_SHIFT) /* 2 words in the Capture B0 FIFO. */ -# define SMC_CB0CNT_03 (3 << SMC_CB0CNT_SHIFT) /* 3 words in the Capture B0 FIFO. */ -# define SMC_CB0CNT_04 (4 << SMC_CB0CNT_SHIFT) /* 4 words in the Capture B0 FIFO. */ -# define SMC_CB0CNT_05 (5 << SMC_CB0CNT_SHIFT) /* 5 words in the Capture B0 FIFO. */ -# define SMC_CB0CNT_06 (6 << SMC_CB0CNT_SHIFT) /* 6 words in the Capture B0 FIFO. */ -# define SMC_CB0CNT_07 (7 << SMC_CB0CNT_SHIFT) /* 7 words in the Capture B0 FIFO. */ -#define SMC_CB1CNT_SHIFT (13) /* Bits: 13-15 Capture B1 FIFO Word Count */ -#define SMC_CB1CNT_MASK (7 << SMC_CB1CNT_SHIFT) -# define SMC_CB1CNT(n) ((uint32_t)(n) << SMC_CB1CNT_SHIFT) -# define SMC_CB1CNT_00 (0 << SMC_CB1CNT_SHIFT) /* 0 words in the Capture B1 FIFO. */ -# define SMC_CB1CNT_01 (1 << SMC_CB1CNT_SHIFT) /* 1 words in the Capture B1 FIFO. */ -# define SMC_CB1CNT_02 (2 << SMC_CB1CNT_SHIFT) /* 2 words in the Capture B1 FIFO. */ -# define SMC_CB1CNT_03 (3 << SMC_CB1CNT_SHIFT) /* 3 words in the Capture B1 FIFO. */ -# define SMC_CB1CNT_04 (4 << SMC_CB1CNT_SHIFT) /* 4 words in the Capture B1 FIFO. */ -# define SMC_CB1CNT_05 (5 << SMC_CB1CNT_SHIFT) /* 5 words in the Capture B1 FIFO. */ -# define SMC_CB1CNT_06 (6 << SMC_CB1CNT_SHIFT) /* 6 words in the Capture B1 FIFO. */ -# define SMC_CB1CNT_07 (7 << SMC_CB1CNT_SHIFT) /* 7 words in the Capture B1 FIFO. */ - -/* Capture Compare B Register */ - -#define SMC_EDGCMPB_SHIFT (0) /* Bits: 0-7 Edge Compare B */ -#define SMC_EDGCMPB_MASK (0xff << SMC_EDGCMPB_SHIFT) -# define SMC_EDGCMPB(n) ((uint32_t)(n) << SMC_EDGCMPB_SHIFT) -#define SMC_EDGCNTB_SHIFT (8) /* Bits: 8-15 Edge Counter B */ -#define SMC_EDGCNTB_MASK (0xff << SMC_EDGCNTB_SHIFT) -# define SMC_EDGCNTB(n) ((uint32_t)(n) << SMC_EDGCNTB_SHIFT) - -/* Capture Control X Register */ - -#define SMC_ARMX (1 << 0) /* Bit: 0 Arm X */ -#define SMC_ONESHOTX (1 << 1) /* Bit: 1 One Shot Mode Aux */ -#define SMC_EDGX0_SHIFT (2) /* Bits: 2-3 Edge X 0 */ -#define SMC_EDGX0_MASK (3 << SMC_EDGX0_SHIFT) -# define SMC_EDGX0(n) ((uint32_t)(n) << SMC_EDGX0_SHIFT) -# define SMC_EDGX0_DIS (0 << SMC_EDGX0_SHIFT) /* Disabled */ -# define SMC_EDGX0_FALLING (1 << SMC_EDGX0_SHIFT) /* Capture falling edges */ -# define SMC_EDGX0_RISING (2 << SMC_EDGX0_SHIFT) /* Capture rising edges */ -# define SMC_EDGX0_BOTH (3 << SMC_EDGX0_SHIFT) /* Capture any edge */ -#define SMC_EDGX1_SHIFT (4) /* Bits: 4-5 Edge X 1 */ -#define SMC_EDGX1_MASK (3 << SMC_EDGX1_SHIFT) -# define SMC_EDGX1(n) ((uint32_t)(n) << SMC_EDGX1_SHIFT) -# define SMC_EDGX1_DIS (0 << SMC_EDGX1_SHIFT) /* Disabled */ -# define SMC_EDGX1_FALLING (1 << SMC_EDGX1_SHIFT) /* Capture falling edges */ -# define SMC_EDGX1_RISING (2 << SMC_EDGX1_SHIFT) /* Capture rising edges */ -# define SMC_EDGX1_BOTH (3 << SMC_EDGX1_SHIFT) /* Capture any edge */ -#define SMC_INP_SELX (1 << 6) /* Bit: 6 Input Select X */ -#define SMC_EDGCNTX_EN (1 << 7) /* Bit: 7 Edge Counter X Enable */ -#define SMC_CFXWM_SHIFT (8) /* Bits: 8-9 Capture X FIFOs Water Mark */ -#define SMC_CFXWM_MASK (3 << SMC_CFXWM_SHIFT) -# define SMC_CFXWM(n) ((uint32_t)(n) << SMC_CFXWM_SHIFT) -# define SMC_CFXWM_1 (0 << SMC_CFXWM_SHIFT) /* Water mark level of 1 for capture X FIFOs */ -# define SMC_CFXWM_2 (1 << SMC_CFXWM_SHIFT) /* Water mark level of 2 for capture X FIFOs */ -# define SMC_CFXWM_3 (2 << SMC_CFXWM_SHIFT) /* Water mark level of 3 for capture X FIFOs */ -# define SMC_CFXWM_4 (3 << SMC_CFXWM_SHIFT) /* Water mark level of 4 for capture X FIFOs */ -#define SMC_CX0CNT_SHIFT (10) /* Bits: 10-12 Capture X0 FIFO Word Count */ -#define SMC_CX0CNT_MASK (7 << SMC_CX0CNT_SHIFT) -# define SMC_CX0CNT(n) ((uint32_t)(n) << SMC_CX0CNT_SHIFT) -# define SMC_CX0CNT_00 (0 << SMC_CX0CNT_SHIFT) /* 0 words in the Capture X0 FIFO. */ -# define SMC_CX0CNT_01 (1 << SMC_CX0CNT_SHIFT) /* 1 word in the Capture X0 FIFO. */ -# define SMC_CX0CNT_02 (2 << SMC_CX0CNT_SHIFT) /* 2 words in the Capture X0 FIFO. */ -# define SMC_CX0CNT_03 (3 << SMC_CX0CNT_SHIFT) /* 3 words in the Capture X0 FIFO. */ -# define SMC_CX0CNT_04 (4 << SMC_CX0CNT_SHIFT) /* 4 words in the Capture X0 FIFO. */ -# define SMC_CX0CNT_05 (5 << SMC_CX0CNT_SHIFT) /* 5 words in the Capture X0 FIFO. */ -# define SMC_CX0CNT_06 (6 << SMC_CX0CNT_SHIFT) /* 6 words in the Capture X0 FIFO. */ -# define SMC_CX0CNT_07 (7 << SMC_CX0CNT_SHIFT) /* 7 words in the Capture X0 FIFO. */ -#define SMC_CX1CNT_SHIFT (13) /* Bits: 13-15 Capture X1 FIFO Word Count */ -#define SMC_CX1CNT_MASK (7 << SMC_CX1CNT_SHIFT) -# define SMC_CX1CNT(n) ((uint32_t)(n) << SMC_CX1CNT_SHIFT) -# define SMC_CX1CNT_00 (0 << SMC_CX1CNT_SHIFT) /* 0 words in the Capture X1 FIFO. */ -# define SMC_CX1CNT_01 (1 << SMC_CX1CNT_SHIFT) /* 1 word in the Capture X1 FIFO. */ -# define SMC_CX1CNT_02 (2 << SMC_CX1CNT_SHIFT) /* 2 words in the Capture X1 FIFO. */ -# define SMC_CX1CNT_03 (3 << SMC_CX1CNT_SHIFT) /* 3 words in the Capture X1 FIFO. */ -# define SMC_CX1CNT_04 (4 << SMC_CX1CNT_SHIFT) /* 4 words in the Capture X1 FIFO. */ -# define SMC_CX1CNT_05 (5 << SMC_CX1CNT_SHIFT) /* 5 words in the Capture X1 FIFO. */ -# define SMC_CX1CNT_06 (6 << SMC_CX1CNT_SHIFT) /* 6 words in the Capture X1 FIFO. */ -# define SMC_CX1CNT_07 (7 << SMC_CX1CNT_SHIFT) /* 7 words in the Capture X1 FIFO. */ - -/* Capture Compare X Register */ - -#define SMC_EDGCMPX_SHIFT (0) /* Bits: 0-7 Edge Compare X */ -#define SMC_EDGCMPX_MASK (0xff << SMC_EDGCMPX_SHIFT) -# define SMC_EDGCMPX(n) ((uint32_t)(n) << SMC_EDGCMPX_SHIFT) -#define SMC_EDGCNTX_SHIFT (8) /* Bits: 8-15 Edge Counter X */ -#define SMC_EDGCNTX_MASK (0xff << SMC_EDGCNTX_SHIFT) -# define SMC_EDGCNTX(n) ((uint32_t)(n) << SMC_EDGCNTX_SHIFT) - -/* Capture Value 0 Cycle Register */ - -#define SMC_CVAL0CYC_SHIFT (0) /* Bits: 0-3 CVAL0CYC */ -#define SMC_CVAL0CYC_MASK (0xf << SMC_CVAL0CYC_SHIFT) - /* Bits: 4-15 Reserved */ - -/* Capture Value 1 Cycle Register */ - -#define SMC_CVAL1CYC_SHIFT (0) /* Bits: 0-3 CVAL1CYC */ -#define SMC_CVAL1CYC_MASK (0xf << SMC_CVAL1CYC_SHIFT) - /* Bits: 4-15 Reserved */ - -/* Capture Value 2 Cycle Register */ - -#define SMC_CVAL2CYC_SHIFT (0) /* Bits: 0-3 CVAL2CYC */ -#define SMC_CVAL2CYC_MASK (0xf << SMC_CVAL2CYC_SHIFT) - /* Bits: 4-15 Reserved */ - -/* Capture Value 3 Cycle Register */ - -#define SMC_CVAL3CYC_SHIFT (0) /* Bits: 0-3 CVAL3CYC */ -#define SMC_CVAL3CYC_MASK (0xf << SMC_CVAL3CYC_SHIFT) - /* Bits: 4-15 Reserved */ - -/* Capture Value 4 Cycle Register */ - -#define SMC_CVAL4CYC_SHIFT (0) /* Bits: 0-3 CVAL4CYC */ -#define SMC_CVAL4CYC_MASK (0xf << SMC_CVAL4CYC_SHIFT) - /* Bits: 4-15 Reserved */ - -/* Capture Value 5 Cycle Register */ - -#define SMC_CVAL5CYC_SHIFT (0) /* Bits: 0-3 CVAL5CYC */ -#define SMC_CVAL5CYC_MASK (0xf << SMC_CVAL5CYC_SHIFT) - /* Bits: 4-15 Reserved */ - -/* Output Enable Register */ - -#define OUTEN_PWMX_EN_SHIFT (0) /* Bits: 0-3 PWM_X Output Enables */ -#define OUTEN_PWMX_EN_MASK (0xf << OUTEN_PWMX_EN_SHIFT) -# define OUTEN_PWMX_EN(n) ((uint32_t)(n) << OUTEN_PWMX_EN_SHIFT) -# define OUTEN_PWMX_EN_ALL_DIS (0 << OUTEN_PWMX_EN_SHIFT) /* All disabled */ -# define OUTEN_PWMX_EN_SM0 (1 << OUTEN_PWMX_EN_SHIFT) /* Enable the PWM_X outputs of submodules 0 */ -# define OUTEN_PWMX_EN_SM1 (2 << OUTEN_PWMX_EN_SHIFT) /* Enable the PWM_X outputs of submodules 1 */ -# define OUTEN_PWMX_EN_SM2 (4 << OUTEN_PWMX_EN_SHIFT) /* Enable the PWM_X outputs of submodules 2 */ -# define OUTEN_PWMX_EN_SM3 (8 << OUTEN_PWMX_EN_SHIFT) /* Enable the PWM_X outputs of submodules 3 */ -# define OUTEN_PWMX_EN_ALL (0xf << OUTEN_PWMX_EN_SHIFT) /* All enabled */ -#define OUTEN_PWMB_EN_SHIFT (4) /* Bits: 4-7 PWM_B Output Enables */ -#define OUTEN_PWMB_EN_MASK (0xf << OUTEN_PWMB_EN_SHIFT) -# define OUTEN_PWMB_EN(n) ((uint32_t)(n) << OUTEN_PWMB_EN_SHIFT) -# define OUTEN_PWMB_EN_ALL_DIS (0 << OUTEN_PWMB_EN_SHIFT) /* All disabled */ -# define OUTEN_PWMB_EN_SM0 (1 << OUTEN_PWMB_EN_SHIFT) /* Enable the PWM_B outputs of submodules 0 */ -# define OUTEN_PWMB_EN_SM1 (2 << OUTEN_PWMB_EN_SHIFT) /* Enable the PWM_B outputs of submodules 1 */ -# define OUTEN_PWMB_EN_SM2 (4 << OUTEN_PWMB_EN_SHIFT) /* Enable the PWM_B outputs of submodules 2 */ -# define OUTEN_PWMB_EN_SM3 (8 << OUTEN_PWMB_EN_SHIFT) /* Enable the PWM_B outputs of submodules 3 */ -# define OUTEN_PWMB_EN_ALL (0xf << OUTEN_PWMB_EN_SHIFT) /* All enabled */ -#define OUTEN_PWMA_EN_SHIFT (8) /* Bits: 8-11 PWM_A Output Enables */ -#define OUTEN_PWMA_EN_MASK (0xf << OUTEN_PWMA_EN_SHIFT) -# define OUTEN_PWMA_EN(n) ((uint32_t)(n) << OUTEN_PWMA_EN_SHIFT) -# define OUTEN_PWMA_EN_ALL_DIS (0 << OUTEN_PWMA_EN_SHIFT) /* All disabled */ -# define OUTEN_PWMA_EN_SM0 (1 << OUTEN_PWMA_EN_SHIFT) /* Enable the PWM_A outputs of submodules 0 */ -# define OUTEN_PWMA_EN_SM1 (2 << OUTEN_PWMA_EN_SHIFT) /* Enable the PWM_A outputs of submodules 1 */ -# define OUTEN_PWMA_EN_SM2 (4 << OUTEN_PWMA_EN_SHIFT) /* Enable the PWM_A outputs of submodules 2 */ -# define OUTEN_PWMA_EN_SM3 (8 << OUTEN_PWMA_EN_SHIFT) /* Enable the PWM_A outputs of submodules 3 */ -# define OUTEN_PWMA_EN_ALL (0xf << OUTEN_PWMA_EN_SHIFT) /* All enabled */ - /* Bits: 12-15 Reserved */ - -/* Mask Register */ - -#define MASK_MASKX_SHIFT (0) /* Bits: 0-3 PWM_X Masks */ -#define MASK_MASKX_MASK (0xf << MASK_MASKX_SHIFT) -# define MASK_MASKX(n) ((uint32_t)(n) << MASK_MASKX_SHIFT) -# define MASK_MASKX_SM0 (1 << MASK_MASKX_SHIFT) /* Mask the PWM_X outputs of submodules 0 (forces output to 0) */ -# define MASK_MASKX_SM1 (2 << MASK_MASKX_SHIFT) /* Mask the PWM_X outputs of submodules 1 (forces output to 0) */ -# define MASK_MASKX_SM2 (4 << MASK_MASKX_SHIFT) /* Mask the PWM_X outputs of submodules 2 (forces output to 0) */ -# define MASK_MASKX_SM3 (8 << MASK_MASKX_SHIFT) /* Mask the PWM_X outputs of submodules 3 (forces output to 0) */ -#define MASK_MASKB_SHIFT (4) /* Bits: 4-7 PWM_B Masks */ -#define MASK_MASKB_MASK (0xf << MASK_MASKB_SHIFT) -# define MASK_MASKB(n) ((uint32_t)(n) << MASK_MASKB_SHIFT) -# define MASK_MASKB_SM0 (1 << MASK_MASKB_SHIFT) /* Mask the PWM_B outputs of submodules 0 (forces output to 0) */ -# define MASK_MASKB_SM1 (2 << MASK_MASKB_SHIFT) /* Mask the PWM_B outputs of submodules 1 (forces output to 0) */ -# define MASK_MASKB_SM2 (4 << MASK_MASKB_SHIFT) /* Mask the PWM_B outputs of submodules 2 (forces output to 0) */ -# define MASK_MASKB_SM3 (8 << MASK_MASKB_SHIFT) /* Mask the PWM_B outputs of submodules 3 (forces output to 0) */ -#define MASK_MASKA_SHIFT (8) /* Bits: 8-11 PWM_A Masks */ -#define MASK_MASKA_MASK (0xf << MASK_MASKB_SHIFT) -# define MASK_MASKA(n) ((uint32_t)(n) << MASK_MASKA_SHIFT) -# define MASK_MASKA_SM0 (1 << MASK_MASKA_SHIFT) /* Mask the PWM_A outputs of submodules 0 (forces output to 0) */ -# define MASK_MASKA_SM1 (2 << MASK_MASKA_SHIFT) /* Mask the PWM_A outputs of submodules 1 (forces output to 0) */ -# define MASK_MASKA_SM2 (4 << MASK_MASKA_SHIFT) /* Mask the PWM_A outputs of submodules 2 (forces output to 0) */ -# define MASK_MASKA_SM3 (8 << MASK_MASKA_SHIFT) /* Mask the PWM_A outputs of submodules 3 (forces output to 0) */ -#define MASK_UPDATE_MASK_SHIFT (12) /* Bits: 12-15 Update Mask Bits Immediately */ -#define MASK_UPDATE_MASK_MASK (0xf << MASK_UPDATE_MASK_SHIFT) -# define MASK_UPDATE_MASK(n) ((uint32_t)(n) << MASK_UPDATE_MASK_SHIFT) -# define MASK_UPDATE_MASK_SM0 (1 << MASK_UPDATE_MASK_SHIFT) /* Immediate update operation on PWM_X output of submodules 0 */ -# define MASK_UPDATE_MASK_SM1 (2 << MASK_UPDATE_MASK_SHIFT) /* Immediate update operation on PWM_X output of submodules 1 */ -# define MASK_UPDATE_MASK_SM2 (4 << MASK_UPDATE_MASK_SHIFT) /* Immediate update operation on PWM_X output of submodules 2 */ -# define MASK_UPDATE_MASK_SM3 (8 << MASK_UPDATE_MASK_SHIFT) /* Immediate update operation on PWM_X output of submodules 3 */ - -/* Software Controlled Output Register */ - -#define SWCOUT_SM0OUT45 (1 << 0) /* Bit: 0 Submodule 0 Software Controlled Output 45 */ -#define SWCOUT_SM0OUT23 (1 << 1) /* Bit: 1 Submodule 0 Software Controlled Output 23 */ -#define SWCOUT_SM1OUT45 (1 << 2) /* Bit: 2 Submodule 1 Software Controlled Output 45 */ -#define SWCOUT_SM1OUT23 (1 << 3) /* Bit: 3 Submodule 1 Software Controlled Output 23 */ -#define SWCOUT_SM2OUT45 (1 << 4) /* Bit: 4 Submodule 2 Software Controlled Output 45 */ -#define SWCOUT_SM2OUT23 (1 << 5) /* Bit: 5 Submodule 2 Software Controlled Output 23 */ -#define SWCOUT_SM3OUT45 (1 << 6) /* Bit: 6 Submodule 3 Software Controlled Output 45 */ -#define SWCOUT_SM3OUT23 (1 << 7) /* Bit: 7 Submodule 3 Software Controlled Output 23 */ - /* Bits: 8-15 Reserved */ - -/* PWM Source Select Register */ - -/* Register Bit Definitions *********************************************************/ - -#define DTSRCSEL_SM0SEL45_SHIFT (0) /* Bits: 0-1 Submodule 0 PWM45 Control Select */ -#define DTSRCSEL_SM0SEL45_MASK (3 << DTSRCSEL_SM0SEL45_SHIFT) -# define DTSRCSEL_SM0SEL45(n) ((uint32_t)(n) << DTSRCSEL_SM0SEL45_SHIFT) -# define DTSRCSEL_SM0SEL45_NORM (0 << DTSRCSEL_SM0SEL45_SHIFT) /* Generated SM0PWM45 signal is used by the deadtime logic. */ -# define DTSRCSEL_SM0SEL45_INVERT (1 << DTSRCSEL_SM0SEL45_SHIFT) /* Inverted generated SM0PWM45 signal is used by the deadtime logic. */ -# define DTSRCSEL_SM0SEL45_SWCOUT (2 << DTSRCSEL_SM0SEL45_SHIFT) /* SWCOUT[SM0OUT45] is used by the deadtime logic. */ -# define DTSRCSEL_SM0SEL45_PWM0_EXTB (3 << DTSRCSEL_SM0SEL45_SHIFT) /* PWM0_EXTB signal is used by the deadtime logic. */ -#define DTSRCSEL_SM0SEL23_SHIFT (2) /* Bits: 2-3 Submodule 0 PWM23 Control Select */ -#define DTSRCSEL_SM0SEL23_MASK (3 << DTSRCSEL_SM0SEL23_SHIFT) -# define DTSRCSEL_SM0SEL23(n) ((uint32_t)(n) << DTSRCSEL_SM0SEL23_SHIFT) -# define DTSRCSEL_SM0SEL23_NORM (0 << DTSRCSEL_SM0SEL23_SHIFT) /* Generated SM0PWM23 signal is used by the deadtime logic. */ -# define DTSRCSEL_SM0SEL23_INVERT (1 << DTSRCSEL_SM0SEL23_SHIFT) /* Inverted generated SM0PWM23 signal is used by the deadtime logic. */ -# define DTSRCSEL_SM0SEL23_SWCOUT (2 << DTSRCSEL_SM0SEL23_SHIFT) /* SWCOUT[SM0OUT23] is used by the deadtime logic. */ -# define DTSRCSEL_SM0SEL23_PWM0_EXTA (3 << DTSRCSEL_SM0SEL23_SHIFT) /* PWM0_EXTA signal is used by the deadtime logic. */ -#define DTSRCSEL_SM1SEL45_SHIFT (4) /* Bits: 4-5 Submodule 1 PWM45 Control Select */ -#define DTSRCSEL_SM1SEL45_MASK (3 << DTSRCSEL_SM1SEL45_SHIFT) -# define DTSRCSEL_SM1SEL45(n) ((uint32_t)(n) << DTSRCSEL_SM1SEL45_SHIFT) -# define DTSRCSEL_SM1SEL45_NORM (0 << DTSRCSEL_SM1SEL45_SHIFT) /* Generated SM1PWM45 signal is used by the deadtime logic. */ -# define DTSRCSEL_SM1SEL45_INVERT (1 << DTSRCSEL_SM1SEL45_SHIFT) /* Inverted generated SM1PWM45 signal is used by the deadtime logic. */ -# define DTSRCSEL_SM1SEL45_SWCOUT (2 << DTSRCSEL_SM1SEL45_SHIFT) /* SWCOUT[SM1OUT45] is used by the deadtime logic. */ -# define DTSRCSEL_SM1SEL45_PWM1_EXTB (3 << DTSRCSEL_SM1SEL45_SHIFT) /* PWM1_EXTB signal is used by the deadtime logic. */ -#define DTSRCSEL_SM1SEL23_SHIFT (6) /* Bits: 6-7 Submodule 1 PWM23 Control Select */ -#define DTSRCSEL_SM1SEL23_MASK (3 << DTSRCSEL_SM1SEL23_SHIFT) -# define DTSRCSEL_SM1SEL23(n) ((uint32_t)(n) << DTSRCSEL_SM1SEL23_SHIFT) -# define DTSRCSEL_SM1SEL23_NORM (0 << DTSRCSEL_SM1SEL23_SHIFT) /* Generated SM1PWM23 signal is used by the deadtime logic. */ -# define DTSRCSEL_SM1SEL23_INVERT (1 << DTSRCSEL_SM1SEL23_SHIFT) /* Inverted generated SM1PWM23 signal is used by the deadtime logic. */ -# define DTSRCSEL_SM1SEL23_SWCOUT (2 << DTSRCSEL_SM1SEL23_SHIFT) /* SWCOUT[SM1OUT23] is used by the deadtime logic. */ -# define DTSRCSEL_SM1SEL23_PWM1_EXTA (3 << DTSRCSEL_SM1SEL23_SHIFT) /* PWM1_EXTA signal is used by the deadtime logic */ -#define DTSRCSEL_SM2SEL45_SHIFT (8) /* Bits: 8-9 Submodule 2 PWM45 Control Select */ -#define DTSRCSEL_SM2SEL45_MASK (3 << DTSRCSEL_SM2SEL45_SHIFT) -# define DTSRCSEL_SM2SEL45(n) ((uint32_t)(n) << DTSRCSEL_SM2SEL45_SHIFT) -# define DTSRCSEL_SM2SEL45_NORM (0 << DTSRCSEL_SM2SEL45_SHIFT) /* Generated SM2PWM45 signal is used by the deadtime logic. */ -# define DTSRCSEL_SM2SEL45_INVERT (1 << DTSRCSEL_SM2SEL45_SHIFT) /* Inverted generated SM2PWM45 signal is used by the deadtime logic. */ -# define DTSRCSEL_SM2SEL45_SWCOUT (2 << DTSRCSEL_SM2SEL45_SHIFT) /* SWCOUT[SM2OUT45] is used by the deadtime logic. */ -# define DTSRCSEL_SM2SEL45_PWM2_EXTB (3 << DTSRCSEL_SM2SEL45_SHIFT) /* PWM2_EXTB signal is used by the deadtime logic. */ -#define DTSRCSEL_SM2SEL23_SHIFT (10) /* Bits: 10-11 Submodule 2 PWM23 Control Select */ -#define DTSRCSEL_SM2SEL23_MASK (3 << DTSRCSEL_SM2SEL23_SHIFT) -# define DTSRCSEL_SM2SEL23(n) ((uint32_t)(n) << DTSRCSEL_SM2SEL23_SHIFT) -# define DTSRCSEL_SM2SEL23_NORM (0 << DTSRCSEL_SM2SEL23_SHIFT) /* Generated SM2PWM23 signal is used by the deadtime logic. */ -# define DTSRCSEL_SM2SEL23_INVERT (1 << DTSRCSEL_SM2SEL23_SHIFT) /* Inverted generated SM2PWM23 signal is used by the deadtime logic. */ -# define DTSRCSEL_SM2SEL23_SWCOUT (2 << DTSRCSEL_SM2SEL23_SHIFT) /* SWCOUT[SM2OUT23] is used by the deadtime logic. */ -# define DTSRCSEL_SM2SEL23_PWM2_EXTA (3 << DTSRCSEL_SM2SEL23_SHIFT) /* PWM2_EXTA signal is used by the deadtime logic */ -#define DTSRCSEL_SM3SEL45_SHIFT (12) /* Bits: 12-13 Submodule 3 PWM45 Control Select */ -#define DTSRCSEL_SM3SEL45_MASK (3 << DTSRCSEL_SM3SEL45_SHIFT) -# define DTSRCSEL_SM3SEL45(n) ((uint32_t)(n) << DTSRCSEL_SM3SEL45_SHIFT) -# define DTSRCSEL_SM3SEL45_NORM (0 << DTSRCSEL_SM3SEL45_SHIFT) /* Generated SM3PWM45 signal is used by the deadtime logic. */ -# define DTSRCSEL_SM3SEL45_INVERT (1 << DTSRCSEL_SM3SEL45_SHIFT) /* Inverted generated SM3PWM45 signal is used by the deadtime logic. */ -# define DTSRCSEL_SM3SEL45_SWCOUT (2 << DTSRCSEL_SM3SEL45_SHIFT) /* SWCOUT[SM3OUT45] is used by the deadtime logic. */ -# define DTSRCSEL_SM3SEL45_PWM3_EXTB (3 << DTSRCSEL_SM3SEL45_SHIFT) /* PWM3_EXTB signal is used by the deadtime logic. */ -#define DTSRCSEL_SM3SEL23_SHIFT (14) /* Bits: 14-15 Submodule 3 PWM23 Control Select */ -#define DTSRCSEL_SM3SEL23_MASK (3 << DTSRCSEL_SM3SEL23_SHIFT) -# define DTSRCSEL_SM3SEL23(n) ((uint32_t)(n) << DTSRCSEL_SM3SEL23_SHIFT) -# define DTSRCSEL_SM3SEL23_NORM (0 << DTSRCSEL_SM3SEL23_SHIFT) /* Generated SM3PWM23 signal is used by the deadtime logic. */ -# define DTSRCSEL_SM3SEL23_INVERT (1 << DTSRCSEL_SM3SEL23_SHIFT) /* Inverted generated SM3PWM23 signal is used by the deadtime logic. */ -# define DTSRCSEL_SM3SEL23_SWCOUT (2 << DTSRCSEL_SM3SEL23_SHIFT) /* SWCOUT[SM3OUT23] is used by the deadtime logic. */ -# define DTSRCSEL_SM3SEL23_PWM3_EXTA (3 << DTSRCSEL_SM3SEL23_SHIFT) /* PWM3_EXTA signal is used by the deadtime logic. */ - -/* Master Control Register */ - -#define MCTRL_LDOK_SHIFT (0) /* Bits: 0-3 Load Okay */ -#define MCTRL_LDOK_MASK (15 << MCTRL_LDOK_SHIFT) -# define MCTRL_LDOK(n) ((uint32_t)(n) << MCTRL_LDOK_SHIFT) -# define MCTRL_LDOK_SM0 (1 << MCTRL_LDOK_SHIFT) /* Load prescaler, modulus, and PWM values of submodule 0 */ -# define MCTRL_LDOK_SM1 (2 << MCTRL_LDOK_SHIFT) /* Load prescaler, modulus, and PWM values of submodule 1 */ -# define MCTRL_LDOK_SM2 (4 << MCTRL_LDOK_SHIFT) /* Load prescaler, modulus, and PWM values of submodule 2 */ -# define MCTRL_LDOK_SM3 (8 << MCTRL_LDOK_SHIFT) /* Load prescaler, modulus, and PWM values of submodule 3 */ -#define MCTRL_CLDOK_SHIFT (4) /* Bits: 4-7 Clear Load Okay */ -#define MCTRL_CLDOK_MASK (15 << MCTRL_CLDOK_SHIFT) -# define MCTRL_CLDOK(n) ((uint32_t)(n) << MCTRL_CLDOK_SHIFT) -# define MCTRL_CLDOK_SM0 (1 << MCTRL_CLDOK_SHIFT) /* Clear Load Okay of submodule 0 */ -# define MCTRL_CLDOK_SM1 (2 << MCTRL_CLDOK_SHIFT) /* Clear Load Okay of submodule 1 */ -# define MCTRL_CLDOK_SM2 (4 << MCTRL_CLDOK_SHIFT) /* Clear Load Okay of submodule 2 */ -# define MCTRL_CLDOK_SM3 (8 << MCTRL_CLDOK_SHIFT) /* Clear Load Okay of submodule 3 */ -#define MCTRL_RUN_SHIFT (8) /* Bits: 8-11 Run */ -#define MCTRL_RUN_MASK (15 << MCTRL_RUN_SHIFT) -# define MCTRL_RUN(n) ((uint32_t)(n) << MCTRL_RUN_SHIFT) -# define MCTRL_RUN_SM0 (1 << MCTRL_RUN_SHIFT) /* Enable PWM generator of submodules 0 */ -# define MCTRL_RUN_SM1 (2 << MCTRL_RUN_SHIFT) /* Enable PWM generator of submodules 1 */ -# define MCTRL_RUN_SM2 (4 << MCTRL_RUN_SHIFT) /* Enable PWM generator of submodules 2 */ -# define MCTRL_RUN_SM3 (8 << MCTRL_RUN_SHIFT) /* Enable PWM generator of submodules 3 */ -#define MCTRL_IPOL_SHIFT (12) /* Bits: 12-15 Current Polarity */ -#define MCTRL_IPOL_MASK (15 << MCTRL_IPOL_SHIFT) -# define MCTRL_IPOL(n) ((uint32_t)(n) << MCTRL_IPOL_SHIFT) -# define MCTRL_IPOL_SM0 (1 << MCTRL_IPOL_SHIFT) /* PWM45 is used to generate complementary PWM pair in submodule 0. */ -# define MCTRL_IPOL_SM1 (2 << MCTRL_IPOL_SHIFT) /* PWM45 is used to generate complementary PWM pair in submodule 1. */ -# define MCTRL_IPOL_SM2 (4 << MCTRL_IPOL_SHIFT) /* PWM45 is used to generate complementary PWM pair in submodule 2. */ -# define MCTRL_IPOL_SM3 (8 << MCTRL_IPOL_SHIFT) /* PWM45 is used to generate complementary PWM pair in submodule 3. */ - -/* Master Control 2 Register */ - -/* Register Bit Definitions *********************************************************/ - -#define MCTRL2_MONPLL_SHIFT (0) /* Bits: 0-1 Monitor PLL State */ -#define MCTRL2_MONPLL_MASK (3 << MCTRL2_MONPLL_SHIFT) -# define MCTRL2_MONPLL(n) ((uint32_t)(n) << MCTRL2_MONPLL_SHIFT) -# define MCTRL2_MONPLL_NOT_LOCKED (0 << MCTRL2_MONPLL_SHIFT) /* Not locked. Do not monitor PLL operation. */ -# define MCTRL2_MONPLL_NOT_LOCKED_NONITOR (1 << MCTRL2_MONPLL_SHIFT) /* Not locked. Monitor PLL operation. */ -# define MCTRL2_MONPLL_LOCKED (2 << MCTRL2_MONPLL_SHIFT) /* Locked. Do not monitor PLL operation. */ -# define MCTRL2_MONPLL_LOCKED_NONITOR (3 << MCTRL2_MONPLL_SHIFT) /* Locked. Monitor PLL operation */ - -/* Fault Control Register */ - -#define FCTRL_FIE_SHIFT (0) /* Bits: 0-3 Fault Interrupt Enables */ -#define FCTRL_FIE_MASK (15 << FCTRL_FIE_SHIFT) -# define FCTRL_FIE(n) ((uint32_t)(n) << FCTRL_FIE_SHIFT) -# define FCTRL_FIE_ALL_DIS (0 << FCTRL_FIE_SHIFT) /* All Normal mode. PWM outputs disabled by this fault are not enabled */ -# define FCTRL_FIE_FAULT0 (1 << FCTRL_FIE_SHIFT) /* FAULT0 Safe mode. PWM outputs disabled by this fault */ -# define FCTRL_FIE_FAULT1 (2 << FCTRL_FIE_SHIFT) /* FAULT1 Safe mode. PWM outputs disabled by this fault */ -# define FCTRL_FIE_FAULT2 (4 << FCTRL_FIE_SHIFT) /* FAULT2 Safe mode. PWM outputs disabled by this fault */ -# define FCTRL_FIE_FAULT3 (8 << FCTRL_FIE_SHIFT) /* FAULT3 Safe mode. PWM outputs disabled by this fault */ -#define FCTRL0_FSAFE_SHIFT (4) /* Bits: 4-7 Fault Safety Mode */ -#define FCTRL0_FSAFE_MASK (15 << FCTRL0_FSAFE_SHIFT) -# define FCTRL0_FSAFE(n) ((uint32_t)(n) << FCTRL0_FSAFE_SHIFT) -# define FCTRL0_FSAFE_ALL_DIS (0 << FCTRL0_FSAFE_SHIFT) /* All FAULT CPU interrupt requests disabled */ -# define FCTRL0_FSAFE_FAULT0 (1 << FCTRL0_FSAFE_SHIFT) /* FAULT0 CPU interrupt requests enabled */ -# define FCTRL0_FSAFE_FAULT1 (2 << FCTRL0_FSAFE_SHIFT) /* FAULT1 CPU interrupt requests enabled */ -# define FCTRL0_FSAFE_FAULT2 (4 << FCTRL0_FSAFE_SHIFT) /* FAULT2 CPU interrupt requests enabled */ -# define FCTRL0_FSAFE_FAULT3 (8 << FCTRL0_FSAFE_SHIFT) /* FAULT3 CPU interrupt requests enabled */ -#define FCTRL0_FAUTO_SHIFT (8) /* Bits: 8-11 Automatic Fault Clearing */ -#define FCTRL0_FAUTO_MASK (15 << FCTRL0_FAUTO_SHIFT) -# define FCTRL0_FAUTO(n) ((uint32_t)(n) << FCTRL0_FAUTO_SHIFT) -# define FCTRL0_FAUTO_ALL_MANUAL (0 << FCTRL0_FAUTO_SHIFT) /* All Manual fault clearing */ -# define FCTRL0_FAUTO_FAULT0 (1 << FCTRL0_FAUTO_SHIFT) /* FAULT0 Automatic fault clearing. */ -# define FCTRL0_FAUTO_FAULT1 (2 << FCTRL0_FAUTO_SHIFT) /* FAULT1 Automatic fault clearing. */ -# define FCTRL0_FAUTO_FAULT2 (4 << FCTRL0_FAUTO_SHIFT) /* FAULT2 Automatic fault clearing. */ -# define FCTRL0_FAUTO_FAULT3 (8 << FCTRL0_FAUTO_SHIFT) /* FAULT3 Automatic fault clearing. */ -#define FCTRL0_FLVL_SHIFT (12) /* Bits: 12-15 Fault Level */ -#define FCTRL0_FLVL_MASK (15 << FCTRL0_FLVL_SHIFT) -# define FCTRL0_FLVL(n) ((uint32_t)(n) << FCTRL0_FLVL_SHIFT) -# define FCTRL0_FLVL_ALL_FAULT_LOW (0 << FCTRL0_FLVL_SHIFT) /* A logic 0 on the ALL fault input indicates a fault condition */ -# define FCTRL0_FLVL_FAULT0 (1 << FCTRL0_FLVL_SHIFT) /* A logic 1 on the FAULT0 input indicates a fault condition */ -# define FCTRL0_FLVL_FAULT1 (2 << FCTRL0_FLVL_SHIFT) /* A logic 1 on the FAULT1 input indicates a fault condition */ -# define FCTRL0_FLVL_FAULT2 (4 << FCTRL0_FLVL_SHIFT) /* A logic 1 on the FAULT2 input indicates a fault condition */ -# define FCTRL0_FLVL_FAULT3 (8 << FCTRL0_FLVL_SHIFT) /* A logic 1 on the FAULT3 input indicates a fault condition */ - -/* Fault Status Register */ - -#define FSTS_FFLAG_SHIFT (0) /* Bits: 0-3 Fault Flags */ -#define FSTS_FFLAG_MASK (15 << FSTS_FFLAG_SHIFT) -# define FSTS_FFLAG(n) ((uint32_t)(n) << FSTS_FFLAG_SHIFT) -# define FSTS_FFLAG_ALL_NO_FAULT (0 << FSTS_FFLAG_SHIFT) /* No fault on the ALL of the FAULT pins */ -# define FSTS_FFLAG_FAULT0 (1 << FSTS_FFLAG_SHIFT) /* Fault on the FAULT0 pin */ -# define FSTS_FFLAG_FAULT1 (2 << FSTS_FFLAG_SHIFT) /* Fault on the FAULT1 pin */ -# define FSTS_FFLAG_FAULT2 (4 << FSTS_FFLAG_SHIFT) /* Fault on the FAULT2 pin */ -# define FSTS_FFLAG_FAULT3 (8 << FSTS_FFLAG_SHIFT) /* Fault on the FAULT3 pin */ -#define FSTS_FFULL_SHIFT (4) /* Bits: 4-7 Full Cycle */ -#define FSTS_FFULL_MASK (15 << FSTS_FFULL_SHIFT) -# define FSTS_FFULL(n) ((uint32_t)(n) << FSTS_FFULL_SHIFT) -# define FSTS_FFULL_ALL_NOT_REENABLED (0 << FSTS_FFULL_SHIFT) /* All PWM outputs are not re-enabled at the start of a full cycle */ -# define FSTS_FFULL_SM0 (1 << FSTS_FFULL_SHIFT) /* SM0 PWM output is re-enabled at the start of a full cycle */ -# define FSTS_FFULL_SM1 (2 << FSTS_FFULL_SHIFT) /* SM1 PWM output is re-enabled at the start of a full cycle */ -# define FSTS_FFULL_SM2 (4 << FSTS_FFULL_SHIFT) /* SM2 PWM output is re-enabled at the start of a full cycle */ -# define FSTS_FFULL_SM3 (8 << FSTS_FFULL_SHIFT) /* SM3 PWM output is re-enabled at the start of a full cycle */ -#define FSTS_FFPIN_SHIFT (8) /* Bits: 8-11 Filtered Fault Pins */ -#define FSTS_FFPIN_MASK (15 << FSTS_FFPIN_SHIFT) -# define FSTS_FFPIN(n) ((uint32_t)(n) << FSTS_FFPIN_SHIFT) -# define FSTS_FFPIN_ALL_NO_FAULT (0 << FSTS_FFPIN_SHIFT) /* No Faults as current state of the filtered FAULT pins */ -# define FSTS_FFPIN_FAULT0 (1 << FSTS_FFPIN_SHIFT) /* This read-only bit reflect the current state of the filtered FAULT0 pin */ -# define FSTS_FFPIN_FAULT1 (2 << FSTS_FFPIN_SHIFT) /* This read-only bit reflect the current state of the filtered FAULT1 pin */ -# define FSTS_FFPIN_FAULT2 (4 << FSTS_FFPIN_SHIFT) /* This read-only bit reflect the current state of the filtered FAULT2 pin */ -# define FSTS_FFPIN_FAULT3 (8 << FSTS_FFPIN_SHIFT) /* This read-only bit reflect the current state of the filtered FAULT3 pin */ -#define FSTS_FHALF_SHIFT (12) /* Bits: 12-15 Half Cycle Fault Recovery */ -#define FSTS_FHALF_MASK (15 << FSTS_FHALF_SHIFT) -# define FSTS_FHALF(n) ((uint32_t)(n) << FSTS_FHALF_SHIFT) -# define FSTS_FHALF_ALL_NOT_REENABLED (0 << FSTS_FHALF_SHIFT) /* All PWM outputs are not re-enabled at the start of a half cycle */ -# define FSTS_FHALF_SM0 (1 << FSTS_FHALF_SHIFT) /* SM0 PWM output is re-enabled at the start of a half cycle (as defined by VAL0).*/ -# define FSTS_FHALF_SM1 (2 << FSTS_FHALF_SHIFT) /* SM1 PWM output is re-enabled at the start of a half cycle (as defined by VAL0).*/ -# define FSTS_FHALF_SM2 (4 << FSTS_FHALF_SHIFT) /* SM2 PWM output is re-enabled at the start of a half cycle (as defined by VAL0).*/ -# define FSTS_FHALF_SM3 (8 << FSTS_FHALF_SHIFT) /* SM3 PWM output is re-enabled at the start of a half cycle (as defined by VAL0).*/ - -/* Fault Filter Register */ - -#define FFILT_FILT_PER_SHIFT (0) /* Bits: 0-7 Fault Filter Period */ -#define FFILT_FILT_PER_MASK (0xff << FFILT_FILT_PER_SHIFT) -# define FFILT_FILT_PER(n) ((uint32_t)(n) << FFILT_FILT_PER_SHIFT) -#define FFILT_FILT_CNT_SHIFT (8) /* Bits: 8-10 Fault Filter Count */ -#define FFILT_FILT_CNT_MASK (7 << FFILT_FILT_CNT_SHIFT) -# define FFILT_FILT_CNT(n) ((uint32_t)(n) << FFILT_FILT_CNT_SHIFT) -# define FFILT_FILT_CNT_3 (0 << FFILT_FILT_CNT_SHIFT) /* */ -# define FFILT_FILT_CNT_4 (1 << FFILT_FILT_CNT_SHIFT) /* */ -# define FFILT_FILT_CNT_5 (2 << FFILT_FILT_CNT_SHIFT) /* */ -# define FFILT_FILT_CNT_6 (3 << FFILT_FILT_CNT_SHIFT) /* */ -# define FFILT_FILT_CNT_7 (4 << FFILT_FILT_CNT_SHIFT) /* */ -# define FFILT_FILT_CNT_8 (5 << FFILT_FILT_CNT_SHIFT) /* */ -# define FFILT_FILT_CNT_9 (6 << FFILT_FILT_CNT_SHIFT) /* */ -# define FFILT_FILT_CNT_10 (7 << FFILT_FILT_CNT_SHIFT) /* */ - /* Bits: 11-14 Reserved */ -#define FFILT_GSTR (1 << 15) /* Bit: 15 Fault Glitch Stretch Enable */ - -/* Fault Test Register */ - -#define FTST0_FTEST (1 << 0) /* Bit: 0 Fault Test */ - /* Bits: 1-15 Reserved */ - -/* Fault Control 2 Register */ - -#define FCTRL20_NOCOMB_SHIFT (0) /* Bits: 0-3 No Combinational Path From Fault Input To PWM Output */ -#define FCTRL20_NOCOMB_MASK (0xf << FCTRL20_NOCOMB_SHIFT) -# define FCTRL20_NOCOMB(n) ((uint32_t)(n) << FCTRL20_NOCOMB_SHIFT) -# define FCTRL20_NOCOMB_ALL_ENABLED (0 << FCTRL20_NOCOMB_SHIFT) /* All combinational link from the fault inputs to the PWM outputs are enabled */ -# define FCTRL20_NOCOMB_FAULT0 (1 << FCTRL20_NOCOMB_SHIFT) /* Disable direct combinational path from the FAULT0 input to the PWM output */ -# define FCTRL20_NOCOMB_FAULT1 (2 << FCTRL20_NOCOMB_SHIFT) /* Disable direct combinational path from the FAULT1 input to the PWM output */ -# define FCTRL20_NOCOMB_FAULT2 (4 << FCTRL20_NOCOMB_SHIFT) /* Disable direct combinational path from the FAULT2 input to the PWM output */ -# define FCTRL20_NOCOMB_FAULT3 (8 << FCTRL20_NOCOMB_SHIFT) /* Disable direct combinational path from the FAULT3 input to the PWM output */ - -#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_FLEXPWM_H */ diff --git a/arch/arm/src/imxrt/chip/imxrt_gpio.h b/arch/arm/src/imxrt/chip/imxrt_gpio.h deleted file mode 100644 index 28d979bf751..00000000000 --- a/arch/arm/src/imxrt/chip/imxrt_gpio.h +++ /dev/null @@ -1,93 +0,0 @@ -/******************************************************************************************** - * arch/arm/src/imxrt/imxrt_gpio.h - * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * David Sidrane - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ********************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_GPIO_H -#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_GPIO_H - -/******************************************************************************************** - * Included Files - ********************************************************************************************/ - -#include - -#if defined(CONFIG_ARCH_FAMILY_IMXRT102x) -# include "chip/rt102x/imxrt102x_gpio.h" -#elif defined(CONFIG_ARCH_FAMILY_IMXRT105x) -# include "chip/rt105x/imxrt105x_gpio.h" -#elif defined(CONFIG_ARCH_FAMILY_IMXRT106x) -# include "chip/rt106x/imxrt106x_gpio.h" -#else -# error Unrecognized i.MX RT architecture -#endif - -/******************************************************************************************** - * Pre-processor Definitions - ********************************************************************************************/ - -#define GPIO1 0 /* Port 1 index */ -#define GPIO2 1 /* Port 2 index */ -#define GPIO3 2 /* Port 3 index */ -#define GPIO4 3 /* Port 4 index */ -#define GPIO5 4 /* Port 5 index */ -#if IMXRT_GPIO_NPORTS > 5 -#define GPIO6 5 /* Port 6 index */ -#define GPIO7 6 /* Port 7 index */ -#define GPIO8 7 /* Port 8 index */ -#define GPIO9 8 /* Port 9 index */ -#endif -#define IMXRT_GPIO_NPINS 32 /* Up to 32 pins per port */ - -/* Register bit definitions *****************************************************************/ - -/* Most registers are laid out simply with one bit per pin */ - -#define GPIO_PIN(n) (1 << (n)) /* Bit n: Pin n, n=0-31 */ - -/* GPIO interrupt configuration register 1/2 */ - -#define GPIO_ICR_INDEX(n) (((n) >> 4) & 1) -#define GPIO_ICR_OFFSET(n) (GPIO_ICR1_OFFSET + (GPIO_ICR_INDEX(n) << 2)) - -#define GPIO_ICR_LOWLEVEL 0 /* Interrupt is low-level sensitive */ -#define GPIO_ICR_HIGHLEVEL 1 /* Interrupt is high-level sensitive */ -#define GPIO_ICR_RISINGEDGE 2 /* Interrupt is rising-edge sensitive */ -#define GPIO_ICR_FALLINGEDGE 3 /* Interrupt is falling-edge sensitive */ - -#define GPIO_ICR_SHIFT(n) (((n) & 15) << 1) -#define GPIO_ICR_MASK(n) (3 << GPIO_ICR_SHIFT(n)) -#define GPIO_ICR(i,n) ((uint32_t)(i) << GPIO_ICR_SHIFT(n)) - -#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_GPIO_H */ diff --git a/arch/arm/src/imxrt/chip/imxrt_gpt.h b/arch/arm/src/imxrt/chip/imxrt_gpt.h deleted file mode 100644 index ffee5865351..00000000000 --- a/arch/arm/src/imxrt/chip/imxrt_gpt.h +++ /dev/null @@ -1,182 +0,0 @@ -/************************************************************************************ - * arch/arm/src/imxrt/chip/imxrt_gpt.h - * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * David Sidrane - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_GPT_H -#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_GPT_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include -#include "chip/imxrt_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register Offsets *****************************************************************/ - -#define IMXRT_GPT_CR_OFFSET 0x0000 /* GPT Control Register */ -#define IMXRT_GPT_PR_OFFSET 0x0004 /* GPT Prescaler Register */ -#define IMXRT_GPT_SR_OFFSET 0x0008 /* GPT Status Register */ -#define IMXRT_GPT_IR_OFFSET 0x000c /* GPT Interrupt Register */ -#define IMXRT_GPT_OCR1_OFFSET 0x0010 /* GPT Output Compare Register 1 */ -#define IMXRT_GPT_OCR2_OFFSET 0x0014 /* GPT Output Compare Register 2 */ -#define IMXRT_GPT_OCR3_OFFSET 0x0018 /* GPT Output Compare Register 3 */ -#define IMXRT_GPT_ICR1_OFFSET 0x001c /* GPT Input Capture Register 1 */ -#define IMXRT_GPT_ICR2_OFFSET 0x0020 /* GPT Input Capture Register 2 */ -#define IMXRT_GPT_CNT_OFFSET 0x0024 /* GPT Counter Register */ - -/* Register addresses ***********************************************************************/ - -#define IMXRT_GPT1_CR (IMXRT_GPT1_BASE + IMXRT_GPT1_CR_OFFSET) /* GPT 1 Control Register */ -#define IMXRT_GPT1_PR (IMXRT_GPT1_BASE + IMXRT_GPT1_PR_OFFSET) /* GPT 1 Prescaler Register */ -#define IMXRT_GPT1_SR (IMXRT_GPT1_BASE + IMXRT_GPT1_SR_OFFSET) /* GPT 1 Status Register */ -#define IMXRT_GPT1_IR (IMXRT_GPT1_BASE + IMXRT_GPT1_IR_OFFSET) /* GPT 1 Interrupt Register */ -#define IMXRT_GPT1_OCR1 (IMXRT_GPT1_BASE + IMXRT_GPT1_OCR1_OFFSET) /* GPT 1 Output Compare Register 1 */ -#define IMXRT_GPT1_OCR2 (IMXRT_GPT1_BASE + IMXRT_GPT1_OCR2_OFFSET) /* GPT 1 Output Compare Register 2 */ -#define IMXRT_GPT1_OCR3 (IMXRT_GPT1_BASE + IMXRT_GPT1_OCR3_OFFSET) /* GPT 1 Output Compare Register 3 */ -#define IMXRT_GPT1_ICR1 (IMXRT_GPT1_BASE + IMXRT_GPT1_ICR1_OFFSET) /* GPT 1 Input Capture Register 1 */ -#define IMXRT_GPT1_ICR2 (IMXRT_GPT1_BASE + IMXRT_GPT1_ICR2_OFFSET) /* GPT 1 Input Capture Register 2 */ -#define IMXRT_GPT1_CNT (IMXRT_GPT1_BASE + IMXRT_GPT1_CNT_OFFSET) /* GPT 1 Counter Register */ -#define IMXRT_GPT2_CR (IMXRT_GPT2_BASE + IMXRT_GPT2_CR_OFFSET) /* GPT 2 Control Register */ -#define IMXRT_GPT2_PR (IMXRT_GPT2_BASE + IMXRT_GPT2_PR_OFFSET) /* GPT 2 Prescaler Register */ -#define IMXRT_GPT2_SR (IMXRT_GPT2_BASE + IMXRT_GPT2_SR_OFFSET) /* GPT 2 Status Register */ -#define IMXRT_GPT2_IR (IMXRT_GPT2_BASE + IMXRT_GPT2_IR_OFFSET) /* GPT 2 Interrupt Register */ -#define IMXRT_GPT2_OCR1 (IMXRT_GPT2_BASE + IMXRT_GPT2_OCR1_OFFSET) /* GPT 2 Output Compare Register 1 */ -#define IMXRT_GPT2_OCR2 (IMXRT_GPT2_BASE + IMXRT_GPT2_OCR2_OFFSET) /* GPT 2 Output Compare Register 2 */ -#define IMXRT_GPT2_OCR3 (IMXRT_GPT2_BASE + IMXRT_GPT2_OCR3_OFFSET) /* GPT 2 Output Compare Register 3 */ -#define IMXRT_GPT2_ICR1 (IMXRT_GPT2_BASE + IMXRT_GPT2_ICR1_OFFSET) /* GPT 2 Input Capture Register 1 */ -#define IMXRT_GPT2_ICR2 (IMXRT_GPT2_BASE + IMXRT_GPT2_ICR2_OFFSET) /* GPT 2 Input Capture Register 2 */ -#define IMXRT_GPT2_CNT (IMXRT_GPT2_BASE + IMXRT_GPT2_CNT_OFFSET) /* GPT 2 Counter Register */ - -/* GPT Control Register */ - -/* Register Bit Definitions *********************************************************/ - -#define GPT_CR_EN (1 << 0) /* Bit: 0 GPT Enable. */ -#define GPT_CR_ENMOD (1 << 1) /* Bit: 1 GPT Enable mode. */ -#define GPT_CR_DBGEN (1 << 2) /* Bit: 2 GPT debug mode enable. */ -#define GPT_CR_WAITEN (1 << 3) /* Bit: 3 GPT Wait Mode enable. */ -#define GPT_CR_DOZEEN (1 << 4) /* Bit: 4 GPT Doze Mode Enable. */ -#define GPT_CR_STOPEN (1 << 5) /* Bit: 5 GPT Stop Mode enable. */ -#define GPT_CR_CLKSRC_SHIFT (6) /* Bits: 6-8 Clock Source select. */ -#define GPT_CR_CLKSRC_MASK (7 << GPT_CR_CLKSRC_SHIFT) -# define GPT_CR_CLKSRC(n) ((uint32_t)(n) << GPT_CR_CLKSRC_SHIFT) -# define GPT_CR_CLKSRC_NONE (0 << GPT_CR_CLKSRC_SHIFT) /* No clock */ -# define GPT_CR_CLKSRC_IPG (1 << GPT_CR_CLKSRC_SHIFT) /* Peripheral Clock (ipg_clk) */ -# define GPT_CR_CLKSRC_IPG_HFR (2 << GPT_CR_CLKSRC_SHIFT) /* High Frequency Reference Clock (ipg_clk_highfreq) */ -# define GPT_CR_CLKSRC_EXT (3 << GPT_CR_CLKSRC_SHIFT) /* External Clock */ -# define GPT_CR_CLKSRC_IPG_LFR (4 << GPT_CR_CLKSRC_SHIFT) /* Low Frequency Reference Clock (ipg_clk_32k) */ -# define GPT_CR_CLKSRC_IPG_24M (5 << GPT_CR_CLKSRC_SHIFT) /* Crystal oscillator as Reference Clock (ipg_clk_24M) */ -#define GPT_CR_FRR (1 << 9) /* Bit: 9 Free-Run or Restart mode. */ -#define GPT_CR_EN_24M (1 << 10) /* Bit: 10 Enable 24 MHz clock input from crystal. */ - /* Bits: 11-14 Reserved */ -#define GPT_CR_SWR (1 << 15) /* Bit: 15 Software reset. */ -#define GPT_CR_IM1_SHIFT (16) /* Bits: 16-17 See IM2 */ -#define GPT_CR_IM1_MASK (3 << GPT_CR_IM1_SHIFT) -# define GPT_CR_IM1(n) ((uint32_t)(n) << GPT_CR_IM1_SHIFT) -# define GPT_CR_IM1_DIS (0 << GPT_CR_IM1_SHIFT) /* Capture disabled */ -# define GPT_CR_IM1_RISING (1 << GPT_CR_IM1_SHIFT) /* Capture on rising edge */ -# define GPT_CR_IM1_FALLING (2 << GPT_CR_IM1_SHIFT) /* Capture on falling edge */ -# define GPT_CR_IM1_BOTH (3 << GPT_CR_IM1_SHIFT) /* Capture on both edges */ -#define GPT_CR_IM2_SHIFT (18) /* Bits: 18-19 IM2 (bits 19-18, Input Capture Channel 2 operating mode) */ -#define GPT_CR_IM2_MASK (3 << GPT_CR_IM2_SHIFT) -# define GPT_CR_IM2(n) ((uint32_t)(n) << GPT_CR_IM2_SHIFT) -# define GPT_CR_IM2_DIS (0 << GPT_CR_IM2_SHIFT) /* Capture disabled */ -# define GPT_CR_IM2_RISING (1 << GPT_CR_IM2_SHIFT) /* Capture on rising edge */ -# define GPT_CR_IM2_FALLING (2 << GPT_CR_IM2_SHIFT) /* Capture on falling edge */ -# define GPT_CR_IM2_BOTH (3 << GPT_CR_IM2_SHIFT) /* Capture on both edges */ -#define GPT_CR_OM1_SHIFT (20) /* Bits: 20-22 See OM3 */ -#define GPT_CR_OM1_MASK (7 << GPT_CR_OM1_SHIFT) -# define GPT_CR_OM1(n) ((uint32_t)(n) << GPT_CR_OM1_SHIFT) -# define GPT_CR_OM1_DIS (0 << GPT_CR_OM1_SHIFT) /* Output disconnected. No response on pin. */ -# define GPT_CR_OM1_TOGGLE (1 << GPT_CR_OM1_SHIFT) /* Toggle output pin */ -# define GPT_CR_OM1_CLEAR (2 << GPT_CR_OM1_SHIFT) /* Clear output pin */ -# define GPT_CR_OM1_SET (3 << GPT_CR_OM1_SHIFT) /* Set output pin */ -# define GPT_CR_OM1_PULSE (4 << GPT_CR_OM1_SHIFT) /* Generate an active low pulse */ -#define GPT_CR_OM2_SHIFT (23) /* Bits: 23-25 See OM3 */ -#define GPT_CR_OM2_MASK (7 << GPT_CR_OM2_SHIFT) -# define GPT_CR_OM2(n) ((uint32_t)(n) << GPT_CR_OM2_SHIFT) -# define GPT_CR_OM2_DIS (0 << GPT_CR_OM2_SHIFT) /* Output disconnected. No response on pin. */ -# define GPT_CR_OM2_TOGGLE (1 << GPT_CR_OM2_SHIFT) /* Toggle output pin */ -# define GPT_CR_OM2_CLEAR (2 << GPT_CR_OM2_SHIFT) /* Clear output pin */ -# define GPT_CR_OM2_SET (3 << GPT_CR_OM2_SHIFT) /* Set output pin */ -# define GPT_CR_OM2_PULSE (4 << GPT_CR_OM2_SHIFT) /* Generate an active low pulse */ -#define GPT_CR_OM3_SHIFT (26) /* Bits: 26-28 OM3 (bits 28-26) controls the Output Compare Channel 3 operating mode. */ -#define GPT_CR_OM3_MASK (7 << GPT_CR_OM3_SHIFT) -# define GPT_CR_OM3(n) ((uint32_t)(n) << GPT_CR_OM3_SHIFT) -# define GPT_CR_OM3_DIS (0 << GPT_CR_OM3_SHIFT) /* Output disconnected. No response on pin. */ -# define GPT_CR_OM3_TOGGLE (1 << GPT_CR_OM3_SHIFT) /* Toggle output pin */ -# define GPT_CR_OM3_CLEAR (2 << GPT_CR_OM3_SHIFT) /* Clear output pin */ -# define GPT_CR_OM3_SET (3 << GPT_CR_OM3_SHIFT) /* Set output pin */ -# define GPT_CR_OM3_PULSE (4 << GPT_CR_OM3_SHIFT) /* Generate an active low pulse */ -#define GPT_CR_FO1 (1 << 29) /* Bit: 29 See F03 */ -#define GPT_CR_FO2 (1 << 30) /* Bit: 30 See F03 */ -#define GPT_CR_FO3 (1 << 31) /* Bit: 31 FO3 Force Output Compare Channel 3 */ - -/* GPT Prescaler Register */ - -#define GPT_PR_PRESCALER_SHIFT (0) /* Bits: 0-11 Prescaler bits. */ -#define GPT_PR_PRESCALER_MASK (0xfff << GPT_PR_PRESCALER_SHIFT) -# define GPT_PR_PRESCALER(n) ((uint32_t)(n) << GPT_PR_PRESCALER_SHIFT) -#define GPT_PR_PRESCALER24M_SHIFT (12) /* Bits: 12-15 Prescaler bits. */ -#define GPT_PR_PRESCALER24M_MASK (0xf << GPT_PR_PRESCALER24M_SHIFT) -# define GPT_PR_PRESCALER24M(n) ((uint32_t)(n) << GPT_PR_PRESCALER24M_SHIFT) - /* Bits: 16-31 Reserved */ - -/* GPT Status Register */ - -#define GPT_SR_OF1 (1 << 0) /* Bit: 0 Output Compare 1 Flag*/ -#define GPT_SR_OF2 (1 << 1) /* Bit: 1 Output Compare 2 Flag*/ -#define GPT_SR_OF3 (1 << 2) /* Bit: 2 Output Compare 3 Flag */ -#define GPT_SR_IF1 (1 << 3) /* Bit: 3 Input capture 1 Flag */ -#define GPT_SR_IF2 (1 << 4) /* Bit: 4 Input capture 2 Flag */ -#define GPT_SR_ROV (1 << 5) /* Bit: 5 Rollover Flag. */ - /* Bits: 6-31 Reserved */ - -/* GPT Interrupt Register */ - -#define GPT_IR_OF1IE (1 << 0) /* Bit: 0 Output Compare 1 Interrupt Enable */ -#define GPT_IR_OF2IE (1 << 1) /* Bit: 1 Output Compare 2 Interrupt Enable */ -#define GPT_IR_OF3IE (1 << 2) /* Bit: 2 Output Compare 3 Interrupt Enable */ -#define GPT_IR_IF1IE (1 << 3) /* Bit: 3 Input capture 1 Interrupt Enable */ -#define GPT_IR_IF2IE (1 << 4) /* Bit: 4 Input capture 2 Interrupt Enable */ -#define GPT_IR_ROVIE (1 << 5) /* Bit: 5 Rollover Interrupt Enable. */ - /* Bits: 6-31 Reserved */ - -#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_GPT_H */ diff --git a/arch/arm/src/imxrt/chip/imxrt_iomuxc.h b/arch/arm/src/imxrt/chip/imxrt_iomuxc.h deleted file mode 100644 index 53fa0a38627..00000000000 --- a/arch/arm/src/imxrt/chip/imxrt_iomuxc.h +++ /dev/null @@ -1,124 +0,0 @@ -/************************************************************************************ - * arch/arm/src/imxrt/imxrt_iomuxc.h - * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * David Sidrane - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_IOMUXC_H -#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_IOMUXC_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#if defined(CONFIG_ARCH_FAMILY_IMXRT102x) -# include "chip/rt102x/imxrt102x_iomuxc.h" -#elif defined(CONFIG_ARCH_FAMILY_IMXRT105x) -# include "chip/rt105x/imxrt105x_iomuxc.h" -#elif defined(CONFIG_ARCH_FAMILY_IMXRT106x) -# include "chip/rt106x/imxrt106x_iomuxc.h" -#else -# error Unrecognized i.MX RT architecture -#endif - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Pad Mux Registers */ - -#define PADMUX_MUXMODE_SHIFT (0) /* Bit 0-2: Software Input On Field */ -#define PADMUX_MUXMODE_MASK (7 << PADMUX_MUXMODE_SHIFT) -# define PADMUX_MUXMODE_ALT0 (0 << PADMUX_MUXMODE_SHIFT) -# define PADMUX_MUXMODE_ALT1 (1 << PADMUX_MUXMODE_SHIFT) -# define PADMUX_MUXMODE_ALT2 (2 << PADMUX_MUXMODE_SHIFT) -# define PADMUX_MUXMODE_ALT3 (3 << PADMUX_MUXMODE_SHIFT) -# define PADMUX_MUXMODE_ALT4 (4 << PADMUX_MUXMODE_SHIFT) -# define PADMUX_MUXMODE_ALT5 (5 << PADMUX_MUXMODE_SHIFT) -# define PADMUX_MUXMODE_ALT7 (7 << PADMUX_MUXMODE_SHIFT) -#define PADMUX_SION_SHIFT (4) /* Bit 4: Software Input On Field */ -# define PADMUX_SION (1 << PADMUX_SION_SHIFT) - -/* Pad Control Registers */ - -#define DRIVE_HIZ (0) /* HI-Z */ -#define DRIVE_260OHM (1) /* 150 Ohm @3.3V, 260 Ohm @1.8V */ -#define DRIVE_130OHM (2) /* 75 Ohm @3.3V, 130 Ohm @1.8V */ -#define DRIVE_90OHM (3) /* 50 Ohm @3.3V, 90 Ohm @1.8V */ -#define DRIVE_60OHM (4) /* 37 Ohm @3.3V, 60 Ohm @1.8V */ -#define DRIVE_50OHM (5) /* 30 Ohm @3.3V, 50 Ohm @1.8V */ -#define DRIVE_40OHM (6) /* 25 Ohm @3.3V, 40 Ohm @1.8V */ -#define DRIVE_33OHM (7) /* 20 Ohm @3.3V, 33 Ohm @1.8V */ - -#define SPEED_LOW (0) /* Low frequency (50 MHz) */ -#define SPEED_MEDIUM (2) /* Medium frequency (100, MHz) */ -#define SPEED_MAX (3) /* Maximum frequency (200 MHz) */ - -#define PULL_DOWN_100K (0) /* 100K Ohm Pull Down */ -#define PULL_UP_47K (1) /* 47K Ohm Pull Up */ -#define PULL_UP_100K (2) /* 100K Ohm Pull Up */ -#define PULL_UP_22K (3) /* 22K Ohm Pull Up */ - -#define PADCTL_SRE (1 << 0) /* Bit 0: Slew Rate Field */ -#define PADCTL_DSE_SHIFT (3) /* Bits 3-5: Drive Strength Field */ -#define PADCTL_DSE_MASK (7 << PADCTL_DSE_SHIFT) -# define PADCTL_DSE(n) ((uint32_t)(n) << PADCTL_DSE_SHIFT) /* n=DRIVE_* */ -# define PADCTL_DSE_HIZ (0 << PADCTL_DSE_SHIFT) /* HI-Z */ -# define PADCTL_DSE_260OHM (1 << PADCTL_DSE_SHIFT) /* 150 Ohm @3.3V, 260 Ohm @1.8V */ -# define PADCTL_DSE_130OHM (2 << PADCTL_DSE_SHIFT) /* 75 Ohm @3.3V, 130 Ohm @1.8V */ -# define PADCTL_DSE_90OHM (3 << PADCTL_DSE_SHIFT) /* 50 Ohm @3.3V, 90 Ohm @1.8V */ -# define PADCTL_DSE_60OHM (4 << PADCTL_DSE_SHIFT) /* 37 Ohm @3.3V, 60 Ohm @1.8V */ -# define PADCTL_DSE_50OHM (5 << PADCTL_DSE_SHIFT) /* 30 Ohm @3.3V, 50 Ohm @1.8V */ -# define PADCTL_DSE_40OHM (6 << PADCTL_DSE_SHIFT) /* 25 Ohm @3.3V, 40 Ohm @1.8V */ -# define PADCTL_DSE_33OHM (7 << PADCTL_DSE_SHIFT) /* 20 Ohm @3.3V, 33 Ohm @1.8V */ -#define PADCTL_SPEED_SHIFT (6) /* Bits 6-7: Speed Field */ -#define PADCTL_SPEED_MASK (3 << PADCTL_SPEED_SHIFT) -# define PADCTL_SPEED(n) ((uint32_t)(n) << PADCTL_SPEED_SHIFT) /* n=SPEED_* */ -# define PADCTL_SPEED_LOW (0 << PADCTL_SPEED_SHIFT) /* Low frequency (50 MHz) */ -# define PADCTL_SPEED_MEDIUM (1 << PADCTL_SPEED_SHIFT) /* Medium frequency (100, 150 MHz) */ -# define PADCTL_SPEED_MAX (3 << PADCTL_SPEED_SHIFT) /* Maximum frequency (100, 150, 200 MHz) */ -#define PADCTL_ODE (1 << 11) /* Bit 11: Open Drain Enable Field */ -#define PADCTL_PKE (1 << 12) /* Bit 12: Pull / Keep Enable Field */ -#define PADCTL_PUE (1 << 13) /* Bit 13: Pull / Keep Select Field */ -#define PADCTL_PUS_SHIFT (14) /* Bits 14-15: Pull Up / Down Config. Field */ -#define PADCTL_PUS_MASK (3 << PADCTL_PUS_SHIFT) -# define PADCTL_PUS(n) ((uint32_t)(n) << PADCTL_PUS_SHIFT) /* n=PULL_* */ -# define PADCTL_PUS_DOWN_100K (0 << PADCTL_PUS_SHIFT) /* 100K Ohm Pull Down */ -# define PADCTL_PUS_UP_47K (1 << PADCTL_PUS_SHIFT) /* 47K Ohm Pull Up */ -# define PADCTL_PUS_UP_100K (2 << PADCTL_PUS_SHIFT) /* 100K Ohm Pull Up */ -# define PADCTL_PUS_UP_22K (3 << PADCTL_PUS_SHIFT) /* 22K Ohm Pull Up */ -#define PADCTL_HYS (1 << 16) /* Bit 16: Hysteresis Enable Field */ - -#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_IOMUXC_H */ diff --git a/arch/arm/src/imxrt/chip/imxrt_lcd.h b/arch/arm/src/imxrt/chip/imxrt_lcd.h deleted file mode 100644 index 4a7b94e254d..00000000000 --- a/arch/arm/src/imxrt/chip/imxrt_lcd.h +++ /dev/null @@ -1,1709 +0,0 @@ -/************************************************************************************************ - * arch/arm/src/imxrt/chip/imxrt_lcd.h - * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Copyright (C) 2016-2018 NXP. All rights reserved. - * Author: Johannes Schock (Port) - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_LCD_H -#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_LCD_H - -/************************************************************************************************ - * Included Files - ************************************************************************************************/ - -#include -#include "chip/imxrt_memorymap.h" - -/************************************************************************************************ - * Pre-processor Definitions - ************************************************************************************************/ - -/* Register offsets *****************************************************************************/ - -#define IMXRT_LCDIF_CTRL_OFFSET 0x0000 /* General Control Register */ -#define IMXRT_LCDIF_CTRL_SET_OFFSET 0x0004 /* General Control Register */ -#define IMXRT_LCDIF_CTRL_CLR_OFFSET 0x0008 /* General Control Register */ -#define IMXRT_LCDIF_CTRL_TOG_OFFSET 0x000c /* General Control Register */ -#define IMXRT_LCDIF_CTRL1_OFFSET 0x0010 /* General Control1 Register */ -#define IMXRT_LCDIF_CTRL1_SET_OFFSET 0x0014 /* General Control1 Register */ -#define IMXRT_LCDIF_CTRL1_CLR_OFFSET 0x0018 /* General Control1 Register */ -#define IMXRT_LCDIF_CTRL1_TOG_OFFSET 0x001c /* General Control1 Register */ -#define IMXRT_LCDIF_CTRL2_OFFSET 0x0020 /* General Control2 Register */ -#define IMXRT_LCDIF_CTRL2_SET_OFFSET 0x0024 /* General Control2 Register */ -#define IMXRT_LCDIF_CTRL2_CLR_OFFSET 0x0028 /* General Control2 Register */ -#define IMXRT_LCDIF_CTRL2_TOG_OFFSET 0x002c /* General Control2 Register */ -#define IMXRT_LCDIF_TRANSFER_COUNT_OFFSET 0x0030 /* Horizontal and Vertical Valid Data Count Register */ -#define IMXRT_LCDIF_CUR_BUF_OFFSET 0x0040 /* Current Buffer Address Register */ -#define IMXRT_LCDIF_NEXT_BUF_OFFSET 0x0050 /* Next Buffer Address Register */ -#define IMXRT_LCDIF_VDCTRL0_OFFSET 0x0070 /* VSYNC Mode and Dotclk Mode Control Register0 */ -#define IMXRT_LCDIF_VDCTRL0_SET_OFFSET 0x0074 /* VSYNC Mode and Dotclk Mode Control Register0 */ -#define IMXRT_LCDIF_VDCTRL0_CLR_OFFSET 0x0078 /* VSYNC Mode and Dotclk Mode Control Register0 */ -#define IMXRT_LCDIF_VDCTRL0_TOG_OFFSET 0x007c /* VSYNC Mode and Dotclk Mode Control Register0 */ -#define IMXRT_LCDIF_VDCTRL1_OFFSET 0x0080 /* VSYNC Mode and Dotclk Mode Control Register1 */ -#define IMXRT_LCDIF_VDCTRL2_OFFSET 0x0090 /* VSYNC Mode and Dotclk Mode Control Register2 */ -#define IMXRT_LCDIF_VDCTRL3_OFFSET 0x00a0 /* VSYNC Mode and Dotclk Mode Control Register3 */ -#define IMXRT_LCDIF_VDCTRL4_OFFSET 0x00b0 /* VSYNC Mode and Dotclk Mode Control Register4 */ -#define IMXRT_LCDIF_BM_ERROR_STAT_OFFSET 0x0190 /* Bus Master Error Status Register */ -#define IMXRT_LCDIF_CRC_STAT_OFFSET 0x01a0 /* CRC Status Register */ -#define IMXRT_LCDIF_STAT_OFFSET 0x01b0 /* LCD Interface Status Register */ -#define IMXRT_LCDIF_THRES_OFFSET 0x0200 /* Threshold Register */ - -#define IMXRT_LCDIF_PIGEONCTRL0_OFFSET 0x0380 /* Pigeon Mode Control0 Register */ -#define IMXRT_LCDIF_PIGEONCTRL0_SET_OFFSET 0x0384 /* Pigeon Mode Control0 Register */ -#define IMXRT_LCDIF_PIGEONCTRL0_CLR_OFFSET 0x0388 /* Pigeon Mode Control0 Register */ -#define IMXRT_LCDIF_PIGEONCTRL0_TOG_OFFSET 0x038c /* Pigeon Mode Control0 Register */ -#define IMXRT_LCDIF_PIGEONCTRL1_OFFSET 0x0390 /* Pigeon Mode Control1 Register */ -#define IMXRT_LCDIF_PIGEONCTRL1_SET_OFFSET 0x0394 /* Pigeon Mode Control1 Register */ -#define IMXRT_LCDIF_PIGEONCTRL1_CLR_OFFSET 0x0398 /* Pigeon Mode Control1 Register */ -#define IMXRT_LCDIF_PIGEONCTRL1_TOG_OFFSET 0x039c /* Pigeon Mode Control1 Register */ -#define IMXRT_LCDIF_PIGEONCTRL2_OFFSET 0x03a0 /* Pigeon Mode Control2 Register */ -#define IMXRT_LCDIF_PIGEONCTRL2_SET_OFFSET 0x03a4 /* Pigeon Mode Control2 Register */ -#define IMXRT_LCDIF_PIGEONCTRL2_CLR_OFFSET 0x03a8 /* Pigeon Mode Control2 Register */ -#define IMXRT_LCDIF_PIGEONCTRL2_TOG_OFFSET 0x03ac /* Pigeon Mode Control2 Register */ - -#define IMXRT_LCDIF_PIGEON_START_OFFSET 0x0800 /* Pigeon */ -# define IMXRT_LCDIF_PIGEON0_OFFSET 0x0000 /* Pigeon 0 */ -# define IMXRT_LCDIF_PIGEON1_OFFSET 0x0010 /* Pigeon 1 */ -# define IMXRT_LCDIF_PIGEON2_OFFSET 0x0020 /* Pigeon 2 */ -# define IMXRT_LCDIF_PIGEON_SIZE 0x0040 /* Pigeon Element Size */ -# define IMXRT_LCDIF_PIGEON_NUM 12 /* Pigeon Element Number */ -# define IMXRT_LCDIF_PIGEON_OFFSET(n) (IMXRT_LCDIF_PIGEON_START_OFFSET + ((n) * IMXRT_LCDIF_PIGEON_SIZE)) - -#define IMXRT_LCDIF_LUT_CTRL_OFFSET 0x0b00 /* Lookup Table Data Register */ -#define IMXRT_LCDIF_LUT0_ADDR_OFFSET 0x0b10 /* Lookup Table Control Register */ -#define IMXRT_LCDIF_LUT0_DATA_OFFSET 0x0b20 /* Lookup Table Data Register */ -#define IMXRT_LCDIF_LUT1_ADDR_OFFSET 0x0b30 /* Lookup Table Control Register */ -#define IMXRT_LCDIF_LUT1_DATA_OFFSET 0x0b40 /* Lookup Table Data Register */ - -/* Register Addresses ***************************************************************************/ - -#define IMXRT_LCDIF_CTRL (IMXRT_LCDIF_BASE + IMXRT_LCDIF_CTRL_OFFSET) -#define IMXRT_LCDIF_CTRL_SET (IMXRT_LCDIF_BASE + IMXRT_LCDIF_CTRL_SET_OFFSET) -#define IMXRT_LCDIF_CTRL_CLR (IMXRT_LCDIF_BASE + IMXRT_LCDIF_CTRL_CLR_OFFSET) -#define IMXRT_LCDIF_CTRL_TOG (IMXRT_LCDIF_BASE + IMXRT_LCDIF_CTRL_TOG_OFFSET) -#define IMXRT_LCDIF_CTRL1 (IMXRT_LCDIF_BASE + IMXRT_LCDIF_CTRL1_OFFSET) -#define IMXRT_LCDIF_CTRL1_SET (IMXRT_LCDIF_BASE + IMXRT_LCDIF_CTRL1_SET_OFFSET) -#define IMXRT_LCDIF_CTRL1_CLR (IMXRT_LCDIF_BASE + IMXRT_LCDIF_CTRL1_CLR_OFFSET) -#define IMXRT_LCDIF_CTRL1_TOG (IMXRT_LCDIF_BASE + IMXRT_LCDIF_CTRL1_TOG_OFFSET) -#define IMXRT_LCDIF_CTRL2 (IMXRT_LCDIF_BASE + IMXRT_LCDIF_CTRL2_OFFSET) -#define IMXRT_LCDIF_CTRL2_SET (IMXRT_LCDIF_BASE + IMXRT_LCDIF_CTRL2_SET_OFFSET) -#define IMXRT_LCDIF_CTRL2_CLR (IMXRT_LCDIF_BASE + IMXRT_LCDIF_CTRL2_CLR_OFFSET) -#define IMXRT_LCDIF_CTRL2_TOG (IMXRT_LCDIF_BASE + IMXRT_LCDIF_CTRL2_TOG_OFFSET) -#define IMXRT_LCDIF_TRANSFER_COUNT (IMXRT_LCDIF_BASE + IMXRT_LCDIF_TRANSFER_COUNT_OFFSET) -#define IMXRT_LCDIF_CUR_BUF (IMXRT_LCDIF_BASE + IMXRT_LCDIF_CUR_BUF_OFFSET) -#define IMXRT_LCDIF_NEXT_BUF (IMXRT_LCDIF_BASE + IMXRT_LCDIF_NEXT_BUF_OFFSET) -#define IMXRT_LCDIF_VDCTRL0 (IMXRT_LCDIF_BASE + IMXRT_LCDIF_VDCTRL0_OFFSET) -#define IMXRT_LCDIF_VDCTRL0_SET (IMXRT_LCDIF_BASE + IMXRT_LCDIF_VDCTRL0_SET_OFFSET) -#define IMXRT_LCDIF_VDCTRL0_CLR (IMXRT_LCDIF_BASE + IMXRT_LCDIF_VDCTRL0_CLR_OFFSET) -#define IMXRT_LCDIF_VDCTRL0_TOG (IMXRT_LCDIF_BASE + IMXRT_LCDIF_VDCTRL0_TOG_OFFSET) -#define IMXRT_LCDIF_VDCTRL1 (IMXRT_LCDIF_BASE + IMXRT_LCDIF_VDCTRL1_OFFSET) -#define IMXRT_LCDIF_VDCTRL2 (IMXRT_LCDIF_BASE + IMXRT_LCDIF_VDCTRL2_OFFSET) -#define IMXRT_LCDIF_VDCTRL3 (IMXRT_LCDIF_BASE + IMXRT_LCDIF_VDCTRL3_OFFSET) -#define IMXRT_LCDIF_VDCTRL4 (IMXRT_LCDIF_BASE + IMXRT_LCDIF_VDCTRL4_OFFSET) -#define IMXRT_LCDIF_BM_ERROR_STAT (IMXRT_LCDIF_BASE + IMXRT_LCDIF_BM_ERROR_STAT_OFFSET) -#define IMXRT_LCDIF_CRC_STAT (IMXRT_LCDIF_BASE + IMXRT_LCDIF_CRC_STAT_OFFSET) -#define IMXRT_LCDIF_STAT (IMXRT_LCDIF_BASE + IMXRT_LCDIF_STAT_OFFSET) -#define IMXRT_LCDIF_THRES (IMXRT_LCDIF_BASE + IMXRT_LCDIF_THRES_OFFSET) - -#define IMXRT_LCDIF_PIGEONCTRL0 (IMXRT_LCDIF_BASE + IMXRT_LCDIF_PIGEONCTRL0_OFFSET) -#define IMXRT_LCDIF_PIGEONCTRL0_SET (IMXRT_LCDIF_BASE + IMXRT_LCDIF_PIGEONCTRL0_SET_OFFSET) -#define IMXRT_LCDIF_PIGEONCTRL0_CLR (IMXRT_LCDIF_BASE + IMXRT_LCDIF_PIGEONCTRL0_CLR_OFFSET) -#define IMXRT_LCDIF_PIGEONCTRL0_TOG (IMXRT_LCDIF_BASE + IMXRT_LCDIF_PIGEONCTRL0_TOG_OFFSET) -#define IMXRT_LCDIF_PIGEONCTRL1 (IMXRT_LCDIF_BASE + IMXRT_LCDIF_PIGEONCTRL1_OFFSET) -#define IMXRT_LCDIF_PIGEONCTRL1_SET (IMXRT_LCDIF_BASE + IMXRT_LCDIF_PIGEONCTRL1_SET_OFFSET) -#define IMXRT_LCDIF_PIGEONCTRL1_CLR (IMXRT_LCDIF_BASE + IMXRT_LCDIF_PIGEONCTRL1_CLR_OFFSET) -#define IMXRT_LCDIF_PIGEONCTRL1_TOG (IMXRT_LCDIF_BASE + IMXRT_LCDIF_PIGEONCTRL1_TOG_OFFSET) -#define IMXRT_LCDIF_PIGEONCTRL2 (IMXRT_LCDIF_BASE + IMXRT_LCDIF_PIGEONCTRL2_OFFSET) -#define IMXRT_LCDIF_PIGEONCTRL2_SET (IMXRT_LCDIF_BASE + IMXRT_LCDIF_PIGEONCTRL2_SET_OFFSET) -#define IMXRT_LCDIF_PIGEONCTRL2_CLR (IMXRT_LCDIF_BASE + IMXRT_LCDIF_PIGEONCTRL2_CLR_OFFSET) -#define IMXRT_LCDIF_PIGEONCTRL2_TOG (IMXRT_LCDIF_BASE + IMXRT_LCDIF_PIGEONCTRL2_TOG_OFFSET) - -#define IMXRT_LCDIF_PIGEON0(n) (IMXRT_LCDIF_BASE + IMXRT_LCDIF_PIGEON_OFFSET(n) + IMXRT_LCDIF_PIGEON0_OFFSET) -#define IMXRT_LCDIF_PIGEON1(n) (IMXRT_LCDIF_BASE + IMXRT_LCDIF_PIGEON_OFFSET(n) + IMXRT_LCDIF_PIGEON1_OFFSET) -#define IMXRT_LCDIF_PIGEON2(n) (IMXRT_LCDIF_BASE + IMXRT_LCDIF_PIGEON_OFFSET(n) + IMXRT_LCDIF_PIGEON2_OFFSET) - -#define IMXRT_LCDIF_LUT_CTRL (IMXRT_LCDIF_BASE + IMXRT_LCDIF_LUT_CTRL_OFFSET) -#define IMXRT_LCDIF_LUT0_ADDR (IMXRT_LCDIF_BASE + IMXRT_LCDIF_LUT0_ADDR_OFFSET) -#define IMXRT_LCDIF_LUT0_DATA (IMXRT_LCDIF_BASE + IMXRT_LCDIF_LUT0_DATA_OFFSET) -#define IMXRT_LCDIF_LUT1_ADDR (IMXRT_LCDIF_BASE + IMXRT_LCDIF_LUT1_ADDR_OFFSET) -#define IMXRT_LCDIF_LUT1_DATA (IMXRT_LCDIF_BASE + IMXRT_LCDIF_LUT1_DATA_OFFSET) -#define IMXRT_LCDIF_LUT_ENTRY_NUM (256) - -/* Register Bitfield Definitions ****************************************************************/ - -/* CTRL - LCDIF General Control Register */ - -#define LCDIF_CTRL_RUN_MASK (0x1U) -#define LCDIF_CTRL_RUN_SHIFT (0U) -#define LCDIF_CTRL_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RUN_SHIFT)) & LCDIF_CTRL_RUN_MASK) -#define LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK (0x2U) -#define LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT (1U) -/* DATA_FORMAT_24_BIT - * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. - * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. - */ -#define LCDIF_CTRL_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK) -#define LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK (0x4U) -#define LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT (2U) -/* DATA_FORMAT_18_BIT - * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. - * 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. - */ -#define LCDIF_CTRL_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK) -#define LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK (0x8U) -#define LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT (3U) -#define LCDIF_CTRL_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK) -#define LCDIF_CTRL_RSRVD0_MASK (0x10U) -#define LCDIF_CTRL_RSRVD0_SHIFT (4U) -#define LCDIF_CTRL_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RSRVD0_SHIFT)) & LCDIF_CTRL_RSRVD0_MASK) -#define LCDIF_CTRL_MASTER_MASK (0x20U) -#define LCDIF_CTRL_MASTER_SHIFT (5U) -#define LCDIF_CTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_MASTER_SHIFT)) & LCDIF_CTRL_MASTER_MASK) -#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK (0x40U) -#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT (6U) -#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK) -#define LCDIF_CTRL_WORD_LENGTH_MASK (0x300U) -#define LCDIF_CTRL_WORD_LENGTH_SHIFT (8U) -/* WORD_LENGTH - * 0b00..Input data is 16 bits per pixel. - * 0b01..Input data is 8 bits wide. - * 0b10..Input data is 18 bits per pixel. - * 0b11..Input data is 24 bits per pixel. - */ -#define LCDIF_CTRL_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_WORD_LENGTH_MASK) -#define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0xc00U) -#define LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT (10U) - -/* LCD_DATABUS_WIDTH - * 0b00..16-bit data bus mode. - * 0b01..8-bit data bus mode. - * 0b10..18-bit data bus mode. - * 0b11..24-bit data bus mode. - */ - -#define LCDIF_CTRL_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK) -#define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3000U) -#define LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT (12U) - -/* CSC_DATA_SWIZZLE - * 0b00..No byte swapping.(Little endian) - * 0b00..Little Endian byte ordering (same as NO_SWAP). - * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). - * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). - * 0b10..Swap half-words. - * 0b11..Swap bytes within each half-word. - */ - -#define LCDIF_CTRL_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK) -#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0xc000U) -#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT (14U) - -/* INPUT_DATA_SWIZZLE - * 0b00..No byte swapping.(Little endian) - * 0b00..Little Endian byte ordering (same as NO_SWAP). - * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). - * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). - * 0b10..Swap half-words. - * 0b11..Swap bytes within each half-word. - */ - -#define LCDIF_CTRL_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK) -#define LCDIF_CTRL_DOTCLK_MODE_MASK (0x20000U) -#define LCDIF_CTRL_DOTCLK_MODE_SHIFT (17U) -#define LCDIF_CTRL_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_DOTCLK_MODE_MASK) -#define LCDIF_CTRL_BYPASS_COUNT_MASK (0x80000U) -#define LCDIF_CTRL_BYPASS_COUNT_SHIFT (19U) -#define LCDIF_CTRL_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_BYPASS_COUNT_MASK) -#define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x3e00000U) -#define LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT (21U) -#define LCDIF_CTRL_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SHIFT_NUM_BITS_MASK) -#define LCDIF_CTRL_DATA_SHIFT_DIR_MASK (0x4000000U) -#define LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT (26U) - -/* DATA_SHIFT_DIR - * 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. - * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. - */ - -#define LCDIF_CTRL_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_DATA_SHIFT_DIR_MASK) -#define LCDIF_CTRL_CLKGATE_MASK (0x40000000U) -#define LCDIF_CTRL_CLKGATE_SHIFT (30U) -#define LCDIF_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLKGATE_SHIFT)) & LCDIF_CTRL_CLKGATE_MASK) -#define LCDIF_CTRL_SFTRST_MASK (0x80000000U) -#define LCDIF_CTRL_SFTRST_SHIFT (31U) -#define LCDIF_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SFTRST_SHIFT)) & LCDIF_CTRL_SFTRST_MASK) - -/* CTRL_SET - LCDIF General Control Register */ - -#define LCDIF_CTRL_SET_RUN_MASK (0x1U) -#define LCDIF_CTRL_SET_RUN_SHIFT (0U) -#define LCDIF_CTRL_SET_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RUN_SHIFT)) & LCDIF_CTRL_SET_RUN_MASK) -#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK (0x2U) -#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT (1U) - -/* DATA_FORMAT_24_BIT - * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. - * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. - */ - -#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK) -#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK (0x4U) -#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT (2U) - -/* DATA_FORMAT_18_BIT - * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. - * 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. - */ - -#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK) -#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK (0x8U) -#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT (3U) -#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK) -#define LCDIF_CTRL_SET_RSRVD0_MASK (0x10U) -#define LCDIF_CTRL_SET_RSRVD0_SHIFT (4U) -#define LCDIF_CTRL_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RSRVD0_SHIFT)) & LCDIF_CTRL_SET_RSRVD0_MASK) -#define LCDIF_CTRL_SET_MASTER_MASK (0x20U) -#define LCDIF_CTRL_SET_MASTER_SHIFT (5U) -#define LCDIF_CTRL_SET_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_MASTER_SHIFT)) & LCDIF_CTRL_SET_MASTER_MASK) -#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK (0x40U) -#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT (6U) -#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK) -#define LCDIF_CTRL_SET_WORD_LENGTH_MASK (0x300U) -#define LCDIF_CTRL_SET_WORD_LENGTH_SHIFT (8U) - -/* WORD_LENGTH - * 0b00..Input data is 16 bits per pixel. - * 0b01..Input data is 8 bits wide. - * 0b10..Input data is 18 bits per pixel. - * 0b11..Input data is 24 bits per pixel. - */ - -#define LCDIF_CTRL_SET_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_SET_WORD_LENGTH_MASK) -#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK (0xc00U) -#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT (10U) - -/* LCD_DATABUS_WIDTH - * 0b00..16-bit data bus mode. - * 0b01..8-bit data bus mode. - * 0b10..18-bit data bus mode. - * 0b11..24-bit data bus mode. - */ - -#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK) -#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK (0x3000U) -#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT (12U) - -/* CSC_DATA_SWIZZLE - * 0b00..No byte swapping.(Little endian) - * 0b00..Little Endian byte ordering (same as NO_SWAP). - * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). - * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). - * 0b10..Swap half-words. - * 0b11..Swap bytes within each half-word. - */ - -#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK) -#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK (0xc000U) -#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT (14U) - -/* INPUT_DATA_SWIZZLE - * 0b00..No byte swapping.(Little endian) - * 0b00..Little Endian byte ordering (same as NO_SWAP). - * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). - * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). - * 0b10..Swap half-words. - * 0b11..Swap bytes within each half-word. - */ - -#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK) -#define LCDIF_CTRL_SET_DOTCLK_MODE_MASK (0x20000U) -#define LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT (17U) -#define LCDIF_CTRL_SET_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_SET_DOTCLK_MODE_MASK) -#define LCDIF_CTRL_SET_BYPASS_COUNT_MASK (0x80000U) -#define LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT (19U) -#define LCDIF_CTRL_SET_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_SET_BYPASS_COUNT_MASK) -#define LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK (0x3e00000U) -#define LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT (21U) -#define LCDIF_CTRL_SET_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK) -#define LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK (0x4000000U) -#define LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT (26U) - -/* DATA_SHIFT_DIR - * 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. - * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. - */ - -#define LCDIF_CTRL_SET_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK) -#define LCDIF_CTRL_SET_CLKGATE_MASK (0x40000000U) -#define LCDIF_CTRL_SET_CLKGATE_SHIFT (30U) -#define LCDIF_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CLKGATE_SHIFT)) & LCDIF_CTRL_SET_CLKGATE_MASK) -#define LCDIF_CTRL_SET_SFTRST_MASK (0x80000000U) -#define LCDIF_CTRL_SET_SFTRST_SHIFT (31U) -#define LCDIF_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SFTRST_SHIFT)) & LCDIF_CTRL_SET_SFTRST_MASK) - -/* CTRL_CLR - LCDIF General Control Register */ - -#define LCDIF_CTRL_CLR_RUN_MASK (0x1U) -#define LCDIF_CTRL_CLR_RUN_SHIFT (0U) -#define LCDIF_CTRL_CLR_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RUN_SHIFT)) & LCDIF_CTRL_CLR_RUN_MASK) -#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK (0x2U) -#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT (1U) - -/* DATA_FORMAT_24_BIT - * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. - * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. - */ - -#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK) -#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK (0x4U) -#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT (2U) - -/* DATA_FORMAT_18_BIT - * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. - * 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. - */ - -#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK) -#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK (0x8U) -#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT (3U) -#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK) -#define LCDIF_CTRL_CLR_RSRVD0_MASK (0x10U) -#define LCDIF_CTRL_CLR_RSRVD0_SHIFT (4U) -#define LCDIF_CTRL_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL_CLR_RSRVD0_MASK) -#define LCDIF_CTRL_CLR_MASTER_MASK (0x20U) -#define LCDIF_CTRL_CLR_MASTER_SHIFT (5U) -#define LCDIF_CTRL_CLR_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_MASTER_SHIFT)) & LCDIF_CTRL_CLR_MASTER_MASK) -#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK (0x40U) -#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT (6U) -#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK) -#define LCDIF_CTRL_CLR_WORD_LENGTH_MASK (0x300U) -#define LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT (8U) - -/* WORD_LENGTH - * 0b00..Input data is 16 bits per pixel. - * 0b01..Input data is 8 bits wide. - * 0b10..Input data is 18 bits per pixel. - * 0b11..Input data is 24 bits per pixel. - */ - -#define LCDIF_CTRL_CLR_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_CLR_WORD_LENGTH_MASK) -#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK (0xc00U) -#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT (10U) - -/* LCD_DATABUS_WIDTH - * 0b00..16-bit data bus mode. - * 0b01..8-bit data bus mode. - * 0b10..18-bit data bus mode. - * 0b11..24-bit data bus mode. - */ - -#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK) -#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK (0x3000U) -#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT (12U) - -/* CSC_DATA_SWIZZLE - * 0b00..No byte swapping.(Little endian) - * 0b00..Little Endian byte ordering (same as NO_SWAP). - * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). - * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). - * 0b10..Swap half-words. - * 0b11..Swap bytes within each half-word. - */ - -#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK) -#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK (0xc000U) -#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT (14U) - -/* INPUT_DATA_SWIZZLE - * 0b00..No byte swapping.(Little endian) - * 0b00..Little Endian byte ordering (same as NO_SWAP). - * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). - * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). - * 0b10..Swap half-words. - * 0b11..Swap bytes within each half-word. - */ - -#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK) -#define LCDIF_CTRL_CLR_DOTCLK_MODE_MASK (0x20000U) -#define LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT (17U) -#define LCDIF_CTRL_CLR_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_CLR_DOTCLK_MODE_MASK) -#define LCDIF_CTRL_CLR_BYPASS_COUNT_MASK (0x80000U) -#define LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT (19U) -#define LCDIF_CTRL_CLR_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_CLR_BYPASS_COUNT_MASK) -#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK (0x3e00000U) -#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT (21U) -#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK) -#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK (0x4000000U) -#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT (26U) - -/* DATA_SHIFT_DIR - * 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. - * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. - */ - -#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK) -#define LCDIF_CTRL_CLR_CLKGATE_MASK (0x40000000U) -#define LCDIF_CTRL_CLR_CLKGATE_SHIFT (30U) -#define LCDIF_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CLKGATE_SHIFT)) & LCDIF_CTRL_CLR_CLKGATE_MASK) -#define LCDIF_CTRL_CLR_SFTRST_MASK (0x80000000U) -#define LCDIF_CTRL_CLR_SFTRST_SHIFT (31U) -#define LCDIF_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SFTRST_SHIFT)) & LCDIF_CTRL_CLR_SFTRST_MASK) - -/* CTRL_TOG - LCDIF General Control Register */ - -#define LCDIF_CTRL_TOG_RUN_MASK (0x1U) -#define LCDIF_CTRL_TOG_RUN_SHIFT (0U) -#define LCDIF_CTRL_TOG_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RUN_SHIFT)) & LCDIF_CTRL_TOG_RUN_MASK) -#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK (0x2U) -#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT (1U) - -/* DATA_FORMAT_24_BIT - * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. - * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. - */ - -#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK) -#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK (0x4U) -#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT (2U) - -/* DATA_FORMAT_18_BIT - * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. - * 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. - */ - -#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK) -#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK (0x8U) -#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT (3U) -#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK) -#define LCDIF_CTRL_TOG_RSRVD0_MASK (0x10U) -#define LCDIF_CTRL_TOG_RSRVD0_SHIFT (4U) -#define LCDIF_CTRL_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL_TOG_RSRVD0_MASK) -#define LCDIF_CTRL_TOG_MASTER_MASK (0x20U) -#define LCDIF_CTRL_TOG_MASTER_SHIFT (5U) -#define LCDIF_CTRL_TOG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_MASTER_SHIFT)) & LCDIF_CTRL_TOG_MASTER_MASK) -#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK (0x40U) -#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT (6U) -#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK) -#define LCDIF_CTRL_TOG_WORD_LENGTH_MASK (0x300U) -#define LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT (8U) - -/* WORD_LENGTH - * 0b00..Input data is 16 bits per pixel. - * 0b01..Input data is 8 bits wide. - * 0b10..Input data is 18 bits per pixel. - * 0b11..Input data is 24 bits per pixel. - */ - -#define LCDIF_CTRL_TOG_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_TOG_WORD_LENGTH_MASK) -#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK (0xc00U) -#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT (10U) - -/* LCD_DATABUS_WIDTH - * 0b00..16-bit data bus mode. - * 0b01..8-bit data bus mode. - * 0b10..18-bit data bus mode. - * 0b11..24-bit data bus mode. - */ - -#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK) -#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK (0x3000U) -#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT (12U) - -/* CSC_DATA_SWIZZLE - * 0b00..No byte swapping.(Little endian) - * 0b00..Little Endian byte ordering (same as NO_SWAP). - * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). - * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). - * 0b10..Swap half-words. - * 0b11..Swap bytes within each half-word. - */ - -#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK) -#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK (0xc000U) -#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT (14U) - -/* INPUT_DATA_SWIZZLE - * 0b00..No byte swapping.(Little endian) - * 0b00..Little Endian byte ordering (same as NO_SWAP). - * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). - * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). - * 0b10..Swap half-words. - * 0b11..Swap bytes within each half-word. - */ - -#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK) -#define LCDIF_CTRL_TOG_DOTCLK_MODE_MASK (0x20000U) -#define LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT (17U) -#define LCDIF_CTRL_TOG_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_TOG_DOTCLK_MODE_MASK) -#define LCDIF_CTRL_TOG_BYPASS_COUNT_MASK (0x80000U) -#define LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT (19U) -#define LCDIF_CTRL_TOG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_TOG_BYPASS_COUNT_MASK) -#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK (0x3e00000U) -#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT (21U) -#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK) -#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK (0x4000000U) -#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT (26U) - -/* DATA_SHIFT_DIR - * 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. - * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. - */ - -#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK) -#define LCDIF_CTRL_TOG_CLKGATE_MASK (0x40000000U) -#define LCDIF_CTRL_TOG_CLKGATE_SHIFT (30U) -#define LCDIF_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CLKGATE_SHIFT)) & LCDIF_CTRL_TOG_CLKGATE_MASK) -#define LCDIF_CTRL_TOG_SFTRST_MASK (0x80000000U) -#define LCDIF_CTRL_TOG_SFTRST_SHIFT (31U) -#define LCDIF_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SFTRST_SHIFT)) & LCDIF_CTRL_TOG_SFTRST_MASK) - -/* CTRL1 - LCDIF General Control1 Register */ - -#define LCDIF_CTRL1_RSRVD0_MASK (0xf8U) -#define LCDIF_CTRL1_RSRVD0_SHIFT (3U) -#define LCDIF_CTRL1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RSRVD0_SHIFT)) & LCDIF_CTRL1_RSRVD0_MASK) -#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK (0x100U) -#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT (8U) - -/* VSYNC_EDGE_IRQ - * 0b0..No Interrupt Request Pending. - * 0b1..Interrupt Request Pending. - */ - -#define LCDIF_CTRL1_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK) -#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK (0x200U) -#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT (9U) - -/* CUR_FRAME_DONE_IRQ - * 0b0..No Interrupt Request Pending. - * 0b1..Interrupt Request Pending. - */ - -#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK) -#define LCDIF_CTRL1_UNDERFLOW_IRQ_MASK (0x400U) -#define LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT (10U) - -/* UNDERFLOW_IRQ - * 0b0..No Interrupt Request Pending. - * 0b1..Interrupt Request Pending. - */ - -#define LCDIF_CTRL1_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_MASK) -#define LCDIF_CTRL1_OVERFLOW_IRQ_MASK (0x800U) -#define LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT (11U) - -/* OVERFLOW_IRQ - * 0b0..No Interrupt Request Pending. - * 0b1..Interrupt Request Pending. - */ - -#define LCDIF_CTRL1_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_MASK) -#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) -#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT (12U) -#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK) -#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) -#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) -#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK) -#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK (0x4000U) -#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT (14U) -#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK) -#define LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK (0x8000U) -#define LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT (15U) -#define LCDIF_CTRL1_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK) -#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xf0000U) -#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT (16U) -#define LCDIF_CTRL1_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK) -#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) -#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) -#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK) -#define LCDIF_CTRL1_FIFO_CLEAR_MASK (0x200000U) -#define LCDIF_CTRL1_FIFO_CLEAR_SHIFT (21U) -#define LCDIF_CTRL1_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_FIFO_CLEAR_MASK) -#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) -#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) -#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK) -#define LCDIF_CTRL1_INTERLACE_FIELDS_MASK (0x800000U) -#define LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT (23U) -#define LCDIF_CTRL1_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_INTERLACE_FIELDS_MASK) -#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) -#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT (24U) -#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK) -#define LCDIF_CTRL1_BM_ERROR_IRQ_MASK (0x2000000U) -#define LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT (25U) - -/* BM_ERROR_IRQ - * 0b0..No Interrupt Request Pending. - * 0b1..Interrupt Request Pending. - */ - -#define LCDIF_CTRL1_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_MASK) -#define LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK (0x4000000U) -#define LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT (26U) -#define LCDIF_CTRL1_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK) -#define LCDIF_CTRL1_CS_OUT_SELECT_MASK (0x40000000U) -#define LCDIF_CTRL1_CS_OUT_SELECT_SHIFT (30U) -#define LCDIF_CTRL1_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CS_OUT_SELECT_MASK) -#define LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK (0x80000000U) -#define LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT (31U) -#define LCDIF_CTRL1_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK) - -/* CTRL1_SET - LCDIF General Control1 Register */ - -#define LCDIF_CTRL1_SET_RSRVD0_MASK (0xf8U) -#define LCDIF_CTRL1_SET_RSRVD0_SHIFT (3U) -#define LCDIF_CTRL1_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RSRVD0_SHIFT)) & LCDIF_CTRL1_SET_RSRVD0_MASK) -#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK (0x100U) -#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT (8U) - -/* VSYNC_EDGE_IRQ - * 0b0..No Interrupt Request Pending. - * 0b1..Interrupt Request Pending. - */ - -#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK) -#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK (0x200U) -#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT (9U) - -/* CUR_FRAME_DONE_IRQ - * 0b0..No Interrupt Request Pending. - * 0b1..Interrupt Request Pending. - */ - -#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK) -#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK (0x400U) -#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT (10U) - -/* UNDERFLOW_IRQ - * 0b0..No Interrupt Request Pending. - * 0b1..Interrupt Request Pending. - */ - -#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK) -#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK (0x800U) -#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT (11U) - -/* OVERFLOW_IRQ - * 0b0..No Interrupt Request Pending. - * 0b1..Interrupt Request Pending. - */ - -#define LCDIF_CTRL1_SET_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK) -#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) -#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT (12U) -#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK) -#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) -#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) -#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK) -#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK (0x4000U) -#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT (14U) -#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK) -#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK (0x8000U) -#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT (15U) -#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK) -#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK (0xf0000U) -#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT (16U) -#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK) -#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) -#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) -#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK) -#define LCDIF_CTRL1_SET_FIFO_CLEAR_MASK (0x200000U) -#define LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT (21U) -#define LCDIF_CTRL1_SET_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_SET_FIFO_CLEAR_MASK) -#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) -#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) -#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK) -#define LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK (0x800000U) -#define LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT (23U) -#define LCDIF_CTRL1_SET_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK) -#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) -#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT (24U) -#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK) -#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK (0x2000000U) -#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT (25U) - -/* BM_ERROR_IRQ - * 0b0..No Interrupt Request Pending. - * 0b1..Interrupt Request Pending. - */ - -#define LCDIF_CTRL1_SET_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK) -#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK (0x4000000U) -#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT (26U) -#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK) -#define LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK (0x40000000U) -#define LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT (30U) -#define LCDIF_CTRL1_SET_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK) -#define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK (0x80000000U) -#define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT (31U) -#define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK) - -/* CTRL1_CLR - LCDIF General Control1 Register */ - -#define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xf8U) -#define LCDIF_CTRL1_CLR_RSRVD0_SHIFT (3U) -#define LCDIF_CTRL1_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK) -#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK (0x100U) -#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT (8U) - -/* VSYNC_EDGE_IRQ - * 0b0..No Interrupt Request Pending. - * 0b1..Interrupt Request Pending. - */ - -#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK) -#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK (0x200U) -#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT (9U) - -/* CUR_FRAME_DONE_IRQ - * 0b0..No Interrupt Request Pending. - * 0b1..Interrupt Request Pending. - */ - -#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK) -#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK (0x400U) -#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT (10U) - -/* UNDERFLOW_IRQ - * 0b0..No Interrupt Request Pending. - * 0b1..Interrupt Request Pending. - */ - -#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK) -#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK (0x800U) -#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT (11U) - -/* OVERFLOW_IRQ - * 0b0..No Interrupt Request Pending. - * 0b1..Interrupt Request Pending. - */ - -#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK) -#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) -#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT (12U) -#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK) -#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) -#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) -#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK) -#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK (0x4000U) -#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT (14U) -#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK) -#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK (0x8000U) -#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT (15U) -#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK) -#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK (0xf0000U) -#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT (16U) -#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK) -#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) -#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) -#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK) -#define LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK (0x200000U) -#define LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT (21U) -#define LCDIF_CTRL1_CLR_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK) -#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) -#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) -#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK) -#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK (0x800000U) -#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT (23U) -#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK) -#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) -#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT (24U) -#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK) -#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK (0x2000000U) -#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT (25U) - -/* BM_ERROR_IRQ - * 0b0..No Interrupt Request Pending. - * 0b1..Interrupt Request Pending. - */ - -#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK) -#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK (0x4000000U) -#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT (26U) -#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK) -#define LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK (0x40000000U) -#define LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT (30U) -#define LCDIF_CTRL1_CLR_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK) -#define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK (0x80000000U) -#define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT (31U) -#define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK) - -/* CTRL1_TOG - LCDIF General Control1 Register */ - -#define LCDIF_CTRL1_TOG_RSRVD0_MASK (0xf8U) -#define LCDIF_CTRL1_TOG_RSRVD0_SHIFT (3U) -#define LCDIF_CTRL1_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL1_TOG_RSRVD0_MASK) -#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK (0x100U) -#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT (8U) - -/* VSYNC_EDGE_IRQ - * 0b0..No Interrupt Request Pending. - * 0b1..Interrupt Request Pending. - */ - -#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK) -#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK (0x200U) -#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT (9U) - -/* CUR_FRAME_DONE_IRQ - * 0b0..No Interrupt Request Pending. - * 0b1..Interrupt Request Pending. - */ - -#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK) -#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK (0x400U) -#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT (10U) - -/* UNDERFLOW_IRQ - * 0b0..No Interrupt Request Pending. - * 0b1..Interrupt Request Pending. - */ - -#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK) -#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK (0x800U) -#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT (11U) - -/* OVERFLOW_IRQ - * 0b0..No Interrupt Request Pending. - * 0b1..Interrupt Request Pending. - */ - -#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK) -#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) -#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT (12U) -#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK) -#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) -#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) -#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK) -#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK (0x4000U) -#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT (14U) -#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK) -#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK (0x8000U) -#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT (15U) -#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK) -#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK (0xf0000U) -#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT (16U) -#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK) -#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) -#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) -#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK) -#define LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK (0x200000U) -#define LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT (21U) -#define LCDIF_CTRL1_TOG_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK) -#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) -#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) -#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK) -#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK (0x800000U) -#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT (23U) -#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK) -#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) -#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT (24U) -#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK) -#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK (0x2000000U) -#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT (25U) - -/* BM_ERROR_IRQ - * 0b0..No Interrupt Request Pending. - * 0b1..Interrupt Request Pending. - */ - -#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK) -#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK (0x4000000U) -#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT (26U) -#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK) -#define LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK (0x40000000U) -#define LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT (30U) -#define LCDIF_CTRL1_TOG_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK) -#define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK (0x80000000U) -#define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT (31U) -#define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK) - -/* CTRL2 - LCDIF General Control2 Register */ - -#define LCDIF_CTRL2_RSRVD0_MASK (0xfffU) -#define LCDIF_CTRL2_RSRVD0_SHIFT (0U) -#define LCDIF_CTRL2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD0_SHIFT)) & LCDIF_CTRL2_RSRVD0_MASK) -#define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7000U) -#define LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT (12U) - -/* EVEN_LINE_PATTERN - * 0b000..RGB - * 0b001..RBG - * 0b010..GBR - * 0b011..GRB - * 0b100..BRG - * 0b101..BGR - */ - -#define LCDIF_CTRL2_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK) -#define LCDIF_CTRL2_RSRVD3_MASK (0x8000U) -#define LCDIF_CTRL2_RSRVD3_SHIFT (15U) -#define LCDIF_CTRL2_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD3_SHIFT)) & LCDIF_CTRL2_RSRVD3_MASK) -#define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x70000U) -#define LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT (16U) - -/* ODD_LINE_PATTERN - * 0b000..RGB - * 0b001..RBG - * 0b010..GBR - * 0b011..GRB - * 0b100..BRG - * 0b101..BGR - */ - -#define LCDIF_CTRL2_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_ODD_LINE_PATTERN_MASK) -#define LCDIF_CTRL2_RSRVD4_MASK (0x80000U) -#define LCDIF_CTRL2_RSRVD4_SHIFT (19U) -#define LCDIF_CTRL2_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD4_SHIFT)) & LCDIF_CTRL2_RSRVD4_MASK) -#define LCDIF_CTRL2_BURST_LEN_8_MASK (0x100000U) -#define LCDIF_CTRL2_BURST_LEN_8_SHIFT (20U) -#define LCDIF_CTRL2_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_BURST_LEN_8_MASK) -#define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0xe00000U) -#define LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT (21U) - -/* OUTSTANDING_REQS - * 0b000..REQ_1 - * 0b001..REQ_2 - * 0b010..REQ_4 - * 0b011..REQ_8 - * 0b100..REQ_16 - */ - -#define LCDIF_CTRL2_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_OUTSTANDING_REQS_MASK) -#define LCDIF_CTRL2_RSRVD5_MASK (0xff000000U) -#define LCDIF_CTRL2_RSRVD5_SHIFT (24U) -#define LCDIF_CTRL2_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD5_SHIFT)) & LCDIF_CTRL2_RSRVD5_MASK) - -/* CTRL2_SET - LCDIF General Control2 Register */ - -#define LCDIF_CTRL2_SET_RSRVD0_MASK (0xfffU) -#define LCDIF_CTRL2_SET_RSRVD0_SHIFT (0U) -#define LCDIF_CTRL2_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD0_SHIFT)) & LCDIF_CTRL2_SET_RSRVD0_MASK) -#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK (0x7000U) -#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT (12U) - -/* EVEN_LINE_PATTERN - * 0b000..RGB - * 0b001..RBG - * 0b010..GBR - * 0b011..GRB - * 0b100..BRG - * 0b101..BGR - */ - -#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK) -#define LCDIF_CTRL2_SET_RSRVD3_MASK (0x8000U) -#define LCDIF_CTRL2_SET_RSRVD3_SHIFT (15U) -#define LCDIF_CTRL2_SET_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD3_SHIFT)) & LCDIF_CTRL2_SET_RSRVD3_MASK) -#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK (0x70000U) -#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT (16U) - -/* ODD_LINE_PATTERN - * 0b000..RGB - * 0b001..RBG - * 0b010..GBR - * 0b011..GRB - * 0b100..BRG - * 0b101..BGR - */ - -#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK) -#define LCDIF_CTRL2_SET_RSRVD4_MASK (0x80000U) -#define LCDIF_CTRL2_SET_RSRVD4_SHIFT (19U) -#define LCDIF_CTRL2_SET_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD4_SHIFT)) & LCDIF_CTRL2_SET_RSRVD4_MASK) -#define LCDIF_CTRL2_SET_BURST_LEN_8_MASK (0x100000U) -#define LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT (20U) -#define LCDIF_CTRL2_SET_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_SET_BURST_LEN_8_MASK) -#define LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK (0xe00000U) -#define LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT (21U) - -/* OUTSTANDING_REQS - * 0b000..REQ_1 - * 0b001..REQ_2 - * 0b010..REQ_4 - * 0b011..REQ_8 - * 0b100..REQ_16 - */ - -#define LCDIF_CTRL2_SET_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK) -#define LCDIF_CTRL2_SET_RSRVD5_MASK (0xff000000U) -#define LCDIF_CTRL2_SET_RSRVD5_SHIFT (24U) -#define LCDIF_CTRL2_SET_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD5_SHIFT)) & LCDIF_CTRL2_SET_RSRVD5_MASK) - -/* CTRL2_CLR - LCDIF General Control2 Register */ - -#define LCDIF_CTRL2_CLR_RSRVD0_MASK (0xfffU) -#define LCDIF_CTRL2_CLR_RSRVD0_SHIFT (0U) -#define LCDIF_CTRL2_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD0_MASK) -#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK (0x7000U) -#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT (12U) - -/* EVEN_LINE_PATTERN - * 0b000..RGB - * 0b001..RBG - * 0b010..GBR - * 0b011..GRB - * 0b100..BRG - * 0b101..BGR - */ - -#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK) -#define LCDIF_CTRL2_CLR_RSRVD3_MASK (0x8000U) -#define LCDIF_CTRL2_CLR_RSRVD3_SHIFT (15U) -#define LCDIF_CTRL2_CLR_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD3_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD3_MASK) -#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK (0x70000U) -#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT (16U) - -/* ODD_LINE_PATTERN - * 0b000..RGB - * 0b001..RBG - * 0b010..GBR - * 0b011..GRB - * 0b100..BRG - * 0b101..BGR - */ - -#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK) -#define LCDIF_CTRL2_CLR_RSRVD4_MASK (0x80000U) -#define LCDIF_CTRL2_CLR_RSRVD4_SHIFT (19U) -#define LCDIF_CTRL2_CLR_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD4_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD4_MASK) -#define LCDIF_CTRL2_CLR_BURST_LEN_8_MASK (0x100000U) -#define LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT (20U) -#define LCDIF_CTRL2_CLR_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_CLR_BURST_LEN_8_MASK) -#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK (0xe00000U) -#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT (21U) - -/* OUTSTANDING_REQS - * 0b000..REQ_1 - * 0b001..REQ_2 - * 0b010..REQ_4 - * 0b011..REQ_8 - * 0b100..REQ_16 - */ - -#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK) -#define LCDIF_CTRL2_CLR_RSRVD5_MASK (0xff000000U) -#define LCDIF_CTRL2_CLR_RSRVD5_SHIFT (24U) -#define LCDIF_CTRL2_CLR_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD5_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD5_MASK) - -/* CTRL2_TOG - LCDIF General Control2 Register */ - -#define LCDIF_CTRL2_TOG_RSRVD0_MASK (0xfffU) -#define LCDIF_CTRL2_TOG_RSRVD0_SHIFT (0U) -#define LCDIF_CTRL2_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD0_MASK) -#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK (0x7000U) -#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT (12U) - -/* EVEN_LINE_PATTERN - * 0b000..RGB - * 0b001..RBG - * 0b010..GBR - * 0b011..GRB - * 0b100..BRG - * 0b101..BGR - */ - -#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK) -#define LCDIF_CTRL2_TOG_RSRVD3_MASK (0x8000U) -#define LCDIF_CTRL2_TOG_RSRVD3_SHIFT (15U) -#define LCDIF_CTRL2_TOG_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD3_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD3_MASK) -#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK (0x70000U) -#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT (16U) - -/* ODD_LINE_PATTERN - * 0b000..RGB - * 0b001..RBG - * 0b010..GBR - * 0b011..GRB - * 0b100..BRG - * 0b101..BGR - */ - -#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK) -#define LCDIF_CTRL2_TOG_RSRVD4_MASK (0x80000U) -#define LCDIF_CTRL2_TOG_RSRVD4_SHIFT (19U) -#define LCDIF_CTRL2_TOG_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD4_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD4_MASK) -#define LCDIF_CTRL2_TOG_BURST_LEN_8_MASK (0x100000U) -#define LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT (20U) -#define LCDIF_CTRL2_TOG_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_TOG_BURST_LEN_8_MASK) -#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK (0xe00000U) -#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT (21U) - -/* OUTSTANDING_REQS - * 0b000..REQ_1 - * 0b001..REQ_2 - * 0b010..REQ_4 - * 0b011..REQ_8 - * 0b100..REQ_16 - */ - -#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK) -#define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xff000000U) -#define LCDIF_CTRL2_TOG_RSRVD5_SHIFT (24U) -#define LCDIF_CTRL2_TOG_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK) - -/* TRANSFER_COUNT - LCDIF Horizontal and Vertical Valid Data Count Register */ - -#define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xffffU) -#define LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT (0U) -#define LCDIF_TRANSFER_COUNT_H_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_H_COUNT_MASK) -#define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xffff0000U) -#define LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT (16U) -#define LCDIF_TRANSFER_COUNT_V_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_V_COUNT_MASK) - -/* CUR_BUF - LCD Interface Current Buffer Address Register */ - -#define LCDIF_CUR_BUF_ADDR_MASK (0xffffffffU) -#define LCDIF_CUR_BUF_ADDR_SHIFT (0U) -#define LCDIF_CUR_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CUR_BUF_ADDR_SHIFT)) & LCDIF_CUR_BUF_ADDR_MASK) - -/* NEXT_BUF - LCD Interface Next Buffer Address Register */ - -#define LCDIF_NEXT_BUF_ADDR_MASK (0xffffffffU) -#define LCDIF_NEXT_BUF_ADDR_SHIFT (0U) -#define LCDIF_NEXT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_NEXT_BUF_ADDR_SHIFT)) & LCDIF_NEXT_BUF_ADDR_MASK) - -/* VDCTRL0 - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ - -#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK (0x3ffffU) -#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT (0U) -#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK) -#define LCDIF_VDCTRL0_HALF_LINE_MODE_MASK (0x40000U) -#define LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT (18U) -#define LCDIF_VDCTRL0_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MODE_MASK) -#define LCDIF_VDCTRL0_HALF_LINE_MASK (0x80000U) -#define LCDIF_VDCTRL0_HALF_LINE_SHIFT (19U) -#define LCDIF_VDCTRL0_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MASK) -#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) -#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) -#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK) -#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK (0x200000U) -#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT (21U) -#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK) -#define LCDIF_VDCTRL0_RSRVD1_MASK (0xc00000U) -#define LCDIF_VDCTRL0_RSRVD1_SHIFT (22U) -#define LCDIF_VDCTRL0_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_RSRVD1_MASK) -#define LCDIF_VDCTRL0_ENABLE_POL_MASK (0x1000000U) -#define LCDIF_VDCTRL0_ENABLE_POL_SHIFT (24U) -#define LCDIF_VDCTRL0_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_ENABLE_POL_MASK) -#define LCDIF_VDCTRL0_DOTCLK_POL_MASK (0x2000000U) -#define LCDIF_VDCTRL0_DOTCLK_POL_SHIFT (25U) -#define LCDIF_VDCTRL0_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_DOTCLK_POL_MASK) -#define LCDIF_VDCTRL0_HSYNC_POL_MASK (0x4000000U) -#define LCDIF_VDCTRL0_HSYNC_POL_SHIFT (26U) -#define LCDIF_VDCTRL0_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_HSYNC_POL_MASK) -#define LCDIF_VDCTRL0_VSYNC_POL_MASK (0x8000000U) -#define LCDIF_VDCTRL0_VSYNC_POL_SHIFT (27U) -#define LCDIF_VDCTRL0_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_VSYNC_POL_MASK) -#define LCDIF_VDCTRL0_ENABLE_PRESENT_MASK (0x10000000U) -#define LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT (28U) -#define LCDIF_VDCTRL0_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_ENABLE_PRESENT_MASK) -#define LCDIF_VDCTRL0_RSRVD2_MASK (0xe0000000U) -#define LCDIF_VDCTRL0_RSRVD2_SHIFT (29U) -#define LCDIF_VDCTRL0_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_RSRVD2_MASK) - -/* VDCTRL0_SET - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ - -#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK (0x3ffffU) -#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT (0U) -#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK) -#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK (0x40000U) -#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT (18U) -#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK) -#define LCDIF_VDCTRL0_SET_HALF_LINE_MASK (0x80000U) -#define LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT (19U) -#define LCDIF_VDCTRL0_SET_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MASK) -#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) -#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) -#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK) -#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK (0x200000U) -#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT (21U) -#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK) -#define LCDIF_VDCTRL0_SET_RSRVD1_MASK (0xc00000U) -#define LCDIF_VDCTRL0_SET_RSRVD1_SHIFT (22U) -#define LCDIF_VDCTRL0_SET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD1_MASK) -#define LCDIF_VDCTRL0_SET_ENABLE_POL_MASK (0x1000000U) -#define LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT (24U) -#define LCDIF_VDCTRL0_SET_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_POL_MASK) -#define LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK (0x2000000U) -#define LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT (25U) -#define LCDIF_VDCTRL0_SET_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK) -#define LCDIF_VDCTRL0_SET_HSYNC_POL_MASK (0x4000000U) -#define LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT (26U) -#define LCDIF_VDCTRL0_SET_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_HSYNC_POL_MASK) -#define LCDIF_VDCTRL0_SET_VSYNC_POL_MASK (0x8000000U) -#define LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT (27U) -#define LCDIF_VDCTRL0_SET_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_POL_MASK) -#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK (0x10000000U) -#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT (28U) -#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK) -#define LCDIF_VDCTRL0_SET_RSRVD2_MASK (0xe0000000U) -#define LCDIF_VDCTRL0_SET_RSRVD2_SHIFT (29U) -#define LCDIF_VDCTRL0_SET_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD2_MASK) - -/* VDCTRL0_CLR - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ - -#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK (0x3ffffU) -#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT (0U) -#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK) -#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK (0x40000U) -#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT (18U) -#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK) -#define LCDIF_VDCTRL0_CLR_HALF_LINE_MASK (0x80000U) -#define LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT (19U) -#define LCDIF_VDCTRL0_CLR_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MASK) -#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) -#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) -#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK) -#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK (0x200000U) -#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT (21U) -#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK) -#define LCDIF_VDCTRL0_CLR_RSRVD1_MASK (0xc00000U) -#define LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT (22U) -#define LCDIF_VDCTRL0_CLR_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD1_MASK) -#define LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK (0x1000000U) -#define LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT (24U) -#define LCDIF_VDCTRL0_CLR_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK) -#define LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK (0x2000000U) -#define LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT (25U) -#define LCDIF_VDCTRL0_CLR_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK) -#define LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK (0x4000000U) -#define LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT (26U) -#define LCDIF_VDCTRL0_CLR_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK) -#define LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK (0x8000000U) -#define LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT (27U) -#define LCDIF_VDCTRL0_CLR_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK) -#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK (0x10000000U) -#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT (28U) -#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK) -#define LCDIF_VDCTRL0_CLR_RSRVD2_MASK (0xe0000000U) -#define LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT (29U) -#define LCDIF_VDCTRL0_CLR_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD2_MASK) - -/* VDCTRL0_TOG - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ - -#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK (0x3ffffU) -#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT (0U) -#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK) -#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK (0x40000U) -#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT (18U) -#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK) -#define LCDIF_VDCTRL0_TOG_HALF_LINE_MASK (0x80000U) -#define LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT (19U) -#define LCDIF_VDCTRL0_TOG_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MASK) -#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) -#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) -#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK) -#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK (0x200000U) -#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT (21U) -#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK) -#define LCDIF_VDCTRL0_TOG_RSRVD1_MASK (0xc00000U) -#define LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT (22U) -#define LCDIF_VDCTRL0_TOG_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD1_MASK) -#define LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK (0x1000000U) -#define LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT (24U) -#define LCDIF_VDCTRL0_TOG_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK) -#define LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK (0x2000000U) -#define LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT (25U) -#define LCDIF_VDCTRL0_TOG_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK) -#define LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK (0x4000000U) -#define LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT (26U) -#define LCDIF_VDCTRL0_TOG_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK) -#define LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK (0x8000000U) -#define LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT (27U) -#define LCDIF_VDCTRL0_TOG_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK) -#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK (0x10000000U) -#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT (28U) -#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK) -#define LCDIF_VDCTRL0_TOG_RSRVD2_MASK (0xe0000000U) -#define LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT (29U) -#define LCDIF_VDCTRL0_TOG_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD2_MASK) - -/* VDCTRL1 - LCDIF VSYNC Mode and Dotclk Mode Control Register1 */ - -#define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK (0xffffffffU) -#define LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT (0U) -#define LCDIF_VDCTRL1_VSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL1_VSYNC_PERIOD_MASK) - -/* VDCTRL2 - LCDIF VSYNC Mode and Dotclk Mode Control Register2 */ - -#define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK (0x3ffffU) -#define LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT (0U) -#define LCDIF_VDCTRL2_HSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PERIOD_MASK) -#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xfffc0000U) -#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT (18U) -#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK) - -/* VDCTRL3 - LCDIF VSYNC Mode and Dotclk Mode Control Register3 */ - -#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xffffU) -#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT (0U) -#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK) -#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xfff0000U) -#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT (16U) -#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK) -#define LCDIF_VDCTRL3_VSYNC_ONLY_MASK (0x10000000U) -#define LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT (28U) -#define LCDIF_VDCTRL3_VSYNC_ONLY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT)) & LCDIF_VDCTRL3_VSYNC_ONLY_MASK) -#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK (0x20000000U) -#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT (29U) -#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT)) & LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK) -#define LCDIF_VDCTRL3_RSRVD0_MASK (0xc0000000U) -#define LCDIF_VDCTRL3_RSRVD0_SHIFT (30U) -#define LCDIF_VDCTRL3_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK) - -/* VDCTRL4 - LCDIF VSYNC Mode and Dotclk Mode Control Register4 */ - -#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK (0x3ffffU) -#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT (0U) -#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK) -#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK (0x40000U) -#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT (18U) -#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT)) & LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK) -#define LCDIF_VDCTRL4_RSRVD0_MASK (0x1ff80000U) -#define LCDIF_VDCTRL4_RSRVD0_SHIFT (19U) -#define LCDIF_VDCTRL4_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_RSRVD0_SHIFT)) & LCDIF_VDCTRL4_RSRVD0_MASK) -#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0xe0000000U) -#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT (29U) -#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK) - -/* BM_ERROR_STAT - Bus Master Error Status Register */ - -#define LCDIF_BM_ERROR_STAT_ADDR_MASK (0xffffffffU) -#define LCDIF_BM_ERROR_STAT_ADDR_SHIFT (0U) -#define LCDIF_BM_ERROR_STAT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_BM_ERROR_STAT_ADDR_SHIFT)) & LCDIF_BM_ERROR_STAT_ADDR_MASK) - -/* CRC_STAT - CRC Status Register */ - -#define LCDIF_CRC_STAT_CRC_VALUE_MASK (0xffffffffU) -#define LCDIF_CRC_STAT_CRC_VALUE_SHIFT (0U) -#define LCDIF_CRC_STAT_CRC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CRC_STAT_CRC_VALUE_SHIFT)) & LCDIF_CRC_STAT_CRC_VALUE_MASK) - -/* STAT - LCD Interface Status Register */ - -#define LCDIF_STAT_LFIFO_COUNT_MASK (0x1ffU) -#define LCDIF_STAT_LFIFO_COUNT_SHIFT (0U) -#define LCDIF_STAT_LFIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_COUNT_SHIFT)) & LCDIF_STAT_LFIFO_COUNT_MASK) -#define LCDIF_STAT_RSRVD0_MASK (0x1fffe00U) -#define LCDIF_STAT_RSRVD0_SHIFT (9U) -#define LCDIF_STAT_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_RSRVD0_SHIFT)) & LCDIF_STAT_RSRVD0_MASK) -#define LCDIF_STAT_TXFIFO_EMPTY_MASK (0x4000000U) -#define LCDIF_STAT_TXFIFO_EMPTY_SHIFT (26U) -#define LCDIF_STAT_TXFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_EMPTY_SHIFT)) & LCDIF_STAT_TXFIFO_EMPTY_MASK) -#define LCDIF_STAT_TXFIFO_FULL_MASK (0x8000000U) -#define LCDIF_STAT_TXFIFO_FULL_SHIFT (27U) -#define LCDIF_STAT_TXFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_FULL_SHIFT)) & LCDIF_STAT_TXFIFO_FULL_MASK) -#define LCDIF_STAT_LFIFO_EMPTY_MASK (0x10000000U) -#define LCDIF_STAT_LFIFO_EMPTY_SHIFT (28U) -#define LCDIF_STAT_LFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_EMPTY_SHIFT)) & LCDIF_STAT_LFIFO_EMPTY_MASK) -#define LCDIF_STAT_LFIFO_FULL_MASK (0x20000000U) -#define LCDIF_STAT_LFIFO_FULL_SHIFT (29U) -#define LCDIF_STAT_LFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_FULL_SHIFT)) & LCDIF_STAT_LFIFO_FULL_MASK) -#define LCDIF_STAT_DMA_REQ_MASK (0x40000000U) -#define LCDIF_STAT_DMA_REQ_SHIFT (30U) -#define LCDIF_STAT_DMA_REQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_DMA_REQ_SHIFT)) & LCDIF_STAT_DMA_REQ_MASK) -#define LCDIF_STAT_PRESENT_MASK (0x80000000U) -#define LCDIF_STAT_PRESENT_SHIFT (31U) -#define LCDIF_STAT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_PRESENT_SHIFT)) & LCDIF_STAT_PRESENT_MASK) - -/* THRES - LCDIF Threshold Register */ - -#define LCDIF_THRES_PANIC_MASK (0x1ffU) -#define LCDIF_THRES_PANIC_SHIFT (0U) -#define LCDIF_THRES_PANIC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_PANIC_SHIFT)) & LCDIF_THRES_PANIC_MASK) -#define LCDIF_THRES_RSRVD1_MASK (0xfe00U) -#define LCDIF_THRES_RSRVD1_SHIFT (9U) -#define LCDIF_THRES_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD1_SHIFT)) & LCDIF_THRES_RSRVD1_MASK) -#define LCDIF_THRES_FASTCLOCK_MASK (0x1ff0000U) -#define LCDIF_THRES_FASTCLOCK_SHIFT (16U) -#define LCDIF_THRES_FASTCLOCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_FASTCLOCK_SHIFT)) & LCDIF_THRES_FASTCLOCK_MASK) -#define LCDIF_THRES_RSRVD2_MASK (0xfe000000U) -#define LCDIF_THRES_RSRVD2_SHIFT (25U) -#define LCDIF_THRES_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD2_SHIFT)) & LCDIF_THRES_RSRVD2_MASK) - -/* PIGEONCTRL0 - LCDIF Pigeon Mode Control0 Register */ - -#define LCDIF_PIGEONCTRL0_FD_PERIOD_MASK (0xfffU) -#define LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT (0U) -#define LCDIF_PIGEONCTRL0_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_FD_PERIOD_MASK) -#define LCDIF_PIGEONCTRL0_LD_PERIOD_MASK (0xfff0000U) -#define LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT (16U) -#define LCDIF_PIGEONCTRL0_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_LD_PERIOD_MASK) - -/* PIGEONCTRL0_SET - LCDIF Pigeon Mode Control0 Register */ - -#define LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK (0xfffU) -#define LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT (0U) -#define LCDIF_PIGEONCTRL0_SET_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK) -#define LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK (0xfff0000U) -#define LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT (16U) -#define LCDIF_PIGEONCTRL0_SET_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK) - -/* PIGEONCTRL0_CLR - LCDIF Pigeon Mode Control0 Register */ - -#define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK (0xfffU) -#define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT (0U) -#define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK) -#define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK (0xfff0000U) -#define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT (16U) -#define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK) - -/* PIGEONCTRL0_TOG - LCDIF Pigeon Mode Control0 Register */ - -#define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK (0xfffU) -#define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT (0U) -#define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK) -#define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK (0xfff0000U) -#define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT (16U) -#define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK) - -/* PIGEONCTRL1 - LCDIF Pigeon Mode Control1 Register */ - -#define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK (0xfffU) -#define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT (0U) -#define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK) -#define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK (0xfff0000U) -#define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT (16U) -#define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK) - -/* PIGEONCTRL1_SET - LCDIF Pigeon Mode Control1 Register */ - -#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK (0xfffU) -#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT (0U) -#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK) -#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK (0xfff0000U) -#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT (16U) -#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK) - -/* PIGEONCTRL1_CLR - LCDIF Pigeon Mode Control1 Register */ - -#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK (0xfffU) -#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT (0U) -#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK) -#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK (0xfff0000U) -#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT (16U) -#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK) - -/* PIGEONCTRL1_TOG - LCDIF Pigeon Mode Control1 Register */ - -#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK (0xfffU) -#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT (0U) -#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK) -#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK (0xfff0000U) -#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT (16U) -#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK) - -/* PIGEONCTRL2 - LCDIF Pigeon Mode Control2 Register */ - -#define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK (0x1U) -#define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT (0U) -#define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK) -#define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK (0x2U) -#define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT (1U) -#define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK) - -/* PIGEONCTRL2_SET - LCDIF Pigeon Mode Control2 Register */ - -#define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK (0x1U) -#define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT (0U) -#define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK) -#define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK (0x2U) -#define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT (1U) -#define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK) - -/* PIGEONCTRL2_CLR - LCDIF Pigeon Mode Control2 Register */ - -#define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK (0x1U) -#define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT (0U) -#define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK) -#define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK (0x2U) -#define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT (1U) -#define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK) - -/* PIGEONCTRL2_TOG - LCDIF Pigeon Mode Control2 Register */ - -#define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK (0x1U) -#define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT (0U) -#define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK) -#define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK (0x2U) -#define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT (1U) -#define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK) - -/* PIGEON_0 - Panel Interface Signal Generator Register */ - -#define LCDIF_PIGEON_0_EN_MASK (0x1U) -#define LCDIF_PIGEON_0_EN_SHIFT (0U) -#define LCDIF_PIGEON_0_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_EN_SHIFT)) & LCDIF_PIGEON_0_EN_MASK) -#define LCDIF_PIGEON_0_POL_MASK (0x2U) -#define LCDIF_PIGEON_0_POL_SHIFT (1U) - -/* POL - * 0b0..Normal Signal (Active high) - * 0b1..Inverted signal (Active low) - */ - -#define LCDIF_PIGEON_0_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_POL_SHIFT)) & LCDIF_PIGEON_0_POL_MASK) -#define LCDIF_PIGEON_0_INC_SEL_MASK (0xcU) -#define LCDIF_PIGEON_0_INC_SEL_SHIFT (2U) - -/* INC_SEL - * 0b00..pclk - * 0b01..Line start pulse - * 0b10..Frame start pulse - * 0b11..Use another signal as tick event - */ - -#define LCDIF_PIGEON_0_INC_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_INC_SEL_SHIFT)) & LCDIF_PIGEON_0_INC_SEL_MASK) -#define LCDIF_PIGEON_0_OFFSET_MASK (0xf0U) -#define LCDIF_PIGEON_0_OFFSET_SHIFT (4U) -#define LCDIF_PIGEON_0_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_OFFSET_SHIFT)) & LCDIF_PIGEON_0_OFFSET_MASK) -#define LCDIF_PIGEON_0_MASK_CNT_SEL_MASK (0xf00U) -#define LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT (8U) - -/* MASK_CNT_SEL - * 0b0000..pclk counter within one hscan state - * 0b0001..pclk cycle within one hscan state - * 0b0010..line counter within one vscan state - * 0b0011..line cycle within one vscan state - * 0b0100..frame counter - * 0b0101..frame cycle - * 0b0110..horizontal counter (pclk counter within one line ) - * 0b0111..vertical counter (line counter within one frame) - */ - -#define LCDIF_PIGEON_0_MASK_CNT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_SEL_MASK) -#define LCDIF_PIGEON_0_MASK_CNT_MASK (0xfff000U) -#define LCDIF_PIGEON_0_MASK_CNT_SHIFT (12U) -#define LCDIF_PIGEON_0_MASK_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_MASK) -#define LCDIF_PIGEON_0_STATE_MASK_MASK (0xff000000U) -#define LCDIF_PIGEON_0_STATE_MASK_SHIFT (24U) - -/* STATE_MASK - * 0b00000001..FRAME SYNC - * 0b00000010..FRAME BEGIN - * 0b00000100..FRAME DATA - * 0b00001000..FRAME END - * 0b00010000..LINE SYNC - * 0b00100000..LINE BEGIN - * 0b01000000..LINE DATA - * 0b10000000..LINE END - */ - -#define LCDIF_PIGEON_0_STATE_MASK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_STATE_MASK_SHIFT)) & LCDIF_PIGEON_0_STATE_MASK_MASK) - -/* The count of LCDIF_PIGEON_0 */ - -#define LCDIF_PIGEON_0_COUNT (12U) - -/* PIGEON_1 - Panel Interface Signal Generator Register */ - -#define LCDIF_PIGEON_1_SET_CNT_MASK (0xffffU) -#define LCDIF_PIGEON_1_SET_CNT_SHIFT (0U) - -/* SET_CNT - * 0b0000000000000000..Start as active - */ - -#define LCDIF_PIGEON_1_SET_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_SET_CNT_SHIFT)) & LCDIF_PIGEON_1_SET_CNT_MASK) -#define LCDIF_PIGEON_1_CLR_CNT_MASK (0xffff0000U) -#define LCDIF_PIGEON_1_CLR_CNT_SHIFT (16U) - -/* CLR_CNT - * 0b0000000000000000..Keep active until mask off - */ - -#define LCDIF_PIGEON_1_CLR_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_CLR_CNT_SHIFT)) & LCDIF_PIGEON_1_CLR_CNT_MASK) - -/* The count of LCDIF_PIGEON_1 */ - -#define LCDIF_PIGEON_1_COUNT (12U) - -/* PIGEON_2 - Panel Interface Signal Generator Register */ - -#define LCDIF_PIGEON_2_SIG_LOGIC_MASK (0xfU) -#define LCDIF_PIGEON_2_SIG_LOGIC_SHIFT (0U) - -/* SIG_LOGIC - * 0b0000..No logic operation - * 0b0001..sigout = sig_another AND this_sig - * 0b0010..sigout = sig_another OR this_sig - * 0b0011..mask = sig_another AND other_masks - */ - -#define LCDIF_PIGEON_2_SIG_LOGIC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_LOGIC_SHIFT)) & LCDIF_PIGEON_2_SIG_LOGIC_MASK) -#define LCDIF_PIGEON_2_SIG_ANOTHER_MASK (0x1f0U) -#define LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT (4U) - -/* SIG_ANOTHER - * 0b00000..Keep active until mask off - */ - -#define LCDIF_PIGEON_2_SIG_ANOTHER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT)) & LCDIF_PIGEON_2_SIG_ANOTHER_MASK) -#define LCDIF_PIGEON_2_RSVD_MASK (0xfffffe00U) -#define LCDIF_PIGEON_2_RSVD_SHIFT (9U) -#define LCDIF_PIGEON_2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_RSVD_SHIFT)) & LCDIF_PIGEON_2_RSVD_MASK) - -/* The count of LCDIF_PIGEON_2 */ - -#define LCDIF_PIGEON_2_COUNT (12U) - -/* LUT_CTRL - Lookup Table Data Register. */ - -#define LCDIF_LUT_CTRL_LUT_BYPASS_MASK (0x1U) -#define LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT (0U) -#define LCDIF_LUT_CTRL_LUT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT)) & LCDIF_LUT_CTRL_LUT_BYPASS_MASK) - -/* LUT0_ADDR - Lookup Table Control Register. */ - -#define LCDIF_LUT0_ADDR_ADDR_MASK (0xffU) -#define LCDIF_LUT0_ADDR_ADDR_SHIFT (0U) -#define LCDIF_LUT0_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_ADDR_ADDR_SHIFT)) & LCDIF_LUT0_ADDR_ADDR_MASK) - -/* LUT0_DATA - Lookup Table Data Register. */ - -#define LCDIF_LUT0_DATA_DATA_MASK (0xffffffffU) -#define LCDIF_LUT0_DATA_DATA_SHIFT (0U) -#define LCDIF_LUT0_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_DATA_DATA_SHIFT)) & LCDIF_LUT0_DATA_DATA_MASK) - -/* LUT1_ADDR - Lookup Table Control Register. */ - -#define LCDIF_LUT1_ADDR_ADDR_MASK (0xffU) -#define LCDIF_LUT1_ADDR_ADDR_SHIFT (0U) -#define LCDIF_LUT1_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_ADDR_ADDR_SHIFT)) & LCDIF_LUT1_ADDR_ADDR_MASK) - -/* LUT1_DATA - Lookup Table Data Register. */ - -#define LCDIF_LUT1_DATA_DATA_MASK (0xffffffffU) -#define LCDIF_LUT1_DATA_DATA_SHIFT (0U) -#define LCDIF_LUT1_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_DATA_DATA_SHIFT)) & LCDIF_LUT1_DATA_DATA_MASK) - -#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_LCD_H */ diff --git a/arch/arm/src/imxrt/chip/imxrt_lpi2c.h b/arch/arm/src/imxrt/chip/imxrt_lpi2c.h deleted file mode 100644 index a7d15b0b549..00000000000 --- a/arch/arm/src/imxrt/chip/imxrt_lpi2c.h +++ /dev/null @@ -1,622 +0,0 @@ -/******************************************************************************************** - * arch/arm/src/imxrt/imxrt_lpi2c.h - * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Ivan Ucherdzhiev - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ********************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_LPI2C_H -#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_LPI2C_H - -/******************************************************************************************** - * Included Files - ********************************************************************************************/ - -#include - -/******************************************************************************************** - * Pre-processor Definitions - ********************************************************************************************/ - -/* Register offsets *************************************************************************/ - -#define IMXRT_LPI2C_VERID_OFFSET 0x0000 /* Version ID Register offset */ -#define IMXRT_LPI2C_PARAM_OFFSET 0x0004 /* Parameter Register offset */ -#define IMXRT_LPI2C_MCR_OFFSET 0x0010 /* Master Control Register offset */ -#define IMXRT_LPI2C_MSR_OFFSET 0x0014 /* Master Status Register offset */ -#define IMXRT_LPI2C_MIER_OFFSET 0x0018 /* Master Interrupt Enable Register offset */ -#define IMXRT_LPI2C_MDER_OFFSET 0x001c /* Master DMA Enable Register offset */ -#define IMXRT_LPI2C_MCFGR0_OFFSET 0x0020 /* Master Config Register 0 offset */ -#define IMXRT_LPI2C_MCFGR1_OFFSET 0x0024 /* Master Config Register 1 offset */ -#define IMXRT_LPI2C_MCFGR2_OFFSET 0x0028 /* Master Config Register 2 offset */ -#define IMXRT_LPI2C_MCFGR3_OFFSET 0x002c /* Master Config Register 3 offset */ -#define IMXRT_LPI2C_MDMR_OFFSET 0x0040 /* Master Data Match Register offset */ -#define IMXRT_LPI2C_MCCR0_OFFSET 0x0048 /* Master Clock Configuration Register 0 offset */ -#define IMXRT_LPI2C_MCCR1_OFFSET 0x0050 /* Master Clock Configuration Register 1 offset */ -#define IMXRT_LPI2C_MFCR_OFFSET 0x0058 /* Master FIFO Control Register offset */ -#define IMXRT_LPI2C_MFSR_OFFSET 0x005C /* Master FIFO Status Register offset */ -#define IMXRT_LPI2C_MTDR_OFFSET 0x0060 /* Master Transmit Data Register offset */ -#define IMXRT_LPI2C_MRDR_OFFSET 0x0070 /* Master Receive Data Register offset */ -#define IMXRT_LPI2C_SCR_OFFSET 0x0110 /* Slave Control Register offset */ -#define IMXRT_LPI2C_SSR_OFFSET 0x0114 /* Slave Status Register offset */ -#define IMXRT_LPI2C_SIER_OFFSET 0x0118 /* Slave Interrupt Enable Register offset */ -#define IMXRT_LPI2C_SDER_OFFSET 0x011c /* Slave DMA Enable Register offset */ -#define IMXRT_LPI2C_SCFGR1_OFFSET 0x0124 /* Slave Config Register 1 offset */ -#define IMXRT_LPI2C_SCFGR2_OFFSET 0x0128 /* Slave Config Register 2 offset */ -#define IMXRT_LPI2C_SAMR_OFFSET 0x0140 /* Slave Address Match Register offset */ -#define IMXRT_LPI2C_SASR_OFFSET 0x0150 /* Slave Address Status Register offset */ -#define IMXRT_LPI2C_STAR_OFFSET 0x0154 /* Slave Transmit ACK Register offset */ -#define IMXRT_LPI2C_STDR_OFFSET 0x0160 /* Slave Transmit Data Register offset */ -#define IMXRT_LPI2C_SRDR_OFFSET 0x0170 /* Slave Receive Data Register offset */ - -/* Register addresses ***********************************************************************/ - -/* LPI2C1 Registers */ - -#define IMXRT_LPI2C1_VERID (IMXRT_LPI2C1_BASE + IMXRT_LPI2C_VERID_OFFSET) /* Version ID Register */ -#define IMXRT_LPI2C1_PARAM (IMXRT_LPI2C1_BASE + IMXRT_LPI2C_PARAM_OFFSET) /* Parameter Register */ -#define IMXRT_LPI2C1_MCR (IMXRT_LPI2C1_BASE + IMXRT_LPI2C_MCR_OFFSET) /* Master Control Register */ -#define IMXRT_LPI2C1_MSR (IMXRT_LPI2C1_BASE + IMXRT_LPI2C_MSR_OFFSET) /* Master Status Register */ -#define IMXRT_LPI2C1_MIER (IMXRT_LPI2C1_BASE + IMXRT_LPI2C_MIER_OFFSET) /* Master Interrupt Enable Register */ -#define IMXRT_LPI2C1_MDER (IMXRT_LPI2C1_BASE + IMXRT_LPI2C_MDER_OFFSET) /* Master DMA Enable Register */ -#define IMXRT_LPI2C1_MCFGR0 (IMXRT_LPI2C1_BASE + IMXRT_LPI2C_MCFGR0_OFFSET) /* Master Config Register 0 */ -#define IMXRT_LPI2C1_MCFGR1 (IMXRT_LPI2C1_BASE + IMXRT_LPI2C_MCFGR1_OFFSET) /* Master Config Register 1 */ -#define IMXRT_LPI2C1_MCFGR2 (IMXRT_LPI2C1_BASE + IMXRT_LPI2C_MCFGR2_OFFSET) /* Master Config Register 2 */ -#define IMXRT_LPI2C1_MCFGR3 (IMXRT_LPI2C1_BASE + IMXRT_LPI2C_MCFGR3_OFFSET) /* Master Config Register 3 */ -#define IMXRT_LPI2C1_MDMR (IMXRT_LPI2C1_BASE + IMXRT_LPI2C_MDMR_OFFSET) /* Master Data Match Register */ -#define IMXRT_LPI2C1_MCCR0 (IMXRT_LPI2C1_BASE + IMXRT_LPI2C_MCCR0_OFFSET) /* Master Clock Configuration Register 0 */ -#define IMXRT_LPI2C1_MCCR1 (IMXRT_LPI2C1_BASE + IMXRT_LPI2C_MCCR1_OFFSET) /* Master Clock Configuration Register 1 */ -#define IMXRT_LPI2C1_MFCR (IMXRT_LPI2C1_BASE + IMXRT_LPI2C_MFCR_OFFSET) /* Master FIFO Control Register */ -#define IMXRT_LPI2C1_MFSR (IMXRT_LPI2C1_BASE + IMXRT_LPI2C_MFSR_OFFSET) /* Master FIFO Status Register */ -#define IMXRT_LPI2C1_MTDR (IMXRT_LPI2C1_BASE + IMXRT_LPI2C_MTDR_OFFSET) /* Master Transmit Data Register */ -#define IMXRT_LPI2C1_MRDR (IMXRT_LPI2C1_BASE + IMXRT_LPI2C_MRDR_OFFSET) /* Master Receive Data Register */ -#define IMXRT_LPI2C1_SCR (IMXRT_LPI2C1_BASE + IMXRT_LPI2C_SCR_OFFSET) /* Slave Control Register */ -#define IMXRT_LPI2C1_SSR (IMXRT_LPI2C1_BASE + IMXRT_LPI2C_SSR_OFFSET) /* Slave Status Register */ -#define IMXRT_LPI2C1_SIER (IMXRT_LPI2C1_BASE + IMXRT_LPI2C_SIER_OFFSET) /* Slave Interrupt Enable Register */ -#define IMXRT_LPI2C1_SDER (IMXRT_LPI2C1_BASE + IMXRT_LPI2C_SDER_OFFSET) /* Slave DMA Enable Register */ -#define IMXRT_LPI2C1_SCFGR1 (IMXRT_LPI2C1_BASE + IMXRT_LPI2C_SCFGR1_OFFSET) /* Slave Config Register 1 */ -#define IMXRT_LPI2C1_SCFGR2 (IMXRT_LPI2C1_BASE + IMXRT_LPI2C_SCFGR2_OFFSET) /* Slave Config Register 2 */ -#define IMXRT_LPI2C1_SAMR (IMXRT_LPI2C1_BASE + IMXRT_LPI2C_SAMR_OFFSET) /* Slave Address Match Register */ -#define IMXRT_LPI2C1_SASR (IMXRT_LPI2C1_BASE + IMXRT_LPI2C_SASR_OFFSET) /* Slave Address Status Register */ -#define IMXRT_LPI2C1_STAR (IMXRT_LPI2C1_BASE + IMXRT_LPI2C_STAR_OFFSET) /* Slave Transmit ACK Register */ -#define IMXRT_LPI2C1_STDR (IMXRT_LPI2C1_BASE + IMXRT_LPI2C_STDR_OFFSET) /* Slave Transmit Data Register */ -#define IMXRT_LPI2C1_SRDR (IMXRT_LPI2C1_BASE + IMXRT_LPI2C_SRDR_OFFSET) /* Slave Receive Data Register */ - -/* LPI2C2 Registers */ - -#define IMXRT_LPI2C2_VERID (IMXRT_LPI2C2_BASE + IMXRT_LPI2C_VERID_OFFSET) /* Version ID Register */ -#define IMXRT_LPI2C2_PARAM (IMXRT_LPI2C2_BASE + IMXRT_LPI2C_PARAM_OFFSET) /* Parameter Register */ -#define IMXRT_LPI2C2_MCR (IMXRT_LPI2C2_BASE + IMXRT_LPI2C_MCR_OFFSET) /* Master Control Register */ -#define IMXRT_LPI2C2_MSR (IMXRT_LPI2C2_BASE + IMXRT_LPI2C_MSR_OFFSET) /* Master Status Register */ -#define IMXRT_LPI2C2_MIER (IMXRT_LPI2C2_BASE + IMXRT_LPI2C_MIER_OFFSET) /* Master Interrupt Enable Register */ -#define IMXRT_LPI2C2_MDER (IMXRT_LPI2C2_BASE + IMXRT_LPI2C_MDER_OFFSET) /* Master DMA Enable Register */ -#define IMXRT_LPI2C2_MCFGR0 (IMXRT_LPI2C2_BASE + IMXRT_LPI2C_MCFGR0_OFFSET) /* Master Config Register 0 */ -#define IMXRT_LPI2C2_MCFGR1 (IMXRT_LPI2C2_BASE + IMXRT_LPI2C_MCFGR1_OFFSET) /* Master Config Register 1 */ -#define IMXRT_LPI2C2_MCFGR2 (IMXRT_LPI2C2_BASE + IMXRT_LPI2C_MCFGR2_OFFSET) /* Master Config Register 2 */ -#define IMXRT_LPI2C2_MCFGR3 (IMXRT_LPI2C2_BASE + IMXRT_LPI2C_MCFGR3_OFFSET) /* Master Config Register 3 */ -#define IMXRT_LPI2C2_MDMR (IMXRT_LPI2C2_BASE + IMXRT_LPI2C_MDMR_OFFSET) /* Master Data Match Register */ -#define IMXRT_LPI2C2_MCCR0 (IMXRT_LPI2C2_BASE + IMXRT_LPI2C_MCCR0_OFFSET) /* Master Clock Configuration Register 0 */ -#define IMXRT_LPI2C2_MCCR1 (IMXRT_LPI2C2_BASE + IMXRT_LPI2C_MCCR1_OFFSET) /* Master Clock Configuration Register 1 */ -#define IMXRT_LPI2C2_MFCR (IMXRT_LPI2C2_BASE + IMXRT_LPI2C_MFCR_OFFSET) /* Master FIFO Control Register */ -#define IMXRT_LPI2C2_MFSR (IMXRT_LPI2C2_BASE + IMXRT_LPI2C_MFSR_OFFSET) /* Master FIFO Status Register */ -#define IMXRT_LPI2C2_MTDR (IMXRT_LPI2C2_BASE + IMXRT_LPI2C_MTDR_OFFSET) /* Master Transmit Data Register */ -#define IMXRT_LPI2C2_MRDR (IMXRT_LPI2C2_BASE + IMXRT_LPI2C_MRDR_OFFSET) /* Master Receive Data Register */ -#define IMXRT_LPI2C2_SCR (IMXRT_LPI2C2_BASE + IMXRT_LPI2C_SCR_OFFSET) /* Slave Control Register */ -#define IMXRT_LPI2C2_SSR (IMXRT_LPI2C2_BASE + IMXRT_LPI2C_SSR_OFFSET) /* Slave Status Register */ -#define IMXRT_LPI2C2_SIER (IMXRT_LPI2C2_BASE + IMXRT_LPI2C_SIER_OFFSET) /* Slave Interrupt Enable Register */ -#define IMXRT_LPI2C2_SDER (IMXRT_LPI2C2_BASE + IMXRT_LPI2C_SDER_OFFSET) /* Slave DMA Enable Register */ -#define IMXRT_LPI2C2_SCFGR1 (IMXRT_LPI2C2_BASE + IMXRT_LPI2C_SCFGR1_OFFSET) /* Slave Config Register 1 */ -#define IMXRT_LPI2C2_SCFGR2 (IMXRT_LPI2C2_BASE + IMXRT_LPI2C_SCFGR2_OFFSET) /* Slave Config Register 2 */ -#define IMXRT_LPI2C2_SAMR (IMXRT_LPI2C2_BASE + IMXRT_LPI2C_SAMR_OFFSET) /* Slave Address Match Register */ -#define IMXRT_LPI2C2_SASR (IMXRT_LPI2C2_BASE + IMXRT_LPI2C_SASR_OFFSET) /* Slave Address Status Register */ -#define IMXRT_LPI2C2_STAR (IMXRT_LPI2C2_BASE + IMXRT_LPI2C_STAR_OFFSET) /* Slave Transmit ACK Register */ -#define IMXRT_LPI2C2_STDR (IMXRT_LPI2C2_BASE + IMXRT_LPI2C_STDR_OFFSET) /* Slave Transmit Data Register */ -#define IMXRT_LPI2C2_SRDR (IMXRT_LPI2C2_BASE + IMXRT_LPI2C_SRDR_OFFSET) /* Slave Receive Data Register */ - -/* LPI2C3 Registers */ - -#define IMXRT_LPI2C3_VERID (IMXRT_LPI2C3_BASE + IMXRT_LPI2C_VERID_OFFSET) /* Version ID Register */ -#define IMXRT_LPI2C3_PARAM (IMXRT_LPI2C3_BASE + IMXRT_LPI2C_PARAM_OFFSET) /* Parameter Register */ -#define IMXRT_LPI2C3_MCR (IMXRT_LPI2C3_BASE + IMXRT_LPI2C_MCR_OFFSET) /* Master Control Register */ -#define IMXRT_LPI2C3_MSR (IMXRT_LPI2C3_BASE + IMXRT_LPI2C_MSR_OFFSET) /* Master Status Register */ -#define IMXRT_LPI2C3_MIER (IMXRT_LPI2C3_BASE + IMXRT_LPI2C_MIER_OFFSET) /* Master Interrupt Enable Register */ -#define IMXRT_LPI2C3_MDER (IMXRT_LPI2C3_BASE + IMXRT_LPI2C_MDER_OFFSET) /* Master DMA Enable Register */ -#define IMXRT_LPI2C3_MCFGR0 (IMXRT_LPI2C3_BASE + IMXRT_LPI2C_MCFGR0_OFFSET) /* Master Config Register 0 */ -#define IMXRT_LPI2C3_MCFGR1 (IMXRT_LPI2C3_BASE + IMXRT_LPI2C_MCFGR1_OFFSET) /* Master Config Register 1 */ -#define IMXRT_LPI2C3_MCFGR2 (IMXRT_LPI2C3_BASE + IMXRT_LPI2C_MCFGR2_OFFSET) /* Master Config Register 2 */ -#define IMXRT_LPI2C3_MCFGR3 (IMXRT_LPI2C3_BASE + IMXRT_LPI2C_MCFGR3_OFFSET) /* Master Config Register 3 */ -#define IMXRT_LPI2C3_MDMR (IMXRT_LPI2C3_BASE + IMXRT_LPI2C_MDMR_OFFSET) /* Master Data Match Register */ -#define IMXRT_LPI2C3_MCCR0 (IMXRT_LPI2C3_BASE + IMXRT_LPI2C_MCCR0_OFFSET) /* Master Clock Configuration Register 0 */ -#define IMXRT_LPI2C3_MCCR1 (IMXRT_LPI2C3_BASE + IMXRT_LPI2C_MCCR1_OFFSET) /* Master Clock Configuration Register 1 */ -#define IMXRT_LPI2C3_MFCR (IMXRT_LPI2C3_BASE + IMXRT_LPI2C_MFCR_OFFSET) /* Master FIFO Control Register */ -#define IMXRT_LPI2C3_MFSR (IMXRT_LPI2C3_BASE + IMXRT_LPI2C_MFSR_OFFSET) /* Master FIFO Status Register */ -#define IMXRT_LPI2C3_MTDR (IMXRT_LPI2C3_BASE + IMXRT_LPI2C_MTDR_OFFSET) /* Master Transmit Data Register */ -#define IMXRT_LPI2C3_MRDR (IMXRT_LPI2C3_BASE + IMXRT_LPI2C_MRDR_OFFSET) /* Master Receive Data Register */ -#define IMXRT_LPI2C3_SCR (IMXRT_LPI2C3_BASE + IMXRT_LPI2C_SCR_OFFSET) /* Slave Control Register */ -#define IMXRT_LPI2C3_SSR (IMXRT_LPI2C3_BASE + IMXRT_LPI2C_SSR_OFFSET) /* Slave Status Register */ -#define IMXRT_LPI2C3_SIER (IMXRT_LPI2C3_BASE + IMXRT_LPI2C_SIER_OFFSET) /* Slave Interrupt Enable Register */ -#define IMXRT_LPI2C3_SDER (IMXRT_LPI2C3_BASE + IMXRT_LPI2C_SDER_OFFSET) /* Slave DMA Enable Register */ -#define IMXRT_LPI2C3_SCFGR1 (IMXRT_LPI2C3_BASE + IMXRT_LPI2C_SCFGR1_OFFSET) /* Slave Config Register 1 */ -#define IMXRT_LPI2C3_SCFGR2 (IMXRT_LPI2C3_BASE + IMXRT_LPI2C_SCFGR2_OFFSET) /* Slave Config Register 2 */ -#define IMXRT_LPI2C3_SAMR (IMXRT_LPI2C3_BASE + IMXRT_LPI2C_SAMR_OFFSET) /* Slave Address Match Register */ -#define IMXRT_LPI2C3_SASR (IMXRT_LPI2C3_BASE + IMXRT_LPI2C_SASR_OFFSET) /* Slave Address Status Register */ -#define IMXRT_LPI2C3_STAR (IMXRT_LPI2C3_BASE + IMXRT_LPI2C_STAR_OFFSET) /* Slave Transmit ACK Register */ -#define IMXRT_LPI2C3_STDR (IMXRT_LPI2C3_BASE + IMXRT_LPI2C_STDR_OFFSET) /* Slave Transmit Data Register */ -#define IMXRT_LPI2C3_SRDR (IMXRT_LPI2C3_BASE + IMXRT_LPI2C_SRDR_OFFSET) /* Slave Receive Data Register */ - -/* LPI2C4 Registers */ - -#define IMXRT_LPI2C4_VERID (IMXRT_LPI2C4_BASE + IMXRT_LPI2C_VERID_OFFSET) /* Version ID Register */ -#define IMXRT_LPI2C4_PARAM (IMXRT_LPI2C4_BASE + IMXRT_LPI2C_PARAM_OFFSET) /* Parameter Register */ -#define IMXRT_LPI2C4_MCR (IMXRT_LPI2C4_BASE + IMXRT_LPI2C_MCR_OFFSET) /* Master Control Register */ -#define IMXRT_LPI2C4_MSR (IMXRT_LPI2C4_BASE + IMXRT_LPI2C_MSR_OFFSET) /* Master Status Register */ -#define IMXRT_LPI2C4_MIER (IMXRT_LPI2C4_BASE + IMXRT_LPI2C_MIER_OFFSET) /* Master Interrupt Enable Register */ -#define IMXRT_LPI2C4_MDER (IMXRT_LPI2C4_BASE + IMXRT_LPI2C_MDER_OFFSET) /* Master DMA Enable Register */ -#define IMXRT_LPI2C4_MCFGR0 (IMXRT_LPI2C4_BASE + IMXRT_LPI2C_MCFGR0_OFFSET) /* Master Config Register 0 */ -#define IMXRT_LPI2C4_MCFGR1 (IMXRT_LPI2C4_BASE + IMXRT_LPI2C_MCFGR1_OFFSET) /* Master Config Register 1 */ -#define IMXRT_LPI2C4_MCFGR2 (IMXRT_LPI2C4_BASE + IMXRT_LPI2C_MCFGR2_OFFSET) /* Master Config Register 2 */ -#define IMXRT_LPI2C4_MCFGR3 (IMXRT_LPI2C4_BASE + IMXRT_LPI2C_MCFGR3_OFFSET) /* Master Config Register 3 */ -#define IMXRT_LPI2C4_MDMR (IMXRT_LPI2C4_BASE + IMXRT_LPI2C_MDMR_OFFSET) /* Master Data Match Register */ -#define IMXRT_LPI2C4_MCCR0 (IMXRT_LPI2C4_BASE + IMXRT_LPI2C_MCCR0_OFFSET) /* Master Clock Configuration Register 0 */ -#define IMXRT_LPI2C4_MCCR1 (IMXRT_LPI2C4_BASE + IMXRT_LPI2C_MCCR1_OFFSET) /* Master Clock Configuration Register 1 */ -#define IMXRT_LPI2C4_MFCR (IMXRT_LPI2C4_BASE + IMXRT_LPI2C_MFCR_OFFSET) /* Master FIFO Control Register */ -#define IMXRT_LPI2C4_MFSR (IMXRT_LPI2C4_BASE + IMXRT_LPI2C_MFSR_OFFSET) /* Master FIFO Status Register */ -#define IMXRT_LPI2C4_MTDR (IMXRT_LPI2C4_BASE + IMXRT_LPI2C_MTDR_OFFSET) /* Master Transmit Data Register */ -#define IMXRT_LPI2C4_MRDR (IMXRT_LPI2C4_BASE + IMXRT_LPI2C_MRDR_OFFSET) /* Master Receive Data Register */ -#define IMXRT_LPI2C4_SCR (IMXRT_LPI2C4_BASE + IMXRT_LPI2C_SCR_OFFSET) /* Slave Control Register */ -#define IMXRT_LPI2C4_SSR (IMXRT_LPI2C4_BASE + IMXRT_LPI2C_SSR_OFFSET) /* Slave Status Register */ -#define IMXRT_LPI2C4_SIER (IMXRT_LPI2C4_BASE + IMXRT_LPI2C_SIER_OFFSET) /* Slave Interrupt Enable Register */ -#define IMXRT_LPI2C4_SDER (IMXRT_LPI2C4_BASE + IMXRT_LPI2C_SDER_OFFSET) /* Slave DMA Enable Register */ -#define IMXRT_LPI2C4_SCFGR1 (IMXRT_LPI2C4_BASE + IMXRT_LPI2C_SCFGR1_OFFSET) /* Slave Config Register 1 */ -#define IMXRT_LPI2C4_SCFGR2 (IMXRT_LPI2C4_BASE + IMXRT_LPI2C_SCFGR2_OFFSET) /* Slave Config Register 2 */ -#define IMXRT_LPI2C4_SAMR (IMXRT_LPI2C4_BASE + IMXRT_LPI2C_SAMR_OFFSET) /* Slave Address Match Register */ -#define IMXRT_LPI2C4_SASR (IMXRT_LPI2C4_BASE + IMXRT_LPI2C_SASR_OFFSET) /* Slave Address Status Register */ -#define IMXRT_LPI2C4_STAR (IMXRT_LPI2C4_BASE + IMXRT_LPI2C_STAR_OFFSET) /* Slave Transmit ACK Register */ -#define IMXRT_LPI2C4_STDR (IMXRT_LPI2C4_BASE + IMXRT_LPI2C_STDR_OFFSET) /* Slave Transmit Data Register */ -#define IMXRT_LPI2C4_SRDR (IMXRT_LPI2C4_BASE + IMXRT_LPI2C_SRDR_OFFSET) /* Slave Receive Data Register */ - -/* Register bit definitions *****************************************************************/ - -/* LPI2C Version ID Register */ - -#define LPI2C_VERID_FEATURE_SHIFT (0) -#define LPI2C_VERID_FEATURE_MASK (0xffff << LPI2C_VERID_FEATURE_SHIFT) -#define LPI2C_VERID_MINOR_SHIFT (16) -#define LPI2C_VERID_MINOR_MASK (0xff << LPI2C_VERID_MINOR_SHIFT) -#define LPI2C_VERID_MAJOR_SHIFT (24) -#define LPI2C_VERID_MAJOR_MASK (0xff << LPI2C_VERID_MAJOR_SHIFT) - -/* LPI2C Parameter Register */ - -#define LPI2C_PARAM_MTXFIFO_MASK (0x0f) /* Config number of words in master transmit fifo to 2^MTXFIFO (pow(2,MTXFIFO )) */ -# define LPI2C_PARAM_MTXFIFO_1_WORDS (0) -# define LPI2C_PARAM_MTXFIFO_2_WORDS (1) -# define LPI2C_PARAM_MTXFIFO_4_WORDS (2) -# define LPI2C_PARAM_MTXFIFO_8_WORDS (3) -# define LPI2C_PARAM_MTXFIFO_16_WORDS (4) -# define LPI2C_PARAM_MTXFIFO_32_WORDS (5) -# define LPI2C_PARAM_MTXFIFO_64_WORDS (6) -# define LPI2C_PARAM_MTXFIFO_128_WORDS (7) -# define LPI2C_PARAM_MTXFIFO_256_WORDS (8) -# define LPI2C_PARAM_MTXFIFO_512_WORDS (9) -# define LPI2C_PARAM_MTXFIFO_1024_WORDS (10) -# define LPI2C_PARAM_MTXFIFO_2048_WORDS (11) -# define LPI2C_PARAM_MTXFIFO_4096_WORDS (12) -# define LPI2C_PARAM_MTXFIFO_8192_WORDS (13) -# define LPI2C_PARAM_MTXFIFO_16384_WORDS (14) -# define LPI2C_PARAM_MTXFIFO_32768_WORDS (15) - -#define LPI2C_PARAM_MRXFIFO_SHIFT (8) -#define LPI2C_PARAM_MRXFIFO_MASK (0x0f << LPI2C_PARAM_MRXFIFO_SHIFT) /* Config number of words in master receive fifo 2^MRXFIFO (pow(2,MTRFIFO )) */ -# define LPI2C_PARAM_MRXFIFO_1_WORDS (0 << LPI2C_PARAM_MRXFIFO_SHIFT) -# define LPI2C_PARAM_MRXFIFO_2_WORDS (1 << LPI2C_PARAM_MRXFIFO_SHIFT) -# define LPI2C_PARAM_MRXFIFO_4_WORDS (2 << LPI2C_PARAM_MRXFIFO_SHIFT) -# define LPI2C_PARAM_MRXFIFO_8_WORDS (3 << LPI2C_PARAM_MRXFIFO_SHIFT) -# define LPI2C_PARAM_MRXFIFO_16_WORDS (4 << LPI2C_PARAM_MRXFIFO_SHIFT) -# define LPI2C_PARAM_MRXFIFO_32_WORDS (5 << LPI2C_PARAM_MRXFIFO_SHIFT) -# define LPI2C_PARAM_MRXFIFO_64_WORDS (6 << LPI2C_PARAM_MRXFIFO_SHIFT) -# define LPI2C_PARAM_MRXFIFO_128_WORDS (7 << LPI2C_PARAM_MRXFIFO_SHIFT) -# define LPI2C_PARAM_MRXFIFO_256_WORDS (8 << LPI2C_PARAM_MRXFIFO_SHIFT) -# define LPI2C_PARAM_MRXFIFO_512_WORDS (9 << LPI2C_PARAM_MRXFIFO_SHIFT) -# define LPI2C_PARAM_MRXFIFO_1024_WORDS (10 << LPI2C_PARAM_MRXFIFO_SHIFT) -# define LPI2C_PARAM_MRXFIFO_2048_WORDS (11 << LPI2C_PARAM_MRXFIFO_SHIFT) -# define LPI2C_PARAM_MRXFIFO_4096_WORDS (12 << LPI2C_PARAM_MRXFIFO_SHIFT) -# define LPI2C_PARAM_MRXFIFO_8192_WORDS (13 << LPI2C_PARAM_MRXFIFO_SHIFT) -# define LPI2C_PARAM_MRXFIFO_16384_WORDS (14 << LPI2C_PARAM_MRXFIFO_SHIFT) -# define LPI2C_PARAM_MRXFIFO_32768_WORDS (15 << LPI2C_PARAM_MRXFIFO_SHIFT) - -/* LPI2C Master Control Register */ - -#define LPI2C_MCR_MEN (1 << 0) /* Master Enable Bit */ -#define LPI2C_MCR_RST (1 << 1) /* Software Reset Bit */ -#define LPI2C_MCR_DOZEN (1 << 2) /* Doze Mode Enable Bit */ -#define LPI2C_MCR_DBGEN (1 << 3) /* Debug Enable Bit */ - /* Bits 7-4 Reserved */ -#define LPI2C_MCR_RTF (1 << 8) /* Reset Transmit FIFO Bit */ -#define LPI2C_MCR_RRF (1 << 9) /* Reset Receive FIFO Bit */ - /* Bits 31-10 Reserved */ - -/* LPI2C Master Status Register */ - -#define LPI2C_MSR_TDF (1 << 0) /* Transmit Data Flag Bit */ -#define LPI2C_MSR_RDF (1 << 1) /* Receive Data Flag Bit */ - /* Bits 7-2 Reserved */ -#define LPI2C_MSR_EPF (1 << 8) /* End Packet Flag Bit */ -#define LPI2C_MSR_SDF (1 << 9) /* STOP Detect Flag Bit */ -#define LPI2C_MSR_NDF (1 << 10) /* NACK Detect Flag Bit */ -#define LPI2C_MSR_ALF (1 << 11) /* Arbitration Lost Flag Bit */ -#define LPI2C_MSR_FEF (1 << 12) /* FIFO Error Flag Bit */ -#define LPI2C_MSR_PLTF (1 << 13) /* Pin Low Timeout Flag Bit */ -#define LPI2C_MSR_DMF (1 << 14) /* Data Match Flag Bit */ - /* Bits 23-15 Reserved */ -#define LPI2C_MSR_MBF (1 << 24) /* Master Busy Flag Bit */ -#define LPI2C_MSR_BBF (1 << 25) /* Bus Busy Flag Bit */ - /* Bits 31-26 Reserved */ -#define LPI2C_MSR_ERROR_MASK (LPI2C_MSR_NDF | LPI2C_MSR_ALF | \ - LPI2C_MSR_BBF | LPI2C_MSR_FEF) - -/* LPI2C Master Interrupt Enable Register */ - -#define LPI2C_MIER_TDIE (1 << 0) /* Transmit Data Interrupt Enable Bit */ -#define LPI2C_MIER_RDIE (1 << 1) /* Receive Data Interrupt Enable Bit */ - /* Bits 7-2 Reserved */ -#define LPI2C_MIER_EPIE (1 << 8) /* End Packet Interrupt Enable Bit */ -#define LPI2C_MIER_SDIE (1 << 9) /* STOP Detect Interrupt Enable Bit */ -#define LPI2C_MIER_NDIE (1 << 10) /* NACK Detect Interrupt Enable Bit */ -#define LPI2C_MIER_ALIE (1 << 11) /* Arbitration Lost Interrupt Enable Bit */ -#define LPI2C_MIER_FEIE (1 << 12) /* FIFO Error Interrupt Enable Bit */ -#define LPI2C_MIER_PLTIE (1 << 13) /* Pin Low Timeout Interrupt Enable Bit */ -#define LPI2C_MIER_DMIE (1 << 14) /* Data Match Interrupt Enable Bit */ - /* Bits 31-15 Reserved */ - -/* LPI2C Master DMA Enable Register */ - -#define LPI2C_MDER_TDDE (1 << 0) /* Transmit Data DMA Enable Bit */ -#define LPI2C_MDER_RDDE (1 << 1) /* Transmit Data DMA Enable Bit */ - /* Bits 31-2 Reserved */ - -/* LPI2C Master Config Register 0 */ - -#define LPI2C_MCFG0_HREN (1 << 0) /* Host Request Enable Bit */ -#define LPI2C_MCFG0_HRPOL (1 << 1) /* Host Request Polarity Bit */ -#define LPI2C_MCFG0_HRSEL (1 << 2) /* Host Request Select Bit */ - /* Bits 7-3 Reserved */ -#define LPI2C_MCFG0_CIRFIFO (1 << 8) /* Circular FIFO Enable Bit */ -#define LPI2C_MCFG0_RDMO (1 << 9) /* Receive Data Match Only Bit */ - /* Bits 31-10 Reserved */ - -/* LPI2C Master Config Register 1 */ - -#define LPI2C_MCFGR1_PRESCALE_MASK (7 << 0) /* Clock Prescaler Bit Mask */ -#define LPI2C_MCFGR1_PRESCALE(n) (n & LPI2C_MCFGR1_PRESCALE_MASK) -# define LPI2C_MCFGR1_PRESCALE_1 (0) -# define LPI2C_MCFGR1_PRESCALE_2 (1) -# define LPI2C_MCFGR1_PRESCALE_4 (2) -# define LPI2C_MCFGR1_PRESCALE_8 (3) -# define LPI2C_MCFGR1_PRESCALE_16 (4) -# define LPI2C_MCFGR1_PRESCALE_32 (5) -# define LPI2C_MCFGR1_PRESCALE_64 (6) -# define LPI2C_MCFGR1_PRESCALE_128 (7) -#define LPI2C_MCFGR1_AUTOSTOP (1 << 8) /* Automatic STOP Generation Bit */ -#define LPI2C_MCFGR1_IGNACK (1 << 9) /* Ignore NACK Bit */ -#define LPI2C_MCFGR1_TIMECFG (1 << 10) /* Timeout Configuration Bit */ - /* Bits 15-11 Reserved */ -#define LPI2C_MCFGR1_MATCFG_SHIFT (16) -#define LPI2C_MCFGR1_MATCFG_MASK (7 << LPI2C_MCFGR1_MATCFG_SHIFT) /* Match Configuration Bit Mask */ -#define LPI2C_MCFGR1_MATCFG(n) ((n << LPI2C_MCFGR1_MATCFG_SHIFT) & LPI2C_MCFGR1_MATCFG_MASK) -# define LPI2C_MCFGR1_MATCFG_DISABLE (0 << LPI2C_MCFGR1_MATCFG_SHIFT) - /* LPI2C_MCFG1_MATCFG = 001b Reserved */ -# define LPI2C_MCFGR1_MATCFG2 (2 << LPI2C_MCFGR1_MATCFG_SHIFT) -# define LPI2C_MCFGR1_MATCFG3 (3 << LPI2C_MCFGR1_MATCFG_SHIFT) -# define LPI2C_MCFGR1_MATCFG4 (4 << LPI2C_MCFGR1_MATCFG_SHIFT) -# define LPI2C_MCFGR1_MATCFG5 (5 << LPI2C_MCFGR1_MATCFG_SHIFT) -# define LPI2C_MCFGR1_MATCFG6 (6 << LPI2C_MCFGR1_MATCFG_SHIFT) -# define LPI2C_MCFGR1_MATCFG7 (7 << LPI2C_MCFGR1_MATCFG_SHIFT) - /* Bits 23-19 Reserved */ -#define LPI2C_MCFGR1_PINCFG_SHIFT (24) -#define LPI2C_MCFGR1_PINCFG_MASK (7 << LPI2C_MCFGR1_PINCFG_SHIFT) /* Pin Configuration Bit Mask */ -#define LPI2C_MCFGR1_PINCFG(n) ((n << LPI2C_MCFGR1_PINCFG_SHIFT) & LPI2C_MCFGR1_PINCFG_MASK) -# define LPI2C_MCFGR1_PINCFG0 (0 << LPI2C_MCFGR1_PINCFG_SHIFT) -# define LPI2C_MCFGR1_PINCFG1 (1 << LPI2C_MCFGR1_PINCFG_SHIFT) -# define LPI2C_MCFGR1_PINCFG2 (2 << LPI2C_MCFGR1_PINCFG_SHIFT) -# define LPI2C_MCFGR1_PINCFG3 (3 << LPI2C_MCFGR1_PINCFG_SHIFT) -# define LPI2C_MCFGR1_PINCFG4 (4 << LPI2C_MCFGR1_PINCFG_SHIFT) -# define LPI2C_MCFGR1_PINCFG5 (5 << LPI2C_MCFGR1_PINCFG_SHIFT) -# define LPI2C_MCFGR1_PINCFG6 (6 << LPI2C_MCFGR1_PINCFG_SHIFT) -# define LPI2C_MCFGR1_PINCFG7 (7 << LPI2C_MCFGR1_PINCFG_SHIFT) - /* Bits 31-27 Reserved */ - -/* LPI2C Master Config Register 2 */ - -#define LPI2C_MCFG2_BUSIDLE_MASK (0xfff << 0) /* Bus Idle Timeout Period in Clock Cycles */ -#define LPI2C_MCFG2_BUSIDLE_DISABLE (0) -#define LPI2C_MCFG2_BUSIDLE(n) (n & LPI2C_MCFG2_BUSIDLE_MASK) - /* Bits 15-12 Reserved */ -#define LPI2C_MCFG2_FILTSCL_SHIFT (16) -#define LPI2C_MCFG2_FILTSCL_MASK (15 << LPI2C_MCFG2_FILTSCL_SHIFT) /* Glitch Filter SCL */ -#define LPI2C_MCFG2_FILTSCL_DISABLE (0 << LPI2C_MCFG2_FILTSCL_SHIFT) -#define LPI2C_MCFG2_FILTSCL_CYCLES(n) ((n << LPI2C_MCFG2_FILTSCL_SHIFT) & LPI2C_MCFG2_FILTSCL_MASK) - /* Bits 23-20 Reserved */ -#define LPI2C_MCFG2_FILTSDA_SHIFT (24) -#define LPI2C_MCFG2_FILTSDA_MASK (15 << LPI2C_MCFG2_FILTSDA_SHIFT) /* Glitch Filter SDA */ -#define LPI2C_MCFG2_FILTSDA_DISABLE (0 << LPI2C_MCFG2_FILTSDA_SHIFT) -#define LPI2C_MCFG2_FILTSDA_CYCLES(n) ((n << LPI2C_MCFG2_FILTSDA_SHIFT) & LPI2C_MCFG2_FILTSDA_MASK) - /* Bits 31-28 Reserved */ -/* LPI2C Master Config Register 3 */ - - /* Bits 7-0 Reserved */ -#define LPI2C_MCFG3_PINLOW_SHIFT (8) -#define LPI2C_MCFG3_PINLOW_MASK (0xfff << LPI2C_MCFG3_PINLOW_SHIFT) /* Configure The Pin Low Timeout in Clock Cycles */ -#define LPI2C_MCFG3_PINLOW_CYCLES(n) ((n << LPI2C_MCFG3_PINLOW_SHIFT) & LPI2C_MCFG3_PINLOW_MASK) - /* Bits 31-20 Reserved */ - -/* LPI2C Master Data Match Register */ - -#define LPI2C_MDMR_MATCH0_SHIFT (0) -#define LPI2C_MDMR_MATCH0_MASK (0xff << LPI2C_MDMR_MATCH0_SHIFT) /* Match 0 Value */ -#define LPI2C_MDMR_MATCH0(n) ((n << LPI2C_MDMR_MATCH0_SHIFT) & LPI2C_MDMR_MATCH0_MASK) - /* Bits 15-8 Reserved */ -#define LPI2C_MDMR_MATCH1_SHIFT (16) -#define LPI2C_MDMR_MATCH1_MASK (0xff << LPI2C_MDMR_MATCH1_SHIFT) /* Match 1 Value */ -#define LPI2C_MDMR_MATCH1(n) ((n << LPI2C_MDMR_MATCH1_SHIFT) & LPI2C_MDMR_MATCH1_MASK) - /* Bits 31-24 Reserved */ - -/* LPI2C Master Clock Configuration Register 0 */ - -#define LPI2C_MCCR0_CLKLO_SHIFT (0) -#define LPI2C_MCCR0_CLKLO_MASK (0x3f << LPI2C_MCCR0_CLKLO_SHIFT) /* Clock Low Period */ -#define LPI2C_MCCR0_CLKLO(n) ((n << LPI2C_MCCR0_CLKLO_SHIFT) & LPI2C_MCCR0_CLKLO_MASK) - /* Bits 7-6 Reserved */ -#define LPI2C_MCCR0_CLKHI_SHIFT (8) -#define LPI2C_MCCR0_CLKHI_MASK (0x3f << LPI2C_MCCR0_CLKHI_SHIFT) /* Clock High Period */ -#define LPI2C_MCCR0_CLKHI(n) ((n << LPI2C_MCCR0_CLKHI_SHIFT) & LPI2C_MCCR0_CLKHI_MASK) - /* Bits 15-14 Reserved */ -#define LPI2C_MCCR0_SETHOLD_SHIFT (16) -#define LPI2C_MCCR0_SETHOLD_MASK (0x3f << LPI2C_MCCR0_SETHOLD_SHIFT) /* Setup Hold Delay */ -#define LPI2C_MCCR0_SETHOLD(n) ((n << LPI2C_MCCR0_SETHOLD_SHIFT) & LPI2C_MCCR0_SETHOLD_MASK) - /* Bits 23-22 Reserved */ -#define LPI2C_MCCR0_DATAVD_SHIFT (24) -#define LPI2C_MCCR0_DATAVD_MASK (0x3f << LPI2C_MCCR0_DATAVD_SHIFT) /* Setup Hold Delay */ -#define LPI2C_MCCR0_DATAVD(n) ((n << LPI2C_MCCR0_DATAVD_SHIFT) & LPI2C_MCCR0_DATAVD_MASK) - /* Bits 31-30 Reserved */ - -/* LPI2C Master Clock Configuration Register 1 */ - -#define LPI2C_MCCR1_CLKLO_SHIFT (0) -#define LPI2C_MCCR1_CLKLO_MASK (0x3f << LPI2C_MCCR1_CLKLO_SHIFT) /* Clock Low Period */ -#define LPI2C_MCCR1_CLKLO(n) ((n << LPI2C_MCCR1_CLKLO_SHIFT) & LPI2C_MCCR1_CLKLO_MASK) - /* Bits 7-6 Reserved */ -#define LPI2C_MCCR1_CLKHI_SHIFT (8) -#define LPI2C_MCCR1_CLKHI_MASK (0x3f << LPI2C_MCCR1_CLKHI_SHIFT) /* Clock High Period */ -#define LPI2C_MCCR1_CLKHI(n) ((n << LPI2C_MCCR1_CLKHI_SHIFT) & LPI2C_MCCR1_CLKHI_MASK) - /* Bits 15-14 Reserved */ -#define LPI2C_MCCR1_SETHOLD_SHIFT (16) -#define LPI2C_MCCR1_SETHOLD_MASK (0x3f << LPI2C_MCCR1_SETHOLD_SHIFT) /* Setup Hold Delay */ -#define LPI2C_MCCR1_SETHOLD(n) ((n << LPI2C_MCCR1_SETHOLD_SHIFT) & LPI2C_MCCR1_SETHOLD_MASK) - /* Bits 23-22 Reserved */ -#define LPI2C_MCCR1_DATAVD_SHIFT (24) -#define LPI2C_MCCR1_DATAVD_MASK (0x3f << LPI2C_MCCR1_DATAVD_SHIFT) /* Setup Hold Delay */ -#define LPI2C_MCCR1_DATAVD(n) ((n << LPI2C_MCCR1_DATAVD_SHIFT) & LPI2C_MCCR1_DATAVD_MASK) - /* Bits 31-30 Reserved */ - - -/* LPI2C Master FIFO Control Register */ - -#define LPI2C_MFCR_TXWATER_SHIFT (0) -#define LPI2C_MFCR_TXWATER_MASK (3 << LPI2C_MFCR_TXWATER_SHIFT) /* Transmit FIFO Watermark*/ -#define LPI2C_MFCR_TXWATER(n) ((n << LPI2C_MFCR_TXWATER_SHIFT) & LPI2C_MFCR_TXWATER_MASK) /* Transmit FIFO Watermark*/ - /* Bits 15-2 Reserved */ -#define LPI2C_MFCR_RXWATER_SHIFT (16) -#define LPI2C_MFCR_RXWATER_MASK (3 << LPI2C_MFCR_RXWATER_SHIFT) /* Receive FIFO Watermark */ -#define LPI2C_MFCR_RXWATER(n) ((n << LPI2C_MFCR_RXWATER_SHIFT) & LPI2C_MFCR_RXWATER_MASK) /* Transmit FIFO Watermark*/ - /* Bits 31-18 Reserved */ - -/* LPI2C Master FIFO Status Register */ - -#define LPI2C_MFSR_TXCOUNT_SHIFT (0) -#define LPI2C_MFSR_TXCOUNT_MASK (3 << LPI2C_MFSR_TXCOUNT_SHIFT) /* Transmit FIFO Count */ - /* Bits 15-2 Reserved */ -#define LPI2C_MFSR_RXCOUNT_SHIFT (16) -#define LPI2C_MFSR_RXCOUNT_MASK (3 << LPI2C_MFSR_RXCOUNT_SHIFT) /* Receive FIFO Count */ - /* Bits 31-18 Reserved */ - -/* LPI2C Master Transmit Data Register */ - -#define LPI2C_MTDR_DATA_SHIFT (0) -#define LPI2C_MTDR_DATA_MASK (0xff << LPI2C_MTDR_DATA_SHIFT) /* Transmit Data */ -#define LPI2C_MTDR_DATA(n) (n & LPI2C_MTDR_DATA_MASK) -#define LPI2C_MTDR_CMD_SHIFT (8) -#define LPI2C_MTDR_CMD_MASK (7 << LPI2C_MTDR_CMD_SHIFT) /* Command Data */ -#define LPI2C_MTDR_CMD(n) ((n << LPI2C_MTDR_CMD_SHIFT) & LPI2C_MTDR_CMD_MASK) -# define LPI2C_MTDR_CMD_TXD (0 << LPI2C_MTDR_CMD_SHIFT) -# define LPI2C_MTDR_CMD_RXD (1 << LPI2C_MTDR_CMD_SHIFT) -# define LPI2C_MTDR_CMD_STOP (2 << LPI2C_MTDR_CMD_SHIFT) -# define LPI2C_MTDR_CMD_RXD_DISC (3 << LPI2C_MTDR_CMD_SHIFT) -# define LPI2C_MTDR_CMD_START (4 << LPI2C_MTDR_CMD_SHIFT) -# define LPI2C_MTDR_CMD_START_NACK (5 << LPI2C_MTDR_CMD_SHIFT) -# define LPI2C_MTDR_CMD_START_HI (6 << LPI2C_MTDR_CMD_SHIFT) -# define LPI2C_MTDR_CMD_START_HI_NACK (7 << LPI2C_MTDR_CMD_SHIFT) - /* Bits 31-11 Reserved */ - -/* LPI2C Master Receive Data Register */ - -#define LPI2C_MRDR_DATA_SHIFT (0) -#define LPI2C_MRDR_DATA_MASK (0xff << LPI2C_MRDR_DATA_SHIFT) /* Receive Data */ - /* Bits 13-8 Reserved */ -#define LPI2C_MRDR_RXEMPTY_SHIFT (14) -#define LPI2C_MRDR_RXEMPTY_MASK (1 << LPI2C_MRDR_RXEMPTY_SHIFT) /* Rx Empty */ - /* Bits 31-15 Reserved */ - -/* LPI2C Slave Control Register */ - -#define LPI2C_SCR_SEN (1 << 0) /* Slave Enable Bit */ -#define LPI2C_SCR_RST (1 << 1) /* Software Reset Bit */ - /* Bits 3-2 Reserved */ -#define LPI2C_SCR_FILTEN (1 << 4) /* Filter Enable Bit */ -#define LPI2C_SCR_FILTDZ (1 << 5) /* Filter Doze Enable Bit */ - /* Bits 7-4 Reserved */ -#define LPI2C_SCR_RTF (1 << 8) /* Reset Transmit FIFO Bit */ -#define LPI2C_SCR_RRF (1 << 9) /* Reset Receive FIFO Bit */ - /* Bits 31-10 Reserved */ - -/* LPI2C Slave Status Register */ - -#define LPI2C_SSR_TDF (1 << 0) /* Transmit Data Flag Bit */ -#define LPI2C_SSR_RDF (1 << 1) /* Receive Data Flag Bit */ -#define LPI2C_SSR_AVF (1 << 2) /* Address Valid Flag Bit */ -#define LPI2C_SSR_TAF (1 << 3) /* Transmit ACK Flag Bit */ - /* Bits 7-4 Reserved */ -#define LPI2C_SSR_RSF (1 << 8) /* Repeated Start Flag Bit */ -#define LPI2C_SSR_SDF (1 << 9) /* STOP Detect Flag Bit */ -#define LPI2C_SSR_BEF (1 << 10) /* Bit Error Flag Bit */ -#define LPI2C_SSR_FEF (1 << 11) /* FIFO Error Flag Bit */ -#define LPI2C_SSR_AM0F (1 << 12) /* Address Match 0 Flag Bit */ -#define LPI2C_SSR_AM1F (1 << 13) /* Address Match 1 Flag Bit */ -#define LPI2C_SSR_GCF (1 << 14) /* General Call Flag Bit */ -#define LPI2C_SSR_SARF (1 << 15) /* SMBus Alert Response Flag Bit */ - /* Bits 23-16 Reserved */ -#define LPI2C_MSR_SBF (1 << 24) /* Slave Busy Flag Bit */ -#define LPI2C_MSR_BBF (1 << 25) /* Bus Busy Flag Bit */ - /* Bits 31-26 Reserved */ - -/* LPI2C Slave Interrupt Enable Register */ - -#define LPI2C_SIER_TDIE (1 << 0) /* Transmit Data Interrupt Enable Bit */ -#define LPI2C_SIER_RDIE (1 << 1) /* Receive Data Interrupt Enable Bit */ -#define LPI2C_SIER_AVIE (1 << 2) /* Address Valid Interrupt Enable Bit */ -#define LPI2C_SIER_TAIE (1 << 3) /* Transmit ACK Interrupt Enable Bit */ - /* Bits 7-4 Reserved */ -#define LPI2C_SIER_RSIE (1 << 8) /* Repeated Start Interrupt Enable Bit */ -#define LPI2C_SIER_SDIE (1 << 9) /* STOP Detect Interrupt Enable Bit */ -#define LPI2C_SIER_BEIE (1 << 10) /* Bit Error Interrupt Enable Bit */ -#define LPI2C_SIER_FEIE (1 << 11) /* FIFO Error Interrupt Enable Bit */ -#define LPI2C_SIER_AM0IE (1 << 12) /* Address Match 0 Interrupt Enable Bit */ -#define LPI2C_SIER_AM1IE (1 << 13) /* Address Match 1 Interrupt Enable Bit */ -#define LPI2C_SIER_GCIE (1 << 14) /* General Call Interrupt Enable Bit */ -#define LPI2C_SIER_SARIE (1 << 15) /* SMBus Alert Response Interrupt Enable Bit */ - /* Bits 31-16 Reserved */ - -/* LPI2C Slave DMA Enable Register */ - -#define LPI2C_SDER_TDDE (1 << 0) /* Transmit Data DMA Enable Bit */ -#define LPI2C_SDER_RDDE (1 << 1) /* Transmit Data DMA Enable Bit */ -#define LPI2C_SDER_AVDE (1 << 2) /* Address Valid DMA Enable Bit */ - /* Bits 31-3 Reserved */ - -/* LPI2C Slave Configuration Register 1 */ - -#define LPI2C_SCFGR1_ADRSTALL (1 << 0) /* Address SCL Stall */ -#define LPI2C_SCFGR1_RXSTALL (1 << 1) /* RX SCL Stall */ -#define LPI2C_SCFGR1_TXSTALL (1 << 2) /* TX Data SCL Stall */ -#define LPI2C_SCFGR1_ACKSTALL (1 << 3) /* ACK SCL Stall */ - /* Bits 7-4 Reserved */ -#define LPI2C_SCFGR1_GCEN (1 << 8) /* General Call Enable */ -#define LPI2C_SCFGR1_SAEN (1 << 9) /* SMBus Alert Enable */ -#define LPI2C_SCFGR1_TXCFG (1 << 10) /* Transmit Flag Configuration */ -#define LPI2C_SCFGR1_RXCFG (1 << 11) /* Receive Data Configuration */ -#define LPI2C_SCFGR1_IFNACK (1 << 12) /* Ignore NACK */ -#define LPI2C_SCFGR1_HSMEN (1 << 13) /* High Speed Mode Enable */ - /* Bits 15-14 Reserved */ -#define LPI2C_SCFG1_ADDRCFG_SHIFT (16) -#define LPI2C_SCFG1_ADDRCFG_MASK (7 << LPI2C_SCFG1_ADDRCFG_SHIFT) /* Address Configuration Bit Mask */ -#define LPI2C_SCFG1_ADDRCFG(n) ((n << LPI2C_SCFG1_ADDRCFG_SHIFT) & LPI2C_SCFG1_ADDRCFG_MASK) -# define LPI2C_SCFG1_ADDRCFG0 (0 << LPI2C_SCFG1_ADDRCFG_SHIFT) -# define LPI2C_SCFG1_ADDRCFG1 (2 << LPI2C_SCFG1_ADDRCFG_SHIFT) -# define LPI2C_SCFG1_ADDRCFG2 (2 << LPI2C_SCFG1_ADDRCFG_SHIFT) -# define LPI2C_SCFG1_ADDRCFG3 (3 << LPI2C_SCFG1_ADDRCFG_SHIFT) -# define LPI2C_SCFG1_ADDRCFG4 (4 << LPI2C_SCFG1_ADDRCFG_SHIFT) -# define LPI2C_SCFG1_ADDRCFG5 (5 << LPI2C_SCFG1_ADDRCFG_SHIFT) -# define LPI2C_SCFG1_ADDRCFG6 (6 << LPI2C_SCFG1_ADDRCFG_SHIFT) -# define LPI2C_SCFG1_ADDRCFG7 (7 << LPI2C_SCFG1_ADDRCFG_SHIFT) - /* Bits 31-19 Reserved */ - -/* LPI2C Slave Configuration Register 2 */ - -#define LPI2C_SCFG2_CLKHOLD_MASK (15 << 0) /* Clock Hold Time */ -#define LPI2C_SCFG2_CLKHOLD(n) (n & LPI2C_SCFG2_CLKHOLD_MASK) - /* Bits 7-4 Reserved */ -#define LPI2C_SCFG2_DATAVD_SHIFT (8) -#define LPI2C_SCFG2_DATAVD_MASK (0x3f << LPI2C_SCFG2_DATAVD_SHIFT) /* Data Valid Delay */ -#define LPI2C_SCFG2_DATAVD(n) ((n << LPI2C_SCFG2_DATAVD_SHIFT) & LPI2C_SCFG2_DATAVD_MASK) - /* Bits 15-14 Reserved */ -#define LPI2C_SCFG2_FILTSCL_SHIFT (16) -#define LPI2C_SCFG2_FILTSCL_MASK (15 << LPI2C_SCFG2_FILTSCL_SHIFT) /* Glitch Filter SCL */ -#define LPI2C_SCFG2_FILTSCL_DISABLE (0 << LPI2C_SCFG2_FILTSCL_SHIFT) -#define LPI2C_SCFG2_FILTSCL_CYCLES(n) ((n << LPI2C_SCFG2_FILTSCL_SHIFT) & LPI2C_SCFG2_FILTSCL_MASK) - /* Bits 23-20 Reserved */ -#define LPI2C_SCFG2_FILTSDA_SHIFT (24) -#define LPI2C_SCFG2_FILTSDA_MASK (15 << LPI2C_SCFG2_FILTSDA_SHIFT) /* Glitch Filter SDA */ -#define LPI2C_SCFG2_FILTSDA_DISABLE (0 << LPI2C_SCFG2_FILTSDA_SHIFT) -#define LPI2C_SCFG2_FILTSDA_CYCLES(n) ((n << LPI2C_SCFG2_FILTSDA_SHIFT) & LPI2C_SCFG2_FILTSDA_MASK) - /* Bits 31-28 Reserved */ - -/* LPI2C Slave Address Match Register */ - - /* Bit 0 Reserved */ -#define LPI2C_SAMR_ADDR0_SHIFT (1) -#define LPI2C_SAMR_ADDR0_MASK (0x3ff << LPI2C_SAMR_ADDR0_SHIFT) /* Address 0 Value */ -#define LPI2C_SAMR_ADDR0(n) ((n << LPI2C_SAMR_ADDR0_SHIFT) & LPI2C_SAMR_ADDR0_MASK) - /* Bits 16-11 Reserved */ -#define LPI2C_SAMR_ADDR1_SHIFT (17) -#define LPI2C_SAMR_ADDR1_MASK (0x3ff << LPI2C_SAMR_ADDR1_SHIFT) /* Address 1 Value */ -#define LPI2C_SAMR_ADDR1(n) ((n << LPI2C_SAMR_ADDR1_SHIFT) & LPI2C_SAMR_ADDR1_MASK) - /* Bits 31-27 Reserved */ - -/* LPI2C Slave Address Status Register */ - -#define LPI2C_SASR_RADDR_MASK (0x7ff << 0) /* Received Address */ - /* Bits 16-11 Reserved */ -#define LPI2C_SASR_ANV (1 << 14) /* Address Not Valid */ - /* Bits 31-15 Reserved */ - -/* LPI2C Slave Transmit ACK Register */ - -#define LPI2C_STAR_TXNACK (1 << 0) /* Transmit NACK */ - /* Bits 31-1 Reserved */ - -/* LPI2C Slave Transmit Data Register */ - -#define LPI2C_STDR_DATA_SHIFT (0) -#define LPI2C_STDR_DATA_MASK (0xff << LPI2C_STDR_DATA_SHIFT) /* Transmit Data */ -#define LPI2C_STDR_DATA(n) ((n << LPI2C_STDR_DATA_SHIFT) & LPI2C_STDR_DATA_MASK) - /* Bits 31-8 Reserved */ - -/* LPI2C Slave Receive Data Register */ - -#define LPI2C_SRDR_DATA_SHIFT (0) -#define LPI2C_SRDR_DATA_MASK (0xff << LPI2C_SRDR_DATA_SHIFT) /* Receive Data */ -#define LPI2C_SRDR_DATA(n) ((n << LPI2C_SRDR_DATA_SHIFT) & LPI2C_SRDR_DATA_MASK) - /* Bits 13-8 Reserved */ -#define LPI2C_STAR_SOF (1 << 14) /* RX Empty */ -#define LPI2C_STAR_RXEMPTY (1 << 15) /* Start Of Frame */ - /* Bits 31-16 Reserved */ - -#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_LPI2C_H */ diff --git a/arch/arm/src/imxrt/chip/imxrt_lpspi.h b/arch/arm/src/imxrt/chip/imxrt_lpspi.h deleted file mode 100644 index 699e4eddf45..00000000000 --- a/arch/arm/src/imxrt/chip/imxrt_lpspi.h +++ /dev/null @@ -1,371 +0,0 @@ -/******************************************************************************************** - * arch/arm/src/imxrt/imxrt_lpspi.h - * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Pavlina Koleva - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ********************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_LPSPI_H -#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_LPSPI_H - -/******************************************************************************************** - * Included Files - ********************************************************************************************/ - -#include -#include "chip/imxrt_memorymap.h" - -/******************************************************************************************** - * Pre-processor Definitions - ********************************************************************************************/ - -/* Register offsets *************************************************************************/ - -#define IMXRT_LPSPI_VERID_OFFSET 0x0000 /* Version ID Register offset */ -#define IMXRT_LPSPI_PARAM_OFFSET 0x0004 /* Parameter Register offset */ -#define IMXRT_LPSPI_CR_OFFSET 0x0010 /* Control Register offset */ -#define IMXRT_LPSPI_SR_OFFSET 0x0014 /* Status Register offset */ -#define IMXRT_LPSPI_IER_OFFSET 0x0018 /* Interrupt Enable Register offset */ -#define IMXRT_LPSPI_DER_OFFSET 0x001C /* DMA Enable Register offset */ -#define IMXRT_LPSPI_CFGR0_OFFSET 0x0020 /* Configuration Register 0 offset */ -#define IMXRT_LPSPI_CFGR1_OFFSET 0x0024 /* Configuration Register 1 offset */ -#define IMXRT_LPSPI_DMR0_OFFSET 0x0030 /* Data Match Register 0 offset */ -#define IMXRT_LPSPI_DMR1_OFFSET 0x0034 /* Data Match Register 1 offset */ -#define IMXRT_LPSPI_CCR_OFFSET 0x0040 /* Clock Configuration Register offset */ -#define IMXRT_LPSPI_FCR_OFFSET 0x0058 /* FIFO Control Register offset */ -#define IMXRT_LPSPI_FSR_OFFSET 0x005C /* FIFO Status Register offset */ -#define IMXRT_LPSPI_TCR_OFFSET 0x0060 /* Transmit Command Register offset */ -#define IMXRT_LPSPI_TDR_OFFSET 0x0064 /* Transmit Data Register offset */ -#define IMXRT_LPSPI_RSR_OFFSET 0x0070 /* Receive Status Register offset */ -#define IMXRT_LPSPI_RDR_OFFSET 0x0074 /* Receive Data Register offset */ - -/* Register addresses ***********************************************************************/ - -#define IMXRT_LPSPI1_VERID (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_VERID_OFFSET) -#define IMXRT_LPSPI1_PARAM (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_PARAM_OFFSET) -#define IMXRT_LPSPI1_CR (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_CR_OFFSET) -#define IMXRT_LPSPI1_SR (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_SR_OFFSET) -#define IMXRT_LPSPI1_IER (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_IER_OFFSET) -#define IMXRT_LPSPI1_DER (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_DER_OFFSET) -#define IMXRT_LPSPI1_CFGR0 (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_CFGR0_OFFSET) -#define IMXRT_LPSPI1_CFGR1 (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_CFGR1_OFFSET) -#define IMXRT_LPSPI1_DMR0 (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_DMR0_OFFSET) -#define IMXRT_LPSPI1_DMR1 (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_DMR1_OFFSET) -#define IMXRT_LPSPI1_CCR (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_CCR_OFFSET) -#define IMXRT_LPSPI1_FCR (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_FCR_OFFSET) -#define IMXRT_LPSPI1_FSR (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_FSR_OFFSET) -#define IMXRT_LPSPI1_TCR (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_TCR_OFFSET) -#define IMXRT_LPSPI1_TDR (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_TDR_OFFSET) -#define IMXRT_LPSPI1_RSR (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_RSR_OFFSET) -#define IMXRT_LPSPI1_RDR (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_RDR_OFFSET) - -#define IMXRT_LPSPI2_VERID (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_VERID_OFFSET) -#define IMXRT_LPSPI2_PARAM (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_PARAM_OFFSET) -#define IMXRT_LPSPI2_CR (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_CR_OFFSET) -#define IMXRT_LPSPI2_SR (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_SR_OFFSET) -#define IMXRT_LPSPI2_IER (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_IER_OFFSET) -#define IMXRT_LPSPI2_DER (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_DER_OFFSET) -#define IMXRT_LPSPI2_CFGR0 (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_CFGR0_OFFSET) -#define IMXRT_LPSPI2_CFGR1 (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_CFGR1_OFFSET) -#define IMXRT_LPSPI2_DMR0 (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_DMR0_OFFSET) -#define IMXRT_LPSPI2_DMR1 (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_DMR1_OFFSET) -#define IMXRT_LPSPI2_CCR (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_CCR_OFFSET) -#define IMXRT_LPSPI2_FCR (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_FCR_OFFSET) -#define IMXRT_LPSPI2_FSR (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_FSR_OFFSET) -#define IMXRT_LPSPI2_TCR (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_TCR_OFFSET) -#define IMXRT_LPSPI2_TDR (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_TDR_OFFSET) -#define IMXRT_LPSPI2_RSR (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_RSR_OFFSET) -#define IMXRT_LPSPI2_RDR (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_RDR_OFFSET) - -#define IMXRT_LPSPI3_VERID (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_VERID_OFFSET) -#define IMXRT_LPSPI3_PARAM (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_PARAM_OFFSET) -#define IMXRT_LPSPI3_CR (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_CR_OFFSET) -#define IMXRT_LPSPI3_SR (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_SR_OFFSET) -#define IMXRT_LPSPI3_IER (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_IER_OFFSET) -#define IMXRT_LPSPI3_DER (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_DER_OFFSET) -#define IMXRT_LPSPI3_CFGR0 (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_CFGR0_OFFSET) -#define IMXRT_LPSPI3_CFGR1 (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_CFGR1_OFFSET) -#define IMXRT_LPSPI3_DMR0 (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_DMR0_OFFSET) -#define IMXRT_LPSPI3_DMR1 (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_DMR1_OFFSET) -#define IMXRT_LPSPI3_CCR (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_CCR_OFFSET) -#define IMXRT_LPSPI3_FCR (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_FCR_OFFSET) -#define IMXRT_LPSPI3_FSR (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_FSR_OFFSET) -#define IMXRT_LPSPI3_TCR (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_TCR_OFFSET) -#define IMXRT_LPSPI3_TDR (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_TDR_OFFSET) -#define IMXRT_LPSPI3_RSR (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_RSR_OFFSET) -#define IMXRT_LPSPI3_RDR (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_RDR_OFFSET) - -#define IMXRT_LPSPI4_VERID (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_VERID_OFFSET) -#define IMXRT_LPSPI4_PARAM (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_PARAM_OFFSET) -#define IMXRT_LPSPI4_CR (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_CR_OFFSET) -#define IMXRT_LPSPI4_SR (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_SR_OFFSET) -#define IMXRT_LPSPI4_IER (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_IER_OFFSET) -#define IMXRT_LPSPI4_DER (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_DER_OFFSET) -#define IMXRT_LPSPI4_CFGR0 (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_CFGR0_OFFSET) -#define IMXRT_LPSPI4_CFGR1 (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_CFGR1_OFFSET) -#define IMXRT_LPSPI4_DMR0 (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_DMR0_OFFSET) -#define IMXRT_LPSPI4_DMR1 (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_DMR1_OFFSET) -#define IMXRT_LPSPI4_CCR (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_CCR_OFFSET) -#define IMXRT_LPSPI4_FCR (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_FCR_OFFSET) -#define IMXRT_LPSPI4_FSR (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_FSR_OFFSET) -#define IMXRT_LPSPI4_TCR (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_TCR_OFFSET) -#define IMXRT_LPSPI4_TDR (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_TDR_OFFSET) -#define IMXRT_LPSPI4_RSR (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_RSR_OFFSET) -#define IMXRT_LPSPI4_RDR (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_RDR_OFFSET) - -/* Register bit definitions *****************************************************************/ - -/* Version ID Register */ - -#define LPSPI_VERID_FEATURE_SHIFT (0) /* Bits 0-15: Module Identification Number */ -#define LPSPI_VERID_FEATURE_MASK (0xffff << LPSPI_VERID_FEATURE_SHIFT) -#define LPSPI_VERID_MINOR_SHIFT (16) /* Bits 16-23: Minor Version Number */ -#define LPSPI_VERID_MINOR_MASK (0xff << LPSPI_VERID_MINOR_SHIFT) -#define LPSPI_VERID_MAJOR_SHIFT (24) /* Bits 24-31: Major Version Number */ -#define LPSPI_VERID_MAJOR_MASK (0xff << LPSPI_VERID_MAJOR_SHIFT) - -/* Parameter Register */ - -#define LPSPI_PARAM_TXFIFO_SHIFT (0) /* Bits 0-7: Transmit FIFO Size */ -#define LPSPI_PARAM_TXFIFO_MASK (0xff << LPSPI_PARAM_TXFIFO_SHIFT) -#define LPSPI_PARAM_RXFIFO_SHIFT (8) /* Bits 8-15: Receive FIFO Size */ -#define LPSPI_PARAM_RXFIFO_MASK (0xff << LPSPI_PARAM_RXFIFO_SHIFT) -#define LPSPI_PARAM_PCSNUM_SHIFT (16) /* Bits 16-23: PCS Number */ -#define LPSPI_PARAM_PCSNUM_MASK (0xff << LPSPI_PARAM_PCSNUM_SHIFT) - /* Bits 24-31: Reserved */ - -/* Control Register */ - -#define LPSPI_CR_MEN (1 << 0) /* Bit 0: Module Enable */ -#define LPSPI_CR_RST (1 << 1) /* Bit 1: Software Reset */ -#define LPSPI_CR_DOZEN (1 << 2) /* Bit 2: Doze mode enable */ -# define LPSPI_CR_DOZEN_EN (0 << 2) /* Module is enabled in Doze mode */ -# define LPSPI_CR_DOZEN_DIS (1 << 2) /* Module is disabled in Doze mode */ -#define LPSPI_CR_DBGEN (1 << 3) /* Bit 3: Debug Enable */ - /* Bits 4-7: Reserved */ -#define LPSPI_CR_RTF (1 << 8) /* Bit 8: Reset Transmit FIFO */ -#define LPSPI_CR_RRF (1 << 9) /* Bit 9: Reset Receive FIFO */ - /* Bits 10-31: Reserved */ - -/* Status Register */ - -#define LPSPI_SR_TDF (1 << 0) /* Bit 0: Transmit Data Flag */ -#define LPSPI_SR_RDF (1 << 1) /* Bit 1: Receive Data Flag */ - /* Bits 2-7: Reserved */ -#define LPSPI_SR_WCF (1 << 8) /* Bit 8: Word Complete Flag */ -#define LPSPI_SR_FCF (1 << 9) /* Bit 9: Frame Complete Flag */ -#define LPSPI_SR_TCF (1 << 10) /* Bit 10: Transfer Complete Flag */ -#define LPSPI_SR_TEF (1 << 11) /* Bit 11: Transmit Error Flag */ -#define LPSPI_SR_REF (1 << 12) /* Bit 12: Receive Error Flag */ -#define LPSPI_SR_DMF (1 << 13) /* Bit 13: Data Match Flag */ - /* Bits 14-23: Reserved */ -#define LPSPI_SR_MBF (1 << 24) /* Bit 24: Module Busy Flag */ - /* Bits 25-31: Reserved */ - -/* Interrupt Enable Register */ - -#define LPSPI_IER_TDIE (1 << 0) /* Bit 0: Transmit Data Interrupt Enable */ -#define LPSPI_IER_RDIE (1 << 1) /* Bit 1: Receive Data Interrupt Enable */ - /* Bits 2-7: Reserved */ -#define LPSPI_IER_WCIE (1 << 8) /* Bit 8: Word Complete Interrupt Enable */ -#define LPSPI_IER_FCIE (1 << 9) /* Bit 9: Frame Complete Interrupt Enable */ -#define LPSPI_IER_TCIE (1 << 10) /* Bit 10: Transfer Complete Interrupt Enable */ -#define LPSPI_IER_TEIE (1 << 11) /* Bit 11: Transmit Error Interrupt Enable */ -#define LPSPI_IER_REIE (1 << 12) /* Bit 12: Receive Error Interrupt Enable */ -#define LPSPI_IER_DMIE (1 << 13) /* Bit 13: Data Match Interrupt Enable */ - /* Bits 14-31: Reserved */ - -/* DMA Enable Register */ - -#define LPSPI_DER_TDDE (1 << 0) /* Bit 0: Transmit Data DMA Enable */ -#define LPSPI_DER_RDDE (1 << 1) /* Bit 1: Receive Data DMA Enable */ - /* Bits 2-31: Reserved */ - -/* Configuration Register 0 */ - -#define LPSPI_CFGR0_HREN (1 << 0) /* Bit 0: Host Request Enable */ -#define LPSPI_CFGR0_HRPOL (1 << 1) /* Bit 1: Host Request Polarity */ -# define LPSPI_CFGR0_HRPOL_LOW (0 << 1) /* Active low */ -# define LPSPI_CFGR0_HRPOL_HIGH (1 << 1) /* Active high */ -#define LPSPI_CFGR0_HRSEL (1 << 2) /* Bit 2: Host Request Select */ -# define LPSPI_CFGR0_HRSEL_HREQ (0 << 2) /* Host request input is the LPSPI_HREQ pin */ -# define LPSPI_CFGR0_HRSEL_INTR (1 << 2) /* Host request input is the input trigger */ - /* Bits 3-7: Reserved */ -#define LPSPI_CFGR0_CIRFIFO (1 << 8) /* Bits 8: Circular FIFO Enable */ -#define LPSPI_CFGR0_RDMO (1 << 9) /* Bits 9: Receive Data Match Only */ -# define LPSPI_CFGR0_RDMO_FIFO (0 << 9) /* RD stored in the receive FIFO as in normal operations */ -# define LPSPI_CFGR0_RDMO_DMF (1 << 9) /* RD discarded unless the Data Match Flag (DMF) is set */ - /* Bits 10-31: Reserved */ - -/* Configuration Register 1 */ - -#define LPSPI_CFGR1_MASTER (1 << 0) /* Bit 0: Master Mode */ -#define LPSPI_CFGR1_SAMPLE (1 << 1) /* Bit 1: Sample Point */ -# define LPSPI_CFGR1_SAMPLE_SCK (0 << 1) /* Input data is sampled on SCK edge */ -# define LPSPI_CFGR1_SAMPLE_DELAY (1 << 1) /* Input data is sampled on delayed SCK edge */ -#define LPSPI_CFGR1_AUTOPCS (1 << 2) /* Bit 2: Automatic PCS enabled */ -#define LPSPI_CFGR1_NOSTALL (1 << 3) /* Bit 3: No Stall enabled */ - /* Bits 4-7: Reserved */ -#define LPSPI_CFGR1_PCSPOL_SHIFT (8) /* Bits 8-11: Peripheral Chip Select Polarity */ -#define LPSPI_CFGR1_PCSPOL_MASK (0xf << LPSPI_CFGR1_PCSPOL_SHIFT) -# define LPSPI_CFGR1_PCSPOL_LOW (0 << LPSPI_CFGR1_PCSPOL_SHIFT) /* The Peripheral Chip Select pin PCSx is active low */ -# define LPSPI_CFGR1_PCSPOL_HIGH (1 << LPSPI_CFGR1_PCSPOL_SHIFT) /* The Peripheral Chip Select pin PCSx is active high */ - /* Bits 12-15: Reserved */ -#define LPSPI_CFGR1_MATCFG_SHIFT (16) /* Bits 16-18: Match Configuration */ -#define LPSPI_CFGR1_MATCFG_MASK (7 << LPSPI_CFGR1_MATCFG_SHIFT) -# define LPSPI_CFGR1_MATCFG(n) ((uint32_t)(n) << LPSPI_CFGR1_MATCFG_SHIFT) - /* Bits 19-23: Reserved */ -#define LPSPI_CFGR1_PINCFG_SHIFT (24) /* Bits 24-25: Pin Configuration */ -#define LPSPI_CFGR1_PINCFG_MASK (3 << LPSPI_CFGR1_PINCFG_SHIFT) -# define LPSPI_CFGR1_PINCFG_SIN_SOUT (0 << LPSPI_CFGR1_PINCFG_SHIFT) /* SIN is used for input data and SOUT is used for output data */ -# define LPSPI_CFGR1_PINCFG_SIN_SIN (1 << LPSPI_CFGR1_PINCFG_SHIFT) /* SIN is used for both input and output data */ -# define LPSPI_CFGR1_PINCFG_SOUT_SOUT (2 << LPSPI_CFGR1_PINCFG_SHIFT) /* SOUT is used for both input and output data */ -# define LPSPI_CFGR1_PINCFG_SOUT_SIN (3 << LPSPI_CFGR1_PINCFG_SHIFT) /* SOUT is used for input data and SIN is used for output data */ -# define LPSPI_CFGR1_PINCFG(n) ((uint32_t)(n) << LPSPI_CFGR1_PINCFG_SHIFT) -#define LPSPI_CFGR1_OUTCFG (1 << 26) /* Bit 26: Output Config */ -# define LPSPI_CFGR1_OUTCFG_RETAIN (0 << 26) /* Output data retains last value when chip select is negated */ -# define LPSPI_CFGR1_OUTCFG_TRISTATE (1 << 26) /* Output data is tristated when chip select is negated */ -#define LPSPI_CFGR1_PCSCFG (1 << 27) /* Bit 27: Peripheral Chip Select Configuration */ -# define LPSPI_CFGR1_PCSCFG_EN (0 << 27) /* PCS[3:2] are enabled */ -# define LPSPI_CFGR1_PCSCFG_DIS (1 << 27) /* PCS[3:2] are disabled */ - /* Bits 28-31: Reserved */ - -/* Data Match Register 0 */ - -#define LPSPI_DMR0_MATCH0_SHIFT (0) /* Bits 0-31: Match 0 Value */ -#define LPSPI_DMR0_MATCH0_MASK (0xffffffff << LPSPI_DMR0_MATCH0_SHIFT) -# define LPSPI_DMR0_MATCH0(n) ((uint32_t)(n) << LPSPI_DMR0_MATCH0_SHIFT) - -/* Data Match Register 0 */ - -#define LPSPI_DMR1_MATCH1_SHIFT (0) /* Bits 0-31: Match 1 Value */ -#define LPSPI_DMR1_MATCH1_MASK (0xffffffff << LPSPI_DMR1_MATCH1_SHIFT) -# define LPSPI_DMR1_MATCH1(n) ((uint32_t)(n) << LPSPI_DMR1_MATCH1_SHIFT) - -/* Clock Configuration Register */ - -#define LPSPI_CCR_SCKDIV_SHIFT (0) /* Bits 0-7: SCK Divider */ -#define LPSPI_CCR_SCKDIV_MASK (0xff << LPSPI_CCR_SCKDIV_SHIFT) -# define LPSPI_CCR_SCKDIV(n) ((uint32_t)(n) << LPSPI_CCR_SCKDIV_SHIFT) -#define LPSPI_CCR_DBT_SHIFT (8) /* Bits 8-15: Delay Between Transfers */ -#define LPSPI_CCR_DBT_MASK (0xff << LPSPI_CCR_DBT_SHIFT) -# define LPSPI_CCR_DBT(n) ((uint32_t)(n) << LPSPI_CCR_DBT_SHIFT) -#define LPSPI_CCR_PCSSCK_SHIFT (16) /* Bits 16-23: PCS-to-SCK Delay */ -#define LPSPI_CCR_PCSSCK_MASK (0xff << LPSPI_CCR_PCSSCK_SHIFT) -# define LPSPI_CCR_PCSSCK(n) ((uint32_t)(n) << LPSPI_CCR_PCSSCK_SHIFT) -#define LPSPI_CCR_SCKPCS_SHIFT (24) /* Bits 24-31: SCK-to-PCS Delay */ -#define LPSPI_CCR_SCKPCS_MASK (0xff << LPSPI_CCR_SCKPCS_SHIFT) -# define LPSPI_CCR_SCKPCS(n) ((uint32_t)(n) << LPSPI_CCR_SCKPCS_SHIFT) - -/* FIFO Control Register */ - -#define LPSPI_FCR_TXWATER_SHIFT (0) /* Bits 0-3: Transmit FIFO Watermark */ -#define LPSPI_FCR_TXWATER_MASK (0xf << LPSPI_FCR_TXWATER_SHIFT) -# define LPSPI_FCR_TXWATER(n) ((uint32_t)(n) << LPSPI_FCR_TXWATER_SHIFT) - /* Bits 4-7: Reserved */ - /* Bits 8-15: Reserved */ -#define LPSPI_FCR_RXWATER_SHIFT (8) /* Bits 16-19: Receive FIFO Watermark */ -#define LPSPI_FCR_RXWATER_MASK (0xf << LPSPI_FCR_RXWATER_SHIFT) -# define LPSPI_FCR_RXWATER(n) ((uint32_t)(n) << LPSPI_FCR_RXWATER_SHIFT) - /* Bits 20-23: Reserved */ - /* Bits 24-31: Reserved */ - -/* FIFO Status Register */ - -#define LPSPI_FSR_TXCOUNT_SHIFT (0) /* Bits 0-4: Transmit FIFO Count */ -#define LPSPI_FSR_TXCOUNT_MASK (0x1f << LPSPI_FSR_TXCOUNT_SHIFT) - /* Bits 5-7: Reserved */ - /* Bits 8-15: Reserved */ -#define LPSPI_FSR_RXCOUNT_SHIFT (16) /* Bits 16-20: Receive FIFO Count */ -#define LPSPI_FSR_RXCOUNT_MASK (0x1f << LPSPI_FSR_RXCOUNT_SHIFT) - /* Bits 21-23: Reserved */ - /* Bits 24-31: Reserved */ - -/* Transmit Command Register */ - -#define LPSPI_TCR_FRAMESZ_SHIFT (0) /* Bits 0-11: Frame Size */ -#define LPSPI_TCR_FRAMESZ_MASK (0xfff << LPSPI_TCR_FRAMESZ_SHIFT) -# define LPSPI_TCR_FRAMESZ(n) ((uint32_t)(n) << LPSPI_TCR_FRAMESZ_SHIFT) - /* Bits 12-15: Reserved */ -#define LPSPI_TCR_WIDTH_SHIFT (16) /* Bits 16-17: Transfer Width */ -#define LPSPI_TCR_WIDTH_MASK (3 << LPSPI_TCR_WIDTH_SHIFT) -# define LPSPI_TCR_WIDTH_1BIT (0 << LPSPI_TCR_WIDTH_SHIFT) /* 1 bit transfer */ -# define LPSPI_TCR_WIDTH_2BIT (1 << LPSPI_TCR_WIDTH_SHIFT) /* 2 bit transfer */ -# define LPSPI_TCR_WIDTH_4BIT (2 << LPSPI_TCR_WIDTH_SHIFT) /* 4 bit transfer */ -#define LPSPI_TCR_TXMSK (1 << 18) /* Bit 18: Transmit Data Mask */ -#define LPSPI_TCR_RXMSK (1 << 19) /* Bit 19: Receive Data Mask */ -#define LPSPI_TCR_CONTC (1 << 20) /* Bit 20: Continuing Command */ -#define LPSPI_TCR_CONT (1 << 21) /* Bit 21: Continuous Transfer */ -#define LPSPI_TCR_BYSW (1 << 22) /* Bit 22: Byte Swap */ -#define LPSPI_TCR_LSBF (1 << 23) /* Bit 23: LSB First */ -# define LPSPI_TCR_MSBF (0 << 23) /* MSB First */ -#define LPSPI_TCR_PCS_SHIFT (24) /* Bits 24-25: Peripheral Chip Select */ -#define LPSPI_TCR_PCS_MASK (3 << LPSPI_TCR_PCS_SHIFT) -# define LPSPI_TCR_PCS_0 (0 << LPSPI_TCR_PCS_SHIFT) /* Transfer using LPSPI_PCS[0] */ -# define LPSPI_TCR_PCS_1 (1 << LPSPI_TCR_PCS_SHIFT) /* Transfer using LPSPI_PCS[1] */ -# define LPSPI_TCR_PCS_2 (2 << LPSPI_TCR_PCS_SHIFT) /* Transfer using LPSPI_PCS[2] */ -# define LPSPI_TCR_PCS_3 (3 << LPSPI_TCR_PCS_SHIFT) /* Transfer using LPSPI_PCS[3] */ - /* Bit 26: Reserved */ -#define LPSPI_TCR_PRESCALE_SHIFT (27) /* Bits 27-29: Prescaler Value */ -#define LPSPI_TCR_PRESCALE_MASK (7 << LPSPI_TCR_PRESCALE_SHIFT) -# define LPSPI_TCR_PRESCALE_1 (0 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 1 */ -# define LPSPI_TCR_PRESCALE_2 (1 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 2 */ -# define LPSPI_TCR_PRESCALE_4 (2 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 4 */ -# define LPSPI_TCR_PRESCALE_8 (3 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 8 */ -# define LPSPI_TCR_PRESCALE_16 (4 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 16 */ -# define LPSPI_TCR_PRESCALE_32 (5 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 32 */ -# define LPSPI_TCR_PRESCALE_64 (6 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 64 */ -# define LPSPI_TCR_PRESCALE_128 (7 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 128 */ -# define LPSPI_TCR_PRESCALE(n) ((uint32_t)(n) << LPSPI_TCR_PRESCALE_SHIFT) -#define LPSPI_TCR_CPHA (1 << 30) /* Bit 30: Clock Phase */ -# define LPSPI_TCR_CPHA_CPT_LEAD (0 << 30) /* Data captured - leading edge of SCK and changed - following edge of SCK */ -# define LPSPI_TCR_CPHA_CPT_FOLLOW (1 << 30) /* Data changed - leading edge of SCK and captured - following edge of SCK */ -#define LPSPI_TCR_CPOL (1 << 31) /* Bit 31: Clock Polarity */ -# define LPSPI_TCR_CPOL_INACT_LOW (0 << 31) /* The inactive state value of SCK is low */ -# define LPSPI_TCR_CPOL_INACT_HIGH (1 << 31) /* The inactive state value of SCK is high */ - -/* Transmit Data Register */ - -#define LPSPI_TDR_DATA_SHIFT (0) /* Bits 0-31: Transmit Data */ -# define LPSPI_TCR_DATA(n) ((uint32_t)(n) << LPSPI_TDR_DATA_SHIFT) - -/* Receive Status Register */ - -#define LPSPI_RSR_SOF (1 << 0) /* Bit 0: Start Of Frame */ -#define LPSPI_RSR_RXEMPTY (1 << 1) /* Bit 1: RX FIFO Empty */ - /* Bits 2-31: Reserved */ - -/* Receive Data Register */ - -#define LPSPI_RDR_DATA_SHIFT (0) /* Bits 0-31: Receive Data */ -#define LPSPI_RDR_DATA_MASK (0xffffffff << LPSPI_RDR_DATA_SHIFT) - -#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_LPSPI_H */ diff --git a/arch/arm/src/imxrt/chip/imxrt_lpuart.h b/arch/arm/src/imxrt/chip/imxrt_lpuart.h deleted file mode 100644 index 2ea9e584465..00000000000 --- a/arch/arm/src/imxrt/chip/imxrt_lpuart.h +++ /dev/null @@ -1,416 +0,0 @@ -/******************************************************************************************** - * arch/arm/src/imxrt/imxrt_lpuart.h - * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ********************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_LPUART_H -#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_LPUART_H - -/******************************************************************************************** - * Included Files - ********************************************************************************************/ - -#include -#include "chip/imxrt_memorymap.h" - -/******************************************************************************************** - * Pre-processor Definitions - ********************************************************************************************/ - -/* Register offsets *************************************************************************/ - -#define IMXRT_LPUART_VERID_OFFSET 0x0000 /* Version ID Register */ -#define IMXRT_LPUART_PARAM_OFFSET 0x0004 /* Parameter Register */ -#define IMXRT_LPUART_GLOBAL_OFFSET 0x0008 /* LPUART Global Register */ -#define IMXRT_LPUART_PINCFG_OFFSET 0x000c /* LPUART Pin Configuration Register */ -#define IMXRT_LPUART_BAUD_OFFSET 0x0010 /* LPUART Baud Rate Register */ -#define IMXRT_LPUART_STAT_OFFSET 0x0014 /* LPUART Status Register */ -#define IMXRT_LPUART_CTRL_OFFSET 0x0018 /* LPUART Control Register */ -#define IMXRT_LPUART_DATA_OFFSET 0x001c /* LPUART Data Register */ -#define IMXRT_LPUART_MATCH_OFFSET 0x0020 /* LPUART Match Address Register */ -#define IMXRT_LPUART_MODIR_OFFSET 0x0024 /* LPUART Modem IrDA Register */ -#define IMXRT_LPUART_FIFO_OFFSET 0x0028 /* LPUART FIFO Register */ -#define IMXRT_LPUART_WATER_OFFSET 0x002c /* LPUART Watermark Register */ - -/* Register addresses ***********************************************************************/ - -#define IMXRT_LPUART1_VERID (IMXRT_LPUART1_BASE + IMXRT_LPUART_VERID_OFFSET) -#define IMXRT_LPUART1_PARAM (IMXRT_LPUART1_BASE + IMXRT_LPUART_PARAM_OFFSET) -#define IMXRT_LPUART1_GLOBAL (IMXRT_LPUART1_BASE + IMXRT_LPUART_GLOBAL_OFFSET) -#define IMXRT_LPUART1_PINCFG (IMXRT_LPUART1_BASE + IMXRT_LPUART_PINCFG_OFFSET) -#define IMXRT_LPUART1_BAUD (IMXRT_LPUART1_BASE + IMXRT_LPUART_BAUD_OFFSET) -#define IMXRT_LPUART1_STAT (IMXRT_LPUART1_BASE + IMXRT_LPUART_STAT_OFFSET) -#define IMXRT_LPUART1_CTRL (IMXRT_LPUART1_BASE + IMXRT_LPUART_CTRL_OFFSET) -#define IMXRT_LPUART1_DATA (IMXRT_LPUART1_BASE + IMXRT_LPUART_DATA_OFFSET) -#define IMXRT_LPUART1_MATCH (IMXRT_LPUART1_BASE + IMXRT_LPUART_MATCH_OFFSET) -#define IMXRT_LPUART1_MODIR (IMXRT_LPUART1_BASE + IMXRT_LPUART_MODIR_OFFSET) -#define IMXRT_LPUART1_FIFO (IMXRT_LPUART1_BASE + IMXRT_LPUART_FIFO_OFFSET) -#define IMXRT_LPUART1_WATER (IMXRT_LPUART1_BASE + IMXRT_LPUART_WATER_OFFSET) - -#define IMXRT_LPUART2_VERID (IMXRT_LPUART2_BASE + IMXRT_LPUART_VERID_OFFSET) -#define IMXRT_LPUART2_PARAM (IMXRT_LPUART2_BASE + IMXRT_LPUART_PARAM_OFFSET) -#define IMXRT_LPUART2_GLOBAL (IMXRT_LPUART2_BASE + IMXRT_LPUART_GLOBAL_OFFSET) -#define IMXRT_LPUART2_PINCFG (IMXRT_LPUART2_BASE + IMXRT_LPUART_PINCFG_OFFSET) -#define IMXRT_LPUART2_BAUD (IMXRT_LPUART2_BASE + IMXRT_LPUART_BAUD_OFFSET) -#define IMXRT_LPUART2_STAT (IMXRT_LPUART2_BASE + IMXRT_LPUART_STAT_OFFSET) -#define IMXRT_LPUART2_CTRL (IMXRT_LPUART2_BASE + IMXRT_LPUART_CTRL_OFFSET) -#define IMXRT_LPUART2_DATA (IMXRT_LPUART2_BASE + IMXRT_LPUART_DATA_OFFSET) -#define IMXRT_LPUART2_MATCH (IMXRT_LPUART2_BASE + IMXRT_LPUART_MATCH_OFFSET) -#define IMXRT_LPUART2_MODIR (IMXRT_LPUART2_BASE + IMXRT_LPUART_MODIR_OFFSET) -#define IMXRT_LPUART2_FIFO (IMXRT_LPUART2_BASE + IMXRT_LPUART_FIFO_OFFSET) -#define IMXRT_LPUART2_WATER (IMXRT_LPUART2_BASE + IMXRT_LPUART_WATER_OFFSET) - -#define IMXRT_LPUART3_VERID (IMXRT_LPUART3_BASE + IMXRT_LPUART_VERID_OFFSET) -#define IMXRT_LPUART3_PARAM (IMXRT_LPUART3_BASE + IMXRT_LPUART_PARAM_OFFSET) -#define IMXRT_LPUART3_GLOBAL (IMXRT_LPUART3_BASE + IMXRT_LPUART_GLOBAL_OFFSET) -#define IMXRT_LPUART3_PINCFG (IMXRT_LPUART3_BASE + IMXRT_LPUART_PINCFG_OFFSET) -#define IMXRT_LPUART3_BAUD (IMXRT_LPUART3_BASE + IMXRT_LPUART_BAUD_OFFSET) -#define IMXRT_LPUART3_STAT (IMXRT_LPUART3_BASE + IMXRT_LPUART_STAT_OFFSET) -#define IMXRT_LPUART3_CTRL (IMXRT_LPUART3_BASE + IMXRT_LPUART_CTRL_OFFSET) -#define IMXRT_LPUART3_DATA (IMXRT_LPUART3_BASE + IMXRT_LPUART_DATA_OFFSET) -#define IMXRT_LPUART3_MATCH (IMXRT_LPUART3_BASE + IMXRT_LPUART_MATCH_OFFSET) -#define IMXRT_LPUART3_MODIR (IMXRT_LPUART3_BASE + IMXRT_LPUART_MODIR_OFFSET) -#define IMXRT_LPUART3_FIFO (IMXRT_LPUART3_BASE + IMXRT_LPUART_FIFO_OFFSET) -#define IMXRT_LPUART3_WATER (IMXRT_LPUART3_BASE + IMXRT_LPUART_WATER_OFFSET) - -#define IMXRT_LPUART4_VERID (IMXRT_LPUART4_BASE + IMXRT_LPUART_VERID_OFFSET) -#define IMXRT_LPUART4_PARAM (IMXRT_LPUART4_BASE + IMXRT_LPUART_PARAM_OFFSET) -#define IMXRT_LPUART4_GLOBAL (IMXRT_LPUART4_BASE + IMXRT_LPUART_GLOBAL_OFFSET) -#define IMXRT_LPUART4_PINCFG (IMXRT_LPUART4_BASE + IMXRT_LPUART_PINCFG_OFFSET) -#define IMXRT_LPUART4_BAUD (IMXRT_LPUART4_BASE + IMXRT_LPUART_BAUD_OFFSET) -#define IMXRT_LPUART4_STAT (IMXRT_LPUART4_BASE + IMXRT_LPUART_STAT_OFFSET) -#define IMXRT_LPUART4_CTRL (IMXRT_LPUART4_BASE + IMXRT_LPUART_CTRL_OFFSET) -#define IMXRT_LPUART4_DATA (IMXRT_LPUART4_BASE + IMXRT_LPUART_DATA_OFFSET) -#define IMXRT_LPUART4_MATCH (IMXRT_LPUART4_BASE + IMXRT_LPUART_MATCH_OFFSET) -#define IMXRT_LPUART4_MODIR (IMXRT_LPUART4_BASE + IMXRT_LPUART_MODIR_OFFSET) -#define IMXRT_LPUART4_FIFO (IMXRT_LPUART4_BASE + IMXRT_LPUART_FIFO_OFFSET) -#define IMXRT_LPUART4_WATER (IMXRT_LPUART4_BASE + IMXRT_LPUART_WATER_OFFSET) - -#define IMXRT_LPUART5_VERID (IMXRT_LPUART5_BASE + IMXRT_LPUART_VERID_OFFSET) -#define IMXRT_LPUART5_PARAM (IMXRT_LPUART5_BASE + IMXRT_LPUART_PARAM_OFFSET) -#define IMXRT_LPUART5_GLOBAL (IMXRT_LPUART5_BASE + IMXRT_LPUART_GLOBAL_OFFSET) -#define IMXRT_LPUART5_PINCFG (IMXRT_LPUART5_BASE + IMXRT_LPUART_PINCFG_OFFSET) -#define IMXRT_LPUART5_BAUD (IMXRT_LPUART5_BASE + IMXRT_LPUART_BAUD_OFFSET) -#define IMXRT_LPUART5_STAT (IMXRT_LPUART5_BASE + IMXRT_LPUART_STAT_OFFSET) -#define IMXRT_LPUART5_CTRL (IMXRT_LPUART5_BASE + IMXRT_LPUART_CTRL_OFFSET) -#define IMXRT_LPUART5_DATA (IMXRT_LPUART5_BASE + IMXRT_LPUART_DATA_OFFSET) -#define IMXRT_LPUART5_MATCH (IMXRT_LPUART5_BASE + IMXRT_LPUART_MATCH_OFFSET) -#define IMXRT_LPUART5_MODIR (IMXRT_LPUART5_BASE + IMXRT_LPUART_MODIR_OFFSET) -#define IMXRT_LPUART5_FIFO (IMXRT_LPUART5_BASE + IMXRT_LPUART_FIFO_OFFSET) -#define IMXRT_LPUART5_WATER (IMXRT_LPUART5_BASE + IMXRT_LPUART_WATER_OFFSET) - -#define IMXRT_LPUART6_VERID (IMXRT_LPUART6_BASE + IMXRT_LPUART_VERID_OFFSET) -#define IMXRT_LPUART6_PARAM (IMXRT_LPUART6_BASE + IMXRT_LPUART_PARAM_OFFSET) -#define IMXRT_LPUART6_GLOBAL (IMXRT_LPUART6_BASE + IMXRT_LPUART_GLOBAL_OFFSET) -#define IMXRT_LPUART6_PINCFG (IMXRT_LPUART6_BASE + IMXRT_LPUART_PINCFG_OFFSET) -#define IMXRT_LPUART6_BAUD (IMXRT_LPUART6_BASE + IMXRT_LPUART_BAUD_OFFSET) -#define IMXRT_LPUART6_STAT (IMXRT_LPUART6_BASE + IMXRT_LPUART_STAT_OFFSET) -#define IMXRT_LPUART6_CTRL (IMXRT_LPUART6_BASE + IMXRT_LPUART_CTRL_OFFSET) -#define IMXRT_LPUART6_DATA (IMXRT_LPUART6_BASE + IMXRT_LPUART_DATA_OFFSET) -#define IMXRT_LPUART6_MATCH (IMXRT_LPUART6_BASE + IMXRT_LPUART_MATCH_OFFSET) -#define IMXRT_LPUART6_MODIR (IMXRT_LPUART6_BASE + IMXRT_LPUART_MODIR_OFFSET) -#define IMXRT_LPUART6_FIFO (IMXRT_LPUART6_BASE + IMXRT_LPUART_FIFO_OFFSET) -#define IMXRT_LPUART6_WATER (IMXRT_LPUART6_BASE + IMXRT_LPUART_WATER_OFFSET) - -#define IMXRT_LPUART7_VERID (IMXRT_LPUART7_BASE + IMXRT_LPUART_VERID_OFFSET) -#define IMXRT_LPUART7_PARAM (IMXRT_LPUART7_BASE + IMXRT_LPUART_PARAM_OFFSET) -#define IMXRT_LPUART7_GLOBAL (IMXRT_LPUART7_BASE + IMXRT_LPUART_GLOBAL_OFFSET) -#define IMXRT_LPUART7_PINCFG (IMXRT_LPUART7_BASE + IMXRT_LPUART_PINCFG_OFFSET) -#define IMXRT_LPUART7_BAUD (IMXRT_LPUART7_BASE + IMXRT_LPUART_BAUD_OFFSET) -#define IMXRT_LPUART7_STAT (IMXRT_LPUART7_BASE + IMXRT_LPUART_STAT_OFFSET) -#define IMXRT_LPUART7_CTRL (IMXRT_LPUART7_BASE + IMXRT_LPUART_CTRL_OFFSET) -#define IMXRT_LPUART7_DATA (IMXRT_LPUART7_BASE + IMXRT_LPUART_DATA_OFFSET) -#define IMXRT_LPUART7_MATCH (IMXRT_LPUART7_BASE + IMXRT_LPUART_MATCH_OFFSET) -#define IMXRT_LPUART7_MODIR (IMXRT_LPUART7_BASE + IMXRT_LPUART_MODIR_OFFSET) -#define IMXRT_LPUART7_FIFO (IMXRT_LPUART7_BASE + IMXRT_LPUART_FIFO_OFFSET) -#define IMXRT_LPUART7_WATER (IMXRT_LPUART7_BASE + IMXRT_LPUART_WATER_OFFSET) - -#define IMXRT_LPUART8_VERID (IMXRT_LPUART8_BASE + IMXRT_LPUART_VERID_OFFSET) -#define IMXRT_LPUART8_PARAM (IMXRT_LPUART8_BASE + IMXRT_LPUART_PARAM_OFFSET) -#define IMXRT_LPUART8_GLOBAL (IMXRT_LPUART8_BASE + IMXRT_LPUART_GLOBAL_OFFSET) -#define IMXRT_LPUART8_PINCFG (IMXRT_LPUART8_BASE + IMXRT_LPUART_PINCFG_OFFSET) -#define IMXRT_LPUART8_BAUD (IMXRT_LPUART8_BASE + IMXRT_LPUART_BAUD_OFFSET) -#define IMXRT_LPUART8_STAT (IMXRT_LPUART8_BASE + IMXRT_LPUART_STAT_OFFSET) -#define IMXRT_LPUART8_CTRL (IMXRT_LPUART8_BASE + IMXRT_LPUART_CTRL_OFFSET) -#define IMXRT_LPUART8_DATA (IMXRT_LPUART8_BASE + IMXRT_LPUART_DATA_OFFSET) -#define IMXRT_LPUART8_MATCH (IMXRT_LPUART8_BASE + IMXRT_LPUART_MATCH_OFFSET) -#define IMXRT_LPUART8_MODIR (IMXRT_LPUART8_BASE + IMXRT_LPUART_MODIR_OFFSET) -#define IMXRT_LPUART8_FIFO (IMXRT_LPUART8_BASE + IMXRT_LPUART_FIFO_OFFSET) -#define IMXRT_LPUART8_WATER (IMXRT_LPUART8_BASE + IMXRT_LPUART_WATER_OFFSET) - -/* Register bit definitions *****************************************************************/ - -/* Version ID Register */ - -#define LPUART_VERID_FEATURE_SHIFT (0) /* Bits 0-15: Feature Identification Number */ -#define LPUART_VERID_FEATURE_MASK (0xffff << LPUART_VERID_FEATURE_SHIFT) -# define LPUART_VERID_FEATURE_STD (1 << LPUART_VERID_FEATURE_SHIFT) /* Standard feature set */ -# define LPUART_VERID_FEATURE_MODEM (3 << LPUART_VERID_FEATURE_SHIFT) /* MODEM/IrDA support */ -#define LPUART_VERID_MINOR_SHIFT (16) /* Bits 16-23: Minor Version Number */ -#define LPUART_VERID_MINOR_MASK (0xff << LPUART_VERID_MINOR_SHIFT) -#define LPUART_VERID_MAJOR_SHIFT (24) /* Bits 24-31: Major Version Number */ -#define LPUART_VERID_MAJOR_MASK (0xff << LPUART_VERID_MAJOR_SHIFT) - -/* Parameter Register */ - -#define LPUART_PARAM_TXFIFO_SHIFT (0) /* Bits 0-7: Transmit FIFO Size */ -#define LPUART_PARAM_TXFIFO_MASK (0xff << LPUART_PARAM_TXFIFO_SHIFT) -#define LPUART_PARAM_RXFIFO_SHIFT (8) /* Bits 8-15: Transmit FIFO Size */ -#define LPUART_PARAM_RXFIFO_MASK (0xff << LPUART_PARAM_RXFIFO_SHIFT) - /* Bits 16-31: Reserved */ - -/* LPUART Global Register */ - - /* Bit 0: Reserved */ -#define LPUART_GLOBAL_RST (1 << 1) /* Bit 1: Software Reset */ - /* Bits 2-31: Reserved */ - -/* LPUART Pin Configuration Register */ - -#define LPUART_PINCFG_TRGSEL_SHIFT (0) /* Bits 0-1: Trigger Select */ -#define LPUART_PINCFG_TRGSEL_MASK (3 << LPUART_PINCFG_TRGSEL_SHIFT) -# define LPUART_PINCFG_TRGSEL_DISABLE (0 << LPUART_PINCFG_TRGSEL_SHIFT) /* Trigger disabled */ -# define LPUART_PINCFG_TRGSEL_RXD (1 << LPUART_PINCFG_TRGSEL_SHIFT) /* Trigger used instead of RXD pin */ -# define LPUART_PINCFG_TRGSEL_CTSB (2 << LPUART_PINCFG_TRGSEL_SHIFT) /* Trigger used instead of CTS_B pin */ -# define LPUART_PINCFG_TRGSEL_TXDMOD (3 << LPUART_PINCFG_TRGSEL_SHIFT) /* Trigger used to modulate the TXD output */ - /* Bits 2-31: Reserved */ - -/* LPUART Baud Rate Register */ - -#define LPUART_BAUD_SBR_SHIFT (0) /* Bits 0-12: Baud Rate Modulo Divisor. */ -#define LPUART_BAUD_SBR_MASK (0x1fff << LPUART_BAUD_SBR_SHIFT) -# define LPUART_BAUD_SBR(n) ((uint32_t)(n) << LPUART_BAUD_SBR_SHIFT) -#define LPUART_BAUD_SBNS (1 << 13) /* Bit 13: Stop Bit Number Select */ -#define LPUART_BAUD_RXEDGIE (1 << 14) /* Bit 14: RX Input Active Edge Interrupt Enable */ -#define LPUART_BAUD_LBKDIE (1 << 15) /* Bit 15: LIN Break Detect Interrupt Enable */ -#define LPUART_BAUD_RESYNCDIS (1 << 16) /* Bit 16: Resynchronization Disable */ -#define LPUART_BAUD_BOTHEDGE (1 << 17) /* Bit 17: Both Edge Sampling */ -#define LPUART_BAUD_MATCFG_SHIFT (18) /* Bits 18-19: Match Configuration */ -#define LPUART_BAUD_MATCFG_MASK (3 << LPUART_BAUD_MATCFG_SHIFT) -# define LPUART_BAUD_MATCFG_ADDR (0 << LPUART_BAUD_MATCFG_SHIFT) /* Address Match Wakeup */ -# define LPUART_BAUD_MATCFG_IDLE (1 << LPUART_BAUD_MATCFG_SHIFT) /* Idle Match Wakeup */ -# define LPUART_BAUD_MATCFG_ONOFF (2 << LPUART_BAUD_MATCFG_SHIFT) /* Match On and Match Off */ -# define LPUART_BAUD_MATCFG_RWUENAB (3 << LPUART_BAUD_MATCFG_SHIFT) /* Enables RWU on Data Match and Match - * On/Off for transmitter CTS input */ - /* Bit 20: Reserved */ -#define LPUART_BAUD_RDMAE (1 << 21) /* Bit 21: Receiver Full DMA Enable */ - /* Bit 22: Reserved */ -#define LPUART_BAUD_TDMAE (1 << 23) /* Bit 23: Transmitter DMA Enable */ -#define LPUART_BAUD_OSR_SHIFT (24) /* Bits 24-28: Oversampling Ratio */ -#define LPUART_BAUD_OSR_MASK (15 << LPUART_BAUD_OSR_SHIFT) -# define LPUART_BAUD_OSR(n) ((uint32_t)((n) - 1) << LPUART_BAUD_OSR_SHIFT) -#define LPUART_BAUD_M10 (1 << 29) /* Bit 20: 10-bit Mode select */ -#define LPUART_BAUD_MAEN2 (1 << 30) /* Bit 30: Match Address Mode Enable 2 */ -#define LPUART_BAUD_MAEN1 (1 << 31) /* Bit 31: Match Address Mode Enable 1 */ - -/* LPUART Status Register */ - - /* Bits 0-13: Reserved */ -#define LPUART_STAT_MA2F (1 << 14) /* Bit 14: Match 2 Flag */ -#define LPUART_STAT_MA1F (1 << 15) /* Bit 15: Match 1 Flag */ -#define LPUART_STAT_PF (1 << 16) /* Bit 16: Parity Error Flag */ -#define LPUART_STAT_FE (1 << 17) /* Bit 17: Framing Error Flag */ -#define LPUART_STAT_NF (1 << 18) /* Bit 18: Noise Flag */ -#define LPUART_STAT_OR (1 << 19) /* Bit 19: Receiver Overrun Flag */ -#define LPUART_STAT_IDLE (1 << 20) /* Bit 20: Idle Line Flag */ -#define LPUART_STAT_RDRF (1 << 21) /* Bit 21: Receive Data Register Full Flag */ -#define LPUART_STAT_TC (1 << 22) /* Bit 22: Transmission Complete Flag */ -#define LPUART_STAT_TDRE (1 << 23) /* Bit 23: Transmit Data Register Empty Flag */ -#define LPUART_STAT_RAF (1 << 24) /* Bit 24: Receiver Active Flag */ -#define LPUART_STAT_LBKDE (1 << 25) /* Bit 25: LIN Break Detection Enable */ -#define LPUART_STAT_BRK13 (1 << 26) /* Bit 26: Break Character Generation Length */ -#define LPUART_STAT_RWUID (1 << 27) /* Bit 27: Receive Wake Up Idle Detect */ -#define LPUART_STAT_RXINV (1 << 28) /* Bit 28: Receive Data Inversion */ -#define LPUART_STAT_MSBF (1 << 29) /* Bit 29: MSB First */ -#define LPUART_STAT_RXEDGIF (1 << 30) /* Bit 30: RXD Pin Active Edge Interrupt Flag */ -#define LPUART_STAT_LBKDIF (1 << 31) /* Bit 31: LIN Break Detect Interrupt Flag */ - -/* LPUART Control Register */ - -#define LPUART_CTRL_PT (1 << 0) /* Bit 0: Parity Type */ -# define LPUART_CTRL_PT_EVEN (0 << 0) /* Even parity */ -# define LPUART_CTRL_PT_ODD (1 << 0) /* Odd parity */ -#define LPUART_CTRL_PE (1 << 1) /* Bit 1: Parity Enable */ -#define LPUART_CTRL_ILT (1 << 2) /* Bit 2: Idle Line Type Select */ -#define LPUART_CTRL_WAKE (1 << 3) /* Bit 3: Receiver Wakeup Method Select */ -#define LPUART_CTRL_M (1 << 4) /* Bit 4: 9-Bit or 8-Bit Mode Select */ -#define LPUART_CTRL_RSRC (1 << 5) /* Bit 5: Receiver Source Select */ -#define LPUART_CTRL_DOZEEN (1 << 6) /* Bit 6: Doze Enable */ -#define LPUART_CTRL_LOOPS (1 << 7) /* Bit 7: Loop Mode Select */ -#define LPUART_CTRL_IDLECFG_SHIFT (8) /* Bits 8-10: Idle Configuration */ -#define LPUART_CTRL_IDLECFG_MASK (7 << LPUART_CTRL_IDLECFG_SHIFT) -# define LPUART_CTRL_IDLECFG_1 (0 << LPUART_CTRL_IDLECFG_SHIFT) /* 1 idle character */ -# define LPUART_CTRL_IDLECFG_2 (1 << LPUART_CTRL_IDLECFG_SHIFT) /* 2 idle characters */ -# define LPUART_CTRL_IDLECFG_4 (2 << LPUART_CTRL_IDLECFG_SHIFT) /* 4 idle characters */ -# define LPUART_CTRL_IDLECFG_8 (3 << LPUART_CTRL_IDLECFG_SHIFT) /* 8 idle characters */ -# define LPUART_CTRL_IDLECFG_16 (4 << LPUART_CTRL_IDLECFG_SHIFT) /* 6 idle characters */ -# define LPUART_CTRL_IDLECFG_32 (5 << LPUART_CTRL_IDLECFG_SHIFT) /* 32 idle characters */ -# define LPUART_CTRL_IDLECFG_64 (6 << LPUART_CTRL_IDLECFG_SHIFT) /* 64 idle characters */ -# define LPUART_CTRL_IDLECFG_128 (7 << LPUART_CTRL_IDLECFG_SHIFT) /* 128 idle characters */ -#define LPUART_CTRL_M7 (1 << 11) /* Bit 11: 7-Bit Mode Select */ - /* Bits 12-13: Reserved */ -#define LPUART_CTRL_MA2IE (1 << 14) /* Bit 14: Match 2 Interrupt Enable */ -#define LPUART_CTRL_MA1IE (1 << 15) /* Bit 15: Match 1 Interrupt Enable */ -#define LPUART_CTRL_SBK (1 << 16) /* Bit 16: Send Break */ -#define LPUART_CTRL_RWU (1 << 17) /* Bit 17: Receiver Wakeup Control */ -#define LPUART_CTRL_RE (1 << 18) /* Bit 18: Receiver Enable */ -#define LPUART_CTRL_TE (1 << 19) /* Bit 19: Transmitter Enable */ -#define LPUART_CTRL_ILIE (1 << 20) /* Bit 20: Idle Line Interrupt Enable */ -#define LPUART_CTRL_RIE (1 << 21) /* Bit 21: Receiver Interrupt Enable */ -#define LPUART_CTRL_TCIE (1 << 22) /* Bit 22: Transmission Complete Interrupt Enable */ -#define LPUART_CTRL_TIE (1 << 23) /* Bit 23: Transmit Interrupt Enable */ -#define LPUART_CTRL_PEIE (1 << 24) /* Bit 24: Parity Error Interrupt Enable */ -#define LPUART_CTRL_FEIE (1 << 25) /* Bit 25: Framing Error Interrupt Enable */ -#define LPUART_CTRL_NEIE (1 << 26) /* Bit 26: Noise Error Interrupt Enable */ -#define LPUART_CTRL_ORIE (1 << 27) /* Bit 27: Overrun Interrupt Enable */ -#define LPUART_CTRL_TXINV (1 << 28) /* Bit 28: Transmit Data Inversion */ -#define LPUART_CTRL_TXDIR (1 << 29) /* Bit 29: TXD Pin Direction in Single-Wire Mode */ -#define LPUART_CTRL_R9T8 (1 << 30) /* Bit 30: Receive Bit 9 / Transmit Bit 8 */ -#define LPUART_CTRL_R8T9 (1 << 31) /* Bit 31: Receive Bit 8 / Transmit Bit 9 */ - -#define LPUART_ALL_INTS (LPUART_CTRL_ORIE | LPUART_CTRL_NEIE | LPUART_CTRL_FEIE | \ - LPUART_CTRL_PEIE | LPUART_CTRL_TIE | LPUART_CTRL_TCIE | \ - LPUART_CTRL_RIE | LPUART_CTRL_ILIE | LPUART_CTRL_MA1IE | \ - LPUART_CTRL_MA2IE) - -/* LPUART Data Register */ - -#define LPUART_DATA_SHIFT (0) /* Bits 0-9: Data bits 0-9 */ -#define LPUART_DATA_MASK (0x3ff << LPUART_DATA_SHIFT) - /* Bit 10: Reserved */ -#define LPUART_DATA_STATUS_SHIFT (11) /* Bit 11: Idle Line status */ -#define LPUART_DATA_IDLINE (1 << 11) /* Bit 11: Idle Line */ -#define LPUART_DATA_RXEMPT (1 << 12) /* Bit 12: Receive Buffer Empty */ -#define LPUART_DATA_FRETSC (1 << 13) /* Bit 13: Frame Error / Transmit Special Character */ -#define LPUART_DATA_PARITYE (1 << 14) /* Bit 14: Parity Error */ -#define LPUART_DATA_NOISY (1 << 15) /* Bit 15: Noisy */ - /* Bits 16-31: Reserved */ - -/* LPUART Match Address Register */ - -#define LPUART_MATCH_MA1_SHIFT (0) /* Bits 0-9: Match Address 1 */ -#define LPUART_MATCH_MA1_MASK (0x3ff << LPUART_MATCH_MA1_SHIFT) -# define LPUART_MATCH_MA1(n) ((uint32_t)(n) << LPUART_MATCH_MA1_SHIFT) - /* Bits 10-15: Reserved */ -#define LPUART_MATCH_MA2_SHIFT (16) /* Bits 16-25: Match Address 2 */ -#define LPUART_MATCH_MA2_MASK (0x3ff << LPUART_MATCH_MA2_SHIFT) -# define LPUART_MATCH_MA2(n) ((uint32_t)(n) << LPUART_MATCH_MA2_SHIFT) - /* Bits 26-31: Reserved */ - -/* LPUART Modem IrDA Register */ - -#define LPUART_MODIR_TXCTSE (1 << 0) /* Bit nn: Transmitter clear-to-send enable */ -#define LPUART_MODIR_TXRTSE (1 << 1) /* Bit nn: Transmitter request-to-send enable */ -#define LPUART_MODIR_TXRTSPOL (1 << 2) /* Bit nn: Transmitter request-to-send polarity */ -#define LPUART_MODIR_RXRTSE (1 << 3) /* Bit nn: Receiver request-to-send enable */ -#define LPUART_MODIR_TXCTSC (1 << 4) /* Bit nn: Transmit CTS Configuration */ -# define LPUART_MODIR_TXCTSC_START (0 << 4) /* CTS sampled at start of character */ -# define LPUART_MODIR_TXCTSC_IDLE (1 << 4) /* CTS sampled when transmitter idle */ -#define LPUART_MODIR_TXCTSSRC (1 << 5) /* Bit nn: Transmit CTS Source */ -# define LPUART_MODIR_TXCTSSRC_CTSB (0 << 5) /* Bit nn: CTS input is CTS_B pin */ -# define LPUART_MODIR_TXCTSSRC_RXMAT (1 << 5) /* Bit nn: Transmit CTS Source */ - /* Bits 6-7: Reserved */ -#define LPUART_MODIR_RTSWATER (8) /* Bits 8-9: Receive RTS Configuration */ - /* Bits 10-15: Reserved */ -#define LPUART_MODIR_TNP_SHIFT (16) /* Bits 16-17: Transmitter narrow pulse */ -#define LPUART_MODIR_TNP_MASK (3 << LPUART_MODIR_TNP_SHIFT) -# define LPUART_MODIR_TNP(n) ((uint32_t)((n) - 1) << LPUART_MODIR_TNP_SHIFT) /* n/OSR */ -#define LPUART_MODIR_IREN (1 << 18) /* Bit nn: Infrared enable */ - /* Bits 19-31: Reserved */ - -/* LPUART FIFO Register */ - -#define LPUART_FIFO_RXFIFOSIZE_SHIFT (0) /* Bits 0-2: Receive FIFO. Buffer Depth */ -#define LPUART_FIFO_RXFIFOSIZE_MASK (7 << LPUART_FIFO_RXFIFOSIZE_SHIFT) -# define LPUART_FIFO_RXFIFOSIZE_1 (0 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 1 datawords */ -# define LPUART_FIFO_RXFIFOSIZE_4 (1 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 4 datawords */ -# define LPUART_FIFO_RXFIFOSIZE_8 (2 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 8 datawords */ -# define LPUART_FIFO_RXFIFOSIZE_16 (3 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 16 datawords */ -# define LPUART_FIFO_RXFIFOSIZE_32 (4 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 32 datawords */ -# define LPUART_FIFO_RXFIFOSIZE_64 (5 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 64 datawords */ -# define LPUART_FIFO_RXFIFOSIZE_128 (6 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 128 datawords */ -# define LPUART_FIFO_RXFIFOSIZE_256 (7 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 256 datawords */ -#define LPUART_FIFO_TXFIFOSIZE_SHIFT (4) /* Bits 4-6: Transmit FIFO. Buffer Depth */ -#define LPUART_FIFO_TXFIFOSIZE_MASK (7 << LPUART_FIFO_TXFIFOSIZE_SHIFT) -# define LPUART_FIFO_TXFIFOSIZE_1 (0 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 1 datawords */ -# define LPUART_FIFO_TXFIFOSIZE_4 (1 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 4 datawords */ -# define LPUART_FIFO_TXFIFOSIZE_8 (2 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 8 datawords */ -# define LPUART_FIFO_TXFIFOSIZE_16 (3 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 16 datawords */ -# define LPUART_FIFO_TXFIFOSIZE_32 (4 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 32 datawords */ -# define LPUART_FIFO_TXFIFOSIZE_64 (5 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 64 datawords */ -# define LPUART_FIFO_TXFIFOSIZE_128 (6 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 128 datawords */ -# define LPUART_FIFO_TXFIFOSIZE_256 (7 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 256 datawords */ - -#define LPUART_FIFO_TXFE (1 << 7) /* Bit 7: Transmit FIFO Enable */ -#define LPUART_FIFO_RXUFE (1 << 8) /* Bit 8: Receive FIFO Underflow Interrupt Enable */ -#define LPUART_FIFO_TXOFE (1 << 9) /* Bit 9: Transmit FIFO Overflow Interrupt Enable */ -#define LPUART_FIFO_RXIDEN_SHIFT (10) /* Bits 10-12: Receiver Idle Empty Enable */ -#define LPUART_FIFO_RXIDEN_MASK (7 << LPUART_FIFO_RXIDEN_SHIFT) -# define LPUART_FIFO_RXIDEN_DISABLE (0 << LPUART_FIFO_RXIDEN_SHIFT) /* Disable RDRF assertion when receiver is idle */ -# define LPUART_FIFO_RXIDEN_1 (1 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 1 word */ -# define LPUART_FIFO_RXIDEN_2 (2 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 2 words */ -# define LPUART_FIFO_RXIDEN_4 (3 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 4 words */ -# define LPUART_FIFO_RXIDEN_8 (4 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 8 words */ -# define LPUART_FIFO_RXIDEN_16 (5 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 16 words */ -# define LPUART_FIFO_RXIDEN_32 (6 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 32 words */ -# define LPUART_FIFO_RXIDEN_64 (7 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 64 words */ - -#define LPUART_FIFO_RXFLUSH (1 << 14) /* Bit 14: Receive FIFO/Buffer Flush */ -#define LPUART_FIFO_TXFLUSH (1 << 15) /* Bit 15: Transmit FIFO/Buffer Flush */ -#define LPUART_FIFO_RXUF (1 << 16) /* Bit 16: Receiver Buffer Underflow Flag */ -#define LPUART_FIFO_TXOF (1 << 17) /* Bit 17: Transmitter Buffer Overflow Flag */ - /* Bits 18-21: Reserved */ -#define LPUART_FIFO_RXEMPT (1 << 22) /* Bit 22: Receive Buffer/FIFO Empty */ -#define LPUART_FIFO_TXEMPT (1 << 23) /* Bit 23: Transmit Buffer/FIFO Empty */ - /* Bits 24-31: Reserved */ - -/* LPUART Watermark Register */ - -#define LPUART_WATER_TXWATER_SHIFT (0) /* Bits 0-1: Transmit Watermark */ -#define LPUART_WATER_TXWATER_MASK (3 << LPUART_WATER_TXWATER_SHIFT) -# define LPUART_WATER_TXWATER(n) ((uint32_t)(n) << LPUART_WATER_TXWATER_SHIFT) - /* Bits 2-7: Reserved */ -#define LPUART_WATER_TXCOUNT_SHIFT (8) /* Bits 8-10:Transmit Counter */ -#define LPUART_WATER_TXCOUNT_MASK (7 << LPUART_WATER_TXCOUNT_SHIFT) -# define LPUART_WATER_TXCOUNT(n) ((uint32_t)(n) << LPUART_WATER_TXCOUNT_SHIFT) - /* Bits 11-15: Reserved */ -#define LPUART_WATER_RXWATER_SHIFT (16) /* Bits 16-17: Receive Watermark */ -#define LPUART_WATER_RXWATER_MASK (3 << LPUART_WATER_RXWATER_SHIFT) -# define LPUART_WATER_RXWATER(n) ((uint32_t)(n) << LPUART_WATER_RXWATER_SHIFT) - /* Bits 18-23: Reserved */ -#define LPUART_WATER_RXCOUNT_SHIFT (24) /* Bits 24-26: Receive Counter */ -#define LPUART_WATER_RXCOUNT_MASK (7 << LPUART_WATER_RXCOUNT_SHIFT) -# define LPUART_WATER_RXCOUNT(n) ((uint32_t)(n) << LPUART_WATER_RXCOUNT_SHIFT) - /* Bits 27-31: Reserved */ - -#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_LPUART_H */ diff --git a/arch/arm/src/imxrt/chip/imxrt_memorymap.h b/arch/arm/src/imxrt/chip/imxrt_memorymap.h deleted file mode 100644 index 217b5a20f69..00000000000 --- a/arch/arm/src/imxrt/chip/imxrt_memorymap.h +++ /dev/null @@ -1,55 +0,0 @@ -/************************************************************************************ - * arch/arm/src/imxrt/chip/imxrt_memorymap.h - * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_MEMORYMAP_H -#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_MEMORYMAP_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#if defined(CONFIG_ARCH_FAMILY_IMXRT102x) -# include "chip/rt102x/imxrt102x_memorymap.h" -#elif defined(CONFIG_ARCH_FAMILY_IMXRT105x) -# include "chip/rt105x/imxrt105x_memorymap.h" -#elif defined(CONFIG_ARCH_FAMILY_IMXRT106x) -# include "chip/rt106x/imxrt106x_memorymap.h" -#else -# error Unrecognized i.MX RT architecture -#endif - -#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_MEMORYMAP_H */ diff --git a/arch/arm/src/imxrt/chip/imxrt_ocotp.h b/arch/arm/src/imxrt/chip/imxrt_ocotp.h deleted file mode 100644 index d4d5d3f0cb4..00000000000 --- a/arch/arm/src/imxrt/chip/imxrt_ocotp.h +++ /dev/null @@ -1,429 +0,0 @@ -/************************************************************************************************************************************ - * arch/arm/src/imxrt/chip/imxrt_ocotp.h - * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * David Sidrane - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_OCOTP_H -#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_OCOTP_H - -/* The OCOTP IP block provides a set of register to access the On Chip OPT. - * It also provides a shadow image of the 64 OTP entries that are read only - * memory addressable (OCOTP Shadow Offsets). To read or write the actual - * OTP, OCOTP Indexes are used. - */ - -/************************************************************************************************************************************ - * Included Files - ************************************************************************************************************************************/ - -#include -#include "chip/imxrt_memorymap.h" - -/************************************************************************************************************************************ - * Pre-processor Definitions - ************************************************************************************************************************************/ - -/* Register Offsets *****************************************************************/ - -#define IMXRT_OCOTP_CTRL_OFFSET 0x0000 /* OTP Controller Control Register */ -#define IMXRT_OCOTP_CTRL_SET_OFFSET 0x0004 /* OTP Controller Control Register */ -#define IMXRT_OCOTP_CTRL_CLR_OFFSET 0x0008 /* OTP Controller Control Register */ -#define IMXRT_OCOTP_CTRL_TOG_OFFSET 0x000c /* OTP Controller Control Register */ -#define IMXRT_OCOTP_TIMING_OFFSET 0x0010 /* OTP Controller Timing Register */ -#define IMXRT_OCOTP_DATA_OFFSET 0x0020 /* OTP Controller Write Data Register */ -#define IMXRT_OCOTP_READ_CTRL_OFFSET 0x0030 /* OTP Controller Write Data Register */ -#define IMXRT_OCOTP_READ_FUSE_DATA_OFFSET 0x0040 /* OTP Controller Read Data Register */ -#define IMXRT_OCOTP_SW_STICKY_OFFSET 0x0050 /* Sticky bit Register */ -#define IMXRT_OCOTP_SCS_OFFSET 0x0060 /* Software Controllable Signals Register */ -#define IMXRT_OCOTP_SCS_SET_OFFSET 0x0064 /* Software Controllable Signals Register */ -#define IMXRT_OCOTP_SCS_CLR_OFFSET 0x0068 /* Software Controllable Signals Register */ -#define IMXRT_OCOTP_SCS_TOG_OFFSET 0x006c /* Software Controllable Signals Register */ -#define IMXRT_OCOTP_CRC_ADDR_OFFSET 0x0070 /* OTP Controller CRC test address */ -#define IMXRT_OCOTP_CRC_VALUE_OFFSET 0x0080 /* OTP Controller CRC Value Register */ -#define IMXRT_OCOTP_VERSION_OFFSET 0x0090 /* OTP Controller Version Register */ -#define IMXRT_OCOTP_TIMING2_OFFSET 0x0100 /* OTP Controller Timing Register */ - -/* OCOTP Shadow Offsets *************************************************************/ - -#define IMXRT_OCOTP_LOCK_OFFSET 0x0400 /* Value of OTP Bank0 Word0 (Lock controls) */ -#define IMXRT_OCOTP_CFG0_OFFSET 0x0410 /* Value of OTP Bank0 Word1 (Configuration and Manufacturing */ -#define IMXRT_OCOTP_CFG1_OFFSET 0x0420 /* Value of OTP Bank0 Word2 (Configuration and Manufacturing */ -#define IMXRT_OCOTP_CFG2_OFFSET 0x0430 /* Value of OTP Bank0 Word3 (Configuration and Manufacturing */ -#define IMXRT_OCOTP_CFG3_OFFSET 0x0440 /* Value of OTP Bank0 Word4 (Configuration and Manufacturing */ -#define IMXRT_OCOTP_CFG4_OFFSET 0x0450 /* Value of OTP Bank0 Word5 (Configuration and Manufacturing */ -#define IMXRT_OCOTP_CFG5_OFFSET 0x0460 /* Value of OTP Bank0 Word6 (Configuration and Manufacturing */ -#define IMXRT_OCOTP_CFG6_OFFSET 0x0470 /* Value of OTP Bank0 Word7 (Configuration and Manufacturing */ -#define IMXRT_OCOTP_MEM0_OFFSET 0x0480 /* Value of OTP Bank1 Word0 (Memory Related Info.) */ -#define IMXRT_OCOTP_MEM1_OFFSET 0x0490 /* Value of OTP Bank1 Word1 (Memory Related Info.) */ -#define IMXRT_OCOTP_MEM2_OFFSET 0x04a0 /* Value of OTP Bank1 Word2 (Memory Related Info.) */ -#define IMXRT_OCOTP_MEM3_OFFSET 0x04b0 /* Value of OTP Bank1 Word3 (Memory Related Info.) */ -#define IMXRT_OCOTP_MEM4_OFFSET 0x04c0 /* Value of OTP Bank1 Word4 (Memory Related Info.) */ -#define IMXRT_OCOTP_ANA0_OFFSET 0x04d0 /* Value of OTP Bank1 Word5 (Analog Info.) */ -#define IMXRT_OCOTP_ANA1_OFFSET 0x04e0 /* Value of OTP Bank1 Word6 (Analog Info.) */ -#define IMXRT_OCOTP_ANA2_OFFSET 0x04f0 /* Value of OTP Bank1 Word7 (Analog Info.) */ -#define IMXRT_OCOTP_OTPMK0_OFFSET 0x0500 /* Value of OTP Bank2 Word0 (OTPMK Key) */ -#define IMXRT_OCOTP_OTPMK1_OFFSET 0x0510 /* Value of OTP Bank2 Word1 (OTPMK Key) */ -#define IMXRT_OCOTP_OTPMK2_OFFSET 0x0520 /* Value of OTP Bank2 Word2 (OTPMK Key) */ -#define IMXRT_OCOTP_OTPMK3_OFFSET 0x0530 /* Value of OTP Bank2 Word3 (OTPMK Key) */ -#define IMXRT_OCOTP_OTPMK4_OFFSET 0x0540 /* Value of OTP Bank2 Word4 (OTPMK Key) */ -#define IMXRT_OCOTP_OTPMK5_OFFSET 0x0550 /* Value of OTP Bank2 Word5 (OTPMK Key) */ -#define IMXRT_OCOTP_OTPMK6_OFFSET 0x0560 /* Value of OTP Bank2 Word6 (OTPMK Key) */ -#define IMXRT_OCOTP_OTPMK7_OFFSET 0x0570 /* Value of OTP Bank2 Word7 (OTPMK Key) */ -#define IMXRT_OCOTP_SRK0_OFFSET 0x0580 /* Shadow Register for OTP Bank3 Word0 (SRK Hash) */ -#define IMXRT_OCOTP_SRK1_OFFSET 0x0590 /* Shadow Register for OTP Bank3 Word1 (SRK Hash) */ -#define IMXRT_OCOTP_SRK2_OFFSET 0x05a0 /* Shadow Register for OTP Bank3 Word2 (SRK Hash) */ -#define IMXRT_OCOTP_SRK3_OFFSET 0x05b0 /* Shadow Register for OTP Bank3 Word3 (SRK Hash) */ -#define IMXRT_OCOTP_SRK4_OFFSET 0x05c0 /* Shadow Register for OTP Bank3 Word4 (SRK Hash) */ -#define IMXRT_OCOTP_SRK5_OFFSET 0x05d0 /* Shadow Register for OTP Bank3 Word5 (SRK Hash) */ -#define IMXRT_OCOTP_SRK6_OFFSET 0x05e0 /* Shadow Register for OTP Bank3 Word6 (SRK Hash) */ -#define IMXRT_OCOTP_SRK7_OFFSET 0x05f0 /* Shadow Register for OTP Bank3 Word7 (SRK Hash) */ -#define IMXRT_OCOTP_SJC_RESP0_OFFSET 0x0600 /* Value of OTP Bank4 Word0 (Secure JTAG Response Field) */ -#define IMXRT_OCOTP_SJC_RESP1_OFFSET 0x0610 /* Value of OTP Bank4 Word1 (Secure JTAG Response Field) */ -#define IMXRT_OCOTP_MAC0_OFFSET 0x0620 /* Value of OTP Bank4 Word2 (MAC Address) */ -#define IMXRT_OCOTP_MAC1_OFFSET 0x0630 /* Value of OTP Bank4 Word3 (MAC Address) */ -#define IMXRT_OCOTP_MAC2_OFFSET 0x0640 /* Value of OTP Bank4 Word4 (MAC Address) */ -#define IMXRT_OCOTP_OTPMK_CRC32_OFFSET 0x0650 /* Value of OTP Bank4 Word5 (CRC Key) */ -#define IMXRT_OCOTP_SW_GP1_OFFSET 0x0680 /* Value of OTP Bank5 Word0 (SW GP1) */ -#define IMXRT_OCOTP_SW_GP20_OFFSET 0x0690 /* Value of OTP Bank5 Word1 (SW GP2) */ -#define IMXRT_OCOTP_SW_GP21_OFFSET 0x06a0 /* Value of OTP Bank5 Word2 (SW GP2) */ -#define IMXRT_OCOTP_SW_GP22_OFFSET 0x06b0 /* Value of OTP Bank5 Word3 (SW GP2) */ -#define IMXRT_OCOTP_SW_GP23_OFFSET 0x06c0 /* Value of OTP Bank5 Word4 (SW GP2) */ -#define IMXRT_OCOTP_MISC_CONF0_OFFSET 0x06d0 /* Value of OTP Bank5 Word5 (Misc Conf) */ -#define IMXRT_OCOTP_MISC_CONF1_OFFSET 0x06e0 /* Value of OTP Bank5 Word6 (Misc Conf) */ -#define IMXRT_OCOTP_SRK_REVOKE_OFFSET 0x06f0 /* Value of OTP Bank5 Word7 (SRK Revoke) */ - -#define IMXRT_OCOTP_ROM_PATCH0_OFFSET 0x0800 /* Value of OTP Bank6 Word0 (ROM Patch) */ -#define IMXRT_OCOTP_ROM_PATCH1_OFFSET 0x0810 /* Value of OTP Bank6 Word1 (ROM Patch) */ -#define IMXRT_OCOTP_ROM_PATCH2_OFFSET 0x0820 /* Value of OTP Bank6 Word2 (ROM Patch) */ -#define IMXRT_OCOTP_ROM_PATCH3_OFFSET 0x0830 /* Value of OTP Bank6 Word3 (ROM Patch) */ -#define IMXRT_OCOTP_ROM_PATCH4_OFFSET 0x0840 /* Value of OTP Bank6 Word4 (ROM Patch) */ -#define IMXRT_OCOTP_ROM_PATCH5_OFFSET 0x0850 /* Value of OTP Bank6 Word5 (ROM Patch) */ -#define IMXRT_OCOTP_ROM_PATCH6_OFFSET 0x0860 /* Value of OTP Bank6 Word6 (ROM Patch) */ -#define IMXRT_OCOTP_ROM_PATCH7_OFFSET 0x0870 /* Value of OTP Bank6 Word7 (ROM Patch) */ -#define IMXRT_OCOTP_GP30_OFFSET 0x0880 /* Value of OTP Bank7 Word0 (GP3) */ -#define IMXRT_OCOTP_GP31_OFFSET 0x0890 /* Value of OTP Bank7 Word1 (GP3) */ -#define IMXRT_OCOTP_GP32_OFFSET 0x08a0 /* Value of OTP Bank7 Word2 (GP3) */ -#define IMXRT_OCOTP_GP33_OFFSET 0x08b0 /* Value of OTP Bank7 Word3 (GP3) */ -#define IMXRT_OCOTP_GP40_OFFSET 0x08c0 /* Value of OTP Bank7 Word4 (GP4) */ -#define IMXRT_OCOTP_GP41_OFFSET 0x08d0 /* Value of OTP Bank7 Word5 (GP4) */ -#define IMXRT_OCOTP_GP42_OFFSET 0x08e0 /* Value of OTP Bank7 Word6 (GP4) */ -#define IMXRT_OCOTP_GP43_OFFSET 0x08f0 /* Value of OTP Bank7 Word7 (GP4) */ - -/* OCOTP Indexes *****************************************************************/ - -#define IMXRT_OCOTP_O2I(offset) (((offset) - IMXRT_OCOTP_LOCK_OFFSET) >> 4) - -#define IMXRT_OCOTP_LOCK_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_LOCK_OFFSET) /* Value of OTP Bank0 Word0 (Lock controls) */ -#define IMXRT_OCOTP_CFG0_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_CFG0_OFFSET) /* Value of OTP Bank0 Word1 (Configuration and Manufacturing */ -#define IMXRT_OCOTP_CFG1_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_CFG1_OFFSET) /* Value of OTP Bank0 Word2 (Configuration and Manufacturing */ -#define IMXRT_OCOTP_CFG2_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_CFG2_OFFSET) /* Value of OTP Bank0 Word3 (Configuration and Manufacturing */ -#define IMXRT_OCOTP_CFG3_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_CFG3_OFFSET) /* Value of OTP Bank0 Word4 (Configuration and Manufacturing */ -#define IMXRT_OCOTP_CFG4_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_CFG4_OFFSET) /* Value of OTP Bank0 Word5 (Configuration and Manufacturing */ -#define IMXRT_OCOTP_CFG5_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_CFG5_OFFSET) /* Value of OTP Bank0 Word6 (Configuration and Manufacturing */ -#define IMXRT_OCOTP_CFG6_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_CFG6_OFFSET) /* Value of OTP Bank0 Word7 (Configuration and Manufacturing */ -#define IMXRT_OCOTP_MEM0_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_MEM0_OFFSET) /* Value of OTP Bank1 Word0 (Memory Related Info.) */ -#define IMXRT_OCOTP_MEM1_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_MEM1_OFFSET) /* Value of OTP Bank1 Word1 (Memory Related Info.) */ -#define IMXRT_OCOTP_MEM2_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_MEM2_OFFSET) /* Value of OTP Bank1 Word2 (Memory Related Info.) */ -#define IMXRT_OCOTP_MEM3_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_MEM3_OFFSET) /* Value of OTP Bank1 Word3 (Memory Related Info.) */ -#define IMXRT_OCOTP_MEM4_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_MEM4_OFFSET) /* Value of OTP Bank1 Word4 (Memory Related Info.) */ -#define IMXRT_OCOTP_ANA0_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_ANA0_OFFSET) /* Value of OTP Bank1 Word5 (Analog Info.) */ -#define IMXRT_OCOTP_ANA1_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_ANA1_OFFSET) /* Value of OTP Bank1 Word6 (Analog Info.) */ -#define IMXRT_OCOTP_ANA2_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_ANA2_OFFSET) /* Value of OTP Bank1 Word7 (Analog Info.) */ -#define IMXRT_OCOTP_OTPMK0_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_OTPMK0_OFFSET) /* Value of OTP Bank2 Word0 (OTPMK Key) */ -#define IMXRT_OCOTP_OTPMK1_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_OTPMK1_OFFSET) /* Value of OTP Bank2 Word1 (OTPMK Key) */ -#define IMXRT_OCOTP_OTPMK2_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_OTPMK2_OFFSET) /* Value of OTP Bank2 Word2 (OTPMK Key) */ -#define IMXRT_OCOTP_OTPMK3_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_OTPMK3_OFFSET) /* Value of OTP Bank2 Word3 (OTPMK Key) */ -#define IMXRT_OCOTP_OTPMK4_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_OTPMK4_OFFSET) /* Value of OTP Bank2 Word4 (OTPMK Key) */ -#define IMXRT_OCOTP_OTPMK5_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_OTPMK5_OFFSET) /* Value of OTP Bank2 Word5 (OTPMK Key) */ -#define IMXRT_OCOTP_OTPMK6_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_OTPMK6_OFFSET) /* Value of OTP Bank2 Word6 (OTPMK Key) */ -#define IMXRT_OCOTP_OTPMK7_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_OTPMK7_OFFSET) /* Value of OTP Bank2 Word7 (OTPMK Key) */ -#define IMXRT_OCOTP_SRK0_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_SRK0_OFFSET) /* Shadow Register for OTP Bank3 Word0 (SRK Hash) */ -#define IMXRT_OCOTP_SRK1_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_SRK1_OFFSET) /* Shadow Register for OTP Bank3 Word1 (SRK Hash) */ -#define IMXRT_OCOTP_SRK2_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_SRK2_OFFSET) /* Shadow Register for OTP Bank3 Word2 (SRK Hash) */ -#define IMXRT_OCOTP_SRK3_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_SRK3_OFFSET) /* Shadow Register for OTP Bank3 Word3 (SRK Hash) */ -#define IMXRT_OCOTP_SRK4_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_SRK4_OFFSET) /* Shadow Register for OTP Bank3 Word4 (SRK Hash) */ -#define IMXRT_OCOTP_SRK5_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_SRK5_OFFSET) /* Shadow Register for OTP Bank3 Word5 (SRK Hash) */ -#define IMXRT_OCOTP_SRK6_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_SRK6_OFFSET) /* Shadow Register for OTP Bank3 Word6 (SRK Hash) */ -#define IMXRT_OCOTP_SRK7_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_SRK7_OFFSET) /* Shadow Register for OTP Bank3 Word7 (SRK Hash) */ -#define IMXRT_OCOTP_SJC_RESP0_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_SJC_RESP0_OFFSET) /* Value of OTP Bank4 Word0 (Secure JTAG Response Field) */ -#define IMXRT_OCOTP_SJC_RESP1_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_SJC_RESP1_OFFSET) /* Value of OTP Bank4 Word1 (Secure JTAG Response Field) */ -#define IMXRT_OCOTP_MAC0_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_MAC0_OFFSET) /* Value of OTP Bank4 Word2 (MAC Address) */ -#define IMXRT_OCOTP_MAC1_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_MAC1_OFFSET) /* Value of OTP Bank4 Word3 (MAC Address) */ -#define IMXRT_OCOTP_MAC2_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_MAC2_OFFSET) /* Value of OTP Bank4 Word4 (MAC Address) */ -#define IMXRT_OCOTP_OTPMK_CRC32_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_OTPMK_CRC32_OFFSET) /* Value of OTP Bank4 Word5 (CRC Key) */ -#define IMXRT_OCOTP_SW_GP1_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_SW_GP1_OFFSET) /* Value of OTP Bank5 Word0 (SW GP1) */ -#define IMXRT_OCOTP_SW_GP20_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_SW_GP20_OFFSET) /* Value of OTP Bank5 Word1 (SW GP2) */ -#define IMXRT_OCOTP_SW_GP21_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_SW_GP21_OFFSET) /* Value of OTP Bank5 Word2 (SW GP2) */ -#define IMXRT_OCOTP_SW_GP22_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_SW_GP22_OFFSET) /* Value of OTP Bank5 Word3 (SW GP2) */ -#define IMXRT_OCOTP_SW_GP23_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_SW_GP23_OFFSET) /* Value of OTP Bank5 Word4 (SW GP2) */ -#define IMXRT_OCOTP_MISC_CONF0_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_MISC_CONF0_OFFSET) /* Value of OTP Bank5 Word5 (Misc Conf) */ -#define IMXRT_OCOTP_MISC_CONF1_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_MISC_CONF1_OFFSET) /* Value of OTP Bank5 Word6 (Misc Conf) */ -#define IMXRT_OCOTP_SRK_REVOKE_INDEX IMXRT_OCOTP_O2I(IMXRT_OCOTP_SRK_REVOKE_OFFSET) /* Value of OTP Bank5 Word7 (SRK Revoke) */ - -#define IMXRT_OCOTP_O2IP(offset) (((offset) - (IMXRT_OCOTP_LOCK_OFFSET + 0x100)) >> 4) - -#define IMXRT_OCOTP_ROM_PATCH0_INDEX IMXRT_OCOTP_O2IP(IMXRT_OCOTP_ROM_PATCH0_OFFSET) /* Value of OTP Bank6 Word0 (ROM Patch) */ -#define IMXRT_OCOTP_ROM_PATCH1_INDEX IMXRT_OCOTP_O2IP(IMXRT_OCOTP_ROM_PATCH1_OFFSET) /* Value of OTP Bank6 Word1 (ROM Patch) */ -#define IMXRT_OCOTP_ROM_PATCH2_INDEX IMXRT_OCOTP_O2IP(IMXRT_OCOTP_ROM_PATCH2_OFFSET) /* Value of OTP Bank6 Word2 (ROM Patch) */ -#define IMXRT_OCOTP_ROM_PATCH3_INDEX IMXRT_OCOTP_O2IP(IMXRT_OCOTP_ROM_PATCH3_OFFSET) /* Value of OTP Bank6 Word3 (ROM Patch) */ -#define IMXRT_OCOTP_ROM_PATCH4_INDEX IMXRT_OCOTP_O2IP(IMXRT_OCOTP_ROM_PATCH4_OFFSET) /* Value of OTP Bank6 Word4 (ROM Patch) */ -#define IMXRT_OCOTP_ROM_PATCH5_INDEX IMXRT_OCOTP_O2IP(IMXRT_OCOTP_ROM_PATCH5_OFFSET) /* Value of OTP Bank6 Word5 (ROM Patch) */ -#define IMXRT_OCOTP_ROM_PATCH6_INDEX IMXRT_OCOTP_O2IP(IMXRT_OCOTP_ROM_PATCH6_OFFSET) /* Value of OTP Bank6 Word6 (ROM Patch) */ -#define IMXRT_OCOTP_ROM_PATCH7_INDEX IMXRT_OCOTP_O2IP(IMXRT_OCOTP_ROM_PATCH7_OFFSET) /* Value of OTP Bank6 Word7 (ROM Patch) */ -#define IMXRT_OCOTP_GP30_INDEX IMXRT_OCOTP_O2IP(IMXRT_OCOTP_GP30_OFFSET) /* Value of OTP Bank7 Word0 (GP3) */ -#define IMXRT_OCOTP_GP31_INDEX IMXRT_OCOTP_O2IP(IMXRT_OCOTP_GP31_OFFSET) /* Value of OTP Bank7 Word1 (GP3) */ -#define IMXRT_OCOTP_GP32_INDEX IMXRT_OCOTP_O2IP(IMXRT_OCOTP_GP32_OFFSET) /* Value of OTP Bank7 Word2 (GP3) */ -#define IMXRT_OCOTP_GP33_INDEX IMXRT_OCOTP_O2IP(IMXRT_OCOTP_GP33_OFFSET) /* Value of OTP Bank7 Word3 (GP3) */ -#define IMXRT_OCOTP_GP40_INDEX IMXRT_OCOTP_O2IP(IMXRT_OCOTP_GP40_OFFSET) /* Value of OTP Bank7 Word4 (GP4) */ -#define IMXRT_OCOTP_GP41_INDEX IMXRT_OCOTP_O2IP(IMXRT_OCOTP_GP41_OFFSET) /* Value of OTP Bank7 Word5 (GP4) */ -#define IMXRT_OCOTP_GP42_INDEX IMXRT_OCOTP_O2IP(IMXRT_OCOTP_GP42_OFFSET) /* Value of OTP Bank7 Word6 (GP4) */ -#define IMXRT_OCOTP_GP43_INDEX IMXRT_OCOTP_O2IP(IMXRT_OCOTP_GP43_OFFSET) /* Value of OTP Bank7 Word7 (GP4) */ - -/* Register addresses ***********************************************************************************************************************/ - -#define IMXRT_OCOTP_CTRL (IMXRT_OCOTP_BASE + IMXRT_OCOTP_CTRL_OFFSET) /* OTP Controller Control Register */ -#define IMXRT_OCOTP_CTRL_SET (IMXRT_OCOTP_BASE + IMXRT_OCOTP_CTRL_SET_OFFSET) /* OTP Controller Control Register */ -#define IMXRT_OCOTP_CTRL_CLR (IMXRT_OCOTP_BASE + IMXRT_OCOTP_CTRL_CLR_OFFSET) /* OTP Controller Control Register */ -#define IMXRT_OCOTP_CTRL_TOG (IMXRT_OCOTP_BASE + IMXRT_OCOTP_CTRL_TOG_OFFSET) /* OTP Controller Control Register */ -#define IMXRT_OCOTP_TIMING (IMXRT_OCOTP_BASE + IMXRT_OCOTP_TIMING_OFFSET) /* OTP Controller Timing Register */ -#define IMXRT_OCOTP_DATA (IMXRT_OCOTP_BASE + IMXRT_OCOTP_DATA_OFFSET) /* OTP Controller Write Data Register */ -#define IMXRT_OCOTP_READ_CTRL (IMXRT_OCOTP_BASE + IMXRT_OCOTP_READ_CTRL_OFFSET) /* OTP Controller Write Data Register */ -#define IMXRT_OCOTP_READ_FUSE_DATA (IMXRT_OCOTP_BASE + IMXRT_OCOTP_READ_FUSE_DATA_OFFSET) /* OTP Controller Read Data Register */ -#define IMXRT_OCOTP_SW_STICKY (IMXRT_OCOTP_BASE + IMXRT_OCOTP_SW_STICKY_OFFSET) /* Sticky bit Register */ -#define IMXRT_OCOTP_SCS (IMXRT_OCOTP_BASE + IMXRT_OCOTP_SCS_OFFSET) /* Software Controllable Signals Register */ -#define IMXRT_OCOTP_SCS_SET (IMXRT_OCOTP_BASE + IMXRT_OCOTP_SCS_SET_OFFSET) /* Software Controllable Signals Register */ -#define IMXRT_OCOTP_SCS_CLR (IMXRT_OCOTP_BASE + IMXRT_OCOTP_SCS_CLR_OFFSET) /* Software Controllable Signals Register */ -#define IMXRT_OCOTP_SCS_TOG (IMXRT_OCOTP_BASE + IMXRT_OCOTP_SCS_TOG_OFFSET) /* Software Controllable Signals Register */ -#define IMXRT_OCOTP_CRC_ADDR (IMXRT_OCOTP_BASE + IMXRT_OCOTP_CRC_ADDR_OFFSET) /* OTP Controller CRC test address */ -#define IMXRT_OCOTP_CRC_VALUE (IMXRT_OCOTP_BASE + IMXRT_OCOTP_CRC_VALUE_OFFSET) /* OTP Controller CRC Value Register */ -#define IMXRT_OCOTP_VERSION (IMXRT_OCOTP_BASE + IMXRT_OCOTP_VERSION_OFFSET) /* OTP Controller Version Register */ -#define IMXRT_OCOTP_TIMING2 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_TIMING2_OFFSET) /* OTP Controller Timing Register */ -#define IMXRT_OCOTP_LOCK (IMXRT_OCOTP_BASE + IMXRT_OCOTP_LOCK_OFFSET) /* Value of OTP Bank0 Word0 (Lock controls) */ -#define IMXRT_OCOTP_CFG0 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_CFG0_OFFSET) /* Value of OTP Bank0 Word1 (Configuration and Manufacturing */ -#define IMXRT_OCOTP_CFG1 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_CFG1_OFFSET) /* Value of OTP Bank0 Word2 (Configuration and Manufacturing */ -#define IMXRT_OCOTP_CFG2 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_CFG2_OFFSET) /* Value of OTP Bank0 Word3 (Configuration and Manufacturing */ -#define IMXRT_OCOTP_CFG3 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_CFG3_OFFSET) /* Value of OTP Bank0 Word4 (Configuration and Manufacturing */ -#define IMXRT_OCOTP_CFG4 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_CFG4_OFFSET) /* Value of OTP Bank0 Word5 (Configuration and Manufacturing */ -#define IMXRT_OCOTP_CFG5 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_CFG5_OFFSET) /* Value of OTP Bank0 Word6 (Configuration and Manufacturing */ -#define IMXRT_OCOTP_CFG6 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_CFG6_OFFSET) /* Value of OTP Bank0 Word7 (Configuration and Manufacturing */ -#define IMXRT_OCOTP_MEM0 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_MEM0_OFFSET) /* Value of OTP Bank1 Word0 (Memory Related Info.) */ -#define IMXRT_OCOTP_MEM1 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_MEM1_OFFSET) /* Value of OTP Bank1 Word1 (Memory Related Info.) */ -#define IMXRT_OCOTP_MEM2 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_MEM2_OFFSET) /* Value of OTP Bank1 Word2 (Memory Related Info.) */ -#define IMXRT_OCOTP_MEM3 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_MEM3_OFFSET) /* Value of OTP Bank1 Word3 (Memory Related Info.) */ -#define IMXRT_OCOTP_MEM4 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_MEM4_OFFSET) /* Value of OTP Bank1 Word4 (Memory Related Info.) */ -#define IMXRT_OCOTP_ANA0 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_ANA0_OFFSET) /* Value of OTP Bank1 Word5 (Analog Info.) */ -#define IMXRT_OCOTP_ANA1 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_ANA1_OFFSET) /* Value of OTP Bank1 Word6 (Analog Info.) */ -#define IMXRT_OCOTP_ANA2 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_ANA2_OFFSET) /* Value of OTP Bank1 Word7 (Analog Info.) */ -#define IMXRT_OCOTP_OTPMK0 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_OTPMK0_OFFSET) /* Value of OTP Bank2 Word0 (OTPMK Key) */ -#define IMXRT_OCOTP_OTPMK1 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_OTPMK1_OFFSET) /* Value of OTP Bank2 Word1 (OTPMK Key) */ -#define IMXRT_OCOTP_OTPMK2 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_OTPMK2_OFFSET) /* Value of OTP Bank2 Word2 (OTPMK Key) */ -#define IMXRT_OCOTP_OTPMK3 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_OTPMK3_OFFSET) /* Value of OTP Bank2 Word3 (OTPMK Key) */ -#define IMXRT_OCOTP_OTPMK4 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_OTPMK4_OFFSET) /* Value of OTP Bank2 Word4 (OTPMK Key) */ -#define IMXRT_OCOTP_OTPMK5 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_OTPMK5_OFFSET) /* Value of OTP Bank2 Word5 (OTPMK Key) */ -#define IMXRT_OCOTP_OTPMK6 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_OTPMK6_OFFSET) /* Value of OTP Bank2 Word6 (OTPMK Key) */ -#define IMXRT_OCOTP_OTPMK7 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_OTPMK7_OFFSET) /* Value of OTP Bank2 Word7 (OTPMK Key) */ -#define IMXRT_OCOTP_SRK0 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_SRK0_OFFSET) /* Shadow Register for OTP Bank3 Word0 (SRK Hash) */ -#define IMXRT_OCOTP_SRK1 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_SRK1_OFFSET) /* Shadow Register for OTP Bank3 Word1 (SRK Hash) */ -#define IMXRT_OCOTP_SRK2 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_SRK2_OFFSET) /* Shadow Register for OTP Bank3 Word2 (SRK Hash) */ -#define IMXRT_OCOTP_SRK3 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_SRK3_OFFSET) /* Shadow Register for OTP Bank3 Word3 (SRK Hash) */ -#define IMXRT_OCOTP_SRK4 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_SRK4_OFFSET) /* Shadow Register for OTP Bank3 Word4 (SRK Hash) */ -#define IMXRT_OCOTP_SRK5 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_SRK5_OFFSET) /* Shadow Register for OTP Bank3 Word5 (SRK Hash) */ -#define IMXRT_OCOTP_SRK6 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_SRK6_OFFSET) /* Shadow Register for OTP Bank3 Word6 (SRK Hash) */ -#define IMXRT_OCOTP_SRK7 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_SRK7_OFFSET) /* Shadow Register for OTP Bank3 Word7 (SRK Hash) */ -#define IMXRT_OCOTP_SJC_RESP0 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_SJC_RESP0_OFFSET) /* Value of OTP Bank4 Word0 (Secure JTAG Response Field) */ -#define IMXRT_OCOTP_SJC_RESP1 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_SJC_RESP1_OFFSET) /* Value of OTP Bank4 Word1 (Secure JTAG Response Field) */ -#define IMXRT_OCOTP_MAC0 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_MAC0_OFFSET) /* Value of OTP Bank4 Word2 (MAC Address) */ -#define IMXRT_OCOTP_MAC1 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_MAC1_OFFSET) /* Value of OTP Bank4 Word3 (MAC Address) */ -#define IMXRT_OCOTP_MAC2 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_MAC2_OFFSET) /* Value of OTP Bank4 Word4 (MAC Address) */ -#define IMXRT_OCOTP_OTPMK_CRC32 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_OTPMK_CRC32_OFFSET) /* Value of OTP Bank4 Word5 (CRC Key) */ -#define IMXRT_OCOTP_SW_GP1 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_SW_GP1_OFFSET) /* Value of OTP Bank5 Word0 (SW GP1) */ -#define IMXRT_OCOTP_SW_GP20 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_SW_GP20_OFFSET) /* Value of OTP Bank5 Word1 (SW GP2) */ -#define IMXRT_OCOTP_SW_GP21 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_SW_GP21_OFFSET) /* Value of OTP Bank5 Word2 (SW GP2) */ -#define IMXRT_OCOTP_SW_GP22 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_SW_GP22_OFFSET) /* Value of OTP Bank5 Word3 (SW GP2) */ -#define IMXRT_OCOTP_SW_GP23 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_SW_GP23_OFFSET) /* Value of OTP Bank5 Word4 (SW GP2) */ -#define IMXRT_OCOTP_MISC_CONF0 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_MISC_CONF0_OFFSET) /* Value of OTP Bank5 Word5 (Misc Conf) */ -#define IMXRT_OCOTP_MISC_CONF1 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_MISC_CONF1_OFFSET) /* Value of OTP Bank5 Word6 (Misc Conf) */ -#define IMXRT_OCOTP_SRK_REVOKE (IMXRT_OCOTP_BASE + IMXRT_OCOTP_SRK_REVOKE_OFFSET) /* Value of OTP Bank5 Word7 (SRK Revoke) */ -#define IMXRT_OCOTP_ROM_PATCH0 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_ROM_PATCH0_OFFSET) /* Value of OTP Bank6 Word0 (ROM Patch) */ -#define IMXRT_OCOTP_ROM_PATCH1 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_ROM_PATCH1_OFFSET) /* Value of OTP Bank6 Word1 (ROM Patch) */ -#define IMXRT_OCOTP_ROM_PATCH2 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_ROM_PATCH2_OFFSET) /* Value of OTP Bank6 Word2 (ROM Patch) */ -#define IMXRT_OCOTP_ROM_PATCH3 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_ROM_PATCH3_OFFSET) /* Value of OTP Bank6 Word3 (ROM Patch) */ -#define IMXRT_OCOTP_ROM_PATCH4 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_ROM_PATCH4_OFFSET) /* Value of OTP Bank6 Word4 (ROM Patch) */ -#define IMXRT_OCOTP_ROM_PATCH5 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_ROM_PATCH5_OFFSET) /* Value of OTP Bank6 Word5 (ROM Patch) */ -#define IMXRT_OCOTP_ROM_PATCH6 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_ROM_PATCH6_OFFSET) /* Value of OTP Bank6 Word6 (ROM Patch) */ -#define IMXRT_OCOTP_ROM_PATCH7 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_ROM_PATCH7_OFFSET) /* Value of OTP Bank6 Word7 (ROM Patch) */ -#define IMXRT_OCOTP_GP30 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_GP30_OFFSET) /* Value of OTP Bank7 Word0 (GP3) */ -#define IMXRT_OCOTP_GP31 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_GP31_OFFSET) /* Value of OTP Bank7 Word1 (GP3) */ -#define IMXRT_OCOTP_GP32 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_GP32_OFFSET) /* Value of OTP Bank7 Word2 (GP3) */ -#define IMXRT_OCOTP_GP33 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_GP33_OFFSET) /* Value of OTP Bank7 Word3 (GP3) */ -#define IMXRT_OCOTP_GP40 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_GP40_OFFSET) /* Value of OTP Bank7 Word4 (GP4) */ -#define IMXRT_OCOTP_GP41 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_GP41_OFFSET) /* Value of OTP Bank7 Word5 (GP4) */ -#define IMXRT_OCOTP_GP42 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_GP42_OFFSET) /* Value of OTP Bank7 Word6 (GP4) */ -#define IMXRT_OCOTP_GP43 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_GP43_OFFSET) /* Value of OTP Bank7 Word7 (GP4) */ - -/* Register Bit Definitions *********************************************************************************************************/ - -/* OTP Controller Control Register */ - -#define OCOTP_CTRL_ADDR_SHIFT (0) /* Bits: 0-5 ADDR */ -#define OCOTP_CTRL_ADDR_MASK (0x3f << OCOTP_CTRL_ADDR_SHIFT) -# define OCOTP_CTRL_ADDR(n) ((uint32_t)(n) << OCOTP_CTRL_ADDR_SHIFT) - /* Bits: 6-7 Reserved */ -#define OCOTP_CTRL_BUSY (1 << 8) /* Bit: 8 BUSY */ -#define OCOTP_CTRL_ERROR (1 << 9) /* Bit: 9 ERROR */ -#define OCOTP_CTRL_RELOAD_SHADOWS (1 << 10) /* Bit: 10 OWS */ -#define OCOTP_CTRL_CRC_TEST (1 << 11) /* Bit: 11 CRC_TEST */ -#define OCOTP_CTRL_CRC_FAIL (1 << 12) /* Bit: 12 CRC_FAIL */ - /* Bits: 13-15 Reserved */ -#define OCOTP_CTRL_WR_UNLOCK_SHIFT (16) /* Bits: 16-31 WR_UNLOCK */ -#define OCOTP_CTRL_WR_UNLOCK_MASK (0xffff << OCOTP_CTRL_WR_UNLOCK_SHIFT) -# define OCOTP_CTRL_WR_UNLOCK (0x3e77 << OCOTP_CTRL_WR_UNLOCK_SHIFT) - -/* OTP Controller Timing Register */ - -#define OCOTP_TIMING_STROBE_PROG_SHIFT (0) /* Bits: 0-11 Specifies the strobe period in one time write OTP */ -#define OCOTP_TIMING_STROBE_PROG_MASK (0xfff << OCOTP_TIMING_STROBE_PROG_SHIFT) -# define OCOTP_TIMING_STROBE_PROG(n) ((uint32_t)(n) << OCOTP_TIMING_STROBE_PROG_SHIFT) -#define OCOTP_TIMING_RELAX_SHIFT (12) /* Bits: 12-15 Specifies the time to add to all default timing parameters other than the Tpgm and Trd. */ -#define OCOTP_TIMING_RELAX_MASK (15 << OCOTP_TIMING_RELAX_SHIFT) -# define OCOTP_TIMING_RELAX(n) ((uint32_t)(n) << OCOTP_TIMING_RELAX_SHIFT) -#define OCOTP_TIMING_STROBE_READ_SHIFT (16) /* Bits: 16-21 Specifies the strobe period in one time read OTP. */ -#define OCOTP_TIMING_STROBE_READ_MASK (0x3f << OCOTP_TIMING_STROBE_READ_SHIFT) -# define OCOTP_TIMING_STROBE_READ(n) ((uint32_t)(n) << OCOTP_TIMING_STROBE_READ_SHIFT) -#define OCOTP_TIMING_WAIT_SHIFT (22) /* Bits: 22-27 Specifies time interval between auto read and write access in one time program */ -#define OCOTP_TIMING_WAIT_MASK (0x3f << OCOTP_TIMING_WAIT_SHIFT) -# define OCOTP_TIMING_WAIT(n) ((uint32_t)(n) << OCOTP_TIMING_WAIT_SHIFT) - /* Bits: 28-31 Reserved */ - -/* OTP Controller Write Data Register */ - -#define OCOTP_READ_CTRL_READ_FUSE (1 << 0) /* Bit: 0 Used to initiate a read to OTP */ - /* Bits: 1-31 Reserved */ - -/* Sticky bit Register */ - -#define OCOTP_SW_STICKY_BLOCK_DTCP_KEY (1 << 0) /* Bit: 0 Shadow register read and OTP read lock for DTCP_KEY region. */ -#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK (1 << 1) /* Bit: 1 Shadow register write and OTP write lock for SRK_REVOKE region. */ -#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK (1 << 2) /* Bit: 2 Shadow register write and OTP write lock for FIELD_RETURN region. */ -#define OCOTP_SW_STICKY_BLOCK_ROM_PART (1 << 3) /* Bit: 3 Set by ARM during Boot after DTCP is initialized and before test mode entry, if ROM_PART_LOCK=1.*/ -#define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE (1 << 4) /* Bit: 4 Set by ARM during Boot after DTCP is initialized and before test mode entry. */ - /* Bits: 5-31 Reserved */ - -/* Software Controllable Signals Register */ - -#define OCOTP_SCS_HAB_JDE (1 << 0) /* Bit: 0 HAB JTAG Debug Enable. */ -#define OCOTP_SCS_SPARE_SHIFT (1) /* Bits: 1-30 Unallocated read/write bits for implementation specific software use. */ -#define OCOTP_SCS_SPARE_MASK (0x3fffffff << OCOTP_SCS_SPARE_SHIFT) -# define OCOTP_SCS_SPARE(n) ((uint32_t)(n) << OCOTP_SCS_SPARE_SHIFT) -#define OCOTP_SCS_LOCK (1 << 31) /* Bit: 31 LOCK */ - -/* OTP Controller CRC test address */ - -#define OCOTP_CRC_ADDR_DATA_START_ADDR_SHIFT (0) /* Bits: 0-7 Start address of fuse location for CRC calculation */ -#define OCOTP_CRC_ADDR_DATA_START_ADDR_MASK (0xff << OCOTP_CRC_ADDR_DATA_START_ADDR_SHIFT) -# define OCOTP_CRC_ADDR_DATA_START_ADDR(n) ((uint32_t)(n) << OCOTP_CRC_ADDR_DATA_START_ADDR_SHIFT) -#define OCOTP_CRC_ADDR_DATA_END_ADDR_SHIFT (8) /* Bits: 8-15 End address of fuse location for CRC calculation */ -#define OCOTP_CRC_ADDR_DATA_END_ADDR_MASK (0xff << OCOTP_CRC_ADDR_DATA_END_ADDR_SHIFT) -# define OCOTP_CRC_ADDR_DATA_END_ADDR(n) ((uint32_t)(n) << OCOTP_CRC_ADDR_DATA_END_ADDR_SHIFT) -#define OCOTP_CRC_ADDR_CRC_ADDR_SHIFT (16) /* Bits: 16-23 Address of 32-bit CRC result for comparing */ -#define OCOTP_CRC_ADDR_CRC_ADDR_MASK (0xff << OCOTP_CRC_ADDR_CRC_ADDR_SHIFT) -# define OCOTP_CRC_ADDR_CRC_ADDR(n) ((uint32_t)(n) << OCOTP_CRC_ADDR_CRC_ADDR_SHIFT) -#define OCOTP_CRC_ADDR_OTPMK_CRC (1 << 24) /* Bit: 24 Enable bit for OCOTP CRC32 calculation address. */ - /* Bits: 25-31 Reserved */ - -/* OTP Controller Version Register */ - -#define OCOTP_VERSION_STEP_SHIFT (0) /* Bits: 0-15 STEP field of the RTL version.*/ -#define OCOTP_VERSION_STEP_MASK (0xffff << OCOTP_VERSION_STEP_SHIFT) -# define OCOTP_VERSION_STEP(n) ((uint32_t)(n) << OCOTP_VERSION_STEP_SHIFT) -#define OCOTP_VERSION_MINOR_SHIFT (16) /* Bits: 16-23 MINOR field of the RTL version. */ -#define OCOTP_VERSION_MINOR_MASK (0xff << OCOTP_VERSION_MINOR_SHIFT) -# define OCOTP_VERSION_MINOR(n) ((uint32_t)(n) << OCOTP_VERSION_MINOR_SHIFT) -#define OCOTP_VERSION_MAJOR_SHIFT (24) /* Bits: 24-31 MAJOR field of the RTL version. */ -#define OCOTP_VERSION_MAJOR_MASK (0xff << OCOTP_VERSION_MAJOR_SHIFT) -# define OCOTP_VERSION_MAJOR(n) ((uint32_t)(n) << OCOTP_VERSION_MAJOR_SHIFT) - -/* OTP Controller Timing Register */ - -#define OCOTP_TIMING2_RELAX_PROG_SHIFT (0) /* Bits: 0-11 Specifies the strobe period in one time write OTP. */ -#define OCOTP_TIMING2_RELAX_PROG_MASK (0xfff << OCOTP_TIMING2_RELAX_PROG_SHIFT) -# define OCOTP_TIMING2_RELAX_PROG(n) ((uint32_t)(n) << OCOTP_TIMING2_RELAX_PROG_SHIFT) - /* Bits: 12-15 Reserved. These bits always read back zero. */ -#define OCOTP_TIMING2_RELAX_READ_SHIFT (16) /* Bits: 16-21 Specifies the strobe period in one time read OTP. */ -#define OCOTP_TIMING2_RELAX_READ_MASK (0x3f << OCOTP_TIMING2_RELAX_READ_SHIFT) -# define OCOTP_TIMING2_RELAX_READ(n) ((uint32_t)(n) << OCOTP_TIMING2_RELAX_READ_SHIFT) - /* Bits: 22-31 Reserved. These bits always read back zero. */ - -/* Value of OTP Bank0 Word0 (Lock controls) */ - -#define OCOTP_LOCK_TESTER_SHIFT (0) /* Bits: 0-1 Chapter 22 On-Chip OTP Controller (OCOTP_CTRL) */ -#define OCOTP_LOCK_TESTER_MASK (3 << OCOTP_LOCK_TESTER_SHIFT) -# define OCOTP_LOCK_TESTER(n) ((uint32_t)(n) << OCOTP_LOCK_TESTER_SHIFT) -#define OCOTP_LOCK_BOOT_CFG_SHIFT (2) /* Bits: 2-3 Status of shadow register and OTP write lock for boot_cfg region. */ -#define OCOTP_LOCK_BOOT_CFG_MASK (3 << OCOTP_LOCK_BOOT_CFG_SHIFT) -# define OCOTP_LOCK_BOOT_CFG(n) ((uint32_t)(n) << OCOTP_LOCK_BOOT_CFG_SHIFT) -#define OCOTP_LOCK_MEM_TRIM_SHIFT (4) /* Bits: 4-5 Status of shadow register and OTP write lock for mem_trim region. */ -#define OCOTP_LOCK_MEM_TRIM_MASK (3 << OCOTP_LOCK_MEM_TRIM_SHIFT) -# define OCOTP_LOCK_MEM_TRIM(n) ((uint32_t)(n) << OCOTP_LOCK_MEM_TRIM_SHIFT) -#define OCOTP_LOCK_SJC_RESP (1 << 6) /* Bit: 6 Status of shadow register read and write, OTP read and write lock for sjc_resp region. */ -#define OCOTP_LOCK_GP4_RLOCK (1 << 7) /* Bit: 7 Status of shadow register and OTP read lock for gp4 region. */ -#define OCOTP_LOCK_MAC_ADDR_SHIFT (8) /* Bits: 8-9 Status of shadow register and OTP write lock for mac_addr region. */ -#define OCOTP_LOCK_MAC_ADDR_MASK (3 << OCOTP_LOCK_MAC_ADDR_SHIFT) -# define OCOTP_LOCK_MAC_ADDR(n) ((uint32_t)(n) << OCOTP_LOCK_MAC_ADDR_SHIFT) -#define OCOTP_LOCK_GP1_SHIFT (10) /* Bits: 10-11 Status of shadow register and OTP write lock for gp2 region. */ -#define OCOTP_LOCK_GP1_MASK (3 << OCOTP_LOCK_GP1_SHIFT) -# define OCOTP_LOCK_GP1(n) ((uint32_t)(n) << OCOTP_LOCK_GP1_SHIFT) -#define OCOTP_LOCK_GP2_SHIFT (12) /* Bits: 12-13 Status of shadow register and OTP write lock for gp2 region.*/ -#define OCOTP_LOCK_GP2_MASK (3 << OCOTP_LOCK_GP2_SHIFT) -# define OCOTP_LOCK_GP2(n) ((uint32_t)(n) << OCOTP_LOCK_GP2_SHIFT) -#define OCOTP_LOCK_SRK (1 << 14) /* Bit: 14 Status of shadow register and OTP write lock for srk region. */ -#define OCOTP_LOCK_ROM_PATCH (1 << 15) /* Bit: 15 Status of shadow register and OTP write lock for rom_patch region. */ -#define OCOTP_LOCK_SW_GP1 (1 << 16) /* Bit: 16 Status of shadow register and OTP write lock for sw_gp1 region.*/ -#define OCOTP_LOCK_OTPMK (1 << 17) /* Bit: 17 Status of shadow register and OTP write lock for OTPMK region. */ -#define OCOTP_LOCK_ANALOG_SHIFT (18) /* Bits: 18-19 Status of shadow register and OTP write lock for analog region. */ -#define OCOTP_LOCK_ANALOG_MASK (3 << OCOTP_LOCK_ANALOG_SHIFT) -#define OCOTP_LOCK_SW_GP2_LOCK (1 << 21) /* Bit: 21 Status of shadow register and OTP write lock for sw_gp2 region.*/ -#define OCOTP_LOCK_MISC_CONF (1 << 22) /* Bit: 22 Status of shadow register and OTP write lock for misc_conf region.*/ -#define OCOTP_LOCK_SW_GP2_RLOCK (1 << 23) /* Bit: 23 Status of shadow register and OTP read lock for sw_gp2 region. */ -#define OCOTP_LOCK_GP4_SHIFT (24) /* Bits: 24-25 Status of shadow register and OTP write lock for GP4 region. */ -#define OCOTP_LOCK_GP4_MASK (3 << OCOTP_LOCK_GP4_SHIFT) -# define OCOTP_LOCK_GP4(n) ((uint32_t)(n) << OCOTP_LOCK_GP4_SHIFT) -#define OCOTP_LOCK_GP3_SHIFT (26) /* Bits: 26-27 Status of shadow register and OTP write lock for GP3 region. */ -#define OCOTP_LOCK_GP3_MASK (3 << OCOTP_LOCK_GP3_SHIFT) -# define OCOTP_LOCK_GP3(n) ((uint32_t)(n) << OCOTP_LOCK_GP3_SHIFT) -#define OCOTP_LOCK_FIELD_RETURN_SHIFT (28) /* Bits: 28-31 When write field_return shadow register(only highest 4bits valid), the bits[27:0] must be kept as 0. */ -#define OCOTP_LOCK_FIELD_RETURN_MASK (15 << OCOTP_LOCK_FIELD_RETURN_SHIFT) -# define OCOTP_LOCK_FIELD_RETURN(n) ((uint32_t)(n) << OCOTP_LOCK_FIELD_RETURN_SHIFT) - -#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_OCOTP_H */ diff --git a/arch/arm/src/imxrt/chip/imxrt_pinmux.h b/arch/arm/src/imxrt/chip/imxrt_pinmux.h deleted file mode 100644 index ffcdc1f6ab8..00000000000 --- a/arch/arm/src/imxrt/chip/imxrt_pinmux.h +++ /dev/null @@ -1,56 +0,0 @@ -/************************************************************************************ - * arch/arm/src/imxrt/chip/imxrt_pinmux.h - * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * David Sidrane - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_PINMUX_H -#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_PINMUX_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#if defined(CONFIG_ARCH_FAMILY_IMXRT102x) -# include "chip/rt102x/imxrt102x_pinmux.h" -#elif defined(CONFIG_ARCH_FAMILY_IMXRT105x) -# include "chip/rt105x/imxrt105x_pinmux.h" -#elif defined(CONFIG_ARCH_FAMILY_IMXRT106x) -# include "chip/rt106x/imxrt106x_pinmux.h" -#else -# error Unrecognized i.MX RT architecture -#endif - -#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_PINMUX_H */ diff --git a/arch/arm/src/imxrt/chip/imxrt_pit.h b/arch/arm/src/imxrt/chip/imxrt_pit.h deleted file mode 100644 index 69241853071..00000000000 --- a/arch/arm/src/imxrt/chip/imxrt_pit.h +++ /dev/null @@ -1,131 +0,0 @@ -/************************************************************************************ - * arch/arm/src/imxrt/chip/imxrt_pit.h - * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * David Sidrane - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_PIT_H -#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_PIT_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include -#include "chip/imxrt_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register Offsets *****************************************************************/ - -#define IMXRT_PIT_MCR_OFFSET 0x0000 /* PIT Module Control Register */ -#define IMXRT_PIT_LTMR64H_OFFSET 0x00e0 /* PIT Upper Lifetime Timer Register */ -#define IMXRT_PIT_LTMR64L_OFFSET 0x00e4 /* PIT Lower Lifetime Timer Register */ -#define IMXRT_PIT_LDVAL0_OFFSET 0x0100 /* Timer Load Value Register */ -#define IMXRT_PIT_CVAL0_OFFSET 0x0104 /* Current Timer Value Register */ -#define IMXRT_PIT_TCTRL0_OFFSET 0x0108 /* Timer Control Register */ -#define IMXRT_PIT_TFLG0_OFFSET 0x010c /* Timer Flag Register */ -#define IMXRT_PIT_LDVAL1_OFFSET 0x0110 /* Timer Load Value Register */ -#define IMXRT_PIT_CVAL1_OFFSET 0x0114 /* Current Timer Value Register */ -#define IMXRT_PIT_TCTRL1_OFFSET 0x0118 /* Timer Control Register */ -#define IMXRT_PIT_TFLG1_OFFSET 0x011c /* Timer Flag Register */ -#define IMXRT_PIT_LDVAL2_OFFSET 0x0120 /* Timer Load Value Register */ -#define IMXRT_PIT_CVAL2_OFFSET 0x0124 /* Current Timer Value Register */ -#define IMXRT_PIT_TCTRL2_OFFSET 0x0128 /* Timer Control Register */ -#define IMXRT_PIT_TFLG2_OFFSET 0x012c /* Timer Flag Register */ -#define IMXRT_PIT_LDVAL3_OFFSET 0x0130 /* Timer Load Value Register */ -#define IMXRT_PIT_CVAL3_OFFSET 0x0134 /* Current Timer Value Register */ -#define IMXRT_PIT_TCTRL3_OFFSET 0x0138 /* Timer Control Register */ -#define IMXRT_PIT_TFLG3_OFFSET 0x013c /* Timer Flag Register */ - -/* Register Addresses ***************************************************************/ - -#define IMXRT_PIT_MCR (IMXRT_PIT_BASE+IMXRT_PIT_MCR_OFFSET) -#define IMXRT_PIT_LTMR64H (IMXRT_PIT_BASE+IMXRT_PIT_LTMR64H_OFFSET) -#define IMXRT_PIT_LTMR64L (IMXRT_PIT_BASE+IMXRT_PIT_LTMR64L_OFFSET) -#define IMXRT_PIT_LDVAL0 (IMXRT_PIT_BASE+IMXRT_PIT_LDVAL0_OFFSET) -#define IMXRT_PIT_CVAL0 (IMXRT_PIT_BASE+IMXRT_PIT_CVAL0_OFFSET) -#define IMXRT_PIT_TCTRL0 (IMXRT_PIT_BASE+IMXRT_PIT_TCTRL0_OFFSET) -#define IMXRT_PIT_TFLG0 (IMXRT_PIT_BASE+IMXRT_PIT_TFLG0_OFFSET) -#define IMXRT_PIT_LDVAL1 (IMXRT_PIT_BASE+IMXRT_PIT_LDVAL1_OFFSET) -#define IMXRT_PIT_CVAL1 (IMXRT_PIT_BASE+IMXRT_PIT_CVAL1_OFFSET) -#define IMXRT_PIT_TCTRL1 (IMXRT_PIT_BASE+IMXRT_PIT_TCTRL1_OFFSET) -#define IMXRT_PIT_TFLG1 (IMXRT_PIT_BASE+IMXRT_PIT_TFLG1_OFFSET) -#define IMXRT_PIT_LDVAL2 (IMXRT_PIT_BASE+IMXRT_PIT_LDVAL2_OFFSET) -#define IMXRT_PIT_CVAL2 (IMXRT_PIT_BASE+IMXRT_PIT_CVAL2_OFFSET) -#define IMXRT_PIT_TCTRL2 (IMXRT_PIT_BASE+IMXRT_PIT_TCTRL2_OFFSET) -#define IMXRT_PIT_TFLG2 (IMXRT_PIT_BASE+IMXRT_PIT_TFLG2_OFFSET) -#define IMXRT_PIT_LDVAL3 (IMXRT_PIT_BASE+IMXRT_PIT_LDVAL3_OFFSET) -#define IMXRT_PIT_CVAL3 (IMXRT_PIT_BASE+IMXRT_PIT_CVAL3_OFFSET) -#define IMXRT_PIT_TCTRL3 (IMXRT_PIT_BASE+IMXRT_PIT_TCTRL3_OFFSET) -#define IMXRT_PIT_TFLG3 (IMXRT_PIT_BASE+IMXRT_PIT_TFLG3_OFFSET) - -/* Register Bit Definitions *********************************************************/ - -/* PIT Module Control Register */ - -#define PIT_MCR_FRZ (1 << 0) /* Bit 0: Freeze */ -#define PIT_MCR_MDIS (1 << 1) /* Bit 1: Module Disable */ - /* Bits 2-31: Reserved */ - -/* Timer Load Value Register (32-bit Timer Start Value Bits) */ -/* Current Timer Value Register (32-bit Current Timer Value) */ - -/* Timer Control Register */ - -#define PIT_TCTRL_TEN (1 << 0) /* Bit 0: Timer Enable Bit */ -#define PIT_TCTRL_TIE (1 << 1) /* Bit 1: Timer Interrupt Enable Bit */ - /* Bits 2-31: Reserved */ -#define PIT_TCTRL_CHN (1 << 2) /* Bit 2: Chain Mode */ - /* Bits 3-31: Reserved */ - -/* Timer Flag Register */ - -#define PIT_TFLG_TIF (1 << 0) /* Bit 0: Timer Interrupt Flag */ - /* Bits 1-31: Reserved */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_PIT_H */ diff --git a/arch/arm/src/imxrt/chip/imxrt_snvs.h b/arch/arm/src/imxrt/chip/imxrt_snvs.h deleted file mode 100644 index 7bead26f3e6..00000000000 --- a/arch/arm/src/imxrt/chip/imxrt_snvs.h +++ /dev/null @@ -1,297 +0,0 @@ -/******************************************************************************************** - * arch/arm/src/imxrt/imxrt_snvs.h - * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ********************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_SNVS_H -#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_SNVS_H - -/******************************************************************************************** - * Included Files - ********************************************************************************************/ - -#include -#include "chip/imxrt_memorymap.h" - -/******************************************************************************************** - * Pre-processor Definitions - ********************************************************************************************/ - -#define IMXRT_SNVS_LP_MAXTAMPER 10 - -/* Register offsets *************************************************************************/ - -#define IMXRT_SNVS_HPLR_OFFSET 0x0000 /* SNVS_HP Lock Register */ -#define IMXRT_SNVS_HPCOMR_OFFSET 0x0004 /* SNVS_HP Command Register */ -#define IMXRT_SNVS_HPCR_OFFSET 0x0008 /* SNVS_HP Control Register */ -#define IMXRT_SNVS_HPSR_OFFSET 0x0014 /* SNVS_HP Status Register */ -#define IMXRT_SNVS_HPRTCMR_OFFSET 0x0024 /* SNVS_HP Real Time Counter MSB Register */ -#define IMXRT_SNVS_HPRTCLR_OFFSET 0x0028 /* SNVS_HP Real Time Counter LSB Register */ -#define IMXRT_SNVS_HPTAMR_OFFSET 0x002c /* SNVS_HP Time Alarm MSB Register */ -#define IMXRT_SNVS_HPTALR_OFFSET 0x0030 /* SNVS_HP Time Alarm LSB Register */ -#define IMXRT_SNVS_LPLR_OFFSET 0x0034 /* SNVS_LP Lock Register */ -#define IMXRT_SNVS_LPCR_OFFSET 0x0038 /* SNVS_LP Control Register */ -#define IMXRT_SNVS_LPSR_OFFSET 0x004c /* SNVS_LP Status Register */ -#define IMXRT_SNVS_LPSMCMR_OFFSET 0x005c /* SNVS_LP Secure Monotonic Counter MSB Register */ -#define IMXRT_SNVS_LPSMCLR_OFFSET 0x0060 /* SNVS_LP Secure Monotonic Counter LSB Register */ - -#define IMXRT_SNVS_LPGPR0L_OFFSET 0x0068 /* SNVS_LP General Purpose Register 0 (legacy alias) */ - -#define IMXRT_SNVS_LPGPRA_OFFSET(n) (0x0090 + ((n) << 2)) -#define IMXRT_SNVS_LPGPR0A_OFFSET 0x0090 /* NVS_LP General Purpose Registers 0 LPGPR0_alias */ -#define IMXRT_SNVS_LPGPR1A_OFFSET 0x0094 /* NVS_LP General Purpose Registers 1 LPGPR1_alias */ -#define IMXRT_SNVS_LPGPR2A_OFFSET 0x0098 /* NVS_LP General Purpose Registers 2 LPGPR2_alias */ -#define IMXRT_SNVS_LPGPR3A_OFFSET 0x009c /* NVS_LP General Purpose Registers 3 LPGPR3_alias */ - -#define IMXRT_SNVS_LPGPR_OFFSET(n) (0x0100 + ((n) << 2)) -#define IMXRT_SNVS_LPGPR0_OFFSET 0x0100 /* SNVS_LP General Purpose Registers 0 */ -#define IMXRT_SNVS_LPGPR1_OFFSET 0x0104 /* SNVS_LP General Purpose Registers 1 */ -#define IMXRT_SNVS_LPGPR2_OFFSET 0x0108 /* SNVS_LP General Purpose Registers 2 */ -#define IMXRT_SNVS_LPGPR3_OFFSET 0x010c /* SNVS_LP General Purpose Registers 3 */ - -#define IMXRT_SNVS_HPVIDR1_OFFSET 0x0bf8 /* SNVS_HP Version ID Register 1 */ -#define IMXRT_SNVS_HPVIDR2_OFFSET 0x0bfc /* SNVS_HP Version ID Register 2 */ - -/* Register addresses ***********************************************************************/ - -#define IMXRT_SNVS_HPLR (IMXRT_SNVSHP_BASE + IMXRT_SNVS_HPLR_OFFSET) -#define IMXRT_SNVS_HPCOMR (IMXRT_SNVSHP_BASE + IMXRT_SNVS_HPCOMR_OFFSET) -#define IMXRT_SNVS_HPCR (IMXRT_SNVSHP_BASE + IMXRT_SNVS_HPCR_OFFSET) -#define IMXRT_SNVS_HPSR (IMXRT_SNVSHP_BASE + IMXRT_SNVS_HPSR_OFFSET) -#define IMXRT_SNVS_HPRTCMR (IMXRT_SNVSHP_BASE + IMXRT_SNVS_HPRTCMR_OFFSET) -#define IMXRT_SNVS_HPRTCLR (IMXRT_SNVSHP_BASE + IMXRT_SNVS_HPRTCLR_OFFSET) -#define IMXRT_SNVS_HPTAMR (IMXRT_SNVSHP_BASE + IMXRT_SNVS_HPTAMR_OFFSET) -#define IMXRT_SNVS_HPTALR (IMXRT_SNVSHP_BASE + IMXRT_SNVS_HPTALR_OFFSET) -#define IMXRT_SNVS_LPLR (IMXRT_SNVSHP_BASE + IMXRT_SNVS_LPLR_OFFSET) -#define IMXRT_SNVS_LPCR (IMXRT_SNVSHP_BASE + IMXRT_SNVS_LPCR_OFFSET) -#define IMXRT_SNVS_LPSR (IMXRT_SNVSHP_BASE + IMXRT_SNVS_LPSR_OFFSET) -#define IMXRT_SNVS_LPSMCMR (IMXRT_SNVSHP_BASE + IMXRT_SNVS_LPSMCMR_OFFSET) -#define IMXRT_SNVS_LPSMCLR (IMXRT_SNVSHP_BASE + IMXRT_SNVS_LPSMCLR_OFFSET) - -#define IMXRT_SNVS_LPGPR0L (IMXRT_SNVSHP_BASE + IMXRT_SNVS_LPGPR0L_OFFSET) - -#define IMXRT_SNVS_LPGPRA(n) (IMXRT_SNVSHP_BASE + IMXRT_SNVS_LPGPRA_OFFSET(n)) -#define IMXRT_SNVS_LPGPR0A (IMXRT_SNVSHP_BASE + IMXRT_SNVS_LPGPR0A_OFFSET) -#define IMXRT_SNVS_LPGPR1A (IMXRT_SNVSHP_BASE + IMXRT_SNVS_LPGPR1A_OFFSET) -#define IMXRT_SNVS_LPGPR2A (IMXRT_SNVSHP_BASE + IMXRT_SNVS_LPGPR2A_OFFSET) -#define IMXRT_SNVS_LPGPR3A (IMXRT_SNVSHP_BASE + IMXRT_SNVS_LPGPR3A_OFFSET) - -#define IMXRT_SNVS_LPGPR(n) (IMXRT_SNVSHP_BASE + IMXRT_SNVS_LPGPR_OFFSET(n)) -#define IMXRT_SNVS_LPGPR0 (IMXRT_SNVSHP_BASE + IMXRT_SNVS_LPGPR0_OFFSET) -#define IMXRT_SNVS_LPGPR1 (IMXRT_SNVSHP_BASE + IMXRT_SNVS_LPGPR1_OFFSET) -#define IMXRT_SNVS_LPGPR2 (IMXRT_SNVSHP_BASE + IMXRT_SNVS_LPGPR2_OFFSET) -#define IMXRT_SNVS_LPGPR3 (IMXRT_SNVSHP_BASE + IMXRT_SNVS_LPGPR3_OFFSET) - -#define IMXRT_SNVS_HPVIDR1 (IMXRT_SNVSHP_BASE + IMXRT_SNVS_HPVIDR1_OFFSET) -#define IMXRT_SNVS_HPVIDR2 (IMXRT_SNVSHP_BASE + IMXRT_SNVS_HPVIDR2_OFFSET) - -/* Register bit definitions *****************************************************************/ - -/* SNVS_HP Lock Register */ - - /* Bits 0-3: Reserved */ -#define SNVS_HPLR_MCSL (1 << 4) /* Bit 4: Monotonic Counter Soft Lock */ -#define SNVS_HPLR_GPRSL (1 << 5) /* Bit 5: General Purpose Register Soft Lock */ - /* Bits 6-31: Reserved */ - -/* SNVS_HP Command Register */ - - /* Bits 0-3: Reserved */ -#define SNVS_HPCOMR_LPSWR (1 << 4) /* Bit 4: LP Software Reset */ -#define SNVS_HPCOMR_LPSWRDIS (1 << 5) /* Bit 5: LP Software Reset Disable */ - /* Bits 6-7: Reserved */ -#define SNVS_HPCOMR_SWSV (1 << 8) /* Bit 8: */ - /* Bits 9-30: Reserved */ -#define SNVS_HPCOMR_NPSWAEN (1 << 31) /* Bit 31: Non-Privileged Software Access Enable */ - -/* SNVS_HP Control Register */ - -#define SNVS_HPCR_RTCEN (1 << 0) /* Bit 0: HP Real Time Counter Enable */ -#define SNVS_HPCR_HPTAEN (1 << 1) /* Bit 1: HP Time Alarm Enable */ -#define SNVS_HPCR_DISPI (1 << 2) /* Bit 2: Disable periodic interrupt in the functional interrupt */ - /* Bit 2: Reserved */ -#define SNVS_HPCR_PIEN (1 << 3) /* Bit 3: HP Periodic Interrupt Enable */ -#define SNVS_HPCR_PIFREQ_SHIFT (4) /* Bits 4-7: Periodic Interrupt Frequency */ -#define SNVS_HPCR_PIFREQ_MASK (15 << SNVS_HPCR_PIFREQ_SHIFT) -# define SNVS_HPCR_PIFREQ(n) ((uint32_t)(n) << SNVS_HPCR_PIFREQ_SHIFT) -#define SNVS_HPCR_HPCALBEN (1 << 8) /* Bit 8: HP Real Time Counter Calibration Enabled */ - /* Bit 9: Reserved */ -#define SNVS_HPCR_HPCALBVAL_SHIFT (10) /* Bits 10-14: HP Calibration Value */ -#define SNVS_HPCR_HPCALBVAL_MASK (31 << SNVS_HPCR_HPCALBVAL_SHIFT) -# define SNVS_HPCR_HPCALBVAL(n) ((uint32_t)(n) << SNVS_HPCR_HPCALBVAL_SHIFT) -# define SNVS_HPCR_HPCALBVAL_ZERO (0 << SNVS_HPCR_HPCALBVAL_SHIFT) /* +0 counts per 32768 ticks */ -# define SNVS_HPCR_HPCALBVAL_P1 (1 << SNVS_HPCR_HPCALBVAL_SHIFT) /* +1 counts per 32768 ticks */ -# define SNVS_HPCR_HPCALBVAL_P2 (2 << SNVS_HPCR_HPCALBVAL_SHIFT) /* +2 counts per 32768 ticks */ -# define SNVS_HPCR_HPCALBVAL_P15 (15 << SNVS_HPCR_HPCALBVAL_SHIFT) /* +15 counts per 32768 ticks */ -# define SNVS_HPCR_HPCALBVAL_M16 (16 << SNVS_HPCR_HPCALBVAL_SHIFT) /* -16 counts per 32768 ticks */ -# define SNVS_HPCR_HPCALBVAL_M15 (17 << SNVS_HPCR_HPCALBVAL_SHIFT) /* -15 counts per 32768 ticks */ -# define SNVS_HPCR_HPCALBVAL_M2 (30 << SNVS_HPCR_HPCALBVAL_SHIFT) /* -2 counts per 32768 ticks */ -# define SNVS_HPCR_HPCALBVAL_M1 (31 << SNVS_HPCR_HPCALBVAL_SHIFT) /* -1 counts per 32768 ticks */ - /* Bits 15: Reserved */ -#define SNVS_HPCR_HPTS (1 << 16) /* Bit 16: LPSRTC time sychronization */ - /* Bits 17-23: Reserved */ -#define SNVS_HPCR_BTNCONFIG_SHIFT (24) /* Bits 24-26: Button Configuration */ -#define SNVS_HPCR_BTNCONFIG_MASK (7 << SNVS_HPCR_BTNCONFIG_SHIFT) -# define SNVS_HPCR_BTNCONFIG_ LOW (0 << SNVS_HPCR_BTNCONFIG_SHIFT) /* Button signal active low */ -# define SNVS_HPCR_BTNCONFIG_HIGH (1 << SNVS_HPCR_BTNCONFIG_SHIFT) /* Button signal active high */ -# define SNVS_HPCR_BTNCONFIG_RISING (2 << SNVS_HPCR_BTNCONFIG_SHIFT) /* Button signal active on rising edge */ -# define SNVS_HPCR_BTNCONFIG_FALLING (3 << SNVS_HPCR_BTNCONFIG_SHIFT) /* Button signal active on falling edge */ -# define SNVS_HPCR_BTNCONFIG_BOTH (4 << SNVS_HPCR_BTNCONFIG_SHIFT) /* Button signal active on any edge */ -#define SNVS_HPCR_BTNMASK (1 << 27) /* Bit 27: Button interrupt mask */ - /* Bits 28-31: Reserved */ - -/* SNVS_HP Status Register */ - -#define SNVS_HPSR_HPTA (1 << 0) /* Bit 0: HP Time Alarm */ -#define SNVS_HPSR_PI (1 << 1) /* Bit 1: Periodic Interrupt */ - /* Bits 2-3: Reserved */ -#define SNVS_HPSR_LPDIS (1 << 4) /* Bit 4: Low Power Disable */ - /* Bit 95 Reserved */ -#define SNVS_HPSR_BTN (1 << 6) /* Bit 6: Button */ -#define SNVS_HPSR_BI (1 << 7) /* Bit 7: Button Interrupt */ - /* Bits 8-31: Reserved */ - -/* SNVS_HP Real Time Counter MSB Register (15-bit MSB of counter) */ -/* SNVS_HP Real Time Counter LSB Register (32-bit LSB of counter) */ - -#define SNVS_HPRTCMR_MASK 0x00007fff /* Bits 0-14: HP Real Time Counter */ - -/* SNVS_HP Time Alarm MSB Register (15-bit MSB of counter) */ -/* SNVS_HP Time Alarm LSB Register (32-bit LSB of counter) */ - -#define SNVS_HPTAMR_MASK 0x00007fff /* Bits 0-14: HP Time Alarm, most-significant 15 bits */ - -/* SNVS_LP Lock Register */ - - /* Bits 0-3: Reserved */ -#define SNVS_LPLR_MCHL (1 << 4) /* Bit 4: Monotonic Counter Hard Lock */ -#define SNVS_LPLR_GPRHL (1 << 5) /* Bit 5: General Purpose Register Hard Lock */ - /* Bits 6-31: Reserved */ - -/* SNVS_LP Control Register */ - -#define SVNS_LPCR_SRTCENV (1 << 0) /* Bit 0: Start SVNS RTC time counter */ -#define SVNS_LPCR_LPTAEN (1 << 1) /* Bit 1: Enable SVNS RTC time alarm */ -#define SNVS_LPCR_MCENV (1 << 2) /* Bit 2: Monotonic Counter Enabled and Valid */ -#define SNVS_LPCR_LPWUIEN (1 << 3) /* Bit 3: LP Wake-Up Interrupt Enable */ - /* Bit 4: Reserved */ -#define SNVS_LPCR_DPEN (1 << 5) /* Bit 5: Dumb PMIC Enabled */ -#define SNVS_LPCR_TOP (1 << 6) /* Bit 6: Turn off System Power */ -#define SNVS_LPCR_PWRGLITCHEN (1 << 7) /* Bit 7: Power Glitch Enable */ - /* Bits 8-15: Reserved for i.MX1050 family */ -#define SNVS_LPCR_LPCALBEN (1 << 8) /* Bit 8: LP Real Time Counter Calibration Enabled */ - /* Bit 9: Reserved */ -#define SNVS_LPCR_LPCALBVAL_SHIFT (10) /* Bits 10-14: LP Calibration Value */ -#define SNVS_LPCR_LPCALBVAL_MASK (31 << SNVS_LPCR_LPCALBVAL_SHIFT) -# define SNVS_LPCR_LPCALBVAL(n) ((uint32_t)(n) << SNVS_LPCR_LPCALBVAL_SHIFT) -# define SNVS_LPCR_LPCALBVAL_ZERO (0 << SNVS_LPCR_LPCALBVAL_SHIFT) /* +0 counts per 32768 ticks */ -# define SNVS_LPCR_LPCALBVAL_P1 (1 << SNVS_LPCR_LPCALBVAL_SHIFT) /* +1 counts per 32768 ticks */ -# define SNVS_LPCR_LPCALBVAL_P2 (2 << SNVS_LPCR_LPCALBVAL_SHIFT) /* +2 counts per 32768 ticks */ -# define SNVS_LPCR_LPCALBVAL_P15 (15 << SNVS_LPCR_LPCALBVAL_SHIFT) /* +15 counts per 32768 ticks */ -# define SNVS_LPCR_LPCALBVAL_M16 (16 << SNVS_LPCR_LPCALBVAL_SHIFT) /* -16 counts per 32768 ticks */ -# define SNVS_LPCR_LPCALBVAL_M15 (17 << SNVS_LPCR_LPCALBVAL_SHIFT) /* -15 counts per 32768 ticks */ -# define SNVS_LPCR_LPCALBVAL_M2 (30 << SNVS_LPCR_LPCALBVAL_SHIFT) /* -2 counts per 32768 ticks */ -# define SNVS_LPCR_LPCALBVAL_M1 (31 << SNVS_LPCR_LPCALBVAL_SHIFT) /* -1 counts per 32768 ticks */ - /* Bit 15: Reserved */ -#define SNVS_LPCR_BTNPRESSTIME_SHIFT (16) /* Bits 16-17: PMIC button press time out values */ -#define SNVS_LPCR_BTNPRESSTIME_MASK (3 << SNVS_LPCR_BTNPRESSTIME_SHIFT) -# define SNVS_LPCR_BTNPRESSTIME_5SEC (0 << SNVS_LPCR_BTNPRESSTIME_SHIFT) /* 5 secs */ -# define SNVS_LPCR_BTNPRESSTIME_10SEC (1 << SNVS_LPCR_BTNPRESSTIME_SHIFT) /* 10 secs */ -# define SNVS_LPCR_BTNPRESSTIME_15SEC (2 << SNVS_LPCR_BTNPRESSTIME_SHIFT) /* 15 secs */ -# define SNVS_LPCR_BTNPRESSTIME_DESAB (3 << SNVS_LPCR_BTNPRESSTIME_SHIFT) /* Long press disabled */ -#define SNVS_LPCR_DEBOUNCE_SHIFT (18) /* Bits 18-19: Debounce time for BTN input signal */ -#define SNVS_LPCR_DEBOUNCE_MASK (3 << SNVS_LPCR_DEBOUNCE_SHIFT) -# define SNVS_LPCR_DEBOUNCE_50MS (0 << SNVS_LPCR_DEBOUNCE_SHIFT) /* 50msec debounce */ -# define SNVS_LPCR_DEBOUNCE_100MS (1 << SNVS_LPCR_DEBOUNCE_SHIFT) /* 100msec debounce */ -# define SNVS_LPCR_DEBOUNCE_500MS (2 << SNVS_LPCR_DEBOUNCE_SHIFT) /* 500msec debounce */ -# define SNVS_LPCR_DEBOUNCE_NONE (3 << SNVS_LPCR_DEBOUNCE_SHIFT) /* 0msec debounce */ -#define SNVS_LPCR_ONTIME_SHIFT (20) /* Bits 20-21: ON time configuration */ -#define SNVS_LPCR_ONTIME_MASK (3 << SNVS_LPCR_ONTIME_SHIFT) -# define SNVS_LPCR_ONTIME_500MS (0 << SNVS_LPCR_ONTIME_SHIFT) /* 500msec off->on transition time */ -# define SNVS_LPCR_ONTIME_50MS (1 << SNVS_LPCR_ONTIME_SHIFT) /* 50msec off->on transition time */ -# define SNVS_LPCR_ONTIME_100MS (2 << SNVS_LPCR_ONTIME_SHIFT) /* 100msec off->on transition time */ -# define SNVS_LPCR_ONTIME_NONE (3 << SNVS_LPCR_ONTIME_SHIFT) /* 0msec off->on transition time */ -#define SNVS_LPCR_PKEN (1 << 22) /* Bit 22: PMIC On Request Enable */ -#define SNVS_LPCR_PKOVERRIDE (1 << 23) /* Bit 23: PMIC On Request Override */ - /* Bits 24-31: Reserved */ - -/* SNVS_LP Status Register */ - - /* Bits 0-1: Reserved */ -#define SNVS_LPSR_MCR (1 << 2) /* Bit 2: Monotonic Counter Rollover */ - /* Bits 3-16: Reserved */ -#define SNVS_LPSR_EO (1 << 17) /* Bit 17: Emergency Off */ -#define SNVS_LPSR_SPO (1 << 18) /* Bit 18: Set Power Off */ - /* Bits 19-31: Reserved */ - -/* SNVS_LP Secure Monotonic Counter MSB Register */ -/* SNVS_LP Secure Monotonic Counter LSB Register (32-bit LSB counter value) */ - -#define SNVS_LPSMCMR_MONCOUNTER_SHIFT (0) /* Bits 0-15: Monotonic Counter most-significant 16 Bits */ -#define SNVS_LPSMCMR_MONCOUNTER_MASK (0xffff << SNVS_LPSMCMR_MONCOUNTER_SHIFT) -# define SNVS_LPSMCMR_MONCOUNTER(n) ((uint32_t)(n) << SNVS_LPSMCMR_MONCOUNTER_SHIFT) -#define SNVS_LPSMCMR_MCERABITS_SHIFT (16) /* Bits 16-31: Monotonic Counter Era Bits */ -#define SNVS_LPSMCMR_MCERABITS_MASK (0xffff << SNVS_LPSMCMR_MCERABITS_SHIFT) -# define SNVS_LPSMCMR_MCERABITS(n) ((uint32_t)(n) << SNVS_LPSMCMR_MCERABITS_SHIFT) - -/* SNVS_LP General Purpose Register 0 (legacy alias) (32-bit value) */ -/* NVS_LP General Purpose Registers 0 LPGPR0_alias (32-bit value) */ -/* NVS_LP General Purpose Registers 1 LPGPR1_alias (32-bit value) */ -/* NVS_LP General Purpose Registers 2 LPGPR2_alias (32-bit value) */ -/* NVS_LP General Purpose Registers 3 LPGPR3_alias (32-bit value) */ -/* SNVS_LP General Purpose Registers 0 (32-bit value) */ -/* SNVS_LP General Purpose Registers 1 (32-bit value) */ -/* SNVS_LP General Purpose Registers 2 (32-bit value) */ -/* SNVS_LP General Purpose Registers 3 (32-bit value) */ - -/* SNVS_HP Version ID Register 1 */ - -#define SNVS_HPVIDR1_MINORREV_SHIFT (0) /* Bits 0-7: SNVS block minor version number */ -#define SNVS_HPVIDR1_MINORREV_MASK (0xff << SNVS_HPVIDR1_MINORREV_SHIFT) -#define SNVS_HPVIDR1_MAJORREV_SHIFT (8) /* Bits 8-15: SNVS block major version number */ -#define SNVS_HPVIDR1_MAJORREV_MASK (0xff << SNVS_HPVIDR1_MAJORREV_SHIFT) -#define SNVS_HPVIDR1_IPID_SHIFT (16) /* Bits 16-31: SNVS block ID */ -#define SNVS_HPVIDR1_IPID_MASK (0xffff << SNVS_HPVIDR1_IPID_SHIFT) - -/* SNVS_HP Version ID Register 2 */ - -#define SNVS_HPVIDR2_CONFIGOPT_SHIFT (0) /* Bits 0-7: SNVS Configuration Options */ -#define SNVS_HPVIDR2_CONFIGOPT_MASK (0xff << SNVS_HPVIDR2_CONFIGOPT_SHIFT) -#define SNVS_HPVIDR2_ECOREV_SHIFT (8) /* Bits 8-15: SNVS ECO Revision */ -#define SNVS_HPVIDR2_ECOREV_MASK (0xff << SNVS_HPVIDR2_ECOREV_SHIFT) -#define SNVS_HPVIDR2_INTGOPT_SHIFT (16) /* Bits 16-23: SNVS Integration Options */ -#define SNVS_HPVIDR2_INTGOPT_MASK (0xff << SNVS_HPVIDR2_INTGOPT_SHIFT) -#define SNVS_HPVIDR2_IPERA_SHIFT (24) /* Bits 24-31: IP Era */ -#define SNVS_HPVIDR2_IPERA_MASK (0xff << SNVS_HPVIDR2_IPERA_SHIFT) - -#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_SNVS_H */ diff --git a/arch/arm/src/imxrt/chip/imxrt_src.h b/arch/arm/src/imxrt/chip/imxrt_src.h deleted file mode 100644 index 60beeedbe96..00000000000 --- a/arch/arm/src/imxrt/chip/imxrt_src.h +++ /dev/null @@ -1,157 +0,0 @@ -/******************************************************************************************** - * arch/arm/src/imxrt/imxrt_src.h - * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ********************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_SRC_H -#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_SRC_H - -/******************************************************************************************** - * Included Files - ********************************************************************************************/ - -#include -#include "chip/imxrt_memorymap.h" - -/******************************************************************************************** - * Pre-processor Definitions - ********************************************************************************************/ - -/* Register offsets *************************************************************************/ - -#define IMXRT_SRC_SCR_OFFSET 0x0000 /* SRC Control Register */ -#define IMXRT_SRC_SBMR1_OFFSET 0x0004 /* SRC Boot Mode Register 1 */ -#define IMXRT_SRC_SRSR_OFFSET 0x0008 /* SRC Reset Status Register */ -#define IMXRT_SRC_SBMR2_OFFSET 0x001c /* SRC Boot Mode Register 2 */ -#define IMXRT_SRC_GPR1_OFFSET 0x0020 /* SRC General Purpose Register 1 */ -#define IMXRT_SRC_GPR2_OFFSET 0x0024 /* SRC General Purpose Register 2 */ -#define IMXRT_SRC_GPR3_OFFSET 0x0028 /* SRC General Purpose Register 3 */ -#define IMXRT_SRC_GPR4_OFFSET 0x002c /* SRC General Purpose Register 4 */ -#define IMXRT_SRC_GPR5_OFFSET 0x0030 /* SRC General Purpose Register 5 */ -#define IMXRT_SRC_GPR6_OFFSET 0x0034 /* SRC General Purpose Register 6 */ -#define IMXRT_SRC_GPR7_OFFSET 0x0038 /* SRC General Purpose Register 7 */ -#define IMXRT_SRC_GPR8_OFFSET 0x003c /* SRC General Purpose Register 8 */ -#define IMXRT_SRC_GPR9_OFFSET 0x0040 /* SRC General Purpose Register 9 */ -#define IMXRT_SRC_GPR10_OFFSET 0x0044 /* SRC General Purpose Register 10 */ - -/* Register addresses ***********************************************************************/ - -#define IMXRT_SRC_SCR (IMXRT_SRC_BASE + IMXRT_SRC_SCR_OFFSET) -#define IMXRT_SRC_SBMR1 (IMXRT_SRC_BASE + IMXRT_SRC_SBMR1_OFFSET) -#define IMXRT_SRC_SRSR (IMXRT_SRC_BASE + IMXRT_SRC_SRSR_OFFSET) -#define IMXRT_SRC_SBMR2 (IMXRT_SRC_BASE + IMXRT_SRC_SBMR2_OFFSET) -#define IMXRT_SRC_GPR1 (IMXRT_SRC_BASE + IMXRT_SRC_GPR1_OFFSET) -#define IMXRT_SRC_GPR2 (IMXRT_SRC_BASE + IMXRT_SRC_GPR2_OFFSET) -#define IMXRT_SRC_GPR3 (IMXRT_SRC_BASE + IMXRT_SRC_GPR3_OFFSET) -#define IMXRT_SRC_GPR4 (IMXRT_SRC_BASE + IMXRT_SRC_GPR4_OFFSET) -#define IMXRT_SRC_GPR5 (IMXRT_SRC_BASE + IMXRT_SRC_GPR5_OFFSET) -#define IMXRT_SRC_GPR6 (IMXRT_SRC_BASE + IMXRT_SRC_GPR6_OFFSET) -#define IMXRT_SRC_GPR7 (IMXRT_SRC_BASE + IMXRT_SRC_GPR7_OFFSET) -#define IMXRT_SRC_GPR8 (IMXRT_SRC_BASE + IMXRT_SRC_GPR8_OFFSET) -#define IMXRT_SRC_GPR9 (IMXRT_SRC_BASE + IMXRT_SRC_GPR9_OFFSET) -#define IMXRT_SRC_GPR10 (IMXRT_SRC_BASE + IMXRT_SRC_GPR10_OFFSET) - -/* Register bit definitions *****************************************************************/ - -/* SRC Control Register */ - - /* Bits 0-3: Reserved */ -#define SRC_SCR_LOCKUP_RST (1 << 4) /* Bit 4: Lockup reset enable bit */ - /* Bits 5-6: Reserved */ -#define SRC_SCR_MASK_WDOG_RST_SHIFT (7) /* Bits 7-10: Mask wdog_rst_b source */ -#define SRC_SCR_MASK_WDOG_RST_MASK (15 << SRC_SCR_MASK_WDOG_RST_SHIFT) -# define SRC_SCR_MASK_WDOG_RST_MASKED (5 << SRC_SCR_MASK_WDOG_RST_SHIFT) -# define SRC_SCR_MASK_WDOG_RST_UNMASKED (10 << SRC_SCR_MASK_WDOG_RST_SHIFT) - /* Bits 11-12: Reserved */ -#define SRC_SCR_CORE0_RST (1 << 13) /* Bit 13: Software reset for core0 only. */ - /* Bits 14-16: Reserved */ -#define SRC_SCR_CORE0_DBG_RST (1 << 17) /* Bit 17: Software reset for core0 debug only */ - /* Bits 18-24: Reserved */ -#define SRC_SCR_DBG_RST_MSK_PG (1 << 25) /* Bit 25: Do not assert debug resets - * after power gating event of core */ - /* Bits 26-27: Reserved */ -#define SRC_SCR_MASK_WDOG3_RST_SHIFT (28) /* Bits 38-31: Mask wdog3_rst_b source */ -#define SRC_SCR_MASK_WDOG3_RST_MASK (15 << SRC_SCR_MASK_WDOG3_RST_SHIFT) -# define SRC_SCR_MASK_WDOG3_RST_MASKED (5 << SRC_SCR_MASK_WDOG3_RST_SHIFT) -# define SRC_SCR_MASK_WDOG3_RST_UNMASKED (10 << SRC_SCR_MASK_WDOG3_RST_SHIFT) - -/* SRC Boot Mode Register 1 */ - -#define SRC_SBMR1_BOOT_CFG_SHIFT (24) /* Bits 24-31: Refer to fusemap */ -#define SRC_SBMR1_BOOT_CFG_MASK (0xff << SRC_SBMR1_BOOT_CFG_SHIFT) -#define SRC_SBMR1_BOOT_CFG2_SHIFT (16) /* Bits 16-23: Refer to fusemap */ -#define SRC_SBMR1_BOOT_CFG2_MASK (0xff << SRC_SBMR1_BOOT_CFG2_SHIFT) -#define SRC_SBMR1_BOOT_CFG3_SHIFT (8) /* Bits 8-15: Refer to fusemap */ -#define SRC_SBMR1_BOOT_CFG3_MASK (0xff << SRC_SBMR1_BOOT_CFG3_SHIFT) -#define SRC_SBMR1_BOOT_CFG4_SHIFT (0) /* Bits 0-7: Refer to fusemap */ -#define SRC_SBMR1_BOOT_CFG4_MASK (0xff << SRC_SBMR1_BOOT_CFG4_SHIFT) - -/* SRC Reset Status Register */ - -#define SRC_SRSR_IPP_RESET_B (1 << 0) /* Bit 0: Indicates whether reset was the - * result of ipp_reset_b pin (Power-up - * sequence) */ -#define SRC_SRSR_LOCKUP_SYSRESETREQ (1 << 1) /* Bit 1: Indicates a reset has been - * caused by CPU lockup or software setting - * of SYSRESETREQ bit */ -#define SRC_SRSR_CSU_RESET_B (1 << 2) /* Bit 2: Indicates whether the reset was - * the result of the csu_reset_b input */ -#define SRC_SRSR_IPP_USER_RESET_B (1 << 3) /* Bit 3: Indicates whether the reset was - * the result of the ipp_user_reset_b qualified - * reset */ -#define SRC_SRSR_WDOG_RST_B (1 << 4) /* Bit 4: IC Watchdog Time-out reset */ -#define SRC_SRSR_JTAG_RST_B (1 << 5) /* Bit 5: HIGH - Z JTAG reset */ -#define SRC_SRSR_JTAG_SW_RST (1 << 6) /* Bit 6: JTAG software reset */ -#define SRC_SRSR_WDOG3_RST_B (1 << 7) /* Bit 7: IC Watchdog3 Time-out reset */ -#define SRC_SRSR_TEMPSENSE_RST_B (1 << 8) /* Bit 8: Temper Sensor software reset */ - /* Bits 9-31: Reserved */ - -/* SRC Boot Mode Register 2 */ - -#define SRC_SBMR2_SEC_CONFIG_SHIFT (0) /* Bits 0-1: State of the corresponding - * SECONFIG fuse */ - /* Bit 2: Reserved */ -#define SRC_SBMR2_DIR_BT_DIS (1 << 3) /* Bit 3: State of the DIR_BT_DIS fuse */ -#define SRC_SBMR2_BT_FUSE_SEL (1 << 4) /* Bit 4: State of the BT_FUSE_SEL fuse */ - /* Bits 5-23: Reserved */ -#define SRC_SBMR2_BMOD_SHIFT (24) /* Bits 24-25: Latched state of the BOOT_MODE - * and BOOT_MODE0 signals on POR. - /* Bits 26-31: Reserved */ - -/* SRC General Purpose Register 1 (32-bit values, some have reserved bits) - * NOTE: Ald GPR registers are used by the ROM code and should not be used by application - * software. - */ - -#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_SRC_H */ - diff --git a/arch/arm/src/imxrt/chip/imxrt_tmr.h b/arch/arm/src/imxrt/chip/imxrt_tmr.h deleted file mode 100644 index ae24118fe99..00000000000 --- a/arch/arm/src/imxrt/chip/imxrt_tmr.h +++ /dev/null @@ -1,662 +0,0 @@ -/******************************************************************************************************************************************** - * arch/arm/src/imxrt/chip/imxrt_tmr.h - * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * David Sidrane - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ********************************************************************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_TMR_H -#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_TMR_H - -/******************************************************************************************************************************************** - * Included Files - ********************************************************************************************************************************************/ - -#include -#include "chip/imxrt_memorymap.h" - -/******************************************************************************************************************************************** - * Pre-processor Definitions - ********************************************************************************************************************************************/ - -/* Register Offsets *************************************************************************************************************************/ - -#define IMXRT_TMR_COMP1_OFFSET 0x0000 /* Timer Channel Compare Register 1 */ -#define IMXRT_TMR_COMP2_OFFSET 0x0002 /* Timer Channel Compare Register 2 */ -#define IMXRT_TMR_CAPT_OFFSET 0x0004 /* Timer Channel Capture Register */ -#define IMXRT_TMR_LOAD_OFFSET 0x0006 /* Timer Channel Load Register */ -#define IMXRT_TMR_HOLD_OFFSET 0x0008 /* Timer Channel Hold Register */ -#define IMXRT_TMR_CNTR_OFFSET 0x000a /* Timer Channel Counter Register */ -#define IMXRT_TMR_CTRL_OFFSET 0x000c /* Timer Channel Control Register */ -#define IMXRT_TMR_SCTRL_OFFSET 0x000e /* Timer Channel Status and Control Register */ -#define IMXRT_TMR_CMPLD1_OFFSET 0x0010 /* Timer Channel Comparator Load Register 1 */ -#define IMXRT_TMR_CMPLD2_OFFSET 0x0012 /* Timer Channel Comparator Load Register 2 */ -#define IMXRT_TMR_CSCTRL_OFFSET 0x0014 /* Timer Channel Comparator Status and Control Register */ -#define IMXRT_TMR_FILT_OFFSET 0x0016 /* Timer Channel Input Filter Register */ -#define IMXRT_TMR_DMA_OFFSET 0x0018 /* Timer Channel DMA Enable Register */ -#define IMXRT_TMR_ENBL_OFFSET 0x001e /* Timer Channel Enable Register */ - -#define IMXRT_TMR_CHANNEL_SPACING 0x20 /* Each timer has 4 Channels spaced 0x20 apart */ -#define IMXRT_TMR_CH0 (0 * IMXRT_TMR_CHANNEL_SPACING) -#define IMXRT_TMR_CH1 (1 * IMXRT_TMR_CHANNEL_SPACING) -#define IMXRT_TMR_CH2 (2 * IMXRT_TMR_CHANNEL_SPACING) -#define IMXRT_TMR_CH3 (3 * IMXRT_TMR_CHANNEL_SPACING) - -#define IMXRT_TMR_OFFSET(ch,r) ((r) + (ch)) - -#define IMXRT_TMR1_COMP10_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_COMP1_OFFSET) /* Timer Channel Compare Register 1 */ -#define IMXRT_TMR1_COMP20_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_COMP2_OFFSET) /* Timer Channel Compare Register 2 */ -#define IMXRT_TMR1_CAPT0_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_CAPT_OFFSET) /* Timer Channel Capture Register */ -#define IMXRT_TMR1_LOAD0_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_LOAD_OFFSET) /* Timer Channel Load Register */ -#define IMXRT_TMR1_HOLD0_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_HOLD_OFFSET) /* Timer Channel Hold Register */ -#define IMXRT_TMR1_CNTR0_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_CNTR_OFFSET) /* Timer Channel Counter Register */ -#define IMXRT_TMR1_CTRL0_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_CTRL_OFFSET) /* Timer Channel Control Register */ -#define IMXRT_TMR1_SCTRL0_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_SCTRL_OFFSET) /* Timer Channel Status and Control Register */ -#define IMXRT_TMR1_CMPLD10_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_CMPLD1_OFFSET) /* Timer Channel Comparator Load Register 1 */ -#define IMXRT_TMR1_CMPLD20_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_CMPLD2_OFFSET) /* Timer Channel Comparator Load Register 2 */ -#define IMXRT_TMR1_CSCTRL0_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_CSCTRL_OFFSET) /* Timer Channel Comparator Status and Control Register */ -#define IMXRT_TMR1_FILT0_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_FILT_OFFSET) /* Timer Channel Input Filter Register */ -#define IMXRT_TMR1_DMA0_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_DMA_OFFSET) /* Timer Channel DMA Enable Register */ -#define IMXRT_TMR1_ENBL_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_ENBL_OFFSET) /* Timer Channel Enable Register */ -#define IMXRT_TMR1_COMP11_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_COMP1_OFFSET) /* Timer Channel Compare Register 1 */ -#define IMXRT_TMR1_COMP21_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_COMP2_OFFSET) /* Timer Channel Compare Register 2 */ -#define IMXRT_TMR1_CAPT1_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_CAPT_OFFSET) /* Timer Channel Capture Register */ -#define IMXRT_TMR1_LOAD1_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_LOAD_OFFSET) /* Timer Channel Load Register */ -#define IMXRT_TMR1_HOLD1_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_HOLD_OFFSET) /* Timer Channel Hold Register */ -#define IMXRT_TMR1_CNTR1_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_CNTR_OFFSET) /* Timer Channel Counter Register */ -#define IMXRT_TMR1_CTRL1_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_CTRL_OFFSET) /* Timer Channel Control Register */ -#define IMXRT_TMR1_SCTRL1_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_SCTRL_OFFSET) /* Timer Channel Status and Control Register */ -#define IMXRT_TMR1_CMPLD11_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_CMPLD1_OFFSET) /* Timer Channel Comparator Load Register 1 */ -#define IMXRT_TMR1_CMPLD21_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_CMPLD2_OFFSET) /* Timer Channel Comparator Load Register 2 */ -#define IMXRT_TMR1_CSCTRL1_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_CSCTRL_OFFSET) /* Timer Channel Comparator Status and Control Register */ -#define IMXRT_TMR1_FILT1_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_FILT_OFFSET) /* Timer Channel Input Filter Register */ -#define IMXRT_TMR1_DMA1_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_DMA_OFFSET) /* Timer Channel DMA Enable Register */ -#define IMXRT_TMR1_COMP12_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_COMP1_OFFSET) /* Timer Channel Compare Register 1 */ -#define IMXRT_TMR1_COMP22_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_COMP2_OFFSET) /* Timer Channel Compare Register 2 */ -#define IMXRT_TMR1_CAPT2_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_CAPT_OFFSET) /* Timer Channel Capture Register */ -#define IMXRT_TMR1_LOAD2_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_LOAD_OFFSET) /* Timer Channel Load Register */ -#define IMXRT_TMR1_HOLD2_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_HOLD_OFFSET) /* Timer Channel Hold Register */ -#define IMXRT_TMR1_CNTR2_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_CNTR_OFFSET) /* Timer Channel Counter Register */ -#define IMXRT_TMR1_CTRL2_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_CTRL_OFFSET) /* Timer Channel Control Register */ -#define IMXRT_TMR1_SCTRL2_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_SCTRL_OFFSET) /* Timer Channel Status and Control Register */ -#define IMXRT_TMR1_CMPLD12_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_CMPLD1_OFFSET) /* Timer Channel Comparator Load Register 1 */ -#define IMXRT_TMR1_CMPLD22_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_CMPLD2_OFFSET) /* Timer Channel Comparator Load Register 2 */ -#define IMXRT_TMR1_CSCTRL2_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_CSCTRL_OFFSET) /* Timer Channel Comparator Status and Control Register */ -#define IMXRT_TMR1_FILT2_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_FILT_OFFSET) /* Timer Channel Input Filter Register */ -#define IMXRT_TMR1_DMA2_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_DMA_OFFSET) /* Timer Channel DMA Enable Register */ -#define IMXRT_TMR1_COMP13_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_COMP1_OFFSET) /* Timer Channel Compare Register 1 */ -#define IMXRT_TMR1_COMP23_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_COMP2_OFFSET) /* Timer Channel Compare Register 2 */ -#define IMXRT_TMR1_CAPT3_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_CAPT_OFFSET) /* Timer Channel Capture Register */ -#define IMXRT_TMR1_LOAD3_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_LOAD_OFFSET) /* Timer Channel Load Register */ -#define IMXRT_TMR1_HOLD3_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_HOLD_OFFSET) /* Timer Channel Hold Register */ -#define IMXRT_TMR1_CNTR3_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_CNTR_OFFSET) /* Timer Channel Counter Register */ -#define IMXRT_TMR1_CTRL3_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_CTRL_OFFSET) /* Timer Channel Control Register */ -#define IMXRT_TMR1_SCTRL3_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_SCTRL_OFFSET) /* Timer Channel Status and Control Register */ -#define IMXRT_TMR1_CMPLD13_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_CMPLD1_OFFSET) /* Timer Channel Comparator Load Register 1 */ -#define IMXRT_TMR1_CMPLD23_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_CMPLD2_OFFSET) /* Timer Channel Comparator Load Register 2 */ -#define IMXRT_TMR1_CSCTRL3_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_CSCTRL_OFFSET) /* Timer Channel Comparator Status and Control Register */ -#define IMXRT_TMR1_FILT3_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_FILT_OFFSET) /* Timer Channel Input Filter Register */ -#define IMXRT_TMR1_DMA3_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_DMA_OFFSET) /* Timer Channel DMA Enable Register */ - -/* Timer 2 offset */ - -#define IMXRT_TMR2_COMP10_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_COMP1_OFFSET) /* Timer Channel Compare Register 1 */ -#define IMXRT_TMR2_COMP20_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_COMP2_OFFSET) /* Timer Channel Compare Register 2 */ -#define IMXRT_TMR2_CAPT0_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_CAPT_OFFSET) /* Timer Channel Capture Register */ -#define IMXRT_TMR2_LOAD0_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_LOAD_OFFSET) /* Timer Channel Load Register */ -#define IMXRT_TMR2_HOLD0_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_HOLD_OFFSET) /* Timer Channel Hold Register */ -#define IMXRT_TMR2_CNTR0_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_CNTR_OFFSET) /* Timer Channel Counter Register */ -#define IMXRT_TMR2_CTRL0_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_CTRL_OFFSET) /* Timer Channel Control Register */ -#define IMXRT_TMR2_SCTRL0_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_SCTRL_OFFSET) /* Timer Channel Status and Control Register */ -#define IMXRT_TMR2_CMPLD10_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_CMPLD1_OFFSET) /* Timer Channel Comparator Load Register 1 */ -#define IMXRT_TMR2_CMPLD20_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_CMPLD2_OFFSET) /* Timer Channel Comparator Load Register 2 */ -#define IMXRT_TMR2_CSCTRL0_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_CSCTRL_OFFSET) /* Timer Channel Comparator Status and Control Register */ -#define IMXRT_TMR2_FILT0_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_FILT_OFFSET) /* Timer Channel Input Filter Register */ -#define IMXRT_TMR2_DMA0_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_DMA_OFFSET) /* Timer Channel DMA Enable Register */ -#define IMXRT_TMR2_ENBL_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_ENBL_OFFSET) /* Timer Channel Enable Register */ -#define IMXRT_TMR2_COMP11_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_COMP1_OFFSET) /* Timer Channel Compare Register 1 */ -#define IMXRT_TMR2_COMP21_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_COMP2_OFFSET) /* Timer Channel Compare Register 2 */ -#define IMXRT_TMR2_CAPT1_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_CAPT_OFFSET) /* Timer Channel Capture Register */ -#define IMXRT_TMR2_LOAD1_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_LOAD_OFFSET) /* Timer Channel Load Register */ -#define IMXRT_TMR2_HOLD1_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_HOLD_OFFSET) /* Timer Channel Hold Register */ -#define IMXRT_TMR2_CNTR1_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_CNTR_OFFSET) /* Timer Channel Counter Register */ -#define IMXRT_TMR2_CTRL1_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_CTRL_OFFSET) /* Timer Channel Control Register */ -#define IMXRT_TMR2_SCTRL1_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_SCTRL_OFFSET) /* Timer Channel Status and Control Register */ -#define IMXRT_TMR2_CMPLD11_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_CMPLD1_OFFSET) /* Timer Channel Comparator Load Register 1 */ -#define IMXRT_TMR2_CMPLD21_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_CMPLD2_OFFSET) /* Timer Channel Comparator Load Register 2 */ -#define IMXRT_TMR2_CSCTRL1_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_CSCTRL_OFFSET) /* Timer Channel Comparator Status and Control Register */ -#define IMXRT_TMR2_FILT1_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_FILT_OFFSET) /* Timer Channel Input Filter Register */ -#define IMXRT_TMR2_DMA1_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_DMA_OFFSET) /* Timer Channel DMA Enable Register */ -#define IMXRT_TMR2_COMP12_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_COMP1_OFFSET) /* Timer Channel Compare Register 1 */ -#define IMXRT_TMR2_COMP22_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_COMP2_OFFSET) /* Timer Channel Compare Register 2 */ -#define IMXRT_TMR2_CAPT2_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_CAPT_OFFSET) /* Timer Channel Capture Register */ -#define IMXRT_TMR2_LOAD2_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_LOAD_OFFSET) /* Timer Channel Load Register */ -#define IMXRT_TMR2_HOLD2_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_HOLD_OFFSET) /* Timer Channel Hold Register */ -#define IMXRT_TMR2_CNTR2_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_CNTR_OFFSET) /* Timer Channel Counter Register */ -#define IMXRT_TMR2_CTRL2_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_CTRL_OFFSET) /* Timer Channel Control Register */ -#define IMXRT_TMR2_SCTRL2_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_SCTRL_OFFSET) /* Timer Channel Status and Control Register */ -#define IMXRT_TMR2_CMPLD12_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_CMPLD1_OFFSET) /* Timer Channel Comparator Load Register 1 */ -#define IMXRT_TMR2_CMPLD22_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_CMPLD2_OFFSET) /* Timer Channel Comparator Load Register 2 */ -#define IMXRT_TMR2_CSCTRL2_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_CSCTRL_OFFSET) /* Timer Channel Comparator Status and Control Register */ -#define IMXRT_TMR2_FILT2_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_FILT_OFFSET) /* Timer Channel Input Filter Register */ -#define IMXRT_TMR2_DMA2_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_DMA_OFFSET) /* Timer Channel DMA Enable Register */ -#define IMXRT_TMR2_COMP13_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_COMP1_OFFSET) /* Timer Channel Compare Register 1 */ -#define IMXRT_TMR2_COMP23_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_COMP2_OFFSET) /* Timer Channel Compare Register 2 */ -#define IMXRT_TMR2_CAPT3_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_CAPT_OFFSET) /* Timer Channel Capture Register */ -#define IMXRT_TMR2_LOAD3_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_LOAD_OFFSET) /* Timer Channel Load Register */ -#define IMXRT_TMR2_HOLD3_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_HOLD_OFFSET) /* Timer Channel Hold Register */ -#define IMXRT_TMR2_CNTR3_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_CNTR_OFFSET) /* Timer Channel Counter Register */ -#define IMXRT_TMR2_CTRL3_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_CTRL_OFFSET) /* Timer Channel Control Register */ -#define IMXRT_TMR2_SCTRL3_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_SCTRL_OFFSET) /* Timer Channel Status and Control Register */ -#define IMXRT_TMR2_CMPLD13_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_CMPLD1_OFFSET) /* Timer Channel Comparator Load Register 1 */ -#define IMXRT_TMR2_CMPLD23_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_CMPLD2_OFFSET) /* Timer Channel Comparator Load Register 2 */ -#define IMXRT_TMR2_CSCTRL3_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_CSCTRL_OFFSET) /* Timer Channel Comparator Status and Control Register */ -#define IMXRT_TMR2_FILT3_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_FILT_OFFSET) /* Timer Channel Input Filter Register */ -#define IMXRT_TMR2_DMA3_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_DMA_OFFSET) /* Timer Channel DMA Enable Register */ - -/* Timer 3 offset */ - -#define IMXRT_TMR3_COMP10_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_COMP1_OFFSET) /* Timer Channel Compare Register 1 */ -#define IMXRT_TMR3_COMP20_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_COMP2_OFFSET) /* Timer Channel Compare Register 2 */ -#define IMXRT_TMR3_CAPT0_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_CAPT_OFFSET) /* Timer Channel Capture Register */ -#define IMXRT_TMR3_LOAD0_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_LOAD_OFFSET) /* Timer Channel Load Register */ -#define IMXRT_TMR3_HOLD0_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_HOLD_OFFSET) /* Timer Channel Hold Register */ -#define IMXRT_TMR3_CNTR0_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_CNTR_OFFSET) /* Timer Channel Counter Register */ -#define IMXRT_TMR3_CTRL0_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_CTRL_OFFSET) /* Timer Channel Control Register */ -#define IMXRT_TMR3_SCTRL0_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_SCTRL_OFFSET) /* Timer Channel Status and Control Register */ -#define IMXRT_TMR3_CMPLD10_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_CMPLD1_OFFSET) /* Timer Channel Comparator Load Register 1 */ -#define IMXRT_TMR3_CMPLD20_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_CMPLD2_OFFSET) /* Timer Channel Comparator Load Register 2 */ -#define IMXRT_TMR3_CSCTRL0_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_CSCTRL_OFFSET) /* Timer Channel Comparator Status and Control Register */ -#define IMXRT_TMR3_FILT0_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_FILT_OFFSET) /* Timer Channel Input Filter Register */ -#define IMXRT_TMR3_DMA0_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_DMA_OFFSET) /* Timer Channel DMA Enable Register */ -#define IMXRT_TMR3_ENBL_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_ENBL_OFFSET) /* Timer Channel Enable Register */ -#define IMXRT_TMR3_COMP11_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_COMP1_OFFSET) /* Timer Channel Compare Register 1 */ -#define IMXRT_TMR3_COMP21_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_COMP2_OFFSET) /* Timer Channel Compare Register 2 */ -#define IMXRT_TMR3_CAPT1_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_CAPT_OFFSET) /* Timer Channel Capture Register */ -#define IMXRT_TMR3_LOAD1_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_LOAD_OFFSET) /* Timer Channel Load Register */ -#define IMXRT_TMR3_HOLD1_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_HOLD_OFFSET) /* Timer Channel Hold Register */ -#define IMXRT_TMR3_CNTR1_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_CNTR_OFFSET) /* Timer Channel Counter Register */ -#define IMXRT_TMR3_CTRL1_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_CTRL_OFFSET) /* Timer Channel Control Register */ -#define IMXRT_TMR3_SCTRL1_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_SCTRL_OFFSET) /* Timer Channel Status and Control Register */ -#define IMXRT_TMR3_CMPLD11_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_CMPLD1_OFFSET) /* Timer Channel Comparator Load Register 1 */ -#define IMXRT_TMR3_CMPLD21_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_CMPLD2_OFFSET) /* Timer Channel Comparator Load Register 2 */ -#define IMXRT_TMR3_CSCTRL1_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_CSCTRL_OFFSET) /* Timer Channel Comparator Status and Control Register */ -#define IMXRT_TMR3_FILT1_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_FILT_OFFSET) /* Timer Channel Input Filter Register */ -#define IMXRT_TMR3_DMA1_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_DMA_OFFSET) /* Timer Channel DMA Enable Register */ -#define IMXRT_TMR3_COMP12_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_COMP1_OFFSET) /* Timer Channel Compare Register 1 */ -#define IMXRT_TMR3_COMP22_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_COMP2_OFFSET) /* Timer Channel Compare Register 2 */ -#define IMXRT_TMR3_CAPT2_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_CAPT_OFFSET) /* Timer Channel Capture Register */ -#define IMXRT_TMR3_LOAD2_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_LOAD_OFFSET) /* Timer Channel Load Register */ -#define IMXRT_TMR3_HOLD2_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_HOLD_OFFSET) /* Timer Channel Hold Register */ -#define IMXRT_TMR3_CNTR2_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_CNTR_OFFSET) /* Timer Channel Counter Register */ -#define IMXRT_TMR3_CTRL2_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_CTRL_OFFSET) /* Timer Channel Control Register */ -#define IMXRT_TMR3_SCTRL2_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_SCTRL_OFFSET) /* Timer Channel Status and Control Register */ -#define IMXRT_TMR3_CMPLD12_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_CMPLD1_OFFSET) /* Timer Channel Comparator Load Register 1 */ -#define IMXRT_TMR3_CMPLD22_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_CMPLD2_OFFSET) /* Timer Channel Comparator Load Register 2 */ -#define IMXRT_TMR3_CSCTRL2_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_CSCTRL_OFFSET) /* Timer Channel Comparator Status and Control Register */ -#define IMXRT_TMR3_FILT2_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_FILT_OFFSET) /* Timer Channel Input Filter Register */ -#define IMXRT_TMR3_DMA2_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_DMA_OFFSET) /* Timer Channel DMA Enable Register */ -#define IMXRT_TMR3_COMP13_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_COMP1_OFFSET) /* Timer Channel Compare Register 1 */ -#define IMXRT_TMR3_COMP23_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_COMP2_OFFSET) /* Timer Channel Compare Register 2 */ -#define IMXRT_TMR3_CAPT3_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_CAPT_OFFSET) /* Timer Channel Capture Register */ -#define IMXRT_TMR3_LOAD3_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_LOAD_OFFSET) /* Timer Channel Load Register */ -#define IMXRT_TMR3_HOLD3_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_HOLD_OFFSET) /* Timer Channel Hold Register */ -#define IMXRT_TMR3_CNTR3_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_CNTR_OFFSET) /* Timer Channel Counter Register */ -#define IMXRT_TMR3_CTRL3_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_CTRL_OFFSET) /* Timer Channel Control Register */ -#define IMXRT_TMR3_SCTRL3_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_SCTRL_OFFSET) /* Timer Channel Status and Control Register */ -#define IMXRT_TMR3_CMPLD13_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_CMPLD1_OFFSET) /* Timer Channel Comparator Load Register 1 */ -#define IMXRT_TMR3_CMPLD23_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_CMPLD2_OFFSET) /* Timer Channel Comparator Load Register 2 */ -#define IMXRT_TMR3_CSCTRL3_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_CSCTRL_OFFSET) /* Timer Channel Comparator Status and Control Register */ -#define IMXRT_TMR3_FILT3_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_FILT_OFFSET) /* Timer Channel Input Filter Register */ -#define IMXRT_TMR3_DMA3_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_DMA_OFFSET) /* Timer Channel DMA Enable Register */ - -/* Timer 4 offset */ - -#define IMXRT_TMR4_COMP10_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_COMP1_OFFSET) /* Timer Channel Compare Register 1 */ -#define IMXRT_TMR4_COMP20_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_COMP2_OFFSET) /* Timer Channel Compare Register 2 */ -#define IMXRT_TMR4_CAPT0_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_CAPT_OFFSET) /* Timer Channel Capture Register */ -#define IMXRT_TMR4_LOAD0_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_LOAD_OFFSET) /* Timer Channel Load Register */ -#define IMXRT_TMR4_HOLD0_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_HOLD_OFFSET) /* Timer Channel Hold Register */ -#define IMXRT_TMR4_CNTR0_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_CNTR_OFFSET) /* Timer Channel Counter Register */ -#define IMXRT_TMR4_CTRL0_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_CTRL_OFFSET) /* Timer Channel Control Register */ -#define IMXRT_TMR4_SCTRL0_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_SCTRL_OFFSET) /* Timer Channel Status and Control Register */ -#define IMXRT_TMR4_CMPLD10_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_CMPLD1_OFFSET) /* Timer Channel Comparator Load Register 1 */ -#define IMXRT_TMR4_CMPLD20_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_CMPLD2_OFFSET) /* Timer Channel Comparator Load Register 2 */ -#define IMXRT_TMR4_CSCTRL0_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_CSCTRL_OFFSET) /* Timer Channel Comparator Status and Control Register */ -#define IMXRT_TMR4_FILT0_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_FILT_OFFSET) /* Timer Channel Input Filter Register */ -#define IMXRT_TMR4_DMA0_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_DMA_OFFSET) /* Timer Channel DMA Enable Register */ -#define IMXRT_TMR4_ENBL_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH0, IMXRT_TMR_ENBL_OFFSET) /* Timer Channel Enable Register */ -#define IMXRT_TMR4_COMP11_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_COMP1_OFFSET) /* Timer Channel Compare Register 1 */ -#define IMXRT_TMR4_COMP21_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_COMP2_OFFSET) /* Timer Channel Compare Register 2 */ -#define IMXRT_TMR4_CAPT1_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_CAPT_OFFSET) /* Timer Channel Capture Register */ -#define IMXRT_TMR4_LOAD1_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_LOAD_OFFSET) /* Timer Channel Load Register */ -#define IMXRT_TMR4_HOLD1_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_HOLD_OFFSET) /* Timer Channel Hold Register */ -#define IMXRT_TMR4_CNTR1_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_CNTR_OFFSET) /* Timer Channel Counter Register */ -#define IMXRT_TMR4_CTRL1_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_CTRL_OFFSET) /* Timer Channel Control Register */ -#define IMXRT_TMR4_SCTRL1_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_SCTRL_OFFSET) /* Timer Channel Status and Control Register */ -#define IMXRT_TMR4_CMPLD11_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_CMPLD1_OFFSET) /* Timer Channel Comparator Load Register 1 */ -#define IMXRT_TMR4_CMPLD21_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_CMPLD2_OFFSET) /* Timer Channel Comparator Load Register 2 */ -#define IMXRT_TMR4_CSCTRL1_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_CSCTRL_OFFSET) /* Timer Channel Comparator Status and Control Register */ -#define IMXRT_TMR4_FILT1_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_FILT_OFFSET) /* Timer Channel Input Filter Register */ -#define IMXRT_TMR4_DMA1_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH1, IMXRT_TMR_DMA_OFFSET) /* Timer Channel DMA Enable Register */ -#define IMXRT_TMR4_COMP12_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_COMP1_OFFSET) /* Timer Channel Compare Register 1 */ -#define IMXRT_TMR4_COMP22_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_COMP2_OFFSET) /* Timer Channel Compare Register 2 */ -#define IMXRT_TMR4_CAPT2_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_CAPT_OFFSET) /* Timer Channel Capture Register */ -#define IMXRT_TMR4_LOAD2_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_LOAD_OFFSET) /* Timer Channel Load Register */ -#define IMXRT_TMR4_HOLD2_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_HOLD_OFFSET) /* Timer Channel Hold Register */ -#define IMXRT_TMR4_CNTR2_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_CNTR_OFFSET) /* Timer Channel Counter Register */ -#define IMXRT_TMR4_CTRL2_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_CTRL_OFFSET) /* Timer Channel Control Register */ -#define IMXRT_TMR4_SCTRL2_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_SCTRL_OFFSET) /* Timer Channel Status and Control Register */ -#define IMXRT_TMR4_CMPLD12_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_CMPLD1_OFFSET) /* Timer Channel Comparator Load Register 1 */ -#define IMXRT_TMR4_CMPLD22_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_CMPLD2_OFFSET) /* Timer Channel Comparator Load Register 2 */ -#define IMXRT_TMR4_CSCTRL2_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_CSCTRL_OFFSET) /* Timer Channel Comparator Status and Control Register */ -#define IMXRT_TMR4_FILT2_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_FILT_OFFSET) /* Timer Channel Input Filter Register */ -#define IMXRT_TMR4_DMA2_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH2, IMXRT_TMR_DMA_OFFSET) /* Timer Channel DMA Enable Register */ -#define IMXRT_TMR4_COMP13_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_COMP1_OFFSET) /* Timer Channel Compare Register 1 */ -#define IMXRT_TMR4_COMP23_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_COMP2_OFFSET) /* Timer Channel Compare Register 2 */ -#define IMXRT_TMR4_CAPT3_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_CAPT_OFFSET) /* Timer Channel Capture Register */ -#define IMXRT_TMR4_LOAD3_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_LOAD_OFFSET) /* Timer Channel Load Register */ -#define IMXRT_TMR4_HOLD3_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_HOLD_OFFSET) /* Timer Channel Hold Register */ -#define IMXRT_TMR4_CNTR3_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_CNTR_OFFSET) /* Timer Channel Counter Register */ -#define IMXRT_TMR4_CTRL3_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_CTRL_OFFSET) /* Timer Channel Control Register */ -#define IMXRT_TMR4_SCTRL3_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_SCTRL_OFFSET) /* Timer Channel Status and Control Register */ -#define IMXRT_TMR4_CMPLD13_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_CMPLD1_OFFSET) /* Timer Channel Comparator Load Register 1 */ -#define IMXRT_TMR4_CMPLD23_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_CMPLD2_OFFSET) /* Timer Channel Comparator Load Register 2 */ -#define IMXRT_TMR4_CSCTRL3_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_CSCTRL_OFFSET) /* Timer Channel Comparator Status and Control Register */ -#define IMXRT_TMR4_FILT3_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_FILT_OFFSET) /* Timer Channel Input Filter Register */ -#define IMXRT_TMR4_DMA3_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_DMA_OFFSET) /* Timer Channel DMA Enable Register */ - -/* Register addresses *******************************************************************************************************************************/ - -#define IMXRT_TMR1_COMP10 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_COMP10_OFFSET) /* Timer Channel Compare Register 1 */ -#define IMXRT_TMR1_COMP20 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_COMP20_OFFSET) /* Timer Channel Compare Register 2 */ -#define IMXRT_TMR1_CAPT0 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_CAPT0_OFFSET) /* Timer Channel Capture Register */ -#define IMXRT_TMR1_LOAD0 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_LOAD0_OFFSET) /* Timer Channel Load Register */ -#define IMXRT_TMR1_HOLD0 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_HOLD0_OFFSET) /* Timer Channel Hold Register */ -#define IMXRT_TMR1_CNTR0 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_CNTR0_OFFSET) /* Timer Channel Counter Register */ -#define IMXRT_TMR1_CTRL0 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_CTRL0_OFFSET) /* Timer Channel Control Register */ -#define IMXRT_TMR1_SCTRL0 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_SCTRL0_OFFSET) /* Timer Channel Status and Control Register */ -#define IMXRT_TMR1_CMPLD10 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_CMPLD10_OFFSET) /* Timer Channel Comparator Load Register 1 */ -#define IMXRT_TMR1_CMPLD20 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_CMPLD20_OFFSET) /* Timer Channel Comparator Load Register 2 */ -#define IMXRT_TMR1_CSCTRL0 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_CSCTRL0_OFFSET) /* Timer Channel Comparator Status and Control Register */ -#define IMXRT_TMR1_FILT0 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_FILT0_OFFSET) /* Timer Channel Input Filter Register */ -#define IMXRT_TMR1_DMA0 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_DMA0_OFFSET) /* Timer Channel DMA Enable Register */ -#define IMXRT_TMR1_ENBL (IMXRT_QTIMER1_BASE + IMXRT_TMR1_ENBL_OFFSET) /* Timer Channel Enable Register */ -#define IMXRT_TMR1_COMP11 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_COMP11_OFFSET) /* Timer Channel Compare Register 1 */ -#define IMXRT_TMR1_COMP21 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_COMP21_OFFSET) /* Timer Channel Compare Register 2 */ -#define IMXRT_TMR1_CAPT1 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_CAPT1_OFFSET) /* Timer Channel Capture Register */ -#define IMXRT_TMR1_LOAD1 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_LOAD1_OFFSET) /* Timer Channel Load Register */ -#define IMXRT_TMR1_HOLD1 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_HOLD1_OFFSET) /* Timer Channel Hold Register */ -#define IMXRT_TMR1_CNTR1 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_CNTR1_OFFSET) /* Timer Channel Counter Register */ -#define IMXRT_TMR1_CTRL1 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_CTRL1_OFFSET) /* Timer Channel Control Register */ -#define IMXRT_TMR1_SCTRL1 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_SCTRL1_OFFSET) /* Timer Channel Status and Control Register */ -#define IMXRT_TMR1_CMPLD11 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_CMPLD11_OFFSET) /* Timer Channel Comparator Load Register 1 */ -#define IMXRT_TMR1_CMPLD21 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_CMPLD21_OFFSET) /* Timer Channel Comparator Load Register 2 */ -#define IMXRT_TMR1_CSCTRL1 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_CSCTRL1_OFFSET) /* Timer Channel Comparator Status and Control Register */ -#define IMXRT_TMR1_FILT1 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_FILT1_OFFSET) /* Timer Channel Input Filter Register */ -#define IMXRT_TMR1_DMA1 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_DMA1_OFFSET) /* Timer Channel DMA Enable Register */ -#define IMXRT_TMR1_COMP12 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_COMP12_OFFSET) /* Timer Channel Compare Register 1 */ -#define IMXRT_TMR1_COMP22 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_COMP22_OFFSET) /* Timer Channel Compare Register 2 */ -#define IMXRT_TMR1_CAPT2 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_CAPT2_OFFSET) /* Timer Channel Capture Register */ -#define IMXRT_TMR1_LOAD2 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_LOAD2_OFFSET) /* Timer Channel Load Register */ -#define IMXRT_TMR1_HOLD2 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_HOLD2_OFFSET) /* Timer Channel Hold Register */ -#define IMXRT_TMR1_CNTR2 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_CNTR2_OFFSET) /* Timer Channel Counter Register */ -#define IMXRT_TMR1_CTRL2 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_CTRL2_OFFSET) /* Timer Channel Control Register */ -#define IMXRT_TMR1_SCTRL2 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_SCTRL2_OFFSET) /* Timer Channel Status and Control Register */ -#define IMXRT_TMR1_CMPLD12 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_CMPLD12_OFFSET) /* Timer Channel Comparator Load Register 1 */ -#define IMXRT_TMR1_CMPLD22 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_CMPLD22_OFFSET) /* Timer Channel Comparator Load Register 2 */ -#define IMXRT_TMR1_CSCTRL2 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_CSCTRL2_OFFSET) /* Timer Channel Comparator Status and Control Register */ -#define IMXRT_TMR1_FILT2 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_FILT2_OFFSET) /* Timer Channel Input Filter Register */ -#define IMXRT_TMR1_DMA2 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_DMA2_OFFSET) /* Timer Channel DMA Enable Register */ -#define IMXRT_TMR1_COMP13 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_COMP13_OFFSET) /* Timer Channel Compare Register 1 */ -#define IMXRT_TMR1_COMP23 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_COMP23_OFFSET) /* Timer Channel Compare Register 2 */ -#define IMXRT_TMR1_CAPT3 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_CAPT3_OFFSET) /* Timer Channel Capture Register */ -#define IMXRT_TMR1_LOAD3 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_LOAD3_OFFSET) /* Timer Channel Load Register */ -#define IMXRT_TMR1_HOLD3 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_HOLD3_OFFSET) /* Timer Channel Hold Register */ -#define IMXRT_TMR1_CNTR3 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_CNTR3_OFFSET) /* Timer Channel Counter Register */ -#define IMXRT_TMR1_CTRL3 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_CTRL3_OFFSET) /* Timer Channel Control Register */ -#define IMXRT_TMR1_SCTRL3 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_SCTRL3_OFFSET) /* Timer Channel Status and Control Register */ -#define IMXRT_TMR1_CMPLD13 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_CMPLD13_OFFSET) /* Timer Channel Comparator Load Register 1 */ -#define IMXRT_TMR1_CMPLD23 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_CMPLD23_OFFSET) /* Timer Channel Comparator Load Register 2 */ -#define IMXRT_TMR1_CSCTRL3 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_CSCTRL3_OFFSET) /* Timer Channel Comparator Status and Control Register */ -#define IMXRT_TMR1_FILT3 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_FILT3_OFFSET) /* Timer Channel Input Filter Register */ -#define IMXRT_TMR1_DMA3 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_DMA3_OFFSET) /* Timer Channel DMA Enable Register */ -#define IMXRT_TMR2_COMP10 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_COMP10_OFFSET) /* Timer Channel Compare Register 1 */ -#define IMXRT_TMR2_COMP20 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_COMP20_OFFSET) /* Timer Channel Compare Register 2 */ -#define IMXRT_TMR2_CAPT0 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_CAPT0_OFFSET) /* Timer Channel Capture Register */ -#define IMXRT_TMR2_LOAD0 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_LOAD0_OFFSET) /* Timer Channel Load Register */ -#define IMXRT_TMR2_HOLD0 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_HOLD0_OFFSET) /* Timer Channel Hold Register */ -#define IMXRT_TMR2_CNTR0 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_CNTR0_OFFSET) /* Timer Channel Counter Register */ -#define IMXRT_TMR2_CTRL0 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_CTRL0_OFFSET) /* Timer Channel Control Register */ -#define IMXRT_TMR2_SCTRL0 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_SCTRL0_OFFSET) /* Timer Channel Status and Control Register */ -#define IMXRT_TMR2_CMPLD10 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_CMPLD10_OFFSET) /* Timer Channel Comparator Load Register 1 */ -#define IMXRT_TMR2_CMPLD20 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_CMPLD20_OFFSET) /* Timer Channel Comparator Load Register 2 */ -#define IMXRT_TMR2_CSCTRL0 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_CSCTRL0_OFFSET) /* Timer Channel Comparator Status and Control Register */ -#define IMXRT_TMR2_FILT0 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_FILT0_OFFSET) /* Timer Channel Input Filter Register */ -#define IMXRT_TMR2_DMA0 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_DMA0_OFFSET) /* Timer Channel DMA Enable Register */ -#define IMXRT_TMR2_ENBL (IMXRT_QTIMER2_BASE + IMXRT_TMR2_ENBL_OFFSET) /* Timer Channel Enable Register */ -#define IMXRT_TMR2_COMP11 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_COMP11_OFFSET) /* Timer Channel Compare Register 1 */ -#define IMXRT_TMR2_COMP21 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_COMP21_OFFSET) /* Timer Channel Compare Register 2 */ -#define IMXRT_TMR2_CAPT1 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_CAPT1_OFFSET) /* Timer Channel Capture Register */ -#define IMXRT_TMR2_LOAD1 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_LOAD1_OFFSET) /* Timer Channel Load Register */ -#define IMXRT_TMR2_HOLD1 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_HOLD1_OFFSET) /* Timer Channel Hold Register */ -#define IMXRT_TMR2_CNTR1 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_CNTR1_OFFSET) /* Timer Channel Counter Register */ -#define IMXRT_TMR2_CTRL1 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_CTRL1_OFFSET) /* Timer Channel Control Register */ -#define IMXRT_TMR2_SCTRL1 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_SCTRL1_OFFSET) /* Timer Channel Status and Control Register */ -#define IMXRT_TMR2_CMPLD11 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_CMPLD11_OFFSET) /* Timer Channel Comparator Load Register 1 */ -#define IMXRT_TMR2_CMPLD21 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_CMPLD21_OFFSET) /* Timer Channel Comparator Load Register 2 */ -#define IMXRT_TMR2_CSCTRL1 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_CSCTRL1_OFFSET) /* Timer Channel Comparator Status and Control Register */ -#define IMXRT_TMR2_FILT1 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_FILT1_OFFSET) /* Timer Channel Input Filter Register */ -#define IMXRT_TMR2_DMA1 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_DMA1_OFFSET) /* Timer Channel DMA Enable Register */ -#define IMXRT_TMR2_COMP12 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_COMP12_OFFSET) /* Timer Channel Compare Register 1 */ -#define IMXRT_TMR2_COMP22 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_COMP22_OFFSET) /* Timer Channel Compare Register 2 */ -#define IMXRT_TMR2_CAPT2 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_CAPT2_OFFSET) /* Timer Channel Capture Register */ -#define IMXRT_TMR2_LOAD2 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_LOAD2_OFFSET) /* Timer Channel Load Register */ -#define IMXRT_TMR2_HOLD2 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_HOLD2_OFFSET) /* Timer Channel Hold Register */ -#define IMXRT_TMR2_CNTR2 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_CNTR2_OFFSET) /* Timer Channel Counter Register */ -#define IMXRT_TMR2_CTRL2 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_CTRL2_OFFSET) /* Timer Channel Control Register */ -#define IMXRT_TMR2_SCTRL2 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_SCTRL2_OFFSET) /* Timer Channel Status and Control Register */ -#define IMXRT_TMR2_CMPLD12 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_CMPLD12_OFFSET) /* Timer Channel Comparator Load Register 1 */ -#define IMXRT_TMR2_CMPLD22 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_CMPLD22_OFFSET) /* Timer Channel Comparator Load Register 2 */ -#define IMXRT_TMR2_CSCTRL2 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_CSCTRL2_OFFSET) /* Timer Channel Comparator Status and Control Register */ -#define IMXRT_TMR2_FILT2 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_FILT2_OFFSET) /* Timer Channel Input Filter Register */ -#define IMXRT_TMR2_DMA2 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_DMA2_OFFSET) /* Timer Channel DMA Enable Register */ -#define IMXRT_TMR2_COMP13 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_COMP13_OFFSET) /* Timer Channel Compare Register 1 */ -#define IMXRT_TMR2_COMP23 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_COMP23_OFFSET) /* Timer Channel Compare Register 2 */ -#define IMXRT_TMR2_CAPT3 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_CAPT3_OFFSET) /* Timer Channel Capture Register */ -#define IMXRT_TMR2_LOAD3 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_LOAD3_OFFSET) /* Timer Channel Load Register */ -#define IMXRT_TMR2_HOLD3 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_HOLD3_OFFSET) /* Timer Channel Hold Register */ -#define IMXRT_TMR2_CNTR3 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_CNTR3_OFFSET) /* Timer Channel Counter Register */ -#define IMXRT_TMR2_CTRL3 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_CTRL3_OFFSET) /* Timer Channel Control Register */ -#define IMXRT_TMR2_SCTRL3 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_SCTRL3_OFFSET) /* Timer Channel Status and Control Register */ -#define IMXRT_TMR2_CMPLD13 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_CMPLD13_OFFSET) /* Timer Channel Comparator Load Register 1 */ -#define IMXRT_TMR2_CMPLD23 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_CMPLD23_OFFSET) /* Timer Channel Comparator Load Register 2 */ -#define IMXRT_TMR2_CSCTRL3 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_CSCTRL3_OFFSET) /* Timer Channel Comparator Status and Control Register */ -#define IMXRT_TMR2_FILT3 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_FILT3_OFFSET) /* Timer Channel Input Filter Register */ -#define IMXRT_TMR2_DMA3 (IMXRT_QTIMER2_BASE + IMXRT_TMR2_DMA3_OFFSET) /* Timer Channel DMA Enable Register */ -#define IMXRT_TMR3_COMP10 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_COMP10_OFFSET) /* Timer Channel Compare Register 1 */ -#define IMXRT_TMR3_COMP20 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_COMP20_OFFSET) /* Timer Channel Compare Register 2 */ -#define IMXRT_TMR3_CAPT0 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_CAPT0_OFFSET) /* Timer Channel Capture Register */ -#define IMXRT_TMR3_LOAD0 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_LOAD0_OFFSET) /* Timer Channel Load Register */ -#define IMXRT_TMR3_HOLD0 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_HOLD0_OFFSET) /* Timer Channel Hold Register */ -#define IMXRT_TMR3_CNTR0 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_CNTR0_OFFSET) /* Timer Channel Counter Register */ -#define IMXRT_TMR3_CTRL0 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_CTRL0_OFFSET) /* Timer Channel Control Register */ -#define IMXRT_TMR3_SCTRL0 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_SCTRL0_OFFSET) /* Timer Channel Status and Control Register */ -#define IMXRT_TMR3_CMPLD10 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_CMPLD10_OFFSET) /* Timer Channel Comparator Load Register 1 */ -#define IMXRT_TMR3_CMPLD20 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_CMPLD20_OFFSET) /* Timer Channel Comparator Load Register 2 */ -#define IMXRT_TMR3_CSCTRL0 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_CSCTRL0_OFFSET) /* Timer Channel Comparator Status and Control Register */ -#define IMXRT_TMR3_FILT0 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_FILT0_OFFSET) /* Timer Channel Input Filter Register */ -#define IMXRT_TMR3_DMA0 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_DMA0_OFFSET) /* Timer Channel DMA Enable Register */ -#define IMXRT_TMR3_ENBL (IMXRT_QTIMER3_BASE + IMXRT_TMR3_ENBL_OFFSET) /* Timer Channel Enable Register */ -#define IMXRT_TMR3_COMP11 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_COMP11_OFFSET) /* Timer Channel Compare Register 1 */ -#define IMXRT_TMR3_COMP21 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_COMP21_OFFSET) /* Timer Channel Compare Register 2 */ -#define IMXRT_TMR3_CAPT1 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_CAPT1_OFFSET) /* Timer Channel Capture Register */ -#define IMXRT_TMR3_LOAD1 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_LOAD1_OFFSET) /* Timer Channel Load Register */ -#define IMXRT_TMR3_HOLD1 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_HOLD1_OFFSET) /* Timer Channel Hold Register */ -#define IMXRT_TMR3_CNTR1 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_CNTR1_OFFSET) /* Timer Channel Counter Register */ -#define IMXRT_TMR3_CTRL1 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_CTRL1_OFFSET) /* Timer Channel Control Register */ -#define IMXRT_TMR3_SCTRL1 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_SCTRL1_OFFSET) /* Timer Channel Status and Control Register */ -#define IMXRT_TMR3_CMPLD11 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_CMPLD11_OFFSET) /* Timer Channel Comparator Load Register 1 */ -#define IMXRT_TMR3_CMPLD21 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_CMPLD21_OFFSET) /* Timer Channel Comparator Load Register 2 */ -#define IMXRT_TMR3_CSCTRL1 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_CSCTRL1_OFFSET) /* Timer Channel Comparator Status and Control Register */ -#define IMXRT_TMR3_FILT1 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_FILT1_OFFSET) /* Timer Channel Input Filter Register */ -#define IMXRT_TMR3_DMA1 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_DMA1_OFFSET) /* Timer Channel DMA Enable Register */ -#define IMXRT_TMR3_COMP12 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_COMP12_OFFSET) /* Timer Channel Compare Register 1 */ -#define IMXRT_TMR3_COMP22 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_COMP22_OFFSET) /* Timer Channel Compare Register 2 */ -#define IMXRT_TMR3_CAPT2 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_CAPT2_OFFSET) /* Timer Channel Capture Register */ -#define IMXRT_TMR3_LOAD2 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_LOAD2_OFFSET) /* Timer Channel Load Register */ -#define IMXRT_TMR3_HOLD2 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_HOLD2_OFFSET) /* Timer Channel Hold Register */ -#define IMXRT_TMR3_CNTR2 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_CNTR2_OFFSET) /* Timer Channel Counter Register */ -#define IMXRT_TMR3_CTRL2 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_CTRL2_OFFSET) /* Timer Channel Control Register */ -#define IMXRT_TMR3_SCTRL2 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_SCTRL2_OFFSET) /* Timer Channel Status and Control Register */ -#define IMXRT_TMR3_CMPLD12 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_CMPLD12_OFFSET) /* Timer Channel Comparator Load Register 1 */ -#define IMXRT_TMR3_CMPLD22 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_CMPLD22_OFFSET) /* Timer Channel Comparator Load Register 2 */ -#define IMXRT_TMR3_CSCTRL2 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_CSCTRL2_OFFSET) /* Timer Channel Comparator Status and Control Register */ -#define IMXRT_TMR3_FILT2 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_FILT2_OFFSET) /* Timer Channel Input Filter Register */ -#define IMXRT_TMR3_DMA2 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_DMA2_OFFSET) /* Timer Channel DMA Enable Register */ -#define IMXRT_TMR3_COMP13 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_COMP13_OFFSET) /* Timer Channel Compare Register 1 */ -#define IMXRT_TMR3_COMP23 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_COMP23_OFFSET) /* Timer Channel Compare Register 2 */ -#define IMXRT_TMR3_CAPT3 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_CAPT3_OFFSET) /* Timer Channel Capture Register */ -#define IMXRT_TMR3_LOAD3 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_LOAD3_OFFSET) /* Timer Channel Load Register */ -#define IMXRT_TMR3_HOLD3 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_HOLD3_OFFSET) /* Timer Channel Hold Register */ -#define IMXRT_TMR3_CNTR3 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_CNTR3_OFFSET) /* Timer Channel Counter Register */ -#define IMXRT_TMR3_CTRL3 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_CTRL3_OFFSET) /* Timer Channel Control Register */ -#define IMXRT_TMR3_SCTRL3 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_SCTRL3_OFFSET) /* Timer Channel Status and Control Register */ -#define IMXRT_TMR3_CMPLD13 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_CMPLD13_OFFSET) /* Timer Channel Comparator Load Register 1 */ -#define IMXRT_TMR3_CMPLD23 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_CMPLD23_OFFSET) /* Timer Channel Comparator Load Register 2 */ -#define IMXRT_TMR3_CSCTRL3 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_CSCTRL3_OFFSET) /* Timer Channel Comparator Status and Control Register */ -#define IMXRT_TMR3_FILT3 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_FILT3_OFFSET) /* Timer Channel Input Filter Register */ -#define IMXRT_TMR3_DMA3 (IMXRT_QTIMER3_BASE + IMXRT_TMR3_DMA3_OFFSET) /* Timer Channel DMA Enable Register */ -#define IMXRT_TMR4_COMP10 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_COMP10_OFFSET) /* Timer Channel Compare Register 1 */ -#define IMXRT_TMR4_COMP20 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_COMP20_OFFSET) /* Timer Channel Compare Register 2 */ -#define IMXRT_TMR4_CAPT0 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_CAPT0_OFFSET) /* Timer Channel Capture Register */ -#define IMXRT_TMR4_LOAD0 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_LOAD0_OFFSET) /* Timer Channel Load Register */ -#define IMXRT_TMR4_HOLD0 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_HOLD0_OFFSET) /* Timer Channel Hold Register */ -#define IMXRT_TMR4_CNTR0 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_CNTR0_OFFSET) /* Timer Channel Counter Register */ -#define IMXRT_TMR4_CTRL0 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_CTRL0_OFFSET) /* Timer Channel Control Register */ -#define IMXRT_TMR4_SCTRL0 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_SCTRL0_OFFSET) /* Timer Channel Status and Control Register */ -#define IMXRT_TMR4_CMPLD10 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_CMPLD10_OFFSET) /* Timer Channel Comparator Load Register 1 */ -#define IMXRT_TMR4_CMPLD20 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_CMPLD20_OFFSET) /* Timer Channel Comparator Load Register 2 */ -#define IMXRT_TMR4_CSCTRL0 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_CSCTRL0_OFFSET) /* Timer Channel Comparator Status and Control Register */ -#define IMXRT_TMR4_FILT0 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_FILT0_OFFSET) /* Timer Channel Input Filter Register */ -#define IMXRT_TMR4_DMA0 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_DMA0_OFFSET) /* Timer Channel DMA Enable Register */ -#define IMXRT_TMR4_ENBL (IMXRT_QTIMER4_BASE + IMXRT_TMR4_ENBL_OFFSET) /* Timer Channel Enable Register */ -#define IMXRT_TMR4_COMP11 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_COMP11_OFFSET) /* Timer Channel Compare Register 1 */ -#define IMXRT_TMR4_COMP21 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_COMP21_OFFSET) /* Timer Channel Compare Register 2 */ -#define IMXRT_TMR4_CAPT1 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_CAPT1_OFFSET) /* Timer Channel Capture Register */ -#define IMXRT_TMR4_LOAD1 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_LOAD1_OFFSET) /* Timer Channel Load Register */ -#define IMXRT_TMR4_HOLD1 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_HOLD1_OFFSET) /* Timer Channel Hold Register */ -#define IMXRT_TMR4_CNTR1 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_CNTR1_OFFSET) /* Timer Channel Counter Register */ -#define IMXRT_TMR4_CTRL1 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_CTRL1_OFFSET) /* Timer Channel Control Register */ -#define IMXRT_TMR4_SCTRL1 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_SCTRL1_OFFSET) /* Timer Channel Status and Control Register */ -#define IMXRT_TMR4_CMPLD11 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_CMPLD11_OFFSET) /* Timer Channel Comparator Load Register 1 */ -#define IMXRT_TMR4_CMPLD21 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_CMPLD21_OFFSET) /* Timer Channel Comparator Load Register 2 */ -#define IMXRT_TMR4_CSCTRL1 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_CSCTRL1_OFFSET) /* Timer Channel Comparator Status and Control Register */ -#define IMXRT_TMR4_FILT1 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_FILT1_OFFSET) /* Timer Channel Input Filter Register */ -#define IMXRT_TMR4_DMA1 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_DMA1_OFFSET) /* Timer Channel DMA Enable Register */ -#define IMXRT_TMR4_COMP12 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_COMP12_OFFSET) /* Timer Channel Compare Register 1 */ -#define IMXRT_TMR4_COMP22 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_COMP22_OFFSET) /* Timer Channel Compare Register 2 */ -#define IMXRT_TMR4_CAPT2 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_CAPT2_OFFSET) /* Timer Channel Capture Register */ -#define IMXRT_TMR4_LOAD2 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_LOAD2_OFFSET) /* Timer Channel Load Register */ -#define IMXRT_TMR4_HOLD2 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_HOLD2_OFFSET) /* Timer Channel Hold Register */ -#define IMXRT_TMR4_CNTR2 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_CNTR2_OFFSET) /* Timer Channel Counter Register */ -#define IMXRT_TMR4_CTRL2 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_CTRL2_OFFSET) /* Timer Channel Control Register */ -#define IMXRT_TMR4_SCTRL2 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_SCTRL2_OFFSET) /* Timer Channel Status and Control Register */ -#define IMXRT_TMR4_CMPLD12 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_CMPLD12_OFFSET) /* Timer Channel Comparator Load Register 1 */ -#define IMXRT_TMR4_CMPLD22 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_CMPLD22_OFFSET) /* Timer Channel Comparator Load Register 2 */ -#define IMXRT_TMR4_CSCTRL2 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_CSCTRL2_OFFSET) /* Timer Channel Comparator Status and Control Register */ -#define IMXRT_TMR4_FILT2 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_FILT2_OFFSET) /* Timer Channel Input Filter Register */ -#define IMXRT_TMR4_DMA2 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_DMA2_OFFSET) /* Timer Channel DMA Enable Register */ -#define IMXRT_TMR4_COMP13 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_COMP13_OFFSET) /* Timer Channel Compare Register 1 */ -#define IMXRT_TMR4_COMP23 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_COMP23_OFFSET) /* Timer Channel Compare Register 2 */ -#define IMXRT_TMR4_CAPT3 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_CAPT3_OFFSET) /* Timer Channel Capture Register */ -#define IMXRT_TMR4_LOAD3 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_LOAD3_OFFSET) /* Timer Channel Load Register */ -#define IMXRT_TMR4_HOLD3 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_HOLD3_OFFSET) /* Timer Channel Hold Register */ -#define IMXRT_TMR4_CNTR3 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_CNTR3_OFFSET) /* Timer Channel Counter Register */ -#define IMXRT_TMR4_CTRL3 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_CTRL3_OFFSET) /* Timer Channel Control Register */ -#define IMXRT_TMR4_SCTRL3 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_SCTRL3_OFFSET) /* Timer Channel Status and Control Register */ -#define IMXRT_TMR4_CMPLD13 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_CMPLD13_OFFSET) /* Timer Channel Comparator Load Register 1 */ -#define IMXRT_TMR4_CMPLD23 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_CMPLD23_OFFSET) /* Timer Channel Comparator Load Register 2 */ -#define IMXRT_TMR4_CSCTRL3 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_CSCTRL3_OFFSET) /* Timer Channel Comparator Status and Control Register */ -#define IMXRT_TMR4_FILT3 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_FILT3_OFFSET) /* Timer Channel Input Filter Register */ -#define IMXRT_TMR4_DMA3 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_DMA3_OFFSET) /* Timer Channel DMA Enable Register */ - -/* Register Bit Definitions *****************************************************************************************************************/ - -/* Timer Channel Control Register */ - -#define TMR_CTRL_OUTMODE_SHIFT (0) /* Bits: 0-2 Output Mode */ -#define TMR_CTRL_OUTMODE_MASK (7 << TMR_CTRL_OUTMODE_SHIFT) -# define TMR_CTRL_OUTMODE(n) ((uint32_t)(n) << TMR_CTRL_OUTMODE_SHIFT) -# define TMR_CTRL_OUTMODE_ON (0 << TMR_CTRL_OUTMODE_SHIFT) /* Asserted while counter is active */ -# define TMR_CTRL_OUTMODE_CLEAR (1 << TMR_CTRL_OUTMODE_SHIFT) /* Clear OFLAG output on successful compare */ -# define TMR_CTRL_OUTMODE_SET (2 << TMR_CTRL_OUTMODE_SHIFT) /* Set OFLAG output on successful compare */ -# define TMR_CTRL_OUTMODE_TOGGLE (3 << TMR_CTRL_OUTMODE_SHIFT) /* Toggle OFLAG output on successful compare */ -# define TMR_CTRL_OUTMODE_TOG_ALT (4 << TMR_CTRL_OUTMODE_SHIFT) /* Toggle OFLAG output using alternating compare registers */ -# define TMR_CTRL_OUTMODE_SET_CLR (5 << TMR_CTRL_OUTMODE_SHIFT) /* Set on compare, cleared on secondary source input edge */ -# define TMR_CTRL_OUTMODE_SET_CLR_ROL (6 << TMR_CTRL_OUTMODE_SHIFT) /* Set on compare, cleared on counter rollover */ -# define TMR_CTRL_OUTMODE_GATED (7 << TMR_CTRL_OUTMODE_SHIFT) /* Enable gated clock output while counter is active */ -#define TMR_CTRL_COINIT (1 << 3) /* Bit: 3 Co-Channel Initialization */ -#define TMR_CTRL_DIR (1 << 4) /* Bit: 4 Count Direction */ -#define TMR_CTRL_LENGTH (1 << 5) /* Bit: 5 Count Length */ -#define TMR_CTRL_ONCE (1 << 6) /* Bit: 6 Count Once */ -#define TMR_CTRL_SCS_SHIFT (7) /* Bits: 7-8 Secondary Count Source */ -#define TMR_CTRL_SCS_MASK (3 << TMR_CTRL_SCS_SHIFT) -# define TMR_CTRL_SCS(n) ((uint32_t)(n) << TMR_CTRL_SCS_SHIFT) -# define TMR_CTRL_SCS_CNTR0 (0 << TMR_CTRL_SCS_SHIFT) /* Counter 0 input pin */ -# define TMR_CTRL_SCS_CNTR1 (1 << TMR_CTRL_SCS_SHIFT) /* Counter 1 input pin */ -# define TMR_CTRL_SCS_CNTR2 (2 << TMR_CTRL_SCS_SHIFT) /* Counter 2 input pin */ -# define TMR_CTRL_SCS_CNTR3 (3 << TMR_CTRL_SCS_SHIFT) /* Counter 3 input pin */ -#define TMR_CTRL_PCS_SHIFT (9) /* Bits: 9-12 Primary Count Source */ -#define TMR_CTRL_PCS_MASK (15 << TMR_CTRL_PCS_SHIFT) -# define TMR_CTRL_PCS(n) ((uint32_t)(n) << TMR_CTRL_PCS_SHIFT) -# define TMR_CTRL_PCS_CNTR0 (0 << TMR_CTRL_PCS_SHIFT) /* Counter 0 input pin */ -# define TMR_CTRL_PCS_CNTR1 (1 << TMR_CTRL_PCS_SHIFT) /* Counter 1 input pin */ -# define TMR_CTRL_PCS_CNTR2 (2 << TMR_CTRL_PCS_SHIFT) /* Counter 2 input pin */ -# define TMR_CTRL_PCS_CNTR3 (3 << TMR_CTRL_PCS_SHIFT) /* Counter 3 input pin */ -# define TMR_CTRL_PCS_OUT0 (4 << TMR_CTRL_PCS_SHIFT) /* Counter 0 output */ -# define TMR_CTRL_PCS_OUT1 (5 << TMR_CTRL_PCS_SHIFT) /* Counter 1 output */ -# define TMR_CTRL_PCS_OUT2 (6 << TMR_CTRL_PCS_SHIFT) /* Counter 2 output */ -# define TMR_CTRL_PCS_OUT3 (7 << TMR_CTRL_PCS_SHIFT) /* Counter 3 output */ -# define TMR_CTRL_PCS_DIV1 (8 << TMR_CTRL_PCS_SHIFT) /* IP bus clock divide by 1 prescaler */ -# define TMR_CTRL_PCS_DIV2 (9 << TMR_CTRL_PCS_SHIFT) /* IP bus clock divide by 2 prescaler */ -# define TMR_CTRL_PCS_DIV4 (10 << TMR_CTRL_PCS_SHIFT) /*IP bus clock divide by 4 prescaler */ -# define TMR_CTRL_PCS_DIV8 (11 << TMR_CTRL_PCS_SHIFT) /*IP bus clock divide by 8 prescaler */ -# define TMR_CTRL_PCS_DIV16 (12 << TMR_CTRL_PCS_SHIFT) /*IP bus clock divide by 16 prescaler */ -# define TMR_CTRL_PCS_DIV32 (13 << TMR_CTRL_PCS_SHIFT) /*IP bus clock divide by 32 prescaler */ -# define TMR_CTRL_PCS_DIV64 (14 << TMR_CTRL_PCS_SHIFT) /*IP bus clock divide by 64 prescaler */ -# define TMR_CTRL_PCS_DIV128 (15 << TMR_CTRL_PCS_SHIFT) /*IP bus clock divide by 128 prescaler */ -#define TMR_CTRL_CM_SHIFT (13) /* Bits: 13-15 Count Mode */ -#define TMR_CTRL_CM_MASK (7 << TMR_CTRL_CM_SHIFT) -# define TMR_CTRL_CM(n) ((uint32_t)(n) << TMR_CTRL_CM_SHIFT) -# define TMR_CTRL_CM_MODE0 (0 << TMR_CTRL_CM_SHIFT) /* No operation */ -# define TMR_CTRL_CM_MODE1 (1 << TMR_CTRL_CM_SHIFT) /* Count rising edges of primary source */ -# define TMR_CTRL_CM_MODE2 (2 << TMR_CTRL_CM_SHIFT) /* Count rising and falling edges of primary source */ -# define TMR_CTRL_CM_MODE3 (3 << TMR_CTRL_CM_SHIFT) /* Count rising edges of primary source while secondary input high active */ -# define TMR_CTRL_CM_MODE4 (4 << TMR_CTRL_CM_SHIFT) /* Quadrature count mode, uses primary and secondary sources */ -# define TMR_CTRL_CM_MODE5 (5 << TMR_CTRL_CM_SHIFT) /* Count rising edges of primary source; secondary source specifies direction */ -# define TMR_CTRL_CM_MODE6 (6 << TMR_CTRL_CM_SHIFT) /* Edge of secondary source triggers primary count until compare */ -# define TMR_CTRL_CM_MODE7 (7 << TMR_CTRL_CM_SHIFT) /* Cascaded counter mode (up/down)*/ - -/* Timer Channel Status and Control Register */ - -#define TMR_SCTRL_OEN (1 << 0) /* Bit: 0 Output Enable */ -#define TMR_SCTRL_OPS (1 << 1) /* Bit: 1 Output Polarity Select */ -#define TMR_SCTRL_FORCE (1 << 2) /* Bit: 2 Force OFLAG Output */ -#define TMR_SCTRL_VAL (1 << 3) /* Bit: 3 Forced OFLAG Value */ -#define TMR_SCTRL_EEOF (1 << 4) /* Bit: 4 Enable External OFLAG Force */ -#define TMR_SCTRL_MSTR (1 << 5) /* Bit: 5 Master Mode */ -#define TMR_SCTRL_CAPTURE_MODE_SHIFT (6) /* Bits: 6-7 Input Capture Mode */ -#define TMR_SCTRL_CAPTURE_MODE_MASK (3 << TMR_SCTRL_CAPTURE_MODE_SHIFT) -# define TMR_SCTRL_CAPTURE_MODE(n) ((uint32_t)(n) << TMR_SCTRL_CAPTURE_MODE_SHIFT) -# define TMR_SCTRL_CAPTURE_DIS (0 << TMR_SCTRL_CAPTURE_MODE_SHIFT) /* Capture function is disabled */ -# define TMR_SCTRL_CAPTURE_RISING (1 << TMR_SCTRL_CAPTURE_MODE_SHIFT) /* Load capture register on rising edge (when IPS=0) or falling edge (when IPS=1) of input */ -# define TMR_SCTRL_CAPTURE_FALLING (2 << TMR_SCTRL_CAPTURE_MODE_SHIFT) /* Load capture register on falling edge (when IPS=0) or rising edge (when IPS=1) of input */ -# define TMR_SCTRL_CAPTURE_BOTH (3 << TMR_SCTRL_CAPTURE_MODE_SHIFT) /* Load capture register on both edges of input */ -#define TMR_SCTRL_INPUT (1 << 8) /* Bit: 8 External Input Signal */ -#define TMR_SCTRL_IPS (1 << 9) /* Bit: 9 Input Polarity Select */ -#define TMR_SCTRL_IEFIE (1 << 10) /* Bit: 10 Input Edge Flag Interrupt Enable */ -#define TMR_SCTRL_IEF (1 << 11) /* Bit: 11 Input Edge Flag */ -#define TMR_SCTRL_TOFIE (1 << 12) /* Bit: 12 Timer Overflow Flag Interrupt Enable */ -#define TMR_SCTRL_TOF (1 << 13) /* Bit: 13 Timer Overflow Flag */ -#define TMR_SCTRL_TCFIE (1 << 14) /* Bit: 14 Timer Compare Flag Interrupt Enable */ -#define TMR_SCTRL_TCF (1 << 15) /* Bit: 15 Timer Compare Flag */ - -/* Timer Channel Comparator Status and Control Register */ - -#define TMR_CSCTRL_CL1_SHIFT (0) /* Bits: 0-1 Compare Load Control 1 */ -#define TMR_CSCTRL_CL1_MASK (3 << TMR_CSCTRL_CL1_SHIFT) -# define TMR_CSCTRL_CL1(n) ((uint32_t)(n) << TMR_CSCTRL_CL1_SHIFT) -# define TMR_CSCTRL_CL1_DIS (0 << TMR_CSCTRL_CL1_SHIFT) /* Never preload */ -# define TMR_CSCTRL_CL1_COMP1 (1 << TMR_CSCTRL_CL1_SHIFT) /* Load upon successful compare with the value in COMP1 */ -# define TMR_CSCTRL_CL1_COMP2 (2 << TMR_CSCTRL_CL1_SHIFT) /* Load upon successful compare with the value in COMP2 */ -#define TMR_CSCTRL_CL2_SHIFT (2) /* Bits: 2-3 Compare Load Control 2 */ -#define TMR_CSCTRL_CL2_MASK (3 << TMR_CSCTRL_CL2_SHIFT) -# define TMR_CSCTRL_CL2(n) ((uint32_t)(n) << TMR_CSCTRL_CL2_SHIFT) -# define TMR_CSCTRL_CL2_DIS (0 << TMR_CSCTRL_CL2_SHIFT) /* Never preload */ -# define TMR_CSCTRL_CL2_COMP1 (1 << TMR_CSCTRL_CL2_SHIFT) /* Load upon successful compare with the value in COMP1 */ -# define TMR_CSCTRL_CL2_COMP2 (2 << TMR_CSCTRL_CL2_SHIFT) /* Load upon successful compare with the value in COMP2 */ -#define TMR_CSCTRL_TCF1 (1 << 4) /* Bit: 4 Timer Compare 1 Interrupt Flag */ -#define TMR_CSCTRL_TCF2 (1 << 5) /* Bit: 5 Timer Compare 2 Interrupt Flag */ -#define TMR_CSCTRL_TCF1EN (1 << 6) /* Bit: 6 Timer Compare 1 Interrupt Enable */ -#define TMR_CSCTRL_TCF2EN (1 << 7) /* Bit: 7 Timer Compare 2 Interrupt Enable */ - /* Bit: 8 This field is reserved. */ -#define TMR_CSCTRL_UP (1 << 9) /* Bit: 9 Counting Direction Indicator */ -#define TMR_CSCTRL_TCI (1 << 10) /* Bit: 10 Triggered Count Initialization Control */ -#define TMR_CSCTRL_ROC (1 << 11) /* Bit: 11 Reload on Capture */ -#define TMR_CSCTRL_ALT_LOAD (1 << 12) /* Bit: 12 Alternative Load Enable */ -#define TMR_CSCTRL_FAULT (1 << 13) /* Bit: 13 Fault Enable */ -#define TMR_CSCTRL_DBG_EN_SHIFT (14) /* Bits: 14-15 Debug Actions Enable */ -#define TMR_CSCTRL_DBG_EN_MASK (3 << TMR_CSCTRL_DBG_EN_SHIFT) -# define TMR_CSCTRL_DBG_EN(n) ((uint32_t)(n) << TMR_CSCTRL_DBG_EN_SHIFT) -# define TMR_CSCTRL_DBG_EN_NORMAL (0 << TMR_CSCTRL_DBG_EN_SHIFT) /* Continue with normal operation during debug mode. (default) */ -# define TMR_CSCTRL_DBG_EN_HALT (1 << TMR_CSCTRL_DBG_EN_SHIFT) /* Halt TMR counter during debug mode. */ -# define TMR_CSCTRL_DBG_EN_FORCE (2 << TMR_CSCTRL_DBG_EN_SHIFT) /* Force TMR output to logic 0 (prior to consideration of SCTRL[OPS]). */ -# define TMR_CSCTRL_DBG_EN_HALT_FORCE (3 << TMR_CSCTRL_DBG_EN_SHIFT) /* Both halt counter and force output to 0 during debug mode.*/ - -/* Timer Channel Input Filter Register */ - -#define TMR_FILT_FILT_PER_SHIFT (0) /* Bits: 0-7 Input Filter Sample Period */ -#define TMR_FILT_FILT_PER_MASK (0xff << TMR_FILT_FILT_PER_SHIFT) -# define TMR_FILT_FILT_PER(n) ((uint32_t)(n) << TMR_FILT_FILT_PER_SHIFT) -#define TMR_FILT_FILT_CNT_SHIFT (8) /* Bits: 8-10 Input Filter Sample Count */ -#define TMR_FILT_FILT_CNT_MASK (7 << TMR_FILT_FILT_CNT_SHIFT) -# define TMR_FILT_FILT_CNT(n) ((uint32_t)(n) << TMR_FILT_FILT_CNT_SHIFT) -# define TMR_FILT_FILT_CNT_3 (0 << TMR_FILT_FILT_CNT_SHIFT) /* These bits represent the number of consecutive */ -# define TMR_FILT_FILT_CNT_4 (1 << TMR_FILT_FILT_CNT_SHIFT) /* samples that must agree prior to the input */ -# define TMR_FILT_FILT_CNT_5 (2 << TMR_FILT_FILT_CNT_SHIFT) /* filter accepting an input transition. A value */ -# define TMR_FILT_FILT_CNT_6 (3 << TMR_FILT_FILT_CNT_SHIFT) /* of 0x0 represents 3 samples. A value of 0x7 */ -# define TMR_FILT_FILT_CNT_7 (4 << TMR_FILT_FILT_CNT_SHIFT) /* represents 10 samples. The value */ -# define TMR_FILT_FILT_CNT_8 (5 << TMR_FILT_FILT_CNT_SHIFT) /* of FILT_CNT affects the input latency. */ -# define TMR_FILT_FILT_CNT_9 (6 << TMR_FILT_FILT_CNT_SHIFT) -# define TMR_FILT_FILT_CNT_10 (7 << TMR_FILT_FILT_CNT_SHIFT) - /* Bits: 11-15 Reserved */ - -/* Timer Channel DMA Enable Register */ - -#define TMR_DMA_IEFDE (1 << 0) /* Bit: 0 Input Edge Flag DMA Enable */ -#define TMR_DMA_CMPLD1DE (1 << 1) /* Bit: 1 Comparator Preload Register 1 DMA Enable */ -#define TMR_DMA_CMPLD2DE (1 << 2) /* Bit: 2 Comparator Preload Register 2 DMA Enable */ - /* Bits: 3-15 Reserved */ - -/* Timer Channel Enable Register */ - -#define TMR_ENBL_ENBL_SHIFT (0) /* Bits: 0-3 Timer Channel Enable */ -#define TMR_ENBL_ENBL_MASK (15 << TMR_ENBL_ENBL_SHIFT) -# define TMR_ENBL_ENBL(n) ((uint32_t)(n) << TMR_ENBL_ENBL_SHIFT) -# define TMR_ENBL_CHN0 (1 << TMR_ENBL_ENBL_SHIFT) /* Channel 0 enable */ -# define TMR_ENBL_CHN1 (2 << TMR_ENBL_ENBL_SHIFT) /* Channel 1 enable */ -# define TMR_ENBL_CHN3 (4 << TMR_ENBL_ENBL_SHIFT) /* Channel 2 enable */ -# define TMR_ENBL_CHN4 (8 << TMR_ENBL_ENBL_SHIFT) /* Channel 3 enable */ - /* Bits: 4-15 Reserved */ - -#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_TMR_H */ diff --git a/arch/arm/src/imxrt/chip/imxrt_usb_analog.h b/arch/arm/src/imxrt/chip/imxrt_usb_analog.h deleted file mode 100644 index a7ca8f96cd5..00000000000 --- a/arch/arm/src/imxrt/chip/imxrt_usb_analog.h +++ /dev/null @@ -1,209 +0,0 @@ -/************************************************************************************************************************************ - * arch/arm/src/imxrt/chip/imxrt_usb_analog.h - * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * David Sidrane - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_USB_ANALOG_H -#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_USB_ANALOG_H - -/************************************************************************************************************************************ - * Included Files - ************************************************************************************************************************************/ - -#include -#include "chip/imxrt_memorymap.h" - -/************************************************************************************************************************************ - * Pre-processor Definitions - ************************************************************************************************************************************/ - -/* Register Offsets *****************************************************************************************************************/ - -#define IMXRT_USB_ANALOG_USB1_VBUS_DETECT_OFFSET 0x01a0 /* USB VBUS Detect Register */ -#define IMXRT_USB_ANALOG_USB1_VBUS_DETECT_SET_OFFSET 0x01a4 /* USB VBUS Detect Set Register */ -#define IMXRT_USB_ANALOG_USB1_VBUS_DETECT_CLR_OFFSET 0x01a8 /* USB VBUS Detect Clear Register */ -#define IMXRT_USB_ANALOG_USB1_VBUS_DETECT_TOG_OFFSET 0x01ac /* USB VBUS Detect Toggle Register */ -#define IMXRT_USB_ANALOG_USB1_CHRG_DETECT_OFFSET 0x01b0 /* USB Charger Detect Register */ -#define IMXRT_USB_ANALOG_USB1_CHRG_DETECT_SET_OFFSET 0x01b4 /* USB Charger Detect Set Register */ -#define IMXRT_USB_ANALOG_USB1_CHRG_DETECT_CLR_OFFSET 0x01b8 /* USB Charger Detect Clear Register */ -#define IMXRT_USB_ANALOG_USB1_CHRG_DETECT_TOG_OFFSET 0x01bc /* USB Charger Detect Toggle Register */ -#define IMXRT_USB_ANALOG_USB1_VBUS_DETECT_STAT_OFFSET 0x01c0 /* USB VBUS Detect Status Register */ -#define IMXRT_USB_ANALOG_USB1_CHRG_DETECT_STAT_OFFSET 0x01d0 /* USB Charger Detect Status Register */ -#define IMXRT_USB_ANALOG_USB1_MISC_OFFSET 0x01f0 /* USB Misc Register */ -#define IMXRT_USB_ANALOG_USB1_MISC_SET_OFFSET 0x01f4 /* USB Misc Set Register */ -#define IMXRT_USB_ANALOG_USB1_MISC_CLR_OFFSET 0x01f8 /* USB Misc Clear Register */ -#define IMXRT_USB_ANALOG_USB1_MISC_TOG_OFFSET 0x01fc /* USB Misc Toggle Register */ -#define IMXRT_USB_ANALOG_USB2_VBUS_DETECT_OFFSET 0x0200 /* USB VBUS Detect Register */ -#define IMXRT_USB_ANALOG_USB2_VBUS_DETECT_SET_OFFSET 0x0204 /* USB VBUS Detect Set Register */ -#define IMXRT_USB_ANALOG_USB2_VBUS_DETECT_CLR_OFFSET 0x0208 /* USB VBUS Detect Clear Register */ -#define IMXRT_USB_ANALOG_USB2_VBUS_DETECT_TOG_OFFSET 0x020c /* USB VBUS Detect Toggle Register */ -#define IMXRT_USB_ANALOG_USB2_CHRG_DETECT_OFFSET 0x0210 /* USB Charger Detect Register */ -#define IMXRT_USB_ANALOG_USB2_CHRG_DETECT_SET_OFFSET 0x0214 /* USB Charger Detect Set Register */ -#define IMXRT_USB_ANALOG_USB2_CHRG_DETECT_CLR_OFFSET 0x0218 /* USB Charger Detect Clear Register */ -#define IMXRT_USB_ANALOG_USB2_CHRG_DETECT_TOG_OFFSET 0x021c /* USB Charger Detect Toggle Register */ -#define IMXRT_USB_ANALOG_USB2_VBUS_DETECT_STAT_OFFSET 0x0220 /* USB VBUS Detect Status Register */ -#define IMXRT_USB_ANALOG_USB2_CHRG_DETECT_STAT_OFFSET 0x0230 /* USB Charger Detect Status Register */ -#define IMXRT_USB_ANALOG_USB2_MISC_OFFSET 0x0250 /* USB Misc Register */ -#define IMXRT_USB_ANALOG_USB2_MISC_SET_OFFSET 0x0254 /* USB Misc Set Register */ -#define IMXRT_USB_ANALOG_USB2_MISC_CLR_OFFSET 0x0258 /* USB Misc Clear Register */ -#define IMXRT_USB_ANALOG_USB2_MISC_TOG_OFFSET 0x025c /* USB Misc Toggle Register */ -#define IMXRT_USB_ANALOG_DIGPROG_OFFSET 0x0260 /* Chip Silicon Version */ - -/* Register addresses ***********************************************************************************************************************/ - -/* Analog USB1 Register Addresses */ - -#define IMXRT_USB_ANALOG_USB1_VBUS_DETECT (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_VBUS_DETECT_OFFSET) /* USB_ANALOG1 USB VBUS Detect Register */ -#define IMXRT_USB_ANALOG_USB1_VBUS_DETECT_SET (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_VBUS_DETECT_SET_OFFSET) /* USB_ANALOG1 USB VBUS Detect Set Register */ -#define IMXRT_USB_ANALOG_USB1_VBUS_DETECT_CLR (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_VBUS_DETECT_CLR_OFFSET) /* USB_ANALOG1 USB VBUS Detect Clear Register */ -#define IMXRT_USB_ANALOG_USB1_VBUS_DETECT_TOG (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_VBUS_DETECT_TOG_OFFSET) /* USB_ANALOG1 USB VBUS Detect Toggle Register */ -#define IMXRT_USB_ANALOG_USB1_CHRG_DETECT (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_CHRG_DETECT_OFFSET) /* USB_ANALOG1 USB Charger Detect Register */ -#define IMXRT_USB_ANALOG_USB1_CHRG_DETECT_SET (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_CHRG_DETECT_SET_OFFSET) /* USB_ANALOG1 USB Charger Detect Set Register */ -#define IMXRT_USB_ANALOG_USB1_CHRG_DETECT_CLR (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_CHRG_DETECT_CLR_OFFSET) /* USB_ANALOG1 USB Charger Detect Clear Register */ -#define IMXRT_USB_ANALOG_USB1_CHRG_DETECT_TOG (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_CHRG_DETECT_TOG_OFFSET) /* USB_ANALOG1 USB Charger Detect Toggle Register */ -#define IMXRT_USB_ANALOG_USB1_VBUS_DETECT_STAT (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_VBUS_DETECT_STAT_OFFSET) /* USB_ANALOG1 USB VBUS Detect Status Register */ -#define IMXRT_USB_ANALOG_USB1_CHRG_DETECT_STAT (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_CHRG_DETECT_STAT_OFFSET) /* USB_ANALOG1 USB Charger Detect Status Register */ -#define IMXRT_USB_ANALOG_USB1_MISC (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_MISC_OFFSET) /* USB_ANALOG1 USB Misc Register */ -#define IMXRT_USB_ANALOG_USB1_MISC_SET (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_MISC_SET_OFFSET) /* USB_ANALOG1 USB Misc Set Register */ -#define IMXRT_USB_ANALOG_USB1_MISC_CLR (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_MISC_CLR_OFFSET) /* USB_ANALOG1 USB Misc Clear Register */ -#define IMXRT_USB_ANALOG_USB1_MISC_TOG (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_MISC_TOG_OFFSET) /* USB_ANALOG1 USB Misc Toggle Register */ -#define IMXRT_USB_ANALOG_USB2_VBUS_DETECT (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_VBUS_DETECT_OFFSET) /* USB_ANALOG1 USB VBUS Detect Register */ -#define IMXRT_USB_ANALOG_USB2_VBUS_DETECT_SET (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_VBUS_DETECT_SET_OFFSET) /* USB_ANALOG1 USB VBUS Detect Set Register */ -#define IMXRT_USB_ANALOG_USB2_VBUS_DETECT_CLR (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_VBUS_DETECT_CLR_OFFSET) /* USB_ANALOG1 USB VBUS Detect Clear Register */ -#define IMXRT_USB_ANALOG_USB2_VBUS_DETECT_TOG (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_VBUS_DETECT_TOG_OFFSET) /* USB_ANALOG1 USB VBUS Detect Toggle Register */ -#define IMXRT_USB_ANALOG_USB2_CHRG_DETECT (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_CHRG_DETECT_OFFSET) /* USB_ANALOG1 USB Charger Detect Register */ -#define IMXRT_USB_ANALOG_USB2_CHRG_DETECT_SET (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_CHRG_DETECT_SET_OFFSET) /* USB_ANALOG1 USB Charger Detect Set Register */ -#define IMXRT_USB_ANALOG_USB2_CHRG_DETECT_CLR (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_CHRG_DETECT_CLR_OFFSET) /* USB_ANALOG1 USB Charger Detect Clear Register */ -#define IMXRT_USB_ANALOG_USB2_CHRG_DETECT_TOG (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_CHRG_DETECT_TOG_OFFSET) /* USB_ANALOG1 USB Charger Detect Toggle Register */ -#define IMXRT_USB_ANALOG_USB2_VBUS_DETECT_STAT (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_VBUS_DETECT_STAT_OFFSET) /* USB_ANALOG1 USB VBUS Detect Status Register */ -#define IMXRT_USB_ANALOG_USB2_CHRG_DETECT_STAT (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_CHRG_DETECT_STAT_OFFSET) /* USB_ANALOG1 USB Charger Detect Status Register */ -#define IMXRT_USB_ANALOG_USB2_MISC (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_MISC_OFFSET) /* USB_ANALOG1 USB Misc Register */ -#define IMXRT_USB_ANALOG_USB2_MISC_SET (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_MISC_SET_OFFSET) /* USB_ANALOG1 USB Misc Set Register */ -#define IMXRT_USB_ANALOG_USB2_MISC_CLR (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_MISC_CLR_OFFSET) /* USB_ANALOG1 USB Misc Clear Register */ -#define IMXRT_USB_ANALOG_USB2_MISC_TOG (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_MISC_TOG_OFFSET) /* USB_ANALOG1 USB Misc Toggle Register */ -#define IMXRT_USB_ANALOG_DIGPROG (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_DIGPROG_OFFSET) /* USB_ANALOG1 Chip Silicon Version */ - -/* Analog USB2 Register Addresses */ - -#define IMXRT_USB_ANALOG_USB1_VBUS_DETECT (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_VBUS_DETECT_OFFSET) /* USB_ANALOG2 USB VBUS Detect Register */ -#define IMXRT_USB_ANALOG_USB1_VBUS_DETECT_SET (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_VBUS_DETECT_SET_OFFSET) /* USB_ANALOG2 USB VBUS Detect Set Register */ -#define IMXRT_USB_ANALOG_USB1_VBUS_DETECT_CLR (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_VBUS_DETECT_CLR_OFFSET) /* USB_ANALOG2 USB VBUS Detect Clear Register */ -#define IMXRT_USB_ANALOG_USB1_VBUS_DETECT_TOG (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_VBUS_DETECT_TOG_OFFSET) /* USB_ANALOG2 USB VBUS Detect Toggle Register */ -#define IMXRT_USB_ANALOG_USB1_CHRG_DETECT (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_CHRG_DETECT_OFFSET) /* USB_ANALOG2 USB Charger Detect Register */ -#define IMXRT_USB_ANALOG_USB1_CHRG_DETECT_SET (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_CHRG_DETECT_SET_OFFSET) /* USB_ANALOG2 USB Charger Detect Set Register */ -#define IMXRT_USB_ANALOG_USB1_CHRG_DETECT_CLR (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_CHRG_DETECT_CLR_OFFSET) /* USB_ANALOG2 USB Charger Detect Clear Register */ -#define IMXRT_USB_ANALOG_USB1_CHRG_DETECT_TOG (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_CHRG_DETECT_TOG_OFFSET) /* USB_ANALOG2 USB Charger Detect Toggle Register */ -#define IMXRT_USB_ANALOG_USB1_VBUS_DETECT_STAT (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_VBUS_DETECT_STAT_OFFSET) /* USB_ANALOG2 USB VBUS Detect Status Register */ -#define IMXRT_USB_ANALOG_USB1_CHRG_DETECT_STAT (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_CHRG_DETECT_STAT_OFFSET) /* USB_ANALOG2 USB Charger Detect Status Register */ -#define IMXRT_USB_ANALOG_USB1_MISC (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_MISC_OFFSET) /* USB_ANALOG2 USB Misc Register */ -#define IMXRT_USB_ANALOG_USB1_MISC_SET (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_MISC_SET_OFFSET) /* USB_ANALOG2 USB Misc Set Register */ -#define IMXRT_USB_ANALOG_USB1_MISC_CLR (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_MISC_CLR_OFFSET) /* USB_ANALOG2 USB Misc Clear Register */ -#define IMXRT_USB_ANALOG_USB1_MISC_TOG (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB1_MISC_TOG_OFFSET) /* USB_ANALOG2 USB Misc Toggle Register */ -#define IMXRT_USB_ANALOG_USB2_VBUS_DETECT (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_VBUS_DETECT_OFFSET) /* USB_ANALOG2 USB VBUS Detect Register */ -#define IMXRT_USB_ANALOG_USB2_VBUS_DETECT_SET (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_VBUS_DETECT_SET_OFFSET) /* USB_ANALOG2 USB VBUS Detect Set Register */ -#define IMXRT_USB_ANALOG_USB2_VBUS_DETECT_CLR (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_VBUS_DETECT_CLR_OFFSET) /* USB_ANALOG2 USB VBUS Detect Clear Register */ -#define IMXRT_USB_ANALOG_USB2_VBUS_DETECT_TOG (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_VBUS_DETECT_TOG_OFFSET) /* USB_ANALOG2 USB VBUS Detect Toggle Register */ -#define IMXRT_USB_ANALOG_USB2_CHRG_DETECT (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_CHRG_DETECT_OFFSET) /* USB_ANALOG2 USB Charger Detect Register */ -#define IMXRT_USB_ANALOG_USB2_CHRG_DETECT_SET (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_CHRG_DETECT_SET_OFFSET) /* USB_ANALOG2 USB Charger Detect Set Register */ -#define IMXRT_USB_ANALOG_USB2_CHRG_DETECT_CLR (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_CHRG_DETECT_CLR_OFFSET) /* USB_ANALOG2 USB Charger Detect Clear Register */ -#define IMXRT_USB_ANALOG_USB2_CHRG_DETECT_TOG (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_CHRG_DETECT_TOG_OFFSET) /* USB_ANALOG2 USB Charger Detect Toggle Register */ -#define IMXRT_USB_ANALOG_USB2_VBUS_DETECT_STAT (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_VBUS_DETECT_STAT_OFFSET) /* USB_ANALOG2 USB VBUS Detect Status Register */ -#define IMXRT_USB_ANALOG_USB2_CHRG_DETECT_STAT (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_CHRG_DETECT_STAT_OFFSET) /* USB_ANALOG2 USB Charger Detect Status Register */ -#define IMXRT_USB_ANALOG_USB2_MISC (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_MISC_OFFSET) /* USB_ANALOG2 USB Misc Register */ -#define IMXRT_USB_ANALOG_USB2_MISC_SET (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_MISC_SET_OFFSET) /* USB_ANALOG2 USB Misc Set Register */ -#define IMXRT_USB_ANALOG_USB2_MISC_CLR (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_MISC_CLR_OFFSET) /* USB_ANALOG2 USB Misc Clear Register */ -#define IMXRT_USB_ANALOG_USB2_MISC_TOG (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_MISC_TOG_OFFSET) /* USB_ANALOG2 USB Misc Toggle Register */ -#define IMXRT_USB_ANALOG_DIGPROG (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_DIGPROG_OFFSET) /* USB_ANALOG2 Chip Silicon Version */ - -/* Register Bit Definitions *********************************************************************************************************/ - -/* USB VBUS Detect Register */ - -#define USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0) /* Bits: 0-2 Set the threshold for the VBUSVALID comparator. */ -#define USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_MASK (7 << USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_SHIFT) -# define USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH(n) ((uint32_t)(n) << USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_SHIFT) -# define USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_4V0 (0 << USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_SHIFT) /* 4V0 — 4.0V */ -# define USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_4V1 (1 << USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_SHIFT) /* 4V1 — 4.1V */ -# define USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_4V2 (2 << USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_SHIFT) /* 4V2 — 4.2V */ -# define USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_4V3 (3 << USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_SHIFT) /* 4V3 — 4.3V */ -# define USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_4V4 (4 << USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_SHIFT) /* 4V4 — 4.4V (default) */ -# define USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_4V5 (5 << USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_SHIFT) /* 4V5 — 4.5V */ -# define USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_4V6 (6 << USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_SHIFT) /* 4V6 — 4.6V */ -# define USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_4V7 (7 << USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_SHIFT) /* 4V7 — 4.7V */ - /* Bits: 3-19 Reserved */ -#define USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_PWRUP_CMPS (1 << 20) /* Bit: 20 Powers up comparators for vbus_valid detector. */ - /* Bits: 21-25 Reserved */ -#define USB_ANALOG_USB_VBUS_DETECT_DISCHARGE_VBUS (1 << 26) /* Bit: 26 USB OTG discharge VBUS. */ -#define USB_ANALOG_USB_VBUS_DETECT_CHARGE_VBUS (1 << 27) /* Bit: 27 USB OTG charge VBUS. */ - /* Bits: 28-31 Reserved */ - -/* USB Charger Detect Register */ - - /* Bits: 0-17 Reserved */ -#define USB_ANALOG_USB_CHRG_DETECT_CHK_CONTACT (1 << 18) /* Bit: 18 Check the contact of USB plug */ -#define USB_ANALOG_USB_CHRG_DETECT_CHK_CHRG_B (1 << 19) /* Bit: 19 Check the charger connection */ -#define USB_ANALOG_USB_CHRG_DETECT_EN_B (1 << 20) /* Bit: 20 Control the charger detector. */ - /* Bits: 21-22 Reserved */ - /* Bit: 23 Reserved */ - /* Bits: 24-31 Reserved */ - -/* USB VBUS Detect Status Register */ - -#define USB_ANALOG_USB_VBUS_DETECT_STAT_SESSEND (1 << 0) /* Bit: 0 Session End for USB OTG. */ -#define USB_ANALOG_USB_VBUS_DETECT_STAT_BVALID (1 << 1) /* Bit: 1 Indicates VBus is valid for a B-peripheral. */ -#define USB_ANALOG_USB_VBUS_DETECT_STAT_AVALID (1 << 2) /* Bit: 2 Indicates VBus is valid for a A-peripheral. */ -#define USB_ANALOG_USB_VBUS_DETECT_STAT_VBUS_VALID (1 << 3) /* Bit: 3 VBus valid for USB OTG. */ - /* Bits: 4-31 Reserved */ - -/* USB Charger Detect Status Register */ - -#define USB_ANALOG_USB_CHRG_DETECT_STAT_PLUG_CONTACT (1 << 0) /* Bit: 0 State of the USB plug contact detector. */ -#define USB_ANALOG_USB_CHRG_DETECT_STAT_CHRG_ (1 << 1) /* Bit: 1 DETECTED */ -#define USB_ANALOG_USB_CHRG_DETECT_STAT_DM_STATE (1 << 2) /* Bit: 2 DM line state output of the charger detector. */ -#define USB_ANALOG_USB_CHRG_DETECT_STAT_DP_STATE (1 << 3) /* Bit: 3 DP line state output of the charger detector. */ - /* Bits: 4-31 Reserved */ - -/* USB Misc Register */ - -#define USB_ANALOG_USB_MISC_HS_USE_EXTERNAL_R (1 << 0) /* Bit: 0 Use external resistor to generate the current bias for the high speed transmitter. */ -#define USB_ANALOG_USB_MISC_EN_DEGLITCH (1 << 1) /* Bit: 1 Enable the deglitching circuit of the USB PLL output. */ - /* Bits: 2-29 Reserved */ -#define USB_ANALOG_USB_MISC_EN_CLK_UTMI (1 << 30) /* Bit: 30 Enables the clk to the UTMI block. */ - /* Bit: 31 Reserved */ - -/* Chip Silicon Version */ - -#define USB_ANALOG_DIGPROG_SILICON_REVISION 0x006C0000 /* Silicon revision 1.0 */ - -#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_USB_ANALOG_H */ diff --git a/arch/arm/src/imxrt/chip/imxrt_usdhc.h b/arch/arm/src/imxrt/chip/imxrt_usdhc.h deleted file mode 100644 index 9cc10b997c0..00000000000 --- a/arch/arm/src/imxrt/chip/imxrt_usdhc.h +++ /dev/null @@ -1,555 +0,0 @@ -/************************************************************************************ - * arch/arm/src/imxrt/chip/imxrt_usdhc.h - * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt & Contributors - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_USDHC_H -#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_USDHC_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register Offsets *****************************************************************/ - -#define IMXRT_USDHC_DSADDR_OFFSET 0x0000 /* DMA System Address Register */ -#define IMXRT_USDHC_BLKATTR_OFFSET 0x0004 /* Block Attributes Register */ -#define IMXRT_USDHC_CMDARG_OFFSET 0x0008 /* Command Argument Register */ -#define IMXRT_USDHC_XFERTYP_OFFSET 0x000c /* Transfer Type Register */ -#define IMXRT_USDHC_CMDRSP0_OFFSET 0x0010 /* Command Response 0 */ -#define IMXRT_USDHC_CMDRSP1_OFFSET 0x0014 /* Command Response 1 */ -#define IMXRT_USDHC_CMDRSP2_OFFSET 0x0018 /* Command Response 2 */ -#define IMXRT_USDHC_CMDRSP3_OFFSET 0x001c /* Command Response 3 */ -#define IMXRT_USDHC_DATPORT_OFFSET 0x0020 /* Buffer Data Port Register */ -#define IMXRT_USDHC_PRSSTAT_OFFSET 0x0024 /* Present State Register */ -#define IMXRT_USDHC_PROCTL_OFFSET 0x0028 /* Protocol Control Register */ -#define IMXRT_USDHC_SYSCTL_OFFSET 0x002c /* System Control Register */ -#define IMXRT_USDHC_IRQSTAT_OFFSET 0x0030 /* Interrupt Status Register */ -#define IMXRT_USDHC_IRQSTATEN_OFFSET 0x0034 /* Interrupt Status Enable Register */ -#define IMXRT_USDHC_IRQSIGEN_OFFSET 0x0038 /* Interrupt Signal Enable Register */ -#define IMXRT_USDHC_AC12ERR_OFFSET 0x003c /* Auto CMD12 Error Status Register */ -#define IMXRT_USDHC_HTCAPBLT_OFFSET 0x0040 /* Host Controller Capabilities */ -#define IMXRT_USDHC_WML_OFFSET 0x0044 /* Watermark Level Register */ -#define IMXRT_USDHC_MIX_OFFSET 0x0048 /* Mixer Control Register */ -#define IMXRT_USDHC_FEVT_OFFSET 0x0050 /* Force Event Register */ -#define IMXRT_USDHC_ADMAES_OFFSET 0x0054 /* ADMA Error Status Register */ -#define IMXRT_USDHC_ADSADDR_OFFSET 0x0058 /* ADMA System Address Register */ -#define IMXRT_USDHC_DLL_CONTROL_OFFSET 0x0060 /* DLL Control Register */ -#define IMXRT_USDHC_DLL_STATUS_OFFSET 0x0064 /* DLL Status Register */ -#define IMXRT_USDHC_CLK_TUNE_CTRL_OFFSET 0x0068 /* Clock turing control Register */ -#define IMXRT_USDHC_VENDOR_OFFSET 0x00c0 /* Vendor Specific Register */ -#define IMXRT_USDHC_MMCBOOT_OFFSET 0x00c4 /* MMC Boot Register */ -#define IMXRT_USDHC_VENDOR2_OFFSET 0x00c8 /* Vendor 2 Register */ -#define IMXRT_USDHC_TC_OFFSET 0x00cc /* Tuning Control Register */ - -/* Register Addresses ***************************************************************/ - -/* For USDHC1 ... */ - -#define IMXRT_USDHC1_DSADDR (IMXRT_USDHC1_BASE + IMXRT_USDHC_DSADDR_OFFSET) -#define IMXRT_USDHC1_BLKATTR (IMXRT_USDHC1_BASE + IMXRT_USDHC_BLKATTR_OFFSET) -#define IMXRT_USDHC1_CMDARG (IMXRT_USDHC1_BASE + IMXRT_USDHC_CMDARG_OFFSET) -#define IMXRT_USDHC1_XFERTYP (IMXRT_USDHC1_BASE + IMXRT_USDHC_XFERTYP_OFFSET) -#define IMXRT_USDHC1_CMDRSP0 (IMXRT_USDHC1_BASE + IMXRT_USDHC_CMDRSP0_OFFSET) -#define IMXRT_USDHC1_CMDRSP1 (IMXRT_USDHC1_BASE + IMXRT_USDHC_CMDRSP1_OFFSET) -#define IMXRT_USDHC1_CMDRSP2 (IMXRT_USDHC1_BASE + IMXRT_USDHC_CMDRSP2_OFFSET) -#define IMXRT_USDHC1_CMDRSP3 (IMXRT_USDHC1_BASE + IMXRT_USDHC_CMDRSP3_OFFSET) -#define IMXRT_USDHC1_DATPORT (IMXRT_USDHC1_BASE + IMXRT_USDHC_DATPORT_OFFSET) -#define IMXRT_USDHC1_PRSSTAT (IMXRT_USDHC1_BASE + IMXRT_USDHC_PRSSTAT_OFFSET) -#define IMXRT_USDHC1_PROCTL (IMXRT_USDHC1_BASE + IMXRT_USDHC_PROCTL_OFFSET) -#define IMXRT_USDHC1_SYSCTL (IMXRT_USDHC1_BASE + IMXRT_USDHC_SYSCTL_OFFSET) -#define IMXRT_USDHC1_IRQSTAT (IMXRT_USDHC1_BASE + IMXRT_USDHC_IRQSTAT_OFFSET) -#define IMXRT_USDHC1_IRQSTATEN (IMXRT_USDHC1_BASE + IMXRT_USDHC_IRQSTATEN_OFFSET) -#define IMXRT_USDHC1_IRQSIGEN (IMXRT_USDHC1_BASE + IMXRT_USDHC_IRQSIGEN_OFFSET) -#define IMXRT_USDHC1_AC12ERR (IMXRT_USDHC1_BASE + IMXRT_USDHC_AC12ERR_OFFSET) -#define IMXRT_USDHC1_HTCAPBLT (IMXRT_USDHC1_BASE + IMXRT_USDHC_HTCAPBLT_OFFSET) -#define IMXRT_USDHC1_WML (IMXRT_USDHC1_BASE + IMXRT_USDHC_WML_OFFSET) -#define IMXRT_USDHC1_MIX (IMXRT_USDHC1_BASE + IMXRT_USDHC_MIX_OFFSET) -#define IMXRT_USDHC1_FEVT (IMXRT_USDHC1_BASE + IMXRT_USDHC_FEVT_OFFSET) -#define IMXRT_USDHC1_ADMAES (IMXRT_USDHC1_BASE + IMXRT_USDHC_ADMAES_OFFSET) -#define IMXRT_USDHC1_ADSADDR (IMXRT_USDHC1_BASE + IMXRT_USDHC_ADSADDR_OFFSET) -#define IMXRT_USDHC_DLL_CONTROL (IMXRT_USDHC1_BASE + IMXRT_USDHC_DLL_CONTROL_OFFSET) -#define IMXRT_USDHC_DLL_STATUS (IMXRT_USDHC1_BASE + IMXRT_USDHC_DLL_STATUS) -#define IMXRT_USDHC_CLK_TUNE_CTRL (IMXRT_USDHC1_BASE + IMXRT_USDHC_CLK_TUNE_CTRL) -#define IMXRT_USDHC1_VENDOR (IMXRT_USDHC1_BASE + IMXRT_USDHC_VENDOR_OFFSET) -#define IMXRT_USDHC1_MMCBOOT (IMXRT_USDHC1_BASE + IMXRT_USDHC_MMCBOOT_OFFSET) -#define IMXRT_USDHC1_VENDOR2 (IMXRT_USDHC1_BASE + IMXRT_USDHC_VENDOR2_OFFSET) -#define IMXRT_USDHC1_TC (IMXRT_USDHC1_BASE + IMXRT_USDHC_TC_OFFSET) - -/* For USDHC2 ... */ - -#define IMXRT_USDHC2_DSADDR (IMXRT_USDHC2_BASE + IMXRT_USDHC_DSADDR_OFFSET) -#define IMXRT_USDHC2_BLKATTR (IMXRT_USDHC2_BASE + IMXRT_USDHC_BLKATTR_OFFSET) -#define IMXRT_USDHC2_CMDARG (IMXRT_USDHC2_BASE + IMXRT_USDHC_CMDARG_OFFSET) -#define IMXRT_USDHC2_XFERTYP (IMXRT_USDHC2_BASE + IMXRT_USDHC_XFERTYP_OFFSET) -#define IMXRT_USDHC2_CMDRSP0 (IMXRT_USDHC2_BASE + IMXRT_USDHC_CMDRSP0_OFFSET) -#define IMXRT_USDHC2_CMDRSP1 (IMXRT_USDHC2_BASE + IMXRT_USDHC_CMDRSP1_OFFSET) -#define IMXRT_USDHC2_CMDRSP2 (IMXRT_USDHC2_BASE + IMXRT_USDHC_CMDRSP2_OFFSET) -#define IMXRT_USDHC2_CMDRSP3 (IMXRT_USDHC2_BASE + IMXRT_USDHC_CMDRSP3_OFFSET) -#define IMXRT_USDHC2_DATPORT (IMXRT_USDHC2_BASE + IMXRT_USDHC_DATPORT_OFFSET) -#define IMXRT_USDHC2_PRSSTAT (IMXRT_USDHC2_BASE + IMXRT_USDHC_PRSSTAT_OFFSET) -#define IMXRT_USDHC2_PROCTL (IMXRT_USDHC2_BASE + IMXRT_USDHC_PROCTL_OFFSET) -#define IMXRT_USDHC2_SYSCTL (IMXRT_USDHC2_BASE + IMXRT_USDHC_SYSCTL_OFFSET) -#define IMXRT_USDHC2_IRQSTAT (IMXRT_USDHC2_BASE + IMXRT_USDHC_IRQSTAT_OFFSET) -#define IMXRT_USDHC2_IRQSTATEN (IMXRT_USDHC2_BASE + IMXRT_USDHC_IRQSTATEN_OFFSET) -#define IMXRT_USDHC2_IRQSIGEN (IMXRT_USDHC2_BASE + IMXRT_USDHC_IRQSIGEN_OFFSET) -#define IMXRT_USDHC2_AC12ERR (IMXRT_USDHC2_BASE + IMXRT_USDHC_AC12ERR_OFFSET) -#define IMXRT_USDHC2_HTCAPBLT (IMXRT_USDHC2_BASE + IMXRT_USDHC_HTCAPBLT_OFFSET) -#define IMXRT_USDHC2_WML (IMXRT_USDHC2_BASE + IMXRT_USDHC_WML_OFFSET) -#define IMXRT_USDHC2_FEVT (IMXRT_USDHC2_BASE + IMXRT_USDHC_FEVT_OFFSET) -#define IMXRT_USDHC2_ADMAES (IMXRT_USDHC2_BASE + IMXRT_USDHC_ADMAES_OFFSET) -#define IMXRT_USDHC2_ADSADDR (IMXRT_USDHC2_BASE + IMXRT_USDHC_ADSADDR_OFFSET) -#define IMXRT_USDHC2_DLL_CONTROL (IMXRT_USDHC2_BASE + IMXRT_USDHC_DLL_CONTROL_OFFSET) -#define IMXRT_USDHC2_DLL_STATUS (IMXRT_USDHC2_BASE + IMXRT_USDHC_DLL_STATUS) -#define IMXRT_USSDHC_CLK_TUNE_CTRL (IMXRT_USDHC2_BASE + IMXRT_USDHC_CLK_TUNE_CTRL) -#define IMXRT_USDHC2_VENDOR (IMXRT_USDHC2_BASE + IMXRT_USDHC_VENDOR_OFFSET) -#define IMXRT_USDHC2_MMCBOOT (IMXRT_USDHC2_BASE + IMXRT_USDHC_MMCBOOT_OFFSET) -#define IMXRT_USDHC2_VENDOR2 (IMXRT_USDHC2_BASE + IMXRT_USDHC_VENDOR2_OFFSET) -#define IMXRT_USDHC2_TC (IMXRT_USDHC2_BASE + IMXRT_USDHC_TC_OFFSET) - -/* Register Bit Definitions *********************************************************/ - -/* DMA System Address Register */ - -#define USDHC_DSADDR_SHIFT (0) /* Bits 2-31: DMA System Address */ -#define USDHC_DSADDR_MASK (0xfffffffc) /* Bits 0-1: 32 bit aligned, low bits Reserved */ - -/* Block Attributes Register */ - -#define USDHC_BLKATTR_SIZE_SHIFT (0) /* Bits 0-12: Transfer Block Size */ -#define USDHC_BLKATTR_SIZE_MASK (0x1fff << USDHC_BLKATTR_SIZE_SHIFT) -# define USDHC_BLKATTR_SIZE(n) ((n) << USDHC_BLKATTR_SIZE_SHIFT) - /* Bits 13-15: Reserved */ -#define USDHC_BLKATTR_CNT_SHIFT (16) /* Bits 16-31: Blocks Count For Current Transfer */ -#define USDHC_BLKATTR_CNT_MASK (0xffff << USDHC_BLKATTR_CNT_SHIFT) -# define USDHC_BLKATTR_CNT(n) ((n) << USDHC_BLKATTR_CNT_SHIFT) - -/* Command Argument Register (32-bit cmd/arg data) */ - -/* Transfer Type Register */ - - /* Bits 0-15: Reserved */ -#define USDHC_XFERTYP_RSPTYP_SHIFT (16) /* Bits 16-17: Response Type Select */ -#define USDHC_XFERTYP_RSPTYP_MASK (3 << USDHC_XFERTYP_RSPTYP_SHIFT) -# define USDHC_XFERTYP_RSPTYP_NONE (0 << USDHC_XFERTYP_RSPTYP_SHIFT) /* No response */ -# define USDHC_XFERTYP_RSPTYP_LEN136 (1 << USDHC_XFERTYP_RSPTYP_SHIFT) /* Response length 136 */ -# define USDHC_XFERTYP_RSPTYP_LEN48 (2 << USDHC_XFERTYP_RSPTYP_SHIFT) /* Response length 48 */ -# define USDHC_XFERTYP_RSPTYP_LEN48BSY (3 << USDHC_XFERTYP_RSPTYP_SHIFT) /* Response length 48, check busy */ - /* Bit 18: Reserved */ -#define USDHC_XFERTYP_CCCEN (1 << 19) /* Bit 19: Command CRC Check Enable */ -#define USDHC_XFERTYP_CICEN (1 << 20) /* Bit 20: Command Index Check Enable */ -#define USDHC_XFERTYP_DPSEL (1 << 21) /* Bit 21: Data Present Select */ -#define USDHC_XFERTYP_CMDTYP_SHIFT (22) /* Bits 22-23: Command Type */ -#define USDHC_XFERTYP_CMDTYP_MASK (3 << USDHC_XFERTYP_CMDTYP_SHIFT) -# define USDHC_XFERTYP_CMDTYP_NORMAL (0 << USDHC_XFERTYP_CMDTYP_SHIFT) /* Normal other commands */ -# define USDHC_XFERTYP_CMDTYP_SUSPEND (1 << USDHC_XFERTYP_CMDTYP_SHIFT) /* Suspend CMD52 for writing bus suspend in CCCR */ -# define USDHC_XFERTYP_CMDTYP_RESUME (2 << USDHC_XFERTYP_CMDTYP_SHIFT) /* Resume CMD52 for writing function select in CCCR */ -# define USDHC_XFERTYP_CMDTYP_ABORT (3 << USDHC_XFERTYP_CMDTYP_SHIFT) /* Abort CMD12, CMD52 for writing I/O abort in CCCR */ -#define USDHC_XFERTYP_CMDINX_SHIFT (24) /* Bits 24-29: Command Index */ -#define USDHC_XFERTYP_CMDINX_MASK (0x3f << USDHC_XFERTYP_CMDINX_SHIFT) - /* Bits 30-31: Reserved */ - -/* Command Response 0-3 (32-bit response data) */ - -/* Buffer Data Port Register (32-bit data content) */ - -/* Present State Register */ - -#define USDHC_PRSSTAT_CIHB (1 << 0) /* Bit 0: Command Inhibit (CMD) */ -#define USDHC_PRSSTAT_CDIHB (1 << 1) /* Bit 1: Command Inhibit (DAT) */ -#define USDHC_PRSSTAT_DLA (1 << 2) /* Bit 2: Data Line Active */ -#define USDHC_PRSSTAT_SDSTB (1 << 3) /* Bit 3: SD Clock Stable */ -#define USDHC_PRSSTAT_IPGOFF (1 << 4) /* Bit 4: Bus Clock */ -#define USDHC_PRSSTAT_HCKOFF (1 << 5) /* Bit 5: System Clock */ -#define USDHC_PRSSTAT_PEROFF (1 << 6) /* Bit 6: USDHC clock */ -#define USDHC_PRSSTAT_SDOFF (1 << 7) /* Bit 7: SD Clock Gated Off Internally */ -#define USDHC_PRSSTAT_WTA (1 << 8) /* Bit 8: Write Transfer Active */ -#define USDHC_PRSSTAT_RTA (1 << 9) /* Bit 9: Read Transfer Active */ -#define USDHC_PRSSTAT_BWEN (1 << 10) /* Bit 10: Buffer Write Enable */ -#define USDHC_PRSSTAT_BREN (1 << 11) /* Bit 11: Buffer Read Enable */ -#define USDHC_PRSSTAT_RTR (1 << 12) /* Bit 12: Retuning request */ - /* Bits 13-14: Reserved */ -#define USDHC_PRSSTAT_TSCD (1 << 15) /* Bit 15: Tape Select Change Done */ -#define USDHC_PRSSTAT_CINS (1 << 16) /* Bit 16: Card Inserted */ - /* Bit 17: Reserved */ -#define USDHC_PRSSTAT_CDPL (1 << 18) /* Bit 18: Card Detect Pin Level */ -#define USDHC_PRSSTAT_WPSPL (1 << 19) /* Bit 19: Write Protect Switch Pin Level */ - /* Bits 20-22: Reserved */ -#define USDHC_PRSSTAT_CLSL (1 << 23) /* Bit 23: CMD Line Signal Level */ -#define USDHC_PRSSTAT_DLSL_SHIFT (24) /* Bits 24-31: DAT Line Signal Level */ -#define USDHC_PRSSTAT_DLSL_MASK (0xff << USDHC_PRSSTAT_DLSL_SHIFT) -# define USDHC_PRSSTAT_DLSL_DAT0 (0x01 << USDHC_PRSSTAT_DLSL_SHIFT) -# define USDHC_PRSSTAT_DLSL_DAT1 (0x02 << USDHC_PRSSTAT_DLSL_SHIFT) -# define USDHC_PRSSTAT_DLSL_DAT2 (0x04 << USDHC_PRSSTAT_DLSL_SHIFT) -# define USDHC_PRSSTAT_DLSL_DAT3 (0x08 << USDHC_PRSSTAT_DLSL_SHIFT) -# define USDHC_PRSSTAT_DLSL_DAT4 (0x10 << USDHC_PRSSTAT_DLSL_SHIFT) -# define USDHC_PRSSTAT_DLSL_DAT5 (0x20 << USDHC_PRSSTAT_DLSL_SHIFT) -# define USDHC_PRSSTAT_DLSL_DAT6 (0x40 << USDHC_PRSSTAT_DLSL_SHIFT) -# define USDHC_PRSSTAT_DLSL_DAT7 (0x80 << USDHC_PRSSTAT_DLSL_SHIFT) - -/* Protocol Control Register */ - -#define USDHC_PROCTL_LCTL (1 << 0) /* Bit 0: LED Control */ -#define USDHC_PROCTL_DTW_SHIFT (1) /* Bits 1-2: Data Transfer Width */ -#define USDHC_PROCTL_DTW_MASK (3 << USDHC_PROCTL_DTW_SHIFT) -# define USDHC_PROCTL_DTW_1BIT (0 << USDHC_PROCTL_DTW_SHIFT) /* 1-bit mode */ -# define USDHC_PROCTL_DTW_4BIT (1 << USDHC_PROCTL_DTW_SHIFT) /* 4-bit mode */ -# define USDHC_PROCTL_DTW_8BIT (2 << USDHC_PROCTL_DTW_SHIFT) /* 8-bit mode */ -#define USDHC_PROCTL_D3CD (1 << 3) /* Bit 3: DAT3 as Card Detection Pin */ -#define USDHC_PROCTL_EMODE_SHIFT (4) /* Bits 4-5: Endian mode */ -#define USDHC_PROCTL_EMODE_MASK (3 << USDHC_PROCTL_EMODE_SHIFT) -# define USDHC_PROCTL_EMODE_BE (0 << USDHC_PROCTL_EMODE_SHIFT) /* Big endian mode */ -# define USDHC_PROCTL_EMODE_HWBE (1 << USDHC_PROCTL_EMODE_SHIFT) /* Half word big endian mode */ -# define USDHC_PROCTL_EMODE_LE (2 << USDHC_PROCTL_EMODE_SHIFT) /* Little endian mode */ -#define USDHC_PROCTL_CDTL (1 << 6) /* Bit 6: Card Detect Test Level */ -#define USDHC_PROCTL_CDSS (1 << 7) /* Bit 7: Card Detect Signal Selection */ -#define USDHC_PROCTL_DMAS_SHIFT (8) /* Bits 8-9: DMA Select */ -#define USDHC_PROCTL_DMAS_MASK (3 << USDHC_PROCTL_DMAS_SHIFT) -# define USDHC_PROCTL_DMAS_NODMA (0 << USDHC_PROCTL_DMAS_SHIFT) /* No DMA or simple DMA is selected */ -# define USDHC_PROCTL_DMAS_ADMA1 (1 << USDHC_PROCTL_DMAS_SHIFT) /* ADMA1 is selected */ -# define USDHC_PROCTL_DMAS_ADMA2 (2 << USDHC_PROCTL_DMAS_SHIFT) /* ADMA2 is selected */ - /* Bits 10-15: Reserved */ -#define USDHC_PROCTL_SABGREQ (1 << 16) /* Bit 16: Stop At Block Gap Request */ -#define USDHC_PROCTL_CREQ (1 << 17) /* Bit 17: Continue Request */ -#define USDHC_PROCTL_RWCTL (1 << 18) /* Bit 18: Read Wait Control */ -#define USDHC_PROCTL_IABG (1 << 19) /* Bit 19: Interrupt At Block Gap */ -#define USDHC_PROCTL_RDDONENO8CLK (1 << 20) /* Bit 20: Read done to 8 clock */ -#define USDHC_PROCTL_RESV2023 (4 << 21) /* Bits 21-23: Reserved, write as 0x100 */ -#define USDHC_PROCTL_WECINT (1 << 24) /* Bit 24: Wakeup Event Enable On Card Interrupt */ -#define USDHC_PROCTL_WECINS (1 << 25) /* Bit 25: Wakeup Event Enable On SD Card Insertion */ -#define USDHC_PROCTL_WECRM (1 << 26) /* Bit 26: Wakeup Event Enable On SD Card Removal */ -#define USDHC_PROCTL_BURST_SHIFT (27) /* Bits 27-29: Burst Length */ -#define USDHC_PROCTL_BURST_MASK (7 << USDHC_PROCTL_BUSRT_SHIFT) -# define USDHC_PROCTL_BURST_INCR (1 << USDHC_PROCTL_BURST_SHIFT) /* Burst for Incr */ -# define USDHC_PROCTL_BURST_4816 (2 << USDHC_PROCTL_BURST_SHIFT) /* Burst for 4/8/16 */ -# define USDHC_PROCTL_BURST_4W8W16W (4 << USDHC_PROCTL_BURST_SHIFT) /* Burst for 4w/8w/16w */ -#define USDHC_PROTCTL_NEBLKRD (1 << 30) /* Bit 30: Non-exect block read */ - /* Bit 31: Reserved */ -/* System Control Register */ - -#define USDHC_SYSCTL_RES0 (0x0F << 0) /* Bit 0-3: Reserved, set to 1 */ -#define USDHC_SYSCTL_DVS_SHIFT (4) /* Bits 4-7: Divisor */ -#define USDHC_SYSCTL_DVS_MASK (0x0f << USDHC_SYSCTL_DVS_SHIFT) -# define USDHC_SYSCTL_DVS_DIV(n) (((n) - 1) << USDHC_SYSCTL_DVS_SHIFT) /* Divide by n, n=1..16 */ -#define USDHC_SYSCTL_SDCLKFS_SHIFT (8) /* Bits 8-15: SDCLK Frequency Select */ -#define USDHC_SYSCTL_SDCLKFS_MASK (0xff << USDHC_SYSCTL_SDCLKFS_SHIFT) -# define USDHC_SYSCTL_SDCLKFS_BYPASS (0x00 << USDHC_SYSCTL_SDCLKFS_SHIFT) /* Bypass the prescaler */ -# define USDHC_SYSCTL_SDCLKFS_DIV2 (0x01 << USDHC_SYSCTL_SDCLKFS_SHIFT) /* Base clock / 2 */ -# define USDHC_SYSCTL_SDCLKFS_DIV4 (0x02 << USDHC_SYSCTL_SDCLKFS_SHIFT) /* Base clock / 4 */ -# define USDHC_SYSCTL_SDCLKFS_DIV8 (0x04 << USDHC_SYSCTL_SDCLKFS_SHIFT) /* Base clock / 8 */ -# define USDHC_SYSCTL_SDCLKFS_DIV16 (0x08 << USDHC_SYSCTL_SDCLKFS_SHIFT) /* Base clock / 16 */ -# define USDHC_SYSCTL_SDCLKFS_DIV32 (0x10 << USDHC_SYSCTL_SDCLKFS_SHIFT) /* Base clock / 32 */ -# define USDHC_SYSCTL_SDCLKFS_DIV64 (0x20 << USDHC_SYSCTL_SDCLKFS_SHIFT) /* Base clock / 64 */ -# define USDHC_SYSCTL_SDCLKFS_DIV128 (0x40 << USDHC_SYSCTL_SDCLKFS_SHIFT) /* Base clock / 128 */ -# define USDHC_SYSCTL_SDCLKFS_DIV256 (0x80 << USDHC_SYSCTL_SDCLKFS_SHIFT) /* Base clock / 256 */ -#define USDHC_SYSCTL_DTOCV_SHIFT (16) /* Bits 16-19: Data Timeout Counter Value */ -#define USDHC_SYSCTL_DTOCV_MASK (0x0f << USDHC_SYSCTL_DTOCV_SHIFT) -# define USDHC_SYSCTL_DTOCV_MUL(n) (((n) - 213) << USDHC_SYSCTL_DTOCV_SHIFT) /* SDCLK x n, n=213..227 */ - /* Bits 20-22: Reserved */ -#define USDHC_SYSCTL_IPPRSTN (1 << 23) /* Bit 23: Card /reset (default 1) */ -#define USDHC_SYSCTL_RSTA (1 << 24) /* Bit 24: Software Reset For ALL */ -#define USDHC_SYSCTL_RSTC (1 << 25) /* Bit 25: Software Reset For CMD Line */ -#define USDHC_SYSCTL_RSTD (1 << 26) /* Bit 26: Software Reset For DAT Line */ -#define USDHC_SYSCTL_INITA (1 << 27) /* Bit 27: Initialization Active */ -#define USDHC_SYSCTL_RSTT (1 << 28) /* Bit 28: Reset tuning */ - /* Bits 29-31: Reserved */ - -/* Interrupt Status Register, Interrupt Status Enable Register and Interrupt Signal Enable Register - * Common interrupt bit definitions - */ - -#define USDHC_INT_CC (1 << 0) /* Bit 0: Command Complete */ -#define USDHC_INT_TC (1 << 1) /* Bit 1: Transfer Complete */ -#define USDHC_INT_BGE (1 << 2) /* Bit 2: Block Gap Event */ -#define USDHC_INT_DINT (1 << 3) /* Bit 3: DMA Interrupt */ -#define USDHC_INT_BWR (1 << 4) /* Bit 4: Buffer Write Ready */ -#define USDHC_INT_BRR (1 << 5) /* Bit 5: Buffer Read Ready */ -#define USDHC_INT_CINS (1 << 6) /* Bit 6: Card Insertion */ -#define USDHC_INT_CRM (1 << 7) /* Bit 7: Card Removal */ -#define USDHC_INT_CINT (1 << 8) /* Bit 8: Card Interrupt */ - /* Bits 9-11: Reserved */ -#define USDHC_INT_RTR (1 << 12) /* Bit 12: Re-tuning event */ - /* Bit 13: Reserved */ -#define USDHC_INT_TP (1 << 14) /* Bit 14: Tuning pass */ - /* Bit 15: Reserved */ -#define USDHC_INT_CTOE (1 << 16) /* Bit 16: Command Timeout Error */ -#define USDHC_INT_CCE (1 << 17) /* Bit 17: Command CRC Error */ -#define USDHC_INT_CEBE (1 << 18) /* Bit 18: Command End Bit Error */ -#define USDHC_INT_CIE (1 << 19) /* Bit 19: Command Index Error */ -#define USDHC_INT_DTOE (1 << 20) /* Bit 20: Data Timeout Error */ -#define USDHC_INT_DCE (1 << 21) /* Bit 21: Data CRC Error */ -#define USDHC_INT_DEBE (1 << 22) /* Bit 22: Data End Bit Error */ - /* Bit 23: Reserved */ -#define USDHC_INT_AC12E (1 << 24) /* Bit 24: Auto CMD12 Error */ - /* Bit 25: Reserved */ -#define USDHC_INT_TNE (1 << 25) /* Bit 26: Tuning error */ - /* Bit 27: Reserved */ -#define USDHC_INT_DMAE (1 << 28) /* Bit 28: DMA Error */ - /* Bits 29-31: Reserved */ -#define USDHC_INT_ALL 0x117f01ff - -/* Auto CMD12 Error Status Register */ - -#define USDHC_AC12ERR_NE (1 << 0) /* Bit 0: Auto CMD12 Not Executed */ -#define USDHC_AC12ERR_TOE (1 << 1) /* Bit 1: Auto CMD12 Timeout Error */ -#define USDHC_AC12ERR_EBE (1 << 2) /* Bit 2: Auto CMD12 End Bit Error */ -#define USDHC_AC12ERR_CE (1 << 3) /* Bit 3: Auto CMD12 CRC Error */ -#define USDHC_AC12ERR_IE (1 << 4) /* Bit 4: Auto CMD12 Index Error */ - /* Bits 5-6: Reserved */ -#define USDHC_AC12ERR_CNI (1 << 7) /* Bit 7: Command Not Issued By Auto CMD12 Error */ - /* Bits 8-21: Reserved */ -#define USDHC_AC12ERR_EXECUTE_TUNING (1 << 22) /* Bit 22: Execute Tuning */ -#define USDHC_AC12ERR_SMP_CLK_SEL (1 << 23) /* Bit 23: Sample clock sel */ - /* Bits 24-31: Reserved */ - -/* Host Controller Capabilities */ - -#define USDHC_HTCAPBLT_SDR50 (1 << 0) /* Bit 0: SDR50 support indication */ -#define USDHC_HTCAPBLT_SDR104 (1 << 1) /* Bit 1: SDR104 support indication */ -#define USDHC_HTCAPBLT_DDR50 (1 << 2) /* Bit 2: DDR50 support indication */ - /* Bits 3-7: Reserved */ -#define USDHC_HTCAPBLT_TCR_SHIFT (8) /* Bits 8-11: Time count retuning */ -#define USDHC_HTCAPBLT_TCR_MASK (0xF << USDHC_HTCAPBLT_TCR_SHIFT) -# define USDHC_HTCAPBLT_TCR(n) ((n) << USDHC_HTCAPBLT_TCR_SHIFT) -#define USDHC_HTCAPBLT_USE_TUNING_SDR50 (1 << 13) /* Bit 13: Use tuning for SDR50 */ -#define USDHC_HTCAPBLT_RET_MODE_SHIFT (14) /* bit 14-15: Retuning mode */ -#define USDHC_HTCAPBLT_RET_MODE_MASK (3< - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_WDOG_H -#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_WDOG_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include -#include "chip/imxrt_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ - -#define IMXRT_WDOG_WCR_OFFSET 0x0000 /* Watchdog control register */ -#define IMXRT_WDOG_WSR_OFFSET 0x0002 /* Watchdog service register */ -#define IMXRT_WDOG_WRSR_OFFSET 0x0004 /* Watchdog reset status */ -#define IMXRT_WDOG_WICR_OFFSET 0x0006 /* Watchdog interrupt control */ -#define IMXRT_WDOG_WMCR_OFFSET 0x0008 /* Watchdog misc control */ - -#define IMXRT_RTWDOG_CS_OFFSET 0x0000 /* Watchdog control and status register */ -#define IMXRT_RTWDOG_CNT_OFFSET 0x0004 /* Watchdog counter register */ -#define IMXRT_RTWDOG_TOVAL_OFFSET 0x0008 /* Watchdog timeout value register */ -#define IMXRT_RTWDOG_WIN_OFFSET 0x000c /* Watchdog window register */ - -/* Register addresses ***************************************************************/ - -#define IMXRT_WDOG1_WCR (IMXRT_WDOG1_BASE + IMXRT_WDOG_WCR_OFFSET) -#define IMXRT_WDOG1_WSR (IMXRT_WDOG1_BASE + IMXRT_WDOG_WSR_OFFSET) -#define IMXRT_WDOG1_WRSR (IMXRT_WDOG1_BASE + IMXRT_WDOG_WRSR_OFFSET) -#define IMXRT_WDOG1_WICR (IMXRT_WDOG1_BASE + IMXRT_WDOG_WICR_OFFSET) -#define IMXRT_WDOG1_WMCR (IMXRT_WDOG1_BASE + IMXRT_WDOG_WMCR_OFFSET) - -#define IMXRT_WDOG2_WCR (IMXRT_WDOG2_BASE + IMXRT_WDOG_WCR_OFFSET) -#define IMXRT_WDOG2_WSR (IMXRT_WDOG2_BASE + IMXRT_WDOG_WSR_OFFSET) -#define IMXRT_WDOG2_WRSR (IMXRT_WDOG2_BASE + IMXRT_WDOG_WRSR_OFFSET) -#define IMXRT_WDOG2_WMCR (IMXRT_WDOG2_BASE + IMXRT_WDOG_WMCR_OFFSET) - -#define IMXRT_RTWDOG_CS (IMXRT_WDOG3_BASE + IMXRT_RTWDOG_CS_OFFSET) -#define IMXRT_RTWDOG_CNT (IMXRT_WDOG3_BASE + IMXRT_RTWDOG_CNT_OFFSET) -#define IMXRT_RTWDOG_TOVAL (IMXRT_WDOG3_BASE + IMXRT_RTWDOG_TOVAL_OFFSET) -#define IMXRT_RTWDOG_WIN (IMXRT_WDOG3_BASE + IMXRT_RTWDOG_WIN_OFFSET) - -/* Register bit definitions *********************************************************/ - -/* Watchdog control and status register */ - -#define WDOG_WCR_WDZST (1 << 0) /* Bit 0: Watchdog Low Power */ -#define WDOG_WCR_WDBG (1 << 1) /* Bit 1: Watchdog DEBUG Enable */ -#define WDOG_WCR_WDE (1 << 2) /* Bit 2: Watchdog Enable */ -#define WDOG_WCR_WDT (1 << 3) /* Bit 3: WDOG_B Time-out assertion */ -#define WDOG_WCR_SRS (1 << 4) /* Bit 4: Software Reset Signal */ -#define WDOG_WCR_WDA (1 << 5) /* Bit 5: WDOG_B assertion */ -#define WDOG_WCR_SRE (1 << 6) /* Bit 6: Software reset extension */ -#define WDOG_WCR_WDW (1 << 7) /* Bit 7: Watchdog Disable for Wait */ - -#define WDOG_WCR_WT_SHIFT (8) /* Bits 8-15: Watchdog time-out value */ -#define WDOG_WCR_WT_MASK (0xff << WDOG_WCR_WT_SHIFT) -# define WDOG_WCR_WT(n) ((uint16_t)((n)) << WDOG_WCR_WT_SHIFT) - -/* Watchdog reset status */ - -#define WDOG_WRSR_SFTW (1 << 0) /* Bit 0: Software Reset */ -#define WDOG_WRSR_TOUT (1 << 1) /* Bit 1: Timeout */ - /* Bits 2-3: reserved */ -#define WDOG_WRSR_POR (1 << 4) /* Bit 4: Power on reset */ - /* Bits 5-15: Reserved */ -/* Watchdog interrupt control */ - -#define WDOG_WICR_WICT_SHIFT (0) /* Bits 0-7: Watchdog Interrupt Count Time-out */ -#define WDOG_WICR_WICT_MASK (0xff << WDOG_WCR_WT_SHIFT) -# define WDOG_WICR_WICT(n) ((uint16_t)((n)) << WDOG_WICR_WICT_SHIFT) - /* Bits 8-13: Reserved */ -#define WDOG_WICR_WTIS (1 << 14) /* Bit 14: Watchdog Timer Interrupt Status */ -#define WDOG_WICR_WIE (1 << 15) /* Bit 15: Watchdog Timer Interrupt enable */ - -/* Watchdog misc control */ - -#define WDOG_WMCR_PDE (1 << 0) /* Bit 0: Power Down Enable */ - /* Bits 1-15: Reserved */ -/* RT Watchdog Control and Status Register */ - -#define RTWDOG_CS_STOP (1 << 0) /* Bit 0: Stop enable */ -#define RTWDOG_CS_WAIT (1 << 1) /* Bit 1: Wait enable */ -#define RTWDOG_CS_DBG (1 << 2) /* Bit 2: Debug Enable */ -#define RTWDOG_CS_TST_SHIFT (3) /* Bits 3-4: Enables the fast test mode */ -#define RTWDOG_CS_TST_MASK (0x03 << RTWDOG_CS_TST_SHIFT) -# define RTWDOG_CS_TST(n) ((uint32_t)((n)) << RTWDOG_CS_TST_SHIFT) -#define RTWDOG_CS_UPDATE (1 << 5) /* Bit 5: Update */ -#define RTWDOG_CS_INT (1 << 6) /* Bit 6: Interrupt */ -#define RTWDOG_CS_EN (1 << 7) /* Bit 7: Enable */ -#define RTWDOG_CS_CLK_SHIFT (8) /* Bits 8-9: Clock */ -#define RTWDOG_CS_CLK_MASK (0x03 << RTWDOG_CS_CLK_SHIFT) -# define RTWDOG_CS_CLK(n) ((uint32_t)((n)) << RTWDOG_CS_CLK_SHIFT) -#define RTWDOG_CS_RCS (1 << 10) /* Bit 10: Reconfiguration Success */ -#define RTWDOG_CS_ULK (1 << 11) /* Bit 11: Unlock status */ -#define RTWDOG_CS_PRES (1 << 12) /* Bit 12: Watchdog prescaler */ -#define RTWDOG_CS_CMD32EN (1 << 13) /* Bit 13: WDOG support for 32-bit */ -#define RTWDOG_CS_FLG (1 << 14) /* Bit 14: Interrupt Flag */ -#define RTWDOG_CS_WIN (1 << 15) /* Bit 15: Watchdog Window */ - -#define RTWDOG_UPDATE_KEY (0xd928c520) -#define RTWDOG_REFRESH_KEY (0xb480a602) - -#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_WDOG_H */ diff --git a/arch/arm/src/imxrt/chip/imxrt_xbar.h b/arch/arm/src/imxrt/chip/imxrt_xbar.h deleted file mode 100644 index 47bab85828b..00000000000 --- a/arch/arm/src/imxrt/chip/imxrt_xbar.h +++ /dev/null @@ -1,74 +0,0 @@ -/************************************************************************************ - * arch/arm/src/imxrt/chip/imxrt_abar.h - * - * Copyright (C) 2019 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * David Sidrane - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_XBAR_H -#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_XBAR_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include -#include -#include "chip/imxrt_memorymap.h" - -#if defined(CONFIG_ARCH_FAMILY_IMXRT102x) -# include "chip/rt102x/imxrt102x_xbar.h" -#elif defined(CONFIG_ARCH_FAMILY_IMXRT105x) -# include "chip/rt105x/imxrt105x_xbar.h" -#elif defined(CONFIG_ARCH_FAMILY_IMXRT106x) -# include "chip/rt106x/imxrt106x_xbar.h" -#else -# error Unrecognized i.MX RT architecture -#endif - - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -#define IMXRT_SEL_PER_REG 2 - -#define IMXRT_SEL0_SHIFTS 0 /* Bits 0-6: Input (XBARA_INn) to be muxed to - * XBARA_OUTm */ -#define IMXRT_SEL0_MASK (0x7f << IMXRT_SEL0_SHIFTS) - /* Bit 7: Reserved */ -#define IMXRT_SEL1_SHIFTS 8 /* Bits 8-14: Input (XBARA_INn) to be muxed to - * XBARA_OUTm */ -#define IMXRT_SEL1_MASK (0x7f << IMXRT_SEL1_SHIFTS) - /* Bit 15 Reserved */ - -#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_XBAR_H */ diff --git a/arch/arm/src/imxrt/chip/rt102x/imxrt102x_ccm.h b/arch/arm/src/imxrt/chip/rt102x/imxrt102x_ccm.h deleted file mode 100644 index 0c1c27e64ff..00000000000 --- a/arch/arm/src/imxrt/chip/rt102x/imxrt102x_ccm.h +++ /dev/null @@ -1,970 +0,0 @@ -/***************************************************************************** - * arch/arm/src/imxrt/chip/rt102x/imxrt102x_ccm.h - * - * Copyright (C) 2018-2019 Gregory Nutt. All rights reserved. - * Authors: Janne Rosberg - * David Sidrane - * Dave Marples - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_CCM_H -#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_CCM_H - -/***************************************************************************** - * Included Files - *****************************************************************************/ - -#include -#include "chip/imxrt_memorymap.h" - -/***************************************************************************** - * Pre-processor Definitions - *****************************************************************************/ - -/* Register offsets **********************************************************/ - -#define IMXRT_CCM_CCR_OFFSET 0x0000 /* CCM Control Register */ - /* 0x0004 Reserved */ -#define IMXRT_CCM_CSR_OFFSET 0x0008 /* CCM Status Register */ -#define IMXRT_CCM_CCSR_OFFSET 0x000c /* CCM Clock Switcher Register */ -#define IMXRT_CCM_CACRR_OFFSET 0x0010 /* CCM Arm Clock Root Register */ -#define IMXRT_CCM_CBCDR_OFFSET 0x0014 /* CCM Bus Clock Divider Register */ -#define IMXRT_CCM_CBCMR_OFFSET 0x0018 /* CCM Bus Clock Multiplexer Register */ -#define IMXRT_CCM_CSCMR1_OFFSET 0x001c /* CCM Serial Clock Multiplexer Register 1 */ -#define IMXRT_CCM_CSCMR2_OFFSET 0x0020 /* CCM Serial Clock Multiplexer Register 2 */ -#define IMXRT_CCM_CSCDR1_OFFSET 0x0024 /* CCM Serial Clock Divider Register 1 */ -#define IMXRT_CCM_CS1CDR_OFFSET 0x0028 /* CCM Clock Divider Register */ -#define IMXRT_CCM_CS2CDR_OFFSET 0x002c /* CCM Clock Divider Register */ -#define IMXRT_CCM_CDCDR_OFFSET 0x0030 /* CCM D1 Clock Divider Register */ - /* 0x0034 Reserved */ -#define IMXRT_CCM_CSCDR2_OFFSET 0x0038 /* CCM Serial Clock Divider Register 2 */ -#define IMXRT_CCM_CSCDR3_OFFSET 0x003c /* CCM Serial Clock Divider Register 3 */ - /* 0x0040 Reserved */ - /* 0x0044 Reserved */ -#define IMXRT_CCM_CDHIPR_OFFSET 0x0048 /* CCM Divider Handshake In-Process Register */ - /* 0x004c Reserved */ - /* 0x0050 Reserved */ -#define IMXRT_CCM_CLPCR_OFFSET 0x0054 /* CCM Low Power Control Register */ - -#define IMXRT_CCM_CISR_OFFSET 0x0058 /* CCM Interrupt Status Register */ -#define IMXRT_CCM_CIMR_OFFSET 0x005c /* CCM Interrupt Mask Register */ -#define IMXRT_CCM_CCOSR_OFFSET 0x0060 /* CCM Clock Output Source Register */ -#define IMXRT_CCM_CGPR_OFFSET 0x0064 /* CCM General Purpose Register */ -#define IMXRT_CCM_CCGR0_OFFSET 0x0068 /* CCM Clock Gating Register 0 */ -#define IMXRT_CCM_CCGR1_OFFSET 0x006c /* CCM Clock Gating Register 1 */ -#define IMXRT_CCM_CCGR2_OFFSET 0x0070 /* CCM Clock Gating Register 2 */ -#define IMXRT_CCM_CCGR3_OFFSET 0x0074 /* CCM Clock Gating Register 3 */ -#define IMXRT_CCM_CCGR4_OFFSET 0x0078 /* CCM Clock Gating Register 4 */ -#define IMXRT_CCM_CCGR5_OFFSET 0x007c /* CCM Clock Gating Register 5 */ -#define IMXRT_CCM_CCGR6_OFFSET 0x0080 /* CCM Clock Gating Register 6 */ - /* 0x0084 Reserved */ -#define IMXRT_CCM_CMEOR_OFFSET 0x0088 /* CCM Module Enable Overide Register */ - -/* Analog */ - -#define IMXRT_CCM_ANALOG_PLL_USB1_OFFSET 0x0010 /* Analog USB1 480MHz PLL Control Register */ -#define IMXRT_CCM_ANALOG_PLL_SYS_OFFSET 0x0030 /* Analog System PLL Control Register */ -#define IMXRT_CCM_ANALOG_PLL_SYS_SS_OFFSET 0x0040 /* 528MHz System PLL Spread Spectrum Register */ -#define IMXRT_CCM_ANALOG_PLL_SYS_NUM_OFFSET 0x0050 /* Numerator of 528MHz System PLL Fractional Loop Divider */ -#define IMXRT_CCM_ANALOG_PLL_SYS_DENOM_OFFSET 0x0060 /* Denominator of 528MHz System PLL Fractional Loop Divider */ -#define IMXRT_CCM_ANALOG_PLL_AUDIO_OFFSET 0x0070 /* Analog Audio PLL control Register */ -#define IMXRT_CCM_ANALOG_PLL_AUDIO_NUM_OFFSET 0x0080 /* Numerator of Audio PLL Fractional Loop Divider */ -#define IMXRT_CCM_ANALOG_PLL_AUDIO_DENOM_OFFSET 0x0090 /* Denominator of Audio PLL Fractional Loop Divider */ -#define IMXRT_CCM_ANALOG_PLL_ENET_OFFSET 0x00e0 /* Analog ENET PLL Control Register */ -#define IMXRT_CCM_ANALOG_PFD_480_OFFSET 0x00f0 /* 480MHz Clock (PLL3) Phase Fractional Divider Control */ -#define IMXRT_CCM_ANALOG_PFD_528_OFFSET 0x0100 /* 528MHz Clock (PLL2) Phase Fractional Divider Control */ -#define IMXRT_CCM_ANALOG_MISC0_OFFSET 0x0150 /* Miscellaneous Register 0 */ -#define IMXRT_CCM_ANALOG_MISC1_OFFSET 0x0160 /* Miscellaneous Register 1 */ -#define IMXRT_CCM_ANALOG_MISC2_OFFSET 0x0170 /* Miscellaneous Register 2 */ - -/* Register addresses ********************************************************/ - -#define IMXRT_CCM_CCR (IMXRT_CCM_BASE + IMXRT_CCM_CCR_OFFSET) -#define IMXRT_CCM_CSR (IMXRT_CCM_BASE + IMXRT_CCM_CSR_OFFSET) -#define IMXRT_CCM_CCSR (IMXRT_CCM_BASE + IMXRT_CCM_CCSR_OFFSET) -#define IMXRT_CCM_CACRR (IMXRT_CCM_BASE + IMXRT_CCM_CACRR_OFFSET) -#define IMXRT_CCM_CBCDR (IMXRT_CCM_BASE + IMXRT_CCM_CBCDR_OFFSET) -#define IMXRT_CCM_CBCMR (IMXRT_CCM_BASE + IMXRT_CCM_CBCMR_OFFSET) -#define IMXRT_CCM_CSCMR1 (IMXRT_CCM_BASE + IMXRT_CCM_CSCMR1_OFFSET) -#define IMXRT_CCM_CSCMR2 (IMXRT_CCM_BASE + IMXRT_CCM_CSCMR2_OFFSET) -#define IMXRT_CCM_CSCDR1 (IMXRT_CCM_BASE + IMXRT_CCM_CSCDR1_OFFSET) -#define IMXRT_CCM_CS1CDR (IMXRT_CCM_BASE + IMXRT_CCM_CS1CDR_OFFSET) -#define IMXRT_CCM_CS2CDR (IMXRT_CCM_BASE + IMXRT_CCM_CS2CDR_OFFSET) -#define IMXRT_CCM_CDCDR (IMXRT_CCM_BASE + IMXRT_CCM_CDCDR_OFFSET) -#define IMXRT_CCM_CSCDR2 (IMXRT_CCM_BASE + IMXRT_CCM_CSCDR2_OFFSET) -#define IMXRT_CCM_CSCDR3 (IMXRT_CCM_BASE + IMXRT_CCM_CSCDR3_OFFSET) -#define IMXRT_CCM_CDHIPR (IMXRT_CCM_BASE + IMXRT_CCM_CDHIPR_OFFSET) -#define IMXRT_CCM_CLPCR (IMXRT_CCM_BASE + IMXRT_CCM_CLPCR_OFFSET) -#define IMXRT_CCM_CISR (IMXRT_CCM_BASE + IMXRT_CCM_CISR_OFFSET) -#define IMXRT_CCM_CIMR (IMXRT_CCM_BASE + IMXRT_CCM_CIMR_OFFSET) -#define IMXRT_CCM_CCOSR (IMXRT_CCM_BASE + IMXRT_CCM_CCOSR_OFFSET) -#define IMXRT_CCM_CGPR (IMXRT_CCM_BASE + IMXRT_CCM_CGPR_OFFSET) -#define IMXRT_CCM_CCGR0 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR0_OFFSET) -#define IMXRT_CCM_CCGR1 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR1_OFFSET) -#define IMXRT_CCM_CCGR2 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR2_OFFSET) -#define IMXRT_CCM_CCGR3 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR3_OFFSET) -#define IMXRT_CCM_CCGR4 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR4_OFFSET) -#define IMXRT_CCM_CCGR5 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR5_OFFSET) -#define IMXRT_CCM_CCGR6 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR6_OFFSET) -#define IMXRT_CCM_CMEOR (IMXRT_CCM_BASE + IMXRT_CCM_CMEOR_OFFSET) - -#define IMXRT_CCM_ANALOG_PLL_ARM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_ARM_OFFSET) -#define IMXRT_CCM_ANALOG_PLL_USB1 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_USB1_OFFSET) -#define IMXRT_CCM_ANALOG_PLL_SYS (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_SYS_OFFSET) -#define IMXRT_CCM_ANALOG_PLL_SYS_SS (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_SYS_SS_OFFSET) -#define IMXRT_CCM_ANALOG_PLL_SYS_NUM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_SYS_NUM_OFFSET) -#define IMXRT_CCM_ANALOG_PLL_SYS_DENOM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_SYS_DENOM_OFFSET) -#define IMXRT_CCM_ANALOG_PLL_AUDIO (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_AUDIO_OFFSET) -#define IMXRT_CCM_ANALOG_PLL_AUDIO_NUM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_AUDIO_NUM_OFFSET) -#define IMXRT_CCM_ANALOG_PLL_AUDIO_DENOM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_AUDIO_DENOM_OFFSET) -#define IMXRT_CCM_ANALOG_PLL_ENET (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_ENET_OFFSET) -#define IMXRT_CCM_ANALOG_PFD_480 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PFD_480_OFFSET) -#define IMXRT_CCM_ANALOG_PFD_528 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PFD_528_OFFSET) -#define IMXRT_CCM_ANALOG_MISC0 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_MISC0_OFFSET) -#define IMXRT_CCM_ANALOG_MISC1 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_MISC1_OFFSET) -#define IMXRT_CCM_ANALOG_MISC2 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_MISC2_OFFSET) - -/* Helper Macros *************************************************************/ - -#define CCM_PODF_FROM_DIVISOR(n) ((n)-1) /* PODF Values are divisor-1 */ - -/* Register bit definitions **************************************************/ - -/* Control Register */ - -#define CCM_CCR_OSCNT_SHIFT (0) /* Bits 0-7: Oscillator ready counter value */ -#define CCM_CCR_OSCNT_MASK (0xff << CCM_CCR_OSCNT_SHIFT) -# define CCM_CCR_OSCNT(n) ((uint32_t)(n) << CCM_CCR_OSCNT_SHIFT) - /* Bits 8-11: Reserved */ -#define CCM_CCR_COSC_EN (1 << 12) /* Bit 12: On chip oscillator enable */ - /* Bits 13-20: Reserved */ -#define CCM_CCR_REG_BYPASS_COUNT_SHIFT (21) /* Bits 21-26: Counter for analog_reg_bypass */ -#define CCM_CCR_REG_BYPASS_COUNT_MASK (0x3f << CCM_CCR_REG_BYPASS_COUNT_SHIFT) -# define CCM_CCR_REG_BYPASS_COUNT(n) ((uint32_t)(n) << CCM_CCR_REG_BYPASS_COUNT_SHIFT) -#define CCM_CCR_RBC_EN (1 << 27) /* Bit 27: Enable for REG_BYPASS_COUNTER */ - /* Bits 28-31: Reserved */ -/* Status Register */ - -#define CCM_CSR_REF_EN_B (1 << 0) /* Bit 0: Status of the value of CCM_REF_EN_B */ - /* Bits 1-2: Reserved */ -#define CCM_CSR_CAMP2_READY (3 << 0) /* Bit 3: Status indication of CAMP2 */ - /* Bit 4: Reserved */ -#define CCM_CSR_COSC_READY (5 << 0) /* Bit 5: Status indication of on board oscillator */ - /* Bits 6-31: Reserved */ -/* Clock Switcher Register */ - -#define CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0) /* Bit 0: Selects source to generate pll3_sw_clk */ - -/* Arm Clock Root Register */ - -#define CCM_CACRR_ARM_PODF_SHIFT (0) /* Bits 0-2: Divider for ARM clock root */ -#define CCM_CACRR_ARM_PODF_MASK (0x7 << CCM_CACRR_ARM_PODF_SHIFT) -# define CCM_CACRR_ARM_PODF(n) ((uint32_t)(n) << CCM_CACRR_ARM_PODF_SHIFT) - -/* Bus Clock Divider Register */ - - /* Bits 0-5: Reserved */ -#define CCM_CBCDR_SEMC_CLK_SEL (1 << 6) /* Bit 6: SEMC clock source select */ -#define CCM_CBCDR_SEMC_ALT_CLK_SEL (1 << 7) /* Bit 7: SEMC alternative clock select */ -#define CCM_CBCDR_SEMC_ALT_CLK_SEL_PLL2 (0 << 7) /* Bit 7: PLL2 PFD2 will be selected */ -#define CCM_CBCDR_SEMC_ALT_CLK_SEL_PLL3 (1 << 7) /* Bit 7: PLL3 PFD1 will be selected */ -#define CCM_CBCDR_IPG_PODF_SHIFT (8) /* Bits 8-9: Divider for ipg podf */ -#define CCM_CBCDR_IPG_PODF_MASK (0x3 << CCM_CBCDR_IPG_PODF_SHIFT) -# define CCM_CBCDR_IPG_PODF(n) ((uint32_t)(n) << CCM_CBCDR_IPG_PODF_SHIFT) -#define CCM_CBCDR_AHB_PODF_SHIFT (10) /* Bits 10-12: Divider for AHB PODF */ -#define CCM_CBCDR_AHB_PODF_MASK (0x7 << CCM_CBCDR_AHB_PODF_SHIFT) -# define CCM_CBCDR_AHB_PODF(n) ((uint32_t)(n) << CCM_CBCDR_AHB_PODF_SHIFT) - /* Bits 13-15: Reserved */ -#define CCM_CBCDR_SEMC_PODF_SHIFT (16) /* Bits 16-18: Post divider for SEMC clock */ -#define CCM_CBCDR_SEMC_PODF_MASK (0x7 << CCM_CBCDR_SEMC_PODF_SHIFT) -# define CCM_CBCDR_SEMC_PODF(n) ((uint32_t)(n) << CCM_CBCDR_SEMC_PODF_SHIFT) - /* Bits 19-24: Reserved */ -#define CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25) /* Bit 25: Selector for peripheral main clock */ -#define CCM_CBCDR_PERIPH_CLK_SEL_MASK (1 << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT) -# define CCM_CBCDR_PERIPH_CLK_SEL(n) ((uint32_t)(n) << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT) -# define CCM_CBCDR_PERIPH_CLK_SEL_PRE_PERIPH (0) -# define CCM_CBCDR_PERIPH_CLK_SEL_PERIPH_CLK2 (1) - - /* Bit 26: Reserved */ -#define CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT (27) /* Bits 27-29: Divider for periph_clk2_podf */ -#define CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) -# define CCM_CBCDR_PERIPH_CLK2_PODF(n) ((uint32_t)(n) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) - /* Bits 30-31: Reserved */ - -/* Bus Clock Multiplexer Register */ - - /* Bits 0-3: Reserved */ -#define CCM_CBCMR_LPSPI_CLK_SEL_SHIFT (4) /* Bits 4-5: Selector for lpspi clock multiplexer */ -#define CCM_CBCMR_LPSPI_CLK_SEL_MASK (0x3 << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) -# define CCM_CBCMR_LPSPI_CLK_SEL(n) ((uint32_t)(n) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) -# define CCM_CBCMR_LPSPI_CLK_SEL_PLL3_PFD1 ((uint32_t)(0) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) -# define CCM_CBCMR_LPSPI_CLK_SEL_PLL3_PFD0 ((uint32_t)(1) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) -# define CCM_CBCMR_LPSPI_CLK_SEL_PLL2 ((uint32_t)(2) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) -# define CCM_CBCMR_LPSPI_CLK_SEL_PLL2_PFD2 ((uint32_t)(3) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) - /* Bits 6-11: Reserved */ -#define CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT (12) /* Bits 12-13: Selector for peripheral clk2 clock multiplexer */ -#define CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT) -# define CCM_CBCMR_PERIPH_CLK2_SEL(n) ((uint32_t)(n) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT) -# define CCM_CBCMR_PERIPH_CLK2_SEL_PLL3_SW ((uint32_t)(0) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT) -# define CCM_CBCMR_PERIPH_CLK2_SEL_OSC_CLK ((uint32_t)(1) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT) -# define CCM_CBCMR_PERIPH_CLK2_SEL_PLL2_BP ((uint32_t)(2) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT) -#define CCM_CBCMR_TRACE_CLK_SEL_SHIFT (14) /* Bits 14-15: Selector for Trace clock multiplexer */ -#define CCM_CBCMR_TRACE_CLK_SEL_MASK (0x3 << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) -# define CCM_CBCMR_TRACE_CLK_SEL(n) ((uint32_t)(n) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) -# define CCM_CBCMR_TRACE_CLK_SEL_PLL2 ((uint32_t)(0) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) -# define CCM_CBCMR_TRACE_CLK_SEL_PLL2_PFD2 ((uint32_t)(1) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) -# define CCM_CBCMR_TRACE_CLK_SEL_PLL2_PFD0 ((uint32_t)(2) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) -# define CCM_CBCMR_TRACE_CLK_SEL_PLL2_PFD1 ((uint32_t)(3) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) - /* Bits 16-17: Reserved */ -#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18) /* Bits 18-19: Selector for pre_periph clock multiplexer */ -#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT) -# define CCM_CBCMR_PRE_PERIPH_CLK_SEL(n) ((uint32_t)(n) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT) -# define CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL2 (0) -# define CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL3_PFD3 (1) -# define CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL2_PFD3 (2) -# define CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL6 (3) - /* Bits 20-25: Reserved */ -#define CCM_CBCMR_LPSPI_PODF_SHIFT (26) /* Bits 26-28: Divider for LPSPI */ -#define CCM_CBCMR_LPSPI_PODF_MASK (0x7 << CCM_CBCMR_LPSPI_PODF_SHIFT) -# define CCM_CBCMR_LPSPI_PODF(n) ((uint32_t)(n) << CCM_CBCMR_LPSPI_PODF_SHIFT) - -/* Serial Clock Multiplexer Register 1 */ - -#define CCM_CSCMR1_PERCLK_PODF_SHIFT (0) /* Bits 0-5: Divider for perclk podf */ -#define CCM_CSCMR1_PERCLK_PODF_MASK (0x3f << CCM_CSCMR1_PERCLK_PODF_SHIFT) -# define CCM_CSCMR1_PERCLK_PODF(n) ((uint32_t)(n) << CCM_CSCMR1_PERCLK_PODF_SHIFT) -#define CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT (6) /* Bit 6: Selector for the perclk clock multiplexer */ -#define CCM_CSCMR1_PERCLK_CLK_SEL_MASK (1 << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT) -# define CCM_CSCMR1_PERCLK_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT) -# define CCM_CSCMR1_PERCLK_CLK_SEL_IPG_CLK_ROOT (0) -# define CCM_CSCMR1_PERCLK_CLK_SEL_OSC_CLK (1) - /* Bits 7-9: Reserved */ -#define CCM_CSCMR1_SAI1_CLK_SEL_SHIFT (10) /* Bits 10-11: Selector for sai1 clock multiplexer */ -#define CCM_CSCMR1_SAI1_CLK_SEL_MASK (0x3 << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT) -# define CCM_CSCMR1_SAI1_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT) -# define CCM_CSCMR1_SAI1_CLK_SEL_PLL3_PFD2 ((uint32_t)(0) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT) -# define CCM_CSCMR1_SAI1_CLK_SEL_PLL4 ((uint32_t)(2) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT) -#define CCM_CSCMR1_SAI2_CLK_SEL_SHIFT (12) /* Bits 12-13: Selector for sai2 clock multiplexer */ -#define CCM_CSCMR1_SAI2_CLK_SEL_MASK (0x3 << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT) -# define CCM_CSCMR1_SAI2_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT) -# define CCM_CSCMR1_SAI2_CLK_SEL_PLL3_PFD2 ((uint32_t)(0) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT) -# define CCM_CSCMR1_SAI2_CLK_SEL_PLL4 ((uint32_t)(2) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT) -#define CCM_CSCMR1_SAI3_CLK_SEL_SHIFT (14) /* Bits 14-15: Selector for sai3 clock multiplexer */ -#define CCM_CSCMR1_SAI3_CLK_SEL_MASK (0x3 << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT) -# define CCM_CSCMR1_SAI3_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT) -# define CCM_CSCMR1_SAI3_CLK_SEL_PLL3_PFD2 ((uint32_t)(0) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT) -# define CCM_CSCMR1_SAI3_CLK_SEL_PLL4 ((uint32_t)(2) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT) -#define CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16) /* Bit 16: Selector for usdhc1 clock multiplexer */ -# define CCM_CSCMR1_USDHC1_CLK_SEL_PLL2_PFD2 (0 << 16) /* derive clock from PLL2 PFD2 */ -# define CCM_CSCMR1_USDHC1_CLK_SEL_PLL2_PFD0 (1 << 16) /* derive clock from PLL2 PFD0 */ -#define CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17) /* Bit 17: Selector for usdhc2 clock multiplexer */ -# define CCM_CSCMR1_USDHC2_CLK_SEL_PLL2_PFD2 (0 << 17) /* derive clock from PLL2 PFD2 */ -# define CCM_CSCMR1_USDHC2_CLK_SEL_PLL2_PFD0 (1 << 17) /* derive clock from PLL2 PFD0 */ - /* Bits 18-22: Reserved */ -#define CCM_CSCMR1_FLEXSPI_PODF_SHIFT (23) /* Bits 23-25: Divider for flexspi clock root */ -#define CCM_CSCMR1_FLEXSPI_PODF_MASK (0x7 << CCM_CSCMR1_FLEXSPI_PODF_SHIFT) -# define CCM_CSCMR1_FLEXSPI_PODF(n) ((uint32_t)(n) << CCM_CSCMR1_FLEXSPI_PODF_SHIFT) - /* Bits 26-28: Reserved */ -#define CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT (29) /* Bits 29-30: Selector for flexspi clock multiplexer */ -#define CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK (0x3 << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) -# define CCM_CSCMR1_FLEXSPI_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) -# define CCM_CSCMR1_FLEXSPI_CLK_SEL_SEMC_CLK ((uint32_t)(0) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) -# define CCM_CSCMR1_FLEXSPI_CLK_SEL_PLL3_SW ((uint32_t)(1) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) -# define CCM_CSCMR1_FLEXSPI_CLK_SEL_PLL2_PFD2 ((uint32_t)(2) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) -# define CCM_CSCMR1_FLEXSPI_CLK_SEL_PLL3_PFD0 ((uint32_t)(3) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) - /* Bit 31: Reserved */ -/* Serial Clock Multiplexer Register 2 */ - -#define CCM_CSCMR2_CAN_CLK_PODF_SHIFT (2) /* Bits 2-7: Divider for can clock podf */ -#define CCM_CSCMR2_CAN_CLK_PODF_MASK (0x3f << CCM_CSCMR2_CAN_CLK_PODF_SHIFT) -# define CCM_CSCMR2_CAN_CLK_PODF(n) ((uint32_t)(n) << CCM_CSCMR2_CAN_CLK_PODF_SHIFT) -#define CCM_CSCMR2_CAN_CLK_SEL_SHIFT (8) /* Bits 8-9: Selector for FlexCAN clock multiplexer */ -#define CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << CCM_CSCMR2_CAN_CLK_SEL_SHIFT) -# define CCM_CSCMR2_CAN_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT) -# define CCM_CSCMR2_CAN_CLK_SEL_PLL3_SW_60 ((uint32_t)(0) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT) -# define CCM_CSCMR2_CAN_CLK_SEL_OSC_CLK ((uint32_t)(1) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT) -# define CCM_CSCMR2_CAN_CLK_SEL_PLL3_SW_80 ((uint32_t)(2) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT) - /* Bits 10-18: Reserved */ -#define CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT (19) /* Bits 19-20: Selector for flexio2 clock multiplexer */ -#define CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK (0x3 << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT) -# define CCM_CSCMR2_FLEXIO2_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT) -# define CCM_CSCMR2_FLEXIO2_CLK_SEL_PLL4 ((uint32_t)(0) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT) -# define CCM_CSCMR2_FLEXIO2_CLK_SEL_PLL3_PFD2 ((uint32_t)(1) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT) -# define CCM_CSCMR2_FLEXIO2_CLK_SEL_PLL3_SW ((uint32_t)(3) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT) - /* Bits 21-31: Reserved */ - -/* Serial Clock Divider Register 1 */ - -#define CCM_CSCDR1_UART_CLK_PODF_SHIFT (0) /* Bits 0-5: Divider for uart clock podf */ -#define CCM_CSCDR1_UART_CLK_PODF_MASK (0x3f << CCM_CSCDR1_UART_CLK_PODF_SHIFT) -# define CCM_CSCDR1_UART_CLK_PODF(n) ((uint32_t)(n) << CCM_CSCDR1_UART_CLK_PODF_SHIFT) -#define CCM_CSCDR1_UART_CLK_SEL (1 << 6) /* Bit 6: Selector for the UART clock multiplexer */ -# define CCM_CSCDR1_UART_CLK_SEL_PLL3_80 (0 << 6) /* derive clock from pll3_80m */ -# define CCM_CSCDR1_UART_CLK_SEL_OSC_CLK (1 << 6) /* derive clock from osc_clk */ - /* Bits 7-10: Reserved */ -#define CCM_CSCDR1_USDHC1_PODF_SHIFT (11) /* Bits 11-13: Divider for usdhc1 clock podf */ -#define CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << CCM_CSCDR1_USDHC1_PODF_SHIFT) -# define CCM_CSCDR1_USDHC1_PODF(n) ((uint32_t)(n) << CCM_CSCDR1_USDHC1_PODF_SHIFT) - /* Bits 14-15: Reserved */ -#define CCM_CSCDR1_USDHC2_PODF_SHIFT (16) /* Bits 16-18: Divider for usdhc2 clock */ -#define CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << CCM_CSCDR1_USDHC2_PODF_SHIFT) -# define CCM_CSCDR1_USDHC2_PODF(n) ((uint32_t)(n) << CCM_CSCDR1_USDHC2_PODF_SHIFT) - /* Bits 19-24: Reserved */ -#define CCM_CSCDR1_TRACE_PODF_SHIFT (25) /* Bits 25-27: Divider for trace clock */ -# define CCM_CSCDR1_TRACE_PODF_MASK (0x3 << CCM_CSCDR1_TRACE_PODF_SHIFT) - /* Bits 27-31: Reserved */ -# define CCM_CSCDR1_TRACE_PODF(n) ((uint32_t)(n) << CCM_CSCDR1_TRACE_PODF_SHIFT) - -/* Clock Divider Register 1 */ - -#define CCM_CS1CDR_SAI1_CLK_PODF_SHIFT (0) /* Bits 0-5: Divider for sai1 clock podf */ -#define CCM_CS1CDR_SAI1_CLK_PODF_MASK (0x3f << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT) -# define CCM_CS1CDR_SAI1_CLK_PODF(n) ((uint32_t)(n) << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT) -#define CCM_CS1CDR_SAI1_CLK_PRED_SHIFT (6) /* Bits 6-8: Divider for sai1 clock pred */ -#define CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x7 << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT) -# define CCM_CS1CDR_SAI1_CLK_PRED(n) ((uint32_t)(n) << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT) -#define CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT (9) /* Bits 9-11: Divider for flexio2 clock */ -#define CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK (0x7 << CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT) -# define CCM_CS1CDR_FLEXIO2_CLK_PRED(n) ((uint32_t)(n) << CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT) - /* Bits 12-15: Reserved */ -#define CCM_CS1CDR_SAI3_CLK_PODF_SHIFT (16) /* Bits 16-21: Divider for sai3 clock podf */ -#define CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3f << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT) -# define CCM_CS1CDR_SAI3_CLK_PODF(n) ((uint32_t)(n) << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT) -#define CCM_CS1CDR_SAI3_CLK_PRED_SHIFT (22) /* Bits 22-24: Divider for sai3 clock pred */ -#define CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x7 << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT) -# define CCM_CS1CDR_SAI3_CLK_PRED(n) ((uint32_t)(n) << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT) -#define CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT (25) /* Bits 25-27: Divider for flexio2 clock */ -#define CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK (0x7 << CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT) -# define CCM_CS1CDR_FLEXIO2_CLK_PODF(n) ((uint32_t)(n) << CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT) - /* Bits 28-31: Reserved */ -/* Clock Divider Register 2 */ - -#define CCM_CS2CDR_SAI2_CLK_PODF_SHIFT (0) /* Bits 0-5: Divider for sai2 clock podf */ -#define CCM_CS2CDR_SAI2_CLK_PODF_MASK (0x3f << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT) -# define CCM_CS2CDR_SAI2_CLK_PODF(n) ((uint32_t)(n) << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT) -#define CCM_CS2CDR_SAI2_CLK_PRED_SHIFT (6) /* Bits 6-8: Divider for sai2 clock pred */ -#define CCM_CS2CDR_SAI2_CLK_PRED_MASK (0x7 << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT) -# define CCM_CS2CDR_SAI2_CLK_PRED(n) ((uint32_t)(n) << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT) - -/* D1 Clock Divider Register */ - -#define CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT (20) /* Bits 20-21: Selector for spdif0 clock multiplexer */ -#define CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) -# define CCM_CDCDR_SPDIF0_CLK_SEL(n) ((uint32_t)(n) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) -# define CCM_CDCDR_SPDIF0_CLK_SEL_PLL4 ((uint32_t)(0) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) -# define CCM_CDCDR_SPDIF0_CLK_SEL_PLL3_PFD2 ((uint32_t)(1) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) -# define CCM_CDCDR_SPDIF0_CLK_SEL_PLL3_PLL3_SW ((uint32_t)(3) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) -#define CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT (22) /* Bits 22-24: Divider for spdif0 clock podf */ -#define CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT) -# define CCM_CDCDR_SPDIF0_CLK_PODF(n) ((uint32_t)(n) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT) -#define CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT (25) /* Bits 25-27: Divider for spdif0 clock pred */ -#define CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT) -# define CCM_CDCDR_SPDIF0_CLK_PRED(n) ((uint32_t)(n) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT) - -/* Serial Clock Divider Register 2 */ - - /* Bits 0-17: Reserved */ -#define CCM_CSCDR2_LPI2C_CLK_SEL (1 << 18) /* Bit 18: Selector for the LPI2C clock multiplexer */ -# define CCM_CSCDR2_LPI2C_CLK_SEL_PLL3_60M (0 << 18) /* derive clock from pll3_60m */ -# define CCM_CSCDR2_LPI2C_CLK_SEL_OSC_CLK (1 << 18) /* derive clock from ock_clk */ -#define CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT (19) /* Bits 19-24: Divider for lpi2c clock podf */ -#define CCM_CSCDR2_LPI2C_CLK_PODF_MASK (0x3f << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT) -# define CCM_CSCDR2_LPI2C_CLK_PODF(n) ((uint32_t)(n) << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT) - /* Bits 25-31: Reserved */ - -/* Divider Handshake In-Process Register */ - -#define CCM_CDHIPR_SEMC_PODF_BUSY (1 << 0) /* Bit 0: Busy indicator for semc_podf */ -#define CCM_CDHIPR_AHB_PODF_BUSY (1 << 1) /* Bit 1: Busy indicator for ahb_podf */ - /* Bit 2: Reserved */ -#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3) /* Bit 3: Busy indicator for periph2_clk_sel mux control */ - /* Bit 4: Reserved */ -#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5) /* Bit 5: Busy indicator for periph_clk_sel mux control */ - /* Bits 6-15: Reserved */ -#define CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) /* Bit 16: Busy indicator for arm_podf */ - /* Bits 17-31: Reserved */ - -/* Low Power Control Register */ - -#define CCM_CLPCR_LPM_SHIFT (0) /* Bits 0-1: Setting the low power mode */ -#define CCM_CLPCR_LPM_MASK (0x3 << CCM_CLPCR_LPM_SHIFT) -# define CCM_CLPCR_LPM(n) ((uint32_t)(n) << CCM_CLPCR_LPM_SHIFT) -# define CCM_CLPCR_LPM_RUN ((uint32_t)(0) << CCM_CLPCR_LPM_SHIFT) /* Remain in run mode */ -# define CCM_CLPCR_LPM_WAIT ((uint32_t)(1) << CCM_CLPCR_LPM_SHIFT) /* Transfer to wait mode */ -# define CCM_CLPCR_LPM_STOP ((uint32_t)(2) << CCM_CLPCR_LPM_SHIFT) /* Transfer to stop mode */ - /* Bits 2-4: Reserved */ -#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5) /* Bit 5: ARM clocks disabled on wait mode */ -#define CCM_CLPCR_SBYOS (1 << 6) /* Bit 6: Standby clock oscillator bit */ -#define CCM_CLPCR_DIS_REF_OSC (1 << 7) /* Bit 7: external high frequency oscillator disable */ -#define CCM_CLPCR_VSTBY (1 << 8) /* Bit 8: Voltage standby request bit */ -#define CCM_CLPCR_STBY_COUNT_SHIFT (9) /* Bits 9-10: Standby counter definition */ -#define CCM_CLPCR_STBY_COUNT_MASK (0x3 << CCM_CLPCR_STBY_COUNT_SHIFT) -# define CCM_CLPCR_STBY_COUNT(n) ((uint32_t)(n) << CCM_CLPCR_STBY_COUNT_SHIFT) -#define CCM_CLPCR_COSC_PWRDOWN (1 << 11) /* Bit 11: On chip oscillator power down */ - /* Bits 12-18: Reserved */ -#define CCM_CLPCR_BYPASS_LPM_HS1 (1 << 19) /* Bit 19: Bypass low power mode handshake */ - /* Bit 20: Reserved */ -#define CCM_CLPCR_BYPASS_LPM_HS0 (1 << 21) /* Bit 21: Bypass low power mode handshake */ -#define CCM_CLPCR_MASK_CORE0_WFI (1 << 22) /* Bit 22: Mask WFI of core0 for entering low power mode */ - /* Bits 23-25: Reserved */ -#define CCM_CLPCR_MASK_SCU_IDLE (1 << 26) /* Bit 26: Mask SCU IDLE for entering low power mode */ -#define CCM_CLPCR_MASK_L2CC_IDLE (1 << 27) /* Bit 27: Mask L2CC IDLE for entering low power mode */ - /* Bits 28-31: Reserved */ - -/* Interrupt Status Register */ - -#define CCM_CISR_LRF_PLL (1 << 0) /* Bit 0: CCM irq2, lock of all enabled and not bypassed PLLs */ - /* Bits 1-5: Reserved */ -#define CCM_CISR_COSC_READY (1 << 6) /* Bit 6: CCM irq2, on board oscillator ready */ - /* Bits 7-16: Reserved */ -#define CCM_CISR_SEMC_PODF_LOADED (1 << 17) /* Bit 17: CCM irq1, frequency change of semc_podf */ - /* Bit 18: Reserved */ -#define CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19) /* Bit 19: CCM irq1, frequency change of periph2_clk_sel */ -#define CCM_CISR_AHB_PODF_LOADED (1 << 20) /* Bit 20: CCM irq1, frequency change of ahb_podf */ - /* Bit 21: Reserved */ -#define CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22) /* Bit 22: CCM irq1, update of periph_clk_sel */ - /* Bits 23-25: Reserved */ -#define CCM_CISR_ARM_PODF_LOADED (1 << 26) /* Bit 26: CCM irq1, frequency change of arm_podf */ - /* Bits 27-31: Reserved */ - -/* Interrupt Mask Register */ - -#define CCM_CIMR_MASK_LRF_PLL (1 << 0) /* Bit 0: mask interrupt generation due to lrf of PLLs */ - /* Bits 1-5: Reserved */ -#define CCM_CIMR_MASK_COSC_READY (1 << 6) /* Bit 6: mask interrupt generation due to on board oscillator ready */ - /* Bits 7-16: Reserved */ -#define CCM_CIMR_MASK_SEMC_PODF_LOADED (1 << 17) /* Bit 17: mask interrupt generation due to frequency change of semc_podf */ - /* Bit 18: Reserved */ -#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 19) /* Bit 19: mask interrupt generation due to update of periph2_clk_sel */ -#define CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20) /* Bit 20: mask interrupt generation due to frequency change of ahb_podf */ - /* Bit 21: Reserved */ -#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22) /* Bit 22: mask interrupt generation due to update of periph_clk_sel */ - /* Bits 23-25: Reserved */ -#define CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26) /* Bit 26: mask interrupt generation due to frequency change of arm_podf */ - /* Bits 27-31: Reserved */ - -/* Clock Output Source Register */ - -#define CCM_CCOSR_CLKO1_SEL_SHIFT (0) /* Bits 0-3: Selection of the clock to be generated on CCM_CLKO1 */ -#define CCM_CCOSR_CLKO1_SEL_MASK (0xF << CCM_CCOSR_CLKO1_SEL_SHIFT) - -# define CCM_CCOSR_CLKO1_SEL_PLL3_SW_DIV2_CLK ((uint32_t)(0) << CCM_CCOSR_CLKO1_SEL_SHIFT) -# define CCM_CCOSR_CLKO1_SEL_PLL2_DIV2_CLK ((uint32_t)(1) << CCM_CCOSR_CLKO1_SEL_SHIFT) -# define CCM_CCOSR_CLKO1_SEL_ENET_PLL_DIV2_CLK ((uint32_t)(2) << CCM_CCOSR_CLKO1_SEL_SHIFT) -# define CCM_CCOSR_CLKO1_SEL_SEMC_CLK ((uint32_t)(5) << CCM_CCOSR_CLKO1_SEL_SHIFT) -# define CCM_CCOSR_CLKO1_SEL_AHB_CLK ((uint32_t)(11) << CCM_CCOSR_CLKO1_SEL_SHIFT) -# define CCM_CCOSR_CLKO1_SEL_IPG_CLK ((uint32_t)(12) << CCM_CCOSR_CLKO1_SEL_SHIFT) -# define CCM_CCOSR_CLKO1_SEL_PER_CLK ((uint32_t)(13) << CCM_CCOSR_CLKO1_SEL_SHIFT) -# define CCM_CCOSR_CLKO1_SEL_PLL4_MAIN_CLK ((uint32_t)(15) << CCM_CCOSR_CLKO1_SEL_SHIFT) - -#define CCM_CCOSR_CLKO1_DIV_SHIFT (4) /* Bits 4-6: Setting the divider of CCM_CLKO1 */ -#define CCM_CCOSR_CLKO1_DIV_MASK (0x7 << CCM_CCOSR_CLKO1_DIV_SHIFT) -# define CCM_CCOSR_CLKO1_DIV(n) ((uint32_t)(n) << CCM_CCOSR_CLKO1_DIV_SHIFT) -#define CCM_CCOSR_CLKO1_EN (1 << 7) /* Bit 7: Enable of CCM_CLKO1 clock */ -#define CCM_CCOSR_CLK_OUT_SEL (1 << 8) /* Bit 8: CCM_CLKO1 output to reflect CCM_CLKO1 or CCM_CLKO2 clocks */ - /* Bits 9-15: Reserved */ -#define CCM_CCOSR_CLKO2_SEL_SHIFT (16) /* Bits 16-20: Selection of the clock to be generated on CCM_CLKO2 */ -#define CCM_CCOSR_CLKO2_SEL_MASK (0x1F << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_USDHC1_CLK ((uint32_t)(3) << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_LPI2C_CLK ((uint32_t)(6) << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_OSC_CLK ((uint32_t)(14) << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_USDHC2_CLK ((uint32_t)(17) << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_SAI1_CLK ((uint32_t)(18) << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_SAI2_CLK ((uint32_t)(19) << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_SAI3_CLK ((uint32_t)(20) << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_TRACE_CLK ((uint32_t)(22) << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_CAN_CLK ((uint32_t)(23) << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_FLEXSPI_CLK ((uint32_t)(27) << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_UART_CLK ((uint32_t)(28) << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_SPDIF0_CLK ((uint32_t)(29) << CCM_CCOSR_CLKO2_SEL_SHIFT) - -#define CCM_CCOSR_CLKO2_DIV_SHIFT (21) /* Bits 21-23: Setting the divider of CCM_CLKO2 */ -#define CCM_CCOSR_CLKO2_DIV_MASK (0x7 << CCM_CCOSR_CLKO2_DIV_SHIFT) -# define CCM_CCOSR_CLKO2_DIV(n) ((uint32_t)(n) << CCM_CCOSR_CLKO2_DIV_SHIFT) -#define CCM_CCOSR_CLKO2_EN (1 << 24) /* Bit 24: Enable of CCM_CLKO2 clock */ - /* Bits 25-31: Reserved */ - -/* General Purpose Register */ - -#define CCM_CGPR_PMIC_DELAY_SCALER (1 << 0) /* Bit 0: Defines clock division of clock for stby_count */ - /* Bits 1-3: Reserved */ -#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4) /* Bit 4: allow fuse programing */ - /* Bits 5-13: Reserved */ -#define CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT (14) /* Bits 14-15: System memory DS control */ -#define CCM_CGPR_SYS_MEM_DS_CTRL_MASK (0x7 << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT) -# define CCM_CGPR_SYS_MEM_DS_CTRL(n) ((uint32_t)(n) << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT) -#define CCM_CGPR_FPL (1 << 16) /* Bit 16: Fast PLL enable */ -#define CCM_CGPR_INT_MEM_CLK_LPM (1 << 17) /* Bit 17: Control for the Deep Sleep signal to the ARM Platform memories */ - /* Bits 18-31: Reserved */ - -/* Clock Gating Register 0-6 */ - -#define CCM_CG_OFF (0) /* Clock is off during all modes */ -#define CCM_CG_RUN (1) /* Clock is on in run mode, but off in WAIT and STOP modes */ -#define CCM_CG_ALL (3) /* Clock is on during all modes, except STOP mode. */ - -#define CCM_CCGRX_CG_SHIFT(r) ((r) << 1) -#define CCM_CCGRX_CG_MASK(r) (0x3 << CCM_CCGRX_CG_SHIFT(r)) -# define CCM_CCGRX_CG(r,v) ((uint32_t)(v) << CCM_CCGRX_CG_SHIFT(r)) - -#define CCM_CCGRX_CG0_SHIFT (0) -#define CCM_CCGRX_CG0_MASK (0x3 << CCM_CCGRX_CG0_SHIFT) -# define CCM_CCGRX_CG0(n) ((uint32_t)(n) << CCM_CCGRX_CG0_SHIFT) -#define CCM_CCGRX_CG1_SHIFT (2) -#define CCM_CCGRX_CG1_MASK (0x3 << CCM_CCGRX_CG1_SHIFT) -# define CCM_CCGRX_CG1(n) ((uint32_t)(n) << CCM_CCGRX_CG1_SHIFT) -#define CCM_CCGRX_CG2_SHIFT (4) -#define CCM_CCGRX_CG2_MASK (0x3 << CCM_CCGRX_CG2_SHIFT) -# define CCM_CCGRX_CG2(n) ((uint32_t)(n) << CCM_CCGRX_CG2_SHIFT) -#define CCM_CCGRX_CG3_SHIFT (6) -#define CCM_CCGRX_CG3_MASK (0x3 << CCM_CCGRX_CG3_SHIFT) -# define CCM_CCGRX_CG3(n) ((uint32_t)(n) << CCM_CCGRX_CG3_SHIFT) -#define CCM_CCGRX_CG4_SHIFT (8) -#define CCM_CCGRX_CG4_MASK (0x3 << CCM_CCGRX_CG4_SHIFT) -# define CCM_CCGRX_CG4(n) ((uint32_t)(n) << CCM_CCGRX_CG4_SHIFT) -#define CCM_CCGRX_CG5_SHIFT (10) -#define CCM_CCGRX_CG5_MASK (0x3 << CCM_CCGRX_CG5_SHIFT) -# define CCM_CCGRX_CG5(n) ((uint32_t)(n) << CCM_CCGRX_CG5_SHIFT) -#define CCM_CCGRX_CG6_SHIFT (12) -#define CCM_CCGRX_CG6_MASK (0x3 << CCM_CCGRX_CG6_SHIFT) -# define CCM_CCGRX_CG6(n) ((uint32_t)(n) << CCM_CCGRX_CG6_SHIFT) -#define CCM_CCGRX_CG7_SHIFT (14) -#define CCM_CCGRX_CG7_MASK (0x3 << CCM_CCGRX_CG7_SHIFT) -# define CCM_CCGRX_CG7(n) ((uint32_t)(n) << CCM_CCGRX_CG7_SHIFT) -#define CCM_CCGRX_CG8_SHIFT (16) -#define CCM_CCGRX_CG8_MASK (0x3 << CCM_CCGRX_CG8_SHIFT) -# define CCM_CCGRX_CG8(n) ((uint32_t)(n) << CCM_CCGRX_CG8_SHIFT) -#define CCM_CCGRX_CG9_SHIFT (18) -#define CCM_CCGRX_CG9_MASK (0x3 << CCM_CCGRX_CG9_SHIFT) -# define CCM_CCGRX_CG9(n) ((uint32_t)(n) << CCM_CCGRX_CG9_SHIFT) -#define CCM_CCGRX_CG10_SHIFT (20) -#define CCM_CCGRX_CG10_MASK (0x3 << CCM_CCGRX_CG10_SHIFT) -# define CCM_CCGRX_CG10(n) ((uint32_t)(n) << CCM_CCGRX_CG10_SHIFT) -#define CCM_CCGRX_CG11_SHIFT (22) -#define CCM_CCGRX_CG11_MASK (0x3 << CCM_CCGRX_CG11_SHIFT) -# define CCM_CCGRX_CG11(n) ((uint32_t)(n) << CCM_CCGRX_CG11_SHIFT) -#define CCM_CCGRX_CG12_SHIFT (24) -#define CCM_CCGRX_CG12_MASK (0x3 << CCM_CCGRX_CG12_SHIFT) -# define CCM_CCGRX_CG12(n) ((uint32_t)(n) << CCM_CCGRX_CG12_SHIFT) -#define CCM_CCGRX_CG13_SHIFT (26) -#define CCM_CCGRX_CG13_MASK (0x3 << CCM_CCGRX_CG13_SHIFT) -# define CCM_CCGRX_CG13(n) ((uint32_t)(n) << CCM_CCGRX_CG13_SHIFT) -#define CCM_CCGRX_CG14_SHIFT (28) -#define CCM_CCGRX_CG14_MASK (0x3 << CCM_CCGRX_CG14_SHIFT) -# define CCM_CCGRX_CG14(n) ((uint32_t)(n) << CCM_CCGRX_CG14_SHIFT) -#define CCM_CCGRX_CG15_SHIFT (30) -#define CCM_CCGRX_CG15_MASK (0x3 << CCM_CCGRX_CG15_SHIFT) -# define CCM_CCGRX_CG15(n) ((uint32_t)(n) << CCM_CCGRX_CG15_SHIFT) - -/* Macros used by imxrt_periphclks.h */ - -#define CCM_CCGR_GPIO2 IMXRT_CCM_CCGR0, 15 -#define CCM_CCGR_LPUART2 IMXRT_CCM_CCGR0, 14 -#define CCM_CCGR_GPT2_SERIAL IMXRT_CCM_CCGR0, 13 -#define CCM_CCGR_GPT2_BUS IMXRT_CCM_CCGR0, 12 -#define CCM_CCGR_TRACE IMXRT_CCM_CCGR0, 11 -#define CCM_CCGR_CAN2_SERIAL IMXRT_CCM_CCGR0, 10 -#define CCM_CCGR_CAN2 IMXRT_CCM_CCGR0, 9 -#define CCM_CCGR_CAN1_SERIAL IMXRT_CCM_CCGR0, 8 -#define CCM_CCGR_CAN1 IMXRT_CCM_CCGR0, 7 -#define CCM_CCGR_LPUART3 IMXRT_CCM_CCGR0, 6 -#define CCM_CCGR_DCP IMXRT_CCM_CCGR0, 5 -# define CCM_CCGR_SIM_M_CLK_R_CLK IMXRT_CCM_CCGR0, 4 - /* 3 : Reserved */ -#define CCM_CCGR_MQS IMXRT_CCM_CCGR0, 2 -#define CCM_CCGR_AIPS_TZ2 IMXRT_CCM_CCGR0, 1 -#define CCM_CCGR_AIPS_TZ1 IMXRT_CCM_CCGR0, 0 - -# define CCM_CCGR_GPIO5 IMXRT_CCM_CCGR1, 15 -#define CCM_CCGR_CSU IMXRT_CCM_CCGR1, 14 -#define CCM_CCGR_GPIO1 IMXRT_CCM_CCGR1, 13 -#define CCM_CCGR_LPUART4 IMXRT_CCM_CCGR1, 12 -#define CCM_CCGR_GPT_SERIAL IMXRT_CCM_CCGR1, 11 -#define CCM_CCGR_GPT_BUS IMXRT_CCM_CCGR1, 10 -#define CCM_CCGR_SEMC_EXSC IMXRT_CCM_CCGR1, 9 -#define CCM_CCGR_ADC1 IMXRT_CCM_CCGR1, 8 - /* 7 : Reserved */ -#define CCM_CCGR_PIT IMXRT_CCM_CCGR1, 6 -#define CCM_CCGR_ENET IMXRT_CCM_CCGR1, 5 -#define CCM_CCGR_ADC2 IMXRT_CCM_CCGR1, 4 -#define CCM_CCGR_LPSPI4 IMXRT_CCM_CCGR1, 3 -#define CCM_CCGR_LPSPI3 IMXRT_CCM_CCGR1, 2 -#define CCM_CCGR_LPSPI2 IMXRT_CCM_CCGR1, 1 -#define CCM_CCGR_LPSPI1 IMXRT_CCM_CCGR1, 0 - - /* 15 : Reserved */ - /* 14 : Reserved */ -#define CCM_CCGR_GPIO3 IMXRT_CCM_CCGR2, 13 -#define CCM_CCGR_XBAR2 IMXRT_CCM_CCGR2, 12 -#define CCM_CCGR_XBAR1 IMXRT_CCM_CCGR2, 11 - /* 10 : Reserved */ - /* 9 : Reserved */ - /* 8 : Reserved */ - /* 7 : Reserved */ -#define CCM_CCGR_OCOTP_CTRL IMXRT_CCM_CCGR2, 6 -#define CCM_CCGR_LPI2C3 IMXRT_CCM_CCGR2, 5 -#define CCM_CCGR_LPI2C2 IMXRT_CCM_CCGR2, 4 -#define CCM_CCGR_LPI2C1 IMXRT_CCM_CCGR2, 3 -#define CCM_CCGR_IOMUXC_SNVS IMXRT_CCM_CCGR2, 2 - /* 1 : Reserved */ -#define CCM_CCGR_OCRAM_EXSC IMXRT_CCM_CCGR2, 0 - -#define CCM_CCGR_IOMUXC_SNVS_GPR IMXRT_CCM_CCGR3, 15 - /* 14 : Reserved */ -#define CCM_CCGR_ACMP4 IMXRT_CCM_CCGR3, 13 -#define CCM_CCGR_ACMP3 IMXRT_CCM_CCGR3, 12 -#define CCM_CCGR_ACMP2 IMXRT_CCM_CCGR3, 11 -#define CCM_CCGR_ACMP1 IMXRT_CCM_CCGR3, 10 -#define CCM_CCGR_FLEXRAM IMXRT_CCM_CCGR3, 9 -#define CCM_CCGR_WDOG1 IMXRT_CCM_CCGR3, 8 -#define CCM_CCGR_EWM IMXRT_CCM_CCGR3, 7 - /* 6 : Reserved */ - /* 5 : Reserved */ -#define CCM_CCGR_AOI1 IMXRT_CCM_CCGR3, 4 -#define CCM_CCGR_LPUART6 IMXRT_CCM_CCGR3, 3 -#define CCM_CCGR_SEMC IMXRT_CCM_CCGR3, 2 -#define CCM_CCGR_LPUART5 IMXRT_CCM_CCGR3, 1 - /* 0 : Reserved */ - - /* 15 : Reserved */ - /* 14 : Reserved */ -#define CCM_CCGR_ENC2 IMXRT_CCM_CCGR4, 13 -#define CCM_CCGR_ENC1 IMXRT_CCM_CCGR4, 12 - /* 11 : Reserved */ - /* 10 : Reserved */ -#define CCM_CCGR_PWM2 IMXRT_CCM_CCGR4, 9 -#define CCM_CCGR_PWM1 IMXRT_CCM_CCGR4, 8 -#define CCM_CCGR_SIM_EMS IMXRT_CCM_CCGR4, 7 -#define CCM_CCGR_SIM_M IMXRT_CCM_CCGR4, 6 - /* 5 : Reserved */ -#define CCM_CCGR_SIM_M7 IMXRT_CCM_CCGR4, 4 -#define CCM_CCGR_BEE IMXRT_CCM_CCGR4, 3 -#define CCM_CCGR_IOMUXC_GPR IMXRT_CCM_CCGR4, 2 -#define CCM_CCGR_IOMUXC IMXRT_CCM_CCGR4, 1 -#define CCM_CCGR_SIM_M7_R_EN IMXRT_CCM_CCGR4, 0 - -#define CCM_CCGR_SNVS_LP IMXRT_CCM_CCGR5, 15 -#define CCM_CCGR_SNVS_HP IMXRT_CCM_CCGR5, 14 -#define CCM_CCGR_LPUART7 IMXRT_CCM_CCGR5, 13 -#define CCM_CCGR_LPUART1 IMXRT_CCM_CCGR5, 12 -#define CCM_CCGR_SAI3 IMXRT_CCM_CCGR5, 11 -#define CCM_CCGR_SAI2 IMXRT_CCM_CCGR5, 10 -#define CCM_CCGR_SAI1 IMXRT_CCM_CCGR5, 9 - /* 8 : Reserved */ -#define CCM_CCGR_SPDIF IMXRT_CCM_CCGR5, 7 -#define CCM_CCGR_AIPSTZ4 IMXRT_CCM_CCGR5, 6 -#define CCM_CCGR_WDOG2 IMXRT_CCM_CCGR5, 5 -#define CCM_CCGR_KPP IMXRT_CCM_CCGR5, 4 -#define CCM_CCGR_DMA IMXRT_CCM_CCGR5, 3 -#define CCM_CCGR_WDOG3 IMXRT_CCM_CCGR5, 2 -#define CCM_CCGR_FLEXIO1 IMXRT_CCM_CCGR5, 1 -#define CCM_CCGR_ROM IMXRT_CCM_CCGR5, 0 - - /* 15 : Reserved */ -#define CCM_CCGR_TIMER2 IMXRT_CCM_CCGR6, 14 -#define CCM_CCGR_TIMER1 IMXRT_CCM_CCGR6, 13 -#define CCM_CCGR_LPI2C4_SERIAL IMXRT_CCM_CCGR6, 12 -#define CCM_CCGR_ANADIG IMXRT_CCM_CCGR6, 11 -#define CCM_CCGR_SIM_PER IMXRT_CCM_CCGR6, 10 -#define CCM_CCGR_AIPS_TZ3 IMXRT_CCM_CCGR6, 9 - /* 8 : Reserved */ -#define CCM_CCGR_LPUART8 IMXRT_CCM_CCGR6, 7 -#define CCM_CCGR_TRNG IMXRT_CCM_CCGR6, 6 -#define CCM_CCGR_FLEXSPI IMXRT_CCM_CCGR6, 5 - /* 4 : Reserved */ -#define CCM_CCGR_DCDC IMXRT_CCM_CCGR6, 3 -#define CCM_CCGR_USDHC2 IMXRT_CCM_CCGR6, 2 -#define CCM_CCGR_USDHC1 IMXRT_CCM_CCGR6, 1 -#define CCM_CCGR_USBOH3 IMXRT_CCM_CCGR6, 0 - -/* Module Enable Override Register */ - - /* Bits 0-4: Reserved */ -#define CCM_CMEOR_MOD_EN_OV_GPT (1 << 5) /* Bit 5: Overide clock enable signal from GPT */ -#define CCM_CMEOR_MOD_EN_OV_PIT (1 << 6) /* Bit 6: Overide clock enable signal from PIT */ -#define CCM_CMEOR_MOD_EN_OV_USDHC (1 << 7) /* Bit 7: Overide clock enable signal from USDHC */ -#define CCM_CMEOR_MOD_EN_OV_TRNG (1 << 9) /* Bit 9: Overide clock enable signal from TRNG */ - /* Bits 10-27: Reserved */ -#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI (1 << 28) /* Bit 28: Overide clock enable signal from CAN2 */ -#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI (1 << 30) /* Bit 30: Overide clock enable signal from CAN1 */ - /* Bit 31: Reserved */ - -/* Analog System PLL (2) Control Register **********************************/ - -#define CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT (0) /* Bits 0: This field controls the PLL loop divider 20 or 22 */ -#define CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK (0x3 << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_SYS_DIV_SELECT(n) ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_SYS_DIV_SELECT_20 (0) -# define CCM_ANALOG_PLL_SYS_DIV_SELECT_22 (1) -#define CCM_ANALOG_PLL_SYS_DIV_VAL(n) (((n)==CCM_ANALOG_PLL_SYS_DIV_SELECT_20)?20:22) - /* Bit 1-11: Reserved */ -#define CCM_ANALOG_PLL_SYS_POWERDOWN (1 << 12) /* Bit 12: Powers down the PLL */ -#define CCM_ANALOG_PLL_SYS_ENABLE (1 << 13) /* Bit 13: Enable the PLL clock output */ -#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ -#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) -# define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ -#define CCM_ANALOG_PLL_SYS_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ - /* Bits 17-30 Reserved */ -#define CCM_ANALOG_PLL_SYS_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ - -/* Analog USB1 480MHz PLL (3) Control Register **********************************/ - /* Bit 0: Reserved */ -#define CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT (1) /* Bit 1: This field controls the PLL loop divider 20 or 22 */ -#define CCM_ANALOG_PLL_USB1_DIV_SELECT(n) ((uint32_t)(n) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT) -#define CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK CCM_ANALOG_PLL_USB1_DIV_SELECT(1) -#define CCM_ANALOG_PLL_USB1_DIV_VAL(n) (((n)==CCM_ANALOG_PLL_USB1_DIV_SELECT_20)?20:22) -# define CCM_ANALOG_PLL_USB1_DIV_SELECT_20 (0) -# define CCM_ANALOG_PLL_USB1_DIV_SELECT_22 (1) - /* Bits 2-5 Reserved */ -#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS (1 << 6) /* Bit 6: Enable PLL outputs for USBPHYn */ - /* Bits 7-11 Reserved */ -#define CCM_ANALOG_PLL_USB1_POWER (1 << 12) /* Bit 12: Powers up the PLL */ -#define CCM_ANALOG_PLL_USB1_ENABLE (1 << 13) /* Bit 13: Enable the PLL clock output */ -#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ -#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) -# define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ -#define CCM_ANALOG_PLL_USB1_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ - /* Bits 17-30 Reserved */ -#define CCM_ANALOG_PLL_USB1_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ - -/* 528MHz System PLL Spread Spectrum Register */ - -#define CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT (0) /* Bits 0-14: Frequency change step */ -#define CCM_ANALOG_PLL_SYS_SS_STEP_MASK (0x3FFF << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT) -# define CCM_ANALOG_PLL_SYS_SS_STEP(n) ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT) -#define CCM_ANALOG_PLL_SYS_SS_ENABLE (1 << 15) /* Bit 15: Enable bit */ -#define CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT (0) /* Bits 16-31: Frequency change */ -#define CCM_ANALOG_PLL_SYS_SS_STOP_MASK (0xFFFF << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT) -# define CCM_ANALOG_PLL_SYS_SS_STOP(n) ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT) - -/* Numerator of 528MHz System PLL Fractional Loop Divider Register */ - -#define CCM_ANALOG_PLL_SYS_NUM_A_SHIFT (0) /* Bits 0-29: 30 bit numerator (A) */ -#define CCM_ANALOG_PLL_SYS_NUM_A_MASK (0x3FFFFFFF << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT) -#define CCM_ANALOG_PLL_SYS_NUM_A(n) ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT) - /* Bits 30-31: Reserved */ - -/* Denominator of 528MHz System PLL Fractional Loop Divider Register */ - -#define CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT (0) /* Bits 0-29: 30 bit numerator (A) */ -#define CCM_ANALOG_PLL_SYS_DENOM_B_MASK (0x3FFFFFFF << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT) -#define CCM_ANALOG_PLL_SYS_DENOM_B(n) ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT) - /* Bits 30-31: Reserved */ - -/* Analog Audio PLL control Register */ - -#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT (0) /* Bits 0-6: This field controls the PLL loop divider: 27-54 */ -#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK (0x7f << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(n) ((uint32_t)(n) << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT) - /* Bits 7-11: Reserved */ -#define CCM_ANALOG_PLL_AUDIO_POWERDOWN (1 << 12) /* Bit 12: Powers down the PLL */ -#define CCM_ANALOG_PLL_AUDIO_ENABLE (1 << 13) /* Bit 13: Enable PLL output */ -#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ -#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT) -# define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ -#define CCM_ANALOG_PLL_AUDIO_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ - /* Bit 17-18: Reserved */ -#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT (19) /* Bits 19-20: These bits implement a divider after the PLL */ -#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK (0x7f << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_DIV4 ((uint32_t)(0) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_DIV2 ((uint32_t)(1) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_DIV1 ((uint32_t)(2) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT) - /* Bits 21-30: Reserved */ -#define CCM_ANALOG_PLL_AUDIO_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ - -/* Numerator of Audio PLL Fractional Loop Divider Register */ - -#define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT (0) /* Bits 0-29: 30 bit numerator (A) */ -#define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK (0x3FFFFFFF << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT) -#define CCM_ANALOG_PLL_AUDIO_NUM_A(n) ((uint32_t)(n) << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT) -/* Bits 30-31: Reserved */ - -/* Denominator of Audio PLL Fractional Loop Divider Register */ - -#define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT (0) /* Bits 0-29: 30 bit numerator (A) */ -#define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK (0x3FFFFFFF << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT) -#define CCM_ANALOG_PLL_AUDIO_DENOM_B(n) ((uint32_t)(n) << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT) - /* Bits 30-31: Reserved */ -/* Analog ENET PLL Control Register */ - -#define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT (0) /* Bits 0-1: Controls the frequency of the ethernet0 reference clock */ -#define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_MASK (0x3 << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_25MHZ ((uint32_t)(0) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_50MHZ ((uint32_t)(1) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_100MHZ ((uint32_t)(2) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_125MHZ ((uint32_t)(3) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT) - - /* Bits 2-11: Reserved */ -#define CCM_ANALOG_PLL_ENET_POWERDOWN (1 << 12) /* Bit 12: Powers down the PLL */ -#define CCM_ANALOG_PLL_ENET_ENET1_125M_EN (1 << 13) /* Bit 13: Enable the PLL providing the ENET1 125 MHz reference clock */ -#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ -#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT) -# define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ -#define CCM_ANALOG_PLL_ENET_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ - /* Bit 17-20: Reserved */ -#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN (1 << 21) /* Bit 21: Enable the PLL providing ENET 25 MHz reference clock */ -#define CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN (1 << 22) /* Bit 22: Enable the PLL providing NET 500 MHz reference clock */ -#define CCM_ANALOG_PLL_ENET_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ - -/* 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ - -#define CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT (0) /* Bits 0-5: This field controls the fractional divide value */ -#define CCM_ANALOG_PFD_480_PFD0_FRAC_MASK (0x3f << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT) -# define CCM_ANALOG_PFD_480_PFD0_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT) -#define CCM_ANALOG_PFD_480_PFD0_STABLE (1 << 6) /* Bit 6: */ -#define CCM_ANALOG_PFD_480_PFD0_CLKGATE (1 << 7) /* Bit 7: If set to 1, the IO fractional divider clock is off */ -#define CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT (8) /* Bits 8-13: This field controls the fractional divide value */ -#define CCM_ANALOG_PFD_480_PFD1_FRAC_MASK (0x3f << CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT) -# define CCM_ANALOG_PFD_480_PFD1_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_481_PFD1_FRAC_SHIFT) -#define CCM_ANALOG_PFD_480_PFD1_STABLE (1 << 14) /* Bit 14: */ -#define CCM_ANALOG_PFD_480_PFD1_CLKGATE (1 << 15) /* Bit 15: If set to 1, the IO fractional divider clock is off */ -#define CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT (16) /* Bits 8-21: This field controls the fractional divide value */ -#define CCM_ANALOG_PFD_480_PFD2_FRAC_MASK (0x3f << CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT) -# define CCM_ANALOG_PFD_480_PFD2_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_482_PFD2_FRAC_SHIFT) -#define CCM_ANALOG_PFD_480_PFD2_STABLE (1 << 22) /* Bit 22: */ -#define CCM_ANALOG_PFD_480_PFD2_CLKGATE (1 << 23) /* Bit 23: If set to 1, the IO fractional divider clock is off */ -#define CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT (24) /* Bits 24-29: This field controls the fractional divide value */ -#define CCM_ANALOG_PFD_480_PFD3_FRAC_MASK (0x3f << CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT) -# define CCM_ANALOG_PFD_480_PFD3_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_482_PFD3_FRAC_SHIFT) -#define CCM_ANALOG_PFD_480_PFD3_STABLE (1 << 30) /* Bit 30: */ -#define CCM_ANALOG_PFD_480_PFD3_CLKGATE (1 << 31) /* Bit 31: If set to 1, the IO fractional divider clock is off */ - -/* 528MHz Clock (PLL2) Phase Fractional Divider Control */ - -#define CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT (0) /* Bits 0-5: This field controls the fractional divide value */ -#define CCM_ANALOG_PFD_528_PFD0_FRAC_MASK (0x3f << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT) -# define CCM_ANALOG_PFD_528_PFD0_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT) -#define CCM_ANALOG_PFD_528_PFD0_STABLE (1 << 6) /* Bit 6: */ -#define CCM_ANALOG_PFD_528_PFD0_CLKGATE (1 << 7) /* Bit 7: If set to 1, the IO fractional divider clock is off */ -#define CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT (8) /* Bits 8-13: This field controls the fractional divide value */ -#define CCM_ANALOG_PFD_528_PFD1_FRAC_MASK (0x3f << CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT) -# define CCM_ANALOG_PFD_528_PFD1_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_481_PFD1_FRAC_SHIFT) -#define CCM_ANALOG_PFD_528_PFD1_STABLE (1 << 14) /* Bit 14: */ -#define CCM_ANALOG_PFD_528_PFD1_CLKGATE (1 << 15) /* Bit 15: If set to 1, the IO fractional divider clock is off */ -#define CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT (16) /* Bits 8-21: This field controls the fractional divide value */ -#define CCM_ANALOG_PFD_528_PFD2_FRAC_MASK (0x3f << CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT) -# define CCM_ANALOG_PFD_528_PFD2_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_482_PFD2_FRAC_SHIFT) -#define CCM_ANALOG_PFD_528_PFD2_STABLE (1 << 22) /* Bit 22: */ -#define CCM_ANALOG_PFD_528_PFD2_CLKGATE (1 << 23) /* Bit 23: If set to 1, the IO fractional divider clock is off */ -#define CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT (24) /* Bits 24-29: This field controls the fractional divide value */ -#define CCM_ANALOG_PFD_528_PFD3_FRAC_MASK (0x3f << CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT) -# define CCM_ANALOG_PFD_528_PFD3_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_482_PFD3_FRAC_SHIFT) -#define CCM_ANALOG_PFD_528_PFD3_STABLE (1 << 30) /* Bit 30: */ -#define CCM_ANALOG_PFD_528_PFD3_CLKGATE (1 << 31) /* Bit 31: If set to 1, the IO fractional divider clock is off */ - -/* Miscellaneous Register 0 */ - -#define CCM_ANALOG_MISC0_REFTOP_PWD (1 << 0) /* Bit 0: Control bit to power-down the analog bandgap reference circuitry */ - /* Bits 1-2: Reserved */ -#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF (1 << 2) /* Bit 3: Control bit to disable the self-bias circuit in the analog bandgap */ -#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT (4) /* Bits 4-6: VBG (PMU) */ -#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK (0x7 << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT) -# define CCM_ANALOG_MISC0_REFTOP_VBGADJ(n) ((uint32_t)(n) << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT) -#define CCM_ANALOG_MISC0_REFTOP_VBGUP (1 << 7) /* Bit 7: Status bit that signals the analog bandgap voltage is up and stable */ - /* Bits 8-9: Reserved */ -#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT (10) /* Bits 10-11: Configure the analog behavior in stop mode */ -#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK (0x3 << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT) -# define CCM_ANALOG_MISC0_STOP_MODE_CONFIG(n) ((uint32_t)(n) << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT) -#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS (1 << 12) /* Bit 12: This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN */ -#define CCM_ANALOG_MISC0_OSC_I_SHIFT (13) /* Bits 13-14: This field determines the bias current in the 24MHz oscillator */ -#define CCM_ANALOG_MISC0_OSC_I_MASK (0x3 << CCM_ANALOG_MISC0_OSC_I_SHIFT) -# define CCM_ANALOG_MISC0_OSC_I(n) ((uint32_t)(n) << CCM_ANALOG_MISC0_OSC_I_SHIFT) -#define CCM_ANALOG_MISC0_OSC_XTALOK (1 << 15) /* Bit 15: bit that signals 24-MHz crystal oscillator is stable */ -#define CCM_ANALOG_MISC0_OSC_XTALOK_EN (1 << 16) /* Bit 16: enables the detector that signals 24MHz crystal oscillator is stable */ - /* Bits 17-24: Reserved */ -#define CCM_ANALOG_MISC0_CLKGATE_CTRL (1 << 25) /* Bit 25: This bit allows disabling the clock gate */ -#define CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT (26) /* Bits 26-28: delay powering up the XTAL 24MHz */ -#define CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK (0x7 << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT) -# define CCM_ANALOG_MISC0_CLKGATE_DELAY(n) ((uint32_t)(n) << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT) -#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE (1 << 29) /* Bit 29: which chip source is being used for the rtc clock */ -#define CCM_ANALOG_MISC0_XTAL_24M_PWD (1 << 30) /* Bit 30: power down the 24M crystal oscillator if set true */ - /* Bit 31: Reserved */ - -/* Miscellaneous Register 1 */ - - /* Bits 0-15: Reserved */ -#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN (1 << 16) /* Bit 16: */ -#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN (1 << 17) /* Bit 17: */ - /* Bits 18-26: Reserved */ -#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC (1 << 27) /* Bit 27: temperature sensor panic interrupt */ -#define CCM_ANALOG_MISC1_IRQ_TEMPLOW (1 << 28) /* Bit 28: temperature sensor low interrupt */ -#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH (1 << 29) /* Bit 29: temperature sensor high interrupt */ -#define CCM_ANALOG_MISC1_IRQ_ANA_BO (1 << 30) /* Bit 30: analog regulator brownout interrupt */ -#define CCM_ANALOG_MISC1_IRQ_DIG_BO (1 << 31) /* Bit 31: digital regulator brownout interrupt */ - -/* Miscellaneous Register 2 */ - /* Bit 0-4: Reserved */ -#define CCM_ANALOG_MISC2_REG0_ENABLE_BO (1 << 5) /* Bit 5: Enables the brownout detection */ -#define CCM_ANALOG_MISC2_REG0_OK (1 << 6) /* Bit 6: ARM supply */ -#define CCM_ANALOG_MISC2_PLL3_DISABLE (1 << 7) /* Bit 7: PLL3 can be disabled when the SoC is not in any low power mode */ -#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT (8) /* Bits 8-10: This field defines the brown out voltage offset */ -#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK (0x7 << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT) -# define CCM_ANALOG_MISC2_REG1_BO_OFFSET_0_100 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT) -# define CCM_ANALOG_MISC2_REG1_BO_OFFSET_0_175 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT) -#define CCM_ANALOG_MISC2_REG1_BO_STATUS (1 << 11) /* Bit 11: Reg1 brownout status bit */ - /* Bit 12: Reserved */ -#define CCM_ANALOG_MISC2_REG1_ENABLE_BO (1 << 13) /* Bit 13: Enables the brownout detection */ -#define CCM_ANALOG_MISC2_REG1_OK (1 << 14) /* Bit 14: GPU/VPU supply */ -#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB (1 << 15) /* Bit 15: LSB of Post-divider for Audio PLL */ - -#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT (16) /* Bits 16-18: This field defines the brown out voltage offset */ -#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK (0x7 << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT) -# define CCM_ANALOG_MISC2_REG2_BO_OFFSET_0_100 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT) -# define CCM_ANALOG_MISC2_REG2_BO_OFFSET_0_175 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT) -#define CCM_ANALOG_MISC2_REG2_BO_STATUS (1 << 19) /* Bit 19: Reg2 brownout status bit */ - /* Bit 20: Reserved */ -#define CCM_ANALOG_MISC2_REG2_ENABLE_BO (1 << 21) /* Bit 21: Enables the brownout detection */ -#define CCM_ANALOG_MISC2_REG2_OK (1 << 22) /* Bit 22: voltage is above the brownout level for the SOC supply */ -#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB (1 << 23) /* Bit 23: MSB of Post-divider for Audio PLL */ -#define CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT (24) /* Bits 24-25: Number of clock periods (24MHz clock) */ -#define CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK (0x3 << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC2_REG0_STEP_TIME_64 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC2_REG0_STEP_TIME_128 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC2_REG0_STEP_TIME_256 ((uint32_t)(2) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC2_REG0_STEP_TIME_512 ((uint32_t)(3) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT) -#define CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT (26) /* Bits 26-27: Number of clock periods (24MHz clock) */ -#define CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK (0x3 << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC2_REG1_STEP_TIME_64 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC2_REG1_STEP_TIME_128 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC2_REG1_STEP_TIME_256 ((uint32_t)(2) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC2_REG1_STEP_TIME_512 ((uint32_t)(3) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT) -#define CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT (28) /* Bits 28-29: Number of clock periods (24MHz clock) */ -#define CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK (0x3 << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC2_REG2_STEP_TIME_64 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC2_REG2_STEP_TIME_128 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC2_REG2_STEP_TIME_256 ((uint32_t)(2) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC2_REG2_STEP_TIME_512 ((uint32_t)(3) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT) - -#define CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT (30) /* Bits 30-31: Post-divider for video */ -#define CCM_ANALOG_MISC2_VIDEO_DIV_MASK (0x3 << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT) -# define CCM_ANALOG_MISC2_VIDEO_DIV(n) ((uint32_t)(n) << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT) - -#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_CCM_H */ diff --git a/arch/arm/src/imxrt/chip/rt102x/imxrt102x_dmamux.h b/arch/arm/src/imxrt/chip/rt102x/imxrt102x_dmamux.h deleted file mode 100644 index d83fa2bca63..00000000000 --- a/arch/arm/src/imxrt/chip/rt102x/imxrt102x_dmamux.h +++ /dev/null @@ -1,143 +0,0 @@ -/***************************************************************************** - * arch/arm/src/imxrt/chip/rt102x/imxrt102x_dmamux.h - * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Dave Marples - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_DMAMUX_H -#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_DMAMUX_H - -/***************************************************************************** - * Included Files - *****************************************************************************/ - -#include - -/***************************************************************************** - * Preprocessor Definitions - *****************************************************************************/ - -/* Peripheral DMA request channels */ - -#define IMXRT_DMACHAN_FLEXIO1_01 0 /* FlexIO1 DMA 0/1, Async DMA 0/1 */ -#define IMXRT_DMACHAN_FLEXIO1_45 1 /* FlexIO1 DMA 4/5, Async DMA 4/5 */ -#define IMXRT_DMACHAN_LPUART1_TX 2 /* LPUART1 TX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPUART1_RX 3 /* LPUART1 RX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPUART3_TX 4 /* LPUART3 RX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPUART3_RX 5 /* LPUART3 RX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPUART5_TX 6 /* LPUART5 TX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPUART5_RX 7 /* LPUART5 RX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPUART7_TX 8 /* LPUART7 TX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPUART7_RX 9 /* LPUART7 RX FIFO DMA / Async DMA */ - -#define IMXRT_DMACHAN_LPSPI1_RX 13 /* LPSPI1 RX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPSPI1_TX 14 /* LPSPI1 TX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPSPI3_RX 15 /* LPSPI3 RX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPSPI3_TX 16 /* LPSPI3 TX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPI2C1 17 /* LPI2C1 Master/Slave RX/TX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPI2C3 18 /* LPI2C3 Master/Slave RX/TX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_SAI1_RX 19 /* SAI1 RX FIFO DMA */ -#define IMXRT_DMACHAN_SAI1_TX 20 /* SAI1 TX FIFO DMA */ -#define IMXRT_DMACHAN_SAI2_RX 21 /* SAI2 RX FIFO DMA */ -#define IMXRT_DMACHAN_SAI2_TX 22 /* SAI2 TX FIFO DMA */ -#define IMXRT_DMACHAN_ADC_ETC 23 /* ADC ETC DMA */ -#define IMXRT_DMACHAN_ADC1 24 /* ADC1 DMA */ -#define IMXRT_DMACHAN_ACMP1 25 /* ACMP1 DMA */ -#define IMXRT_DMACHAN_ACMP3 26 /* ACMP3 DMA */ -#define IMXRT_DMACHAN_FLEXSPI_RX 28 /* FlexSPI RX FIFO DMA */ -#define IMXRT_DMACHAN_FLEXSPI_TX 29 /* FlexSPI TX FIFO DMA */ -#define IMXRT_DMACHAN_XBAR1_0 30 /* XBAR1 DMA 0 */ -#define IMXRT_DMACHAN_XBAR1_1 31 /* XBAR1 DMA 1 */ -#define IMXRT_DMACHAN_FLEXPWM1_RX0 32 /* FlexPWM1 RX sub-module0 capture */ -#define IMXRT_DMACHAN_FLEXPWM1_RX1 33 /* FlexPWM1 RX sub-module1 capture */ -#define IMXRT_DMACHAN_FLEXPWM1_RX2 34 /* FlexPWM1 RX sub-module2 capture */ -#define IMXRT_DMACHAN_FLEXPWM1_RX3 35 /* FlexPWM1 RX sub-module3 capture */ -#define IMXRT_DMACHAN_FLEXPWM1_TX0 36 /* FlexPWM1 TX sub-module0 value */ -#define IMXRT_DMACHAN_FLEXPWM1_TX1 37 /* FlexPWM1 TX sub-module1 value */ -#define IMXRT_DMACHAN_FLEXPWM1_TX2 38 /* FlexPWM1 TX sub-module2 value */ -#define IMXRT_DMACHAN_FLEXPWM1_TX3 39 /* FlexPWM1 TX sub-module3 value */ -#define IMXRT_DMACHAN_QTIMER1_RX0 48 /* QTimer1 RX capture timer 0 */ -#define IMXRT_DMACHAN_QTIMER1_RX1 49 /* QTimer1 RX capture timer 1 */ -#define IMXRT_DMACHAN_QTIMER1_RX2 50 /* QTimer1 RX capture timer 2 */ -#define IMXRT_DMACHAN_QTIMER1_RX3 51 /* QTimer1 RX capture timer 3 */ -#define IMXRT_DMACHAN_QTIMER1_TX0 52 /* QTimer1 TX cmpld1 timer 0 / cmld2 timer 1 */ -#define IMXRT_DMACHAN_QTIMER1_TX1 53 /* QTimer1 TX cmpld1 timer 1 / cmld2 timer 0 */ -#define IMXRT_DMACHAN_QTIMER1_TX2 54 /* QTimer1 TX cmpld1 timer 2 / cmld2 timer 3 */ -#define IMXRT_DMACHAN_QTIMER1_TX3 55 /* QTimer1 TX cmpld1 timer 3 / cmld2 timer 2 */ -#define IMXRT_DMACHAN_FLEXIO1_23 64 /* FlexIO1 DMA 2 / Async DMA 2 / DMA 3 / Async DMA 3 */ -#define IMXRT_DMACHAN_FLEXIO1_67 65 /* FlexIO1 DMA 6 / Async DMA 6 / DMA 7 / Async DMA 7 */ -#define IMXRT_DMACHAN_LPUART2_TX 66 /* LPUART2 TX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPUART2_RX 67 /* LPUART2 RX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPUART4_TX 68 /* LPUART4 TX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPUART4_RX 69 /* LPUART4 RX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPUART6_TX 70 /* LPUART6 TX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPUART6_RX 71 /* LPUART6 RX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPUART8_TX 72 /* LPUART8 TX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPUART8_RX 73 /* LPUART8 RX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPSPI2_RX 77 /* LPSPI2 RX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPSPI2_TX 78 /* LPSPI2 TX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPSPI4_RX 79 /* LPSPI4 RX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPSPI4_TX 80 /* LPSPI4 TX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPI2C2 81 /* LPI2C2 Master/Slave RX/TX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPI2C4 82 /* LPI2C4 Master/Slave RX/TX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_SAI3_RX 83 /* SAI3 RX FIFO DMA */ -#define IMXRT_DMACHAN_SAI3_TX 84 /* SAI3 RX FIFO DMA */ -#define IMXRT_DMACHAN_SPDIF_RX 85 /* SPDIF RX DMA */ -#define IMXRT_DMACHAN_SPDIF_TX 86 /* SPDIF TX DMA */ -#define IMXRT_DMACHAN_ADC2 88 /* ADC2 DMA */ -#define IMXRT_DMACHAN_ACMP2 89 /* ACMP2 DMA */ -#define IMXRT_DMACHAN_ACMP4 90 /* ACMP4 DMA */ -#define IMXRT_DMACHAN_ENET_0 92 /* ENET Timer DMA 0 */ -#define IMXRT_DMACHAN_ENET_1 93 /* ENET Timer DMA 1 */ -#define IMXRT_DMACHAN_XBAR1_2 94 /* XBAR1 DMA 2 */ -#define IMXRT_DMACHAN_XBAR1_3 95 /* XBAR1 DMA 3 */ -#define IMXRT_DMACHAN_FLEXPWM2_RX0 96 /* FlexPWM2 RX sub-module0 capture */ -#define IMXRT_DMACHAN_FLEXPWM2_RX1 97 /* FlexPWM2 RX sub-module1 capture */ -#define IMXRT_DMACHAN_FLEXPWM2_RX2 98 /* FlexPWM2 RX sub-module2 capture */ -#define IMXRT_DMACHAN_FLEXPWM2_RX3 99 /* FlexPWM2 RX sub-module3 capture */ -#define IMXRT_DMACHAN_FLEXPWM2_TX0 100 /* FlexPWM2 TX sub-module0 value */ -#define IMXRT_DMACHAN_FLEXPWM2_TX1 101 /* FlexPWM2 TX sub-module1 value */ -#define IMXRT_DMACHAN_FLEXPWM2_TX2 102 /* FlexPWM2 TX sub-module2 value */ -#define IMXRT_DMACHAN_FLEXPWM2_TX3 103 /* FlexPWM2 TX sub-module3 value */ -#define IMXRT_DMACHAN_QTIMER2_RX0 112 /* QTimer2 RX capture timer 0 */ -#define IMXRT_DMACHAN_QTIMER2_RX1 113 /* QTimer2 RX capture timer 1 */ -#define IMXRT_DMACHAN_QTIMER2_RX2 114 /* QTimer2 RX capture timer 2 */ -#define IMXRT_DMACHAN_QTIMER2_RX3 115 /* QTimer2 RX capture timer 3 */ -#define IMXRT_DMACHAN_QTIMER2_TX0 116 /* QTimer2 TX cmpld1 timer 0 / cmld2 timer 1 */ -#define IMXRT_DMACHAN_QTIMER2_TX1 117 /* QTimer2 TX cmpld1 timer 1 / cmld2 timer 0 */ -#define IMXRT_DMACHAN_QTIMER2_TX2 118 /* QTimer2 TX cmpld1 timer 2 / cmld2 timer 3 */ -#define IMXRT_DMACHAN_QTIMER2_TX3 119 /* QTimer2 TX cmpld1 timer 3 / cmld2 timer 2 */ - -#define IMXRT_DMA_NCHANNELS 128 /* Includes reserved channels */ - -#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_DMAMUX_H */ diff --git a/arch/arm/src/imxrt/chip/rt102x/imxrt102x_gpio.h b/arch/arm/src/imxrt/chip/rt102x/imxrt102x_gpio.h deleted file mode 100644 index fe288177cb6..00000000000 --- a/arch/arm/src/imxrt/chip/rt102x/imxrt102x_gpio.h +++ /dev/null @@ -1,116 +0,0 @@ -/***************************************************************************** - * arch/arm/src/imxrt/chip/rt102x/imxrt105x_gpio.h - * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * David Sidrane - * Dave Marples - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_GPIO_H -#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_GPIO_H - -/***************************************************************************** - * Included Files - *****************************************************************************/ - -#include -#include "chip/imxrt_memorymap.h" - -/***************************************************************************** - * Pre-processor Definitions - *****************************************************************************/ - -/* Register offsets **********************************************************/ - -#define IMXRT_GPIO_DR_OFFSET 0x0000 /* GPIO data register */ -#define IMXRT_GPIO_GDIR_OFFSET 0x0004 /* GPIO direction register */ -#define IMXRT_GPIO_PSR_OFFSET 0x0008 /* GPIO pad status register */ -#define IMXRT_GPIO_ICR1_OFFSET 0x000c /* GPIO interrupt configuration register1 */ -#define IMXRT_GPIO_ICR2_OFFSET 0x0010 /* GPIO interrupt configuration register2 */ -#define IMXRT_GPIO_IMR_OFFSET 0x0014 /* GPIO interrupt mask register */ -#define IMXRT_GPIO_ISR_OFFSET 0x0018 /* GPIO interrupt status register */ -#define IMXRT_GPIO_EDGE_OFFSET 0x001c /* GPIO edge select register */ -#define IMXRT_GPIO_SET_OFFSET 0x0084 /* GPIO data register SET */ -#define IMXRT_GPIO_CLEAR_OFFSET 0x0088 /* GPIO data register CLEAR */ -#define IMXRT_GPIO_TOGGLE_OFFSET 0x008c /* GPIO data register TOGGLE */ - -/* Register addresses ********************************************************/ - -#define IMXRT_GPIO1_DR (IMXRT_GPIO1_BASE + IMXRT_GPIO_DR_OFFSET) -#define IMXRT_GPIO1_GDIR (IMXRT_GPIO1_BASE + IMXRT_GPIO_GDIR_OFFSET) -#define IMXRT_GPIO1_PSR (IMXRT_GPIO1_BASE + IMXRT_GPIO_PSR_OFFSET) -#define IMXRT_GPIO1_ICR1 (IMXRT_GPIO1_BASE + IMXRT_GPIO_ICR1_OFFSET) -#define IMXRT_GPIO1_ICR2 (IMXRT_GPIO1_BASE + IMXRT_GPIO_ICR2_OFFSET) -#define IMXRT_GPIO1_IMR (IMXRT_GPIO1_BASE + IMXRT_GPIO_IMR_OFFSET) -#define IMXRT_GPIO1_ISR (IMXRT_GPIO1_BASE + IMXRT_GPIO_ISR_OFFSET) -#define IMXRT_GPIO1_EDGE (IMXRT_GPIO1_BASE + IMXRT_GPIO_EDGE_OFFSET) -#define IMXRT_GPIO1_SET (IMXRT_GPIO1_BASE + IMXRT_GPIO_SET_OFFSET) -#define IMXRT_GPIO1_CLEAR (IMXRT_GPIO1_BASE + IMXRT_GPIO_CLEAR_OFFSET) -#define IMXRT_GPIO1_TOGGLE (IMXRT_GPIO1_BASE + IMXRT_GPIO_TOGGLE_OFFSET) - -#define IMXRT_GPIO2_DR (IMXRT_GPIO2_BASE + IMXRT_GPIO_DR_OFFSET) -#define IMXRT_GPIO2_GDIR (IMXRT_GPIO2_BASE + IMXRT_GPIO_GDIR_OFFSET) -#define IMXRT_GPIO2_PSR (IMXRT_GPIO2_BASE + IMXRT_GPIO_PSR_OFFSET) -#define IMXRT_GPIO2_ICR1 (IMXRT_GPIO2_BASE + IMXRT_GPIO_ICR1_OFFSET) -#define IMXRT_GPIO2_ICR2 (IMXRT_GPIO2_BASE + IMXRT_GPIO_ICR2_OFFSET) -#define IMXRT_GPIO2_IMR (IMXRT_GPIO2_BASE + IMXRT_GPIO_IMR_OFFSET) -#define IMXRT_GPIO2_ISR (IMXRT_GPIO2_BASE + IMXRT_GPIO_ISR_OFFSET) -#define IMXRT_GPIO2_EDGE (IMXRT_GPIO2_BASE + IMXRT_GPIO_EDGE_OFFSET) -#define IMXRT_GPIO2_SET (IMXRT_GPIO2_BASE + IMXRT_GPIO_SET_OFFSET) -#define IMXRT_GPIO2_CLEAR (IMXRT_GPIO2_BASE + IMXRT_GPIO_CLEAR_OFFSET) -#define IMXRT_GPIO2_TOGGLE (IMXRT_GPIO2_BASE + IMXRT_GPIO_TOGGLE_OFFSET) - -#define IMXRT_GPIO3_DR (IMXRT_GPIO3_BASE + IMXRT_GPIO_DR_OFFSET) -#define IMXRT_GPIO3_GDIR (IMXRT_GPIO3_BASE + IMXRT_GPIO_GDIR_OFFSET) -#define IMXRT_GPIO3_PSR (IMXRT_GPIO3_BASE + IMXRT_GPIO_PSR_OFFSET) -#define IMXRT_GPIO3_ICR1 (IMXRT_GPIO3_BASE + IMXRT_GPIO_ICR1_OFFSET) -#define IMXRT_GPIO3_ICR2 (IMXRT_GPIO3_BASE + IMXRT_GPIO_ICR2_OFFSET) -#define IMXRT_GPIO3_IMR (IMXRT_GPIO3_BASE + IMXRT_GPIO_IMR_OFFSET) -#define IMXRT_GPIO3_ISR (IMXRT_GPIO3_BASE + IMXRT_GPIO_ISR_OFFSET) -#define IMXRT_GPIO3_EDGE (IMXRT_GPIO3_BASE + IMXRT_GPIO_EDGE_OFFSET) -#define IMXRT_GPIO3_SET (IMXRT_GPIO3_BASE + IMXRT_GPIO_SET_OFFSET) -#define IMXRT_GPIO3_CLEAR (IMXRT_GPIO3_BASE + IMXRT_GPIO_CLEAR_OFFSET) -#define IMXRT_GPIO3_TOGGLE (IMXRT_GPIO3_BASE + IMXRT_GPIO_TOGGLE_OFFSET) - -#define IMXRT_GPIO5_DR (IMXRT_GPIO5_BASE + IMXRT_GPIO_DR_OFFSET) -#define IMXRT_GPIO5_GDIR (IMXRT_GPIO5_BASE + IMXRT_GPIO_GDIR_OFFSET) -#define IMXRT_GPIO5_PSR (IMXRT_GPIO5_BASE + IMXRT_GPIO_PSR_OFFSET) -#define IMXRT_GPIO5_ICR1 (IMXRT_GPIO5_BASE + IMXRT_GPIO_ICR1_OFFSET) -#define IMXRT_GPIO5_ICR2 (IMXRT_GPIO5_BASE + IMXRT_GPIO_ICR2_OFFSET) -#define IMXRT_GPIO5_IMR (IMXRT_GPIO5_BASE + IMXRT_GPIO_IMR_OFFSET) -#define IMXRT_GPIO5_ISR (IMXRT_GPIO5_BASE + IMXRT_GPIO_ISR_OFFSET) -#define IMXRT_GPIO5_EDGE (IMXRT_GPIO5_BASE + IMXRT_GPIO_EDGE_OFFSET) -#define IMXRT_GPIO5_SET (IMXRT_GPIO5_BASE + IMXRT_GPIO_SET_OFFSET) -#define IMXRT_GPIO5_CLEAR (IMXRT_GPIO5_BASE + IMXRT_GPIO_CLEAR_OFFSET) -#define IMXRT_GPIO5_TOGGLE (IMXRT_GPIO5_BASE + IMXRT_GPIO_TOGGLE_OFFSET) - -#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_GPIO_H */ diff --git a/arch/arm/src/imxrt/chip/rt102x/imxrt102x_iomuxc.h b/arch/arm/src/imxrt/chip/rt102x/imxrt102x_iomuxc.h deleted file mode 100644 index 4d5f325b081..00000000000 --- a/arch/arm/src/imxrt/chip/rt102x/imxrt102x_iomuxc.h +++ /dev/null @@ -1,1606 +0,0 @@ -/**************************************************************************** - * arch/arm/src/imxrt/chip/rt102x/imxrt102x_iomuxc.h - * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * David Sidrane - * Dave Marples - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - *****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_IOMUXC_H -#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_IOMUXC_H - -/***************************************************************************** - * Included Files - *****************************************************************************/ - -#include -#include "chip/imxrt_memorymap.h" - -/***************************************************************************** - * Pre-processor Definitions - *****************************************************************************/ - -/* Register offsets **********************************************************/ - -#define IMXRT_IOMUXC_GPR_GPR0_OFFSET 0x0000 /* GPR0 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR1_OFFSET 0x0004 /* GPR1 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR2_OFFSET 0x0008 /* GPR2 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR3_OFFSET 0x000c /* GPR3 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR4_OFFSET 0x0010 /* GPR4 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR5_OFFSET 0x0014 /* GPR5 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR6_OFFSET 0x0018 /* GPR6 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR7_OFFSET 0x001c /* GPR7 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR8_OFFSET 0x0020 /* GPR8 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR9_OFFSET 0x0024 /* GPR9 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR10_OFFSET 0x0028 /* GPR10 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR11_OFFSET 0x002c /* GPR11 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR12_OFFSET 0x0030 /* GPR12 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR13_OFFSET 0x0034 /* GPR13 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR14_OFFSET 0x0038 /* GPR14 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR15_OFFSET 0x003c /* GPR15 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR16_OFFSET 0x0040 /* GPR16 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR17_OFFSET 0x0044 /* GPR17 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR18_OFFSET 0x0048 /* GPR18 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR19_OFFSET 0x004c /* GPR19 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR20_OFFSET 0x0050 /* GPR20 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR21_OFFSET 0x0054 /* GPR21 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR22_OFFSET 0x0058 /* GPR22 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR23_OFFSET 0x005c /* GPR23 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR24_OFFSET 0x0060 /* GPR24 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR25_OFFSET 0x0064 /* GPR25 General Purpose Register*/ - -#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_OFFSET 0x0000 /* SW_MUX_CTL_PAD_WAKEUP SW MUX Control Register */ -#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_OFFSET 0x0004 /* SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register */ -#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_OFFSET 0x0008 /* SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register */ -#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_OFFSET 0x000c /* SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register */ -#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_OFFSET 0x0010 /* SW_PAD_CTL_PAD_POR_B SW PAD Control Register */ -#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_OFFSET 0x0014 /* SW_PAD_CTL_PAD_ONOFF SW PAD Control Register */ -#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_OFFSET 0x0018 /* SW_PAD_CTL_PAD_WAKEUP SW PAD Control Register */ -#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_OFFSET 0x001c /* SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register */ -#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_OFFSET 0x0020 /* SW_PAD_CTL_PAD_PMIC_STBY_REQ SW PAD Control Register */ - -#define IMXRT_IOMUXC_SNVS_GPR_GPR0_OFFSET 0x0000 /* SNVC GPR0 General Purpose Register */ -#define IMXRT_IOMUXC_SNVS_GPR_GPR1_OFFSET 0x0004 /* SNVC GPR1 General Purpose Register */ -#define IMXRT_IOMUXC_SNVS_GPR_GPR2_OFFSET 0x0008 /* SNVC GPR2 General Purpose Register */ -#define IMXRT_IOMUXC_SNVS_GPR_GPR3_OFFSET 0x000c /* SNVC GPR3 General Purpose Register */ - -/* Pad Mux Register Indices (used by software for table lookups) */ - -#define IMXRT_PADMUX_GPIO_EMC_00_INDEX 0 -#define IMXRT_PADMUX_GPIO_EMC_01_INDEX 1 -#define IMXRT_PADMUX_GPIO_EMC_02_INDEX 2 -#define IMXRT_PADMUX_GPIO_EMC_03_INDEX 3 -#define IMXRT_PADMUX_GPIO_EMC_04_INDEX 4 -#define IMXRT_PADMUX_GPIO_EMC_05_INDEX 5 -#define IMXRT_PADMUX_GPIO_EMC_06_INDEX 6 -#define IMXRT_PADMUX_GPIO_EMC_07_INDEX 7 -#define IMXRT_PADMUX_GPIO_EMC_08_INDEX 8 -#define IMXRT_PADMUX_GPIO_EMC_09_INDEX 9 -#define IMXRT_PADMUX_GPIO_EMC_10_INDEX 10 -#define IMXRT_PADMUX_GPIO_EMC_11_INDEX 11 -#define IMXRT_PADMUX_GPIO_EMC_12_INDEX 12 -#define IMXRT_PADMUX_GPIO_EMC_13_INDEX 13 -#define IMXRT_PADMUX_GPIO_EMC_14_INDEX 14 -#define IMXRT_PADMUX_GPIO_EMC_15_INDEX 15 -#define IMXRT_PADMUX_GPIO_EMC_16_INDEX 16 -#define IMXRT_PADMUX_GPIO_EMC_17_INDEX 17 -#define IMXRT_PADMUX_GPIO_EMC_18_INDEX 18 -#define IMXRT_PADMUX_GPIO_EMC_19_INDEX 19 -#define IMXRT_PADMUX_GPIO_EMC_20_INDEX 20 -#define IMXRT_PADMUX_GPIO_EMC_21_INDEX 21 -#define IMXRT_PADMUX_GPIO_EMC_22_INDEX 22 -#define IMXRT_PADMUX_GPIO_EMC_23_INDEX 23 -#define IMXRT_PADMUX_GPIO_EMC_24_INDEX 24 -#define IMXRT_PADMUX_GPIO_EMC_25_INDEX 25 -#define IMXRT_PADMUX_GPIO_EMC_26_INDEX 26 -#define IMXRT_PADMUX_GPIO_EMC_27_INDEX 27 -#define IMXRT_PADMUX_GPIO_EMC_28_INDEX 28 -#define IMXRT_PADMUX_GPIO_EMC_29_INDEX 29 -#define IMXRT_PADMUX_GPIO_EMC_30_INDEX 30 -#define IMXRT_PADMUX_GPIO_EMC_31_INDEX 31 -#define IMXRT_PADMUX_GPIO_EMC_32_INDEX 32 -#define IMXRT_PADMUX_GPIO_EMC_33_INDEX 33 -#define IMXRT_PADMUX_GPIO_EMC_34_INDEX 34 -#define IMXRT_PADMUX_GPIO_EMC_35_INDEX 35 -#define IMXRT_PADMUX_GPIO_EMC_36_INDEX 36 -#define IMXRT_PADMUX_GPIO_EMC_37_INDEX 37 -#define IMXRT_PADMUX_GPIO_EMC_38_INDEX 38 -#define IMXRT_PADMUX_GPIO_EMC_39_INDEX 39 -#define IMXRT_PADMUX_GPIO_EMC_40_INDEX 40 -#define IMXRT_PADMUX_GPIO_EMC_41_INDEX 41 -#define IMXRT_PADMUX_GPIO_AD_B0_00_INDEX 42 -#define IMXRT_PADMUX_GPIO_AD_B0_01_INDEX 43 -#define IMXRT_PADMUX_GPIO_AD_B0_02_INDEX 44 -#define IMXRT_PADMUX_GPIO_AD_B0_03_INDEX 45 -#define IMXRT_PADMUX_GPIO_AD_B0_04_INDEX 46 -#define IMXRT_PADMUX_GPIO_AD_B0_05_INDEX 47 -#define IMXRT_PADMUX_GPIO_AD_B0_06_INDEX 48 -#define IMXRT_PADMUX_GPIO_AD_B0_07_INDEX 49 -#define IMXRT_PADMUX_GPIO_AD_B0_08_INDEX 50 -#define IMXRT_PADMUX_GPIO_AD_B0_09_INDEX 51 -#define IMXRT_PADMUX_GPIO_AD_B0_10_INDEX 52 -#define IMXRT_PADMUX_GPIO_AD_B0_11_INDEX 53 -#define IMXRT_PADMUX_GPIO_AD_B0_12_INDEX 54 -#define IMXRT_PADMUX_GPIO_AD_B0_13_INDEX 55 -#define IMXRT_PADMUX_GPIO_AD_B0_14_INDEX 56 -#define IMXRT_PADMUX_GPIO_AD_B0_15_INDEX 57 -#define IMXRT_PADMUX_GPIO_AD_B1_00_INDEX 58 -#define IMXRT_PADMUX_GPIO_AD_B1_01_INDEX 59 -#define IMXRT_PADMUX_GPIO_AD_B1_02_INDEX 60 -#define IMXRT_PADMUX_GPIO_AD_B1_03_INDEX 61 -#define IMXRT_PADMUX_GPIO_AD_B1_04_INDEX 62 -#define IMXRT_PADMUX_GPIO_AD_B1_05_INDEX 63 -#define IMXRT_PADMUX_GPIO_AD_B1_06_INDEX 64 -#define IMXRT_PADMUX_GPIO_AD_B1_07_INDEX 65 -#define IMXRT_PADMUX_GPIO_AD_B1_08_INDEX 66 -#define IMXRT_PADMUX_GPIO_AD_B1_09_INDEX 67 -#define IMXRT_PADMUX_GPIO_AD_B1_10_INDEX 68 -#define IMXRT_PADMUX_GPIO_AD_B1_11_INDEX 69 -#define IMXRT_PADMUX_GPIO_AD_B1_12_INDEX 70 -#define IMXRT_PADMUX_GPIO_AD_B1_13_INDEX 71 -#define IMXRT_PADMUX_GPIO_AD_B1_14_INDEX 72 -#define IMXRT_PADMUX_GPIO_AD_B1_15_INDEX 73 -#define IMXRT_PADMUX_GPIO_SD_B0_00_INDEX 74 -#define IMXRT_PADMUX_GPIO_SD_B0_01_INDEX 75 -#define IMXRT_PADMUX_GPIO_SD_B0_02_INDEX 76 -#define IMXRT_PADMUX_GPIO_SD_B0_03_INDEX 77 -#define IMXRT_PADMUX_GPIO_SD_B0_04_INDEX 78 -#define IMXRT_PADMUX_GPIO_SD_B0_05_INDEX 79 -#define IMXRT_PADMUX_GPIO_SD_B0_06_INDEX 80 -#define IMXRT_PADMUX_GPIO_SD_B1_00_INDEX 81 -#define IMXRT_PADMUX_GPIO_SD_B1_01_INDEX 82 -#define IMXRT_PADMUX_GPIO_SD_B1_02_INDEX 83 -#define IMXRT_PADMUX_GPIO_SD_B1_03_INDEX 84 -#define IMXRT_PADMUX_GPIO_SD_B1_04_INDEX 85 -#define IMXRT_PADMUX_GPIO_SD_B1_05_INDEX 86 -#define IMXRT_PADMUX_GPIO_SD_B1_06_INDEX 87 -#define IMXRT_PADMUX_GPIO_SD_B1_07_INDEX 88 -#define IMXRT_PADMUX_GPIO_SD_B1_08_INDEX 89 -#define IMXRT_PADMUX_GPIO_SD_B1_09_INDEX 90 -#define IMXRT_PADMUX_GPIO_SD_B1_10_INDEX 91 -#define IMXRT_PADMUX_GPIO_SD_B1_11_INDEX 92 -#define IMXRT_PADMUX_WAKEUP_INDEX 93 -#define IMXRT_PADMUX_PMIC_ON_REQ_INDEX 94 -#define IMXRT_PADMUX_PMIC_STBY_REQ_INDEX 95 - -#define IMXRT_PADMUX_NREGISTERS 96 - -/* Pad Mux Register Offsets */ - -#define IMXRT_PADMUX_OFFSET(n) (0x0014 + ((unsigned int)(n) << 2)) -#define IMXRT_PADMUX_OFFSET_SNVS(n) ((unsigned int)(n) << 2) - -#define IMXRT_PADMUX_GPIO_EMC_00_OFFSET 0x0014 -#define IMXRT_PADMUX_GPIO_EMC_01_OFFSET 0x0018 -#define IMXRT_PADMUX_GPIO_EMC_02_OFFSET 0x001c -#define IMXRT_PADMUX_GPIO_EMC_03_OFFSET 0x0020 -#define IMXRT_PADMUX_GPIO_EMC_04_OFFSET 0x0024 -#define IMXRT_PADMUX_GPIO_EMC_05_OFFSET 0x0028 -#define IMXRT_PADMUX_GPIO_EMC_06_OFFSET 0x002c -#define IMXRT_PADMUX_GPIO_EMC_07_OFFSET 0x0030 -#define IMXRT_PADMUX_GPIO_EMC_08_OFFSET 0x0034 -#define IMXRT_PADMUX_GPIO_EMC_09_OFFSET 0x0038 -#define IMXRT_PADMUX_GPIO_EMC_10_OFFSET 0x003c -#define IMXRT_PADMUX_GPIO_EMC_11_OFFSET 0x0040 -#define IMXRT_PADMUX_GPIO_EMC_12_OFFSET 0x0044 -#define IMXRT_PADMUX_GPIO_EMC_13_OFFSET 0x0048 -#define IMXRT_PADMUX_GPIO_EMC_14_OFFSET 0x004c -#define IMXRT_PADMUX_GPIO_EMC_15_OFFSET 0x0050 -#define IMXRT_PADMUX_GPIO_EMC_16_OFFSET 0x0054 -#define IMXRT_PADMUX_GPIO_EMC_17_OFFSET 0x0058 -#define IMXRT_PADMUX_GPIO_EMC_18_OFFSET 0x005c -#define IMXRT_PADMUX_GPIO_EMC_19_OFFSET 0x0060 -#define IMXRT_PADMUX_GPIO_EMC_20_OFFSET 0x0064 -#define IMXRT_PADMUX_GPIO_EMC_21_OFFSET 0x0068 -#define IMXRT_PADMUX_GPIO_EMC_22_OFFSET 0x006c -#define IMXRT_PADMUX_GPIO_EMC_23_OFFSET 0x0070 -#define IMXRT_PADMUX_GPIO_EMC_24_OFFSET 0x0074 -#define IMXRT_PADMUX_GPIO_EMC_25_OFFSET 0x0078 -#define IMXRT_PADMUX_GPIO_EMC_26_OFFSET 0x007c -#define IMXRT_PADMUX_GPIO_EMC_27_OFFSET 0x0080 -#define IMXRT_PADMUX_GPIO_EMC_28_OFFSET 0x0084 -#define IMXRT_PADMUX_GPIO_EMC_29_OFFSET 0x0088 -#define IMXRT_PADMUX_GPIO_EMC_30_OFFSET 0x008c -#define IMXRT_PADMUX_GPIO_EMC_31_OFFSET 0x0090 -#define IMXRT_PADMUX_GPIO_EMC_32_OFFSET 0x0094 -#define IMXRT_PADMUX_GPIO_EMC_33_OFFSET 0x0098 -#define IMXRT_PADMUX_GPIO_EMC_34_OFFSET 0x009c -#define IMXRT_PADMUX_GPIO_EMC_35_OFFSET 0x00a0 -#define IMXRT_PADMUX_GPIO_EMC_36_OFFSET 0x00a4 -#define IMXRT_PADMUX_GPIO_EMC_37_OFFSET 0x00a8 -#define IMXRT_PADMUX_GPIO_EMC_38_OFFSET 0x00ac -#define IMXRT_PADMUX_GPIO_EMC_39_OFFSET 0x00b0 -#define IMXRT_PADMUX_GPIO_EMC_40_OFFSET 0x00b4 -#define IMXRT_PADMUX_GPIO_EMC_41_OFFSET 0x00b8 -#define IMXRT_PADMUX_GPIO_AD_B0_00_OFFSET 0x00bc -#define IMXRT_PADMUX_GPIO_AD_B0_01_OFFSET 0x00c0 -#define IMXRT_PADMUX_GPIO_AD_B0_02_OFFSET 0x00c4 -#define IMXRT_PADMUX_GPIO_AD_B0_03_OFFSET 0x00c8 -#define IMXRT_PADMUX_GPIO_AD_B0_04_OFFSET 0x00cc -#define IMXRT_PADMUX_GPIO_AD_B0_05_OFFSET 0x00d0 -#define IMXRT_PADMUX_GPIO_AD_B0_06_OFFSET 0x00d4 -#define IMXRT_PADMUX_GPIO_AD_B0_07_OFFSET 0x00d8 -#define IMXRT_PADMUX_GPIO_AD_B0_08_OFFSET 0x00dc -#define IMXRT_PADMUX_GPIO_AD_B0_09_OFFSET 0x00e0 -#define IMXRT_PADMUX_GPIO_AD_B0_10_OFFSET 0x00e4 -#define IMXRT_PADMUX_GPIO_AD_B0_11_OFFSET 0x00e8 -#define IMXRT_PADMUX_GPIO_AD_B0_12_OFFSET 0x00ec -#define IMXRT_PADMUX_GPIO_AD_B0_13_OFFSET 0x00f0 -#define IMXRT_PADMUX_GPIO_AD_B0_14_OFFSET 0x00f4 -#define IMXRT_PADMUX_GPIO_AD_B0_15_OFFSET 0x00f8 -#define IMXRT_PADMUX_GPIO_AD_B1_00_OFFSET 0x00fc -#define IMXRT_PADMUX_GPIO_AD_B1_01_OFFSET 0x0100 -#define IMXRT_PADMUX_GPIO_AD_B1_02_OFFSET 0x0104 -#define IMXRT_PADMUX_GPIO_AD_B1_03_OFFSET 0x0108 -#define IMXRT_PADMUX_GPIO_AD_B1_04_OFFSET 0x010c -#define IMXRT_PADMUX_GPIO_AD_B1_05_OFFSET 0x0110 -#define IMXRT_PADMUX_GPIO_AD_B1_06_OFFSET 0x0114 -#define IMXRT_PADMUX_GPIO_AD_B1_07_OFFSET 0x0118 -#define IMXRT_PADMUX_GPIO_AD_B1_08_OFFSET 0x011c -#define IMXRT_PADMUX_GPIO_AD_B1_09_OFFSET 0x0120 -#define IMXRT_PADMUX_GPIO_AD_B1_10_OFFSET 0x0124 -#define IMXRT_PADMUX_GPIO_AD_B1_11_OFFSET 0x0128 -#define IMXRT_PADMUX_GPIO_AD_B1_12_OFFSET 0x012c -#define IMXRT_PADMUX_GPIO_AD_B1_13_OFFSET 0x0130 -#define IMXRT_PADMUX_GPIO_AD_B1_14_OFFSET 0x0134 -#define IMXRT_PADMUX_GPIO_AD_B1_15_OFFSET 0x0138 -#define IMXRT_PADMUX_GPIO_SD_B0_00_OFFSET 0x013c -#define IMXRT_PADMUX_GPIO_SD_B0_01_OFFSET 0x0140 -#define IMXRT_PADMUX_GPIO_SD_B0_02_OFFSET 0x0144 -#define IMXRT_PADMUX_GPIO_SD_B0_03_OFFSET 0x0148 -#define IMXRT_PADMUX_GPIO_SD_B0_04_OFFSET 0x014c -#define IMXRT_PADMUX_GPIO_SD_B0_05_OFFSET 0x0150 -#define IMXRT_PADMUX_GPIO_SD_B0_06_OFFSET 0x0154 -#define IMXRT_PADMUX_GPIO_SD_B1_00_OFFSET 0x0158 -#define IMXRT_PADMUX_GPIO_SD_B1_01_OFFSET 0x015c -#define IMXRT_PADMUX_GPIO_SD_B1_02_OFFSET 0x0160 -#define IMXRT_PADMUX_GPIO_SD_B1_03_OFFSET 0x0164 -#define IMXRT_PADMUX_GPIO_SD_B1_04_OFFSET 0x0168 -#define IMXRT_PADMUX_GPIO_SD_B1_05_OFFSET 0x016c -#define IMXRT_PADMUX_GPIO_SD_B1_06_OFFSET 0x0170 -#define IMXRT_PADMUX_GPIO_SD_B1_07_OFFSET 0x0174 -#define IMXRT_PADMUX_GPIO_SD_B1_08_OFFSET 0x0178 -#define IMXRT_PADMUX_GPIO_SD_B1_09_OFFSET 0x017c -#define IMXRT_PADMUX_GPIO_SD_B1_10_OFFSET 0x0180 -#define IMXRT_PADMUX_GPIO_SD_B1_11_OFFSET 0x0184 - -/* Pad Control Registers - * Pad Control Register Indices (used by software for table lookups) - */ - -#define IMXRT_PADCTL_GPIO_EMC_00_INDEX 0 -#define IMXRT_PADCTL_GPIO_EMC_01_INDEX 1 -#define IMXRT_PADCTL_GPIO_EMC_02_INDEX 2 -#define IMXRT_PADCTL_GPIO_EMC_03_INDEX 3 -#define IMXRT_PADCTL_GPIO_EMC_04_INDEX 4 -#define IMXRT_PADCTL_GPIO_EMC_05_INDEX 5 -#define IMXRT_PADCTL_GPIO_EMC_06_INDEX 6 -#define IMXRT_PADCTL_GPIO_EMC_07_INDEX 7 -#define IMXRT_PADCTL_GPIO_EMC_08_INDEX 8 -#define IMXRT_PADCTL_GPIO_EMC_09_INDEX 9 -#define IMXRT_PADCTL_GPIO_EMC_10_INDEX 10 -#define IMXRT_PADCTL_GPIO_EMC_11_INDEX 11 -#define IMXRT_PADCTL_GPIO_EMC_12_INDEX 12 -#define IMXRT_PADCTL_GPIO_EMC_13_INDEX 13 -#define IMXRT_PADCTL_GPIO_EMC_14_INDEX 14 -#define IMXRT_PADCTL_GPIO_EMC_15_INDEX 15 -#define IMXRT_PADCTL_GPIO_EMC_16_INDEX 16 -#define IMXRT_PADCTL_GPIO_EMC_17_INDEX 17 -#define IMXRT_PADCTL_GPIO_EMC_18_INDEX 18 -#define IMXRT_PADCTL_GPIO_EMC_19_INDEX 19 -#define IMXRT_PADCTL_GPIO_EMC_20_INDEX 20 -#define IMXRT_PADCTL_GPIO_EMC_21_INDEX 21 -#define IMXRT_PADCTL_GPIO_EMC_22_INDEX 22 -#define IMXRT_PADCTL_GPIO_EMC_23_INDEX 23 -#define IMXRT_PADCTL_GPIO_EMC_24_INDEX 24 -#define IMXRT_PADCTL_GPIO_EMC_25_INDEX 25 -#define IMXRT_PADCTL_GPIO_EMC_26_INDEX 26 -#define IMXRT_PADCTL_GPIO_EMC_27_INDEX 27 -#define IMXRT_PADCTL_GPIO_EMC_28_INDEX 28 -#define IMXRT_PADCTL_GPIO_EMC_29_INDEX 29 -#define IMXRT_PADCTL_GPIO_EMC_30_INDEX 30 -#define IMXRT_PADCTL_GPIO_EMC_31_INDEX 31 -#define IMXRT_PADCTL_GPIO_EMC_32_INDEX 32 -#define IMXRT_PADCTL_GPIO_EMC_33_INDEX 33 -#define IMXRT_PADCTL_GPIO_EMC_34_INDEX 34 -#define IMXRT_PADCTL_GPIO_EMC_35_INDEX 35 -#define IMXRT_PADCTL_GPIO_EMC_36_INDEX 36 -#define IMXRT_PADCTL_GPIO_EMC_37_INDEX 37 -#define IMXRT_PADCTL_GPIO_EMC_38_INDEX 38 -#define IMXRT_PADCTL_GPIO_EMC_39_INDEX 39 -#define IMXRT_PADCTL_GPIO_EMC_40_INDEX 40 -#define IMXRT_PADCTL_GPIO_EMC_41_INDEX 41 -#define IMXRT_PADCTL_GPIO_AD_B0_00_INDEX 42 -#define IMXRT_PADCTL_GPIO_AD_B0_01_INDEX 43 -#define IMXRT_PADCTL_GPIO_AD_B0_02_INDEX 44 -#define IMXRT_PADCTL_GPIO_AD_B0_03_INDEX 45 -#define IMXRT_PADCTL_GPIO_AD_B0_04_INDEX 46 -#define IMXRT_PADCTL_GPIO_AD_B0_05_INDEX 47 -#define IMXRT_PADCTL_GPIO_AD_B0_06_INDEX 48 -#define IMXRT_PADCTL_GPIO_AD_B0_07_INDEX 49 -#define IMXRT_PADCTL_GPIO_AD_B0_08_INDEX 50 -#define IMXRT_PADCTL_GPIO_AD_B0_09_INDEX 51 -#define IMXRT_PADCTL_GPIO_AD_B0_10_INDEX 52 -#define IMXRT_PADCTL_GPIO_AD_B0_11_INDEX 53 -#define IMXRT_PADCTL_GPIO_AD_B0_12_INDEX 54 -#define IMXRT_PADCTL_GPIO_AD_B0_13_INDEX 55 -#define IMXRT_PADCTL_GPIO_AD_B0_14_INDEX 56 -#define IMXRT_PADCTL_GPIO_AD_B0_15_INDEX 57 -#define IMXRT_PADCTL_GPIO_AD_B1_00_INDEX 58 -#define IMXRT_PADCTL_GPIO_AD_B1_01_INDEX 59 -#define IMXRT_PADCTL_GPIO_AD_B1_02_INDEX 60 -#define IMXRT_PADCTL_GPIO_AD_B1_03_INDEX 61 -#define IMXRT_PADCTL_GPIO_AD_B1_04_INDEX 62 -#define IMXRT_PADCTL_GPIO_AD_B1_05_INDEX 63 -#define IMXRT_PADCTL_GPIO_AD_B1_06_INDEX 64 -#define IMXRT_PADCTL_GPIO_AD_B1_07_INDEX 65 -#define IMXRT_PADCTL_GPIO_AD_B1_08_INDEX 66 -#define IMXRT_PADCTL_GPIO_AD_B1_09_INDEX 67 -#define IMXRT_PADCTL_GPIO_AD_B1_10_INDEX 68 -#define IMXRT_PADCTL_GPIO_AD_B1_11_INDEX 69 -#define IMXRT_PADCTL_GPIO_AD_B1_12_INDEX 70 -#define IMXRT_PADCTL_GPIO_AD_B1_13_INDEX 71 -#define IMXRT_PADCTL_GPIO_AD_B1_14_INDEX 72 -#define IMXRT_PADCTL_GPIO_AD_B1_15_INDEX 73 -#define IMXRT_PADCTL_GPIO_SD_B0_00_INDEX 74 -#define IMXRT_PADCTL_GPIO_SD_B0_01_INDEX 75 -#define IMXRT_PADCTL_GPIO_SD_B0_02_INDEX 76 -#define IMXRT_PADCTL_GPIO_SD_B0_03_INDEX 77 -#define IMXRT_PADCTL_GPIO_SD_B0_04_INDEX 78 -#define IMXRT_PADCTL_GPIO_SD_B0_05_INDEX 79 -#define IMXRT_PADCTL_GPIO_SD_B0_06_INDEX 80 -#define IMXRT_PADCTL_GPIO_SD_B1_00_INDEX 81 -#define IMXRT_PADCTL_GPIO_SD_B1_01_INDEX 82 -#define IMXRT_PADCTL_GPIO_SD_B1_02_INDEX 83 -#define IMXRT_PADCTL_GPIO_SD_B1_03_INDEX 84 -#define IMXRT_PADCTL_GPIO_SD_B1_04_INDEX 85 -#define IMXRT_PADCTL_GPIO_SD_B1_05_INDEX 86 -#define IMXRT_PADCTL_GPIO_SD_B1_06_INDEX 87 -#define IMXRT_PADCTL_GPIO_SD_B1_07_INDEX 88 -#define IMXRT_PADCTL_GPIO_SD_B1_08_INDEX 89 -#define IMXRT_PADCTL_GPIO_SD_B1_09_INDEX 90 -#define IMXRT_PADCTL_GPIO_SD_B1_10_INDEX 91 -#define IMXRT_PADCTL_GPIO_SD_B1_11_INDEX 92 - -#define IMXRT_PADCTL_WAKEUP_INDEX 93 -#define IMXRT_PADCTL_PMIC_ON_REQ_INDEX 94 -#define IMXRT_PADCTL_PMIC_STBY_REQ_INDEX 95 - -#define IMXRT_PADCTL_NREGISTERS 96 - -/* Pad Control Register Offsets */ - -#define IMXRT_PADCTL_OFFSET(n) (0x0188 + ((unsigned int)(n) << 2)) -#define IMXRT_PADCTL_OFFSET_SNVS(n) (0x18 + ((unsigned int)(n-IMXRT_PADCTL_WAKEUP_INDEX) << 2)) - -#define IMXRT_PADCTL_GPIO_EMC_00_OFFSET 0x0188 -#define IMXRT_PADCTL_GPIO_EMC_01_OFFSET 0x018c -#define IMXRT_PADCTL_GPIO_EMC_02_OFFSET 0x0190 -#define IMXRT_PADCTL_GPIO_EMC_03_OFFSET 0x0194 -#define IMXRT_PADCTL_GPIO_EMC_04_OFFSET 0x0198 -#define IMXRT_PADCTL_GPIO_EMC_05_OFFSET 0x019c -#define IMXRT_PADCTL_GPIO_EMC_06_OFFSET 0x01a0 -#define IMXRT_PADCTL_GPIO_EMC_07_OFFSET 0x01a4 -#define IMXRT_PADCTL_GPIO_EMC_08_OFFSET 0x01a8 -#define IMXRT_PADCTL_GPIO_EMC_09_OFFSET 0x01ac -#define IMXRT_PADCTL_GPIO_EMC_10_OFFSET 0x01b0 -#define IMXRT_PADCTL_GPIO_EMC_11_OFFSET 0x01b4 -#define IMXRT_PADCTL_GPIO_EMC_12_OFFSET 0x01b8 -#define IMXRT_PADCTL_GPIO_EMC_13_OFFSET 0x01bc -#define IMXRT_PADCTL_GPIO_EMC_14_OFFSET 0x01c0 -#define IMXRT_PADCTL_GPIO_EMC_15_OFFSET 0x01c4 -#define IMXRT_PADCTL_GPIO_EMC_16_OFFSET 0x01c8 -#define IMXRT_PADCTL_GPIO_EMC_17_OFFSET 0x01cc -#define IMXRT_PADCTL_GPIO_EMC_18_OFFSET 0x01d0 -#define IMXRT_PADCTL_GPIO_EMC_19_OFFSET 0x01d4 -#define IMXRT_PADCTL_GPIO_EMC_20_OFFSET 0x01d8 -#define IMXRT_PADCTL_GPIO_EMC_21_OFFSET 0x01dc -#define IMXRT_PADCTL_GPIO_EMC_22_OFFSET 0x01e0 -#define IMXRT_PADCTL_GPIO_EMC_23_OFFSET 0x01e4 -#define IMXRT_PADCTL_GPIO_EMC_24_OFFSET 0x01e8 -#define IMXRT_PADCTL_GPIO_EMC_25_OFFSET 0x01ec -#define IMXRT_PADCTL_GPIO_EMC_26_OFFSET 0x01f0 -#define IMXRT_PADCTL_GPIO_EMC_27_OFFSET 0x01f4 -#define IMXRT_PADCTL_GPIO_EMC_28_OFFSET 0x01f8 -#define IMXRT_PADCTL_GPIO_EMC_29_OFFSET 0x01fc -#define IMXRT_PADCTL_GPIO_EMC_30_OFFSET 0x0200 -#define IMXRT_PADCTL_GPIO_EMC_31_OFFSET 0x0204 -#define IMXRT_PADCTL_GPIO_EMC_32_OFFSET 0x0208 -#define IMXRT_PADCTL_GPIO_EMC_33_OFFSET 0x020c -#define IMXRT_PADCTL_GPIO_EMC_34_OFFSET 0x0210 -#define IMXRT_PADCTL_GPIO_EMC_35_OFFSET 0x0214 -#define IMXRT_PADCTL_GPIO_EMC_36_OFFSET 0x0218 -#define IMXRT_PADCTL_GPIO_EMC_37_OFFSET 0x021c -#define IMXRT_PADCTL_GPIO_EMC_38_OFFSET 0x0220 -#define IMXRT_PADCTL_GPIO_EMC_39_OFFSET 0x0224 -#define IMXRT_PADCTL_GPIO_EMC_40_OFFSET 0x0228 -#define IMXRT_PADCTL_GPIO_EMC_41_OFFSET 0x022c -#define IMXRT_PADCTL_GPIO_AD_B0_00_OFFSET 0x0230 -#define IMXRT_PADCTL_GPIO_AD_B0_01_OFFSET 0x0234 -#define IMXRT_PADCTL_GPIO_AD_B0_02_OFFSET 0x0238 -#define IMXRT_PADCTL_GPIO_AD_B0_03_OFFSET 0x023c -#define IMXRT_PADCTL_GPIO_AD_B0_04_OFFSET 0x0240 -#define IMXRT_PADCTL_GPIO_AD_B0_05_OFFSET 0x0244 -#define IMXRT_PADCTL_GPIO_AD_B0_06_OFFSET 0x0248 -#define IMXRT_PADCTL_GPIO_AD_B0_07_OFFSET 0x024c -#define IMXRT_PADCTL_GPIO_AD_B0_08_OFFSET 0x0250 -#define IMXRT_PADCTL_GPIO_AD_B0_09_OFFSET 0x0254 -#define IMXRT_PADCTL_GPIO_AD_B0_10_OFFSET 0x0258 -#define IMXRT_PADCTL_GPIO_AD_B0_11_OFFSET 0x025c -#define IMXRT_PADCTL_GPIO_AD_B0_12_OFFSET 0x0260 -#define IMXRT_PADCTL_GPIO_AD_B0_13_OFFSET 0x0264 -#define IMXRT_PADCTL_GPIO_AD_B0_14_OFFSET 0x0268 -#define IMXRT_PADCTL_GPIO_AD_B0_15_OFFSET 0x026c -#define IMXRT_PADCTL_GPIO_AD_B1_00_OFFSET 0x0270 -#define IMXRT_PADCTL_GPIO_AD_B1_01_OFFSET 0x0274 -#define IMXRT_PADCTL_GPIO_AD_B1_02_OFFSET 0x0278 -#define IMXRT_PADCTL_GPIO_AD_B1_03_OFFSET 0x027c -#define IMXRT_PADCTL_GPIO_AD_B1_04_OFFSET 0x0280 -#define IMXRT_PADCTL_GPIO_AD_B1_05_OFFSET 0x0284 -#define IMXRT_PADCTL_GPIO_AD_B1_06_OFFSET 0x0288 -#define IMXRT_PADCTL_GPIO_AD_B1_07_OFFSET 0x028c -#define IMXRT_PADCTL_GPIO_AD_B1_08_OFFSET 0x0290 -#define IMXRT_PADCTL_GPIO_AD_B1_09_OFFSET 0x0294 -#define IMXRT_PADCTL_GPIO_AD_B1_10_OFFSET 0x0298 -#define IMXRT_PADCTL_GPIO_AD_B1_11_OFFSET 0x029c -#define IMXRT_PADCTL_GPIO_AD_B1_12_OFFSET 0x02a0 -#define IMXRT_PADCTL_GPIO_AD_B1_13_OFFSET 0x02a4 -#define IMXRT_PADCTL_GPIO_AD_B1_14_OFFSET 0x02a8 -#define IMXRT_PADCTL_GPIO_AD_B1_15_OFFSET 0x02ac -#define IMXRT_PADCTL_GPIO_SD_B0_00_OFFSET 0x02b0 -#define IMXRT_PADCTL_GPIO_SD_B0_01_OFFSET 0x02b4 -#define IMXRT_PADCTL_GPIO_SD_B0_02_OFFSET 0x02b8 -#define IMXRT_PADCTL_GPIO_SD_B0_03_OFFSET 0x02bc -#define IMXRT_PADCTL_GPIO_SD_B0_04_OFFSET 0x02c0 -#define IMXRT_PADCTL_GPIO_SD_B0_05_OFFSET 0x02c4 -#define IMXRT_PADCTL_GPIO_SD_B0_06_OFFSET 0x02c8 -#define IMXRT_PADCTL_GPIO_SD_B1_00_OFFSET 0x02cc -#define IMXRT_PADCTL_GPIO_SD_B1_01_OFFSET 0x02d0 -#define IMXRT_PADCTL_GPIO_SD_B1_02_OFFSET 0x02d4 -#define IMXRT_PADCTL_GPIO_SD_B1_03_OFFSET 0x02d8 -#define IMXRT_PADCTL_GPIO_SD_B1_04_OFFSET 0x02dc -#define IMXRT_PADCTL_GPIO_SD_B1_05_OFFSET 0x02e0 -#define IMXRT_PADCTL_GPIO_SD_B1_06_OFFSET 0x02e4 -#define IMXRT_PADCTL_GPIO_SD_B1_07_OFFSET 0x02e8 -#define IMXRT_PADCTL_GPIO_SD_B1_08_OFFSET 0x02ec -#define IMXRT_PADCTL_GPIO_SD_B1_09_OFFSET 0x02f0 -#define IMXRT_PADCTL_GPIO_SD_B1_10_OFFSET 0x02f4 -#define IMXRT_PADCTL_GPIO_SD_B1_11_OFFSET 0x02f8 - -/* Select Input Daisy Register Offsets */ - -#define IMXRT_INPUT_INDEX2OFFSET(n) (0x02fc + ((unsigned int)(n) << 2)) -#define IMXRT_INPUT_OFFSET2INDEX(o) (((unsigned int)(o) - 0x02fc) >> 2) - -#define IMXRT_INPUT_ANATOP_USB_OTG1_ID_OFFSET 0x02fc -#define IMXRT_INPUT_CCM_PMIC_READY_OFFSET 0x0300 -#define IMXRT_INPUT_ENET_IPG_CLK_RMII_OFFSET 0x0304 -#define IMXRT_INPUT_ENET_MDIO_OFFSET 0x0308 -#define IMXRT_INPUT_ENET_RXDATA0_OFFSET 0x030c -#define IMXRT_INPUT_ENET_RXDATA1_OFFSET 0x0310 -#define IMXRT_INPUT_ENET_RXEN_OFFSET 0x0314 -#define IMXRT_INPUT_ENET_RXERR_OFFSET 0x0318 -#define IMXRT_INPUT_ENET_TXCLK_OFFSET 0x031c -#define IMXRT_INPUT_FLEXCAN1_RX_OFFSET 0x0320 -#define IMXRT_INPUT_FLEXCAN2_RX_OFFSET 0x0324 -#define IMXRT_INPUT_FLEXPWM1_PWMA0_OFFSET 0x0328 -#define IMXRT_INPUT_FLEXPWM1_PWMA1_OFFSET 0x032c -#define IMXRT_INPUT_FLEXPWM1_PWMA2_OFFSET 0x0330 -#define IMXRT_INPUT_FLEXPWM1_PWMA3_OFFSET 0x0334 -#define IMXRT_INPUT_FLEXPWM1_PWMB0_OFFSET 0x0338 -#define IMXRT_INPUT_FLEXPWM1_PWMB1_OFFSET 0x033c -#define IMXRT_INPUT_FLEXPWM1_PWMB2_OFFSET 0x0340 -#define IMXRT_INPUT_FLEXPWM1_PWMB3_OFFSET 0x0344 -#define IMXRT_INPUT_FLEXPWM2_PWMA0_OFFSET 0x0348 -#define IMXRT_INPUT_FLEXPWM2_PWMA1_OFFSET 0x034c -#define IMXRT_INPUT_FLEXPWM2_PWMA2_OFFSET 0x0350 -#define IMXRT_INPUT_FLEXPWM2_PWMA3_OFFSET 0x0354 -#define IMXRT_INPUT_FLEXPWM2_PWMB0_OFFSET 0x0358 -#define IMXRT_INPUT_FLEXPWM2_PWMB1_OFFSET 0x035c -#define IMXRT_INPUT_FLEXPWM2_PWMB2_OFFSET 0x0360 -#define IMXRT_INPUT_FLEXPWM2_PWMB3_OFFSET 0x0364 -#define IMXRT_INPUT_FLEXSPIA_DATA0_OFFSET 0x0368 -#define IMXRT_INPUT_FLEXSPIA_DATA1_OFFSET 0x036c -#define IMXRT_INPUT_FLEXSPIA_DATA2_OFFSET 0x0370 -#define IMXRT_INPUT_FLEXSPIA_DATA3_OFFSET 0x0374 -#define IMXRT_INPUT_FLEXSPIA_SCK_OFFSET 0x0378 -#define IMXRT_INPUT_LPI2C1_SCL_OFFSET 0x037c -#define IMXRT_INPUT_LPI2C1_SDA_OFFSET 0x0380 -#define IMXRT_INPUT_LPI2C2_SCL_OFFSET 0x0384 -#define IMXRT_INPUT_LPI2C2_SDA_OFFSET 0x0388 -#define IMXRT_INPUT_LPI2C3_SCL_OFFSET 0x038c -#define IMXRT_INPUT_LPI2C3_SDA_OFFSET 0x0390 -#define IMXRT_INPUT_LPI2C4_SCL_OFFSET 0x0394 -#define IMXRT_INPUT_LPI2C4_SDA_OFFSET 0x0398 -#define IMXRT_INPUT_LPSPI1_PCS0_OFFSET 0x039c -#define IMXRT_INPUT_LPSPI1_SCK_OFFSET 0x03a0 -#define IMXRT_INPUT_LPSPI1_SDI_OFFSET 0x03a4 -#define IMXRT_INPUT_LPSPI1_SDO_OFFSET 0x03a8 -#define IMXRT_INPUT_LPSPI2_PCS0_OFFSET 0x03ac -#define IMXRT_INPUT_LPSPI2_SCK_OFFSET 0x03b0 -#define IMXRT_INPUT_LPSPI2_SDI_OFFSET 0x03b4 -#define IMXRT_INPUT_LPSPI2_SDO_OFFSET 0x03b8 -#define IMXRT_INPUT_LPSPI4_PCS0_OFFSET 0x03bc -#define IMXRT_INPUT_LPSPI4_SCK_OFFSET 0x03c0 -#define IMXRT_INPUT_LPSPI4_SDI_OFFSET 0x03c4 -#define IMXRT_INPUT_LPSPI4_SDO_OFFSET 0x03c8 -#define IMXRT_INPUT_LPUART3_CTS_B_OFFSET 0x03cc -#define IMXRT_INPUT_LPUART2_RX_OFFSET 0x03d0 -#define IMXRT_INPUT_LPUART2_TX_OFFSET 0x03d4 -#define IMXRT_INPUT_LPUART3_RX_OFFSET 0x03d8 -#define IMXRT_INPUT_LPUART3_TX_OFFSET 0x03dc -#define IMXRT_INPUT_LPUART4_CTS_B_OFFSET 0x03e0 -#define IMXRT_INPUT_LPUART4_RX_OFFSET 0x03e4 -#define IMXRT_INPUT_LPUART4_TX_OFFSET 0x03e8 -#define IMXRT_INPUT_LPUART5_RX_OFFSET 0x03ec -#define IMXRT_INPUT_LPUART5_TX_OFFSET 0x03f0 -#define IMXRT_INPUT_LPUART6_RX_OFFSET 0x03f4 -#define IMXRT_INPUT_LPUART6_TX_OFFSET 0x03f8 -#define IMXRT_INPUT_LPUART7_RX_OFFSET 0x03fc -#define IMXRT_INPUT_LPUART7_TX_OFFSET 0x0400 -#define IMXRT_INPUT_LPUART8_RX_OFFSET 0x0404 -#define IMXRT_INPUT_LPUART8_TX_OFFSET 0x0408 -#define IMXRT_INPUT_NMI_GLUE_NMI_OFFSET 0x040c -#define IMXRT_INPUT_QTIMER1_TIMER0_OFFSET 0x0410 -#define IMXRT_INPUT_QTIMER1_TIMER1_OFFSET 0x0414 -#define IMXRT_INPUT_QTIMER1_TIMER2_OFFSET 0x0418 -#define IMXRT_INPUT_QTIMER1_TIMER3_OFFSET 0x041c -#define IMXRT_INPUT_QTIMER2_TIMER0_OFFSET 0x0420 -#define IMXRT_INPUT_QTIMER2_TIMER1_OFFSET 0x0424 -#define IMXRT_INPUT_QTIMER2_TIMER2_OFFSET 0x0428 -#define IMXRT_INPUT_QTIMER2_TIMER3_OFFSET 0x042c -#define IMXRT_INPUT_SAI1_MCLK_OFFSET 0x0430 -#define IMXRT_INPUT_SAI1_RX_BCLK_OFFSET 0x0434 -#define IMXRT_INPUT_SAI1_RX_DATA0_OFFSET 0x0438 -#define IMXRT_INPUT_SAI1_RX_DATA1_OFFSET 0x043c -#define IMXRT_INPUT_SAI1_RX_DATA2_OFFSET 0x0440 -#define IMXRT_INPUT_SAI1_RX_DATA3_OFFSET 0x0444 -#define IMXRT_INPUT_SAI1_RX_SYNC_OFFSET 0x0448 -#define IMXRT_INPUT_SAI1_TX_BCLK_OFFSET 0x044c -#define IMXRT_INPUT_SAI1_TX_SYNC_OFFSET 0x0450 -#define IMXRT_INPUT_SAI2_MCLK_OFFSET 0x0454 -#define IMXRT_INPUT_SAI2_RX_BCLK_OFFSET 0x0458 -#define IMXRT_INPUT_SAI2_RX_DATA0_OFFSET 0x045c -#define IMXRT_INPUT_SAI2_RX_SYNC_OFFSET 0x0460 -#define IMXRT_INPUT_SAI2_TX_BCLK_OFFSET 0x0464 -#define IMXRT_INPUT_SAI2_TX_SYNC_OFFSET 0x0468 -#define IMXRT_INPUT_SAI3_MCLK_OFFSET 0x046c -#define IMXRT_INPUT_SAI3_RX_BCLK_OFFSET 0x0470 -#define IMXRT_INPUT_SAI3_RX_DATA0_OFFSET 0x0474 -#define IMXRT_INPUT_SAI3_RX_SYNC_OFFSET 0x0478 -#define IMXRT_INPUT_SAI3_TX_BCLK_OFFSET 0x047c -#define IMXRT_INPUT_SAI3_TX_SYNC_OFFSET 0x0480 -#define IMXRT_INPUT_SEMC_READY_OFFSET 0x0484 -#define IMXRT_INPUT_SPDIF_IN_OFFSET 0x0488 -#define IMXRT_INPUT_USB_OTG1_OC_OFFSET 0x048c -#define IMXRT_INPUT_USDHC1_CD_B_OFFSET 0x0490 -#define IMXRT_INPUT_USDHC1_WP_OFFSET 0x0494 -#define IMXRT_INPUT_USDHC2_CD_B_OFFSET 0x0498 -#define IMXRT_INPUT_USDHC2_CMD_OFFSET 0x049c -#define IMXRT_INPUT_XBAR1_IN14_OFFSET 0x04a0 -#define IMXRT_INPUT_XBAR1_IN15_OFFSET 0x04a4 -#define IMXRT_INPUT_XBAR1_IN16_OFFSET 0x04a8 -#define IMXRT_INPUT_XBAR1_IN17_OFFSET 0x04ac -#define IMXRT_INPUT_XBAR1_IN10_OFFSET 0x04b0 -#define IMXRT_INPUT_XBAR1_IN12_OFFSET 0x04b4 -#define IMXRT_INPUT_XBAR1_IN13_OFFSET 0x04b8 -#define IMXRT_INPUT_XBAR1_IN18_OFFSET 0x04bc -#define IMXRT_INPUT_XBAR1_IN19_OFFSET 0x04c0 - -/* Register addresses ********************************************************/ - -#define IMXRT_IOMUXC_GPR_GPR0 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR0_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR1 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR1_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR2 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR2_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR3 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR3_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR4 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR4_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR5 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR5_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR6 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR6_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR7 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR7_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR8 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR8_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR9 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR9_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR10 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR10_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR11 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR11_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR12 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR12_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR13 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR13_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR14 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR14_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR15 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR15_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR16 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR16_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR17 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR17_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR18 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR18_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR19 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR19_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR20 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR20_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR21 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR21_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR22 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR22_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR23 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR23_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR24 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR24_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR25 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR25_OFFSET) - -#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_OFFSET) -#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_OFFSET) -#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_OFFSET) -#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_OFFSET) -#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_OFFSET) -#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_OFFSET) -#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_OFFSET) -#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_OFFSET) -#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_OFFSET) - -#define IMXRT_IOMUXC_SNVS_GPR_GPR0 (IMXRT_IOMUXCSNVSGPR_BASE + IMXRT_IOMUXC_SNVS_GPR_GPR0_OFFSET) -#define IMXRT_IOMUXC_SNVS_GPR_GPR1 (IMXRT_IOMUXCSNVSGPR_BASE + IMXRT_IOMUXC_SNVS_GPR_GPR1_OFFSET) -#define IMXRT_IOMUXC_SNVS_GPR_GPR2 (IMXRT_IOMUXCSNVSGPR_BASE + IMXRT_IOMUXC_SNVS_GPR_GPR2_OFFSET) -#define IMXRT_IOMUXC_SNVS_GPR_GPR3 (IMXRT_IOMUXCSNVSGPR_BASE + IMXRT_IOMUXC_SNVS_GPR_GPR3_OFFSET) - -/* Pad Mux Registers */ - -#define IMXRT_PADMUX_ADDRESS(n) (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_OFFSET(n)) -#define IMXRT_PADMUX_ADDRESS_SNVS(n) (IMXRT_IOMUXCSNVS_BASE + IMXRT_PADMUX_OFFSET_SNVS(n)) - -#define IMXRT_PADMUX_GPIO_EMC_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_00_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_01_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_02_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_03_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_04_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_05_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_06_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_07 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_07_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_08 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_08_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_09 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_09_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_10 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_10_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_11 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_11_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_12 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_12_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_13 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_13_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_14 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_14_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_15 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_15_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_16 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_16_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_17 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_17_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_18 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_18_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_19 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_19_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_20 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_20_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_21 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_21_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_22 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_22_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_23 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_23_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_24 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_24_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_25 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_25_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_26 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_26_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_27 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_27_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_28 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_28_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_29 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_29_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_30 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_30_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_31 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_31_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_32 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_32_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_33 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_33_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_34 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_34_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_35 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_35_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_36 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_36_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_37 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_37_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_38 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_38_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_39 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_39_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_40 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_40_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_41 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_41_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_00_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_01_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_02_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_03_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_04_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_05_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_06_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_07 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_07_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_08 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_08_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_09 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_09_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_10 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_10_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_11 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_11_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_12 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_12_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_13 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_13_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_14 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_14_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_15 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_15_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_00_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_01_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_02_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_03_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_04_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_05_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_06_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_07 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_07_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_08 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_08_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_09 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_09_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_10 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_10_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_11 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_11_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_12 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_12_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_13 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_13_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_14 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_14_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_15 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_15_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B0_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_00_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B0_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_01_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B0_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_02_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B0_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_03_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B0_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_04_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B0_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_05_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B0_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_06_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B1_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_00_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B1_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_01_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B1_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_02_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B1_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_03_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B1_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_04_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B1_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_05_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B1_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_06_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B1_07 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_07_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B1_08 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_08_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B1_09 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_09_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B1_10 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_10_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B1_11 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_11_OFFSET) - -/* Pad Control Registers */ - -#define IMXRT_PADCTL_ADDRESS(n) (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_OFFSET(n)) -#define IMXRT_PADCTL_ADDRESS_SNVS(n) (IMXRT_IOMUXCSNVS_BASE + IMXRT_PADCTL_OFFSET_SNVS(n)) - -#define IMXRT_PADCTL_GPIO_EMC_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_00_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_01_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_02_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_03_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_04_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_05_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_06_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_07 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_07_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_08 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_08_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_09 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_09_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_10 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_10_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_11 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_11_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_12 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_12_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_13 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_13_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_14 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_14_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_15 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_15_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_16 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_16_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_17 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_17_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_18 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_18_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_19 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_19_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_20 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_20_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_21 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_21_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_22 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_22_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_23 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_23_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_24 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_24_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_25 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_25_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_26 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_26_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_27 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_27_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_28 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_28_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_29 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_29_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_30 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_30_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_31 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_31_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_32 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_32_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_33 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_33_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_34 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_34_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_35 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_35_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_36 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_36_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_37 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_37_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_38 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_38_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_39 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_39_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_40 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_40_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_41 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_41_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_00_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_01_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_02_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_03_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_04_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_05_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_06_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_07 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_07_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_08 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_08_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_09 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_09_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_10 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_10_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_11 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_11_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_12 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_12_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_13 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_13_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_14 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_14_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_15 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_15_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_00_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_01_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_02_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_03_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_04_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_05_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_06_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_07 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_07_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_08 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_08_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_09 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_09_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_10 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_10_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_11 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_11_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_12 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_12_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_13 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_13_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_14 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_14_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_15 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_15_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B0_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_00_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B0_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_01_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B0_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_02_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B0_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_03_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B0_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_04_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B0_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_05_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B0_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_06_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B1_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_00_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B1_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_01_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B1_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_02_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B1_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_03_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B1_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_04_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B1_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_05_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B1_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_06_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B1_07 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_07_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B1_08 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_08_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B1_09 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_09_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B1_10 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_10_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B1_11 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_11_OFFSET) - -/* Select Input Registers */ - -#define IMXRT_INPUT_ANATOP_USB_OTG1_ID (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ANATOP_USB_OTG1_ID_OFFSET) -#define IMXRT_INPUT_CCM_PMIC_READY (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CCM_PMIC_READY_OFFSET) -#define IMXRT_INPUT_ENET_IPG_CLK_RMII (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET_IPG_CLK_RMII_OFFSET) -#define IMXRT_INPUT_ENET_MDIO (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET_MDIO_OFFSET) -#define IMXRT_INPUT_ENET0_RXDATA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET0_RXDATA_OFFSET) -#define IMXRT_INPUT_ENET1_RXDATA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET1_RXDATA_OFFSET) -#define IMXRT_INPUT_ENET_RXEN (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET_RXEN_OFFSET) -#define IMXRT_INPUT_ENET_RXERR (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET_RXERR_OFFSET) -#define IMXRT_INPUT_ENET_TXCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET_TXCLK_OFFSET) -#define IMXRT_INPUT_FLEXCAN1_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXCAN1_RX_OFFSET) -#define IMXRT_INPUT_FLEXCAN2_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXCAN2_RX_OFFSET) -#define IMXRT_INPUT_FLEXPWM1_PWMA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMA0_OFFSET) -#define IMXRT_INPUT_FLEXPWM1_PWMA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMA1_OFFSET) -#define IMXRT_INPUT_FLEXPWM1_PWMA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMA2_OFFSET) -#define IMXRT_INPUT_FLEXPWM1_PWMA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMA3_OFFSET) -#define IMXRT_INPUT_FLEXPWM1_PWMB0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMB0_OFFSET) -#define IMXRT_INPUT_FLEXPWM1_PWMB1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMB1_OFFSET) -#define IMXRT_INPUT_FLEXPWM1_PWMB2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMB2_OFFSET) -#define IMXRT_INPUT_FLEXPWM1_PWMB3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMB3_OFFSET) -#define IMXRT_INPUT_FLEXPWM2_PWMA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMA0_OFFSET) -#define IMXRT_INPUT_FLEXPWM2_PWMA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMA1_OFFSET) -#define IMXRT_INPUT_FLEXPWM2_PWMA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMA2_OFFSET) -#define IMXRT_INPUT_FLEXPWM2_PWMA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMA3_OFFSET) -#define IMXRT_INPUT_FLEXPWM2_PWMB0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMB0_OFFSET) -#define IMXRT_INPUT_FLEXPWM2_PWMB1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMB1_OFFSET) -#define IMXRT_INPUT_FLEXPWM2_PWMB2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMB2_OFFSET) -#define IMXRT_INPUT_FLEXPWM2_PWMB3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMB3_OFFSET) -#define IMXRT_INPUT_FLEXSPIA_DATA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_DATA0_OFFSET) -#define IMXRT_INPUT_FLEXSPIA_DATA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_DATA1_OFFSET) -#define IMXRT_INPUT_FLEXSPIA_DATA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_DATA2_OFFSET) -#define IMXRT_INPUT_FLEXSPIA_DATA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_DATA3_OFFSET) -#define IMXRT_INPUT_FLEXSPIA_SCK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_SCK_OFFSET) -#define IMXRT_INPUT_LPI2C1_SCL (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C1_SCL_OFFSET) -#define IMXRT_INPUT_LPI2C1_SDA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C1_SDA_OFFSET) -#define IMXRT_INPUT_LPI2C2_SCL (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C2_SCL_OFFSET) -#define IMXRT_INPUT_LPI2C2_SDA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C2_SDA_OFFSET) -#define IMXRT_INPUT_LPI2C3_SCL (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C3_SCL_OFFSET) -#define IMXRT_INPUT_LPI2C3_SDA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C3_SDA_OFFSET) -#define IMXRT_INPUT_LPI2C4_SCL (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C4_SCL_OFFSET) -#define IMXRT_INPUT_LPI2C4_SDA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C4_SDA_OFFSET) -#define IMXRT_INPUT_LPSPI1_PCS0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI1_PCS0_OFFSET) -#define IMXRT_INPUT_LPSPI1_SCK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI1_SCK_OFFSET) -#define IMXRT_INPUT_LPSPI1_SDI (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI1_SDI_OFFSET) -#define IMXRT_INPUT_LPSPI1_SDO (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI1_SDO_OFFSET) -#define IMXRT_INPUT_LPSPI2_PCS0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI2_PCS0_OFFSET) -#define IMXRT_INPUT_LPSPI2_SCK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI2_SCK_OFFSET) -#define IMXRT_INPUT_LPSPI2_SDI (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI2_SDI_OFFSET) -#define IMXRT_INPUT_LPSPI2_SDO (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI2_SDO_OFFSET) -#define IMXRT_INPUT_LPSPI4_PCS0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI4_PCS0_OFFSET) -#define IMXRT_INPUT_LPSPI4_SCK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI4_SCK_OFFSET) -#define IMXRT_INPUT_LPSPI4_SDI (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI4_SDI_OFFSET) -#define IMXRT_INPUT_LPSPI4_SDO (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI4_SDO_OFFSET) -#define IMXRT_INPUT_LPUART2_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART2_RX_OFFSET) -#define IMXRT_INPUT_LPUART2_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART2_TX_OFFSET) -#define IMXRT_INPUT_LPUART3_CTS_B (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART3_CTS_B_OFFSET) -#define IMXRT_INPUT_LPUART3_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART3_RX_OFFSET) -#define IMXRT_INPUT_LPUART3_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART3_TX_OFFSET) -#define IMXRT_INPUT_LPUART4_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART4_RX_OFFSET) -#define IMXRT_INPUT_LPUART4_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART4_TX_OFFSET) -#define IMXRT_INPUT_LPUART5_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART5_RX_OFFSET) -#define IMXRT_INPUT_LPUART5_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART5_TX_OFFSET) -#define IMXRT_INPUT_LPUART6_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART6_RX_OFFSET) -#define IMXRT_INPUT_LPUART6_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART6_TX_OFFSET) -#define IMXRT_INPUT_LPUART7_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART7_RX_OFFSET) -#define IMXRT_INPUT_LPUART7_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART7_TX_OFFSET) -#define IMXRT_INPUT_LPUART8_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART8_RX_OFFSET) -#define IMXRT_INPUT_LPUART8_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART8_TX_OFFSET) -#define IMXRT_INPUT_NMI_GLUE_NMI (IMXRT_IOMUXC_BASE + IMXRT_INPUT_NMI_GLUE_NMI_OFFSET) -#define IMXRT_INPUT_QTIMER1_TIMER0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER1_TIMER0_OFFSET) -#define IMXRT_INPUT_QTIMER1_TIMER1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER1_TIMER1_OFFSET) -#define IMXRT_INPUT_QTIMER1_TIMER2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER1_TIMER2_OFFSET) -#define IMXRT_INPUT_QTIMER1_TIMER3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER1_TIMER3_OFFSET) -#define IMXRT_INPUT_QTIMER2_TIMER0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER2_TIMER0_OFFSET) -#define IMXRT_INPUT_QTIMER2_TIMER1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER2_TIMER1_OFFSET) -#define IMXRT_INPUT_QTIMER2_TIMER2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER2_TIMER2_OFFSET) -#define IMXRT_INPUT_QTIMER2_TIMER3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER2_TIMER3_OFFSET) -#define IMXRT_INPUT_SAI1_MCLK2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_MCLK2_OFFSET) -#define IMXRT_INPUT_SAI1_RX_BCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_BCLK_OFFSET) -#define IMXRT_INPUT_SAI1_RX_DATA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_DATA0_OFFSET) -#define IMXRT_INPUT_SAI1_RX_DATA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_DATA1_OFFSET) -#define IMXRT_INPUT_SAI1_RX_DATA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_DATA2_OFFSET) -#define IMXRT_INPUT_SAI1_RX_DATA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_DATA3_OFFSET) -#define IMXRT_INPUT_SAI1_RX_SYNC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_SYNC_OFFSET) -#define IMXRT_INPUT_SAI1_TX_BCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_TX_BCLK_OFFSET) -#define IMXRT_INPUT_SAI1_TX_SYNC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_TX_SYNC_OFFSET) -#define IMXRT_INPUT_SAI2_MCLK2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_MCLK2_OFFSET) -#define IMXRT_INPUT_SAI2_RX_BCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_RX_BCLK_OFFSET) -#define IMXRT_INPUT_SAI2_RX_DATA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_RX_DATA0_OFFSET) -#define IMXRT_INPUT_SAI2_RX_SYNC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_RX_SYNC_OFFSET) -#define IMXRT_INPUT_SAI2_TX_BCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_TX_BCLK_OFFSET) -#define IMXRT_INPUT_SAI2_TX_SYNC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_TX_SYNC_OFFSET) -#define IMXRT_INPUT_SPDIF_IN (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SPDIF_IN_OFFSET) -#define IMXRT_INPUT_USB_OTG1_OC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USB_OTG1_OC_OFFSET) -#define IMXRT_INPUT_USDHC1_CD_B (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC1_CD_B_OFFSET) -#define IMXRT_INPUT_USDHC1_WP (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC1_WP_OFFSET) -#define IMXRT_INPUT_USDHC2_CLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_CLK_OFFSET) -#define IMXRT_INPUT_USDHC2_CD_B (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_CD_B_OFFSET) -#define IMXRT_INPUT_XBAR1_IN14 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN14_OFFSET) -#define IMXRT_INPUT_XBAR1_IN15 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN15_OFFSET) -#define IMXRT_INPUT_XBAR1_IN16 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN16_OFFSET) -#define IMXRT_INPUT_XBAR1_IN17 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN17_OFFSET) -#define IMXRT_INPUT_XBAR1_IN10 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN10_OFFSET) -#define IMXRT_INPUT_XBAR1_IN12 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN12_OFFSET) -#define IMXRT_INPUT_XBAR1_IN13 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN13_OFFSET) -#define IMXRT_INPUT_XBAR1_IN18 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN18_OFFSET) -#define IMXRT_INPUT_XBAR1_IN19 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN19_OFFSET) - -/* Register bit definitions **************************************************/ - -/* General Purpose Register 0 (GPR0) - Reserved */ - -/* General Purpose Register 1 (GPR1) */ - -#define GPR_GPR1_SAI1_MCLK1_SEL_SHIFT (0) -#define GPR_GPR1_SAI1_MCLK1_SEL_MASK (7 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK1_SEL_CCM_SSI1_CLK_ROOT (0 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK1_SEL_CCM_SSI2_CLK_ROOT (1 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK1_SEL_CCM_SSI3_CLK_ROOT (2 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK1_SEL_IOMUX_SAI1_IPG_CLK_SAI_MCLK2 (3 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK1_SEL_IOMUX_SAI2_IPG_CLK_SAI_MCLK2 (4 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK1_SEL_IOMUX_SAI3_IPG_CLK_SAI_MCLK2 (5 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) -#define GPR_GPR1_SAI1_MCLK2_SEL_SHIFT (3) -#define GPR_GPR1_SAI1_MCLK2_SEL_MASK (7 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK2_SEL_CCM_SSI1_CLK_ROOT (0 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK2_SEL_CCM_SSI2_CLK_ROOT (1 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK2_SEL_CCM_SSI3_CLK_ROOT (2 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK2_SEL_IOMUX_SAI1_IPG_CLK_SAI_MCLK2 (3 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK2_SEL_IOMUX_SAI2_IPG_CLK_SAI_MCLK2 (4 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK2_SEL_IOMUX_SAI3_IPG_CLK_SAI_MCLK2 (5 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) -#define GPR_GPR1_SAI1_MCLK3_SEL_SHIFT (6) -#define GPR_GPR1_SAI1_MCLK3_SEL_MASK (3 << GPR_GPR1_SAI1_MCLK3_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK3_SEL_CCM_SPDIF0_CLK_ROOT (0 << GPR_GPR1_SAI1_MCLK3_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK3_SEL_IOMUX_SPDIF_TX_CLK2 (1 << GPR_GPR1_SAI1_MCLK3_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK3_SEL_SPDIF_SPDIF_SRCLK (2 << GPR_GPR1_SAI1_MCLK3_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK3_SEL_SPDIF_SPDIF_OUTCLOCK (3 << GPR_GPR1_SAI1_MCLK3_SEL_SHIFT) -#define GPR_GPR1_SAI2_MCLK3_SEL_SHIFT (8) -#define GPR_GPR1_SAI2_MCLK3_SEL_MASK (3 << GPR_GPR1_SAI2_MCLK3_SEL_SHIFT) -# define GPR_GPR1_SAI2_MCLK3_SEL_CCM_SPDIF0_CLK_ROOT (0 << GPR_GPR1_SAI2_MCLK3_SEL_SHIFT) -# define GPR_GPR1_SAI2_MCLK3_SEL_IOMUX_SPDIF_TX_CLK2 (1 << GPR_GPR1_SAI2_MCLK3_SEL_SHIFT) -# define GPR_GPR1_SAI2_MCLK3_SEL_SPDIF_SPDIF_SRCLK (2 << GPR_GPR1_SAI2_MCLK3_SEL_SHIFT) -# define GPR_GPR1_SAI2_MCLK3_SEL_SPDIF_SPDIF_OUTCLOCK (3 << GPR_GPR1_SAI2_MCLK3_SEL_SHIFT) -#define GPR_GPR1_SAI3_MCLK3_SEL_SHIFT (10) -#define GPR_GPR1_SAI3_MCLK3_SEL_MASK (3 << GPR_GPR1_SAI3_MCLK3_SEL_SHIFT) -# define GPR_GPR1_SAI3_MCLK3_SEL_CCM_SPDIF0_CLK_ROOT (0 << GPR_GPR1_SAI3_MCLK3_SEL_SHIFT) -# define GPR_GPR1_SAI3_MCLK3_SEL_IOMUX_SPDIF_TX_CLK2 (1 << GPR_GPR1_SAI3_MCLK3_SEL_SHIFT) -# define GPR_GPR1_SAI3_MCLK3_SEL_SPDIF_SPDIF_SRCLK (2 << GPR_GPR1_SAI3_MCLK3_SEL_SHIFT) -# define GPR_GPR1_SAI3_MCLK3_SEL_SPDIF_SPDIF_OUTCLOCK (3 << GPR_GPR1_SAI3_MCLK3_SEL_SHIFT) -#define GPR_GPR1_GINT (1 << 12) -#define GPR_GPR1_ENET1_CLK_SEL (1 << 13) -#define GPR_GPR1_USB_EXP_MODE_EN (1 << 15) -#define GPR_GPR1_ENET1_TX_CLK_OUT_EN (1 << 17) -#define GPR_GPR1_SAI1_MCLK_DIR_IN (0 << 19) -#define GPR_GPR1_SAI1_MCLK_DIR_OUT (1 << 19) -#define GPR_GPR1_SAI2_MCLK_DIR_IN (0 << 20) -#define GPR_GPR1_SAI2_MCLK_DIR_OUT (1 << 20) -#define GPR_GPR1_SAI3_MCLK_DIR_IN (0 << 21) -#define GPR_GPR1_SAI3_MCLK_DIR_OUT (1 << 21) -#define GPR_GPR1_EXC_MON_OKAY (0 << 22) -#define GPR_GPR1_EXC_MON_SLVERR (1 << 22) -#define GPR_GPR1_ENET_IMG_CLS_S_EN (1 << 23) -#define GPR_GPR1_CM7_FORCE_HCLK_EN (1 << 31) - -/* General Purpose Register 2 (GPR2) */ - -#define GPR_GPR2_L2_MEM_POWERSAVE_EN (1 << 12) -#define GPR_GPR2_RAM_AUTO_CLK_GATING_EN (1 << 13) -#define GPR_GPR2_L2_MEM_FORCE_DEEPSLEEP (1 << 14) -#define GPR_GPR2_MQS_CLK_DIV_SHIFT (16) -#define GPR_GPR2_MQS_CLK_DIV_MASK (255 << GPR_GPR2_MQS_CLK_DIV_SHIFT) -# define GPR_GPR2_MQS_CLK_DIV(n) ((n - 1) << GPR_GPR2_MQS_CLK_DIV_SHIFT) -#define GPR_GPR2_MQS_SW_RST_EN (1 << 24) -#define GPR_GPR2_MQS_EN (1 << 25) -#define GPR_GPR2_MQS_OVERSAMPLE32 (0 << 26) -#define GPR_GPR2_MQS_OVERSAMPLE64 (1 << 26) -#define GPR_GPR2_QTIM1_TMR_RESET (1 << 28) -#define GPR_GPR2_QTIM2_TMR_RESET (1 << 29) - -/* General Purpose Register 3 (GPR3) */ - -#define GPR_GPR3_OCRAM_CTL_SHIFT (0) -#define GPR_GPR3_OCRAM_CTL_MASK (15 << GPR_GPR3_OCRAM_CTL_SHIFT) -# define GPR_GPR3_OCRAM_CTL_READ_DATA_PIPELINE_EN (1 << GPR_GPR3_OCRAM_CTL_SHIFT) -# define GPR_GPR3_OCRAM_CTL_READ_ADDR_PIPELINE_EN (2 << GPR_GPR3_OCRAM_CTL_SHIFT) -# define GPR_GPR3_OCRAM_CTL_WRITE_DATA_PIPELINE_EN (4 << GPR_GPR3_OCRAM_CTL_SHIFT) -# define GPR_GPR3_OCRAM_CTL_WRITE_ADDR_PIPELINE_EN (8 << GPR_GPR3_OCRAM_CTL_SHIFT) -#define GPR_GPR3_DCP_KEY_SEL_128 (0 << 4) -#define GPR_GPR3_DCP_KEY_SEL_256 (1 << 4) -#define GPR_GPR3_OCRAM_STATUS_SHIFT (16) -#define GPR_GPR3_OCRAM_STATUS_MASK (15 << GPR_GPR3_OCRAM_STATUS_SHIFT) -# define GPR_GPR3_OCRAM_STATUS_READ_DATA_PIPELINE_EN (1 << GPR_GPR3_OCRAM_STATUS_SHIFT) -# define GPR_GPR3_OCRAM_STATUS_READ_ADDR_PIPELINE_EN (2 << GPR_GPR3_OCRAM_STATUS_SHIFT) -# define GPR_GPR3_OCRAM_STATUS_WRITE_DATA_PIPELINE_EN (4 << GPR_GPR3_OCRAM_STATUS_SHIFT) -# define GPR_GPR3_OCRAM_STATUS_WRITE_ADDR_PIPELINE_EN (8 << GPR_GPR3_OCRAM_STATUS_SHIFT) - -/* General Purpose Register 4 (GPR4) */ - -#define GPR_GRP4_EDMA_STOP_REQ (1 << 0) -#define GPR_GPR4_CAN1_STOP_REQ (1 << 1) -#define GPR_GPR4_CAN2_STOP_REQ (1 << 2) -#define GPR_GPR4_TRNG_STOP_REQ (1 << 3) -#define GPR_GPR4_ENET_STOP_REQ (1 << 4) -#define GPR_GPR4_SAI1_STOP_REQ (1 << 5) -#define GPR_GPR4_SAI2_STOP_REQ (1 << 6) -#define GPR_GPR4_SAI3_STOP_REQ (1 << 7) -#define GPR_GPR4_SEMC_STOP_REQ (1 << 9) -#define GPR_GPR4_PIT_STOP_REQ (1 << 10) -#define GPR_GPR4_FLEXSPI_STOP_REQ (1 << 11) -#define GPR_GPR4_FLEXIO1_STOP_REQ (1 << 12) -#define GPR_GRP4_EDMA_STOP_ACK (1 << 16) -#define GPR_GPR4_CAN1_STOP_ACK (1 << 17) -#define GPR_GPR4_CAN2_STOP_ACK (1 << 18) -#define GPR_GPR4_TRNG_STOP_ACK (1 << 19) -#define GPR_GPR4_ENET_STOP_ACK (1 << 20) -#define GPR_GPR4_SAI1_STOP_ACK (1 << 21) -#define GPR_GPR4_SAI2_STOP_ACK (1 << 22) -#define GPR_GPR4_SAI3_STOP_ACK (1 << 23) -#define GPR_GPR4_SEMC_STOP_ACK (1 << 25) -#define GPR_GPR4_PIT_STOP_ACK (1 << 26) -#define GPR_GPR4_FLEXSPI_STOP_ACK (1 << 27) -#define GPR_GPR4_FLEXIO1_STOP_ACK (1 << 28) - -/* General Purpose Register 5 (GPR5) */ - -#define GPR_GPR5_WDOG1_MASK (1 << 6) -#define GPR_GPR5_WDOG2_MASK (1 << 7) -#define GPR_GPR5_GPT2_CAPIN1_SEL_PAD (0 << 23) -#define GPR_GPR5_GPT2_CAPIN1_SEL_ENET1 (1 << 23) -#define GPR_GPR5_ENET_EVENT3IN_SEL_ENET (0 << 25) -#define GPR_GPR5_ENET_EVENT3IN_SEL_GPT2CMP1 (1 << 25) -#define GPR_GPR5_VREF_1M_CLK_GPT1_IPG_PERCLK (0 << 28) -#define GPR_GPR5_VREF_1M_CLK_GPT1_ANATOP (1 << 28) -#define GPR_GPR5_VREF_1M_CLK_GPT2_IPG_PERCLK (0 << 29) -#define GPR_GPR5_VREF_1M_CLK_GPT2_ANATOP (1 << 29) - -/* General Purpose Register 6 (GPR6) */ - -#define GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT (0) -#define GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT) -#define GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT (1) -#define GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT) -#define GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT (2) -#define GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT) -#define GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT (3) -#define GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT) -#define GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT (4) -#define GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT) -#define GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT (5) -#define GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT) -#define GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT (6) -#define GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT) -#define GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT (7) -#define GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT (16) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT (17) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT (18) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT (19) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT (20) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT (21) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT (22) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT (23) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT (24) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT (25) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT (26) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT (27) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT (28) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT (29) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT (30) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT (31) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT) - -/* General Purpose Register 7 (GPR7) */ - -#define GPR_GPR7_LPI2C1_STOP_REQ (1 << 0) -#define GPR_GPR7_LPI2C2_STOP_REQ (1 << 1) -#define GPR_GPR7_LPI2C3_STOP_REQ (1 << 2) -#define GPR_GPR7_LPI2C4_STOP_REQ (1 << 3) -#define GPR_GPR7_LPSPI1_STOP_REQ (1 << 4) -#define GPR_GPR7_LPSPI2_STOP_REQ (1 << 5) -#define GPR_GPR7_LPSPI3_STOP_REQ (1 << 6) -#define GPR_GPR7_LPSPI4_STOP_REQ (1 << 7) -#define GPR_GPR7_LPUART1_STOP_REQ (1 << 8) -#define GPR_GPR7_LPUART2_STOP_REQ (1 << 9) -#define GPR_GPR7_LPUART3_STOP_REQ (1 << 10) -#define GPR_GPR7_LPUART4_STOP_REQ (1 << 11) -#define GPR_GPR7_LPUART5_STOP_REQ (1 << 12) -#define GPR_GPR7_LPUART6_STOP_REQ (1 << 13) -#define GPR_GPR7_LPUART7_STOP_REQ (1 << 14) -#define GPR_GPR7_LPUART8_STOP_REQ (1 << 15) -#define GPR_GPR7_LPI2C1_STOP_ACK (1 << 16) -#define GPR_GPR7_LPI2C2_STOP_ACK (1 << 17) -#define GPR_GPR7_LPI2C3_STOP_ACK (1 << 18) -#define GPR_GPR7_LPI2C4_STOP_ACK (1 << 19) -#define GPR_GPR7_LPSPI1_STOP_ACK (1 << 20) -#define GPR_GPR7_LPSPI2_STOP_ACK (1 << 21) -#define GPR_GPR7_LPSPI3_STOP_ACK (1 << 22) -#define GPR_GPR7_LPSPI4_STOP_ACK (1 << 23) -#define GPR_GPR7_LPUART1_STOP_ACK (1 << 24) -#define GPR_GPR7_LPUART2_STOP_ACK (1 << 25) -#define GPR_GPR7_LPUART3_STOP_ACK (1 << 26) -#define GPR_GPR7_LPUART4_STOP_ACK (1 << 27) -#define GPR_GPR7_LPUART5_STOP_ACK (1 << 28) -#define GPR_GPR7_LPUART6_STOP_ACK (1 << 29) -#define GPR_GPR7_LPUART7_STOP_ACK (1 << 30) -#define GPR_GPR7_LPUART8_STOP_ACK (1 << 31) - -/* General Purpose Register 8 (GPR8) */ - -#define GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT (0) -#define GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPI2C1_IPG_ON_IN_STOP (0 << GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPI2C1_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT) -#define GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT (1) -#define GPR_GPR8_LPI2C1_IPG_DOZE_MASK (1 << GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPI2C1_IPG_NOT_DOZED (0 << GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPI2C1_IPG_DOZED (1 << GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT) -#define GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT (2) -#define GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPI2C2_IPG_ON_IN_STOP (0 << GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPI2C2_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT) -#define GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT (3) -#define GPR_GPR8_LPI2C2_IPG_DOZE_MASK (1 << GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPI2C2_IPG_NOT_DOZED (0 << GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPI2C2_IPG_DOZED (1 << GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT) -#define GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT (4) -#define GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPI2C3_IPG_ON_IN_STOP (0 << GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPI2C3_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT) -#define GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT (5) -#define GPR_GPR8_LPI2C3_IPG_DOZE_MASK (1 << GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPI2C3_IPG_NOT_DOZED (0 << GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPI2C3_IPG_DOZED (1 << GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT) -#define GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT (6) -#define GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPI2C4_IPG_ON_IN_STOP (0 << GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPI2C4_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT) -#define GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT (7) -#define GPR_GPR8_LPI2C4_IPG_DOZE_MASK (1 << GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPI2C4_IPG_NOT_DOZED (0 << GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPI2C4_IPG_DOZED (1 << GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT) -#define GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT (8) -#define GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPSPI1_IPG_ON_IN_STOP (0 << GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPSPI1_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT) -#define GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT (9) -#define GPR_GPR8_LPSPI1_IPG_DOZE_MASK (1 << GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPSPI1_IPG_NOT_DOZED (0 << GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPSPI1_IPG_DOZED (1 << GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT) -#define GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT (10) -#define GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPSPI2_IPG_ON_IN_STOP (0 << GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPSPI2_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT) -#define GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT (11) -#define GPR_GPR8_LPSPI2_IPG_DOZE_MASK (1 << GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPSPI2_IPG_NOT_DOZED (0 << GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPSPI2_IPG_DOZED (1 << GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT) -#define GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT (12) -#define GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPSPI3_IPG_ON_IN_STOP (0 << GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPSPI3_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT) -#define GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT (13) -#define GPR_GPR8_LPSPI3_IPG_DOZE_MASK (1 << GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPSPI3_IPG_NOT_DOZED (0 << GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPSPI3_IPG_DOZED (1 << GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT) -#define GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT (14) -#define GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPSPI4_IPG_ON_IN_STOP (0 << GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPSPI4_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT) -#define GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT (15) -#define GPR_GPR8_LPSPI4_IPG_DOZE_MASK (1 << GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPSPI4_IPG_NOT_DOZED (0 << GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPSPI4_IPG_DOZED (1 << GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT) -#define GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT (16) -#define GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPUART1_IPG_ON_IN_STOP (0 << GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPUART1_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT) -#define GPR_GPR8_LPUART1_IPG_DOZE_SHIFT (17) -#define GPR_GPR8_LPUART1_IPG_DOZE_MASK (1 << GPR_GPR8_LPUART1_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPUART1_IPG_NOT_DOZED (0 << GPR_GPR8_LPUART1_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPUART1_IPG_DOZED (1 << GPR_GPR8_LPUART1_IPG_DOZE_SHIFT) -#define GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT (18) -#define GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPUART2_IPG_ON_IN_STOP (0 << GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPUART2_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT) -#define GPR_GPR8_LPUART2_IPG_DOZE_SHIFT (19) -#define GPR_GPR8_LPUART2_IPG_DOZE_MASK (1 << GPR_GPR8_LPUART2_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPUART2_IPG_NOT_DOZED (0 << GPR_GPR8_LPUART2_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPUART2_IPG_DOZED (1 << GPR_GPR8_LPUART2_IPG_DOZE_SHIFT) -#define GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT (20) -#define GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPUART3_IPG_ON_IN_STOP (0 << GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPUART3_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT) -#define GPR_GPR8_LPUART3_IPG_DOZE_SHIFT (21) -#define GPR_GPR8_LPUART3_IPG_DOZE_MASK (1 << GPR_GPR8_LPUART3_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPUART3_IPG_NOT_DOZED (0 << GPR_GPR8_LPUART3_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPUART3_IPG_DOZED (1 << GPR_GPR8_LPUART3_IPG_DOZE_SHIFT) -#define GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT (22) -#define GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPUART4_IPG_ON_IN_STOP (0 << GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPUART4_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT) -#define GPR_GPR8_LPUART4_IPG_DOZE_SHIFT (23) -#define GPR_GPR8_LPUART4_IPG_DOZE_MASK (1 << GPR_GPR8_LPUART4_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPUART4_IPG_NOT_DOZED (0 << GPR_GPR8_LPUART4_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPUART4_IPG_DOZED (1 << GPR_GPR8_LPUART4_IPG_DOZE_SHIFT) -#define GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT (24) -#define GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPUART5_IPG_ON_IN_STOP (0 << GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPUART5_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT) -#define GPR_GPR8_LPUART5_IPG_DOZE_SHIFT (25) -#define GPR_GPR8_LPUART5_IPG_DOZE_MASK (1 << GPR_GPR8_LPUART5_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPUART5_IPG_NOT_DOZED (0 << GPR_GPR8_LPUART5_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPUART5_IPG_DOZED (1 << GPR_GPR8_LPUART5_IPG_DOZE_SHIFT) -#define GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT (26) -#define GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPUART6_IPG_ON_IN_STOP (0 << GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPUART6_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT) -#define GPR_GPR8_LPUART6_IPG_DOZE_SHIFT (27) -#define GPR_GPR8_LPUART6_IPG_DOZE_MASK (1 << GPR_GPR8_LPUART6_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPUART6_IPG_NOT_DOZED (0 << GPR_GPR8_LPUART6_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPUART6_IPG_DOZED (1 << GPR_GPR8_LPUART6_IPG_DOZE_SHIFT) -#define GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT (28) -#define GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPUART7_IPG_ON_IN_STOP (0 << GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPUART7_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT) -#define GPR_GPR8_LPUART7_IPG_DOZE_SHIFT (29) -#define GPR_GPR8_LPUART7_IPG_DOZE_MASK (1 << GPR_GPR8_LPUART7_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPUART7_IPG_NOT_DOZED (0 << GPR_GPR8_LPUART7_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPUART7_IPG_DOZED (1 << GPR_GPR8_LPUART7_IPG_DOZE_SHIFT) -#define GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT (30) -#define GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPUART8_IPG_ON_IN_STOP (0 << GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPUART8_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT) -#define GPR_GPR8_LPUART8_IPG_DOZE_SHIFT (31) -#define GPR_GPR8_LPUART8_IPG_DOZE_MASK (1 << GPR_GPR8_LPUART8_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPUART8_IPG_NOT_DOZED (0 << GPR_GPR8_LPUART8_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPUART8_IPG_DOZED (1 << GPR_GPR8_LPUART8_IPG_DOZE_SHIFT) - -/* General Purpose Register 9 (GPR9) - Reserved */ - -/* General Purpose Register 10 (GPR10) */ - -#define GPR_GPR10_NIDEN (1 << 0) -#define GPR_GPR10_DBG_EN (1 << 1) -#define GPR_GPR10_SEC_ERR_RESP (1 << 2) -#define GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX (1 << 4) -#define GPR_GPR10_OCRAM_TZ_EN (1 << 8) -#define GPR_GPR10_OCRAM_TZ_ADDR_SHIFT (9) -#define GPR_GPR10_OCRAM_TZ_ADDR_MASK (0x3f << GPR_GPR10_OCRAM_TZ_ADDR_SHIFT) -# define GPR_GPR10_OCRAM_TZ_ADDR(n) ((uint32_t)(n) << GPR_GPR10_OCRAM_TZ_ADDR_SHIFT) -#define GPR_GPR10_LOCK_NIDEN (1 << 16) -#define GPR_GPR10_LOCK_DBG_EN (1 << 17) -#define GPR_GPR10_LOCK_SEC_ERR_RESP (1 << 18) -#define GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX (1 << 20) -#define GPR_GPR10_LOCK_OCRAM_TZ_EN (1 << 24) -#define GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT (25) -#define GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK (0x3f << GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT) -# define GPR_GPR10_LOCK_OCRAM_TZ_ADDR(n) ((uint32_t)(n) << GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT) - -/* General Purpose Register 11 (GPR11) */ - -#define GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFTS (0) -#define GPR_GPR11_M7_APC_AC_R0_CTRL_MASK (3 << GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFTS) -# define GPR_GPR11_M7_APC_AC_R0_CTRL_NO_ACCESS (0 << GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFTS) -# define GPR_GPR11_M7_APC_AC_R0_CTRL_NO_DEBUG (1 << GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFTS) -#define GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFTS (2) -#define GPR_GPR11_M7_APC_AC_R1_CTRL_MASK (3 << GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFTS) -# define GPR_GPR11_M7_APC_AC_R1_CTRL_NO_ACCESS (0 << GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFTS) -# define GPR_GPR11_M7_APC_AC_R1_CTRL_NO_DEBUG (1 << GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFTS) -#define GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFTS (4) -#define GPR_GPR11_M7_APC_AC_R2_CTRL_MASK (3 << GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFTS) -# define GPR_GPR11_M7_APC_AC_R2_CTRL_NO_ACCESS (0 << GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFTS) -# define GPR_GPR11_M7_APC_AC_R2_CTRL_NO_DEBUG (1 << GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFTS) -#define GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFTS (6) -#define GPR_GPR11_M7_APC_AC_R3_CTRL_MASK (3 << GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFTS) -# define GPR_GPR11_M7_APC_AC_R3_CTRL_NO_ACCESS (0 << GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFTS) -# define GPR_GPR11_M7_APC_AC_R3_CTRL_NO_DEBUG (1 << GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFTS) -#define GPR_GPR11_BEE_DE_RX_EN_SHIFTS (8) -#define GPR_GPR11_BEE_DE_RX_EN_MASK (0xf << GPR_GPR11_BEE_DE_RX_EN_SHIFTS) -# define GPR_GPR11_BEE_DE_RX_EN(n) ((uint32_t)(n) << GPR_GPR11_BEE_DE_RX_EN_SHIFTS) -# define GPR_GPR11_BEE_DE_R0_EN (1) << GPR_GPR11_BEE_DE_RX_EN_SHIFTS) -# define GPR_GPR11_BEE_DE_R1_EN (2) << GPR_GPR11_BEE_DE_RX_EN_SHIFTS) -# define GPR_GPR11_BEE_DE_R2_EN (4) << GPR_GPR11_BEE_DE_RX_EN_SHIFTS) -# define GPR_GPR11_BEE_DE_R3_EN (8) << GPR_GPR11_BEE_DE_RX_EN_SHIFTS) -#define GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFTS (16) -#define GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_MASK (3 << GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFTS) -# define GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_NO_ACCESS (0 << GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFTS) -# define GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_NO_DEBUG (1 << GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFTS) -#define GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFTS (18) -#define GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_MASK (3 << GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFTS) -# define GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_NO_ACCESS (0 << GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFTS) -# define GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_NO_DEBUG (1 << GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFTS) -#define GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFTS (20) -#define GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_MASK (3 << GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFTS) -# define GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_NO_ACCESS (0 << GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFTS) -# define GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_NO_DEBUG (1 << GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFTS) -#define GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFTS (22) -#define GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_MASK (3 << GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFTS) -# define GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_NO_ACCESS (0 << GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFTS) -# define GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_NO_DEBUG (1 << GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFTS) -#define GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFTS (24) -#define GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK (0xf << GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFTS) -# define GPR_GPR11_LOCK_BEE_DE_RX_EN(n) ((uint32_t)(n) << GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFTS) -# define GPR_GPR11_LOCK_BEE_DE_R0_EN (1) << GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFTS) -# define GPR_GPR11_LOCK_BEE_DE_R1_EN (2) << GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFTS) -# define GPR_GPR11_LOCK_BEE_DE_R2_EN (4) << GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFTS) -# define GPR_GPR11_LOCK_BEE_DE_R3_EN (8) << GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFTS) - -/* General Purpose Register 12 (GPR12) */ - -#define GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT (0) -#define GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK (1 << GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT) -# define GPR_GPR12_FLEXIO1_IPG_ON_IN_STOP (0 << GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT) -# define GPR_GPR12_FLEXIO1_IPG_OFF_IN_STOP (1 << GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT) -#define GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT (1) -#define GPR_GPR12_FLEXIO1_IPG_DOZE_MASK (1 << GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT) -# define GPR_GPR12_FLEXIO1_IPG_NOT_DOZED (0 << GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT) -# define GPR_GPR12_FLEXIO1_IPG_DOZED (1 << GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT) -#define GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT (4) -#define GPR_GPR12_ACMP_IPG_STOP_MODE_MASK (1 << GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT) -# define GPR_GPR12_ACMP_IPG_ON_IN_STOP (0 << GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT) -# define GPR_GPR12_ACMP_IPG_OFF_IN_STOP (1 << GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT) - -/* General Purpose Register 13 (GPR13) */ - -#define GPR_GPR13_ARCACHE_USDHC_CACHEABLE (1 << 0) -#define GPR_GPR13_AWCACHE_USDHC_CACHEABLE (1 << 1) -#define GPR_GPR13_CACHE_ENET_CACHEABLE (1 << 7) -#define GPR_GPR13_CACHE_USB_CACHEABLE (1 << 13) - -/* General Purpose Register 14 (GPR14) */ - -#define GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN (1 << 0) -#define GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN (1 << 1) -#define GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN (1 << 2) -#define GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN (1 << 3) -#define GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP (1 << 4) -#define GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP (1 << 5) -#define GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP (1 << 6) -#define GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP (1 << 7) -#define GPR_GPR14_ACMP1_SAMPLE_SYNC_EN (1 << 8) -#define GPR_GPR14_ACMP2_SAMPLE_SYNC_EN (1 << 9) -#define GPR_GPR14_ACMP3_SAMPLE_SYNC_EN (1 << 10) -#define GPR_GPR14_ACMP4_SAMPLE_SYNC_EN (1 << 11) -#define GPR_GPR14_CM7_CFGITCMSZ_SHIFT (16) -#define GPR_GPR14_CM7_CFGITCMSZ_MASK (0x4 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGITCMSZ_0KB (0 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGITCMSZ_4KB (3 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGITCMSZ_8KB (4 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGITCMSZ_16KB (6 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGITCMSZ_32KB (6 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGITCMSZ_64KB (7 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGITCMSZ_128KB (8 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGITCMSZ_256KB (9 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) -#define GPR_GPR14_CM7_CFGDTCMSZ_SHIFT (20) -#define GPR_GPR14_CM7_CFGDTCMSZ_MASK (0xf << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGDTCMSZ_0KB (0 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGDTCMSZ_4KB (3 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGDTCMSZ_8KB (4 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGDTCMSZ_16KB (6 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGDTCMSZ_32KB (6 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGDTCMSZ_64KB (7 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGDTCMSZ_128KB (8 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGDTCMSZ_256KB (9 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) - -/* General Purpose Register 15 (GPR16) - Reserved */ - -/* General Purpose Register 16 (GPR16) */ - -#define GPR_GPR16_INIT_ITCM_EN (1 << 0) -#define GPR_GPR16_INIT_DTCM_EN (1 << 1) -#define GPR_GPR16_FLEXRAM_BANK_CFG_SELF (1 << 2) - -/* General Purpose Register 17 (GPR17) */ - -#define GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT (0) -#define GPR_GPR17_FLEXRAM_BANK_CFG_MASK (0xffffffff << GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT) -#define GPR_GPR17_FLEXRAM_BANK_CFG(n) ((uint32_t)(n)) << GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT) -#define GPR_GPR17_FLEXRAM_BANK0_SHIFT (0) -#define GPR_GPR17_FLEXRAM_BANK0_MASK (3 << GPR_GPR17_FLEXRAM_BANK0_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK0_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK0_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK0_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK0_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK0_DTCM (2 << GPR_GPR17_FLEXRAM_BANK0_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK0_ITCM (3 << GPR_GPR17_FLEXRAM_BANK0_SHIFT) -#define GPR_GPR17_FLEXRAM_BANK1_SHIFT (2) -#define GPR_GPR17_FLEXRAM_BANK1_MASK (3 << GPR_GPR17_FLEXRAM_BANK1_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK1_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK1_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK1_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK1_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK1_DTCM (2 << GPR_GPR17_FLEXRAM_BANK1_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK1_ITCM (3 << GPR_GPR17_FLEXRAM_BANK1_SHIFT) -#define GPR_GPR17_FLEXRAM_BANK2_SHIFT (4) -#define GPR_GPR17_FLEXRAM_BANK2_MASK (3 << GPR_GPR17_FLEXRAM_BANK2_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK2_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK2_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK2_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK2_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK2_DTCM (2 << GPR_GPR17_FLEXRAM_BANK2_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK2_ITCM (3 << GPR_GPR17_FLEXRAM_BANK2_SHIFT) -#define GPR_GPR17_FLEXRAM_BANK3_SHIFT (6) -#define GPR_GPR17_FLEXRAM_BANK3_MASK (3 << GPR_GPR17_FLEXRAM_BANK3_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK3_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK3_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK3_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK3_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK3_DTCM (2 << GPR_GPR17_FLEXRAM_BANK3_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK3_ITCM (3 << GPR_GPR17_FLEXRAM_BANK3_SHIFT) -#define GPR_GPR17_FLEXRAM_BANK4_SHIFT (8) -#define GPR_GPR17_FLEXRAM_BANK4_MASK (3 << GPR_GPR17_FLEXRAM_BANK4_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK4_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK4_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK4_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK4_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK4_DTCM (2 << GPR_GPR17_FLEXRAM_BANK4_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK4_ITCM (3 << GPR_GPR17_FLEXRAM_BANK4_SHIFT) -#define GPR_GPR17_FLEXRAM_BANK5_SHIFT (10) -#define GPR_GPR17_FLEXRAM_BANK5_MASK (3 << GPR_GPR17_FLEXRAM_BANK5_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK5_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK5_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK5_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK5_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK5_DTCM (2 << GPR_GPR17_FLEXRAM_BANK5_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK5_ITCM (3 << GPR_GPR17_FLEXRAM_BANK5_SHIFT) -#define GPR_GPR17_FLEXRAM_BANK6_SHIFT (12) -#define GPR_GPR17_FLEXRAM_BANK6_MASK (3 << GPR_GPR17_FLEXRAM_BANK6_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK6_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK6_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK6_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK6_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK6_DTCM (2 << GPR_GPR17_FLEXRAM_BANK6_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK6_ITCM (3 << GPR_GPR17_FLEXRAM_BANK6_SHIFT) -#define GPR_GPR17_FLEXRAM_BANK7_SHIFT (14) -#define GPR_GPR17_FLEXRAM_BANK7_MASK (3 << GPR_GPR17_FLEXRAM_BANK7_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK7_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK7_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK7_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK7_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK7_DTCM (2 << GPR_GPR17_FLEXRAM_BANK7_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK7_ITCM (3 << GPR_GPR17_FLEXRAM_BANK7_SHIFT) - -/* General Purpose Register 18 (GPR18) */ - -#define GPR_GPR18_LOCK_M7_APC_AC_R0_BOT (1 << 0) -#define GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT (3) -#define GPR_GPR18_M7_APC_AC_R0_BOT_MASK (0x1fffffff << GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT) -#define GPR_GPR18_M7_APC_AC_R0_BOT(n) ((uint32_t)(n)) << GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT) - -/* General Purpose Register 19 (GPR19) */ - -#define GPR_GPR19_LOCK_M7_APC_AC_R0_TOP (1 << 0) -#define GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT (3) -#define GPR_GPR19_M7_APC_AC_R0_TOP_MASK (0x1fffffff << GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT) -#define GPR_GPR19_M7_APC_AC_R0_TOP(n) ((uint32_t)(n)) << GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT) - -/* General Purpose Register 20 (GPR20) */ - -#define GPR_GPR20_LOCK_M7_APC_AC_R1_BOT (1 << 0) -#define GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT (3) -#define GPR_GPR20_M7_APC_AC_R1_BOT_MASK (0x1fffffff << GPR_GPR18_M7_APC_AC_R1_BOT_SHIFT) -#define GPR_GPR20_M7_APC_AC_R1_BOT(n) ((uint32_t)(n)) << GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT) - -/* General Purpose Register 21 (GPR21) */ - -#define GPR_GPR21_LOCK_M7_APC_AC_R1_TOP (1 << 0) -#define GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT (3) -#define GPR_GPR21_M7_APC_AC_R1_TOP_MASK (0x1fffffff << GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT) -#define GPR_GPR21_M7_APC_AC_R1_TOP(n) ((uint32_t)(n)) << GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT) - -/* General Purpose Register 22 (GPR22) */ - -#define GPR_GPR22_LOCK_M7_APC_AC_R2_BOT (1 << 0) -#define GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT (3) -#define GPR_GPR22_M7_APC_AC_R2_BOT_MASK (0x1fffffff << GPR_GPR18_M7_APC_AC_R2_BOT_SHIFT) -#define GPR_GPR22_M7_APC_AC_R2_BOT(n) ((uint32_t)(n)) << GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT) - -/* General Purpose Register 23 (GPR23) */ - -#define GPR_GPR23_LOCK_M7_APC_AC_R2_TOP (1 << 0) -#define GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT (3) -#define GPR_GPR23_M7_APC_AC_R2_TOP_MASK (0x1fffffff << GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT) -#define GPR_GPR23_M7_APC_AC_R2_TOP(n) ((uint32_t)(n)) << GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT) - -/* General Purpose Register 24 (GPR24) */ - -#define GPR_GPR24_LOCK_M7_APC_AC_R3_BOT (1 << 0) -#define GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT (3) -#define GPR_GPR24_M7_APC_AC_R3_BOT_MASK (0x1fffffff << GPR_GPR18_M7_APC_AC_R3_BOT_SHIFT) -#define GPR_GPR24_M7_APC_AC_R3_BOT(n) ((uint32_t)(n)) << GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT) - -/* General Purpose Register 25 (GPR25) */ - -#define GPR_GPR25_LOCK_M7_APC_AC_R3_TOP (1 << 0) -#define GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT (3) -#define GPR_GPR25_M7_APC_AC_R3_TOP_MASK (0x1fffffff << GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT) -#define GPR_GPR25_M7_APC_AC_R3_TOP(n) ((uint32_t)(n)) << GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT) - -#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_IOMUXC_H */ diff --git a/arch/arm/src/imxrt/chip/rt102x/imxrt102x_memorymap.h b/arch/arm/src/imxrt/chip/rt102x/imxrt102x_memorymap.h deleted file mode 100644 index f380cb48077..00000000000 --- a/arch/arm/src/imxrt/chip/rt102x/imxrt102x_memorymap.h +++ /dev/null @@ -1,261 +0,0 @@ -/**************************************************************************** - * arch/arm/src/imxrt/chip/rt102x/imxrt102x_memorymap.h - * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Dave Marples - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_MEMORYMAP_H -#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_MEMORYMAP_H - -/***************************************************************************** - * Included Files - *****************************************************************************/ - -#include - -/***************************************************************************** - * Pre-processor Definitions - *****************************************************************************/ - -/* System memory map */ - -#define IMXRT_ITCM_BASE 0x00000000 /* 256KB ITCM */ - /* 0x00040000 768KB ITCM Reserved */ - /* 0x00100000 1MB ITCM Reserved */ -#define IMXRT_ROMCP_BASE 0x00200000 /* 96KB ROMCP */ - /* 0x00218000 416KB ROMCP Reserved */ - /* 0x00280000 1536KB Reserved */ - /* 0x00400000 124MB Reserved */ - /* 0x00800000 1527MB Reserved */ -#define IMXRT_FLEXSPI_BASE 0x06000000 /* 128MB FlexSPI (Aliased) */ -#define IMXRT_SEMCA_BASE 0x06800000 /* 639MB SEMC (Aliased) */ - /* 0x90000000 256MB SEMC (Aliased) */ -#define IMXRT_DTCM_BASE 0x20000000 /* 256KB DTCM */ - /* 0x20040000 768KB DTCM Reserved */ - /* 0x20100000 1MB Reserved */ -#define IMXRT_OCRAM_BASE 0x20200000 /* 256KB OCRAM */ - /* 0x20240000 1792KB OCRAM Reserved */ - /* 0x20400000 252MB Reserved */ - /* 0x30000000 256MB Reserved */ -#define IMXRT_AIPS1_BASE 0x40000000 /* 1MB AIPS-1 */ -#define IMXRT_AIPS2_BASE 0x40100000 /* 1MB AIPS-2 */ -#define IMXRT_AIPS3_BASE 0x40200000 /* 1MB AIPS-3 */ -#define IMXRT_AIPS4_BASE 0x40300000 /* 1MB AIPS-4 */ - /* 0x40400000 12MB Reserved */ - /* 0x41000000 1MB Reserved */ -#define IMXRT_MCNF_BASE 0x41100000 /* 1MB "m" configuration port */ - /* 41200000 1MB Reserved for "per" GPV */ - /* 41300000 1MB Reserved for "ems" GPV */ -#define IMXRT_CPUCNF_BASE 0x41400000 /* 1MB "cpu" configuration port */ - /* 0x41500000 1MB GPV Reserved */ - /* 0x41600000 1MB GPV Reserved */ - /* 0x41700000 1MB GPV Reserved */ - /* 0x41800000 8MB Reserved */ - /* 0x42000000 32MB Reserved */ - /* 0x44000000 64MB Reserved */ - /* 0x48000000 384MB Reserved */ -#define IMXRT_FLEXCIPHER_BASE 0x60000000 /* 504MB FlexSPI/ FlexSPI ciphertext */ -#define IMXRT_FLEXSPITX_BASE 0x7f800000 /* 4MB FlexSPI TX FIFO */ -#define IMXRT_FLEXSPIRX_BASE 0x7fc00000 /* 4MB FlexSPI RX FIFO */ -#define IMXRT_EXTMEM_BASE 0x80000000 /* 1.5GB SEMC external memories shared memory space */ -#define IMXRT_CM7_BASE 0xe0000000 /* 1MB CM7 PPB */ - /* 0xe0100000 511MB Reserved */ - -/* AIPS-1 memory map */ - - /* 0x40000000 256KB Reserved */ - /* 0x40040000 240KB Reserved */ -#define IMXRT_AIPS1CNF_BASE 0x4007c000 /* 16KB AIPS-1 Configuration */ -#define IMXRT_DCDC_BASE 0x40080000 /* 16KB DCDC */ -#define IMXRT_PIT_BASE 0x40084000 /* 16KB PIT */ - /* 0x40088000 16KB Reserved */ - /* 0x4008c000 16KB Reserved */ - /* 0x40090000 16KB Reserved */ -#define IMXRT_ACMP_BASE 0x40094000 /* 16KB ACMP */ - /* 0x40098000 16KB Reserved */ - /* 0x4009c000 16KB Reserved */ - /* 0x400a0000 16KB Reserved */ -#define IMXRT_IOMUXCSNVSGPR_BASE 0x400a4000 /* 16KB IOMUXC_SNVS_GPR */ -#define IMXRT_IOMUXCSNVS_BASE 0x400a8000 /* 16KB IOMUXC_SNVS */ -#define IMXRT_IOMUXCGPR_BASE 0x400ac000 /* 16KB IOMUXC_GPR */ -#define IMXRT_FLEXRAM_BASE 0x400b0000 /* 16KB CM7_MXRT(FLEXRAM) */ -#define IMXRT_EWM_BASE 0x400b4000 /* 16KB EWM */ -#define IMXRT_WDOG1_BASE 0x400b8000 /* 16KB WDOG1 */ -#define IMXRT_WDOG3_BASE 0x400bc000 /* 16KB WDOG3 */ -#define IMXRT_GPIO5_BASE 0x400c0000 /* 16KB GPIO5 */ -#define IMXRT_ADC1_BASE 0x400c4000 /* 16KB ADC1 */ -#define IMXRT_ADC2_BASE 0x400c8000 /* 16KB ADC2 */ -#define IMXRT_TRNG_BASE 0x400cc000 /* 16KB TRNG */ -#define IMXRT_WDOG2_BASE 0x400d0000 /* 16KB WDOG2 */ -#define IMXRT_SNVSHP_BASE 0x400d4000 /* 16KB SNVS_HP */ -#define IMXRT_ANATOP_BASE 0x400d8000 /* 16KB ANATOP */ -#define IMXRT_CSU_BASE 0x400dc000 /* 16KB CSU */ - /* 0x400e0000 16KB Reserved */ - /* 0x400e4000 16KB Reserved */ -#define IMXRT_EDMA_BASE 0x400e8000 /* 16KB EDMA */ -#define IMXRT_DMAMUX_BASE 0x400ec000 /* 16KB DMA_CH_MUX */ - /* 400f0000 16KB Reserved */ -#define IMXRT_GPC_BASE 0x400f4000 /* 16KB GPC */ -#define IMXRT_SRC_BASE 0x400f8000 /* 16KB SRC */ -#define IMXRT_CCM_BASE 0x400fc000 /* 16KB CCM */ - -/* AIPS-2 memory map */ - - /* 0x40100000 256KB Reserved */ - /* 0x40140000 240KB Reserved */ -#define IMXRT_AIPS2CNF_BASE 0x4017c000 /* 16KB AIPS-2 Configuration */ -#define IMXRT_ROMCPC_BASE 0x40180000 /* 16KB ROMCP controller*/ -#define IMXRT_LPUART1_BASE 0x40184000 /* 16KB LPUART1 */ -#define IMXRT_LPUART2_BASE 0x40188000 /* 16KB LPUART2 */ -#define IMXRT_LPUART3_BASE 0x4018c000 /* 16KB LPUART3 */ -#define IMXRT_LPUART4_BASE 0x40190000 /* 16KB LPUART4 */ -#define IMXRT_LPUART5_BASE 0x40194000 /* 16KB LPUART5 */ -#define IMXRT_LPUART6_BASE 0x40198000 /* 16KB LPUART6 */ -#define IMXRT_LPUART7_BASE 0x4019c000 /* 16KB LPUART7 */ -#define IMXRT_LPUART8_BASE 0x401a0000 /* 16KB LPUART8 */ - /* 0x401a4000 16KB Reserved */ - /* 0x401a8000 16KB Reserved */ -#define IMXRT_FLEXIO1_BASE 0x401ac000 /* 16KB FlexIO1 */ - /* 0x401b0000 16KB Reserved */ - /* 0x401b4000 16KB Reserved */ -#define IMXRT_GPIO1_BASE 0x401b8000 /* 16KB GPIO1 */ -#define IMXRT_GPIO2_BASE 0x401bc000 /* 16KB GPIO2 */ -#define IMXRT_GPIO3_BASE 0x401c0000 /* 16KB GPIO3 */ - /* 0x401c4000 16KB Reserved */ - /* 0x401c8000 16KB Reserved */ - /* 0x401cc000 16KB Reserved */ -#define IMXRT_CAN1_BASE 0x401d0000 /* 16KB CAN1 */ -#define IMXRT_CAN2_BASE 0x401d4000 /* 16KB CAN2 */ - /* 0x401d8000 16KB Reserved */ -#define IMXRT_QTIMER1_BASE 0x401dc000 /* 16KB QTimer1 */ -#define IMXRT_QTIMER2_BASE 0x401e0000 /* 16KB QTimer2 */ - /* 0x401e4000 16KB Reserved */ - /* 0x401e8000 16KB Reserved */ -#define IMXRT_GPT1_BASE 0x401ec000 /* 16KB GPT1 */ -#define IMXRT_GPT2_BASE 0x401f0000 /* 16KB GPT2 */ -#define IMXRT_OCOTP_BASE 0x401f4000 /* 16KB OCOTP */ -#define IMXRT_IOMUXC_BASE 0x401f8000 /* 16KB IOMUXC */ -#define IMXRT_KPP_BASE 0x401fc000 /* 16KB KPP */ - -/* AIPS-3 memory map */ - - /* 0x40200000 256KB Reserved */ - /* 0x40240000 240KB Reserved */ -#define IMXRT_AIOS3CNF_BASE 0x4027c000 /* 16KB AIPS-3 Configuration */ - /* 0x40280000 16KB Reserved */ - /* 0x40284000 16KB Reserved */ - /* 0x40288000 16KB Reserved */ - /* 0x4028c000 16KB Reserved */ - /* 0x40290000 16KB Reserved */ - /* 0x40294000 16KB Reserved */ - /* 0x40298000 16KB Reserved */ - /* 0x4029c000 16KB Reserved */ - /* 0x402a0000 16KB Reserved */ - /* 0x402a4000 16KB Reserved */ -#define IMXRT_FLEXSPIC_BASE 0x402a8000 /* 16KB FlexSPI controller */ - /* 0x402ac000 16KB Reserved */ - /* 0x402b0000 16KB Reserved */ - /* 0x402b4000 16KB Reserved */ - /* 0x402b8000 16KB Reserved */ - /* 0x402bc000 16KB Reserved */ -#define IMXRT_USDHC1_BASE 0x402c0000 /* 16KB USDHC1 */ -#define IMXRT_USDHC2_BASE 0x402c4000 /* 16KB USDHC2 */ - /* 0x402c8000 16KB Reserved */ - /* 0x402cc000 16KB Reserved */ - /* 0x402d0000 16KB Reserved */ - /* 0x402d4000 16KB Reserved */ -#define IMXRT_ENET_BASE 0x402d8000 /* 16KB ENET */ - /* 0x402dc000 16KB Reserved */ -#define IMXRT_USB_BASE 0x402e0000 /* 16KB USB(USB) */ - /* 0x402e4000 16KB Reserved */ - /* 0x402e8000 16KB Reserved */ - /* 0x402ec000 16KB Reserved */ -#define IMXRT_SEMC_BASE 0x402f0000 /* 16KB SEMC */ - /* 0x402f4000 16KB Reserved */ - /* 0x402f8000 16KB Reserved */ -#define IMXRT_DCP_BASE 0x402fc000 /* 16KB DCP */ - -/* AIPS-4 memory map */ - - /* 0x40300000 256KB Reserved */ - /* 0x40340000 240KB Reserved */ -#define IMXRT_AIPS4CNF_BASE 0x4037c000 /* 16KB AIPS-4 Configuration */ -#define IMXRT_SPDIF_BASE 0x40380000 /* 16KB SPDIF */ -#define IMXRT_SAI1_BASE 0x40384000 /* 16KB SAI1 */ -#define IMXRT_SAI2_BASE 0x40388000 /* 16KB SAI2 */ -#define IMXRT_SAI3_BASE 0x4038c000 /* 16KB SAI3 */ - /* 0x40390000 16KB Reserved */ -#define IMXRT_LPSPI1_BASE 0x40394000 /* 16KB LPSPI1 */ -#define IMXRT_LPSPI2_BASE 0x40398000 /* 16KB LPSPI2 */ -#define IMXRT_LPSPI3_BASE 0x4039c000 /* 16KB LPSPI3 */ -#define IMXRT_LPSPI4_BASE 0x403a0000 /* 16KB LPSPI4 */ - /* 0x403a4000 16KB Reserved */ - /* 0x403a8000 16KB Reserved */ - /* 0x403ac000 16KB Reserved */ -#define IMXRT_ADCETC_BASE 0x403b0000 /* 16KB ADC_ETC */ -#define IMXRT_AOI1_BASE 0x403b4000 /* 16KB AOI1 */ - /* 0x403b8000 16KB Reserved */ -#define IMXRT_XBAR1_BASE 0x403bc000 /* 16KB XBAR1 */ -#define IMXRT_XBAR2_BASE 0x403c0000 /* 16KB XBAR2 */ - /* 0x403c4000 16KB Reserved */ -#define IMXRT_ENC1_BASE 0x403c8000 /* 16KB ENC1 */ -#define IMXRT_ENC2_BASE 0x403cc000 /* 16KB ENC2 */ - /* 0x403d0000 16KB Reserved */ - /* 0x403d4000 16KB Reserved */ - /* 0x403d8000 16KB Reserved */ -#define IMXRT_FLEXPWM1_BASE 0x403dc000 /* 16KB FLEXPWM1 */ -#define IMXRT_FLEXPWM2_BASE 0x403e0000 /* 16KB FLEXPWM2 */ - /* 0x403e4000 16KB Reserved */ - /* 0x403e8000 16KB Reserved */ -#define IMXRT_BEE_BASE 0x403ec000 /* 16KB BEE */ -#define IMXRT_LPI2C1_BASE 0x403f0000 /* 16KB */ -#define IMXRT_LPI2C2_BASE 0x403f4000 /* 16KB LPI2C2 */ -#define IMXRT_LPI2C3_BASE 0x403f8000 /* 16KB LPI2C3 */ -#define IMXRT_LPI2C4_BASE 0x403fc000 /* 16KB LPI2C4 */ - -/* PPB memory map */ - -#define IMXRT_TPIU_BASE 0xe0040000 /* 4KB TPIU */ -#define IMXRT_ETM_BASE 0xe0041000 /* 4KB ETM */ -#define IMXRT_CTI_BASE 0xe0042000 /* 4KB CTI */ -#define IMXRT_TSGEN_BASE 0xe0043000 /* 4KB TSGEN */ -#define IMXRT_PPBRES_BASE 0xe0044000 /* 4KB PPB RES */ - /* 0xe0045000 236KB PPB Reserved */ -#define IMXRT_MCM_BASE 0xe0080000 /* 4KB MCM */ - /* 0xe0081000 444KB PPB Reserved */ - /* 0xe00f0000 52KB PPB Reserved */ -#define IMXRT_SYSROM_BASE 0xe00fd000 /* 4KB SYS ROM */ -#define IMXRT_PROCROM_BASE 0xe00fe000 /* 4KB Processor ROM */ -#define IMXRT_PPBROM_BASE 0xe00ff000 /* 4KB PPB ROM */ - -#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_MEMORYMAP_H */ diff --git a/arch/arm/src/imxrt/chip/rt102x/imxrt102x_pinmux.h b/arch/arm/src/imxrt/chip/rt102x/imxrt102x_pinmux.h deleted file mode 100644 index 600f2565e3e..00000000000 --- a/arch/arm/src/imxrt/chip/rt102x/imxrt102x_pinmux.h +++ /dev/null @@ -1,914 +0,0 @@ -/***************************************************************************** - * arch/arm/src/imxrt/chip/rt102x/imxrt102x_pinmux.h - * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Dave Marples - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_PINMUX_H -#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_PINMUX_H - -/***************************************************************************** - * Included Files - *****************************************************************************/ - -#include -#include "chip/imxrt_iomuxc.h" - -/***************************************************************************** - * Pre-processor Definitions - *****************************************************************************/ - -/* Alternate Pin Functions. - * - * Alternative pin selections are provided with a numeric suffix like _1, _2, - * etc. Drivers, however, will use the pin selection without the numeric - * suffix. Additional definitions are required in the board.h file. - * For example, if LPUART1 CTS connects via the AD_B1_04 pin, then the - * following definition should appear in the board.h header file for - * that board: - * - * #define GPIO_LPUART3_CTS GPIO_LPUART3_CTS_1 - * - * The driver will then automatically configure to use the AD_B1_04 pin - * for LPUART1 CTS. - */ - -/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! - * Additional effort is required to select specific IOMUX options such as - * frequency, open-drain, push-pull, and pull-up/down! Just the basics are - * defined for most pins in this file. See the upper imxrt_gpio.h and - * imxrt_iomuxc.h header files for available definitions. - */ - -/* Analog Comparator (ACMP) */ - -#define GPIO_ACMP_OUT00 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_12_INDEX)) -#define GPIO_ACMP_OUT01 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_13_INDEX)) -#define GPIO_ACMP_OUT02 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_14_INDEX)) -#define GPIO_ACMP_OUT03 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_15_INDEX)) - -/* ARM */ - -#define GPIO_ARM_CM7_RXEV (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_15_INDEX)) -#define GPIO_ARM_CM7_TXEV (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_08_INDEX)) - -/* Clock Controller Module (CCM) */ - -#define GPIO_CCM_CLKO1 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_02_INDEX)) -#define GPIO_CCM_CLKO2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_03_INDEX)) -#define GPIO_CCM_PMIC_RDY (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_36_INDEX)) -#define GPIO_CCM_PMIC_READY_1 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_05_INDEX)) -#define GPIO_CCM_PMIC_READY_2 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_13_INDEX)) -#define GPIO_CCM_PMIC_READY_3 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_03_INDEX)) - -#define GPIO_CCM_PMIC_VSTBY_REQ (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_PMIC_STBY_REQ_INDEX)) -#define GPIO_CCM_REF_EN (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_09_INDEX)) -#define GPIO_CCM_STOP (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_06_INDEX)) -#define GPIO_CCM_WAIT (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_04_INDEX)) - -/* Ethernet (ENET) */ - -#define GPIO_ENET_1588_EVENT0_IN (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_15_INDEX)) -#define GPIO_ENET_1588_EVENT0_OUT (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_14_INDEX)) -#define GPIO_ENET_1588_EVENT1_IN (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_03_INDEX)) -#define GPIO_ENET_1588_EVENT1_OUT (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_02_INDEX)) -#define GPIO_ENET_1588_EVENT2_IN (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX)) -#define GPIO_ENET_1588_EVENT2_OUT (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX)) -#define GPIO_ENET_1588_EVENT3_IN (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX)) -#define GPIO_ENET_1588_EVENT3_OUT (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX)) -#define GPIO_ENET_COL (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_35_INDEX)) -#define GPIO_ENET_CRS (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_34_INDEX)) -#define GPIO_ENET_MDC_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_41_INDEX) | \ - IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ - IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) -#define GPIO_ENET_MDC_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_05_INDEX) | \ - IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ - IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) -#define GPIO_ENET_MDC_3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_03_INDEX) | \ - IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ - IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) -#define GPIO_ENET_MDIO_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_40_INDEX) | \ - IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_OPENDRAIN | \ - IOMUX_SPEED_LOW | IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) -#define GPIO_ENET_MDIO_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX) | \ - IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_OPENDRAIN | \ - IOMUX_SPEED_LOW | IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) -#define GPIO_ENET_MDIO_3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_02_INDEX) | \ - IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_OPENDRAIN | \ - IOMUX_SPEED_LOW | IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) -#define GPIO_ENET_RDATA00 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_10_INDEX)) -#define GPIO_ENET_RDATA01 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_09_INDEX)) - -#define GPIO_ENET_REF_CLK_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_04_INDEX) | \ - IOMUX_SLEW_FAST | IOMUX_DRIVE_40OHM | IOMUX_SPEED_LOW | \ - IOMUX_PULL_DOWN_100K | IOMUX_PULL_KEEP) -#define GPIO_ENET_REF_CLK_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_08_INDEX) | \ - IOMUX_SLEW_FAST | IOMUX_DRIVE_40OHM | IOMUX_SPEED_LOW | \ - IOMUX_PULL_DOWN_100K | IOMUX_PULL_KEEP) -#define GPIO_ENET_RX_CLK (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC36_INDEX)) -#define GPIO_ENET_RX_DATA00 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_06_INDEX) | \ - IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ - IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) -#define GPIO_ENET_RX_DATA01 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_05_INDEX) | \ - IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ - IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) -#define GPIO_ENET_RX_DATA02 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_38_INDEX)) -#define GPIO_ENET_RX_DATA03 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_37_INDEX)) -#define GPIO_ENET_RX_EN_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_11_INDEX) | \ - IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ - IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) -#define GPIO_ENET_RX_EN_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_07_INDEX) | \ - IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ - IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) -#define GPIO_ENET_RX_ER_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_12_INDEX) | \ - IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ - IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) -#define GPIO_ENET_RX_ER_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_08_INDEX) | \ - IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ - IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) -#define GPIO_ENET_TDATA00 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_14_INDEX) | \ - IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX ) -#define GPIO_ENET_TDATA01 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_15_INDEX) | \ - IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX ) -#define GPIO_ENET_TX_CLK_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_08_INDEX) | \ - IOMUX_SLEW_FAST | IOMUX_DRIVE_40OHM | IOMUX_SPEED_LOW | \ - IOMUX_PULL_DOWN_100K | IOMUX_PULL_KEEP | GPIO_SION_ENABLE ) -#define GPIO_ENET_TX_CLK_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_04_INDEX) | \ - IOMUX_SLEW_FAST | IOMUX_DRIVE_40OHM | IOMUX_SPEED_LOW | \ - IOMUX_PULL_DOWN_100K | IOMUX_PULL_KEEP | GPIO_SION_ENABLE ) -#define GPIO_ENET_TX_DATA00 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_10_INDEX) | \ - IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ - IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) -#define GPIO_ENET_TX_DATA01 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_11_INDEX) | \ - IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ - IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) -#define GPIO_ENET_TX_DATA02 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_41_INDEX)) -#define GPIO_ENET_TX_DATA03 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_40_INDEX)) -#define GPIO_ENET_TX_EN_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_13_INDEX) | \ - IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ - IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) -#define GPIO_ENET_TX_EN_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_09_INDEX) | \ - IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ - IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) -#define GPIO_ENET_TX_ER (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_39_INDEX)) - -/* External Watchdog Monitor (EWM) */ - -#define GPIO_EWM_OUT_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_28_INDEX)) -#define GPIO_EWM_OUT_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_04_INDEX)) -#define GPIO_EWM_OUT_3 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX)) - -/* Flexible Controller Area Network (FLEXCAN) */ - -#define GPIO_FLEXCAN1_RX_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_05_INDEX)) -#define GPIO_FLEXCAN1_RX_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_01_INDEX)) -#define GPIO_FLEXCAN1_RX_3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_01_INDEX)) -#define GPIO_FLEXCAN1_RX_4 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_15_INDEX)) -#define GPIO_FLEXCAN1_TX_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX)) -#define GPIO_FLEXCAN1_TX_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_00_INDEX)) -#define GPIO_FLEXCAN1_TX_3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_00_INDEX)) -#define GPIO_FLEXCAN1_TX_4 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_14_INDEX)) -#define GPIO_FLEXCAN2_RX_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_15_INDEX)) -#define GPIO_FLEXCAN2_RX_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_05_INDEX)) -#define GPIO_FLEXCAN2_RX_3 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_09_INDEX)) -#define GPIO_FLEXCAN2_RX_4 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX)) -#define GPIO_FLEXCAN2_TX_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_14_INDEX)) -#define GPIO_FLEXCAN2_TX_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_04_INDEX)) -#define GPIO_FLEXCAN2_TX_3 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_08_INDEX)) -#define GPIO_FLEXCAN2_TX_4 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX)) - -/* Flexible I/O (FlexIO) */ - -#define GPIO_FLEXIO1_FLEXIO00 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_15_INDEX)) -#define GPIO_FLEXIO1_FLEXIO01 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_14_INDEX)) -#define GPIO_FLEXIO1_FLEXIO02 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_13_INDEX)) -#define GPIO_FLEXIO1_FLEXIO03 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_12_INDEX)) -#define GPIO_FLEXIO1_FLEXIO04 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_11_INDEX)) -#define GPIO_FLEXIO1_FLEXIO05 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_10_INDEX)) -#define GPIO_FLEXIO1_FLEXIO06 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX)) -#define GPIO_FLEXIO1_FLEXIO07 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX)) -#define GPIO_FLEXIO1_FLEXIO08 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX)) -#define GPIO_FLEXIO1_FLEXIO09 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX)) -#define GPIO_FLEXIO1_FLEXIO10 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX)) -#define GPIO_FLEXIO1_FLEXIO11 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX)) -#define GPIO_FLEXIO1_FLEXIO12 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX)) -#define GPIO_FLEXIO1_FLEXIO13 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX)) -#define GPIO_FLEXIO1_FLEXIO14 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX)) -#define GPIO_FLEXIO1_FLEXIO15 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX)) -#define GPIO_FLEXIO1_FLEXIO16 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_04_INDEX)) -#define GPIO_FLEXIO1_FLEXIO17 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_05_INDEX)) -#define GPIO_FLEXIO1_FLEXIO18 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_06_INDEX)) -#define GPIO_FLEXIO1_FLEXIO19 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_07_INDEX)) -#define GPIO_FLEXIO1_FLEXIO20 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_08_INDEX)) -#define GPIO_FLEXIO1_FLEXIO21 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_09_INDEX)) -#define GPIO_FLEXIO1_FLEXIO22 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_18_INDEX)) -#define GPIO_FLEXIO1_FLEXIO23 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_19_INDEX)) -#define GPIO_FLEXIO1_FLEXIO24 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_20_INDEX)) -#define GPIO_FLEXIO1_FLEXIO25 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_21_INDEX)) -#define GPIO_FLEXIO1_FLEXIO26 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_22_INDEX)) -#define GPIO_FLEXIO1_FLEXIO27 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_23_INDEX)) -#define GPIO_FLEXIO1_FLEXIO28 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_24_INDEX)) -#define GPIO_FLEXIO1_FLEXIO29 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_25_INDEX)) -#define GPIO_FLEXIO1_FLEXIO30 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_26_INDEX)) -#define GPIO_FLEXIO1_FLEXIO31 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_27_INDEX)) - -/* Enhanced Flex Pulse Width Modulator (eFlexPWM) */ - -#define GPIO_FLEXPWM1_PWMA00_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_26_INDEX)) -#define GPIO_FLEXPWM1_PWMA00_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX)) -#define GPIO_FLEXPWM1_PWMA01_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_24_INDEX)) -#define GPIO_FLEXPWM1_PWMA01_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX)) -#define GPIO_FLEXPWM1_PWMA02_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_22_INDEX)) -#define GPIO_FLEXPWM1_PWMA02_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_10_INDEX)) -#define GPIO_FLEXPWM1_PWMA03_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_20_INDEX)) -#define GPIO_FLEXPWM1_PWMA03_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_12_INDEX)) -#define GPIO_FLEXPWM1_PWMB00_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_27_INDEX)) -#define GPIO_FLEXPWM1_PWMB00_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX)) -#define GPIO_FLEXPWM1_PWMB01_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_25_INDEX)) -#define GPIO_FLEXPWM1_PWMB01_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX)) -#define GPIO_FLEXPWM1_PWMB02_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_23_INDEX)) -#define GPIO_FLEXPWM1_PWMB02_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_11_INDEX)) -#define GPIO_FLEXPWM1_PWMB03_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_21_INDEX)) -#define GPIO_FLEXPWM1_PWMB03_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_13_INDEX)) -#define GPIO_FLEXPWM1_PWMX00 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_28_INDEX)) -#define GPIO_FLEXPWM1_PWMX01 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_29_INDEX)) -#define GPIO_FLEXPWM1_PWMX02 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_30_INDEX)) -#define GPIO_FLEXPWM1_PWMX03 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_31_INDEX)) -#define GPIO_FLEXPWM2_PWMA00_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_38_INDEX)) -#define GPIO_FLEXPWM2_PWMA00_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_14_INDEX)) -#define GPIO_FLEXPWM2_PWMA01_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_36_INDEX)) -#define GPIO_FLEXPWM2_PWMA01_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_12_INDEX)) -#define GPIO_FLEXPWM2_PWMA02_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_30_INDEX)) -#define GPIO_FLEXPWM2_PWMA02_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_10_INDEX)) -#define GPIO_FLEXPWM2_PWMA03_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_28_INDEX)) -#define GPIO_FLEXPWM2_PWMA03_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_06_INDEX)) -#define GPIO_FLEXPWM2_PWMB00_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_39_INDEX)) -#define GPIO_FLEXPWM2_PWMB00_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_15_INDEX)) -#define GPIO_FLEXPWM2_PWMB01_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_37_INDEX)) -#define GPIO_FLEXPWM2_PWMB01_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_13_INDEX)) -#define GPIO_FLEXPWM2_PWMB02_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_31_INDEX)) -#define GPIO_FLEXPWM2_PWMB02_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_11_INDEX)) -#define GPIO_FLEXPWM2_PWMB03_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_29_INDEX)) -#define GPIO_FLEXPWM2_PWMB03_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_07_INDEX)) -#define GPIO_FLEXPWM2_PWMX00 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_10_INDEX)) -#define GPIO_FLEXPWM2_PWMX01 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_11_INDEX)) -#define GPIO_FLEXPWM2_PWMX02 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_12_INDEX)) -#define GPIO_FLEXPWM2_PWMX03 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_13_INDEX)) - -/* Flexible SPI (FlexSPI) */ - -#define GPIO_FLEXSPIA_DATA00_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX)) -#define GPIO_FLEXSPIA_DATA00_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_08_INDEX)) -#define GPIO_FLEXSPIA_DATA01_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX)) -#define GPIO_FLEXSPIA_DATA01_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_10_INDEX)) -#define GPIO_FLEXSPIA_DATA02_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX)) -#define GPIO_FLEXSPIA_DATA02_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_09_INDEX)) -#define GPIO_FLEXSPIA_DATA03_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX)) -#define GPIO_FLEXSPIA_DATA03_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_06_INDEX)) -#define GPIO_FLEXSPIA_DQS (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_05_INDEX)) -#define GPIO_FLEXSPIA_SCLK_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX)) -#define GPIO_FLEXSPIA_SCLK_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_07_INDEX)) -#define GPIO_FLEXSPIA_SS0_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX)) -#define GPIO_FLEXSPIA_SS0_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_11_INDEX)) -#define GPIO_FLEXSPIA_SS1_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_01_INDEX)) -#define GPIO_FLEXSPIA_SS1_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_00_INDEX)) - -#define GPIO_FLEXSPIB_DATA00 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_02_INDEX)) -#define GPIO_FLEXSPIB_DATA01 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_04_INDEX)) -#define GPIO_FLEXSPIB_DATA02 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_03_INDEX)) -#define GPIO_FLEXSPIB_DATA03 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_00_INDEX)) -#define GPIO_FLEXSPIB_DQS (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_05_INDEX)) -#define GPIO_FLEXSPIB_SCLK (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_01_INDEX)) -#define GPIO_FLEXSPIB_SS0_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_05_INDEX)) -#define GPIO_FLEXSPIB_SS0_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_04_INDEX)) -#define GPIO_FLEXSPIB_SS1 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_01_INDEX)) - -/* GPIO */ - -#define GPIO_GPIO1_IO00 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_00_INDEX)) -#define GPIO_GPIO1_IO01 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_01_INDEX)) -#define GPIO_GPIO1_IO02 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_02_INDEX)) -#define GPIO_GPIO1_IO03 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_03_INDEX)) -#define GPIO_GPIO1_IO04 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX)) -#define GPIO_GPIO1_IO05 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_05_INDEX)) -#define GPIO_GPIO1_IO06 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_06_INDEX)) -#define GPIO_GPIO1_IO07 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_07_INDEX)) -#define GPIO_GPIO1_IO08 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_08_INDEX)) -#define GPIO_GPIO1_IO09 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_09_INDEX)) -#define GPIO_GPIO1_IO10 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_10_INDEX)) -#define GPIO_GPIO1_IO11 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_11_INDEX)) -#define GPIO_GPIO1_IO12 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_12_INDEX)) -#define GPIO_GPIO1_IO13 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_13_INDEX)) -#define GPIO_GPIO1_IO14 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_14_INDEX)) -#define GPIO_GPIO1_IO15 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_15_INDEX)) -#define GPIO_GPIO1_IO16 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX)) -#define GPIO_GPIO1_IO17 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX)) -#define GPIO_GPIO1_IO18 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX)) -#define GPIO_GPIO1_IO19 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX)) -#define GPIO_GPIO1_IO20 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX)) -#define GPIO_GPIO1_IO21 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX)) -#define GPIO_GPIO1_IO22 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX)) -#define GPIO_GPIO1_IO23 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX)) -#define GPIO_GPIO1_IO24 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX)) -#define GPIO_GPIO1_IO25 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX)) -#define GPIO_GPIO1_IO26 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_10_INDEX)) -#define GPIO_GPIO1_IO27 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_11_INDEX)) -#define GPIO_GPIO1_IO28 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_12_INDEX)) -#define GPIO_GPIO1_IO29 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_13_INDEX)) -#define GPIO_GPIO1_IO30 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_14_INDEX)) -#define GPIO_GPIO1_IO31 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_15_INDEX)) - -#define GPIO_GPIO2_IO00 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_00_INDEX)) -#define GPIO_GPIO2_IO01 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_01_INDEX)) -#define GPIO_GPIO2_IO02 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_02_INDEX)) -#define GPIO_GPIO2_IO03 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_03_INDEX)) -#define GPIO_GPIO2_IO04 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_04_INDEX)) -#define GPIO_GPIO2_IO05 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_05_INDEX)) -#define GPIO_GPIO2_IO06 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_06_INDEX)) -#define GPIO_GPIO2_IO07 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_07_INDEX)) -#define GPIO_GPIO2_IO08 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_08_INDEX)) -#define GPIO_GPIO2_IO09 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_09_INDEX)) -#define GPIO_GPIO2_IO10 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_10_INDEX)) -#define GPIO_GPIO2_IO11 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_11_INDEX)) -#define GPIO_GPIO2_IO12 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_12_INDEX)) -#define GPIO_GPIO2_IO13 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_13_INDEX)) -#define GPIO_GPIO2_IO14 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_14_INDEX)) -#define GPIO_GPIO2_IO15 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_15_INDEX)) -#define GPIO_GPIO2_IO16 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_16_INDEX)) -#define GPIO_GPIO2_IO17 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_17_INDEX)) -#define GPIO_GPIO2_IO18 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_18_INDEX)) -#define GPIO_GPIO2_IO19 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_19_INDEX)) -#define GPIO_GPIO2_IO20 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_20_INDEX)) -#define GPIO_GPIO2_IO21 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_21_INDEX)) -#define GPIO_GPIO2_IO22 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_22_INDEX)) -#define GPIO_GPIO2_IO23 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_23_INDEX)) -#define GPIO_GPIO2_IO24 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_24_INDEX)) -#define GPIO_GPIO2_IO25 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_25_INDEX)) -#define GPIO_GPIO2_IO26 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_26_INDEX)) -#define GPIO_GPIO2_IO27 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_27_INDEX)) -#define GPIO_GPIO2_IO28 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_28_INDEX)) -#define GPIO_GPIO2_IO29 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_29_INDEX)) -#define GPIO_GPIO2_IO30 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_30_INDEX)) -#define GPIO_GPIO2_IO31 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_31_INDEX)) - -#define GPIO_GPIO3_IO00 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC32_INDEX)) -#define GPIO_GPIO3_IO01 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC33_INDEX)) -#define GPIO_GPIO3_IO02 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC34_INDEX)) -#define GPIO_GPIO3_IO03 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC39_INDEX)) -#define GPIO_GPIO3_IO04 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC36_INDEX)) -#define GPIO_GPIO3_IO05 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC37_INDEX)) -#define GPIO_GPIO3_IO06 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC38_INDEX)) -#define GPIO_GPIO3_IO07 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC39_INDEX)) -#define GPIO_GPIO3_IO08 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC40_INDEX)) -#define GPIO_GPIO3_IO09 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC41_INDEX)) -#define GPIO_GPIO3_IO13 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_00_INDEX)) -#define GPIO_GPIO3_IO14 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_01_INDEX)) -#define GPIO_GPIO3_IO15 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_02_INDEX)) -#define GPIO_GPIO3_IO16 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_03_INDEX)) -#define GPIO_GPIO3_IO17 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_04_INDEX)) -#define GPIO_GPIO3_IO18 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_05_INDEX)) -#define GPIO_GPIO3_IO19 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_06_INDEX)) -#define GPIO_GPIO3_IO20 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_00_INDEX)) -#define GPIO_GPIO3_IO21 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_01_INDEX)) -#define GPIO_GPIO3_IO22 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_02_INDEX)) -#define GPIO_GPIO3_IO23 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_03_INDEX)) -#define GPIO_GPIO3_IO24 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_04_INDEX)) -#define GPIO_GPIO3_IO25 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_05_INDEX)) -#define GPIO_GPIO3_IO26 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_06_INDEX)) -#define GPIO_GPIO3_IO27 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_07_INDEX)) -#define GPIO_GPIO3_IO28 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_08_INDEX)) -#define GPIO_GPIO3_IO29 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_09_INDEX)) -#define GPIO_GPIO3_IO30 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_10_INDEX)) -#define GPIO_GPIO3_IO31 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_11_INDEX)) - -#define GPIO_GPIO5_IO00 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_WAKEUP_INDEX)) -#define GPIO_GPIO5_IO01 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_PMIC_ON_REQ_INDEX)) -#define GPIO_GPIO5_IO02 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_PMIC_STBY_REQ_INDEX)) - -/* General Purpose Timer (GPT) */ - -#define GPIO_GPT1_CAPTURE1 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_02_INDEX)) -#define GPIO_GPT1_CAPTURE2 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_01_INDEX)) -#define GPIO_GPT1_CLK (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC39_INDEX)) -#define GPIO_GPT1_COMPARE1 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_00_INDEX)) -#define GPIO_GPT1_COMPARE2 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_41_INDEX)) -#define GPIO_GPT1_COMPARE3 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_40_INDEX)) - -#define GPIO_GPT2_CAPTURE1 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_10_INDEX)) -#define GPIO_GPT2_CAPTURE2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_28_INDEX)) -#define GPIO_GPT2_CLK (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_31_INDEX)) -#define GPIO_GPT2_COMPARE1 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_11_INDEX)) -#define GPIO_GPT2_COMPARE2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_29_INDEX)) -#define GPIO_GPT2_COMPARE3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_30_INDEX)) - -/* JTAG */ - -#define GPIO_JTAG_MOD (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_02_INDEX)) -#define GPIO_JTAG_TCK (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_01_INDEX)) -#define GPIO_JTAG_TDI (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_3_INDEX)) -#define GPIO_JTAG_TDO (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX)) -#define GPIO_JTAG_TMS (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_00_INDEX)) -#define GPIO_JTAG_TRSTB (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_05_INDEX)) - -/* Keypad Port (KPP) */ - -#define GPIO_KPP_COL00 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_08_INDEX)) -#define GPIO_KPP_COL01 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_10_INDEX)) -#define GPIO_KPP_COL02 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_12_INDEX)) -#define GPIO_KPP_COL03 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_14_INDEX)) -#define GPIO_KPP_COL04 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX)) -#define GPIO_KPP_COL05 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX)) -#define GPIO_KPP_COL06 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX)) -#define GPIO_KPP_COL07 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX)) -#define GPIO_KPP_ROW00 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_09_INDEX)) -#define GPIO_KPP_ROW01 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_11_INDEX)) -#define GPIO_KPP_ROW02 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_13_INDEX)) -#define GPIO_KPP_ROW03 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_15_INDEX)) -#define GPIO_KPP_ROW04 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX)) -#define GPIO_KPP_ROW05 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX)) -#define GPIO_KPP_ROW06 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX)) -#define GPIO_KPP_ROW07 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX)) - -/* Low Power Inter-Integrated Circuit (LPI2C) */ - -#define GPIO_LPI2C1_HREQ (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_13_INDEX)) -#define GPIO_LPI2C1_SCL_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_14_INDEX)) -#define GPIO_LPI2C1_SCL_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_02_INDEX) | \ - GPIO_SION_ENABLE | IOMUX_PULL_UP_22K | IOMUX_OPENDRAIN | \ - IOMUX_SPEED_MEDIUM | IOMUX_DRIVE_33OHM) -#define GPIO_LPI2C1_SDA_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_15_INDEX)) -#define GPIO_LPI2C1_SDA_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_03_INDEX) | \ - GPIO_SION_ENABLE | IOMUX_PULL_UP_22K | IOMUX_OPENDRAIN | \ - IOMUX_SPEED_MEDIUM | IOMUX_DRIVE_33OHM) - -#define GPIO_LPI2C2_SCL_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX)) -#define GPIO_LPI2C2_SCL_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_19_INDEX)) -#define GPIO_LPI2C2_SDA_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX)) -#define GPIO_LPI2C2_SDA_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_18_INDEX)) - -#define GPIO_LPI2C3_SCL_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_08_INDEX)) -#define GPIO_LPI2C3_SCL_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_00_INDEX) | \ - GPIO_SION_ENABLE | IOMUX_OPENDRAIN | IOMUX_SPEED_MEDIUM | IOMUX_DRIVE_33OHM) -#define GPIO_LPI2C3_SDA_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_09_INDEX)) -#define GPIO_LPI2C3_SDA_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_01_INDEX) | \ - GPIO_SION_ENABLE | IOMUX_OPENDRAIN | IOMUX_SPEED_MEDIUM | IOMUX_DRIVE_33OHM) - -#define GPIO_LPI2C4_SCL_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_11_INDEX) | \ - IOMUX_OPENDRAIN | IOMUX_SPEED_MEDIUM | IOMUX_DRIVE_33OHM) -#define GPIO_LPI2C4_SDA_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_10_INDEX) | \ - GPIO_SION_ENABLE | IOMUX_OPENDRAIN | IOMUX_SPEED_MEDIUM | IOMUX_DRIVE_33OHM) -#define GPIO_LPI2C4_SDA_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_03_INDEX) | \ - GPIO_SION_ENABLE | IOMUX_OPENDRAIN | IOMUX_SPEED_MEDIUM | IOMUX_DRIVE_33OHM) - -/* Low Power Serial Peripheral Interface (LPSPI) */ - -#define IOMUX_LPSPI (IOMUX_PULL_UP_100K | IOMUX_CMOS_OUTPUT | IOMUX_DRIVE_40OHM | \ - IOMUX_SLEW_FAST | IOMUX_SPEED_MEDIUM) - -#define GPIO_LPSPI1_PCS0_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_11_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI1_PCS0_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_03_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI1_PCS1 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI1_PCS2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI1_PCS3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI1_SCK_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_10_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI1_SCK_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_02_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI1_SDI_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_13_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI1_SDI_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_05_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI1_SDO_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_12_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI1_SDO_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_04_INDEX) | IOMUX_LPSPI) - -#define GPIO_LPSPI2_PCS0_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_01_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI2_PCS0_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_11_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI2_PCS0_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_06_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI2_PCS1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_14_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI2_PCS2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_10_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI2_PCS3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_11_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI2_SCK_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_00_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI2_SCK_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_10_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI2_SCK_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_07_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI2_SDI_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_03_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI2_SDI_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_13_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI2_SDI_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_09_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI2_SDO_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_02_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI2_SDO_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_12_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI2_SDO_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_08_INDEX) | IOMUX_LPSPI) - -#define GPIO_LPSPI3_PCS0 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_13_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI3_PCS1 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI3_PCS2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI3_PCS3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI3_SCK (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_12_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI3_SDI (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_15_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI3_SDO (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_14_INDEX) | IOMUX_LPSPI) - -#define GPIO_LPSPI4_PCS0_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI4_PCS0_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_33_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI4_PCS1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_36_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI4_PCS2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_37_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI4_PCS3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_38_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI4_SCK_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI4_SCK_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_32_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI4_SDI_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI4_SDI_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_35_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI4_SDO_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI4_SDO_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_34_INDEX) | IOMUX_LPSPI) - -/* Low Power Universal Asynchronous Receiver/Transmitter (LPUART) */ - -#define IOMUX_UART (IOMUX_PULL_UP_100K | IOMUX_CMOS_OUTPUT | IOMUX_DRIVE_40OHM | \ - IOMUX_SLEW_FAST | IOMUX_SPEED_MEDIUM | IOMUX_SCHMITT_TRIGGER) - -#define GPIO_LPUART1_CTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_08_INDEX)) -#define GPIO_LPUART1_RTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_09_INDEX)) -#define GPIO_LPUART1_RX (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_07_INDEX) | IOMUX_UART) -#define GPIO_LPUART1_TX (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_06_INDEX) | IOMUX_UART) - -#define GPIO_LPUART2_CTS_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_20_INDEX)) -#define GPIO_LPUART2_CTS_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX)) -#define GPIO_LPUART2_RTS_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_21_INDEX)) -#define GPIO_LPUART2_RTS_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX)) -#define GPIO_LPUART2_RX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_23_INDEX) | IOMUX_UART) -#define GPIO_LPUART2_RX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX) | IOMUX_UART) -#define GPIO_LPUART2_TX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_22_INDEX) | IOMUX_UART) -#define GPIO_LPUART2_TX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX) | IOMUX_UART) - -#define GPIO_LPUART3_CTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_12_INDEX)) -#define GPIO_LPUART3_RTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_13_INDEX)) -#define GPIO_LPUART3_RX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_07_INDEX) | IOMUX_UART) -#define GPIO_LPUART3_RX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_15_INDEX) | IOMUX_UART) -#define GPIO_LPUART3_TX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_06_INDEX) | IOMUX_UART) -#define GPIO_LPUART3_TX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_14_INDEX) | IOMUX_UART) - -#define GPIO_LPUART4_CTS_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_00_INDEX)) -#define GPIO_LPUART4_CTS_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_30_INDEX)) -#define GPIO_LPUART4_RTS_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_01_INDEX)) -#define GPIO_LPUART4_RTS_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_31_INDEX)) -#define GPIO_LPUART4_RX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_03_INDEX) | IOMUX_UART) -#define GPIO_LPUART4_RX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_33_INDEX) | IOMUX_UART) -#define GPIO_LPUART4_RX_3 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_11_INDEX) | IOMUX_UART) -#define GPIO_LPUART4_TX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_02_INDEX) | IOMUX_UART) -#define GPIO_LPUART4_TX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_32_INDEX) | IOMUX_UART) -#define GPIO_LPUART4_TX_3 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_10_INDEX) | IOMUX_UART) - -#define GPIO_LPUART5_CTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_36_INDEX)) -#define GPIO_LPUART5_RTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_37_INDEX)) -#define GPIO_LPUART5_RX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_39_INDEX) | IOMUX_UART) -#define GPIO_LPUART5_RX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_11_INDEX)) -#define GPIO_LPUART5_TX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_38_INDEX) | IOMUX_UART) -#define GPIO_LPUART5_TX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_10_INDEX)) - -#define GPIO_LPUART6_CTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_14_INDEX)) -#define GPIO_LPUART6_RTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_15_INDEX)) -#define GPIO_LPUART6_RX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_13_INDEX) | IOMUX_UART) -#define GPIO_LPUART6_RX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_01_INDEX) | IOMUX_UART) -#define GPIO_LPUART6_TX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_12_INDEX) | IOMUX_UART) -#define GPIO_LPUART6_TX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_00_INDEX) | IOMUX_UART) - -#define GPIO_LPUART7_CTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_02_INDEX)) -#define GPIO_LPUART7_RTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_03_INDEX)) -#define GPIO_LPUART7_RX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_35_INDEX)) -#define GPIO_LPUART7_RX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_05_INDEX)) -#define GPIO_LPUART7_TX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_34_INDEX)) -#define GPIO_LPUART7_TX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_04_INDEX)) - -#define GPIO_LPUART8_CTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_24_INDEX)) -#define GPIO_LPUART8_RTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_25_INDEX)) -#define GPIO_LPUART8_RX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_27_INDEX) | IOMUX_UART) -#define GPIO_LPUART8_RX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_03_INDEX) | IOMUX_UART) -#define GPIO_LPUART8_TX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_26_INDEX) | IOMUX_UART) -#define GPIO_LPUART8_TX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_02_INDEX) | IOMUX_UART) - -/* Medium Quality Sound (MQS) */ - -#define GPIO_MQS_LEFT_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_07_INDEX)) -#define GPIO_MQS_LEFT_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_17_INDEX)) -#define GPIO_MQS_LEFT_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_38_INDEX)) -#define GPIO_MQS_RIGHT_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_06_INDEX)) -#define GPIO_MQS_RIGHT_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_16_INDEX)) -#define GPIO_MQS_RIGHT_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_37_INDEX)) - -/* NMI */ - -#define GPIO_NMI_GLUE_NMI_1 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_WAKEUP_INDEX)) -#define GPIO_NMI_GLUE_NMI_2 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_BO_05_INDEX)) - -/* Periodic Interrupt Timer (PIT) */ - -#define GPIO_PIT_TRIGGER0 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_06_INDEX)) -#define GPIO_PIT_TRIGGER1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_07_INDEX)) -#define GPIO_PIT_TRIGGER2 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_00_INDEX)) -#define GPIO_PIT_TRIGGER3 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_01_INDEX)) - -/* Quad Timer (QTimer) */ - -#define GPIO_QTIMER1_TIMER0_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_32_INDEX)) -#define GPIO_QTIMER1_TIMER0_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_00INDEX)) -#define GPIO_QTIMER1_TIMER1_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_33_INDEX)) -#define GPIO_QTIMER1_TIMER1_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_01_INDEX)) -#define GPIO_QTIMER1_TIMER2_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_34_INDEX)) -#define GPIO_QTIMER1_TIMER2_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_02_INDEX)) -#define GPIO_QTIMER1_TIMER3_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_35_INDEX)) -#define GPIO_QTIMER1_TIMER3_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_03_INDEX)) - -#define GPIO_QTIMER2_TIMER0_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_00_INDEX)) -#define GPIO_QTIMER2_TIMER0_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX)) -#define GPIO_QTIMER2_TIMER1_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_01_INDEX)) -#define GPIO_QTIMER2_TIMER1_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_05_INDEX)) -#define GPIO_QTIMER2_TIMER2_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_02_INDEX)) -#define GPIO_QTIMER2_TIMER2_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_06_INDEX)) -#define GPIO_QTIMER2_TIMER3_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_03_INDEX)) -#define GPIO_QTIMER2_TIMER3_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_BO_07_INDEX)) - -/* Synchronous Audio Interface (SAI) */ - -#define GPIO_SAI1_MCLK_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_00_INDEX)) -#define GPIO_SAI1_MCLK_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_20_INDEX)) -#define GPIO_SAI1_MCLK_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_03_INDEX)) -#define GPIO_SAI1_MCLK_4 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX)) -#define GPIO_SAI1_RX_BCLK_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_14_INDEX)) -#define GPIO_SAI1_RX_BCLK_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_19_INDEX)) -#define GPIO_SAI1_RX_BCLK_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX)) -#define GPIO_SAI1_RX_DATA00_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_13_INDEX)) -#define GPIO_SAI1_RX_DATA00_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_21_INDEX)) -#define GPIO_SAI1_RX_DATA00_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX)) -#define GPIO_SAI1_RX_SYNC_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_15_INDEX)) -#define GPIO_SAI1_RX_SYNC_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_18_INDEX)) -#define GPIO_SAI1_RX_SYNC_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX)) -#define GPIO_SAI1_TX_BCLK_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_11_INDEX)) -#define GPIO_SAI1_TX_BCLK_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_26_INDEX)) -#define GPIO_SAI1_TX_BCLK_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX)) -#define GPIO_SAI1_TX_DATA00_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_12_INDEX)) -#define GPIO_SAI1_TX_DATA00_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_25_INDEX)) -#define GPIO_SAI1_TX_DATA00_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX)) -#define GPIO_SAI1_TX_DATA01_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_24_INDEX)) -#define GPIO_SAI1_TX_DATA01_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX)) -#define GPIO_SAI1_TX_DATA02_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_23_INDEX)) -#define GPIO_SAI1_TX_DATA02_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX)) -#define GPIO_SAI1_TX_DATA03_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_28_INDEX)) -#define GPIO_SAI1_TX_DATA03_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX)) -#define GPIO_SAI1_TX_SYNC_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_10_INDEX)) -#define GPIO_SAI1_TX_SYNC_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_27_INDEX)) -#define GPIO_SAI1_TX_SYNC_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX)) - -#define GPIO_SAI2_MCLK_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_16_INDEX)) -#define GPIO_SAI2_MCLK_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_00_INDEX)) -#define GPIO_SAI2_RX_BCLK_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_09_INDEX)) -#define GPIO_SAI2_RX_BCLK_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_02_INDEX)) -#define GPIO_SAI2_RX_DATA_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_08_INDEX)) -#define GPIO_SAI2_RX_DATA_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_03_INDEX)) -#define GPIO_SAI2_RX_SYNC_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_07_INDEX)) -#define GPIO_SAI2_RX_SYNC_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_01_INDEX)) -#define GPIO_SAI2_TX_BCLK_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_04_INDEX)) -#define GPIO_SAI2_TX_BCLK_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_05_INDEX)) -#define GPIO_SAI2_TX_DATA_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_06_INDEX)) -#define GPIO_SAI2_TX_DATA_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_04_INDEX)) -#define GPIO_SAI2_TX_SYNC_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_05_INDEX)) -#define GPIO_SAI2_TX_SYNC_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_06_INDEX)) - -#define GPIO_SAI3_MCLK_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_17_INDEX)) -#define GPIO_SAI3_MCLK_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_28_INDEX)) -#define GPIO_SAI3_MCLK_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_05_INDEX)) -#define GPIO_SAI3_RX_BCLK_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_29_INDEX)) -#define GPIO_SAI3_RX_BCLK_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_09_INDEX)) -#define GPIO_SAI3_RX_DATA_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_31_INDEX)) -#define GPIO_SAI3_RX_DATA_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_11_INDEX)) -#define GPIO_SAI3_RX_SYNC_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_30_INDEX)) -#define GPIO_SAI3_RX_SYNC_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_10_INDEX)) -#define GPIO_SAI3_TX_BCLK_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_33_INDEX)) -#define GPIO_SAI3_TX_BCLK_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_06_INDEX)) -#define GPIO_SAI3_TX_DATA_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_32_INDEX)) -#define GPIO_SAI3_TX_DATA_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_08_INDEX)) -#define GPIO_SAI3_TX_SYNC_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_34_INDEX)) -#define GPIO_SAI3_TX_SYNC_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_07_INDEX)) - -/* Smart External Memory Controller (SEMC) */ - -#define GPIO_SEMC_ADDR00 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_16_INDEX)) -#define GPIO_SEMC_ADDR01 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_17_INDEX)) -#define GPIO_SEMC_ADDR02 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_18_INDEX)) -#define GPIO_SEMC_ADDR03 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_19_INDEX)) -#define GPIO_SEMC_ADDR04 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_20_INDEX)) -#define GPIO_SEMC_ADDR05 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_21_INDEX)) -#define GPIO_SEMC_ADDR06 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_22_INDEX)) -#define GPIO_SEMC_ADDR07 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_23_INDEX)) -#define GPIO_SEMC_ADDR08 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_24_INDEX)) -#define GPIO_SEMC_ADDR09 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_25_INDEX)) -#define GPIO_SEMC_ADDR10 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_15_INDEX)) -#define GPIO_SEMC_ADDR11 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_26_INDEX)) -#define GPIO_SEMC_ADDR12 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_27_INDEX)) -#define GPIO_SEMC_BA0 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_13_INDEX)) -#define GPIO_SEMC_BA1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_14_INDEX)) -#define GPIO_SEMC_CAS (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_10_INDEX)) -#define GPIO_SEMC_CKE (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_29_INDEX)) -#define GPIO_SEMC_CLK (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_30_INDEX)) -#define GPIO_SEMC_CS0 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_12_INDEX)) -#define GPIO_SEMC_CSX00_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_40_INDEX)) -#define GPIO_SEMC_CSX00_2 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX)) -#define GPIO_SEMC_CSX01 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX)) -#define GPIO_SEMC_CSX02 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX)) -#define GPIO_SEMC_CSX03 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX)) -#define GPIO_SEMC_DATA00 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_00_INDEX)) -#define GPIO_SEMC_DATA01 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_01_INDEX)) -#define GPIO_SEMC_DATA02 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_02_INDEX)) -#define GPIO_SEMC_DATA03 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_03_INDEX)) -#define GPIO_SEMC_DATA04 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_04_INDEX)) -#define GPIO_SEMC_DATA05 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_05_INDEX)) -#define GPIO_SEMC_DATA06 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_06_INDEX)) -#define GPIO_SEMC_DATA07 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_07_INDEX)) -#define GPIO_SEMC_DATA08 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_32_INDEX)) -#define GPIO_SEMC_DATA09 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_33_INDEX)) -#define GPIO_SEMC_DATA10 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_34_INDEX)) -#define GPIO_SEMC_DATA11 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_35_INDEX)) -#define GPIO_SEMC_DATA12 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_36_INDEX)) -#define GPIO_SEMC_DATA13 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_37_INDEX)) -#define GPIO_SEMC_DATA14 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_38_INDEX)) -#define GPIO_SEMC_DATA15 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_39_INDEX)) -#define GPIO_SEMC_DM00 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_08_INDEX)) -#define GPIO_SEMC_DM01 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_31_INDEX)) -#define GPIO_SEMC_DQS (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_28_INDEX)) -#define GPIO_SEMC_RAS (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_11_INDEX)) -#define GPIO_SEMC_RDY_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_41_INDEX)) -#define GPIO_SEMC_RDY_2 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX)) -#define GPIO_SEMC_WE (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_09_INDEX)) - -/* Secure Non-Volatile Storage (SNVS) */ - -#define GPIO_SNVS_LP_PMIC_ON_REQ (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_PMIC_ON_REQ_INDEX)) -#define GPIO_SNVS_VIO_5 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_13_INDEX)) -#define GPIO_SNVS_VIO_5_CTL (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_12_INDEX)) - -/* Sony/Philips Digital Interface (SPDIF) */ - -#define GPIO_SPDIF_EXT_CLK (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_03_INDEX)) -#define GPIO_SPDIF_IN_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_05_INDEX)) -#define GPIO_SPDIF_IN_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_41_INDEX)) -#define GPIO_SPDIF_LOCK (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_02_INDEX)) -#define GPIO_SPDIF_OUT_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_04_INDEX)) -#define GPIO_SPDIF_OUT_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_40_INDEX)) -#define GPIO_SPDIF_OUT_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_01_INDEX)) -#define GPIO_SPDIF_SR_CLK (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_00_INDEX)) - -/* Boot Configuration */ - -#define GPIO_SRC_BOOT_MODE00 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_16_INDEX)) -#define GPIO_SRC_BOOT_MODE01 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_17_INDEX)) - -#define GPIO_SRC_BOOT_CFG00 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_18_INDEX)) -#define GPIO_SRC_BOOT_CFG01 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_19_INDEX)) -#define GPIO_SRC_BOOT_CFG02 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_20_INDEX)) -#define GPIO_SRC_BOOT_CFG03 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_21_INDEX)) -#define GPIO_SRC_BOOT_CFG04 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_22_INDEX)) -#define GPIO_SRC_BOOT_CFG05 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_23_INDEX)) -#define GPIO_SRC_BOOT_CFG06 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_24_INDEX)) -#define GPIO_SRC_BOOT_CFG07 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_25_INDEX)) -#define GPIO_SRC_BOOT_CFG08 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_26_INDEX)) -#define GPIO_SRC_BOOT_CFG09 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_27_INDEX)) - -#define GPIO_SRC_EARLY_RESET (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_11_INDEX)) -#define GPIO_SRC_POR_B (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_POR_B)) -#define GPIO_SRC_RESET_B (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_ONOFF)) -#define GPIO_SRC_SYSTEM_RESET (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_10_INDEX)) -#define GPIO_SRC_TESTER_ACK (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_33_INDEX)) - -/* USB OTG */ - -#define GPIO_USB_OTG_ID_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_11_INDEX)) -#define GPIO_USB_OTG_ID_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_39_INDEX)) -#define GPIO_USB_OTG_ID_3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_05_INDEX)) -#define GPIO_USB_OTG_OC_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_12_INDEX)) -#define GPIO_USB_OTG_OC_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_39_INDEX)) -#define GPIO_USB_OTG_OC_3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_03_INDEX)) -#define GPIO_USB_OTG_PWR_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_10_INDEX)) -#define GPIO_USB_OTG_PWR_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_41_INDEX)) -#define GPIO_USB_OTG_PWR_3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX)) - -#define GPIO_USBPHY1_TSTI_TX_DN (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_06_INDEX)) -#define GPIO_USBPHY1_TSTI_TX_DP (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_33_INDEX)) -#define GPIO_USBPHY1_TSTI_TX_EN (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_00_INDEX)) -#define GPIO_USBPHY1_TSTI_TX_HIZ (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_01_INDEX)) -#define GPIO_USBPHY1_TSTI_TX_HS_MODE (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_05_INDEX)) -#define GPIO_USBPHY1_TSTI_TX_LS_MODE (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_02_INDEX)) -#define GPIO_USBPHY1_TSTO_PLL_CLK20DIV (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_04_INDEX)) -#define GPIO_USBPHY1_TSTO_RX_DISC_DET (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_08_INDEX)) -#define GPIO_USBPHY1_TSTO_RX_FS_RXD (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_32_INDEX)) -#define GPIOUSBPHY1_TSTO_RX_HS_RXD (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_09_INDEX)) -#define GPIO_USBPHY1_TSTO_RX_SQUELCH (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_07_INDEX)) - -/* Ultra Secured Digital Host Controller (uSDHC) */ - -#define GPIO_USDHC1_CD_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_06_INDEX)) -#define GPIO_USDHC1_CD_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_05_INDEX)) -#define GPIO_USDHC1_CD_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_10_INDEX)) -#define GPIO_USDHC1_CD_4 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_38_INDEX)) -#define GPIO_USDHC1_CLK (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_03_INDEX)) -#define GPIO_USDHC1_CMD (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_02_INDEX)) -#define GPIO_USDHC1_DATA0 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_04_INDEX)) -#define GPIO_USDHC1_DATA1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_05_INDEX)) -#define GPIO_USDHC1_DATA2 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_00_INDEX)) -#define GPIO_USDHC1_DATA3 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_01_INDEX)) -#define GPIO_USDHC1_RESET_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX)) -#define GPIO_USDHC1_RESET_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_06_INDEX)) -#define GPIO_USDHC1_VSELECT_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX)) -#define GPIO_USDHC1_VSELECT_2 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_37_INDEX)) -#define GPIO_USDHC1_WP_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX)) -#define GPIO_USDHC1_WP_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX)) -#define GPIO_USDHC1_WP_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_11_INDEX)) -#define GPIO_USDHC1_WP_4 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_03_INDEX)) -#define GPIO_USDHC1_WP_5 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_36_INDEX)) - -#define GPIO_USDHC2_CD_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_06_INDEX)) -#define GPIO_USDHC2_CD_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_03_INDEX)) -#define GPIO_USDHC2_CD_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_12_INDEX)) -#define GPIO_USDHC2_CLK (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_03_INDEX)) -#define GPIO_USDHC2_CMD (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_02_INDEX)) -#define GPIO_USDHC2_DATA0 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_04_INDEX)) -#define GPIO_USDHC2_DATA1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_05_INDEX)) -#define GPIO_USDHC2_DATA2 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_00_INDEX)) -#define GPIO_USDHC2_DATA3 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_01_INDEX)) -#define GPIO_USDHC2_DATA4 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_08_INDEX)) -#define GPIO_USDHC2_DATA5 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_09_INDEX)) -#define GPIO_USDHC2_DATA6 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_10_INDEX)) -#define GPIO_USDHC2_DATA7 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_11_INDEX)) -#define GPIO_USDHC2_RESET (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_07_INDEX)) -#define GPIO_USDHC2_WP_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_35_INDEX)) -#define GPIO_USDHC2_WP_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_13_INDEX)) - -/* Watchdog Timer (WDOG1-2) */ - -#define GPIO_WDOG1_ANY (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_14_INDEX)) -#define GPIO_WDOG1_WDOG_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_03_INDEX)) -#define GPIO_WDOG1_WDOG_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_15_INDEX)) -#define GPIO_WDOG1_WDOG_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_39_INDEX)) -#define GPIO_WDOG1_WDOG_4 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_06_INDEX)) -#define GPIO_WDOG1_WDOG_RST_DEB (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_30_INDEX)) - -#define GPIO_WDOG2_WDOG (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_31_INDEX)) -#define GPIO_WDOG2_RESET_DEB (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_29_INDEX)) - -/* Inter-Peripheral Crossbar Switch (XBAR) */ - -#define GPIO_XBAR1_INOUT04 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_04_INDEX)) -#define GPIO_XBAR1_INOUT05 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_05_INDEX)) -#define GPIO_XBAR1_INOUT06 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_06_INDEX)) -#define GPIO_XBAR1_INOUT07 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_07_INDEX)) -#define GPIO_XBAR1_INOUT08 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_08_INDEX)) -#define GPIO_XBAR1_INOUT09 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_09_INDEX)) -#define GPIO_XBAR1_INOUT10_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_10_INDEX)) -#define GPIO_XBAR1_INOUT10_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_00_INDEX)) -#define GPIO_XBAR1_INOUT11 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_11_INDEX)) -#define GPIO_XBAR1_INOUT12_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_12_INDEX)) -#define GPIO_XBAR1_INOUT12_2 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX)) -#define GPIO_XBAR1_INOUT13_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_13_INDEX)) -#define GPIO_XBAR1_INOUT13_2 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX)) -#define GPIO_XBAR1_INOUT14_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_14_INDEX)) -#define GPIO_XBAR1_INOUT14_2 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_00_INDEX)) -#define GPIO_XBAR1_INOUT15_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_15_INDEX)) -#define GPIO_XBAR1_INOUT15_2 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_01_INDEX)) -#define GPIO_XBAR1_INOUT16_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_18_INDEX)) -#define GPIO_XBAR1_INOUT16_2 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_02_INDEX)) -#define GPIO_XBAR1_INOUT17_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_19_INDEX)) -#define GPIO_XBAR1_INOUT17_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_06_INDEX)) -#define GPIO_XBAR1_INOUT18_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_40_INDEX)) -#define GPIO_XBAR1_INOUT18_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_28_INDEX)) -#define GPIO_XBAR1_INOUT19_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_41_INDEX)) -#define GPIO_XBAR1_INOUT19_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_29_INDEX)) - -/* XTAL Osc */ - -#define GPIO_REF_24M_OUT_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_01_INDEX)) -#define GPIO_REF_24M_OUT_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_07_INDEX)) -#define GPIO_REF_24M_OUT_3 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_06_INDEX)) -#define GPIO_REF_32K_OUT_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_06_INDEX)) -#define GPIO_REF_32K_OUT_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_06_INDEX)) - -#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_PINMUX_H */ diff --git a/arch/arm/src/imxrt/chip/rt102x/imxrt102x_xbar.h b/arch/arm/src/imxrt/chip/rt102x/imxrt102x_xbar.h deleted file mode 100644 index f8d6aefd1f1..00000000000 --- a/arch/arm/src/imxrt/chip/rt102x/imxrt102x_xbar.h +++ /dev/null @@ -1,324 +0,0 @@ -/* XBAR Defines for IMXRT102x */ - -/* XBARA1 Mux inputs (I values) ***************************************************************************************************************************************/ - -#define IMXRT_XBARA1_IN_LOGIC_LOW IMXRT_XBARA1(XBAR_INPUT, 0) /* LOGIC_LOW output assigned to XBARA1_IN0 input. */ -#define IMXRT_XBARA1_IN_LOGIC_HIGH IMXRT_XBARA1(XBAR_INPUT, 1) /* LOGIC_HIGH output assigned to XBARA1_IN1 input. */ -/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 2) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 3) RESERVED */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO04 IMXRT_XBARA1(XBAR_INPUT, 4) /* IOMUX_XBAR_INOUT04 output assigned to XBARA1_IN4 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO05 IMXRT_XBARA1(XBAR_INPUT, 5) /* IOMUX_XBAR_INOUT05 output assigned to XBARA1_IN5 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO06 IMXRT_XBARA1(XBAR_INPUT, 6) /* IOMUX_XBAR_INOUT06 output assigned to XBARA1_IN6 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO07 IMXRT_XBARA1(XBAR_INPUT, 7) /* IOMUX_XBAR_INOUT07 output assigned to XBARA1_IN7 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO08 IMXRT_XBARA1(XBAR_INPUT, 8) /* IOMUX_XBAR_INOUT08 output assigned to XBARA1_IN8 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO09 IMXRT_XBARA1(XBAR_INPUT, 9) /* IOMUX_XBAR_INOUT09 output assigned to XBARA1_IN9 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO10 IMXRT_XBARA1(XBAR_INPUT, 10) /* IOMUX_XBAR_INOUT10 output assigned to XBARA1_IN10 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO11 IMXRT_XBARA1(XBAR_INPUT, 11) /* IOMUX_XBAR_INOUT11 output assigned to XBARA1_IN11 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO12 IMXRT_XBARA1(XBAR_INPUT, 12) /* IOMUX_XBAR_INOUT12 output assigned to XBARA1_IN12 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO13 IMXRT_XBARA1(XBAR_INPUT, 13) /* IOMUX_XBAR_INOUT13 output assigned to XBARA1_IN13 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO14 IMXRT_XBARA1(XBAR_INPUT, 14) /* IOMUX_XBAR_INOUT14 output assigned to XBARA1_IN14 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO15 IMXRT_XBARA1(XBAR_INPUT, 15) /* IOMUX_XBAR_INOUT15 output assigned to XBARA1_IN15 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO16 IMXRT_XBARA1(XBAR_INPUT, 16) /* IOMUX_XBAR_INOUT16 output assigned to XBARA1_IN16 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO17 IMXRT_XBARA1(XBAR_INPUT, 17) /* IOMUX_XBAR_INOUT17 output assigned to XBARA1_IN17 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO18 IMXRT_XBARA1(XBAR_INPUT, 18) /* IOMUX_XBAR_INOUT18 output assigned to XBARA1_IN18 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO19 IMXRT_XBARA1(XBAR_INPUT, 19) /* IOMUX_XBAR_INOUT19 output assigned to XBARA1_IN19 input. */ -/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 20) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 21) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 22) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 23) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 24) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 25) RESERVED */ -#define IMXRT_XBARA1_IN_ACMP1_OUT IMXRT_XBARA1(XBAR_INPUT, 26) /* ACMP1_OUT output assigned to XBARA1_IN26 input. */ -#define IMXRT_XBARA1_IN_ACMP2_OUT IMXRT_XBARA1(XBAR_INPUT, 27) /* ACMP2_OUT output assigned to XBARA1_IN27 input. */ -#define IMXRT_XBARA1_IN_ACMP3_OUT IMXRT_XBARA1(XBAR_INPUT, 28) /* ACMP3_OUT output assigned to XBARA1_IN28 input. */ -#define IMXRT_XBARA1_IN_ACMP4_OUT IMXRT_XBARA1(XBAR_INPUT, 29) /* ACMP4_OUT output assigned to XBARA1_IN29 input. */ -/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 30) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 31) RESERVED */ -#define IMXRT_XBARA1_IN_QTIMER1_TMR0_OUT IMXRT_XBARA1(XBAR_INPUT, 32) /* QTIMER3_TMR0_OUTPUT output assigned to XBARA1_IN32 input. */ -#define IMXRT_XBARA1_IN_QTIMER1_TMR1_OUT IMXRT_XBARA1(XBAR_INPUT, 33) /* QTIMER3_TMR1_OUTPUT output assigned to XBARA1_IN33 input. */ -#define IMXRT_XBARA1_IN_QTIMER1_TMR2_OUT IMXRT_XBARA1(XBAR_INPUT, 34) /* QTIMER3_TMR2_OUTPUT output assigned to XBARA1_IN34 input. */ -#define IMXRT_XBARA1_IN_QTIMER1_TMR3_OUT IMXRT_XBARA1(XBAR_INPUT, 35) /* QTIMER3_TMR3_OUTPUT output assigned to XBARA1_IN35 input. */ -#define IMXRT_XBARA1_IN_QTIMER2_TMR0_OUT IMXRT_XBARA1(XBAR_INPUT, 36) /* QTIMER4_TMR0_OUTPUT output assigned to XBARA1_IN36 input. */ -#define IMXRT_XBARA1_IN_QTIMER2_TMR1_OUT IMXRT_XBARA1(XBAR_INPUT, 37) /* QTIMER4_TMR1_OUTPUT output assigned to XBARA1_IN37 input. */ -#define IMXRT_XBARA1_IN_QTIMER2_TMR2_OUT IMXRT_XBARA1(XBAR_INPUT, 38) /* QTIMER4_TMR2_OUTPUT output assigned to XBARA1_IN38 input. */ -#define IMXRT_XBARA1_IN_QTIMER2_TMR3_OUT IMXRT_XBARA1(XBAR_INPUT, 39) /* QTIMER4_TMR3_OUTPUT output assigned to XBARA1_IN39 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM1_PWM1_OUT_TRIG0 IMXRT_XBARA1(XBAR_INPUT, 40) /* FLEXPWM1_PWM1_OUT_TRIG0 output OR assigned to XBARA1_IN40 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM1_PWM1_OUT_TRIG1 IMXRT_XBARA1(XBAR_INPUT, 40) /* FLEXPWM1_PWM1_OUT_TRIG1 output OR assigned to XBARA1_IN40 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM1_PWM2_OUT_TRIG0 IMXRT_XBARA1(XBAR_INPUT, 41) /* FLEXPWM1_PWM2_OUT_TRIG0 output OR assigned to XBARA1_IN41 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM1_PWM2_OUT_TRIG1 IMXRT_XBARA1(XBAR_INPUT, 41) /* FLEXPWM1_PWM2_OUT_TRIG1 output OR assigned to XBARA1_IN41 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM1_PWM3_OUT_TRIG0 IMXRT_XBARA1(XBAR_INPUT, 42) /* FLEXPWM1_PWM3_OUT_TRIG0 output OR assigned to XBARA1_IN42 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM1_PWM3_OUT_TRIG1 IMXRT_XBARA1(XBAR_INPUT, 42) /* FLEXPWM1_PWM3_OUT_TRIG1 output OR assigned to XBARA1_IN42 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM1_PWM4_OUT_TRIG0 IMXRT_XBARA1(XBAR_INPUT, 43) /* FLEXPWM1_PWM4_OUT_TRIG0 output OR assigned to XBARA1_IN43 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM1_PWM4_OUT_TRIG1 IMXRT_XBARA1(XBAR_INPUT, 43) /* FLEXPWM1_PWM4_OUT_TRIG1 output OR assigned to XBARA1_IN43 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM2_PWM1_OUT_TRIG0 IMXRT_XBARA1(XBAR_INPUT, 44) /* FLEXPWM2_PWM1_OUT_TRIG0 output OR assigned to XBARA1_IN44 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM2_PWM1_OUT_TRIG1 IMXRT_XBARA1(XBAR_INPUT, 44) /* FLEXPWM2_PWM1_OUT_TRIG1 output OR assigned to XBARA1_IN44 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM2_PWM2_OUT_TRIG0 IMXRT_XBARA1(XBAR_INPUT, 45) /* FLEXPWM2_PWM2_OUT_TRIG0 output OR assigned to XBARA1_IN45 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM2_PWM2_OUT_TRIG1 IMXRT_XBARA1(XBAR_INPUT, 45) /* FLEXPWM2_PWM2_OUT_TRIG1 output OR assigned to XBARA1_IN45 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM2_PWM3_OUT_TRIG0 IMXRT_XBARA1(XBAR_INPUT, 46) /* FLEXPWM2_PWM3_OUT_TRIG0 output OR assigned to XBARA1_IN46 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM2_PWM3_OUT_TRIG1 IMXRT_XBARA1(XBAR_INPUT, 46) /* FLEXPWM2_PWM3_OUT_TRIG1 output OR assigned to XBARA1_IN46 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM2_PWM4_OUT_TRIG0 IMXRT_XBARA1(XBAR_INPUT, 47) /* FLEXPWM2_PWM4_OUT_TRIG0 output OR assigned to XBARA1_IN47 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM2_PWM4_OUT_TRIG1 IMXRT_XBARA1(XBAR_INPUT, 47) /* FLEXPWM2_PWM4_OUT_TRIG1 output OR assigned to XBARA1_IN47 input. */ -/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 48) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 49) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 50) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 51) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 52) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 53) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 54) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 55) RESERVED */ -#define IMXRT_XBARA1_IN_PIT_TRIGGER0 IMXRT_XBARA1(XBAR_INPUT, 56) /* PIT_TRIGGER0 output assigned to XBARA1_IN56 input. */ -#define IMXRT_XBARA1_IN_PIT_TRIGGER1 IMXRT_XBARA1(XBAR_INPUT, 57) /* PIT_TRIGGER1 output assigned to XBARA1_IN57 input. */ -#define IMXRT_XBARA1_IN_PIT_TRIGGER2 IMXRT_XBARA1(XBAR_INPUT, 58) /* PIT_TRIGGER2 output assigned to XBARA1_IN58 input. */ -#define IMXRT_XBARA1_IN_PIT_TRIGGER3 IMXRT_XBARA1(XBAR_INPUT, 59) /* PIT_TRIGGER3 output assigned to XBARA1_IN59 input. */ -#define IMXRT_XBARA1_IN_ENC1_POS_MATCH IMXRT_XBARA1(XBAR_INPUT, 60) /* ENC1_POS_MATCH output assigned to XBARA1_IN60 input. */ -#define IMXRT_XBARA1_IN_ENC2_POS_MATCH IMXRT_XBARA1(XBAR_INPUT, 61) /* ENC2_POS_MATCH output assigned to XBARA1_IN61 input. */ -/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 62) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 63) RESERVED */ -#define IMXRT_XBARA1_IN_DMA_DONE0 IMXRT_XBARA1(XBAR_INPUT, 64) /* DMA_DONE0 output assigned to XBARA1_IN64 input. */ -#define IMXRT_XBARA1_IN_DMA_DONE1 IMXRT_XBARA1(XBAR_INPUT, 65) /* DMA_DONE1 output assigned to XBARA1_IN65 input. */ -#define IMXRT_XBARA1_IN_DMA_DONE2 IMXRT_XBARA1(XBAR_INPUT, 66) /* DMA_DONE2 output assigned to XBARA1_IN66 input. */ -#define IMXRT_XBARA1_IN_DMA_DONE3 IMXRT_XBARA1(XBAR_INPUT, 67) /* DMA_DONE3 output assigned to XBARA1_IN67 input. */ -#define IMXRT_XBARA1_IN_DMA_DONE4 IMXRT_XBARA1(XBAR_INPUT, 68) /* DMA_DONE4 output assigned to XBARA1_IN68 input. */ -#define IMXRT_XBARA1_IN_DMA_DONE5 IMXRT_XBARA1(XBAR_INPUT, 69) /* DMA_DONE5 output assigned to XBARA1_IN69 input. */ -#define IMXRT_XBARA1_IN_DMA_DONE6 IMXRT_XBARA1(XBAR_INPUT, 70) /* DMA_DONE6 output assigned to XBARA1_IN70 input. */ -#define IMXRT_XBARA1_IN_DMA_DONE7 IMXRT_XBARA1(XBAR_INPUT, 71) /* DMA_DONE7 output assigned to XBARA1_IN71 input. */ -#define IMXRT_XBARA1_IN_AOI1_OUT0 IMXRT_XBARA1(XBAR_INPUT, 72) /* AOI1_OUT0 output assigned to XBARA1_IN72 input. */ -#define IMXRT_XBARA1_IN_AOI1_OUT1 IMXRT_XBARA1(XBAR_INPUT, 73) /* AOI1_OUT1 output assigned to XBARA1_IN73 input. */ -#define IMXRT_XBARA1_IN_AOI1_OUT2 IMXRT_XBARA1(XBAR_INPUT, 74) /* AOI1_OUT2 output assigned to XBARA1_IN74 input. */ -#define IMXRT_XBARA1_IN_AOI1_OUT3 IMXRT_XBARA1(XBAR_INPUT, 75) /* AOI1_OUT3 output assigned to XBARA1_IN75 input. */ -/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 76) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 77) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 78) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 79) RESERVED */ -#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO0 IMXRT_XBARA1(XBAR_INPUT, 80) /* ADC_ETC_XBAR0_COCO0 output assigned to XBARA1_IN80 input. */ -#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO1 IMXRT_XBARA1(XBAR_INPUT, 81) /* ADC_ETC_XBAR0_COCO1 output assigned to XBARA1_IN81 input. */ -#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO2 IMXRT_XBARA1(XBAR_INPUT, 82) /* ADC_ETC_XBAR0_COCO2 output assigned to XBARA1_IN82 input. */ -#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO3 IMXRT_XBARA1(XBAR_INPUT, 83) /* ADC_ETC_XBAR0_COCO3 output assigned to XBARA1_IN83 input. */ -#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO0 IMXRT_XBARA1(XBAR_INPUT, 84) /* ADC_ETC_XBAR1_COCO0 output assigned to XBARA1_IN84 input. */ -#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO1 IMXRT_XBARA1(XBAR_INPUT, 85) /* ADC_ETC_XBAR1_COCO1 output assigned to XBARA1_IN85 input. */ -#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO2 IMXRT_XBARA1(XBAR_INPUT, 86) /* ADC_ETC_XBAR1_COCO2 output assigned to XBARA1_IN86 input. */ -#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO3 IMXRT_XBARA1(XBAR_INPUT, 87) /* ADC_ETC_XBAR1_COCO3 output assigned to XBARA1_IN87 input. */ - -/* XBARA1 Mux Output (M Muxes) ***************************************************************************************************************/ - -#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ30_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 0) /* XBARA1_OUT0 output assigned to DMA_CH_MUX_REQ30 */ -#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ31_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 1) /* XBARA1_OUT1 output assigned to DMA_CH_MUX_REQ31 */ -#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ94_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 2) /* XBARA1_OUT2 output assigned to DMA_CH_MUX_REQ94 */ -#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ95_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 3) /* XBARA1_OUT3 output assigned to DMA_CH_MUX_REQ95 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO04_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 4) /* XBARA1_OUT4 output assigned to IOMUX_XBAR_INOUT04 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO05_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 5) /* XBARA1_OUT5 output assigned to IOMUX_XBAR_INOUT05 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO06_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 6) /* XBARA1_OUT6 output assigned to IOMUX_XBAR_INOUT06 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO07_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 7) /* XBARA1_OUT7 output assigned to IOMUX_XBAR_INOUT07 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO08_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 8) /* XBARA1_OUT8 output assigned to IOMUX_XBAR_INOUT08 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO09_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 9) /* XBARA1_OUT9 output assigned to IOMUX_XBAR_INOUT09 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO10_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 10) /* XBARA1_OUT10 output assigned to IOMUX_XBAR_INOUT10 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO11_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 11) /* XBARA1_OUT11 output assigned to IOMUX_XBAR_INOUT11 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO12_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 12) /* XBARA1_OUT12 output assigned to IOMUX_XBAR_INOUT12 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO13_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 13) /* XBARA1_OUT13 output assigned to IOMUX_XBAR_INOUT13 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO14_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 14) /* XBARA1_OUT14 output assigned to IOMUX_XBAR_INOUT14 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO15_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 15) /* XBARA1_OUT15 output assigned to IOMUX_XBAR_INOUT15 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO16_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 16) /* XBARA1_OUT16 output assigned to IOMUX_XBAR_INOUT16 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO17_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 17) /* XBARA1_OUT17 output assigned to IOMUX_XBAR_INOUT17 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO18_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 18) /* XBARA1_OUT18 output assigned to IOMUX_XBAR_INOUT18 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO19_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 19) /* XBARA1_OUT19 output assigned to IOMUX_XBAR_INOUT19 */ -#define IMXRT_XBARA1_OUT_ACMP1_SAMPLE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 20) /* XBARA1_OUT20 output assigned to ACMP1_SAMPLE */ -#define IMXRT_XBARA1_OUT_ACMP2_SAMPLE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 21) /* XBARA1_OUT21 output assigned to ACMP2_SAMPLE */ -#define IMXRT_XBARA1_OUT_ACMP3_SAMPLE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 22) /* XBARA1_OUT22 output assigned to ACMP3_SAMPLE */ -#define IMXRT_XBARA1_OUT_ACMP4_SAMPLE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 23) /* XBARA1_OUT23 output assigned to ACMP4_SAMPLE */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 24) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 25) RESERVED */ -#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 26) /* XBARA1_OUT26 output assigned to FLEXPWM1_EXTA0 */ -#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 27) /* XBARA1_OUT27 output assigned to FLEXPWM1_EXTA1 */ -#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 28) /* XBARA1_OUT28 output assigned to FLEXPWM1_EXTA2 */ -#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 29) /* XBARA1_OUT29 output assigned to FLEXPWM1_EXTA3 */ -#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 30) /* XBARA1_OUT30 output assigned to FLEXPWM1_EXT_SYNC0 */ -#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 31) /* XBARA1_OUT31 output assigned to FLEXPWM1_EXT_SYNC1 */ -#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 32) /* XBARA1_OUT32 output assigned to FLEXPWM1_EXT_SYNC2 */ -#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 33) /* XBARA1_OUT33 output assigned to FLEXPWM1_EXT_SYNC3 */ -#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_CLK_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 34) /* XBARA1_OUT34 output assigned to FLEXPWM1_EXT_CLK */ -#define IMXRT_XBARA1_OUT_FLEXPWM1_FAULT0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 35) /* XBARA1_OUT35 output assigned to FLEXPWM1_FAULT0 */ -#define IMXRT_XBARA1_OUT_FLEXPWM1_FAULT1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 36) /* XBARA1_OUT36 output assigned to FLEXPWM1_FAULT1 */ -#define IMXRT_XBARA1_OUT_FLEXPWM12_FAULT2_SEL_OFFSET IMXXRT_XBARA1(XBAR_OUTPUT,37) /* XBARA1_OUT37 output assigned to FLEXPWM1_2_FAULT2 */ -#define IMXRT_XBARA1_OUT_FLEXPWM12_FAULT3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 38) /* XBARA1_OUT38 output assigned to FLEXPWM1_2_FAULT3 */ -#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_FORCE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 39) /* XBARA1_OUT39 output assigned to FLEXPWM1_EXT_FORCE */ -#define IMXRT_XBARA1_OUT_FLEXPWM2_EXTA0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 40) /* XBARA1_OUT40 output assigned to FLEXPWM2_EXTA0 */ -#define IMXRT_XBARA1_OUT_FLEXPWM2_EXTA1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 41) /* XBARA1_OUT41 output assigned to FLEXPWM2_EXTA1 */ -#define IMXRT_XBARA1_OUT_FLEXPWM2_EXTA2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 42) /* XBARA1_OUT42 output assigned to FLEXPWM2_EXTA2 */ -#define IMXRT_XBARA1_OUT_FLEXPWM2_EXTA3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 43) /* XBARA1_OUT43 output assigned to FLEXPWM2_EXTA3 */ - -#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 44) /* XBARA1_OUT44 output assigned to FLEXPWM2_EXT_SYNC0 */ -#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 45) /* XBARA1_OUT45 output assigned to FLEXPWM2_EXT_SYNC1 */ -#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 46) /* XBARA1_OUT46 output assigned to FLEXPWM2_EXT_SYNC2 */ -#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 47) /* XBARA1_OUT47 output assigned to FLEXPWM2_EXT_SYNC3 */ -#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_CLK_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 48) /* XBARA1_OUT48 output assigned to FLEXPWM2_EXT_CLK */ -#define IMXRT_XBARA1_OUT_FLEXPWM2_FAULT0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 49) /* XBARA1_OUT49 output assigned to FLEXPWM2_FAULT0 */ -#define IMXRT_XBARA1_OUT_FLEXPWM2_FAULT1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 50) /* XBARA1_OUT50 output assigned to FLEXPWM2_FAULT1 */ -#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_FORCE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 51) /* XBARA1_OUT51 output assigned to FLEXPWM2_EXT_FORCE */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 52) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 53) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 54) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 55) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 56) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 57) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 58) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 59) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 60) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 61) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 62) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 63) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 64) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 65) RESERVED */ -#define IMXRT_XBARA1_OUT_ENC1_PHASE_AIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 66) /* XBARA1_OUT66 output assigned to ENC1_PHASE_A_IN */ -#define IMXRT_XBARA1_OUT_ENC1_PHASE_BIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 67) /* XBARA1_OUT67 output assigned to ENC1_PHASE_B_IN */ -#define IMXRT_XBARA1_OUT_ENC1_INDEX_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 68) /* XBARA1_OUT68 output assigned to ENC1_INDEX */ -#define IMXRT_XBARA1_OUT_ENC1_HOME_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 69) /* XBARA1_OUT69 output assigned to ENC1_HOME */ -#define IMXRT_XBARA1_OUT_ENC1_TRIGGER_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 70) /* XBARA1_OUT70 output assigned to ENC1_TRIGGER */ -#define IMXRT_XBARA1_OUT_ENC2_PHASE_AIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 71) /* XBARA1_OUT71 output assigned to ENC2_PHASE_A_IN */ -#define IMXRT_XBARA1_OUT_ENC2_PHASE_BIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 72) /* XBARA1_OUT72 output assigned to ENC2_PHASE_B_IN */ -#define IMXRT_XBARA1_OUT_ENC2_INDEX_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 73) /* XBARA1_OUT73 output assigned to ENC2_INDEX */ -#define IMXRT_XBARA1_OUT_ENC2_HOME_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 74) /* XBARA1_OUT74 output assigned to ENC2_HOME */ -#define IMXRT_XBARA1_OUT_ENC2_TRIGGER_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 75) /* XBARA1_OUT75 output assigned to ENC2_TRIGGER */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 76) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 77) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 78) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 79) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 80) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 81) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 82) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 83) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 84) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 85) RESERVED */ -#define IMXRT_XBARA1_OUT_QTIMER1_TMR0_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 86) /* XBARA1_OUT86 output assigned to QTIMER1_TMR0_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER1_TMR1_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 87) /* XBARA1_OUT87 output assigned to QTIMER1_TMR1_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER1_TMR2_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 88) /* XBARA1_OUT88 output assigned to QTIMER1_TMR2_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER1_TMR3_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 89) /* XBARA1_OUT89 output assigned to QTIMER1_TMR3_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER2_TMR0_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 90) /* XBARA1_OUT90 output assigned to QTIMER2_TMR0_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER2_TMR1_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 91) /* XBARA1_OUT91 output assigned to QTIMER2_TMR1_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER2_TMR2_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 92) /* XBARA1_OUT92 output assigned to QTIMER2_TMR2_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER2_TMR3_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 93) /* XBARA1_OUT93 output assigned to QTIMER2_TMR3_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER3_TMR0_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 94) /* XBARA1_OUT94 output assigned to QTIMER3_TMR0_IN_ */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 95) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 96) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 97) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 98) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 99) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 100) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 101) RESERVED */ -#define IMXRT_XBARA1_OUT_EWM_EWM_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 102) /* XBARA1_OUT102 output assigned to EWM_EWM_IN */ -#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 103) /* XBARA1_OUT103 output assigned to ADC_ETC_XBAR0_TRIG0 */ -#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 104) /* XBARA1_OUT104 output assigned to ADC_ETC_XBAR0_TRIG1 */ -#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 105) /* XBARA1_OUT105 output assigned to ADC_ETC_XBAR0_TRIG2 */ -#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 106) /* XBARA1_OUT106 output assigned to ADC_ETC_XBAR0_TRIG3 */ -#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG10_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 107) /* XBARA1_OUT107 output assigned to ADC_ETC_XBAR1_TRIG10 */ -#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG11_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 108) /* XBARA1_OUT108 output assigned to ADC_ETC_XBAR1_TRIG11 */ -#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG12_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 109) /* XBARA1_OUT109 output assigned to ADC_ETC_XBAR1_TRIG12 */ -#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG13_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 110) /* XBARA1_OUT110 output assigned to ADC_ETC_XBAR1_TRIG13 */ -#define IMXRT_XBARA1_OUT_LPI2C1_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 111) /* XBARA1_OUT111 output assigned to LPI2C1_TRG_IN */ -#define IMXRT_XBARA1_OUT_LPI2C2_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 112) /* XBARA1_OUT112 output assigned to LPI2C2_TRG_IN */ -#define IMXRT_XBARA1_OUT_LPI2C3_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 113) /* XBARA1_OUT113 output assigned to LPI2C3_TRG_IN */ -#define IMXRT_XBARA1_OUT_LPI2C4_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 114) /* XBARA1_OUT114 output assigned to LPI2C4_TRG_IN */ -#define IMXRT_XBARA1_OUT_LPSPI1_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 115) /* XBARA1_OUT115 output assigned to LPSPI1_TRG_IN */ -#define IMXRT_XBARA1_OUT_LPSPI2_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 116) /* XBARA1_OUT116 output assigned to LPSPI2_TRG_IN */ -#define IMXRT_XBARA1_OUT_LPSPI3_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 117) /* XBARA1_OUT117 output assigned to LPSPI3_TRG_IN */ -#define IMXRT_XBARA1_OUT_LPSPI4_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 118) /* XBARA1_OUT118 output assigned to LPSPI4_TRG_IN */ -#define IMXRT_XBARA1_OUT_LPUART1_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 119) /* XBARA1_OUT119 output assigned to LPUART1_TRG_IN */ -#define IMXRT_XBARA1_OUT_LPUART2_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 120) /* XBARA1_OUT120 output assigned to LPUART2_TRG_IN */ -#define IMXRT_XBARA1_OUT_LPUART3_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 121) /* XBARA1_OUT121 output assigned to LPUART3_TRG_IN */ -#define IMXRT_XBARA1_OUT_LPUART4_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 122) /* XBARA1_OUT122 output assigned to LPUART4_TRG_IN */ -#define IMXRT_XBARA1_OUT_LPUART5_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 123) /* XBARA1_OUT123 output assigned to LPUART5_TRG_IN */ -#define IMXRT_XBARA1_OUT_LPUART6_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 124) /* XBARA1_OUT124 output assigned to LPUART6_TRG_IN */ -#define IMXRT_XBARA1_OUT_LPUART7_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 125) /* XBARA1_OUT125 output assigned to LPUART7_TRG_IN */ -#define IMXRT_XBARA1_OUT_LPUART8_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 126) /* XBARA1_OUT126 output assigned to LPUART8_TRG_IN */ -#define IMXRT_XBARA1_OUT_FLEXIO1_TRIGGER_IN0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 127) /* XBARA1_OUT127 output assigned to FLEXIO1_TRIGGER_IN0 */ -#define IMXRT_XBARA1_OUT_FLEXIO1_TRIGGER_IN1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 128) /* XBARA1_OUT128 output assigned to FLEXIO1_TRIGGER_IN1 */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 129) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 130) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 131) RESERVED */ - -/* XBARB2 Mux inputs (I values) *******************************************************************************************************************/ - -#define IMXRT_XBARB2_IN_LOGIC_LOW IMXRT_XBARB2(XBAR_INPUT, 0) /* LOGIC_LOW output assigned to XBARB2_IN0 input. */ -#define IMXRT_XBARB2_IN_LOGIC_HIGH IMXRT_XBARB2(XBAR_INPUT, 1) /* LOGIC_HIGH output assigned to XBARB2_IN1 input. */ -/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 2) RESERVED */ -/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 3) RESERVED */ -/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 4) RESERVED */ -/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 5) RESERVED */ -#define IMXRT_XBARB2_IN_ACMP1_OUT IMXRT_XBARB2(XBAR_INPUT, 6) /* ACMP1_OUT output assigned to XBARB2_IN6 input. */ -#define IMXRT_XBARB2_IN_ACMP2_OUT IMXRT_XBARB2(XBAR_INPUT, 7) /* ACMP2_OUT output assigned to XBARB2_IN7 input. */ -#define IMXRT_XBARB2_IN_ACMP3_OUT IMXRT_XBARB2(XBAR_INPUT, 8) /* ACMP3_OUT output assigned to XBARB2_IN8 input. */ -#define IMXRT_XBARB2_IN_ACMP4_OUT IMXRT_XBARB2(XBAR_INPUT, 9) /* ACMP4_OUT output assigned to XBARB2_IN9 input. */ -/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 10) RESERVED */ -/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 11) RESERVED */ -#define IMXRT_XBARB2_IN_QTIMER1_TMR0_OUT IMXRT_XBARB2(XBAR_INPUT, 12) /* QTIMER3_TMR0_OUTPUT output assigned to XBARB2_IN12 input. */ -#define IMXRT_XBARB2_IN_QTIMER1_TMR1_OUT IMXRT_XBARB2(XBAR_INPUT, 13) /* QTIMER3_TMR1_OUTPUT output assigned to XBARB2_IN13 input. */ -#define IMXRT_XBARB2_IN_QTIMER1_TMR2_OUT IMXRT_XBARB2(XBAR_INPUT, 14) /* QTIMER3_TMR2_OUTPUT output assigned to XBARB2_IN14 input. */ -#define IMXRT_XBARB2_IN_QTIMER1_TMR3_OUT IMXRT_XBARB2(XBAR_INPUT, 15) /* QTIMER3_TMR3_OUTPUT output assigned to XBARB2_IN15 input. */ -#define IMXRT_XBARB2_IN_QTIMER2_TMR0_OUT IMXRT_XBARB2(XBAR_INPUT, 16) /* QTIMER4_TMR0_OUTPUT output assigned to XBARB2_IN16 input. */ -#define IMXRT_XBARB2_IN_QTIMER2_TMR1_OUT IMXRT_XBARB2(XBAR_INPUT, 17) /* QTIMER4_TMR1_OUTPUT output assigned to XBARB2_IN17 input. */ -#define IMXRT_XBARB2_IN_QTIMER2_TMR2_OUT IMXRT_XBARB2(XBAR_INPUT, 18) /* QTIMER4_TMR2_OUTPUT output assigned to XBARB2_IN18 input. */ -#define IMXRT_XBARB2_IN_QTIMER2_TMR3_OUT IMXRT_XBARB2(XBAR_INPUT, 19) /* QTIMER4_TMR3_OUTPUT output assigned to XBARB2_IN19 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM1_PWM1_OUT_TRIG0 IMXRT_XBARB2(XBAR_INPUT, 20) /* FLEXPWM1_PWM1_OUT_TRIG0 output OR assigned to XBARB2_IN20 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM1_PWM1_OUT_TRIG1 IMXRT_XBARB2(XBAR_INPUT, 20) /* FLEXPWM1_PWM1_OUT_TRIG1 output OR assigned to XBARB2_IN20 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM1_PWM2_OUT_TRIG0 IMXRT_XBARB2(XBAR_INPUT, 21) /* FLEXPWM1_PWM2_OUT_TRIG0 output OR assigned to XBARB2_IN21 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM1_PWM2_OUT_TRIG1 IMXRT_XBARB2(XBAR_INPUT, 21) /* FLEXPWM1_PWM2_OUT_TRIG1 output OR assigned to XBARB2_IN21 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM1_PWM3_OUT_TRIG0 IMXRT_XBARB2(XBAR_INPUT, 22) /* FLEXPWM1_PWM3_OUT_TRIG0 output OR assigned to XBARB2_IN22 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM1_PWM3_OUT_TRIG1 IMXRT_XBARB2(XBAR_INPUT, 22) /* FLEXPWM1_PWM3_OUT_TRIG1 output OR assigned to XBARB2_IN22 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM1_PWM4_OUT_TRIG0 IMXRT_XBARB2(XBAR_INPUT, 23) /* FLEXPWM1_PWM4_OUT_TRIG0 output OR assigned to XBARB2_IN23 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM1_PWM4_OUT_TRIG1 IMXRT_XBARB2(XBAR_INPUT, 23) /* FLEXPWM1_PWM4_OUT_TRIG1 output OR assigned to XBARB2_IN23 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM2_PWM1_OUT_TRIG0 IMXRT_XBARB2(XBAR_INPUT, 24) /* FLEXPWM2_PWM1_OUT_TRIG0 output OR assigned to XBARB2_IN24 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM2_PWM1_OUT_TRIG1 IMXRT_XBARB2(XBAR_INPUT, 24) /* FLEXPWM2_PWM1_OUT_TRIG1 output OR assigned to XBARB2_IN24 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM2_PWM2_OUT_TRIG0 IMXRT_XBARB2(XBAR_INPUT, 25) /* FLEXPWM2_PWM2_OUT_TRIG0 output OR assigned to XBARB2_IN25 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM2_PWM2_OUT_TRIG1 IMXRT_XBARB2(XBAR_INPUT, 25) /* FLEXPWM2_PWM2_OUT_TRIG1 output OR assigned to XBARB2_IN25 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM2_PWM3_OUT_TRIG0 IMXRT_XBARB2(XBAR_INPUT, 26) /* FLEXPWM2_PWM3_OUT_TRIG0 output OR assigned to XBARB2_IN26 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM2_PWM3_OUT_TRIG1 IMXRT_XBARB2(XBAR_INPUT, 26) /* FLEXPWM2_PWM3_OUT_TRIG1 output OR assigned to XBARB2_IN26 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM2_PWM4_OUT_TRIG0 IMXRT_XBARB2(XBAR_INPUT, 27) /* FLEXPWM2_PWM4_OUT_TRIG0 output OR assigned to XBARB2_IN27 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM2_PWM4_OUT_TRIG1 IMXRT_XBARB2(XBAR_INPUT, 27) /* FLEXPWM2_PWM4_OUT_TRIG1 output OR assigned to XBARB2_IN27 input. */ -/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 28) RESERVED */ -/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 29) RESERVED */ -/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 30) RESERVED */ -/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 31) RESERVED */ -/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 32) RESERVED */ -/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 33) RESERVED */ -/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 34) RESERVED */ -/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 35) RESERVED */ -#define IMXRT_XBARB2_IN_PIT_TRIGGER0 IMXRT_XBARB2(XBAR_INPUT, 36) /* PIT_TRIGGER0 output assigned to XBARB2_IN36 input. */ -#define IMXRT_XBARB2_IN_PIT_TRIGGER1 IMXRT_XBARB2(XBAR_INPUT, 37) /* PIT_TRIGGER1 output assigned to XBARB2_IN37 input. */ -#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO0 IMXRT_XBARB2(XBAR_INPUT, 38) /* ADC_ETC_XBAR0_COCO0 output assigned to XBARB2_IN38 input. */ -#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO1 IMXRT_XBARB2(XBAR_INPUT, 39) /* ADC_ETC_XBAR0_COCO1 output assigned to XBARB2_IN39 input. */ -#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO2 IMXRT_XBARB2(XBAR_INPUT, 40) /* ADC_ETC_XBAR0_COCO2 output assigned to XBARB2_IN40 input. */ -#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO3 IMXRT_XBARB2(XBAR_INPUT, 41) /* ADC_ETC_XBAR0_COCO3 output assigned to XBARB2_IN41 input. */ -#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO0 IMXRT_XBARB2(XBAR_INPUT, 42) /* ADC_ETC_XBAR1_COCO0 output assigned to XBARB2_IN42 input. */ -#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO1 IMXRT_XBARB2(XBAR_INPUT, 43) /* ADC_ETC_XBAR1_COCO1 output assigned to XBARB2_IN43 input. */ -#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO2 IMXRT_XBARB2(XBAR_INPUT, 44) /* ADC_ETC_XBAR1_COCO2 output assigned to XBARB2_IN44 input. */ -#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO3 IMXRT_XBARB2(XBAR_INPUT, 45) /* ADC_ETC_XBAR1_COCO3 output assigned to XBARB2_IN45 input. */ -#define IMXRT_XBARB2_IN_ENC1_POS_MATCH IMXRT_XBARB2(XBAR_INPUT, 46) /* ENC1_POS_MATCH output assigned to XBARB2_IN46 input. */ -#define IMXRT_XBARB2_IN_ENC2_POS_MATCH IMXRT_XBARB2(XBAR_INPUT, 47) /* ENC2_POS_MATCH output assigned to XBARB2_IN47 input. */ -/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 48) RESERVED */ -/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 49) RESERVED */ -#define IMXRT_XBARB2_IN_DMA_DONE0 IMXRT_XBARB2(XBAR_INPUT, 50) /* DMA_DONE0 output assigned to XBARB2_IN50 input. */ -#define IMXRT_XBARB2_IN_DMA_DONE1 IMXRT_XBARB2(XBAR_INPUT, 51) /* DMA_DONE1 output assigned to XBARB2_IN51 input. */ -#define IMXRT_XBARB2_IN_DMA_DONE2 IMXRT_XBARB2(XBAR_INPUT, 52) /* DMA_DONE2 output assigned to XBARB2_IN52 input. */ -#define IMXRT_XBARB2_IN_DMA_DONE3 IMXRT_XBARB2(XBAR_INPUT, 53) /* DMA_DONE3 output assigned to XBARB2_IN53 input. */ -#define IMXRT_XBARB2_IN_DMA_DONE4 IMXRT_XBARB2(XBAR_INPUT, 54) /* DMA_DONE4 output assigned to XBARB2_IN54 input. */ -#define IMXRT_XBARB2_IN_DMA_DONE5 IMXRT_XBARB2(XBAR_INPUT, 55) /* DMA_DONE5 output assigned to XBARB2_IN55 input. */ -#define IMXRT_XBARB2_IN_DMA_DONE6 IMXRT_XBARB2(XBAR_INPUT, 56) /* DMA_DONE6 output assigned to XBARB2_IN56 input. */ -#define IMXRT_XBARB2_IN_DMA_DONE7 IMXRT_XBARB2(XBAR_INPUT, 57) /* DMA_DONE7 output assigned to XBARB2_IN57 input. */ - -/* XBARB2 Mux Output (M Muxes) ********************************************************************************************************************/ - -#define IMXRT_XBARB2_OUT_AOI1_IN00_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 0) /* XBARB2_OUT0 output assigned to AOI1_IN00 */ -#define IMXRT_XBARB2_OUT_AOI1_IN01_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 1) /* XBARB2_OUT1 output assigned to AOI1_IN01 */ -#define IMXRT_XBARB2_OUT_AOI1_IN02_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 2) /* XBARB2_OUT2 output assigned to AOI1_IN02 */ -#define IMXRT_XBARB2_OUT_AOI1_IN03_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 3) /* XBARB2_OUT3 output assigned to AOI1_IN03 */ -#define IMXRT_XBARB2_OUT_AOI1_IN04_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 4) /* XBARB2_OUT4 output assigned to AOI1_IN04 */ -#define IMXRT_XBARB2_OUT_AOI1_IN05_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 5) /* XBARB2_OUT5 output assigned to AOI1_IN05 */ -#define IMXRT_XBARB2_OUT_AOI1_IN06_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 6) /* XBARB2_OUT6 output assigned to AOI1_IN06 */ -#define IMXRT_XBARB2_OUT_AOI1_IN07_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 7) /* XBARB2_OUT7 output assigned to AOI1_IN07 */ -#define IMXRT_XBARB2_OUT_AOI1_IN08_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 8) /* XBARB2_OUT8 output assigned to AOI1_IN08 */ -#define IMXRT_XBARB2_OUT_AOI1_IN09_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 9) /* XBARB2_OUT9 output assigned to AOI1_IN09 */ -#define IMXRT_XBARB2_OUT_AOI1_IN10_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 10) /* XBARB2_OUT10 output assigned to AOI1_IN10 */ -#define IMXRT_XBARB2_OUT_AOI1_IN11_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 11) /* XBARB2_OUT11 output assigned to AOI1_IN11 */ -#define IMXRT_XBARB2_OUT_AOI1_IN12_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 12) /* XBARB2_OUT12 output assigned to AOI1_IN12 */ -#define IMXRT_XBARB2_OUT_AOI1_IN13_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 13) /* XBARB2_OUT13 output assigned to AOI1_IN13 */ -#define IMXRT_XBARB2_OUT_AOI1_IN14_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 14) /* XBARB2_OUT14 output assigned to AOI1_IN14 */ -#define IMXRT_XBARB2_OUT_AOI1_IN15_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 15) /* XBARB2_OUT15 output assigned to AOI1_IN15 */ diff --git a/arch/arm/src/imxrt/chip/rt105x/imxrt105x_ccm.h b/arch/arm/src/imxrt/chip/rt105x/imxrt105x_ccm.h deleted file mode 100644 index 5b214127fb4..00000000000 --- a/arch/arm/src/imxrt/chip/rt105x/imxrt105x_ccm.h +++ /dev/null @@ -1,1145 +0,0 @@ -/************************************************************************************************************ - * arch/arm/src/imxrt/chip/rt105x/imxrt_ccm.h - * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Authors: Janne Rosberg - * David Sidrane - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_CCM_H -#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_CCM_H - -/************************************************************************************************************ - * Included Files - ************************************************************************************************************/ - -#include -#include "chip/imxrt_memorymap.h" - -/************************************************************************************************************ - * Pre-processor Definitions - ************************************************************************************************************/ - -/* Register offsets *****************************************************************************************/ - -#define IMXRT_CCM_CCR_OFFSET 0x0000 /* CCM Control Register */ - /* 0x0004 Reserved */ -#define IMXRT_CCM_CSR_OFFSET 0x0008 /* CCM Status Register */ -#define IMXRT_CCM_CCSR_OFFSET 0x000c /* CCM Clock Switcher Register */ -#define IMXRT_CCM_CACRR_OFFSET 0x0010 /* CCM Arm Clock Root Register */ -#define IMXRT_CCM_CBCDR_OFFSET 0x0014 /* CCM Bus Clock Divider Register */ -#define IMXRT_CCM_CBCMR_OFFSET 0x0018 /* CCM Bus Clock Multiplexer Register */ -#define IMXRT_CCM_CSCMR1_OFFSET 0x001c /* CCM Serial Clock Multiplexer Register 1 */ -#define IMXRT_CCM_CSCMR2_OFFSET 0x0020 /* CCM Serial Clock Multiplexer Register 2 */ -#define IMXRT_CCM_CSCDR1_OFFSET 0x0024 /* CCM Serial Clock Divider Register 1 */ -#define IMXRT_CCM_CS1CDR_OFFSET 0x0028 /* CCM Clock Divider Register */ -#define IMXRT_CCM_CS2CDR_OFFSET 0x002c /* CCM Clock Divider Register */ -#define IMXRT_CCM_CDCDR_OFFSET 0x0030 /* CCM D1 Clock Divider Register */ - /* 0x0034 Reserved */ -#define IMXRT_CCM_CSCDR2_OFFSET 0x0038 /* CCM Serial Clock Divider Register 2 */ -#define IMXRT_CCM_CSCDR3_OFFSET 0x003c /* CCM Serial Clock Divider Register 3 */ - /* 0x0040 Reserved */ - /* 0x0044 Reserved */ -#define IMXRT_CCM_CDHIPR_OFFSET 0x0048 /* CCM Divider Handshake In-Process Register */ - /* 0x004c Reserved */ - /* 0x0050 Reserved */ -#define IMXRT_CCM_CLPCR_OFFSET 0x0054 /* CCM Low Power Control Register */ - -#define IMXRT_CCM_CISR_OFFSET 0x0058 /* CCM Interrupt Status Register */ -#define IMXRT_CCM_CIMR_OFFSET 0x005c /* CCM Interrupt Mask Register */ -#define IMXRT_CCM_CCOSR_OFFSET 0x0060 /* CCM Clock Output Source Register */ -#define IMXRT_CCM_CGPR_OFFSET 0x0064 /* CCM General Purpose Register */ -#define IMXRT_CCM_CCGR0_OFFSET 0x0068 /* CCM Clock Gating Register 0 */ -#define IMXRT_CCM_CCGR1_OFFSET 0x006c /* CCM Clock Gating Register 1 */ -#define IMXRT_CCM_CCGR2_OFFSET 0x0070 /* CCM Clock Gating Register 2 */ -#define IMXRT_CCM_CCGR3_OFFSET 0x0074 /* CCM Clock Gating Register 3 */ -#define IMXRT_CCM_CCGR4_OFFSET 0x0078 /* CCM Clock Gating Register 4 */ -#define IMXRT_CCM_CCGR5_OFFSET 0x007c /* CCM Clock Gating Register 5 */ -#define IMXRT_CCM_CCGR6_OFFSET 0x0080 /* CCM Clock Gating Register 6 */ - /* 0x0084 Reserved */ -#define IMXRT_CCM_CMEOR_OFFSET 0x0088 /* CCM Module Enable Overide Register */ - -/* Analog */ - -#define IMXRT_CCM_ANALOG_PLL_ARM_OFFSET 0x0000 /* Analog ARM PLL control Register */ -#define IMXRT_CCM_ANALOG_PLL_USB1_OFFSET 0x0010 /* Analog USB1 480MHz PLL Control Register */ -#define IMXRT_CCM_ANALOG_PLL_USB2_OFFSET 0x0020 /* Analog USB2 480MHz PLL Control Register */ -#define IMXRT_CCM_ANALOG_PLL_SYS_OFFSET 0x0030 /* Analog System PLL Control Register */ -#define IMXRT_CCM_ANALOG_PLL_SYS_SS_OFFSET 0x0040 /* 528MHz System PLL Spread Spectrum Register */ -#define IMXRT_CCM_ANALOG_PLL_SYS_NUM_OFFSET 0x0050 /* Numerator of 528MHz System PLL Fractional Loop Divider */ -#define IMXRT_CCM_ANALOG_PLL_SYS_DENOM_OFFSET 0x0060 /* Denominator of 528MHz System PLL Fractional Loop Divider */ -#define IMXRT_CCM_ANALOG_PLL_AUDIO_OFFSET 0x0070 /* Analog Audio PLL control Register */ -#define IMXRT_CCM_ANALOG_PLL_AUDIO_NUM_OFFSET 0x0080 /* Numerator of Audio PLL Fractional Loop Divider */ -#define IMXRT_CCM_ANALOG_PLL_AUDIO_DENOM_OFFSET 0x0090 /* Denominator of Audio PLL Fractional Loop Divider */ -#define IMXRT_CCM_ANALOG_PLL_VIDEO_OFFSET 0x00a0 /* Analog Video PLL control Register */ -#define IMXRT_CCM_ANALOG_PLL_VIDEO_NUM_OFFSET 0x00b0 /* Numerator of Video PLL Fractional Loop Divider */ -#define IMXRT_CCM_ANALOG_PLL_VIDEO_DENOM_OFFSET 0x00c0 /* Denominator of Video PLL Fractional Loop Divider */ -#define IMXRT_CCM_ANALOG_PLL_ENET_OFFSET 0x00e0 /* Analog ENET PLL Control Register */ -#define IMXRT_CCM_ANALOG_PFD_480_OFFSET 0x00f0 /* 480MHz Clock (PLL3) Phase Fractional Divider Control */ -#define IMXRT_CCM_ANALOG_PFD_528_OFFSET 0x0100 /* 528MHz Clock (PLL2) Phase Fractional Divider Control */ -#define IMXRT_CCM_ANALOG_MISC0_OFFSET 0x0150 /* Miscellaneous Register 0 */ -#define IMXRT_CCM_ANALOG_MISC1_OFFSET 0x0160 /* Miscellaneous Register 1 */ -#define IMXRT_CCM_ANALOG_MISC2_OFFSET 0x0170 /* Miscellaneous Register 2 */ - -/* Register addresses ***************************************************************************************/ - -#define IMXRT_CCM_CCR (IMXRT_CCM_BASE + IMXRT_CCM_CCR_OFFSET) -#define IMXRT_CCM_CSR (IMXRT_CCM_BASE + IMXRT_CCM_CSR_OFFSET) -#define IMXRT_CCM_CCSR (IMXRT_CCM_BASE + IMXRT_CCM_CCSR_OFFSET) -#define IMXRT_CCM_CACRR (IMXRT_CCM_BASE + IMXRT_CCM_CACRR_OFFSET) -#define IMXRT_CCM_CBCDR (IMXRT_CCM_BASE + IMXRT_CCM_CBCDR_OFFSET) -#define IMXRT_CCM_CBCMR (IMXRT_CCM_BASE + IMXRT_CCM_CBCMR_OFFSET) -#define IMXRT_CCM_CSCMR1 (IMXRT_CCM_BASE + IMXRT_CCM_CSCMR1_OFFSET) -#define IMXRT_CCM_CSCMR2 (IMXRT_CCM_BASE + IMXRT_CCM_CSCMR2_OFFSET) -#define IMXRT_CCM_CSCDR1 (IMXRT_CCM_BASE + IMXRT_CCM_CSCDR1_OFFSET) -#define IMXRT_CCM_CS1CDR (IMXRT_CCM_BASE + IMXRT_CCM_CS1CDR_OFFSET) -#define IMXRT_CCM_CS2CDR (IMXRT_CCM_BASE + IMXRT_CCM_CS2CDR_OFFSET) -#define IMXRT_CCM_CDCDR (IMXRT_CCM_BASE + IMXRT_CCM_CDCDR_OFFSET) -#define IMXRT_CCM_CSCDR2 (IMXRT_CCM_BASE + IMXRT_CCM_CSCDR2_OFFSET) -#define IMXRT_CCM_CSCDR3 (IMXRT_CCM_BASE + IMXRT_CCM_CSCDR3_OFFSET) -#define IMXRT_CCM_CDHIPR (IMXRT_CCM_BASE + IMXRT_CCM_CDHIPR_OFFSET) -#define IMXRT_CCM_CLPCR (IMXRT_CCM_BASE + IMXRT_CCM_CLPCR_OFFSET) -#define IMXRT_CCM_CISR (IMXRT_CCM_BASE + IMXRT_CCM_CISR_OFFSET) -#define IMXRT_CCM_CIMR (IMXRT_CCM_BASE + IMXRT_CCM_CIMR_OFFSET) -#define IMXRT_CCM_CCOSR (IMXRT_CCM_BASE + IMXRT_CCM_CCOSR_OFFSET) -#define IMXRT_CCM_CGPR (IMXRT_CCM_BASE + IMXRT_CCM_CGPR_OFFSET) -#define IMXRT_CCM_CCGR0 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR0_OFFSET) -#define IMXRT_CCM_CCGR1 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR1_OFFSET) -#define IMXRT_CCM_CCGR2 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR2_OFFSET) -#define IMXRT_CCM_CCGR3 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR3_OFFSET) -#define IMXRT_CCM_CCGR4 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR4_OFFSET) -#define IMXRT_CCM_CCGR5 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR5_OFFSET) -#define IMXRT_CCM_CCGR6 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR6_OFFSET) -#define IMXRT_CCM_CMEOR (IMXRT_CCM_BASE + IMXRT_CCM_CMEOR_OFFSET) - -#define IMXRT_CCM_ANALOG_PLL_ARM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_ARM_OFFSET) -#define IMXRT_CCM_ANALOG_PLL_USB1 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_USB1_OFFSET) -#define IMXRT_CCM_ANALOG_PLL_USB2 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_USB2_OFFSET) -#define IMXRT_CCM_ANALOG_PLL_SYS (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_SYS_OFFSET) -#define IMXRT_CCM_ANALOG_PLL_SYS_SS (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_SYS_SS_OFFSET) -#define IMXRT_CCM_ANALOG_PLL_SYS_NUM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_SYS_NUM_OFFSET) -#define IMXRT_CCM_ANALOG_PLL_SYS_DENOM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_SYS_DENOM_OFFSET) -#define IMXRT_CCM_ANALOG_PLL_AUDIO (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_AUDIO_OFFSET) -#define IMXRT_CCM_ANALOG_PLL_AUDIO_NUM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_AUDIO_NUM_OFFSET) -#define IMXRT_CCM_ANALOG_PLL_AUDIO_DENOM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_AUDIO_DENOM_OFFSET) -#define IMXRT_CCM_ANALOG_PLL_VIDEO (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_VIDEO_OFFSET) -#define IMXRT_CCM_ANALOG_PLL_VIDEO_NUM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_VIDEO_NUM_OFFSET) -#define IMXRT_CCM_ANALOG_PLL_VIDEO_DENOM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_VIDEO_DENOM_OFFSET) -#define IMXRT_CCM_ANALOG_PLL_ENET (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_ENET_OFFSET) -#define IMXRT_CCM_ANALOG_PFD_480 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PFD_480_OFFSET) -#define IMXRT_CCM_ANALOG_PFD_528 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PFD_528_OFFSET) -#define IMXRT_CCM_ANALOG_MISC0 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_MISC0_OFFSET) -#define IMXRT_CCM_ANALOG_MISC1 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_MISC1_OFFSET) -#define IMXRT_CCM_ANALOG_MISC2 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_MISC2_OFFSET) - -/* Helper Macros *********************************************************************************/ - -#define CCM_PODF_FROM_DIVISOR(n) ((n)-1) /* PODF Values are divisor-1 */ - -/* Register bit definitions *********************************************************************************/ - -/* Control Register */ - -#define CCM_CCR_OSCNT_SHIFT (0) /* Bits 0-7: Oscillator ready counter value */ -#define CCM_CCR_OSCNT_MASK (0xff << CCM_CCR_OSCNT_SHIFT) -# define CCM_CCR_OSCNT(n) ((uint32_t)(n) << CCM_CCR_OSCNT_SHIFT) - /* Bits 8-11: Reserved */ -#define CCM_CCR_COSC_EN (1 << 12) /* Bit 12: On chip oscillator enable */ - /* Bits 13-20: Reserved */ -#define CCM_CCR_REG_BYPASS_COUNT_SHIFT (21) /* Bits 21-26: Counter for analog_reg_bypass */ -#define CCM_CCR_REG_BYPASS_COUNT_MASK (0x3f << CCM_CCR_REG_BYPASS_COUNT_SHIFT) -# define CCM_CCR_REG_BYPASS_COUNT(n) ((uint32_t)(n) << CCM_CCR_REG_BYPASS_COUNT_SHIFT) -#define CCM_CCR_RBC_EN (1 << 27) /* Bit 27: Enable for REG_BYPASS_COUNTER */ - /* Bits 28-31: Reserved */ -/* Status Register */ - -#define CCM_CSR_REF_EN_B (1 << 0) /* Bit 0: Status of the value of CCM_REF_EN_B */ - /* Bits 1-2: Reserved */ -#define CCM_CSR_CAMP2_READY (3 << 0) /* Bit 3: Status indication of CAMP2 */ - /* Bit 4: Reserved */ -#define CCM_CSR_COSC_READY (5 << 0) /* Bit 5: Status indication of on board oscillator */ - /* Bits 6-31: Reserved */ -/* Clock Switcher Register */ - -#define CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0) /* Bit 0: Selects source to generate pll3_sw_clk */ - -/* Arm Clock Root Register */ - -#define CCM_CACRR_ARM_PODF_SHIFT (0) /* Bits 0-2: Divider for ARM clock root */ -#define CCM_CACRR_ARM_PODF_MASK (0x3 << CCM_CACRR_ARM_PODF_SHIFT) -# define CCM_CACRR_ARM_PODF(n) ((uint32_t)(n) << CCM_CACRR_ARM_PODF_SHIFT) - -/* Bus Clock Divider Register */ - - /* Bits 0-5: Reserved */ -#define CCM_CBCDR_SEMC_CLK_SEL (1 << 6) /* Bit 6: SEMC clock source select */ -#define CCM_CBCDR_SEMC_ALT_CLK_SEL (1 << 7) /* Bit 7: SEMC alternative clock select */ -#define CCM_CBCDR_SEMC_ALT_CLK_SEL_PLL2 (0 << 7) /* Bit 7: PLL2 PFD2 will be selected */ -#define CCM_CBCDR_SEMC_ALT_CLK_SEL_PLL3 (1 << 7) /* Bit 7: PLL3 PFD1 will be selected */ -#define CCM_CBCDR_IPG_PODF_SHIFT (8) /* Bits 8-9: Divider for ipg podf */ -#define CCM_CBCDR_IPG_PODF_MASK (0x3 << CCM_CBCDR_IPG_PODF_SHIFT) -# define CCM_CBCDR_IPG_PODF(n) ((uint32_t)(n) << CCM_CBCDR_IPG_PODF_SHIFT) -#define CCM_CBCDR_AHB_PODF_SHIFT (10) /* Bits 10-12: Divider for AHB PODF */ -#define CCM_CBCDR_AHB_PODF_MASK (0x3 << CCM_CBCDR_AHB_PODF_SHIFT) -# define CCM_CBCDR_AHB_PODF(n) ((uint32_t)(n) << CCM_CBCDR_AHB_PODF_SHIFT) - /* Bits 13-15: Reserved */ -#define CCM_CBCDR_SEMC_PODF_SHIFT (16) /* Bits 16-18: Post divider for SEMC clock */ -#define CCM_CBCDR_SEMC_PODF_MASK (0x3 << CCM_CBCDR_SEMC_PODF_SHIFT) -# define CCM_CBCDR_SEMC_PODF(n) ((uint32_t)(n) << CCM_CBCDR_SEMC_PODF_SHIFT) - /* Bits 19-24: Reserved */ -#define CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25) /* Bit 25: Selector for peripheral main clock */ -#define CCM_CBCDR_PERIPH_CLK_SEL_MASK (1 << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT) -# define CCM_CBCDR_PERIPH_CLK_SEL(n) ((uint32_t)(n) << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT) -# define CCM_CBCDR_PERIPH_CLK_SEL_PRE_PERIPH (0) -# define CCM_CBCDR_PERIPH_CLK_SEL_PERIPH_CLK2 (1) - - /* Bit 26: Reserved */ -#define CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT (27) /* Bits 27-29: Divider for periph_clk2_podf */ -#define CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) -# define CCM_CBCDR_PERIPH_CLK2_PODF(n) ((uint32_t)(n) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) - /* Bits 30-31: Reserved */ - -/* Bus Clock Multiplexer Register */ - - /* Bits 0-3: Reserved */ -#define CCM_CBCMR_LPSPI_CLK_SEL_SHIFT (4) /* Bits 4-5: Selector for lpspi clock multiplexer */ -#define CCM_CBCMR_LPSPI_CLK_SEL_MASK (0x3 << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) -# define CCM_CBCMR_LPSPI_CLK_SEL(n) ((uint32_t)(n) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) -# define CCM_CBCMR_LPSPI_CLK_SEL_PLL3_PFD1 ((uint32_t)(0) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) -# define CCM_CBCMR_LPSPI_CLK_SEL_PLL3_PFD0 ((uint32_t)(1) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) -# define CCM_CBCMR_LPSPI_CLK_SEL_PLL2 ((uint32_t)(2) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) -# define CCM_CBCMR_LPSPI_CLK_SEL_PLL2_PFD2 ((uint32_t)(3) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) - /* Bits 6-11: Reserved */ -#define CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT (12) /* Bits 12-13: Selector for peripheral clk2 clock multiplexer */ -#define CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT) -# define CCM_CBCMR_PERIPH_CLK2_SEL(n) ((uint32_t)(n) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT) -# define CCM_CBCMR_PERIPH_CLK2_SEL_PLL3_SW ((uint32_t)(0) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT) -# define CCM_CBCMR_PERIPH_CLK2_SEL_OSC_CLK ((uint32_t)(1) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT) -# define CCM_CBCMR_PERIPH_CLK2_SEL_PLL2_BP ((uint32_t)(2) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT) -#define CCM_CBCMR_TRACE_CLK_SEL_SHIFT (14) /* Bits 14-15: Selector for Trace clock multiplexer */ -#define CCM_CBCMR_TRACE_CLK_SEL_MASK (0x3 << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) -# define CCM_CBCMR_TRACE_CLK_SEL(n) ((uint32_t)(n) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) -# define CCM_CBCMR_TRACE_CLK_SEL_PLL2 ((uint32_t)(0) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) -# define CCM_CBCMR_TRACE_CLK_SEL_PLL2_PFD2 ((uint32_t)(1) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) -# define CCM_CBCMR_TRACE_CLK_SEL_PLL2_PFD0 ((uint32_t)(2) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) -# define CCM_CBCMR_TRACE_CLK_SEL_PLL2_PFD1 ((uint32_t)(3) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) - /* Bits 16-17: Reserved */ -#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18) /* Bits 18-19: Selector for pre_periph clock multiplexer */ -#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT) -# define CCM_CBCMR_PRE_PERIPH_CLK_SEL(n) ((uint32_t)(n) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT) -# define CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL2 (0) -# define CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL2_PFD2 (1) -# define CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL2_PFD0 (2) -# define CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL1 (3) - /* Bits 20-22: Reserved */ -#define CCM_CBCMR_LCDIF_PODF_SHIFT (23) /* Bits 23-25: Post-divider for LCDIF clock */ -#define CCM_CBCMR_LCDIF_PODF_MASK (0x7 << CCM_CBCMR_LCDIF_PODF_SHIFT) -# define CCM_CBCMR_LCDIF_PODF(n) ((uint32_t)(n) << CCM_CBCMR_LCDIF_PODF_SHIFT) -#define CCM_CBCMR_LPSPI_PODF_SHIFT (26) /* Bits 26-28: Divider for LPSPI */ -#define CCM_CBCMR_LPSPI_PODF_MASK (0x7 << CCM_CBCMR_LPSPI_PODF_SHIFT) -# define CCM_CBCMR_LPSPI_PODF(n) ((uint32_t)(n) << CCM_CBCMR_LPSPI_PODF_SHIFT) - -/* Serial Clock Multiplexer Register 1 */ - -#define CCM_CSCMR1_PERCLK_PODF_SHIFT (0) /* Bits 0-5: Divider for perclk podf */ -#define CCM_CSCMR1_PERCLK_PODF_MASK (0x3f << CCM_CSCMR1_PERCLK_PODF_SHIFT) -# define CCM_CSCMR1_PERCLK_PODF(n) ((uint32_t)(n) << CCM_CSCMR1_PERCLK_PODF_SHIFT) -#define CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT (6) /* Bit 6: Selector for the perclk clock multiplexer */ -#define CCM_CSCMR1_PERCLK_CLK_SEL_MASK (1 << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT) -# define CCM_CSCMR1_PERCLK_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT) -# define CCM_CSCMR1_PERCLK_CLK_SEL_IPG_CLK_ROOT (0) -# define CCM_CSCMR1_PERCLK_CLK_SEL_OSC_CLK (1) - /* Bits 7-9: Reserved */ -#define CCM_CSCMR1_SAI1_CLK_SEL_SHIFT (10) /* Bits 10-11: Selector for sai1 clock multiplexer */ -#define CCM_CSCMR1_SAI1_CLK_SEL_MASK (0x3 << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT) -# define CCM_CSCMR1_SAI1_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT) -# define CCM_CSCMR1_SAI1_CLK_SEL_PLL3_PFD2 ((uint32_t)(0) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT) -# define CCM_CSCMR1_SAI1_CLK_SEL_PLL5 ((uint32_t)(1) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT) -# define CCM_CSCMR1_SAI1_CLK_SEL_PLL4 ((uint32_t)(2) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT) -#define CCM_CSCMR1_SAI2_CLK_SEL_SHIFT (12) /* Bits 12-13: Selector for sai2 clock multiplexer */ -#define CCM_CSCMR1_SAI2_CLK_SEL_MASK (0x3 << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT) -# define CCM_CSCMR1_SAI2_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT) -# define CCM_CSCMR1_SAI2_CLK_SEL_PLL3_PFD2 ((uint32_t)(0) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT) -# define CCM_CSCMR1_SAI2_CLK_SEL_PLL5 ((uint32_t)(1) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT) -# define CCM_CSCMR1_SAI2_CLK_SEL_PLL4 ((uint32_t)(2) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT) -#define CCM_CSCMR1_SAI3_CLK_SEL_SHIFT (14) /* Bits 14-15: Selector for sai3 clock multiplexer */ -#define CCM_CSCMR1_SAI3_CLK_SEL_MASK (0x3 << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT) -# define CCM_CSCMR1_SAI3_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT) -# define CCM_CSCMR1_SAI3_CLK_SEL_PLL3_PFD2 ((uint32_t)(0) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT) -# define CCM_CSCMR1_SAI3_CLK_SEL_PLL5 ((uint32_t)(1) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT) -# define CCM_CSCMR1_SAI3_CLK_SEL_PLL4 ((uint32_t)(2) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT) -#define CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16) /* Bit 16: Selector for usdhc1 clock multiplexer */ -# define CCM_CSCMR1_USDHC1_CLK_SEL_PLL2_PFD2 (0 << 16) /* derive clock from PLL2 PFD2 */ -# define CCM_CSCMR1_USDHC1_CLK_SEL_PLL2_PFD0 (1 << 16) /* derive clock from PLL2 PFD0 */ -#define CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17) /* Bit 17: Selector for usdhc2 clock multiplexer */ -# define CCM_CSCMR1_USDHC2_CLK_SEL_PLL2_PFD2 (0 << 17) /* derive clock from PLL2 PFD2 */ -# define CCM_CSCMR1_USDHC2_CLK_SEL_PLL2_PFD0 (1 << 17) /* derive clock from PLL2 PFD0 */ - /* Bits 18-22: Reserved */ -#define CCM_CSCMR1_FLEXSPI_PODF_SHIFT (23) /* Bits 23-25: Divider for flexspi clock root */ -#define CCM_CSCMR1_FLEXSPI_PODF_MASK (0x7 << CCM_CSCMR1_FLEXSPI_PODF_SHIFT) -# define CCM_CSCMR1_FLEXSPI_PODF(n) ((uint32_t)(n) << CCM_CSCMR1_FLEXSPI_PODF_SHIFT) - /* Bits 26-28: Reserved */ -#define CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT (29) /* Bits 29-30: Selector for flexspi clock multiplexer */ -#define CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK (0x3 << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) -# define CCM_CSCMR1_FLEXSPI_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) -# define CCM_CSCMR1_FLEXSPI_CLK_SEL_SEMC_CLK ((uint32_t)(0) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) -# define CCM_CSCMR1_FLEXSPI_CLK_SEL_PLL3_SW ((uint32_t)(1) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) -# define CCM_CSCMR1_FLEXSPI_CLK_SEL_PLL2_PFD2 ((uint32_t)(2) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) -# define CCM_CSCMR1_FLEXSPI_CLK_SEL_PLL3_PFD0 ((uint32_t)(3) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) - /* Bit 31: Reserved */ - -/* Serial Clock Multiplexer Register 2 */ - -#define CCM_CSCMR2_CAN_CLK_PODF_SHIFT (2) /* Bits 2-7: Divider for can clock podf */ -#define CCM_CSCMR2_CAN_CLK_PODF_MASK (0x3f << CCM_CSCMR2_CAN_CLK_PODF_SHIFT) -# define CCM_CSCMR2_CAN_CLK_PODF(n) ((uint32_t)(n) << CCM_CSCMR2_CAN_CLK_PODF_SHIFT) -#define CCM_CSCMR2_CAN_CLK_SEL_SHIFT (8) /* Bits 8-9: Selector for FlexCAN clock multiplexer */ -#define CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << CCM_CSCMR2_CAN_CLK_SEL_SHIFT) -# define CCM_CSCMR2_CAN_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT) -# define CCM_CSCMR2_CAN_CLK_SEL_PLL3_SW_60 ((uint32_t)(0) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT) -# define CCM_CSCMR2_CAN_CLK_SEL_OSC_CLK ((uint32_t)(1) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT) -# define CCM_CSCMR2_CAN_CLK_SEL_PLL3_SW_80 ((uint32_t)(2) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT) - /* Bits 10-18: Reserved */ -#define CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT (19) /* Bits 19-20: Selector for flexio2 clock multiplexer */ -#define CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK (0x3 << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT) -# define CCM_CSCMR2_FLEXIO2_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT) -# define CCM_CSCMR2_FLEXIO2_CLK_SEL_PLL4 ((uint32_t)(0) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT) -# define CCM_CSCMR2_FLEXIO2_CLK_SEL_PLL3_PFD2 ((uint32_t)(1) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT) -# define CCM_CSCMR2_FLEXIO2_CLK_SEL_PLL5 ((uint32_t)(2) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT) -# define CCM_CSCMR2_FLEXIO2_CLK_SEL_PLL3_SW ((uint32_t)(3) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT) - /* Bits 21-31: Reserved */ - -/* Serial Clock Divider Register 1 */ - -#define CCM_CSCDR1_UART_CLK_PODF_SHIFT (0) /* Bits 0-5: Divider for uart clock podf */ -#define CCM_CSCDR1_UART_CLK_PODF_MASK (0x3f << CCM_CSCDR1_UART_CLK_PODF_SHIFT) -# define CCM_CSCDR1_UART_CLK_PODF(n) ((uint32_t)(n) << CCM_CSCDR1_UART_CLK_PODF_SHIFT) -#define CCM_CSCDR1_UART_CLK_SEL (1 << 6) /* Bit 6: Selector for the UART clock multiplexer */ -# define CCM_CSCDR1_UART_CLK_SEL_PLL3_80 (0 << 6) /* derive clock from pll3_80m */ -# define CCM_CSCDR1_UART_CLK_SEL_OSC_CLK (1 << 6) /* derive clock from osc_clk */ - /* Bits 7-10: Reserved */ -#define CCM_CSCDR1_USDHC1_PODF_SHIFT (11) /* Bits 11-13: Divider for usdhc1 clock podf */ -#define CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << CCM_CSCDR1_USDHC1_PODF_SHIFT) -# define CCM_CSCDR1_USDHC1_PODF(n) ((uint32_t)(n) << CCM_CSCDR1_USDHC1_PODF_SHIFT) - /* Bits 14-15: Reserved */ -#define CCM_CSCDR1_USDHC2_PODF_SHIFT (16) /* Bits 16-18: Divider for usdhc2 clock */ -#define CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << CCM_CSCDR1_USDHC2_PODF_SHIFT) -# define CCM_CSCDR1_USDHC2_PODF(n) ((uint32_t)(n) << CCM_CSCDR1_USDHC2_PODF_SHIFT) - /* Bits 19-24: Reserved */ -#define CCM_CSCDR1_TRACE_PODF_SHIFT (25) /* Bits 25-27: Divider for trace clock */ -#define CCM_CSCDR1_TRACE_PODF_MASK (0x7 << CCM_CSCDR1_TRACE_PODF_SHIFT) -# define CCM_CSCDR1_TRACE_PODF(n) ((uint32_t)(n) << CCM_CSCDR1_TRACE_PODF_SHIFT) - /* Bits 28-31: Reserved */ - -/* Clock Divider Register 1 */ - -#define CCM_CS1CDR_SAI1_CLK_PODF_SHIFT (0) /* Bits 0-5: Divider for sai1 clock podf */ -#define CCM_CS1CDR_SAI1_CLK_PODF_MASK (0x3f << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT) -# define CCM_CS1CDR_SAI1_CLK_PODF(n) ((uint32_t)(n) << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT) -#define CCM_CS1CDR_SAI1_CLK_PRED_SHIFT (6) /* Bits 6-8: Divider for sai1 clock pred */ -#define CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x7 << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT) -# define CCM_CS1CDR_SAI1_CLK_PRED(n) ((uint32_t)(n) << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT) -#define CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT (9) /* Bits 9-11: Divider for flexio2 clock */ -#define CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK (0x7 << CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT) -# define CCM_CS1CDR_FLEXIO2_CLK_PRED(n) ((uint32_t)(n) << CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT) - /* Bits 12-15: Reserved */ -#define CCM_CS1CDR_SAI3_CLK_PODF_SHIFT (16) /* Bits 16-21: Divider for sai3 clock podf */ -#define CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3f << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT) -# define CCM_CS1CDR_SAI3_CLK_PODF(n) ((uint32_t)(n) << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT) -#define CCM_CS1CDR_SAI3_CLK_PRED_SHIFT (22) /* Bits 22-24: Divider for sai3 clock pred */ -#define CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x7 << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT) -# define CCM_CS1CDR_SAI3_CLK_PRED(n) ((uint32_t)(n) << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT) -#define CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT (25) /* Bits 25-27: Divider for flexio2 clock */ -#define CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK (0x7 << CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT) -# define CCM_CS1CDR_FLEXIO2_CLK_PODF(n) ((uint32_t)(n) << CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT) - /* Bits 28-31: Reserved */ - -/* Clock Divider Register 2 */ - -#define CCM_CS2CDR_SAI2_CLK_PODF_SHIFT (0) /* Bits 0-5: Divider for sai2 clock podf */ -#define CCM_CS2CDR_SAI2_CLK_PODF_MASK (0x3f << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT) -# define CCM_CS2CDR_SAI2_CLK_PODF(n) ((uint32_t)(n) << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT) -#define CCM_CS2CDR_SAI2_CLK_PRED_SHIFT (6) /* Bits 6-8: Divider for sai2 clock pred */ -#define CCM_CS2CDR_SAI2_CLK_PRED_MASK (0x7 << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT) -# define CCM_CS2CDR_SAI2_CLK_PRED(n) ((uint32_t)(n) << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT) - -/* D1 Clock Divider Register */ - -#define CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT (7) /* Bits 7-8: Selector for flexio1 clock multiplexer */ -#define CCM_CDCDR_FLEXIO1_CLK_SEL_MASK (0x3 << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT) -# define CCM_CDCDR_FLEXIO1_CLK_SEL(n) ((uint32_t)(n) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT) -# define CCM_CDCDR_FLEXIO1_CLK_SEL_PLL4 ((uint32_t)(0) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT) -# define CCM_CDCDR_FLEXIO1_CLK_SEL_PLL3_PFD2 ((uint32_t)(1) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT) -# define CCM_CDCDR_FLEXIO1_CLK_SEL_PLL3_PLL5 ((uint32_t)(2) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT) -# define CCM_CDCDR_FLEXIO1_CLK_SEL_PLL3_PLL3_SW ((uint32_t)(3) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT) -#define CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT (9) /* Bits 9-11: Divider for flexio1 clock podf */ -#define CCM_CDCDR_FLEXIO1_CLK_PODF_MASK (0x7 << CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT) -# define CCM_CDCDR_FLEXIO1_CLK_PODF(n) ((uint32_t)(n) << CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT) -#define CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT (12) /* Bits 12-14: Divider for flexio1 clock pred */ -#define CCM_CDCDR_FLEXIO1_CLK_PRED_MASK (0x7 << CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT) -# define CCM_CDCDR_FLEXIO1_CLK_PRED(n) ((uint32_t)(n) << CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT) - /* Bits 15-19: Reserved */ -#define CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT (20) /* Bits 20-21: Selector for spdif0 clock multiplexer */ -#define CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) -# define CCM_CDCDR_SPDIF0_CLK_SEL(n) ((uint32_t)(n) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) -# define CCM_CDCDR_SPDIF0_CLK_SEL_PLL4 ((uint32_t)(0) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) -# define CCM_CDCDR_SPDIF0_CLK_SEL_PLL3_PFD2 ((uint32_t)(1) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) -# define CCM_CDCDR_SPDIF0_CLK_SEL_PLL3_PLL5 ((uint32_t)(2) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) -# define CCM_CDCDR_SPDIF0_CLK_SEL_PLL3_PLL3_SW ((uint32_t)(3) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) -#define CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT (22) /* Bits 22-24: Divider for spdif0 clock podf */ -#define CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT) -# define CCM_CDCDR_SPDIF0_CLK_PODF(n) ((uint32_t)(n) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT) -#define CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT (25) /* Bits 25-27: Divider for spdif0 clock pred */ -#define CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT) -# define CCM_CDCDR_SPDIF0_CLK_PRED(n) ((uint32_t)(n) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT) - -/* Serial Clock Divider Register 2 */ - - /* Bits 0-8: Reserved */ -#define CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT (9) /* Bits 9-11: Selector for LCDIF root clock multiplexer */ -#define CCM_CSCDR2_LCDIF_CLK_SEL_MASK (0x7 << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT) -# define CCM_CSCDR2_LCDIF_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT) -# define CCM_CSCDR2_LCDIF_CLK_SEL_LCDIF ((uint32_t)(0) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT) -# define CCM_CSCDR2_LCDIF_CLK_SEL_IPP_DI0_CLK ((uint32_t)(1) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT) -# define CCM_CSCDR2_LCDIF_CLK_SEL_IPP_DI1_CLK ((uint32_t)(2) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT) -# define CCM_CSCDR2_LCDIF_CLK_SEL_IDB_DI0_CLK ((uint32_t)(3) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT) -# define CCM_CSCDR2_LCDIF_CLK_SEL_IDB_DI1_CLK ((uint32_t)(4) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT) -#define CCM_CSCDR2_LCDIF_PRED_SHIFT (12) /* Bits 12-14: Pre-divider for lcdif clock */ -#define CCM_CSCDR2_LCDIF_PRED_MASK (0x7 << CCM_CSCDR2_LCDIF_PRED_SHIFT) -# define CCM_CSCDR2_LCDIF_PRED(n) ((uint32_t)(n) << CCM_CSCDR2_LCDIF_PRED_SHIFT) -#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT (15) /* Bits 15-17: Selector for lcdif root clock pre-multiplexer */ -#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK (0x7 << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) -# define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_(n) ((uint32_t)(n) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) -# define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL2 ((uint32_t)(0) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) -# define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL3_PFD3 ((uint32_t)(1) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) -# define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL5 ((uint32_t)(2) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) -# define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL2_PFD0 ((uint32_t)(3) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) -# define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL2_PFD1 ((uint32_t)(4) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) -# define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL3_PFD1 ((uint32_t)(5) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) -#define CCM_CSCDR2_LPI2C_CLK_SEL (1 << 18) /* Bit 18: Selector for the LPI2C clock multiplexer */ -# define CCM_CSCDR2_LPI2C_CLK_SEL_PLL3_60M (0 << 18) /* derive clock from pll3_60m */ -# define CCM_CSCDR2_LPI2C_CLK_SEL_OSC_CLK (1 << 18) /* derive clock from ock_clk */ -#define CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT (19) /* Bits 19-24: Divider for lpi2c clock podf */ -#define CCM_CSCDR2_LPI2C_CLK_PODF_MASK (0x3f << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT) -# define CCM_CSCDR2_LPI2C_CLK_PODF(n) ((uint32_t)(n) << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT) - /* Bits 25-31: Reserved */ - -/* Serial Clock Divider Register 3 */ - - /* Bits 0-8: Reserved */ -#define CCM_CSCDR3_CSI_CLK_SEL_SHIFT (9) /* Bits 9-10: Selector for csi_mclk multiplexer */ -#define CCM_CSCDR3_CSI_CLK_SEL_MASK (0x3 << CCM_CSCDR3_CSI_CLK_SEL_SHIFT) -# define CCM_CSCDR3_CSI_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT) -# define CCM_CSCDR3_CSI_CLK_SEL_OSC_CLK ((uint32_t)(0) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT) -# define CCM_CSCDR3_CSI_CLK_SEL_OSC_PLL2_PFD2 ((uint32_t)(1) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT) -# define CCM_CSCDR3_CSI_CLK_SEL_OSC_PLL3_120M ((uint32_t)(2) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT) -# define CCM_CSCDR3_CSI_CLK_SEL_OSC_PLL3_PFD1 ((uint32_t)(3) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT) -#define CCM_CSCDR3_CSI_PODF_SHIFT (11) /* Bits 11-13: Post divider for csi_mclk */ -#define CCM_CSCDR3_CSI_PODF_MASK (0x3 << CCM_CSCDR3_CSI_PODF_SHIFT) -# define CCM_CSCDR3_CSI_PODF(n) ((uint32_t)(n) << CCM_CSCDR3_CSI_PODF_SHIFT) - -/* Divider Handshake In-Process Register */ - -#define CCM_CDHIPR_SEMC_PODF_BUSY (1 << 0) /* Bit 0: Busy indicator for semc_podf */ -#define CCM_CDHIPR_AHB_PODF_BUSY (1 << 1) /* Bit 1: Busy indicator for ahb_podf */ - /* Bit 2: Reserved */ -#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3) /* Bit 3: Busy indicator for periph2_clk_sel mux control */ - /* Bit 4: Reserved */ -#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5) /* Bit 5: Busy indicator for periph_clk_sel mux control */ - /* Bits 6-15: Reserved */ -#define CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) /* Bit 16: Busy indicator for arm_podf */ - /* Bits 17-31: Reserved */ - -/* Low Power Control Register */ - -#define CCM_CLPCR_LPM_SHIFT (0) /* Bits 0-1: Setting the low power mode */ -#define CCM_CLPCR_LPM_MASK (0x3 << CCM_CLPCR_LPM_SHIFT) -# define CCM_CLPCR_LPM(n) ((uint32_t)(n) << CCM_CLPCR_LPM_SHIFT) -# define CCM_CLPCR_LPM_RUN ((uint32_t)(0) << CCM_CLPCR_LPM_SHIFT) /* Remain in run mode */ -# define CCM_CLPCR_LPM_WAIT ((uint32_t)(1) << CCM_CLPCR_LPM_SHIFT) /* Transfer to wait mode */ -# define CCM_CLPCR_LPM_STOP ((uint32_t)(2) << CCM_CLPCR_LPM_SHIFT) /* Transfer to stop mode */ - /* Bits 2-4: Reserved */ -#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5) /* Bit 5: ARM clocks disabled on wait mode */ -#define CCM_CLPCR_SBYOS (1 << 6) /* Bit 6: Standby clock oscillator bit */ -#define CCM_CLPCR_DIS_REF_OSC (1 << 7) /* Bit 7: external high frequency oscillator disable */ -#define CCM_CLPCR_VSTBY (1 << 8) /* Bit 8: Voltage standby request bit */ -#define CCM_CLPCR_STBY_COUNT_SHIFT (9) /* Bits 9-10: Standby counter definition */ -#define CCM_CLPCR_STBY_COUNT_MASK (0x3 << CCM_CLPCR_STBY_COUNT_SHIFT) -# define CCM_CLPCR_STBY_COUNT(n) ((uint32_t)(n) << CCM_CLPCR_STBY_COUNT_SHIFT) -#define CCM_CLPCR_COSC_PWRDOWN (1 << 11) /* Bit 11: On chip oscillator power down */ - /* Bits 12-18: Reserved */ -#define CCM_CLPCR_BYPASS_LPM_HS1 (1 << 19) /* Bit 19: Bypass low power mode handshake */ - /* Bit 20: Reserved */ -#define CCM_CLPCR_BYPASS_LPM_HS0 (1 << 21) /* Bit 21: Bypass low power mode handshake */ -#define CCM_CLPCR_MASK_CORE0_WFI (1 << 22) /* Bit 22: Mask WFI of core0 for entering low power mode */ - /* Bits 23-25: Reserved */ -#define CCM_CLPCR_MASK_SCU_IDLE (1 << 26) /* Bit 26: Mask SCU IDLE for entering low power mode */ -#define CCM_CLPCR_MASK_L2CC_IDLE (1 << 27) /* Bit 27: Mask L2CC IDLE for entering low power mode */ - /* Bits 28-31: Reserved */ - -/* Interrupt Status Register */ - -#define CCM_CISR_LRF_PLL (1 << 0) /* Bit 0: CCM irq2, lock of all enabled and not bypassed PLLs */ - /* Bits 1-5: Reserved */ -#define CCM_CISR_COSC_READY (1 << 6) /* Bit 6: CCM irq2, on board oscillator ready */ - /* Bits 7-16: Reserved */ -#define CCM_CISR_SEMC_PODF_LOADED (1 << 17) /* Bit 17: CCM irq1, frequency change of semc_podf */ - /* Bit 18: Reserved */ -#define CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19) /* Bit 19: CCM irq1, frequency change of periph2_clk_sel */ -#define CCM_CISR_AHB_PODF_LOADED (1 << 20) /* Bit 20: CCM irq1, frequency change of ahb_podf */ - /* Bit 21: Reserved */ -#define CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22) /* Bit 22: CCM irq1, update of periph_clk_sel */ - /* Bits 23-25: Reserved */ -#define CCM_CISR_ARM_PODF_LOADED (1 << 26) /* Bit 26: CCM irq1, frequency change of arm_podf */ - /* Bits 27-31: Reserved */ - -/* Interrupt Mask Register */ - -#define CCM_CIMR_MASK_LRF_PLL (1 << 0) /* Bit 0: mask interrupt generation due to lrf of PLLs */ - /* Bits 1-5: Reserved */ -#define CCM_CIMR_MASK_COSC_READY (1 << 6) /* Bit 6: mask interrupt generation due to on board oscillator ready */ - /* Bits 7-16: Reserved */ -#define CCM_CIMR_MASK_SEMC_PODF_LOADED (1 << 17) /* Bit 17: mask interrupt generation due to frequency change of semc_podf */ - /* Bit 18: Reserved */ -#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 19) /* Bit 19: mask interrupt generation due to update of periph2_clk_sel */ -#define CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20) /* Bit 20: mask interrupt generation due to frequency change of ahb_podf */ - /* Bit 21: Reserved */ -#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22) /* Bit 22: mask interrupt generation due to update of periph_clk_sel */ - /* Bits 23-25: Reserved */ -#define CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26) /* Bit 26: mask interrupt generation due to frequency change of arm_podf */ - /* Bits 27-31: Reserved */ - -/* Clock Output Source Register */ - -#define CCM_CCOSR_CLKO1_SEL_SHIFT (0) /* Bits 0-3: Selection of the clock to be generated on CCM_CLKO1 */ -#define CCM_CCOSR_CLKO1_SEL_MASK (0xF << CCM_CCOSR_CLKO1_SEL_SHIFT) -# define CCM_CCOSR_CLKO1_SEL_SEMC_CLK ((uint32_t)(5) << CCM_CCOSR_CLKO1_SEL_SHIFT) -# define CCM_CCOSR_CLKO1_SEL_ENC_CLK ((uint32_t)(6) << CCM_CCOSR_CLKO1_SEL_SHIFT) -# define CCM_CCOSR_CLKO1_SEL_LCDIF_PIX_CLK ((uint32_t)(10) << CCM_CCOSR_CLKO1_SEL_SHIFT) -# define CCM_CCOSR_CLKO1_SEL_AHB_CLK ((uint32_t)(11) << CCM_CCOSR_CLKO1_SEL_SHIFT) -# define CCM_CCOSR_CLKO1_SEL_IPG_CLK ((uint32_t)(12) << CCM_CCOSR_CLKO1_SEL_SHIFT) -# define CCM_CCOSR_CLKO1_SEL_PER_CLK ((uint32_t)(13) << CCM_CCOSR_CLKO1_SEL_SHIFT) -# define CCM_CCOSR_CLKO1_SEL_CKIL_SYNC_CLK ((uint32_t)(14) << CCM_CCOSR_CLKO1_SEL_SHIFT) -# define CCM_CCOSR_CLKO1_SEL_PLL4_MAIN_CLK ((uint32_t)(15) << CCM_CCOSR_CLKO1_SEL_SHIFT) -#define CCM_CCOSR_CLKO1_DIV_SHIFT (4) /* Bits 4-6: Setting the divider of CCM_CLKO1 */ -#define CCM_CCOSR_CLKO1_DIV_MASK (0x7 << CCM_CCOSR_CLKO1_DIV_SHIFT) -# define CCM_CCOSR_CLKO1_DIV(n) ((uint32_t)(n) << CCM_CCOSR_CLKO1_DIV_SHIFT) -#define CCM_CCOSR_CLKO1_EN (1 << 7) /* Bit 7: Enable of CCM_CLKO1 clock */ -#define CCM_CCOSR_CLK_OUT_SEL (1 << 8) /* Bit 8: CCM_CLKO1 output to reflect CCM_CLKO1 or CCM_CLKO2 clocks */ - /* Bits 9-15: Reserved */ -#define CCM_CCOSR_CLKO2_SEL_SHIFT (16) /* Bits 16-20: Selection of the clock to be generated on CCM_CLKO2 */ -#define CCM_CCOSR_CLKO2_SEL_MASK (0x1F << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_USDHC1_CLK ((uint32_t)(3) << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_WRCK_CLK ((uint32_t)(5) << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_LPI2C_CLK ((uint32_t)(6) << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_CSI_CORE ((uint32_t)(11) << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_OSC_CLK ((uint32_t)(14) << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_USDHC2_CLK ((uint32_t)(17) << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_SAI1_CLK ((uint32_t)(18) << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_SAI2_CLK ((uint32_t)(19) << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_SAI3_CLK ((uint32_t)(20) << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_CAN_CLK ((uint32_t)(23) << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_FLEXSPI_CLK ((uint32_t)(27) << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_UART_CLK ((uint32_t)(28) << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_SPDIF0_CLK ((uint32_t)(29) << CCM_CCOSR_CLKO2_SEL_SHIFT) -#define CCM_CCOSR_CLKO2_DIV_SHIFT (21) /* Bits 21-23: Setting the divider of CCM_CLKO2 */ -#define CCM_CCOSR_CLKO2_DIV_MASK (0x7 << CCM_CCOSR_CLKO2_DIV_SHIFT) -# define CCM_CCOSR_CLKO2_DIV(n) ((uint32_t)(n) << CCM_CCOSR_CLKO2_DIV_SHIFT) -#define CCM_CCOSR_CLKO2_EN (1 << 24) /* Bit 24: Enable of CCM_CLKO2 clock */ - /* Bits 25-31: Reserved */ - -/* General Purpose Register */ - -#define CCM_CGPR_PMIC_DELAY_SCALER (1 << 0) /* Bit 0: Defines clock division of clock for stby_count */ - /* Bits 1-3: Reserved */ -#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4) /* Bit 4: allow fuse programing */ - /* Bits 5-13: Reserved */ -#define CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT (14) /* Bits 14-15: System memory DS control */ -#define CCM_CGPR_SYS_MEM_DS_CTRL_MASK (0x7 << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT) -# define CCM_CGPR_SYS_MEM_DS_CTRL(n) ((uint32_t)(n) << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT) -#define CCM_CGPR_FPL (1 << 16) /* Bit 16: Fast PLL enable */ -#define CCM_CGPR_INT_MEM_CLK_LPM (1 << 17) /* Bit 17: Control for the Deep Sleep signal to the ARM Platform memories */ - /* Bits 18-31: Reserved */ - -/* Clock Gating Register 0-6 */ - -#define CCM_CG_OFF (0) /* Clock is off during all modes */ -#define CCM_CG_RUN (1) /* Clock is on in run mode, but off in WAIT and STOP modes */ -#define CCM_CG_ALL (3) /* Clock is on during all modes, except STOP mode. */ - -#define CCM_CCGRX_CG_SHIFT(r) ((r) << 1) -#define CCM_CCGRX_CG_MASK(r) (0x3 << CCM_CCGRX_CG_SHIFT(r)) -# define CCM_CCGRX_CG(r,v) ((uint32_t)(v) << CCM_CCGRX_CG_SHIFT(r)) - -#define CCM_CCGRX_CG0_SHIFT (0) -#define CCM_CCGRX_CG0_MASK (0x3 << CCM_CCGRX_CG0_SHIFT) -# define CCM_CCGRX_CG0(n) ((uint32_t)(n) << CCM_CCGRX_CG0_SHIFT) -#define CCM_CCGRX_CG1_SHIFT (2) -#define CCM_CCGRX_CG1_MASK (0x3 << CCM_CCGRX_CG1_SHIFT) -# define CCM_CCGRX_CG1(n) ((uint32_t)(n) << CCM_CCGRX_CG1_SHIFT) -#define CCM_CCGRX_CG2_SHIFT (4) -#define CCM_CCGRX_CG2_MASK (0x3 << CCM_CCGRX_CG2_SHIFT) -# define CCM_CCGRX_CG2(n) ((uint32_t)(n) << CCM_CCGRX_CG2_SHIFT) -#define CCM_CCGRX_CG3_SHIFT (6) -#define CCM_CCGRX_CG3_MASK (0x3 << CCM_CCGRX_CG3_SHIFT) -# define CCM_CCGRX_CG3(n) ((uint32_t)(n) << CCM_CCGRX_CG3_SHIFT) -#define CCM_CCGRX_CG4_SHIFT (8) -#define CCM_CCGRX_CG4_MASK (0x3 << CCM_CCGRX_CG4_SHIFT) -# define CCM_CCGRX_CG4(n) ((uint32_t)(n) << CCM_CCGRX_CG4_SHIFT) -#define CCM_CCGRX_CG5_SHIFT (10) -#define CCM_CCGRX_CG5_MASK (0x3 << CCM_CCGRX_CG5_SHIFT) -# define CCM_CCGRX_CG5(n) ((uint32_t)(n) << CCM_CCGRX_CG5_SHIFT) -#define CCM_CCGRX_CG6_SHIFT (12) -#define CCM_CCGRX_CG6_MASK (0x3 << CCM_CCGRX_CG6_SHIFT) -# define CCM_CCGRX_CG6(n) ((uint32_t)(n) << CCM_CCGRX_CG6_SHIFT) -#define CCM_CCGRX_CG7_SHIFT (14) -#define CCM_CCGRX_CG7_MASK (0x3 << CCM_CCGRX_CG7_SHIFT) -# define CCM_CCGRX_CG7(n) ((uint32_t)(n) << CCM_CCGRX_CG7_SHIFT) -#define CCM_CCGRX_CG8_SHIFT (16) -#define CCM_CCGRX_CG8_MASK (0x3 << CCM_CCGRX_CG8_SHIFT) -# define CCM_CCGRX_CG8(n) ((uint32_t)(n) << CCM_CCGRX_CG8_SHIFT) -#define CCM_CCGRX_CG9_SHIFT (18) -#define CCM_CCGRX_CG9_MASK (0x3 << CCM_CCGRX_CG9_SHIFT) -# define CCM_CCGRX_CG9(n) ((uint32_t)(n) << CCM_CCGRX_CG9_SHIFT) -#define CCM_CCGRX_CG10_SHIFT (20) -#define CCM_CCGRX_CG10_MASK (0x3 << CCM_CCGRX_CG10_SHIFT) -# define CCM_CCGRX_CG10(n) ((uint32_t)(n) << CCM_CCGRX_CG10_SHIFT) -#define CCM_CCGRX_CG11_SHIFT (22) -#define CCM_CCGRX_CG11_MASK (0x3 << CCM_CCGRX_CG11_SHIFT) -# define CCM_CCGRX_CG11(n) ((uint32_t)(n) << CCM_CCGRX_CG11_SHIFT) -#define CCM_CCGRX_CG12_SHIFT (24) -#define CCM_CCGRX_CG12_MASK (0x3 << CCM_CCGRX_CG12_SHIFT) -# define CCM_CCGRX_CG12(n) ((uint32_t)(n) << CCM_CCGRX_CG12_SHIFT) -#define CCM_CCGRX_CG13_SHIFT (26) -#define CCM_CCGRX_CG13_MASK (0x3 << CCM_CCGRX_CG13_SHIFT) -# define CCM_CCGRX_CG13(n) ((uint32_t)(n) << CCM_CCGRX_CG13_SHIFT) -#define CCM_CCGRX_CG14_SHIFT (28) -#define CCM_CCGRX_CG14_MASK (0x3 << CCM_CCGRX_CG14_SHIFT) -# define CCM_CCGRX_CG14(n) ((uint32_t)(n) << CCM_CCGRX_CG14_SHIFT) -#define CCM_CCGRX_CG15_SHIFT (30) -#define CCM_CCGRX_CG15_MASK (0x3 << CCM_CCGRX_CG15_SHIFT) -# define CCM_CCGRX_CG15(n) ((uint32_t)(n) << CCM_CCGRX_CG15_SHIFT) - -/* Macros used by imxrt_periphclks.h */ - -#define CCM_CCGR_GPIO2 IMXRT_CCM_CCGR0, 15 -#define CCM_CCGR_LPUART2 IMXRT_CCM_CCGR0, 14 -#define CCM_CCGR_GPT2_SERIAL IMXRT_CCM_CCGR0, 13 -#define CCM_CCGR_GPT2_BUS IMXRT_CCM_CCGR0, 12 -#define CCM_CCGR_TRACE IMXRT_CCM_CCGR0, 11 -#define CCM_CCGR_CAN2_SERIAL IMXRT_CCM_CCGR0, 10 -#define CCM_CCGR_CAN2 IMXRT_CCM_CCGR0, 9 -#define CCM_CCGR_CAN1_SERIAL IMXRT_CCM_CCGR0, 8 -#define CCM_CCGR_CAN1 IMXRT_CCM_CCGR0, 7 -#define CCM_CCGR_LPUART3 IMXRT_CCM_CCGR0, 6 -#define CCM_CCGR_DCP IMXRT_CCM_CCGR0, 5 -#define CCM_CCGR_MQS IMXRT_CCM_CCGR0, 2 -#define CCM_CCGR_AIPS_TZ2 IMXRT_CCM_CCGR0, 1 -#define CCM_CCGR_AIPS_TZ1 IMXRT_CCM_CCGR0, 0 - -#define CCM_CCGR_CSU IMXRT_CCM_CCGR1, 14 -#define CCM_CCGR_GPIO1 IMXRT_CCM_CCGR1, 13 -#define CCM_CCGR_LPUART4 IMXRT_CCM_CCGR1, 12 -#define CCM_CCGR_GPT_SERIAL IMXRT_CCM_CCGR1, 11 -#define CCM_CCGR_GPT_BUS IMXRT_CCM_CCGR1, 10 -#define CCM_CCGR_ADC1 IMXRT_CCM_CCGR1, 8 -#define CCM_CCGR_AOI2 IMXRT_CCM_CCGR1, 7 -#define CCM_CCGR_PIT IMXRT_CCM_CCGR1, 6 -#define CCM_CCGR_ENET IMXRT_CCM_CCGR1, 5 -#define CCM_CCGR_ADC2 IMXRT_CCM_CCGR1, 4 -#define CCM_CCGR_LPSPI4 IMXRT_CCM_CCGR1, 3 -#define CCM_CCGR_LPSPI3 IMXRT_CCM_CCGR1, 2 -#define CCM_CCGR_LPSPI2 IMXRT_CCM_CCGR1, 1 -#define CCM_CCGR_LPSPI1 IMXRT_CCM_CCGR1, 0 - -#define CCM_CCGR_PXP IMXRT_CCM_CCGR2, 15 -#define CCM_CCGR_LCD IMXRT_CCM_CCGR2, 14 -#define CCM_CCGR_GPIO3 IMXRT_CCM_CCGR2, 13 -#define CCM_CCGR_XBAR2 IMXRT_CCM_CCGR2, 12 -#define CCM_CCGR_XBAR1 IMXRT_CCM_CCGR2, 11 -#define CCM_CCGR_IPMUX3 IMXRT_CCM_CCGR2, 10 -#define CCM_CCGR_IPMUX2 IMXRT_CCM_CCGR2, 9 -#define CCM_CCGR_IPMUX1 IMXRT_CCM_CCGR2, 8 -#define CCM_CCGR_XBAR3 IMXRT_CCM_CCGR2, 7 -#define CCM_CCGR_OCOTP_CTRL IMXRT_CCM_CCGR2, 6 -#define CCM_CCGR_LPI2C3 IMXRT_CCM_CCGR2, 5 -#define CCM_CCGR_LPI2C2 IMXRT_CCM_CCGR2, 4 -#define CCM_CCGR_LPI2C1 IMXRT_CCM_CCGR2, 3 -#define CCM_CCGR_IOMUXC_SNVS IMXRT_CCM_CCGR2, 2 -#define CCM_CCGR_CSI IMXRT_CCM_CCGR2, 1 - -#define CCM_CCGR_IOMUXC_SNVS_GPR IMXRT_CCM_CCGR3, 15 -#define CCM_CCGR_OCRAM IMXRT_CCM_CCGR3, 14 -#define CCM_CCGR_ACMP4 IMXRT_CCM_CCGR3, 13 -#define CCM_CCGR_ACMP3 IMXRT_CCM_CCGR3, 12 -#define CCM_CCGR_ACMP2 IMXRT_CCM_CCGR3, 11 -#define CCM_CCGR_ACMP1 IMXRT_CCM_CCGR3, 10 -#define CCM_CCGR_FLEXRAM IMXRT_CCM_CCGR3, 9 -#define CCM_CCGR_WDOG1 IMXRT_CCM_CCGR3, 8 -#define CCM_CCGR_EWM IMXRT_CCM_CCGR3, 7 -#define CCM_CCGR_GPIO4 IMXRT_CCM_CCGR3, 6 -#define CCM_CCGR_LCDIF_PIX IMXRT_CCM_CCGR3, 5 -#define CCM_CCGR_AOI1 IMXRT_CCM_CCGR3, 4 -#define CCM_CCGR_LPUART6 IMXRT_CCM_CCGR3, 3 -#define CCM_CCGR_SEMC IMXRT_CCM_CCGR3, 2 -#define CCM_CCGR_LPUART5 IMXRT_CCM_CCGR3, 1 -#define CCM_CCGR_FLEXIO2 IMXRT_CCM_CCGR3, 0 - -#define CCM_CCGR_ENC4 IMXRT_CCM_CCGR4, 15 -#define CCM_CCGR_ENC3 IMXRT_CCM_CCGR4, 14 -#define CCM_CCGR_ENC2 IMXRT_CCM_CCGR4, 13 -#define CCM_CCGR_ENC1 IMXRT_CCM_CCGR4, 12 -#define CCM_CCGR_PWM4 IMXRT_CCM_CCGR4, 11 -#define CCM_CCGR_PWM3 IMXRT_CCM_CCGR4, 10 -#define CCM_CCGR_PWM2 IMXRT_CCM_CCGR4, 9 -#define CCM_CCGR_PWM1 IMXRT_CCM_CCGR4, 8 -#define CCM_CCGR_SIM_EMS IMXRT_CCM_CCGR4, 7 -#define CCM_CCGR_SIM_M IMXRT_CCM_CCGR4, 6 -#define CCM_CCGR_TSC_DIG IMXRT_CCM_CCGR4, 5 -#define CCM_CCGR_SIM_M7 IMXRT_CCM_CCGR4, 4 -#define CCM_CCGR_BEE IMXRT_CCM_CCGR4, 3 -#define CCM_CCGR_IOMUXC_GPR IMXRT_CCM_CCGR4, 2 -#define CCM_CCGR_IOMUXC IMXRT_CCM_CCGR4, 1 - -#define CCM_CCGR_SNVS_LP IMXRT_CCM_CCGR5, 15 -#define CCM_CCGR_SNVS_HP IMXRT_CCM_CCGR5, 14 -#define CCM_CCGR_LPUART7 IMXRT_CCM_CCGR5, 13 -#define CCM_CCGR_LPUART1 IMXRT_CCM_CCGR5, 12 -#define CCM_CCGR_SAI3 IMXRT_CCM_CCGR5, 11 -#define CCM_CCGR_SAI2 IMXRT_CCM_CCGR5, 10 -#define CCM_CCGR_SAI1 IMXRT_CCM_CCGR5, 9 -#define CCM_CCGR_SIM_MAIN IMXRT_CCM_CCGR5, 8 -#define CCM_CCGR_SPDIF IMXRT_CCM_CCGR5, 7 -#define CCM_CCGR_AIPSTZ4 IMXRT_CCM_CCGR5, 6 -#define CCM_CCGR_WDOG2 IMXRT_CCM_CCGR5, 5 -#define CCM_CCGR_KPP IMXRT_CCM_CCGR5, 4 -#define CCM_CCGR_DMA IMXRT_CCM_CCGR5, 3 -#define CCM_CCGR_WDOG3 IMXRT_CCM_CCGR5, 2 -#define CCM_CCGR_FLEXIO1 IMXRT_CCM_CCGR5, 1 -#define CCM_CCGR_ROM IMXRT_CCM_CCGR5, 0 - -#define CCM_CCGR_TIMER3 IMXRT_CCM_CCGR6, 15 -#define CCM_CCGR_TIMER2 IMXRT_CCM_CCGR6, 14 -#define CCM_CCGR_TIMER1 IMXRT_CCM_CCGR6, 13 -#define CCM_CCGR_LPI2C4_SERIAL IMXRT_CCM_CCGR6, 12 -#define CCM_CCGR_ANADIG IMXRT_CCM_CCGR6, 11 -#define CCM_CCGR_SIM_PER IMXRT_CCM_CCGR6, 10 -#define CCM_CCGR_AIPS_TZ3 IMXRT_CCM_CCGR6, 9 -#define CCM_CCGR_TIMER4 IMXRT_CCM_CCGR6, 8 -#define CCM_CCGR_LPUART8 IMXRT_CCM_CCGR6, 7 -#define CCM_CCGR_TRNG IMXRT_CCM_CCGR6, 6 -#define CCM_CCGR_FLEXSPI IMXRT_CCM_CCGR6, 5 -#define CCM_CCGR_IPMUX4 IMXRT_CCM_CCGR6, 4 -#define CCM_CCGR_DCDC IMXRT_CCM_CCGR6, 3 -#define CCM_CCGR_USDHC2 IMXRT_CCM_CCGR6, 2 -#define CCM_CCGR_USDHC1 IMXRT_CCM_CCGR6, 1 -#define CCM_CCGR_USBOH3 IMXRT_CCM_CCGR6, 0 - -/* Module Enable Override Register */ - - /* Bits 0-4: Reserved */ -#define CCM_CMEOR_MOD_EN_OV_GPT (1 << 5) /* Bit 5: Overide clock enable signal from GPT */ -#define CCM_CMEOR_MOD_EN_OV_PIT (1 << 6) /* Bit 6: Overide clock enable signal from PIT */ -#define CCM_CMEOR_MOD_EN_OV_USDHC (1 << 7) /* Bit 7: Overide clock enable signal from USDHC */ -#define CCM_CMEOR_MOD_EN_OV_TRNG (1 << 9) /* Bit 9: Overide clock enable signal from TRNG */ - /* Bits 10-27: Reserved */ -#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI (1 << 28) /* Bit 28: Overide clock enable signal from CAN2 */ -#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI (1 << 30) /* Bit 30: Overide clock enable signal from CAN1 */ - /* Bit 31: Reserved */ - -/* Analog ARM PLL control Register */ - -#define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT (0) /* Bits 0-6: This field controls the PLL loop divider 54-108 */ -#define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK (0x7f << CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_ARM_DIV_SELECT(n) ((uint32_t)(n) << CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT) - /* Bits 7-11 Reserved */ -#define CCM_ANALOG_PLL_ARM_POWERDOWN (1 << 12) /* Bit 12: Powers down the PLL */ -#define CCM_ANALOG_PLL_ARM_ENABLE (1 << 13) /* Bit 13: Enable the clock output */ -#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ -#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT) -# define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ -# define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ -#define CCM_ANALOG_PLL_ARM_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ - /* Bits 17-18 Reserved */ -#define CCM_ANALOG_PLL_ARM_PLL_SEL (1 << 39) /* Bit 19: ? */ -#define CCM_ANALOG_PLL_ARM_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ - -/* Analog USB1 480MHz PLL Control Register */ - -#define CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT (1) /* Bits 0-1: This field controls the PLL loop divider 20 or 22 */ -#define CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK (0x1 << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_USB1_DIV_SELECT_20 ((uint32_t)(0) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_USB1_DIV_SELECT_22 ((uint32_t)(1) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT) - /* Bits 2-5 Reserved */ -#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS (1 << 6) /* Bit 6: Enable PLL outputs for USBPHYn */ -#define CCM_ANALOG_PLL_USB1_POWER (1 << 12) /* Bit 12: Powers up the PLL */ -#define CCM_ANALOG_PLL_USB1_ENABLE (1 << 13) /* Bit 13: Enable the PLL clock output */ -#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ -#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) -# define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ -# define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ -# define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_GPANAIO ((uint32_t)(2) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) /* */ -# define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_CHRG_DET_B ((uint32_t)(3) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) /* */ -#define CCM_ANALOG_PLL_USB1_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ - /* Bits 17-30 Reserved */ -#define CCM_ANALOG_PLL_USB1_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ - -/* Analog USB2 480MHz PLL Control Register */ - -#define CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT (0) /* Bits 0-1: This field controls the PLL loop divider 20 or 22 */ -#define CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK (0x3 << CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_USB2_DIV_SELECT_20 ((uint32_t)(0) << CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_USB2_DIV_SELECT_22 ((uint32_t)(1) << CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT) - /* Bits 2-5 Reserved */ -#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS (1 << 6) /* Bit 6: Enable PLL outputs for USBPHYn */ -#define CCM_ANALOG_PLL_USB2_POWER (1 << 12) /* Bit 12: Powers up the PLL */ -#define CCM_ANALOG_PLL_USB2_ENABLE (1 << 13) /* Bit 13: Enable the PLL clock output */ -#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ -#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT) -# define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ -# define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ -#define CCM_ANALOG_PLL_USB2_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ - /* Bits 17-30 Reserved */ -#define CCM_ANALOG_PLL_USB2_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ - -/* Analog System PLL Control Register */ - -#define CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT (0) /* Bits 0-1: This field controls the PLL loop divider 20 or 22 */ -#define CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK (0x3 << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_SYS_DIV_SELECT(n) ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_SYS_DIV_SELECT_20 (0) -# define CCM_ANALOG_PLL_SYS_DIV_SELECT_22 (1) -#define CCM_ANALOG_PLL_SYS_POWERDOWN (1 << 12) /* Bit 12: Powers down the PLL */ -#define CCM_ANALOG_PLL_SYS_ENABLE (1 << 13) /* Bit 13: Enable the PLL clock output */ -#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ -#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) -# define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ -# define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ -# define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_GPANAIO ((uint32_t)(2) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) /* */ -# define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_CHRG_DET_B ((uint32_t)(3) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) /* */ -#define CCM_ANALOG_PLL_SYS_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ - /* Bit 17: Reserved */ -#define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN (1 << 18) /* Bit 18: Enables an offset in the phase frequency detector */ - /* Bits 19-30 Reserved */ -#define CCM_ANALOG_PLL_SYS_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ - -/* 528MHz System PLL Spread Spectrum Register */ - -#define CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT (0) /* Bits 0-14: Frequency change step */ -#define CCM_ANALOG_PLL_SYS_SS_STEP_MASK (0x3FFF << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT) -# define CCM_ANALOG_PLL_SYS_SS_STEP(n) ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT) -#define CCM_ANALOG_PLL_SYS_SS_ENABLE (1 << 15) /* Bit 15: Enable bit */ -#define CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT (0) /* Bits 16-31: Frequency change */ -#define CCM_ANALOG_PLL_SYS_SS_STOP_MASK (0xFFFF << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT) -# define CCM_ANALOG_PLL_SYS_SS_STOP(n) ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT) - -/* Numerator of 528MHz System PLL Fractional Loop Divider Register */ - -#define CCM_ANALOG_PLL_SYS_NUM_A_SHIFT (0) /* Bits 0-29: 30 bit numerator (A) */ -#define CCM_ANALOG_PLL_SYS_NUM_A_MASK (0x3FFFFFFF << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT) -#define CCM_ANALOG_PLL_SYS_NUM_A(n) ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT) - /* Bits 30-31: Reserved */ - -/* Denominator of 528MHz System PLL Fractional Loop Divider Register */ - -#define CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT (0) /* Bits 0-29: 30 bit numerator (A) */ -#define CCM_ANALOG_PLL_SYS_DENOM_B_MASK (0x3FFFFFFF << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT) -#define CCM_ANALOG_PLL_SYS_DENOM_B(n) ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT) - /* Bits 30-31: Reserved */ - -/* Analog Audio PLL control Register */ - -#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT (0) /* Bits 0-6: This field controls the PLL loop divider: 27-54 */ -#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK (0x7f << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(n) ((uint32_t)(n) << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT) - /* Bits 7-11: Reserved */ -#define CCM_ANALOG_PLL_AUDIO_POWERDOWN (1 << 12) /* Bit 12: Powers down the PLL */ -#define CCM_ANALOG_PLL_AUDIO_ENABLE (1 << 13) /* Bit 13: Enable PLL output */ -#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ -#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT) -# define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ -# define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ -#define CCM_ANALOG_PLL_AUDIO_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ - /* Bit 17: Reserved */ -#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN (1 << 18) /* Bit 18: Enables an offset in the phase frequency detector */ -#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT (19) /* Bits 19-20: These bits implement a divider after the PLL */ -#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK (0x7f << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_DIV4 ((uint32_t)(0) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_DIV2 ((uint32_t)(1) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_DIV1 ((uint32_t)(2) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT) - /* Bits 21-30: Reserved */ -#define CCM_ANALOG_PLL_AUDIO_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ - -/* Numerator of Audio PLL Fractional Loop Divider Register */ - -#define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT (0) /* Bits 0-29: 30 bit numerator (A) */ -#define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK (0x3FFFFFFF << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT) -#define CCM_ANALOG_PLL_AUDIO_NUM_A(n) ((uint32_t)(n) << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT) -/* Bits 30-31: Reserved */ - -/* Denominator of Audio PLL Fractional Loop Divider Register */ - -#define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT (0) /* Bits 0-29: 30 bit numerator (A) */ -#define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK (0x3FFFFFFF << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT) -#define CCM_ANALOG_PLL_AUDIO_DENOM_B(n) ((uint32_t)(n) << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT) - /* Bits 30-31: Reserved */ -/* Analog Video PLL control Register */ - -#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT (0) /* Bits 0-6: This field controls the PLL loop divider: 27-54 */ -#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK (0x7f << CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_VIDEO_DIV_SELECT(n) ((uint32_t)(n) << CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT) - /* Bits 7-11: Reserved */ -#define CCM_ANALOG_PLL_VIDEO_POWERDOWN (1 << 12) /* Bit 12: Powers down the PLL */ -#define CCM_ANALOG_PLL_VIDEO_ENABLE (1 << 13) /* Bit 13: Enable PLL output */ -#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ -#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT) -# define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ -# define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ -#define CCM_ANALOG_PLL_VIDEO_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ - /* Bit 17: Reserved */ -#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN (1 << 18) /* Bit 18: Enables an offset in the phase frequency detector */ -#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT (19) /* Bits 19-20: These bits implement a divider after the PLL */ -#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK (0x7f << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_DIV4 ((uint32_t)(0) << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_DIV2 ((uint32_t)(1) << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_DIV1 ((uint32_t)(2) << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT) - /* Bits 21-30: Reserved */ -#define CCM_ANALOG_PLL_VIDEO_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ - -/* Numerator of Video PLL Fractional Loop Divider Register */ - -#define CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT (0) /* Bits 0-29: 30 bit numerator (A) */ -#define CCM_ANALOG_PLL_VIDEO_NUM_A_MASK (0x3FFFFFFF << CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT) -#define CCM_ANALOG_PLL_VIDEO_NUM_A(n) ((uint32_t)(n) << CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT) - /* Bits 30-31: Reserved */ - -/* Denominator of Video PLL Fractional Loop Divider Register */ - -#define CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT (0) /* Bits 0-29: 30 bit numerator (A) */ -#define CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK (0x3FFFFFFF << CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT) -#define CCM_ANALOG_PLL_VIDEO_DENOM_B(n) ((uint32_t)(n) << CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT) - /* Bits 30-31: Reserved */ - -/* Analog ENET PLL Control Register */ - -#define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT (0) /* Bits 0-1: Controls the frequency of the ethernet0 reference clock */ -#define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_MASK (0x3 << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_25MHZ ((uint32_t)(0) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_50MHZ ((uint32_t)(1) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_100MHZ ((uint32_t)(2) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_125MHZ ((uint32_t)(3) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT) -#define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT (2) /* Bits 0-1: Controls the frequency of the ethernet1 reference clock */ -#define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_MASK (0x3 << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_25MHZ ((uint32_t)(0) << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_50MHZ ((uint32_t)(1) << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_100MHZ ((uint32_t)(2) << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_125MHZ ((uint32_t)(3) << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT) - /* Bits 4-11: Reserved */ -#define CCM_ANALOG_PLL_ENET_POWERDOWN (1 << 12) /* Bit 12: Powers down the PLL */ -#define CCM_ANALOG_PLL_ENET_ENET1_125M_EN (1 << 13) /* Bit 13: Enable the PLL providing the ENET1 125 MHz reference clock */ -#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ -#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT) -# define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ -# define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ -#define CCM_ANALOG_PLL_ENET_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ - /* Bit 17: Reserved */ -#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN (1 << 18) /* Bit 18: Enables an offset in the phase frequency detector */ -#define CCM_ANALOG_PLL_ENET_ENABLE_125M (1 << 19) /* Bit 19: */ -#define CCM_ANALOG_PLL_ENET_ENET2_125M_EN (1 << 20) /* Bit 20: Enable the PLL providing the ENET2 125 MHz reference clock */ -#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN (1 << 21) /* Bit 21: Enable the PLL providing ENET 25 MHz reference clock */ -#define CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN (1 << 22) /* Bit 22: Enable the PLL providing NET 500 MHz reference clock */ - -#define CCM_ANALOG_PLL_ENET_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ - -/* 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ - -#define CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT (0) /* Bits 0-5: This field controls the fractional divide value */ -#define CCM_ANALOG_PFD_480_PFD0_FRAC_MASK (0x3f << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT) -# define CCM_ANALOG_PFD_480_PFD0_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT) -#define CCM_ANALOG_PFD_480_PFD0_STABLE (6) /* Bit 6: */ -#define CCM_ANALOG_PFD_480_PFD0_CLKGATE (7) /* Bit 7: If set to 1, the IO fractional divider clock is off */ -#define CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT (8) /* Bits 8-13: This field controls the fractional divide value */ -#define CCM_ANALOG_PFD_480_PFD1_FRAC_MASK (0x3f << CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT) -# define CCM_ANALOG_PFD_480_PFD1_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_481_PFD1_FRAC_SHIFT) -#define CCM_ANALOG_PFD_480_PFD1_STABLE (14) /* Bit 14: */ -#define CCM_ANALOG_PFD_480_PFD1_CLKGATE (15) /* Bit 15: If set to 1, the IO fractional divider clock is off */ -#define CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT (16) /* Bits 8-21: This field controls the fractional divide value */ -#define CCM_ANALOG_PFD_480_PFD2_FRAC_MASK (0x3f << CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT) -# define CCM_ANALOG_PFD_480_PFD2_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_482_PFD2_FRAC_SHIFT) -#define CCM_ANALOG_PFD_480_PFD2_STABLE (22) /* Bit 22: */ -#define CCM_ANALOG_PFD_480_PFD2_CLKGATE (23) /* Bit 23: If set to 1, the IO fractional divider clock is off */ -#define CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT (24) /* Bits 24-29: This field controls the fractional divide value */ -#define CCM_ANALOG_PFD_480_PFD3_FRAC_MASK (0x3f << CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT) -# define CCM_ANALOG_PFD_480_PFD3_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_482_PFD3_FRAC_SHIFT) -#define CCM_ANALOG_PFD_480_PFD3_STABLE (30) /* Bit 30: */ -#define CCM_ANALOG_PFD_480_PFD3_CLKGATE (31) /* Bit 31: If set to 1, the IO fractional divider clock is off */ - -/* 528MHz Clock (PLL2) Phase Fractional Divider Control */ - -#define CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT (0) /* Bits 0-5: This field controls the fractional divide value */ -#define CCM_ANALOG_PFD_528_PFD0_FRAC_MASK (0x3f << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT) -# define CCM_ANALOG_PFD_528_PFD0_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT) -#define CCM_ANALOG_PFD_528_PFD0_STABLE (6) /* Bit 6: */ -#define CCM_ANALOG_PFD_528_PFD0_CLKGATE (7) /* Bit 7: If set to 1, the IO fractional divider clock is off */ -#define CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT (8) /* Bits 8-13: This field controls the fractional divide value */ -#define CCM_ANALOG_PFD_528_PFD1_FRAC_MASK (0x3f << CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT) -# define CCM_ANALOG_PFD_528_PFD1_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_481_PFD1_FRAC_SHIFT) -#define CCM_ANALOG_PFD_528_PFD1_STABLE (14) /* Bit 14: */ -#define CCM_ANALOG_PFD_528_PFD1_CLKGATE (15) /* Bit 15: If set to 1, the IO fractional divider clock is off */ -#define CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT (16) /* Bits 8-21: This field controls the fractional divide value */ -#define CCM_ANALOG_PFD_528_PFD2_FRAC_MASK (0x3f << CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT) -# define CCM_ANALOG_PFD_528_PFD2_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_482_PFD2_FRAC_SHIFT) -#define CCM_ANALOG_PFD_528_PFD2_STABLE (22) /* Bit 22: */ -#define CCM_ANALOG_PFD_528_PFD2_CLKGATE (23) /* Bit 23: If set to 1, the IO fractional divider clock is off */ -#define CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT (24) /* Bits 24-29: This field controls the fractional divide value */ -#define CCM_ANALOG_PFD_528_PFD3_FRAC_MASK (0x3f << CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT) -# define CCM_ANALOG_PFD_528_PFD3_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_482_PFD3_FRAC_SHIFT) -#define CCM_ANALOG_PFD_528_PFD3_STABLE (30) /* Bit 30: */ -#define CCM_ANALOG_PFD_528_PFD3_CLKGATE (31) /* Bit 31: If set to 1, the IO fractional divider clock is off */ - -/* Miscellaneous Register 0 */ - -#define CCM_ANALOG_MISC0_REFTOP_PWD (1 << 0) /* Bit 0: Control bit to power-down the analog bandgap reference circuitry */ - /* Bits 1-2: Reserved */ -#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF (1 << 2) /* Bit 3: Control bit to disable the self-bias circuit in the analog bandgap */ -#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT (4) /* Bits 4-6: VBG (PMU) */ -#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK (0x3 << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT) -# define CCM_ANALOG_MISC0_REFTOP_VBGADJ(n) ((uint32_t)(n) << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT) -#define CCM_ANALOG_MISC0_REFTOP_VBGUP (1 << 7) /* Bit 7: Status bit that signals the analog bandgap voltage is up and stable */ - /* Bits 8-9: Reserved */ -#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT (10) /* Bits 10-11: Configure the analog behavior in stop mode */ -#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK (0x3 << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT) -# define CCM_ANALOG_MISC0_STOP_MODE_CONFIG(n) ((uint32_t)(n) << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT) -#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS (1 << 12) /* Bit 12: This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN */ -#define CCM_ANALOG_MISC0_OSC_I_SHIFT (13) /* Bits 13-14: This field determines the bias current in the 24MHz oscillator */ -#define CCM_ANALOG_MISC0_OSC_I_MASK (0x3 << CCM_ANALOG_MISC0_OSC_I_SHIFT) -# define CCM_ANALOG_MISC0_OSC_I(n) ((uint32_t)(n) << CCM_ANALOG_MISC0_OSC_I_SHIFT) -#define CCM_ANALOG_MISC0_OSC_XTALOK (1 << 15) /* Bit 15: bit that signals 24-MHz crystal oscillator is stable */ -#define CCM_ANALOG_MISC0_OSC_XTALOK_EN (1 << 16) /* Bit 16: enables the detector that signals 24MHz crystal oscillator is stable */ - /* Bits 17-24: Reserved */ -#define CCM_ANALOG_MISC0_CLKGATE_CTRL (1 << 25) /* Bit 25: This bit allows disabling the clock gate */ -#define CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT (26) /* Bits 26-28: delay powering up the XTAL 24MHz */ -#define CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK (0x7 << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT) -# define CCM_ANALOG_MISC0_CLKGATE_DELAY(n) ((uint32_t)(n) << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT) -#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE (1 << 29) /* Bit 29: which chip source is being used for the rtc clock */ -#define CCM_ANALOG_MISC0_XTAL_24M_PWD (1 << 30) /* Bit 30: power down the 24M crystal oscillator if set true */ -#define CCM_ANALOG_MISC0_VID_PLL_PREDIV (1 << 31) /* Bit 31: Predivider for the source clock of the PLL's */ -#define CCM_ANALOG_MISC0_VID_PLL_PREDIV_1 (0 << 31) /* Bit 31: Predivider for the source clock of the PLL's */ -#define CCM_ANALOG_MISC0_VID_PLL_PREDIV_2 (1 << 31) /* Bit 31: Predivider for the source clock of the PLL's */ - -/* Miscellaneous Register 1 */ - -#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT (0) /* Bits 0-4: This field selects the clk to be routed to anaclk1/1b */ -#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK (0x1f << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) -# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_ARM_PLL ((uint32_t)(0) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) -# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SYS_PLL ((uint32_t)(1) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) -# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD4 ((uint32_t)(2) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) -# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD5 ((uint32_t)(3) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) -# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD6 ((uint32_t)(4) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) -# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD7 ((uint32_t)(5) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) -# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_AUDIO_PLL ((uint32_t)(6) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) -# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_VIDEO_PLL ((uint32_t)(7) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) -# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_ETHERNET_REF ((uint32_t)(9) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) -# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_USB1_PLL ((uint32_t)(12) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) -# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_USB2_PLL ((uint32_t)(13) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) -# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD0 ((uint32_t)(14) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) -# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD1 ((uint32_t)(15) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) -# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD2 ((uint32_t)(16) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) -# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD3 ((uint32_t)(17) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) -# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_XTAL ((uint32_t)(18) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) - /* Bits 5-9: Reserved */ -#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN (1 << 10) /* Bit 10: This enables the LVDS output buffer for anaclk1/1b */ - /* Bit 11: Reserved */ -#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN (1 << 12) /* Bit 12: This enables the LVDS input buffer for anaclk1/1b */ - /* Bits 13-15: Reserved */ -#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN (1 << 16) /* Bit 16: */ -#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN (1 << 17) /* Bit 17: */ - /* Bits 18-26: Reserved */ -#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC (1 << 27) /* Bit 27: temperature sensor panic interrupt */ -#define CCM_ANALOG_MISC1_IRQ_TEMPLOW (1 << 28) /* Bit 28: temperature sensor low interrupt */ -#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH (1 << 29) /* Bit 29: temperature sensor high interrupt */ -#define CCM_ANALOG_MISC1_IRQ_ANA_BO (1 << 30) /* Bit 30: analog regulator brownout interrupt */ -#define CCM_ANALOG_MISC1_IRQ_DIG_BO (1 << 31) /* Bit 31: digital regulator brownout interrupt */ - -/* Miscellaneous Register 2 */ - -#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT (0) /* Bits 0-2: This field defines the brown out voltage offset */ -#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK (0x7 << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT) -# define CCM_ANALOG_MISC2_REG0_BO_OFFSET_0_100 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT) -# define CCM_ANALOG_MISC2_REG0_BO_OFFSET_0_175 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT) -#define CCM_ANALOG_MISC2_REG0_BO_STATUS (1 << 3) /* Bit 3: Reg0 brownout status bit */ - /* Bit 4: Reserved */ -#define CCM_ANALOG_MISC2_REG0_ENABLE_BO (1 << 5) /* Bit 5: Enables the brownout detection */ -#define CCM_ANALOG_MISC2_REG0_OK (1 << 6) /* Bit 6: ARM supply */ -#define CCM_ANALOG_MISC2_PLL3_DISABLE (1 << 7) /* Bit 7: PLL3 can be disabled when the SoC is not in any low power mode */ -#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT (8) /* Bits 8-10: This field defines the brown out voltage offset */ -#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK (0x7 << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT) -# define CCM_ANALOG_MISC2_REG1_BO_OFFSET_0_100 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT) -# define CCM_ANALOG_MISC2_REG1_BO_OFFSET_0_175 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT) -#define CCM_ANALOG_MISC2_REG1_BO_STATUS (1 << 11) /* Bit 11: Reg1 brownout status bit */ - /* Bit 12: Reserved */ -#define CCM_ANALOG_MISC2_REG1_ENABLE_BO (1 << 13) /* Bit 13: Enables the brownout detection */ -#define CCM_ANALOG_MISC2_REG1_OK (1 << 14) /* Bit 14: GPU/VPU supply */ -#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB (1 << 15) /* Bit 15: LSB of Post-divider for Audio PLL */ - -#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT (16) /* Bits 16-18: This field defines the brown out voltage offset */ -#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK (0x7 << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT) -# define CCM_ANALOG_MISC2_REG2_BO_OFFSET_0_100 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT) -# define CCM_ANALOG_MISC2_REG2_BO_OFFSET_0_175 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT) -#define CCM_ANALOG_MISC2_REG2_BO_STATUS (1 << 19) /* Bit 19: Reg2 brownout status bit */ - /* Bit 20: Reserved */ -#define CCM_ANALOG_MISC2_REG2_ENABLE_BO (1 << 21) /* Bit 21: Enables the brownout detection */ -#define CCM_ANALOG_MISC2_REG2_OK (1 << 22) /* Bit 22: voltage is above the brownout level for the SOC supply */ -#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB (1 << 23) /* Bit 23: MSB of Post-divider for Audio PLL */ -#define CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT (24) /* Bits 24-25: Number of clock periods (24MHz clock) */ -#define CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK (0x3 << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC2_REG0_STEP_TIME_64 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC2_REG0_STEP_TIME_128 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC2_REG0_STEP_TIME_256 ((uint32_t)(2) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC2_REG0_STEP_TIME_512 ((uint32_t)(3) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT) -#define CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT (26) /* Bits 26-27: Number of clock periods (24MHz clock) */ -#define CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK (0x3 << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC2_REG1_STEP_TIME_64 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC2_REG1_STEP_TIME_128 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC2_REG1_STEP_TIME_256 ((uint32_t)(2) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC2_REG1_STEP_TIME_512 ((uint32_t)(3) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT) -#define CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT (28) /* Bits 28-29: Number of clock periods (24MHz clock) */ -#define CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK (0x3 << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC2_REG2_STEP_TIME_64 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC2_REG2_STEP_TIME_128 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC2_REG2_STEP_TIME_256 ((uint32_t)(2) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC2_REG2_STEP_TIME_512 ((uint32_t)(3) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT) - -#define CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT (30) /* Bits 30-31: Post-divider for video */ -#define CCM_ANALOG_MISC2_VIDEO_DIV_MASK (0x3 << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT) -# define CCM_ANALOG_MISC2_VIDEO_DIV(n) ((uint32_t)(n) << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT) - -#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_CCM_H */ diff --git a/arch/arm/src/imxrt/chip/rt105x/imxrt105x_dmamux.h b/arch/arm/src/imxrt/chip/rt105x/imxrt105x_dmamux.h deleted file mode 100644 index a1c9dae722b..00000000000 --- a/arch/arm/src/imxrt/chip/rt105x/imxrt105x_dmamux.h +++ /dev/null @@ -1,168 +0,0 @@ -/************************************************************************************ - * arch/arm/src/imxrt/chip/imxrt105x_dmamux.h - * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_DMAMUX_H -#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_DMAMUX_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -/************************************************************************************ - * Preprocessor Definitions - ************************************************************************************/ - -/* Peripheral DMA request channels */ - -#define IMXRT_DMACHAN_FLEXIO1 0 /* FlexIO1 DMA 0/1, Async DMA 0/1 */ -#define IMXRT_DMACHAN_FLEXIO2 1 /* FlexIO1 DMA 0/1, Async DMA 0/1 */ -#define IMXRT_DMACHAN_LPUART1_TX 2 /* LPUART1 TX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPUART1_RX 3 /* LPUART1 RX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPUART3_TX 4 /* LPUART3 RX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPUART3_RX 5 /* LPUART3 RX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPUART5_TX 6 /* LPUART5 TX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPUART5_RX 7 /* LPUART5 RX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPUART7_TX 8 /* LPUART7 TX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPUART7_RX 9 /* LPUART7 RX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_CSI 12 /* CSI Write DMA */ -#define IMXRT_DMACHAN_LPSPI1_RX 13 /* LPSPI1 RX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPSPI1_TX 14 /* LPSPI1 TX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPSPI3_RX 15 /* LPSPI3 RX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPSPI3_TX 16 /* LPSPI3 TX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPI2C1 17 /* LPI2C1 Master/Slave RX/TX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPI2C3 18 /* LPI2C3 Master/Slave RX/TX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_SAI1_RX 19 /* SAI1 RX FIFO DMA */ -#define IMXRT_DMACHAN_SAI1_TX 20 /* SAI1 TX FIFO DMA */ -#define IMXRT_DMACHAN_SAI2_RX 21 /* SAI2 RX FIFO DMA */ -#define IMXRT_DMACHAN_SAI2_TX 22 /* SAI2 TX FIFO DMA */ -#define IMXRT_DMACHAN_ADC_ETC 23 /* ADC ETC DMA */ -#define IMXRT_DMACHAN_ADC1 24 /* ADC1 DMA */ -#define IMXRT_DMACHAN_ACMP1 25 /* ACMP1 DMA */ -#define IMXRT_DMACHAN_ACMP2 26 /* ACMP2 DMA */ -#define IMXRT_DMACHAN_FLEXSPI_RX 28 /* FlexSPI RX FIFO DMA */ -#define IMXRT_DMACHAN_FLEXSPI_TX 29 /* FlexSPI TX FIFO DMA */ -#define IMXRT_DMACHAN_XBAR1_0 30 /* XBAR1 DMA 0 */ -#define IMXRT_DMACHAN_XBAR1_1 31 /* XBAR1 DMA 1 */ -#define IMXRT_DMACHAN_FLEXPWM1_RX0 32 /* FlexPWM1 RX sub-module0 capture */ -#define IMXRT_DMACHAN_FLEXPWM1_RX1 33 /* FlexPWM1 RX sub-module1 capture */ -#define IMXRT_DMACHAN_FLEXPWM1_RX2 34 /* FlexPWM1 RX sub-module2 capture */ -#define IMXRT_DMACHAN_FLEXPWM1_RX3 35 /* FlexPWM1 RX sub-module3 capture */ -#define IMXRT_DMACHAN_FLEXPWM1_TX0 36 /* FlexPWM1 TX sub-module0 value */ -#define IMXRT_DMACHAN_FLEXPWM1_TX1 37 /* FlexPWM1 TX sub-module1 value */ -#define IMXRT_DMACHAN_FLEXPWM1_TX2 38 /* FlexPWM1 TX sub-module2 value */ -#define IMXRT_DMACHAN_FLEXPWM1_TX3 39 /* FlexPWM1 TX sub-module3 value */ -#define IMXRT_DMACHAN_FLEXPWM3_RX0 40 /* FlexPWM3 RX sub-module0 capture */ -#define IMXRT_DMACHAN_FLEXPWM3_RX1 41 /* FlexPWM3 RX sub-module1 capture */ -#define IMXRT_DMACHAN_FLEXPWM3_RX2 42 /* FlexPWM3 RX sub-module2 capture */ -#define IMXRT_DMACHAN_FLEXPWM3_RX3 43 /* FlexPWM3 RX sub-module3 capture */ -#define IMXRT_DMACHAN_FLEXPWM3_TX0 44 /* FlexPWM3 TX sub-module0 value */ -#define IMXRT_DMACHAN_FLEXPWM3_TX1 45 /* FlexPWM3 TX sub-module1 value */ -#define IMXRT_DMACHAN_FLEXPWM3_TX2 46 /* FlexPWM3 TX sub-module2 value */ -#define IMXRT_DMACHAN_FLEXPWM3_TX3 47 /* FlexPWM3 TX sub-module3 value */ -#define IMXRT_DMACHAN_QTIMER1_RX0 48 /* QTimer1 RX capture timer 0 */ -#define IMXRT_DMACHAN_QTIMER1_RX1 49 /* QTimer1 RX capture timer 1 */ -#define IMXRT_DMACHAN_QTIMER1_RX2 50 /* QTimer1 RX capture timer 2 */ -#define IMXRT_DMACHAN_QTIMER1_RX3 51 /* QTimer1 RX capture timer 3 */ -#define IMXRT_DMACHAN_QTIMER1_TX0 52 /* QTimer1 TX cmpld1 timer 0 / cmld2 timer 1 */ -#define IMXRT_DMACHAN_QTIMER1_TX1 53 /* QTimer1 TX cmpld1 timer 1 / cmld2 timer 0 */ -#define IMXRT_DMACHAN_QTIMER1_TX2 54 /* QTimer1 TX cmpld1 timer 2 / cmld2 timer 3 */ -#define IMXRT_DMACHAN_QTIMER1_TX3 55 /* QTimer1 TX cmpld1 timer 3 / cmld2 timer 2 */ -#define IMXRT_DMACHAN_QTIMER3_RXTX0 56 /* QTimer1 RX capture timer 0 / TX cmpld1 timer 0 / cmld2 timer 1 */ -#define IMXRT_DMACHAN_QTIMER3_RXTX1 57 /* QTimer1 RX capture timer 1 / TX cmpld1 timer 1 / cmld2 timer 0 */ -#define IMXRT_DMACHAN_QTIMER3_RXTX2 58 /* QTimer1 RX capture timer 2 / TX cmpld1 timer 2 / cmld2 timer 3 */ -#define IMXRT_DMACHAN_QTIMER3_RXTX3 59 /* QTimer1 RX capture timer 3 / TX cmpld1 timer 3 / cmld2 timer 2 */ -#define IMXRT_DMACHAN_FLEXIO1_01 64 /* FlexIO1 DMA 0 / Async DMA 0 / DMA 1 / Async DMA 1 */ -#define IMXRT_DMACHAN_FLEXIO2_23 65 /* FlexIO1 DMA 2 / Async DMA 2 / DMA 3 / Async DMA 3 */ -#define IMXRT_DMACHAN_LPUART2_TX 66 /* LPUART2 TX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPUART2_RX 67 /* LPUART2 RX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPUART4_TX 68 /* LPUART4 TX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPUART4_RX 69 /* LPUART4 RX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPUART6_TX 70 /* LPUART6 TX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPUART6_RX 71 /* LPUART6 RX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPUART8_TX 72 /* LPUART8 TX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPUART8_RX 73 /* LPUART8 RX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_PXP 75 /* PXP DMA Event */ -#define IMXRT_DMACHAN_LCDIF 76 /* LCDIF DMA Event */ -#define IMXRT_DMACHAN_LPSPI2_RX 77 /* LPSPI2 RX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPSPI2_TX 78 /* LPSPI2 TX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPSPI4_RX 79 /* LPSPI4 RX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPSPI4_TX 80 /* LPSPI4 TX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPI2C2 81 /* LPI2C2 Master/Slave RX/TX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPI2C4 82 /* LPI2C4 Master/Slave RX/TX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_SAI3_RX 83 /* SAI3 RX FIFO DMA */ -#define IMXRT_DMACHAN_SAI3_TX 84 /* SAI3 RX FIFO DMA */ -#define IMXRT_DMACHAN_SPDIF_RX 85 /* SPDIF RX DMA */ -#define IMXRT_DMACHAN_SPDIF_TX 86 /* SPDIF TX DMA */ -#define IMXRT_DMACHAN_ADC2 88 /* ADC2 DMA */ -#define IMXRT_DMACHAN_ACMP3 89 /* ACMP3 DMA */ -#define IMXRT_DMACHAN_ACMP4 90 /* ACMP4 DMA */ -#define IMXRT_DMACHAN_ENET_0 92 /* ENET Timer DMA 0 */ -#define IMXRT_DMACHAN_ENET_1 93 /* ENET Timer DMA 1 */ -#define IMXRT_DMACHAN_XBAR1_2 94 /* XBAR1 DMA 2 */ -#define IMXRT_DMACHAN_XBAR1_3 95 /* XBAR1 DMA 3 */ -#define IMXRT_DMACHAN_FLEXPWM2_RX0 96 /* FlexPWM2 RX sub-module0 capture */ -#define IMXRT_DMACHAN_FLEXPWM2_RX1 97 /* FlexPWM2 RX sub-module1 capture */ -#define IMXRT_DMACHAN_FLEXPWM2_RX2 98 /* FlexPWM2 RX sub-module2 capture */ -#define IMXRT_DMACHAN_FLEXPWM2_RX3 99 /* FlexPWM2 RX sub-module3 capture */ -#define IMXRT_DMACHAN_FLEXPWM2_TX0 100 /* FlexPWM2 TX sub-module0 value */ -#define IMXRT_DMACHAN_FLEXPWM2_TX1 101 /* FlexPWM2 TX sub-module1 value */ -#define IMXRT_DMACHAN_FLEXPWM2_TX2 102 /* FlexPWM2 TX sub-module2 value */ -#define IMXRT_DMACHAN_FLEXPWM2_TX3 103 /* FlexPWM2 TX sub-module3 value */ -#define IMXRT_DMACHAN_FLEXPWM4_RX0 104 /* FlexPWM4 RX sub-module0 capture */ -#define IMXRT_DMACHAN_FLEXPWM4_RX1 105 /* FlexPWM4 RX sub-module1 capture */ -#define IMXRT_DMACHAN_FLEXPWM4_RX2 106 /* FlexPWM4 RX sub-module2 capture */ -#define IMXRT_DMACHAN_FLEXPWM4_RX3 107 /* FlexPWM4 RX sub-module3 capture */ -#define IMXRT_DMACHAN_FLEXPWM4_TX0 108 /* FlexPWM4 TX sub-module0 value */ -#define IMXRT_DMACHAN_FLEXPWM4_TX1 109 /* FlexPWM4 TX sub-module1 value */ -#define IMXRT_DMACHAN_FLEXPWM4_TX2 110 /* FlexPWM4 TX sub-module2 value */ -#define IMXRT_DMACHAN_FLEXPWM4_TX3 111 /* FlexPWM4 TX sub-module3 value */ -#define IMXRT_DMACHAN_QTIMER2_RX0 112 /* QTimer2 RX capture timer 0 */ -#define IMXRT_DMACHAN_QTIMER2_RX1 113 /* QTimer2 RX capture timer 1 */ -#define IMXRT_DMACHAN_QTIMER2_RX2 114 /* QTimer2 RX capture timer 2 */ -#define IMXRT_DMACHAN_QTIMER2_RX3 115 /* QTimer2 RX capture timer 3 */ -#define IMXRT_DMACHAN_QTIMER2_TX0 116 /* QTimer2 TX cmpld1 timer 0 / cmld2 timer 1 */ -#define IMXRT_DMACHAN_QTIMER2_TX1 117 /* QTimer2 TX cmpld1 timer 1 / cmld2 timer 0 */ -#define IMXRT_DMACHAN_QTIMER2_TX2 118 /* QTimer2 TX cmpld1 timer 2 / cmld2 timer 3 */ -#define IMXRT_DMACHAN_QTIMER2_TX3 119 /* QTimer2 TX cmpld1 timer 3 / cmld2 timer 2 */ -#define IMXRT_DMACHAN_QTIMER4_RXTX0 120 /* QTimer4 RX capture timer 0 / TX cmpld1 timer 0 / cmld2 timer 1 */ -#define IMXRT_DMACHAN_QTIMER4_RXTX1 121 /* QTimer4 RX capture timer 1 / TX cmpld1 timer 1 / cmld2 timer 0 */ -#define IMXRT_DMACHAN_QTIMER4_RXTX2 122 /* QTimer4 RX capture timer 2 / TX cmpld1 timer 2 / cmld2 timer 3 */ -#define IMXRT_DMACHAN_QTIMER4_RXTX3 123 /* QTimer4 RX capture timer 3 / TX cmpld1 timer 3 / cmld2 timer 2 */ - -#define IMXRT_DMA_NCHANNLES 128 /* Includes reserved channels */ - -#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_DMAMUX_H */ diff --git a/arch/arm/src/imxrt/chip/rt105x/imxrt105x_gpio.h b/arch/arm/src/imxrt/chip/rt105x/imxrt105x_gpio.h deleted file mode 100644 index 2970ac4224c..00000000000 --- a/arch/arm/src/imxrt/chip/rt105x/imxrt105x_gpio.h +++ /dev/null @@ -1,127 +0,0 @@ -/******************************************************************************************** - * arch/arm/src/imxrt/rt105x/imxrt105x_gpio.h - * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * David Sidrane - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ********************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_GPIO_H -#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_GPIO_H - -/******************************************************************************************** - * Included Files - ********************************************************************************************/ - -#include -#include "chip/imxrt_memorymap.h" - -/******************************************************************************************** - * Pre-processor Definitions - ********************************************************************************************/ - -/* Register offsets *************************************************************************/ - -#define IMXRT_GPIO_DR_OFFSET 0x0000 /* GPIO data register */ -#define IMXRT_GPIO_GDIR_OFFSET 0x0004 /* GPIO direction register */ -#define IMXRT_GPIO_PSR_OFFSET 0x0008 /* GPIO pad status register */ -#define IMXRT_GPIO_ICR1_OFFSET 0x000c /* GPIO interrupt configuration register1 */ -#define IMXRT_GPIO_ICR2_OFFSET 0x0010 /* GPIO interrupt configuration register2 */ -#define IMXRT_GPIO_IMR_OFFSET 0x0014 /* GPIO interrupt mask register */ -#define IMXRT_GPIO_ISR_OFFSET 0x0018 /* GPIO interrupt status register */ -#define IMXRT_GPIO_EDGE_OFFSET 0x001c /* GPIO edge select register */ -#define IMXRT_GPIO_SET_OFFSET 0x0084 /* GPIO data register SET */ -#define IMXRT_GPIO_CLEAR_OFFSET 0x0088 /* GPIO data register CLEAR */ -#define IMXRT_GPIO_TOGGLE_OFFSET 0x008c /* GPIO data register TOGGLE */ - -/* Register addresses ***********************************************************************/ - -#define IMXRT_GPIO1_DR (IMXRT_GPIO1_BASE + IMXRT_GPIO_DR_OFFSET) -#define IMXRT_GPIO1_GDIR (IMXRT_GPIO1_BASE + IMXRT_GPIO_GDIR_OFFSET) -#define IMXRT_GPIO1_PSR (IMXRT_GPIO1_BASE + IMXRT_GPIO_PSR_OFFSET) -#define IMXRT_GPIO1_ICR1 (IMXRT_GPIO1_BASE + IMXRT_GPIO_ICR1_OFFSET) -#define IMXRT_GPIO1_ICR2 (IMXRT_GPIO1_BASE + IMXRT_GPIO_ICR2_OFFSET) -#define IMXRT_GPIO1_IMR (IMXRT_GPIO1_BASE + IMXRT_GPIO_IMR_OFFSET) -#define IMXRT_GPIO1_ISR (IMXRT_GPIO1_BASE + IMXRT_GPIO_ISR_OFFSET) -#define IMXRT_GPIO1_EDGE (IMXRT_GPIO1_BASE + IMXRT_GPIO_EDGE_OFFSET) -#define IMXRT_GPIO1_SET (IMXRT_GPIO1_BASE + IMXRT_GPIO_SET_OFFSET) -#define IMXRT_GPIO1_CLEAR (IMXRT_GPIO1_BASE + IMXRT_GPIO_CLEAR_OFFSET) -#define IMXRT_GPIO1_TOGGLE (IMXRT_GPIO1_BASE + IMXRT_GPIO_TOGGLE_OFFSET) - -#define IMXRT_GPIO2_DR (IMXRT_GPIO2_BASE + IMXRT_GPIO_DR_OFFSET) -#define IMXRT_GPIO2_GDIR (IMXRT_GPIO2_BASE + IMXRT_GPIO_GDIR_OFFSET) -#define IMXRT_GPIO2_PSR (IMXRT_GPIO2_BASE + IMXRT_GPIO_PSR_OFFSET) -#define IMXRT_GPIO2_ICR1 (IMXRT_GPIO2_BASE + IMXRT_GPIO_ICR1_OFFSET) -#define IMXRT_GPIO2_ICR2 (IMXRT_GPIO2_BASE + IMXRT_GPIO_ICR2_OFFSET) -#define IMXRT_GPIO2_IMR (IMXRT_GPIO2_BASE + IMXRT_GPIO_IMR_OFFSET) -#define IMXRT_GPIO2_ISR (IMXRT_GPIO2_BASE + IMXRT_GPIO_ISR_OFFSET) -#define IMXRT_GPIO2_EDGE (IMXRT_GPIO2_BASE + IMXRT_GPIO_EDGE_OFFSET) -#define IMXRT_GPIO2_SET (IMXRT_GPIO2_BASE + IMXRT_GPIO_SET_OFFSET) -#define IMXRT_GPIO2_CLEAR (IMXRT_GPIO2_BASE + IMXRT_GPIO_CLEAR_OFFSET) -#define IMXRT_GPIO2_TOGGLE (IMXRT_GPIO2_BASE + IMXRT_GPIO_TOGGLE_OFFSET) - -#define IMXRT_GPIO3_DR (IMXRT_GPIO3_BASE + IMXRT_GPIO_DR_OFFSET) -#define IMXRT_GPIO3_GDIR (IMXRT_GPIO3_BASE + IMXRT_GPIO_GDIR_OFFSET) -#define IMXRT_GPIO3_PSR (IMXRT_GPIO3_BASE + IMXRT_GPIO_PSR_OFFSET) -#define IMXRT_GPIO3_ICR1 (IMXRT_GPIO3_BASE + IMXRT_GPIO_ICR1_OFFSET) -#define IMXRT_GPIO3_ICR2 (IMXRT_GPIO3_BASE + IMXRT_GPIO_ICR2_OFFSET) -#define IMXRT_GPIO3_IMR (IMXRT_GPIO3_BASE + IMXRT_GPIO_IMR_OFFSET) -#define IMXRT_GPIO3_ISR (IMXRT_GPIO3_BASE + IMXRT_GPIO_ISR_OFFSET) -#define IMXRT_GPIO3_EDGE (IMXRT_GPIO3_BASE + IMXRT_GPIO_EDGE_OFFSET) -#define IMXRT_GPIO3_SET (IMXRT_GPIO3_BASE + IMXRT_GPIO_SET_OFFSET) -#define IMXRT_GPIO3_CLEAR (IMXRT_GPIO3_BASE + IMXRT_GPIO_CLEAR_OFFSET) -#define IMXRT_GPIO3_TOGGLE (IMXRT_GPIO3_BASE + IMXRT_GPIO_TOGGLE_OFFSET) - -#define IMXRT_GPIO4_DR (IMXRT_GPIO4_BASE + IMXRT_GPIO_DR_OFFSET) -#define IMXRT_GPIO4_GDIR (IMXRT_GPIO4_BASE + IMXRT_GPIO_GDIR_OFFSET) -#define IMXRT_GPIO4_PSR (IMXRT_GPIO4_BASE + IMXRT_GPIO_PSR_OFFSET) -#define IMXRT_GPIO4_ICR1 (IMXRT_GPIO4_BASE + IMXRT_GPIO_ICR1_OFFSET) -#define IMXRT_GPIO4_ICR2 (IMXRT_GPIO4_BASE + IMXRT_GPIO_ICR2_OFFSET) -#define IMXRT_GPIO4_IMR (IMXRT_GPIO4_BASE + IMXRT_GPIO_IMR_OFFSET) -#define IMXRT_GPIO4_ISR (IMXRT_GPIO4_BASE + IMXRT_GPIO_ISR_OFFSET) -#define IMXRT_GPIO4_EDGE (IMXRT_GPIO4_BASE + IMXRT_GPIO_EDGE_OFFSET) -#define IMXRT_GPIO4_SET (IMXRT_GPIO4_BASE + IMXRT_GPIO_SET_OFFSET) -#define IMXRT_GPIO4_CLEAR (IMXRT_GPIO4_BASE + IMXRT_GPIO_CLEAR_OFFSET) -#define IMXRT_GPIO4_TOGGLE (IMXRT_GPIO4_BASE + IMXRT_GPIO_TOGGLE_OFFSET) - -#define IMXRT_GPIO5_DR (IMXRT_GPIO5_BASE + IMXRT_GPIO_DR_OFFSET) -#define IMXRT_GPIO5_GDIR (IMXRT_GPIO5_BASE + IMXRT_GPIO_GDIR_OFFSET) -#define IMXRT_GPIO5_PSR (IMXRT_GPIO5_BASE + IMXRT_GPIO_PSR_OFFSET) -#define IMXRT_GPIO5_ICR1 (IMXRT_GPIO5_BASE + IMXRT_GPIO_ICR1_OFFSET) -#define IMXRT_GPIO5_ICR2 (IMXRT_GPIO5_BASE + IMXRT_GPIO_ICR2_OFFSET) -#define IMXRT_GPIO5_IMR (IMXRT_GPIO5_BASE + IMXRT_GPIO_IMR_OFFSET) -#define IMXRT_GPIO5_ISR (IMXRT_GPIO5_BASE + IMXRT_GPIO_ISR_OFFSET) -#define IMXRT_GPIO5_EDGE (IMXRT_GPIO5_BASE + IMXRT_GPIO_EDGE_OFFSET) -#define IMXRT_GPIO5_SET (IMXRT_GPIO5_BASE + IMXRT_GPIO_SET_OFFSET) -#define IMXRT_GPIO5_CLEAR (IMXRT_GPIO5_BASE + IMXRT_GPIO_CLEAR_OFFSET) -#define IMXRT_GPIO5_TOGGLE (IMXRT_GPIO5_BASE + IMXRT_GPIO_TOGGLE_OFFSET) - -#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_GPIO_H */ diff --git a/arch/arm/src/imxrt/chip/rt105x/imxrt105x_iomuxc.h b/arch/arm/src/imxrt/chip/rt105x/imxrt105x_iomuxc.h deleted file mode 100644 index 6666f7a3f8e..00000000000 --- a/arch/arm/src/imxrt/chip/rt105x/imxrt105x_iomuxc.h +++ /dev/null @@ -1,1994 +0,0 @@ -/************************************************************************************ - * arch/arm/src/imxrt/rt105x/imxrt105x_iomuxc.h - * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * David Sidrane - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_IOMUXC_H -#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_IOMUXC_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include -#include "chip/imxrt_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ - -#define IMXRT_IOMUXC_GPR_GPR0_OFFSET 0x0000 /* GPR0 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR1_OFFSET 0x0004 /* GPR1 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR2_OFFSET 0x0008 /* GPR2 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR3_OFFSET 0x000c /* GPR3 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR4_OFFSET 0x0010 /* GPR4 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR5_OFFSET 0x0014 /* GPR5 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR6_OFFSET 0x0018 /* GPR6 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR7_OFFSET 0x001c /* GPR7 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR8_OFFSET 0x0020 /* GPR8 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR9_OFFSET 0x0024 /* GPR9 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR10_OFFSET 0x0028 /* GPR10 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR11_OFFSET 0x002c /* GPR11 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR12_OFFSET 0x0030 /* GPR12 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR13_OFFSET 0x0034 /* GPR13 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR14_OFFSET 0x0038 /* GPR14 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR15_OFFSET 0x003c /* GPR15 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR16_OFFSET 0x0040 /* GPR16 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR17_OFFSET 0x0044 /* GPR17 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR18_OFFSET 0x0048 /* GPR18 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR19_OFFSET 0x004c /* GPR19 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR20_OFFSET 0x0050 /* GPR20 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR21_OFFSET 0x0054 /* GPR21 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR22_OFFSET 0x0058 /* GPR22 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR23_OFFSET 0x005c /* GPR23 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR24_OFFSET 0x0060 /* GPR24 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR25_OFFSET 0x0064 /* GPR25 General Purpose Register*/ - -#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_OFFSET 0x0000 /* SW_MUX_CTL_PAD_WAKEUP SW MUX Control Register */ -#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_OFFSET 0x0004 /* SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register */ -#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_OFFSET 0x0008 /* SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register */ -#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_OFFSET 0x000c /* SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register */ -#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_OFFSET 0x0010 /* SW_PAD_CTL_PAD_POR_B SW PAD Control Register */ -#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_OFFSET 0x0014 /* SW_PAD_CTL_PAD_ONOFF SW PAD Control Register */ -#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_OFFSET 0x0018 /* SW_PAD_CTL_PAD_WAKEUP SW PAD Control Register */ -#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_OFFSET 0x001c /* SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register */ -#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_OFFSET 0x0020 /* SW_PAD_CTL_PAD_PMIC_STBY_REQ SW PAD Control Register */ - -#define IMXRT_IOMUXC_SNVS_GPR_GPR0_OFFSET 0x0000 /* SNVC GPR0 General Purpose Register */ -#define IMXRT_IOMUXC_SNVS_GPR_GPR1_OFFSET 0x0004 /* SNVC GPR1 General Purpose Register */ -#define IMXRT_IOMUXC_SNVS_GPR_GPR2_OFFSET 0x0008 /* SNVC GPR2 General Purpose Register */ -#define IMXRT_IOMUXC_SNVS_GPR_GPR3_OFFSET 0x000c /* SNVC GPR3 General Purpose Register */ - -/* Pad Mux Registers */ -/* Pad Mux Register Indices (used by software for table lookups) */ - -#define IMXRT_PADMUX_GPIO_EMC_00_INDEX 0 -#define IMXRT_PADMUX_GPIO_EMC_01_INDEX 1 -#define IMXRT_PADMUX_GPIO_EMC_02_INDEX 2 -#define IMXRT_PADMUX_GPIO_EMC_03_INDEX 3 -#define IMXRT_PADMUX_GPIO_EMC_04_INDEX 4 -#define IMXRT_PADMUX_GPIO_EMC_05_INDEX 5 -#define IMXRT_PADMUX_GPIO_EMC_06_INDEX 6 -#define IMXRT_PADMUX_GPIO_EMC_07_INDEX 7 -#define IMXRT_PADMUX_GPIO_EMC_08_INDEX 8 -#define IMXRT_PADMUX_GPIO_EMC_09_INDEX 9 -#define IMXRT_PADMUX_GPIO_EMC_10_INDEX 10 -#define IMXRT_PADMUX_GPIO_EMC_11_INDEX 11 -#define IMXRT_PADMUX_GPIO_EMC_12_INDEX 12 -#define IMXRT_PADMUX_GPIO_EMC_13_INDEX 13 -#define IMXRT_PADMUX_GPIO_EMC_14_INDEX 14 -#define IMXRT_PADMUX_GPIO_EMC_15_INDEX 15 -#define IMXRT_PADMUX_GPIO_EMC_16_INDEX 16 -#define IMXRT_PADMUX_GPIO_EMC_17_INDEX 17 -#define IMXRT_PADMUX_GPIO_EMC_18_INDEX 18 -#define IMXRT_PADMUX_GPIO_EMC_19_INDEX 19 -#define IMXRT_PADMUX_GPIO_EMC_20_INDEX 20 -#define IMXRT_PADMUX_GPIO_EMC_21_INDEX 21 -#define IMXRT_PADMUX_GPIO_EMC_22_INDEX 22 -#define IMXRT_PADMUX_GPIO_EMC_23_INDEX 23 -#define IMXRT_PADMUX_GPIO_EMC_24_INDEX 24 -#define IMXRT_PADMUX_GPIO_EMC_25_INDEX 25 -#define IMXRT_PADMUX_GPIO_EMC_26_INDEX 26 -#define IMXRT_PADMUX_GPIO_EMC_27_INDEX 27 -#define IMXRT_PADMUX_GPIO_EMC_28_INDEX 28 -#define IMXRT_PADMUX_GPIO_EMC_29_INDEX 29 -#define IMXRT_PADMUX_GPIO_EMC_30_INDEX 30 -#define IMXRT_PADMUX_GPIO_EMC_31_INDEX 31 -#define IMXRT_PADMUX_GPIO_EMC_32_INDEX 32 -#define IMXRT_PADMUX_GPIO_EMC_33_INDEX 33 -#define IMXRT_PADMUX_GPIO_EMC_34_INDEX 34 -#define IMXRT_PADMUX_GPIO_EMC_35_INDEX 35 -#define IMXRT_PADMUX_GPIO_EMC_36_INDEX 36 -#define IMXRT_PADMUX_GPIO_EMC_37_INDEX 37 -#define IMXRT_PADMUX_GPIO_EMC_38_INDEX 38 -#define IMXRT_PADMUX_GPIO_EMC_39_INDEX 39 -#define IMXRT_PADMUX_GPIO_EMC_40_INDEX 40 -#define IMXRT_PADMUX_GPIO_EMC_41_INDEX 41 -#define IMXRT_PADMUX_GPIO_AD_B0_00_INDEX 42 -#define IMXRT_PADMUX_GPIO_AD_B0_01_INDEX 43 -#define IMXRT_PADMUX_GPIO_AD_B0_02_INDEX 44 -#define IMXRT_PADMUX_GPIO_AD_B0_03_INDEX 45 -#define IMXRT_PADMUX_GPIO_AD_B0_04_INDEX 46 -#define IMXRT_PADMUX_GPIO_AD_B0_05_INDEX 47 -#define IMXRT_PADMUX_GPIO_AD_B0_06_INDEX 48 -#define IMXRT_PADMUX_GPIO_AD_B0_07_INDEX 49 -#define IMXRT_PADMUX_GPIO_AD_B0_08_INDEX 50 -#define IMXRT_PADMUX_GPIO_AD_B0_09_INDEX 51 -#define IMXRT_PADMUX_GPIO_AD_B0_10_INDEX 52 -#define IMXRT_PADMUX_GPIO_AD_B0_11_INDEX 53 -#define IMXRT_PADMUX_GPIO_AD_B0_12_INDEX 54 -#define IMXRT_PADMUX_GPIO_AD_B0_13_INDEX 55 -#define IMXRT_PADMUX_GPIO_AD_B0_14_INDEX 56 -#define IMXRT_PADMUX_GPIO_AD_B0_15_INDEX 57 -#define IMXRT_PADMUX_GPIO_AD_B1_00_INDEX 58 -#define IMXRT_PADMUX_GPIO_AD_B1_01_INDEX 59 -#define IMXRT_PADMUX_GPIO_AD_B1_02_INDEX 60 -#define IMXRT_PADMUX_GPIO_AD_B1_03_INDEX 61 -#define IMXRT_PADMUX_GPIO_AD_B1_04_INDEX 62 -#define IMXRT_PADMUX_GPIO_AD_B1_05_INDEX 63 -#define IMXRT_PADMUX_GPIO_AD_B1_06_INDEX 64 -#define IMXRT_PADMUX_GPIO_AD_B1_07_INDEX 65 -#define IMXRT_PADMUX_GPIO_AD_B1_08_INDEX 66 -#define IMXRT_PADMUX_GPIO_AD_B1_09_INDEX 67 -#define IMXRT_PADMUX_GPIO_AD_B1_10_INDEX 68 -#define IMXRT_PADMUX_GPIO_AD_B1_11_INDEX 69 -#define IMXRT_PADMUX_GPIO_AD_B1_12_INDEX 70 -#define IMXRT_PADMUX_GPIO_AD_B1_13_INDEX 71 -#define IMXRT_PADMUX_GPIO_AD_B1_14_INDEX 72 -#define IMXRT_PADMUX_GPIO_AD_B1_15_INDEX 73 -#define IMXRT_PADMUX_GPIO_B0_00_INDEX 74 -#define IMXRT_PADMUX_GPIO_B0_01_INDEX 75 -#define IMXRT_PADMUX_GPIO_B0_02_INDEX 76 -#define IMXRT_PADMUX_GPIO_B0_03_INDEX 77 -#define IMXRT_PADMUX_GPIO_B0_04_INDEX 78 -#define IMXRT_PADMUX_GPIO_B0_05_INDEX 79 -#define IMXRT_PADMUX_GPIO_B0_06_INDEX 80 -#define IMXRT_PADMUX_GPIO_B0_07_INDEX 81 -#define IMXRT_PADMUX_GPIO_B0_08_INDEX 82 -#define IMXRT_PADMUX_GPIO_B0_09_INDEX 83 -#define IMXRT_PADMUX_GPIO_B0_10_INDEX 84 -#define IMXRT_PADMUX_GPIO_B0_11_INDEX 85 -#define IMXRT_PADMUX_GPIO_B0_12_INDEX 86 -#define IMXRT_PADMUX_GPIO_B0_13_INDEX 87 -#define IMXRT_PADMUX_GPIO_B0_14_INDEX 88 -#define IMXRT_PADMUX_GPIO_B0_15_INDEX 89 -#define IMXRT_PADMUX_GPIO_B1_00_INDEX 90 -#define IMXRT_PADMUX_GPIO_B1_01_INDEX 91 -#define IMXRT_PADMUX_GPIO_B1_02_INDEX 92 -#define IMXRT_PADMUX_GPIO_B1_03_INDEX 93 -#define IMXRT_PADMUX_GPIO_B1_04_INDEX 94 -#define IMXRT_PADMUX_GPIO_B1_05_INDEX 95 -#define IMXRT_PADMUX_GPIO_B1_06_INDEX 96 -#define IMXRT_PADMUX_GPIO_B1_07_INDEX 97 -#define IMXRT_PADMUX_GPIO_B1_08_INDEX 98 -#define IMXRT_PADMUX_GPIO_B1_09_INDEX 99 -#define IMXRT_PADMUX_GPIO_B1_10_INDEX 100 -#define IMXRT_PADMUX_GPIO_B1_11_INDEX 101 -#define IMXRT_PADMUX_GPIO_B1_12_INDEX 102 -#define IMXRT_PADMUX_GPIO_B1_13_INDEX 103 -#define IMXRT_PADMUX_GPIO_B1_14_INDEX 104 -#define IMXRT_PADMUX_GPIO_B1_15_INDEX 105 -#define IMXRT_PADMUX_GPIO_SD_B0_00_INDEX 106 -#define IMXRT_PADMUX_GPIO_SD_B0_01_INDEX 107 -#define IMXRT_PADMUX_GPIO_SD_B0_02_INDEX 108 -#define IMXRT_PADMUX_GPIO_SD_B0_03_INDEX 109 -#define IMXRT_PADMUX_GPIO_SD_B0_04_INDEX 110 -#define IMXRT_PADMUX_GPIO_SD_B0_05_INDEX 111 -#define IMXRT_PADMUX_GPIO_SD_B1_00_INDEX 112 -#define IMXRT_PADMUX_GPIO_SD_B1_01_INDEX 113 -#define IMXRT_PADMUX_GPIO_SD_B1_02_INDEX 114 -#define IMXRT_PADMUX_GPIO_SD_B1_03_INDEX 115 -#define IMXRT_PADMUX_GPIO_SD_B1_04_INDEX 116 -#define IMXRT_PADMUX_GPIO_SD_B1_05_INDEX 117 -#define IMXRT_PADMUX_GPIO_SD_B1_06_INDEX 118 -#define IMXRT_PADMUX_GPIO_SD_B1_07_INDEX 119 -#define IMXRT_PADMUX_GPIO_SD_B1_08_INDEX 120 -#define IMXRT_PADMUX_GPIO_SD_B1_09_INDEX 121 -#define IMXRT_PADMUX_GPIO_SD_B1_10_INDEX 122 -#define IMXRT_PADMUX_GPIO_SD_B1_11_INDEX 123 - -#define IMXRT_PADMUX_WAKEUP_INDEX 124 -#define IMXRT_PADMUX_PMIC_ON_REQ_INDEX 125 -#define IMXRT_PADMUX_PMIC_STBY_REQ_INDEX 126 - -#define IMXRT_PADMUX_NREGISTERS 127 - -/* Pad Mux Register Offsets */ - -#define IMXRT_PADMUX_OFFSET(n) (0x0014 + ((unsigned int)(n) << 2)) -#define IMXRT_PADMUX_OFFSET_SNVS(n) ((unsigned int)(n) << 2) - -#define IMXRT_PADMUX_GPIO_EMC_00_OFFSET 0x0014 -#define IMXRT_PADMUX_GPIO_EMC_01_OFFSET 0x0018 -#define IMXRT_PADMUX_GPIO_EMC_02_OFFSET 0x001c -#define IMXRT_PADMUX_GPIO_EMC_03_OFFSET 0x0020 -#define IMXRT_PADMUX_GPIO_EMC_04_OFFSET 0x0024 -#define IMXRT_PADMUX_GPIO_EMC_05_OFFSET 0x0028 -#define IMXRT_PADMUX_GPIO_EMC_06_OFFSET 0x002c -#define IMXRT_PADMUX_GPIO_EMC_07_OFFSET 0x0030 -#define IMXRT_PADMUX_GPIO_EMC_08_OFFSET 0x0034 -#define IMXRT_PADMUX_GPIO_EMC_09_OFFSET 0x0038 -#define IMXRT_PADMUX_GPIO_EMC_10_OFFSET 0x003c -#define IMXRT_PADMUX_GPIO_EMC_11_OFFSET 0x0040 -#define IMXRT_PADMUX_GPIO_EMC_12_OFFSET 0x0044 -#define IMXRT_PADMUX_GPIO_EMC_13_OFFSET 0x0048 -#define IMXRT_PADMUX_GPIO_EMC_14_OFFSET 0x004c -#define IMXRT_PADMUX_GPIO_EMC_15_OFFSET 0x0050 -#define IMXRT_PADMUX_GPIO_EMC_16_OFFSET 0x0054 -#define IMXRT_PADMUX_GPIO_EMC_17_OFFSET 0x0058 -#define IMXRT_PADMUX_GPIO_EMC_18_OFFSET 0x005c -#define IMXRT_PADMUX_GPIO_EMC_19_OFFSET 0x0060 -#define IMXRT_PADMUX_GPIO_EMC_20_OFFSET 0x0064 -#define IMXRT_PADMUX_GPIO_EMC_21_OFFSET 0x0068 -#define IMXRT_PADMUX_GPIO_EMC_22_OFFSET 0x006c -#define IMXRT_PADMUX_GPIO_EMC_23_OFFSET 0x0070 -#define IMXRT_PADMUX_GPIO_EMC_24_OFFSET 0x0074 -#define IMXRT_PADMUX_GPIO_EMC_25_OFFSET 0x0078 -#define IMXRT_PADMUX_GPIO_EMC_26_OFFSET 0x007c -#define IMXRT_PADMUX_GPIO_EMC_27_OFFSET 0x0080 -#define IMXRT_PADMUX_GPIO_EMC_28_OFFSET 0x0084 -#define IMXRT_PADMUX_GPIO_EMC_29_OFFSET 0x0088 -#define IMXRT_PADMUX_GPIO_EMC_30_OFFSET 0x008c -#define IMXRT_PADMUX_GPIO_EMC_31_OFFSET 0x0090 -#define IMXRT_PADMUX_GPIO_EMC_32_OFFSET 0x0094 -#define IMXRT_PADMUX_GPIO_EMC_33_OFFSET 0x0098 -#define IMXRT_PADMUX_GPIO_EMC_34_OFFSET 0x009c -#define IMXRT_PADMUX_GPIO_EMC_35_OFFSET 0x00a0 -#define IMXRT_PADMUX_GPIO_EMC_36_OFFSET 0x00a4 -#define IMXRT_PADMUX_GPIO_EMC_37_OFFSET 0x00a8 -#define IMXRT_PADMUX_GPIO_EMC_38_OFFSET 0x00ac -#define IMXRT_PADMUX_GPIO_EMC_39_OFFSET 0x00b0 -#define IMXRT_PADMUX_GPIO_EMC_40_OFFSET 0x00b4 -#define IMXRT_PADMUX_GPIO_EMC_41_OFFSET 0x00b8 -#define IMXRT_PADMUX_GPIO_AD_B0_00_OFFSET 0x00bc -#define IMXRT_PADMUX_GPIO_AD_B0_01_OFFSET 0x00c0 -#define IMXRT_PADMUX_GPIO_AD_B0_02_OFFSET 0x00c4 -#define IMXRT_PADMUX_GPIO_AD_B0_03_OFFSET 0x00c8 -#define IMXRT_PADMUX_GPIO_AD_B0_04_OFFSET 0x00cc -#define IMXRT_PADMUX_GPIO_AD_B0_05_OFFSET 0x00d0 -#define IMXRT_PADMUX_GPIO_AD_B0_06_OFFSET 0x00d4 -#define IMXRT_PADMUX_GPIO_AD_B0_07_OFFSET 0x00d8 -#define IMXRT_PADMUX_GPIO_AD_B0_08_OFFSET 0x00dc -#define IMXRT_PADMUX_GPIO_AD_B0_09_OFFSET 0x00e0 -#define IMXRT_PADMUX_GPIO_AD_B0_10_OFFSET 0x00e4 -#define IMXRT_PADMUX_GPIO_AD_B0_11_OFFSET 0x00e8 -#define IMXRT_PADMUX_GPIO_AD_B0_12_OFFSET 0x00ec -#define IMXRT_PADMUX_GPIO_AD_B0_13_OFFSET 0x00f0 -#define IMXRT_PADMUX_GPIO_AD_B0_14_OFFSET 0x00f4 -#define IMXRT_PADMUX_GPIO_AD_B0_15_OFFSET 0x00f8 -#define IMXRT_PADMUX_GPIO_AD_B1_00_OFFSET 0x00fc -#define IMXRT_PADMUX_GPIO_AD_B1_01_OFFSET 0x0100 -#define IMXRT_PADMUX_GPIO_AD_B1_02_OFFSET 0x0104 -#define IMXRT_PADMUX_GPIO_AD_B1_03_OFFSET 0x0108 -#define IMXRT_PADMUX_GPIO_AD_B1_04_OFFSET 0x010c -#define IMXRT_PADMUX_GPIO_AD_B1_05_OFFSET 0x0110 -#define IMXRT_PADMUX_GPIO_AD_B1_06_OFFSET 0x0114 -#define IMXRT_PADMUX_GPIO_AD_B1_07_OFFSET 0x0118 -#define IMXRT_PADMUX_GPIO_AD_B1_08_OFFSET 0x011c -#define IMXRT_PADMUX_GPIO_AD_B1_09_OFFSET 0x0120 -#define IMXRT_PADMUX_GPIO_AD_B1_10_OFFSET 0x0124 -#define IMXRT_PADMUX_GPIO_AD_B1_11_OFFSET 0x0128 -#define IMXRT_PADMUX_GPIO_AD_B1_12_OFFSET 0x012c -#define IMXRT_PADMUX_GPIO_AD_B1_13_OFFSET 0x0130 -#define IMXRT_PADMUX_GPIO_AD_B1_14_OFFSET 0x0134 -#define IMXRT_PADMUX_GPIO_AD_B1_15_OFFSET 0x0138 -#define IMXRT_PADMUX_GPIO_B0_00_OFFSET 0x013c -#define IMXRT_PADMUX_GPIO_B0_01_OFFSET 0x0140 -#define IMXRT_PADMUX_GPIO_B0_02_OFFSET 0x0144 -#define IMXRT_PADMUX_GPIO_B0_03_OFFSET 0x0148 -#define IMXRT_PADMUX_GPIO_B0_04_OFFSET 0x014c -#define IMXRT_PADMUX_GPIO_B0_05_OFFSET 0x0150 -#define IMXRT_PADMUX_GPIO_B0_06_OFFSET 0x0154 -#define IMXRT_PADMUX_GPIO_B0_07_OFFSET 0x0158 -#define IMXRT_PADMUX_GPIO_B0_08_OFFSET 0x015c -#define IMXRT_PADMUX_GPIO_B0_09_OFFSET 0x0160 -#define IMXRT_PADMUX_GPIO_B0_10_OFFSET 0x0164 -#define IMXRT_PADMUX_GPIO_B0_11_OFFSET 0x0168 -#define IMXRT_PADMUX_GPIO_B0_12_OFFSET 0x016c -#define IMXRT_PADMUX_GPIO_B0_13_OFFSET 0x0170 -#define IMXRT_PADMUX_GPIO_B0_14_OFFSET 0x0174 -#define IMXRT_PADMUX_GPIO_B0_15_OFFSET 0x0178 -#define IMXRT_PADMUX_GPIO_B1_00_OFFSET 0x017c -#define IMXRT_PADMUX_GPIO_B1_01_OFFSET 0x0180 -#define IMXRT_PADMUX_GPIO_B1_02_OFFSET 0x0184 -#define IMXRT_PADMUX_GPIO_B1_03_OFFSET 0x0188 -#define IMXRT_PADMUX_GPIO_B1_04_OFFSET 0x018c -#define IMXRT_PADMUX_GPIO_B1_05_OFFSET 0x0190 -#define IMXRT_PADMUX_GPIO_B1_06_OFFSET 0x0194 -#define IMXRT_PADMUX_GPIO_B1_07_OFFSET 0x0198 -#define IMXRT_PADMUX_GPIO_B1_08_OFFSET 0x019c -#define IMXRT_PADMUX_GPIO_B1_09_OFFSET 0x01a0 -#define IMXRT_PADMUX_GPIO_B1_10_OFFSET 0x01a4 -#define IMXRT_PADMUX_GPIO_B1_11_OFFSET 0x01a8 -#define IMXRT_PADMUX_GPIO_B1_12_OFFSET 0x01ac -#define IMXRT_PADMUX_GPIO_B1_13_OFFSET 0x01b0 -#define IMXRT_PADMUX_GPIO_B1_14_OFFSET 0x01b4 -#define IMXRT_PADMUX_GPIO_B1_15_OFFSET 0x01b8 -#define IMXRT_PADMUX_GPIO_SD_B0_00_OFFSET 0x01bc -#define IMXRT_PADMUX_GPIO_SD_B0_01_OFFSET 0x01c0 -#define IMXRT_PADMUX_GPIO_SD_B0_02_OFFSET 0x01c4 -#define IMXRT_PADMUX_GPIO_SD_B0_03_OFFSET 0x01c8 -#define IMXRT_PADMUX_GPIO_SD_B0_04_OFFSET 0x01cc -#define IMXRT_PADMUX_GPIO_SD_B0_05_OFFSET 0x01d0 -#define IMXRT_PADMUX_GPIO_SD_B1_00_OFFSET 0x01d4 -#define IMXRT_PADMUX_GPIO_SD_B1_01_OFFSET 0x01d8 -#define IMXRT_PADMUX_GPIO_SD_B1_02_OFFSET 0x01dc -#define IMXRT_PADMUX_GPIO_SD_B1_03_OFFSET 0x01e0 -#define IMXRT_PADMUX_GPIO_SD_B1_04_OFFSET 0x01e4 -#define IMXRT_PADMUX_GPIO_SD_B1_05_OFFSET 0x01e8 -#define IMXRT_PADMUX_GPIO_SD_B1_06_OFFSET 0x01ec -#define IMXRT_PADMUX_GPIO_SD_B1_07_OFFSET 0x01f0 -#define IMXRT_PADMUX_GPIO_SD_B1_08_OFFSET 0x01f4 -#define IMXRT_PADMUX_GPIO_SD_B1_09_OFFSET 0x01f8 -#define IMXRT_PADMUX_GPIO_SD_B1_10_OFFSET 0x01fc -#define IMXRT_PADMUX_GPIO_SD_B1_11_OFFSET 0x0200 - -/* Pad Control Registers - * Pad Control Register Indices (used by software for table lookups) - */ - -#define IMXRT_PADCTL_GPIO_EMC_00_INDEX 0 -#define IMXRT_PADCTL_GPIO_EMC_01_INDEX 1 -#define IMXRT_PADCTL_GPIO_EMC_02_INDEX 2 -#define IMXRT_PADCTL_GPIO_EMC_03_INDEX 3 -#define IMXRT_PADCTL_GPIO_EMC_04_INDEX 4 -#define IMXRT_PADCTL_GPIO_EMC_05_INDEX 5 -#define IMXRT_PADCTL_GPIO_EMC_06_INDEX 6 -#define IMXRT_PADCTL_GPIO_EMC_07_INDEX 7 -#define IMXRT_PADCTL_GPIO_EMC_08_INDEX 8 -#define IMXRT_PADCTL_GPIO_EMC_09_INDEX 9 -#define IMXRT_PADCTL_GPIO_EMC_10_INDEX 10 -#define IMXRT_PADCTL_GPIO_EMC_11_INDEX 11 -#define IMXRT_PADCTL_GPIO_EMC_12_INDEX 12 -#define IMXRT_PADCTL_GPIO_EMC_13_INDEX 13 -#define IMXRT_PADCTL_GPIO_EMC_14_INDEX 14 -#define IMXRT_PADCTL_GPIO_EMC_15_INDEX 15 -#define IMXRT_PADCTL_GPIO_EMC_16_INDEX 16 -#define IMXRT_PADCTL_GPIO_EMC_17_INDEX 17 -#define IMXRT_PADCTL_GPIO_EMC_18_INDEX 18 -#define IMXRT_PADCTL_GPIO_EMC_19_INDEX 19 -#define IMXRT_PADCTL_GPIO_EMC_20_INDEX 20 -#define IMXRT_PADCTL_GPIO_EMC_21_INDEX 21 -#define IMXRT_PADCTL_GPIO_EMC_22_INDEX 22 -#define IMXRT_PADCTL_GPIO_EMC_23_INDEX 23 -#define IMXRT_PADCTL_GPIO_EMC_24_INDEX 24 -#define IMXRT_PADCTL_GPIO_EMC_25_INDEX 25 -#define IMXRT_PADCTL_GPIO_EMC_26_INDEX 26 -#define IMXRT_PADCTL_GPIO_EMC_27_INDEX 27 -#define IMXRT_PADCTL_GPIO_EMC_28_INDEX 28 -#define IMXRT_PADCTL_GPIO_EMC_29_INDEX 29 -#define IMXRT_PADCTL_GPIO_EMC_30_INDEX 30 -#define IMXRT_PADCTL_GPIO_EMC_31_INDEX 31 -#define IMXRT_PADCTL_GPIO_EMC_32_INDEX 32 -#define IMXRT_PADCTL_GPIO_EMC_33_INDEX 33 -#define IMXRT_PADCTL_GPIO_EMC_34_INDEX 34 -#define IMXRT_PADCTL_GPIO_EMC_35_INDEX 35 -#define IMXRT_PADCTL_GPIO_EMC_36_INDEX 36 -#define IMXRT_PADCTL_GPIO_EMC_37_INDEX 37 -#define IMXRT_PADCTL_GPIO_EMC_38_INDEX 38 -#define IMXRT_PADCTL_GPIO_EMC_39_INDEX 39 -#define IMXRT_PADCTL_GPIO_EMC_40_INDEX 40 -#define IMXRT_PADCTL_GPIO_EMC_41_INDEX 41 -#define IMXRT_PADCTL_GPIO_AD_B0_00_INDEX 42 -#define IMXRT_PADCTL_GPIO_AD_B0_01_INDEX 43 -#define IMXRT_PADCTL_GPIO_AD_B0_02_INDEX 44 -#define IMXRT_PADCTL_GPIO_AD_B0_03_INDEX 45 -#define IMXRT_PADCTL_GPIO_AD_B0_04_INDEX 46 -#define IMXRT_PADCTL_GPIO_AD_B0_05_INDEX 47 -#define IMXRT_PADCTL_GPIO_AD_B0_06_INDEX 48 -#define IMXRT_PADCTL_GPIO_AD_B0_07_INDEX 49 -#define IMXRT_PADCTL_GPIO_AD_B0_08_INDEX 50 -#define IMXRT_PADCTL_GPIO_AD_B0_09_INDEX 51 -#define IMXRT_PADCTL_GPIO_AD_B0_10_INDEX 52 -#define IMXRT_PADCTL_GPIO_AD_B0_11_INDEX 53 -#define IMXRT_PADCTL_GPIO_AD_B0_12_INDEX 54 -#define IMXRT_PADCTL_GPIO_AD_B0_13_INDEX 55 -#define IMXRT_PADCTL_GPIO_AD_B0_14_INDEX 56 -#define IMXRT_PADCTL_GPIO_AD_B0_15_INDEX 57 -#define IMXRT_PADCTL_GPIO_AD_B1_00_INDEX 58 -#define IMXRT_PADCTL_GPIO_AD_B1_01_INDEX 59 -#define IMXRT_PADCTL_GPIO_AD_B1_02_INDEX 60 -#define IMXRT_PADCTL_GPIO_AD_B1_03_INDEX 61 -#define IMXRT_PADCTL_GPIO_AD_B1_04_INDEX 62 -#define IMXRT_PADCTL_GPIO_AD_B1_05_INDEX 63 -#define IMXRT_PADCTL_GPIO_AD_B1_06_INDEX 64 -#define IMXRT_PADCTL_GPIO_AD_B1_07_INDEX 65 -#define IMXRT_PADCTL_GPIO_AD_B1_08_INDEX 66 -#define IMXRT_PADCTL_GPIO_AD_B1_09_INDEX 67 -#define IMXRT_PADCTL_GPIO_AD_B1_10_INDEX 68 -#define IMXRT_PADCTL_GPIO_AD_B1_11_INDEX 69 -#define IMXRT_PADCTL_GPIO_AD_B1_12_INDEX 70 -#define IMXRT_PADCTL_GPIO_AD_B1_13_INDEX 71 -#define IMXRT_PADCTL_GPIO_AD_B1_14_INDEX 72 -#define IMXRT_PADCTL_GPIO_AD_B1_15_INDEX 73 -#define IMXRT_PADCTL_GPIO_B0_00_INDEX 74 -#define IMXRT_PADCTL_GPIO_B0_01_INDEX 75 -#define IMXRT_PADCTL_GPIO_B0_02_INDEX 76 -#define IMXRT_PADCTL_GPIO_B0_03_INDEX 77 -#define IMXRT_PADCTL_GPIO_B0_04_INDEX 78 -#define IMXRT_PADCTL_GPIO_B0_05_INDEX 79 -#define IMXRT_PADCTL_GPIO_B0_06_INDEX 80 -#define IMXRT_PADCTL_GPIO_B0_07_INDEX 81 -#define IMXRT_PADCTL_GPIO_B0_08_INDEX 82 -#define IMXRT_PADCTL_GPIO_B0_09_INDEX 83 -#define IMXRT_PADCTL_GPIO_B0_10_INDEX 84 -#define IMXRT_PADCTL_GPIO_B0_11_INDEX 85 -#define IMXRT_PADCTL_GPIO_B0_12_INDEX 86 -#define IMXRT_PADCTL_GPIO_B0_13_INDEX 87 -#define IMXRT_PADCTL_GPIO_B0_14_INDEX 88 -#define IMXRT_PADCTL_GPIO_B0_15_INDEX 89 -#define IMXRT_PADCTL_GPIO_B1_00_INDEX 90 -#define IMXRT_PADCTL_GPIO_B1_01_INDEX 91 -#define IMXRT_PADCTL_GPIO_B1_02_INDEX 92 -#define IMXRT_PADCTL_GPIO_B1_03_INDEX 93 -#define IMXRT_PADCTL_GPIO_B1_04_INDEX 94 -#define IMXRT_PADCTL_GPIO_B1_05_INDEX 95 -#define IMXRT_PADCTL_GPIO_B1_06_INDEX 96 -#define IMXRT_PADCTL_GPIO_B1_07_INDEX 97 -#define IMXRT_PADCTL_GPIO_B1_08_INDEX 98 -#define IMXRT_PADCTL_GPIO_B1_09_INDEX 99 -#define IMXRT_PADCTL_GPIO_B1_10_INDEX 100 -#define IMXRT_PADCTL_GPIO_B1_11_INDEX 101 -#define IMXRT_PADCTL_GPIO_B1_12_INDEX 102 -#define IMXRT_PADCTL_GPIO_B1_13_INDEX 103 -#define IMXRT_PADCTL_GPIO_B1_14_INDEX 104 -#define IMXRT_PADCTL_GPIO_B1_15_INDEX 105 -#define IMXRT_PADCTL_GPIO_SD_B0_00_INDEX 106 -#define IMXRT_PADCTL_GPIO_SD_B0_01_INDEX 107 -#define IMXRT_PADCTL_GPIO_SD_B0_02_INDEX 108 -#define IMXRT_PADCTL_GPIO_SD_B0_03_INDEX 109 -#define IMXRT_PADCTL_GPIO_SD_B0_04_INDEX 110 -#define IMXRT_PADCTL_GPIO_SD_B0_05_INDEX 111 -#define IMXRT_PADCTL_GPIO_SD_B1_00_INDEX 112 -#define IMXRT_PADCTL_GPIO_SD_B1_01_INDEX 113 -#define IMXRT_PADCTL_GPIO_SD_B1_02_INDEX 114 -#define IMXRT_PADCTL_GPIO_SD_B1_03_INDEX 115 -#define IMXRT_PADCTL_GPIO_SD_B1_04_INDEX 116 -#define IMXRT_PADCTL_GPIO_SD_B1_05_INDEX 117 -#define IMXRT_PADCTL_GPIO_SD_B1_06_INDEX 118 -#define IMXRT_PADCTL_GPIO_SD_B1_07_INDEX 119 -#define IMXRT_PADCTL_GPIO_SD_B1_08_INDEX 120 -#define IMXRT_PADCTL_GPIO_SD_B1_09_INDEX 121 -#define IMXRT_PADCTL_GPIO_SD_B1_10_INDEX 122 -#define IMXRT_PADCTL_GPIO_SD_B1_11_INDEX 123 - -#define IMXRT_PADCTL_WAKEUP_INDEX 124 -#define IMXRT_PADCTL_PMIC_ON_REQ_INDEX 125 -#define IMXRT_PADCTL_PMIC_STBY_REQ_INDEX 126 - -#define IMXRT_PADCTL_NREGISTERS 127 - -/* Pad Control Register Offsets */ - -#define IMXRT_PADCTL_OFFSET(n) (0x0204 + ((unsigned int)(n) << 2)) -#define IMXRT_PADCTL_OFFSET_SNVS(n) (0x18 + ((unsigned int)(n) << 2)) - -#define IMXRT_PADCTL_GPIO_EMC_00_OFFSET 0x0204 -#define IMXRT_PADCTL_GPIO_EMC_01_OFFSET 0x0208 -#define IMXRT_PADCTL_GPIO_EMC_02_OFFSET 0x020c -#define IMXRT_PADCTL_GPIO_EMC_03_OFFSET 0x0210 -#define IMXRT_PADCTL_GPIO_EMC_04_OFFSET 0x0214 -#define IMXRT_PADCTL_GPIO_EMC_05_OFFSET 0x0218 -#define IMXRT_PADCTL_GPIO_EMC_06_OFFSET 0x021c -#define IMXRT_PADCTL_GPIO_EMC_07_OFFSET 0x0220 -#define IMXRT_PADCTL_GPIO_EMC_08_OFFSET 0x0224 -#define IMXRT_PADCTL_GPIO_EMC_09_OFFSET 0x0228 -#define IMXRT_PADCTL_GPIO_EMC_10_OFFSET 0x022c -#define IMXRT_PADCTL_GPIO_EMC_11_OFFSET 0x0230 -#define IMXRT_PADCTL_GPIO_EMC_12_OFFSET 0x0234 -#define IMXRT_PADCTL_GPIO_EMC_13_OFFSET 0x0238 -#define IMXRT_PADCTL_GPIO_EMC_14_OFFSET 0x023c -#define IMXRT_PADCTL_GPIO_EMC_15_OFFSET 0x0240 -#define IMXRT_PADCTL_GPIO_EMC_16_OFFSET 0x0244 -#define IMXRT_PADCTL_GPIO_EMC_17_OFFSET 0x0248 -#define IMXRT_PADCTL_GPIO_EMC_18_OFFSET 0x024c -#define IMXRT_PADCTL_GPIO_EMC_19_OFFSET 0x0250 -#define IMXRT_PADCTL_GPIO_EMC_20_OFFSET 0x0254 -#define IMXRT_PADCTL_GPIO_EMC_21_OFFSET 0x0258 -#define IMXRT_PADCTL_GPIO_EMC_22_OFFSET 0x025c -#define IMXRT_PADCTL_GPIO_EMC_23_OFFSET 0x0260 -#define IMXRT_PADCTL_GPIO_EMC_24_OFFSET 0x0264 -#define IMXRT_PADCTL_GPIO_EMC_25_OFFSET 0x0268 -#define IMXRT_PADCTL_GPIO_EMC_26_OFFSET 0x026c -#define IMXRT_PADCTL_GPIO_EMC_27_OFFSET 0x0270 -#define IMXRT_PADCTL_GPIO_EMC_28_OFFSET 0x0274 -#define IMXRT_PADCTL_GPIO_EMC_29_OFFSET 0x0278 -#define IMXRT_PADCTL_GPIO_EMC_30_OFFSET 0x027c -#define IMXRT_PADCTL_GPIO_EMC_31_OFFSET 0x0280 -#define IMXRT_PADCTL_GPIO_EMC_32_OFFSET 0x0284 -#define IMXRT_PADCTL_GPIO_EMC_33_OFFSET 0x0288 -#define IMXRT_PADCTL_GPIO_EMC_34_OFFSET 0x028c -#define IMXRT_PADCTL_GPIO_EMC_35_OFFSET 0x0290 -#define IMXRT_PADCTL_GPIO_EMC_36_OFFSET 0x0294 -#define IMXRT_PADCTL_GPIO_EMC_37_OFFSET 0x0298 -#define IMXRT_PADCTL_GPIO_EMC_38_OFFSET 0x029c -#define IMXRT_PADCTL_GPIO_EMC_39_OFFSET 0x02a0 -#define IMXRT_PADCTL_GPIO_EMC_40_OFFSET 0x02a4 -#define IMXRT_PADCTL_GPIO_EMC_41_OFFSET 0x02a8 -#define IMXRT_PADCTL_GPIO_AD_B0_00_OFFSET 0x02ac -#define IMXRT_PADCTL_GPIO_AD_B0_01_OFFSET 0x02b0 -#define IMXRT_PADCTL_GPIO_AD_B0_02_OFFSET 0x02b4 -#define IMXRT_PADCTL_GPIO_AD_B0_03_OFFSET 0x02b8 -#define IMXRT_PADCTL_GPIO_AD_B0_04_OFFSET 0x02bc -#define IMXRT_PADCTL_GPIO_AD_B0_05_OFFSET 0x02c0 -#define IMXRT_PADCTL_GPIO_AD_B0_06_OFFSET 0x02c4 -#define IMXRT_PADCTL_GPIO_AD_B0_07_OFFSET 0x02c8 -#define IMXRT_PADCTL_GPIO_AD_B0_08_OFFSET 0x02cc -#define IMXRT_PADCTL_GPIO_AD_B0_09_OFFSET 0x02d0 -#define IMXRT_PADCTL_GPIO_AD_B0_10_OFFSET 0x02d4 -#define IMXRT_PADCTL_GPIO_AD_B0_11_OFFSET 0x02d8 -#define IMXRT_PADCTL_GPIO_AD_B0_12_OFFSET 0x02dc -#define IMXRT_PADCTL_GPIO_AD_B0_13_OFFSET 0x02e0 -#define IMXRT_PADCTL_GPIO_AD_B0_14_OFFSET 0x02e4 -#define IMXRT_PADCTL_GPIO_AD_B0_15_OFFSET 0x02e8 -#define IMXRT_PADCTL_GPIO_AD_B1_00_OFFSET 0x02ec -#define IMXRT_PADCTL_GPIO_AD_B1_01_OFFSET 0x02f0 -#define IMXRT_PADCTL_GPIO_AD_B1_02_OFFSET 0x02f4 -#define IMXRT_PADCTL_GPIO_AD_B1_03_OFFSET 0x02f8 -#define IMXRT_PADCTL_GPIO_AD_B1_04_OFFSET 0x02fc -#define IMXRT_PADCTL_GPIO_AD_B1_05_OFFSET 0x0300 -#define IMXRT_PADCTL_GPIO_AD_B1_06_OFFSET 0x0304 -#define IMXRT_PADCTL_GPIO_AD_B1_07_OFFSET 0x0308 -#define IMXRT_PADCTL_GPIO_AD_B1_08_OFFSET 0x030c -#define IMXRT_PADCTL_GPIO_AD_B1_09_OFFSET 0x0310 -#define IMXRT_PADCTL_GPIO_AD_B1_10_OFFSET 0x0314 -#define IMXRT_PADCTL_GPIO_AD_B1_11_OFFSET 0x0318 -#define IMXRT_PADCTL_GPIO_AD_B1_12_OFFSET 0x031c -#define IMXRT_PADCTL_GPIO_AD_B1_13_OFFSET 0x0320 -#define IMXRT_PADCTL_GPIO_AD_B1_14_OFFSET 0x0324 -#define IMXRT_PADCTL_GPIO_AD_B1_15_OFFSET 0x0328 -#define IMXRT_PADCTL_GPIO_B0_00_OFFSET 0x032c -#define IMXRT_PADCTL_GPIO_B0_01_OFFSET 0x0330 -#define IMXRT_PADCTL_GPIO_B0_02_OFFSET 0x0334 -#define IMXRT_PADCTL_GPIO_B0_03_OFFSET 0x0338 -#define IMXRT_PADCTL_GPIO_B0_04_OFFSET 0x033c -#define IMXRT_PADCTL_GPIO_B0_05_OFFSET 0x0340 -#define IMXRT_PADCTL_GPIO_B0_06_OFFSET 0x0344 -#define IMXRT_PADCTL_GPIO_B0_07_OFFSET 0x0348 -#define IMXRT_PADCTL_GPIO_B0_08_OFFSET 0x034c -#define IMXRT_PADCTL_GPIO_B0_09_OFFSET 0x0350 -#define IMXRT_PADCTL_GPIO_B0_10_OFFSET 0x0354 -#define IMXRT_PADCTL_GPIO_B0_11_OFFSET 0x0358 -#define IMXRT_PADCTL_GPIO_B0_12_OFFSET 0x035c -#define IMXRT_PADCTL_GPIO_B0_13_OFFSET 0x0360 -#define IMXRT_PADCTL_GPIO_B0_14_OFFSET 0x0364 -#define IMXRT_PADCTL_GPIO_B0_15_OFFSET 0x0368 -#define IMXRT_PADCTL_GPIO_B1_00_OFFSET 0x036c -#define IMXRT_PADCTL_GPIO_B1_01_OFFSET 0x0370 -#define IMXRT_PADCTL_GPIO_B1_02_OFFSET 0x0374 -#define IMXRT_PADCTL_GPIO_B1_03_OFFSET 0x0378 -#define IMXRT_PADCTL_GPIO_B1_04_OFFSET 0x037c -#define IMXRT_PADCTL_GPIO_B1_05_OFFSET 0x0380 -#define IMXRT_PADCTL_GPIO_B1_06_OFFSET 0x0384 -#define IMXRT_PADCTL_GPIO_B1_07_OFFSET 0x0388 -#define IMXRT_PADCTL_GPIO_B1_08_OFFSET 0x038c -#define IMXRT_PADCTL_GPIO_B1_09_OFFSET 0x0390 -#define IMXRT_PADCTL_GPIO_B1_10_OFFSET 0x0394 -#define IMXRT_PADCTL_GPIO_B1_11_OFFSET 0x0398 -#define IMXRT_PADCTL_GPIO_B1_12_OFFSET 0x039c -#define IMXRT_PADCTL_GPIO_B1_13_OFFSET 0x03a0 -#define IMXRT_PADCTL_GPIO_B1_14_OFFSET 0x03a4 -#define IMXRT_PADCTL_GPIO_B1_15_OFFSET 0x03a8 -#define IMXRT_PADCTL_GPIO_SD_B0_00_OFFSET 0x03ac -#define IMXRT_PADCTL_GPIO_SD_B0_01_OFFSET 0x03b0 -#define IMXRT_PADCTL_GPIO_SD_B0_02_OFFSET 0x03b4 -#define IMXRT_PADCTL_GPIO_SD_B0_03_OFFSET 0x03b8 -#define IMXRT_PADCTL_GPIO_SD_B0_04_OFFSET 0x03bc -#define IMXRT_PADCTL_GPIO_SD_B0_05_OFFSET 0x03c0 -#define IMXRT_PADCTL_GPIO_SD_B1_00_OFFSET 0x03c4 -#define IMXRT_PADCTL_GPIO_SD_B1_01_OFFSET 0x03c8 -#define IMXRT_PADCTL_GPIO_SD_B1_02_OFFSET 0x03cc -#define IMXRT_PADCTL_GPIO_SD_B1_03_OFFSET 0x03d0 -#define IMXRT_PADCTL_GPIO_SD_B1_04_OFFSET 0x03d4 -#define IMXRT_PADCTL_GPIO_SD_B1_05_OFFSET 0x03d8 -#define IMXRT_PADCTL_GPIO_SD_B1_06_OFFSET 0x03dc -#define IMXRT_PADCTL_GPIO_SD_B1_07_OFFSET 0x03e0 -#define IMXRT_PADCTL_GPIO_SD_B1_08_OFFSET 0x03e4 -#define IMXRT_PADCTL_GPIO_SD_B1_09_OFFSET 0x03e8 -#define IMXRT_PADCTL_GPIO_SD_B1_10_OFFSET 0x03ec -#define IMXRT_PADCTL_GPIO_SD_B1_11_OFFSET 0x03f0 - -/* Select Input Daisy Register Offsets */ - -#define IMXRT_INPUT_INDEX2OFFSET(n) (0x03f4 + ((unsigned int)(n) << 2)) -#define IMXRT_INPUT_OFFSET2INDEX(o) (((unsigned int)(o) - 0x03f4) >> 2) - -#define IMXRT_INPUT_ANATOP_USB_OTG1_ID_OFFSET 0x03f4 -#define IMXRT_INPUT_ANATOP_USB_OTG2_ID_OFFSET 0x03f8 -#define IMXRT_INPUT_CCM_PMIC_READY_OFFSET 0x03fc -#define IMXRT_INPUT_CSI_DATA02_OFFSET 0x0400 -#define IMXRT_INPUT_CSI_DATA03_OFFSET 0x0404 -#define IMXRT_INPUT_CSI_DATA04_OFFSET 0x0408 -#define IMXRT_INPUT_CSI_DATA05_OFFSET 0x040c -#define IMXRT_INPUT_CSI_DATA06_OFFSET 0x0410 -#define IMXRT_INPUT_CSI_DATA07_OFFSET 0x0414 -#define IMXRT_INPUT_CSI_DATA08_OFFSET 0x0418 -#define IMXRT_INPUT_CSI_DATA09_OFFSET 0x041c -#define IMXRT_INPUT_CSI_HSYNC_OFFSET 0x0420 -#define IMXRT_INPUT_CSI_PIXCLK_OFFSET 0x0424 -#define IMXRT_INPUT_CSI_VSYNC_OFFSET 0x0428 -#define IMXRT_INPUT_ENET_IPG_CLK_RMII_OFFSET 0x042c -#define IMXRT_INPUT_ENET_MDIO_OFFSET 0x0430 -#define IMXRT_INPUT_ENET0_RXDATA_OFFSET 0x0434 -#define IMXRT_INPUT_ENET1_RXDATA_OFFSET 0x0438 -#define IMXRT_INPUT_ENET_RXEN_OFFSET 0x043c -#define IMXRT_INPUT_ENET_RXERR_OFFSET 0x0440 -#define IMXRT_INPUT_ENET0_TIMER_OFFSET 0x0444 -#define IMXRT_INPUT_ENET_TXCLK_OFFSET 0x0448 -#define IMXRT_INPUT_FLEXCAN1_RX_OFFSET 0x044c -#define IMXRT_INPUT_FLEXCAN2_RX_OFFSET 0x0450 -#define IMXRT_INPUT_FLEXPWM1_PWMA3_OFFSET 0x0454 -#define IMXRT_INPUT_FLEXPWM1_PWMA0_OFFSET 0x0458 -#define IMXRT_INPUT_FLEXPWM1_PWMA1_OFFSET 0x045c -#define IMXRT_INPUT_FLEXPWM1_PWMA2_OFFSET 0x0460 -#define IMXRT_INPUT_FLEXPWM1_PWMB3_OFFSET 0x0464 -#define IMXRT_INPUT_FLEXPWM1_PWMB0_OFFSET 0x0468 -#define IMXRT_INPUT_FLEXPWM1_PWMB1_OFFSET 0x046c -#define IMXRT_INPUT_FLEXPWM1_PWMB2_OFFSET 0x0470 -#define IMXRT_INPUT_FLEXPWM2_PWMA3_OFFSET 0x0474 -#define IMXRT_INPUT_FLEXPWM2_PWMA0_OFFSET 0x0478 -#define IMXRT_INPUT_FLEXPWM2_PWMA1_OFFSET 0x047c -#define IMXRT_INPUT_FLEXPWM2_PWMA2_OFFSET 0x0480 -#define IMXRT_INPUT_FLEXPWM2_PWMB3_OFFSET 0x0484 -#define IMXRT_INPUT_FLEXPWM2_PWMB0_OFFSET 0x0488 -#define IMXRT_INPUT_FLEXPWM2_PWMB1_OFFSET 0x048c -#define IMXRT_INPUT_FLEXPWM2_PWMB2_OFFSET 0x0490 -#define IMXRT_INPUT_FLEXPWM4_PWMA0_OFFSET 0x0494 -#define IMXRT_INPUT_FLEXPWM4_PWMA1_OFFSET 0x0498 -#define IMXRT_INPUT_FLEXPWM4_PWMA2_OFFSET 0x049c -#define IMXRT_INPUT_FLEXPWM4_PWMA3_OFFSET 0x04a0 -#define IMXRT_INPUT_FLEXSPIA_DQS_OFFSET 0x04a4 -#define IMXRT_INPUT_FLEXSPIA_DATA0_OFFSET 0x04a8 -#define IMXRT_INPUT_FLEXSPIA_DATA1_OFFSET 0x04ac -#define IMXRT_INPUT_FLEXSPIA_DATA2_OFFSET 0x04b0 -#define IMXRT_INPUT_FLEXSPIA_DATA3_OFFSET 0x04b4 -#define IMXRT_INPUT_FLEXSPIB_DATA0_OFFSET 0x04b8 -#define IMXRT_INPUT_FLEXSPIB_DATA1_OFFSET 0x04bc -#define IMXRT_INPUT_FLEXSPIB_DATA2_OFFSET 0x04c0 -#define IMXRT_INPUT_FLEXSPIB_DATA3_OFFSET 0x04c4 -#define IMXRT_INPUT_FLEXSPIA_SCK_OFFSET 0x04c8 -#define IMXRT_INPUT_LPI2C1_SCL_OFFSET 0x04cc -#define IMXRT_INPUT_LPI2C1_SDA_OFFSET 0x04d0 -#define IMXRT_INPUT_LPI2C2_SCL_OFFSET 0x04d4 -#define IMXRT_INPUT_LPI2C2_SDA_OFFSET 0x04d8 -#define IMXRT_INPUT_LPI2C3_SCL_OFFSET 0x04dc -#define IMXRT_INPUT_LPI2C3_SDA_OFFSET 0x04e0 -#define IMXRT_INPUT_LPI2C4_SCL_OFFSET 0x04e4 -#define IMXRT_INPUT_LPI2C4_SDA_OFFSET 0x04e8 -#define IMXRT_INPUT_LPSPI1_PCS0_OFFSET 0x04ec -#define IMXRT_INPUT_LPSPI1_SCK_OFFSET 0x04f0 -#define IMXRT_INPUT_LPSPI1_SDI_OFFSET 0x04f4 -#define IMXRT_INPUT_LPSPI1_SDO_OFFSET 0x04f8 -#define IMXRT_INPUT_LPSPI2_PCS0_OFFSET 0x04fc -#define IMXRT_INPUT_LPSPI2_SCK_OFFSET 0x0500 -#define IMXRT_INPUT_LPSPI2_SDI_OFFSET 0x0504 -#define IMXRT_INPUT_LPSPI2_SDO_OFFSET 0x0508 -#define IMXRT_INPUT_LPSPI3_PCS0_OFFSET 0x050c -#define IMXRT_INPUT_LPSPI3_SCK_OFFSET 0x0510 -#define IMXRT_INPUT_LPSPI3_SDI_OFFSET 0x0514 -#define IMXRT_INPUT_LPSPI3_SDO_OFFSET 0x0518 -#define IMXRT_INPUT_LPSPI4_PCS0_OFFSET 0x051c -#define IMXRT_INPUT_LPSPI4_SCK_OFFSET 0x0520 -#define IMXRT_INPUT_LPSPI4_SDI_OFFSET 0x0524 -#define IMXRT_INPUT_LPSPI4_SDO_OFFSET 0x0528 -#define IMXRT_INPUT_LPUART2_RX_OFFSET 0x052c -#define IMXRT_INPUT_LPUART2_TX_OFFSET 0x0530 -#define IMXRT_INPUT_LPUART3_CTS_B_OFFSET 0x0534 -#define IMXRT_INPUT_LPUART3_RX_OFFSET 0x0538 -#define IMXRT_INPUT_LPUART3_TX_OFFSET 0x053c -#define IMXRT_INPUT_LPUART4_RX_OFFSET 0x0540 -#define IMXRT_INPUT_LPUART4_TX_OFFSET 0x0544 -#define IMXRT_INPUT_LPUART5_RX_OFFSET 0x0548 -#define IMXRT_INPUT_LPUART5_TX_OFFSET 0x054c -#define IMXRT_INPUT_LPUART6_RX_OFFSET 0x0550 -#define IMXRT_INPUT_LPUART6_TX_OFFSET 0x0554 -#define IMXRT_INPUT_LPUART7_RX_OFFSET 0x0558 -#define IMXRT_INPUT_LPUART7_TX_OFFSET 0x055c -#define IMXRT_INPUT_LPUART8_RX_OFFSET 0x0560 -#define IMXRT_INPUT_LPUART8_TX_OFFSET 0x0564 -#define IMXRT_INPUT_NMI_GLUE_NMI_OFFSET 0x0568 -#define IMXRT_INPUT_QTIMER2_TIMER0_OFFSET 0x056c -#define IMXRT_INPUT_QTIMER2_TIMER1_OFFSET 0x0570 -#define IMXRT_INPUT_QTIMER2_TIMER2_OFFSET 0x0574 -#define IMXRT_INPUT_QTIMER2_TIMER3_OFFSET 0x0578 -#define IMXRT_INPUT_QTIMER3_TIMER0_OFFSET 0x057c -#define IMXRT_INPUT_QTIMER3_TIMER1_OFFSET 0x0580 -#define IMXRT_INPUT_QTIMER3_TIMER2_OFFSET 0x0584 -#define IMXRT_INPUT_QTIMER3_TIMER3_OFFSET 0x0588 -#define IMXRT_INPUT_SAI1_MCLK2_OFFSET 0x058c -#define IMXRT_INPUT_SAI1_RX_BCLK_OFFSET 0x0590 -#define IMXRT_INPUT_SAI1_RX_DATA0_OFFSET 0x0594 -#define IMXRT_INPUT_SAI1_RX_DATA1_OFFSET 0x0598 -#define IMXRT_INPUT_SAI1_RX_DATA2_OFFSET 0x059c -#define IMXRT_INPUT_SAI1_RX_DATA3_OFFSET 0x05a0 -#define IMXRT_INPUT_SAI1_RX_SYNC_OFFSET 0x05a4 -#define IMXRT_INPUT_SAI1_TX_BCLK_OFFSET 0x05a8 -#define IMXRT_INPUT_SAI1_TX_SYNC_OFFSET 0x05ac -#define IMXRT_INPUT_SAI2_MCLK2_OFFSET 0x05b0 -#define IMXRT_INPUT_SAI2_RX_BCLK_OFFSET 0x05b4 -#define IMXRT_INPUT_SAI2_RX_DATA0_OFFSET 0x05b8 -#define IMXRT_INPUT_SAI2_RX_SYNC_OFFSET 0x05bc -#define IMXRT_INPUT_SAI2_TX_BCLK_OFFSET 0x05c0 -#define IMXRT_INPUT_SAI2_TX_SYNC_OFFSET 0x05c4 -#define IMXRT_INPUT_SPDIF_IN_OFFSET 0x05c8 -#define IMXRT_INPUT_USB_OTG2_OC_OFFSET 0x05cc -#define IMXRT_INPUT_USB_OTG1_OC_OFFSET 0x05d0 -#define IMXRT_INPUT_USDHC1_CD_B_OFFSET 0x05d4 -#define IMXRT_INPUT_USDHC1_WP_OFFSET 0x05d8 -#define IMXRT_INPUT_USDHC2_CLK_OFFSET 0x05dc -#define IMXRT_INPUT_USDHC2_CD_B_OFFSET 0x05e0 -#define IMXRT_INPUT_USDHC2_CMD_OFFSET 0x05e4 -#define IMXRT_INPUT_USDHC2_DATA0_OFFSET 0x05e8 -#define IMXRT_INPUT_USDHC2_DATA1_OFFSET 0x05ec -#define IMXRT_INPUT_USDHC2_DATA2_OFFSET 0x05f0 -#define IMXRT_INPUT_USDHC2_DATA3_OFFSET 0x05f4 -#define IMXRT_INPUT_USDHC2_DATA4_OFFSET 0x05f8 -#define IMXRT_INPUT_USDHC2_DATA5_OFFSET 0x05fc -#define IMXRT_INPUT_USDHC2_DATA6_OFFSET 0x0600 -#define IMXRT_INPUT_USDHC2_DATA7_OFFSET 0x0604 -#define IMXRT_INPUT_USDHC2_WP_OFFSET 0x0608 -#define IMXRT_INPUT_XBAR1_IN02_OFFSET 0x060c -#define IMXRT_INPUT_XBAR1_IN03_OFFSET 0x0610 -#define IMXRT_INPUT_XBAR1_IN04_OFFSET 0x0614 -#define IMXRT_INPUT_XBAR1_IN05_OFFSET 0x0618 -#define IMXRT_INPUT_XBAR1_IN06_OFFSET 0x061c -#define IMXRT_INPUT_XBAR1_IN07_OFFSET 0x0620 -#define IMXRT_INPUT_XBAR1_IN08_OFFSET 0x0624 -#define IMXRT_INPUT_XBAR1_IN09_OFFSET 0x0628 -#define IMXRT_INPUT_XBAR1_IN17_OFFSET 0x062c -#define IMXRT_INPUT_XBAR1_IN18_OFFSET 0x0630 -#define IMXRT_INPUT_XBAR1_IN20_OFFSET 0x0634 -#define IMXRT_INPUT_XBAR1_IN22_OFFSET 0x0638 -#define IMXRT_INPUT_XBAR1_IN23_OFFSET 0x063c -#define IMXRT_INPUT_XBAR1_IN24_OFFSET 0x0640 -#define IMXRT_INPUT_XBAR1_IN14_OFFSET 0x0644 -#define IMXRT_INPUT_XBAR1_IN15_OFFSET 0x0648 -#define IMXRT_INPUT_XBAR1_IN16_OFFSET 0x064c -#define IMXRT_INPUT_XBAR1_IN25_OFFSET 0x0650 -#define IMXRT_INPUT_XBAR1_IN19_OFFSET 0x0654 -#define IMXRT_INPUT_XBAR1_IN21_OFFSET 0x0658 - -/* Register addresses ***************************************************************/ - -#define IMXRT_IOMUXC_GPR_GPR0 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR0_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR1 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR1_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR2 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR2_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR3 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR3_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR4 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR4_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR5 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR5_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR6 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR6_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR7 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR7_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR8 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR8_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR9 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR9_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR10 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR10_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR11 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR11_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR12 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR12_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR13 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR13_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR14 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR14_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR15 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR15_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR16 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR16_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR17 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR17_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR18 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR18_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR19 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR19_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR20 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR20_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR21 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR21_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR22 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR22_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR23 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR23_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR24 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR24_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR25 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR25_OFFSET) - -#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_OFFSET) -#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_OFFSET) -#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_OFFSET) -#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_OFFSET) -#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_OFFSET) -#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_OFFSET) -#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_OFFSET) -#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_OFFSET) -#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_OFFSET) - -#define IMXRT_IOMUXC_SNVS_GPR_GPR0 (IMXRT_IOMUXCSNVSGPR_BASE + IMXRT_IOMUXC_SNVS_GPR_GPR0_OFFSET) -#define IMXRT_IOMUXC_SNVS_GPR_GPR1 (IMXRT_IOMUXCSNVSGPR_BASE + IMXRT_IOMUXC_SNVS_GPR_GPR1_OFFSET) -#define IMXRT_IOMUXC_SNVS_GPR_GPR2 (IMXRT_IOMUXCSNVSGPR_BASE + IMXRT_IOMUXC_SNVS_GPR_GPR2_OFFSET) -#define IMXRT_IOMUXC_SNVS_GPR_GPR3 (IMXRT_IOMUXCSNVSGPR_BASE + IMXRT_IOMUXC_SNVS_GPR_GPR3_OFFSET) - -/* Pad Mux Registers */ - -#define IMXRT_PADMUX_ADDRESS(n) (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_OFFSET(n)) -#define IMXRT_PADMUX_ADDRESS_SNVS(n) (IMXRT_IOMUXCSNVS_BASE + IMXRT_PADMUX_OFFSET_SNVS(n)) - -#define IMXRT_PADMUX_GPIO_EMC_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_00_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_01_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_02_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_03_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_04_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_05_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_06_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_07 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_07_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_08 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_08_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_09 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_09_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_10 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_10_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_11 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_11_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_12 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_12_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_13 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_13_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_14 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_14_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_15 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_15_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_16 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_16_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_17 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_17_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_18 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_18_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_19 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_19_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_20 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_20_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_21 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_21_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_22 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_22_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_23 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_23_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_24 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_24_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_25 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_25_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_26 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_26_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_27 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_27_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_28 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_28_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_29 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_29_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_30 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_30_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_31 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_31_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_32 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_32_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_33 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_33_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_34 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_34_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_35 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_35_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_36 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_36_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_37 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_37_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_38 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_38_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_39 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_39_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_40 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_40_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_41 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_41_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_00_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_01_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_02_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_03_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_04_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_05_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_06_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_07 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_07_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_08 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_08_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_09 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_09_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_10 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_10_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_11 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_11_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_12 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_12_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_13 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_13_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_14 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_14_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_15 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_15_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_00_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_01_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_02_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_03_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_04_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_05_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_06_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_07 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_07_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_08 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_08_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_09 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_09_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_10 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_10_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_11 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_11_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_12 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_12_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_13 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_13_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_14 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_14_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_15 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_15_OFFSET) -#define IMXRT_PADMUX_GPIO_B0_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_00_OFFSET) -#define IMXRT_PADMUX_GPIO_B0_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_01_OFFSET) -#define IMXRT_PADMUX_GPIO_B0_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_02_OFFSET) -#define IMXRT_PADMUX_GPIO_B0_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_03_OFFSET) -#define IMXRT_PADMUX_GPIO_B0_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_04_OFFSET) -#define IMXRT_PADMUX_GPIO_B0_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_05_OFFSET) -#define IMXRT_PADMUX_GPIO_B0_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_06_OFFSET) -#define IMXRT_PADMUX_GPIO_B0_07 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_07_OFFSET) -#define IMXRT_PADMUX_GPIO_B0_08 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_08_OFFSET) -#define IMXRT_PADMUX_GPIO_B0_09 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_09_OFFSET) -#define IMXRT_PADMUX_GPIO_B0_10 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_10_OFFSET) -#define IMXRT_PADMUX_GPIO_B0_11 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_11_OFFSET) -#define IMXRT_PADMUX_GPIO_B0_12 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_12_OFFSET) -#define IMXRT_PADMUX_GPIO_B0_13 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_13_OFFSET) -#define IMXRT_PADMUX_GPIO_B0_14 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_14_OFFSET) -#define IMXRT_PADMUX_GPIO_B0_15 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_15_OFFSET) -#define IMXRT_PADMUX_GPIO_B1_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_00_OFFSET) -#define IMXRT_PADMUX_GPIO_B1_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_01_OFFSET) -#define IMXRT_PADMUX_GPIO_B1_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_02_OFFSET) -#define IMXRT_PADMUX_GPIO_B1_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_03_OFFSET) -#define IMXRT_PADMUX_GPIO_B1_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_04_OFFSET) -#define IMXRT_PADMUX_GPIO_B1_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_05_OFFSET) -#define IMXRT_PADMUX_GPIO_B1_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_06_OFFSET) -#define IMXRT_PADMUX_GPIO_B1_07 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_07_OFFSET) -#define IMXRT_PADMUX_GPIO_B1_08 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_08_OFFSET) -#define IMXRT_PADMUX_GPIO_B1_09 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_09_OFFSET) -#define IMXRT_PADMUX_GPIO_B1_10 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_10_OFFSET) -#define IMXRT_PADMUX_GPIO_B1_11 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_11_OFFSET) -#define IMXRT_PADMUX_GPIO_B1_12 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_12_OFFSET) -#define IMXRT_PADMUX_GPIO_B1_13 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_13_OFFSET) -#define IMXRT_PADMUX_GPIO_B1_14 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_14_OFFSET) -#define IMXRT_PADMUX_GPIO_B1_15 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_15_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B0_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_00_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B0_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_01_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B0_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_02_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B0_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_03_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B0_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_04_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B0_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_05_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B1_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_00_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B1_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_01_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B1_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_02_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B1_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_03_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B1_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_04_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B1_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_05_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B1_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_06_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B1_07 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_07_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B1_08 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_08_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B1_09 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_09_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B1_10 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_10_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B1_11 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_11_OFFSET) - -/* Pad Control Registers */ - -#define IMXRT_PADCTL_ADDRESS(n) (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_OFFSET(n)) -#define IMXRT_PADCTL_ADDRESS_SNVS(n) (IMXRT_IOMUXCSNVS_BASE + IMXRT_PADCTL_OFFSET_SNVS(n)) - -#define IMXRT_PADCTL_GPIO_EMC_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_00_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_01_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_02_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_03_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_04_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_05_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_06_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_07 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_07_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_08 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_08_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_09 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_09_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_10 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_10_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_11 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_11_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_12 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_12_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_13 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_13_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_14 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_14_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_15 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_15_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_16 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_16_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_17 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_17_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_18 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_18_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_19 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_19_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_20 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_20_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_21 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_21_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_22 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_22_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_23 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_23_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_24 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_24_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_25 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_25_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_26 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_26_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_27 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_27_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_28 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_28_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_29 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_29_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_30 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_30_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_31 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_31_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_32 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_32_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_33 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_33_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_34 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_34_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_35 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_35_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_36 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_36_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_37 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_37_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_38 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_38_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_39 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_39_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_40 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_40_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_41 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_41_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_00_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_01_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_02_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_03_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_04_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_05_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_06_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_07 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_07_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_08 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_08_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_09 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_09_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_10 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_10_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_11 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_11_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_12 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_12_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_13 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_13_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_14 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_14_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_15 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_15_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_00_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_01_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_02_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_03_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_04_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_05_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_06_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_07 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_07_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_08 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_08_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_09 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_09_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_10 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_10_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_11 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_11_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_12 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_12_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_13 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_13_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_14 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_14_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_15 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_15_OFFSET) -#define IMXRT_PADCTL_GPIO_B0_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_00_OFFSET) -#define IMXRT_PADCTL_GPIO_B0_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_01_OFFSET) -#define IMXRT_PADCTL_GPIO_B0_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_02_OFFSET) -#define IMXRT_PADCTL_GPIO_B0_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_03_OFFSET) -#define IMXRT_PADCTL_GPIO_B0_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_04_OFFSET) -#define IMXRT_PADCTL_GPIO_B0_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_05_OFFSET) -#define IMXRT_PADCTL_GPIO_B0_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_06_OFFSET) -#define IMXRT_PADCTL_GPIO_B0_07 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_07_OFFSET) -#define IMXRT_PADCTL_GPIO_B0_08 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_08_OFFSET) -#define IMXRT_PADCTL_GPIO_B0_09 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_09_OFFSET) -#define IMXRT_PADCTL_GPIO_B0_10 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_10_OFFSET) -#define IMXRT_PADCTL_GPIO_B0_11 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_11_OFFSET) -#define IMXRT_PADCTL_GPIO_B0_12 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_12_OFFSET) -#define IMXRT_PADCTL_GPIO_B0_13 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_13_OFFSET) -#define IMXRT_PADCTL_GPIO_B0_14 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_14_OFFSET) -#define IMXRT_PADCTL_GPIO_B0_15 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_15_OFFSET) -#define IMXRT_PADCTL_GPIO_B1_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_00_OFFSET) -#define IMXRT_PADCTL_GPIO_B1_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_01_OFFSET) -#define IMXRT_PADCTL_GPIO_B1_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_02_OFFSET) -#define IMXRT_PADCTL_GPIO_B1_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_03_OFFSET) -#define IMXRT_PADCTL_GPIO_B1_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_04_OFFSET) -#define IMXRT_PADCTL_GPIO_B1_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_05_OFFSET) -#define IMXRT_PADCTL_GPIO_B1_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_06_OFFSET) -#define IMXRT_PADCTL_GPIO_B1_07 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_07_OFFSET) -#define IMXRT_PADCTL_GPIO_B1_08 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_08_OFFSET) -#define IMXRT_PADCTL_GPIO_B1_09 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_09_OFFSET) -#define IMXRT_PADCTL_GPIO_B1_10 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_10_OFFSET) -#define IMXRT_PADCTL_GPIO_B1_11 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_11_OFFSET) -#define IMXRT_PADCTL_GPIO_B1_12 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_12_OFFSET) -#define IMXRT_PADCTL_GPIO_B1_13 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_13_OFFSET) -#define IMXRT_PADCTL_GPIO_B1_14 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_14_OFFSET) -#define IMXRT_PADCTL_GPIO_B1_15 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_15_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B0_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_00_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B0_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_01_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B0_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_02_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B0_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_03_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B0_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_04_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B0_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_05_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B1_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_00_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B1_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_01_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B1_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_02_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B1_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_03_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B1_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_04_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B1_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_05_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B1_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_06_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B1_07 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_07_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B1_08 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_08_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B1_09 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_09_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B1_10 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_10_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B1_11 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_11_OFFSET) - -/* Select Input Registers */ - -#define IMXRT_INPUT_ANATOP_USB_OTG1_ID (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ANATOP_USB_OTG1_ID_OFFSET) -#define IMXRT_INPUT_ANATOP_USB_OTG2_ID (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ANATOP_USB_OTG2_ID_OFFSET) -#define IMXRT_INPUT_CCM_PMIC_READY (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CCM_PMIC_READY_OFFSET) -#define IMXRT_INPUT_CSI_DATA02 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_DATA02_OFFSET) -#define IMXRT_INPUT_CSI_DATA03 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_DATA03_OFFSET) -#define IMXRT_INPUT_CSI_DATA04 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_DATA04_OFFSET) -#define IMXRT_INPUT_CSI_DATA05 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_DATA05_OFFSET) -#define IMXRT_INPUT_CSI_DATA06 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_DATA06_OFFSET) -#define IMXRT_INPUT_CSI_DATA07 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_DATA07_OFFSET) -#define IMXRT_INPUT_CSI_DATA08 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_DATA08_OFFSET) -#define IMXRT_INPUT_CSI_DATA09 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_DATA09_OFFSET) -#define IMXRT_INPUT_CSI_HSYNC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_HSYNC_OFFSET) -#define IMXRT_INPUT_CSI_PIXCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_PIXCLK_OFFSET) -#define IMXRT_INPUT_CSI_VSYNC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_VSYNC_OFFSET) -#define IMXRT_INPUT_ENET_IPG_CLK_RMII (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET_IPG_CLK_RMII_OFFSET) -#define IMXRT_INPUT_ENET_MDIO (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET_MDIO_OFFSET) -#define IMXRT_INPUT_ENET0_RXDATA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET0_RXDATA_OFFSET) -#define IMXRT_INPUT_ENET1_RXDATA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET1_RXDATA_OFFSET) -#define IMXRT_INPUT_ENET_RXEN (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET_RXEN_OFFSET) -#define IMXRT_INPUT_ENET_RXERR (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET_RXERR_OFFSET) -#define IMXRT_INPUT_ENET0_TIMER (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET0_TIMER_OFFSET) -#define IMXRT_INPUT_ENET_TXCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET_TXCLK_OFFSET) -#define IMXRT_INPUT_FLEXCAN1_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXCAN1_RX_OFFSET) -#define IMXRT_INPUT_FLEXCAN2_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXCAN2_RX_OFFSET) -#define IMXRT_INPUT_FLEXPWM1_PWMA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMA3_OFFSET) -#define IMXRT_INPUT_FLEXPWM1_PWMA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMA0_OFFSET) -#define IMXRT_INPUT_FLEXPWM1_PWMA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMA1_OFFSET) -#define IMXRT_INPUT_FLEXPWM1_PWMA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMA2_OFFSET) -#define IMXRT_INPUT_FLEXPWM1_PWMB3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMB3_OFFSET) -#define IMXRT_INPUT_FLEXPWM1_PWMB0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMB0_OFFSET) -#define IMXRT_INPUT_FLEXPWM1_PWMB1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMB1_OFFSET) -#define IMXRT_INPUT_FLEXPWM1_PWMB2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMB2_OFFSET) -#define IMXRT_INPUT_FLEXPWM2_PWMA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMA3_OFFSET) -#define IMXRT_INPUT_FLEXPWM2_PWMA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMA0_OFFSET) -#define IMXRT_INPUT_FLEXPWM2_PWMA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMA1_OFFSET) -#define IMXRT_INPUT_FLEXPWM2_PWMA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMA2_OFFSET) -#define IMXRT_INPUT_FLEXPWM2_PWMB3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMB3_OFFSET) -#define IMXRT_INPUT_FLEXPWM2_PWMB0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMB0_OFFSET) -#define IMXRT_INPUT_FLEXPWM2_PWMB1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMB1_OFFSET) -#define IMXRT_INPUT_FLEXPWM2_PWMB2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMB2_OFFSET) -#define IMXRT_INPUT_FLEXPWM4_PWMA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM4_PWMA0_OFFSET) -#define IMXRT_INPUT_FLEXPWM4_PWMA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM4_PWMA1_OFFSET) -#define IMXRT_INPUT_FLEXPWM4_PWMA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM4_PWMA2_OFFSET) -#define IMXRT_INPUT_FLEXPWM4_PWMA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM4_PWMA3_OFFSET) -#define IMXRT_INPUT_FLEXSPIA_DQS (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_DQS_OFFSET) -#define IMXRT_INPUT_FLEXSPIA_DATA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_DATA0_OFFSET) -#define IMXRT_INPUT_FLEXSPIA_DATA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_DATA1_OFFSET) -#define IMXRT_INPUT_FLEXSPIA_DATA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_DATA2_OFFSET) -#define IMXRT_INPUT_FLEXSPIA_DATA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_DATA3_OFFSET) -#define IMXRT_INPUT_FLEXSPIB_DATA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIB_DATA0_OFFSET) -#define IMXRT_INPUT_FLEXSPIB_DATA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIB_DATA1_OFFSET) -#define IMXRT_INPUT_FLEXSPIB_DATA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIB_DATA2_OFFSET) -#define IMXRT_INPUT_FLEXSPIB_DATA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIB_DATA3_OFFSET) -#define IMXRT_INPUT_FLEXSPIA_SCK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_SCK_OFFSET) -#define IMXRT_INPUT_LPI2C1_SCL (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C1_SCL_OFFSET) -#define IMXRT_INPUT_LPI2C1_SDA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C1_SDA_OFFSET) -#define IMXRT_INPUT_LPI2C2_SCL (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C2_SCL_OFFSET) -#define IMXRT_INPUT_LPI2C2_SDA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C2_SDA_OFFSET) -#define IMXRT_INPUT_LPI2C3_SCL (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C3_SCL_OFFSET) -#define IMXRT_INPUT_LPI2C3_SDA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C3_SDA_OFFSET) -#define IMXRT_INPUT_LPI2C4_SCL (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C4_SCL_OFFSET) -#define IMXRT_INPUT_LPI2C4_SDA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C4_SDA_OFFSET) -#define IMXRT_INPUT_LPSPI1_PCS0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI1_PCS0_OFFSET) -#define IMXRT_INPUT_LPSPI1_SCK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI1_SCK_OFFSET) -#define IMXRT_INPUT_LPSPI1_SDI (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI1_SDI_OFFSET) -#define IMXRT_INPUT_LPSPI1_SDO (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI1_SDO_OFFSET) -#define IMXRT_INPUT_LPSPI2_PCS0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI2_PCS0_OFFSET) -#define IMXRT_INPUT_LPSPI2_SCK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI2_SCK_OFFSET) -#define IMXRT_INPUT_LPSPI2_SDI (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI2_SDI_OFFSET) -#define IMXRT_INPUT_LPSPI2_SDO (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI2_SDO_OFFSET) -#define IMXRT_INPUT_LPSPI3_PCS0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI3_PCS0_OFFSET) -#define IMXRT_INPUT_LPSPI3_SCK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI3_SCK_OFFSET) -#define IMXRT_INPUT_LPSPI3_SDI (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI3_SDI_OFFSET) -#define IMXRT_INPUT_LPSPI3_SDO (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI3_SDO_OFFSET) -#define IMXRT_INPUT_LPSPI4_PCS0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI4_PCS0_OFFSET) -#define IMXRT_INPUT_LPSPI4_SCK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI4_SCK_OFFSET) -#define IMXRT_INPUT_LPSPI4_SDI (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI4_SDI_OFFSET) -#define IMXRT_INPUT_LPSPI4_SDO (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI4_SDO_OFFSET) -#define IMXRT_INPUT_LPUART2_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART2_RX_OFFSET) -#define IMXRT_INPUT_LPUART2_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART2_TX_OFFSET) -#define IMXRT_INPUT_LPUART3_CTS_B (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART3_CTS_B_OFFSET) -#define IMXRT_INPUT_LPUART3_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART3_RX_OFFSET) -#define IMXRT_INPUT_LPUART3_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART3_TX_OFFSET) -#define IMXRT_INPUT_LPUART4_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART4_RX_OFFSET) -#define IMXRT_INPUT_LPUART4_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART4_TX_OFFSET) -#define IMXRT_INPUT_LPUART5_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART5_RX_OFFSET) -#define IMXRT_INPUT_LPUART5_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART5_TX_OFFSET) -#define IMXRT_INPUT_LPUART6_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART6_RX_OFFSET) -#define IMXRT_INPUT_LPUART6_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART6_TX_OFFSET) -#define IMXRT_INPUT_LPUART7_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART7_RX_OFFSET) -#define IMXRT_INPUT_LPUART7_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART7_TX_OFFSET) -#define IMXRT_INPUT_LPUART8_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART8_RX_OFFSET) -#define IMXRT_INPUT_LPUART8_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART8_TX_OFFSET) -#define IMXRT_INPUT_NMI_GLUE_NMI (IMXRT_IOMUXC_BASE + IMXRT_INPUT_NMI_GLUE_NMI_OFFSET) -#define IMXRT_INPUT_QTIMER2_TIMER0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER2_TIMER0_OFFSET) -#define IMXRT_INPUT_QTIMER2_TIMER1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER2_TIMER1_OFFSET) -#define IMXRT_INPUT_QTIMER2_TIMER2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER2_TIMER2_OFFSET) -#define IMXRT_INPUT_QTIMER2_TIMER3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER2_TIMER3_OFFSET) -#define IMXRT_INPUT_QTIMER3_TIMER0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER3_TIMER0_OFFSET) -#define IMXRT_INPUT_QTIMER3_TIMER1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER3_TIMER1_OFFSET) -#define IMXRT_INPUT_QTIMER3_TIMER2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER3_TIMER2_OFFSET) -#define IMXRT_INPUT_QTIMER3_TIMER3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER3_TIMER3_OFFSET) -#define IMXRT_INPUT_SAI1_MCLK2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_MCLK2_OFFSET) -#define IMXRT_INPUT_SAI1_RX_BCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_BCLK_OFFSET) -#define IMXRT_INPUT_SAI1_RX_DATA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_DATA0_OFFSET) -#define IMXRT_INPUT_SAI1_RX_DATA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_DATA1_OFFSET) -#define IMXRT_INPUT_SAI1_RX_DATA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_DATA2_OFFSET) -#define IMXRT_INPUT_SAI1_RX_DATA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_DATA3_OFFSET) -#define IMXRT_INPUT_SAI1_RX_SYNC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_SYNC_OFFSET) -#define IMXRT_INPUT_SAI1_TX_BCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_TX_BCLK_OFFSET) -#define IMXRT_INPUT_SAI1_TX_SYNC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_TX_SYNC_OFFSET) -#define IMXRT_INPUT_SAI2_MCLK2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_MCLK2_OFFSET) -#define IMXRT_INPUT_SAI2_RX_BCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_RX_BCLK_OFFSET) -#define IMXRT_INPUT_SAI2_RX_DATA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_RX_DATA0_OFFSET) -#define IMXRT_INPUT_SAI2_RX_SYNC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_RX_SYNC_OFFSET) -#define IMXRT_INPUT_SAI2_TX_BCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_TX_BCLK_OFFSET) -#define IMXRT_INPUT_SAI2_TX_SYNC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_TX_SYNC_OFFSET) -#define IMXRT_INPUT_SPDIF_IN (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SPDIF_IN_OFFSET) -#define IMXRT_INPUT_USB_OTG2_OC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USB_OTG2_OC_OFFSET) -#define IMXRT_INPUT_USB_OTG1_OC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USB_OTG1_OC_OFFSET) -#define IMXRT_INPUT_USDHC1_CD_B (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC1_CD_B_OFFSET) -#define IMXRT_INPUT_USDHC1_WP (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC1_WP_OFFSET) -#define IMXRT_INPUT_USDHC2_CLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_CLK_OFFSET) -#define IMXRT_INPUT_USDHC2_CD_B (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_CD_B_OFFSET) -#define IMXRT_INPUT_USDHC2_CMD (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_CMD_OFFSET) -#define IMXRT_INPUT_USDHC2_DATA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_DATA0_OFFSET) -#define IMXRT_INPUT_USDHC2_DATA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_DATA1_OFFSET) -#define IMXRT_INPUT_USDHC2_DATA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_DATA2_OFFSET) -#define IMXRT_INPUT_USDHC2_DATA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_DATA3_OFFSET) -#define IMXRT_INPUT_USDHC2_DATA4 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_DATA4_OFFSET) -#define IMXRT_INPUT_USDHC2_DATA5 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_DATA5_OFFSET) -#define IMXRT_INPUT_USDHC2_DATA6 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_DATA6_OFFSET) -#define IMXRT_INPUT_USDHC2_DATA7 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_DATA7_OFFSET) -#define IMXRT_INPUT_USDHC2_WP (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_WP_OFFSET) -#define IMXRT_INPUT_XBAR1_IN02 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN02_OFFSET) -#define IMXRT_INPUT_XBAR1_IN03 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN03_OFFSET) -#define IMXRT_INPUT_XBAR1_IN04 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN04_OFFSET) -#define IMXRT_INPUT_XBAR1_IN05 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN05_OFFSET) -#define IMXRT_INPUT_XBAR1_IN06 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN05_OFFSET) -#define IMXRT_INPUT_XBAR1_IN07 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN07_OFFSET) -#define IMXRT_INPUT_XBAR1_IN08 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN08_OFFSET) -#define IMXRT_INPUT_XBAR1_IN09 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN09_OFFSET) -#define IMXRT_INPUT_XBAR1_IN17 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN17_OFFSET) -#define IMXRT_INPUT_XBAR1_IN18 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN18_OFFSET) -#define IMXRT_INPUT_XBAR1_IN20 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN20_OFFSET) -#define IMXRT_INPUT_XBAR1_IN22 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN22_OFFSET) -#define IMXRT_INPUT_XBAR1_IN23 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN23_OFFSET) -#define IMXRT_INPUT_XBAR1_IN24 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN24_OFFSET) -#define IMXRT_INPUT_XBAR1_IN14 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN14_OFFSET) -#define IMXRT_INPUT_XBAR1_IN15 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN15_OFFSET) -#define IMXRT_INPUT_XBAR1_IN16 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN16_OFFSET) -#define IMXRT_INPUT_XBAR1_IN25 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN25_OFFSET) -#define IMXRT_INPUT_XBAR1_IN19 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN19_OFFSET) -#define IMXRT_INPUT_XBAR1_IN21 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN21_OFFSET) - -/* Register bit definitions *********************************************************/ - -/* General Purpose Register 0 (GPR0) - Reserved */ - -/* General Purpose Register 1 (GPR1) */ - -#define GPR_GPR1_SAI1_MCLK1_SEL_SHIFT (0) -#define GPR_GPR1_SAI1_MCLK1_SEL_MASK (7 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK1_SEL_CCM_SSI1_CLK_ROOT (0 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK1_SEL_CCM_SSI2_CLK_ROOT (1 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK1_SEL_CCM_SSI3_CLK_ROOT (2 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK1_SEL_IOMUX_SAI1_IPG_CLK_SAI_MCLK2 (3 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK1_SEL_IOMUX_SAI2_IPG_CLK_SAI_MCLK2 (4 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK1_SEL_IOMUX_SAI3_IPG_CLK_SAI_MCLK2 (5 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) -#define GPR_GPR1_SAI1_MCLK2_SEL_SHIFT (3) -#define GPR_GPR1_SAI1_MCLK2_SEL_MASK (7 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK2_SEL_CCM_SSI1_CLK_ROOT (0 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK2_SEL_CCM_SSI2_CLK_ROOT (1 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK2_SEL_CCM_SSI3_CLK_ROOT (2 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK2_SEL_IOMUX_SAI1_IPG_CLK_SAI_MCLK2 (3 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK2_SEL_IOMUX_SAI2_IPG_CLK_SAI_MCLK2 (4 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK2_SEL_IOMUX_SAI3_IPG_CLK_SAI_MCLK2 (5 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) -#define GPR_GPR1_SAI1_MCLK3_SEL_SHIFT (6) -#define GPR_GPR1_SAI1_MCLK3_SEL_MASK (3 << GPR_GPR1_SAI1_MCLK3_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK3_SEL_CCM_SPDIF0_CLK_ROOT (0 << GPR_GPR1_SAI1_MCLK3_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK3_SEL_IOMUX_SPDIF_TX_CLK2 (1 << GPR_GPR1_SAI1_MCLK3_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK3_SEL_SPDIF_SPDIF_SRCLK (2 << GPR_GPR1_SAI1_MCLK3_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK3_SEL_SPDIF_SPDIF_OUTCLOCK (3 << GPR_GPR1_SAI1_MCLK3_SEL_SHIFT) -#define GPR_GPR1_SAI2_MCLK3_SEL_SHIFT (8) -#define GPR_GPR1_SAI2_MCLK3_SEL_MASK (3 << GPR_GPR1_SAI2_MCLK3_SEL_SHIFT) -# define GPR_GPR1_SAI2_MCLK3_SEL_CCM_SPDIF0_CLK_ROOT (0 << GPR_GPR1_SAI2_MCLK3_SEL_SHIFT) -# define GPR_GPR1_SAI2_MCLK3_SEL_IOMUX_SPDIF_TX_CLK2 (1 << GPR_GPR1_SAI2_MCLK3_SEL_SHIFT) -# define GPR_GPR1_SAI2_MCLK3_SEL_SPDIF_SPDIF_SRCLK (2 << GPR_GPR1_SAI2_MCLK3_SEL_SHIFT) -# define GPR_GPR1_SAI2_MCLK3_SEL_SPDIF_SPDIF_OUTCLOCK (3 << GPR_GPR1_SAI2_MCLK3_SEL_SHIFT) -#define GPR_GPR1_SAI3_MCLK3_SEL_SHIFT (10) -#define GPR_GPR1_SAI3_MCLK3_SEL_MASK (3 << GPR_GPR1_SAI3_MCLK3_SEL_SHIFT) -# define GPR_GPR1_SAI3_MCLK3_SEL_CCM_SPDIF0_CLK_ROOT (0 << GPR_GPR1_SAI3_MCLK3_SEL_SHIFT) -# define GPR_GPR1_SAI3_MCLK3_SEL_IOMUX_SPDIF_TX_CLK2 (1 << GPR_GPR1_SAI3_MCLK3_SEL_SHIFT) -# define GPR_GPR1_SAI3_MCLK3_SEL_SPDIF_SPDIF_SRCLK (2 << GPR_GPR1_SAI3_MCLK3_SEL_SHIFT) -# define GPR_GPR1_SAI3_MCLK3_SEL_SPDIF_SPDIF_OUTCLOCK (3 << GPR_GPR1_SAI3_MCLK3_SEL_SHIFT) -#define GPR_GPR1_GINT (1 << 12) -#define GPR_GPR1_ENET1_CLK_SEL (1 << 13) -#define GPR_GPR1_USB_EXP_MODE_EN (1 << 15) -#define GPR_GPR1_ENET1_TX_CLK_OUT_EN (1 << 17) -#define GPR_GPR1_SAI1_MCLK_DIR_IN (0 << 19) -#define GPR_GPR1_SAI1_MCLK_DIR_OUT (1 << 19) -#define GPR_GPR1_SAI2_MCLK_DIR_IN (0 << 20) -#define GPR_GPR1_SAI2_MCLK_DIR_OUT (1 << 20) -#define GPR_GPR1_SAI3_MCLK_DIR_IN (0 << 21) -#define GPR_GPR1_SAI3_MCLK_DIR_OUT (1 << 21) -#define GPR_GPR1_EXC_MON_OKAY (0 << 22) -#define GPR_GPR1_EXC_MON_SLVERR (1 << 22) -#define GPR_GPR1_ENET_IMG_CLS_S_EN (1 << 23) -#define GPR_GPR1_CM7_FORCE_HCLK_EN (1 << 31) - -/* General Purpose Register 2 (GPR2) */ - -#define GPR_GPR2_L2_MEM_POWERSAVE_EN (1 << 12) -#define GPR_GPR2_L2_MEM_FORCE_DEEPSLEEP (1 << 14) -#define GPR_GPR2_MQS_CLK_DIV_SHIFT (16) -#define GPR_GPR2_MQS_CLK_DIV_MASK (255 << GPR_GPR2_MQS_CLK_DIV_SHIFT) -# define GPR_GPR2_MQS_CLK_DIV(n) ((n - 1) << GPR_GPR2_MQS_CLK_DIV_SHIFT) -#define GPR_GPR2_MQS_SW_RST_EN (1 << 24) -#define GPR_GPR2_MQS_EN (1 << 25) -#define GPR_GPR2_MQS_OVERSAMPLE32 (0 << 26) -#define GPR_GPR2_MQS_OVERSAMPLE64 (1 << 26) -#define GPR_GPR2_QTIM1_TMR_RESET (1 << 28) -#define GPR_GPR2_QTIM2_TMR_RESET (1 << 29) -#define GPR_GPR2_QTIM3_TMR_RESET (1 << 30) -#define GPR_GPR2_QTIM4_TMR_RESET (1 << 31) - -/* General Purpose Register 3 (GPR3) */ - -#define GPR_GPR3_OCRAM_CTL_SHIFT (0) -#define GPR_GPR3_OCRAM_CTL_MASK (15 << GPR_GPR3_OCRAM_CTL_SHIFT) -# define GPR_GPR3_OCRAM_CTL_READ_DATA_PIPELINE_EN (1 << GPR_GPR3_OCRAM_CTL_SHIFT) -# define GPR_GPR3_OCRAM_CTL_READ_ADDR_PIPELINE_EN (2 << GPR_GPR3_OCRAM_CTL_SHIFT) -# define GPR_GPR3_OCRAM_CTL_WRITE_DATA_PIPELINE_EN (4 << GPR_GPR3_OCRAM_CTL_SHIFT) -# define GPR_GPR3_OCRAM_CTL_WRITE_ADDR_PIPELINE_EN (8 << GPR_GPR3_OCRAM_CTL_SHIFT) -#define GPR_GPR3_DCP_KEY_SEL_128 (0 << 4) -#define GPR_GPR3_DCP_KEY_SEL_256 (1 << 4) -#define GPR_GPR3_OCRAM_STATUS_SHIFT (16) -#define GPR_GPR3_OCRAM_STATUS_MASK (15 << GPR_GPR3_OCRAM_STATUS_SHIFT) -# define GPR_GPR3_OCRAM_STATUS_READ_DATA_PIPELINE_EN (1 << GPR_GPR3_OCRAM_STATUS_SHIFT) -# define GPR_GPR3_OCRAM_STATUS_READ_ADDR_PIPELINE_EN (2 << GPR_GPR3_OCRAM_STATUS_SHIFT) -# define GPR_GPR3_OCRAM_STATUS_WRITE_DATA_PIPELINE_EN (4 << GPR_GPR3_OCRAM_STATUS_SHIFT) -# define GPR_GPR3_OCRAM_STATUS_WRITE_ADDR_PIPELINE_EN (8 << GPR_GPR3_OCRAM_STATUS_SHIFT) - -/* General Purpose Register 4 (GPR4) */ - -#define GPR_GRP4_EDMA_STOP_REQ (1 << 0) -#define GPR_GPR4_CAN1_STOP_REQ (1 << 1) -#define GPR_GPR4_CAN2_STOP_REQ (1 << 2) -#define GPR_GPR4_TRNG_STOP_REQ (1 << 3) -#define GPR_GPR4_ENET_STOP_REQ (1 << 4) -#define GPR_GPR4_SAI1_STOP_REQ (1 << 5) -#define GPR_GPR4_SAI2_STOP_REQ (1 << 6) -#define GPR_GPR4_SAI3_STOP_REQ (1 << 7) -#define GPR_GPR4_SEMC_STOP_REQ (1 << 9) -#define GPR_GPR4_PIT_STOP_REQ (1 << 10) -#define GPR_GPR4_FLEXSPI_STOP_REQ (1 << 11) -#define GPR_GPR4_FLEXIO1_STOP_REQ (1 << 12) -#define GPR_GPR4_FLEXIO2_STOP_REQ (1 << 13) -#define GPR_GRP4_EDMA_STOP_ACK (1 << 16) -#define GPR_GPR4_CAN1_STOP_ACK (1 << 17) -#define GPR_GPR4_CAN2_STOP_ACK (1 << 18) -#define GPR_GPR4_TRNG_STOP_ACK (1 << 19) -#define GPR_GPR4_ENET_STOP_ACK (1 << 20) -#define GPR_GPR4_SAI1_STOP_ACK (1 << 21) -#define GPR_GPR4_SAI2_STOP_ACK (1 << 22) -#define GPR_GPR4_SAI3_STOP_ACK (1 << 23) -#define GPR_GPR4_SEMC_STOP_ACK (1 << 25) -#define GPR_GPR4_PIT_STOP_ACK (1 << 26) -#define GPR_GPR4_FLEXSPI_STOP_ACK (1 << 27) -#define GPR_GPR4_FLEXIO1_STOP_ACK (1 << 28) -#define GPR_GPR4_FLEXIO2_STOP_ACK (1 << 29) - -/* General Purpose Register 5 (GPR5) */ - -#define GPR_GPR5_WDOG1_MASK (1 << 6) -#define GPR_GPR5_WDOG2_MASK (1 << 7) -#define GPR_GPR5_GPT2_CAPIN1_SEL_PAD (0 << 23) -#define GPR_GPR5_GPT2_CAPIN1_SEL_ENET1 (1 << 23) -#define GPR_GPR5_ENET_EVENT3IN_SEL_ENET (0 << 25) -#define GPR_GPR5_ENET_EVENT3IN_SEL_GPT2CMP1 (1 << 25) -#define GPR_GPR5_VREF_1M_CLK_GPT1_IPG_PERCLK (0 << 28) -#define GPR_GPR5_VREF_1M_CLK_GPT1_ANATOP (1 << 28) -#define GPR_GPR5_VREF_1M_CLK_GPT2_IPG_PERCLK (0 << 29) -#define GPR_GPR5_VREF_1M_CLK_GPT2_ANATOP (1 << 29) - -/* General Purpose Register 6 (GPR6) */ - -#define GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT (0) -#define GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT) -#define GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT (1) -#define GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT) -#define GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT (2) -#define GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT) -#define GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT (3) -#define GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT) -#define GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT (4) -#define GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT) -#define GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT (5) -#define GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT) -#define GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT (6) -#define GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT) -#define GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT (7) -#define GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT) -#define GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT (8) -#define GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT) -#define GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT (9) -#define GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT) -#define GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT (10) -#define GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT) -#define GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT (11) -#define GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT) -#define GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT (12) -#define GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT) -#define GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT (13) -#define GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT) -#define GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT (14) -#define GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT) -#define GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT (15) -#define GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT (16) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT (17) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT (18) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT (19) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT (20) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT (21) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT (22) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT (23) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT (24) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT (25) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT (26) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT (27) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT (28) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT (29) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT (30) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT (31) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT) - -/* General Purpose Register 7 (GPR7) */ - -#define GPR_GPR7_LPI2C1_STOP_REQ (1 << 0) -#define GPR_GPR7_LPI2C2_STOP_REQ (1 << 1) -#define GPR_GPR7_LPI2C3_STOP_REQ (1 << 2) -#define GPR_GPR7_LPI2C4_STOP_REQ (1 << 3) -#define GPR_GPR7_LPSPI1_STOP_REQ (1 << 4) -#define GPR_GPR7_LPSPI2_STOP_REQ (1 << 5) -#define GPR_GPR7_LPSPI3_STOP_REQ (1 << 6) -#define GPR_GPR7_LPSPI4_STOP_REQ (1 << 7) -#define GPR_GPR7_LPUART1_STOP_REQ (1 << 8) -#define GPR_GPR7_LPUART2_STOP_REQ (1 << 9) -#define GPR_GPR7_LPUART3_STOP_REQ (1 << 10) -#define GPR_GPR7_LPUART4_STOP_REQ (1 << 11) -#define GPR_GPR7_LPUART5_STOP_REQ (1 << 12) -#define GPR_GPR7_LPUART6_STOP_REQ (1 << 13) -#define GPR_GPR7_LPUART7_STOP_REQ (1 << 14) -#define GPR_GPR7_LPUART8_STOP_REQ (1 << 15) -#define GPR_GPR7_LPI2C1_STOP_ACK (1 << 16) -#define GPR_GPR7_LPI2C2_STOP_ACK (1 << 17) -#define GPR_GPR7_LPI2C3_STOP_ACK (1 << 18) -#define GPR_GPR7_LPI2C4_STOP_ACK (1 << 19) -#define GPR_GPR7_LPSPI1_STOP_ACK (1 << 20) -#define GPR_GPR7_LPSPI2_STOP_ACK (1 << 21) -#define GPR_GPR7_LPSPI3_STOP_ACK (1 << 22) -#define GPR_GPR7_LPSPI4_STOP_ACK (1 << 23) -#define GPR_GPR7_LPUART1_STOP_ACK (1 << 24) -#define GPR_GPR7_LPUART2_STOP_ACK (1 << 25) -#define GPR_GPR7_LPUART3_STOP_ACK (1 << 26) -#define GPR_GPR7_LPUART4_STOP_ACK (1 << 27) -#define GPR_GPR7_LPUART5_STOP_ACK (1 << 28) -#define GPR_GPR7_LPUART6_STOP_ACK (1 << 29) -#define GPR_GPR7_LPUART7_STOP_ACK (1 << 30) -#define GPR_GPR7_LPUART8_STOP_ACK (1 << 31) - -/* General Purpose Register 8 (GPR8) */ - -#define GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT (0) -#define GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPI2C1_IPG_ON_IN_STOP (0 << GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPI2C1_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT) -#define GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT (1) -#define GPR_GPR8_LPI2C1_IPG_DOZE_MASK (1 << GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPI2C1_IPG_NOT_DOZED (0 << GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPI2C1_IPG_DOZED (1 << GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT) -#define GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT (2) -#define GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPI2C2_IPG_ON_IN_STOP (0 << GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPI2C2_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT) -#define GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT (3) -#define GPR_GPR8_LPI2C2_IPG_DOZE_MASK (1 << GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPI2C2_IPG_NOT_DOZED (0 << GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPI2C2_IPG_DOZED (1 << GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT) -#define GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT (4) -#define GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPI2C3_IPG_ON_IN_STOP (0 << GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPI2C3_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT) -#define GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT (5) -#define GPR_GPR8_LPI2C3_IPG_DOZE_MASK (1 << GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPI2C3_IPG_NOT_DOZED (0 << GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPI2C3_IPG_DOZED (1 << GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT) -#define GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT (6) -#define GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPI2C4_IPG_ON_IN_STOP (0 << GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPI2C4_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT) -#define GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT (7) -#define GPR_GPR8_LPI2C4_IPG_DOZE_MASK (1 << GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPI2C4_IPG_NOT_DOZED (0 << GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPI2C4_IPG_DOZED (1 << GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT) -#define GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT (8) -#define GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPSPI1_IPG_ON_IN_STOP (0 << GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPSPI1_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT) -#define GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT (9) -#define GPR_GPR8_LPSPI1_IPG_DOZE_MASK (1 << GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPSPI1_IPG_NOT_DOZED (0 << GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPSPI1_IPG_DOZED (1 << GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT) -#define GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT (10) -#define GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPSPI2_IPG_ON_IN_STOP (0 << GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPSPI2_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT) -#define GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT (11) -#define GPR_GPR8_LPSPI2_IPG_DOZE_MASK (1 << GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPSPI2_IPG_NOT_DOZED (0 << GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPSPI2_IPG_DOZED (1 << GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT) -#define GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT (12) -#define GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPSPI3_IPG_ON_IN_STOP (0 << GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPSPI3_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT) -#define GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT (13) -#define GPR_GPR8_LPSPI3_IPG_DOZE_MASK (1 << GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPSPI3_IPG_NOT_DOZED (0 << GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPSPI3_IPG_DOZED (1 << GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT) -#define GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT (14) -#define GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPSPI4_IPG_ON_IN_STOP (0 << GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPSPI4_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT) -#define GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT (15) -#define GPR_GPR8_LPSPI4_IPG_DOZE_MASK (1 << GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPSPI4_IPG_NOT_DOZED (0 << GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPSPI4_IPG_DOZED (1 << GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT) -#define GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT (16) -#define GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPUART1_IPG_ON_IN_STOP (0 << GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPUART1_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT) -#define GPR_GPR8_LPUART1_IPG_DOZE_SHIFT (17) -#define GPR_GPR8_LPUART1_IPG_DOZE_MASK (1 << GPR_GPR8_LPUART1_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPUART1_IPG_NOT_DOZED (0 << GPR_GPR8_LPUART1_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPUART1_IPG_DOZED (1 << GPR_GPR8_LPUART1_IPG_DOZE_SHIFT) -#define GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT (18) -#define GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPUART2_IPG_ON_IN_STOP (0 << GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPUART2_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT) -#define GPR_GPR8_LPUART2_IPG_DOZE_SHIFT (19) -#define GPR_GPR8_LPUART2_IPG_DOZE_MASK (1 << GPR_GPR8_LPUART2_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPUART2_IPG_NOT_DOZED (0 << GPR_GPR8_LPUART2_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPUART2_IPG_DOZED (1 << GPR_GPR8_LPUART2_IPG_DOZE_SHIFT) -#define GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT (20) -#define GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPUART3_IPG_ON_IN_STOP (0 << GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPUART3_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT) -#define GPR_GPR8_LPUART3_IPG_DOZE_SHIFT (21) -#define GPR_GPR8_LPUART3_IPG_DOZE_MASK (1 << GPR_GPR8_LPUART3_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPUART3_IPG_NOT_DOZED (0 << GPR_GPR8_LPUART3_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPUART3_IPG_DOZED (1 << GPR_GPR8_LPUART3_IPG_DOZE_SHIFT) -#define GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT (22) -#define GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPUART4_IPG_ON_IN_STOP (0 << GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPUART4_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT) -#define GPR_GPR8_LPUART4_IPG_DOZE_SHIFT (23) -#define GPR_GPR8_LPUART4_IPG_DOZE_MASK (1 << GPR_GPR8_LPUART4_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPUART4_IPG_NOT_DOZED (0 << GPR_GPR8_LPUART4_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPUART4_IPG_DOZED (1 << GPR_GPR8_LPUART4_IPG_DOZE_SHIFT) -#define GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT (24) -#define GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPUART5_IPG_ON_IN_STOP (0 << GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPUART5_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT) -#define GPR_GPR8_LPUART5_IPG_DOZE_SHIFT (25) -#define GPR_GPR8_LPUART5_IPG_DOZE_MASK (1 << GPR_GPR8_LPUART5_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPUART5_IPG_NOT_DOZED (0 << GPR_GPR8_LPUART5_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPUART5_IPG_DOZED (1 << GPR_GPR8_LPUART5_IPG_DOZE_SHIFT) -#define GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT (26) -#define GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPUART6_IPG_ON_IN_STOP (0 << GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPUART6_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT) -#define GPR_GPR8_LPUART6_IPG_DOZE_SHIFT (27) -#define GPR_GPR8_LPUART6_IPG_DOZE_MASK (1 << GPR_GPR8_LPUART6_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPUART6_IPG_NOT_DOZED (0 << GPR_GPR8_LPUART6_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPUART6_IPG_DOZED (1 << GPR_GPR8_LPUART6_IPG_DOZE_SHIFT) -#define GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT (28) -#define GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPUART7_IPG_ON_IN_STOP (0 << GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPUART7_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT) -#define GPR_GPR8_LPUART7_IPG_DOZE_SHIFT (29) -#define GPR_GPR8_LPUART7_IPG_DOZE_MASK (1 << GPR_GPR8_LPUART7_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPUART7_IPG_NOT_DOZED (0 << GPR_GPR8_LPUART7_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPUART7_IPG_DOZED (1 << GPR_GPR8_LPUART7_IPG_DOZE_SHIFT) -#define GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT (30) -#define GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPUART8_IPG_ON_IN_STOP (0 << GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPUART8_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT) -#define GPR_GPR8_LPUART8_IPG_DOZE_SHIFT (31) -#define GPR_GPR8_LPUART8_IPG_DOZE_MASK (1 << GPR_GPR8_LPUART8_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPUART8_IPG_NOT_DOZED (0 << GPR_GPR8_LPUART8_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPUART8_IPG_DOZED (1 << GPR_GPR8_LPUART8_IPG_DOZE_SHIFT) - -/* General Purpose Register 9 (GPR9) - Reserved */ - -/* General Purpose Register 10 (GPR10) */ - -#define GPR_GPR10_NIDEN (1 << 0) -#define GPR_GPR10_DBG_EN (1 << 1) -#define GPR_GPR10_SEC_ERR_RESP (1 << 2) -#define GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX (1 << 4) -#define GPR_GPR10_OCRAM_TZ_EN (1 << 8) -#define GPR_GPR10_OCRAM_TZ_ADDR_SHIFT (9) -#define GPR_GPR10_OCRAM_TZ_ADDR_MASK (0x3f << GPR_GPR10_OCRAM_TZ_ADDR_SHIFT) -# define GPR_GPR10_OCRAM_TZ_ADDR(n) ((uint32_t)(n) << GPR_GPR10_OCRAM_TZ_ADDR_SHIFT) -#define GPR_GPR10_LOCK_NIDEN (1 << 16) -#define GPR_GPR10_LOCK_DBG_EN (1 << 17) -#define GPR_GPR10_LOCK_SEC_ERR_RESP (1 << 18) -#define GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX (1 << 20) -#define GPR_GPR10_LOCK_OCRAM_TZ_EN (1 << 24) -#define GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT (25) -#define GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK (0x3f << GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT) -# define GPR_GPR10_LOCK_OCRAM_TZ_ADDR(n) ((uint32_t)(n) << GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT) - -/* General Purpose Register 11 (GPR11) */ - -#define GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFTS (0) -#define GPR_GPR11_M7_APC_AC_R0_CTRL_MASK (3 << GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFTS) -# define GPR_GPR11_M7_APC_AC_R0_CTRL_NO_ACCESS (0 << GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFTS) -# define GPR_GPR11_M7_APC_AC_R0_CTRL_NO_DEBUG (1 << GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFTS) -# define GPR_GPR11_M7_APC_AC_R0_CTRL_NO_FLEXSPI (2 << GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFTS) -# define GPR_GPR11_M7_APC_AC_R0_CTRL_NO_DEBUG_FLEXSPI (3 << GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFTS) -#define GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFTS (2) -#define GPR_GPR11_M7_APC_AC_R1_CTRL_MASK (3 << GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFTS) -# define GPR_GPR11_M7_APC_AC_R1_CTRL_NO_ACCESS (0 << GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFTS) -# define GPR_GPR11_M7_APC_AC_R1_CTRL_NO_DEBUG (1 << GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFTS) -# define GPR_GPR11_M7_APC_AC_R1_CTRL_NO_FLEXSPI (2 << GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFTS) -# define GPR_GPR11_M7_APC_AC_R1_CTRL_NO_DEBUG_FLEXSPI (3 << GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFTS) -#define GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFTS (4) -#define GPR_GPR11_M7_APC_AC_R2_CTRL_MASK (3 << GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFTS) -# define GPR_GPR11_M7_APC_AC_R2_CTRL_NO_ACCESS (0 << GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFTS) -# define GPR_GPR11_M7_APC_AC_R2_CTRL_NO_DEBUG (1 << GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFTS) -# define GPR_GPR11_M7_APC_AC_R2_CTRL_NO_FLEXSPI (2 << GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFTS) -# define GPR_GPR11_M7_APC_AC_R2_CTRL_NO_DEBUG_FLEXSPI (3 << GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFTS) -#define GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFTS (6) -#define GPR_GPR11_M7_APC_AC_R3_CTRL_MASK (3 << GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFTS) -# define GPR_GPR11_M7_APC_AC_R3_CTRL_NO_ACCESS (0 << GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFTS) -# define GPR_GPR11_M7_APC_AC_R3_CTRL_NO_DEBUG (1 << GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFTS) -# define GPR_GPR11_M7_APC_AC_R3_CTRL_NO_FLEXSPI (2 << GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFTS) -# define GPR_GPR11_M7_APC_AC_R3_CTRL_NO_DEBUG_FLEXSPI (3 << GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFTS) -#define GPR_GPR11_BEE_DE_RX_EN_SHIFTS (8) -#define GPR_GPR11_BEE_DE_RX_EN_MASK (0xf << GPR_GPR11_BEE_DE_RX_EN_SHIFTS) -# define GPR_GPR11_BEE_DE_RX_EN(n) ((uint32_t)(n) << GPR_GPR11_BEE_DE_RX_EN_SHIFTS) -# define GPR_GPR11_BEE_DE_R0_EN (1) << GPR_GPR11_BEE_DE_RX_EN_SHIFTS) -# define GPR_GPR11_BEE_DE_R1_EN (2) << GPR_GPR11_BEE_DE_RX_EN_SHIFTS) -# define GPR_GPR11_BEE_DE_R2_EN (4) << GPR_GPR11_BEE_DE_RX_EN_SHIFTS) -# define GPR_GPR11_BEE_DE_R3_EN (8) << GPR_GPR11_BEE_DE_RX_EN_SHIFTS) -#define GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFTS (16) -#define GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_MASK (3 << GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFTS) -# define GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_NO_ACCESS (0 << GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFTS) -# define GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_NO_DEBUG (1 << GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFTS) -# define GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_NO_FLEXSPI (2 << GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFTS) -# define GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_NO_DEBUG_FLEXSPI (3 << GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFTS) -#define GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFTS (18) -#define GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_MASK (3 << GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFTS) -# define GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_NO_ACCESS (0 << GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFTS) -# define GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_NO_DEBUG (1 << GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFTS) -# define GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_NO_FLEXSPI (2 << GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFTS) -# define GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_NO_DEBUG_FLEXSPI (3 << GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFTS) -#define GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFTS (20) -#define GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_MASK (3 << GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFTS) -# define GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_NO_ACCESS (0 << GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFTS) -# define GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_NO_DEBUG (1 << GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFTS) -# define GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_NO_FLEXSPI (2 << GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFTS) -# define GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_NO_DEBUG_FLEXSPI (3 << GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFTS) -#define GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFTS (22) -#define GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_MASK (3 << GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFTS) -# define GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_NO_ACCESS (0 << GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFTS) -# define GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_NO_DEBUG (1 << GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFTS) -# define GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_NO_FLEXSPI (2 << GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFTS) -# define GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_NO_DEBUG_FLEXSPI (3 << GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFTS) -#define GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFTS (24) -#define GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK (0xf << GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFTS) -# define GPR_GPR11_LOCK_BEE_DE_RX_EN(n) ((uint32_t)(n) << GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFTS) -# define GPR_GPR11_LOCK_BEE_DE_R0_EN (1) << GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFTS) -# define GPR_GPR11_LOCK_BEE_DE_R1_EN (2) << GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFTS) -# define GPR_GPR11_LOCK_BEE_DE_R2_EN (4) << GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFTS) -# define GPR_GPR11_LOCK_BEE_DE_R3_EN (8) << GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFTS) - -/* General Purpose Register 12 (GPR12) */ - -#define GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT (0) -#define GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK (1 << GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT) -# define GPR_GPR12_FLEXIO1_IPG_ON_IN_STOP (0 << GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT) -# define GPR_GPR12_FLEXIO1_IPG_OFF_IN_STOP (1 << GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT) -#define GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT (1) -#define GPR_GPR12_FLEXIO1_IPG_DOZE_MASK (1 << GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT) -# define GPR_GPR12_FLEXIO1_IPG_NOT_DOZED (0 << GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT) -# define GPR_GPR12_FLEXIO1_IPG_DOZED (1 << GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT) -#define GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT (2) -#define GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK (1 << GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT) -# define GPR_GPR12_FLEXIO2_IPG_ON_IN_STOP (0 << GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT) -# define GPR_GPR12_FLEXIO2_IPG_OFF_IN_STOP (1 << GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT) -#define GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT (3) -#define GPR_GPR12_FLEXIO2_IPG_DOZE_MASK (1 << GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT) -# define GPR_GPR12_FLEXIO2_IPG_NOT_DOZED (0 << GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT) -# define GPR_GPR12_FLEXIO2_IPG_DOZED (1 << GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT) -#define GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT (4) -#define GPR_GPR12_ACMP_IPG_STOP_MODE_MASK (1 << GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT) -# define GPR_GPR12_ACMP_IPG_ON_IN_STOP (0 << GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT) -# define GPR_GPR12_ACMP_IPG_OFF_IN_STOP (1 << GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT) - -/* General Purpose Register 13 (GPR13) */ - -#define GPR_GPR13_ARCACHE_USDHC_CACHEABLE (1 << 0) -#define GPR_GPR13_AWCACHE_USDHC_CACHEABLE (1 << 1) -#define GPR_GPR13_CACHE_ENET_CACHEABLE (1 << 7) -#define GPR_GPR13_CACHE_USB_CACHEABLE (1 << 13) - -/* General Purpose Register 14 (GPR14) */ - -#define GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN (1 << 0) -#define GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN (1 << 1) -#define GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN (1 << 2) -#define GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN (1 << 3) -#define GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP (1 << 4) -#define GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP (1 << 5) -#define GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP (1 << 6) -#define GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP (1 << 7) -#define GPR_GPR14_ACMP1_SAMPLE_SYNC_EN (1 << 8) -#define GPR_GPR14_ACMP2_SAMPLE_SYNC_EN (1 << 9) -#define GPR_GPR14_ACMP3_SAMPLE_SYNC_EN (1 << 10) -#define GPR_GPR14_ACMP4_SAMPLE_SYNC_EN (1 << 11) -#define GPR_GPR14_CM7_CFGITCMSZ_SHIFT (16) -#define GPR_GPR14_CM7_CFGITCMSZ_MASK (0x4 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGITCMSZ_0KB (0 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGITCMSZ_4KB (3 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGITCMSZ_8KB (4 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGITCMSZ_16KB (6 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGITCMSZ_32KB (6 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGITCMSZ_64KB (7 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGITCMSZ_128KB (8 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGITCMSZ_256KB (9 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGITCMSZ_512KB (10 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) -#define GPR_GPR14_CM7_CFGDTCMSZ_SHIFT (20) -#define GPR_GPR14_CM7_CFGDTCMSZ_MASK (0xf << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGDTCMSZ_0KB (0 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGDTCMSZ_4KB (3 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGDTCMSZ_8KB (4 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGDTCMSZ_16KB (6 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGDTCMSZ_32KB (6 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGDTCMSZ_64KB (7 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGDTCMSZ_128KB (8 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGDTCMSZ_256KB (9 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGDTCMSZ_512KB (10 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) - -/* General Purpose Register 15 (GPR16) - Reserved */ - -/* General Purpose Register 16 (GPR16) */ - -#define GPR_GPR16_INIT_ITCM_EN (1 << 0) -#define GPR_GPR16_INIT_DTCM_EN (1 << 1) -#define GPR_GPR16_FLEXRAM_BANK_CFG_SELF (1 << 2) -#define GPR_GPR16_CM7_INIT_VTOR_SHIFT (7) -#define GPR_GPR16_CM7_INIT_VTOR_MASK (0xffffff1 << GPR_GPR16_CM7_INIT_VTOR_SHIFT) -#define GPR_GPR16_CM7_INIT_VTOR(n) (((uint32_t)(n) & 0x1ffffff)) << GPR_GPR16_CM7_INIT_VTOR_SHIFT) - -/* General Purpose Register 17 (GPR17) */ - -#define GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT (0) -#define GPR_GPR17_FLEXRAM_BANK_CFG_MASK (0xffffffff << GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT) -#define GPR_GPR17_FLEXRAM_BANK_CFG(n) ((uint32_t)(n)) << GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT) -#define GPR_GPR17_FLEXRAM_BANK0_SHIFT (0) -#define GPR_GPR17_FLEXRAM_BANK0_MASK (3 << GPR_GPR17_FLEXRAM_BANK0_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK0_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK0_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK0_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK0_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK0_DTCM (2 << GPR_GPR17_FLEXRAM_BANK0_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK0_ITCM (3 << GPR_GPR17_FLEXRAM_BANK0_SHIFT) -#define GPR_GPR17_FLEXRAM_BANK1_SHIFT (2) -#define GPR_GPR17_FLEXRAM_BANK1_MASK (3 << GPR_GPR17_FLEXRAM_BANK1_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK1_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK1_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK1_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK1_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK1_DTCM (2 << GPR_GPR17_FLEXRAM_BANK1_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK1_ITCM (3 << GPR_GPR17_FLEXRAM_BANK1_SHIFT) -#define GPR_GPR17_FLEXRAM_BANK2_SHIFT (4) -#define GPR_GPR17_FLEXRAM_BANK2_MASK (3 << GPR_GPR17_FLEXRAM_BANK2_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK2_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK2_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK2_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK2_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK2_DTCM (2 << GPR_GPR17_FLEXRAM_BANK2_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK2_ITCM (3 << GPR_GPR17_FLEXRAM_BANK2_SHIFT) -#define GPR_GPR17_FLEXRAM_BANK3_SHIFT (6) -#define GPR_GPR17_FLEXRAM_BANK3_MASK (3 << GPR_GPR17_FLEXRAM_BANK3_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK3_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK3_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK3_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK3_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK3_DTCM (2 << GPR_GPR17_FLEXRAM_BANK3_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK3_ITCM (3 << GPR_GPR17_FLEXRAM_BANK3_SHIFT) -#define GPR_GPR17_FLEXRAM_BANK4_SHIFT (8) -#define GPR_GPR17_FLEXRAM_BANK4_MASK (3 << GPR_GPR17_FLEXRAM_BANK4_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK4_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK4_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK4_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK4_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK4_DTCM (2 << GPR_GPR17_FLEXRAM_BANK4_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK4_ITCM (3 << GPR_GPR17_FLEXRAM_BANK4_SHIFT) -#define GPR_GPR17_FLEXRAM_BANK5_SHIFT (10) -#define GPR_GPR17_FLEXRAM_BANK5_MASK (3 << GPR_GPR17_FLEXRAM_BANK5_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK5_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK5_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK5_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK5_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK5_DTCM (2 << GPR_GPR17_FLEXRAM_BANK5_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK5_ITCM (3 << GPR_GPR17_FLEXRAM_BANK5_SHIFT) -#define GPR_GPR17_FLEXRAM_BANK6_SHIFT (12) -#define GPR_GPR17_FLEXRAM_BANK6_MASK (3 << GPR_GPR17_FLEXRAM_BANK6_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK6_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK6_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK6_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK6_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK6_DTCM (2 << GPR_GPR17_FLEXRAM_BANK6_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK6_ITCM (3 << GPR_GPR17_FLEXRAM_BANK6_SHIFT) -#define GPR_GPR17_FLEXRAM_BANK7_SHIFT (14) -#define GPR_GPR17_FLEXRAM_BANK7_MASK (3 << GPR_GPR17_FLEXRAM_BANK7_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK7_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK7_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK7_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK7_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK7_DTCM (2 << GPR_GPR17_FLEXRAM_BANK7_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK7_ITCM (3 << GPR_GPR17_FLEXRAM_BANK7_SHIFT) -#define GPR_GPR17_FLEXRAM_BANK8_SHIFT (16) -#define GPR_GPR17_FLEXRAM_BANK8_MASK (3 << GPR_GPR17_FLEXRAM_BANK8_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK8_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK8_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK8_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK8_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK8_DTCM (2 << GPR_GPR17_FLEXRAM_BANK8_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK8_ITCM (3 << GPR_GPR17_FLEXRAM_BANK8_SHIFT) -#define GPR_GPR17_FLEXRAM_BANK9_SHIFT (18) -#define GPR_GPR17_FLEXRAM_BANK9_MASK (3 << GPR_GPR17_FLEXRAM_BANK9_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK9_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK9_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK9_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK9_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK9_DTCM (2 << GPR_GPR17_FLEXRAM_BANK9_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK9_ITCM (3 << GPR_GPR17_FLEXRAM_BANK9_SHIFT) -#define GPR_GPR17_FLEXRAM_BANK10_SHIFT (20) -#define GPR_GPR17_FLEXRAM_BANK10_MASK (3 << GPR_GPR17_FLEXRAM_BANK10_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK10_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK10_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK10_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK10_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK10_DTCM (2 << GPR_GPR17_FLEXRAM_BANK10_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK10_ITCM (3 << GPR_GPR17_FLEXRAM_BANK10_SHIFT) -#define GPR_GPR17_FLEXRAM_BANK11_SHIFT (22) -#define GPR_GPR17_FLEXRAM_BANK11_MASK (3 << GPR_GPR17_FLEXRAM_BANK11_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK11_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK11_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK11_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK11_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK11_DTCM (2 << GPR_GPR17_FLEXRAM_BANK11_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK11_ITCM (3 << GPR_GPR17_FLEXRAM_BANK11_SHIFT) -#define GPR_GPR17_FLEXRAM_BANK12_SHIFT (24) -#define GPR_GPR17_FLEXRAM_BANK12_MASK (3 << GPR_GPR17_FLEXRAM_BANK12_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK12_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK12_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK12_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK12_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK12_DTCM (2 << GPR_GPR17_FLEXRAM_BANK12_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK12_ITCM (3 << GPR_GPR17_FLEXRAM_BANK12_SHIFT) -#define GPR_GPR17_FLEXRAM_BANK13_SHIFT (26) -#define GPR_GPR17_FLEXRAM_BANK13_MASK (3 << GPR_GPR17_FLEXRAM_BANK13_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK13_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK13_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK13_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK13_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK13_DTCM (2 << GPR_GPR17_FLEXRAM_BANK13_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK13_ITCM (3 << GPR_GPR17_FLEXRAM_BANK13_SHIFT) -#define GPR_GPR17_FLEXRAM_BANK14_SHIFT (28) -#define GPR_GPR17_FLEXRAM_BANK14_MASK (3 << GPR_GPR17_FLEXRAM_BANK14_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK14_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK14_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK14_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK14_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK14_DTCM (2 << GPR_GPR17_FLEXRAM_BANK14_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK14_ITCM (3 << GPR_GPR17_FLEXRAM_BANK14_SHIFT) -#define GPR_GPR17_FLEXRAM_BANK15_SHIFT (30) -#define GPR_GPR17_FLEXRAM_BANK15_MASK (3 << GPR_GPR17_FLEXRAM_BANK15_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK15_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK15_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK15_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK15_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK15_DTCM (2 << GPR_GPR17_FLEXRAM_BANK15_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK15_ITCM (3 << GPR_GPR17_FLEXRAM_BANK15_SHIFT) - -/* General Purpose Register 18 (GPR18) */ - -#define GPR_GPR18_LOCK_M7_APC_AC_R0_BOT (1 << 0) -#define GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT (3) -#define GPR_GPR18_M7_APC_AC_R0_BOT_MASK (0x1fffffff << GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT) -#define GPR_GPR18_M7_APC_AC_R0_BOT(n) ((uint32_t)(n)) << GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT) - -/* General Purpose Register 19 (GPR19) */ - -#define GPR_GPR19_LOCK_M7_APC_AC_R0_TOP (1 << 0) -#define GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT (3) -#define GPR_GPR19_M7_APC_AC_R0_TOP_MASK (0x1fffffff << GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT) -#define GPR_GPR19_M7_APC_AC_R0_TOP(n) ((uint32_t)(n)) << GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT) - -/* General Purpose Register 20 (GPR20) */ - -#define GPR_GPR20_LOCK_M7_APC_AC_R1_BOT (1 << 0) -#define GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT (3) -#define GPR_GPR20_M7_APC_AC_R1_BOT_MASK (0x1fffffff << GPR_GPR18_M7_APC_AC_R1_BOT_SHIFT) -#define GPR_GPR20_M7_APC_AC_R1_BOT(n) ((uint32_t)(n)) << GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT) - -/* General Purpose Register 21 (GPR21) */ - -#define GPR_GPR21_LOCK_M7_APC_AC_R1_TOP (1 << 0) -#define GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT (3) -#define GPR_GPR21_M7_APC_AC_R1_TOP_MASK (0x1fffffff << GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT) -#define GPR_GPR21_M7_APC_AC_R1_TOP(n) ((uint32_t)(n)) << GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT) - -/* General Purpose Register 22 (GPR22) */ - -#define GPR_GPR22_LOCK_M7_APC_AC_R2_BOT (1 << 0) -#define GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT (3) -#define GPR_GPR22_M7_APC_AC_R2_BOT_MASK (0x1fffffff << GPR_GPR18_M7_APC_AC_R2_BOT_SHIFT) -#define GPR_GPR22_M7_APC_AC_R2_BOT(n) ((uint32_t)(n)) << GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT) - -/* General Purpose Register 23 (GPR23) */ - -#define GPR_GPR23_LOCK_M7_APC_AC_R2_TOP (1 << 0) -#define GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT (3) -#define GPR_GPR23_M7_APC_AC_R2_TOP_MASK (0x1fffffff << GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT) -#define GPR_GPR23_M7_APC_AC_R2_TOP(n) ((uint32_t)(n)) << GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT) - -/* General Purpose Register 24 (GPR24) */ - -#define GPR_GPR24_LOCK_M7_APC_AC_R3_BOT (1 << 0) -#define GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT (3) -#define GPR_GPR24_M7_APC_AC_R3_BOT_MASK (0x1fffffff << GPR_GPR18_M7_APC_AC_R3_BOT_SHIFT) -#define GPR_GPR24_M7_APC_AC_R3_BOT(n) ((uint32_t)(n)) << GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT) - -/* General Purpose Register 25 (GPR25) */ - -#define GPR_GPR25_LOCK_M7_APC_AC_R3_TOP (1 << 0) -#define GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT (3) -#define GPR_GPR25_M7_APC_AC_R3_TOP_MASK (0x1fffffff << GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT) -#define GPR_GPR25_M7_APC_AC_R3_TOP(n) ((uint32_t)(n)) << GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT) - -#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_IOMUXC_H */ diff --git a/arch/arm/src/imxrt/chip/rt105x/imxrt105x_memorymap.h b/arch/arm/src/imxrt/chip/rt105x/imxrt105x_memorymap.h deleted file mode 100644 index 1ab9d130d39..00000000000 --- a/arch/arm/src/imxrt/chip/rt105x/imxrt105x_memorymap.h +++ /dev/null @@ -1,258 +0,0 @@ -/************************************************************************************ - * arch/arm/src/imxrt/chip/rt105x/imxrt105x_memorymap.h - * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_MEMORYMAP_H -#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_MEMORYMAP_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* System memory map */ - -#define IMXRT_ITCM_BASE 0x00000000 /* 512KB ITCM */ - /* 0x00080000 512KB ITCM Reserved */ - /* 0x00100000 1MB ITCM Reserved */ -#define IMXRT_ROMCP_BASE 0x00200000 /* 96KB ROMCP */ - /* 0x00218000 416KB ROMCP Reserved */ - /* 0x00280000 1536KB Reserved */ - /* 0x00400000 124MB Reserved */ -#define IMXRT_FLEXSPI_BASE 0x08000000 /* 128MB FlexSPI (Aliased) */ -#define IMXRT_SEMCA_BASE 0x10000000 /* 256MB SEMC (Aliased) */ -#define IMXRT_DTCM_BASE 0x20000000 /* 512KB DTCM */ - /* 0x20080000 512KB DTCM Reserved */ - /* 0x20100000 1MB Reserved */ -#define IMXRT_OCRAM_BASE 0x20200000 /* 512KB OCRAM */ - /* 0x20280000 1536KB OCRAM Reserved */ - /* 0x20400000 252MB Reserved */ - /* 0x30000000 256MB Reserved */ -#define IMXRT_AIPS1_BASE 0x40000000 /* 1MB AIPS-1 */ -#define IMXRT_AIPS2_BASE 0x40100000 /* 1MB AIPS-2 */ -#define IMXRT_AIPS3_BASE 0x40200000 /* 1MB AIPS-3 */ -#define IMXRT_AIPS4_BASE 0x40300000 /* 1MB AIPS-4 */ - /* 40400000 12MB Reserved */ -#define IMXRT_MAINCNF_BASE 0x41000000 /* 1MB "main" configuration port */ -#define IMXRT_MCNF_BASE 0x41100000 /* 1MB "m" configuration port */ - /* 41200000 1MB Reserved for "per" GPV */ - /* 41300000 1MB Reserved for "ems" GPV */ -#define IMXRT_CPUCNF_BASE 0x41400000 /* 1MB "cpu" configuration port */ - /* 0x41500000 1MB GPV Reserved */ - /* 0x41600000 1MB GPV Reserved */ - /* 0x41700000 1MB GPV Reserved */ - /* 0x41800000 8MB Reserved */ - /* 0x42000000 32MB Reserved */ - /* 0x44000000 64MB Reserved */ - /* 0x48000000 384MB Reserved */ -#define IMXRT_FLEXCIPHER_BASE 0x60000000 /* 504MB FlexSPI/ FlexSPI ciphertext */ -#define IMXRT_FLEXSPITX_BASE 0x7f800000 /* 4MB FlexSPI TX FIFO */ -#define IMXRT_FLEXSPIRX_BASE 0x7fc00000 /* 4MB FlexSPI RX FIFO */ -#define IMXRT_EXTMEM_BASE 0x80000000 /* 1.5GB SEMC external memories shared memory space */ -#define IMXRT_CM7_BASE 0xe0000000 /* 1MB CM7 PPB */ - /* 0xe0100000 511MB Reserved */ - -/* AIPS-1 memory map */ - - /* 0x40000000 256KB Reserved */ - /* 0x40040000 240KB Reserved */ -#define IMXRT_AIPS1CNF_BASE 0x4007c000 /* 6KB AIPS-1 Configuration */ -#define IMXRT_DCDC_BASE 0x40080000 /* 16KB DCDC */ -#define IMXRT_PIT_BASE 0x40084000 /* 16KB PIT */ - /* 0x40088000 16KB Reserved */ - /* 0x4008c000 16KB Reserved */ -#define IMXRT_MTR_BASE 0x40090000 /* 16KB MTR */ -#define IMXRT_ACMP_BASE 0x40094000 /* 16KB ACMP */ - /* 0x40098000 16KB Reserved */ - /* 0x4009c000 16KB Reserved */ - /* 0x400a0000 16KB Reserved */ -#define IMXRT_IOMUXCSNVSGPR_BASE 0x400a4000 /* 16KB IOMUXC_SNVS_GPR */ -#define IMXRT_IOMUXCSNVS_BASE 0x400a8000 /* 16KB IOMUXC_SNVS */ -#define IMXRT_IOMUXCGPR_BASE 0x400ac000 /* 16KB IOMUXC_GPR */ -#define IMXRT_FLEXRAM_BASE 0x400b0000 /* 16KB CM7_MX6RT(FLEXRAM) */ -#define IMXRT_EWM_BASE 0x400b4000 /* 16KB EWM */ -#define IMXRT_WDOG1_BASE 0x400b8000 /* 16KB WDOG1 */ -#define IMXRT_WDOG3_BASE 0x400bc000 /* 16KB WDOG3 */ -#define IMXRT_GPIO5_BASE 0x400c0000 /* 16KB GPIO5 */ -#define IMXRT_ADC1_BASE 0x400c4000 /* 16KB ADC1 */ -#define IMXRT_ADC2_BASE 0x400c8000 /* 16KB ADC2 */ -#define IMXRT_TRNG_BASE 0x400cc000 /* 16KB TRNG */ -#define IMXRT_WDOG2_BASE 0x400d0000 /* 16KB WDOG2 */ -#define IMXRT_SNVSHP_BASE 0x400d4000 /* 16KB SNVS_HP */ -#define IMXRT_ANATOP_BASE 0x400d8000 /* 16KB ANATOP */ -#define IMXRT_CSU_BASE 0x400dc000 /* 16KB CSU */ - /* 0x400e0000 16KB Reserved */ - /* 0x400e4000 16KB Reserved */ -#define IMXRT_EDMA_BASE 0x400e8000 /* 16KB EDMA */ -#define IMXRT_DMAMUX_BASE 0x400ec000 /* 16KB DMA_CH_MUX */ - /* 400f0000 16KB Reserved */ -#define IMXRT_GPC_BASE 0x400f4000 /* 16KB GPC */ -#define IMXRT_SRC_BASE 0x400f8000 /* 16KB SRC */ -#define IMXRT_CCM_BASE 0x400fc000 /* 16KB CCM */ - -/* AIPS-2 memory map */ - - /* 0x40100000 256KB Reserved */ - /* 0x40140000 240KB Reserved */ -#define IMXRT_AIPS2CNF_BASE 0x4017c000 /* 16KB AIPS-2 Configuration */ -#define IMXRT_ROMCPC_BASE 0x40180000 /* 16KB ROMCP controller*/ -#define IMXRT_LPUART1_BASE 0x40184000 /* 16KB LPUART1 */ -#define IMXRT_LPUART2_BASE 0x40188000 /* 16KB LPUART2 */ -#define IMXRT_LPUART3_BASE 0x4018c000 /* 16KB LPUART3 */ -#define IMXRT_LPUART4_BASE 0x40190000 /* 16KB LPUART4 */ -#define IMXRT_LPUART5_BASE 0x40194000 /* 16KB LPUART5 */ -#define IMXRT_LPUART6_BASE 0x40198000 /* 16KB LPUART6 */ -#define IMXRT_LPUART7_BASE 0x4019c000 /* 16KB LPUART7 */ -#define IMXRT_LPUART8_BASE 0x401a0000 /* 16KB LPUART8 */ - /* 0x401a4000 16KB Reserved */ - /* 0x401a8000 16KB Reserved */ -#define IMXRT_FLEXIO1_BASE 0x401ac000 /* 16KB FlexIO1 */ -#define IMXRT_FLEXIO2_BASE 0x401b0000 /* 16KB FlexIO2 */ - /* 0x401b4000 16KB Reserved */ -#define IMXRT_GPIO1_BASE 0x401b8000 /* 16KB GPIO1 */ -#define IMXRT_GPIO2_BASE 0x401bc000 /* 16KB GPIO2 */ -#define IMXRT_GPIO3_BASE 0x401c0000 /* 16KB GPIO3 */ -#define IMXRT_GPIO4_BASE 0x401c4000 /* 16KB GPIO4 */ - /* 0x401c8000 16KB Reserved */ - /* 0x401cc000 16KB Reserved */ -#define IMXRT_CAN1_BASE 0x401d0000 /* 16KB CAN1 */ -#define IMXRT_CAN2_BASE 0x401d4000 /* 16KB CAN2 */ - /* 0x401d8000 16KB Reserved */ -#define IMXRT_QTIMER1_BASE 0x401dc000 /* 16KB QTimer1 */ -#define IMXRT_QTIMER2_BASE 0x401e0000 /* 16KB QTimer2 */ -#define IMXRT_QTIMER3_BASE 0x401e4000 /* 16KB QTimer3 */ -#define IMXRT_QTIMER4_BASE 0x401e8000 /* 16KB QTimer4 */ -#define IMXRT_GPT1_BASE 0x401ec000 /* 16KB GPT1 */ -#define IMXRT_GPT2_BASE 0x401f0000 /* 16KB GPT2 */ -#define IMXRT_OCOTP_BASE 0x401f4000 /* 16KB OCOTP */ -#define IMXRT_IOMUXC_BASE 0x401f8000 /* 16KB IOMUXC */ -#define IMXRT_KPP_BASE 0x401fc000 /* 16KB KPP */ - -/* AIPS-3 memory map */ - - /* 0x40200000 256KB Reserved */ - /* 0x40240000 240KB Reserved */ -#define IMXRT_AIOS3CNF_BASE 0x4027c000 /* 16KB AIPS-3 Configuration */ - /* 0x40280000 16KB Reserved */ - /* 0x40284000 16KB Reserved */ - /* 0x40288000 16KB Reserved */ - /* 0x4028c000 16KB Reserved */ - /* 0x40290000 16KB Reserved */ - /* 0x40294000 16KB Reserved */ - /* 0x40298000 16KB Reserved */ - /* 0x4029c000 16KB Reserved */ - /* 0x402a0000 16KB Reserved */ - /* 0x402a4000 16KB Reserved */ -#define IMXRT_FLEXSPIC_BASE 0x402a8000 /* 16KB FlexSPI controller */ - /* 0x402ac000 16KB Reserved */ - /* 0x402b0000 16KB Reserved */ -#define IMXRT_PXP_BASE 0x402b4000 /* 16KB PXP */ -#define IMXRT_LCDIF_BASE 0x402b8000 /* 16KB LCDIF */ -#define IMXRT_CSI_BASE 0x402bc000 /* 16KB CSI */ -#define IMXRT_USDHC1_BASE 0x402c0000 /* 16KB USDHC1 */ -#define IMXRT_USDHC2_BASE 0x402c4000 /* 16KB USDHC2 */ - /* 0x402c8000 16KB Reserved */ - /* 0x402cc000 16KB Reserved */ - /* 0x402d0000 16KB Reserved */ - /* 0x402d4000 16KB Reserved */ -#define IMXRT_ENET_BASE 0x402d8000 /* 16KB ENET */ -#define IMXRT_USBPL301_BASE 0x402dc000 /* 16KB USB(PL301) */ -#define IMXRT_USB_BASE 0x402e0000 /* 16KB USB(USB) */ - /* 0x402e4000 16KB Reserved */ - /* 0x402e8000 16KB Reserved */ - /* 0x402ec000 16KB Reserved */ -#define IMXRT_SEMC_BASE 0x402f0000 /* 16KB SEMC */ - /* 0x402f4000 16KB Reserved */ - /* 0x402f8000 16KB Reserved */ -#define IMXRT_DCP_BASE 0x402fc000 /* 16KB DCP */ - -/* AIPS-4 memory map */ - - /* 0x40300000 256KB Reserved */ - /* 0x40340000 240KB Reserved */ -#define IMXRT_AIPS4CNF_BASE 0x4037c000 /* 16KB AIPS-4 Configuration */ -#define IMXRT_SPDIF_BASE 0x40380000 /* 16KB SPDIF */ -#define IMXRT_SAI1_BASE 0x40384000 /* 16KB SAI1 */ -#define IMXRT_SAI2_BASE 0x40388000 /* 16KB SAI2 */ -#define IMXRT_SAI3_BASE 0x4038c000 /* 16KB SAI3 */ - /* 0x40390000 16KB Reserved */ -#define IMXRT_LPSPI1_BASE 0x40394000 /* 16KB LPSPI1 */ -#define IMXRT_LPSPI2_BASE 0x40398000 /* 16KB LPSPI2 */ -#define IMXRT_LPSPI3_BASE 0x4039c000 /* 16KB LPSPI3 */ -#define IMXRT_LPSPI4_BASE 0x403a0000 /* 16KB LPSPI4 */ - /* 0x403a4000 16KB Reserved */ - /* 0x403a8000 16KB Reserved */ - /* 0x403ac000 16KB Reserved */ -#define IMXRT_ADCETC_BASE 0x403b0000 /* 16KB ADC_ETC */ -#define IMXRT_AOI1_BASE 0x403b4000 /* 16KB AOI1 */ -#define IMXRT_AOI2_BASE 0x403b8000 /* 16KB AOI2 */ -#define IMXRT_XBAR1_BASE 0x403bc000 /* 16KB XBAR1 */ -#define IMXRT_XBAR2_BASE 0x403c0000 /* 16KB XBAR2 */ -#define IMXRT_XBAR3_BASE 0x403c4000 /* 16KB XBAR3 */ -#define IMXRT_ENC1_BASE 0x403c8000 /* 16KB ENC1 */ -#define IMXRT_ENC2_BASE 0x403cc000 /* 16KB ENC2 */ -#define IMXRT_ENC3_BASE 0x403d0000 /* 16KB ENC3 */ -#define IMXRT_ENC4_BASE 0x403d4000 /* 16KB ENC4 */ - /* 0x403d8000 16KB Reserved */ -#define IMXRT_FLEXPWM1_BASE 0x403dc000 /* 16KB FLEXPWM1 */ -#define IMXRT_FLEXPWM2_BASE 0x403e0000 /* 16KB FLEXPWM2 */ -#define IMXRT_FLEXPWM3_BASE 0x403e4000 /* 16KB FLEXPWM3 */ -#define IMXRT_FLEXPWM4_BASE 0x403e8000 /* 16KB FLEXPWM4 */ -#define IMXRT_BEE_BASE 0x403ec000 /* 16KB BEE */ -#define IMXRT_LPI2C1_BASE 0x403f0000 /* 16KB */ -#define IMXRT_LPI2C2_BASE 0x403f4000 /* 16KB LPI2C2 */ -#define IMXRT_LPI2C3_BASE 0x403f8000 /* 16KB LPI2C3 */ -#define IMXRT_LPI2C4_BASE 0x403fc000 /* 16KB LPI2C4 */ - -/* PPB memory map */ - -#define IMXRT_TPIU_BASE 0xe0040000 /* 4KB TPIU */ -#define IMXRT_ETM_BASE 0xe0041000 /* 4KB ETM */ -#define IMXRT_CTI_BASE 0xe0042000 /* 4KB CTI */ -#define IMXRT_TSGEN_BASE 0xe0043000 /* 4KB TSGEN */ -#define IMXRT_PPBRES_BASE 0xe0044000 /* 4KB PPB RES */ - /* 0xe0045000 236KB PPB Reserved */ -#define IMXRT_MCM_BASE 0xe0080000 /* 4KB MCM */ - /* 0xe0081000 444KB PPB Reserved */ - /* 0xe00f0000 52KB PPB Reserved */ -#define IMXRT_SYSROM_BASE 0xe00fd000 /* 4KB SYS ROM */ -#define IMXRT_PROCROM_BASE 0xe00fe000 /* 4KB Processor ROM */ -#define IMXRT_PPBROM_BASE 0xe00ff000 /* 4KB PPB ROM */ - -#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_MEMORYMAP_H */ diff --git a/arch/arm/src/imxrt/chip/rt105x/imxrt105x_pinmux.h b/arch/arm/src/imxrt/chip/rt105x/imxrt105x_pinmux.h deleted file mode 100644 index 59955e2183a..00000000000 --- a/arch/arm/src/imxrt/chip/rt105x/imxrt105x_pinmux.h +++ /dev/null @@ -1,1090 +0,0 @@ -/***************************************************************************************************** - * arch/arm/src/imxrt/chip/rt105x/imxrt105x_pinmux.h - * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *****************************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_PINMUX_H -#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_PINMUX_H - -/***************************************************************************************************** - * Included Files - *****************************************************************************************************/ - -#include -#include "chip/imxrt_iomuxc.h" - -/***************************************************************************************************** - * Pre-processor Definitions - *****************************************************************************************************/ - -/* Alternate Pin Functions. - * - * Alternative pin selections are provided with a numeric suffix like _1, _2, etc. Drivers, however, - * will use the pin selection without the numeric suffix. Additional definitions are required in the - * board.h file. For example, if LPUART1 CTS connects via the AD_B1_04 pin, then the following - * definition should appear in the board.h header file for that board: - * - * #define GPIO_LPUART3_CTS GPIO_LPUART3_CTS_1 - * - * The driver will then automatically configure to use the AD_B1_04 pin for LPUART1 CTS. - */ - -/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! - * Additional effort is required to select specific IOMUX options such as frequency, open-drain, - * push-pull, and pull-up/down! Just the basics are defined for most pins in this file. See the - * upper imxrt_gpio.h and imxrt_iomuxc.h header files for available definitions. - */ - -/* Analog Comparator (ACMP) */ - -#define GPIO_ACMP_OUT00 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_12_INDEX)) -#define GPIO_ACMP_OUT01 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_13_INDEX)) -#define GPIO_ACMP_OUT02 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_14_INDEX)) -#define GPIO_ACMP_OUT03 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_15_INDEX)) - -/* ARM */ - -#define GPIO_ARM_CM7_RXEV (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_15_INDEX)) -#define GPIO_ARM_CM7_TXEV (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_14_INDEX)) - -/* Clock Controller Module (CCM) */ - -#define GPIO_CCM_CLKO1 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_04_INDEX)) -#define GPIO_CCM_CLKO2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_05_INDEX)) -#define GPIO_CCM_PMIC_RDY (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_32_INDEX)) -#define GPIO_CCM_PMIC_READY_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_12_INDEX)) -#define GPIO_CCM_PMIC_READY_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX)) -#define GPIO_CCM_PMIC_READY_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX)) -#define GPIO_CCM_PMIC_READY_4 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_03_INDEX)) -#define GPIO_CCM_PMIC_VSTBY_REQ (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_PMIC_STBY_REQ_INDEX)) -#define GPIO_CCM_REF_EN (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_07_INDEX)) -#define GPIO_CCM_STOP (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_04_INDEX)) -#define GPIO_CCM_WAIT (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_02_INDEX)) - -/* CMOS Sensor Interface (CSI) */ - -#define GPIO_CSI_DATA00 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_10_INDEX)) -#define GPIO_CSI_DATA01 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_11_INDEX)) -#define GPIO_CSI_DATA02_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_11_INDEX)) -#define GPIO_CSI_DATA02_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_15_INDEX)) -#define GPIO_CSI_DATA03_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_10_INDEX)) -#define GPIO_CSI_DATA03_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_14_INDEX)) -#define GPIO_CSI_DATA04_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_09_INDEX)) -#define GPIO_CSI_DATA04_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_13_INDEX)) -#define GPIO_CSI_DATA05_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_08_INDEX)) -#define GPIO_CSI_DATA05_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_12_INDEX)) -#define GPIO_CSI_DATA06_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_07_INDEX)) -#define GPIO_CSI_DATA06_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_11_INDEX)) -#define GPIO_CSI_DATA07_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_06_INDEX)) -#define GPIO_CSI_DATA07_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_10_INDEX)) -#define GPIO_CSI_DATA08_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_05_INDEX)) -#define GPIO_CSI_DATA08_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX)) -#define GPIO_CSI_DATA09_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX)) -#define GPIO_CSI_DATA09_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX)) -#define GPIO_CSI_DATA10 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_09_INDEX)) -#define GPIO_CSI_DATA11 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_08_INDEX)) -#define GPIO_CSI_DATA12 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_07_INDEX)) -#define GPIO_CSI_DATA13 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_06_INDEX)) -#define GPIO_CSI_DATA14 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_05_INDEX)) -#define GPIO_CSI_DATA15 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_04_INDEX)) -#define GPIO_CSI_DATA16 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_37_INDEX)) -#define GPIO_CSI_DATA17 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_36_INDEX)) -#define GPIO_CSI_DATA18 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_35_INDEX)) -#define GPIO_CSI_DATA19 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_34_INDEX)) -#define GPIO_CSI_DATA20 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_33_INDEX)) -#define GPIO_CSI_DATA21 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_32_INDEX)) -#define GPIO_CSI_DATA22 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_31_INDEX)) -#define GPIO_CSI_DATA23 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_30_INDEX)) -#define GPIO_CSI_FIELD (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_38_INDEX)) -#define GPIO_CSI_HSYNC_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_14_INDEX)) -#define GPIO_CSI_HSYNC_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_15_INDEX)) -#define GPIO_CSI_HSYNC_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX)) -#define GPIO_CSI_MCLK_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_15_INDEX)) -#define GPIO_CSI_MCLK_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX)) -#define GPIO_CSI_PIXCLK_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_12_INDEX)) -#define GPIO_CSI_PIXCLK_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX)) -#define GPIO_CSI_VSYNC_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_13_INDEX)) -#define GPIO_CSI_VSYNC_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_14_INDEX)) -#define GPIO_CSI_VSYNC_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX)) - -/* Ethernet (ENET) */ - -#define GPIO_ENET_1588_EVENT0_IN_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_15_INDEX)) -#define GPIO_ENET_1588_EVENT0_IN_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_12_INDEX)) -#define GPIO_ENET_1588_EVENT0_IN_3 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_11_INDEX)) -#define GPIO_ENET_1588_EVENT0_OUT_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_14_INDEX)) -#define GPIO_ENET_1588_EVENT0_OUT_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_13_INDEX)) -#define GPIO_ENET_1588_EVENT0_OUT_3 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_10_INDEX)) -#define GPIO_ENET_1588_EVENT1_IN (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_13_INDEX)) -#define GPIO_ENET_1588_EVENT1_OUT (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_12_INDEX)) -#define GPIO_ENET_1588_EVENT2_IN (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX)) -#define GPIO_ENET_1588_EVENT2_OUT (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX)) -#define GPIO_ENET_1588_EVENT3_IN (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_08_INDEX)) -#define GPIO_ENET_1588_EVENT3_OUT (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_07_INDEX)) -#define GPIO_ENET_COL (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_11_INDEX)) -#define GPIO_ENET_CRS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_10_INDEX)) -#define GPIO_ENET_MDC_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_14_INDEX)) -#define GPIO_ENET_MDC_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX)) -#define GPIO_ENET_MDC_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_40_INDEX) | \ - IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ - IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) -#define GPIO_ENET_MDIO_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_15_INDEX)) -#define GPIO_ENET_MDIO_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX)) -#define GPIO_ENET_MDIO_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_41_INDEX) | \ - IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_OPENDRAIN | \ - IOMUX_SPEED_LOW | IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) -#define GPIO_ENET_RDATA00 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_20_INDEX)) -#define GPIO_ENET_RDATA01 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_19_INDEX)) -#define GPIO_ENET_REF_CLK_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_25_INDEX)) -#define GPIO_ENET_REF_CLK_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_10_INDEX) | \ - IOMUX_SLEW_FAST | IOMUX_DRIVE_40OHM | IOMUX_SPEED_LOW | \ - IOMUX_PULL_DOWN_100K | IOMUX_PULL_KEEP) -#define GPIO_ENET_RX_CLK (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_06_INDEX)) -#define GPIO_ENET_RX_DATA00 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_04_INDEX) | \ - IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ - IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) -#define GPIO_ENET_RX_DATA01 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_05_INDEX) | \ - IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ - IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) -#define GPIO_ENET_RX_DATA02 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_09_INDEX)) -#define GPIO_ENET_RX_DATA03 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_08_INDEX)) -#define GPIO_ENET_RX_EN_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_06_INDEX) | \ - IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ - IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) -#define GPIO_ENET_RX_EN_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_23_INDEX)) -#define GPIO_ENET_RX_ER_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_11_INDEX) | \ - IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ - IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) -#define GPIO_ENET_RX_ER_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_26_INDEX)) -#define GPIO_ENET_TDATA00 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_22_INDEX)) -#define GPIO_ENET_TDATA01 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_21_INDEX)) -#define GPIO_ENET_TX_CLK_1 (GPIO_PERIPH | GPIO_ALT6 | GPIO_SION_ENABLE | \ - GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_10_INDEX) | \ - IOMUX_SLEW_FAST | IOMUX_DRIVE_40OHM | IOMUX_SPEED_LOW | \ - IOMUX_PULL_DOWN_100K | IOMUX_PULL_KEEP) -#define GPIO_ENET_TX_CLK_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_25_INDEX)) -#define GPIO_ENET_TX_DATA00 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_07_INDEX) | \ - IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ - IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) -#define GPIO_ENET_TX_DATA01 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_08_INDEX) | \ - IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ - IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) -#define GPIO_ENET_TX_DATA02 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_05_INDEX)) -#define GPIO_ENET_TX_DATA03 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX)) -#define GPIO_ENET_TX_EN_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_09_INDEX) | \ - IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ - IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) -#define GPIO_ENET_TX_EN_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_24_INDEX)) -#define GPIO_ENET_TX_ER (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_07_INDEX)) - -/* External Watchdog Monitor (EWM) */ - -#define GPIO_EWM_OUT_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_11_INDEX)) -#define GPIO_EWM_OUT_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_13_INDEX)) -#define GPIO_EWM_OUT_3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_01_INDEX)) - -/* Flexible Controller Area Network (FLEXCAN) */ - -#define GPIO_FLEXCAN1_RX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX)) -#define GPIO_FLEXCAN1_RX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_03_INDEX)) -#define GPIO_FLEXCAN1_RX_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_18_INDEX)) -#define GPIO_FLEXCAN1_RX_4 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_03_INDEX)) -#define GPIO_FLEXCAN1_TX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX)) -#define GPIO_FLEXCAN1_TX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_02_INDEX)) -#define GPIO_FLEXCAN1_TX_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_17_INDEX)) -#define GPIO_FLEXCAN1_TX_4 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_02_INDEX)) - -#define GPIO_FLEXCAN2_RX_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_03_INDEX)) -#define GPIO_FLEXCAN2_RX_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_10_INDEX)) -#define GPIO_FLEXCAN2_RX_3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_15_INDEX)) -#define GPIO_FLEXCAN2_RX_4 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_09_INDEX)) -#define GPIO_FLEXCAN2_TX_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_02_INDEX)) -#define GPIO_FLEXCAN2_TX_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_09_INDEX)) -#define GPIO_FLEXCAN2_TX_3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_14_INDEX)) -#define GPIO_FLEXCAN2_TX_4 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_08_INDEX)) - -/* Flexible I/O (FlexIO) */ - -#define GPIO_FLEXIO1_FLEXIO00 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_00_INDEX)) -#define GPIO_FLEXIO1_FLEXIO01 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_01_INDEX)) -#define GPIO_FLEXIO1_FLEXIO02 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_02_INDEX)) -#define GPIO_FLEXIO1_FLEXIO03 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_03_INDEX)) -#define GPIO_FLEXIO1_FLEXIO04 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_04_INDEX)) -#define GPIO_FLEXIO1_FLEXIO05 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_05_INDEX)) -#define GPIO_FLEXIO1_FLEXIO06 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_06_INDEX)) -#define GPIO_FLEXIO1_FLEXIO07 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_07_INDEX)) -#define GPIO_FLEXIO1_FLEXIO08 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_08_INDEX)) -#define GPIO_FLEXIO1_FLEXIO09 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_09_INDEX)) -#define GPIO_FLEXIO1_FLEXIO10 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_10_INDEX)) -#define GPIO_FLEXIO1_FLEXIO11 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_11_INDEX)) -#define GPIO_FLEXIO1_FLEXIO12 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_26_INDEX)) -#define GPIO_FLEXIO1_FLEXIO13 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_27_INDEX)) -#define GPIO_FLEXIO1_FLEXIO14 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_28_INDEX)) -#define GPIO_FLEXIO1_FLEXIO15 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_29_INDEX)) - -#define GPIO_FLEXIO2_FLEXIO00 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_00_INDEX)) -#define GPIO_FLEXIO2_FLEXIO01 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_01_INDEX)) -#define GPIO_FLEXIO2_FLEXIO02 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_02_INDEX)) -#define GPIO_FLEXIO2_FLEXIO03 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_03_INDEX)) -#define GPIO_FLEXIO2_FLEXIO04 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_04_INDEX)) -#define GPIO_FLEXIO2_FLEXIO05 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_05_INDEX)) -#define GPIO_FLEXIO2_FLEXIO06 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_06_INDEX)) -#define GPIO_FLEXIO2_FLEXIO07 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_07_INDEX)) -#define GPIO_FLEXIO2_FLEXIO08 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_08_INDEX)) -#define GPIO_FLEXIO2_FLEXIO09 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_09_INDEX)) -#define GPIO_FLEXIO2_FLEXIO10 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_10_INDEX)) -#define GPIO_FLEXIO2_FLEXIO11 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_11_INDEX)) -#define GPIO_FLEXIO2_FLEXIO12 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_12_INDEX)) -#define GPIO_FLEXIO2_FLEXIO13 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_13_INDEX)) -#define GPIO_FLEXIO2_FLEXIO14 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_14_INDEX)) -#define GPIO_FLEXIO2_FLEXIO15 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_15_INDEX)) -#define GPIO_FLEXIO2_FLEXIO16 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_00_INDEX)) -#define GPIO_FLEXIO2_FLEXIO17 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_01_INDEX)) -#define GPIO_FLEXIO2_FLEXIO18 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_02_INDEX)) -#define GPIO_FLEXIO2_FLEXIO19 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_03_INDEX)) -#define GPIO_FLEXIO2_FLEXIO20 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_04_INDEX)) -#define GPIO_FLEXIO2_FLEXIO21 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_05_INDEX)) -#define GPIO_FLEXIO2_FLEXIO22 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_06_INDEX)) -#define GPIO_FLEXIO2_FLEXIO23 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_07_INDEX)) -#define GPIO_FLEXIO2_FLEXIO24 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_08_INDEX)) -#define GPIO_FLEXIO2_FLEXIO25 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_09_INDEX)) -#define GPIO_FLEXIO2_FLEXIO26 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_10_INDEX)) -#define GPIO_FLEXIO2_FLEXIO27 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_11_INDEX)) -#define GPIO_FLEXIO2_FLEXIO28 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_12_INDEX)) -#define GPIO_FLEXIO2_FLEXIO29 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_13_INDEX)) -#define GPIO_FLEXIO2_FLEXIO30 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_14_INDEX)) -#define GPIO_FLEXIO2_FLEXIO31 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_15_INDEX)) - -/* Enhanced Flex Pulse Width Modulator (eFlexPWM) */ - -#define GPIO_FLEXPWM1_PWMA00_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_23_INDEX)) -#define GPIO_FLEXPWM1_PWMA00_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_00_INDEX)) -#define GPIO_FLEXPWM1_PWMA01_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_25_INDEX)) -#define GPIO_FLEXPWM1_PWMA01_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_02_INDEX)) -#define GPIO_FLEXPWM1_PWMA02_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_27_INDEX)) -#define GPIO_FLEXPWM1_PWMA02_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_04_INDEX)) -#define GPIO_FLEXPWM1_PWMA03_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_10_INDEX)) -#define GPIO_FLEXPWM1_PWMA03_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_38_INDEX)) -#define GPIO_FLEXPWM1_PWMA03_3 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_00_INDEX)) -#define GPIO_FLEXPWM1_PWMA03_4 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_12_INDEX)) -#define GPIO_FLEXPWM1_PWMA03_5 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_00_INDEX)) -#define GPIO_FLEXPWM1_PWMB00_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_24_INDEX)) -#define GPIO_FLEXPWM1_PWMB00_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_01_INDEX)) -#define GPIO_FLEXPWM1_PWMB01_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_26_INDEX)) -#define GPIO_FLEXPWM1_PWMB01_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_03_INDEX)) -#define GPIO_FLEXPWM1_PWMB02_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_28_INDEX)) -#define GPIO_FLEXPWM1_PWMB02_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_05_INDEX)) -#define GPIO_FLEXPWM1_PWMB03_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_11_INDEX)) -#define GPIO_FLEXPWM1_PWMB03_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_39_INDEX)) -#define GPIO_FLEXPWM1_PWMB03_3 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_01_INDEX)) -#define GPIO_FLEXPWM1_PWMB03_4 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_13_INDEX)) -#define GPIO_FLEXPWM1_PWMB03_5 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_01_INDEX)) -#define GPIO_FLEXPWM1_PWMX00 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_02_INDEX)) -#define GPIO_FLEXPWM1_PWMX01 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_03_INDEX)) -#define GPIO_FLEXPWM1_PWMX02 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_12_INDEX)) -#define GPIO_FLEXPWM1_PWMX03 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_13_INDEX)) - -#define GPIO_FLEXPWM2_PWMA00_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_06_INDEX)) -#define GPIO_FLEXPWM2_PWMA00_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_06_INDEX)) -#define GPIO_FLEXPWM2_PWMA01_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_08_INDEX)) -#define GPIO_FLEXPWM2_PWMA01_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_08_INDEX)) -#define GPIO_FLEXPWM2_PWMA02_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_10_INDEX)) -#define GPIO_FLEXPWM2_PWMA02_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_10_INDEX)) -#define GPIO_FLEXPWM2_PWMA03_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_00_INDEX)) -#define GPIO_FLEXPWM2_PWMA03_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_09_INDEX)) -#define GPIO_FLEXPWM2_PWMA03_3 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_19_INDEX)) -#define GPIO_FLEXPWM2_PWMA03_4 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_02_INDEX)) -#define GPIO_FLEXPWM2_PWMA03_5 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_02_INDEX)) -#define GPIO_FLEXPWM2_PWMB00_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_07_INDEX)) -#define GPIO_FLEXPWM2_PWMB00_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_07_INDEX)) -#define GPIO_FLEXPWM2_PWMB01_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_09_INDEX)) -#define GPIO_FLEXPWM2_PWMB01_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_09_INDEX)) -#define GPIO_FLEXPWM2_PWMB02_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_11_INDEX)) -#define GPIO_FLEXPWM2_PWMB02_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_11_INDEX)) -#define GPIO_FLEXPWM2_PWMB03_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_01_INDEX)) -#define GPIO_FLEXPWM2_PWMB03_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_20_INDEX)) -#define GPIO_FLEXPWM2_PWMB03_3 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_03_INDEX)) -#define GPIO_FLEXPWM2_PWMB03_4 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_03_INDEX)) - -#define GPIO_FLEXPWM3_PWMA00 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_29_INDEX)) -#define GPIO_FLEXPWM3_PWMA01 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_31_INDEX)) -#define GPIO_FLEXPWM3_PWMA02 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_33_INDEX)) -#define GPIO_FLEXPWM3_PWMA03 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_21_INDEX)) -#define GPIO_FLEXPWM3_PWMB00 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_30_INDEX)) -#define GPIO_FLEXPWM3_PWMB01 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_32_INDEX)) -#define GPIO_FLEXPWM3_PWMB02 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_34_INDEX)) -#define GPIO_FLEXPWM3_PWMB03 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_22_INDEX)) - -#define GPIO_FLEXPWM4_PWMA00_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX)) -#define GPIO_FLEXPWM4_PWMA00_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_00_INDEX)) -#define GPIO_FLEXPWM4_PWMA01_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX)) -#define GPIO_FLEXPWM4_PWMA01_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_02_INDEX)) -#define GPIO_FLEXPWM4_PWMA02_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_14_INDEX)) -#define GPIO_FLEXPWM4_PWMA02_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_04_INDEX)) -#define GPIO_FLEXPWM4_PWMA03_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_15_INDEX)) -#define GPIO_FLEXPWM4_PWMA03_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_17_INDEX)) -#define GPIO_FLEXPWM4_PWMB00 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_01_INDEX)) -#define GPIO_FLEXPWM4_PWMB01 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_03_INDEX)) -#define GPIO_FLEXPWM4_PWMB02 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_05_INDEX)) -#define GPIO_FLEXPWM4_PWMB03 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_18_INDEX)) - -/* Flexible SPI (FlexSPI) */ - -#define GPIO_FLEXSPIA_DATA00_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_13_INDEX)) -#define GPIO_FLEXSPIA_DATA00_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_08_INDEX)) -#define GPIO_FLEXSPIA_DATA01_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_12_INDEX)) -#define GPIO_FLEXSPIA_DATA01_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_09_INDEX)) -#define GPIO_FLEXSPIA_DATA02_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_11_INDEX)) -#define GPIO_FLEXSPIA_DATA02_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_10_INDEX)) -#define GPIO_FLEXSPIA_DATA03_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_10_INDEX)) -#define GPIO_FLEXSPIA_DATA03_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_11_INDEX)) -#define GPIO_FLEXSPIA_DQS_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX)) -#define GPIO_FLEXSPIA_DQS_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_05_INDEX)) -#define GPIO_FLEXSPIA_SCLK_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_14_INDEX)) -#define GPIO_FLEXSPIA_SCLK_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_07_INDEX)) -#define GPIO_FLEXSPIA_SS0_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_15_INDEX)) -#define GPIO_FLEXSPIA_SS0_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_06_INDEX)) -#define GPIO_FLEXSPIA_SS1_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX)) -#define GPIO_FLEXSPIA_SS1_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_04_INDEX)) -#define GPIO_FLEXSPIA_SS1_3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_00_INDEX)) - -#define GPIO_FLEXSPIB_DATA00_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX)) -#define GPIO_FLEXSPIB_DATA00_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_03_INDEX)) -#define GPIO_FLEXSPIB_DATA01_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX)) -#define GPIO_FLEXSPIB_DATA01_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_02_INDEX)) -#define GPIO_FLEXSPIB_DATA02_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX)) -#define GPIO_FLEXSPIB_DATA02_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_01_INDEX)) -#define GPIO_FLEXSPIB_DATA03_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX)) -#define GPIO_FLEXSPIB_DATA03_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_00_INDEX)) -#define GPIO_FLEXSPIB_DQS (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_05_INDEX)) -#define GPIO_FLEXSPIB_SCLK (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_04_INDEX)) -#define GPIO_FLEXSPIB_SS0_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_04_INDEX)) -#define GPIO_FLEXSPIB_SS0_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_05_INDEX)) -#define GPIO_FLEXSPIB_SS1 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_01_INDEX)) - -/* GPIO */ - -#define GPIO_GPIO1_IO00 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_00_INDEX)) -#define GPIO_GPIO1_IO01 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_01_INDEX)) -#define GPIO_GPIO1_IO02 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_02_INDEX)) -#define GPIO_GPIO1_IO03 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_03_INDEX)) -#define GPIO_GPIO1_IO04 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX)) -#define GPIO_GPIO1_IO05 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_05_INDEX)) -#define GPIO_GPIO1_IO06 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_06_INDEX)) -#define GPIO_GPIO1_IO07 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_07_INDEX)) -#define GPIO_GPIO1_IO08 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_08_INDEX)) -#define GPIO_GPIO1_IO09 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_09_INDEX)) -#define GPIO_GPIO1_IO10 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_10_INDEX)) -#define GPIO_GPIO1_IO11 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_11_INDEX)) -#define GPIO_GPIO1_IO12 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_12_INDEX)) -#define GPIO_GPIO1_IO13 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_13_INDEX)) -#define GPIO_GPIO1_IO14 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_14_INDEX)) -#define GPIO_GPIO1_IO15 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_15_INDEX)) -#define GPIO_GPIO1_IO16 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX)) -#define GPIO_GPIO1_IO17 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX)) -#define GPIO_GPIO1_IO18 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX)) -#define GPIO_GPIO1_IO19 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX)) -#define GPIO_GPIO1_IO20 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX)) -#define GPIO_GPIO1_IO21 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX)) -#define GPIO_GPIO1_IO22 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX)) -#define GPIO_GPIO1_IO23 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX)) -#define GPIO_GPIO1_IO24 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX)) -#define GPIO_GPIO1_IO25 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX)) -#define GPIO_GPIO1_IO26 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_10_INDEX)) -#define GPIO_GPIO1_IO27 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_11_INDEX)) -#define GPIO_GPIO1_IO28 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_12_INDEX)) -#define GPIO_GPIO1_IO29 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_13_INDEX)) -#define GPIO_GPIO1_IO30 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_14_INDEX)) -#define GPIO_GPIO1_IO31 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_15_INDEX)) - -#define GPIO_GPIO2_IO00 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_00_INDEX)) -#define GPIO_GPIO2_IO01 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_01_INDEX)) -#define GPIO_GPIO2_IO02 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_02_INDEX)) -#define GPIO_GPIO2_IO03 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_03_INDEX)) -#define GPIO_GPIO2_IO04 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_04_INDEX)) -#define GPIO_GPIO2_IO05 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_05_INDEX)) -#define GPIO_GPIO2_IO06 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_06_INDEX)) -#define GPIO_GPIO2_IO07 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_07_INDEX)) -#define GPIO_GPIO2_IO08 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_08_INDEX)) -#define GPIO_GPIO2_IO09 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_09_INDEX)) -#define GPIO_GPIO2_IO10 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_10_INDEX)) -#define GPIO_GPIO2_IO11 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_11_INDEX)) -#define GPIO_GPIO2_IO12 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_12_INDEX)) -#define GPIO_GPIO2_IO13 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_13_INDEX)) -#define GPIO_GPIO2_IO14 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_14_INDEX)) -#define GPIO_GPIO2_IO15 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_15_INDEX)) -#define GPIO_GPIO2_IO16 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_00_INDEX)) -#define GPIO_GPIO2_IO17 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_01_INDEX)) -#define GPIO_GPIO2_IO18 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_02_INDEX)) -#define GPIO_GPIO2_IO19 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_03_INDEX)) -#define GPIO_GPIO2_IO20 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_04_INDEX)) -#define GPIO_GPIO2_IO21 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_05_INDEX)) -#define GPIO_GPIO2_IO22 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_06_INDEX)) -#define GPIO_GPIO2_IO23 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_07_INDEX)) -#define GPIO_GPIO2_IO24 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_08_INDEX)) -#define GPIO_GPIO2_IO25 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_09_INDEX)) -#define GPIO_GPIO2_IO26 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_10_INDEX)) -#define GPIO_GPIO2_IO27 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_11_INDEX)) -#define GPIO_GPIO2_IO28 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_12_INDEX)) -#define GPIO_GPIO2_IO29 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_13_INDEX)) -#define GPIO_GPIO2_IO30 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_14_INDEX)) -#define GPIO_GPIO2_IO31 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_15_INDEX)) - -#define GPIO_GPIO3_IO00 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_00_INDEX)) -#define GPIO_GPIO3_IO01 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_01_INDEX)) -#define GPIO_GPIO3_IO02 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_02_INDEX)) -#define GPIO_GPIO3_IO03 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_03_INDEX)) -#define GPIO_GPIO3_IO04 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_04_INDEX)) -#define GPIO_GPIO3_IO05 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_05_INDEX)) -#define GPIO_GPIO3_IO06 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_06_INDEX)) -#define GPIO_GPIO3_IO07 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_07_INDEX)) -#define GPIO_GPIO3_IO08 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_08_INDEX)) -#define GPIO_GPIO3_IO09 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_09_INDEX)) -#define GPIO_GPIO3_IO10 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_10_INDEX)) -#define GPIO_GPIO3_IO11 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_11_INDEX)) -#define GPIO_GPIO3_IO12 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_00_INDEX)) -#define GPIO_GPIO3_IO13 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_01_INDEX)) -#define GPIO_GPIO3_IO14 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_02_INDEX)) -#define GPIO_GPIO3_IO15 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_03_INDEX)) -#define GPIO_GPIO3_IO16 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_04_INDEX)) -#define GPIO_GPIO3_IO17 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_05_INDEX)) -#define GPIO_GPIO3_IO18 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_32_INDEX)) -#define GPIO_GPIO3_IO19 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_33_INDEX)) -#define GPIO_GPIO3_IO20 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_34_INDEX)) -#define GPIO_GPIO3_IO21 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_35_INDEX)) -#define GPIO_GPIO3_IO22 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_36_INDEX)) -#define GPIO_GPIO3_IO23 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_37_INDEX)) -#define GPIO_GPIO3_IO24 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_38_INDEX)) -#define GPIO_GPIO3_IO25 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_39_INDEX)) -#define GPIO_GPIO3_IO26 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_40_INDEX)) -#define GPIO_GPIO3_IO27 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_41_INDEX)) - -#define GPIO_GPIO4_IO00 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_00_INDEX)) -#define GPIO_GPIO4_IO01 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_01_INDEX)) -#define GPIO_GPIO4_IO02 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_02_INDEX)) -#define GPIO_GPIO4_IO03 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_03_INDEX)) -#define GPIO_GPIO4_IO04 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_04_INDEX)) -#define GPIO_GPIO4_IO05 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_05_INDEX)) -#define GPIO_GPIO4_IO06 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_06_INDEX)) -#define GPIO_GPIO4_IO07 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_07_INDEX)) -#define GPIO_GPIO4_IO08 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_08_INDEX)) -#define GPIO_GPIO4_IO09 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_09_INDEX)) -#define GPIO_GPIO4_IO10 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_10_INDEX)) -#define GPIO_GPIO4_IO11 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_11_INDEX)) -#define GPIO_GPIO4_IO12 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_12_INDEX)) -#define GPIO_GPIO4_IO13 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_13_INDEX)) -#define GPIO_GPIO4_IO14 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_14_INDEX)) -#define GPIO_GPIO4_IO15 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_15_INDEX)) -#define GPIO_GPIO4_IO16 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_16_INDEX)) -#define GPIO_GPIO4_IO17 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_17_INDEX)) -#define GPIO_GPIO4_IO18 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_18_INDEX)) -#define GPIO_GPIO4_IO19 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_19_INDEX)) -#define GPIO_GPIO4_IO20 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_20_INDEX)) -#define GPIO_GPIO4_IO21 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_21_INDEX)) -#define GPIO_GPIO4_IO22 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_22_INDEX)) -#define GPIO_GPIO4_IO23 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_23_INDEX)) -#define GPIO_GPIO4_IO24 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_24_INDEX)) -#define GPIO_GPIO4_IO25 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_25_INDEX)) -#define GPIO_GPIO4_IO26 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_26_INDEX)) -#define GPIO_GPIO4_IO27 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_27_INDEX)) -#define GPIO_GPIO4_IO28 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_28_INDEX)) -#define GPIO_GPIO4_IO29 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_29_INDEX)) -#define GPIO_GPIO4_IO30 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_30_INDEX)) -#define GPIO_GPIO4_IO31 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_31_INDEX)) - -#define GPIO_GPIO5_IO00 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_WAKEUP_INDEX)) -#define GPIO_GPIO5_IO01 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_PMIC_ON_REQ_INDEX)) -#define GPIO_GPIO5_IO02 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_PMIC_STBY_REQ_INDEX)) - -/* General Purpose Timer (GPT) */ - -#define GPIO_GPT1_CAPTURE1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_24_INDEX)) -#define GPIO_GPT1_CAPTURE2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_23_INDEX)) -#define GPIO_GPT1_CLK (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_13_INDEX)) -#define GPIO_GPT1_COMPARE1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_35_INDEX)) -#define GPIO_GPT1_COMPARE2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_36_INDEX)) -#define GPIO_GPT1_COMPARE3 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_37_INDEX)) - -#define GPIO_GPT2_CAPTURE1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_41_INDEX)) -#define GPIO_GPT2_CAPTURE2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_40_INDEX)) -#define GPIO_GPT2_CLK (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_09_INDEX)) -#define GPIO_GPT2_COMPARE2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_07_INDEX)) -#define GPIO_GPT2_COMPARE3 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_08_INDEX)) - -/* JTAG */ - -#define GPIO_JTAG_ACTIVE (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_03_INDEX)) -#define GPIO_JTAG_DE (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_01_INDEX)) -#define GPIO_JTAG_DONE (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_00_INDEX)) -#define GPIO_JTAG_FAIL (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_02_INDEX)) -#define GPIO_JTAG_MOD (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_08_INDEX)) -#define GPIO_JTAG_TCK (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_07_INDEX)) -#define GPIO_JTAG_TDI (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_09_INDEX)) -#define GPIO_JTAG_TDO (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_10_INDEX)) -#define GPIO_JTAG_TRSTB (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_11_INDEX)) - -/* Keypad Port (KPP) */ - -#define GPIO_KPP_COL00 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_15_INDEX)) -#define GPIO_KPP_COL01 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_13_INDEX)) -#define GPIO_KPP_COL02 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_11_INDEX)) -#define GPIO_KPP_COL03 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX)) -#define GPIO_KPP_COL04 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX)) -#define GPIO_KPP_COL05 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX)) -#define GPIO_KPP_COL06 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX)) -#define GPIO_KPP_COL07 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX)) -#define GPIO_KPP_ROW00 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_14_INDEX)) -#define GPIO_KPP_ROW01 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_12_INDEX)) -#define GPIO_KPP_ROW02 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_10_INDEX)) -#define GPIO_KPP_ROW03 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX)) -#define GPIO_KPP_ROW04 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX)) -#define GPIO_KPP_ROW05 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX)) -#define GPIO_KPP_ROW06 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX)) -#define GPIO_KPP_ROW07 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX)) - -/* LCD */ - -#define IOMUX_LCD (IOMUX_PULL_UP_100K | IOMUX_CMOS_OUTPUT | IOMUX_DRIVE_40OHM | \ - IOMUX_SLEW_SLOW | IOMUX_SPEED_MEDIUM | IOMUX_SCHMITT_TRIGGER) - -#define GPIO_LCD_CLK (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_00_INDEX) | IOMUX_LCD) -#define GPIO_LCD_DATA00 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_04_INDEX) | IOMUX_LCD) -#define GPIO_LCD_DATA01 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_05_INDEX) | IOMUX_LCD) -#define GPIO_LCD_DATA02 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_06_INDEX) | IOMUX_LCD) -#define GPIO_LCD_DATA03 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_07_INDEX) | IOMUX_LCD) -#define GPIO_LCD_DATA04 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_08_INDEX) | IOMUX_LCD) -#define GPIO_LCD_DATA05 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_09_INDEX) | IOMUX_LCD) -#define GPIO_LCD_DATA06 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_10_INDEX) | IOMUX_LCD) -#define GPIO_LCD_DATA07 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_11_INDEX) | IOMUX_LCD) -#define GPIO_LCD_DATA08 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_12_INDEX) | IOMUX_LCD) -#define GPIO_LCD_DATA09 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_13_INDEX) | IOMUX_LCD) -#define GPIO_LCD_DATA10 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_14_INDEX) | IOMUX_LCD) -#define GPIO_LCD_DATA11 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_15_INDEX) | IOMUX_LCD) -#define GPIO_LCD_DATA12 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_00_INDEX) | IOMUX_LCD) -#define GPIO_LCD_DATA13 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_01_INDEX) | IOMUX_LCD) -#define GPIO_LCD_DATA14 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_02_INDEX) | IOMUX_LCD) -#define GPIO_LCD_DATA15 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_03_INDEX) | IOMUX_LCD) -#define GPIO_LCD_DATA16 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_04_INDEX) | IOMUX_LCD) -#define GPIO_LCD_DATA17 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_05_INDEX) | IOMUX_LCD) -#define GPIO_LCD_DATA18 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_06_INDEX) | IOMUX_LCD) -#define GPIO_LCD_DATA19 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_07_INDEX) | IOMUX_LCD) -#define GPIO_LCD_DATA20 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_08_INDEX) | IOMUX_LCD) -#define GPIO_LCD_DATA21 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_09_INDEX) | IOMUX_LCD) -#define GPIO_LCD_DATA22 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_10_INDEX) | IOMUX_LCD) -#define GPIO_LCD_DATA23 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_11_INDEX) | IOMUX_LCD) -#define GPIO_LCD_ENABLE (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_01_INDEX) | IOMUX_LCD) -#define GPIO_LCD_HSYNC (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_02_INDEX) | IOMUX_LCD) -#define GPIO_LCD_VSYNC (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_03_INDEX) | IOMUX_LCD) - -/* Low Power Inter-Integrated Circuit (LPI2C) */ - -#define GPIO_LPI2C1_HREQ (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_02_INDEX)) -#define GPIO_LPI2C1_SCL_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_04_INDEX)) -#define GPIO_LPI2C1_SCL_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX) | \ - GPIO_SION_ENABLE | IOMUX_PULL_UP_22K | IOMUX_OPENDRAIN | \ - IOMUX_SPEED_MEDIUM | IOMUX_DRIVE_33OHM) -#define GPIO_LPI2C1_SCLS (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_00_INDEX)) -#define GPIO_LPI2C1_SDA_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_05_INDEX)) -#define GPIO_LPI2C1_SDA_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX) | \ - GPIO_SION_ENABLE | IOMUX_PULL_UP_22K | IOMUX_OPENDRAIN | \ - IOMUX_SPEED_MEDIUM | IOMUX_DRIVE_33OHM) -#define GPIO_LPI2C1_SDAS (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_01_INDEX)) - -#define GPIO_LPI2C2_SCL_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_04_INDEX)) -#define GPIO_LPI2C2_SCL_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_11_INDEX)) -#define GPIO_LPI2C2_SDA_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_05_INDEX)) -#define GPIO_LPI2C2_SDA_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_10_INDEX)) - -#define GPIO_LPI2C3_SCL_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX)) -#define GPIO_LPI2C3_SCL_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_22_INDEX) | \ - GPIO_SION_ENABLE | IOMUX_OPENDRAIN | IOMUX_SPEED_MEDIUM | IOMUX_DRIVE_33OHM) -#define GPIO_LPI2C3_SCL_3 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_00_INDEX)) -#define GPIO_LPI2C3_SDA_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX)) -#define GPIO_LPI2C3_SDA_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_21_INDEX) | \ - GPIO_SION_ENABLE | IOMUX_OPENDRAIN | IOMUX_SPEED_MEDIUM | IOMUX_DRIVE_33OHM) -#define GPIO_LPI2C3_SDA_3 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_01_INDEX)) - -#define GPIO_LPI2C4_SCL_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_12_INDEX)) -#define GPIO_LPI2C4_SCL_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_12_INDEX) | \ - GPIO_SION_ENABLE | IOMUX_OPENDRAIN | IOMUX_SPEED_MEDIUM | IOMUX_DRIVE_33OHM) -#define GPIO_LPI2C4_SDA_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_13_INDEX)) -#define GPIO_LPI2C4_SDA_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_11_INDEX) | \ - GPIO_SION_ENABLE | IOMUX_OPENDRAIN | IOMUX_SPEED_MEDIUM | IOMUX_DRIVE_33OHM) - -/* Low Power Serial Peripheral Interface (LPSPI) */ - -#define IOMUX_LPSPI (IOMUX_PULL_UP_100K | IOMUX_CMOS_OUTPUT | IOMUX_DRIVE_40OHM | \ - IOMUX_SLEW_FAST | IOMUX_SPEED_MEDIUM) - -#define GPIO_LPSPI1_PCS0_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_30_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI1_PCS0_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_01_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI1_PCS1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_31_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI1_PCS2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_40_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI1_PCS3 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_41_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI1_SCK_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_27_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI1_SCK_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_00_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI1_SDI_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_29_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI1_SDI_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_03_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI1_SDO_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_28_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI1_SDO_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_02_INDEX) | IOMUX_LPSPI) - -#define GPIO_LPSPI2_PCS0_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_01_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI2_PCS0_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_06_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI2_PCS1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_14_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI2_PCS2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_10_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI2_PCS3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_11_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI2_SCK_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_00_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI2_SCK_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_07_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI2_SDI_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_03_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI2_SDI_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_09_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI2_SDO_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_02_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI2_SDO_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_08_INDEX) | IOMUX_LPSPI) - -#define GPIO_LPSPI3_PCS0_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_12_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI3_PCS0_2 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_03_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI3_PCS1 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI3_PCS2 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_05_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI3_PCS3 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_06_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI3_SCK_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_15_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI3_SCK_2 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_00_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI3_SDI_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_13_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI3_SDI_2 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_02_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI3_SDO_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_14_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI3_SDO_2 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_01_INDEX) | IOMUX_LPSPI) - -#define GPIO_LPSPI4_PCS0_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_04_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI4_PCS0_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_00_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI4_PCS1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_03_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI4_PCS2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_02_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI4_PCS3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_11_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI4_SCK_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_07_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI4_SCK_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_03_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI4_SDI_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_05_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI4_SDI_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_01_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI4_SDO_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_06_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI4_SDO_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_02_INDEX) | IOMUX_LPSPI) - -/* Low Power Universal Asynchronous Receiver/Transmitter (LPUART) */ - -#define IOMUX_UART (IOMUX_PULL_UP_100K | IOMUX_CMOS_OUTPUT | IOMUX_DRIVE_40OHM | \ - IOMUX_SLEW_FAST | IOMUX_SPEED_MEDIUM | IOMUX_SCHMITT_TRIGGER) - -#define GPIO_LPUART1_CTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_14_INDEX)) -#define GPIO_LPUART1_RTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_15_INDEX)) -#define GPIO_LPUART1_RX (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_13_INDEX) | IOMUX_UART) -#define GPIO_LPUART1_TX (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_12_INDEX) | IOMUX_UART) - -#define GPIO_LPUART2_CTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX)) -#define GPIO_LPUART2_RTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX)) -#define GPIO_LPUART2_RX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX) | IOMUX_UART) -#define GPIO_LPUART2_RX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_10_INDEX) | IOMUX_UART) -#define GPIO_LPUART2_TX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX) | IOMUX_UART) -#define GPIO_LPUART2_TX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_11_INDEX) | IOMUX_UART) - -#define GPIO_LPUART3_CTS_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX)) -#define GPIO_LPUART3_CTS_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_15_INDEX)) -#define GPIO_LPUART3_RTS_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX)) -#define GPIO_LPUART3_RTS_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_16_INDEX)) -#define GPIO_LPUART3_RX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX) | IOMUX_UART) -#define GPIO_LPUART3_RX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_14_INDEX) | IOMUX_UART) -#define GPIO_LPUART3_RX_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_09_INDEX) | IOMUX_UART) -#define GPIO_LPUART3_TX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX) | IOMUX_UART) -#define GPIO_LPUART3_TX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_13_INDEX) | IOMUX_UART) -#define GPIO_LPUART3_TX_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_08_INDEX) | IOMUX_UART) - -#define GPIO_LPUART4_CTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_17_INDEX)) -#define GPIO_LPUART4_RTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_18_INDEX)) -#define GPIO_LPUART4_RX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_01_INDEX) | IOMUX_UART) -#define GPIO_LPUART4_RX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_20_INDEX) | IOMUX_UART) -#define GPIO_LPUART4_RX_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_01_INDEX) | IOMUX_UART) -#define GPIO_LPUART4_TX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_00_INDEX) | IOMUX_UART) -#define GPIO_LPUART4_TX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_19_INDEX) | IOMUX_UART) -#define GPIO_LPUART4_TX_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_00_INDEX) | IOMUX_UART) - -#define GPIO_LPUART5_CTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_28_INDEX)) -#define GPIO_LPUART5_RTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_27_INDEX)) -#define GPIO_LPUART5_RX_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_13_INDEX) | IOMUX_UART) -#define GPIO_LPUART5_RX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_24_INDEX)) -#define GPIO_LPUART5_TX_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_12_INDEX) | IOMUX_UART) -#define GPIO_LPUART5_TX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_23_INDEX)) - -#define GPIO_LPUART6_CTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_30_INDEX)) -#define GPIO_LPUART6_RTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_29_INDEX)) -#define GPIO_LPUART6_RX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_03_INDEX) | IOMUX_UART) -#define GPIO_LPUART6_RX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_26_INDEX) | IOMUX_UART) -#define GPIO_LPUART6_TX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_02_INDEX) | IOMUX_UART) -#define GPIO_LPUART6_TX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_25_INDEX) | IOMUX_UART) -#define GPIO_LPUART6_TX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_25_INDEX) | IOMUX_UART) - -#define GPIO_LPUART7_CTS_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_06_INDEX)) -#define GPIO_LPUART7_RTS_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_07_INDEX)) -#define GPIO_LPUART7_RX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_32_INDEX)) -#define GPIO_LPUART7_RX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_09_INDEX)) -#define GPIO_LPUART7_TX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_31_INDEX)) -#define GPIO_LPUART7_TX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_08_INDEX)) - -#define GPIO_LPUART8_CTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_02_INDEX)) -#define GPIO_LPUART8_RTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_03_INDEX)) -#define GPIO_LPUART8_RX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_11_INDEX) | IOMUX_UART) -#define GPIO_LPUART8_RX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_39_INDEX) | IOMUX_UART) -#define GPIO_LPUART8_RX_3 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_05_INDEX) | IOMUX_UART) -#define GPIO_LPUART8_TX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_10_INDEX) | IOMUX_UART) -#define GPIO_LPUART8_TX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_38_INDEX) | IOMUX_UART) -#define GPIO_LPUART8_TX_3 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_04_INDEX) | IOMUX_UART) - -/* Medium Quality Sound (MQS) */ - -#define GPIO_MQS_LEFT_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_05_INDEX)) -#define GPIO_MQS_LEFT_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_01_INDEX)) -#define GPIO_MQS_LEFT_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_14_INDEX)) -#define GPIO_MQS_RIGHT_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX)) -#define GPIO_MQS_RIGHT_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_00_INDEX)) -#define GPIO_MQS_RIGHT_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_13_INDEX)) - -/* NMI */ - -#define GPIO_NMI_GLUE_NMI (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_WAKEUP_INDEX)) - -/* Periodic Interrupt Timer (PIT) */ - -#define GPIO_PIT_TRIGGER00 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX)) - -/* Quad Timer (QTimer) */ - -#define GPIO_QTIMER1_TIMER0 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_00_INDEX)) -#define GPIO_QTIMER1_TIMER1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_01_INDEX)) -#define GPIO_QTIMER1_TIMER2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_02_INDEX)) -#define GPIO_QTIMER1_TIMER3 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_08_INDEX)) - -#define GPIO_QTIMER2_TIMER0_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_03_INDEX)) -#define GPIO_QTIMER2_TIMER0_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_19_INDEX)) -#define GPIO_QTIMER2_TIMER1_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_04_INDEX)) -#define GPIO_QTIMER2_TIMER1_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_20_INDEX)) -#define GPIO_QTIMER2_TIMER2_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_05_INDEX)) -#define GPIO_QTIMER2_TIMER2_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_21_INDEX)) -#define GPIO_QTIMER2_TIMER3_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_09_INDEX)) -#define GPIO_QTIMER2_TIMER3_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_22_INDEX)) - -#define GPIO_QTIMER3_TIMER0_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX)) -#define GPIO_QTIMER3_TIMER0_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_06_INDEX)) -#define GPIO_QTIMER3_TIMER0_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_15_INDEX)) -#define GPIO_QTIMER3_TIMER1_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX)) -#define GPIO_QTIMER3_TIMER1_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_07_INDEX)) -#define GPIO_QTIMER3_TIMER1_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_16_INDEX)) -#define GPIO_QTIMER3_TIMER2_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX)) -#define GPIO_QTIMER3_TIMER2_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_08_INDEX)) -#define GPIO_QTIMER3_TIMER2_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_17_INDEX)) -#define GPIO_QTIMER3_TIMER3_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX)) -#define GPIO_QTIMER3_TIMER3_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_10_INDEX)) -#define GPIO_QTIMER3_TIMER3_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_18_INDEX)) - -#define GPIO_QTIMER4_TIMER0 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_09_INDEX)) -#define GPIO_QTIMER4_TIMER1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_10_INDEX)) -#define GPIO_QTIMER4_TIMER2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_11_INDEX)) -#define GPIO_QTIMER4_TIMER3 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_11_INDEX)) - -/* XTALOSC Reference Clock */ - -#define GPIO_REF_CLK_24M_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_01_INDEX)) -#define GPIO_REF_CLK_24M_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_03_INDEX)) -#define GPIO_REF_CLK_24M_3 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_13_INDEX)) -#define GPIO_REF_CLK_32K (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_00_INDEX)) - -/* Synchronous Audio Interface (SAI) */ - -#define GPIO_SAI1_MCLK_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX)) -#define GPIO_SAI1_MCLK_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_13_INDEX)) -#define GPIO_SAI1_MCLK_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_03_INDEX)) -#define GPIO_SAI1_RX_BCLK_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_11_INDEX)) -#define GPIO_SAI1_RX_BCLK_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_15_INDEX)) -#define GPIO_SAI1_RX_BCLK_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_05_INDEX)) -#define GPIO_SAI1_RX_DATA00_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_12_INDEX)) -#define GPIO_SAI1_RX_DATA00_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_00_INDEX)) -#define GPIO_SAI1_RX_DATA00_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_06_INDEX)) -#define GPIO_SAI1_RX_SYNC_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_10_INDEX)) -#define GPIO_SAI1_RX_SYNC_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_14_INDEX)) -#define GPIO_SAI1_RX_SYNC_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_04_INDEX)) -#define GPIO_SAI1_TX_BCLK_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_14_INDEX)) -#define GPIO_SAI1_TX_BCLK_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_02_INDEX)) -#define GPIO_SAI1_TX_BCLK_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_08_INDEX)) -#define GPIO_SAI1_TX_DATA00_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_13_INDEX)) -#define GPIO_SAI1_TX_DATA00_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_01_INDEX)) -#define GPIO_SAI1_TX_DATA00_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_07_INDEX)) -#define GPIO_SAI1_TX_DATA01_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_12_INDEX)) -#define GPIO_SAI1_TX_DATA01_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_02_INDEX)) -#define GPIO_SAI1_TX_DATA02_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_11_INDEX)) -#define GPIO_SAI1_TX_DATA02_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_01_INDEX)) -#define GPIO_SAI1_TX_DATA03_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_10_INDEX)) -#define GPIO_SAI1_TX_DATA03_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_00_INDEX)) -#define GPIO_SAI1_TX_SYNC_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_15_INDEX)) -#define GPIO_SAI1_TX_SYNC_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_03_INDEX)) -#define GPIO_SAI1_TX_SYNC_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_09_INDEX)) - -#define GPIO_SAI2_MCLK_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_07_INDEX)) -#define GPIO_SAI2_MCLK_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_10_INDEX)) -#define GPIO_SAI2_RX_BCLK_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_10_INDEX)) -#define GPIO_SAI2_RX_BCLK_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_06_INDEX)) -#define GPIO_SAI2_RX_DATA_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_08_INDEX)) -#define GPIO_SAI2_RX_DATA_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_08_INDEX)) -#define GPIO_SAI2_RX_SYNC_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_09_INDEX)) -#define GPIO_SAI2_RX_SYNC_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_07_INDEX)) -#define GPIO_SAI2_TX_BCLK_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_06_INDEX)) -#define GPIO_SAI2_TX_BCLK_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_05_INDEX)) -#define GPIO_SAI2_TX_DATA_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_04_INDEX)) -#define GPIO_SAI2_TX_DATA_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_09_INDEX)) -#define GPIO_SAI2_TX_SYNC_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_05_INDEX)) -#define GPIO_SAI2_TX_SYNC_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX)) - -#define GPIO_SAI3_MCLK (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_37_INDEX)) -#define GPIO_SAI3_RX_BCLK (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_35_INDEX)) -#define GPIO_SAI3_RX_DATA (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_33_INDEX)) -#define GPIO_SAI3_RX_SYNC (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_34_INDEX)) -#define GPIO_SAI3_TX_BCLK (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_38_INDEX)) -#define GPIO_SAI3_TX_DATA (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_36_INDEX)) -#define GPIO_SAI3_TX_SYNC (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_39_INDEX)) - -/* Smart External Memory Controller (SEMC) */ - -#define GPIO_SEMC_ADDR00 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_09_INDEX)) -#define GPIO_SEMC_ADDR01 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_10_INDEX)) -#define GPIO_SEMC_ADDR02 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_11_INDEX)) -#define GPIO_SEMC_ADDR03 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_12_INDEX)) -#define GPIO_SEMC_ADDR04 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_13_INDEX)) -#define GPIO_SEMC_ADDR05 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_14_INDEX)) -#define GPIO_SEMC_ADDR06 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_15_INDEX)) -#define GPIO_SEMC_ADDR07 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_16_INDEX)) -#define GPIO_SEMC_ADDR08 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_17_INDEX)) -#define GPIO_SEMC_ADDR09 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_18_INDEX)) -#define GPIO_SEMC_ADDR10 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_23_INDEX)) -#define GPIO_SEMC_ADDR11 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_19_INDEX)) -#define GPIO_SEMC_ADDR12 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_20_INDEX)) -#define GPIO_SEMC_BA0 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_21_INDEX)) -#define GPIO_SEMC_BA1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_22_INDEX)) -#define GPIO_SEMC_CAS (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_24_INDEX)) -#define GPIO_SEMC_CKE (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_27_INDEX)) -#define GPIO_SEMC_CLK (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_26_INDEX)) -#define GPIO_SEMC_CS0 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_29_INDEX)) -#define GPIO_SEMC_CSX00 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_41_INDEX)) -#define GPIO_SEMC_CSX01_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_07_INDEX)) -#define GPIO_SEMC_CSX01_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_00_INDEX)) -#define GPIO_SEMC_CSX02_1 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_01_INDEX)) -#define GPIO_SEMC_CSX02_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_08_INDEX)) -#define GPIO_SEMC_CSX03 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_02_INDEX)) -#define GPIO_SEMC_DATA00 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_00_INDEX)) -#define GPIO_SEMC_DATA01 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_01_INDEX)) -#define GPIO_SEMC_DATA02 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_02_INDEX)) -#define GPIO_SEMC_DATA03 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_03_INDEX)) -#define GPIO_SEMC_DATA04 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_04_INDEX)) -#define GPIO_SEMC_DATA05 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_05_INDEX)) -#define GPIO_SEMC_DATA06 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_06_INDEX)) -#define GPIO_SEMC_DATA07 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_07_INDEX)) -#define GPIO_SEMC_DATA08 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_30_INDEX)) -#define GPIO_SEMC_DATA09 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_31_INDEX)) -#define GPIO_SEMC_DATA10 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_32_INDEX)) -#define GPIO_SEMC_DATA11 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_33_INDEX)) -#define GPIO_SEMC_DATA12 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_34_INDEX)) -#define GPIO_SEMC_DATA13 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_35_INDEX)) -#define GPIO_SEMC_DATA14 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_36_INDEX)) -#define GPIO_SEMC_DATA15 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_37_INDEX)) -#define GPIO_SEMC_DM00 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_08_INDEX)) -#define GPIO_SEMC_DM01 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_38_INDEX)) -#define GPIO_SEMC_DQS (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_39_INDEX)) -#define GPIO_SEMC_RAS (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_25_INDEX)) -#define GPIO_SEMC_RDY (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_40_INDEX)) -#define GPIO_SEMC_WE (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_28_INDEX)) - -/* Secure Non-Volatile Storage (SNVS) */ - -#define GPIO_SNVS_LP_PMIC_ON_REQ (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_PMIC_ON_REQ_INDEX)) -#define GPIO_SNVS_VIO_5 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_19_INDEX)) -#define GPIO_SNVS_VIO_5_CTL (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_18_INDEX)) - -/* Sony/Philips Digital Interface (SPDIF) */ - -#define GPIO_SPDIF_EXT_CLK (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX)) -#define GPIO_SPDIF_IN_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX)) -#define GPIO_SPDIF_IN_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_16_INDEX)) -#define GPIO_SPDIF_LOCK (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX)) -#define GPIO_SPDIF_OUT_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX)) -#define GPIO_SPDIF_OUT_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX)) -#define GPIO_SPDIF_OUT_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_15_INDEX)) -#define GPIO_SPDIF_SR_CLK (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX)) - -/* Boot Configuration */ - -#define GPIO_SRC_BOOT_CFG00 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_04_INDEX)) -#define GPIO_SRC_BOOT_CFG01 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_05_INDEX)) -#define GPIO_SRC_BOOT_CFG02 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_06_INDEX)) -#define GPIO_SRC_BOOT_CFG03 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_07_INDEX)) -#define GPIO_SRC_BOOT_CFG04 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_08_INDEX)) -#define GPIO_SRC_BOOT_CFG05 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_09_INDEX)) -#define GPIO_SRC_BOOT_CFG06 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_10_INDEX)) -#define GPIO_SRC_BOOT_CFG07 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_11_INDEX)) -#define GPIO_SRC_BOOT_CFG08 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_12_INDEX)) -#define GPIO_SRC_BOOT_CFG09 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_13_INDEX)) -#define GPIO_SRC_BOOT_CFG10 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_14_INDEX)) -#define GPIO_SRC_BOOT_CFG11 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_15_INDEX)) -#define GPIO_SRC_BOOT_MODE00 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX)) -#define GPIO_SRC_BOOT_MODE01 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_05_INDEX)) - -/* USB OTG */ - -#define GPIO_USB_OTG1_ID_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX)) -#define GPIO_USB_OTG1_ID_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_01_INDEX)) -#define GPIO_USB_OTG1_OC_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX)) -#define GPIO_USB_OTG1_OC_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_03_INDEX)) -#define GPIO_USB_OTG1_PWR_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX)) -#define GPIO_USB_OTG1_PWR_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_02_INDEX)) - -#define GPIO_USB_OTG2_ID_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX)) -#define GPIO_USB_OTG2_ID_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_00_INDEX)) -#define GPIO_USB_OTG2_OC_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_14_INDEX)) -#define GPIO_USB_OTG2_OC_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_40_INDEX)) -#define GPIO_USB_OTG2_PWR_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_15_INDEX)) -#define GPIO_USB_OTG2_PWR_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_41_INDEX)) - -/* Ultra Secured Digital Host Controller (uSDHC) */ - -#define GPIO_USDHC1_CD_1 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX)) -#define GPIO_USDHC1_CD_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_12_INDEX)) -#define GPIO_USDHC1_CD_3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_35_INDEX)) -#define GPIO_USDHC1_CLK (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_01_INDEX)) -#define GPIO_USDHC1_CMD (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_00_INDEX)) -#define GPIO_USDHC1_DATA0 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_02_INDEX)) -#define GPIO_USDHC1_DATA1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_03_INDEX)) -#define GPIO_USDHC1_DATA2 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_04_INDEX)) -#define GPIO_USDHC1_DATA3 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_05_INDEX)) -#define GPIO_USDHC1_RESET_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_33_INDEX)) -#define GPIO_USDHC1_RESET_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_00_INDEX)) -#define GPIO_USDHC1_RESET_3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_15_INDEX)) -#define GPIO_USDHC1_VSELECT_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_34_INDEX)) -#define GPIO_USDHC1_VSELECT_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX)) -#define GPIO_USDHC1_VSELECT_3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_14_INDEX)) -#define GPIO_USDHC1_VSELECT_4 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_41_INDEX)) -#define GPIO_USDHC1_WP_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_12_INDEX)) -#define GPIO_USDHC1_WP_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX)) -#define GPIO_USDHC1_WP_3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_13_INDEX)) -#define GPIO_USDHC1_WP_4 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_36_INDEX)) - -#define GPIO_USDHC2_CD_1 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX)) -#define GPIO_USDHC2_CD_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_39_INDEX)) -#define GPIO_USDHC2_CLK_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_04_INDEX)) -#define GPIO_USDHC2_CLK_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX)) -#define GPIO_USDHC2_CMD_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_05_INDEX)) -#define GPIO_USDHC2_CMD_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX)) -#define GPIO_USDHC2_DATA0_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_03_INDEX)) -#define GPIO_USDHC2_DATA0_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX)) -#define GPIO_USDHC2_DATA1_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_02_INDEX)) -#define GPIO_USDHC2_DATA1_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX)) -#define GPIO_USDHC2_DATA2_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_01_INDEX)) -#define GPIO_USDHC2_DATA2_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX)) -#define GPIO_USDHC2_DATA3_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_00_INDEX)) -#define GPIO_USDHC2_DATA3_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX)) -#define GPIO_USDHC2_DATA4_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_08_INDEX)) -#define GPIO_USDHC2_DATA4_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_12_INDEX)) -#define GPIO_USDHC2_DATA5_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_09_INDEX)) -#define GPIO_USDHC2_DATA5_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_13_INDEX)) -#define GPIO_USDHC2_DATA6_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_10_INDEX)) -#define GPIO_USDHC2_DATA6_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_14_INDEX)) -#define GPIO_USDHC2_DATA7_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_11_INDEX)) -#define GPIO_USDHC2_DATA7_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_15_INDEX)) -#define GPIO_USDHC2_RESET_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_06_INDEX)) -#define GPIO_USDHC2_RESET_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_11_INDEX)) -#define GPIO_USDHC2_RESET_3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_11_INDEX)) -#define GPIO_USDHC2_RESET_4 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_40_INDEX)) -#define GPIO_USDHC2_VSELECT (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_38_INDEX)) -#define GPIO_USDHC2_WP_1 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_10_INDEX)) -#define GPIO_USDHC2_WP_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_37_INDEX)) - -/* Watchdog Timer (WDOG1-2) */ - -#define GPIO_WDOG1_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_13_INDEX)) -#define GPIO_WDOG1_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_10_INDEX)) -#define GPIO_WDOG1_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX)) -#define GPIO_WDOG1_WDOG_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_11_INDEX)) -#define GPIO_WDOG1_WDOG_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_39_INDEX)) -#define GPIO_WDOG1_WDOG_RST_DEB (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_15_INDEX)) - -#define GPIO_WDOG2_RESET_DEB (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_03_INDEX)) -#define GPIO_WDOG2_WDOG (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_12_INDEX)) - -/* Inter-Peripheral Crossbar Switch A (XBARA) */ - -#define GPIO_XBAR1_IN02 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_14_INDEX)) -#define GPIO_XBAR1_IN03_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_15_INDEX)) -#define GPIO_XBAR1_IN03_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_01_INDEX)) -#define GPIO_XBAR1_IN20_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_15_INDEX)) -#define GPIO_XBAR1_IN20_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_08_INDEX)) -#define GPIO_XBAR1_IN21_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_16_INDEX)) -#define GPIO_XBAR1_IN21_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_09_INDEX)) -#define GPIO_XBAR1_IN22_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_36_INDEX)) -#define GPIO_XBAR1_IN22_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_10_INDEX)) -#define GPIO_XBAR1_IN23_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_37_INDEX)) -#define GPIO_XBAR1_IN23_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_11_INDEX)) -#define GPIO_XBAR1_IN24_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_14_INDEX)) -#define GPIO_XBAR1_IN24_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_12_INDEX)) -#define GPIO_XBAR1_IN25_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_15_INDEX)) -#define GPIO_XBAR1_IN25_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_13_INDEX)) -#define GPIO_XBAR1_INOUT04_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_02_INDEX)) -#define GPIO_XBAR1_INOUT04_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_00_INDEX)) -#define GPIO_XBAR1_INOUT05_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_03_INDEX)) -#define GPIO_XBAR1_INOUT05_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_01_INDEX)) -#define GPIO_XBAR1_INOUT06_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_04_INDEX)) -#define GPIO_XBAR1_INOUT06_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_02_INDEX)) -#define GPIO_XBAR1_INOUT07_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_05_INDEX)) -#define GPIO_XBAR1_INOUT07_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_03_INDEX)) -#define GPIO_XBAR1_INOUT08_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_06_INDEX)) -#define GPIO_XBAR1_INOUT08_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_04_INDEX)) -#define GPIO_XBAR1_INOUT09_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_07_INDEX)) -#define GPIO_XBAR1_INOUT09_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_05_INDEX)) -#define GPIO_XBAR1_INOUT10 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_12_INDEX)) -#define GPIO_XBAR1_INOUT11 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_13_INDEX)) -#define GPIO_XBAR1_INOUT12 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_14_INDEX)) -#define GPIO_XBAR1_INOUT13 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_15_INDEX)) -#define GPIO_XBAR1_INOUT14_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_00_INDEX)) -#define GPIO_XBAR1_INOUT14_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_00_INDEX)) -#define GPIO_XBAR1_INOUT15_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_01_INDEX)) -#define GPIO_XBAR1_INOUT15_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_01_INDEX)) -#define GPIO_XBAR1_INOUT16_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_02_INDEX)) -#define GPIO_XBAR1_INOUT16_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_02_INDEX)) -#define GPIO_XBAR1_INOUT17_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_03_INDEX)) -#define GPIO_XBAR1_INOUT17_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_03_INDEX)) -#define GPIO_XBAR1_INOUT17_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_08_INDEX)) -#define GPIO_XBAR1_INOUT17_4 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_05_INDEX)) -#define GPIO_XBAR1_INOUT18_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_35_INDEX)) -#define GPIO_XBAR1_INOUT18_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_06_INDEX)) -#define GPIO_XBAR1_INOUT19_3 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_14_INDEX)) -#define GPIO_XBAR1_INOUT19_4 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_07_INDEX)) -#define GPIO_XBAR1_XBAR_IN02 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_00_INDEX)) - -#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_PINMUX_H */ diff --git a/arch/arm/src/imxrt/chip/rt105x/imxrt105x_xbar.h b/arch/arm/src/imxrt/chip/rt105x/imxrt105x_xbar.h deleted file mode 100644 index 697972163f6..00000000000 --- a/arch/arm/src/imxrt/chip/rt105x/imxrt105x_xbar.h +++ /dev/null @@ -1,386 +0,0 @@ -/* XBAR Defines for IMXRT1050 */ - -/* XBARA1 Mux inputs (I values) ***************************************************************************************************************************************/ - -#define IMXRT_XBARA1_IN_LOGIC_LOW IMXRT_XBARA1(XBAR_INPUT, 0) /* LOGIC_LOW output assigned to XBARA1_IN0 input. */ -#define IMXRT_XBARA1_IN_LOGIC_HIGH IMXRT_XBARA1(XBAR_INPUT, 1) /* LOGIC_HIGH output assigned to XBARA1_IN1 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN02 IMXRT_XBARA1(XBAR_INPUT, 2) /* IOMUX_XBAR_IN02 output assigned to XBARA1_IN2 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN03 IMXRT_XBARA1(XBAR_INPUT, 3) /* IOMUX_XBAR_IN03 output assigned to XBARA1_IN3 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO04 IMXRT_XBARA1(XBAR_INPUT, 4) /* IOMUX_XBAR_INOUT04 output assigned to XBARA1_IN4 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO05 IMXRT_XBARA1(XBAR_INPUT, 5) /* IOMUX_XBAR_INOUT05 output assigned to XBARA1_IN5 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO06 IMXRT_XBARA1(XBAR_INPUT, 6) /* IOMUX_XBAR_INOUT06 output assigned to XBARA1_IN6 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO07 IMXRT_XBARA1(XBAR_INPUT, 7) /* IOMUX_XBAR_INOUT07 output assigned to XBARA1_IN7 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO08 IMXRT_XBARA1(XBAR_INPUT, 8) /* IOMUX_XBAR_INOUT08 output assigned to XBARA1_IN8 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO09 IMXRT_XBARA1(XBAR_INPUT, 9) /* IOMUX_XBAR_INOUT09 output assigned to XBARA1_IN9 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO10 IMXRT_XBARA1(XBAR_INPUT, 10) /* IOMUX_XBAR_INOUT10 output assigned to XBARA1_IN10 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO11 IMXRT_XBARA1(XBAR_INPUT, 11) /* IOMUX_XBAR_INOUT11 output assigned to XBARA1_IN11 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO12 IMXRT_XBARA1(XBAR_INPUT, 12) /* IOMUX_XBAR_INOUT12 output assigned to XBARA1_IN12 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO13 IMXRT_XBARA1(XBAR_INPUT, 13) /* IOMUX_XBAR_INOUT13 output assigned to XBARA1_IN13 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO14 IMXRT_XBARA1(XBAR_INPUT, 14) /* IOMUX_XBAR_INOUT14 output assigned to XBARA1_IN14 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO15 IMXRT_XBARA1(XBAR_INPUT, 15) /* IOMUX_XBAR_INOUT15 output assigned to XBARA1_IN15 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO16 IMXRT_XBARA1(XBAR_INPUT, 16) /* IOMUX_XBAR_INOUT16 output assigned to XBARA1_IN16 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO17 IMXRT_XBARA1(XBAR_INPUT, 17) /* IOMUX_XBAR_INOUT17 output assigned to XBARA1_IN17 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO18 IMXRT_XBARA1(XBAR_INPUT, 18) /* IOMUX_XBAR_INOUT18 output assigned to XBARA1_IN18 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO19 IMXRT_XBARA1(XBAR_INPUT, 19) /* IOMUX_XBAR_INOUT19 output assigned to XBARA1_IN19 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN20 IMXRT_XBARA1(XBAR_INPUT, 20) /* IOMUX_XBAR_IN20 output assigned to XBARA1_IN20 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN21 IMXRT_XBARA1(XBAR_INPUT, 21) /* IOMUX_XBAR_IN21 output assigned to XBARA1_IN21 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN22 IMXRT_XBARA1(XBAR_INPUT, 22) /* IOMUX_XBAR_IN22 output assigned to XBARA1_IN22 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN23 IMXRT_XBARA1(XBAR_INPUT, 23) /* IOMUX_XBAR_IN23 output assigned to XBARA1_IN23 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN24 IMXRT_XBARA1(XBAR_INPUT, 24) /* IOMUX_XBAR_IN24 output assigned to XBARA1_IN24 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN25 IMXRT_XBARA1(XBAR_INPUT, 25) /* IOMUX_XBAR_IN25 output assigned to XBARA1_IN25 input. */ -#define IMXRT_XBARA1_IN_ACMP1_OUT IMXRT_XBARA1(XBAR_INPUT, 26) /* ACMP1_OUT output assigned to XBARA1_IN26 input. */ -#define IMXRT_XBARA1_IN_ACMP2_OUT IMXRT_XBARA1(XBAR_INPUT, 27) /* ACMP2_OUT output assigned to XBARA1_IN27 input. */ -#define IMXRT_XBARA1_IN_ACMP3_OUT IMXRT_XBARA1(XBAR_INPUT, 28) /* ACMP3_OUT output assigned to XBARA1_IN28 input. */ -#define IMXRT_XBARA1_IN_ACMP4_OUT IMXRT_XBARA1(XBAR_INPUT, 29) /* ACMP4_OUT output assigned to XBARA1_IN29 input. */ -#define IMXRT_XBARA1_IN_RESERVED30 IMXRT_XBARA1(XBAR_INPUT, 30) /* XBARA1_IN30 input is reserved. */ -#define IMXRT_XBARA1_IN_RESERVED31 IMXRT_XBARA1(XBAR_INPUT, 31) /* XBARA1_IN31 input is reserved. */ -#define IMXRT_XBARA1_IN_QTIMER3_TMR0_OUT IMXRT_XBARA1(XBAR_INPUT, 32) /* QTIMER3_TMR0_OUTPUT output assigned to XBARA1_IN32 input. */ -#define IMXRT_XBARA1_IN_QTIMER3_TMR1_OUT IMXRT_XBARA1(XBAR_INPUT, 33) /* QTIMER3_TMR1_OUTPUT output assigned to XBARA1_IN33 input. */ -#define IMXRT_XBARA1_IN_QTIMER3_TMR2_OUT IMXRT_XBARA1(XBAR_INPUT, 34) /* QTIMER3_TMR2_OUTPUT output assigned to XBARA1_IN34 input. */ -#define IMXRT_XBARA1_IN_QTIMER3_TMR3_OUT IMXRT_XBARA1(XBAR_INPUT, 35) /* QTIMER3_TMR3_OUTPUT output assigned to XBARA1_IN35 input. */ -#define IMXRT_XBARA1_IN_QTIMER4_TMR0_OUT IMXRT_XBARA1(XBAR_INPUT, 36) /* QTIMER4_TMR0_OUTPUT output assigned to XBARA1_IN36 input. */ -#define IMXRT_XBARA1_IN_QTIMER4_TMR1_OUT IMXRT_XBARA1(XBAR_INPUT, 37) /* QTIMER4_TMR1_OUTPUT output assigned to XBARA1_IN37 input. */ -#define IMXRT_XBARA1_IN_QTIMER4_TMR2_OUT IMXRT_XBARA1(XBAR_INPUT, 38) /* QTIMER4_TMR2_OUTPUT output assigned to XBARA1_IN38 input. */ -#define IMXRT_XBARA1_IN_QTIMER4_TMR3_OUT IMXRT_XBARA1(XBAR_INPUT, 39) /* QTIMER4_TMR3_OUTPUT output assigned to XBARA1_IN39 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM1_PWM1_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 40) /* FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN40 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM1_PWM2_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 41) /* FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN41 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM1_PWM3_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 42) /* FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN42 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM1_PWM4_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 43) /* FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN43 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM2_PWM1_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 44) /* FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN44 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM2_PWM2_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 45) /* FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN45 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM2_PWM3_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 46) /* FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN46 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM2_PWM4_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 47) /* FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN47 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM3_PWM1_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 48) /* FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN48 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM3_PWM2_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 49) /* FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN49 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM3_PWM3_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 50) /* FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN50 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM3_PWM4_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 51) /* FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN51 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM4_PWM1_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 52) /* FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN52 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM4_PWM2_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 53) /* FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN53 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM4_PWM3_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 54) /* FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN54 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM4_PWM4_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 55) /* FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN55 input. */ -#define IMXRT_XBARA1_IN_PIT_TRIGGER0 IMXRT_XBARA1(XBAR_INPUT, 56) /* PIT_TRIGGER0 output assigned to XBARA1_IN56 input. */ -#define IMXRT_XBARA1_IN_PIT_TRIGGER1 IMXRT_XBARA1(XBAR_INPUT, 57) /* PIT_TRIGGER1 output assigned to XBARA1_IN57 input. */ -#define IMXRT_XBARA1_IN_PIT_TRIGGER2 IMXRT_XBARA1(XBAR_INPUT, 58) /* PIT_TRIGGER2 output assigned to XBARA1_IN58 input. */ -#define IMXRT_XBARA1_IN_PIT_TRIGGER3 IMXRT_XBARA1(XBAR_INPUT, 59) /* PIT_TRIGGER3 output assigned to XBARA1_IN59 input. */ -#define IMXRT_XBARA1_IN_ENC1_POS_MATCH IMXRT_XBARA1(XBAR_INPUT, 60) /* ENC1_POS_MATCH output assigned to XBARA1_IN60 input. */ -#define IMXRT_XBARA1_IN_ENC2_POS_MATCH IMXRT_XBARA1(XBAR_INPUT, 61) /* ENC2_POS_MATCH output assigned to XBARA1_IN61 input. */ -#define IMXRT_XBARA1_IN_ENC3_POS_MATCH IMXRT_XBARA1(XBAR_INPUT, 62) /* ENC3_POS_MATCH output assigned to XBARA1_IN62 input. */ -#define IMXRT_XBARA1_IN_ENC4_POS_MATCH IMXRT_XBARA1(XBAR_INPUT, 63) /* ENC4_POS_MATCH output assigned to XBARA1_IN63 input. */ -#define IMXRT_XBARA1_IN_DMA_DONE0 IMXRT_XBARA1(XBAR_INPUT, 64) /* DMA_DONE0 output assigned to XBARA1_IN64 input. */ -#define IMXRT_XBARA1_IN_DMA_DONE1 IMXRT_XBARA1(XBAR_INPUT, 65) /* DMA_DONE1 output assigned to XBARA1_IN65 input. */ -#define IMXRT_XBARA1_IN_DMA_DONE2 IMXRT_XBARA1(XBAR_INPUT, 66) /* DMA_DONE2 output assigned to XBARA1_IN66 input. */ -#define IMXRT_XBARA1_IN_DMA_DONE3 IMXRT_XBARA1(XBAR_INPUT, 67) /* DMA_DONE3 output assigned to XBARA1_IN67 input. */ -#define IMXRT_XBARA1_IN_DMA_DONE4 IMXRT_XBARA1(XBAR_INPUT, 68) /* DMA_DONE4 output assigned to XBARA1_IN68 input. */ -#define IMXRT_XBARA1_IN_DMA_DONE5 IMXRT_XBARA1(XBAR_INPUT, 69) /* DMA_DONE5 output assigned to XBARA1_IN69 input. */ -#define IMXRT_XBARA1_IN_DMA_DONE6 IMXRT_XBARA1(XBAR_INPUT, 70) /* DMA_DONE6 output assigned to XBARA1_IN70 input. */ -#define IMXRT_XBARA1_IN_DMA_DONE7 IMXRT_XBARA1(XBAR_INPUT, 71) /* DMA_DONE7 output assigned to XBARA1_IN71 input. */ -#define IMXRT_XBARA1_IN_AOI1_OUT0 IMXRT_XBARA1(XBAR_INPUT, 72) /* AOI1_OUT0 output assigned to XBARA1_IN72 input. */ -#define IMXRT_XBARA1_IN_AOI1_OUT1 IMXRT_XBARA1(XBAR_INPUT, 73) /* AOI1_OUT1 output assigned to XBARA1_IN73 input. */ -#define IMXRT_XBARA1_IN_AOI1_OUT2 IMXRT_XBARA1(XBAR_INPUT, 74) /* AOI1_OUT2 output assigned to XBARA1_IN74 input. */ -#define IMXRT_XBARA1_IN_AOI1_OUT3 IMXRT_XBARA1(XBAR_INPUT, 75) /* AOI1_OUT3 output assigned to XBARA1_IN75 input. */ -#define IMXRT_XBARA1_IN_AOI2_OUT0 IMXRT_XBARA1(XBAR_INPUT, 76) /* AOI2_OUT0 output assigned to XBARA1_IN76 input. */ -#define IMXRT_XBARA1_IN_AOI2_OUT1 IMXRT_XBARA1(XBAR_INPUT, 77) /* AOI2_OUT1 output assigned to XBARA1_IN77 input. */ -#define IMXRT_XBARA1_IN_AOI2_OUT2 IMXRT_XBARA1(XBAR_INPUT, 78) /* AOI2_OUT2 output assigned to XBARA1_IN78 input. */ -#define IMXRT_XBARA1_IN_AOI2_OUT3 IMXRT_XBARA1(XBAR_INPUT, 79) /* AOI2_OUT3 output assigned to XBARA1_IN79 input. */ -#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO0 IMXRT_XBARA1(XBAR_INPUT, 80) /* ADC_ETC_XBAR0_COCO0 output assigned to XBARA1_IN80 input. */ -#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO1 IMXRT_XBARA1(XBAR_INPUT, 81) /* ADC_ETC_XBAR0_COCO1 output assigned to XBARA1_IN81 input. */ -#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO2 IMXRT_XBARA1(XBAR_INPUT, 82) /* ADC_ETC_XBAR0_COCO2 output assigned to XBARA1_IN82 input. */ -#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO3 IMXRT_XBARA1(XBAR_INPUT, 83) /* ADC_ETC_XBAR0_COCO3 output assigned to XBARA1_IN83 input. */ -#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO0 IMXRT_XBARA1(XBAR_INPUT, 84) /* ADC_ETC_XBAR1_COCO0 output assigned to XBARA1_IN84 input. */ -#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO1 IMXRT_XBARA1(XBAR_INPUT, 85) /* ADC_ETC_XBAR1_COCO1 output assigned to XBARA1_IN85 input. */ -#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO2 IMXRT_XBARA1(XBAR_INPUT, 86) /* ADC_ETC_XBAR1_COCO2 output assigned to XBARA1_IN86 input. */ -#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO3 IMXRT_XBARA1(XBAR_INPUT, 87) /* ADC_ETC_XBAR1_COCO3 output assigned to XBARA1_IN87 input. */ - -/* XBARA1 Mux Output (M Muxes) ***************************************************************************************************************/ - -#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ30_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 0) /* XBARA1_OUT0 output assigned to DMA_CH_MUX_REQ30 */ -#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ31_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 1) /* XBARA1_OUT1 output assigned to DMA_CH_MUX_REQ31 */ -#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ94_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 2) /* XBARA1_OUT2 output assigned to DMA_CH_MUX_REQ94 */ -#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ95_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 3) /* XBARA1_OUT3 output assigned to DMA_CH_MUX_REQ95 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO04_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 4) /* XBARA1_OUT4 output assigned to IOMUX_XBAR_INOUT04 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO05_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 5) /* XBARA1_OUT5 output assigned to IOMUX_XBAR_INOUT05 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO06_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 6) /* XBARA1_OUT6 output assigned to IOMUX_XBAR_INOUT06 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO07_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 7) /* XBARA1_OUT7 output assigned to IOMUX_XBAR_INOUT07 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO08_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 8) /* XBARA1_OUT8 output assigned to IOMUX_XBAR_INOUT08 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO09_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 9) /* XBARA1_OUT9 output assigned to IOMUX_XBAR_INOUT09 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO10_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 10) /* XBARA1_OUT10 output assigned to IOMUX_XBAR_INOUT10 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO11_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 11) /* XBARA1_OUT11 output assigned to IOMUX_XBAR_INOUT11 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO12_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 12) /* XBARA1_OUT12 output assigned to IOMUX_XBAR_INOUT12 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO13_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 13) /* XBARA1_OUT13 output assigned to IOMUX_XBAR_INOUT13 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO14_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 14) /* XBARA1_OUT14 output assigned to IOMUX_XBAR_INOUT14 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO15_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 15) /* XBARA1_OUT15 output assigned to IOMUX_XBAR_INOUT15 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO16_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 16) /* XBARA1_OUT16 output assigned to IOMUX_XBAR_INOUT16 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO17_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 17) /* XBARA1_OUT17 output assigned to IOMUX_XBAR_INOUT17 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO18_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 18) /* XBARA1_OUT18 output assigned to IOMUX_XBAR_INOUT18 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO19_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 19) /* XBARA1_OUT19 output assigned to IOMUX_XBAR_INOUT19 */ -#define IMXRT_XBARA1_OUT_ACMP1_SAMPLE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 20) /* XBARA1_OUT20 output assigned to ACMP1_SAMPLE */ -#define IMXRT_XBARA1_OUT_ACMP2_SAMPLE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 21) /* XBARA1_OUT21 output assigned to ACMP2_SAMPLE */ -#define IMXRT_XBARA1_OUT_ACMP3_SAMPLE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 22) /* XBARA1_OUT22 output assigned to ACMP3_SAMPLE */ -#define IMXRT_XBARA1_OUT_ACMP4_SAMPLE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 23) /* XBARA1_OUT23 output assigned to ACMP4_SAMPLE */ -#define IMXRT_XBARA1_OUT_RESERVED24_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 24) /* XBARA1_OUT24 output is reserved. */ -#define IMXRT_XBARA1_OUT_RESERVED25_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 25) /* XBARA1_OUT25 output is reserved. */ -#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 26) /* XBARA1_OUT26 output assigned to FLEXPWM1_EXTA0 */ -#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 27) /* XBARA1_OUT27 output assigned to FLEXPWM1_EXTA1 */ -#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 28) /* XBARA1_OUT28 output assigned to FLEXPWM1_EXTA2 */ -#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 29) /* XBARA1_OUT29 output assigned to FLEXPWM1_EXTA3 */ -#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 30) /* XBARA1_OUT30 output assigned to FLEXPWM1_EXT_SYNC0 */ -#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 31) /* XBARA1_OUT31 output assigned to FLEXPWM1_EXT_SYNC1 */ -#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 32) /* XBARA1_OUT32 output assigned to FLEXPWM1_EXT_SYNC2 */ -#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 33) /* XBARA1_OUT33 output assigned to FLEXPWM1_EXT_SYNC3 */ -#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_CLK_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 34) /* XBARA1_OUT34 output assigned to FLEXPWM1_EXT_CLK */ -#define IMXRT_XBARA1_OUT_FLEXPWM1_FAULT0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 35) /* XBARA1_OUT35 output assigned to FLEXPWM1_FAULT0 */ -#define IMXRT_XBARA1_OUT_FLEXPWM1_FAULT1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 36) /* XBARA1_OUT36 output assigned to FLEXPWM1_FAULT1 */ -#define IMXRT_XBARA1_OUT_FLEXPWM1234_FAULT2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 37) /* XBARA1_OUT37 output assigned to FLEXPWM1_2_3_4_FAULT2 */ -#define IMXRT_XBARA1_OUT_FLEXPWM1234_FAULT3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 38) /* XBARA1_OUT38 output assigned to FLEXPWM1_2_3_4_FAULT3 */ -#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_FORCE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 39) /* XBARA1_OUT39 output assigned to FLEXPWM1_EXT_FORCE */ -#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 40) /* XBARA1_OUT40 output assigned to FLEXPWM2_3_4_EXTA0 */ -#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 41) /* XBARA1_OUT41 output assigned to FLEXPWM2_3_4_EXTA1 */ -#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 42) /* XBARA1_OUT42 output assigned to FLEXPWM2_3_4_EXTA2 */ -#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 43) /* XBARA1_OUT43 output assigned to FLEXPWM2_3_4_EXTA3 */ -#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 44) /* XBARA1_OUT44 output assigned to FLEXPWM2_EXT_SYNC0 */ -#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 45) /* XBARA1_OUT45 output assigned to FLEXPWM2_EXT_SYNC1 */ -#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 46) /* XBARA1_OUT46 output assigned to FLEXPWM2_EXT_SYNC2 */ -#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 47) /* XBARA1_OUT47 output assigned to FLEXPWM2_EXT_SYNC3 */ -#define IMXRT_XBARA1_OUT_FLEXPWM234_EXT_CLK_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 48) /* XBARA1_OUT48 output assigned to FLEXPWM2_3_4_EXT_CLK */ -#define IMXRT_XBARA1_OUT_FLEXPWM2_FAULT0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 49) /* XBARA1_OUT49 output assigned to FLEXPWM2_FAULT0 */ -#define IMXRT_XBARA1_OUT_FLEXPWM2_FAULT1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 50) /* XBARA1_OUT50 output assigned to FLEXPWM2_FAULT1 */ -#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_FORCE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 51) /* XBARA1_OUT51 output assigned to FLEXPWM2_EXT_FORCE */ -#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 52) /* XBARA1_OUT52 output assigned to FLEXPWM3_EXT_SYNC0 */ -#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 53) /* XBARA1_OUT53 output assigned to FLEXPWM3_EXT_SYNC1 */ -#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 54) /* XBARA1_OUT54 output assigned to FLEXPWM3_EXT_SYNC2 */ -#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 55) /* XBARA1_OUT55 output assigned to FLEXPWM3_EXT_SYNC3 */ -#define IMXRT_XBARA1_OUT_FLEXPWM3_FAULT0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 56) /* XBARA1_OUT56 output assigned to FLEXPWM3_FAULT0 */ -#define IMXRT_XBARA1_OUT_FLEXPWM3_FAULT1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 57) /* XBARA1_OUT57 output assigned to FLEXPWM3_FAULT1 */ -#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_FORCE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 58) /* XBARA1_OUT58 output assigned to FLEXPWM3_EXT_FORCE */ -#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 59) /* XBARA1_OUT59 output assigned to FLEXPWM4_EXT_SYNC0 */ -#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 60) /* XBARA1_OUT60 output assigned to FLEXPWM4_EXT_SYNC1 */ -#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 61) /* XBARA1_OUT61 output assigned to FLEXPWM4_EXT_SYNC2 */ -#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 62) /* XBARA1_OUT62 output assigned to FLEXPWM4_EXT_SYNC3 */ -#define IMXRT_XBARA1_OUT_FLEXPWM4_FAULT0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 63) /* XBARA1_OUT63 output assigned to FLEXPWM4_FAULT0 */ -#define IMXRT_XBARA1_OUT_FLEXPWM4_FAULT1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 64) /* XBARA1_OUT64 output assigned to FLEXPWM4_FAULT1 */ -#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_FORCE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 65) /* XBARA1_OUT65 output assigned to FLEXPWM4_EXT_FORCE */ -#define IMXRT_XBARA1_OUT_ENC1_PHASE_AIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 66) /* XBARA1_OUT66 output assigned to ENC1_PHASE_A_IN_ */ -#define IMXRT_XBARA1_OUT_ENC1_PHASE_BIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 67) /* XBARA1_OUT67 output assigned to ENC1_PHASE_B_IN_ */ -#define IMXRT_XBARA1_OUT_ENC1_INDEX_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 68) /* XBARA1_OUT68 output assigned to ENC1_INDEX */ -#define IMXRT_XBARA1_OUT_ENC1_HOME_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 69) /* XBARA1_OUT69 output assigned to ENC1_HOME */ -#define IMXRT_XBARA1_OUT_ENC1_TRIGGER_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 70) /* XBARA1_OUT70 output assigned to ENC1_TRIGGER */ -#define IMXRT_XBARA1_OUT_ENC2_PHASE_AIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 71) /* XBARA1_OUT71 output assigned to ENC2_PHASE_A_IN_ */ -#define IMXRT_XBARA1_OUT_ENC2_PHASE_BIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 72) /* XBARA1_OUT72 output assigned to ENC2_PHASE_B_IN_ */ -#define IMXRT_XBARA1_OUT_ENC2_INDEX_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 73) /* XBARA1_OUT73 output assigned to ENC2_INDEX */ -#define IMXRT_XBARA1_OUT_ENC2_HOME_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 74) /* XBARA1_OUT74 output assigned to ENC2_HOME */ -#define IMXRT_XBARA1_OUT_ENC2_TRIGGER_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 75) /* XBARA1_OUT75 output assigned to ENC2_TRIGGER */ -#define IMXRT_XBARA1_OUT_ENC3_PHASE_AIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 76) /* XBARA1_OUT76 output assigned to ENC3_PHASE_A_IN_ */ -#define IMXRT_XBARA1_OUT_ENC3_PHASE_BIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 77) /* XBARA1_OUT77 output assigned to ENC3_PHASE_B_IN_ */ -#define IMXRT_XBARA1_OUT_ENC3_INDEX_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 78) /* XBARA1_OUT78 output assigned to ENC3_INDEX */ -#define IMXRT_XBARA1_OUT_ENC3_HOME_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 79) /* XBARA1_OUT79 output assigned to ENC3_HOME */ -#define IMXRT_XBARA1_OUT_ENC3_TRIGGER_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 80) /* XBARA1_OUT80 output assigned to ENC3_TRIGGER */ -#define IMXRT_XBARA1_OUT_ENC4_PHASE_AIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 81) /* XBARA1_OUT81 output assigned to ENC4_PHASE_A_IN_ */ -#define IMXRT_XBARA1_OUT_ENC4_PHASE_BIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 82) /* XBARA1_OUT82 output assigned to ENC4_PHASE_B_IN_ */ -#define IMXRT_XBARA1_OUT_ENC4_INDEX_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 83) /* XBARA1_OUT83 output assigned to ENC4_INDEX */ -#define IMXRT_XBARA1_OUT_ENC4_HOME_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 84) /* XBARA1_OUT84 output assigned to ENC4_HOME */ -#define IMXRT_XBARA1_OUT_ENC4_TRIGGER_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 85) /* XBARA1_OUT85 output assigned to ENC4_TRIGGER */ -#define IMXRT_XBARA1_OUT_QTIMER1_TMR0_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 86) /* XBARA1_OUT86 output assigned to QTIMER1_TMR0_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER1_TMR1_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 87) /* XBARA1_OUT87 output assigned to QTIMER1_TMR1_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER1_TMR2_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 88) /* XBARA1_OUT88 output assigned to QTIMER1_TMR2_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER1_TMR3_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 89) /* XBARA1_OUT89 output assigned to QTIMER1_TMR3_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER2_TMR0_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 90) /* XBARA1_OUT90 output assigned to QTIMER2_TMR0_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER2_TMR1_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 91) /* XBARA1_OUT91 output assigned to QTIMER2_TMR1_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER2_TMR2_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 92) /* XBARA1_OUT92 output assigned to QTIMER2_TMR2_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER2_TMR3_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 93) /* XBARA1_OUT93 output assigned to QTIMER2_TMR3_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER3_TMR0_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 94) /* XBARA1_OUT94 output assigned to QTIMER3_TMR0_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER3_TMR1_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 95) /* XBARA1_OUT95 output assigned to QTIMER3_TMR1_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER3_TMR2_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 96) /* XBARA1_OUT96 output assigned to QTIMER3_TMR2_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER3_TMR3_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 97) /* XBARA1_OUT97 output assigned to QTIMER3_TMR3_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER4_TMR0_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 98) /* XBARA1_OUT98 output assigned to QTIMER4_TMR0_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER4_TMR1_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 99) /* XBARA1_OUT99 output assigned to QTIMER4_TMR1_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER4_TMR2_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 100) /* XBARA1_OUT100 output assigned to QTIMER4_TMR2_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER4_TMR3_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 101) /* XBARA1_OUT101 output assigned to QTIMER4_TMR3_IN_ */ -#define IMXRT_XBARA1_OUT_EWM_EWM_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 102) /* XBARA1_OUT102 output assigned to EWM_EWM_IN */ -#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 103) /* XBARA1_OUT103 output assigned to ADC_ETC_XBAR0_TRIG0 */ -#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 104) /* XBARA1_OUT104 output assigned to ADC_ETC_XBAR0_TRIG1 */ -#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 105) /* XBARA1_OUT105 output assigned to ADC_ETC_XBAR0_TRIG2 */ -#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 106) /* XBARA1_OUT106 output assigned to ADC_ETC_XBAR0_TRIG3 */ -#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 107) /* XBARA1_OUT107 output assigned to ADC_ETC_XBAR1_TRIG0 */ -#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 108) /* XBARA1_OUT108 output assigned to ADC_ETC_XBAR1_TRIG1 */ -#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 109) /* XBARA1_OUT109 output assigned to ADC_ETC_XBAR1_TRIG2 */ -#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 110) /* XBARA1_OUT110 output assigned to ADC_ETC_XBAR1_TRIG3 */ -#define IMXRT_XBARA1_OUT_LPI2C1_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 111) /* XBARA1_OUT111 output assigned to LPI2C1_TRG_IN_ */ -#define IMXRT_XBARA1_OUT_LPI2C2_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 112) /* XBARA1_OUT112 output assigned to LPI2C2_TRG_IN_ */ -#define IMXRT_XBARA1_OUT_LPI2C3_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 113) /* XBARA1_OUT113 output assigned to LPI2C3_TRG_IN_ */ -#define IMXRT_XBARA1_OUT_LPI2C4_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 114) /* XBARA1_OUT114 output assigned to LPI2C4_TRG_IN_ */ -#define IMXRT_XBARA1_OUT_LPSPI1_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 115) /* XBARA1_OUT115 output assigned to LPSPI1_TRG_IN_ */ -#define IMXRT_XBARA1_OUT_LPSPI2_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 116) /* XBARA1_OUT116 output assigned to LPSPI2_TRG_IN_ */ -#define IMXRT_XBARA1_OUT_LPSPI3_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 117) /* XBARA1_OUT117 output assigned to LPSPI3_TRG_IN_ */ -#define IMXRT_XBARA1_OUT_LPSPI4_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 118) /* XBARA1_OUT118 output assigned to LPSPI4_TRG_IN_ */ -#define IMXRT_XBARA1_OUT_LPUART1_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 119) /* XBARA1_OUT119 output assigned to LPUART1_TRG_IN_ */ -#define IMXRT_XBARA1_OUT_LPUART2_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 120) /* XBARA1_OUT120 output assigned to LPUART2_TRG_IN_ */ -#define IMXRT_XBARA1_OUT_LPUART3_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 121) /* XBARA1_OUT121 output assigned to LPUART3_TRG_IN_ */ -#define IMXRT_XBARA1_OUT_LPUART4_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 122) /* XBARA1_OUT122 output assigned to LPUART4_TRG_IN_ */ -#define IMXRT_XBARA1_OUT_LPUART5_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 123) /* XBARA1_OUT123 output assigned to LPUART5_TRG_IN_ */ -#define IMXRT_XBARA1_OUT_LPUART6_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 124) /* XBARA1_OUT124 output assigned to LPUART6_TRG_IN_ */ -#define IMXRT_XBARA1_OUT_LPUART7_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 125) /* XBARA1_OUT125 output assigned to LPUART7_TRG_IN_ */ -#define IMXRT_XBARA1_OUT_LPUART8_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 126) /* XBARA1_OUT126 output assigned to LPUART8_TRG_IN_ */ -#define IMXRT_XBARA1_OUT_FLEXIO1_TRIGGER_IN0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 127) /* XBARA1_OUT127 output assigned to FLEXIO1_TRIGGER_IN0 */ -#define IMXRT_XBARA1_OUT_FLEXIO1_TRIGGER_IN1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 128) /* XBARA1_OUT128 output assigned to FLEXIO1_TRIGGER_IN1 */ -#define IMXRT_XBARA1_OUT_FLEXIO2_TRIGGER_IN0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 129) /* XBARA1_OUT129 output assigned to FLEXIO2_TRIGGER_IN0 */ -#define IMXRT_XBARA1_OUT_FLEXIO2_TRIGGER_IN1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 130) /* XBARA1_OUT130 output assigned to FLEXIO2_TRIGGER_IN1 */ - -/* XBARB2 Mux inputs (I values) *******************************************************************************************************************/ - -#define IMXRT_XBARB2_IN_LOGIC_LOW IMXRT_XBARB2(XBAR_INPUT, 0) /* LOGIC_LOW output assigned to XBARB2_IN0 input. */ -#define IMXRT_XBARB2_IN_LOGIC_HIGH IMXRT_XBARB2(XBAR_INPUT, 1) /* LOGIC_HIGH output assigned to XBARB2_IN1 input. */ -#define IMXRT_XBARB2_IN_RESERVED2 IMXRT_XBARB2(XBAR_INPUT, 2) /* XBARB2_IN2 input is reserved. */ -#define IMXRT_XBARB2_IN_RESERVED3 IMXRT_XBARB2(XBAR_INPUT, 3) /* XBARB2_IN3 input is reserved. */ -#define IMXRT_XBARB2_IN_RESERVED4 IMXRT_XBARB2(XBAR_INPUT, 4) /* XBARB2_IN4 input is reserved. */ -#define IMXRT_XBARB2_IN_RESERVED5 IMXRT_XBARB2(XBAR_INPUT, 5) /* XBARB2_IN5 input is reserved. */ -#define IMXRT_XBARB2_IN_ACMP1_OUT IMXRT_XBARB2(XBAR_INPUT, 6) /* ACMP1_OUT output assigned to XBARB2_IN6 input. */ -#define IMXRT_XBARB2_IN_ACMP2_OUT IMXRT_XBARB2(XBAR_INPUT, 7) /* ACMP2_OUT output assigned to XBARB2_IN7 input. */ -#define IMXRT_XBARB2_IN_ACMP3_OUT IMXRT_XBARB2(XBAR_INPUT, 8) /* ACMP3_OUT output assigned to XBARB2_IN8 input. */ -#define IMXRT_XBARB2_IN_ACMP4_OUT IMXRT_XBARB2(XBAR_INPUT, 9) /* ACMP4_OUT output assigned to XBARB2_IN9 input. */ -#define IMXRT_XBARB2_IN_RESERVED10 IMXRT_XBARB2(XBAR_INPUT, 10) /* XBARB2_IN10 input is reserved. */ -#define IMXRT_XBARB2_IN_RESERVED11 IMXRT_XBARB2(XBAR_INPUT, 11) /* XBARB2_IN11 input is reserved. */ -#define IMXRT_XBARB2_IN_QTIMER3_TMR0_OUT IMXRT_XBARB2(XBAR_INPUT, 12) /* QTIMER3_TMR0_OUTPUT output assigned to XBARB2_IN12 input. */ -#define IMXRT_XBARB2_IN_QTIMER3_TMR1_OUT IMXRT_XBARB2(XBAR_INPUT, 13) /* QTIMER3_TMR1_OUTPUT output assigned to XBARB2_IN13 input. */ -#define IMXRT_XBARB2_IN_QTIMER3_TMR2_OUT IMXRT_XBARB2(XBAR_INPUT, 14) /* QTIMER3_TMR2_OUTPUT output assigned to XBARB2_IN14 input. */ -#define IMXRT_XBARB2_IN_QTIMER3_TMR3_OUT IMXRT_XBARB2(XBAR_INPUT, 15) /* QTIMER3_TMR3_OUTPUT output assigned to XBARB2_IN15 input. */ -#define IMXRT_XBARB2_IN_QTIMER4_TMR0_OUT IMXRT_XBARB2(XBAR_INPUT, 16) /* QTIMER4_TMR0_OUTPUT output assigned to XBARB2_IN16 input. */ -#define IMXRT_XBARB2_IN_QTIMER4_TMR1_OUT IMXRT_XBARB2(XBAR_INPUT, 17) /* QTIMER4_TMR1_OUTPUT output assigned to XBARB2_IN17 input. */ -#define IMXRT_XBARB2_IN_QTIMER4_TMR2_OUT IMXRT_XBARB2(XBAR_INPUT, 18) /* QTIMER4_TMR2_OUTPUT output assigned to XBARB2_IN18 input. */ -#define IMXRT_XBARB2_IN_QTIMER4_TMR3_OUT IMXRT_XBARB2(XBAR_INPUT, 19) /* QTIMER4_TMR3_OUTPUT output assigned to XBARB2_IN19 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM1_PWM1_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 20) /* FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN20 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM1_PWM2_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 21) /* FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN21 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM1_PWM3_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 22) /* FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN22 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM1_PWM4_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 23) /* FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN23 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM2_PWM1_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 24) /* FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN24 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM2_PWM2_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 25) /* FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN25 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM2_PWM3_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 26) /* FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN26 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM2_PWM4_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 27) /* FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN27 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM3_PWM1_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 28) /* FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN28 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM3_PWM2_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 29) /* FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN29 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM3_PWM3_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 30) /* FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN30 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM3_PWM4_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 31) /* FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN31 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM4_PWM1_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 32) /* FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN32 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM4_PWM2_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 33) /* FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN33 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM4_PWM3_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 34) /* FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN34 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM4_PWM4_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 35) /* FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN35 input. */ -#define IMXRT_XBARB2_IN_PIT_TRIGGER0 IMXRT_XBARB2(XBAR_INPUT, 36) /* PIT_TRIGGER0 output assigned to XBARB2_IN36 input. */ -#define IMXRT_XBARB2_IN_PIT_TRIGGER1 IMXRT_XBARB2(XBAR_INPUT, 37) /* PIT_TRIGGER1 output assigned to XBARB2_IN37 input. */ -#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO0 IMXRT_XBARB2(XBAR_INPUT, 38) /* ADC_ETC_XBAR0_COCO0 output assigned to XBARB2_IN38 input. */ -#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO1 IMXRT_XBARB2(XBAR_INPUT, 39) /* ADC_ETC_XBAR0_COCO1 output assigned to XBARB2_IN39 input. */ -#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO2 IMXRT_XBARB2(XBAR_INPUT, 40) /* ADC_ETC_XBAR0_COCO2 output assigned to XBARB2_IN40 input. */ -#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO3 IMXRT_XBARB2(XBAR_INPUT, 41) /* ADC_ETC_XBAR0_COCO3 output assigned to XBARB2_IN41 input. */ -#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO0 IMXRT_XBARB2(XBAR_INPUT, 42) /* ADC_ETC_XBAR1_COCO0 output assigned to XBARB2_IN42 input. */ -#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO1 IMXRT_XBARB2(XBAR_INPUT, 43) /* ADC_ETC_XBAR1_COCO1 output assigned to XBARB2_IN43 input. */ -#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO2 IMXRT_XBARB2(XBAR_INPUT, 44) /* ADC_ETC_XBAR1_COCO2 output assigned to XBARB2_IN44 input. */ -#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO3 IMXRT_XBARB2(XBAR_INPUT, 45) /* ADC_ETC_XBAR1_COCO3 output assigned to XBARB2_IN45 input. */ -#define IMXRT_XBARB2_IN_ENC1_POS_MATCH IMXRT_XBARB2(XBAR_INPUT, 46) /* ENC1_POS_MATCH output assigned to XBARB2_IN46 input. */ -#define IMXRT_XBARB2_IN_ENC2_POS_MATCH IMXRT_XBARB2(XBAR_INPUT, 47) /* ENC2_POS_MATCH output assigned to XBARB2_IN47 input. */ -#define IMXRT_XBARB2_IN_ENC3_POS_MATCH IMXRT_XBARB2(XBAR_INPUT, 48) /* ENC3_POS_MATCH output assigned to XBARB2_IN48 input. */ -#define IMXRT_XBARB2_IN_ENC4_POS_MATCH IMXRT_XBARB2(XBAR_INPUT, 49) /* ENC4_POS_MATCH output assigned to XBARB2_IN49 input. */ -#define IMXRT_XBARB2_IN_DMA_DONE0 IMXRT_XBARB2(XBAR_INPUT, 50) /* DMA_DONE0 output assigned to XBARB2_IN50 input. */ -#define IMXRT_XBARB2_IN_DMA_DONE1 IMXRT_XBARB2(XBAR_INPUT, 51) /* DMA_DONE1 output assigned to XBARB2_IN51 input. */ -#define IMXRT_XBARB2_IN_DMA_DONE2 IMXRT_XBARB2(XBAR_INPUT, 52) /* DMA_DONE2 output assigned to XBARB2_IN52 input. */ -#define IMXRT_XBARB2_IN_DMA_DONE3 IMXRT_XBARB2(XBAR_INPUT, 53) /* DMA_DONE3 output assigned to XBARB2_IN53 input. */ -#define IMXRT_XBARB2_IN_DMA_DONE4 IMXRT_XBARB2(XBAR_INPUT, 54) /* DMA_DONE4 output assigned to XBARB2_IN54 input. */ -#define IMXRT_XBARB2_IN_DMA_DONE5 IMXRT_XBARB2(XBAR_INPUT, 55) /* DMA_DONE5 output assigned to XBARB2_IN55 input. */ -#define IMXRT_XBARB2_IN_DMA_DONE6 IMXRT_XBARB2(XBAR_INPUT, 56) /* DMA_DONE6 output assigned to XBARB2_IN56 input. */ -#define IMXRT_XBARB2_IN_DMA_DONE7 IMXRT_XBARB2(XBAR_INPUT, 57) /* DMA_DONE7 output assigned to XBARB2_IN57 input. */ - -/* XBARB2 Mux Output (M Muxes) ********************************************************************************************************************/ - -#define IMXRT_XBARB2_OUT_AOI1_IN00_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 0) /* XBARB2_OUT0 output assigned to AOI1_IN00 */ -#define IMXRT_XBARB2_OUT_AOI1_IN01_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 1) /* XBARB2_OUT1 output assigned to AOI1_IN01 */ -#define IMXRT_XBARB2_OUT_AOI1_IN02_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 2) /* XBARB2_OUT2 output assigned to AOI1_IN02 */ -#define IMXRT_XBARB2_OUT_AOI1_IN03_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 3) /* XBARB2_OUT3 output assigned to AOI1_IN03 */ -#define IMXRT_XBARB2_OUT_AOI1_IN04_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 4) /* XBARB2_OUT4 output assigned to AOI1_IN04 */ -#define IMXRT_XBARB2_OUT_AOI1_IN05_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 5) /* XBARB2_OUT5 output assigned to AOI1_IN05 */ -#define IMXRT_XBARB2_OUT_AOI1_IN06_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 6) /* XBARB2_OUT6 output assigned to AOI1_IN06 */ -#define IMXRT_XBARB2_OUT_AOI1_IN07_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 7) /* XBARB2_OUT7 output assigned to AOI1_IN07 */ -#define IMXRT_XBARB2_OUT_AOI1_IN08_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 8) /* XBARB2_OUT8 output assigned to AOI1_IN08 */ -#define IMXRT_XBARB2_OUT_AOI1_IN09_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 9) /* XBARB2_OUT9 output assigned to AOI1_IN09 */ -#define IMXRT_XBARB2_OUT_AOI1_IN10_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 10) /* XBARB2_OUT10 output assigned to AOI1_IN10 */ -#define IMXRT_XBARB2_OUT_AOI1_IN11_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 11) /* XBARB2_OUT11 output assigned to AOI1_IN11 */ -#define IMXRT_XBARB2_OUT_AOI1_IN12_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 12) /* XBARB2_OUT12 output assigned to AOI1_IN12 */ -#define IMXRT_XBARB2_OUT_AOI1_IN13_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 13) /* XBARB2_OUT13 output assigned to AOI1_IN13 */ -#define IMXRT_XBARB2_OUT_AOI1_IN14_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 14) /* XBARB2_OUT14 output assigned to AOI1_IN14 */ -#define IMXRT_XBARB2_OUT_AOI1_IN15_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 15) /* XBARB2_OUT15 output assigned to AOI1_IN15 */ - -/* XBARB3 Mux inputs (I values) *******************************************************************************************************************/ - -#define IMXRT_XBARB3_IN_LOGIC_LOW IMXRT_XBARB3(XBAR_INPUT, 0) /* LOGIC_LOW output assigned to XBARB3_IN0 input. */ -#define IMXRT_XBARB3_IN_LOGIC_HIGH IMXRT_XBARB3(XBAR_INPUT, 1) /* LOGIC_HIGH output assigned to XBARB3_IN1 input. */ -#define IMXRT_XBARB3_IN_RESERVED2 IMXRT_XBARB3(XBAR_INPUT, 2) /* XBARB3_IN2 input is reserved. */ -#define IMXRT_XBARB3_IN_RESERVED3 IMXRT_XBARB3(XBAR_INPUT, 3) /* XBARB3_IN3 input is reserved. */ -#define IMXRT_XBARB3_IN_RESERVED4 IMXRT_XBARB3(XBAR_INPUT, 4) /* XBARB3_IN4 input is reserved. */ -#define IMXRT_XBARB3_IN_RESERVED5 IMXRT_XBARB3(XBAR_INPUT, 5) /* XBARB3_IN5 input is reserved. */ -#define IMXRT_XBARB3_IN_ACMP1_OUT IMXRT_XBARB3(XBAR_INPUT, 6) /* ACMP1_OUT output assigned to XBARB3_IN6 input. */ -#define IMXRT_XBARB3_IN_ACMP2_OUT IMXRT_XBARB3(XBAR_INPUT, 7) /* ACMP2_OUT output assigned to XBARB3_IN7 input. */ -#define IMXRT_XBARB3_IN_ACMP3_OUT IMXRT_XBARB3(XBAR_INPUT, 8) /* ACMP3_OUT output assigned to XBARB3_IN8 input. */ -#define IMXRT_XBARB3_IN_ACMP4_OUT IMXRT_XBARB3(XBAR_INPUT, 9) /* ACMP4_OUT output assigned to XBARB3_IN9 input. */ -#define IMXRT_XBARB3_IN_RESERVED10 IMXRT_XBARB3(XBAR_INPUT, 10) /* XBARB3_IN10 input is reserved. */ -#define IMXRT_XBARB3_IN_RESERVED11 IMXRT_XBARB3(XBAR_INPUT, 11) /* XBARB3_IN11 input is reserved. */ -#define IMXRT_XBARB3_IN_QTIMER3_TMR0_OUT IMXRT_XBARB3(XBAR_INPUT, 12) /* QTIMER3_TMR0_OUTPUT output assigned to XBARB3_IN12 input. */ -#define IMXRT_XBARB3_IN_QTIMER3_TMR1_OUT IMXRT_XBARB3(XBAR_INPUT, 13) /* QTIMER3_TMR1_OUTPUT output assigned to XBARB3_IN13 input. */ -#define IMXRT_XBARB3_IN_QTIMER3_TMR2_OUT IMXRT_XBARB3(XBAR_INPUT, 14) /* QTIMER3_TMR2_OUTPUT output assigned to XBARB3_IN14 input. */ -#define IMXRT_XBARB3_IN_QTIMER3_TMR3_OUT IMXRT_XBARB3(XBAR_INPUT, 15) /* QTIMER3_TMR3_OUTPUT output assigned to XBARB3_IN15 input. */ -#define IMXRT_XBARB3_IN_QTIMER4_TMR0_OUT IMXRT_XBARB3(XBAR_INPUT, 16) /* QTIMER4_TMR0_OUTPUT output assigned to XBARB3_IN16 input. */ -#define IMXRT_XBARB3_IN_QTIMER4_TMR1_OUT IMXRT_XBARB3(XBAR_INPUT, 17) /* QTIMER4_TMR1_OUTPUT output assigned to XBARB3_IN17 input. */ -#define IMXRT_XBARB3_IN_QTIMER4_TMR2_OUT IMXRT_XBARB3(XBAR_INPUT, 18) /* QTIMER4_TMR2_OUTPUT output assigned to XBARB3_IN18 input. */ -#define IMXRT_XBARB3_IN_QTIMER4_TMR3_OUT IMXRT_XBARB3(XBAR_INPUT, 19) /* QTIMER4_TMR3_OUTPUT output assigned to XBARB3_IN19 input. */ -#define IMXRT_XBARB3_IN_FLEXPWM1_PWM1_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 20) /* FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN20 input. */ -#define IMXRT_XBARB3_IN_FLEXPWM1_PWM2_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 21) /* FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN21 input. */ -#define IMXRT_XBARB3_IN_FLEXPWM1_PWM3_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 22) /* FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN22 input. */ -#define IMXRT_XBARB3_IN_FLEXPWM1_PWM4_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 23) /* FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN23 input. */ -#define IMXRT_XBARB3_IN_FLEXPWM2_PWM1_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 24) /* FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN24 input. */ -#define IMXRT_XBARB3_IN_FLEXPWM2_PWM2_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 25) /* FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN25 input. */ -#define IMXRT_XBARB3_IN_FLEXPWM2_PWM3_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 26) /* FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN26 input. */ -#define IMXRT_XBARB3_IN_FLEXPWM2_PWM4_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 27) /* FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN27 input. */ -#define IMXRT_XBARB3_IN_FLEXPWM3_PWM1_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 28) /* FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN28 input. */ -#define IMXRT_XBARB3_IN_FLEXPWM3_PWM2_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 29) /* FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN29 input. */ -#define IMXRT_XBARB3_IN_FLEXPWM3_PWM3_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 30) /* FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN30 input. */ -#define IMXRT_XBARB3_IN_FLEXPWM3_PWM4_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 31) /* FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN31 input. */ -#define IMXRT_XBARB3_IN_FLEXPWM4_PWM1_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 32) /* FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN32 input. */ -#define IMXRT_XBARB3_IN_FLEXPWM4_PWM2_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 33) /* FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN33 input. */ -#define IMXRT_XBARB3_IN_FLEXPWM4_PWM3_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 34) /* FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN34 input. */ -#define IMXRT_XBARB3_IN_FLEXPWM4_PWM4_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 35) /* FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN35 input. */ -#define IMXRT_XBARB3_IN_PIT_TRIGGER0 IMXRT_XBARB3(XBAR_INPUT, 36) /* PIT_TRIGGER0 output assigned to XBARB3_IN36 input. */ -#define IMXRT_XBARB3_IN_PIT_TRIGGER1 IMXRT_XBARB3(XBAR_INPUT, 37) /* PIT_TRIGGER1 output assigned to XBARB3_IN37 input. */ -#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO0 IMXRT_XBARB3(XBAR_INPUT, 38) /* ADC_ETC_XBAR0_COCO0 output assigned to XBARB3_IN38 input. */ -#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO1 IMXRT_XBARB3(XBAR_INPUT, 39) /* ADC_ETC_XBAR0_COCO1 output assigned to XBARB3_IN39 input. */ -#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO2 IMXRT_XBARB3(XBAR_INPUT, 40) /* ADC_ETC_XBAR0_COCO2 output assigned to XBARB3_IN40 input. */ -#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO3 IMXRT_XBARB3(XBAR_INPUT, 41) /* ADC_ETC_XBAR0_COCO3 output assigned to XBARB3_IN41 input. */ -#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO0 IMXRT_XBARB3(XBAR_INPUT, 42) /* ADC_ETC_XBAR1_COCO0 output assigned to XBARB3_IN42 input. */ -#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO1 IMXRT_XBARB3(XBAR_INPUT, 43) /* ADC_ETC_XBAR1_COCO1 output assigned to XBARB3_IN43 input. */ -#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO2 IMXRT_XBARB3(XBAR_INPUT, 44) /* ADC_ETC_XBAR1_COCO2 output assigned to XBARB3_IN44 input. */ -#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO3 IMXRT_XBARB3(XBAR_INPUT, 45) /* ADC_ETC_XBAR1_COCO3 output assigned to XBARB3_IN45 input. */ -#define IMXRT_XBARB3_IN_ENC1_POS_MATCH IMXRT_XBARB3(XBAR_INPUT, 46) /* ENC1_POS_MATCH output assigned to XBARB3_IN46 input. */ -#define IMXRT_XBARB3_IN_ENC2_POS_MATCH IMXRT_XBARB3(XBAR_INPUT, 47) /* ENC2_POS_MATCH output assigned to XBARB3_IN47 input. */ -#define IMXRT_XBARB3_IN_ENC3_POS_MATCH IMXRT_XBARB3(XBAR_INPUT, 48) /* ENC3_POS_MATCH output assigned to XBARB3_IN48 input. */ -#define IMXRT_XBARB3_IN_ENC4_POS_MATCH IMXRT_XBARB3(XBAR_INPUT, 49) /* ENC4_POS_MATCH output assigned to XBARB3_IN49 input. */ -#define IMXRT_XBARB3_IN_DMA_DONE0 IMXRT_XBARB3(XBAR_INPUT, 50) /* DMA_DONE0 output assigned to XBARB3_IN50 input. */ -#define IMXRT_XBARB3_IN_DMA_DONE1 IMXRT_XBARB3(XBAR_INPUT, 51) /* DMA_DONE1 output assigned to XBARB3_IN51 input. */ -#define IMXRT_XBARB3_IN_DMA_DONE2 IMXRT_XBARB3(XBAR_INPUT, 52) /* DMA_DONE2 output assigned to XBARB3_IN52 input. */ -#define IMXRT_XBARB3_IN_DMA_DONE3 IMXRT_XBARB3(XBAR_INPUT, 53) /* DMA_DONE3 output assigned to XBARB3_IN53 input. */ -#define IMXRT_XBARB3_IN_DMA_DONE4 IMXRT_XBARB3(XBAR_INPUT, 54) /* DMA_DONE4 output assigned to XBARB3_IN54 input. */ -#define IMXRT_XBARB3_IN_DMA_DONE5 IMXRT_XBARB3(XBAR_INPUT, 55) /* DMA_DONE5 output assigned to XBARB3_IN55 input. */ -#define IMXRT_XBARB3_IN_DMA_DONE6 IMXRT_XBARB3(XBAR_INPUT, 56) /* DMA_DONE6 output assigned to XBARB3_IN56 input. */ -#define IMXRT_XBARB3_IN_DMA_DONE7 IMXRT_XBARB3(XBAR_INPUT, 57) /* DMA_DONE7 output assigned to XBARB3_IN57 input. */ - -/* XBARB3 Mux Output (M Muxes) ********************************************************************************************************************/ - -#define IMXRT_XBARB3_OUT_AOI2_IN00_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 0) /* XBARB3_OUT0 output assigned to AOI2_IN00 */ -#define IMXRT_XBARB3_OUT_AOI2_IN01_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 1) /* XBARB3_OUT1 output assigned to AOI2_IN01 */ -#define IMXRT_XBARB3_OUT_AOI2_IN02_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 2) /* XBARB3_OUT2 output assigned to AOI2_IN02 */ -#define IMXRT_XBARB3_OUT_AOI2_IN03_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 3) /* XBARB3_OUT3 output assigned to AOI2_IN03 */ -#define IMXRT_XBARB3_OUT_AOI2_IN04_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 4) /* XBARB3_OUT4 output assigned to AOI2_IN04 */ -#define IMXRT_XBARB3_OUT_AOI2_IN05_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 5) /* XBARB3_OUT5 output assigned to AOI2_IN05 */ -#define IMXRT_XBARB3_OUT_AOI2_IN06_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 6) /* XBARB3_OUT6 output assigned to AOI2_IN06 */ -#define IMXRT_XBARB3_OUT_AOI2_IN07_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 7) /* XBARB3_OUT7 output assigned to AOI2_IN07 */ -#define IMXRT_XBARB3_OUT_AOI2_IN08_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 8) /* XBARB3_OUT8 output assigned to AOI2_IN08 */ -#define IMXRT_XBARB3_OUT_AOI2_IN09_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 9) /* XBARB3_OUT9 output assigned to AOI2_IN09 */ -#define IMXRT_XBARB3_OUT_AOI2_IN10_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 10) /* XBARB3_OUT10 output assigned to AOI2_IN10 */ -#define IMXRT_XBARB3_OUT_AOI2_IN11_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 11) /* XBARB3_OUT11 output assigned to AOI2_IN11 */ -#define IMXRT_XBARB3_OUT_AOI2_IN12_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 12) /* XBARB3_OUT12 output assigned to AOI2_IN12 */ -#define IMXRT_XBARB3_OUT_AOI2_IN13_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 13) /* XBARB3_OUT13 output assigned to AOI2_IN13 */ -#define IMXRT_XBARB3_OUT_AOI2_IN14_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 14) /* XBARB3_OUT14 output assigned to AOI2_IN14 */ -#define IMXRT_XBARB3_OUT_AOI2_IN15_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 15) /* XBARB3_OUT15 output assigned to AOI2_IN15 */ diff --git a/arch/arm/src/imxrt/chip/rt106x/imxrt106x_ccm.h b/arch/arm/src/imxrt/chip/rt106x/imxrt106x_ccm.h deleted file mode 100644 index d9bb263e082..00000000000 --- a/arch/arm/src/imxrt/chip/rt106x/imxrt106x_ccm.h +++ /dev/null @@ -1,1144 +0,0 @@ -/************************************************************************************************************ - * arch/arm/src/imxrt/chip/rt106x/imxrt_ccm.h - * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Authors: Janne Rosberg - * David Sidrane - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_CCM_H -#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_CCM_H - -/************************************************************************************************************ - * Included Files - ************************************************************************************************************/ - -#include -#include "chip/imxrt_memorymap.h" - -/************************************************************************************************************ - * Pre-processor Definitions - ************************************************************************************************************/ - -/* Register offsets *****************************************************************************************/ - -#define IMXRT_CCM_CCR_OFFSET 0x0000 /* CCM Control Register */ - /* 0x0004 Reserved */ -#define IMXRT_CCM_CSR_OFFSET 0x0008 /* CCM Status Register */ -#define IMXRT_CCM_CCSR_OFFSET 0x000c /* CCM Clock Switcher Register */ -#define IMXRT_CCM_CACRR_OFFSET 0x0010 /* CCM Arm Clock Root Register */ -#define IMXRT_CCM_CBCDR_OFFSET 0x0014 /* CCM Bus Clock Divider Register */ -#define IMXRT_CCM_CBCMR_OFFSET 0x0018 /* CCM Bus Clock Multiplexer Register */ -#define IMXRT_CCM_CSCMR1_OFFSET 0x001c /* CCM Serial Clock Multiplexer Register 1 */ -#define IMXRT_CCM_CSCMR2_OFFSET 0x0020 /* CCM Serial Clock Multiplexer Register 2 */ -#define IMXRT_CCM_CSCDR1_OFFSET 0x0024 /* CCM Serial Clock Divider Register 1 */ -#define IMXRT_CCM_CS1CDR_OFFSET 0x0028 /* CCM Clock Divider Register */ -#define IMXRT_CCM_CS2CDR_OFFSET 0x002c /* CCM Clock Divider Register */ -#define IMXRT_CCM_CDCDR_OFFSET 0x0030 /* CCM D1 Clock Divider Register */ - /* 0x0034 Reserved */ -#define IMXRT_CCM_CSCDR2_OFFSET 0x0038 /* CCM Serial Clock Divider Register 2 */ -#define IMXRT_CCM_CSCDR3_OFFSET 0x003c /* CCM Serial Clock Divider Register 3 */ - /* 0x0040 Reserved */ - /* 0x0044 Reserved */ -#define IMXRT_CCM_CDHIPR_OFFSET 0x0048 /* CCM Divider Handshake In-Process Register */ - /* 0x004c Reserved */ - /* 0x0050 Reserved */ -#define IMXRT_CCM_CLPCR_OFFSET 0x0054 /* CCM Low Power Control Register */ - -#define IMXRT_CCM_CISR_OFFSET 0x0058 /* CCM Interrupt Status Register */ -#define IMXRT_CCM_CIMR_OFFSET 0x005c /* CCM Interrupt Mask Register */ -#define IMXRT_CCM_CCOSR_OFFSET 0x0060 /* CCM Clock Output Source Register */ -#define IMXRT_CCM_CGPR_OFFSET 0x0064 /* CCM General Purpose Register */ -#define IMXRT_CCM_CCGR0_OFFSET 0x0068 /* CCM Clock Gating Register 0 */ -#define IMXRT_CCM_CCGR1_OFFSET 0x006c /* CCM Clock Gating Register 1 */ -#define IMXRT_CCM_CCGR2_OFFSET 0x0070 /* CCM Clock Gating Register 2 */ -#define IMXRT_CCM_CCGR3_OFFSET 0x0074 /* CCM Clock Gating Register 3 */ -#define IMXRT_CCM_CCGR4_OFFSET 0x0078 /* CCM Clock Gating Register 4 */ -#define IMXRT_CCM_CCGR5_OFFSET 0x007c /* CCM Clock Gating Register 5 */ -#define IMXRT_CCM_CCGR6_OFFSET 0x0080 /* CCM Clock Gating Register 6 */ - /* 0x0084 Reserved */ -#define IMXRT_CCM_CMEOR_OFFSET 0x0088 /* CCM Module Enable Overide Register */ - -/* Analog */ - -#define IMXRT_CCM_ANALOG_PLL_ARM_OFFSET 0x0000 /* Analog ARM PLL control Register */ -#define IMXRT_CCM_ANALOG_PLL_USB1_OFFSET 0x0010 /* Analog USB1 480MHz PLL Control Register */ -#define IMXRT_CCM_ANALOG_PLL_USB2_OFFSET 0x0020 /* Analog USB2 480MHz PLL Control Register */ -#define IMXRT_CCM_ANALOG_PLL_SYS_OFFSET 0x0030 /* Analog System PLL Control Register */ -#define IMXRT_CCM_ANALOG_PLL_SYS_SS_OFFSET 0x0040 /* 528MHz System PLL Spread Spectrum Register */ -#define IMXRT_CCM_ANALOG_PLL_SYS_NUM_OFFSET 0x0050 /* Numerator of 528MHz System PLL Fractional Loop Divider */ -#define IMXRT_CCM_ANALOG_PLL_SYS_DENOM_OFFSET 0x0060 /* Denominator of 528MHz System PLL Fractional Loop Divider */ -#define IMXRT_CCM_ANALOG_PLL_AUDIO_OFFSET 0x0070 /* Analog Audio PLL control Register */ -#define IMXRT_CCM_ANALOG_PLL_AUDIO_NUM_OFFSET 0x0080 /* Numerator of Audio PLL Fractional Loop Divider */ -#define IMXRT_CCM_ANALOG_PLL_AUDIO_DENOM_OFFSET 0x0090 /* Denominator of Audio PLL Fractional Loop Divider */ -#define IMXRT_CCM_ANALOG_PLL_VIDEO_OFFSET 0x00a0 /* Analog Video PLL control Register */ -#define IMXRT_CCM_ANALOG_PLL_VIDEO_NUM_OFFSET 0x00b0 /* Numerator of Video PLL Fractional Loop Divider */ -#define IMXRT_CCM_ANALOG_PLL_VIDEO_DENOM_OFFSET 0x00c0 /* Denominator of Video PLL Fractional Loop Divider */ -#define IMXRT_CCM_ANALOG_PLL_ENET_OFFSET 0x00e0 /* Analog ENET PLL Control Register */ -#define IMXRT_CCM_ANALOG_PFD_480_OFFSET 0x00f0 /* 480MHz Clock (PLL3) Phase Fractional Divider Control */ -#define IMXRT_CCM_ANALOG_PFD_528_OFFSET 0x0100 /* 528MHz Clock (PLL2) Phase Fractional Divider Control */ -#define IMXRT_CCM_ANALOG_MISC0_OFFSET 0x0150 /* Miscellaneous Register 0 */ -#define IMXRT_CCM_ANALOG_MISC1_OFFSET 0x0160 /* Miscellaneous Register 1 */ -#define IMXRT_CCM_ANALOG_MISC2_OFFSET 0x0170 /* Miscellaneous Register 2 */ - -/* Register addresses ***************************************************************************************/ - -#define IMXRT_CCM_CCR (IMXRT_CCM_BASE + IMXRT_CCM_CCR_OFFSET) -#define IMXRT_CCM_CSR (IMXRT_CCM_BASE + IMXRT_CCM_CSR_OFFSET) -#define IMXRT_CCM_CCSR (IMXRT_CCM_BASE + IMXRT_CCM_CCSR_OFFSET) -#define IMXRT_CCM_CACRR (IMXRT_CCM_BASE + IMXRT_CCM_CACRR_OFFSET) -#define IMXRT_CCM_CBCDR (IMXRT_CCM_BASE + IMXRT_CCM_CBCDR_OFFSET) -#define IMXRT_CCM_CBCMR (IMXRT_CCM_BASE + IMXRT_CCM_CBCMR_OFFSET) -#define IMXRT_CCM_CSCMR1 (IMXRT_CCM_BASE + IMXRT_CCM_CSCMR1_OFFSET) -#define IMXRT_CCM_CSCMR2 (IMXRT_CCM_BASE + IMXRT_CCM_CSCMR2_OFFSET) -#define IMXRT_CCM_CSCDR1 (IMXRT_CCM_BASE + IMXRT_CCM_CSCDR1_OFFSET) -#define IMXRT_CCM_CS1CDR (IMXRT_CCM_BASE + IMXRT_CCM_CS1CDR_OFFSET) -#define IMXRT_CCM_CS2CDR (IMXRT_CCM_BASE + IMXRT_CCM_CS2CDR_OFFSET) -#define IMXRT_CCM_CDCDR (IMXRT_CCM_BASE + IMXRT_CCM_CDCDR_OFFSET) -#define IMXRT_CCM_CSCDR2 (IMXRT_CCM_BASE + IMXRT_CCM_CSCDR2_OFFSET) -#define IMXRT_CCM_CSCDR3 (IMXRT_CCM_BASE + IMXRT_CCM_CSCDR3_OFFSET) -#define IMXRT_CCM_CDHIPR (IMXRT_CCM_BASE + IMXRT_CCM_CDHIPR_OFFSET) -#define IMXRT_CCM_CLPCR (IMXRT_CCM_BASE + IMXRT_CCM_CLPCR_OFFSET) -#define IMXRT_CCM_CISR (IMXRT_CCM_BASE + IMXRT_CCM_CISR_OFFSET) -#define IMXRT_CCM_CIMR (IMXRT_CCM_BASE + IMXRT_CCM_CIMR_OFFSET) -#define IMXRT_CCM_CCOSR (IMXRT_CCM_BASE + IMXRT_CCM_CCOSR_OFFSET) -#define IMXRT_CCM_CGPR (IMXRT_CCM_BASE + IMXRT_CCM_CGPR_OFFSET) -#define IMXRT_CCM_CCGR0 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR0_OFFSET) -#define IMXRT_CCM_CCGR1 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR1_OFFSET) -#define IMXRT_CCM_CCGR2 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR2_OFFSET) -#define IMXRT_CCM_CCGR3 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR3_OFFSET) -#define IMXRT_CCM_CCGR4 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR4_OFFSET) -#define IMXRT_CCM_CCGR5 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR5_OFFSET) -#define IMXRT_CCM_CCGR6 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR6_OFFSET) -#define IMXRT_CCM_CMEOR (IMXRT_CCM_BASE + IMXRT_CCM_CMEOR_OFFSET) - -#define IMXRT_CCM_ANALOG_PLL_ARM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_ARM_OFFSET) -#define IMXRT_CCM_ANALOG_PLL_USB1 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_USB1_OFFSET) -#define IMXRT_CCM_ANALOG_PLL_USB2 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_USB2_OFFSET) -#define IMXRT_CCM_ANALOG_PLL_SYS (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_SYS_OFFSET) -#define IMXRT_CCM_ANALOG_PLL_SYS_SS (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_SYS_SS_OFFSET) -#define IMXRT_CCM_ANALOG_PLL_SYS_NUM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_SYS_NUM_OFFSET) -#define IMXRT_CCM_ANALOG_PLL_SYS_DENOM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_SYS_DENOM_OFFSET) -#define IMXRT_CCM_ANALOG_PLL_AUDIO (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_AUDIO_OFFSET) -#define IMXRT_CCM_ANALOG_PLL_AUDIO_NUM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_AUDIO_NUM_OFFSET) -#define IMXRT_CCM_ANALOG_PLL_AUDIO_DENOM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_AUDIO_DENOM_OFFSET) -#define IMXRT_CCM_ANALOG_PLL_VIDEO (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_VIDEO_OFFSET) -#define IMXRT_CCM_ANALOG_PLL_VIDEO_NUM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_VIDEO_NUM_OFFSET) -#define IMXRT_CCM_ANALOG_PLL_VIDEO_DENOM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_VIDEO_DENOM_OFFSET) -#define IMXRT_CCM_ANALOG_PLL_ENET (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_ENET_OFFSET) -#define IMXRT_CCM_ANALOG_PFD_480 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PFD_480_OFFSET) -#define IMXRT_CCM_ANALOG_PFD_528 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PFD_528_OFFSET) -#define IMXRT_CCM_ANALOG_MISC0 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_MISC0_OFFSET) -#define IMXRT_CCM_ANALOG_MISC1 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_MISC1_OFFSET) -#define IMXRT_CCM_ANALOG_MISC2 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_MISC2_OFFSET) - -/* Helper Macros *********************************************************************************/ - -#define CCM_PODF_FROM_DIVISOR(n) ((n)-1) /* PODF Values are divisor-1 */ - -/* Register bit definitions *********************************************************************************/ - -/* Control Register */ - -#define CCM_CCR_OSCNT_SHIFT (0) /* Bits 0-7: Oscillator ready counter value */ -#define CCM_CCR_OSCNT_MASK (0xff << CCM_CCR_OSCNT_SHIFT) -# define CCM_CCR_OSCNT(n) ((uint32_t)(n) << CCM_CCR_OSCNT_SHIFT) - /* Bits 8-11: Reserved */ -#define CCM_CCR_COSC_EN (1 << 12) /* Bit 12: On chip oscillator enable */ - /* Bits 13-20: Reserved */ -#define CCM_CCR_REG_BYPASS_COUNT_SHIFT (21) /* Bits 21-26: Counter for analog_reg_bypass */ -#define CCM_CCR_REG_BYPASS_COUNT_MASK (0x3f << CCM_CCR_REG_BYPASS_COUNT_SHIFT) -# define CCM_CCR_REG_BYPASS_COUNT(n) ((uint32_t)(n) << CCM_CCR_REG_BYPASS_COUNT_SHIFT) -#define CCM_CCR_RBC_EN (1 << 27) /* Bit 27: Enable for REG_BYPASS_COUNTER */ - /* Bits 28-31: Reserved */ -/* Status Register */ - -#define CCM_CSR_REF_EN_B (1 << 0) /* Bit 0: Status of the value of CCM_REF_EN_B */ - /* Bits 1-2: Reserved */ -#define CCM_CSR_CAMP2_READY (3 << 0) /* Bit 3: Status indication of CAMP2 */ - /* Bit 4: Reserved */ -#define CCM_CSR_COSC_READY (5 << 0) /* Bit 5: Status indication of on board oscillator */ - /* Bits 6-31: Reserved */ -/* Clock Switcher Register */ - -#define CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0) /* Bit 0: Selects source to generate pll3_sw_clk */ - -/* Arm Clock Root Register */ - -#define CCM_CACRR_ARM_PODF_SHIFT (0) /* Bits 0-2: Divider for ARM clock root */ -#define CCM_CACRR_ARM_PODF_MASK (0x3 << CCM_CACRR_ARM_PODF_SHIFT) -# define CCM_CACRR_ARM_PODF(n) ((uint32_t)(n) << CCM_CACRR_ARM_PODF_SHIFT) - -/* Bus Clock Divider Register */ - - /* Bits 0-5: Reserved */ -#define CCM_CBCDR_SEMC_CLK_SEL (1 << 6) /* Bit 6: SEMC clock source select */ -#define CCM_CBCDR_SEMC_ALT_CLK_SEL (1 << 7) /* Bit 7: SEMC alternative clock select */ -#define CCM_CBCDR_SEMC_ALT_CLK_SEL_PLL2 (0 << 7) /* Bit 7: PLL2 PFD2 will be selected */ -#define CCM_CBCDR_SEMC_ALT_CLK_SEL_PLL3 (1 << 7) /* Bit 7: PLL3 PFD1 will be selected */ -#define CCM_CBCDR_IPG_PODF_SHIFT (8) /* Bits 8-9: Divider for ipg podf */ -#define CCM_CBCDR_IPG_PODF_MASK (0x3 << CCM_CBCDR_IPG_PODF_SHIFT) -# define CCM_CBCDR_IPG_PODF(n) ((uint32_t)(n) << CCM_CBCDR_IPG_PODF_SHIFT) -#define CCM_CBCDR_AHB_PODF_SHIFT (10) /* Bits 10-12: Divider for AHB PODF */ -#define CCM_CBCDR_AHB_PODF_MASK (0x3 << CCM_CBCDR_AHB_PODF_SHIFT) -# define CCM_CBCDR_AHB_PODF(n) ((uint32_t)(n) << CCM_CBCDR_AHB_PODF_SHIFT) - /* Bits 13-15: Reserved */ -#define CCM_CBCDR_SEMC_PODF_SHIFT (16) /* Bits 16-18: Post divider for SEMC clock */ -#define CCM_CBCDR_SEMC_PODF_MASK (0x3 << CCM_CBCDR_SEMC_PODF_SHIFT) -# define CCM_CBCDR_SEMC_PODF(n) ((uint32_t)(n) << CCM_CBCDR_SEMC_PODF_SHIFT) - /* Bits 19-24: Reserved */ -#define CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25) /* Bit 25: Selector for peripheral main clock */ -#define CCM_CBCDR_PERIPH_CLK_SEL_MASK (1 << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT) -# define CCM_CBCDR_PERIPH_CLK_SEL(n) ((uint32_t)(n) << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT) -# define CCM_CBCDR_PERIPH_CLK_SEL_PRE_PERIPH (0) -# define CCM_CBCDR_PERIPH_CLK_SEL_PERIPH_CLK2 (1) - - /* Bit 26: Reserved */ -#define CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT (27) /* Bits 27-29: Divider for periph_clk2_podf */ -#define CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) -# define CCM_CBCDR_PERIPH_CLK2_PODF(n) ((uint32_t)(n) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) - /* Bits 30-31: Reserved */ - -/* Bus Clock Multiplexer Register */ - - /* Bits 0-3: Reserved */ -#define CCM_CBCMR_LPSPI_CLK_SEL_SHIFT (4) /* Bits 4-5: Selector for lpspi clock multiplexer */ -#define CCM_CBCMR_LPSPI_CLK_SEL_MASK (0x3 << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) -# define CCM_CBCMR_LPSPI_CLK_SEL(n) ((uint32_t)(n) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) -# define CCM_CBCMR_LPSPI_CLK_SEL_PLL3_PFD1 ((uint32_t)(0) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) -# define CCM_CBCMR_LPSPI_CLK_SEL_PLL3_PFD0 ((uint32_t)(1) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) -# define CCM_CBCMR_LPSPI_CLK_SEL_PLL2 ((uint32_t)(2) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) -# define CCM_CBCMR_LPSPI_CLK_SEL_PLL2_PFD2 ((uint32_t)(3) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) - /* Bits 6-11: Reserved */ -#define CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT (12) /* Bits 12-13: Selector for peripheral clk2 clock multiplexer */ -#define CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT) -# define CCM_CBCMR_PERIPH_CLK2_SEL(n) ((uint32_t)(n) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT) -# define CCM_CBCMR_PERIPH_CLK2_SEL_PLL3_SW ((uint32_t)(0) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT) -# define CCM_CBCMR_PERIPH_CLK2_SEL_OSC_CLK ((uint32_t)(1) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT) -# define CCM_CBCMR_PERIPH_CLK2_SEL_PLL2_BP ((uint32_t)(2) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT) -#define CCM_CBCMR_TRACE_CLK_SEL_SHIFT (14) /* Bits 14-15: Selector for Trace clock multiplexer */ -#define CCM_CBCMR_TRACE_CLK_SEL_MASK (0x3 << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) -# define CCM_CBCMR_TRACE_CLK_SEL(n) ((uint32_t)(n) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) -# define CCM_CBCMR_TRACE_CLK_SEL_PLL2 ((uint32_t)(0) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) -# define CCM_CBCMR_TRACE_CLK_SEL_PLL2_PFD2 ((uint32_t)(1) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) -# define CCM_CBCMR_TRACE_CLK_SEL_PLL2_PFD0 ((uint32_t)(2) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) -# define CCM_CBCMR_TRACE_CLK_SEL_PLL2_PFD1 ((uint32_t)(3) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) - /* Bits 16-17: Reserved */ -#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18) /* Bits 18-19: Selector for pre_periph clock multiplexer */ -#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT) -# define CCM_CBCMR_PRE_PERIPH_CLK_SEL(n) ((uint32_t)(n) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT) -# define CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL2 (0) -# define CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL2_PFD2 (1) -# define CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL2_PFD0 (2) -# define CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL1 (3) - /* Bits 20-22: Reserved */ -#define CCM_CBCMR_LCDIF_PODF_SHIFT (23) /* Bits 23-25: Post-divider for LCDIF clock */ -#define CCM_CBCMR_LCDIF_PODF_MASK (0x7 << CCM_CBCMR_LCDIF_PODF_SHIFT) -# define CCM_CBCMR_LCDIF_PODF(n) ((uint32_t)(n) << CCM_CBCMR_LCDIF_PODF_SHIFT) -#define CCM_CBCMR_LPSPI_PODF_SHIFT (26) /* Bits 26-28: Divider for LPSPI */ -#define CCM_CBCMR_LPSPI_PODF_MASK (0x7 << CCM_CBCMR_LPSPI_PODF_SHIFT) -# define CCM_CBCMR_LPSPI_PODF(n) ((uint32_t)(n) << CCM_CBCMR_LPSPI_PODF_SHIFT) - -/* Serial Clock Multiplexer Register 1 */ - -#define CCM_CSCMR1_PERCLK_PODF_SHIFT (0) /* Bits 0-5: Divider for perclk podf */ -#define CCM_CSCMR1_PERCLK_PODF_MASK (0x3f << CCM_CSCMR1_PERCLK_PODF_SHIFT) -# define CCM_CSCMR1_PERCLK_PODF(n) ((uint32_t)(n) << CCM_CSCMR1_PERCLK_PODF_SHIFT) -#define CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT (6) /* Bit 6: Selector for the perclk clock multiplexer */ -#define CCM_CSCMR1_PERCLK_CLK_SEL_MASK (1 << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT) -# define CCM_CSCMR1_PERCLK_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT) -# define CCM_CSCMR1_PERCLK_CLK_SEL_IPG_CLK_ROOT (0) -# define CCM_CSCMR1_PERCLK_CLK_SEL_OSC_CLK (1) - /* Bits 7-9: Reserved */ -#define CCM_CSCMR1_SAI1_CLK_SEL_SHIFT (10) /* Bits 10-11: Selector for sai1 clock multiplexer */ -#define CCM_CSCMR1_SAI1_CLK_SEL_MASK (0x3 << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT) -# define CCM_CSCMR1_SAI1_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT) -# define CCM_CSCMR1_SAI1_CLK_SEL_PLL3_PFD2 ((uint32_t)(0) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT) -# define CCM_CSCMR1_SAI1_CLK_SEL_PLL5 ((uint32_t)(1) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT) -# define CCM_CSCMR1_SAI1_CLK_SEL_PLL4 ((uint32_t)(2) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT) -#define CCM_CSCMR1_SAI2_CLK_SEL_SHIFT (12) /* Bits 12-13: Selector for sai2 clock multiplexer */ -#define CCM_CSCMR1_SAI2_CLK_SEL_MASK (0x3 << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT) -# define CCM_CSCMR1_SAI2_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT) -# define CCM_CSCMR1_SAI2_CLK_SEL_PLL3_PFD2 ((uint32_t)(0) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT) -# define CCM_CSCMR1_SAI2_CLK_SEL_PLL5 ((uint32_t)(1) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT) -# define CCM_CSCMR1_SAI2_CLK_SEL_PLL4 ((uint32_t)(2) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT) -#define CCM_CSCMR1_SAI3_CLK_SEL_SHIFT (14) /* Bits 14-15: Selector for sai3 clock multiplexer */ -#define CCM_CSCMR1_SAI3_CLK_SEL_MASK (0x3 << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT) -# define CCM_CSCMR1_SAI3_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT) -# define CCM_CSCMR1_SAI3_CLK_SEL_PLL3_PFD2 ((uint32_t)(0) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT) -# define CCM_CSCMR1_SAI3_CLK_SEL_PLL5 ((uint32_t)(1) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT) -# define CCM_CSCMR1_SAI3_CLK_SEL_PLL4 ((uint32_t)(2) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT) -#define CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16) /* Bit 16: Selector for usdhc1 clock multiplexer */ -# define CCM_CSCMR1_USDHC1_CLK_SEL_PLL2_PFD2 (0 << 16) /* derive clock from PLL2 PFD2 */ -# define CCM_CSCMR1_USDHC1_CLK_SEL_PLL2_PFD0 (1 << 16) /* derive clock from PLL2 PFD0 */ -#define CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17) /* Bit 17: Selector for usdhc2 clock multiplexer */ -# define CCM_CSCMR1_USDHC2_CLK_SEL_PLL2_PFD2 (0 << 17) /* derive clock from PLL2 PFD2 */ -# define CCM_CSCMR1_USDHC2_CLK_SEL_PLL2_PFD0 (1 << 17) /* derive clock from PLL2 PFD0 */ - /* Bits 18-22: Reserved */ -#define CCM_CSCMR1_FLEXSPI_PODF_SHIFT (23) /* Bits 23-25: Divider for flexspi clock root */ -#define CCM_CSCMR1_FLEXSPI_PODF_MASK (0x7 << CCM_CSCMR1_FLEXSPI_PODF_SHIFT) -# define CCM_CSCMR1_FLEXSPI_PODF(n) ((uint32_t)(n) << CCM_CSCMR1_FLEXSPI_PODF_SHIFT) - /* Bits 26-28: Reserved */ -#define CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT (29) /* Bits 29-30: Selector for flexspi clock multiplexer */ -#define CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK (0x3 << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) -# define CCM_CSCMR1_FLEXSPI_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) -# define CCM_CSCMR1_FLEXSPI_CLK_SEL_SEMC_CLK ((uint32_t)(0) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) -# define CCM_CSCMR1_FLEXSPI_CLK_SEL_PLL3_SW ((uint32_t)(1) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) -# define CCM_CSCMR1_FLEXSPI_CLK_SEL_PLL2_PFD2 ((uint32_t)(2) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) -# define CCM_CSCMR1_FLEXSPI_CLK_SEL_PLL3_PFD0 ((uint32_t)(3) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) - /* Bit 31: Reserved */ - -/* Serial Clock Multiplexer Register 2 */ - -#define CCM_CSCMR2_CAN_CLK_PODF_SHIFT (2) /* Bits 2-7: Divider for can clock podf */ -#define CCM_CSCMR2_CAN_CLK_PODF_MASK (0x3f << CCM_CSCMR2_CAN_CLK_PODF_SHIFT) -# define CCM_CSCMR2_CAN_CLK_PODF(n) ((uint32_t)(n) << CCM_CSCMR2_CAN_CLK_PODF_SHIFT) -#define CCM_CSCMR2_CAN_CLK_SEL_SHIFT (8) /* Bits 8-9: Selector for FlexCAN clock multiplexer */ -#define CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << CCM_CSCMR2_CAN_CLK_SEL_SHIFT) -# define CCM_CSCMR2_CAN_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT) -# define CCM_CSCMR2_CAN_CLK_SEL_PLL3_SW_60 ((uint32_t)(0) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT) -# define CCM_CSCMR2_CAN_CLK_SEL_OSC_CLK ((uint32_t)(1) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT) -# define CCM_CSCMR2_CAN_CLK_SEL_PLL3_SW_80 ((uint32_t)(2) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT) - /* Bits 10-18: Reserved */ -#define CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT (19) /* Bits 19-20: Selector for flexio2 clock multiplexer */ -#define CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK (0x3 << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT) -# define CCM_CSCMR2_FLEXIO2_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT) -# define CCM_CSCMR2_FLEXIO2_CLK_SEL_PLL4 ((uint32_t)(0) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT) -# define CCM_CSCMR2_FLEXIO2_CLK_SEL_PLL3_PFD2 ((uint32_t)(1) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT) -# define CCM_CSCMR2_FLEXIO2_CLK_SEL_PLL5 ((uint32_t)(2) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT) -# define CCM_CSCMR2_FLEXIO2_CLK_SEL_PLL3_SW ((uint32_t)(3) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT) - /* Bits 21-31: Reserved */ - -/* Serial Clock Divider Register 1 */ - -#define CCM_CSCDR1_UART_CLK_PODF_SHIFT (0) /* Bits 0-5: Divider for uart clock podf */ -#define CCM_CSCDR1_UART_CLK_PODF_MASK (0x3f << CCM_CSCDR1_UART_CLK_PODF_SHIFT) -# define CCM_CSCDR1_UART_CLK_PODF(n) ((uint32_t)(n) << CCM_CSCDR1_UART_CLK_PODF_SHIFT) -#define CCM_CSCDR1_UART_CLK_SEL (1 << 6) /* Bit 6: Selector for the UART clock multiplexer */ -# define CCM_CSCDR1_UART_CLK_SEL_PLL3_80 (0 << 6) /* derive clock from pll3_80m */ -# define CCM_CSCDR1_UART_CLK_SEL_OSC_CLK (1 << 6) /* derive clock from osc_clk */ - /* Bits 7-10: Reserved */ -#define CCM_CSCDR1_USDHC1_PODF_SHIFT (11) /* Bits 11-13: Divider for usdhc1 clock podf */ -#define CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << CCM_CSCDR1_USDHC1_PODF_SHIFT) -# define CCM_CSCDR1_USDHC1_PODF(n) ((uint32_t)(n) << CCM_CSCDR1_USDHC1_PODF_SHIFT) - /* Bits 14-15: Reserved */ -#define CCM_CSCDR1_USDHC2_PODF_SHIFT (16) /* Bits 16-18: Divider for usdhc2 clock */ -#define CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << CCM_CSCDR1_USDHC2_PODF_SHIFT) -# define CCM_CSCDR1_USDHC2_PODF(n) ((uint32_t)(n) << CCM_CSCDR1_USDHC2_PODF_SHIFT) - /* Bits 19-24: Reserved */ -#define CCM_CSCDR1_TRACE_PODF_SHIFT (25) /* Bits 25-27: Divider for trace clock */ -#define CCM_CSCDR1_TRACE_PODF_MASK (0x7 << CCM_CSCDR1_TRACE_PODF_SHIFT) -# define CCM_CSCDR1_TRACE_PODF(n) ((uint32_t)(n) << CCM_CSCDR1_TRACE_PODF_SHIFT) - /* Bits 28-31: Reserved */ - -/* Clock Divider Register 1 */ - -#define CCM_CS1CDR_SAI1_CLK_PODF_SHIFT (0) /* Bits 0-5: Divider for sai1 clock podf */ -#define CCM_CS1CDR_SAI1_CLK_PODF_MASK (0x3f << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT) -# define CCM_CS1CDR_SAI1_CLK_PODF(n) ((uint32_t)(n) << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT) -#define CCM_CS1CDR_SAI1_CLK_PRED_SHIFT (6) /* Bits 6-8: Divider for sai1 clock pred */ -#define CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x7 << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT) -# define CCM_CS1CDR_SAI1_CLK_PRED(n) ((uint32_t)(n) << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT) -#define CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT (9) /* Bits 9-11: Divider for flexio2 clock */ -#define CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK (0x7 << CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT) -# define CCM_CS1CDR_FLEXIO2_CLK_PRED(n) ((uint32_t)(n) << CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT) - /* Bits 12-15: Reserved */ -#define CCM_CS1CDR_SAI3_CLK_PODF_SHIFT (16) /* Bits 16-21: Divider for sai3 clock podf */ -#define CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3f << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT) -# define CCM_CS1CDR_SAI3_CLK_PODF(n) ((uint32_t)(n) << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT) -#define CCM_CS1CDR_SAI3_CLK_PRED_SHIFT (22) /* Bits 22-24: Divider for sai3 clock pred */ -#define CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x7 << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT) -# define CCM_CS1CDR_SAI3_CLK_PRED(n) ((uint32_t)(n) << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT) -#define CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT (25) /* Bits 25-27: Divider for flexio2 clock */ -#define CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK (0x7 << CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT) -# define CCM_CS1CDR_FLEXIO2_CLK_PODF(n) ((uint32_t)(n) << CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT) - /* Bits 28-31: Reserved */ - -/* Clock Divider Register 2 */ - -#define CCM_CS2CDR_SAI2_CLK_PODF_SHIFT (0) /* Bits 0-5: Divider for sai2 clock podf */ -#define CCM_CS2CDR_SAI2_CLK_PODF_MASK (0x3f << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT) -# define CCM_CS2CDR_SAI2_CLK_PODF(n) ((uint32_t)(n) << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT) -#define CCM_CS2CDR_SAI2_CLK_PRED_SHIFT (6) /* Bits 6-8: Divider for sai2 clock pred */ -#define CCM_CS2CDR_SAI2_CLK_PRED_MASK (0x7 << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT) -# define CCM_CS2CDR_SAI2_CLK_PRED(n) ((uint32_t)(n) << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT) - -/* D1 Clock Divider Register */ - -#define CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT (7) /* Bits 7-8: Selector for flexio1 clock multiplexer */ -#define CCM_CDCDR_FLEXIO1_CLK_SEL_MASK (0x3 << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT) -# define CCM_CDCDR_FLEXIO1_CLK_SEL(n) ((uint32_t)(n) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT) -# define CCM_CDCDR_FLEXIO1_CLK_SEL_PLL4 ((uint32_t)(0) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT) -# define CCM_CDCDR_FLEXIO1_CLK_SEL_PLL3_PFD2 ((uint32_t)(1) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT) -# define CCM_CDCDR_FLEXIO1_CLK_SEL_PLL3_PLL5 ((uint32_t)(2) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT) -# define CCM_CDCDR_FLEXIO1_CLK_SEL_PLL3_PLL3_SW ((uint32_t)(3) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT) -#define CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT (9) /* Bits 9-11: Divider for flexio1 clock podf */ -#define CCM_CDCDR_FLEXIO1_CLK_PODF_MASK (0x7 << CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT) -# define CCM_CDCDR_FLEXIO1_CLK_PODF(n) ((uint32_t)(n) << CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT) -#define CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT (12) /* Bits 12-14: Divider for flexio1 clock pred */ -#define CCM_CDCDR_FLEXIO1_CLK_PRED_MASK (0x7 << CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT) -# define CCM_CDCDR_FLEXIO1_CLK_PRED(n) ((uint32_t)(n) << CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT) - /* Bits 15-19: Reserved */ -#define CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT (20) /* Bits 20-21: Selector for spdif0 clock multiplexer */ -#define CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) -# define CCM_CDCDR_SPDIF0_CLK_SEL(n) ((uint32_t)(n) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) -# define CCM_CDCDR_SPDIF0_CLK_SEL_PLL4 ((uint32_t)(0) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) -# define CCM_CDCDR_SPDIF0_CLK_SEL_PLL3_PFD2 ((uint32_t)(1) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) -# define CCM_CDCDR_SPDIF0_CLK_SEL_PLL3_PLL5 ((uint32_t)(2) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) -# define CCM_CDCDR_SPDIF0_CLK_SEL_PLL3_PLL3_SW ((uint32_t)(3) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) -#define CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT (22) /* Bits 22-24: Divider for spdif0 clock podf */ -#define CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT) -# define CCM_CDCDR_SPDIF0_CLK_PODF(n) ((uint32_t)(n) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT) -#define CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT (25) /* Bits 25-27: Divider for spdif0 clock pred */ -#define CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT) -# define CCM_CDCDR_SPDIF0_CLK_PRED(n) ((uint32_t)(n) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT) - -/* Serial Clock Divider Register 2 */ - - /* Bits 0-8: Reserved */ -#define CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT (9) /* Bits 9-11: Selector for LCDIF root clock multiplexer */ -#define CCM_CSCDR2_LCDIF_CLK_SEL_MASK (0x7 << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT) -# define CCM_CSCDR2_LCDIF_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT) -# define CCM_CSCDR2_LCDIF_CLK_SEL_LCDIF ((uint32_t)(0) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT) -# define CCM_CSCDR2_LCDIF_CLK_SEL_IPP_DI0_CLK ((uint32_t)(1) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT) -# define CCM_CSCDR2_LCDIF_CLK_SEL_IPP_DI1_CLK ((uint32_t)(2) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT) -# define CCM_CSCDR2_LCDIF_CLK_SEL_IDB_DI0_CLK ((uint32_t)(3) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT) -# define CCM_CSCDR2_LCDIF_CLK_SEL_IDB_DI1_CLK ((uint32_t)(4) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT) -#define CCM_CSCDR2_LCDIF_PRED_SHIFT (12) /* Bits 12-14: Pre-divider for lcdif clock */ -#define CCM_CSCDR2_LCDIF_PRED_MASK (0x7 << CCM_CSCDR2_LCDIF_PRED_SHIFT) -# define CCM_CSCDR2_LCDIF_PRED(n) ((uint32_t)(n) << CCM_CSCDR2_LCDIF_PRED_SHIFT) -#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT (15) /* Bits 15-17: Selector for lcdif root clock pre-multiplexer */ -#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK (0x7 << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) -# define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_(n) ((uint32_t)(n) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) -# define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL2 ((uint32_t)(0) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) -# define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL3_PFD3 ((uint32_t)(1) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) -# define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL5 ((uint32_t)(2) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) -# define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL2_PFD0 ((uint32_t)(3) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) -# define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL2_PFD1 ((uint32_t)(4) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) -# define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL3_PFD1 ((uint32_t)(5) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) -#define CCM_CSCDR2_LPI2C_CLK_SEL (1 << 18) /* Bit 18: Selector for the LPI2C clock multiplexer */ -# define CCM_CSCDR2_LPI2C_CLK_SEL_PLL3_60M (0 << 18) /* derive clock from pll3_60m */ -# define CCM_CSCDR2_LPI2C_CLK_SEL_OSC_CLK (1 << 18) /* derive clock from ock_clk */ -#define CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT (19) /* Bits 19-24: Divider for lpi2c clock podf */ -#define CCM_CSCDR2_LPI2C_CLK_PODF_MASK (0x3f << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT) -# define CCM_CSCDR2_LPI2C_CLK_PODF(n) ((uint32_t)(n) << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT) - /* Bits 25-31: Reserved */ - -/* Serial Clock Divider Register 3 */ - - /* Bits 0-8: Reserved */ -#define CCM_CSCDR3_CSI_CLK_SEL_SHIFT (9) /* Bits 9-10: Selector for csi_mclk multiplexer */ -#define CCM_CSCDR3_CSI_CLK_SEL_MASK (0x3 << CCM_CSCDR3_CSI_CLK_SEL_SHIFT) -# define CCM_CSCDR3_CSI_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT) -# define CCM_CSCDR3_CSI_CLK_SEL_OSC_CLK ((uint32_t)(0) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT) -# define CCM_CSCDR3_CSI_CLK_SEL_OSC_PLL2_PFD2 ((uint32_t)(1) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT) -# define CCM_CSCDR3_CSI_CLK_SEL_OSC_PLL3_120M ((uint32_t)(2) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT) -# define CCM_CSCDR3_CSI_CLK_SEL_OSC_PLL3_PFD1 ((uint32_t)(3) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT) -#define CCM_CSCDR3_CSI_PODF_SHIFT (11) /* Bits 11-13: Post divider for csi_mclk */ -#define CCM_CSCDR3_CSI_PODF_MASK (0x3 << CCM_CSCDR3_CSI_PODF_SHIFT) -# define CCM_CSCDR3_CSI_PODF(n) ((uint32_t)(n) << CCM_CSCDR3_CSI_PODF_SHIFT) - -/* Divider Handshake In-Process Register */ - -#define CCM_CDHIPR_SEMC_PODF_BUSY (1 << 0) /* Bit 0: Busy indicator for semc_podf */ -#define CCM_CDHIPR_AHB_PODF_BUSY (1 << 1) /* Bit 1: Busy indicator for ahb_podf */ - /* Bit 2: Reserved */ -#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3) /* Bit 3: Busy indicator for periph2_clk_sel mux control */ - /* Bit 4: Reserved */ -#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5) /* Bit 5: Busy indicator for periph_clk_sel mux control */ - /* Bits 6-15: Reserved */ -#define CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) /* Bit 16: Busy indicator for arm_podf */ - /* Bits 17-31: Reserved */ - -/* Low Power Control Register */ - -#define CCM_CLPCR_LPM_SHIFT (0) /* Bits 0-1: Setting the low power mode */ -#define CCM_CLPCR_LPM_MASK (0x3 << CCM_CLPCR_LPM_SHIFT) -# define CCM_CLPCR_LPM(n) ((uint32_t)(n) << CCM_CLPCR_LPM_SHIFT) -# define CCM_CLPCR_LPM_RUN ((uint32_t)(0) << CCM_CLPCR_LPM_SHIFT) /* Remain in run mode */ -# define CCM_CLPCR_LPM_WAIT ((uint32_t)(1) << CCM_CLPCR_LPM_SHIFT) /* Transfer to wait mode */ -# define CCM_CLPCR_LPM_STOP ((uint32_t)(2) << CCM_CLPCR_LPM_SHIFT) /* Transfer to stop mode */ - /* Bits 2-4: Reserved */ -#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5) /* Bit 5: ARM clocks disabled on wait mode */ -#define CCM_CLPCR_SBYOS (1 << 6) /* Bit 6: Standby clock oscillator bit */ -#define CCM_CLPCR_DIS_REF_OSC (1 << 7) /* Bit 7: external high frequency oscillator disable */ -#define CCM_CLPCR_VSTBY (1 << 8) /* Bit 8: Voltage standby request bit */ -#define CCM_CLPCR_STBY_COUNT_SHIFT (9) /* Bits 9-10: Standby counter definition */ -#define CCM_CLPCR_STBY_COUNT_MASK (0x3 << CCM_CLPCR_STBY_COUNT_SHIFT) -# define CCM_CLPCR_STBY_COUNT(n) ((uint32_t)(n) << CCM_CLPCR_STBY_COUNT_SHIFT) -#define CCM_CLPCR_COSC_PWRDOWN (1 << 11) /* Bit 11: On chip oscillator power down */ - /* Bits 12-18: Reserved */ -#define CCM_CLPCR_BYPASS_LPM_HS1 (1 << 19) /* Bit 19: Bypass low power mode handshake */ - /* Bit 20: Reserved */ -#define CCM_CLPCR_BYPASS_LPM_HS0 (1 << 21) /* Bit 21: Bypass low power mode handshake */ -#define CCM_CLPCR_MASK_CORE0_WFI (1 << 22) /* Bit 22: Mask WFI of core0 for entering low power mode */ - /* Bits 23-25: Reserved */ -#define CCM_CLPCR_MASK_SCU_IDLE (1 << 26) /* Bit 26: Mask SCU IDLE for entering low power mode */ -#define CCM_CLPCR_MASK_L2CC_IDLE (1 << 27) /* Bit 27: Mask L2CC IDLE for entering low power mode */ - /* Bits 28-31: Reserved */ - -/* Interrupt Status Register */ - -#define CCM_CISR_LRF_PLL (1 << 0) /* Bit 0: CCM irq2, lock of all enabled and not bypassed PLLs */ - /* Bits 1-5: Reserved */ -#define CCM_CISR_COSC_READY (1 << 6) /* Bit 6: CCM irq2, on board oscillator ready */ - /* Bits 7-16: Reserved */ -#define CCM_CISR_SEMC_PODF_LOADED (1 << 17) /* Bit 17: CCM irq1, frequency change of semc_podf */ - /* Bit 18: Reserved */ -#define CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19) /* Bit 19: CCM irq1, frequency change of periph2_clk_sel */ -#define CCM_CISR_AHB_PODF_LOADED (1 << 20) /* Bit 20: CCM irq1, frequency change of ahb_podf */ - /* Bit 21: Reserved */ -#define CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22) /* Bit 22: CCM irq1, update of periph_clk_sel */ - /* Bits 23-25: Reserved */ -#define CCM_CISR_ARM_PODF_LOADED (1 << 26) /* Bit 26: CCM irq1, frequency change of arm_podf */ - /* Bits 27-31: Reserved */ - -/* Interrupt Mask Register */ - -#define CCM_CIMR_MASK_LRF_PLL (1 << 0) /* Bit 0: mask interrupt generation due to lrf of PLLs */ - /* Bits 1-5: Reserved */ -#define CCM_CIMR_MASK_COSC_READY (1 << 6) /* Bit 6: mask interrupt generation due to on board oscillator ready */ - /* Bits 7-16: Reserved */ -#define CCM_CIMR_MASK_SEMC_PODF_LOADED (1 << 17) /* Bit 17: mask interrupt generation due to frequency change of semc_podf */ - /* Bit 18: Reserved */ -#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 19) /* Bit 19: mask interrupt generation due to update of periph2_clk_sel */ -#define CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20) /* Bit 20: mask interrupt generation due to frequency change of ahb_podf */ - /* Bit 21: Reserved */ -#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22) /* Bit 22: mask interrupt generation due to update of periph_clk_sel */ - /* Bits 23-25: Reserved */ -#define CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26) /* Bit 26: mask interrupt generation due to frequency change of arm_podf */ - /* Bits 27-31: Reserved */ - -/* Clock Output Source Register */ - -#define CCM_CCOSR_CLKO1_SEL_SHIFT (0) /* Bits 0-3: Selection of the clock to be generated on CCM_CLKO1 */ -#define CCM_CCOSR_CLKO1_SEL_MASK (0xF << CCM_CCOSR_CLKO1_SEL_SHIFT) -# define CCM_CCOSR_CLKO1_SEL_SEMC_CLK ((uint32_t)(5) << CCM_CCOSR_CLKO1_SEL_SHIFT) -# define CCM_CCOSR_CLKO1_SEL_ENC_CLK ((uint32_t)(6) << CCM_CCOSR_CLKO1_SEL_SHIFT) -# define CCM_CCOSR_CLKO1_SEL_LCDIF_PIX_CLK ((uint32_t)(10) << CCM_CCOSR_CLKO1_SEL_SHIFT) -# define CCM_CCOSR_CLKO1_SEL_AHB_CLK ((uint32_t)(11) << CCM_CCOSR_CLKO1_SEL_SHIFT) -# define CCM_CCOSR_CLKO1_SEL_IPG_CLK ((uint32_t)(12) << CCM_CCOSR_CLKO1_SEL_SHIFT) -# define CCM_CCOSR_CLKO1_SEL_PER_CLK ((uint32_t)(13) << CCM_CCOSR_CLKO1_SEL_SHIFT) -# define CCM_CCOSR_CLKO1_SEL_CKIL_SYNC_CLK ((uint32_t)(14) << CCM_CCOSR_CLKO1_SEL_SHIFT) -# define CCM_CCOSR_CLKO1_SEL_PLL4_MAIN_CLK ((uint32_t)(15) << CCM_CCOSR_CLKO1_SEL_SHIFT) -#define CCM_CCOSR_CLKO1_DIV_SHIFT (4) /* Bits 4-6: Setting the divider of CCM_CLKO1 */ -#define CCM_CCOSR_CLKO1_DIV_MASK (0x7 << CCM_CCOSR_CLKO1_DIV_SHIFT) -# define CCM_CCOSR_CLKO1_DIV(n) ((uint32_t)(n) << CCM_CCOSR_CLKO1_DIV_SHIFT) -#define CCM_CCOSR_CLKO1_EN (1 << 7) /* Bit 7: Enable of CCM_CLKO1 clock */ -#define CCM_CCOSR_CLK_OUT_SEL (1 << 8) /* Bit 8: CCM_CLKO1 output to reflect CCM_CLKO1 or CCM_CLKO2 clocks */ - /* Bits 9-15: Reserved */ -#define CCM_CCOSR_CLKO2_SEL_SHIFT (16) /* Bits 16-20: Selection of the clock to be generated on CCM_CLKO2 */ -#define CCM_CCOSR_CLKO2_SEL_MASK (0x1F << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_USDHC1_CLK ((uint32_t)(3) << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_WRCK_CLK ((uint32_t)(5) << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_LPI2C_CLK ((uint32_t)(6) << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_CSI_CORE ((uint32_t)(11) << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_OSC_CLK ((uint32_t)(14) << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_USDHC2_CLK ((uint32_t)(17) << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_SAI1_CLK ((uint32_t)(18) << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_SAI2_CLK ((uint32_t)(19) << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_SAI3_CLK ((uint32_t)(20) << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_CAN_CLK ((uint32_t)(23) << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_FLEXSPI_CLK ((uint32_t)(27) << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_UART_CLK ((uint32_t)(28) << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_SPDIF0_CLK ((uint32_t)(29) << CCM_CCOSR_CLKO2_SEL_SHIFT) -#define CCM_CCOSR_CLKO2_DIV_SHIFT (21) /* Bits 21-23: Setting the divider of CCM_CLKO2 */ -#define CCM_CCOSR_CLKO2_DIV_MASK (0x7 << CCM_CCOSR_CLKO2_DIV_SHIFT) -# define CCM_CCOSR_CLKO2_DIV(n) ((uint32_t)(n) << CCM_CCOSR_CLKO2_DIV_SHIFT) -#define CCM_CCOSR_CLKO2_EN (1 << 24) /* Bit 24: Enable of CCM_CLKO2 clock */ - /* Bits 25-31: Reserved */ - -/* General Purpose Register */ - -#define CCM_CGPR_PMIC_DELAY_SCALER (1 << 0) /* Bit 0: Defines clock division of clock for stby_count */ - /* Bits 1-3: Reserved */ -#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4) /* Bit 4: allow fuse programing */ - /* Bits 5-13: Reserved */ -#define CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT (14) /* Bits 14-15: System memory DS control */ -#define CCM_CGPR_SYS_MEM_DS_CTRL_MASK (0x7 << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT) -# define CCM_CGPR_SYS_MEM_DS_CTRL(n) ((uint32_t)(n) << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT) -#define CCM_CGPR_FPL (1 << 16) /* Bit 16: Fast PLL enable */ -#define CCM_CGPR_INT_MEM_CLK_LPM (1 << 17) /* Bit 17: Control for the Deep Sleep signal to the ARM Platform memories */ - /* Bits 18-31: Reserved */ - -/* Clock Gating Register 0-6 */ - -#define CCM_CG_OFF (0) /* Clock is off during all modes */ -#define CCM_CG_RUN (1) /* Clock is on in run mode, but off in WAIT and STOP modes */ -#define CCM_CG_ALL (3) /* Clock is on during all modes, except STOP mode. */ - -#define CCM_CCGRX_CG_SHIFT(r) ((r) << 1) -#define CCM_CCGRX_CG_MASK(r) (0x3 << CCM_CCGRX_CG_SHIFT(r)) -# define CCM_CCGRX_CG(r,v) ((uint32_t)(v) << CCM_CCGRX_CG_SHIFT(r)) - -#define CCM_CCGRX_CG0_SHIFT (0) -#define CCM_CCGRX_CG0_MASK (0x3 << CCM_CCGRX_CG0_SHIFT) -# define CCM_CCGRX_CG0(n) ((uint32_t)(n) << CCM_CCGRX_CG0_SHIFT) -#define CCM_CCGRX_CG1_SHIFT (2) -#define CCM_CCGRX_CG1_MASK (0x3 << CCM_CCGRX_CG1_SHIFT) -# define CCM_CCGRX_CG1(n) ((uint32_t)(n) << CCM_CCGRX_CG1_SHIFT) -#define CCM_CCGRX_CG2_SHIFT (4) -#define CCM_CCGRX_CG2_MASK (0x3 << CCM_CCGRX_CG2_SHIFT) -# define CCM_CCGRX_CG2(n) ((uint32_t)(n) << CCM_CCGRX_CG2_SHIFT) -#define CCM_CCGRX_CG3_SHIFT (6) -#define CCM_CCGRX_CG3_MASK (0x3 << CCM_CCGRX_CG3_SHIFT) -# define CCM_CCGRX_CG3(n) ((uint32_t)(n) << CCM_CCGRX_CG3_SHIFT) -#define CCM_CCGRX_CG4_SHIFT (8) -#define CCM_CCGRX_CG4_MASK (0x3 << CCM_CCGRX_CG4_SHIFT) -# define CCM_CCGRX_CG4(n) ((uint32_t)(n) << CCM_CCGRX_CG4_SHIFT) -#define CCM_CCGRX_CG5_SHIFT (10) -#define CCM_CCGRX_CG5_MASK (0x3 << CCM_CCGRX_CG5_SHIFT) -# define CCM_CCGRX_CG5(n) ((uint32_t)(n) << CCM_CCGRX_CG5_SHIFT) -#define CCM_CCGRX_CG6_SHIFT (12) -#define CCM_CCGRX_CG6_MASK (0x3 << CCM_CCGRX_CG6_SHIFT) -# define CCM_CCGRX_CG6(n) ((uint32_t)(n) << CCM_CCGRX_CG6_SHIFT) -#define CCM_CCGRX_CG7_SHIFT (14) -#define CCM_CCGRX_CG7_MASK (0x3 << CCM_CCGRX_CG7_SHIFT) -# define CCM_CCGRX_CG7(n) ((uint32_t)(n) << CCM_CCGRX_CG7_SHIFT) -#define CCM_CCGRX_CG8_SHIFT (16) -#define CCM_CCGRX_CG8_MASK (0x3 << CCM_CCGRX_CG8_SHIFT) -# define CCM_CCGRX_CG8(n) ((uint32_t)(n) << CCM_CCGRX_CG8_SHIFT) -#define CCM_CCGRX_CG9_SHIFT (18) -#define CCM_CCGRX_CG9_MASK (0x3 << CCM_CCGRX_CG9_SHIFT) -# define CCM_CCGRX_CG9(n) ((uint32_t)(n) << CCM_CCGRX_CG9_SHIFT) -#define CCM_CCGRX_CG10_SHIFT (20) -#define CCM_CCGRX_CG10_MASK (0x3 << CCM_CCGRX_CG10_SHIFT) -# define CCM_CCGRX_CG10(n) ((uint32_t)(n) << CCM_CCGRX_CG10_SHIFT) -#define CCM_CCGRX_CG11_SHIFT (22) -#define CCM_CCGRX_CG11_MASK (0x3 << CCM_CCGRX_CG11_SHIFT) -# define CCM_CCGRX_CG11(n) ((uint32_t)(n) << CCM_CCGRX_CG11_SHIFT) -#define CCM_CCGRX_CG12_SHIFT (24) -#define CCM_CCGRX_CG12_MASK (0x3 << CCM_CCGRX_CG12_SHIFT) -# define CCM_CCGRX_CG12(n) ((uint32_t)(n) << CCM_CCGRX_CG12_SHIFT) -#define CCM_CCGRX_CG13_SHIFT (26) -#define CCM_CCGRX_CG13_MASK (0x3 << CCM_CCGRX_CG13_SHIFT) -# define CCM_CCGRX_CG13(n) ((uint32_t)(n) << CCM_CCGRX_CG13_SHIFT) -#define CCM_CCGRX_CG14_SHIFT (28) -#define CCM_CCGRX_CG14_MASK (0x3 << CCM_CCGRX_CG14_SHIFT) -# define CCM_CCGRX_CG14(n) ((uint32_t)(n) << CCM_CCGRX_CG14_SHIFT) -#define CCM_CCGRX_CG15_SHIFT (30) -#define CCM_CCGRX_CG15_MASK (0x3 << CCM_CCGRX_CG15_SHIFT) -# define CCM_CCGRX_CG15(n) ((uint32_t)(n) << CCM_CCGRX_CG15_SHIFT) - -/* Macros used by imxrt_periphclks.h */ - -#define CCM_CCGR_GPIO2 IMXRT_CCM_CCGR0, 15 -#define CCM_CCGR_LPUART2 IMXRT_CCM_CCGR0, 14 -#define CCM_CCGR_GPT2_SERIAL IMXRT_CCM_CCGR0, 13 -#define CCM_CCGR_GPT2_BUS IMXRT_CCM_CCGR0, 12 -#define CCM_CCGR_TRACE IMXRT_CCM_CCGR0, 11 -#define CCM_CCGR_CAN2_SERIAL IMXRT_CCM_CCGR0, 10 -#define CCM_CCGR_CAN2 IMXRT_CCM_CCGR0, 9 -#define CCM_CCGR_CAN1_SERIAL IMXRT_CCM_CCGR0, 8 -#define CCM_CCGR_CAN1 IMXRT_CCM_CCGR0, 7 -#define CCM_CCGR_LPUART3 IMXRT_CCM_CCGR0, 6 -#define CCM_CCGR_DCP IMXRT_CCM_CCGR0, 5 -#define CCM_CCGR_MQS IMXRT_CCM_CCGR0, 2 -#define CCM_CCGR_AIPS_TZ2 IMXRT_CCM_CCGR0, 1 -#define CCM_CCGR_AIPS_TZ1 IMXRT_CCM_CCGR0, 0 - -#define CCM_CCGR_CSU IMXRT_CCM_CCGR1, 14 -#define CCM_CCGR_GPIO1 IMXRT_CCM_CCGR1, 13 -#define CCM_CCGR_LPUART4 IMXRT_CCM_CCGR1, 12 -#define CCM_CCGR_GPT_SERIAL IMXRT_CCM_CCGR1, 11 -#define CCM_CCGR_GPT_BUS IMXRT_CCM_CCGR1, 10 -#define CCM_CCGR_ADC1 IMXRT_CCM_CCGR1, 8 -#define CCM_CCGR_AOI2 IMXRT_CCM_CCGR1, 7 -#define CCM_CCGR_PIT IMXRT_CCM_CCGR1, 6 -#define CCM_CCGR_ENET IMXRT_CCM_CCGR1, 5 -#define CCM_CCGR_ADC2 IMXRT_CCM_CCGR1, 4 -#define CCM_CCGR_LPSPI4 IMXRT_CCM_CCGR1, 3 -#define CCM_CCGR_LPSPI3 IMXRT_CCM_CCGR1, 2 -#define CCM_CCGR_LPSPI2 IMXRT_CCM_CCGR1, 1 -#define CCM_CCGR_LPSPI1 IMXRT_CCM_CCGR1, 0 - -#define CCM_CCGR_PXP IMXRT_CCM_CCGR2, 15 -#define CCM_CCGR_LCD IMXRT_CCM_CCGR2, 14 -#define CCM_CCGR_GPIO3 IMXRT_CCM_CCGR2, 13 -#define CCM_CCGR_XBAR2 IMXRT_CCM_CCGR2, 12 -#define CCM_CCGR_XBAR1 IMXRT_CCM_CCGR2, 11 -#define CCM_CCGR_IPMUX3 IMXRT_CCM_CCGR2, 10 -#define CCM_CCGR_IPMUX2 IMXRT_CCM_CCGR2, 9 -#define CCM_CCGR_IPMUX1 IMXRT_CCM_CCGR2, 8 -#define CCM_CCGR_XBAR3 IMXRT_CCM_CCGR2, 7 -#define CCM_CCGR_OCOTP_CTRL IMXRT_CCM_CCGR2, 6 -#define CCM_CCGR_LPI2C3 IMXRT_CCM_CCGR2, 5 -#define CCM_CCGR_LPI2C2 IMXRT_CCM_CCGR2, 4 -#define CCM_CCGR_LPI2C1 IMXRT_CCM_CCGR2, 3 -#define CCM_CCGR_IOMUXC_SNVS IMXRT_CCM_CCGR2, 2 -#define CCM_CCGR_CSI IMXRT_CCM_CCGR2, 1 - -#define CCM_CCGR_IOMUXC_SNVS_GPR IMXRT_CCM_CCGR3, 15 -#define CCM_CCGR_OCRAM IMXRT_CCM_CCGR3, 14 -#define CCM_CCGR_ACMP4 IMXRT_CCM_CCGR3, 13 -#define CCM_CCGR_ACMP3 IMXRT_CCM_CCGR3, 12 -#define CCM_CCGR_ACMP2 IMXRT_CCM_CCGR3, 11 -#define CCM_CCGR_ACMP1 IMXRT_CCM_CCGR3, 10 -#define CCM_CCGR_FLEXRAM IMXRT_CCM_CCGR3, 9 -#define CCM_CCGR_WDOG1 IMXRT_CCM_CCGR3, 8 -#define CCM_CCGR_EWM IMXRT_CCM_CCGR3, 7 -#define CCM_CCGR_GPIO4 IMXRT_CCM_CCGR3, 6 -#define CCM_CCGR_LCDIF_PIX IMXRT_CCM_CCGR3, 5 -#define CCM_CCGR_AOI1 IMXRT_CCM_CCGR3, 4 -#define CCM_CCGR_LPUART6 IMXRT_CCM_CCGR3, 3 -#define CCM_CCGR_SEMC IMXRT_CCM_CCGR3, 2 -#define CCM_CCGR_LPUART5 IMXRT_CCM_CCGR3, 1 -#define CCM_CCGR_FLEXIO2 IMXRT_CCM_CCGR3, 0 - -#define CCM_CCGR_ENC4 IMXRT_CCM_CCGR4, 15 -#define CCM_CCGR_ENC3 IMXRT_CCM_CCGR4, 14 -#define CCM_CCGR_ENC2 IMXRT_CCM_CCGR4, 13 -#define CCM_CCGR_ENC1 IMXRT_CCM_CCGR4, 12 -#define CCM_CCGR_PWM4 IMXRT_CCM_CCGR4, 11 -#define CCM_CCGR_PWM3 IMXRT_CCM_CCGR4, 10 -#define CCM_CCGR_PWM2 IMXRT_CCM_CCGR4, 9 -#define CCM_CCGR_PWM1 IMXRT_CCM_CCGR4, 8 -#define CCM_CCGR_SIM_EMS IMXRT_CCM_CCGR4, 7 -#define CCM_CCGR_SIM_M IMXRT_CCM_CCGR4, 6 -#define CCM_CCGR_TSC_DIG IMXRT_CCM_CCGR4, 5 -#define CCM_CCGR_SIM_M7 IMXRT_CCM_CCGR4, 4 -#define CCM_CCGR_BEE IMXRT_CCM_CCGR4, 3 -#define CCM_CCGR_IOMUXC_GPR IMXRT_CCM_CCGR4, 2 -#define CCM_CCGR_IOMUXC IMXRT_CCM_CCGR4, 1 - -#define CCM_CCGR_SNVS_LP IMXRT_CCM_CCGR5, 15 -#define CCM_CCGR_SNVS_HP IMXRT_CCM_CCGR5, 14 -#define CCM_CCGR_LPUART7 IMXRT_CCM_CCGR5, 13 -#define CCM_CCGR_LPUART1 IMXRT_CCM_CCGR5, 12 -#define CCM_CCGR_SAI3 IMXRT_CCM_CCGR5, 11 -#define CCM_CCGR_SAI2 IMXRT_CCM_CCGR5, 10 -#define CCM_CCGR_SAI1 IMXRT_CCM_CCGR5, 9 -#define CCM_CCGR_SIM_MAIN IMXRT_CCM_CCGR5, 8 -#define CCM_CCGR_SPDIF IMXRT_CCM_CCGR5, 7 -#define CCM_CCGR_AIPSTZ4 IMXRT_CCM_CCGR5, 6 -#define CCM_CCGR_WDOG2 IMXRT_CCM_CCGR5, 5 -#define CCM_CCGR_KPP IMXRT_CCM_CCGR5, 4 -#define CCM_CCGR_DMA IMXRT_CCM_CCGR5, 3 -#define CCM_CCGR_WDOG3 IMXRT_CCM_CCGR5, 2 -#define CCM_CCGR_FLEXIO1 IMXRT_CCM_CCGR5, 1 -#define CCM_CCGR_ROM IMXRT_CCM_CCGR5, 0 - -#define CCM_CCGR_TIMER3 IMXRT_CCM_CCGR6, 15 -#define CCM_CCGR_TIMER2 IMXRT_CCM_CCGR6, 14 -#define CCM_CCGR_TIMER1 IMXRT_CCM_CCGR6, 13 -#define CCM_CCGR_LPI2C4_SERIAL IMXRT_CCM_CCGR6, 12 -#define CCM_CCGR_ANADIG IMXRT_CCM_CCGR6, 11 -#define CCM_CCGR_SIM_PER IMXRT_CCM_CCGR6, 10 -#define CCM_CCGR_AIPS_TZ3 IMXRT_CCM_CCGR6, 9 -#define CCM_CCGR_TIMER4 IMXRT_CCM_CCGR6, 8 -#define CCM_CCGR_LPUART8 IMXRT_CCM_CCGR6, 7 -#define CCM_CCGR_TRNG IMXRT_CCM_CCGR6, 6 -#define CCM_CCGR_FLEXSPI IMXRT_CCM_CCGR6, 5 -#define CCM_CCGR_IPMUX4 IMXRT_CCM_CCGR6, 4 -#define CCM_CCGR_DCDC IMXRT_CCM_CCGR6, 3 -#define CCM_CCGR_USDHC2 IMXRT_CCM_CCGR6, 2 -#define CCM_CCGR_USDHC1 IMXRT_CCM_CCGR6, 1 -#define CCM_CCGR_USBOH3 IMXRT_CCM_CCGR6, 0 - -/* Module Enable Override Register */ - - /* Bits 0-4: Reserved */ -#define CCM_CMEOR_MOD_EN_OV_GPT (1 << 5) /* Bit 5: Overide clock enable signal from GPT */ -#define CCM_CMEOR_MOD_EN_OV_PIT (1 << 6) /* Bit 6: Overide clock enable signal from PIT */ -#define CCM_CMEOR_MOD_EN_OV_USDHC (1 << 7) /* Bit 7: Overide clock enable signal from USDHC */ -#define CCM_CMEOR_MOD_EN_OV_TRNG (1 << 9) /* Bit 9: Overide clock enable signal from TRNG */ - /* Bits 10-27: Reserved */ -#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI (1 << 28) /* Bit 28: Overide clock enable signal from CAN2 */ -#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI (1 << 30) /* Bit 30: Overide clock enable signal from CAN1 */ - /* Bit 31: Reserved */ - -/* Analog ARM PLL control Register */ - -#define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT (0) /* Bits 0-6: This field controls the PLL loop divider 54-108 */ -#define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK (0x7f << CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_ARM_DIV_SELECT(n) ((uint32_t)(n) << CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT) - /* Bits 7-11 Reserved */ -#define CCM_ANALOG_PLL_ARM_POWERDOWN (1 << 12) /* Bit 12: Powers down the PLL */ -#define CCM_ANALOG_PLL_ARM_ENABLE (1 << 13) /* Bit 13: Enable the clock output */ -#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ -#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT) -# define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ -# define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ -#define CCM_ANALOG_PLL_ARM_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ - /* Bits 17-18 Reserved */ -#define CCM_ANALOG_PLL_ARM_PLL_SEL (1 << 39) /* Bit 19: ? */ -#define CCM_ANALOG_PLL_ARM_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ - -/* Analog USB1 480MHz PLL Control Register */ - -#define CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT (1) /* Bits 0-1: This field controls the PLL loop divider 20 or 22 */ -#define CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK (0x1 << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_USB1_DIV_SELECT_20 ((uint32_t)(0) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_USB1_DIV_SELECT_22 ((uint32_t)(1) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT) - /* Bits 2-5 Reserved */ -#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS (1 << 6) /* Bit 6: Enable PLL outputs for USBPHYn */ -#define CCM_ANALOG_PLL_USB1_POWER (1 << 12) /* Bit 12: Powers up the PLL */ -#define CCM_ANALOG_PLL_USB1_ENABLE (1 << 13) /* Bit 13: Enable the PLL clock output */ -#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ -#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) -# define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ -# define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ -# define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_GPANAIO ((uint32_t)(2) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) /* */ -# define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_CHRG_DET_B ((uint32_t)(3) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) /* */ -#define CCM_ANALOG_PLL_USB1_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ - /* Bits 17-30 Reserved */ -#define CCM_ANALOG_PLL_USB1_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ - -/* Analog USB2 480MHz PLL Control Register */ - -#define CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT (0) /* Bits 0-1: This field controls the PLL loop divider 20 or 22 */ -#define CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK (0x3 << CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_USB2_DIV_SELECT_20 ((uint32_t)(0) << CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_USB2_DIV_SELECT_22 ((uint32_t)(1) << CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT) - /* Bits 2-5 Reserved */ -#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS (1 << 6) /* Bit 6: Enable PLL outputs for USBPHYn */ -#define CCM_ANALOG_PLL_USB2_POWER (1 << 12) /* Bit 12: Powers up the PLL */ -#define CCM_ANALOG_PLL_USB2_ENABLE (1 << 13) /* Bit 13: Enable the PLL clock output */ -#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ -#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT) -# define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ -# define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ -#define CCM_ANALOG_PLL_USB2_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ - /* Bits 17-30 Reserved */ -#define CCM_ANALOG_PLL_USB2_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ - -/* Analog System PLL Control Register */ - -#define CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT (0) /* Bits 0-1: This field controls the PLL loop divider 20 or 22 */ -#define CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK (0x3 << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_SYS_DIV_SELECT(n) ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_SYS_DIV_SELECT_20 (0) -# define CCM_ANALOG_PLL_SYS_DIV_SELECT_22 (1) -#define CCM_ANALOG_PLL_SYS_POWERDOWN (1 << 12) /* Bit 12: Powers down the PLL */ -#define CCM_ANALOG_PLL_SYS_ENABLE (1 << 13) /* Bit 13: Enable the PLL clock output */ -#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ -#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) -# define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ -# define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ -# define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_GPANAIO ((uint32_t)(2) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) /* */ -# define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_CHRG_DET_B ((uint32_t)(3) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) /* */ -#define CCM_ANALOG_PLL_SYS_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ - /* Bit 17: Reserved */ -#define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN (1 << 18) /* Bit 18: Enables an offset in the phase frequency detector */ - /* Bits 19-30 Reserved */ -#define CCM_ANALOG_PLL_SYS_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ - -/* 528MHz System PLL Spread Spectrum Register */ - -#define CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT (0) /* Bits 0-14: Frequency change step */ -#define CCM_ANALOG_PLL_SYS_SS_STEP_MASK (0x3FFF << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT) -# define CCM_ANALOG_PLL_SYS_SS_STEP(n) ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT) -#define CCM_ANALOG_PLL_SYS_SS_ENABLE (1 << 15) /* Bit 15: Enable bit */ -#define CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT (0) /* Bits 16-31: Frequency change */ -#define CCM_ANALOG_PLL_SYS_SS_STOP_MASK (0xFFFF << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT) -# define CCM_ANALOG_PLL_SYS_SS_STOP(n) ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT) - -/* Numerator of 528MHz System PLL Fractional Loop Divider Register */ - -#define CCM_ANALOG_PLL_SYS_NUM_A_SHIFT (0) /* Bits 0-29: 30 bit numerator (A) */ -#define CCM_ANALOG_PLL_SYS_NUM_A_MASK (0x3FFFFFFF << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT) -#define CCM_ANALOG_PLL_SYS_NUM_A(n) ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT) - /* Bits 30-31: Reserved */ - -/* Denominator of 528MHz System PLL Fractional Loop Divider Register */ - -#define CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT (0) /* Bits 0-29: 30 bit numerator (A) */ -#define CCM_ANALOG_PLL_SYS_DENOM_B_MASK (0x3FFFFFFF << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT) -#define CCM_ANALOG_PLL_SYS_DENOM_B(n) ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT) - /* Bits 30-31: Reserved */ - -/* Analog Audio PLL control Register */ - -#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT (0) /* Bits 0-6: This field controls the PLL loop divider: 27-54 */ -#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK (0x7f << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(n) ((uint32_t)(n) << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT) - /* Bits 7-11: Reserved */ -#define CCM_ANALOG_PLL_AUDIO_POWERDOWN (1 << 12) /* Bit 12: Powers down the PLL */ -#define CCM_ANALOG_PLL_AUDIO_ENABLE (1 << 13) /* Bit 13: Enable PLL output */ -#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ -#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT) -# define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ -# define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ -#define CCM_ANALOG_PLL_AUDIO_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ - /* Bit 17: Reserved */ -#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN (1 << 18) /* Bit 18: Enables an offset in the phase frequency detector */ -#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT (19) /* Bits 19-20: These bits implement a divider after the PLL */ -#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK (0x7f << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_DIV4 ((uint32_t)(0) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_DIV2 ((uint32_t)(1) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_DIV1 ((uint32_t)(2) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT) - /* Bits 21-30: Reserved */ -#define CCM_ANALOG_PLL_AUDIO_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ - -/* Numerator of Audio PLL Fractional Loop Divider Register */ - -#define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT (0) /* Bits 0-29: 30 bit numerator (A) */ -#define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK (0x3FFFFFFF << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT) -#define CCM_ANALOG_PLL_AUDIO_NUM_A(n) ((uint32_t)(n) << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT) -/* Bits 30-31: Reserved */ - -/* Denominator of Audio PLL Fractional Loop Divider Register */ - -#define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT (0) /* Bits 0-29: 30 bit numerator (A) */ -#define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK (0x3FFFFFFF << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT) -#define CCM_ANALOG_PLL_AUDIO_DENOM_B(n) ((uint32_t)(n) << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT) - /* Bits 30-31: Reserved */ -/* Analog Video PLL control Register */ - -#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT (0) /* Bits 0-6: This field controls the PLL loop divider: 27-54 */ -#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK (0x7f << CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_VIDEO_DIV_SELECT(n) ((uint32_t)(n) << CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT) - /* Bits 7-11: Reserved */ -#define CCM_ANALOG_PLL_VIDEO_POWERDOWN (1 << 12) /* Bit 12: Powers down the PLL */ -#define CCM_ANALOG_PLL_VIDEO_ENABLE (1 << 13) /* Bit 13: Enable PLL output */ -#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ -#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT) -# define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ -# define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ -#define CCM_ANALOG_PLL_VIDEO_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ - /* Bit 17: Reserved */ -#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN (1 << 18) /* Bit 18: Enables an offset in the phase frequency detector */ -#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT (19) /* Bits 19-20: These bits implement a divider after the PLL */ -#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK (0x7f << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_DIV4 ((uint32_t)(0) << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_DIV2 ((uint32_t)(1) << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_DIV1 ((uint32_t)(2) << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT) - /* Bits 21-30: Reserved */ -#define CCM_ANALOG_PLL_VIDEO_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ - -/* Numerator of Video PLL Fractional Loop Divider Register */ - -#define CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT (0) /* Bits 0-29: 30 bit numerator (A) */ -#define CCM_ANALOG_PLL_VIDEO_NUM_A_MASK (0x3FFFFFFF << CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT) -#define CCM_ANALOG_PLL_VIDEO_NUM_A(n) ((uint32_t)(n) << CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT) - /* Bits 30-31: Reserved */ - -/* Denominator of Video PLL Fractional Loop Divider Register */ - -#define CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT (0) /* Bits 0-29: 30 bit numerator (A) */ -#define CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK (0x3FFFFFFF << CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT) -#define CCM_ANALOG_PLL_VIDEO_DENOM_B(n) ((uint32_t)(n) << CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT) - /* Bits 30-31: Reserved */ - -/* Analog ENET PLL Control Register */ - -#define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT (0) /* Bits 0-1: Controls the frequency of the ethernet0 reference clock */ -#define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_MASK (0x3 << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_25MHZ ((uint32_t)(0) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_50MHZ ((uint32_t)(1) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_100MHZ ((uint32_t)(2) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_125MHZ ((uint32_t)(3) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT) -#define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT (2) /* Bits 0-1: Controls the frequency of the ethernet1 reference clock */ -#define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_MASK (0x3 << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_25MHZ ((uint32_t)(0) << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_50MHZ ((uint32_t)(1) << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_100MHZ ((uint32_t)(2) << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_125MHZ ((uint32_t)(3) << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT) - /* Bits 4-11: Reserved */ -#define CCM_ANALOG_PLL_ENET_POWERDOWN (1 << 12) /* Bit 12: Powers down the PLL */ -#define CCM_ANALOG_PLL_ENET_ENET1_125M_EN (1 << 13) /* Bit 13: Enable the PLL providing the ENET1 125 MHz reference clock */ -#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ -#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT) -# define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ -# define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ -#define CCM_ANALOG_PLL_ENET_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ - /* Bit 17: Reserved */ -#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN (1 << 18) /* Bit 18: Enables an offset in the phase frequency detector */ -#define CCM_ANALOG_PLL_ENET_ENABLE_125M (1 << 19) /* Bit 19: */ -#define CCM_ANALOG_PLL_ENET_ENET2_125M_EN (1 << 20) /* Bit 20: Enable the PLL providing the ENET2 125 MHz reference clock */ -#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN (1 << 21) /* Bit 21: Enable the PLL providing ENET 25 MHz reference clock */ -#define CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN (1 << 22) /* Bit 22: Enable the PLL providing NET 500 MHz reference clock */ -#define CCM_ANALOG_PLL_ENET_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ - -/* 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ - -#define CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT (0) /* Bits 0-5: This field controls the fractional divide value */ -#define CCM_ANALOG_PFD_480_PFD0_FRAC_MASK (0x3f << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT) -# define CCM_ANALOG_PFD_480_PFD0_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT) -#define CCM_ANALOG_PFD_480_PFD0_STABLE (6) /* Bit 6: */ -#define CCM_ANALOG_PFD_480_PFD0_CLKGATE (7) /* Bit 7: If set to 1, the IO fractional divider clock is off */ -#define CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT (8) /* Bits 8-13: This field controls the fractional divide value */ -#define CCM_ANALOG_PFD_480_PFD1_FRAC_MASK (0x3f << CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT) -# define CCM_ANALOG_PFD_480_PFD1_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_481_PFD1_FRAC_SHIFT) -#define CCM_ANALOG_PFD_480_PFD1_STABLE (14) /* Bit 14: */ -#define CCM_ANALOG_PFD_480_PFD1_CLKGATE (15) /* Bit 15: If set to 1, the IO fractional divider clock is off */ -#define CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT (16) /* Bits 8-21: This field controls the fractional divide value */ -#define CCM_ANALOG_PFD_480_PFD2_FRAC_MASK (0x3f << CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT) -# define CCM_ANALOG_PFD_480_PFD2_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_482_PFD2_FRAC_SHIFT) -#define CCM_ANALOG_PFD_480_PFD2_STABLE (22) /* Bit 22: */ -#define CCM_ANALOG_PFD_480_PFD2_CLKGATE (23) /* Bit 23: If set to 1, the IO fractional divider clock is off */ -#define CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT (24) /* Bits 24-29: This field controls the fractional divide value */ -#define CCM_ANALOG_PFD_480_PFD3_FRAC_MASK (0x3f << CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT) -# define CCM_ANALOG_PFD_480_PFD3_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_482_PFD3_FRAC_SHIFT) -#define CCM_ANALOG_PFD_480_PFD3_STABLE (30) /* Bit 30: */ -#define CCM_ANALOG_PFD_480_PFD3_CLKGATE (31) /* Bit 31: If set to 1, the IO fractional divider clock is off */ - -/* 528MHz Clock (PLL2) Phase Fractional Divider Control */ - -#define CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT (0) /* Bits 0-5: This field controls the fractional divide value */ -#define CCM_ANALOG_PFD_528_PFD0_FRAC_MASK (0x3f << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT) -# define CCM_ANALOG_PFD_528_PFD0_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT) -#define CCM_ANALOG_PFD_528_PFD0_STABLE (6) /* Bit 6: */ -#define CCM_ANALOG_PFD_528_PFD0_CLKGATE (7) /* Bit 7: If set to 1, the IO fractional divider clock is off */ -#define CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT (8) /* Bits 8-13: This field controls the fractional divide value */ -#define CCM_ANALOG_PFD_528_PFD1_FRAC_MASK (0x3f << CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT) -# define CCM_ANALOG_PFD_528_PFD1_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_481_PFD1_FRAC_SHIFT) -#define CCM_ANALOG_PFD_528_PFD1_STABLE (14) /* Bit 14: */ -#define CCM_ANALOG_PFD_528_PFD1_CLKGATE (15) /* Bit 15: If set to 1, the IO fractional divider clock is off */ -#define CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT (16) /* Bits 8-21: This field controls the fractional divide value */ -#define CCM_ANALOG_PFD_528_PFD2_FRAC_MASK (0x3f << CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT) -# define CCM_ANALOG_PFD_528_PFD2_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_482_PFD2_FRAC_SHIFT) -#define CCM_ANALOG_PFD_528_PFD2_STABLE (22) /* Bit 22: */ -#define CCM_ANALOG_PFD_528_PFD2_CLKGATE (23) /* Bit 23: If set to 1, the IO fractional divider clock is off */ -#define CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT (24) /* Bits 24-29: This field controls the fractional divide value */ -#define CCM_ANALOG_PFD_528_PFD3_FRAC_MASK (0x3f << CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT) -# define CCM_ANALOG_PFD_528_PFD3_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_482_PFD3_FRAC_SHIFT) -#define CCM_ANALOG_PFD_528_PFD3_STABLE (30) /* Bit 30: */ -#define CCM_ANALOG_PFD_528_PFD3_CLKGATE (31) /* Bit 31: If set to 1, the IO fractional divider clock is off */ - -/* Miscellaneous Register 0 */ - -#define CCM_ANALOG_MISC0_REFTOP_PWD (1 << 0) /* Bit 0: Control bit to power-down the analog bandgap reference circuitry */ - /* Bits 1-2: Reserved */ -#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF (1 << 2) /* Bit 3: Control bit to disable the self-bias circuit in the analog bandgap */ -#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT (4) /* Bits 4-6: VBG (PMU) */ -#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK (0x3 << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT) -# define CCM_ANALOG_MISC0_REFTOP_VBGADJ(n) ((uint32_t)(n) << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT) -#define CCM_ANALOG_MISC0_REFTOP_VBGUP (1 << 7) /* Bit 7: Status bit that signals the analog bandgap voltage is up and stable */ - /* Bits 8-9: Reserved */ -#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT (10) /* Bits 10-11: Configure the analog behavior in stop mode */ -#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK (0x3 << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT) -# define CCM_ANALOG_MISC0_STOP_MODE_CONFIG(n) ((uint32_t)(n) << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT) -#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS (1 << 12) /* Bit 12: This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN */ -#define CCM_ANALOG_MISC0_OSC_I_SHIFT (13) /* Bits 13-14: This field determines the bias current in the 24MHz oscillator */ -#define CCM_ANALOG_MISC0_OSC_I_MASK (0x3 << CCM_ANALOG_MISC0_OSC_I_SHIFT) -# define CCM_ANALOG_MISC0_OSC_I(n) ((uint32_t)(n) << CCM_ANALOG_MISC0_OSC_I_SHIFT) -#define CCM_ANALOG_MISC0_OSC_XTALOK (1 << 15) /* Bit 15: bit that signals 24-MHz crystal oscillator is stable */ -#define CCM_ANALOG_MISC0_OSC_XTALOK_EN (1 << 16) /* Bit 16: enables the detector that signals 24MHz crystal oscillator is stable */ - /* Bits 17-24: Reserved */ -#define CCM_ANALOG_MISC0_CLKGATE_CTRL (1 << 25) /* Bit 25: This bit allows disabling the clock gate */ -#define CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT (26) /* Bits 26-28: delay powering up the XTAL 24MHz */ -#define CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK (0x7 << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT) -# define CCM_ANALOG_MISC0_CLKGATE_DELAY(n) ((uint32_t)(n) << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT) -#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE (1 << 29) /* Bit 29: which chip source is being used for the rtc clock */ -#define CCM_ANALOG_MISC0_XTAL_24M_PWD (1 << 30) /* Bit 30: power down the 24M crystal oscillator if set true */ -#define CCM_ANALOG_MISC0_VID_PLL_PREDIV (1 << 31) /* Bit 31: Predivider for the source clock of the PLL's */ -#define CCM_ANALOG_MISC0_VID_PLL_PREDIV_1 (0 << 31) /* Bit 31: Predivider for the source clock of the PLL's */ -#define CCM_ANALOG_MISC0_VID_PLL_PREDIV_2 (1 << 31) /* Bit 31: Predivider for the source clock of the PLL's */ - -/* Miscellaneous Register 1 */ - -#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT (0) /* Bits 0-4: This field selects the clk to be routed to anaclk1/1b */ -#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK (0x1f << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) -# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_ARM_PLL ((uint32_t)(0) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) -# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SYS_PLL ((uint32_t)(1) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) -# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD4 ((uint32_t)(2) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) -# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD5 ((uint32_t)(3) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) -# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD6 ((uint32_t)(4) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) -# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD7 ((uint32_t)(5) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) -# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_AUDIO_PLL ((uint32_t)(6) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) -# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_VIDEO_PLL ((uint32_t)(7) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) -# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_ETHERNET_REF ((uint32_t)(9) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) -# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_USB1_PLL ((uint32_t)(12) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) -# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_USB2_PLL ((uint32_t)(13) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) -# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD0 ((uint32_t)(14) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) -# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD1 ((uint32_t)(15) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) -# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD2 ((uint32_t)(16) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) -# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD3 ((uint32_t)(17) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) -# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_XTAL ((uint32_t)(18) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) - /* Bits 5-9: Reserved */ -#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN (1 << 10) /* Bit 10: This enables the LVDS output buffer for anaclk1/1b */ - /* Bit 11: Reserved */ -#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN (1 << 12) /* Bit 12: This enables the LVDS input buffer for anaclk1/1b */ - /* Bits 13-15: Reserved */ -#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN (1 << 16) /* Bit 16: */ -#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN (1 << 17) /* Bit 17: */ - /* Bits 18-26: Reserved */ -#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC (1 << 27) /* Bit 27: temperature sensor panic interrupt */ -#define CCM_ANALOG_MISC1_IRQ_TEMPLOW (1 << 28) /* Bit 28: temperature sensor low interrupt */ -#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH (1 << 29) /* Bit 29: temperature sensor high interrupt */ -#define CCM_ANALOG_MISC1_IRQ_ANA_BO (1 << 30) /* Bit 30: analog regulator brownout interrupt */ -#define CCM_ANALOG_MISC1_IRQ_DIG_BO (1 << 31) /* Bit 31: digital regulator brownout interrupt */ - -/* Miscellaneous Register 2 */ - -#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT (0) /* Bits 0-2: This field defines the brown out voltage offset */ -#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK (0x7 << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT) -# define CCM_ANALOG_MISC2_REG0_BO_OFFSET_0_100 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT) -# define CCM_ANALOG_MISC2_REG0_BO_OFFSET_0_175 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT) -#define CCM_ANALOG_MISC2_REG0_BO_STATUS (1 << 3) /* Bit 3: Reg0 brownout status bit */ - /* Bit 4: Reserved */ -#define CCM_ANALOG_MISC2_REG0_ENABLE_BO (1 << 5) /* Bit 5: Enables the brownout detection */ -#define CCM_ANALOG_MISC2_REG0_OK (1 << 6) /* Bit 6: ARM supply */ -#define CCM_ANALOG_MISC2_PLL3_DISABLE (1 << 7) /* Bit 7: PLL3 can be disabled when the SoC is not in any low power mode */ -#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT (8) /* Bits 8-10: This field defines the brown out voltage offset */ -#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK (0x7 << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT) -# define CCM_ANALOG_MISC2_REG1_BO_OFFSET_0_100 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT) -# define CCM_ANALOG_MISC2_REG1_BO_OFFSET_0_175 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT) -#define CCM_ANALOG_MISC2_REG1_BO_STATUS (1 << 11) /* Bit 11: Reg1 brownout status bit */ - /* Bit 12: Reserved */ -#define CCM_ANALOG_MISC2_REG1_ENABLE_BO (1 << 13) /* Bit 13: Enables the brownout detection */ -#define CCM_ANALOG_MISC2_REG1_OK (1 << 14) /* Bit 14: GPU/VPU supply */ -#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB (1 << 15) /* Bit 15: LSB of Post-divider for Audio PLL */ - -#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT (16) /* Bits 16-18: This field defines the brown out voltage offset */ -#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK (0x7 << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT) -# define CCM_ANALOG_MISC2_REG2_BO_OFFSET_0_100 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT) -# define CCM_ANALOG_MISC2_REG2_BO_OFFSET_0_175 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT) -#define CCM_ANALOG_MISC2_REG2_BO_STATUS (1 << 19) /* Bit 19: Reg2 brownout status bit */ - /* Bit 20: Reserved */ -#define CCM_ANALOG_MISC2_REG2_ENABLE_BO (1 << 21) /* Bit 21: Enables the brownout detection */ -#define CCM_ANALOG_MISC2_REG2_OK (1 << 22) /* Bit 22: voltage is above the brownout level for the SOC supply */ -#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB (1 << 23) /* Bit 23: MSB of Post-divider for Audio PLL */ -#define CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT (24) /* Bits 24-25: Number of clock periods (24MHz clock) */ -#define CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK (0x3 << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC2_REG0_STEP_TIME_64 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC2_REG0_STEP_TIME_128 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC2_REG0_STEP_TIME_256 ((uint32_t)(2) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC2_REG0_STEP_TIME_512 ((uint32_t)(3) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT) -#define CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT (26) /* Bits 26-27: Number of clock periods (24MHz clock) */ -#define CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK (0x3 << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC2_REG1_STEP_TIME_64 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC2_REG1_STEP_TIME_128 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC2_REG1_STEP_TIME_256 ((uint32_t)(2) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC2_REG1_STEP_TIME_512 ((uint32_t)(3) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT) -#define CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT (28) /* Bits 28-29: Number of clock periods (24MHz clock) */ -#define CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK (0x3 << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC2_REG2_STEP_TIME_64 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC2_REG2_STEP_TIME_128 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC2_REG2_STEP_TIME_256 ((uint32_t)(2) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC2_REG2_STEP_TIME_512 ((uint32_t)(3) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT) - -#define CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT (30) /* Bits 30-31: Post-divider for video */ -#define CCM_ANALOG_MISC2_VIDEO_DIV_MASK (0x3 << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT) -# define CCM_ANALOG_MISC2_VIDEO_DIV(n) ((uint32_t)(n) << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT) - -#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_CCM_H */ diff --git a/arch/arm/src/imxrt/chip/rt106x/imxrt106x_dmamux.h b/arch/arm/src/imxrt/chip/rt106x/imxrt106x_dmamux.h deleted file mode 100644 index 3e05c859fcb..00000000000 --- a/arch/arm/src/imxrt/chip/rt106x/imxrt106x_dmamux.h +++ /dev/null @@ -1,174 +0,0 @@ -/************************************************************************************ - * arch/arm/src/imxrt/chip/rt106x/imxrt106x_dmamux.h - * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * David Sidrane - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_DMAMUX_H -#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_DMAMUX_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -/************************************************************************************ - * Preprocessor Definitions - ************************************************************************************/ - -/* Peripheral DMA request channels */ - -#define IMXRT_DMACHAN_FLEXIO1 0 /* FlexIO1 DMA 0/1, Async DMA 0/1 */ -#define IMXRT_DMACHAN_FLEXIO2 1 /* FlexIO1 DMA 0/1, Async DMA 0/1 */ -#define IMXRT_DMACHAN_LPUART1_TX 2 /* LPUART1 TX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPUART1_RX 3 /* LPUART1 RX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPUART3_TX 4 /* LPUART3 RX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPUART3_RX 5 /* LPUART3 RX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPUART5_TX 6 /* LPUART5 TX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPUART5_RX 7 /* LPUART5 RX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPUART7_TX 8 /* LPUART7 TX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPUART7_RX 9 /* LPUART7 RX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_CAN3 11 /* FLEXCAN3 DMA */ -#define IMXRT_DMACHAN_CSI 12 /* CSI Write DMA */ -#define IMXRT_DMACHAN_LPSPI1_RX 13 /* LPSPI1 RX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPSPI1_TX 14 /* LPSPI1 TX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPSPI3_RX 15 /* LPSPI3 RX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPSPI3_TX 16 /* LPSPI3 TX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPI2C1 17 /* LPI2C1 Master/Slave RX/TX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPI2C3 18 /* LPI2C3 Master/Slave RX/TX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_SAI1_RX 19 /* SAI1 RX FIFO DMA */ -#define IMXRT_DMACHAN_SAI1_TX 20 /* SAI1 TX FIFO DMA */ -#define IMXRT_DMACHAN_SAI2_RX 21 /* SAI2 RX FIFO DMA */ -#define IMXRT_DMACHAN_SAI2_TX 22 /* SAI2 TX FIFO DMA */ -#define IMXRT_DMACHAN_ADC_ETC 23 /* ADC ETC DMA */ -#define IMXRT_DMACHAN_ADC1 24 /* ADC1 DMA */ -#define IMXRT_DMACHAN_ACMP1 25 /* ACMP1 DMA */ -#define IMXRT_DMACHAN_ACMP3 26 /* ACMP3 DMA */ -#define IMXRT_DMACHAN_FLEXSPI_RX 28 /* FlexSPI RX FIFO DMA */ -#define IMXRT_DMACHAN_FLEXSPI_TX 29 /* FlexSPI TX FIFO DMA */ -#define IMXRT_DMACHAN_XBAR1_0 30 /* XBAR1 DMA 0 */ -#define IMXRT_DMACHAN_XBAR1_1 31 /* XBAR1 DMA 1 */ -#define IMXRT_DMACHAN_FLEXPWM1_RX0 32 /* FlexPWM1 RX sub-module0 capture */ -#define IMXRT_DMACHAN_FLEXPWM1_RX1 33 /* FlexPWM1 RX sub-module1 capture */ -#define IMXRT_DMACHAN_FLEXPWM1_RX2 34 /* FlexPWM1 RX sub-module2 capture */ -#define IMXRT_DMACHAN_FLEXPWM1_RX3 35 /* FlexPWM1 RX sub-module3 capture */ -#define IMXRT_DMACHAN_FLEXPWM1_TX0 36 /* FlexPWM1 TX sub-module0 value */ -#define IMXRT_DMACHAN_FLEXPWM1_TX1 37 /* FlexPWM1 TX sub-module1 value */ -#define IMXRT_DMACHAN_FLEXPWM1_TX2 38 /* FlexPWM1 TX sub-module2 value */ -#define IMXRT_DMACHAN_FLEXPWM1_TX3 39 /* FlexPWM1 TX sub-module3 value */ -#define IMXRT_DMACHAN_FLEXPWM3_RX0 40 /* FlexPWM3 RX sub-module0 capture */ -#define IMXRT_DMACHAN_FLEXPWM3_RX1 41 /* FlexPWM3 RX sub-module1 capture */ -#define IMXRT_DMACHAN_FLEXPWM3_RX2 42 /* FlexPWM3 RX sub-module2 capture */ -#define IMXRT_DMACHAN_FLEXPWM3_RX3 43 /* FlexPWM3 RX sub-module3 capture */ -#define IMXRT_DMACHAN_FLEXPWM3_TX0 44 /* FlexPWM3 TX sub-module0 value */ -#define IMXRT_DMACHAN_FLEXPWM3_TX1 45 /* FlexPWM3 TX sub-module1 value */ -#define IMXRT_DMACHAN_FLEXPWM3_TX2 46 /* FlexPWM3 TX sub-module2 value */ -#define IMXRT_DMACHAN_FLEXPWM3_TX3 47 /* FlexPWM3 TX sub-module3 value */ -#define IMXRT_DMACHAN_QTIMER1_RX0 48 /* QTimer1 RX capture timer 0 */ -#define IMXRT_DMACHAN_QTIMER1_RX1 49 /* QTimer1 RX capture timer 1 */ -#define IMXRT_DMACHAN_QTIMER1_RX2 50 /* QTimer1 RX capture timer 2 */ -#define IMXRT_DMACHAN_QTIMER1_RX3 51 /* QTimer1 RX capture timer 3 */ -#define IMXRT_DMACHAN_QTIMER1_TX0 52 /* QTimer1 TX cmpld1 timer 0 / cmld2 timer 1 */ -#define IMXRT_DMACHAN_QTIMER1_TX1 53 /* QTimer1 TX cmpld1 timer 1 / cmld2 timer 0 */ -#define IMXRT_DMACHAN_QTIMER1_TX2 54 /* QTimer1 TX cmpld1 timer 2 / cmld2 timer 3 */ -#define IMXRT_DMACHAN_QTIMER1_TX3 55 /* QTimer1 TX cmpld1 timer 3 / cmld2 timer 2 */ -#define IMXRT_DMACHAN_QTIMER3_RXTX0 56 /* QTimer1 RX capture timer 0 / TX cmpld1 timer 0 / cmld2 timer 1 */ -#define IMXRT_DMACHAN_QTIMER3_RXTX1 57 /* QTimer1 RX capture timer 1 / TX cmpld1 timer 1 / cmld2 timer 0 */ -#define IMXRT_DMACHAN_QTIMER3_RXTX2 58 /* QTimer1 RX capture timer 2 / TX cmpld1 timer 2 / cmld2 timer 3 */ -#define IMXRT_DMACHAN_QTIMER3_RXTX3 59 /* QTimer1 RX capture timer 3 / TX cmpld1 timer 3 / cmld2 timer 2 */ -#define IMXRT_DMACHAN_FLEXSPI2_RX 60 /* FlexSPI2 RX FIFO DMA */ -#define IMXRT_DMACHAN_FLEXSPI2_TX 61 /* FlexSPI2 TX FIFO DMA */ -#define IMXRT_DMACHAN_FLEXIO1_01 64 /* FlexIO1 DMA 0 / Async DMA 0 / DMA 1 / Async DMA 1 */ -#define IMXRT_DMACHAN_FLEXIO2_23 65 /* FlexIO1 DMA 2 / Async DMA 2 / DMA 3 / Async DMA 3 */ -#define IMXRT_DMACHAN_LPUART2_TX 66 /* LPUART2 TX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPUART2_RX 67 /* LPUART2 RX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPUART4_TX 68 /* LPUART4 TX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPUART4_RX 69 /* LPUART4 RX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPUART6_TX 70 /* LPUART6 TX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPUART6_RX 71 /* LPUART6 RX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPUART8_TX 72 /* LPUART8 TX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPUART8_RX 73 /* LPUART8 RX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_PXP 75 /* PXP DMA Event */ -#define IMXRT_DMACHAN_LCDIF 76 /* LCDIF DMA Event */ -#define IMXRT_DMACHAN_LPSPI2_RX 77 /* LPSPI2 RX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPSPI2_TX 78 /* LPSPI2 TX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPSPI4_RX 79 /* LPSPI4 RX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPSPI4_TX 80 /* LPSPI4 TX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPI2C2 81 /* LPI2C2 Master/Slave RX/TX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_LPI2C4 82 /* LPI2C4 Master/Slave RX/TX FIFO DMA / Async DMA */ -#define IMXRT_DMACHAN_SAI3_RX 83 /* SAI3 RX FIFO DMA */ -#define IMXRT_DMACHAN_SAI3_TX 84 /* SAI3 RX FIFO DMA */ -#define IMXRT_DMACHAN_SPDIF_RX 85 /* SPDIF RX DMA */ -#define IMXRT_DMACHAN_SPDIF_TX 86 /* SPDIF TX DMA */ -#define IMXRT_DMACHAN_ADC2 88 /* ADC2 DMA */ -#define IMXRT_DMACHAN_ACMP2 89 /* ACMP2 DMA */ -#define IMXRT_DMACHAN_ACMP4 90 /* ACMP4 DMA */ -#define IMXRT_DMACHAN_ENET_0 92 /* ENET Timer DMA 0 */ -#define IMXRT_DMACHAN_ENET_1 93 /* ENET Timer DMA 1 */ -#define IMXRT_DMACHAN_XBAR1_2 94 /* XBAR1 DMA 2 */ -#define IMXRT_DMACHAN_XBAR1_3 95 /* XBAR1 DMA 3 */ -#define IMXRT_DMACHAN_FLEXPWM2_RX0 96 /* FlexPWM2 RX sub-module0 capture */ -#define IMXRT_DMACHAN_FLEXPWM2_RX1 97 /* FlexPWM2 RX sub-module1 capture */ -#define IMXRT_DMACHAN_FLEXPWM2_RX2 98 /* FlexPWM2 RX sub-module2 capture */ -#define IMXRT_DMACHAN_FLEXPWM2_RX3 99 /* FlexPWM2 RX sub-module3 capture */ -#define IMXRT_DMACHAN_FLEXPWM2_TX0 100 /* FlexPWM2 TX sub-module0 value */ -#define IMXRT_DMACHAN_FLEXPWM2_TX1 101 /* FlexPWM2 TX sub-module1 value */ -#define IMXRT_DMACHAN_FLEXPWM2_TX2 102 /* FlexPWM2 TX sub-module2 value */ -#define IMXRT_DMACHAN_FLEXPWM2_TX3 103 /* FlexPWM2 TX sub-module3 value */ -#define IMXRT_DMACHAN_FLEXPWM4_RX0 104 /* FlexPWM4 RX sub-module0 capture */ -#define IMXRT_DMACHAN_FLEXPWM4_RX1 105 /* FlexPWM4 RX sub-module1 capture */ -#define IMXRT_DMACHAN_FLEXPWM4_RX2 106 /* FlexPWM4 RX sub-module2 capture */ -#define IMXRT_DMACHAN_FLEXPWM4_RX3 107 /* FlexPWM4 RX sub-module3 capture */ -#define IMXRT_DMACHAN_FLEXPWM4_TX0 108 /* FlexPWM4 TX sub-module0 value */ -#define IMXRT_DMACHAN_FLEXPWM4_TX1 109 /* FlexPWM4 TX sub-module1 value */ -#define IMXRT_DMACHAN_FLEXPWM4_TX2 110 /* FlexPWM4 TX sub-module2 value */ -#define IMXRT_DMACHAN_FLEXPWM4_TX3 111 /* FlexPWM4 TX sub-module3 value */ -#define IMXRT_DMACHAN_QTIMER2_RX0 112 /* QTimer2 RX capture timer 0 */ -#define IMXRT_DMACHAN_QTIMER2_RX1 113 /* QTimer2 RX capture timer 1 */ -#define IMXRT_DMACHAN_QTIMER2_RX2 114 /* QTimer2 RX capture timer 2 */ -#define IMXRT_DMACHAN_QTIMER2_RX3 115 /* QTimer2 RX capture timer 3 */ -#define IMXRT_DMACHAN_QTIMER2_TX0 116 /* QTimer2 TX cmpld1 timer 0 / cmld2 timer 1 */ -#define IMXRT_DMACHAN_QTIMER2_TX1 117 /* QTimer2 TX cmpld1 timer 1 / cmld2 timer 0 */ -#define IMXRT_DMACHAN_QTIMER2_TX2 118 /* QTimer2 TX cmpld1 timer 2 / cmld2 timer 3 */ -#define IMXRT_DMACHAN_QTIMER2_TX3 119 /* QTimer2 TX cmpld1 timer 3 / cmld2 timer 2 */ -#define IMXRT_DMACHAN_QTIMER4_RXTX0 120 /* QTimer4 RX capture timer 0 / TX cmpld1 timer 0 / cmld2 timer 1 */ -#define IMXRT_DMACHAN_QTIMER4_RXTX1 121 /* QTimer4 RX capture timer 1 / TX cmpld1 timer 1 / cmld2 timer 0 */ -#define IMXRT_DMACHAN_QTIMER4_RXTX2 122 /* QTimer4 RX capture timer 2 / TX cmpld1 timer 2 / cmld2 timer 3 */ -#define IMXRT_DMACHAN_QTIMER4_RXTX3 123 /* QTimer4 RX capture timer 3 / TX cmpld1 timer 3 / cmld2 timer 2 */ -#define IMXRT_DMACHAN_ENET2_0 124 /* ENET2 Timer DMA 0 */ -#define IMXRT_DMACHAN_ENET2_1 125 /* ENET2 Timer DMA 1 */ - -#define IMXRT_DMA_NCHANNLES 128 /* Includes reserved channels */ - -#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_DMAMUX_H */ diff --git a/arch/arm/src/imxrt/chip/rt106x/imxrt106x_gpio.h b/arch/arm/src/imxrt/chip/rt106x/imxrt106x_gpio.h deleted file mode 100644 index 6e732d5ac24..00000000000 --- a/arch/arm/src/imxrt/chip/rt106x/imxrt106x_gpio.h +++ /dev/null @@ -1,175 +0,0 @@ -/******************************************************************************************** - * arch/arm/src/imxrt/rt106x/imxrt106x_gpio.h - * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * David Sidrane - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ********************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_GPIO_H -#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_GPIO_H - -/******************************************************************************************** - * Included Files - ********************************************************************************************/ - -#include -#include "chip/imxrt_memorymap.h" - -/******************************************************************************************** - * Pre-processor Definitions - ********************************************************************************************/ - -/* Register offsets *************************************************************************/ - -#define IMXRT_GPIO_DR_OFFSET 0x0000 /* GPIO data register */ -#define IMXRT_GPIO_GDIR_OFFSET 0x0004 /* GPIO direction register */ -#define IMXRT_GPIO_PSR_OFFSET 0x0008 /* GPIO pad status register */ -#define IMXRT_GPIO_ICR1_OFFSET 0x000c /* GPIO interrupt configuration register1 */ -#define IMXRT_GPIO_ICR2_OFFSET 0x0010 /* GPIO interrupt configuration register2 */ -#define IMXRT_GPIO_IMR_OFFSET 0x0014 /* GPIO interrupt mask register */ -#define IMXRT_GPIO_ISR_OFFSET 0x0018 /* GPIO interrupt status register */ -#define IMXRT_GPIO_EDGE_OFFSET 0x001c /* GPIO edge select register */ -#define IMXRT_GPIO_SET_OFFSET 0x0084 /* GPIO data register SET */ -#define IMXRT_GPIO_CLEAR_OFFSET 0x0088 /* GPIO data register CLEAR */ -#define IMXRT_GPIO_TOGGLE_OFFSET 0x008c /* GPIO data register TOGGLE */ - -/* Register addresses ***********************************************************************/ - -#define IMXRT_GPIO1_DR (IMXRT_GPIO1_BASE + IMXRT_GPIO_DR_OFFSET) -#define IMXRT_GPIO1_GDIR (IMXRT_GPIO1_BASE + IMXRT_GPIO_GDIR_OFFSET) -#define IMXRT_GPIO1_PSR (IMXRT_GPIO1_BASE + IMXRT_GPIO_PSR_OFFSET) -#define IMXRT_GPIO1_ICR1 (IMXRT_GPIO1_BASE + IMXRT_GPIO_ICR1_OFFSET) -#define IMXRT_GPIO1_ICR2 (IMXRT_GPIO1_BASE + IMXRT_GPIO_ICR2_OFFSET) -#define IMXRT_GPIO1_IMR (IMXRT_GPIO1_BASE + IMXRT_GPIO_IMR_OFFSET) -#define IMXRT_GPIO1_ISR (IMXRT_GPIO1_BASE + IMXRT_GPIO_ISR_OFFSET) -#define IMXRT_GPIO1_EDGE (IMXRT_GPIO1_BASE + IMXRT_GPIO_EDGE_OFFSET) -#define IMXRT_GPIO1_SET (IMXRT_GPIO1_BASE + IMXRT_GPIO_SET_OFFSET) -#define IMXRT_GPIO1_CLEAR (IMXRT_GPIO1_BASE + IMXRT_GPIO_CLEAR_OFFSET) -#define IMXRT_GPIO1_TOGGLE (IMXRT_GPIO1_BASE + IMXRT_GPIO_TOGGLE_OFFSET) - -#define IMXRT_GPIO2_DR (IMXRT_GPIO2_BASE + IMXRT_GPIO_DR_OFFSET) -#define IMXRT_GPIO2_GDIR (IMXRT_GPIO2_BASE + IMXRT_GPIO_GDIR_OFFSET) -#define IMXRT_GPIO2_PSR (IMXRT_GPIO2_BASE + IMXRT_GPIO_PSR_OFFSET) -#define IMXRT_GPIO2_ICR1 (IMXRT_GPIO2_BASE + IMXRT_GPIO_ICR1_OFFSET) -#define IMXRT_GPIO2_ICR2 (IMXRT_GPIO2_BASE + IMXRT_GPIO_ICR2_OFFSET) -#define IMXRT_GPIO2_IMR (IMXRT_GPIO2_BASE + IMXRT_GPIO_IMR_OFFSET) -#define IMXRT_GPIO2_ISR (IMXRT_GPIO2_BASE + IMXRT_GPIO_ISR_OFFSET) -#define IMXRT_GPIO2_EDGE (IMXRT_GPIO2_BASE + IMXRT_GPIO_EDGE_OFFSET) -#define IMXRT_GPIO2_SET (IMXRT_GPIO2_BASE + IMXRT_GPIO_SET_OFFSET) -#define IMXRT_GPIO2_CLEAR (IMXRT_GPIO2_BASE + IMXRT_GPIO_CLEAR_OFFSET) -#define IMXRT_GPIO2_TOGGLE (IMXRT_GPIO2_BASE + IMXRT_GPIO_TOGGLE_OFFSET) - -#define IMXRT_GPIO3_DR (IMXRT_GPIO3_BASE + IMXRT_GPIO_DR_OFFSET) -#define IMXRT_GPIO3_GDIR (IMXRT_GPIO3_BASE + IMXRT_GPIO_GDIR_OFFSET) -#define IMXRT_GPIO3_PSR (IMXRT_GPIO3_BASE + IMXRT_GPIO_PSR_OFFSET) -#define IMXRT_GPIO3_ICR1 (IMXRT_GPIO3_BASE + IMXRT_GPIO_ICR1_OFFSET) -#define IMXRT_GPIO3_ICR2 (IMXRT_GPIO3_BASE + IMXRT_GPIO_ICR2_OFFSET) -#define IMXRT_GPIO3_IMR (IMXRT_GPIO3_BASE + IMXRT_GPIO_IMR_OFFSET) -#define IMXRT_GPIO3_ISR (IMXRT_GPIO3_BASE + IMXRT_GPIO_ISR_OFFSET) -#define IMXRT_GPIO3_EDGE (IMXRT_GPIO3_BASE + IMXRT_GPIO_EDGE_OFFSET) -#define IMXRT_GPIO3_SET (IMXRT_GPIO3_BASE + IMXRT_GPIO_SET_OFFSET) -#define IMXRT_GPIO3_CLEAR (IMXRT_GPIO3_BASE + IMXRT_GPIO_CLEAR_OFFSET) -#define IMXRT_GPIO3_TOGGLE (IMXRT_GPIO3_BASE + IMXRT_GPIO_TOGGLE_OFFSET) - -#define IMXRT_GPIO4_DR (IMXRT_GPIO4_BASE + IMXRT_GPIO_DR_OFFSET) -#define IMXRT_GPIO4_GDIR (IMXRT_GPIO4_BASE + IMXRT_GPIO_GDIR_OFFSET) -#define IMXRT_GPIO4_PSR (IMXRT_GPIO4_BASE + IMXRT_GPIO_PSR_OFFSET) -#define IMXRT_GPIO4_ICR1 (IMXRT_GPIO4_BASE + IMXRT_GPIO_ICR1_OFFSET) -#define IMXRT_GPIO4_ICR2 (IMXRT_GPIO4_BASE + IMXRT_GPIO_ICR2_OFFSET) -#define IMXRT_GPIO4_IMR (IMXRT_GPIO4_BASE + IMXRT_GPIO_IMR_OFFSET) -#define IMXRT_GPIO4_ISR (IMXRT_GPIO4_BASE + IMXRT_GPIO_ISR_OFFSET) -#define IMXRT_GPIO4_EDGE (IMXRT_GPIO4_BASE + IMXRT_GPIO_EDGE_OFFSET) -#define IMXRT_GPIO4_SET (IMXRT_GPIO4_BASE + IMXRT_GPIO_SET_OFFSET) -#define IMXRT_GPIO4_CLEAR (IMXRT_GPIO4_BASE + IMXRT_GPIO_CLEAR_OFFSET) -#define IMXRT_GPIO4_TOGGLE (IMXRT_GPIO4_BASE + IMXRT_GPIO_TOGGLE_OFFSET) - -#define IMXRT_GPIO5_DR (IMXRT_GPIO5_BASE + IMXRT_GPIO_DR_OFFSET) -#define IMXRT_GPIO5_GDIR (IMXRT_GPIO5_BASE + IMXRT_GPIO_GDIR_OFFSET) -#define IMXRT_GPIO5_PSR (IMXRT_GPIO5_BASE + IMXRT_GPIO_PSR_OFFSET) -#define IMXRT_GPIO5_ICR1 (IMXRT_GPIO5_BASE + IMXRT_GPIO_ICR1_OFFSET) -#define IMXRT_GPIO5_ICR2 (IMXRT_GPIO5_BASE + IMXRT_GPIO_ICR2_OFFSET) -#define IMXRT_GPIO5_IMR (IMXRT_GPIO5_BASE + IMXRT_GPIO_IMR_OFFSET) -#define IMXRT_GPIO5_ISR (IMXRT_GPIO5_BASE + IMXRT_GPIO_ISR_OFFSET) -#define IMXRT_GPIO5_EDGE (IMXRT_GPIO5_BASE + IMXRT_GPIO_EDGE_OFFSET) -#define IMXRT_GPIO5_SET (IMXRT_GPIO5_BASE + IMXRT_GPIO_SET_OFFSET) -#define IMXRT_GPIO5_CLEAR (IMXRT_GPIO5_BASE + IMXRT_GPIO_CLEAR_OFFSET) -#define IMXRT_GPIO5_TOGGLE (IMXRT_GPIO5_BASE + IMXRT_GPIO_TOGGLE_OFFSET) - -# define IMXRT_GPIO6_DR (IMXRT_GPIO6_BASE + IMXRT_GPIO_DR_OFFSET) -# define IMXRT_GPIO6_GDIR (IMXRT_GPIO6_BASE + IMXRT_GPIO_GDIR_OFFSET) -# define IMXRT_GPIO6_PSR (IMXRT_GPIO6_BASE + IMXRT_GPIO_PSR_OFFSET) -# define IMXRT_GPIO6_ICR1 (IMXRT_GPIO6_BASE + IMXRT_GPIO_ICR1_OFFSET) -# define IMXRT_GPIO6_ICR2 (IMXRT_GPIO6_BASE + IMXRT_GPIO_ICR2_OFFSET) -# define IMXRT_GPIO6_IMR (IMXRT_GPIO6_BASE + IMXRT_GPIO_IMR_OFFSET) -# define IMXRT_GPIO6_ISR (IMXRT_GPIO6_BASE + IMXRT_GPIO_ISR_OFFSET) -# define IMXRT_GPIO6_EDGE (IMXRT_GPIO6_BASE + IMXRT_GPIO_EDGE_OFFSET) -# define IMXRT_GPIO6_SET (IMXRT_GPIO6_BASE + IMXRT_GPIO_SET_OFFSET) -# define IMXRT_GPIO6_CLEAR (IMXRT_GPIO6_BASE + IMXRT_GPIO_CLEAR_OFFSET) -# define IMXRT_GPIO6_TOGGLE (IMXRT_GPIO6_BASE + IMXRT_GPIO_TOGGLE_OFFSET) - -# define IMXRT_GPIO7_DR (IMXRT_GPIO7_BASE + IMXRT_GPIO_DR_OFFSET) -# define IMXRT_GPIO7_GDIR (IMXRT_GPIO7_BASE + IMXRT_GPIO_GDIR_OFFSET) -# define IMXRT_GPIO7_PSR (IMXRT_GPIO7_BASE + IMXRT_GPIO_PSR_OFFSET) -# define IMXRT_GPIO7_ICR1 (IMXRT_GPIO7_BASE + IMXRT_GPIO_ICR1_OFFSET) -# define IMXRT_GPIO7_ICR2 (IMXRT_GPIO7_BASE + IMXRT_GPIO_ICR2_OFFSET) -# define IMXRT_GPIO7_IMR (IMXRT_GPIO7_BASE + IMXRT_GPIO_IMR_OFFSET) -# define IMXRT_GPIO7_ISR (IMXRT_GPIO7_BASE + IMXRT_GPIO_ISR_OFFSET) -# define IMXRT_GPIO7_EDGE (IMXRT_GPIO7_BASE + IMXRT_GPIO_EDGE_OFFSET) -# define IMXRT_GPIO7_SET (IMXRT_GPIO7_BASE + IMXRT_GPIO_SET_OFFSET) -# define IMXRT_GPIO7_CLEAR (IMXRT_GPIO7_BASE + IMXRT_GPIO_CLEAR_OFFSET) -# define IMXRT_GPIO7_TOGGLE (IMXRT_GPIO7_BASE + IMXRT_GPIO_TOGGLE_OFFSET) - -# define IMXRT_GPIO8_DR (IMXRT_GPIO8_BASE + IMXRT_GPIO_DR_OFFSET) -# define IMXRT_GPIO8_GDIR (IMXRT_GPIO8_BASE + IMXRT_GPIO_GDIR_OFFSET) -# define IMXRT_GPIO8_PSR (IMXRT_GPIO8_BASE + IMXRT_GPIO_PSR_OFFSET) -# define IMXRT_GPIO8_ICR1 (IMXRT_GPIO8_BASE + IMXRT_GPIO_ICR1_OFFSET) -# define IMXRT_GPIO8_ICR2 (IMXRT_GPIO8_BASE + IMXRT_GPIO_ICR2_OFFSET) -# define IMXRT_GPIO8_IMR (IMXRT_GPIO8_BASE + IMXRT_GPIO_IMR_OFFSET) -# define IMXRT_GPIO8_ISR (IMXRT_GPIO8_BASE + IMXRT_GPIO_ISR_OFFSET) -# define IMXRT_GPIO8_EDGE (IMXRT_GPIO8_BASE + IMXRT_GPIO_EDGE_OFFSET) -# define IMXRT_GPIO8_SET (IMXRT_GPIO8_BASE + IMXRT_GPIO_SET_OFFSET) -# define IMXRT_GPIO8_CLEAR (IMXRT_GPIO8_BASE + IMXRT_GPIO_CLEAR_OFFSET) -# define IMXRT_GPIO8_TOGGLE (IMXRT_GPIO8_BASE + IMXRT_GPIO_TOGGLE_OFFSET) - -# define IMXRT_GPIO9_DR (IMXRT_GPIO9_BASE + IMXRT_GPIO_DR_OFFSET) -# define IMXRT_GPIO9_GDIR (IMXRT_GPIO9_BASE + IMXRT_GPIO_GDIR_OFFSET) -# define IMXRT_GPIO9_PSR (IMXRT_GPIO9_BASE + IMXRT_GPIO_PSR_OFFSET) -# define IMXRT_GPIO9_ICR1 (IMXRT_GPIO9_BASE + IMXRT_GPIO_ICR1_OFFSET) -# define IMXRT_GPIO9_ICR2 (IMXRT_GPIO9_BASE + IMXRT_GPIO_ICR2_OFFSET) -# define IMXRT_GPIO9_IMR (IMXRT_GPIO9_BASE + IMXRT_GPIO_IMR_OFFSET) -# define IMXRT_GPIO9_ISR (IMXRT_GPIO9_BASE + IMXRT_GPIO_ISR_OFFSET) -# define IMXRT_GPIO9_EDGE (IMXRT_GPIO9_BASE + IMXRT_GPIO_EDGE_OFFSET) -# define IMXRT_GPIO9_SET (IMXRT_GPIO9_BASE + IMXRT_GPIO_SET_OFFSET) -# define IMXRT_GPIO9_CLEAR (IMXRT_GPIO9_BASE + IMXRT_GPIO_CLEAR_OFFSET) -# define IMXRT_GPIO9_TOGGLE (IMXRT_GPIO9_BASE + IMXRT_GPIO_TOGGLE_OFFSET) - -#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_GPIO_H */ diff --git a/arch/arm/src/imxrt/chip/rt106x/imxrt106x_iomuxc.h b/arch/arm/src/imxrt/chip/rt106x/imxrt106x_iomuxc.h deleted file mode 100644 index 9ec3b043af0..00000000000 --- a/arch/arm/src/imxrt/chip/rt106x/imxrt106x_iomuxc.h +++ /dev/null @@ -1,2546 +0,0 @@ -/************************************************************************************ - * arch/arm/src/imxrt/rt106x/imxrt106x_iomuxc.h - * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * David Sidrane - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_IOMUXC_H -#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_IOMUXC_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include -#include "chip/imxrt_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ - -#define IMXRT_IOMUXC_GPR_GPR0_OFFSET 0x0000 /* GPR0 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR1_OFFSET 0x0004 /* GPR1 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR2_OFFSET 0x0008 /* GPR2 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR3_OFFSET 0x000c /* GPR3 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR4_OFFSET 0x0010 /* GPR4 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR5_OFFSET 0x0014 /* GPR5 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR6_OFFSET 0x0018 /* GPR6 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR7_OFFSET 0x001c /* GPR7 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR8_OFFSET 0x0020 /* GPR8 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR9_OFFSET 0x0024 /* GPR9 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR10_OFFSET 0x0028 /* GPR10 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR11_OFFSET 0x002c /* GPR11 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR12_OFFSET 0x0030 /* GPR12 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR13_OFFSET 0x0034 /* GPR13 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR14_OFFSET 0x0038 /* GPR14 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR15_OFFSET 0x003c /* GPR15 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR16_OFFSET 0x0040 /* GPR16 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR17_OFFSET 0x0044 /* GPR17 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR18_OFFSET 0x0048 /* GPR18 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR19_OFFSET 0x004c /* GPR19 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR20_OFFSET 0x0050 /* GPR20 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR21_OFFSET 0x0054 /* GPR21 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR22_OFFSET 0x0058 /* GPR22 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR23_OFFSET 0x005c /* GPR23 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR24_OFFSET 0x0060 /* GPR24 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR25_OFFSET 0x0064 /* GPR25 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR26_OFFSET 0x0068 /* GPR26 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR27_OFFSET 0x006C /* GPR27 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR28_OFFSET 0x0070 /* GPR28 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR29_OFFSET 0x0074 /* GPR29 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR30_OFFSET 0x0078 /* GPR30 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR31_OFFSET 0x007c /* GPR31 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR32_OFFSET 0x0080 /* GPR32 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR33_OFFSET 0x0084 /* GPR33 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR34_OFFSET 0x0088 /* GPR34 General Purpose Register*/ - -#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_OFFSET 0x0000 /* SW_MUX_CTL_PAD_WAKEUP SW MUX Control Register */ -#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_OFFSET 0x0004 /* SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register */ -#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_OFFSET 0x0008 /* SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register */ -#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_OFFSET 0x000c /* SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register */ -#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_OFFSET 0x0010 /* SW_PAD_CTL_PAD_POR_B SW PAD Control Register */ -#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_OFFSET 0x0014 /* SW_PAD_CTL_PAD_ONOFF SW PAD Control Register */ -#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_OFFSET 0x0018 /* SW_PAD_CTL_PAD_WAKEUP SW PAD Control Register */ -#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_OFFSET 0x001c /* SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register */ -#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_OFFSET 0x0020 /* SW_PAD_CTL_PAD_PMIC_STBY_REQ SW PAD Control Register */ - -#define IMXRT_IOMUXC_SNVS_GPR_GPR0_OFFSET 0x0000 /* SNVC GPR0 General Purpose Register */ -#define IMXRT_IOMUXC_SNVS_GPR_GPR1_OFFSET 0x0004 /* SNVC GPR1 General Purpose Register */ -#define IMXRT_IOMUXC_SNVS_GPR_GPR2_OFFSET 0x0008 /* SNVC GPR2 General Purpose Register */ -#define IMXRT_IOMUXC_SNVS_GPR_GPR3_OFFSET 0x000c /* SNVC GPR3 General Purpose Register */ - -/* Pad Mux Registers */ -/* Pad Mux Register Indices (used by software for table lookups) */ - -#define IMXRT_PADMUX_GPIO_EMC_00_INDEX 0 -#define IMXRT_PADMUX_GPIO_EMC_01_INDEX 1 -#define IMXRT_PADMUX_GPIO_EMC_02_INDEX 2 -#define IMXRT_PADMUX_GPIO_EMC_03_INDEX 3 -#define IMXRT_PADMUX_GPIO_EMC_04_INDEX 4 -#define IMXRT_PADMUX_GPIO_EMC_05_INDEX 5 -#define IMXRT_PADMUX_GPIO_EMC_06_INDEX 6 -#define IMXRT_PADMUX_GPIO_EMC_07_INDEX 7 -#define IMXRT_PADMUX_GPIO_EMC_08_INDEX 8 -#define IMXRT_PADMUX_GPIO_EMC_09_INDEX 9 -#define IMXRT_PADMUX_GPIO_EMC_10_INDEX 10 -#define IMXRT_PADMUX_GPIO_EMC_11_INDEX 11 -#define IMXRT_PADMUX_GPIO_EMC_12_INDEX 12 -#define IMXRT_PADMUX_GPIO_EMC_13_INDEX 13 -#define IMXRT_PADMUX_GPIO_EMC_14_INDEX 14 -#define IMXRT_PADMUX_GPIO_EMC_15_INDEX 15 -#define IMXRT_PADMUX_GPIO_EMC_16_INDEX 16 -#define IMXRT_PADMUX_GPIO_EMC_17_INDEX 17 -#define IMXRT_PADMUX_GPIO_EMC_18_INDEX 18 -#define IMXRT_PADMUX_GPIO_EMC_19_INDEX 19 -#define IMXRT_PADMUX_GPIO_EMC_20_INDEX 20 -#define IMXRT_PADMUX_GPIO_EMC_21_INDEX 21 -#define IMXRT_PADMUX_GPIO_EMC_22_INDEX 22 -#define IMXRT_PADMUX_GPIO_EMC_23_INDEX 23 -#define IMXRT_PADMUX_GPIO_EMC_24_INDEX 24 -#define IMXRT_PADMUX_GPIO_EMC_25_INDEX 25 -#define IMXRT_PADMUX_GPIO_EMC_26_INDEX 26 -#define IMXRT_PADMUX_GPIO_EMC_27_INDEX 27 -#define IMXRT_PADMUX_GPIO_EMC_28_INDEX 28 -#define IMXRT_PADMUX_GPIO_EMC_29_INDEX 29 -#define IMXRT_PADMUX_GPIO_EMC_30_INDEX 30 -#define IMXRT_PADMUX_GPIO_EMC_31_INDEX 31 -#define IMXRT_PADMUX_GPIO_EMC_32_INDEX 32 -#define IMXRT_PADMUX_GPIO_EMC_33_INDEX 33 -#define IMXRT_PADMUX_GPIO_EMC_34_INDEX 34 -#define IMXRT_PADMUX_GPIO_EMC_35_INDEX 35 -#define IMXRT_PADMUX_GPIO_EMC_36_INDEX 36 -#define IMXRT_PADMUX_GPIO_EMC_37_INDEX 37 -#define IMXRT_PADMUX_GPIO_EMC_38_INDEX 38 -#define IMXRT_PADMUX_GPIO_EMC_39_INDEX 39 -#define IMXRT_PADMUX_GPIO_EMC_40_INDEX 40 -#define IMXRT_PADMUX_GPIO_EMC_41_INDEX 41 -#define IMXRT_PADMUX_GPIO_AD_B0_00_INDEX 42 -#define IMXRT_PADMUX_GPIO_AD_B0_01_INDEX 43 -#define IMXRT_PADMUX_GPIO_AD_B0_02_INDEX 44 -#define IMXRT_PADMUX_GPIO_AD_B0_03_INDEX 45 -#define IMXRT_PADMUX_GPIO_AD_B0_04_INDEX 46 -#define IMXRT_PADMUX_GPIO_AD_B0_05_INDEX 47 -#define IMXRT_PADMUX_GPIO_AD_B0_06_INDEX 48 -#define IMXRT_PADMUX_GPIO_AD_B0_07_INDEX 49 -#define IMXRT_PADMUX_GPIO_AD_B0_08_INDEX 50 -#define IMXRT_PADMUX_GPIO_AD_B0_09_INDEX 51 -#define IMXRT_PADMUX_GPIO_AD_B0_10_INDEX 52 -#define IMXRT_PADMUX_GPIO_AD_B0_11_INDEX 53 -#define IMXRT_PADMUX_GPIO_AD_B0_12_INDEX 54 -#define IMXRT_PADMUX_GPIO_AD_B0_13_INDEX 55 -#define IMXRT_PADMUX_GPIO_AD_B0_14_INDEX 56 -#define IMXRT_PADMUX_GPIO_AD_B0_15_INDEX 57 -#define IMXRT_PADMUX_GPIO_AD_B1_00_INDEX 58 -#define IMXRT_PADMUX_GPIO_AD_B1_01_INDEX 59 -#define IMXRT_PADMUX_GPIO_AD_B1_02_INDEX 60 -#define IMXRT_PADMUX_GPIO_AD_B1_03_INDEX 61 -#define IMXRT_PADMUX_GPIO_AD_B1_04_INDEX 62 -#define IMXRT_PADMUX_GPIO_AD_B1_05_INDEX 63 -#define IMXRT_PADMUX_GPIO_AD_B1_06_INDEX 64 -#define IMXRT_PADMUX_GPIO_AD_B1_07_INDEX 65 -#define IMXRT_PADMUX_GPIO_AD_B1_08_INDEX 66 -#define IMXRT_PADMUX_GPIO_AD_B1_09_INDEX 67 -#define IMXRT_PADMUX_GPIO_AD_B1_10_INDEX 68 -#define IMXRT_PADMUX_GPIO_AD_B1_11_INDEX 69 -#define IMXRT_PADMUX_GPIO_AD_B1_12_INDEX 70 -#define IMXRT_PADMUX_GPIO_AD_B1_13_INDEX 71 -#define IMXRT_PADMUX_GPIO_AD_B1_14_INDEX 72 -#define IMXRT_PADMUX_GPIO_AD_B1_15_INDEX 73 -#define IMXRT_PADMUX_GPIO_B0_00_INDEX 74 -#define IMXRT_PADMUX_GPIO_B0_01_INDEX 75 -#define IMXRT_PADMUX_GPIO_B0_02_INDEX 76 -#define IMXRT_PADMUX_GPIO_B0_03_INDEX 77 -#define IMXRT_PADMUX_GPIO_B0_04_INDEX 78 -#define IMXRT_PADMUX_GPIO_B0_05_INDEX 79 -#define IMXRT_PADMUX_GPIO_B0_06_INDEX 80 -#define IMXRT_PADMUX_GPIO_B0_07_INDEX 81 -#define IMXRT_PADMUX_GPIO_B0_08_INDEX 82 -#define IMXRT_PADMUX_GPIO_B0_09_INDEX 83 -#define IMXRT_PADMUX_GPIO_B0_10_INDEX 84 -#define IMXRT_PADMUX_GPIO_B0_11_INDEX 85 -#define IMXRT_PADMUX_GPIO_B0_12_INDEX 86 -#define IMXRT_PADMUX_GPIO_B0_13_INDEX 87 -#define IMXRT_PADMUX_GPIO_B0_14_INDEX 88 -#define IMXRT_PADMUX_GPIO_B0_15_INDEX 89 -#define IMXRT_PADMUX_GPIO_B1_00_INDEX 90 -#define IMXRT_PADMUX_GPIO_B1_01_INDEX 91 -#define IMXRT_PADMUX_GPIO_B1_02_INDEX 92 -#define IMXRT_PADMUX_GPIO_B1_03_INDEX 93 -#define IMXRT_PADMUX_GPIO_B1_04_INDEX 94 -#define IMXRT_PADMUX_GPIO_B1_05_INDEX 95 -#define IMXRT_PADMUX_GPIO_B1_06_INDEX 96 -#define IMXRT_PADMUX_GPIO_B1_07_INDEX 97 -#define IMXRT_PADMUX_GPIO_B1_08_INDEX 98 -#define IMXRT_PADMUX_GPIO_B1_09_INDEX 99 -#define IMXRT_PADMUX_GPIO_B1_10_INDEX 100 -#define IMXRT_PADMUX_GPIO_B1_11_INDEX 101 -#define IMXRT_PADMUX_GPIO_B1_12_INDEX 102 -#define IMXRT_PADMUX_GPIO_B1_13_INDEX 103 -#define IMXRT_PADMUX_GPIO_B1_14_INDEX 104 -#define IMXRT_PADMUX_GPIO_B1_15_INDEX 105 -#define IMXRT_PADMUX_GPIO_SD_B0_00_INDEX 106 -#define IMXRT_PADMUX_GPIO_SD_B0_01_INDEX 107 -#define IMXRT_PADMUX_GPIO_SD_B0_02_INDEX 108 -#define IMXRT_PADMUX_GPIO_SD_B0_03_INDEX 109 -#define IMXRT_PADMUX_GPIO_SD_B0_04_INDEX 110 -#define IMXRT_PADMUX_GPIO_SD_B0_05_INDEX 111 -#define IMXRT_PADMUX_GPIO_SD_B1_00_INDEX 112 -#define IMXRT_PADMUX_GPIO_SD_B1_01_INDEX 113 -#define IMXRT_PADMUX_GPIO_SD_B1_02_INDEX 114 -#define IMXRT_PADMUX_GPIO_SD_B1_03_INDEX 115 -#define IMXRT_PADMUX_GPIO_SD_B1_04_INDEX 116 -#define IMXRT_PADMUX_GPIO_SD_B1_05_INDEX 117 -#define IMXRT_PADMUX_GPIO_SD_B1_06_INDEX 118 -#define IMXRT_PADMUX_GPIO_SD_B1_07_INDEX 119 -#define IMXRT_PADMUX_GPIO_SD_B1_08_INDEX 120 -#define IMXRT_PADMUX_GPIO_SD_B1_09_INDEX 121 -#define IMXRT_PADMUX_GPIO_SD_B1_10_INDEX 122 -#define IMXRT_PADMUX_GPIO_SD_B1_11_INDEX 123 - -#define IMXRT_PADMUX_WAKEUP_INDEX 124 -#define IMXRT_PADMUX_PMIC_ON_REQ_INDEX 125 -#define IMXRT_PADMUX_PMIC_STBY_REQ_INDEX 126 - -#define IMXRT_PADMUX_GPIO_SPI_B0_00_INDEX 127 -#define IMXRT_PADMUX_GPIO_SPI_B0_01_INDEX 128 -#define IMXRT_PADMUX_GPIO_SPI_B0_02_INDEX 129 -#define IMXRT_PADMUX_GPIO_SPI_B0_03_INDEX 130 -#define IMXRT_PADMUX_GPIO_SPI_B0_04_INDEX 131 -#define IMXRT_PADMUX_GPIO_SPI_B0_05_INDEX 132 -#define IMXRT_PADMUX_GPIO_SPI_B0_06_INDEX 133 -#define IMXRT_PADMUX_GPIO_SPI_B0_07_INDEX 134 -#define IMXRT_PADMUX_GPIO_SPI_B0_08_INDEX 135 -#define IMXRT_PADMUX_GPIO_SPI_B0_09_INDEX 136 -#define IMXRT_PADMUX_GPIO_SPI_B0_10_INDEX 137 -#define IMXRT_PADMUX_GPIO_SPI_B0_11_INDEX 138 -#define IMXRT_PADMUX_GPIO_SPI_B0_12_INDEX 139 -#define IMXRT_PADMUX_GPIO_SPI_B0_13_INDEX 140 -#define IMXRT_PADMUX_GPIO_SPI_B1_00_INDEX 141 -#define IMXRT_PADMUX_GPIO_SPI_B1_01_INDEX 142 -#define IMXRT_PADMUX_GPIO_SPI_B1_02_INDEX 143 -#define IMXRT_PADMUX_GPIO_SPI_B1_03_INDEX 144 -#define IMXRT_PADMUX_GPIO_SPI_B1_04_INDEX 145 -#define IMXRT_PADMUX_GPIO_SPI_B1_05_INDEX 146 -#define IMXRT_PADMUX_GPIO_SPI_B1_06_INDEX 147 -#define IMXRT_PADMUX_GPIO_SPI_B1_07_INDEX 148 - -#define IMXRT_PADMUX_NREGISTERS 149 - -/* Pad Mux Register Offsets */ - -#define IMXRT_PADMUX_OFFSET(n) (0x0014 + ((unsigned int)(n) << 2)) -#define IMXRT_PADMUX_OFFSET_SNVS(n) ((unsigned int)(n) << 2) - -#define IMXRT_PADMUX_GPIO_EMC_00_OFFSET 0x0014 -#define IMXRT_PADMUX_GPIO_EMC_01_OFFSET 0x0018 -#define IMXRT_PADMUX_GPIO_EMC_02_OFFSET 0x001c -#define IMXRT_PADMUX_GPIO_EMC_03_OFFSET 0x0020 -#define IMXRT_PADMUX_GPIO_EMC_04_OFFSET 0x0024 -#define IMXRT_PADMUX_GPIO_EMC_05_OFFSET 0x0028 -#define IMXRT_PADMUX_GPIO_EMC_06_OFFSET 0x002c -#define IMXRT_PADMUX_GPIO_EMC_07_OFFSET 0x0030 -#define IMXRT_PADMUX_GPIO_EMC_08_OFFSET 0x0034 -#define IMXRT_PADMUX_GPIO_EMC_09_OFFSET 0x0038 -#define IMXRT_PADMUX_GPIO_EMC_10_OFFSET 0x003c -#define IMXRT_PADMUX_GPIO_EMC_11_OFFSET 0x0040 -#define IMXRT_PADMUX_GPIO_EMC_12_OFFSET 0x0044 -#define IMXRT_PADMUX_GPIO_EMC_13_OFFSET 0x0048 -#define IMXRT_PADMUX_GPIO_EMC_14_OFFSET 0x004c -#define IMXRT_PADMUX_GPIO_EMC_15_OFFSET 0x0050 -#define IMXRT_PADMUX_GPIO_EMC_16_OFFSET 0x0054 -#define IMXRT_PADMUX_GPIO_EMC_17_OFFSET 0x0058 -#define IMXRT_PADMUX_GPIO_EMC_18_OFFSET 0x005c -#define IMXRT_PADMUX_GPIO_EMC_19_OFFSET 0x0060 -#define IMXRT_PADMUX_GPIO_EMC_20_OFFSET 0x0064 -#define IMXRT_PADMUX_GPIO_EMC_21_OFFSET 0x0068 -#define IMXRT_PADMUX_GPIO_EMC_22_OFFSET 0x006c -#define IMXRT_PADMUX_GPIO_EMC_23_OFFSET 0x0070 -#define IMXRT_PADMUX_GPIO_EMC_24_OFFSET 0x0074 -#define IMXRT_PADMUX_GPIO_EMC_25_OFFSET 0x0078 -#define IMXRT_PADMUX_GPIO_EMC_26_OFFSET 0x007c -#define IMXRT_PADMUX_GPIO_EMC_27_OFFSET 0x0080 -#define IMXRT_PADMUX_GPIO_EMC_28_OFFSET 0x0084 -#define IMXRT_PADMUX_GPIO_EMC_29_OFFSET 0x0088 -#define IMXRT_PADMUX_GPIO_EMC_30_OFFSET 0x008c -#define IMXRT_PADMUX_GPIO_EMC_31_OFFSET 0x0090 -#define IMXRT_PADMUX_GPIO_EMC_32_OFFSET 0x0094 -#define IMXRT_PADMUX_GPIO_EMC_33_OFFSET 0x0098 -#define IMXRT_PADMUX_GPIO_EMC_34_OFFSET 0x009c -#define IMXRT_PADMUX_GPIO_EMC_35_OFFSET 0x00a0 -#define IMXRT_PADMUX_GPIO_EMC_36_OFFSET 0x00a4 -#define IMXRT_PADMUX_GPIO_EMC_37_OFFSET 0x00a8 -#define IMXRT_PADMUX_GPIO_EMC_38_OFFSET 0x00ac -#define IMXRT_PADMUX_GPIO_EMC_39_OFFSET 0x00b0 -#define IMXRT_PADMUX_GPIO_EMC_40_OFFSET 0x00b4 -#define IMXRT_PADMUX_GPIO_EMC_41_OFFSET 0x00b8 -#define IMXRT_PADMUX_GPIO_AD_B0_00_OFFSET 0x00bc -#define IMXRT_PADMUX_GPIO_AD_B0_01_OFFSET 0x00c0 -#define IMXRT_PADMUX_GPIO_AD_B0_02_OFFSET 0x00c4 -#define IMXRT_PADMUX_GPIO_AD_B0_03_OFFSET 0x00c8 -#define IMXRT_PADMUX_GPIO_AD_B0_04_OFFSET 0x00cc -#define IMXRT_PADMUX_GPIO_AD_B0_05_OFFSET 0x00d0 -#define IMXRT_PADMUX_GPIO_AD_B0_06_OFFSET 0x00d4 -#define IMXRT_PADMUX_GPIO_AD_B0_07_OFFSET 0x00d8 -#define IMXRT_PADMUX_GPIO_AD_B0_08_OFFSET 0x00dc -#define IMXRT_PADMUX_GPIO_AD_B0_09_OFFSET 0x00e0 -#define IMXRT_PADMUX_GPIO_AD_B0_10_OFFSET 0x00e4 -#define IMXRT_PADMUX_GPIO_AD_B0_11_OFFSET 0x00e8 -#define IMXRT_PADMUX_GPIO_AD_B0_12_OFFSET 0x00ec -#define IMXRT_PADMUX_GPIO_AD_B0_13_OFFSET 0x00f0 -#define IMXRT_PADMUX_GPIO_AD_B0_14_OFFSET 0x00f4 -#define IMXRT_PADMUX_GPIO_AD_B0_15_OFFSET 0x00f8 -#define IMXRT_PADMUX_GPIO_AD_B1_00_OFFSET 0x00fc -#define IMXRT_PADMUX_GPIO_AD_B1_01_OFFSET 0x0100 -#define IMXRT_PADMUX_GPIO_AD_B1_02_OFFSET 0x0104 -#define IMXRT_PADMUX_GPIO_AD_B1_03_OFFSET 0x0108 -#define IMXRT_PADMUX_GPIO_AD_B1_04_OFFSET 0x010c -#define IMXRT_PADMUX_GPIO_AD_B1_05_OFFSET 0x0110 -#define IMXRT_PADMUX_GPIO_AD_B1_06_OFFSET 0x0114 -#define IMXRT_PADMUX_GPIO_AD_B1_07_OFFSET 0x0118 -#define IMXRT_PADMUX_GPIO_AD_B1_08_OFFSET 0x011c -#define IMXRT_PADMUX_GPIO_AD_B1_09_OFFSET 0x0120 -#define IMXRT_PADMUX_GPIO_AD_B1_10_OFFSET 0x0124 -#define IMXRT_PADMUX_GPIO_AD_B1_11_OFFSET 0x0128 -#define IMXRT_PADMUX_GPIO_AD_B1_12_OFFSET 0x012c -#define IMXRT_PADMUX_GPIO_AD_B1_13_OFFSET 0x0130 -#define IMXRT_PADMUX_GPIO_AD_B1_14_OFFSET 0x0134 -#define IMXRT_PADMUX_GPIO_AD_B1_15_OFFSET 0x0138 -#define IMXRT_PADMUX_GPIO_B0_00_OFFSET 0x013c -#define IMXRT_PADMUX_GPIO_B0_01_OFFSET 0x0140 -#define IMXRT_PADMUX_GPIO_B0_02_OFFSET 0x0144 -#define IMXRT_PADMUX_GPIO_B0_03_OFFSET 0x0148 -#define IMXRT_PADMUX_GPIO_B0_04_OFFSET 0x014c -#define IMXRT_PADMUX_GPIO_B0_05_OFFSET 0x0150 -#define IMXRT_PADMUX_GPIO_B0_06_OFFSET 0x0154 -#define IMXRT_PADMUX_GPIO_B0_07_OFFSET 0x0158 -#define IMXRT_PADMUX_GPIO_B0_08_OFFSET 0x015c -#define IMXRT_PADMUX_GPIO_B0_09_OFFSET 0x0160 -#define IMXRT_PADMUX_GPIO_B0_10_OFFSET 0x0164 -#define IMXRT_PADMUX_GPIO_B0_11_OFFSET 0x0168 -#define IMXRT_PADMUX_GPIO_B0_12_OFFSET 0x016c -#define IMXRT_PADMUX_GPIO_B0_13_OFFSET 0x0170 -#define IMXRT_PADMUX_GPIO_B0_14_OFFSET 0x0174 -#define IMXRT_PADMUX_GPIO_B0_15_OFFSET 0x0178 -#define IMXRT_PADMUX_GPIO_B1_00_OFFSET 0x017c -#define IMXRT_PADMUX_GPIO_B1_01_OFFSET 0x0180 -#define IMXRT_PADMUX_GPIO_B1_02_OFFSET 0x0184 -#define IMXRT_PADMUX_GPIO_B1_03_OFFSET 0x0188 -#define IMXRT_PADMUX_GPIO_B1_04_OFFSET 0x018c -#define IMXRT_PADMUX_GPIO_B1_05_OFFSET 0x0190 -#define IMXRT_PADMUX_GPIO_B1_06_OFFSET 0x0194 -#define IMXRT_PADMUX_GPIO_B1_07_OFFSET 0x0198 -#define IMXRT_PADMUX_GPIO_B1_08_OFFSET 0x019c -#define IMXRT_PADMUX_GPIO_B1_09_OFFSET 0x01a0 -#define IMXRT_PADMUX_GPIO_B1_10_OFFSET 0x01a4 -#define IMXRT_PADMUX_GPIO_B1_11_OFFSET 0x01a8 -#define IMXRT_PADMUX_GPIO_B1_12_OFFSET 0x01ac -#define IMXRT_PADMUX_GPIO_B1_13_OFFSET 0x01b0 -#define IMXRT_PADMUX_GPIO_B1_14_OFFSET 0x01b4 -#define IMXRT_PADMUX_GPIO_B1_15_OFFSET 0x01b8 -#define IMXRT_PADMUX_GPIO_SD_B0_00_OFFSET 0x01bc -#define IMXRT_PADMUX_GPIO_SD_B0_01_OFFSET 0x01c0 -#define IMXRT_PADMUX_GPIO_SD_B0_02_OFFSET 0x01c4 -#define IMXRT_PADMUX_GPIO_SD_B0_03_OFFSET 0x01c8 -#define IMXRT_PADMUX_GPIO_SD_B0_04_OFFSET 0x01cc -#define IMXRT_PADMUX_GPIO_SD_B0_05_OFFSET 0x01d0 -#define IMXRT_PADMUX_GPIO_SD_B1_00_OFFSET 0x01d4 -#define IMXRT_PADMUX_GPIO_SD_B1_01_OFFSET 0x01d8 -#define IMXRT_PADMUX_GPIO_SD_B1_02_OFFSET 0x01dc -#define IMXRT_PADMUX_GPIO_SD_B1_03_OFFSET 0x01e0 -#define IMXRT_PADMUX_GPIO_SD_B1_04_OFFSET 0x01e4 -#define IMXRT_PADMUX_GPIO_SD_B1_05_OFFSET 0x01e8 -#define IMXRT_PADMUX_GPIO_SD_B1_06_OFFSET 0x01ec -#define IMXRT_PADMUX_GPIO_SD_B1_07_OFFSET 0x01f0 -#define IMXRT_PADMUX_GPIO_SD_B1_08_OFFSET 0x01f4 -#define IMXRT_PADMUX_GPIO_SD_B1_09_OFFSET 0x01f8 -#define IMXRT_PADMUX_GPIO_SD_B1_10_OFFSET 0x01fc -#define IMXRT_PADMUX_GPIO_SD_B1_11_OFFSET 0x0200 - -/* Pad1 Mux Register Offsets */ - -#define IMXRT_PAD1MUX_OFFSET(n) (0x065c + ((unsigned int)(n) << 2)) - -#define IMXRT_PADMUX_GPIO_SPI_B0_00_OFFSET 0x065c -#define IMXRT_PADMUX_GPIO_SPI_B0_01_OFFSET 0x0660 -#define IMXRT_PADMUX_GPIO_SPI_B0_02_OFFSET 0x0664 -#define IMXRT_PADMUX_GPIO_SPI_B0_03_OFFSET 0x0668 -#define IMXRT_PADMUX_GPIO_SPI_B0_04_OFFSET 0x066c -#define IMXRT_PADMUX_GPIO_SPI_B0_05_OFFSET 0x0670 -#define IMXRT_PADMUX_GPIO_SPI_B0_06_OFFSET 0x0674 -#define IMXRT_PADMUX_GPIO_SPI_B0_07_OFFSET 0x0678 -#define IMXRT_PADMUX_GPIO_SPI_B0_08_OFFSET 0x067c -#define IMXRT_PADMUX_GPIO_SPI_B0_09_OFFSET 0x0680 -#define IMXRT_PADMUX_GPIO_SPI_B0_10_OFFSET 0x0684 -#define IMXRT_PADMUX_GPIO_SPI_B0_11_OFFSET 0x0688 -#define IMXRT_PADMUX_GPIO_SPI_B0_12_OFFSET 0x068c -#define IMXRT_PADMUX_GPIO_SPI_B0_13_OFFSET 0x0690 -#define IMXRT_PADMUX_GPIO_SPI_B1_00_OFFSET 0x0694 -#define IMXRT_PADMUX_GPIO_SPI_B1_01_OFFSET 0x0698 -#define IMXRT_PADMUX_GPIO_SPI_B1_02_OFFSET 0x069c -#define IMXRT_PADMUX_GPIO_SPI_B1_03_OFFSET 0x06a0 -#define IMXRT_PADMUX_GPIO_SPI_B1_04_OFFSET 0x06a4 -#define IMXRT_PADMUX_GPIO_SPI_B1_05_OFFSET 0x06a8 -#define IMXRT_PADMUX_GPIO_SPI_B1_06_OFFSET 0x06ac -#define IMXRT_PADMUX_GPIO_SPI_B1_07_OFFSET 0x06b0 - -/* Pad Control Registers - * Pad Control Register Indices (used by software for table lookups) - */ - -#define IMXRT_PADCTL_GPIO_EMC_00_INDEX 0 -#define IMXRT_PADCTL_GPIO_EMC_01_INDEX 1 -#define IMXRT_PADCTL_GPIO_EMC_02_INDEX 2 -#define IMXRT_PADCTL_GPIO_EMC_03_INDEX 3 -#define IMXRT_PADCTL_GPIO_EMC_04_INDEX 4 -#define IMXRT_PADCTL_GPIO_EMC_05_INDEX 5 -#define IMXRT_PADCTL_GPIO_EMC_06_INDEX 6 -#define IMXRT_PADCTL_GPIO_EMC_07_INDEX 7 -#define IMXRT_PADCTL_GPIO_EMC_08_INDEX 8 -#define IMXRT_PADCTL_GPIO_EMC_09_INDEX 9 -#define IMXRT_PADCTL_GPIO_EMC_10_INDEX 10 -#define IMXRT_PADCTL_GPIO_EMC_11_INDEX 11 -#define IMXRT_PADCTL_GPIO_EMC_12_INDEX 12 -#define IMXRT_PADCTL_GPIO_EMC_13_INDEX 13 -#define IMXRT_PADCTL_GPIO_EMC_14_INDEX 14 -#define IMXRT_PADCTL_GPIO_EMC_15_INDEX 15 -#define IMXRT_PADCTL_GPIO_EMC_16_INDEX 16 -#define IMXRT_PADCTL_GPIO_EMC_17_INDEX 17 -#define IMXRT_PADCTL_GPIO_EMC_18_INDEX 18 -#define IMXRT_PADCTL_GPIO_EMC_19_INDEX 19 -#define IMXRT_PADCTL_GPIO_EMC_20_INDEX 20 -#define IMXRT_PADCTL_GPIO_EMC_21_INDEX 21 -#define IMXRT_PADCTL_GPIO_EMC_22_INDEX 22 -#define IMXRT_PADCTL_GPIO_EMC_23_INDEX 23 -#define IMXRT_PADCTL_GPIO_EMC_24_INDEX 24 -#define IMXRT_PADCTL_GPIO_EMC_25_INDEX 25 -#define IMXRT_PADCTL_GPIO_EMC_26_INDEX 26 -#define IMXRT_PADCTL_GPIO_EMC_27_INDEX 27 -#define IMXRT_PADCTL_GPIO_EMC_28_INDEX 28 -#define IMXRT_PADCTL_GPIO_EMC_29_INDEX 29 -#define IMXRT_PADCTL_GPIO_EMC_30_INDEX 30 -#define IMXRT_PADCTL_GPIO_EMC_31_INDEX 31 -#define IMXRT_PADCTL_GPIO_EMC_32_INDEX 32 -#define IMXRT_PADCTL_GPIO_EMC_33_INDEX 33 -#define IMXRT_PADCTL_GPIO_EMC_34_INDEX 34 -#define IMXRT_PADCTL_GPIO_EMC_35_INDEX 35 -#define IMXRT_PADCTL_GPIO_EMC_36_INDEX 36 -#define IMXRT_PADCTL_GPIO_EMC_37_INDEX 37 -#define IMXRT_PADCTL_GPIO_EMC_38_INDEX 38 -#define IMXRT_PADCTL_GPIO_EMC_39_INDEX 39 -#define IMXRT_PADCTL_GPIO_EMC_40_INDEX 40 -#define IMXRT_PADCTL_GPIO_EMC_41_INDEX 41 -#define IMXRT_PADCTL_GPIO_AD_B0_00_INDEX 42 -#define IMXRT_PADCTL_GPIO_AD_B0_01_INDEX 43 -#define IMXRT_PADCTL_GPIO_AD_B0_02_INDEX 44 -#define IMXRT_PADCTL_GPIO_AD_B0_03_INDEX 45 -#define IMXRT_PADCTL_GPIO_AD_B0_04_INDEX 46 -#define IMXRT_PADCTL_GPIO_AD_B0_05_INDEX 47 -#define IMXRT_PADCTL_GPIO_AD_B0_06_INDEX 48 -#define IMXRT_PADCTL_GPIO_AD_B0_07_INDEX 49 -#define IMXRT_PADCTL_GPIO_AD_B0_08_INDEX 50 -#define IMXRT_PADCTL_GPIO_AD_B0_09_INDEX 51 -#define IMXRT_PADCTL_GPIO_AD_B0_10_INDEX 52 -#define IMXRT_PADCTL_GPIO_AD_B0_11_INDEX 53 -#define IMXRT_PADCTL_GPIO_AD_B0_12_INDEX 54 -#define IMXRT_PADCTL_GPIO_AD_B0_13_INDEX 55 -#define IMXRT_PADCTL_GPIO_AD_B0_14_INDEX 56 -#define IMXRT_PADCTL_GPIO_AD_B0_15_INDEX 57 -#define IMXRT_PADCTL_GPIO_AD_B1_00_INDEX 58 -#define IMXRT_PADCTL_GPIO_AD_B1_01_INDEX 59 -#define IMXRT_PADCTL_GPIO_AD_B1_02_INDEX 60 -#define IMXRT_PADCTL_GPIO_AD_B1_03_INDEX 61 -#define IMXRT_PADCTL_GPIO_AD_B1_04_INDEX 62 -#define IMXRT_PADCTL_GPIO_AD_B1_05_INDEX 63 -#define IMXRT_PADCTL_GPIO_AD_B1_06_INDEX 64 -#define IMXRT_PADCTL_GPIO_AD_B1_07_INDEX 65 -#define IMXRT_PADCTL_GPIO_AD_B1_08_INDEX 66 -#define IMXRT_PADCTL_GPIO_AD_B1_09_INDEX 67 -#define IMXRT_PADCTL_GPIO_AD_B1_10_INDEX 68 -#define IMXRT_PADCTL_GPIO_AD_B1_11_INDEX 69 -#define IMXRT_PADCTL_GPIO_AD_B1_12_INDEX 70 -#define IMXRT_PADCTL_GPIO_AD_B1_13_INDEX 71 -#define IMXRT_PADCTL_GPIO_AD_B1_14_INDEX 72 -#define IMXRT_PADCTL_GPIO_AD_B1_15_INDEX 73 -#define IMXRT_PADCTL_GPIO_B0_00_INDEX 74 -#define IMXRT_PADCTL_GPIO_B0_01_INDEX 75 -#define IMXRT_PADCTL_GPIO_B0_02_INDEX 76 -#define IMXRT_PADCTL_GPIO_B0_03_INDEX 77 -#define IMXRT_PADCTL_GPIO_B0_04_INDEX 78 -#define IMXRT_PADCTL_GPIO_B0_05_INDEX 79 -#define IMXRT_PADCTL_GPIO_B0_06_INDEX 80 -#define IMXRT_PADCTL_GPIO_B0_07_INDEX 81 -#define IMXRT_PADCTL_GPIO_B0_08_INDEX 82 -#define IMXRT_PADCTL_GPIO_B0_09_INDEX 83 -#define IMXRT_PADCTL_GPIO_B0_10_INDEX 84 -#define IMXRT_PADCTL_GPIO_B0_11_INDEX 85 -#define IMXRT_PADCTL_GPIO_B0_12_INDEX 86 -#define IMXRT_PADCTL_GPIO_B0_13_INDEX 87 -#define IMXRT_PADCTL_GPIO_B0_14_INDEX 88 -#define IMXRT_PADCTL_GPIO_B0_15_INDEX 89 -#define IMXRT_PADCTL_GPIO_B1_00_INDEX 90 -#define IMXRT_PADCTL_GPIO_B1_01_INDEX 91 -#define IMXRT_PADCTL_GPIO_B1_02_INDEX 92 -#define IMXRT_PADCTL_GPIO_B1_03_INDEX 93 -#define IMXRT_PADCTL_GPIO_B1_04_INDEX 94 -#define IMXRT_PADCTL_GPIO_B1_05_INDEX 95 -#define IMXRT_PADCTL_GPIO_B1_06_INDEX 96 -#define IMXRT_PADCTL_GPIO_B1_07_INDEX 97 -#define IMXRT_PADCTL_GPIO_B1_08_INDEX 98 -#define IMXRT_PADCTL_GPIO_B1_09_INDEX 99 -#define IMXRT_PADCTL_GPIO_B1_10_INDEX 100 -#define IMXRT_PADCTL_GPIO_B1_11_INDEX 101 -#define IMXRT_PADCTL_GPIO_B1_12_INDEX 102 -#define IMXRT_PADCTL_GPIO_B1_13_INDEX 103 -#define IMXRT_PADCTL_GPIO_B1_14_INDEX 104 -#define IMXRT_PADCTL_GPIO_B1_15_INDEX 105 -#define IMXRT_PADCTL_GPIO_SD_B0_00_INDEX 106 -#define IMXRT_PADCTL_GPIO_SD_B0_01_INDEX 107 -#define IMXRT_PADCTL_GPIO_SD_B0_02_INDEX 108 -#define IMXRT_PADCTL_GPIO_SD_B0_03_INDEX 109 -#define IMXRT_PADCTL_GPIO_SD_B0_04_INDEX 110 -#define IMXRT_PADCTL_GPIO_SD_B0_05_INDEX 111 -#define IMXRT_PADCTL_GPIO_SD_B1_00_INDEX 112 -#define IMXRT_PADCTL_GPIO_SD_B1_01_INDEX 113 -#define IMXRT_PADCTL_GPIO_SD_B1_02_INDEX 114 -#define IMXRT_PADCTL_GPIO_SD_B1_03_INDEX 115 -#define IMXRT_PADCTL_GPIO_SD_B1_04_INDEX 116 -#define IMXRT_PADCTL_GPIO_SD_B1_05_INDEX 117 -#define IMXRT_PADCTL_GPIO_SD_B1_06_INDEX 118 -#define IMXRT_PADCTL_GPIO_SD_B1_07_INDEX 119 -#define IMXRT_PADCTL_GPIO_SD_B1_08_INDEX 120 -#define IMXRT_PADCTL_GPIO_SD_B1_09_INDEX 121 -#define IMXRT_PADCTL_GPIO_SD_B1_10_INDEX 122 -#define IMXRT_PADCTL_GPIO_SD_B1_11_INDEX 123 - -#define IMXRT_PADCTL_WAKEUP_INDEX 124 -#define IMXRT_PADCTL_PMIC_ON_REQ_INDEX 125 -#define IMXRT_PADCTL_PMIC_STBY_REQ_INDEX 126 - -#define IMXRT_PADCTL_GPIO_SPI_B0_00_INDEX 127 -#define IMXRT_PADCTL_GPIO_SPI_B0_01_INDEX 128 -#define IMXRT_PADCTL_GPIO_SPI_B0_02_INDEX 129 -#define IMXRT_PADCTL_GPIO_SPI_B0_03_INDEX 130 -#define IMXRT_PADCTL_GPIO_SPI_B0_04_INDEX 131 -#define IMXRT_PADCTL_GPIO_SPI_B0_05_INDEX 132 -#define IMXRT_PADCTL_GPIO_SPI_B0_06_INDEX 133 -#define IMXRT_PADCTL_GPIO_SPI_B0_07_INDEX 134 -#define IMXRT_PADCTL_GPIO_SPI_B0_08_INDEX 135 -#define IMXRT_PADCTL_GPIO_SPI_B0_09_INDEX 136 -#define IMXRT_PADCTL_GPIO_SPI_B0_10_INDEX 137 -#define IMXRT_PADCTL_GPIO_SPI_B0_11_INDEX 138 -#define IMXRT_PADCTL_GPIO_SPI_B0_12_INDEX 139 -#define IMXRT_PADCTL_GPIO_SPI_B0_13_INDEX 140 -#define IMXRT_PADCTL_GPIO_SPI_B1_00_INDEX 141 -#define IMXRT_PADCTL_GPIO_SPI_B1_01_INDEX 142 -#define IMXRT_PADCTL_GPIO_SPI_B1_02_INDEX 143 -#define IMXRT_PADCTL_GPIO_SPI_B1_03_INDEX 144 -#define IMXRT_PADCTL_GPIO_SPI_B1_04_INDEX 145 -#define IMXRT_PADCTL_GPIO_SPI_B1_05_INDEX 146 -#define IMXRT_PADCTL_GPIO_SPI_B1_06_INDEX 147 -#define IMXRT_PADCTL_GPIO_SPI_B1_07_INDEX 148 - -#define IMXRT_PADCTL_NREGISTERS 149 - -/* Pad Control Register Offsets */ - -#define IMXRT_PADCTL_OFFSET(n) (0x0204 + ((unsigned int)(n) << 2)) -#define IMXRT_PADCTL_OFFSET_SNVS(n) (0x18 + ((unsigned int)(n) << 2)) - -#define IMXRT_PADCTL_GPIO_EMC_00_OFFSET 0x0204 -#define IMXRT_PADCTL_GPIO_EMC_01_OFFSET 0x0208 -#define IMXRT_PADCTL_GPIO_EMC_02_OFFSET 0x020c -#define IMXRT_PADCTL_GPIO_EMC_03_OFFSET 0x0210 -#define IMXRT_PADCTL_GPIO_EMC_04_OFFSET 0x0214 -#define IMXRT_PADCTL_GPIO_EMC_05_OFFSET 0x0218 -#define IMXRT_PADCTL_GPIO_EMC_06_OFFSET 0x021c -#define IMXRT_PADCTL_GPIO_EMC_07_OFFSET 0x0220 -#define IMXRT_PADCTL_GPIO_EMC_08_OFFSET 0x0224 -#define IMXRT_PADCTL_GPIO_EMC_09_OFFSET 0x0228 -#define IMXRT_PADCTL_GPIO_EMC_10_OFFSET 0x022c -#define IMXRT_PADCTL_GPIO_EMC_11_OFFSET 0x0230 -#define IMXRT_PADCTL_GPIO_EMC_12_OFFSET 0x0234 -#define IMXRT_PADCTL_GPIO_EMC_13_OFFSET 0x0238 -#define IMXRT_PADCTL_GPIO_EMC_14_OFFSET 0x023c -#define IMXRT_PADCTL_GPIO_EMC_15_OFFSET 0x0240 -#define IMXRT_PADCTL_GPIO_EMC_16_OFFSET 0x0244 -#define IMXRT_PADCTL_GPIO_EMC_17_OFFSET 0x0248 -#define IMXRT_PADCTL_GPIO_EMC_18_OFFSET 0x024c -#define IMXRT_PADCTL_GPIO_EMC_19_OFFSET 0x0250 -#define IMXRT_PADCTL_GPIO_EMC_20_OFFSET 0x0254 -#define IMXRT_PADCTL_GPIO_EMC_21_OFFSET 0x0258 -#define IMXRT_PADCTL_GPIO_EMC_22_OFFSET 0x025c -#define IMXRT_PADCTL_GPIO_EMC_23_OFFSET 0x0260 -#define IMXRT_PADCTL_GPIO_EMC_24_OFFSET 0x0264 -#define IMXRT_PADCTL_GPIO_EMC_25_OFFSET 0x0268 -#define IMXRT_PADCTL_GPIO_EMC_26_OFFSET 0x026c -#define IMXRT_PADCTL_GPIO_EMC_27_OFFSET 0x0270 -#define IMXRT_PADCTL_GPIO_EMC_28_OFFSET 0x0274 -#define IMXRT_PADCTL_GPIO_EMC_29_OFFSET 0x0278 -#define IMXRT_PADCTL_GPIO_EMC_30_OFFSET 0x027c -#define IMXRT_PADCTL_GPIO_EMC_31_OFFSET 0x0280 -#define IMXRT_PADCTL_GPIO_EMC_32_OFFSET 0x0284 -#define IMXRT_PADCTL_GPIO_EMC_33_OFFSET 0x0288 -#define IMXRT_PADCTL_GPIO_EMC_34_OFFSET 0x028c -#define IMXRT_PADCTL_GPIO_EMC_35_OFFSET 0x0290 -#define IMXRT_PADCTL_GPIO_EMC_36_OFFSET 0x0294 -#define IMXRT_PADCTL_GPIO_EMC_37_OFFSET 0x0298 -#define IMXRT_PADCTL_GPIO_EMC_38_OFFSET 0x029c -#define IMXRT_PADCTL_GPIO_EMC_39_OFFSET 0x02a0 -#define IMXRT_PADCTL_GPIO_EMC_40_OFFSET 0x02a4 -#define IMXRT_PADCTL_GPIO_EMC_41_OFFSET 0x02a8 -#define IMXRT_PADCTL_GPIO_AD_B0_00_OFFSET 0x02ac -#define IMXRT_PADCTL_GPIO_AD_B0_01_OFFSET 0x02b0 -#define IMXRT_PADCTL_GPIO_AD_B0_02_OFFSET 0x02b4 -#define IMXRT_PADCTL_GPIO_AD_B0_03_OFFSET 0x02b8 -#define IMXRT_PADCTL_GPIO_AD_B0_04_OFFSET 0x02bc -#define IMXRT_PADCTL_GPIO_AD_B0_05_OFFSET 0x02c0 -#define IMXRT_PADCTL_GPIO_AD_B0_06_OFFSET 0x02c4 -#define IMXRT_PADCTL_GPIO_AD_B0_07_OFFSET 0x02c8 -#define IMXRT_PADCTL_GPIO_AD_B0_08_OFFSET 0x02cc -#define IMXRT_PADCTL_GPIO_AD_B0_09_OFFSET 0x02d0 -#define IMXRT_PADCTL_GPIO_AD_B0_10_OFFSET 0x02d4 -#define IMXRT_PADCTL_GPIO_AD_B0_11_OFFSET 0x02d8 -#define IMXRT_PADCTL_GPIO_AD_B0_12_OFFSET 0x02dc -#define IMXRT_PADCTL_GPIO_AD_B0_13_OFFSET 0x02e0 -#define IMXRT_PADCTL_GPIO_AD_B0_14_OFFSET 0x02e4 -#define IMXRT_PADCTL_GPIO_AD_B0_15_OFFSET 0x02e8 -#define IMXRT_PADCTL_GPIO_AD_B1_00_OFFSET 0x02ec -#define IMXRT_PADCTL_GPIO_AD_B1_01_OFFSET 0x02f0 -#define IMXRT_PADCTL_GPIO_AD_B1_02_OFFSET 0x02f4 -#define IMXRT_PADCTL_GPIO_AD_B1_03_OFFSET 0x02f8 -#define IMXRT_PADCTL_GPIO_AD_B1_04_OFFSET 0x02fc -#define IMXRT_PADCTL_GPIO_AD_B1_05_OFFSET 0x0300 -#define IMXRT_PADCTL_GPIO_AD_B1_06_OFFSET 0x0304 -#define IMXRT_PADCTL_GPIO_AD_B1_07_OFFSET 0x0308 -#define IMXRT_PADCTL_GPIO_AD_B1_08_OFFSET 0x030c -#define IMXRT_PADCTL_GPIO_AD_B1_09_OFFSET 0x0310 -#define IMXRT_PADCTL_GPIO_AD_B1_10_OFFSET 0x0314 -#define IMXRT_PADCTL_GPIO_AD_B1_11_OFFSET 0x0318 -#define IMXRT_PADCTL_GPIO_AD_B1_12_OFFSET 0x031c -#define IMXRT_PADCTL_GPIO_AD_B1_13_OFFSET 0x0320 -#define IMXRT_PADCTL_GPIO_AD_B1_14_OFFSET 0x0324 -#define IMXRT_PADCTL_GPIO_AD_B1_15_OFFSET 0x0328 -#define IMXRT_PADCTL_GPIO_B0_00_OFFSET 0x032c -#define IMXRT_PADCTL_GPIO_B0_01_OFFSET 0x0330 -#define IMXRT_PADCTL_GPIO_B0_02_OFFSET 0x0334 -#define IMXRT_PADCTL_GPIO_B0_03_OFFSET 0x0338 -#define IMXRT_PADCTL_GPIO_B0_04_OFFSET 0x033c -#define IMXRT_PADCTL_GPIO_B0_05_OFFSET 0x0340 -#define IMXRT_PADCTL_GPIO_B0_06_OFFSET 0x0344 -#define IMXRT_PADCTL_GPIO_B0_07_OFFSET 0x0348 -#define IMXRT_PADCTL_GPIO_B0_08_OFFSET 0x034c -#define IMXRT_PADCTL_GPIO_B0_09_OFFSET 0x0350 -#define IMXRT_PADCTL_GPIO_B0_10_OFFSET 0x0354 -#define IMXRT_PADCTL_GPIO_B0_11_OFFSET 0x0358 -#define IMXRT_PADCTL_GPIO_B0_12_OFFSET 0x035c -#define IMXRT_PADCTL_GPIO_B0_13_OFFSET 0x0360 -#define IMXRT_PADCTL_GPIO_B0_14_OFFSET 0x0364 -#define IMXRT_PADCTL_GPIO_B0_15_OFFSET 0x0368 -#define IMXRT_PADCTL_GPIO_B1_00_OFFSET 0x036c -#define IMXRT_PADCTL_GPIO_B1_01_OFFSET 0x0370 -#define IMXRT_PADCTL_GPIO_B1_02_OFFSET 0x0374 -#define IMXRT_PADCTL_GPIO_B1_03_OFFSET 0x0378 -#define IMXRT_PADCTL_GPIO_B1_04_OFFSET 0x037c -#define IMXRT_PADCTL_GPIO_B1_05_OFFSET 0x0380 -#define IMXRT_PADCTL_GPIO_B1_06_OFFSET 0x0384 -#define IMXRT_PADCTL_GPIO_B1_07_OFFSET 0x0388 -#define IMXRT_PADCTL_GPIO_B1_08_OFFSET 0x038c -#define IMXRT_PADCTL_GPIO_B1_09_OFFSET 0x0390 -#define IMXRT_PADCTL_GPIO_B1_10_OFFSET 0x0394 -#define IMXRT_PADCTL_GPIO_B1_11_OFFSET 0x0398 -#define IMXRT_PADCTL_GPIO_B1_12_OFFSET 0x039c -#define IMXRT_PADCTL_GPIO_B1_13_OFFSET 0x03a0 -#define IMXRT_PADCTL_GPIO_B1_14_OFFSET 0x03a4 -#define IMXRT_PADCTL_GPIO_B1_15_OFFSET 0x03a8 -#define IMXRT_PADCTL_GPIO_SD_B0_00_OFFSET 0x03ac -#define IMXRT_PADCTL_GPIO_SD_B0_01_OFFSET 0x03b0 -#define IMXRT_PADCTL_GPIO_SD_B0_02_OFFSET 0x03b4 -#define IMXRT_PADCTL_GPIO_SD_B0_03_OFFSET 0x03b8 -#define IMXRT_PADCTL_GPIO_SD_B0_04_OFFSET 0x03bc -#define IMXRT_PADCTL_GPIO_SD_B0_05_OFFSET 0x03c0 -#define IMXRT_PADCTL_GPIO_SD_B1_00_OFFSET 0x03c4 -#define IMXRT_PADCTL_GPIO_SD_B1_01_OFFSET 0x03c8 -#define IMXRT_PADCTL_GPIO_SD_B1_02_OFFSET 0x03cc -#define IMXRT_PADCTL_GPIO_SD_B1_03_OFFSET 0x03d0 -#define IMXRT_PADCTL_GPIO_SD_B1_04_OFFSET 0x03d4 -#define IMXRT_PADCTL_GPIO_SD_B1_05_OFFSET 0x03d8 -#define IMXRT_PADCTL_GPIO_SD_B1_06_OFFSET 0x03dc -#define IMXRT_PADCTL_GPIO_SD_B1_07_OFFSET 0x03e0 -#define IMXRT_PADCTL_GPIO_SD_B1_08_OFFSET 0x03e4 -#define IMXRT_PADCTL_GPIO_SD_B1_09_OFFSET 0x03e8 -#define IMXRT_PADCTL_GPIO_SD_B1_10_OFFSET 0x03ec -#define IMXRT_PADCTL_GPIO_SD_B1_11_OFFSET 0x03f0 - -/* Pad1 Control Register Offsets */ - -#define IMXRT_PAD1CTL_OFFSET(n) (0x06b4 + ((unsigned int)(n) << 2)) - -#define IMXRT_PADCTL_GPIO_SPI_B0_00_OFFSET 0x06b4 -#define IMXRT_PADCTL_GPIO_SPI_B0_01_OFFSET 0x06b8 -#define IMXRT_PADCTL_GPIO_SPI_B0_02_OFFSET 0x06bc -#define IMXRT_PADCTL_GPIO_SPI_B0_03_OFFSET 0x06c0 -#define IMXRT_PADCTL_GPIO_SPI_B0_04_OFFSET 0x06c4 -#define IMXRT_PADCTL_GPIO_SPI_B0_05_OFFSET 0x06c8 -#define IMXRT_PADCTL_GPIO_SPI_B0_06_OFFSET 0x06cc -#define IMXRT_PADCTL_GPIO_SPI_B0_07_OFFSET 0x06d0 -#define IMXRT_PADCTL_GPIO_SPI_B0_08_OFFSET 0x06d4 -#define IMXRT_PADCTL_GPIO_SPI_B0_09_OFFSET 0x06d8 -#define IMXRT_PADCTL_GPIO_SPI_B0_10_OFFSET 0x06dc -#define IMXRT_PADCTL_GPIO_SPI_B0_11_OFFSET 0x06e0 -#define IMXRT_PADCTL_GPIO_SPI_B0_12_OFFSET 0x06e4 -#define IMXRT_PADCTL_GPIO_SPI_B0_13_OFFSET 0x06e8 -#define IMXRT_PADCTL_GPIO_SPI_B1_00_OFFSET 0x06ec -#define IMXRT_PADCTL_GPIO_SPI_B1_01_OFFSET 0x06f0 -#define IMXRT_PADCTL_GPIO_SPI_B1_02_OFFSET 0x06f4 -#define IMXRT_PADCTL_GPIO_SPI_B1_03_OFFSET 0x06f8 -#define IMXRT_PADCTL_GPIO_SPI_B1_04_OFFSET 0x06fc -#define IMXRT_PADCTL_GPIO_SPI_B1_05_OFFSET 0x0700 -#define IMXRT_PADCTL_GPIO_SPI_B1_06_OFFSET 0x0704 -#define IMXRT_PADCTL_GPIO_SPI_B1_07_OFFSET 0x0708 - -/* Select Input Daisy Register Offsets */ - -#define IMXRT_INPUT_INDEX2OFFSET(n) (0x03f4 + ((unsigned int)(n) << 2)) -#define IMXRT_INPUT_OFFSET2INDEX(o) (((unsigned int)(o) - 0x03f4) >> 2) - -#define IMXRT_INPUT_ANATOP_USB_OTG1_ID_OFFSET 0x03f4 -#define IMXRT_INPUT_ANATOP_USB_OTG2_ID_OFFSET 0x03f8 -#define IMXRT_INPUT_CCM_PMIC_READY_OFFSET 0x03fc -#define IMXRT_INPUT_CSI_DATA02_OFFSET 0x0400 -#define IMXRT_INPUT_CSI_DATA03_OFFSET 0x0404 -#define IMXRT_INPUT_CSI_DATA04_OFFSET 0x0408 -#define IMXRT_INPUT_CSI_DATA05_OFFSET 0x040c -#define IMXRT_INPUT_CSI_DATA06_OFFSET 0x0410 -#define IMXRT_INPUT_CSI_DATA07_OFFSET 0x0414 -#define IMXRT_INPUT_CSI_DATA08_OFFSET 0x0418 -#define IMXRT_INPUT_CSI_DATA09_OFFSET 0x041c -#define IMXRT_INPUT_CSI_HSYNC_OFFSET 0x0420 -#define IMXRT_INPUT_CSI_PIXCLK_OFFSET 0x0424 -#define IMXRT_INPUT_CSI_VSYNC_OFFSET 0x0428 -#define IMXRT_INPUT_ENET_IPG_CLK_RMII_OFFSET 0x042c -#define IMXRT_INPUT_ENET_MDIO_OFFSET 0x0430 -#define IMXRT_INPUT_ENET0_RXDATA_OFFSET 0x0434 -#define IMXRT_INPUT_ENET1_RXDATA_OFFSET 0x0438 -#define IMXRT_INPUT_ENET_RXEN_OFFSET 0x043c -#define IMXRT_INPUT_ENET_RXERR_OFFSET 0x0440 -#define IMXRT_INPUT_ENET0_TIMER_OFFSET 0x0444 -#define IMXRT_INPUT_ENET_TXCLK_OFFSET 0x0448 -#define IMXRT_INPUT_FLEXCAN1_RX_OFFSET 0x044c -#define IMXRT_INPUT_FLEXCAN2_RX_OFFSET 0x0450 -#define IMXRT_INPUT_FLEXPWM1_PWMA3_OFFSET 0x0454 -#define IMXRT_INPUT_FLEXPWM1_PWMA0_OFFSET 0x0458 -#define IMXRT_INPUT_FLEXPWM1_PWMA1_OFFSET 0x045c -#define IMXRT_INPUT_FLEXPWM1_PWMA2_OFFSET 0x0460 -#define IMXRT_INPUT_FLEXPWM1_PWMB3_OFFSET 0x0464 -#define IMXRT_INPUT_FLEXPWM1_PWMB0_OFFSET 0x0468 -#define IMXRT_INPUT_FLEXPWM1_PWMB1_OFFSET 0x046c -#define IMXRT_INPUT_FLEXPWM1_PWMB2_OFFSET 0x0470 -#define IMXRT_INPUT_FLEXPWM2_PWMA3_OFFSET 0x0474 -#define IMXRT_INPUT_FLEXPWM2_PWMA0_OFFSET 0x0478 -#define IMXRT_INPUT_FLEXPWM2_PWMA1_OFFSET 0x047c -#define IMXRT_INPUT_FLEXPWM2_PWMA2_OFFSET 0x0480 -#define IMXRT_INPUT_FLEXPWM2_PWMB3_OFFSET 0x0484 -#define IMXRT_INPUT_FLEXPWM2_PWMB0_OFFSET 0x0488 -#define IMXRT_INPUT_FLEXPWM2_PWMB1_OFFSET 0x048c -#define IMXRT_INPUT_FLEXPWM2_PWMB2_OFFSET 0x0490 -#define IMXRT_INPUT_FLEXPWM4_PWMA0_OFFSET 0x0494 -#define IMXRT_INPUT_FLEXPWM4_PWMA1_OFFSET 0x0498 -#define IMXRT_INPUT_FLEXPWM4_PWMA2_OFFSET 0x049c -#define IMXRT_INPUT_FLEXPWM4_PWMA3_OFFSET 0x04a0 -#define IMXRT_INPUT_FLEXSPIA_DQS_OFFSET 0x04a4 -#define IMXRT_INPUT_FLEXSPIA_DATA0_OFFSET 0x04a8 -#define IMXRT_INPUT_FLEXSPIA_DATA1_OFFSET 0x04ac -#define IMXRT_INPUT_FLEXSPIA_DATA2_OFFSET 0x04b0 -#define IMXRT_INPUT_FLEXSPIA_DATA3_OFFSET 0x04b4 -#define IMXRT_INPUT_FLEXSPIB_DATA0_OFFSET 0x04b8 -#define IMXRT_INPUT_FLEXSPIB_DATA1_OFFSET 0x04bc -#define IMXRT_INPUT_FLEXSPIB_DATA2_OFFSET 0x04c0 -#define IMXRT_INPUT_FLEXSPIB_DATA3_OFFSET 0x04c4 -#define IMXRT_INPUT_FLEXSPIA_SCK_OFFSET 0x04c8 -#define IMXRT_INPUT_LPI2C1_SCL_OFFSET 0x04cc -#define IMXRT_INPUT_LPI2C1_SDA_OFFSET 0x04d0 -#define IMXRT_INPUT_LPI2C2_SCL_OFFSET 0x04d4 -#define IMXRT_INPUT_LPI2C2_SDA_OFFSET 0x04d8 -#define IMXRT_INPUT_LPI2C3_SCL_OFFSET 0x04dc -#define IMXRT_INPUT_LPI2C3_SDA_OFFSET 0x04e0 -#define IMXRT_INPUT_LPI2C4_SCL_OFFSET 0x04e4 -#define IMXRT_INPUT_LPI2C4_SDA_OFFSET 0x04e8 -#define IMXRT_INPUT_LPSPI1_PCS0_OFFSET 0x04ec -#define IMXRT_INPUT_LPSPI1_SCK_OFFSET 0x04f0 -#define IMXRT_INPUT_LPSPI1_SDI_OFFSET 0x04f4 -#define IMXRT_INPUT_LPSPI1_SDO_OFFSET 0x04f8 -#define IMXRT_INPUT_LPSPI2_PCS0_OFFSET 0x04fc -#define IMXRT_INPUT_LPSPI2_SCK_OFFSET 0x0500 -#define IMXRT_INPUT_LPSPI2_SDI_OFFSET 0x0504 -#define IMXRT_INPUT_LPSPI2_SDO_OFFSET 0x0508 -#define IMXRT_INPUT_LPSPI3_PCS0_OFFSET 0x050c -#define IMXRT_INPUT_LPSPI3_SCK_OFFSET 0x0510 -#define IMXRT_INPUT_LPSPI3_SDI_OFFSET 0x0514 -#define IMXRT_INPUT_LPSPI3_SDO_OFFSET 0x0518 -#define IMXRT_INPUT_LPSPI4_PCS0_OFFSET 0x051c -#define IMXRT_INPUT_LPSPI4_SCK_OFFSET 0x0520 -#define IMXRT_INPUT_LPSPI4_SDI_OFFSET 0x0524 -#define IMXRT_INPUT_LPSPI4_SDO_OFFSET 0x0528 -#define IMXRT_INPUT_LPUART2_RX_OFFSET 0x052c -#define IMXRT_INPUT_LPUART2_TX_OFFSET 0x0530 -#define IMXRT_INPUT_LPUART3_CTS_B_OFFSET 0x0534 -#define IMXRT_INPUT_LPUART3_RX_OFFSET 0x0538 -#define IMXRT_INPUT_LPUART3_TX_OFFSET 0x053c -#define IMXRT_INPUT_LPUART4_RX_OFFSET 0x0540 -#define IMXRT_INPUT_LPUART4_TX_OFFSET 0x0544 -#define IMXRT_INPUT_LPUART5_RX_OFFSET 0x0548 -#define IMXRT_INPUT_LPUART5_TX_OFFSET 0x054c -#define IMXRT_INPUT_LPUART6_RX_OFFSET 0x0550 -#define IMXRT_INPUT_LPUART6_TX_OFFSET 0x0554 -#define IMXRT_INPUT_LPUART7_RX_OFFSET 0x0558 -#define IMXRT_INPUT_LPUART7_TX_OFFSET 0x055c -#define IMXRT_INPUT_LPUART8_RX_OFFSET 0x0560 -#define IMXRT_INPUT_LPUART8_TX_OFFSET 0x0564 -#define IMXRT_INPUT_NMI_GLUE_NMI_OFFSET 0x0568 -#define IMXRT_INPUT_QTIMER2_TIMER0_OFFSET 0x056c -#define IMXRT_INPUT_QTIMER2_TIMER1_OFFSET 0x0570 -#define IMXRT_INPUT_QTIMER2_TIMER2_OFFSET 0x0574 -#define IMXRT_INPUT_QTIMER2_TIMER3_OFFSET 0x0578 -#define IMXRT_INPUT_QTIMER3_TIMER0_OFFSET 0x057c -#define IMXRT_INPUT_QTIMER3_TIMER1_OFFSET 0x0580 -#define IMXRT_INPUT_QTIMER3_TIMER2_OFFSET 0x0584 -#define IMXRT_INPUT_QTIMER3_TIMER3_OFFSET 0x0588 -#define IMXRT_INPUT_SAI1_MCLK2_OFFSET 0x058c -#define IMXRT_INPUT_SAI1_RX_BCLK_OFFSET 0x0590 -#define IMXRT_INPUT_SAI1_RX_DATA0_OFFSET 0x0594 -#define IMXRT_INPUT_SAI1_RX_DATA1_OFFSET 0x0598 -#define IMXRT_INPUT_SAI1_RX_DATA2_OFFSET 0x059c -#define IMXRT_INPUT_SAI1_RX_DATA3_OFFSET 0x05a0 -#define IMXRT_INPUT_SAI1_RX_SYNC_OFFSET 0x05a4 -#define IMXRT_INPUT_SAI1_TX_BCLK_OFFSET 0x05a8 -#define IMXRT_INPUT_SAI1_TX_SYNC_OFFSET 0x05ac -#define IMXRT_INPUT_SAI2_MCLK2_OFFSET 0x05b0 -#define IMXRT_INPUT_SAI2_RX_BCLK_OFFSET 0x05b4 -#define IMXRT_INPUT_SAI2_RX_DATA0_OFFSET 0x05b8 -#define IMXRT_INPUT_SAI2_RX_SYNC_OFFSET 0x05bc -#define IMXRT_INPUT_SAI2_TX_BCLK_OFFSET 0x05c0 -#define IMXRT_INPUT_SAI2_TX_SYNC_OFFSET 0x05c4 -#define IMXRT_INPUT_SPDIF_IN_OFFSET 0x05c8 -#define IMXRT_INPUT_USB_OTG2_OC_OFFSET 0x05cc -#define IMXRT_INPUT_USB_OTG1_OC_OFFSET 0x05d0 -#define IMXRT_INPUT_USDHC1_CD_B_OFFSET 0x05d4 -#define IMXRT_INPUT_USDHC1_WP_OFFSET 0x05d8 -#define IMXRT_INPUT_USDHC2_CLK_OFFSET 0x05dc -#define IMXRT_INPUT_USDHC2_CD_B_OFFSET 0x05e0 -#define IMXRT_INPUT_USDHC2_CMD_OFFSET 0x05e4 -#define IMXRT_INPUT_USDHC2_DATA0_OFFSET 0x05e8 -#define IMXRT_INPUT_USDHC2_DATA1_OFFSET 0x05ec -#define IMXRT_INPUT_USDHC2_DATA2_OFFSET 0x05f0 -#define IMXRT_INPUT_USDHC2_DATA3_OFFSET 0x05f4 -#define IMXRT_INPUT_USDHC2_DATA4_OFFSET 0x05f8 -#define IMXRT_INPUT_USDHC2_DATA5_OFFSET 0x05fc -#define IMXRT_INPUT_USDHC2_DATA6_OFFSET 0x0600 -#define IMXRT_INPUT_USDHC2_DATA7_OFFSET 0x0604 -#define IMXRT_INPUT_USDHC2_WP_OFFSET 0x0608 -#define IMXRT_INPUT_XBAR1_IN02_OFFSET 0x060c -#define IMXRT_INPUT_XBAR1_IN03_OFFSET 0x0610 -#define IMXRT_INPUT_XBAR1_IN04_OFFSET 0x0614 -#define IMXRT_INPUT_XBAR1_IN05_OFFSET 0x0618 -#define IMXRT_INPUT_XBAR1_IN06_OFFSET 0x061c -#define IMXRT_INPUT_XBAR1_IN07_OFFSET 0x0620 -#define IMXRT_INPUT_XBAR1_IN08_OFFSET 0x0624 -#define IMXRT_INPUT_XBAR1_IN09_OFFSET 0x0628 -#define IMXRT_INPUT_XBAR1_IN17_OFFSET 0x062c -#define IMXRT_INPUT_XBAR1_IN18_OFFSET 0x0630 -#define IMXRT_INPUT_XBAR1_IN20_OFFSET 0x0634 -#define IMXRT_INPUT_XBAR1_IN22_OFFSET 0x0638 -#define IMXRT_INPUT_XBAR1_IN23_OFFSET 0x063c -#define IMXRT_INPUT_XBAR1_IN24_OFFSET 0x0640 -#define IMXRT_INPUT_XBAR1_IN14_OFFSET 0x0644 -#define IMXRT_INPUT_XBAR1_IN15_OFFSET 0x0648 -#define IMXRT_INPUT_XBAR1_IN16_OFFSET 0x064c -#define IMXRT_INPUT_XBAR1_IN25_OFFSET 0x0650 -#define IMXRT_INPUT_XBAR1_IN19_OFFSET 0x0654 -#define IMXRT_INPUT_XBAR1_IN21_OFFSET 0x0658 - -/* Select1 Input Daisy Register Offsets */ - -#define IMXRT_INPUT_ENET2_IPG_CLK_RMII_OFFSET 0x070C -#define IMXRT_INPUT_ENET2_IPP_IND_MAC0_MDIO_OFFSET 0x0710 -#define IMXRT_INPUT_ENET2_IPP_IND_MAC0_RXDATA_0_OFFSET 0x0714 -#define IMXRT_INPUT_ENET2_IPP_IND_MAC0_RXDATA_1_OFFSET 0x0718 -#define IMXRT_INPUT_ENET2_IPP_IND_MAC0_RXEN_OFFSET 0x071C -#define IMXRT_INPUT_ENET2_IPP_IND_MAC0_RXERR_OFFSET 0x0720 -#define IMXRT_INPUT_ENET2_IPP_IND_MAC0_TIMER_0_OFFSET 0x0724 -#define IMXRT_INPUT_ENET2_IPP_IND_MAC0_TXCLK_OFFSET 0x0728 -#define IMXRT_INPUT_FLEXSPI2_IPP_IND_DQS_FA_OFFSET 0x072C -#define IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FA_BIT0_OFFSET 0x0730 -#define IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FA_BIT1_OFFSET 0x0734 -#define IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FA_BIT2_OFFSET 0x0738 -#define IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FA_BIT3_OFFSET 0x073C -#define IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FB_BIT0_OFFSET 0x0740 -#define IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FB_BIT1_OFFSET 0x0744 -#define IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FB_BIT2_OFFSET 0x0748 -#define IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FB_BIT3_OFFSET 0x074C -#define IMXRT_INPUT_FLEXSPI2_IPP_IND_SCK_FA_OFFSET 0x0750 -#define IMXRT_INPUT_FLEXSPI2_IPP_IND_SCK_FB_OFFSET 0x0754 -#define IMXRT_INPUT_GPT1_IPP_IND_CAPIN1_OFFSET 0x0758 -#define IMXRT_INPUT_GPT1_IPP_IND_CAPIN2_OFFSET 0x075C -#define IMXRT_INPUT_GPT1_IPP_IND_CLKIN_OFFSET 0x0760 -#define IMXRT_INPUT_GPT2_IPP_IND_CAPIN1_OFFSET 0x0764 -#define IMXRT_INPUT_GPT2_IPP_IND_CAPIN2_OFFSET 0x0768 -#define IMXRT_INPUT_GPT2_IPP_IND_CLKIN_OFFSET 0x076C -#define IMXRT_INPUT_SAI3_IPG_CLK_SAI_MCLK_2_OFFSET 0x0770 -#define IMXRT_INPUT_SAI3_IPP_IND_SAI_RXBCLK_OFFSET 0x0774 -#define IMXRT_INPUT_SAI3_IPP_IND_SAI_RXDATA_0_OFFSET 0x0778 -#define IMXRT_INPUT_SAI3_IPP_IND_SAI_RXSYNC_OFFSET 0x077C -#define IMXRT_INPUT_SAI3_IPP_IND_SAI_TXBCLK_OFFSET 0x0780 -#define IMXRT_INPUT_SAI3_IPP_IND_SAI_TXSYNC_OFFSET 0x0784 -#define IMXRT_INPUT_SEMC_I_IPP_IND_DQS4_OFFSET 0x0788 -#define IMXRT_INPUT_CANFD_IPP_IND_CANRX_OFFSET 0x078C - -/* Register addresses ***************************************************************/ - -#define IMXRT_IOMUXC_GPR_GPR0 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR0_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR1 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR1_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR2 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR2_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR3 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR3_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR4 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR4_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR5 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR5_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR6 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR6_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR7 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR7_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR8 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR8_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR9 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR9_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR10 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR10_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR11 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR11_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR12 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR12_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR13 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR13_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR14 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR14_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR15 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR15_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR16 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR16_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR17 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR17_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR18 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR18_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR19 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR19_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR20 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR20_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR21 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR21_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR22 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR22_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR23 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR23_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR24 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR24_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR25 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR25_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR26 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR26_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR27 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR27_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR28 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR28_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR29 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR29_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR30 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR30_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR31 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR31_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR32 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR32_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR33 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR33_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR34 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR34_OFFSET) - -#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_OFFSET) -#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_OFFSET) -#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_OFFSET) -#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_OFFSET) -#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_OFFSET) -#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_OFFSET) -#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_OFFSET) -#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_OFFSET) -#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_OFFSET) - -#define IMXRT_IOMUXC_SNVS_GPR_GPR0 (IMXRT_IOMUXCSNVSGPR_BASE + IMXRT_IOMUXC_SNVS_GPR_GPR0_OFFSET) -#define IMXRT_IOMUXC_SNVS_GPR_GPR1 (IMXRT_IOMUXCSNVSGPR_BASE + IMXRT_IOMUXC_SNVS_GPR_GPR1_OFFSET) -#define IMXRT_IOMUXC_SNVS_GPR_GPR2 (IMXRT_IOMUXCSNVSGPR_BASE + IMXRT_IOMUXC_SNVS_GPR_GPR2_OFFSET) -#define IMXRT_IOMUXC_SNVS_GPR_GPR3 (IMXRT_IOMUXCSNVSGPR_BASE + IMXRT_IOMUXC_SNVS_GPR_GPR3_OFFSET) - -/* Pad Mux Registers */ - -#define IMXRT_PADMUX_ADDRESS(n) (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_OFFSET(n)) -#define IMXRT_PADMUX_ADDRESS_SNVS(n) (IMXRT_IOMUXCSNVS_BASE + IMXRT_PADMUX_OFFSET_SNVS(n)) - -#define IMXRT_PADMUX_GPIO_EMC_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_00_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_01_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_02_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_03_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_04_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_05_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_06_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_07 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_07_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_08 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_08_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_09 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_09_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_10 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_10_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_11 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_11_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_12 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_12_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_13 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_13_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_14 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_14_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_15 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_15_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_16 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_16_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_17 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_17_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_18 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_18_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_19 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_19_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_20 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_20_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_21 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_21_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_22 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_22_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_23 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_23_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_24 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_24_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_25 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_25_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_26 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_26_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_27 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_27_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_28 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_28_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_29 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_29_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_30 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_30_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_31 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_31_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_32 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_32_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_33 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_33_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_34 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_34_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_35 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_35_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_36 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_36_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_37 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_37_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_38 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_38_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_39 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_39_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_40 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_40_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_41 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_41_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_00_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_01_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_02_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_03_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_04_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_05_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_06_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_07 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_07_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_08 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_08_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_09 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_09_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_10 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_10_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_11 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_11_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_12 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_12_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_13 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_13_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_14 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_14_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_15 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_15_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_00_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_01_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_02_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_03_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_04_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_05_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_06_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_07 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_07_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_08 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_08_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_09 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_09_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_10 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_10_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_11 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_11_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_12 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_12_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_13 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_13_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_14 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_14_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_15 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_15_OFFSET) -#define IMXRT_PADMUX_GPIO_B0_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_00_OFFSET) -#define IMXRT_PADMUX_GPIO_B0_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_01_OFFSET) -#define IMXRT_PADMUX_GPIO_B0_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_02_OFFSET) -#define IMXRT_PADMUX_GPIO_B0_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_03_OFFSET) -#define IMXRT_PADMUX_GPIO_B0_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_04_OFFSET) -#define IMXRT_PADMUX_GPIO_B0_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_05_OFFSET) -#define IMXRT_PADMUX_GPIO_B0_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_06_OFFSET) -#define IMXRT_PADMUX_GPIO_B0_07 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_07_OFFSET) -#define IMXRT_PADMUX_GPIO_B0_08 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_08_OFFSET) -#define IMXRT_PADMUX_GPIO_B0_09 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_09_OFFSET) -#define IMXRT_PADMUX_GPIO_B0_10 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_10_OFFSET) -#define IMXRT_PADMUX_GPIO_B0_11 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_11_OFFSET) -#define IMXRT_PADMUX_GPIO_B0_12 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_12_OFFSET) -#define IMXRT_PADMUX_GPIO_B0_13 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_13_OFFSET) -#define IMXRT_PADMUX_GPIO_B0_14 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_14_OFFSET) -#define IMXRT_PADMUX_GPIO_B0_15 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_15_OFFSET) -#define IMXRT_PADMUX_GPIO_B1_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_00_OFFSET) -#define IMXRT_PADMUX_GPIO_B1_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_01_OFFSET) -#define IMXRT_PADMUX_GPIO_B1_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_02_OFFSET) -#define IMXRT_PADMUX_GPIO_B1_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_03_OFFSET) -#define IMXRT_PADMUX_GPIO_B1_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_04_OFFSET) -#define IMXRT_PADMUX_GPIO_B1_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_05_OFFSET) -#define IMXRT_PADMUX_GPIO_B1_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_06_OFFSET) -#define IMXRT_PADMUX_GPIO_B1_07 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_07_OFFSET) -#define IMXRT_PADMUX_GPIO_B1_08 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_08_OFFSET) -#define IMXRT_PADMUX_GPIO_B1_09 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_09_OFFSET) -#define IMXRT_PADMUX_GPIO_B1_10 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_10_OFFSET) -#define IMXRT_PADMUX_GPIO_B1_11 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_11_OFFSET) -#define IMXRT_PADMUX_GPIO_B1_12 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_12_OFFSET) -#define IMXRT_PADMUX_GPIO_B1_13 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_13_OFFSET) -#define IMXRT_PADMUX_GPIO_B1_14 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_14_OFFSET) -#define IMXRT_PADMUX_GPIO_B1_15 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_15_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B0_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_00_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B0_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_01_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B0_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_02_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B0_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_03_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B0_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_04_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B0_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_05_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B1_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_00_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B1_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_01_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B1_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_02_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B1_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_03_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B1_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_04_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B1_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_05_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B1_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_06_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B1_07 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_07_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B1_08 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_08_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B1_09 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_09_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B1_10 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_10_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B1_11 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_11_OFFSET) - -/* Pad1 Mux Registers */ - -#define IMXRT_PAD1MUX_ADDRESS(n) (IMXRT_IOMUXC_BASE + IMXRT_PAD1MUX_OFFSET(n)) - -#define IMXRT_PADMUX_GPIO_SPI_B0_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SPI_B0_00_OFFSET) -#define IMXRT_PADMUX_GPIO_SPI_B0_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SPI_B0_01_OFFSET) -#define IMXRT_PADMUX_GPIO_SPI_B0_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SPI_B0_02_OFFSET) -#define IMXRT_PADMUX_GPIO_SPI_B0_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SPI_B0_03_OFFSET) -#define IMXRT_PADMUX_GPIO_SPI_B0_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SPI_B0_04_OFFSET) -#define IMXRT_PADMUX_GPIO_SPI_B0_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SPI_B0_05_OFFSET) -#define IMXRT_PADMUX_GPIO_SPI_B0_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SPI_B0_06_OFFSET) -#define IMXRT_PADMUX_GPIO_SPI_B0_07 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SPI_B0_07_OFFSET) -#define IMXRT_PADMUX_GPIO_SPI_B0_08 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SPI_B0_08_OFFSET) -#define IMXRT_PADMUX_GPIO_SPI_B0_09 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SPI_B0_09_OFFSET) -#define IMXRT_PADMUX_GPIO_SPI_B0_10 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SPI_B0_10_OFFSET) -#define IMXRT_PADMUX_GPIO_SPI_B0_11 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SPI_B0_11_OFFSET) -#define IMXRT_PADMUX_GPIO_SPI_B0_12 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SPI_B0_12_OFFSET) -#define IMXRT_PADMUX_GPIO_SPI_B0_13 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SPI_B0_13_OFFSET) -#define IMXRT_PADMUX_GPIO_SPI_B1_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SPI_B1_00_OFFSET) -#define IMXRT_PADMUX_GPIO_SPI_B1_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SPI_B1_01_OFFSET) -#define IMXRT_PADMUX_GPIO_SPI_B1_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SPI_B1_02_OFFSET) -#define IMXRT_PADMUX_GPIO_SPI_B1_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SPI_B1_03_OFFSET) -#define IMXRT_PADMUX_GPIO_SPI_B1_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SPI_B1_04_OFFSET) -#define IMXRT_PADMUX_GPIO_SPI_B1_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SPI_B1_05_OFFSET) -#define IMXRT_PADMUX_GPIO_SPI_B1_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SPI_B1_06_OFFSET) -#define IMXRT_PADMUX_GPIO_SPI_B1_07 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SPI_B1_07_OFFSET) - -/* Pad Control Registers */ - -#define IMXRT_PADCTL_ADDRESS(n) (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_OFFSET(n)) -#define IMXRT_PADCTL_ADDRESS_SNVS(n) (IMXRT_IOMUXCSNVS_BASE + IMXRT_PADCTL_OFFSET_SNVS(n)) - -#define IMXRT_PADCTL_GPIO_EMC_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_00_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_01_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_02_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_03_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_04_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_05_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_06_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_07 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_07_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_08 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_08_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_09 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_09_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_10 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_10_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_11 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_11_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_12 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_12_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_13 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_13_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_14 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_14_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_15 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_15_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_16 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_16_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_17 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_17_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_18 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_18_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_19 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_19_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_20 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_20_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_21 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_21_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_22 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_22_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_23 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_23_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_24 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_24_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_25 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_25_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_26 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_26_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_27 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_27_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_28 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_28_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_29 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_29_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_30 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_30_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_31 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_31_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_32 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_32_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_33 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_33_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_34 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_34_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_35 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_35_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_36 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_36_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_37 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_37_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_38 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_38_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_39 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_39_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_40 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_40_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_41 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_41_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_00_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_01_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_02_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_03_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_04_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_05_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_06_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_07 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_07_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_08 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_08_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_09 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_09_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_10 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_10_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_11 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_11_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_12 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_12_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_13 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_13_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_14 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_14_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_15 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_15_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_00_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_01_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_02_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_03_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_04_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_05_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_06_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_07 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_07_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_08 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_08_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_09 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_09_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_10 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_10_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_11 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_11_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_12 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_12_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_13 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_13_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_14 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_14_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_15 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_15_OFFSET) -#define IMXRT_PADCTL_GPIO_B0_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_00_OFFSET) -#define IMXRT_PADCTL_GPIO_B0_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_01_OFFSET) -#define IMXRT_PADCTL_GPIO_B0_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_02_OFFSET) -#define IMXRT_PADCTL_GPIO_B0_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_03_OFFSET) -#define IMXRT_PADCTL_GPIO_B0_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_04_OFFSET) -#define IMXRT_PADCTL_GPIO_B0_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_05_OFFSET) -#define IMXRT_PADCTL_GPIO_B0_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_06_OFFSET) -#define IMXRT_PADCTL_GPIO_B0_07 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_07_OFFSET) -#define IMXRT_PADCTL_GPIO_B0_08 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_08_OFFSET) -#define IMXRT_PADCTL_GPIO_B0_09 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_09_OFFSET) -#define IMXRT_PADCTL_GPIO_B0_10 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_10_OFFSET) -#define IMXRT_PADCTL_GPIO_B0_11 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_11_OFFSET) -#define IMXRT_PADCTL_GPIO_B0_12 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_12_OFFSET) -#define IMXRT_PADCTL_GPIO_B0_13 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_13_OFFSET) -#define IMXRT_PADCTL_GPIO_B0_14 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_14_OFFSET) -#define IMXRT_PADCTL_GPIO_B0_15 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_15_OFFSET) -#define IMXRT_PADCTL_GPIO_B1_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_00_OFFSET) -#define IMXRT_PADCTL_GPIO_B1_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_01_OFFSET) -#define IMXRT_PADCTL_GPIO_B1_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_02_OFFSET) -#define IMXRT_PADCTL_GPIO_B1_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_03_OFFSET) -#define IMXRT_PADCTL_GPIO_B1_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_04_OFFSET) -#define IMXRT_PADCTL_GPIO_B1_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_05_OFFSET) -#define IMXRT_PADCTL_GPIO_B1_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_06_OFFSET) -#define IMXRT_PADCTL_GPIO_B1_07 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_07_OFFSET) -#define IMXRT_PADCTL_GPIO_B1_08 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_08_OFFSET) -#define IMXRT_PADCTL_GPIO_B1_09 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_09_OFFSET) -#define IMXRT_PADCTL_GPIO_B1_10 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_10_OFFSET) -#define IMXRT_PADCTL_GPIO_B1_11 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_11_OFFSET) -#define IMXRT_PADCTL_GPIO_B1_12 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_12_OFFSET) -#define IMXRT_PADCTL_GPIO_B1_13 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_13_OFFSET) -#define IMXRT_PADCTL_GPIO_B1_14 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_14_OFFSET) -#define IMXRT_PADCTL_GPIO_B1_15 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_15_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B0_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_00_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B0_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_01_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B0_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_02_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B0_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_03_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B0_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_04_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B0_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_05_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B1_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_00_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B1_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_01_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B1_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_02_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B1_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_03_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B1_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_04_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B1_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_05_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B1_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_06_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B1_07 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_07_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B1_08 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_08_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B1_09 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_09_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B1_10 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_10_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B1_11 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_11_OFFSET) - -/* Pad1 Control Registers */ - -#define IMXRT_PAD1CTL_ADDRESS(n) (IMXRT_IOMUXC_BASE + IMXRT_PAD1CTL_OFFSET(n)) - -#define IMXRT_PADCTL_GPIO_SPI_B0_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SPI_B0_00_OFFSET) -#define IMXRT_PADCTL_GPIO_SPI_B0_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SPI_B0_01_OFFSET) -#define IMXRT_PADCTL_GPIO_SPI_B0_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SPI_B0_02_OFFSET) -#define IMXRT_PADCTL_GPIO_SPI_B0_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SPI_B0_03_OFFSET) -#define IMXRT_PADCTL_GPIO_SPI_B0_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SPI_B0_04_OFFSET) -#define IMXRT_PADCTL_GPIO_SPI_B0_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SPI_B0_05_OFFSET) -#define IMXRT_PADCTL_GPIO_SPI_B0_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SPI_B0_06_OFFSET) -#define IMXRT_PADCTL_GPIO_SPI_B0_07 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SPI_B0_07_OFFSET) -#define IMXRT_PADCTL_GPIO_SPI_B0_08 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SPI_B0_08_OFFSET) -#define IMXRT_PADCTL_GPIO_SPI_B0_09 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SPI_B0_09_OFFSET) -#define IMXRT_PADCTL_GPIO_SPI_B0_10 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SPI_B0_10_OFFSET) -#define IMXRT_PADCTL_GPIO_SPI_B0_11 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SPI_B0_11_OFFSET) -#define IMXRT_PADCTL_GPIO_SPI_B0_12 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SPI_B0_12_OFFSET) -#define IMXRT_PADCTL_GPIO_SPI_B0_13 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SPI_B0_13_OFFSET) -#define IMXRT_PADCTL_GPIO_SPI_B1_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SPI_B1_00_OFFSET) -#define IMXRT_PADCTL_GPIO_SPI_B1_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SPI_B1_01_OFFSET) -#define IMXRT_PADCTL_GPIO_SPI_B1_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SPI_B1_02_OFFSET) -#define IMXRT_PADCTL_GPIO_SPI_B1_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SPI_B1_03_OFFSET) -#define IMXRT_PADCTL_GPIO_SPI_B1_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SPI_B1_04_OFFSET) -#define IMXRT_PADCTL_GPIO_SPI_B1_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SPI_B1_05_OFFSET) -#define IMXRT_PADCTL_GPIO_SPI_B1_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SPI_B1_06_OFFSET) -#define IMXRT_PADCTL_GPIO_SPI_B1_07 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SPI_B1_07_OFFSET) - -/* Select Input Registers */ - -#define IMXRT_INPUT_ANATOP_USB_OTG1_ID (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ANATOP_USB_OTG1_ID_OFFSET) -#define IMXRT_INPUT_ANATOP_USB_OTG2_ID (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ANATOP_USB_OTG2_ID_OFFSET) -#define IMXRT_INPUT_CCM_PMIC_READY (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CCM_PMIC_READY_OFFSET) -#define IMXRT_INPUT_CSI_DATA02 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_DATA02_OFFSET) -#define IMXRT_INPUT_CSI_DATA03 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_DATA03_OFFSET) -#define IMXRT_INPUT_CSI_DATA04 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_DATA04_OFFSET) -#define IMXRT_INPUT_CSI_DATA05 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_DATA05_OFFSET) -#define IMXRT_INPUT_CSI_DATA06 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_DATA06_OFFSET) -#define IMXRT_INPUT_CSI_DATA07 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_DATA07_OFFSET) -#define IMXRT_INPUT_CSI_DATA08 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_DATA08_OFFSET) -#define IMXRT_INPUT_CSI_DATA09 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_DATA09_OFFSET) -#define IMXRT_INPUT_CSI_HSYNC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_HSYNC_OFFSET) -#define IMXRT_INPUT_CSI_PIXCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_PIXCLK_OFFSET) -#define IMXRT_INPUT_CSI_VSYNC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_VSYNC_OFFSET) -#define IMXRT_INPUT_ENET_IPG_CLK_RMII (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET_IPG_CLK_RMII_OFFSET) -#define IMXRT_INPUT_ENET_MDIO (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET_MDIO_OFFSET) -#define IMXRT_INPUT_ENET0_RXDATA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET0_RXDATA_OFFSET) -#define IMXRT_INPUT_ENET1_RXDATA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET1_RXDATA_OFFSET) -#define IMXRT_INPUT_ENET_RXEN (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET_RXEN_OFFSET) -#define IMXRT_INPUT_ENET_RXERR (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET_RXERR_OFFSET) -#define IMXRT_INPUT_ENET0_TIMER (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET0_TIMER_OFFSET) -#define IMXRT_INPUT_ENET_TXCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET_TXCLK_OFFSET) -#define IMXRT_INPUT_FLEXCAN1_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXCAN1_RX_OFFSET) -#define IMXRT_INPUT_FLEXCAN2_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXCAN2_RX_OFFSET) -#define IMXRT_INPUT_FLEXPWM1_PWMA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMA3_OFFSET) -#define IMXRT_INPUT_FLEXPWM1_PWMA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMA0_OFFSET) -#define IMXRT_INPUT_FLEXPWM1_PWMA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMA1_OFFSET) -#define IMXRT_INPUT_FLEXPWM1_PWMA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMA2_OFFSET) -#define IMXRT_INPUT_FLEXPWM1_PWMB3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMB3_OFFSET) -#define IMXRT_INPUT_FLEXPWM1_PWMB0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMB0_OFFSET) -#define IMXRT_INPUT_FLEXPWM1_PWMB1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMB1_OFFSET) -#define IMXRT_INPUT_FLEXPWM1_PWMB2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMB2_OFFSET) -#define IMXRT_INPUT_FLEXPWM2_PWMA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMA3_OFFSET) -#define IMXRT_INPUT_FLEXPWM2_PWMA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMA0_OFFSET) -#define IMXRT_INPUT_FLEXPWM2_PWMA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMA1_OFFSET) -#define IMXRT_INPUT_FLEXPWM2_PWMA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMA2_OFFSET) -#define IMXRT_INPUT_FLEXPWM2_PWMB3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMB3_OFFSET) -#define IMXRT_INPUT_FLEXPWM2_PWMB0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMB0_OFFSET) -#define IMXRT_INPUT_FLEXPWM2_PWMB1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMB1_OFFSET) -#define IMXRT_INPUT_FLEXPWM2_PWMB2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMB2_OFFSET) -#define IMXRT_INPUT_FLEXPWM4_PWMA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM4_PWMA0_OFFSET) -#define IMXRT_INPUT_FLEXPWM4_PWMA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM4_PWMA1_OFFSET) -#define IMXRT_INPUT_FLEXPWM4_PWMA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM4_PWMA2_OFFSET) -#define IMXRT_INPUT_FLEXPWM4_PWMA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM4_PWMA3_OFFSET) -#define IMXRT_INPUT_FLEXSPIA_DQS (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_DQS_OFFSET) -#define IMXRT_INPUT_FLEXSPIA_DATA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_DATA0_OFFSET) -#define IMXRT_INPUT_FLEXSPIA_DATA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_DATA1_OFFSET) -#define IMXRT_INPUT_FLEXSPIA_DATA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_DATA2_OFFSET) -#define IMXRT_INPUT_FLEXSPIA_DATA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_DATA3_OFFSET) -#define IMXRT_INPUT_FLEXSPIB_DATA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIB_DATA0_OFFSET) -#define IMXRT_INPUT_FLEXSPIB_DATA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIB_DATA1_OFFSET) -#define IMXRT_INPUT_FLEXSPIB_DATA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIB_DATA2_OFFSET) -#define IMXRT_INPUT_FLEXSPIB_DATA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIB_DATA3_OFFSET) -#define IMXRT_INPUT_FLEXSPIA_SCK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_SCK_OFFSET) -#define IMXRT_INPUT_LPI2C1_SCL (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C1_SCL_OFFSET) -#define IMXRT_INPUT_LPI2C1_SDA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C1_SDA_OFFSET) -#define IMXRT_INPUT_LPI2C2_SCL (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C2_SCL_OFFSET) -#define IMXRT_INPUT_LPI2C2_SDA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C2_SDA_OFFSET) -#define IMXRT_INPUT_LPI2C3_SCL (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C3_SCL_OFFSET) -#define IMXRT_INPUT_LPI2C3_SDA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C3_SDA_OFFSET) -#define IMXRT_INPUT_LPI2C4_SCL (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C4_SCL_OFFSET) -#define IMXRT_INPUT_LPI2C4_SDA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C4_SDA_OFFSET) -#define IMXRT_INPUT_LPSPI1_PCS0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI1_PCS0_OFFSET) -#define IMXRT_INPUT_LPSPI1_SCK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI1_SCK_OFFSET) -#define IMXRT_INPUT_LPSPI1_SDI (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI1_SDI_OFFSET) -#define IMXRT_INPUT_LPSPI1_SDO (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI1_SDO_OFFSET) -#define IMXRT_INPUT_LPSPI2_PCS0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI2_PCS0_OFFSET) -#define IMXRT_INPUT_LPSPI2_SCK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI2_SCK_OFFSET) -#define IMXRT_INPUT_LPSPI2_SDI (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI2_SDI_OFFSET) -#define IMXRT_INPUT_LPSPI2_SDO (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI2_SDO_OFFSET) -#define IMXRT_INPUT_LPSPI3_PCS0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI3_PCS0_OFFSET) -#define IMXRT_INPUT_LPSPI3_SCK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI3_SCK_OFFSET) -#define IMXRT_INPUT_LPSPI3_SDI (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI3_SDI_OFFSET) -#define IMXRT_INPUT_LPSPI3_SDO (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI3_SDO_OFFSET) -#define IMXRT_INPUT_LPSPI4_PCS0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI4_PCS0_OFFSET) -#define IMXRT_INPUT_LPSPI4_SCK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI4_SCK_OFFSET) -#define IMXRT_INPUT_LPSPI4_SDI (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI4_SDI_OFFSET) -#define IMXRT_INPUT_LPSPI4_SDO (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI4_SDO_OFFSET) -#define IMXRT_INPUT_LPUART2_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART2_RX_OFFSET) -#define IMXRT_INPUT_LPUART2_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART2_TX_OFFSET) -#define IMXRT_INPUT_LPUART3_CTS_B (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART3_CTS_B_OFFSET) -#define IMXRT_INPUT_LPUART3_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART3_RX_OFFSET) -#define IMXRT_INPUT_LPUART3_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART3_TX_OFFSET) -#define IMXRT_INPUT_LPUART4_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART4_RX_OFFSET) -#define IMXRT_INPUT_LPUART4_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART4_TX_OFFSET) -#define IMXRT_INPUT_LPUART5_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART5_RX_OFFSET) -#define IMXRT_INPUT_LPUART5_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART5_TX_OFFSET) -#define IMXRT_INPUT_LPUART6_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART6_RX_OFFSET) -#define IMXRT_INPUT_LPUART6_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART6_TX_OFFSET) -#define IMXRT_INPUT_LPUART7_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART7_RX_OFFSET) -#define IMXRT_INPUT_LPUART7_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART7_TX_OFFSET) -#define IMXRT_INPUT_LPUART8_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART8_RX_OFFSET) -#define IMXRT_INPUT_LPUART8_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART8_TX_OFFSET) -#define IMXRT_INPUT_NMI_GLUE_NMI (IMXRT_IOMUXC_BASE + IMXRT_INPUT_NMI_GLUE_NMI_OFFSET) -#define IMXRT_INPUT_QTIMER2_TIMER0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER2_TIMER0_OFFSET) -#define IMXRT_INPUT_QTIMER2_TIMER1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER2_TIMER1_OFFSET) -#define IMXRT_INPUT_QTIMER2_TIMER2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER2_TIMER2_OFFSET) -#define IMXRT_INPUT_QTIMER2_TIMER3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER2_TIMER3_OFFSET) -#define IMXRT_INPUT_QTIMER3_TIMER0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER3_TIMER0_OFFSET) -#define IMXRT_INPUT_QTIMER3_TIMER1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER3_TIMER1_OFFSET) -#define IMXRT_INPUT_QTIMER3_TIMER2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER3_TIMER2_OFFSET) -#define IMXRT_INPUT_QTIMER3_TIMER3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER3_TIMER3_OFFSET) -#define IMXRT_INPUT_SAI1_MCLK2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_MCLK2_OFFSET) -#define IMXRT_INPUT_SAI1_RX_BCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_BCLK_OFFSET) -#define IMXRT_INPUT_SAI1_RX_DATA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_DATA0_OFFSET) -#define IMXRT_INPUT_SAI1_RX_DATA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_DATA1_OFFSET) -#define IMXRT_INPUT_SAI1_RX_DATA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_DATA2_OFFSET) -#define IMXRT_INPUT_SAI1_RX_DATA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_DATA3_OFFSET) -#define IMXRT_INPUT_SAI1_RX_SYNC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_SYNC_OFFSET) -#define IMXRT_INPUT_SAI1_TX_BCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_TX_BCLK_OFFSET) -#define IMXRT_INPUT_SAI1_TX_SYNC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_TX_SYNC_OFFSET) -#define IMXRT_INPUT_SAI2_MCLK2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_MCLK2_OFFSET) -#define IMXRT_INPUT_SAI2_RX_BCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_RX_BCLK_OFFSET) -#define IMXRT_INPUT_SAI2_RX_DATA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_RX_DATA0_OFFSET) -#define IMXRT_INPUT_SAI2_RX_SYNC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_RX_SYNC_OFFSET) -#define IMXRT_INPUT_SAI2_TX_BCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_TX_BCLK_OFFSET) -#define IMXRT_INPUT_SAI2_TX_SYNC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_TX_SYNC_OFFSET) -#define IMXRT_INPUT_SPDIF_IN (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SPDIF_IN_OFFSET) -#define IMXRT_INPUT_USB_OTG2_OC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USB_OTG2_OC_OFFSET) -#define IMXRT_INPUT_USB_OTG1_OC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USB_OTG1_OC_OFFSET) -#define IMXRT_INPUT_USDHC1_CD_B (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC1_CD_B_OFFSET) -#define IMXRT_INPUT_USDHC1_WP (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC1_WP_OFFSET) -#define IMXRT_INPUT_USDHC2_CLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_CLK_OFFSET) -#define IMXRT_INPUT_USDHC2_CD_B (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_CD_B_OFFSET) -#define IMXRT_INPUT_USDHC2_CMD (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_CMD_OFFSET) -#define IMXRT_INPUT_USDHC2_DATA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_DATA0_OFFSET) -#define IMXRT_INPUT_USDHC2_DATA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_DATA1_OFFSET) -#define IMXRT_INPUT_USDHC2_DATA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_DATA2_OFFSET) -#define IMXRT_INPUT_USDHC2_DATA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_DATA3_OFFSET) -#define IMXRT_INPUT_USDHC2_DATA4 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_DATA4_OFFSET) -#define IMXRT_INPUT_USDHC2_DATA5 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_DATA5_OFFSET) -#define IMXRT_INPUT_USDHC2_DATA6 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_DATA6_OFFSET) -#define IMXRT_INPUT_USDHC2_DATA7 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_DATA7_OFFSET) -#define IMXRT_INPUT_USDHC2_WP (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_WP_OFFSET) -#define IMXRT_INPUT_XBAR1_IN02 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN02_OFFSET) -#define IMXRT_INPUT_XBAR1_IN03 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN03_OFFSET) -#define IMXRT_INPUT_XBAR1_IN04 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN04_OFFSET) -#define IMXRT_INPUT_XBAR1_IN05 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN05_OFFSET) -#define IMXRT_INPUT_XBAR1_IN06 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN05_OFFSET) -#define IMXRT_INPUT_XBAR1_IN07 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN07_OFFSET) -#define IMXRT_INPUT_XBAR1_IN08 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN08_OFFSET) -#define IMXRT_INPUT_XBAR1_IN09 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN09_OFFSET) -#define IMXRT_INPUT_XBAR1_IN17 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN17_OFFSET) -#define IMXRT_INPUT_XBAR1_IN18 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN18_OFFSET) -#define IMXRT_INPUT_XBAR1_IN20 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN20_OFFSET) -#define IMXRT_INPUT_XBAR1_IN22 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN22_OFFSET) -#define IMXRT_INPUT_XBAR1_IN23 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN23_OFFSET) -#define IMXRT_INPUT_XBAR1_IN24 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN24_OFFSET) -#define IMXRT_INPUT_XBAR1_IN14 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN14_OFFSET) -#define IMXRT_INPUT_XBAR1_IN15 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN15_OFFSET) -#define IMXRT_INPUT_XBAR1_IN16 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN16_OFFSET) -#define IMXRT_INPUT_XBAR1_IN25 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN25_OFFSET) -#define IMXRT_INPUT_XBAR1_IN19 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN19_OFFSET) -#define IMXRT_INPUT_XBAR1_IN21 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN21_OFFSET) - -/* Select1 Input Registers */ - -#define IMXRT_INPUT_ENET2_IPG_CLK_RMII (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET2_IPG_CLK_RMII_OFFSET) -#define IMXRT_INPUT_ENET2_IPP_IND_MAC0_MDIO (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET2_IPP_IND_MAC0_MDIO_OFFSET) -#define IMXRT_INPUT_ENET2_IPP_IND_MAC0_RXDATA_0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET2_IPP_IND_MAC0_RXDATA_0_OFFSET) -#define IMXRT_INPUT_ENET2_IPP_IND_MAC0_RXDATA_1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET2_IPP_IND_MAC0_RXDATA_1_OFFSET) -#define IMXRT_INPUT_ENET2_IPP_IND_MAC0_RXEN (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET2_IPP_IND_MAC0_RXEN_OFFSET) -#define IMXRT_INPUT_ENET2_IPP_IND_MAC0_RXERR (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET2_IPP_IND_MAC0_RXERR_OFFSET) -#define IMXRT_INPUT_ENET2_IPP_IND_MAC0_TIMER_0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET2_IPP_IND_MAC0_TIMER_0_OFFSET) -#define IMXRT_INPUT_ENET2_IPP_IND_MAC0_TXCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET2_IPP_IND_MAC0_TXCLK_OFFSET) -#define IMXRT_INPUT_FLEXSPI2_IPP_IND_DQS_FA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPI2_IPP_IND_DQS_FA_OFFSET) -#define IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FA_BIT0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FA_BIT0_OFFSET) -#define IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FA_BIT1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FA_BIT1_OFFSET) -#define IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FA_BIT2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FA_BIT2_OFFSET) -#define IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FA_BIT3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FA_BIT3_OFFSET) -#define IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FB_BIT0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FB_BIT0_OFFSET) -#define IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FB_BIT1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FB_BIT1_OFFSET) -#define IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FB_BIT2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FB_BIT2_OFFSET) -#define IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FB_BIT3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FB_BIT3_OFFSET) -#define IMXRT_INPUT_FLEXSPI2_IPP_IND_SCK_FA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPI2_IPP_IND_SCK_FA_OFFSET) -#define IMXRT_INPUT_FLEXSPI2_IPP_IND_SCK_FB (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPI2_IPP_IND_SCK_FB_OFFSET) -#define IMXRT_INPUT_GPT1_IPP_IND_CAPIN1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_GPT1_IPP_IND_CAPIN1_OFFSET) -#define IMXRT_INPUT_GPT1_IPP_IND_CAPIN2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_GPT1_IPP_IND_CAPIN2_OFFSET) -#define IMXRT_INPUT_GPT1_IPP_IND_CLKIN (IMXRT_IOMUXC_BASE + IMXRT_INPUT_GPT1_IPP_IND_CLKIN_OFFSET) -#define IMXRT_INPUT_GPT2_IPP_IND_CAPIN1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_GPT2_IPP_IND_CAPIN1_OFFSET) -#define IMXRT_INPUT_GPT2_IPP_IND_CAPIN2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_GPT2_IPP_IND_CAPIN2_OFFSET) -#define IMXRT_INPUT_GPT2_IPP_IND_CLKIN (IMXRT_IOMUXC_BASE + IMXRT_INPUT_GPT2_IPP_IND_CLKIN_OFFSET) -#define IMXRT_INPUT_SAI3_IPG_CLK_SAI_MCLK_2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI3_IPG_CLK_SAI_MCLK_2_OFFSET) -#define IMXRT_INPUT_SAI3_IPP_IND_SAI_RXBCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI3_IPP_IND_SAI_RXBCLK_OFFSET) -#define IMXRT_INPUT_SAI3_IPP_IND_SAI_RXDATA_0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI3_IPP_IND_SAI_RXDATA_0_OFFSET) -#define IMXRT_INPUT_SAI3_IPP_IND_SAI_RXSYNC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI3_IPP_IND_SAI_RXSYNC_OFFSET) -#define IMXRT_INPUT_SAI3_IPP_IND_SAI_TXBCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI3_IPP_IND_SAI_TXBCLK_OFFSET) -#define IMXRT_INPUT_SAI3_IPP_IND_SAI_TXSYNC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI3_IPP_IND_SAI_TXSYNC_OFFSET) -#define IMXRT_INPUT_SEMC_I_IPP_IND_DQS4 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SEMC_I_IPP_IND_DQS4_OFFSET) -#define IMXRT_INPUT_CANFD_IPP_IND_CANRX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CANFD_IPP_IND_CANRX_OFFSET) - -/* Register bit definitions *********************************************************/ - -/* General Purpose Register 0 (GPR0) - Reserved */ - -/* General Purpose Register 1 (GPR1) */ - -#define GPR_GPR1_SAI1_MCLK1_SEL_SHIFT (0) -#define GPR_GPR1_SAI1_MCLK1_SEL_MASK (7 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK1_SEL_CCM_SSI1_CLK_ROOT (0 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK1_SEL_CCM_SSI2_CLK_ROOT (1 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK1_SEL_CCM_SSI3_CLK_ROOT (2 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK1_SEL_IOMUX_SAI1_IPG_CLK_SAI_MCLK2 (3 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK1_SEL_IOMUX_SAI2_IPG_CLK_SAI_MCLK2 (4 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK1_SEL_IOMUX_SAI3_IPG_CLK_SAI_MCLK2 (5 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) -#define GPR_GPR1_SAI1_MCLK2_SEL_SHIFT (3) -#define GPR_GPR1_SAI1_MCLK2_SEL_MASK (7 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK2_SEL_CCM_SSI1_CLK_ROOT (0 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK2_SEL_CCM_SSI2_CLK_ROOT (1 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK2_SEL_CCM_SSI3_CLK_ROOT (2 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK2_SEL_IOMUX_SAI1_IPG_CLK_SAI_MCLK2 (3 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK2_SEL_IOMUX_SAI2_IPG_CLK_SAI_MCLK2 (4 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK2_SEL_IOMUX_SAI3_IPG_CLK_SAI_MCLK2 (5 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) -#define GPR_GPR1_SAI1_MCLK3_SEL_SHIFT (6) -#define GPR_GPR1_SAI1_MCLK3_SEL_MASK (3 << GPR_GPR1_SAI1_MCLK3_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK3_SEL_CCM_SPDIF0_CLK_ROOT (0 << GPR_GPR1_SAI1_MCLK3_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK3_SEL_IOMUX_SPDIF_TX_CLK2 (1 << GPR_GPR1_SAI1_MCLK3_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK3_SEL_SPDIF_SPDIF_SRCLK (2 << GPR_GPR1_SAI1_MCLK3_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK3_SEL_SPDIF_SPDIF_OUTCLOCK (3 << GPR_GPR1_SAI1_MCLK3_SEL_SHIFT) -#define GPR_GPR1_SAI2_MCLK3_SEL_SHIFT (8) -#define GPR_GPR1_SAI2_MCLK3_SEL_MASK (3 << GPR_GPR1_SAI2_MCLK3_SEL_SHIFT) -# define GPR_GPR1_SAI2_MCLK3_SEL_CCM_SPDIF0_CLK_ROOT (0 << GPR_GPR1_SAI2_MCLK3_SEL_SHIFT) -# define GPR_GPR1_SAI2_MCLK3_SEL_IOMUX_SPDIF_TX_CLK2 (1 << GPR_GPR1_SAI2_MCLK3_SEL_SHIFT) -# define GPR_GPR1_SAI2_MCLK3_SEL_SPDIF_SPDIF_SRCLK (2 << GPR_GPR1_SAI2_MCLK3_SEL_SHIFT) -# define GPR_GPR1_SAI2_MCLK3_SEL_SPDIF_SPDIF_OUTCLOCK (3 << GPR_GPR1_SAI2_MCLK3_SEL_SHIFT) -#define GPR_GPR1_SAI3_MCLK3_SEL_SHIFT (10) -#define GPR_GPR1_SAI3_MCLK3_SEL_MASK (3 << GPR_GPR1_SAI3_MCLK3_SEL_SHIFT) -# define GPR_GPR1_SAI3_MCLK3_SEL_CCM_SPDIF0_CLK_ROOT (0 << GPR_GPR1_SAI3_MCLK3_SEL_SHIFT) -# define GPR_GPR1_SAI3_MCLK3_SEL_IOMUX_SPDIF_TX_CLK2 (1 << GPR_GPR1_SAI3_MCLK3_SEL_SHIFT) -# define GPR_GPR1_SAI3_MCLK3_SEL_SPDIF_SPDIF_SRCLK (2 << GPR_GPR1_SAI3_MCLK3_SEL_SHIFT) -# define GPR_GPR1_SAI3_MCLK3_SEL_SPDIF_SPDIF_OUTCLOCK (3 << GPR_GPR1_SAI3_MCLK3_SEL_SHIFT) -#define GPR_GPR1_GINT (1 << 12) -#define GPR_GPR1_ENET1_CLK_SEL (1 << 13) -#define GPR_GPR1_ENET2_CLK_SEL (1 << 14) -#define GPR_GPR1_USB_EXP_MODE_EN (1 << 15) -#define GPR_GPR1_ENET1_TX_CLK_OUT_EN (1 << 17) -#define GPR_GPR1_SAI1_MCLK_DIR_IN (0 << 19) -#define GPR_GPR1_SAI1_MCLK_DIR_OUT (1 << 19) -#define GPR_GPR1_SAI2_MCLK_DIR_IN (0 << 20) -#define GPR_GPR1_SAI2_MCLK_DIR_OUT (1 << 20) -#define GPR_GPR1_SAI3_MCLK_DIR_IN (0 << 21) -#define GPR_GPR1_SAI3_MCLK_DIR_OUT (1 << 21) -#define GPR_GPR1_EXC_MON_OKAY (0 << 22) -#define GPR_GPR1_EXC_MON_SLVERR (1 << 22) -#define GPR_GPR1_ENET_IMG_CLS_S_EN (1 << 23) -#define GPR_GPR1_CM7_FORCE_HCLK_EN (1 << 31) - -/* General Purpose Register 2 (GPR2) */ - -#define GPR_GPR2_AXBS_L_AHBXL_HIGH_PRIORITY (1 << 0) -#define GPR_GPR2_AXBS_L_DMA_HIGH_PRIORITY (1 << 1) -#define GPR_GPR2_AXBS_L_FORCE_ROUND_ROBIN (1 << 2) -#define GPR_GPR2_AXBS_P_M0_HIGH_PRIORITY (1 << 3) -#define GPR_GPR2_AXBS_P_M1_HIGH_PRIORITY (1 << 4) -#define GPR_GPR2_AXBS_P_FORCE_ROUND_ROBIN (1 << 5) -#define GPR_GPR2_CANFD_FILTER_BYPASS (1 << 6) -#define GPR_GPR2_L2_MEM_POWERSAVE_EN (1 << 12) -#define GPR_GPR2_RAM_AUTO_CLK_GATING_EN (1 << 13) -#define GPR_GPR2_L2_MEM_FORCE_DEEPSLEEP (1 << 14) -#define GPR_GPR2_MQS_CLK_DIV_SHIFT (16) -#define GPR_GPR2_MQS_CLK_DIV_MASK (255 << GPR_GPR2_MQS_CLK_DIV_SHIFT) -# define GPR_GPR2_MQS_CLK_DIV(n) ((n - 1) << GPR_GPR2_MQS_CLK_DIV_SHIFT) -#define GPR_GPR2_MQS_SW_RST_EN (1 << 24) -#define GPR_GPR2_MQS_EN (1 << 25) -#define GPR_GPR2_MQS_OVERSAMPLE32 (0 << 26) -#define GPR_GPR2_MQS_OVERSAMPLE64 (1 << 26) -#define GPR_GPR2_QTIM1_TMR_RESET (1 << 28) -#define GPR_GPR2_QTIM2_TMR_RESET (1 << 29) -#define GPR_GPR2_QTIM3_TMR_RESET (1 << 30) -#define GPR_GPR2_QTIM4_TMR_RESET (1 << 31) - -/* General Purpose Register 3 (GPR3) */ - -#define GPR_GPR3_OCRAM_CTL_SHIFT (0) -#define GPR_GPR3_OCRAM_CTL_MASK (15 << GPR_GPR3_OCRAM_CTL_SHIFT) -# define GPR_GPR3_OCRAM_CTL_READ_DATA_PIPELINE_EN (1 << GPR_GPR3_OCRAM_CTL_SHIFT) -# define GPR_GPR3_OCRAM_CTL_READ_ADDR_PIPELINE_EN (2 << GPR_GPR3_OCRAM_CTL_SHIFT) -# define GPR_GPR3_OCRAM_CTL_WRITE_DATA_PIPELINE_EN (4 << GPR_GPR3_OCRAM_CTL_SHIFT) -# define GPR_GPR3_OCRAM_CTL_WRITE_ADDR_PIPELINE_EN (8 << GPR_GPR3_OCRAM_CTL_SHIFT) -#define GPR_GPR3_DCP_KEY_SEL_128 (0 << 4) -#define GPR_GPR3_DCP_KEY_SEL_256 (1 << 4) -#define GPR_GPR3_OCRAM2_CTL_SHIFT (8) -#define GPR_GPR3_OCRAM2_CTL_MASK (15 << GPR_GPR3_OCRAM2_CTL_SHIFT) -# define GPR_GPR3_OCRAM2_CTL_READ_DATA_PIPELINE_EN (1 << GPR_GPR3_OCRAM2_CTL_SHIFT) -# define GPR_GPR3_OCRAM2_CTL_READ_ADDR_PIPELINE_EN (2 << GPR_GPR3_OCRAM2_CTL_SHIFT) -# define GPR_GPR3_OCRAM2_CTL_WRITE_DATA_PIPELINE_EN (4 << GPR_GPR3_OCRAM2_CTL_SHIFT) -# define GPR_GPR3_OCRAM2_CTL_WRITE_ADDR_PIPELINE_EN (8 << GPR_GPR3_OCRAM2_CTL_SHIFT) -#define GPR_GPR3_AXBS_L_HALT_REQ (1 << 15) -#define GPR_GPR3_OCRAM_STATUS_SHIFT (16) -#define GPR_GPR3_OCRAM_STATUS_MASK (15 << GPR_GPR3_OCRAM_STATUS_SHIFT) -# define GPR_GPR3_OCRAM_STATUS_READ_DATA_PIPELINE_EN (1 << GPR_GPR3_OCRAM_STATUS_SHIFT) -# define GPR_GPR3_OCRAM_STATUS_READ_ADDR_PIPELINE_EN (2 << GPR_GPR3_OCRAM_STATUS_SHIFT) -# define GPR_GPR3_OCRAM_STATUS_WRITE_DATA_PIPELINE_EN (4 << GPR_GPR3_OCRAM_STATUS_SHIFT) -# define GPR_GPR3_OCRAM_STATUS_WRITE_ADDR_PIPELINE_EN (8 << GPR_GPR3_OCRAM_STATUS_SHIFT) -#define GPR_GPR3_OCRAM2_STATUS_SHIFT (24) -#define GPR_GPR3_OCRAM2_STATUS_MASK (15 << GPR_GPR3_OCRAM2_STATUS_SHIFT) -# define GPR_GPR3_OCRAM2_STATUS_READ_DATA_PIPELINE_EN (1 << GPR_GPR3_OCRAM2_STATUS_SHIFT) -# define GPR_GPR3_OCRAM2_STATUS_READ_ADDR_PIPELINE_EN (2 << GPR_GPR3_OCRAM2_STATUS_SHIFT) -# define GPR_GPR3_OCRAM2_STATUS_WRITE_DATA_PIPELINE_EN (4 << GPR_GPR3_OCRAM2_STATUS_SHIFT) -# define GPR_GPR3_OCRAM2_STATUS_WRITE_ADDR_PIPELINE_EN (8 << GPR_GPR3_OCRAM2_STATUS_SHIFT) -#define GPR_GPR3_AXBS_L_HALTED (1 << 31) - -/* General Purpose Register 4 (GPR4) */ - -#define GPR_GRP4_EDMA_STOP_REQ (1 << 0) -#define GPR_GPR4_CAN1_STOP_REQ (1 << 1) -#define GPR_GPR4_CAN2_STOP_REQ (1 << 2) -#define GPR_GPR4_TRNG_STOP_REQ (1 << 3) -#define GPR_GPR4_ENET_STOP_REQ (1 << 4) -#define GPR_GPR4_SAI1_STOP_REQ (1 << 5) -#define GPR_GPR4_SAI2_STOP_REQ (1 << 6) -#define GPR_GPR4_SAI3_STOP_REQ (1 << 7) -#define GPR_GPR4_ENET2_STOP_REQ (1 << 8) -#define GPR_GPR4_SEMC_STOP_REQ (1 << 9) -#define GPR_GPR4_PIT_STOP_REQ (1 << 10) -#define GPR_GPR4_FLEXSPI_STOP_REQ (1 << 11) -#define GPR_GPR4_FLEXIO1_STOP_REQ (1 << 12) -#define GPR_GPR4_FLEXIO2_STOP_REQ (1 << 13) -#define GPR_GPR4_FLEXIO3_STOP_REQ (1 << 14) -#define GPR_GPR4_FLEXSPI2_STOP_REQ (1 << 15) -#define GPR_GRP4_EDMA_STOP_ACK (1 << 16) -#define GPR_GPR4_CAN1_STOP_ACK (1 << 17) -#define GPR_GPR4_CAN2_STOP_ACK (1 << 18) -#define GPR_GPR4_TRNG_STOP_ACK (1 << 19) -#define GPR_GPR4_ENET_STOP_ACK (1 << 20) -#define GPR_GPR4_SAI1_STOP_ACK (1 << 21) -#define GPR_GPR4_SAI2_STOP_ACK (1 << 22) -#define GPR_GPR4_SAI3_STOP_ACK (1 << 23) -#define GPR_GPR4_ENET2_STOP_ACK (1 << 24) -#define GPR_GPR4_SEMC_STOP_ACK (1 << 25) -#define GPR_GPR4_PIT_STOP_ACK (1 << 26) -#define GPR_GPR4_FLEXSPI_STOP_ACK (1 << 27) -#define GPR_GPR4_FLEXIO1_STOP_ACK (1 << 28) -#define GPR_GPR4_FLEXIO2_STOP_ACK (1 << 29) -#define GPR_GPR4_FLEXIO3_STOP_ACK (1 << 30) -#define GPR_GPR4_FLEXSPI2_STOP_ACK (1 << 31) - -/* General Purpose Register 5 (GPR5) */ - -#define GPR_GPR5_WDOG1_MASK (1 << 6) -#define GPR_GPR5_WDOG2_MASK (1 << 7) -#define GPR_GPR5_GPT2_CAPIN1_SEL_PAD (0 << 23) -#define GPR_GPR5_GPT2_CAPIN1_SEL_ENET1 (1 << 23) -#define GPR_GPR5_GPT2_CAPIN2_SEL_PAD (0 << 24) -#define GPR_GPR5_GPT2_CAPIN2_SEL_ENET2 (1 << 24) -#define GPR_GPR5_ENET_EVENT3IN_SEL_ENET (0 << 25) -#define GPR_GPR5_ENET_EVENT3IN_SEL_GPT2CMP1 (1 << 25) -#define GPR_GPR5_ENET2_EVENT3IN_SEL_ENET2 (0 << 26) -#define GPR_GPR5_ENET2_EVENT3IN_SEL_CPT2CMP2 (1 << 26) -#define GPR_GPR5_VREF_1M_CLK_GPT1_IPG_PERCLK (0 << 28) -#define GPR_GPR5_VREF_1M_CLK_GPT1_ANATOP (1 << 28) -#define GPR_GPR5_VREF_1M_CLK_GPT2_IPG_PERCLK (0 << 29) -#define GPR_GPR5_VREF_1M_CLK_GPT2_ANATOP (1 << 29) - -/* General Purpose Register 6 (GPR6) */ - -#define GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT (0) -#define GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT) -#define GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT (1) -#define GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT) -#define GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT (2) -#define GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT) -#define GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT (3) -#define GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT) -#define GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT (4) -#define GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT) -#define GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT (5) -#define GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT) -#define GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT (6) -#define GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT) -#define GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT (7) -#define GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT) -#define GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT (8) -#define GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT) -#define GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT (9) -#define GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT) -#define GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT (10) -#define GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT) -#define GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT (11) -#define GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT) -#define GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT (12) -#define GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT) -#define GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT (13) -#define GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT) -#define GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT (14) -#define GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT) -#define GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT (15) -#define GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT) -# define GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT (16) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT (17) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT (18) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT (19) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT (20) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT (21) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT (22) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT (23) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT (24) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT (25) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT (26) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT (27) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT (28) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT (29) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT (30) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT (31) -#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT) -# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT) - -/* General Purpose Register 7 (GPR7) */ - -#define GPR_GPR7_LPI2C1_STOP_REQ (1 << 0) -#define GPR_GPR7_LPI2C2_STOP_REQ (1 << 1) -#define GPR_GPR7_LPI2C3_STOP_REQ (1 << 2) -#define GPR_GPR7_LPI2C4_STOP_REQ (1 << 3) -#define GPR_GPR7_LPSPI1_STOP_REQ (1 << 4) -#define GPR_GPR7_LPSPI2_STOP_REQ (1 << 5) -#define GPR_GPR7_LPSPI3_STOP_REQ (1 << 6) -#define GPR_GPR7_LPSPI4_STOP_REQ (1 << 7) -#define GPR_GPR7_LPUART1_STOP_REQ (1 << 8) -#define GPR_GPR7_LPUART2_STOP_REQ (1 << 9) -#define GPR_GPR7_LPUART3_STOP_REQ (1 << 10) -#define GPR_GPR7_LPUART4_STOP_REQ (1 << 11) -#define GPR_GPR7_LPUART5_STOP_REQ (1 << 12) -#define GPR_GPR7_LPUART6_STOP_REQ (1 << 13) -#define GPR_GPR7_LPUART7_STOP_REQ (1 << 14) -#define GPR_GPR7_LPUART8_STOP_REQ (1 << 15) -#define GPR_GPR7_LPI2C1_STOP_ACK (1 << 16) -#define GPR_GPR7_LPI2C2_STOP_ACK (1 << 17) -#define GPR_GPR7_LPI2C3_STOP_ACK (1 << 18) -#define GPR_GPR7_LPI2C4_STOP_ACK (1 << 19) -#define GPR_GPR7_LPSPI1_STOP_ACK (1 << 20) -#define GPR_GPR7_LPSPI2_STOP_ACK (1 << 21) -#define GPR_GPR7_LPSPI3_STOP_ACK (1 << 22) -#define GPR_GPR7_LPSPI4_STOP_ACK (1 << 23) -#define GPR_GPR7_LPUART1_STOP_ACK (1 << 24) -#define GPR_GPR7_LPUART2_STOP_ACK (1 << 25) -#define GPR_GPR7_LPUART3_STOP_ACK (1 << 26) -#define GPR_GPR7_LPUART4_STOP_ACK (1 << 27) -#define GPR_GPR7_LPUART5_STOP_ACK (1 << 28) -#define GPR_GPR7_LPUART6_STOP_ACK (1 << 29) -#define GPR_GPR7_LPUART7_STOP_ACK (1 << 30) -#define GPR_GPR7_LPUART8_STOP_ACK (1 << 31) - -/* General Purpose Register 8 (GPR8) */ - -#define GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT (0) -#define GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPI2C1_IPG_ON_IN_STOP (0 << GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPI2C1_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT) -#define GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT (1) -#define GPR_GPR8_LPI2C1_IPG_DOZE_MASK (1 << GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPI2C1_IPG_NOT_DOZED (0 << GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPI2C1_IPG_DOZED (1 << GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT) -#define GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT (2) -#define GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPI2C2_IPG_ON_IN_STOP (0 << GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPI2C2_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT) -#define GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT (3) -#define GPR_GPR8_LPI2C2_IPG_DOZE_MASK (1 << GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPI2C2_IPG_NOT_DOZED (0 << GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPI2C2_IPG_DOZED (1 << GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT) -#define GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT (4) -#define GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPI2C3_IPG_ON_IN_STOP (0 << GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPI2C3_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT) -#define GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT (5) -#define GPR_GPR8_LPI2C3_IPG_DOZE_MASK (1 << GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPI2C3_IPG_NOT_DOZED (0 << GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPI2C3_IPG_DOZED (1 << GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT) -#define GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT (6) -#define GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPI2C4_IPG_ON_IN_STOP (0 << GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPI2C4_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT) -#define GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT (7) -#define GPR_GPR8_LPI2C4_IPG_DOZE_MASK (1 << GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPI2C4_IPG_NOT_DOZED (0 << GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPI2C4_IPG_DOZED (1 << GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT) -#define GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT (8) -#define GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPSPI1_IPG_ON_IN_STOP (0 << GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPSPI1_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT) -#define GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT (9) -#define GPR_GPR8_LPSPI1_IPG_DOZE_MASK (1 << GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPSPI1_IPG_NOT_DOZED (0 << GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPSPI1_IPG_DOZED (1 << GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT) -#define GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT (10) -#define GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPSPI2_IPG_ON_IN_STOP (0 << GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPSPI2_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT) -#define GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT (11) -#define GPR_GPR8_LPSPI2_IPG_DOZE_MASK (1 << GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPSPI2_IPG_NOT_DOZED (0 << GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPSPI2_IPG_DOZED (1 << GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT) -#define GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT (12) -#define GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPSPI3_IPG_ON_IN_STOP (0 << GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPSPI3_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT) -#define GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT (13) -#define GPR_GPR8_LPSPI3_IPG_DOZE_MASK (1 << GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPSPI3_IPG_NOT_DOZED (0 << GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPSPI3_IPG_DOZED (1 << GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT) -#define GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT (14) -#define GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPSPI4_IPG_ON_IN_STOP (0 << GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPSPI4_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT) -#define GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT (15) -#define GPR_GPR8_LPSPI4_IPG_DOZE_MASK (1 << GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPSPI4_IPG_NOT_DOZED (0 << GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPSPI4_IPG_DOZED (1 << GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT) -#define GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT (16) -#define GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPUART1_IPG_ON_IN_STOP (0 << GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPUART1_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT) -#define GPR_GPR8_LPUART1_IPG_DOZE_SHIFT (17) -#define GPR_GPR8_LPUART1_IPG_DOZE_MASK (1 << GPR_GPR8_LPUART1_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPUART1_IPG_NOT_DOZED (0 << GPR_GPR8_LPUART1_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPUART1_IPG_DOZED (1 << GPR_GPR8_LPUART1_IPG_DOZE_SHIFT) -#define GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT (18) -#define GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPUART2_IPG_ON_IN_STOP (0 << GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPUART2_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT) -#define GPR_GPR8_LPUART2_IPG_DOZE_SHIFT (19) -#define GPR_GPR8_LPUART2_IPG_DOZE_MASK (1 << GPR_GPR8_LPUART2_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPUART2_IPG_NOT_DOZED (0 << GPR_GPR8_LPUART2_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPUART2_IPG_DOZED (1 << GPR_GPR8_LPUART2_IPG_DOZE_SHIFT) -#define GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT (20) -#define GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPUART3_IPG_ON_IN_STOP (0 << GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPUART3_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT) -#define GPR_GPR8_LPUART3_IPG_DOZE_SHIFT (21) -#define GPR_GPR8_LPUART3_IPG_DOZE_MASK (1 << GPR_GPR8_LPUART3_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPUART3_IPG_NOT_DOZED (0 << GPR_GPR8_LPUART3_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPUART3_IPG_DOZED (1 << GPR_GPR8_LPUART3_IPG_DOZE_SHIFT) -#define GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT (22) -#define GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPUART4_IPG_ON_IN_STOP (0 << GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPUART4_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT) -#define GPR_GPR8_LPUART4_IPG_DOZE_SHIFT (23) -#define GPR_GPR8_LPUART4_IPG_DOZE_MASK (1 << GPR_GPR8_LPUART4_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPUART4_IPG_NOT_DOZED (0 << GPR_GPR8_LPUART4_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPUART4_IPG_DOZED (1 << GPR_GPR8_LPUART4_IPG_DOZE_SHIFT) -#define GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT (24) -#define GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPUART5_IPG_ON_IN_STOP (0 << GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPUART5_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT) -#define GPR_GPR8_LPUART5_IPG_DOZE_SHIFT (25) -#define GPR_GPR8_LPUART5_IPG_DOZE_MASK (1 << GPR_GPR8_LPUART5_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPUART5_IPG_NOT_DOZED (0 << GPR_GPR8_LPUART5_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPUART5_IPG_DOZED (1 << GPR_GPR8_LPUART5_IPG_DOZE_SHIFT) -#define GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT (26) -#define GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPUART6_IPG_ON_IN_STOP (0 << GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPUART6_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT) -#define GPR_GPR8_LPUART6_IPG_DOZE_SHIFT (27) -#define GPR_GPR8_LPUART6_IPG_DOZE_MASK (1 << GPR_GPR8_LPUART6_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPUART6_IPG_NOT_DOZED (0 << GPR_GPR8_LPUART6_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPUART6_IPG_DOZED (1 << GPR_GPR8_LPUART6_IPG_DOZE_SHIFT) -#define GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT (28) -#define GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPUART7_IPG_ON_IN_STOP (0 << GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPUART7_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT) -#define GPR_GPR8_LPUART7_IPG_DOZE_SHIFT (29) -#define GPR_GPR8_LPUART7_IPG_DOZE_MASK (1 << GPR_GPR8_LPUART7_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPUART7_IPG_NOT_DOZED (0 << GPR_GPR8_LPUART7_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPUART7_IPG_DOZED (1 << GPR_GPR8_LPUART7_IPG_DOZE_SHIFT) -#define GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT (30) -#define GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPUART8_IPG_ON_IN_STOP (0 << GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT) -# define GPR_GPR8_LPUART8_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT) -#define GPR_GPR8_LPUART8_IPG_DOZE_SHIFT (31) -#define GPR_GPR8_LPUART8_IPG_DOZE_MASK (1 << GPR_GPR8_LPUART8_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPUART8_IPG_NOT_DOZED (0 << GPR_GPR8_LPUART8_IPG_DOZE_SHIFT) -# define GPR_GPR8_LPUART8_IPG_DOZED (1 << GPR_GPR8_LPUART8_IPG_DOZE_SHIFT) - -/* General Purpose Register 9 (GPR9) - Reserved */ - -/* General Purpose Register 10 (GPR10) */ - -#define GPR_GPR10_NIDEN (1 << 0) -#define GPR_GPR10_DBG_EN (1 << 1) -#define GPR_GPR10_SEC_ERR_RESP (1 << 2) -#define GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX (1 << 4) -#define GPR_GPR10_OCRAM_TZ_EN (1 << 8) -#define GPR_GPR10_OCRAM_TZ_ADDR_SHIFT (9) -#define GPR_GPR10_OCRAM_TZ_ADDR_MASK (0x3f << GPR_GPR10_OCRAM_TZ_ADDR_SHIFT) -# define GPR_GPR10_OCRAM_TZ_ADDR(n) ((uint32_t)(n) << GPR_GPR10_OCRAM_TZ_ADDR_SHIFT) -#define GPR_GPR10_LOCK_NIDEN (1 << 16) -#define GPR_GPR10_LOCK_DBG_EN (1 << 17) -#define GPR_GPR10_LOCK_SEC_ERR_RESP (1 << 18) -#define GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX (1 << 20) -#define GPR_GPR10_LOCK_OCRAM_TZ_EN (1 << 24) -#define GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT (25) -#define GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK (0x3f << GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT) -# define GPR_GPR10_LOCK_OCRAM_TZ_ADDR(n) ((uint32_t)(n) << GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT) - -/* General Purpose Register 11 (GPR11) */ - -#define GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFTS (0) -#define GPR_GPR11_M7_APC_AC_R0_CTRL_MASK (3 << GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFTS) -# define GPR_GPR11_M7_APC_AC_R0_CTRL_NO_ACCESS (0 << GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFTS) -# define GPR_GPR11_M7_APC_AC_R0_CTRL_NO_DEBUG (1 << GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFTS) -# define GPR_GPR11_M7_APC_AC_R0_CTRL_NO_FLEXSPI (2 << GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFTS) -# define GPR_GPR11_M7_APC_AC_R0_CTRL_NO_DEBUG_FLEXSPI (3 << GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFTS) -#define GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFTS (2) -#define GPR_GPR11_M7_APC_AC_R1_CTRL_MASK (3 << GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFTS) -# define GPR_GPR11_M7_APC_AC_R1_CTRL_NO_ACCESS (0 << GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFTS) -# define GPR_GPR11_M7_APC_AC_R1_CTRL_NO_DEBUG (1 << GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFTS) -# define GPR_GPR11_M7_APC_AC_R1_CTRL_NO_FLEXSPI (2 << GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFTS) -# define GPR_GPR11_M7_APC_AC_R1_CTRL_NO_DEBUG_FLEXSPI (3 << GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFTS) -#define GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFTS (4) -#define GPR_GPR11_M7_APC_AC_R2_CTRL_MASK (3 << GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFTS) -# define GPR_GPR11_M7_APC_AC_R2_CTRL_NO_ACCESS (0 << GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFTS) -# define GPR_GPR11_M7_APC_AC_R2_CTRL_NO_DEBUG (1 << GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFTS) -# define GPR_GPR11_M7_APC_AC_R2_CTRL_NO_FLEXSPI (2 << GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFTS) -# define GPR_GPR11_M7_APC_AC_R2_CTRL_NO_DEBUG_FLEXSPI (3 << GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFTS) -#define GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFTS (6) -#define GPR_GPR11_M7_APC_AC_R3_CTRL_MASK (3 << GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFTS) -# define GPR_GPR11_M7_APC_AC_R3_CTRL_NO_ACCESS (0 << GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFTS) -# define GPR_GPR11_M7_APC_AC_R3_CTRL_NO_DEBUG (1 << GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFTS) -# define GPR_GPR11_M7_APC_AC_R3_CTRL_NO_FLEXSPI (2 << GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFTS) -# define GPR_GPR11_M7_APC_AC_R3_CTRL_NO_DEBUG_FLEXSPI (3 << GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFTS) -#define GPR_GPR11_BEE_DE_RX_EN_SHIFTS (8) -#define GPR_GPR11_BEE_DE_RX_EN_MASK (0xf << GPR_GPR11_BEE_DE_RX_EN_SHIFTS) -# define GPR_GPR11_BEE_DE_RX_EN(n) ((uint32_t)(n) << GPR_GPR11_BEE_DE_RX_EN_SHIFTS) -# define GPR_GPR11_BEE_DE_R0_EN (1) << GPR_GPR11_BEE_DE_RX_EN_SHIFTS) -# define GPR_GPR11_BEE_DE_R1_EN (2) << GPR_GPR11_BEE_DE_RX_EN_SHIFTS) -# define GPR_GPR11_BEE_DE_R2_EN (4) << GPR_GPR11_BEE_DE_RX_EN_SHIFTS) -# define GPR_GPR11_BEE_DE_R3_EN (8) << GPR_GPR11_BEE_DE_RX_EN_SHIFTS) - -/* General Purpose Register 12 (GPR12) */ - -#define GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT (0) -#define GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK (1 << GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT) -# define GPR_GPR12_FLEXIO1_IPG_ON_IN_STOP (0 << GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT) -# define GPR_GPR12_FLEXIO1_IPG_OFF_IN_STOP (1 << GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT) -#define GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT (1) -#define GPR_GPR12_FLEXIO1_IPG_DOZE_MASK (1 << GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT) -# define GPR_GPR12_FLEXIO1_IPG_NOT_DOZED (0 << GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT) -# define GPR_GPR12_FLEXIO1_IPG_DOZED (1 << GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT) -#define GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT (2) -#define GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK (1 << GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT) -# define GPR_GPR12_FLEXIO2_IPG_ON_IN_STOP (0 << GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT) -# define GPR_GPR12_FLEXIO2_IPG_OFF_IN_STOP (1 << GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT) -#define GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT (3) -#define GPR_GPR12_FLEXIO2_IPG_DOZE_MASK (1 << GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT) -# define GPR_GPR12_FLEXIO2_IPG_NOT_DOZED (0 << GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT) -# define GPR_GPR12_FLEXIO2_IPG_DOZED (1 << GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT) -#define GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT (4) -#define GPR_GPR12_ACMP_IPG_STOP_MODE_MASK (1 << GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT) -# define GPR_GPR12_ACMP_IPG_ON_IN_STOP (0 << GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT) -# define GPR_GPR12_ACMP_IPG_OFF_IN_STOP (1 << GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT) - -/* General Purpose Register 13 (GPR13) */ - -#define GPR_GPR13_ARCACHE_USDHC_CACHEABLE (1 << 0) -#define GPR_GPR13_AWCACHE_USDHC_CACHEABLE (1 << 1) -#define GPR_GPR13_CANFD_STOP_REQ (1 << 4) -#define GPR_GPR13_CACHE_ENET_CACHEABLE (1 << 7) -#define GPR_GPR13_CACHE_USB_CACHEABLE (1 << 13) -#define GPR_GPR13_CANFD_STOP_ACK (1 << 20) - -/* General Purpose Register 14 (GPR14) */ - -#define GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN (1 << 0) -#define GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN (1 << 1) -#define GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN (1 << 2) -#define GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN (1 << 3) -#define GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP (1 << 4) -#define GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP (1 << 5) -#define GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP (1 << 6) -#define GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP (1 << 7) -#define GPR_GPR14_ACMP1_SAMPLE_SYNC_EN (1 << 8) -#define GPR_GPR14_ACMP2_SAMPLE_SYNC_EN (1 << 9) -#define GPR_GPR14_ACMP3_SAMPLE_SYNC_EN (1 << 10) -#define GPR_GPR14_ACMP4_SAMPLE_SYNC_EN (1 << 11) -#define GPR_GPR14_CM7_CFGITCMSZ_SHIFT (16) -#define GPR_GPR14_CM7_CFGITCMSZ_MASK (0x4 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGITCMSZ_0KB (0 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGITCMSZ_4KB (3 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGITCMSZ_8KB (4 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGITCMSZ_16KB (6 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGITCMSZ_32KB (6 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGITCMSZ_64KB (7 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGITCMSZ_128KB (8 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGITCMSZ_256KB (9 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGITCMSZ_512KB (10 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) -#define GPR_GPR14_CM7_CFGDTCMSZ_SHIFT (20) -#define GPR_GPR14_CM7_CFGDTCMSZ_MASK (0xf << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGDTCMSZ_0KB (0 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGDTCMSZ_4KB (3 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGDTCMSZ_8KB (4 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGDTCMSZ_16KB (6 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGDTCMSZ_32KB (6 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGDTCMSZ_64KB (7 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGDTCMSZ_128KB (8 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGDTCMSZ_256KB (9 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) -# define GPR_GPR14_CM7_CFGDTCMSZ_512KB (10 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) - -/* General Purpose Register 15 (GPR16) - Reserved */ - -/* General Purpose Register 16 (GPR16) */ - -#define GPR_GPR16_INIT_ITCM_EN (1 << 0) -#define GPR_GPR16_INIT_DTCM_EN (1 << 1) -#define GPR_GPR16_FLEXRAM_BANK_CFG_SELF (1 << 2) -#define GPR_GPR16_CM7_INIT_VTOR_SHIFT (7) -#define GPR_GPR16_CM7_INIT_VTOR_MASK (0xffffff1 << GPR_GPR16_CM7_INIT_VTOR_SHIFT) -#define GPR_GPR16_CM7_INIT_VTOR(n) (((uint32_t)(n) & 0x1ffffff)) << GPR_GPR16_CM7_INIT_VTOR_SHIFT) - -/* General Purpose Register 17 (GPR17) */ - -#define GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT (0) -#define GPR_GPR17_FLEXRAM_BANK_CFG_MASK (0xffffffff << GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT) -#define GPR_GPR17_FLEXRAM_BANK_CFG(n) ((uint32_t)(n)) << GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT) -#define GPR_GPR17_FLEXRAM_BANK0_SHIFT (0) -#define GPR_GPR17_FLEXRAM_BANK0_MASK (3 << GPR_GPR17_FLEXRAM_BANK0_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK0_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK0_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK0_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK0_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK0_DTCM (2 << GPR_GPR17_FLEXRAM_BANK0_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK0_ITCM (3 << GPR_GPR17_FLEXRAM_BANK0_SHIFT) -#define GPR_GPR17_FLEXRAM_BANK1_SHIFT (2) -#define GPR_GPR17_FLEXRAM_BANK1_MASK (3 << GPR_GPR17_FLEXRAM_BANK1_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK1_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK1_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK1_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK1_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK1_DTCM (2 << GPR_GPR17_FLEXRAM_BANK1_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK1_ITCM (3 << GPR_GPR17_FLEXRAM_BANK1_SHIFT) -#define GPR_GPR17_FLEXRAM_BANK2_SHIFT (4) -#define GPR_GPR17_FLEXRAM_BANK2_MASK (3 << GPR_GPR17_FLEXRAM_BANK2_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK2_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK2_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK2_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK2_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK2_DTCM (2 << GPR_GPR17_FLEXRAM_BANK2_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK2_ITCM (3 << GPR_GPR17_FLEXRAM_BANK2_SHIFT) -#define GPR_GPR17_FLEXRAM_BANK3_SHIFT (6) -#define GPR_GPR17_FLEXRAM_BANK3_MASK (3 << GPR_GPR17_FLEXRAM_BANK3_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK3_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK3_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK3_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK3_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK3_DTCM (2 << GPR_GPR17_FLEXRAM_BANK3_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK3_ITCM (3 << GPR_GPR17_FLEXRAM_BANK3_SHIFT) -#define GPR_GPR17_FLEXRAM_BANK4_SHIFT (8) -#define GPR_GPR17_FLEXRAM_BANK4_MASK (3 << GPR_GPR17_FLEXRAM_BANK4_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK4_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK4_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK4_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK4_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK4_DTCM (2 << GPR_GPR17_FLEXRAM_BANK4_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK4_ITCM (3 << GPR_GPR17_FLEXRAM_BANK4_SHIFT) -#define GPR_GPR17_FLEXRAM_BANK5_SHIFT (10) -#define GPR_GPR17_FLEXRAM_BANK5_MASK (3 << GPR_GPR17_FLEXRAM_BANK5_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK5_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK5_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK5_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK5_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK5_DTCM (2 << GPR_GPR17_FLEXRAM_BANK5_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK5_ITCM (3 << GPR_GPR17_FLEXRAM_BANK5_SHIFT) -#define GPR_GPR17_FLEXRAM_BANK6_SHIFT (12) -#define GPR_GPR17_FLEXRAM_BANK6_MASK (3 << GPR_GPR17_FLEXRAM_BANK6_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK6_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK6_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK6_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK6_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK6_DTCM (2 << GPR_GPR17_FLEXRAM_BANK6_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK6_ITCM (3 << GPR_GPR17_FLEXRAM_BANK6_SHIFT) -#define GPR_GPR17_FLEXRAM_BANK7_SHIFT (14) -#define GPR_GPR17_FLEXRAM_BANK7_MASK (3 << GPR_GPR17_FLEXRAM_BANK7_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK7_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK7_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK7_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK7_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK7_DTCM (2 << GPR_GPR17_FLEXRAM_BANK7_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK7_ITCM (3 << GPR_GPR17_FLEXRAM_BANK7_SHIFT) -#define GPR_GPR17_FLEXRAM_BANK8_SHIFT (16) -#define GPR_GPR17_FLEXRAM_BANK8_MASK (3 << GPR_GPR17_FLEXRAM_BANK8_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK8_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK8_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK8_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK8_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK8_DTCM (2 << GPR_GPR17_FLEXRAM_BANK8_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK8_ITCM (3 << GPR_GPR17_FLEXRAM_BANK8_SHIFT) -#define GPR_GPR17_FLEXRAM_BANK9_SHIFT (18) -#define GPR_GPR17_FLEXRAM_BANK9_MASK (3 << GPR_GPR17_FLEXRAM_BANK9_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK9_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK9_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK9_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK9_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK9_DTCM (2 << GPR_GPR17_FLEXRAM_BANK9_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK9_ITCM (3 << GPR_GPR17_FLEXRAM_BANK9_SHIFT) -#define GPR_GPR17_FLEXRAM_BANK10_SHIFT (20) -#define GPR_GPR17_FLEXRAM_BANK10_MASK (3 << GPR_GPR17_FLEXRAM_BANK10_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK10_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK10_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK10_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK10_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK10_DTCM (2 << GPR_GPR17_FLEXRAM_BANK10_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK10_ITCM (3 << GPR_GPR17_FLEXRAM_BANK10_SHIFT) -#define GPR_GPR17_FLEXRAM_BANK11_SHIFT (22) -#define GPR_GPR17_FLEXRAM_BANK11_MASK (3 << GPR_GPR17_FLEXRAM_BANK11_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK11_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK11_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK11_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK11_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK11_DTCM (2 << GPR_GPR17_FLEXRAM_BANK11_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK11_ITCM (3 << GPR_GPR17_FLEXRAM_BANK11_SHIFT) -#define GPR_GPR17_FLEXRAM_BANK12_SHIFT (24) -#define GPR_GPR17_FLEXRAM_BANK12_MASK (3 << GPR_GPR17_FLEXRAM_BANK12_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK12_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK12_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK12_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK12_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK12_DTCM (2 << GPR_GPR17_FLEXRAM_BANK12_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK12_ITCM (3 << GPR_GPR17_FLEXRAM_BANK12_SHIFT) -#define GPR_GPR17_FLEXRAM_BANK13_SHIFT (26) -#define GPR_GPR17_FLEXRAM_BANK13_MASK (3 << GPR_GPR17_FLEXRAM_BANK13_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK13_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK13_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK13_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK13_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK13_DTCM (2 << GPR_GPR17_FLEXRAM_BANK13_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK13_ITCM (3 << GPR_GPR17_FLEXRAM_BANK13_SHIFT) -#define GPR_GPR17_FLEXRAM_BANK14_SHIFT (28) -#define GPR_GPR17_FLEXRAM_BANK14_MASK (3 << GPR_GPR17_FLEXRAM_BANK14_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK14_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK14_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK14_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK14_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK14_DTCM (2 << GPR_GPR17_FLEXRAM_BANK14_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK14_ITCM (3 << GPR_GPR17_FLEXRAM_BANK14_SHIFT) -#define GPR_GPR17_FLEXRAM_BANK15_SHIFT (30) -#define GPR_GPR17_FLEXRAM_BANK15_MASK (3 << GPR_GPR17_FLEXRAM_BANK15_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK15_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK15_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK15_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK15_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK15_DTCM (2 << GPR_GPR17_FLEXRAM_BANK15_SHIFT) -# define GPR_GPR17_FLEXRAM_BANK15_ITCM (3 << GPR_GPR17_FLEXRAM_BANK15_SHIFT) - -/* General Purpose Register 18 (GPR18) */ - -#define GPR_GPR18_LOCK_M7_APC_AC_R0_BOT (1 << 0) -#define GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT (3) -#define GPR_GPR18_M7_APC_AC_R0_BOT_MASK (0x1fffffff << GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT) -#define GPR_GPR18_M7_APC_AC_R0_BOT(n) ((uint32_t)(n)) << GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT) - -/* General Purpose Register 19 (GPR19) */ - -#define GPR_GPR19_LOCK_M7_APC_AC_R0_TOP (1 << 0) -#define GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT (3) -#define GPR_GPR19_M7_APC_AC_R0_TOP_MASK (0x1fffffff << GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT) -#define GPR_GPR19_M7_APC_AC_R0_TOP(n) ((uint32_t)(n)) << GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT) - -/* General Purpose Register 20 (GPR20) */ - -#define GPR_GPR20_LOCK_M7_APC_AC_R1_BOT (1 << 0) -#define GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT (3) -#define GPR_GPR20_M7_APC_AC_R1_BOT_MASK (0x1fffffff << GPR_GPR18_M7_APC_AC_R1_BOT_SHIFT) -#define GPR_GPR20_M7_APC_AC_R1_BOT(n) ((uint32_t)(n)) << GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT) - -/* General Purpose Register 21 (GPR21) */ - -#define GPR_GPR21_LOCK_M7_APC_AC_R1_TOP (1 << 0) -#define GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT (3) -#define GPR_GPR21_M7_APC_AC_R1_TOP_MASK (0x1fffffff << GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT) -#define GPR_GPR21_M7_APC_AC_R1_TOP(n) ((uint32_t)(n)) << GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT) - -/* General Purpose Register 22 (GPR22) */ - -#define GPR_GPR22_LOCK_M7_APC_AC_R2_BOT (1 << 0) -#define GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT (3) -#define GPR_GPR22_M7_APC_AC_R2_BOT_MASK (0x1fffffff << GPR_GPR18_M7_APC_AC_R2_BOT_SHIFT) -#define GPR_GPR22_M7_APC_AC_R2_BOT(n) ((uint32_t)(n)) << GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT) - -/* General Purpose Register 23 (GPR23) */ - -#define GPR_GPR23_LOCK_M7_APC_AC_R2_TOP (1 << 0) -#define GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT (3) -#define GPR_GPR23_M7_APC_AC_R2_TOP_MASK (0x1fffffff << GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT) -#define GPR_GPR23_M7_APC_AC_R2_TOP(n) ((uint32_t)(n)) << GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT) - -/* General Purpose Register 24 (GPR24) */ - -#define GPR_GPR24_LOCK_M7_APC_AC_R3_BOT (1 << 0) -#define GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT (3) -#define GPR_GPR24_M7_APC_AC_R3_BOT_MASK (0x1fffffff << GPR_GPR18_M7_APC_AC_R3_BOT_SHIFT) -#define GPR_GPR24_M7_APC_AC_R3_BOT(n) ((uint32_t)(n)) << GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT) - -/* General Purpose Register 25 (GPR25) */ - -#define GPR_GPR25_LOCK_M7_APC_AC_R3_TOP (1 << 0) -#define GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT (3) -#define GPR_GPR25_M7_APC_AC_R3_TOP_MASK (0x1fffffff << GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT) -#define GPR_GPR25_M7_APC_AC_R3_TOP(n) ((uint32_t)(n)) << GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT) - -/* General Purpose Register 26 (GPR26) */ - -#define GPR_GPR26_GPIO_MUX1_GPIO0_SEL_GPIO1 (0 << 0) -#define GPR_GPR26_GPIO_MUX1_GPIO0_SEL_GPIO6 (1 << 0) -#define GPR_GPR26_GPIO_MUX1_GPIO1_SEL_GPIO1 (0 << 1) -#define GPR_GPR26_GPIO_MUX1_GPIO1_SEL_GPIO6 (1 << 1) -#define GPR_GPR26_GPIO_MUX1_GPIO2_SEL_GPIO1 (0 << 2) -#define GPR_GPR26_GPIO_MUX1_GPIO2_SEL_GPIO6 (1 << 2) -#define GPR_GPR26_GPIO_MUX1_GPIO3_SEL_GPIO1 (0 << 3) -#define GPR_GPR26_GPIO_MUX1_GPIO3_SEL_GPIO6 (1 << 3) -#define GPR_GPR26_GPIO_MUX1_GPIO4_SEL_GPIO1 (0 << 4) -#define GPR_GPR26_GPIO_MUX1_GPIO4_SEL_GPIO6 (1 << 4) -#define GPR_GPR26_GPIO_MUX1_GPIO5_SEL_GPIO1 (0 << 5) -#define GPR_GPR26_GPIO_MUX1_GPIO5_SEL_GPIO6 (1 << 5) -#define GPR_GPR26_GPIO_MUX1_GPIO6_SEL_GPIO1 (0 << 6) -#define GPR_GPR26_GPIO_MUX1_GPIO6_SEL_GPIO6 (1 << 6) -#define GPR_GPR26_GPIO_MUX1_GPIO7_SEL_GPIO1 (0 << 7) -#define GPR_GPR26_GPIO_MUX1_GPIO7_SEL_GPIO6 (1 << 7) -#define GPR_GPR26_GPIO_MUX1_GPIO8_SEL_GPIO1 (0 << 8) -#define GPR_GPR26_GPIO_MUX1_GPIO8_SEL_GPIO6 (1 << 8) -#define GPR_GPR26_GPIO_MUX1_GPIO9_SEL_GPIO1 (0 << 9) -#define GPR_GPR26_GPIO_MUX1_GPIO9_SEL_GPIO6 (1 << 9) -#define GPR_GPR26_GPIO_MUX1_GPIO10_SEL_GPIO1 (0 << 10) -#define GPR_GPR26_GPIO_MUX1_GPIO10_SEL_GPIO6 (1 << 10) -#define GPR_GPR26_GPIO_MUX1_GPIO11_SEL_GPIO1 (0 << 11) -#define GPR_GPR26_GPIO_MUX1_GPIO11_SEL_GPIO6 (1 << 11) -#define GPR_GPR26_GPIO_MUX1_GPIO12_SEL_GPIO1 (0 << 12) -#define GPR_GPR26_GPIO_MUX1_GPIO12_SEL_GPIO6 (1 << 12) -#define GPR_GPR26_GPIO_MUX1_GPIO13_SEL_GPIO1 (0 << 13) -#define GPR_GPR26_GPIO_MUX1_GPIO13_SEL_GPIO6 (1 << 13) -#define GPR_GPR26_GPIO_MUX1_GPIO14_SEL_GPIO1 (0 << 14) -#define GPR_GPR26_GPIO_MUX1_GPIO14_SEL_GPIO6 (1 << 14) -#define GPR_GPR26_GPIO_MUX1_GPIO15_SEL_GPIO1 (0 << 15) -#define GPR_GPR26_GPIO_MUX1_GPIO15_SEL_GPIO6 (1 << 15) -#define GPR_GPR26_GPIO_MUX1_GPIO16_SEL_GPIO1 (0 << 16) -#define GPR_GPR26_GPIO_MUX1_GPIO16_SEL_GPIO6 (1 << 16) -#define GPR_GPR26_GPIO_MUX1_GPIO17_SEL_GPIO1 (0 << 17) -#define GPR_GPR26_GPIO_MUX1_GPIO17_SEL_GPIO6 (1 << 17) -#define GPR_GPR26_GPIO_MUX1_GPIO18_SEL_GPIO1 (0 << 18) -#define GPR_GPR26_GPIO_MUX1_GPIO18_SEL_GPIO6 (1 << 18) -#define GPR_GPR26_GPIO_MUX1_GPIO19_SEL_GPIO1 (0 << 19) -#define GPR_GPR26_GPIO_MUX1_GPIO19_SEL_GPIO6 (1 << 19) -#define GPR_GPR26_GPIO_MUX1_GPIO20_SEL_GPIO1 (0 << 20) -#define GPR_GPR26_GPIO_MUX1_GPIO20_SEL_GPIO6 (1 << 20) -#define GPR_GPR26_GPIO_MUX1_GPIO21_SEL_GPIO1 (0 << 21) -#define GPR_GPR26_GPIO_MUX1_GPIO21_SEL_GPIO6 (1 << 21) -#define GPR_GPR26_GPIO_MUX1_GPIO22_SEL_GPIO1 (0 << 22) -#define GPR_GPR26_GPIO_MUX1_GPIO22_SEL_GPIO6 (1 << 22) -#define GPR_GPR26_GPIO_MUX1_GPIO23_SEL_GPIO1 (0 << 23) -#define GPR_GPR26_GPIO_MUX1_GPIO23_SEL_GPIO6 (1 << 23) -#define GPR_GPR26_GPIO_MUX1_GPIO24_SEL_GPIO1 (0 << 24) -#define GPR_GPR26_GPIO_MUX1_GPIO24_SEL_GPIO6 (1 << 24) -#define GPR_GPR26_GPIO_MUX1_GPIO25_SEL_GPIO1 (0 << 25) -#define GPR_GPR26_GPIO_MUX1_GPIO25_SEL_GPIO6 (1 << 25) -#define GPR_GPR26_GPIO_MUX1_GPIO26_SEL_GPIO1 (0 << 26) -#define GPR_GPR26_GPIO_MUX1_GPIO26_SEL_GPIO6 (1 << 26) -#define GPR_GPR26_GPIO_MUX1_GPIO27_SEL_GPIO1 (0 << 27) -#define GPR_GPR26_GPIO_MUX1_GPIO27_SEL_GPIO6 (1 << 27) -#define GPR_GPR26_GPIO_MUX1_GPIO28_SEL_GPIO1 (0 << 28) -#define GPR_GPR26_GPIO_MUX1_GPIO28_SEL_GPIO6 (1 << 28) -#define GPR_GPR26_GPIO_MUX1_GPIO29_SEL_GPIO1 (0 << 29) -#define GPR_GPR26_GPIO_MUX1_GPIO29_SEL_GPIO6 (1 << 29) -#define GPR_GPR26_GPIO_MUX1_GPIO30_SEL_GPIO1 (0 << 30) -#define GPR_GPR26_GPIO_MUX1_GPIO30_SEL_GPIO6 (1 << 30) -#define GPR_GPR26_GPIO_MUX1_GPIO31_SEL_GPIO1 (0 << 31) -#define GPR_GPR26_GPIO_MUX1_GPIO31_SEL_GPIO6 (1 << 31) - -/* General Purpose Register 27 (GPR27) */ - -#define GPR_GPR27_GPIO_MUX2_GPIO0_SEL_GPIO2 (0 << 0) -#define GPR_GPR27_GPIO_MUX2_GPIO0_SEL_GPIO7 (1 << 0) -#define GPR_GPR27_GPIO_MUX2_GPIO1_SEL_GPIO2 (0 << 1) -#define GPR_GPR27_GPIO_MUX2_GPIO1_SEL_GPIO7 (1 << 1) -#define GPR_GPR27_GPIO_MUX2_GPIO2_SEL_GPIO2 (0 << 2) -#define GPR_GPR27_GPIO_MUX2_GPIO2_SEL_GPIO7 (1 << 2) -#define GPR_GPR27_GPIO_MUX2_GPIO3_SEL_GPIO2 (0 << 3) -#define GPR_GPR27_GPIO_MUX2_GPIO3_SEL_GPIO7 (1 << 3) -#define GPR_GPR27_GPIO_MUX2_GPIO4_SEL_GPIO2 (0 << 4) -#define GPR_GPR27_GPIO_MUX2_GPIO4_SEL_GPIO7 (1 << 4) -#define GPR_GPR27_GPIO_MUX2_GPIO5_SEL_GPIO2 (0 << 5) -#define GPR_GPR27_GPIO_MUX2_GPIO5_SEL_GPIO7 (1 << 5) -#define GPR_GPR27_GPIO_MUX2_GPIO6_SEL_GPIO2 (0 << 6) -#define GPR_GPR27_GPIO_MUX2_GPIO6_SEL_GPIO7 (1 << 6) -#define GPR_GPR27_GPIO_MUX2_GPIO7_SEL_GPIO2 (0 << 7) -#define GPR_GPR27_GPIO_MUX2_GPIO7_SEL_GPIO7 (1 << 7) -#define GPR_GPR27_GPIO_MUX2_GPIO8_SEL_GPIO2 (0 << 8) -#define GPR_GPR27_GPIO_MUX2_GPIO8_SEL_GPIO7 (1 << 8) -#define GPR_GPR27_GPIO_MUX2_GPIO9_SEL_GPIO2 (0 << 9) -#define GPR_GPR27_GPIO_MUX2_GPIO9_SEL_GPIO7 (1 << 9) -#define GPR_GPR27_GPIO_MUX2_GPIO10_SEL_GPIO2 (0 << 10) -#define GPR_GPR27_GPIO_MUX2_GPIO10_SEL_GPIO7 (1 << 10) -#define GPR_GPR27_GPIO_MUX2_GPIO11_SEL_GPIO2 (0 << 11) -#define GPR_GPR27_GPIO_MUX2_GPIO11_SEL_GPIO7 (1 << 11) -#define GPR_GPR27_GPIO_MUX2_GPIO12_SEL_GPIO2 (0 << 12) -#define GPR_GPR27_GPIO_MUX2_GPIO12_SEL_GPIO7 (1 << 12) -#define GPR_GPR27_GPIO_MUX2_GPIO13_SEL_GPIO2 (0 << 13) -#define GPR_GPR27_GPIO_MUX2_GPIO13_SEL_GPIO7 (1 << 13) -#define GPR_GPR27_GPIO_MUX2_GPIO14_SEL_GPIO2 (0 << 14) -#define GPR_GPR27_GPIO_MUX2_GPIO14_SEL_GPIO7 (1 << 14) -#define GPR_GPR27_GPIO_MUX2_GPIO15_SEL_GPIO2 (0 << 15) -#define GPR_GPR27_GPIO_MUX2_GPIO15_SEL_GPIO7 (1 << 15) -#define GPR_GPR27_GPIO_MUX2_GPIO16_SEL_GPIO2 (0 << 16) -#define GPR_GPR27_GPIO_MUX2_GPIO16_SEL_GPIO7 (1 << 16) -#define GPR_GPR27_GPIO_MUX2_GPIO17_SEL_GPIO2 (0 << 17) -#define GPR_GPR27_GPIO_MUX2_GPIO17_SEL_GPIO7 (1 << 17) -#define GPR_GPR27_GPIO_MUX2_GPIO18_SEL_GPIO2 (0 << 18) -#define GPR_GPR27_GPIO_MUX2_GPIO18_SEL_GPIO7 (1 << 18) -#define GPR_GPR27_GPIO_MUX2_GPIO19_SEL_GPIO2 (0 << 19) -#define GPR_GPR27_GPIO_MUX2_GPIO19_SEL_GPIO7 (1 << 19) -#define GPR_GPR27_GPIO_MUX2_GPIO20_SEL_GPIO2 (0 << 20) -#define GPR_GPR27_GPIO_MUX2_GPIO20_SEL_GPIO7 (1 << 20) -#define GPR_GPR27_GPIO_MUX2_GPIO21_SEL_GPIO2 (0 << 21) -#define GPR_GPR27_GPIO_MUX2_GPIO21_SEL_GPIO7 (1 << 21) -#define GPR_GPR27_GPIO_MUX2_GPIO22_SEL_GPIO2 (0 << 22) -#define GPR_GPR27_GPIO_MUX2_GPIO22_SEL_GPIO7 (1 << 22) -#define GPR_GPR27_GPIO_MUX2_GPIO23_SEL_GPIO2 (0 << 23) -#define GPR_GPR27_GPIO_MUX2_GPIO23_SEL_GPIO7 (1 << 23) -#define GPR_GPR27_GPIO_MUX2_GPIO24_SEL_GPIO2 (0 << 24) -#define GPR_GPR27_GPIO_MUX2_GPIO24_SEL_GPIO7 (1 << 24) -#define GPR_GPR27_GPIO_MUX2_GPIO25_SEL_GPIO2 (0 << 25) -#define GPR_GPR27_GPIO_MUX2_GPIO25_SEL_GPIO7 (1 << 25) -#define GPR_GPR27_GPIO_MUX2_GPIO26_SEL_GPIO2 (0 << 26) -#define GPR_GPR27_GPIO_MUX2_GPIO26_SEL_GPIO7 (1 << 26) -#define GPR_GPR27_GPIO_MUX2_GPIO27_SEL_GPIO2 (0 << 27) -#define GPR_GPR27_GPIO_MUX2_GPIO27_SEL_GPIO7 (1 << 27) -#define GPR_GPR27_GPIO_MUX2_GPIO28_SEL_GPIO2 (0 << 28) -#define GPR_GPR27_GPIO_MUX2_GPIO28_SEL_GPIO7 (1 << 28) -#define GPR_GPR27_GPIO_MUX2_GPIO29_SEL_GPIO2 (0 << 29) -#define GPR_GPR27_GPIO_MUX2_GPIO29_SEL_GPIO7 (1 << 29) -#define GPR_GPR27_GPIO_MUX2_GPIO30_SEL_GPIO2 (0 << 30) -#define GPR_GPR27_GPIO_MUX2_GPIO30_SEL_GPIO7 (1 << 30) -#define GPR_GPR27_GPIO_MUX2_GPIO31_SEL_GPIO2 (0 << 31) -#define GPR_GPR27_GPIO_MUX2_GPIO31_SEL_GPIO7 (1 << 31) - -/* General Purpose Register 28 (GPR28) */ - -#define GPR_GPR28_GPIO_MUX3_GPIO0_SEL_GPIO3 (0 << 0) -#define GPR_GPR28_GPIO_MUX3_GPIO0_SEL_GPIO8 (1 << 0) -#define GPR_GPR28_GPIO_MUX3_GPIO1_SEL_GPIO3 (0 << 1) -#define GPR_GPR28_GPIO_MUX3_GPIO1_SEL_GPIO8 (1 << 1) -#define GPR_GPR28_GPIO_MUX3_GPIO2_SEL_GPIO3 (0 << 2) -#define GPR_GPR28_GPIO_MUX3_GPIO2_SEL_GPIO8 (1 << 2) -#define GPR_GPR28_GPIO_MUX3_GPIO3_SEL_GPIO3 (0 << 3) -#define GPR_GPR28_GPIO_MUX3_GPIO3_SEL_GPIO8 (1 << 3) -#define GPR_GPR28_GPIO_MUX3_GPIO4_SEL_GPIO3 (0 << 4) -#define GPR_GPR28_GPIO_MUX3_GPIO4_SEL_GPIO8 (1 << 4) -#define GPR_GPR28_GPIO_MUX3_GPIO5_SEL_GPIO3 (0 << 5) -#define GPR_GPR28_GPIO_MUX3_GPIO5_SEL_GPIO8 (1 << 5) -#define GPR_GPR28_GPIO_MUX3_GPIO6_SEL_GPIO3 (0 << 6) -#define GPR_GPR28_GPIO_MUX3_GPIO6_SEL_GPIO8 (1 << 6) -#define GPR_GPR28_GPIO_MUX3_GPIO7_SEL_GPIO3 (0 << 7) -#define GPR_GPR28_GPIO_MUX3_GPIO7_SEL_GPIO8 (1 << 7) -#define GPR_GPR28_GPIO_MUX3_GPIO8_SEL_GPIO3 (0 << 8) -#define GPR_GPR28_GPIO_MUX3_GPIO8_SEL_GPIO8 (1 << 8) -#define GPR_GPR28_GPIO_MUX3_GPIO9_SEL_GPIO3 (0 << 9) -#define GPR_GPR28_GPIO_MUX3_GPIO9_SEL_GPIO8 (1 << 9) -#define GPR_GPR28_GPIO_MUX3_GPIO10_SEL_GPIO3 (0 << 10) -#define GPR_GPR28_GPIO_MUX3_GPIO10_SEL_GPIO8 (1 << 10) -#define GPR_GPR28_GPIO_MUX3_GPIO11_SEL_GPIO3 (0 << 11) -#define GPR_GPR28_GPIO_MUX3_GPIO11_SEL_GPIO8 (1 << 11) -#define GPR_GPR28_GPIO_MUX3_GPIO12_SEL_GPIO3 (0 << 12) -#define GPR_GPR28_GPIO_MUX3_GPIO12_SEL_GPIO8 (1 << 12) -#define GPR_GPR28_GPIO_MUX3_GPIO13_SEL_GPIO3 (0 << 13) -#define GPR_GPR28_GPIO_MUX3_GPIO13_SEL_GPIO8 (1 << 13) -#define GPR_GPR28_GPIO_MUX3_GPIO14_SEL_GPIO3 (0 << 14) -#define GPR_GPR28_GPIO_MUX3_GPIO14_SEL_GPIO8 (1 << 14) -#define GPR_GPR28_GPIO_MUX3_GPIO15_SEL_GPIO3 (0 << 15) -#define GPR_GPR28_GPIO_MUX3_GPIO15_SEL_GPIO8 (1 << 15) -#define GPR_GPR28_GPIO_MUX3_GPIO16_SEL_GPIO3 (0 << 16) -#define GPR_GPR28_GPIO_MUX3_GPIO16_SEL_GPIO8 (1 << 16) -#define GPR_GPR28_GPIO_MUX3_GPIO17_SEL_GPIO3 (0 << 17) -#define GPR_GPR28_GPIO_MUX3_GPIO17_SEL_GPIO8 (1 << 17) -#define GPR_GPR28_GPIO_MUX3_GPIO18_SEL_GPIO3 (0 << 18) -#define GPR_GPR28_GPIO_MUX3_GPIO18_SEL_GPIO8 (1 << 18) -#define GPR_GPR28_GPIO_MUX3_GPIO19_SEL_GPIO3 (0 << 19) -#define GPR_GPR28_GPIO_MUX3_GPIO19_SEL_GPIO8 (1 << 19) -#define GPR_GPR28_GPIO_MUX3_GPIO20_SEL_GPIO3 (0 << 20) -#define GPR_GPR28_GPIO_MUX3_GPIO20_SEL_GPIO8 (1 << 20) -#define GPR_GPR28_GPIO_MUX3_GPIO21_SEL_GPIO3 (0 << 21) -#define GPR_GPR28_GPIO_MUX3_GPIO21_SEL_GPIO8 (1 << 21) -#define GPR_GPR28_GPIO_MUX3_GPIO22_SEL_GPIO3 (0 << 22) -#define GPR_GPR28_GPIO_MUX3_GPIO22_SEL_GPIO8 (1 << 22) -#define GPR_GPR28_GPIO_MUX3_GPIO23_SEL_GPIO3 (0 << 23) -#define GPR_GPR28_GPIO_MUX3_GPIO23_SEL_GPIO8 (1 << 23) -#define GPR_GPR28_GPIO_MUX3_GPIO24_SEL_GPIO3 (0 << 24) -#define GPR_GPR28_GPIO_MUX3_GPIO24_SEL_GPIO8 (1 << 24) -#define GPR_GPR28_GPIO_MUX3_GPIO25_SEL_GPIO3 (0 << 25) -#define GPR_GPR28_GPIO_MUX3_GPIO25_SEL_GPIO8 (1 << 25) -#define GPR_GPR28_GPIO_MUX3_GPIO26_SEL_GPIO3 (0 << 26) -#define GPR_GPR28_GPIO_MUX3_GPIO26_SEL_GPIO8 (1 << 26) -#define GPR_GPR28_GPIO_MUX3_GPIO27_SEL_GPIO3 (0 << 27) -#define GPR_GPR28_GPIO_MUX3_GPIO27_SEL_GPIO8 (1 << 27) -#define GPR_GPR28_GPIO_MUX3_GPIO28_SEL_GPIO3 (0 << 28) -#define GPR_GPR28_GPIO_MUX3_GPIO28_SEL_GPIO8 (1 << 28) -#define GPR_GPR28_GPIO_MUX3_GPIO29_SEL_GPIO3 (0 << 29) -#define GPR_GPR28_GPIO_MUX3_GPIO29_SEL_GPIO8 (1 << 29) -#define GPR_GPR28_GPIO_MUX3_GPIO30_SEL_GPIO3 (0 << 30) -#define GPR_GPR28_GPIO_MUX3_GPIO30_SEL_GPIO8 (1 << 30) -#define GPR_GPR28_GPIO_MUX3_GPIO31_SEL_GPIO3 (0 << 31) -#define GPR_GPR28_GPIO_MUX3_GPIO31_SEL_GPIO8 (1 << 31) - -/* General Purpose Register 29 (GPR29) */ - -#define GPR_GPR29_GPIO_MUX4_GPIO0_SEL_GPIO4 (0 << 0) -#define GPR_GPR29_GPIO_MUX4_GPIO0_SEL_GPIO9 (1 << 0) -#define GPR_GPR29_GPIO_MUX4_GPIO1_SEL_GPIO4 (0 << 1) -#define GPR_GPR29_GPIO_MUX4_GPIO1_SEL_GPIO9 (1 << 1) -#define GPR_GPR29_GPIO_MUX4_GPIO2_SEL_GPIO4 (0 << 2) -#define GPR_GPR29_GPIO_MUX4_GPIO2_SEL_GPIO9 (1 << 2) -#define GPR_GPR29_GPIO_MUX4_GPIO3_SEL_GPIO4 (0 << 3) -#define GPR_GPR29_GPIO_MUX4_GPIO3_SEL_GPIO9 (1 << 3) -#define GPR_GPR29_GPIO_MUX4_GPIO4_SEL_GPIO4 (0 << 4) -#define GPR_GPR29_GPIO_MUX4_GPIO4_SEL_GPIO9 (1 << 4) -#define GPR_GPR29_GPIO_MUX4_GPIO5_SEL_GPIO4 (0 << 5) -#define GPR_GPR29_GPIO_MUX4_GPIO5_SEL_GPIO9 (1 << 5) -#define GPR_GPR29_GPIO_MUX4_GPIO6_SEL_GPIO4 (0 << 6) -#define GPR_GPR29_GPIO_MUX4_GPIO6_SEL_GPIO9 (1 << 6) -#define GPR_GPR29_GPIO_MUX4_GPIO7_SEL_GPIO4 (0 << 7) -#define GPR_GPR29_GPIO_MUX4_GPIO7_SEL_GPIO9 (1 << 7) -#define GPR_GPR29_GPIO_MUX4_GPIO8_SEL_GPIO4 (0 << 8) -#define GPR_GPR29_GPIO_MUX4_GPIO8_SEL_GPIO9 (1 << 8) -#define GPR_GPR29_GPIO_MUX4_GPIO9_SEL_GPIO4 (0 << 9) -#define GPR_GPR29_GPIO_MUX4_GPIO9_SEL_GPIO9 (1 << 9) -#define GPR_GPR29_GPIO_MUX4_GPIO10_SEL_GPIO4 (0 << 10) -#define GPR_GPR29_GPIO_MUX4_GPIO10_SEL_GPIO9 (1 << 10) -#define GPR_GPR29_GPIO_MUX4_GPIO11_SEL_GPIO4 (0 << 11) -#define GPR_GPR29_GPIO_MUX4_GPIO11_SEL_GPIO9 (1 << 11) -#define GPR_GPR29_GPIO_MUX4_GPIO12_SEL_GPIO4 (0 << 12) -#define GPR_GPR29_GPIO_MUX4_GPIO12_SEL_GPIO9 (1 << 12) -#define GPR_GPR29_GPIO_MUX4_GPIO13_SEL_GPIO4 (0 << 13) -#define GPR_GPR29_GPIO_MUX4_GPIO13_SEL_GPIO9 (1 << 13) -#define GPR_GPR29_GPIO_MUX4_GPIO14_SEL_GPIO4 (0 << 14) -#define GPR_GPR29_GPIO_MUX4_GPIO14_SEL_GPIO9 (1 << 14) -#define GPR_GPR29_GPIO_MUX4_GPIO15_SEL_GPIO4 (0 << 15) -#define GPR_GPR29_GPIO_MUX4_GPIO15_SEL_GPIO9 (1 << 15) -#define GPR_GPR29_GPIO_MUX4_GPIO16_SEL_GPIO4 (0 << 16) -#define GPR_GPR29_GPIO_MUX4_GPIO16_SEL_GPIO9 (1 << 16) -#define GPR_GPR29_GPIO_MUX4_GPIO17_SEL_GPIO4 (0 << 17) -#define GPR_GPR29_GPIO_MUX4_GPIO17_SEL_GPIO9 (1 << 17) -#define GPR_GPR29_GPIO_MUX4_GPIO18_SEL_GPIO4 (0 << 18) -#define GPR_GPR29_GPIO_MUX4_GPIO18_SEL_GPIO9 (1 << 18) -#define GPR_GPR29_GPIO_MUX4_GPIO19_SEL_GPIO4 (0 << 19) -#define GPR_GPR29_GPIO_MUX4_GPIO19_SEL_GPIO9 (1 << 19) -#define GPR_GPR29_GPIO_MUX4_GPIO20_SEL_GPIO4 (0 << 20) -#define GPR_GPR29_GPIO_MUX4_GPIO20_SEL_GPIO9 (1 << 20) -#define GPR_GPR29_GPIO_MUX4_GPIO21_SEL_GPIO4 (0 << 21) -#define GPR_GPR29_GPIO_MUX4_GPIO21_SEL_GPIO9 (1 << 21) -#define GPR_GPR29_GPIO_MUX4_GPIO22_SEL_GPIO4 (0 << 22) -#define GPR_GPR29_GPIO_MUX4_GPIO22_SEL_GPIO9 (1 << 22) -#define GPR_GPR29_GPIO_MUX4_GPIO23_SEL_GPIO4 (0 << 23) -#define GPR_GPR29_GPIO_MUX4_GPIO23_SEL_GPIO9 (1 << 23) -#define GPR_GPR29_GPIO_MUX4_GPIO24_SEL_GPIO4 (0 << 24) -#define GPR_GPR29_GPIO_MUX4_GPIO24_SEL_GPIO9 (1 << 24) -#define GPR_GPR29_GPIO_MUX4_GPIO25_SEL_GPIO4 (0 << 25) -#define GPR_GPR29_GPIO_MUX4_GPIO25_SEL_GPIO9 (1 << 25) -#define GPR_GPR29_GPIO_MUX4_GPIO26_SEL_GPIO4 (0 << 26) -#define GPR_GPR29_GPIO_MUX4_GPIO26_SEL_GPIO9 (1 << 26) -#define GPR_GPR29_GPIO_MUX4_GPIO27_SEL_GPIO4 (0 << 27) -#define GPR_GPR29_GPIO_MUX4_GPIO27_SEL_GPIO9 (1 << 27) -#define GPR_GPR29_GPIO_MUX4_GPIO28_SEL_GPIO4 (0 << 28) -#define GPR_GPR29_GPIO_MUX4_GPIO28_SEL_GPIO9 (1 << 28) -#define GPR_GPR29_GPIO_MUX4_GPIO29_SEL_GPIO4 (0 << 29) -#define GPR_GPR29_GPIO_MUX4_GPIO29_SEL_GPIO9 (1 << 29) -#define GPR_GPR29_GPIO_MUX4_GPIO30_SEL_GPIO4 (0 << 30) -#define GPR_GPR29_GPIO_MUX4_GPIO30_SEL_GPIO9 (1 << 30) -#define GPR_GPR29_GPIO_MUX4_GPIO31_SEL_GPIO4 (0 << 31) -#define GPR_GPR29_GPIO_MUX4_GPIO31_SEL_GPIO9 (1 << 31) - -/* General Purpose Register 30 (GPR30) */ - -#define GPR_GPR30_FLEXSPI_REMAP_ADDR_START_SHIFT (12) -#define GPR_GPR30_FLEXSPI_REMAP_ADDR_START_MASK (1 << GPR_GPR30_FLEXSPI_REMAP_ADDR_START_SHIFT) -# define GPR_GPR30_FLEXSPI_REMAP_ADDR_START(n) ((uint32_t)(n) << GPR_GPR30_FLEXSPI_REMAP_ADDR_START_SHIFT) - -/* General Purpose Register 31 (GPR31) */ - -#define GPR_GPR31_FLEXSPI_REMAP_ADDR_END_SHIFT (12) -#define GPR_GPR31_FLEXSPI_REMAP_ADDR_END_MASK (1 << GPR_GPR31_FLEXSPI_REMAP_ADDR_END_SHIFT) -# define GPR_GPR31_FLEXSPI_REMAP_ADDR_END(n) ((uint32_t)(n) << GPR_GPR31_FLEXSPI_REMAP_ADDR_END_SHIFT) - -/* General Purpose Register 32 (GPR32) */ - -#define GPR_GPR32_FLEXSPI_REMAP_ADDR_OFFSET_SHIFT (12) -#define GPR_GPR32_FLEXSPI_REMAP_ADDR_OFFSET_MASK (1 << GPR_GPR32_FLEXSPI_REMAP_ADDR_OFFSET_SHIFT) -# define GPR_GPR32_FLEXSPI_REMAP_ADDR_OFFSET(n) ((uint32_t)(n) << GPR_GPR32_FLEXSPI_REMAP_ADDR_OFFSET_SHIFT) - -/* General Purpose Register 33 (GPR33) */ - -#define GPR_GPR33_OCRAM2_TZ_EN (1 << 0) -#define GPR_GPR33_OCRAM2_TZ_ADDR_SHIFT (8) -#define GPR_GPR33_OCRAM2_TZ_ADDR_MASK (0x3f << GPR_GPR33_OCRAM2_TZ_ADDR_SHIFT) -# define GPR_GPR33_OCRAM2_TZ_ADDR(n) ((uint32_t)(n) << GPR_GPR33_OCRAM2_TZ_ADDR_SHIFT) -#define GPR_GPR33_LOCK_OCRAM2_TZ_EN (1 << 16) -#define GPR_GPR33_LOCK_OCRAM2_TZ_ADDR_SHIFT (17) -#define GPR_GPR33_LOCK_OCRAM2_TZ_ADDR_MASK (0x3f << GPR_GPR33_LOCK_OCRAM2_TZ_ADDR_SHIFT) -# define GPR_GPR33_LOCK_OCRAM2_TZ_ADDR(n) ((uint32_t)(n) << GPR_GPR33_LOCK_OCRAM2_TZ_ADDR_SHIFT) - -/* General Purpose Register 34 (GPR34) */ - -#define GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL_SHIFT (0) -#define GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL_MASK (0xff << GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL_SHIFT) -#define GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL(n) ((uint32_t)(n) << GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL_SHIFT) -#define GPR_GPR34_SIP_TEST_MUX_QSPI_SIP_EN (1 << 8) - -#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_IOMUXC_H */ diff --git a/arch/arm/src/imxrt/chip/rt106x/imxrt106x_memorymap.h b/arch/arm/src/imxrt/chip/rt106x/imxrt106x_memorymap.h deleted file mode 100644 index 327dfb9d7f1..00000000000 --- a/arch/arm/src/imxrt/chip/rt106x/imxrt106x_memorymap.h +++ /dev/null @@ -1,301 +0,0 @@ -/************************************************************************************ - * arch/arm/src/imxrt/chip/rt106x/imxrt106x_memorymap.h - * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * David Sidrane - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_MEMORYMAP_H -#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_MEMORYMAP_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* System memory map */ - -#define IMXRT_ITCM_BASE 0x00000000 /* 512KB ITCM */ - /* 0x00080000 512KB ITCM Reserved */ - /* 0x00100000 1MB ITCM Reserved */ -#define IMXRT_ROMCP_BASE 0x00200000 /* 128KB ROMCP */ - /* 0x00220000 384KB ROMCP Reserved */ - /* 0x00280000 1536KB Reserved */ - /* 0x00400000 124MB Reserved */ -#define IMXRT_FLEXSPI_BASE 0x08000000 /* 128MB FlexSPI (Aliased) */ -#define IMXRT_SEMCA_BASE 0x10000000 /* 256MB SEMC (Aliased) */ -#define IMXRT_DTCM_BASE 0x20000000 /* 512KB DTCM */ - /* 0x20080000 512KB DTCM Reserved */ - /* 0x20100000 1MB Reserved */ -#define IMXRT_OCRAM2_BASE 0x20200000 /* 512KB OCRAM2 */ -#define IMXRT_OCRAM_BASE 0x20280000 /* 512KB OCRAM FlexRAM */ - /* 0x20300000 512KB OCRAM Reserved */ - /* 0x20400000 252MB Reserved */ - /* 0x30000000 256MB Reserved */ -#define IMXRT_AIPS1_BASE 0x40000000 /* 1MB AIPS-1 */ -#define IMXRT_AIPS2_BASE 0x40100000 /* 1MB AIPS-2 */ -#define IMXRT_AIPS3_BASE 0x40200000 /* 1MB AIPS-3 */ -#define IMXRT_AIPS4_BASE 0x40300000 /* 1MB AIPS-4 */ - /* 40400000 12MB Reserved */ -#define IMXRT_MAINCNF_BASE 0x41000000 /* 1MB "main" configuration port */ -#define IMXRT_MCNF_BASE 0x41100000 /* 1MB "m" configuration port */ - /* 41200000 1MB Reserved for "per" GPV */ - /* 41300000 1MB Reserved for "ems" GPV */ -#define IMXRT_CPUCNF_BASE 0x41400000 /* 1MB "cpu" configuration port */ - /* 0x41500000 1MB GPV Reserved */ - /* 0x41600000 1MB GPV Reserved */ - /* 0x41700000 1MB GPV Reserved */ - /* 0x41800000 8MB Reserved */ -#define IMXRT_AIPS5_BASE 0x42000000 /* 1MB AIPS-5 */ - /* 0x42100000 31MB Reserved */ - /* 0x44000000 64MB Reserved */ - /* 0x48000000 384MB Reserved */ -#define IMXRT_FLEXCIPHER_BASE 0x60000000 /* 256MB FlexSPI/ FlexSPI ciphertext */ -#define IMXRT_FLEX2CIPHER_BASE 0x70000000 /* 240MB FlexSPI2/ FlexSPI ciphertext */ -#define IMXRT_FLEXSPI2TX_BASE 0x7f000000 /* 4MB FlexSPI2 TX FIFO */ -#define IMXRT_FLEXSPI2RX_BASE 0x7f400000 /* 4MB FlexSPI2 RX FIFO */ -#define IMXRT_FLEXSPITX_BASE 0x7f800000 /* 4MB FlexSPI TX FIFO */ -#define IMXRT_FLEXSPIRX_BASE 0x7fc00000 /* 4MB FlexSPI RX FIFO */ -#define IMXRT_EXTMEM_BASE 0x80000000 /* 1.5GB SEMC external memories shared memory space */ -#define IMXRT_CM7_BASE 0xe0000000 /* 1MB CM7 PPB */ - /* 0xe0100000 511MB Reserved */ - -/* AIPS-1 memory map */ - - /* 0x40000000 256KB Reserved */ - /* 0x40040000 240KB Reserved */ -#define IMXRT_AIPS1CNF_BASE 0x4007c000 /* 6KB AIPS-1 Configuration */ -#define IMXRT_DCDC_BASE 0x40080000 /* 16KB DCDC */ -#define IMXRT_PIT_BASE 0x40084000 /* 16KB PIT */ - /* 0x40088000 16KB Reserved */ - /* 0x4008c000 16KB Reserved */ -#define IMXRT_MTR_BASE 0x40090000 /* 16KB MTR */ -#define IMXRT_ACMP_BASE 0x40094000 /* 16KB ACMP */ - /* 0x40098000 16KB Reserved */ - /* 0x4009c000 16KB Reserved */ - /* 0x400a0000 16KB Reserved */ -#define IMXRT_IOMUXCSNVSGPR_BASE 0x400a4000 /* 16KB IOMUXC_SNVS_GPR */ -#define IMXRT_IOMUXCSNVS_BASE 0x400a8000 /* 16KB IOMUXC_SNVS */ -#define IMXRT_IOMUXCGPR_BASE 0x400ac000 /* 16KB IOMUXC_GPR */ -#define IMXRT_FLEXRAM_BASE 0x400b0000 /* 16KB CM7_MX6RT(FLEXRAM) */ -#define IMXRT_EWM_BASE 0x400b4000 /* 16KB EWM */ -#define IMXRT_WDOG1_BASE 0x400b8000 /* 16KB WDOG1 */ -#define IMXRT_WDOG3_BASE 0x400bc000 /* 16KB WDOG3 */ -#define IMXRT_GPIO5_BASE 0x400c0000 /* 16KB GPIO5 */ -#define IMXRT_ADC1_BASE 0x400c4000 /* 16KB ADC1 */ -#define IMXRT_ADC2_BASE 0x400c8000 /* 16KB ADC2 */ -#define IMXRT_TRNG_BASE 0x400cc000 /* 16KB TRNG */ -#define IMXRT_WDOG2_BASE 0x400d0000 /* 16KB WDOG2 */ -#define IMXRT_SNVSHP_BASE 0x400d4000 /* 16KB SNVS_HP */ -#define IMXRT_ANATOP_BASE 0x400d8000 /* 16KB ANATOP */ -#define IMXRT_CSU_BASE 0x400dc000 /* 16KB CSU */ - /* 0x400e0000 16KB Reserved */ - /* 0x400e4000 16KB Reserved */ -#define IMXRT_EDMA_BASE 0x400e8000 /* 16KB EDMA */ -#define IMXRT_DMAMUX_BASE 0x400ec000 /* 16KB DMA_CH_MUX */ - /* 400f0000 16KB Reserved */ -#define IMXRT_GPC_BASE 0x400f4000 /* 16KB GPC */ -#define IMXRT_SRC_BASE 0x400f8000 /* 16KB SRC */ -#define IMXRT_CCM_BASE 0x400fc000 /* 16KB CCM */ - -/* AIPS-2 memory map */ - - /* 0x40100000 256KB Reserved */ - /* 0x40140000 240KB Reserved */ -#define IMXRT_AIPS2CNF_BASE 0x4017c000 /* 16KB AIPS-2 Configuration */ -#define IMXRT_ROMCPC_BASE 0x40180000 /* 16KB ROMCP controller*/ -#define IMXRT_LPUART1_BASE 0x40184000 /* 16KB LPUART1 */ -#define IMXRT_LPUART2_BASE 0x40188000 /* 16KB LPUART2 */ -#define IMXRT_LPUART3_BASE 0x4018c000 /* 16KB LPUART3 */ -#define IMXRT_LPUART4_BASE 0x40190000 /* 16KB LPUART4 */ -#define IMXRT_LPUART5_BASE 0x40194000 /* 16KB LPUART5 */ -#define IMXRT_LPUART6_BASE 0x40198000 /* 16KB LPUART6 */ -#define IMXRT_LPUART7_BASE 0x4019c000 /* 16KB LPUART7 */ -#define IMXRT_LPUART8_BASE 0x401a0000 /* 16KB LPUART8 */ - /* 0x401a4000 16KB Reserved */ - /* 0x401a8000 16KB Reserved */ -#define IMXRT_FLEXIO1_BASE 0x401ac000 /* 16KB FlexIO1 */ -#define IMXRT_FLEXIO2_BASE 0x401b0000 /* 16KB FlexIO2 */ - /* 0x401b4000 16KB Reserved */ -#define IMXRT_GPIO1_BASE 0x401b8000 /* 16KB GPIO1 */ -#define IMXRT_GPIO2_BASE 0x401bc000 /* 16KB GPIO2 */ -#define IMXRT_GPIO3_BASE 0x401c0000 /* 16KB GPIO3 */ -#define IMXRT_GPIO4_BASE 0x401c4000 /* 16KB GPIO4 */ - /* 0x401c8000 16KB Reserved */ - /* 0x401cc000 16KB Reserved */ -#define IMXRT_CAN1_BASE 0x401d0000 /* 16KB CAN1 */ -#define IMXRT_CAN2_BASE 0x401d4000 /* 16KB CAN2 */ -#define IMXRT_CAN3_BASE 0x401d8000 /* 16KB CAN3 */ -#define IMXRT_QTIMER1_BASE 0x401dc000 /* 16KB QTimer1 */ -#define IMXRT_QTIMER2_BASE 0x401e0000 /* 16KB QTimer2 */ -#define IMXRT_QTIMER3_BASE 0x401e4000 /* 16KB QTimer3 */ -#define IMXRT_QTIMER4_BASE 0x401e8000 /* 16KB QTimer4 */ -#define IMXRT_GPT1_BASE 0x401ec000 /* 16KB GPT1 */ -#define IMXRT_GPT2_BASE 0x401f0000 /* 16KB GPT2 */ -#define IMXRT_OCOTP_BASE 0x401f4000 /* 16KB OCOTP */ -#define IMXRT_IOMUXC_BASE 0x401f8000 /* 16KB IOMUXC */ -#define IMXRT_KPP_BASE 0x401fc000 /* 16KB KPP */ - -/* AIPS-3 memory map */ - - /* 0x40200000 256KB Reserved */ - /* 0x40240000 240KB Reserved */ -#define IMXRT_AIOS3CNF_BASE 0x4027c000 /* 16KB AIPS-3 Configuration */ - /* 0x40280000 16KB Reserved */ - /* 0x40284000 16KB Reserved */ - /* 0x40288000 16KB Reserved */ - /* 0x4028c000 16KB Reserved */ - /* 0x40290000 16KB Reserved */ - /* 0x40294000 16KB Reserved */ - /* 0x40298000 16KB Reserved */ - /* 0x4029c000 16KB Reserved */ - /* 0x402a0000 16KB Reserved */ -#define IMXRT_FLEXSPI2C_BASE 0x402a4000 /* 16KB FlexSPI2 */ -#define IMXRT_FLEXSPIC_BASE 0x402a8000 /* 16KB FlexSPI */ - /* 0x402ac000 16KB Reserved */ - /* 0x402b0000 16KB Reserved */ -#define IMXRT_PXP_BASE 0x402b4000 /* 16KB PXP */ -#define IMXRT_LCDIF_BASE 0x402b8000 /* 16KB LCDIF */ -#define IMXRT_CSI_BASE 0x402bc000 /* 16KB CSI */ -#define IMXRT_USDHC1_BASE 0x402c0000 /* 16KB USDHC1 */ -#define IMXRT_USDHC2_BASE 0x402c4000 /* 16KB USDHC2 */ - /* 0x402c8000 16KB Reserved */ - /* 0x402cc000 16KB Reserved */ - /* 0x402d0000 16KB Reserved */ - /* 0x402d4000 16KB Reserved */ -#define IMXRT_ENET2_BASE 0x402d4000 /* 16KB ENET2 */ -#define IMXRT_ENET_BASE 0x402d8000 /* 16KB ENET */ -#define IMXRT_USBPL301_BASE 0x402dc000 /* 16KB USB(PL301) */ -#define IMXRT_USB_BASE 0x402e0000 /* 16KB USB(USB) */ - /* 0x402e4000 16KB Reserved */ - /* 0x402e8000 16KB Reserved */ - /* 0x402ec000 16KB Reserved */ -#define IMXRT_SEMC_BASE 0x402f0000 /* 16KB SEMC */ - /* 0x402f4000 16KB Reserved */ - /* 0x402f8000 16KB Reserved */ -#define IMXRT_DCP_BASE 0x402fc000 /* 16KB DCP */ - -/* AIPS-4 memory map */ - - /* 0x40300000 256KB Reserved */ - /* 0x40340000 240KB Reserved */ -#define IMXRT_AIPS4CNF_BASE 0x4037c000 /* 16KB AIPS-4 Configuration */ -#define IMXRT_SPDIF_BASE 0x40380000 /* 16KB SPDIF */ -#define IMXRT_SAI1_BASE 0x40384000 /* 16KB SAI1 */ -#define IMXRT_SAI2_BASE 0x40388000 /* 16KB SAI2 */ -#define IMXRT_SAI3_BASE 0x4038c000 /* 16KB SAI3 */ - /* 0x40390000 16KB Reserved */ -#define IMXRT_LPSPI1_BASE 0x40394000 /* 16KB LPSPI1 */ -#define IMXRT_LPSPI2_BASE 0x40398000 /* 16KB LPSPI2 */ -#define IMXRT_LPSPI3_BASE 0x4039c000 /* 16KB LPSPI3 */ -#define IMXRT_LPSPI4_BASE 0x403a0000 /* 16KB LPSPI4 */ - /* 0x403a4000 16KB Reserved */ - /* 0x403a8000 16KB Reserved */ - /* 0x403ac000 16KB Reserved */ -#define IMXRT_ADCETC_BASE 0x403b0000 /* 16KB ADC_ETC */ -#define IMXRT_AOI1_BASE 0x403b4000 /* 16KB AOI1 */ -#define IMXRT_AOI2_BASE 0x403b8000 /* 16KB AOI2 */ -#define IMXRT_XBAR1_BASE 0x403bc000 /* 16KB XBAR1 */ -#define IMXRT_XBAR2_BASE 0x403c0000 /* 16KB XBAR2 */ -#define IMXRT_XBAR3_BASE 0x403c4000 /* 16KB XBAR3 */ -#define IMXRT_ENC1_BASE 0x403c8000 /* 16KB ENC1 */ -#define IMXRT_ENC2_BASE 0x403cc000 /* 16KB ENC2 */ -#define IMXRT_ENC3_BASE 0x403d0000 /* 16KB ENC3 */ -#define IMXRT_ENC4_BASE 0x403d4000 /* 16KB ENC4 */ - /* 0x403d8000 16KB Reserved */ -#define IMXRT_FLEXPWM1_BASE 0x403dc000 /* 16KB FLEXPWM1 */ -#define IMXRT_FLEXPWM2_BASE 0x403e0000 /* 16KB FLEXPWM2 */ -#define IMXRT_FLEXPWM3_BASE 0x403e4000 /* 16KB FLEXPWM3 */ -#define IMXRT_FLEXPWM4_BASE 0x403e8000 /* 16KB FLEXPWM4 */ -#define IMXRT_BEE_BASE 0x403ec000 /* 16KB BEE */ -#define IMXRT_LPI2C1_BASE 0x403f0000 /* 16KB */ -#define IMXRT_LPI2C2_BASE 0x403f4000 /* 16KB LPI2C2 */ -#define IMXRT_LPI2C3_BASE 0x403f8000 /* 16KB LPI2C3 */ -#define IMXRT_LPI2C4_BASE 0x403fc000 /* 16KB LPI2C4 */ - -/* AIPS-5 memory map */ - -#define IMXRT_GPIO6_BASE 0x42000000 /* 16KB GPIO6 */ -#define IMXRT_GPIO7_BASE 0x42004000 /* 16KB GPIO7 */ -#define IMXRT_GPIO8_BASE 0x42008000 /* 16KB GPIO8 */ -#define IMXRT_GPIO9_BASE 0x4200c000 /* 16KB GPIO9 */ - /* 0x42010000 16KB Reserved */ - /* 0x42014000 16KB Reserved */ - /* 0x42018000 16KB Reserved */ - /* 0x4201c000 16KB Reserved */ -#define IMXRT_FLEXIO3_BASE 0x42020000 /* 16KB FlexIO3 */ - /* 0x42024000 16KB Reserved */ - /* 0x42028000 16KB Reserved */ - /* 0x4202c000 16KB Reserved */ - /* 0x42030000 16KB Reserved */ - /* 0x42034000 16KB Reserved */ - /* 0x42038000 16KB Reserved */ - /* 0x4203c000 16KB Reserved */ - /* 0x42040000 16KB Reserved */ - /* 0x42044000 16KB Reserved */ - /* 0x42048000 16KB Reserved */ - /* 0x4204c000 16KB Reserved */ - /* 0x42050000 16KB Reserved */ - /* 0x42054000 16KB Reserved */ - /* 0x42058000 16KB Reserved */ - /* 0x4205c000 16KB Reserved */ - /* 0x42060000 16KB Reserved */ - /* 0x42064000 16KB Reserved */ - /* 0x42068000 16KB Reserved */ - /* 0x4206c000 16KB Reserved */ - /* 0x42070000 16KB Reserved */ - /* 0x42074000 16KB Reserved */ - /* 0x42078000 16KB Reserved */ - /* 0x4207c000 16KB Reserved */ - /* 0x42080000 512KB Reserved Off Platform */ - -/* PPB memory map */ - -#define IMXRT_TPIU_BASE 0xe0040000 /* 4KB TPIU */ -#define IMXRT_ETM_BASE 0xe0041000 /* 4KB ETM */ -#define IMXRT_CTI_BASE 0xe0042000 /* 4KB CTI */ -#define IMXRT_TSGEN_BASE 0xe0043000 /* 4KB TSGEN */ -#define IMXRT_PPBRES_BASE 0xe0044000 /* 4KB PPB RES */ - /* 0xe0045000 236KB PPB Reserved */ -#define IMXRT_MCM_BASE 0xe0080000 /* 4KB MCM */ - /* 0xe0081000 444KB PPB Reserved */ - /* 0xe00f0000 52KB PPB Reserved */ -#define IMXRT_SYSROM_BASE 0xe00fd000 /* 4KB SYS ROM */ -#define IMXRT_PROCROM_BASE 0xe00fe000 /* 4KB Processor ROM */ -#define IMXRT_PPBROM_BASE 0xe00ff000 /* 4KB PPB ROM */ - -#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_MEMORYMAP_H */ diff --git a/arch/arm/src/imxrt/chip/rt106x/imxrt106x_pinmux.h b/arch/arm/src/imxrt/chip/rt106x/imxrt106x_pinmux.h deleted file mode 100644 index edb3ed25581..00000000000 --- a/arch/arm/src/imxrt/chip/rt106x/imxrt106x_pinmux.h +++ /dev/null @@ -1,1095 +0,0 @@ -/***************************************************************************************************** - * arch/arm/src/imxrt/chip/rt106x/imxrt106x_pinmux.h - * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * David Sidrane - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *****************************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_PINMUX_H -#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_PINMUX_H - -/***************************************************************************************************** - * Included Files - *****************************************************************************************************/ - -#include -#include "chip/imxrt_iomuxc.h" - -/***************************************************************************************************** - * Pre-processor Definitions - *****************************************************************************************************/ - -/* Alternate Pin Functions. - * - * Alternative pin selections are provided with a numeric suffix like _1, _2, etc. Drivers, however, - * will use the pin selection without the numeric suffix. Additional definitions are required in the - * board.h file. For example, if LPUART1 CTS connects via the AD_B1_04 pin, then the following - * definition should appear in the board.h header file for that board: - * - * #define GPIO_LPUART3_CTS GPIO_LPUART3_CTS_1 - * - * The driver will then automatically configure to use the AD_B1_04 pin for LPUART1 CTS. - */ - -/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! - * Additional effort is required to select specific IOMUX options such as frequency, open-drain, - * push-pull, and pull-up/down! Just the basics are defined for most pins in this file. See the - * upper imxrt_gpio.h and imxrt_iomuxc.h header files for available definitions. - */ - -/* Analog Comparator (ACMP) */ - -#define GPIO_ACMP_OUT00 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_12_INDEX)) -#define GPIO_ACMP_OUT01 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_13_INDEX)) -#define GPIO_ACMP_OUT02 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_14_INDEX)) -#define GPIO_ACMP_OUT03 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_15_INDEX)) - -/* ARM */ - -#define GPIO_ARM_CM7_RXEV (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_15_INDEX)) -#define GPIO_ARM_CM7_TXEV (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_14_INDEX)) - -/* Clock Controller Module (CCM) */ - -#define GPIO_CCM_CLKO1 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_04_INDEX)) -#define GPIO_CCM_CLKO2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_05_INDEX)) -#define GPIO_CCM_PMIC_RDY (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_32_INDEX)) -#define GPIO_CCM_PMIC_READY_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_12_INDEX)) -#define GPIO_CCM_PMIC_READY_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX)) -#define GPIO_CCM_PMIC_READY_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX)) -#define GPIO_CCM_PMIC_READY_4 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_03_INDEX)) -#define GPIO_CCM_PMIC_VSTBY_REQ (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_PMIC_STBY_REQ_INDEX)) -#define GPIO_CCM_REF_EN (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_07_INDEX)) -#define GPIO_CCM_STOP (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_04_INDEX)) -#define GPIO_CCM_WAIT (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_02_INDEX)) - -/* CMOS Sensor Interface (CSI) */ - -#define GPIO_CSI_DATA00 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_10_INDEX)) -#define GPIO_CSI_DATA01 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_11_INDEX)) -#define GPIO_CSI_DATA02_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_11_INDEX)) -#define GPIO_CSI_DATA02_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_15_INDEX)) -#define GPIO_CSI_DATA03_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_10_INDEX)) -#define GPIO_CSI_DATA03_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_14_INDEX)) -#define GPIO_CSI_DATA04_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_09_INDEX)) -#define GPIO_CSI_DATA04_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_13_INDEX)) -#define GPIO_CSI_DATA05_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_08_INDEX)) -#define GPIO_CSI_DATA05_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_12_INDEX)) -#define GPIO_CSI_DATA06_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_07_INDEX)) -#define GPIO_CSI_DATA06_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_11_INDEX)) -#define GPIO_CSI_DATA07_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_06_INDEX)) -#define GPIO_CSI_DATA07_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_10_INDEX)) -#define GPIO_CSI_DATA08_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_05_INDEX)) -#define GPIO_CSI_DATA08_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX)) -#define GPIO_CSI_DATA09_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX)) -#define GPIO_CSI_DATA09_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX)) -#define GPIO_CSI_DATA10 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_09_INDEX)) -#define GPIO_CSI_DATA11 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_08_INDEX)) -#define GPIO_CSI_DATA12 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_07_INDEX)) -#define GPIO_CSI_DATA13 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_06_INDEX)) -#define GPIO_CSI_DATA14 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_05_INDEX)) -#define GPIO_CSI_DATA15 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_04_INDEX)) -#define GPIO_CSI_DATA16 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_37_INDEX)) -#define GPIO_CSI_DATA17 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_36_INDEX)) -#define GPIO_CSI_DATA18 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_35_INDEX)) -#define GPIO_CSI_DATA19 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_34_INDEX)) -#define GPIO_CSI_DATA20 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_33_INDEX)) -#define GPIO_CSI_DATA21 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_32_INDEX)) -#define GPIO_CSI_DATA22 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_31_INDEX)) -#define GPIO_CSI_DATA23 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_30_INDEX)) -#define GPIO_CSI_FIELD (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_38_INDEX)) -#define GPIO_CSI_HSYNC_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_14_INDEX)) -#define GPIO_CSI_HSYNC_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_15_INDEX)) -#define GPIO_CSI_HSYNC_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX)) -#define GPIO_CSI_MCLK_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_15_INDEX)) -#define GPIO_CSI_MCLK_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX)) -#define GPIO_CSI_PIXCLK_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_12_INDEX)) -#define GPIO_CSI_PIXCLK_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX)) -#define GPIO_CSI_VSYNC_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_13_INDEX)) -#define GPIO_CSI_VSYNC_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_14_INDEX)) -#define GPIO_CSI_VSYNC_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX)) - -/* Ethernet (ENET) */ - -#define GPIO_ENET_1588_EVENT0_IN_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_15_INDEX)) -#define GPIO_ENET_1588_EVENT0_IN_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_12_INDEX)) -#define GPIO_ENET_1588_EVENT0_IN_3 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_11_INDEX)) -#define GPIO_ENET_1588_EVENT0_OUT_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_14_INDEX)) -#define GPIO_ENET_1588_EVENT0_OUT_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_13_INDEX)) -#define GPIO_ENET_1588_EVENT0_OUT_3 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_10_INDEX)) -#define GPIO_ENET_1588_EVENT1_IN (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_13_INDEX)) -#define GPIO_ENET_1588_EVENT1_OUT (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_12_INDEX)) -#define GPIO_ENET_1588_EVENT2_IN (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX)) -#define GPIO_ENET_1588_EVENT2_OUT (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX)) -#define GPIO_ENET_1588_EVENT3_IN (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_08_INDEX)) -#define GPIO_ENET_1588_EVENT3_OUT (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_07_INDEX)) -#define GPIO_ENET_COL (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_11_INDEX)) -#define GPIO_ENET_CRS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_10_INDEX)) -#define GPIO_ENET_MDC_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_14_INDEX)) -#define GPIO_ENET_MDC_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX)) -#define GPIO_ENET_MDC_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_40_INDEX) | \ - IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ - IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) -#define GPIO_ENET_MDIO_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_15_INDEX)) -#define GPIO_ENET_MDIO_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX)) -#define GPIO_ENET_MDIO_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_41_INDEX) | \ - IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_OPENDRAIN | \ - IOMUX_SPEED_LOW | IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) -#define GPIO_ENET_RDATA00 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_20_INDEX)) -#define GPIO_ENET_RDATA01 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_19_INDEX)) -#define GPIO_ENET_REF_CLK_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_25_INDEX)) -#define GPIO_ENET_REF_CLK_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_10_INDEX) | \ - IOMUX_SLEW_FAST | IOMUX_DRIVE_40OHM | IOMUX_SPEED_LOW | \ - IOMUX_PULL_DOWN_100K | IOMUX_PULL_KEEP) -#define GPIO_ENET_RX_CLK (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_06_INDEX)) -#define GPIO_ENET_RX_DATA00 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_04_INDEX) | \ - IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ - IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) -#define GPIO_ENET_RX_DATA01 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_05_INDEX) | \ - IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ - IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) -#define GPIO_ENET_RX_DATA02 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_09_INDEX)) -#define GPIO_ENET_RX_DATA03 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_08_INDEX)) -#define GPIO_ENET_RX_EN_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_06_INDEX) | \ - IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ - IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) -#define GPIO_ENET_RX_EN_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_23_INDEX)) -#define GPIO_ENET_RX_ER_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_11_INDEX) | \ - IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ - IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) -#define GPIO_ENET_RX_ER_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_26_INDEX)) -#define GPIO_ENET_TDATA00 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_22_INDEX)) -#define GPIO_ENET_TDATA01 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_21_INDEX)) -#define GPIO_ENET_TX_CLK_1 (GPIO_PERIPH | GPIO_ALT6 | GPIO_SION_ENABLE | \ - GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_10_INDEX) | \ - IOMUX_SLEW_FAST | IOMUX_DRIVE_40OHM | IOMUX_SPEED_LOW | \ - IOMUX_PULL_DOWN_100K | IOMUX_PULL_KEEP) -#define GPIO_ENET_TX_CLK_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_25_INDEX)) -#define GPIO_ENET_TX_DATA00 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_07_INDEX) | \ - IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ - IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) -#define GPIO_ENET_TX_DATA01 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_08_INDEX) | \ - IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ - IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) -#define GPIO_ENET_TX_DATA02 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_05_INDEX)) -#define GPIO_ENET_TX_DATA03 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX)) -#define GPIO_ENET_TX_EN_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_09_INDEX) | \ - IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ - IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) -#define GPIO_ENET_TX_EN_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_24_INDEX)) -#define GPIO_ENET_TX_ER (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_07_INDEX)) - -/* External Watchdog Monitor (EWM) */ - -#define GPIO_EWM_OUT_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_11_INDEX)) -#define GPIO_EWM_OUT_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_13_INDEX)) -#define GPIO_EWM_OUT_3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_01_INDEX)) - -/* Flexible Controller Area Network (FLEXCAN) */ - -#define GPIO_FLEXCAN1_RX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX)) -#define GPIO_FLEXCAN1_RX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_03_INDEX)) -#define GPIO_FLEXCAN1_RX_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_18_INDEX)) -#define GPIO_FLEXCAN1_RX_4 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_03_INDEX)) -#define GPIO_FLEXCAN1_TX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX)) -#define GPIO_FLEXCAN1_TX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_02_INDEX)) -#define GPIO_FLEXCAN1_TX_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_17_INDEX)) -#define GPIO_FLEXCAN1_TX_4 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_02_INDEX)) - -#define GPIO_FLEXCAN2_RX_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_03_INDEX)) -#define GPIO_FLEXCAN2_RX_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_10_INDEX)) -#define GPIO_FLEXCAN2_RX_3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_15_INDEX)) -#define GPIO_FLEXCAN2_RX_4 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_09_INDEX)) -#define GPIO_FLEXCAN2_TX_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_02_INDEX)) -#define GPIO_FLEXCAN2_TX_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_09_INDEX)) -#define GPIO_FLEXCAN2_TX_3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_14_INDEX)) -#define GPIO_FLEXCAN2_TX_4 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_08_INDEX)) - -#define GPIO_FLEXCAN3_RX_1 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_11_INDEX)) -#define GPIO_FLEXCAN3_RX_2 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_15_INDEX)) -#define GPIO_FLEXCAN3_RX_3 (GPIO_PERIPH | GPIO_ALT9 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_37_INDEX)) -#define GPIO_FLEXCAN3_TX_1 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_10_INDEX)) -#define GPIO_FLEXCAN3_TX_2 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_14_INDEX)) -#define GPIO_FLEXCAN3_TX_3 (GPIO_PERIPH | GPIO_ALT9 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_36_INDEX)) - -/* Flexible I/O (FlexIO) */ - -#define GPIO_FLEXIO1_FLEXIO00 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_00_INDEX)) -#define GPIO_FLEXIO1_FLEXIO01 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_01_INDEX)) -#define GPIO_FLEXIO1_FLEXIO02 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_02_INDEX)) -#define GPIO_FLEXIO1_FLEXIO03 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_03_INDEX)) -#define GPIO_FLEXIO1_FLEXIO04 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_04_INDEX)) -#define GPIO_FLEXIO1_FLEXIO05 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_05_INDEX)) -#define GPIO_FLEXIO1_FLEXIO06 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_06_INDEX)) -#define GPIO_FLEXIO1_FLEXIO07 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_07_INDEX)) -#define GPIO_FLEXIO1_FLEXIO08 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_08_INDEX)) -#define GPIO_FLEXIO1_FLEXIO09 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_09_INDEX)) -#define GPIO_FLEXIO1_FLEXIO10 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_10_INDEX)) -#define GPIO_FLEXIO1_FLEXIO11 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_11_INDEX)) -#define GPIO_FLEXIO1_FLEXIO12 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_26_INDEX)) -#define GPIO_FLEXIO1_FLEXIO13 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_27_INDEX)) -#define GPIO_FLEXIO1_FLEXIO14 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_28_INDEX)) -#define GPIO_FLEXIO1_FLEXIO15 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_29_INDEX)) - -#define GPIO_FLEXIO2_FLEXIO00 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_00_INDEX)) -#define GPIO_FLEXIO2_FLEXIO01 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_01_INDEX)) -#define GPIO_FLEXIO2_FLEXIO02 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_02_INDEX)) -#define GPIO_FLEXIO2_FLEXIO03 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_03_INDEX)) -#define GPIO_FLEXIO2_FLEXIO04 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_04_INDEX)) -#define GPIO_FLEXIO2_FLEXIO05 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_05_INDEX)) -#define GPIO_FLEXIO2_FLEXIO06 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_06_INDEX)) -#define GPIO_FLEXIO2_FLEXIO07 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_07_INDEX)) -#define GPIO_FLEXIO2_FLEXIO08 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_08_INDEX)) -#define GPIO_FLEXIO2_FLEXIO09 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_09_INDEX)) -#define GPIO_FLEXIO2_FLEXIO10 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_10_INDEX)) -#define GPIO_FLEXIO2_FLEXIO11 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_11_INDEX)) -#define GPIO_FLEXIO2_FLEXIO12 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_12_INDEX)) -#define GPIO_FLEXIO2_FLEXIO13 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_13_INDEX)) -#define GPIO_FLEXIO2_FLEXIO14 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_14_INDEX)) -#define GPIO_FLEXIO2_FLEXIO15 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_15_INDEX)) -#define GPIO_FLEXIO2_FLEXIO16 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_00_INDEX)) -#define GPIO_FLEXIO2_FLEXIO17 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_01_INDEX)) -#define GPIO_FLEXIO2_FLEXIO18 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_02_INDEX)) -#define GPIO_FLEXIO2_FLEXIO19 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_03_INDEX)) -#define GPIO_FLEXIO2_FLEXIO20 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_04_INDEX)) -#define GPIO_FLEXIO2_FLEXIO21 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_05_INDEX)) -#define GPIO_FLEXIO2_FLEXIO22 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_06_INDEX)) -#define GPIO_FLEXIO2_FLEXIO23 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_07_INDEX)) -#define GPIO_FLEXIO2_FLEXIO24 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_08_INDEX)) -#define GPIO_FLEXIO2_FLEXIO25 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_09_INDEX)) -#define GPIO_FLEXIO2_FLEXIO26 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_10_INDEX)) -#define GPIO_FLEXIO2_FLEXIO27 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_11_INDEX)) -#define GPIO_FLEXIO2_FLEXIO28 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_12_INDEX)) -#define GPIO_FLEXIO2_FLEXIO29 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_13_INDEX)) -#define GPIO_FLEXIO2_FLEXIO30 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_14_INDEX)) -#define GPIO_FLEXIO2_FLEXIO31 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_15_INDEX)) - -/* Enhanced Flex Pulse Width Modulator (eFlexPWM) */ - -#define GPIO_FLEXPWM1_PWMA00_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_23_INDEX)) -#define GPIO_FLEXPWM1_PWMA00_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_00_INDEX)) -#define GPIO_FLEXPWM1_PWMA01_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_25_INDEX)) -#define GPIO_FLEXPWM1_PWMA01_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_02_INDEX)) -#define GPIO_FLEXPWM1_PWMA02_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_27_INDEX)) -#define GPIO_FLEXPWM1_PWMA02_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_04_INDEX)) -#define GPIO_FLEXPWM1_PWMA03_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_10_INDEX)) -#define GPIO_FLEXPWM1_PWMA03_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_38_INDEX)) -#define GPIO_FLEXPWM1_PWMA03_3 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_00_INDEX)) -#define GPIO_FLEXPWM1_PWMA03_4 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_12_INDEX)) -#define GPIO_FLEXPWM1_PWMA03_5 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_00_INDEX)) -#define GPIO_FLEXPWM1_PWMB00_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_24_INDEX)) -#define GPIO_FLEXPWM1_PWMB00_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_01_INDEX)) -#define GPIO_FLEXPWM1_PWMB01_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_26_INDEX)) -#define GPIO_FLEXPWM1_PWMB01_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_03_INDEX)) -#define GPIO_FLEXPWM1_PWMB02_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_28_INDEX)) -#define GPIO_FLEXPWM1_PWMB02_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_05_INDEX)) -#define GPIO_FLEXPWM1_PWMB03_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_11_INDEX)) -#define GPIO_FLEXPWM1_PWMB03_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_39_INDEX)) -#define GPIO_FLEXPWM1_PWMB03_3 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_01_INDEX)) -#define GPIO_FLEXPWM1_PWMB03_4 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_13_INDEX)) -#define GPIO_FLEXPWM1_PWMB03_5 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_01_INDEX)) -#define GPIO_FLEXPWM1_PWMX00 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_02_INDEX)) -#define GPIO_FLEXPWM1_PWMX01 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_03_INDEX)) -#define GPIO_FLEXPWM1_PWMX02 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_12_INDEX)) -#define GPIO_FLEXPWM1_PWMX03 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_13_INDEX)) - -#define GPIO_FLEXPWM2_PWMA00_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_06_INDEX)) -#define GPIO_FLEXPWM2_PWMA00_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_06_INDEX)) -#define GPIO_FLEXPWM2_PWMA01_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_08_INDEX)) -#define GPIO_FLEXPWM2_PWMA01_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_08_INDEX)) -#define GPIO_FLEXPWM2_PWMA02_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_10_INDEX)) -#define GPIO_FLEXPWM2_PWMA02_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_10_INDEX)) -#define GPIO_FLEXPWM2_PWMA03_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_00_INDEX)) -#define GPIO_FLEXPWM2_PWMA03_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_09_INDEX)) -#define GPIO_FLEXPWM2_PWMA03_3 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_19_INDEX)) -#define GPIO_FLEXPWM2_PWMA03_4 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_02_INDEX)) -#define GPIO_FLEXPWM2_PWMA03_5 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_02_INDEX)) -#define GPIO_FLEXPWM2_PWMB00_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_07_INDEX)) -#define GPIO_FLEXPWM2_PWMB00_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_07_INDEX)) -#define GPIO_FLEXPWM2_PWMB01_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_09_INDEX)) -#define GPIO_FLEXPWM2_PWMB01_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_09_INDEX)) -#define GPIO_FLEXPWM2_PWMB02_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_11_INDEX)) -#define GPIO_FLEXPWM2_PWMB02_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_11_INDEX)) -#define GPIO_FLEXPWM2_PWMB03_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_01_INDEX)) -#define GPIO_FLEXPWM2_PWMB03_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_20_INDEX)) -#define GPIO_FLEXPWM2_PWMB03_3 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_03_INDEX)) -#define GPIO_FLEXPWM2_PWMB03_4 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_03_INDEX)) - -#define GPIO_FLEXPWM3_PWMA00 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_29_INDEX)) -#define GPIO_FLEXPWM3_PWMA01 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_31_INDEX)) -#define GPIO_FLEXPWM3_PWMA02 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_33_INDEX)) -#define GPIO_FLEXPWM3_PWMA03 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_21_INDEX)) -#define GPIO_FLEXPWM3_PWMB00 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_30_INDEX)) -#define GPIO_FLEXPWM3_PWMB01 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_32_INDEX)) -#define GPIO_FLEXPWM3_PWMB02 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_34_INDEX)) -#define GPIO_FLEXPWM3_PWMB03 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_22_INDEX)) - -#define GPIO_FLEXPWM4_PWMA00_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX)) -#define GPIO_FLEXPWM4_PWMA00_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_00_INDEX)) -#define GPIO_FLEXPWM4_PWMA01_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX)) -#define GPIO_FLEXPWM4_PWMA01_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_02_INDEX)) -#define GPIO_FLEXPWM4_PWMA02_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_14_INDEX)) -#define GPIO_FLEXPWM4_PWMA02_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_04_INDEX)) -#define GPIO_FLEXPWM4_PWMA03_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_15_INDEX)) -#define GPIO_FLEXPWM4_PWMA03_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_17_INDEX)) -#define GPIO_FLEXPWM4_PWMB00 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_01_INDEX)) -#define GPIO_FLEXPWM4_PWMB01 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_03_INDEX)) -#define GPIO_FLEXPWM4_PWMB02 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_05_INDEX)) -#define GPIO_FLEXPWM4_PWMB03 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_18_INDEX)) - -/* Flexible SPI (FlexSPI) */ - -#define GPIO_FLEXSPIA_DATA00_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_13_INDEX)) -#define GPIO_FLEXSPIA_DATA00_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_08_INDEX)) -#define GPIO_FLEXSPIA_DATA01_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_12_INDEX)) -#define GPIO_FLEXSPIA_DATA01_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_09_INDEX)) -#define GPIO_FLEXSPIA_DATA02_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_11_INDEX)) -#define GPIO_FLEXSPIA_DATA02_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_10_INDEX)) -#define GPIO_FLEXSPIA_DATA03_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_10_INDEX)) -#define GPIO_FLEXSPIA_DATA03_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_11_INDEX)) -#define GPIO_FLEXSPIA_DQS_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX)) -#define GPIO_FLEXSPIA_DQS_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_05_INDEX)) -#define GPIO_FLEXSPIA_SCLK_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_14_INDEX)) -#define GPIO_FLEXSPIA_SCLK_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_07_INDEX)) -#define GPIO_FLEXSPIA_SS0_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_15_INDEX)) -#define GPIO_FLEXSPIA_SS0_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_06_INDEX)) -#define GPIO_FLEXSPIA_SS1_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX)) -#define GPIO_FLEXSPIA_SS1_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_04_INDEX)) -#define GPIO_FLEXSPIA_SS1_3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_00_INDEX)) - -#define GPIO_FLEXSPIB_DATA00_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX)) -#define GPIO_FLEXSPIB_DATA00_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_03_INDEX)) -#define GPIO_FLEXSPIB_DATA01_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX)) -#define GPIO_FLEXSPIB_DATA01_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_02_INDEX)) -#define GPIO_FLEXSPIB_DATA02_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX)) -#define GPIO_FLEXSPIB_DATA02_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_01_INDEX)) -#define GPIO_FLEXSPIB_DATA03_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX)) -#define GPIO_FLEXSPIB_DATA03_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_00_INDEX)) -#define GPIO_FLEXSPIB_DQS (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_05_INDEX)) -#define GPIO_FLEXSPIB_SCLK (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_04_INDEX)) -#define GPIO_FLEXSPIB_SS0_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_04_INDEX)) -#define GPIO_FLEXSPIB_SS0_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_05_INDEX)) -#define GPIO_FLEXSPIB_SS1 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_01_INDEX)) - -/* GPIO */ - -#define GPIO_GPIO1_IO00 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_00_INDEX)) -#define GPIO_GPIO1_IO01 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_01_INDEX)) -#define GPIO_GPIO1_IO02 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_02_INDEX)) -#define GPIO_GPIO1_IO03 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_03_INDEX)) -#define GPIO_GPIO1_IO04 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX)) -#define GPIO_GPIO1_IO05 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_05_INDEX)) -#define GPIO_GPIO1_IO06 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_06_INDEX)) -#define GPIO_GPIO1_IO07 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_07_INDEX)) -#define GPIO_GPIO1_IO08 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_08_INDEX)) -#define GPIO_GPIO1_IO09 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_09_INDEX)) -#define GPIO_GPIO1_IO10 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_10_INDEX)) -#define GPIO_GPIO1_IO11 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_11_INDEX)) -#define GPIO_GPIO1_IO12 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_12_INDEX)) -#define GPIO_GPIO1_IO13 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_13_INDEX)) -#define GPIO_GPIO1_IO14 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_14_INDEX)) -#define GPIO_GPIO1_IO15 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_15_INDEX)) -#define GPIO_GPIO1_IO16 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX)) -#define GPIO_GPIO1_IO17 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX)) -#define GPIO_GPIO1_IO18 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX)) -#define GPIO_GPIO1_IO19 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX)) -#define GPIO_GPIO1_IO20 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX)) -#define GPIO_GPIO1_IO21 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX)) -#define GPIO_GPIO1_IO22 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX)) -#define GPIO_GPIO1_IO23 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX)) -#define GPIO_GPIO1_IO24 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX)) -#define GPIO_GPIO1_IO25 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX)) -#define GPIO_GPIO1_IO26 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_10_INDEX)) -#define GPIO_GPIO1_IO27 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_11_INDEX)) -#define GPIO_GPIO1_IO28 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_12_INDEX)) -#define GPIO_GPIO1_IO29 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_13_INDEX)) -#define GPIO_GPIO1_IO30 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_14_INDEX)) -#define GPIO_GPIO1_IO31 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_15_INDEX)) - -#define GPIO_GPIO2_IO00 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_00_INDEX)) -#define GPIO_GPIO2_IO01 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_01_INDEX)) -#define GPIO_GPIO2_IO02 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_02_INDEX)) -#define GPIO_GPIO2_IO03 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_03_INDEX)) -#define GPIO_GPIO2_IO04 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_04_INDEX)) -#define GPIO_GPIO2_IO05 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_05_INDEX)) -#define GPIO_GPIO2_IO06 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_06_INDEX)) -#define GPIO_GPIO2_IO07 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_07_INDEX)) -#define GPIO_GPIO2_IO08 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_08_INDEX)) -#define GPIO_GPIO2_IO09 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_09_INDEX)) -#define GPIO_GPIO2_IO10 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_10_INDEX)) -#define GPIO_GPIO2_IO11 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_11_INDEX)) -#define GPIO_GPIO2_IO12 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_12_INDEX)) -#define GPIO_GPIO2_IO13 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_13_INDEX)) -#define GPIO_GPIO2_IO14 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_14_INDEX)) -#define GPIO_GPIO2_IO15 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_15_INDEX)) -#define GPIO_GPIO2_IO16 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_00_INDEX)) -#define GPIO_GPIO2_IO17 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_01_INDEX)) -#define GPIO_GPIO2_IO18 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_02_INDEX)) -#define GPIO_GPIO2_IO19 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_03_INDEX)) -#define GPIO_GPIO2_IO20 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_04_INDEX)) -#define GPIO_GPIO2_IO21 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_05_INDEX)) -#define GPIO_GPIO2_IO22 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_06_INDEX)) -#define GPIO_GPIO2_IO23 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_07_INDEX)) -#define GPIO_GPIO2_IO24 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_08_INDEX)) -#define GPIO_GPIO2_IO25 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_09_INDEX)) -#define GPIO_GPIO2_IO26 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_10_INDEX)) -#define GPIO_GPIO2_IO27 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_11_INDEX)) -#define GPIO_GPIO2_IO28 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_12_INDEX)) -#define GPIO_GPIO2_IO29 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_13_INDEX)) -#define GPIO_GPIO2_IO30 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_14_INDEX)) -#define GPIO_GPIO2_IO31 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_15_INDEX)) - -#define GPIO_GPIO3_IO00 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_00_INDEX)) -#define GPIO_GPIO3_IO01 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_01_INDEX)) -#define GPIO_GPIO3_IO02 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_02_INDEX)) -#define GPIO_GPIO3_IO03 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_03_INDEX)) -#define GPIO_GPIO3_IO04 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_04_INDEX)) -#define GPIO_GPIO3_IO05 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_05_INDEX)) -#define GPIO_GPIO3_IO06 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_06_INDEX)) -#define GPIO_GPIO3_IO07 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_07_INDEX)) -#define GPIO_GPIO3_IO08 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_08_INDEX)) -#define GPIO_GPIO3_IO09 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_09_INDEX)) -#define GPIO_GPIO3_IO10 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_10_INDEX)) -#define GPIO_GPIO3_IO11 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_11_INDEX)) -#define GPIO_GPIO3_IO12 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_00_INDEX)) -#define GPIO_GPIO3_IO13 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_01_INDEX)) -#define GPIO_GPIO3_IO14 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_02_INDEX)) -#define GPIO_GPIO3_IO15 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_03_INDEX)) -#define GPIO_GPIO3_IO16 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_04_INDEX)) -#define GPIO_GPIO3_IO17 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_05_INDEX)) -#define GPIO_GPIO3_IO18 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_32_INDEX)) -#define GPIO_GPIO3_IO19 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_33_INDEX)) -#define GPIO_GPIO3_IO20 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_34_INDEX)) -#define GPIO_GPIO3_IO21 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_35_INDEX)) -#define GPIO_GPIO3_IO22 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_36_INDEX)) -#define GPIO_GPIO3_IO23 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_37_INDEX)) -#define GPIO_GPIO3_IO24 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_38_INDEX)) -#define GPIO_GPIO3_IO25 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_39_INDEX)) -#define GPIO_GPIO3_IO26 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_40_INDEX)) -#define GPIO_GPIO3_IO27 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_41_INDEX)) - -#define GPIO_GPIO4_IO00 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_00_INDEX)) -#define GPIO_GPIO4_IO01 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_01_INDEX)) -#define GPIO_GPIO4_IO02 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_02_INDEX)) -#define GPIO_GPIO4_IO03 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_03_INDEX)) -#define GPIO_GPIO4_IO04 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_04_INDEX)) -#define GPIO_GPIO4_IO05 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_05_INDEX)) -#define GPIO_GPIO4_IO06 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_06_INDEX)) -#define GPIO_GPIO4_IO07 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_07_INDEX)) -#define GPIO_GPIO4_IO08 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_08_INDEX)) -#define GPIO_GPIO4_IO09 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_09_INDEX)) -#define GPIO_GPIO4_IO10 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_10_INDEX)) -#define GPIO_GPIO4_IO11 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_11_INDEX)) -#define GPIO_GPIO4_IO12 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_12_INDEX)) -#define GPIO_GPIO4_IO13 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_13_INDEX)) -#define GPIO_GPIO4_IO14 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_14_INDEX)) -#define GPIO_GPIO4_IO15 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_15_INDEX)) -#define GPIO_GPIO4_IO16 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_16_INDEX)) -#define GPIO_GPIO4_IO17 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_17_INDEX)) -#define GPIO_GPIO4_IO18 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_18_INDEX)) -#define GPIO_GPIO4_IO19 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_19_INDEX)) -#define GPIO_GPIO4_IO20 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_20_INDEX)) -#define GPIO_GPIO4_IO21 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_21_INDEX)) -#define GPIO_GPIO4_IO22 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_22_INDEX)) -#define GPIO_GPIO4_IO23 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_23_INDEX)) -#define GPIO_GPIO4_IO24 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_24_INDEX)) -#define GPIO_GPIO4_IO25 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_25_INDEX)) -#define GPIO_GPIO4_IO26 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_26_INDEX)) -#define GPIO_GPIO4_IO27 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_27_INDEX)) -#define GPIO_GPIO4_IO28 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_28_INDEX)) -#define GPIO_GPIO4_IO29 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_29_INDEX)) -#define GPIO_GPIO4_IO30 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_30_INDEX)) -#define GPIO_GPIO4_IO31 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_31_INDEX)) - -#define GPIO_GPIO5_IO00 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_WAKEUP_INDEX)) -#define GPIO_GPIO5_IO01 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_PMIC_ON_REQ_INDEX)) -#define GPIO_GPIO5_IO02 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_PMIC_STBY_REQ_INDEX)) - -/* General Purpose Timer (GPT) */ - -#define GPIO_GPT1_CAPTURE1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_24_INDEX)) -#define GPIO_GPT1_CAPTURE2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_23_INDEX)) -#define GPIO_GPT1_CLK (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_13_INDEX)) -#define GPIO_GPT1_COMPARE1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_35_INDEX)) -#define GPIO_GPT1_COMPARE2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_36_INDEX)) -#define GPIO_GPT1_COMPARE3 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_37_INDEX)) - -#define GPIO_GPT2_CAPTURE1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_41_INDEX)) -#define GPIO_GPT2_CAPTURE2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_40_INDEX)) -#define GPIO_GPT2_CLK (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_09_INDEX)) -#define GPIO_GPT2_COMPARE2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_07_INDEX)) -#define GPIO_GPT2_COMPARE3 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_08_INDEX)) - -/* JTAG */ - -#define GPIO_JTAG_ACTIVE (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_03_INDEX)) -#define GPIO_JTAG_DE (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_01_INDEX)) -#define GPIO_JTAG_DONE (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_00_INDEX)) -#define GPIO_JTAG_FAIL (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_02_INDEX)) -#define GPIO_JTAG_MOD (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_08_INDEX)) -#define GPIO_JTAG_TCK (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_07_INDEX)) -#define GPIO_JTAG_TDI (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_09_INDEX)) -#define GPIO_JTAG_TDO (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_10_INDEX)) -#define GPIO_JTAG_TRSTB (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_11_INDEX)) - -/* Keypad Port (KPP) */ - -#define GPIO_KPP_COL00 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_15_INDEX)) -#define GPIO_KPP_COL01 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_13_INDEX)) -#define GPIO_KPP_COL02 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_11_INDEX)) -#define GPIO_KPP_COL03 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX)) -#define GPIO_KPP_COL04 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX)) -#define GPIO_KPP_COL05 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX)) -#define GPIO_KPP_COL06 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX)) -#define GPIO_KPP_COL07 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX)) -#define GPIO_KPP_ROW00 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_14_INDEX)) -#define GPIO_KPP_ROW01 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_12_INDEX)) -#define GPIO_KPP_ROW02 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_10_INDEX)) -#define GPIO_KPP_ROW03 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX)) -#define GPIO_KPP_ROW04 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX)) -#define GPIO_KPP_ROW05 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX)) -#define GPIO_KPP_ROW06 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX)) -#define GPIO_KPP_ROW07 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX)) - -/* LCD */ - -#define GPIO_LCD_CLK (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_00_INDEX)) -#define GPIO_LCD_DATA00 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_04_INDEX)) -#define GPIO_LCD_DATA01 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_05_INDEX)) -#define GPIO_LCD_DATA02 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_06_INDEX)) -#define GPIO_LCD_DATA03 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_07_INDEX)) -#define GPIO_LCD_DATA04 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_08_INDEX)) -#define GPIO_LCD_DATA05 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_09_INDEX)) -#define GPIO_LCD_DATA06 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_10_INDEX)) -#define GPIO_LCD_DATA07 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_11_INDEX)) -#define GPIO_LCD_DATA08 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_12_INDEX)) -#define GPIO_LCD_DATA09 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_13_INDEX)) -#define GPIO_LCD_DATA10 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_14_INDEX)) -#define GPIO_LCD_DATA11 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_15_INDEX)) -#define GPIO_LCD_DATA12 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_00_INDEX)) -#define GPIO_LCD_DATA13 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_01_INDEX)) -#define GPIO_LCD_DATA14 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_02_INDEX)) -#define GPIO_LCD_DATA15 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_03_INDEX)) -#define GPIO_LCD_DATA16 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_04_INDEX)) -#define GPIO_LCD_DATA17 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_05_INDEX)) -#define GPIO_LCD_DATA18 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_06_INDEX)) -#define GPIO_LCD_DATA19 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_07_INDEX)) -#define GPIO_LCD_DATA20 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_08_INDEX)) -#define GPIO_LCD_DATA21 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_09_INDEX)) -#define GPIO_LCD_DATA22 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_10_INDEX)) -#define GPIO_LCD_DATA23 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_11_INDEX)) -#define GPIO_LCD_ENABLE (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_01_INDEX)) -#define GPIO_LCD_HSYNC (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_02_INDEX)) -#define GPIO_LCD_VSYNC (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_03_INDEX)) - -/* Low Power Inter-Integrated Circuit (LPI2C) */ - -#define GPIO_LPI2C1_HREQ (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_02_INDEX)) -#define GPIO_LPI2C1_SCL_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_04_INDEX)) -#define GPIO_LPI2C1_SCL_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX) | \ - GPIO_SION_ENABLE | IOMUX_PULL_UP_22K | IOMUX_OPENDRAIN | \ - IOMUX_SPEED_MEDIUM | IOMUX_DRIVE_33OHM) -#define GPIO_LPI2C1_SCLS (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_00_INDEX)) -#define GPIO_LPI2C1_SDA_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_05_INDEX)) -#define GPIO_LPI2C1_SDA_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX) | \ - GPIO_SION_ENABLE | IOMUX_PULL_UP_22K | IOMUX_OPENDRAIN | \ - IOMUX_SPEED_MEDIUM | IOMUX_DRIVE_33OHM) -#define GPIO_LPI2C1_SDAS (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_01_INDEX)) - -#define GPIO_LPI2C2_SCL_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_04_INDEX)) -#define GPIO_LPI2C2_SCL_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_11_INDEX)) -#define GPIO_LPI2C2_SDA_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_05_INDEX)) -#define GPIO_LPI2C2_SDA_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_10_INDEX)) - -#define GPIO_LPI2C3_SCL_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX)) -#define GPIO_LPI2C3_SCL_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_22_INDEX) | \ - GPIO_SION_ENABLE | IOMUX_OPENDRAIN | IOMUX_SPEED_MEDIUM | IOMUX_DRIVE_33OHM) -#define GPIO_LPI2C3_SCL_3 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_00_INDEX)) -#define GPIO_LPI2C3_SDA_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX)) -#define GPIO_LPI2C3_SDA_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_21_INDEX) | \ - GPIO_SION_ENABLE | IOMUX_OPENDRAIN | IOMUX_SPEED_MEDIUM | IOMUX_DRIVE_33OHM) -#define GPIO_LPI2C3_SDA_3 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_01_INDEX)) - -#define GPIO_LPI2C4_SCL_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_12_INDEX)) -#define GPIO_LPI2C4_SCL_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_12_INDEX) | \ - GPIO_SION_ENABLE | IOMUX_OPENDRAIN | IOMUX_SPEED_MEDIUM | IOMUX_DRIVE_33OHM) -#define GPIO_LPI2C4_SDA_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_13_INDEX)) -#define GPIO_LPI2C4_SDA_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_11_INDEX) | \ - GPIO_SION_ENABLE | IOMUX_OPENDRAIN | IOMUX_SPEED_MEDIUM | IOMUX_DRIVE_33OHM) - -/* Low Power Serial Peripheral Interface (LPSPI) */ - -#define IOMUX_LPSPI (IOMUX_PULL_UP_100K | IOMUX_CMOS_OUTPUT | IOMUX_DRIVE_40OHM | \ - IOMUX_SLEW_FAST | IOMUX_SPEED_MEDIUM) - -#define GPIO_LPSPI1_PCS0_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_30_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI1_PCS0_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_01_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI1_PCS1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_31_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI1_PCS2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_40_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI1_PCS3 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_41_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI1_SCK_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_27_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI1_SCK_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_00_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI1_SDI_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_29_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI1_SDI_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_03_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI1_SDO_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_28_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI1_SDO_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_02_INDEX) | IOMUX_LPSPI) - -#define GPIO_LPSPI2_PCS0_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_01_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI2_PCS0_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_06_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI2_PCS1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_14_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI2_PCS2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_10_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI2_PCS3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_11_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI2_SCK_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_00_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI2_SCK_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_07_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI2_SDI_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_03_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI2_SDI_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_09_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI2_SDO_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_02_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI2_SDO_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_08_INDEX) | IOMUX_LPSPI) - -#define GPIO_LPSPI3_PCS0_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_12_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI3_PCS0_2 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_03_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI3_PCS1 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI3_PCS2 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_05_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI3_PCS3 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_06_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI3_SCK_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_15_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI3_SCK_2 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_00_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI3_SDI_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_13_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI3_SDI_2 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_02_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI3_SDO_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_14_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI3_SDO_2 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_01_INDEX) | IOMUX_LPSPI) - -#define GPIO_LPSPI4_PCS0_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_04_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI4_PCS0_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_00_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI4_PCS1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_03_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI4_PCS2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_02_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI4_PCS3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_11_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI4_SCK_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_07_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI4_SCK_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_03_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI4_SDI_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_05_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI4_SDI_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_01_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI4_SDO_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_06_INDEX) | IOMUX_LPSPI) -#define GPIO_LPSPI4_SDO_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_02_INDEX) | IOMUX_LPSPI) - -/* Low Power Universal Asynchronous Receiver/Transmitter (LPUART) */ - -#define IOMUX_UART (IOMUX_PULL_UP_100K | IOMUX_CMOS_OUTPUT | IOMUX_DRIVE_40OHM | \ - IOMUX_SLEW_FAST | IOMUX_SPEED_MEDIUM | IOMUX_SCHMITT_TRIGGER) - -#define GPIO_LPUART1_CTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_14_INDEX)) -#define GPIO_LPUART1_RTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_15_INDEX)) -#define GPIO_LPUART1_RX (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_13_INDEX) | IOMUX_UART) -#define GPIO_LPUART1_TX (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_12_INDEX) | IOMUX_UART) - -#define GPIO_LPUART2_CTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX)) -#define GPIO_LPUART2_RTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX)) -#define GPIO_LPUART2_RX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX) | IOMUX_UART) -#define GPIO_LPUART2_RX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_10_INDEX) | IOMUX_UART) -#define GPIO_LPUART2_TX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX) | IOMUX_UART) -#define GPIO_LPUART2_TX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_11_INDEX) | IOMUX_UART) - -#define GPIO_LPUART3_CTS_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX)) -#define GPIO_LPUART3_CTS_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_15_INDEX)) -#define GPIO_LPUART3_RTS_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX)) -#define GPIO_LPUART3_RTS_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_16_INDEX)) -#define GPIO_LPUART3_RX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX) | IOMUX_UART) -#define GPIO_LPUART3_RX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_14_INDEX) | IOMUX_UART) -#define GPIO_LPUART3_RX_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_09_INDEX) | IOMUX_UART) -#define GPIO_LPUART3_TX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX) | IOMUX_UART) -#define GPIO_LPUART3_TX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_13_INDEX) | IOMUX_UART) -#define GPIO_LPUART3_TX_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_08_INDEX) | IOMUX_UART) - -#define GPIO_LPUART4_CTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_17_INDEX)) -#define GPIO_LPUART4_RTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_18_INDEX)) -#define GPIO_LPUART4_RX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_01_INDEX) | IOMUX_UART) -#define GPIO_LPUART4_RX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_20_INDEX) | IOMUX_UART) -#define GPIO_LPUART4_RX_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_01_INDEX) | IOMUX_UART) -#define GPIO_LPUART4_TX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_00_INDEX) | IOMUX_UART) -#define GPIO_LPUART4_TX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_19_INDEX) | IOMUX_UART) -#define GPIO_LPUART4_TX_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_00_INDEX) | IOMUX_UART) - -#define GPIO_LPUART5_CTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_28_INDEX)) -#define GPIO_LPUART5_RTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_27_INDEX)) -#define GPIO_LPUART5_RX_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_13_INDEX) | IOMUX_UART) -#define GPIO_LPUART5_RX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_24_INDEX)) -#define GPIO_LPUART5_TX_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_12_INDEX) | IOMUX_UART) -#define GPIO_LPUART5_TX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_23_INDEX)) - -#define GPIO_LPUART6_CTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_30_INDEX)) -#define GPIO_LPUART6_RTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_29_INDEX)) -#define GPIO_LPUART6_RX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_03_INDEX) | IOMUX_UART) -#define GPIO_LPUART6_RX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_26_INDEX) | IOMUX_UART) -#define GPIO_LPUART6_TX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_02_INDEX) | IOMUX_UART) -#define GPIO_LPUART6_TX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_25_INDEX) | IOMUX_UART) -#define GPIO_LPUART6_TX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_25_INDEX) | IOMUX_UART) - -#define GPIO_LPUART7_CTS_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_06_INDEX)) -#define GPIO_LPUART7_RTS_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_07_INDEX)) -#define GPIO_LPUART7_RX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_32_INDEX)) -#define GPIO_LPUART7_RX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_09_INDEX)) -#define GPIO_LPUART7_TX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_31_INDEX)) -#define GPIO_LPUART7_TX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_08_INDEX)) - -#define GPIO_LPUART8_CTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_02_INDEX)) -#define GPIO_LPUART8_RTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_03_INDEX)) -#define GPIO_LPUART8_RX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_11_INDEX) | IOMUX_UART) -#define GPIO_LPUART8_RX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_39_INDEX) | IOMUX_UART) -#define GPIO_LPUART8_RX_3 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_05_INDEX) | IOMUX_UART) -#define GPIO_LPUART8_TX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_10_INDEX) | IOMUX_UART) -#define GPIO_LPUART8_TX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_38_INDEX) | IOMUX_UART) -#define GPIO_LPUART8_TX_3 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_04_INDEX) | IOMUX_UART) - -/* Medium Quality Sound (MQS) */ - -#define GPIO_MQS_LEFT_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_05_INDEX)) -#define GPIO_MQS_LEFT_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_01_INDEX)) -#define GPIO_MQS_LEFT_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_14_INDEX)) -#define GPIO_MQS_RIGHT_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX)) -#define GPIO_MQS_RIGHT_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_00_INDEX)) -#define GPIO_MQS_RIGHT_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_13_INDEX)) - -/* NMI */ - -#define GPIO_NMI_GLUE_NMI (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_WAKEUP_INDEX)) - -/* Periodic Interrupt Timer (PIT) */ - -#define GPIO_PIT_TRIGGER00 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX)) - -/* Quad Timer (QTimer) */ - -#define GPIO_QTIMER1_TIMER0 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_00_INDEX)) -#define GPIO_QTIMER1_TIMER1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_01_INDEX)) -#define GPIO_QTIMER1_TIMER2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_02_INDEX)) -#define GPIO_QTIMER1_TIMER3 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_08_INDEX)) - -#define GPIO_QTIMER2_TIMER0_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_03_INDEX)) -#define GPIO_QTIMER2_TIMER0_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_19_INDEX)) -#define GPIO_QTIMER2_TIMER1_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_04_INDEX)) -#define GPIO_QTIMER2_TIMER1_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_20_INDEX)) -#define GPIO_QTIMER2_TIMER2_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_05_INDEX)) -#define GPIO_QTIMER2_TIMER2_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_21_INDEX)) -#define GPIO_QTIMER2_TIMER3_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_09_INDEX)) -#define GPIO_QTIMER2_TIMER3_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_22_INDEX)) - -#define GPIO_QTIMER3_TIMER0_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX)) -#define GPIO_QTIMER3_TIMER0_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_06_INDEX)) -#define GPIO_QTIMER3_TIMER0_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_15_INDEX)) -#define GPIO_QTIMER3_TIMER1_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX)) -#define GPIO_QTIMER3_TIMER1_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_07_INDEX)) -#define GPIO_QTIMER3_TIMER1_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_16_INDEX)) -#define GPIO_QTIMER3_TIMER2_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX)) -#define GPIO_QTIMER3_TIMER2_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_08_INDEX)) -#define GPIO_QTIMER3_TIMER2_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_17_INDEX)) -#define GPIO_QTIMER3_TIMER3_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX)) -#define GPIO_QTIMER3_TIMER3_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_10_INDEX)) -#define GPIO_QTIMER3_TIMER3_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_18_INDEX)) - -#define GPIO_QTIMER4_TIMER0 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_09_INDEX)) -#define GPIO_QTIMER4_TIMER1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_10_INDEX)) -#define GPIO_QTIMER4_TIMER2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_11_INDEX)) -#define GPIO_QTIMER4_TIMER3 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_11_INDEX)) - -/* XTALOSC Reference Clock */ - -#define GPIO_REF_CLK_24M_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_01_INDEX)) -#define GPIO_REF_CLK_24M_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_03_INDEX)) -#define GPIO_REF_CLK_24M_3 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_13_INDEX)) -#define GPIO_REF_CLK_32K (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_00_INDEX)) - -/* Synchronous Audio Interface (SAI) */ - -#define GPIO_SAI1_MCLK_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX)) -#define GPIO_SAI1_MCLK_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_13_INDEX)) -#define GPIO_SAI1_MCLK_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_03_INDEX)) -#define GPIO_SAI1_RX_BCLK_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_11_INDEX)) -#define GPIO_SAI1_RX_BCLK_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_15_INDEX)) -#define GPIO_SAI1_RX_BCLK_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_05_INDEX)) -#define GPIO_SAI1_RX_DATA00_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_12_INDEX)) -#define GPIO_SAI1_RX_DATA00_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_00_INDEX)) -#define GPIO_SAI1_RX_DATA00_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_06_INDEX)) -#define GPIO_SAI1_RX_SYNC_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_10_INDEX)) -#define GPIO_SAI1_RX_SYNC_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_14_INDEX)) -#define GPIO_SAI1_RX_SYNC_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_04_INDEX)) -#define GPIO_SAI1_TX_BCLK_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_14_INDEX)) -#define GPIO_SAI1_TX_BCLK_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_02_INDEX)) -#define GPIO_SAI1_TX_BCLK_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_08_INDEX)) -#define GPIO_SAI1_TX_DATA00_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_13_INDEX)) -#define GPIO_SAI1_TX_DATA00_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_01_INDEX)) -#define GPIO_SAI1_TX_DATA00_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_07_INDEX)) -#define GPIO_SAI1_TX_DATA01_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_12_INDEX)) -#define GPIO_SAI1_TX_DATA01_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_02_INDEX)) -#define GPIO_SAI1_TX_DATA02_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_11_INDEX)) -#define GPIO_SAI1_TX_DATA02_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_01_INDEX)) -#define GPIO_SAI1_TX_DATA03_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_10_INDEX)) -#define GPIO_SAI1_TX_DATA03_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_00_INDEX)) -#define GPIO_SAI1_TX_SYNC_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_15_INDEX)) -#define GPIO_SAI1_TX_SYNC_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_03_INDEX)) -#define GPIO_SAI1_TX_SYNC_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_09_INDEX)) - -#define GPIO_SAI2_MCLK_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_07_INDEX)) -#define GPIO_SAI2_MCLK_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_10_INDEX)) -#define GPIO_SAI2_RX_BCLK_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_10_INDEX)) -#define GPIO_SAI2_RX_BCLK_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_06_INDEX)) -#define GPIO_SAI2_RX_DATA_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_08_INDEX)) -#define GPIO_SAI2_RX_DATA_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_08_INDEX)) -#define GPIO_SAI2_RX_SYNC_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_09_INDEX)) -#define GPIO_SAI2_RX_SYNC_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_07_INDEX)) -#define GPIO_SAI2_TX_BCLK_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_06_INDEX)) -#define GPIO_SAI2_TX_BCLK_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_05_INDEX)) -#define GPIO_SAI2_TX_DATA_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_04_INDEX)) -#define GPIO_SAI2_TX_DATA_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_09_INDEX)) -#define GPIO_SAI2_TX_SYNC_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_05_INDEX)) -#define GPIO_SAI2_TX_SYNC_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX)) - -#define GPIO_SAI3_MCLK (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_37_INDEX)) -#define GPIO_SAI3_RX_BCLK (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_35_INDEX)) -#define GPIO_SAI3_RX_DATA (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_33_INDEX)) -#define GPIO_SAI3_RX_SYNC (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_34_INDEX)) -#define GPIO_SAI3_TX_BCLK (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_38_INDEX)) -#define GPIO_SAI3_TX_DATA (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_36_INDEX)) -#define GPIO_SAI3_TX_SYNC (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_39_INDEX)) - -/* Smart External Memory Controller (SEMC) */ - -#define GPIO_SEMC_ADDR00 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_09_INDEX)) -#define GPIO_SEMC_ADDR01 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_10_INDEX)) -#define GPIO_SEMC_ADDR02 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_11_INDEX)) -#define GPIO_SEMC_ADDR03 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_12_INDEX)) -#define GPIO_SEMC_ADDR04 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_13_INDEX)) -#define GPIO_SEMC_ADDR05 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_14_INDEX)) -#define GPIO_SEMC_ADDR06 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_15_INDEX)) -#define GPIO_SEMC_ADDR07 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_16_INDEX)) -#define GPIO_SEMC_ADDR08 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_17_INDEX)) -#define GPIO_SEMC_ADDR09 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_18_INDEX)) -#define GPIO_SEMC_ADDR10 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_23_INDEX)) -#define GPIO_SEMC_ADDR11 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_19_INDEX)) -#define GPIO_SEMC_ADDR12 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_20_INDEX)) -#define GPIO_SEMC_BA0 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_21_INDEX)) -#define GPIO_SEMC_BA1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_22_INDEX)) -#define GPIO_SEMC_CAS (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_24_INDEX)) -#define GPIO_SEMC_CKE (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_27_INDEX)) -#define GPIO_SEMC_CLK (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_26_INDEX)) -#define GPIO_SEMC_CS0 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_29_INDEX)) -#define GPIO_SEMC_CSX00 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_41_INDEX)) -#define GPIO_SEMC_CSX01_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_07_INDEX)) -#define GPIO_SEMC_CSX01_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_00_INDEX)) -#define GPIO_SEMC_CSX02_1 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_01_INDEX)) -#define GPIO_SEMC_CSX02_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_08_INDEX)) -#define GPIO_SEMC_CSX03 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_02_INDEX)) -#define GPIO_SEMC_DATA00 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_00_INDEX)) -#define GPIO_SEMC_DATA01 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_01_INDEX)) -#define GPIO_SEMC_DATA02 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_02_INDEX)) -#define GPIO_SEMC_DATA03 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_03_INDEX)) -#define GPIO_SEMC_DATA04 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_04_INDEX)) -#define GPIO_SEMC_DATA05 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_05_INDEX)) -#define GPIO_SEMC_DATA06 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_06_INDEX)) -#define GPIO_SEMC_DATA07 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_07_INDEX)) -#define GPIO_SEMC_DATA08 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_30_INDEX)) -#define GPIO_SEMC_DATA09 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_31_INDEX)) -#define GPIO_SEMC_DATA10 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_32_INDEX)) -#define GPIO_SEMC_DATA11 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_33_INDEX)) -#define GPIO_SEMC_DATA12 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_34_INDEX)) -#define GPIO_SEMC_DATA13 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_35_INDEX)) -#define GPIO_SEMC_DATA14 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_36_INDEX)) -#define GPIO_SEMC_DATA15 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_37_INDEX)) -#define GPIO_SEMC_DM00 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_08_INDEX)) -#define GPIO_SEMC_DM01 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_38_INDEX)) -#define GPIO_SEMC_DQS (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_39_INDEX)) -#define GPIO_SEMC_RAS (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_25_INDEX)) -#define GPIO_SEMC_RDY (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_40_INDEX)) -#define GPIO_SEMC_WE (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_28_INDEX)) - -/* Secure Non-Volatile Storage (SNVS) */ - -#define GPIO_SNVS_LP_PMIC_ON_REQ (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_PMIC_ON_REQ_INDEX)) -#define GPIO_SNVS_VIO_5 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_19_INDEX)) -#define GPIO_SNVS_VIO_5_CTL (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_18_INDEX)) - -/* Sony/Philips Digital Interface (SPDIF) */ - -#define GPIO_SPDIF_EXT_CLK (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX)) -#define GPIO_SPDIF_IN_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX)) -#define GPIO_SPDIF_IN_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_16_INDEX)) -#define GPIO_SPDIF_LOCK (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX)) -#define GPIO_SPDIF_OUT_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX)) -#define GPIO_SPDIF_OUT_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX)) -#define GPIO_SPDIF_OUT_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_15_INDEX)) -#define GPIO_SPDIF_SR_CLK (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX)) - -/* Boot Configuration */ - -#define GPIO_SRC_BOOT_CFG00 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_04_INDEX)) -#define GPIO_SRC_BOOT_CFG01 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_05_INDEX)) -#define GPIO_SRC_BOOT_CFG02 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_06_INDEX)) -#define GPIO_SRC_BOOT_CFG03 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_07_INDEX)) -#define GPIO_SRC_BOOT_CFG04 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_08_INDEX)) -#define GPIO_SRC_BOOT_CFG05 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_09_INDEX)) -#define GPIO_SRC_BOOT_CFG06 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_10_INDEX)) -#define GPIO_SRC_BOOT_CFG07 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_11_INDEX)) -#define GPIO_SRC_BOOT_CFG08 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_12_INDEX)) -#define GPIO_SRC_BOOT_CFG09 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_13_INDEX)) -#define GPIO_SRC_BOOT_CFG10 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_14_INDEX)) -#define GPIO_SRC_BOOT_CFG11 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_15_INDEX)) -#define GPIO_SRC_BOOT_MODE00 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX)) -#define GPIO_SRC_BOOT_MODE01 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_05_INDEX)) - -/* USB OTG */ - -#define GPIO_USB_OTG1_ID_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX)) -#define GPIO_USB_OTG1_ID_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_01_INDEX)) -#define GPIO_USB_OTG1_OC_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX)) -#define GPIO_USB_OTG1_OC_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_03_INDEX)) -#define GPIO_USB_OTG1_PWR_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX)) -#define GPIO_USB_OTG1_PWR_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_02_INDEX)) - -#define GPIO_USB_OTG2_ID_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX)) -#define GPIO_USB_OTG2_ID_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_00_INDEX)) -#define GPIO_USB_OTG2_OC_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_14_INDEX)) -#define GPIO_USB_OTG2_OC_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_40_INDEX)) -#define GPIO_USB_OTG2_PWR_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_15_INDEX)) -#define GPIO_USB_OTG2_PWR_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_41_INDEX)) - -/* Ultra Secured Digital Host Controller (uSDHC) */ - -#define GPIO_USDHC1_CD_1 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX)) -#define GPIO_USDHC1_CD_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_12_INDEX)) -#define GPIO_USDHC1_CD_3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_35_INDEX)) -#define GPIO_USDHC1_CLK (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_01_INDEX)) -#define GPIO_USDHC1_CMD (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_00_INDEX)) -#define GPIO_USDHC1_DATA0 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_02_INDEX)) -#define GPIO_USDHC1_DATA1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_03_INDEX)) -#define GPIO_USDHC1_DATA2 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_04_INDEX)) -#define GPIO_USDHC1_DATA3 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_05_INDEX)) -#define GPIO_USDHC1_RESET_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_33_INDEX)) -#define GPIO_USDHC1_RESET_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_00_INDEX)) -#define GPIO_USDHC1_RESET_3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_15_INDEX)) -#define GPIO_USDHC1_VSELECT_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_34_INDEX)) -#define GPIO_USDHC1_VSELECT_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX)) -#define GPIO_USDHC1_VSELECT_3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_14_INDEX)) -#define GPIO_USDHC1_VSELECT_4 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_41_INDEX)) -#define GPIO_USDHC1_WP_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_12_INDEX)) -#define GPIO_USDHC1_WP_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX)) -#define GPIO_USDHC1_WP_3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_13_INDEX)) -#define GPIO_USDHC1_WP_4 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_36_INDEX)) - -#define GPIO_USDHC2_CD_1 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX)) -#define GPIO_USDHC2_CD_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_39_INDEX)) -#define GPIO_USDHC2_CLK_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_04_INDEX)) -#define GPIO_USDHC2_CLK_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX)) -#define GPIO_USDHC2_CMD_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_05_INDEX)) -#define GPIO_USDHC2_CMD_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX)) -#define GPIO_USDHC2_DATA0_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_03_INDEX)) -#define GPIO_USDHC2_DATA0_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX)) -#define GPIO_USDHC2_DATA1_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_02_INDEX)) -#define GPIO_USDHC2_DATA1_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX)) -#define GPIO_USDHC2_DATA2_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_01_INDEX)) -#define GPIO_USDHC2_DATA2_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX)) -#define GPIO_USDHC2_DATA3_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_00_INDEX)) -#define GPIO_USDHC2_DATA3_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX)) -#define GPIO_USDHC2_DATA4_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_08_INDEX)) -#define GPIO_USDHC2_DATA4_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_12_INDEX)) -#define GPIO_USDHC2_DATA5_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_09_INDEX)) -#define GPIO_USDHC2_DATA5_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_13_INDEX)) -#define GPIO_USDHC2_DATA6_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_10_INDEX)) -#define GPIO_USDHC2_DATA6_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_14_INDEX)) -#define GPIO_USDHC2_DATA7_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_11_INDEX)) -#define GPIO_USDHC2_DATA7_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_15_INDEX)) -#define GPIO_USDHC2_RESET_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_06_INDEX)) -#define GPIO_USDHC2_RESET_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_11_INDEX)) -#define GPIO_USDHC2_RESET_3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_11_INDEX)) -#define GPIO_USDHC2_RESET_4 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_40_INDEX)) -#define GPIO_USDHC2_VSELECT (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_38_INDEX)) -#define GPIO_USDHC2_WP_1 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_10_INDEX)) -#define GPIO_USDHC2_WP_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_37_INDEX)) - -/* Watchdog Timer (WDOG1-2) */ - -#define GPIO_WDOG1_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_13_INDEX)) -#define GPIO_WDOG1_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_10_INDEX)) -#define GPIO_WDOG1_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX)) -#define GPIO_WDOG1_WDOG_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_11_INDEX)) -#define GPIO_WDOG1_WDOG_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_39_INDEX)) -#define GPIO_WDOG1_WDOG_RST_DEB (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_15_INDEX)) - -#define GPIO_WDOG2_RESET_DEB (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_03_INDEX)) -#define GPIO_WDOG2_WDOG (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_12_INDEX)) - -/* Inter-Peripheral Crossbar Switch A (XBARA) */ - -#define GPIO_XBAR1_IN02 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_14_INDEX)) -#define GPIO_XBAR1_IN03_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_15_INDEX)) -#define GPIO_XBAR1_IN03_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_01_INDEX)) -#define GPIO_XBAR1_IN20_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_15_INDEX)) -#define GPIO_XBAR1_IN20_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_08_INDEX)) -#define GPIO_XBAR1_IN21_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_16_INDEX)) -#define GPIO_XBAR1_IN21_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_09_INDEX)) -#define GPIO_XBAR1_IN22_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_36_INDEX)) -#define GPIO_XBAR1_IN22_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_10_INDEX)) -#define GPIO_XBAR1_IN23_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_37_INDEX)) -#define GPIO_XBAR1_IN23_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_11_INDEX)) -#define GPIO_XBAR1_IN24_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_14_INDEX)) -#define GPIO_XBAR1_IN24_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_12_INDEX)) -#define GPIO_XBAR1_IN25_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_15_INDEX)) -#define GPIO_XBAR1_IN25_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_13_INDEX)) -#define GPIO_XBAR1_INOUT04_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_02_INDEX)) -#define GPIO_XBAR1_INOUT04_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_00_INDEX)) -#define GPIO_XBAR1_INOUT05_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_03_INDEX)) -#define GPIO_XBAR1_INOUT05_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_01_INDEX)) -#define GPIO_XBAR1_INOUT06_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_04_INDEX)) -#define GPIO_XBAR1_INOUT06_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_02_INDEX)) -#define GPIO_XBAR1_INOUT07_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_05_INDEX)) -#define GPIO_XBAR1_INOUT07_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_03_INDEX)) -#define GPIO_XBAR1_INOUT08_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_06_INDEX)) -#define GPIO_XBAR1_INOUT08_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_04_INDEX)) -#define GPIO_XBAR1_INOUT09_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_07_INDEX)) -#define GPIO_XBAR1_INOUT09_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_05_INDEX)) -#define GPIO_XBAR1_INOUT10 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_12_INDEX)) -#define GPIO_XBAR1_INOUT11 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_13_INDEX)) -#define GPIO_XBAR1_INOUT12 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_14_INDEX)) -#define GPIO_XBAR1_INOUT13 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_15_INDEX)) -#define GPIO_XBAR1_INOUT14_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_00_INDEX)) -#define GPIO_XBAR1_INOUT14_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_00_INDEX)) -#define GPIO_XBAR1_INOUT15_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_01_INDEX)) -#define GPIO_XBAR1_INOUT15_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_01_INDEX)) -#define GPIO_XBAR1_INOUT16_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_02_INDEX)) -#define GPIO_XBAR1_INOUT16_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_02_INDEX)) -#define GPIO_XBAR1_INOUT17_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_03_INDEX)) -#define GPIO_XBAR1_INOUT17_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_03_INDEX)) -#define GPIO_XBAR1_INOUT17_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_08_INDEX)) -#define GPIO_XBAR1_INOUT17_4 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_05_INDEX)) -#define GPIO_XBAR1_INOUT18_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_35_INDEX)) -#define GPIO_XBAR1_INOUT18_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_06_INDEX)) -#define GPIO_XBAR1_INOUT19_3 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_14_INDEX)) -#define GPIO_XBAR1_INOUT19_4 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_07_INDEX)) -#define GPIO_XBAR1_XBAR_IN02 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_00_INDEX)) - -#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_PINMUX_H */ diff --git a/arch/arm/src/imxrt/chip/rt106x/imxrt106x_xbar.h b/arch/arm/src/imxrt/chip/rt106x/imxrt106x_xbar.h deleted file mode 100644 index 3d697880494..00000000000 --- a/arch/arm/src/imxrt/chip/rt106x/imxrt106x_xbar.h +++ /dev/null @@ -1,386 +0,0 @@ -/* XBAR Defines for IMXRT1060 */ - -/* XBARA1 Mux inputs (I values) ***************************************************************************************************************************************/ - -#define IMXRT_XBARA1_IN_LOGIC_LOW IMXRT_XBARA1(XBAR_INPUT, 0) /* LOGIC_LOW output assigned to XBARA1_IN0 input. */ -#define IMXRT_XBARA1_IN_LOGIC_HIGH IMXRT_XBARA1(XBAR_INPUT, 1) /* LOGIC_HIGH output assigned to XBARA1_IN1 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN02 IMXRT_XBARA1(XBAR_INPUT, 2) /* IOMUX_XBAR_IN02 output assigned to XBARA1_IN2 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN03 IMXRT_XBARA1(XBAR_INPUT, 3) /* IOMUX_XBAR_IN03 output assigned to XBARA1_IN3 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO04 IMXRT_XBARA1(XBAR_INPUT, 4) /* IOMUX_XBAR_INOUT04 output assigned to XBARA1_IN4 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO05 IMXRT_XBARA1(XBAR_INPUT, 5) /* IOMUX_XBAR_INOUT05 output assigned to XBARA1_IN5 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO06 IMXRT_XBARA1(XBAR_INPUT, 6) /* IOMUX_XBAR_INOUT06 output assigned to XBARA1_IN6 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO07 IMXRT_XBARA1(XBAR_INPUT, 7) /* IOMUX_XBAR_INOUT07 output assigned to XBARA1_IN7 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO08 IMXRT_XBARA1(XBAR_INPUT, 8) /* IOMUX_XBAR_INOUT08 output assigned to XBARA1_IN8 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO09 IMXRT_XBARA1(XBAR_INPUT, 9) /* IOMUX_XBAR_INOUT09 output assigned to XBARA1_IN9 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO10 IMXRT_XBARA1(XBAR_INPUT, 10) /* IOMUX_XBAR_INOUT10 output assigned to XBARA1_IN10 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO11 IMXRT_XBARA1(XBAR_INPUT, 11) /* IOMUX_XBAR_INOUT11 output assigned to XBARA1_IN11 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO12 IMXRT_XBARA1(XBAR_INPUT, 12) /* IOMUX_XBAR_INOUT12 output assigned to XBARA1_IN12 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO13 IMXRT_XBARA1(XBAR_INPUT, 13) /* IOMUX_XBAR_INOUT13 output assigned to XBARA1_IN13 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO14 IMXRT_XBARA1(XBAR_INPUT, 14) /* IOMUX_XBAR_INOUT14 output assigned to XBARA1_IN14 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO15 IMXRT_XBARA1(XBAR_INPUT, 15) /* IOMUX_XBAR_INOUT15 output assigned to XBARA1_IN15 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO16 IMXRT_XBARA1(XBAR_INPUT, 16) /* IOMUX_XBAR_INOUT16 output assigned to XBARA1_IN16 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO17 IMXRT_XBARA1(XBAR_INPUT, 17) /* IOMUX_XBAR_INOUT17 output assigned to XBARA1_IN17 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO18 IMXRT_XBARA1(XBAR_INPUT, 18) /* IOMUX_XBAR_INOUT18 output assigned to XBARA1_IN18 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO19 IMXRT_XBARA1(XBAR_INPUT, 19) /* IOMUX_XBAR_INOUT19 output assigned to XBARA1_IN19 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN20 IMXRT_XBARA1(XBAR_INPUT, 20) /* IOMUX_XBAR_IN20 output assigned to XBARA1_IN20 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN21 IMXRT_XBARA1(XBAR_INPUT, 21) /* IOMUX_XBAR_IN21 output assigned to XBARA1_IN21 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN22 IMXRT_XBARA1(XBAR_INPUT, 22) /* IOMUX_XBAR_IN22 output assigned to XBARA1_IN22 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN23 IMXRT_XBARA1(XBAR_INPUT, 23) /* IOMUX_XBAR_IN23 output assigned to XBARA1_IN23 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN24 IMXRT_XBARA1(XBAR_INPUT, 24) /* IOMUX_XBAR_IN24 output assigned to XBARA1_IN24 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN25 IMXRT_XBARA1(XBAR_INPUT, 25) /* IOMUX_XBAR_IN25 output assigned to XBARA1_IN25 input. */ -#define IMXRT_XBARA1_IN_ACMP1_OUT IMXRT_XBARA1(XBAR_INPUT, 26) /* ACMP1_OUT output assigned to XBARA1_IN26 input. */ -#define IMXRT_XBARA1_IN_ACMP2_OUT IMXRT_XBARA1(XBAR_INPUT, 27) /* ACMP2_OUT output assigned to XBARA1_IN27 input. */ -#define IMXRT_XBARA1_IN_ACMP3_OUT IMXRT_XBARA1(XBAR_INPUT, 28) /* ACMP3_OUT output assigned to XBARA1_IN28 input. */ -#define IMXRT_XBARA1_IN_ACMP4_OUT IMXRT_XBARA1(XBAR_INPUT, 29) /* ACMP4_OUT output assigned to XBARA1_IN29 input. */ -#define IMXRT_XBARA1_IN_RESERVED30 IMXRT_XBARA1(XBAR_INPUT, 30) /* XBARA1_IN30 input is reserved. */ -#define IMXRT_XBARA1_IN_RESERVED31 IMXRT_XBARA1(XBAR_INPUT, 31) /* XBARA1_IN31 input is reserved. */ -#define IMXRT_XBARA1_IN_QTIMER3_TMR0_OUT IMXRT_XBARA1(XBAR_INPUT, 32) /* QTIMER3_TMR0_OUTPUT output assigned to XBARA1_IN32 input. */ -#define IMXRT_XBARA1_IN_QTIMER3_TMR1_OUT IMXRT_XBARA1(XBAR_INPUT, 33) /* QTIMER3_TMR1_OUTPUT output assigned to XBARA1_IN33 input. */ -#define IMXRT_XBARA1_IN_QTIMER3_TMR2_OUT IMXRT_XBARA1(XBAR_INPUT, 34) /* QTIMER3_TMR2_OUTPUT output assigned to XBARA1_IN34 input. */ -#define IMXRT_XBARA1_IN_QTIMER3_TMR3_OUT IMXRT_XBARA1(XBAR_INPUT, 35) /* QTIMER3_TMR3_OUTPUT output assigned to XBARA1_IN35 input. */ -#define IMXRT_XBARA1_IN_QTIMER4_TMR0_OUT IMXRT_XBARA1(XBAR_INPUT, 36) /* QTIMER4_TMR0_OUTPUT output assigned to XBARA1_IN36 input. */ -#define IMXRT_XBARA1_IN_QTIMER4_TMR1_OUT IMXRT_XBARA1(XBAR_INPUT, 37) /* QTIMER4_TMR1_OUTPUT output assigned to XBARA1_IN37 input. */ -#define IMXRT_XBARA1_IN_QTIMER4_TMR2_OUT IMXRT_XBARA1(XBAR_INPUT, 38) /* QTIMER4_TMR2_OUTPUT output assigned to XBARA1_IN38 input. */ -#define IMXRT_XBARA1_IN_QTIMER4_TMR3_OUT IMXRT_XBARA1(XBAR_INPUT, 39) /* QTIMER4_TMR3_OUTPUT output assigned to XBARA1_IN39 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM1_PWM1_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 40) /* FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN40 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM1_PWM2_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 41) /* FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN41 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM1_PWM3_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 42) /* FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN42 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM1_PWM4_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 43) /* FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN43 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM2_PWM1_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 44) /* FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN44 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM2_PWM2_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 45) /* FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN45 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM2_PWM3_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 46) /* FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN46 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM2_PWM4_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 47) /* FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN47 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM3_PWM1_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 48) /* FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN48 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM3_PWM2_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 49) /* FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN49 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM3_PWM3_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 50) /* FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN50 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM3_PWM4_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 51) /* FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN51 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM4_PWM1_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 52) /* FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN52 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM4_PWM2_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 53) /* FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN53 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM4_PWM3_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 54) /* FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN54 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM4_PWM4_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 55) /* FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN55 input. */ -#define IMXRT_XBARA1_IN_PIT_TRIGGER0 IMXRT_XBARA1(XBAR_INPUT, 56) /* PIT_TRIGGER0 output assigned to XBARA1_IN56 input. */ -#define IMXRT_XBARA1_IN_PIT_TRIGGER1 IMXRT_XBARA1(XBAR_INPUT, 57) /* PIT_TRIGGER1 output assigned to XBARA1_IN57 input. */ -#define IMXRT_XBARA1_IN_PIT_TRIGGER2 IMXRT_XBARA1(XBAR_INPUT, 58) /* PIT_TRIGGER2 output assigned to XBARA1_IN58 input. */ -#define IMXRT_XBARA1_IN_PIT_TRIGGER3 IMXRT_XBARA1(XBAR_INPUT, 59) /* PIT_TRIGGER3 output assigned to XBARA1_IN59 input. */ -#define IMXRT_XBARA1_IN_ENC1_POS_MATCH IMXRT_XBARA1(XBAR_INPUT, 60) /* ENC1_POS_MATCH output assigned to XBARA1_IN60 input. */ -#define IMXRT_XBARA1_IN_ENC2_POS_MATCH IMXRT_XBARA1(XBAR_INPUT, 61) /* ENC2_POS_MATCH output assigned to XBARA1_IN61 input. */ -#define IMXRT_XBARA1_IN_ENC3_POS_MATCH IMXRT_XBARA1(XBAR_INPUT, 62) /* ENC3_POS_MATCH output assigned to XBARA1_IN62 input. */ -#define IMXRT_XBARA1_IN_ENC4_POS_MATCH IMXRT_XBARA1(XBAR_INPUT, 63) /* ENC4_POS_MATCH output assigned to XBARA1_IN63 input. */ -#define IMXRT_XBARA1_IN_DMA_DONE0 IMXRT_XBARA1(XBAR_INPUT, 64) /* DMA_DONE0 output assigned to XBARA1_IN64 input. */ -#define IMXRT_XBARA1_IN_DMA_DONE1 IMXRT_XBARA1(XBAR_INPUT, 65) /* DMA_DONE1 output assigned to XBARA1_IN65 input. */ -#define IMXRT_XBARA1_IN_DMA_DONE2 IMXRT_XBARA1(XBAR_INPUT, 66) /* DMA_DONE2 output assigned to XBARA1_IN66 input. */ -#define IMXRT_XBARA1_IN_DMA_DONE3 IMXRT_XBARA1(XBAR_INPUT, 67) /* DMA_DONE3 output assigned to XBARA1_IN67 input. */ -#define IMXRT_XBARA1_IN_DMA_DONE4 IMXRT_XBARA1(XBAR_INPUT, 68) /* DMA_DONE4 output assigned to XBARA1_IN68 input. */ -#define IMXRT_XBARA1_IN_DMA_DONE5 IMXRT_XBARA1(XBAR_INPUT, 69) /* DMA_DONE5 output assigned to XBARA1_IN69 input. */ -#define IMXRT_XBARA1_IN_DMA_DONE6 IMXRT_XBARA1(XBAR_INPUT, 70) /* DMA_DONE6 output assigned to XBARA1_IN70 input. */ -#define IMXRT_XBARA1_IN_DMA_DONE7 IMXRT_XBARA1(XBAR_INPUT, 71) /* DMA_DONE7 output assigned to XBARA1_IN71 input. */ -#define IMXRT_XBARA1_IN_AOI1_OUT0 IMXRT_XBARA1(XBAR_INPUT, 72) /* AOI1_OUT0 output assigned to XBARA1_IN72 input. */ -#define IMXRT_XBARA1_IN_AOI1_OUT1 IMXRT_XBARA1(XBAR_INPUT, 73) /* AOI1_OUT1 output assigned to XBARA1_IN73 input. */ -#define IMXRT_XBARA1_IN_AOI1_OUT2 IMXRT_XBARA1(XBAR_INPUT, 74) /* AOI1_OUT2 output assigned to XBARA1_IN74 input. */ -#define IMXRT_XBARA1_IN_AOI1_OUT3 IMXRT_XBARA1(XBAR_INPUT, 75) /* AOI1_OUT3 output assigned to XBARA1_IN75 input. */ -#define IMXRT_XBARA1_IN_AOI2_OUT0 IMXRT_XBARA1(XBAR_INPUT, 76) /* AOI2_OUT0 output assigned to XBARA1_IN76 input. */ -#define IMXRT_XBARA1_IN_AOI2_OUT1 IMXRT_XBARA1(XBAR_INPUT, 77) /* AOI2_OUT1 output assigned to XBARA1_IN77 input. */ -#define IMXRT_XBARA1_IN_AOI2_OUT2 IMXRT_XBARA1(XBAR_INPUT, 78) /* AOI2_OUT2 output assigned to XBARA1_IN78 input. */ -#define IMXRT_XBARA1_IN_AOI2_OUT3 IMXRT_XBARA1(XBAR_INPUT, 79) /* AOI2_OUT3 output assigned to XBARA1_IN79 input. */ -#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO0 IMXRT_XBARA1(XBAR_INPUT, 80) /* ADC_ETC_XBAR0_COCO0 output assigned to XBARA1_IN80 input. */ -#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO1 IMXRT_XBARA1(XBAR_INPUT, 81) /* ADC_ETC_XBAR0_COCO1 output assigned to XBARA1_IN81 input. */ -#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO2 IMXRT_XBARA1(XBAR_INPUT, 82) /* ADC_ETC_XBAR0_COCO2 output assigned to XBARA1_IN82 input. */ -#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO3 IMXRT_XBARA1(XBAR_INPUT, 83) /* ADC_ETC_XBAR0_COCO3 output assigned to XBARA1_IN83 input. */ -#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO0 IMXRT_XBARA1(XBAR_INPUT, 84) /* ADC_ETC_XBAR1_COCO0 output assigned to XBARA1_IN84 input. */ -#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO1 IMXRT_XBARA1(XBAR_INPUT, 85) /* ADC_ETC_XBAR1_COCO1 output assigned to XBARA1_IN85 input. */ -#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO2 IMXRT_XBARA1(XBAR_INPUT, 86) /* ADC_ETC_XBAR1_COCO2 output assigned to XBARA1_IN86 input. */ -#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO3 IMXRT_XBARA1(XBAR_INPUT, 87) /* ADC_ETC_XBAR1_COCO3 output assigned to XBARA1_IN87 input. */ - -/* XBARA1 Mux Output (M Muxes) ***************************************************************************************************************/ - -#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ30_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 0) /* XBARA1_OUT0 output assigned to DMA_CH_MUX_REQ30 */ -#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ31_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 1) /* XBARA1_OUT1 output assigned to DMA_CH_MUX_REQ31 */ -#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ94_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 2) /* XBARA1_OUT2 output assigned to DMA_CH_MUX_REQ94 */ -#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ95_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 3) /* XBARA1_OUT3 output assigned to DMA_CH_MUX_REQ95 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO04_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 4) /* XBARA1_OUT4 output assigned to IOMUX_XBAR_INOUT04 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO05_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 5) /* XBARA1_OUT5 output assigned to IOMUX_XBAR_INOUT05 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO06_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 6) /* XBARA1_OUT6 output assigned to IOMUX_XBAR_INOUT06 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO07_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 7) /* XBARA1_OUT7 output assigned to IOMUX_XBAR_INOUT07 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO08_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 8) /* XBARA1_OUT8 output assigned to IOMUX_XBAR_INOUT08 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO09_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 9) /* XBARA1_OUT9 output assigned to IOMUX_XBAR_INOUT09 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO10_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 10) /* XBARA1_OUT10 output assigned to IOMUX_XBAR_INOUT10 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO11_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 11) /* XBARA1_OUT11 output assigned to IOMUX_XBAR_INOUT11 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO12_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 12) /* XBARA1_OUT12 output assigned to IOMUX_XBAR_INOUT12 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO13_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 13) /* XBARA1_OUT13 output assigned to IOMUX_XBAR_INOUT13 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO14_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 14) /* XBARA1_OUT14 output assigned to IOMUX_XBAR_INOUT14 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO15_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 15) /* XBARA1_OUT15 output assigned to IOMUX_XBAR_INOUT15 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO16_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 16) /* XBARA1_OUT16 output assigned to IOMUX_XBAR_INOUT16 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO17_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 17) /* XBARA1_OUT17 output assigned to IOMUX_XBAR_INOUT17 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO18_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 18) /* XBARA1_OUT18 output assigned to IOMUX_XBAR_INOUT18 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO19_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 19) /* XBARA1_OUT19 output assigned to IOMUX_XBAR_INOUT19 */ -#define IMXRT_XBARA1_OUT_ACMP1_SAMPLE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 20) /* XBARA1_OUT20 output assigned to ACMP1_SAMPLE */ -#define IMXRT_XBARA1_OUT_ACMP2_SAMPLE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 21) /* XBARA1_OUT21 output assigned to ACMP2_SAMPLE */ -#define IMXRT_XBARA1_OUT_ACMP3_SAMPLE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 22) /* XBARA1_OUT22 output assigned to ACMP3_SAMPLE */ -#define IMXRT_XBARA1_OUT_ACMP4_SAMPLE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 23) /* XBARA1_OUT23 output assigned to ACMP4_SAMPLE */ -#define IMXRT_XBARA1_OUT_RESERVED24_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 24) /* XBARA1_OUT24 output is reserved. */ -#define IMXRT_XBARA1_OUT_RESERVED25_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 25) /* XBARA1_OUT25 output is reserved. */ -#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 26) /* XBARA1_OUT26 output assigned to FLEXPWM1_EXTA0 */ -#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 27) /* XBARA1_OUT27 output assigned to FLEXPWM1_EXTA1 */ -#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 28) /* XBARA1_OUT28 output assigned to FLEXPWM1_EXTA2 */ -#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 29) /* XBARA1_OUT29 output assigned to FLEXPWM1_EXTA3 */ -#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 30) /* XBARA1_OUT30 output assigned to FLEXPWM1_EXT_SYNC0 */ -#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 31) /* XBARA1_OUT31 output assigned to FLEXPWM1_EXT_SYNC1 */ -#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 32) /* XBARA1_OUT32 output assigned to FLEXPWM1_EXT_SYNC2 */ -#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 33) /* XBARA1_OUT33 output assigned to FLEXPWM1_EXT_SYNC3 */ -#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_CLK_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 34) /* XBARA1_OUT34 output assigned to FLEXPWM1_EXT_CLK */ -#define IMXRT_XBARA1_OUT_FLEXPWM1_FAULT0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 35) /* XBARA1_OUT35 output assigned to FLEXPWM1_FAULT0 */ -#define IMXRT_XBARA1_OUT_FLEXPWM1_FAULT1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 36) /* XBARA1_OUT36 output assigned to FLEXPWM1_FAULT1 */ -#define IMXRT_XBARA1_OUT_FLEXPWM1234_FAULT2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 37) /* XBARA1_OUT37 output assigned to FLEXPWM1_2_3_4_FAULT2 */ -#define IMXRT_XBARA1_OUT_FLEXPWM1234_FAULT3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 38) /* XBARA1_OUT38 output assigned to FLEXPWM1_2_3_4_FAULT3 */ -#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_FORCE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 39) /* XBARA1_OUT39 output assigned to FLEXPWM1_EXT_FORCE */ -#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 40) /* XBARA1_OUT40 output assigned to FLEXPWM2_3_4_EXTA0 */ -#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 41) /* XBARA1_OUT41 output assigned to FLEXPWM2_3_4_EXTA1 */ -#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 42) /* XBARA1_OUT42 output assigned to FLEXPWM2_3_4_EXTA2 */ -#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 43) /* XBARA1_OUT43 output assigned to FLEXPWM2_3_4_EXTA3 */ -#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 44) /* XBARA1_OUT44 output assigned to FLEXPWM2_EXT_SYNC0 */ -#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 45) /* XBARA1_OUT45 output assigned to FLEXPWM2_EXT_SYNC1 */ -#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 46) /* XBARA1_OUT46 output assigned to FLEXPWM2_EXT_SYNC2 */ -#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 47) /* XBARA1_OUT47 output assigned to FLEXPWM2_EXT_SYNC3 */ -#define IMXRT_XBARA1_OUT_FLEXPWM234_EXT_CLK_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 48) /* XBARA1_OUT48 output assigned to FLEXPWM2_3_4_EXT_CLK */ -#define IMXRT_XBARA1_OUT_FLEXPWM2_FAULT0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 49) /* XBARA1_OUT49 output assigned to FLEXPWM2_FAULT0 */ -#define IMXRT_XBARA1_OUT_FLEXPWM2_FAULT1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 50) /* XBARA1_OUT50 output assigned to FLEXPWM2_FAULT1 */ -#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_FORCE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 51) /* XBARA1_OUT51 output assigned to FLEXPWM2_EXT_FORCE */ -#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 52) /* XBARA1_OUT52 output assigned to FLEXPWM3_EXT_SYNC0 */ -#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 53) /* XBARA1_OUT53 output assigned to FLEXPWM3_EXT_SYNC1 */ -#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 54) /* XBARA1_OUT54 output assigned to FLEXPWM3_EXT_SYNC2 */ -#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 55) /* XBARA1_OUT55 output assigned to FLEXPWM3_EXT_SYNC3 */ -#define IMXRT_XBARA1_OUT_FLEXPWM3_FAULT0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 56) /* XBARA1_OUT56 output assigned to FLEXPWM3_FAULT0 */ -#define IMXRT_XBARA1_OUT_FLEXPWM3_FAULT1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 57) /* XBARA1_OUT57 output assigned to FLEXPWM3_FAULT1 */ -#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_FORCE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 58) /* XBARA1_OUT58 output assigned to FLEXPWM3_EXT_FORCE */ -#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 59) /* XBARA1_OUT59 output assigned to FLEXPWM4_EXT_SYNC0 */ -#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 60) /* XBARA1_OUT60 output assigned to FLEXPWM4_EXT_SYNC1 */ -#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 61) /* XBARA1_OUT61 output assigned to FLEXPWM4_EXT_SYNC2 */ -#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 62) /* XBARA1_OUT62 output assigned to FLEXPWM4_EXT_SYNC3 */ -#define IMXRT_XBARA1_OUT_FLEXPWM4_FAULT0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 63) /* XBARA1_OUT63 output assigned to FLEXPWM4_FAULT0 */ -#define IMXRT_XBARA1_OUT_FLEXPWM4_FAULT1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 64) /* XBARA1_OUT64 output assigned to FLEXPWM4_FAULT1 */ -#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_FORCE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 65) /* XBARA1_OUT65 output assigned to FLEXPWM4_EXT_FORCE */ -#define IMXRT_XBARA1_OUT_ENC1_PHASE_AIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 66) /* XBARA1_OUT66 output assigned to ENC1_PHASE_A_IN_ */ -#define IMXRT_XBARA1_OUT_ENC1_PHASE_BIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 67) /* XBARA1_OUT67 output assigned to ENC1_PHASE_B_IN_ */ -#define IMXRT_XBARA1_OUT_ENC1_INDEX_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 68) /* XBARA1_OUT68 output assigned to ENC1_INDEX */ -#define IMXRT_XBARA1_OUT_ENC1_HOME_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 69) /* XBARA1_OUT69 output assigned to ENC1_HOME */ -#define IMXRT_XBARA1_OUT_ENC1_TRIGGER_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 70) /* XBARA1_OUT70 output assigned to ENC1_TRIGGER */ -#define IMXRT_XBARA1_OUT_ENC2_PHASE_AIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 71) /* XBARA1_OUT71 output assigned to ENC2_PHASE_A_IN_ */ -#define IMXRT_XBARA1_OUT_ENC2_PHASE_BIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 72) /* XBARA1_OUT72 output assigned to ENC2_PHASE_B_IN_ */ -#define IMXRT_XBARA1_OUT_ENC2_INDEX_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 73) /* XBARA1_OUT73 output assigned to ENC2_INDEX */ -#define IMXRT_XBARA1_OUT_ENC2_HOME_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 74) /* XBARA1_OUT74 output assigned to ENC2_HOME */ -#define IMXRT_XBARA1_OUT_ENC2_TRIGGER_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 75) /* XBARA1_OUT75 output assigned to ENC2_TRIGGER */ -#define IMXRT_XBARA1_OUT_ENC3_PHASE_AIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 76) /* XBARA1_OUT76 output assigned to ENC3_PHASE_A_IN_ */ -#define IMXRT_XBARA1_OUT_ENC3_PHASE_BIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 77) /* XBARA1_OUT77 output assigned to ENC3_PHASE_B_IN_ */ -#define IMXRT_XBARA1_OUT_ENC3_INDEX_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 78) /* XBARA1_OUT78 output assigned to ENC3_INDEX */ -#define IMXRT_XBARA1_OUT_ENC3_HOME_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 79) /* XBARA1_OUT79 output assigned to ENC3_HOME */ -#define IMXRT_XBARA1_OUT_ENC3_TRIGGER_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 80) /* XBARA1_OUT80 output assigned to ENC3_TRIGGER */ -#define IMXRT_XBARA1_OUT_ENC4_PHASE_AIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 81) /* XBARA1_OUT81 output assigned to ENC4_PHASE_A_IN_ */ -#define IMXRT_XBARA1_OUT_ENC4_PHASE_BIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 82) /* XBARA1_OUT82 output assigned to ENC4_PHASE_B_IN_ */ -#define IMXRT_XBARA1_OUT_ENC4_INDEX_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 83) /* XBARA1_OUT83 output assigned to ENC4_INDEX */ -#define IMXRT_XBARA1_OUT_ENC4_HOME_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 84) /* XBARA1_OUT84 output assigned to ENC4_HOME */ -#define IMXRT_XBARA1_OUT_ENC4_TRIGGER_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 85) /* XBARA1_OUT85 output assigned to ENC4_TRIGGER */ -#define IMXRT_XBARA1_OUT_QTIMER1_TMR0_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 86) /* XBARA1_OUT86 output assigned to QTIMER1_TMR0_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER1_TMR1_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 87) /* XBARA1_OUT87 output assigned to QTIMER1_TMR1_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER1_TMR2_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 88) /* XBARA1_OUT88 output assigned to QTIMER1_TMR2_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER1_TMR3_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 89) /* XBARA1_OUT89 output assigned to QTIMER1_TMR3_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER2_TMR0_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 90) /* XBARA1_OUT90 output assigned to QTIMER2_TMR0_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER2_TMR1_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 91) /* XBARA1_OUT91 output assigned to QTIMER2_TMR1_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER2_TMR2_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 92) /* XBARA1_OUT92 output assigned to QTIMER2_TMR2_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER2_TMR3_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 93) /* XBARA1_OUT93 output assigned to QTIMER2_TMR3_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER3_TMR0_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 94) /* XBARA1_OUT94 output assigned to QTIMER3_TMR0_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER3_TMR1_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 95) /* XBARA1_OUT95 output assigned to QTIMER3_TMR1_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER3_TMR2_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 96) /* XBARA1_OUT96 output assigned to QTIMER3_TMR2_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER3_TMR3_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 97) /* XBARA1_OUT97 output assigned to QTIMER3_TMR3_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER4_TMR0_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 98) /* XBARA1_OUT98 output assigned to QTIMER4_TMR0_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER4_TMR1_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 99) /* XBARA1_OUT99 output assigned to QTIMER4_TMR1_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER4_TMR2_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 100) /* XBARA1_OUT100 output assigned to QTIMER4_TMR2_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER4_TMR3_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 101) /* XBARA1_OUT101 output assigned to QTIMER4_TMR3_IN_ */ -#define IMXRT_XBARA1_OUT_EWM_EWM_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 102) /* XBARA1_OUT102 output assigned to EWM_EWM_IN */ -#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 103) /* XBARA1_OUT103 output assigned to ADC_ETC_XBAR0_TRIG0 */ -#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 104) /* XBARA1_OUT104 output assigned to ADC_ETC_XBAR0_TRIG1 */ -#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 105) /* XBARA1_OUT105 output assigned to ADC_ETC_XBAR0_TRIG2 */ -#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 106) /* XBARA1_OUT106 output assigned to ADC_ETC_XBAR0_TRIG3 */ -#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 107) /* XBARA1_OUT107 output assigned to ADC_ETC_XBAR1_TRIG0 */ -#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 108) /* XBARA1_OUT108 output assigned to ADC_ETC_XBAR1_TRIG1 */ -#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 109) /* XBARA1_OUT109 output assigned to ADC_ETC_XBAR1_TRIG2 */ -#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 110) /* XBARA1_OUT110 output assigned to ADC_ETC_XBAR1_TRIG3 */ -#define IMXRT_XBARA1_OUT_LPI2C1_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 111) /* XBARA1_OUT111 output assigned to LPI2C1_TRG_IN_ */ -#define IMXRT_XBARA1_OUT_LPI2C2_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 112) /* XBARA1_OUT112 output assigned to LPI2C2_TRG_IN_ */ -#define IMXRT_XBARA1_OUT_LPI2C3_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 113) /* XBARA1_OUT113 output assigned to LPI2C3_TRG_IN_ */ -#define IMXRT_XBARA1_OUT_LPI2C4_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 114) /* XBARA1_OUT114 output assigned to LPI2C4_TRG_IN_ */ -#define IMXRT_XBARA1_OUT_LPSPI1_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 115) /* XBARA1_OUT115 output assigned to LPSPI1_TRG_IN_ */ -#define IMXRT_XBARA1_OUT_LPSPI2_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 116) /* XBARA1_OUT116 output assigned to LPSPI2_TRG_IN_ */ -#define IMXRT_XBARA1_OUT_LPSPI3_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 117) /* XBARA1_OUT117 output assigned to LPSPI3_TRG_IN_ */ -#define IMXRT_XBARA1_OUT_LPSPI4_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 118) /* XBARA1_OUT118 output assigned to LPSPI4_TRG_IN_ */ -#define IMXRT_XBARA1_OUT_LPUART1_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 119) /* XBARA1_OUT119 output assigned to LPUART1_TRG_IN_ */ -#define IMXRT_XBARA1_OUT_LPUART2_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 120) /* XBARA1_OUT120 output assigned to LPUART2_TRG_IN_ */ -#define IMXRT_XBARA1_OUT_LPUART3_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 121) /* XBARA1_OUT121 output assigned to LPUART3_TRG_IN_ */ -#define IMXRT_XBARA1_OUT_LPUART4_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 122) /* XBARA1_OUT122 output assigned to LPUART4_TRG_IN_ */ -#define IMXRT_XBARA1_OUT_LPUART5_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 123) /* XBARA1_OUT123 output assigned to LPUART5_TRG_IN_ */ -#define IMXRT_XBARA1_OUT_LPUART6_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 124) /* XBARA1_OUT124 output assigned to LPUART6_TRG_IN_ */ -#define IMXRT_XBARA1_OUT_LPUART7_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 125) /* XBARA1_OUT125 output assigned to LPUART7_TRG_IN_ */ -#define IMXRT_XBARA1_OUT_LPUART8_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 126) /* XBARA1_OUT126 output assigned to LPUART8_TRG_IN_ */ -#define IMXRT_XBARA1_OUT_FLEXIO1_TRIGGER_IN0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 127) /* XBARA1_OUT127 output assigned to FLEXIO1_TRIGGER_IN0 */ -#define IMXRT_XBARA1_OUT_FLEXIO1_TRIGGER_IN1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 128) /* XBARA1_OUT128 output assigned to FLEXIO1_TRIGGER_IN1 */ -#define IMXRT_XBARA1_OUT_FLEXIO2_TRIGGER_IN0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 129) /* XBARA1_OUT129 output assigned to FLEXIO2_TRIGGER_IN0 */ -#define IMXRT_XBARA1_OUT_FLEXIO2_TRIGGER_IN1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 130) /* XBARA1_OUT130 output assigned to FLEXIO2_TRIGGER_IN1 */ - -/* XBARB2 Mux inputs (I values) *******************************************************************************************************************/ - -#define IMXRT_XBARB2_IN_LOGIC_LOW IMXRT_XBARB2(XBAR_INPUT, 0) /* LOGIC_LOW output assigned to XBARB2_IN0 input. */ -#define IMXRT_XBARB2_IN_LOGIC_HIGH IMXRT_XBARB2(XBAR_INPUT, 1) /* LOGIC_HIGH output assigned to XBARB2_IN1 input. */ -#define IMXRT_XBARB2_IN_RESERVED2 IMXRT_XBARB2(XBAR_INPUT, 2) /* XBARB2_IN2 input is reserved. */ -#define IMXRT_XBARB2_IN_RESERVED3 IMXRT_XBARB2(XBAR_INPUT, 3) /* XBARB2_IN3 input is reserved. */ -#define IMXRT_XBARB2_IN_RESERVED4 IMXRT_XBARB2(XBAR_INPUT, 4) /* XBARB2_IN4 input is reserved. */ -#define IMXRT_XBARB2_IN_RESERVED5 IMXRT_XBARB2(XBAR_INPUT, 5) /* XBARB2_IN5 input is reserved. */ -#define IMXRT_XBARB2_IN_ACMP1_OUT IMXRT_XBARB2(XBAR_INPUT, 6) /* ACMP1_OUT output assigned to XBARB2_IN6 input. */ -#define IMXRT_XBARB2_IN_ACMP2_OUT IMXRT_XBARB2(XBAR_INPUT, 7) /* ACMP2_OUT output assigned to XBARB2_IN7 input. */ -#define IMXRT_XBARB2_IN_ACMP3_OUT IMXRT_XBARB2(XBAR_INPUT, 8) /* ACMP3_OUT output assigned to XBARB2_IN8 input. */ -#define IMXRT_XBARB2_IN_ACMP4_OUT IMXRT_XBARB2(XBAR_INPUT, 9) /* ACMP4_OUT output assigned to XBARB2_IN9 input. */ -#define IMXRT_XBARB2_IN_RESERVED10 IMXRT_XBARB2(XBAR_INPUT, 10) /* XBARB2_IN10 input is reserved. */ -#define IMXRT_XBARB2_IN_RESERVED11 IMXRT_XBARB2(XBAR_INPUT, 11) /* XBARB2_IN11 input is reserved. */ -#define IMXRT_XBARB2_IN_QTIMER3_TMR0_OUT IMXRT_XBARB2(XBAR_INPUT, 12) /* QTIMER3_TMR0_OUTPUT output assigned to XBARB2_IN12 input. */ -#define IMXRT_XBARB2_IN_QTIMER3_TMR1_OUT IMXRT_XBARB2(XBAR_INPUT, 13) /* QTIMER3_TMR1_OUTPUT output assigned to XBARB2_IN13 input. */ -#define IMXRT_XBARB2_IN_QTIMER3_TMR2_OUT IMXRT_XBARB2(XBAR_INPUT, 14) /* QTIMER3_TMR2_OUTPUT output assigned to XBARB2_IN14 input. */ -#define IMXRT_XBARB2_IN_QTIMER3_TMR3_OUT IMXRT_XBARB2(XBAR_INPUT, 15) /* QTIMER3_TMR3_OUTPUT output assigned to XBARB2_IN15 input. */ -#define IMXRT_XBARB2_IN_QTIMER4_TMR0_OUT IMXRT_XBARB2(XBAR_INPUT, 16) /* QTIMER4_TMR0_OUTPUT output assigned to XBARB2_IN16 input. */ -#define IMXRT_XBARB2_IN_QTIMER4_TMR1_OUT IMXRT_XBARB2(XBAR_INPUT, 17) /* QTIMER4_TMR1_OUTPUT output assigned to XBARB2_IN17 input. */ -#define IMXRT_XBARB2_IN_QTIMER4_TMR2_OUT IMXRT_XBARB2(XBAR_INPUT, 18) /* QTIMER4_TMR2_OUTPUT output assigned to XBARB2_IN18 input. */ -#define IMXRT_XBARB2_IN_QTIMER4_TMR3_OUT IMXRT_XBARB2(XBAR_INPUT, 19) /* QTIMER4_TMR3_OUTPUT output assigned to XBARB2_IN19 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM1_PWM1_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 20) /* FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN20 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM1_PWM2_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 21) /* FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN21 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM1_PWM3_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 22) /* FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN22 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM1_PWM4_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 23) /* FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN23 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM2_PWM1_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 24) /* FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN24 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM2_PWM2_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 25) /* FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN25 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM2_PWM3_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 26) /* FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN26 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM2_PWM4_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 27) /* FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN27 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM3_PWM1_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 28) /* FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN28 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM3_PWM2_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 29) /* FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN29 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM3_PWM3_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 30) /* FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN30 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM3_PWM4_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 31) /* FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN31 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM4_PWM1_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 32) /* FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN32 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM4_PWM2_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 33) /* FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN33 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM4_PWM3_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 34) /* FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN34 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM4_PWM4_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 35) /* FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN35 input. */ -#define IMXRT_XBARB2_IN_PIT_TRIGGER0 IMXRT_XBARB2(XBAR_INPUT, 36) /* PIT_TRIGGER0 output assigned to XBARB2_IN36 input. */ -#define IMXRT_XBARB2_IN_PIT_TRIGGER1 IMXRT_XBARB2(XBAR_INPUT, 37) /* PIT_TRIGGER1 output assigned to XBARB2_IN37 input. */ -#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO0 IMXRT_XBARB2(XBAR_INPUT, 38) /* ADC_ETC_XBAR0_COCO0 output assigned to XBARB2_IN38 input. */ -#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO1 IMXRT_XBARB2(XBAR_INPUT, 39) /* ADC_ETC_XBAR0_COCO1 output assigned to XBARB2_IN39 input. */ -#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO2 IMXRT_XBARB2(XBAR_INPUT, 40) /* ADC_ETC_XBAR0_COCO2 output assigned to XBARB2_IN40 input. */ -#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO3 IMXRT_XBARB2(XBAR_INPUT, 41) /* ADC_ETC_XBAR0_COCO3 output assigned to XBARB2_IN41 input. */ -#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO0 IMXRT_XBARB2(XBAR_INPUT, 42) /* ADC_ETC_XBAR1_COCO0 output assigned to XBARB2_IN42 input. */ -#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO1 IMXRT_XBARB2(XBAR_INPUT, 43) /* ADC_ETC_XBAR1_COCO1 output assigned to XBARB2_IN43 input. */ -#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO2 IMXRT_XBARB2(XBAR_INPUT, 44) /* ADC_ETC_XBAR1_COCO2 output assigned to XBARB2_IN44 input. */ -#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO3 IMXRT_XBARB2(XBAR_INPUT, 45) /* ADC_ETC_XBAR1_COCO3 output assigned to XBARB2_IN45 input. */ -#define IMXRT_XBARB2_IN_ENC1_POS_MATCH IMXRT_XBARB2(XBAR_INPUT, 46) /* ENC1_POS_MATCH output assigned to XBARB2_IN46 input. */ -#define IMXRT_XBARB2_IN_ENC2_POS_MATCH IMXRT_XBARB2(XBAR_INPUT, 47) /* ENC2_POS_MATCH output assigned to XBARB2_IN47 input. */ -#define IMXRT_XBARB2_IN_ENC3_POS_MATCH IMXRT_XBARB2(XBAR_INPUT, 48) /* ENC3_POS_MATCH output assigned to XBARB2_IN48 input. */ -#define IMXRT_XBARB2_IN_ENC4_POS_MATCH IMXRT_XBARB2(XBAR_INPUT, 49) /* ENC4_POS_MATCH output assigned to XBARB2_IN49 input. */ -#define IMXRT_XBARB2_IN_DMA_DONE0 IMXRT_XBARB2(XBAR_INPUT, 50) /* DMA_DONE0 output assigned to XBARB2_IN50 input. */ -#define IMXRT_XBARB2_IN_DMA_DONE1 IMXRT_XBARB2(XBAR_INPUT, 51) /* DMA_DONE1 output assigned to XBARB2_IN51 input. */ -#define IMXRT_XBARB2_IN_DMA_DONE2 IMXRT_XBARB2(XBAR_INPUT, 52) /* DMA_DONE2 output assigned to XBARB2_IN52 input. */ -#define IMXRT_XBARB2_IN_DMA_DONE3 IMXRT_XBARB2(XBAR_INPUT, 53) /* DMA_DONE3 output assigned to XBARB2_IN53 input. */ -#define IMXRT_XBARB2_IN_DMA_DONE4 IMXRT_XBARB2(XBAR_INPUT, 54) /* DMA_DONE4 output assigned to XBARB2_IN54 input. */ -#define IMXRT_XBARB2_IN_DMA_DONE5 IMXRT_XBARB2(XBAR_INPUT, 55) /* DMA_DONE5 output assigned to XBARB2_IN55 input. */ -#define IMXRT_XBARB2_IN_DMA_DONE6 IMXRT_XBARB2(XBAR_INPUT, 56) /* DMA_DONE6 output assigned to XBARB2_IN56 input. */ -#define IMXRT_XBARB2_IN_DMA_DONE7 IMXRT_XBARB2(XBAR_INPUT, 57) /* DMA_DONE7 output assigned to XBARB2_IN57 input. */ - -/* XBARB2 Mux Output (M Muxes) ********************************************************************************************************************/ - -#define IMXRT_XBARB2_OUT_AOI1_IN00_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 0) /* XBARB2_OUT0 output assigned to AOI1_IN00 */ -#define IMXRT_XBARB2_OUT_AOI1_IN01_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 1) /* XBARB2_OUT1 output assigned to AOI1_IN01 */ -#define IMXRT_XBARB2_OUT_AOI1_IN02_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 2) /* XBARB2_OUT2 output assigned to AOI1_IN02 */ -#define IMXRT_XBARB2_OUT_AOI1_IN03_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 3) /* XBARB2_OUT3 output assigned to AOI1_IN03 */ -#define IMXRT_XBARB2_OUT_AOI1_IN04_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 4) /* XBARB2_OUT4 output assigned to AOI1_IN04 */ -#define IMXRT_XBARB2_OUT_AOI1_IN05_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 5) /* XBARB2_OUT5 output assigned to AOI1_IN05 */ -#define IMXRT_XBARB2_OUT_AOI1_IN06_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 6) /* XBARB2_OUT6 output assigned to AOI1_IN06 */ -#define IMXRT_XBARB2_OUT_AOI1_IN07_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 7) /* XBARB2_OUT7 output assigned to AOI1_IN07 */ -#define IMXRT_XBARB2_OUT_AOI1_IN08_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 8) /* XBARB2_OUT8 output assigned to AOI1_IN08 */ -#define IMXRT_XBARB2_OUT_AOI1_IN09_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 9) /* XBARB2_OUT9 output assigned to AOI1_IN09 */ -#define IMXRT_XBARB2_OUT_AOI1_IN10_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 10) /* XBARB2_OUT10 output assigned to AOI1_IN10 */ -#define IMXRT_XBARB2_OUT_AOI1_IN11_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 11) /* XBARB2_OUT11 output assigned to AOI1_IN11 */ -#define IMXRT_XBARB2_OUT_AOI1_IN12_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 12) /* XBARB2_OUT12 output assigned to AOI1_IN12 */ -#define IMXRT_XBARB2_OUT_AOI1_IN13_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 13) /* XBARB2_OUT13 output assigned to AOI1_IN13 */ -#define IMXRT_XBARB2_OUT_AOI1_IN14_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 14) /* XBARB2_OUT14 output assigned to AOI1_IN14 */ -#define IMXRT_XBARB2_OUT_AOI1_IN15_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 15) /* XBARB2_OUT15 output assigned to AOI1_IN15 */ - -/* XBARB3 Mux inputs (I values) *******************************************************************************************************************/ - -#define IMXRT_XBARB3_IN_LOGIC_LOW IMXRT_XBARB3(XBAR_INPUT, 0) /* LOGIC_LOW output assigned to XBARB3_IN0 input. */ -#define IMXRT_XBARB3_IN_LOGIC_HIGH IMXRT_XBARB3(XBAR_INPUT, 1) /* LOGIC_HIGH output assigned to XBARB3_IN1 input. */ -#define IMXRT_XBARB3_IN_RESERVED2 IMXRT_XBARB3(XBAR_INPUT, 2) /* XBARB3_IN2 input is reserved. */ -#define IMXRT_XBARB3_IN_RESERVED3 IMXRT_XBARB3(XBAR_INPUT, 3) /* XBARB3_IN3 input is reserved. */ -#define IMXRT_XBARB3_IN_RESERVED4 IMXRT_XBARB3(XBAR_INPUT, 4) /* XBARB3_IN4 input is reserved. */ -#define IMXRT_XBARB3_IN_RESERVED5 IMXRT_XBARB3(XBAR_INPUT, 5) /* XBARB3_IN5 input is reserved. */ -#define IMXRT_XBARB3_IN_ACMP1_OUT IMXRT_XBARB3(XBAR_INPUT, 6) /* ACMP1_OUT output assigned to XBARB3_IN6 input. */ -#define IMXRT_XBARB3_IN_ACMP2_OUT IMXRT_XBARB3(XBAR_INPUT, 7) /* ACMP2_OUT output assigned to XBARB3_IN7 input. */ -#define IMXRT_XBARB3_IN_ACMP3_OUT IMXRT_XBARB3(XBAR_INPUT, 8) /* ACMP3_OUT output assigned to XBARB3_IN8 input. */ -#define IMXRT_XBARB3_IN_ACMP4_OUT IMXRT_XBARB3(XBAR_INPUT, 9) /* ACMP4_OUT output assigned to XBARB3_IN9 input. */ -#define IMXRT_XBARB3_IN_RESERVED10 IMXRT_XBARB3(XBAR_INPUT, 10) /* XBARB3_IN10 input is reserved. */ -#define IMXRT_XBARB3_IN_RESERVED11 IMXRT_XBARB3(XBAR_INPUT, 11) /* XBARB3_IN11 input is reserved. */ -#define IMXRT_XBARB3_IN_QTIMER3_TMR0_OUT IMXRT_XBARB3(XBAR_INPUT, 12) /* QTIMER3_TMR0_OUTPUT output assigned to XBARB3_IN12 input. */ -#define IMXRT_XBARB3_IN_QTIMER3_TMR1_OUT IMXRT_XBARB3(XBAR_INPUT, 13) /* QTIMER3_TMR1_OUTPUT output assigned to XBARB3_IN13 input. */ -#define IMXRT_XBARB3_IN_QTIMER3_TMR2_OUT IMXRT_XBARB3(XBAR_INPUT, 14) /* QTIMER3_TMR2_OUTPUT output assigned to XBARB3_IN14 input. */ -#define IMXRT_XBARB3_IN_QTIMER3_TMR3_OUT IMXRT_XBARB3(XBAR_INPUT, 15) /* QTIMER3_TMR3_OUTPUT output assigned to XBARB3_IN15 input. */ -#define IMXRT_XBARB3_IN_QTIMER4_TMR0_OUT IMXRT_XBARB3(XBAR_INPUT, 16) /* QTIMER4_TMR0_OUTPUT output assigned to XBARB3_IN16 input. */ -#define IMXRT_XBARB3_IN_QTIMER4_TMR1_OUT IMXRT_XBARB3(XBAR_INPUT, 17) /* QTIMER4_TMR1_OUTPUT output assigned to XBARB3_IN17 input. */ -#define IMXRT_XBARB3_IN_QTIMER4_TMR2_OUT IMXRT_XBARB3(XBAR_INPUT, 18) /* QTIMER4_TMR2_OUTPUT output assigned to XBARB3_IN18 input. */ -#define IMXRT_XBARB3_IN_QTIMER4_TMR3_OUT IMXRT_XBARB3(XBAR_INPUT, 19) /* QTIMER4_TMR3_OUTPUT output assigned to XBARB3_IN19 input. */ -#define IMXRT_XBARB3_IN_FLEXPWM1_PWM1_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 20) /* FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN20 input. */ -#define IMXRT_XBARB3_IN_FLEXPWM1_PWM2_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 21) /* FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN21 input. */ -#define IMXRT_XBARB3_IN_FLEXPWM1_PWM3_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 22) /* FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN22 input. */ -#define IMXRT_XBARB3_IN_FLEXPWM1_PWM4_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 23) /* FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN23 input. */ -#define IMXRT_XBARB3_IN_FLEXPWM2_PWM1_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 24) /* FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN24 input. */ -#define IMXRT_XBARB3_IN_FLEXPWM2_PWM2_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 25) /* FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN25 input. */ -#define IMXRT_XBARB3_IN_FLEXPWM2_PWM3_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 26) /* FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN26 input. */ -#define IMXRT_XBARB3_IN_FLEXPWM2_PWM4_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 27) /* FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN27 input. */ -#define IMXRT_XBARB3_IN_FLEXPWM3_PWM1_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 28) /* FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN28 input. */ -#define IMXRT_XBARB3_IN_FLEXPWM3_PWM2_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 29) /* FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN29 input. */ -#define IMXRT_XBARB3_IN_FLEXPWM3_PWM3_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 30) /* FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN30 input. */ -#define IMXRT_XBARB3_IN_FLEXPWM3_PWM4_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 31) /* FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN31 input. */ -#define IMXRT_XBARB3_IN_FLEXPWM4_PWM1_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 32) /* FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN32 input. */ -#define IMXRT_XBARB3_IN_FLEXPWM4_PWM2_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 33) /* FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN33 input. */ -#define IMXRT_XBARB3_IN_FLEXPWM4_PWM3_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 34) /* FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN34 input. */ -#define IMXRT_XBARB3_IN_FLEXPWM4_PWM4_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 35) /* FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN35 input. */ -#define IMXRT_XBARB3_IN_PIT_TRIGGER0 IMXRT_XBARB3(XBAR_INPUT, 36) /* PIT_TRIGGER0 output assigned to XBARB3_IN36 input. */ -#define IMXRT_XBARB3_IN_PIT_TRIGGER1 IMXRT_XBARB3(XBAR_INPUT, 37) /* PIT_TRIGGER1 output assigned to XBARB3_IN37 input. */ -#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO0 IMXRT_XBARB3(XBAR_INPUT, 38) /* ADC_ETC_XBAR0_COCO0 output assigned to XBARB3_IN38 input. */ -#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO1 IMXRT_XBARB3(XBAR_INPUT, 39) /* ADC_ETC_XBAR0_COCO1 output assigned to XBARB3_IN39 input. */ -#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO2 IMXRT_XBARB3(XBAR_INPUT, 40) /* ADC_ETC_XBAR0_COCO2 output assigned to XBARB3_IN40 input. */ -#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO3 IMXRT_XBARB3(XBAR_INPUT, 41) /* ADC_ETC_XBAR0_COCO3 output assigned to XBARB3_IN41 input. */ -#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO0 IMXRT_XBARB3(XBAR_INPUT, 42) /* ADC_ETC_XBAR1_COCO0 output assigned to XBARB3_IN42 input. */ -#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO1 IMXRT_XBARB3(XBAR_INPUT, 43) /* ADC_ETC_XBAR1_COCO1 output assigned to XBARB3_IN43 input. */ -#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO2 IMXRT_XBARB3(XBAR_INPUT, 44) /* ADC_ETC_XBAR1_COCO2 output assigned to XBARB3_IN44 input. */ -#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO3 IMXRT_XBARB3(XBAR_INPUT, 45) /* ADC_ETC_XBAR1_COCO3 output assigned to XBARB3_IN45 input. */ -#define IMXRT_XBARB3_IN_ENC1_POS_MATCH IMXRT_XBARB3(XBAR_INPUT, 46) /* ENC1_POS_MATCH output assigned to XBARB3_IN46 input. */ -#define IMXRT_XBARB3_IN_ENC2_POS_MATCH IMXRT_XBARB3(XBAR_INPUT, 47) /* ENC2_POS_MATCH output assigned to XBARB3_IN47 input. */ -#define IMXRT_XBARB3_IN_ENC3_POS_MATCH IMXRT_XBARB3(XBAR_INPUT, 48) /* ENC3_POS_MATCH output assigned to XBARB3_IN48 input. */ -#define IMXRT_XBARB3_IN_ENC4_POS_MATCH IMXRT_XBARB3(XBAR_INPUT, 49) /* ENC4_POS_MATCH output assigned to XBARB3_IN49 input. */ -#define IMXRT_XBARB3_IN_DMA_DONE0 IMXRT_XBARB3(XBAR_INPUT, 50) /* DMA_DONE0 output assigned to XBARB3_IN50 input. */ -#define IMXRT_XBARB3_IN_DMA_DONE1 IMXRT_XBARB3(XBAR_INPUT, 51) /* DMA_DONE1 output assigned to XBARB3_IN51 input. */ -#define IMXRT_XBARB3_IN_DMA_DONE2 IMXRT_XBARB3(XBAR_INPUT, 52) /* DMA_DONE2 output assigned to XBARB3_IN52 input. */ -#define IMXRT_XBARB3_IN_DMA_DONE3 IMXRT_XBARB3(XBAR_INPUT, 53) /* DMA_DONE3 output assigned to XBARB3_IN53 input. */ -#define IMXRT_XBARB3_IN_DMA_DONE4 IMXRT_XBARB3(XBAR_INPUT, 54) /* DMA_DONE4 output assigned to XBARB3_IN54 input. */ -#define IMXRT_XBARB3_IN_DMA_DONE5 IMXRT_XBARB3(XBAR_INPUT, 55) /* DMA_DONE5 output assigned to XBARB3_IN55 input. */ -#define IMXRT_XBARB3_IN_DMA_DONE6 IMXRT_XBARB3(XBAR_INPUT, 56) /* DMA_DONE6 output assigned to XBARB3_IN56 input. */ -#define IMXRT_XBARB3_IN_DMA_DONE7 IMXRT_XBARB3(XBAR_INPUT, 57) /* DMA_DONE7 output assigned to XBARB3_IN57 input. */ - -/* XBARB3 Mux Output (M Muxes) ********************************************************************************************************************/ - -#define IMXRT_XBARB3_OUT_AOI2_IN00_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 0) /* XBARB3_OUT0 output assigned to AOI2_IN00 */ -#define IMXRT_XBARB3_OUT_AOI2_IN01_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 1) /* XBARB3_OUT1 output assigned to AOI2_IN01 */ -#define IMXRT_XBARB3_OUT_AOI2_IN02_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 2) /* XBARB3_OUT2 output assigned to AOI2_IN02 */ -#define IMXRT_XBARB3_OUT_AOI2_IN03_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 3) /* XBARB3_OUT3 output assigned to AOI2_IN03 */ -#define IMXRT_XBARB3_OUT_AOI2_IN04_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 4) /* XBARB3_OUT4 output assigned to AOI2_IN04 */ -#define IMXRT_XBARB3_OUT_AOI2_IN05_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 5) /* XBARB3_OUT5 output assigned to AOI2_IN05 */ -#define IMXRT_XBARB3_OUT_AOI2_IN06_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 6) /* XBARB3_OUT6 output assigned to AOI2_IN06 */ -#define IMXRT_XBARB3_OUT_AOI2_IN07_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 7) /* XBARB3_OUT7 output assigned to AOI2_IN07 */ -#define IMXRT_XBARB3_OUT_AOI2_IN08_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 8) /* XBARB3_OUT8 output assigned to AOI2_IN08 */ -#define IMXRT_XBARB3_OUT_AOI2_IN09_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 9) /* XBARB3_OUT9 output assigned to AOI2_IN09 */ -#define IMXRT_XBARB3_OUT_AOI2_IN10_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 10) /* XBARB3_OUT10 output assigned to AOI2_IN10 */ -#define IMXRT_XBARB3_OUT_AOI2_IN11_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 11) /* XBARB3_OUT11 output assigned to AOI2_IN11 */ -#define IMXRT_XBARB3_OUT_AOI2_IN12_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 12) /* XBARB3_OUT12 output assigned to AOI2_IN12 */ -#define IMXRT_XBARB3_OUT_AOI2_IN13_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 13) /* XBARB3_OUT13 output assigned to AOI2_IN13 */ -#define IMXRT_XBARB3_OUT_AOI2_IN14_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 14) /* XBARB3_OUT14 output assigned to AOI2_IN14 */ -#define IMXRT_XBARB3_OUT_AOI2_IN15_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 15) /* XBARB3_OUT15 output assigned to AOI2_IN15 */ diff --git a/arch/arm/src/imxrt/imxrt_allocateheap.c b/arch/arm/src/imxrt/imxrt_allocateheap.c index 8404f2d58c7..22a0a406d1d 100644 --- a/arch/arm/src/imxrt/imxrt_allocateheap.c +++ b/arch/arm/src/imxrt/imxrt_allocateheap.c @@ -54,7 +54,7 @@ #include "up_arch.h" #include "up_internal.h" -#include "chip/imxrt_memorymap.h" +#include "hardware/imxrt_memorymap.h" #include "imxrt_mpuinit.h" #include diff --git a/arch/arm/src/imxrt/imxrt_clockconfig.c b/arch/arm/src/imxrt/imxrt_clockconfig.c index 6d38cae7702..9037d72020b 100644 --- a/arch/arm/src/imxrt/imxrt_clockconfig.c +++ b/arch/arm/src/imxrt/imxrt_clockconfig.c @@ -44,11 +44,11 @@ #include "up_arch.h" #include -#include "chip/imxrt_ccm.h" -#include "chip/imxrt_dcdc.h" +#include "hardware/imxrt_ccm.h" +#include "hardware/imxrt_dcdc.h" #include "imxrt_clockconfig.h" #include "imxrt_lcd.h" -#include "chip/imxrt_memorymap.h" +#include "hardware/imxrt_memorymap.h" #include diff --git a/arch/arm/src/imxrt/imxrt_daisy.c b/arch/arm/src/imxrt/imxrt_daisy.c index 7d668e62680..4fa9d42309d 100644 --- a/arch/arm/src/imxrt/imxrt_daisy.c +++ b/arch/arm/src/imxrt/imxrt_daisy.c @@ -42,7 +42,7 @@ #include #include "chip.h" #include "up_arch.h" -#include "chip/imxrt_daisy.h" +#include "hardware/imxrt_daisy.h" #include "imxrt_iomuxc.h" /**************************************************************************** diff --git a/arch/arm/src/imxrt/imxrt_edma.c b/arch/arm/src/imxrt/imxrt_edma.c index e0c69ede70b..18c79019d60 100644 --- a/arch/arm/src/imxrt/imxrt_edma.c +++ b/arch/arm/src/imxrt/imxrt_edma.c @@ -62,8 +62,8 @@ #include "sched/sched.h" #include "chip.h" -#include "chip/imxrt_edma.h" -#include "chip/imxrt_dmamux.h" +#include "hardware/imxrt_edma.h" +#include "hardware/imxrt_dmamux.h" #include "imxrt_periphclks.h" #include "imxrt_edma.h" @@ -886,7 +886,7 @@ void weak_function up_dma_initialize(void) * * Input Parameters: * dmamux - DMAMUX configuration see DMAMUX channel configuration register - * bit-field definitions in chip/imxrt_dmamux.h. Settings include: + * bit-field definitions in hardware/imxrt_dmamux.h. Settings include: * * DMAMUX_CHCFG_SOURCE Chip-specific DMA source (required) * DMAMUX_CHCFG_AON DMA Channel Always Enable (optional) @@ -896,7 +896,7 @@ void weak_function up_dma_initialize(void) * A value of zero will disable the DMAMUX channel. * dchpri - DCHPRI channel priority configuration. See DCHPRI channel * configuration register bit-field definitions in - * chip/imxrt_edma.h. Meaningful settings include: + * hardware/imxrt_edma.h. Meaningful settings include: * * EDMA_DCHPRI_CHPRI Channel Arbitration Priority * DCHPRI_DPA Disable Preempt Ability diff --git a/arch/arm/src/imxrt/imxrt_edma.h b/arch/arm/src/imxrt/imxrt_edma.h index ed7713b6851..12813a8f127 100644 --- a/arch/arm/src/imxrt/imxrt_edma.h +++ b/arch/arm/src/imxrt/imxrt_edma.h @@ -100,7 +100,7 @@ #include #include -#include "chip/imxrt_edma.h" +#include "hardware/imxrt_edma.h" /************************************************************************************ * Pre-processor Definitions @@ -145,7 +145,7 @@ struct imxrt_edma_xfrconfig_s int16_t doff; /* Sign-extended offset for current destination address. */ uint16_t iter; /* Major loop iteration count. */ uint8_t flags; /* See EDMA_CONFIG_* definitions */ - uint8_t ssize; /* Source data transfer size (see TCD_ATTR_SIZE_* definitions in chip/. */ + uint8_t ssize; /* Source data transfer size (see TCD_ATTR_SIZE_* definitions in rdware/. */ uint8_t dsize; /* Destination data transfer size. */ uint8_t ttype; /* Transfer type (see enum imxrt_edma_xfrtype_e). */ #ifdef CONFIG_IMXRT_EDMA_EMLIM @@ -231,7 +231,7 @@ extern "C" * * Input Parameters: * dmamux - DMAMUX configuration see DMAMUX channel configuration register - * bit-field definitions in chip/imxrt_dmamux.h. Settings include: + * bit-field definitions in hardware/imxrt_dmamux.h. Settings include: * * DMAMUX_CHCFG_SOURCE Chip-specific DMA source (required) * DMAMUX_CHCFG_AON DMA Channel Always Enable (optional) @@ -241,7 +241,7 @@ extern "C" * A value of zero will disable the DMAMUX channel. * dchpri - DCHPRI channel priority configuration. See DCHPRI channel * configuration register bit-field definitions in - * chip/imxrt_edma.h. Meaningful settings include: + * hardware/imxrt_edma.h. Meaningful settings include: * * EDMA_DCHPRI_CHPRI Channel Arbitration Priority * DCHPRI_DPA Disable Preempt Ability diff --git a/arch/arm/src/imxrt/imxrt_enet.c b/arch/arm/src/imxrt/imxrt_enet.c index b08780c5251..3b4eeb7ee5d 100644 --- a/arch/arm/src/imxrt/imxrt_enet.c +++ b/arch/arm/src/imxrt/imxrt_enet.c @@ -66,9 +66,9 @@ #include "up_arch.h" #include "chip.h" #include "imxrt_config.h" -#include "chip/imxrt_enet.h" -#include "chip/imxrt_ccm.h" -#include "chip/imxrt_pinmux.h" +#include "hardware/imxrt_enet.h" +#include "hardware/imxrt_ccm.h" +#include "hardware/imxrt_pinmux.h" #include "imxrt_periphclks.h" #include "imxrt_gpio.h" #include "imxrt_enet.h" diff --git a/arch/arm/src/imxrt/imxrt_enet.h b/arch/arm/src/imxrt/imxrt_enet.h index 311fda56adf..ac63fb1e94a 100644 --- a/arch/arm/src/imxrt/imxrt_enet.h +++ b/arch/arm/src/imxrt/imxrt_enet.h @@ -42,7 +42,7 @@ #include -#include "chip/imxrt_enet.h" +#include "hardware/imxrt_enet.h" #ifdef CONFIG_IMXRT_ENET diff --git a/arch/arm/src/imxrt/imxrt_gpio.c b/arch/arm/src/imxrt/imxrt_gpio.c index 0997c1fb63c..35951e3e780 100644 --- a/arch/arm/src/imxrt/imxrt_gpio.c +++ b/arch/arm/src/imxrt/imxrt_gpio.c @@ -51,7 +51,7 @@ #include "up_arch.h" #include "imxrt_iomuxc.h" #include "imxrt_gpio.h" -#include "chip/imxrt_daisy.h" +#include "hardware/imxrt_daisy.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/imxrt/imxrt_gpio.h b/arch/arm/src/imxrt/imxrt_gpio.h index 3d44e475ba1..825523836d3 100644 --- a/arch/arm/src/imxrt/imxrt_gpio.h +++ b/arch/arm/src/imxrt/imxrt_gpio.h @@ -47,7 +47,7 @@ #include #include "chip.h" -#include "chip/imxrt_gpio.h" +#include "hardware/imxrt_gpio.h" /************************************************************************************ * Pre-processor Definitions diff --git a/arch/arm/src/imxrt/imxrt_hprtc.c b/arch/arm/src/imxrt/imxrt_hprtc.c index 71cffbcc472..9d2488a1e73 100644 --- a/arch/arm/src/imxrt/imxrt_hprtc.c +++ b/arch/arm/src/imxrt/imxrt_hprtc.c @@ -54,7 +54,7 @@ #include "up_arch.h" -#include "chip/imxrt_snvs.h" +#include "hardware/imxrt_snvs.h" #include "imxrt_periphclks.h" #include "imxrt_lpsrtc.h" #include "imxrt_hprtc.h" diff --git a/arch/arm/src/imxrt/imxrt_iomuxc.c b/arch/arm/src/imxrt/imxrt_iomuxc.c index 3b7a15217fd..89deb0c5695 100644 --- a/arch/arm/src/imxrt/imxrt_iomuxc.c +++ b/arch/arm/src/imxrt/imxrt_iomuxc.c @@ -48,7 +48,7 @@ #include #include "up_arch.h" -#include "chip/imxrt_ccm.h" +#include "hardware/imxrt_ccm.h" #include "imxrt_periphclks.h" #include "imxrt_iomuxc.h" diff --git a/arch/arm/src/imxrt/imxrt_iomuxc.h b/arch/arm/src/imxrt/imxrt_iomuxc.h index 994e9231be6..890cc5b4172 100644 --- a/arch/arm/src/imxrt/imxrt_iomuxc.h +++ b/arch/arm/src/imxrt/imxrt_iomuxc.h @@ -44,7 +44,7 @@ #include -#include "chip/imxrt_iomuxc.h" +#include "hardware/imxrt_iomuxc.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/imxrt/imxrt_lcd.c b/arch/arm/src/imxrt/imxrt_lcd.c index 815f08a2e1b..884e54d7446 100644 --- a/arch/arm/src/imxrt/imxrt_lcd.c +++ b/arch/arm/src/imxrt/imxrt_lcd.c @@ -58,7 +58,7 @@ #include "imxrt_gpio.h" #include "imxrt_iomuxc.h" -#include "chip/imxrt_pinmux.h" +#include "hardware/imxrt_pinmux.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/imxrt/imxrt_lcd.h b/arch/arm/src/imxrt/imxrt_lcd.h index a383f5fcf9d..9561bc65467 100644 --- a/arch/arm/src/imxrt/imxrt_lcd.h +++ b/arch/arm/src/imxrt/imxrt_lcd.h @@ -44,7 +44,7 @@ * Included Files ****************************************************************************/ -#include "chip/imxrt_lcd.h" +#include "hardware/imxrt_lcd.h" #include diff --git a/arch/arm/src/imxrt/imxrt_lowputc.c b/arch/arm/src/imxrt/imxrt_lowputc.c index 742d4bf1439..a02dd63c97c 100644 --- a/arch/arm/src/imxrt/imxrt_lowputc.c +++ b/arch/arm/src/imxrt/imxrt_lowputc.c @@ -45,10 +45,10 @@ #include "up_arch.h" -#include "chip/imxrt_iomuxc.h" -#include "chip/imxrt_pinmux.h" -#include "chip/imxrt_ccm.h" -#include "chip/imxrt_lpuart.h" +#include "hardware/imxrt_iomuxc.h" +#include "hardware/imxrt_pinmux.h" +#include "hardware/imxrt_ccm.h" +#include "hardware/imxrt_lpuart.h" #include "imxrt_config.h" #include "imxrt_periphclks.h" #include "imxrt_iomuxc.h" diff --git a/arch/arm/src/imxrt/imxrt_lpi2c.c b/arch/arm/src/imxrt/imxrt_lpi2c.c index b4dd258fc43..310055badb9 100644 --- a/arch/arm/src/imxrt/imxrt_lpi2c.c +++ b/arch/arm/src/imxrt/imxrt_lpi2c.c @@ -61,9 +61,9 @@ #include "imxrt_lpi2c.h" #include "imxrt_gpio.h" -#include "chip/imxrt_pinmux.h" -#include "chip/imxrt_ccm.h" -#include "chip/imxrt_periphclks.h" +#include "hardware/imxrt_pinmux.h" +#include "hardware/imxrt_ccm.h" +#include "hardware/imxrt_periphclks.h" /* At least one I2C peripheral must be enabled */ diff --git a/arch/arm/src/imxrt/imxrt_lpi2c.h b/arch/arm/src/imxrt/imxrt_lpi2c.h index af11de8d340..d229547c228 100644 --- a/arch/arm/src/imxrt/imxrt_lpi2c.h +++ b/arch/arm/src/imxrt/imxrt_lpi2c.h @@ -44,7 +44,7 @@ #include #include "chip.h" -#include "chip/imxrt_lpi2c.h" +#include "hardware/imxrt_lpi2c.h" /**************************************************************************** * Public Function Prototypes diff --git a/arch/arm/src/imxrt/imxrt_lpspi.c b/arch/arm/src/imxrt/imxrt_lpspi.c index 4b346381352..58001ec3b89 100644 --- a/arch/arm/src/imxrt/imxrt_lpspi.c +++ b/arch/arm/src/imxrt/imxrt_lpspi.c @@ -86,10 +86,10 @@ #include "imxrt_lpspi.h" #include "imxrt_gpio.h" -#include "chip/imxrt_pinmux.h" -#include "chip/imxrt_lpspi.h" -#include "chip/imxrt_ccm.h" -#include "chip/imxrt_periphclks.h" +#include "hardware/imxrt_pinmux.h" +#include "hardware/imxrt_lpspi.h" +#include "hardware/imxrt_ccm.h" +#include "hardware/imxrt_periphclks.h" #if defined(CONFIG_IMXRT_LPSPI1) || defined(CONFIG_IMXRT_LPSPI2) || \ defined(CONFIG_IMXRT_LPSPI3) || defined(CONFIG_IMXRT_LPSPI4) diff --git a/arch/arm/src/imxrt/imxrt_lpspi.h b/arch/arm/src/imxrt/imxrt_lpspi.h index 01368f90c86..e2266395820 100644 --- a/arch/arm/src/imxrt/imxrt_lpspi.h +++ b/arch/arm/src/imxrt/imxrt_lpspi.h @@ -47,7 +47,7 @@ #include #include "chip.h" -#include "chip/imxrt_lpspi.h" +#include "hardware/imxrt_lpspi.h" /************************************************************************************ * Public Functions diff --git a/arch/arm/src/imxrt/imxrt_lpsrtc.c b/arch/arm/src/imxrt/imxrt_lpsrtc.c index 219c3734ee4..32f67bd9735 100644 --- a/arch/arm/src/imxrt/imxrt_lpsrtc.c +++ b/arch/arm/src/imxrt/imxrt_lpsrtc.c @@ -54,7 +54,7 @@ #include "up_arch.h" -#include "chip/imxrt_snvs.h" +#include "hardware/imxrt_snvs.h" #include "imxrt_periphclks.h" #include "imxrt_hprtc.h" #include "imxrt_lpsrtc.h" diff --git a/arch/arm/src/imxrt/imxrt_mpuinit.c b/arch/arm/src/imxrt/imxrt_mpuinit.c index 85b3a59116c..ebfebadca69 100644 --- a/arch/arm/src/imxrt/imxrt_mpuinit.c +++ b/arch/arm/src/imxrt/imxrt_mpuinit.c @@ -46,7 +46,7 @@ #include "mpu.h" #include "barriers.h" -#include "chip/imxrt_memorymap.h" +#include "hardware/imxrt_memorymap.h" #include "imxrt_mpuinit.h" diff --git a/arch/arm/src/imxrt/imxrt_ocotp.h b/arch/arm/src/imxrt/imxrt_ocotp.h index 646926cc1c5..800083ae961 100644 --- a/arch/arm/src/imxrt/imxrt_ocotp.h +++ b/arch/arm/src/imxrt/imxrt_ocotp.h @@ -42,7 +42,7 @@ ****************************************************************************/ #include -#include "chip/imxrt_ocotp.h" +#include "hardware/imxrt_ocotp.h" #include #include diff --git a/arch/arm/src/imxrt/imxrt_periphclks.h b/arch/arm/src/imxrt/imxrt_periphclks.h index b259e85ac95..bde77d5bc14 100644 --- a/arch/arm/src/imxrt/imxrt_periphclks.h +++ b/arch/arm/src/imxrt/imxrt_periphclks.h @@ -42,7 +42,7 @@ #include #include -#include "chip/imxrt_ccm.h" +#include "hardware/imxrt_ccm.h" /******************************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/imxrt/imxrt_serial.c b/arch/arm/src/imxrt/imxrt_serial.c index 40204831593..bcb9857588a 100644 --- a/arch/arm/src/imxrt/imxrt_serial.c +++ b/arch/arm/src/imxrt/imxrt_serial.c @@ -65,9 +65,9 @@ #include "up_arch.h" #include "up_internal.h" -#include "chip/imxrt_lpuart.h" +#include "hardware/imxrt_lpuart.h" #include "imxrt_gpio.h" -#include "chip/imxrt_pinmux.h" +#include "hardware/imxrt_pinmux.h" #include "imxrt_config.h" #include "imxrt_lowputc.h" diff --git a/arch/arm/src/imxrt/imxrt_timerisr.c b/arch/arm/src/imxrt/imxrt_timerisr.c index 817b9e1b962..616ca519cba 100644 --- a/arch/arm/src/imxrt/imxrt_timerisr.c +++ b/arch/arm/src/imxrt/imxrt_timerisr.c @@ -54,7 +54,7 @@ #include "up_arch.h" #include "chip.h" -#include "chip/imxrt_ccm.h" +#include "hardware/imxrt_ccm.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/imxrt/imxrt_usdhc.c b/arch/arm/src/imxrt/imxrt_usdhc.c index 5de359050b3..4b9e2150afb 100644 --- a/arch/arm/src/imxrt/imxrt_usdhc.c +++ b/arch/arm/src/imxrt/imxrt_usdhc.c @@ -64,10 +64,10 @@ #include "imxrt_config.h" #include "imxrt_gpio.h" -#include "chip/imxrt_pinmux.h" -#include "chip/imxrt_ccm.h" -#include "chip/imxrt_periphclks.h" -#include "chip/imxrt_usdhc.h" +#include "hardware/imxrt_pinmux.h" +#include "hardware/imxrt_ccm.h" +#include "hardware/imxrt_periphclks.h" +#include "hardware/imxrt_usdhc.h" #ifdef CONFIG_IMXRT_USDHC diff --git a/arch/arm/src/imxrt/imxrt_usdhc.h b/arch/arm/src/imxrt/imxrt_usdhc.h index 983a66515b9..d2e6fd5d7f1 100644 --- a/arch/arm/src/imxrt/imxrt_usdhc.h +++ b/arch/arm/src/imxrt/imxrt_usdhc.h @@ -45,7 +45,7 @@ #include #include "chip.h" -#include "chip/imxrt_usdhc.h" +#include "hardware/imxrt_usdhc.h" /**************************************************************************** * Public Function Prototypes diff --git a/arch/arm/src/imxrt/imxrt_wdog.c b/arch/arm/src/imxrt/imxrt_wdog.c index 8f9f2410ed1..c491e7b1311 100644 --- a/arch/arm/src/imxrt/imxrt_wdog.c +++ b/arch/arm/src/imxrt/imxrt_wdog.c @@ -45,7 +45,7 @@ #include "up_arch.h" -#include "chip/imxrt_wdog.h" +#include "hardware/imxrt_wdog.h" #include "imxrt_config.h" #include /* Include last: has dependencies */ diff --git a/arch/arm/src/imxrt/imxrt_wdog.h b/arch/arm/src/imxrt/imxrt_wdog.h index 03ae7a82760..efed2de0edf 100644 --- a/arch/arm/src/imxrt/imxrt_wdog.h +++ b/arch/arm/src/imxrt/imxrt_wdog.h @@ -49,7 +49,7 @@ #include "up_internal.h" #include "chip.h" -#include "chip/imxrt_wdog.h" +#include "hardware/imxrt_wdog.h" /**************************************************************************** * Public Types diff --git a/arch/arm/src/imxrt/imxrt_xbar.h b/arch/arm/src/imxrt/imxrt_xbar.h index 6636cd9c16b..24c615f89a5 100644 --- a/arch/arm/src/imxrt/imxrt_xbar.h +++ b/arch/arm/src/imxrt/imxrt_xbar.h @@ -43,8 +43,8 @@ #include #include -#include "chip/imxrt_xbar.h" -#include "chip/imxrt_memorymap.h" +#include "hardware/imxrt_xbar.h" +#include "hardware/imxrt_memorymap.h" /************************************************************************************************************************************************** * Pre-processor Definitions @@ -114,7 +114,7 @@ #define IMXRT_SIDE(six) ((six) & IMXRT_XBARA_SIDE_MASK) >> IMXRT_XBARA_SIDE_SHIFTS /* Collect correct XBAR definitions from chip file */ -#include "chip/imxrt_xbar.h" +#include "hardware/imxrt_xbar.h" /************************************************************************************************************************************************** * Public Functions diff --git a/arch/arm/src/stm32l4/stm32l4_hsi48.c b/arch/arm/src/stm32l4/stm32l4_hsi48.c index 527076c1ae8..28fa3aa7c03 100644 --- a/arch/arm/src/stm32l4/stm32l4_hsi48.c +++ b/arch/arm/src/stm32l4/stm32l4_hsi48.c @@ -41,7 +41,7 @@ #include "up_arch.h" #include "chip.h" -#include "hardware/stm32l4_rcc.h" +#include "stm32l4_rcc.h" #include "hardware/stm32l4_crs.h" #include "stm32l4_hsi48.h"