Mirrors_Framework/PX4-Autopilot
1
0
Fork 0
mirror of https://github.com/PX4/PX4-Autopilot.git synced 2026-03-24 02:24:09 +08:00
Code Issues Actions 31 Packages Projects Releases Wiki Activity

drivers: icm42688p fix AFSR register

Browse Source
This commit is contained in:
alexklimaj
2023-10-22 15:49:17 -05:00
committed by Daniel Agar
parent c6287a8a89
commit db765e6cbd
3 changed files with 4 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/drivers/imu/invensense/icm42688p/ICM42688P.cpp
View File

@@ -356,7 +356,7 @@ void ICM42688P::ConfigureCLKIN()
{
for (auto &r0 : _register_bank0_cfg) {
if (r0.reg == Register::BANK_0::INTF_CONFIG1) {
r0.set_bits = INTF_CONFIG1_BIT::RTC_MODE;
r0.set_bits = r0.set_bits | INTF_CONFIG1_BIT::RTC_MODE;
}
}

2
src/drivers/imu/invensense/icm42688p/ICM42688P.hpp
View File

@@ -185,7 +185,7 @@ private:
{ Register::BANK_0::INT_CONFIG, INT_CONFIG_BIT::INT1_MODE | INT_CONFIG_BIT::INT1_DRIVE_CIRCUIT, INT_CONFIG_BIT::INT1_POLARITY },
{ Register::BANK_0::FIFO_CONFIG, FIFO_CONFIG_BIT::FIFO_MODE_STOP_ON_FULL, 0 },
{ Register::BANK_0::INTF_CONFIG0, INTF_CONFIG0_BIT::FIFO_COUNT_ENDIAN | INTF_CONFIG0_BIT::SENSOR_DATA_ENDIAN | INTF_CONFIG0_BIT::UI_SIFS_CFG_DISABLE_I2C, 0},
{ Register::BANK_0::INTF_CONFIG1, 0, 0}, // RTC_MODE[2] set at runtime
{ Register::BANK_0::INTF_CONFIG1, INTF_CONFIG1_BIT::AFSR_SET, INTF_CONFIG1_BIT::AFSR_CLEAR}, // RTC_MODE[2] set at runtime
{ Register::BANK_0::PWR_MGMT0, PWR_MGMT0_BIT::GYRO_MODE_LOW_NOISE | PWR_MGMT0_BIT::ACCEL_MODE_LOW_NOISE, 0 },
{ Register::BANK_0::GYRO_CONFIG0, GYRO_CONFIG0_BIT::GYRO_FS_SEL_2000_DPS | GYRO_CONFIG0_BIT::GYRO_ODR_8KHZ_SET, GYRO_CONFIG0_BIT::GYRO_ODR_8KHZ_CLEAR },
{ Register::BANK_0::ACCEL_CONFIG0, ACCEL_CONFIG0_BIT::ACCEL_FS_SEL_16G | ACCEL_CONFIG0_BIT::ACCEL_ODR_8KHZ_SET, ACCEL_CONFIG0_BIT::ACCEL_ODR_8KHZ_CLEAR },

2
src/drivers/imu/invensense/icm42688p/InvenSense_ICM42688P_registers.hpp
View File

@@ -170,6 +170,8 @@ enum INTF_CONFIG0_BIT : uint8_t {
// INTF_CONFIG1
enum INTF_CONFIG1_BIT : uint8_t {
AFSR_CLEAR = Bit7, // 10: adaptive full scale range on by default, 01: off
AFSR_SET = Bit6,
RTC_MODE = Bit2, // 0: No input RTC clock is required, 1: RTC clock input is required
CLKSEL = Bit0,
CLKSEL_CLEAR = Bit1,