From db765e6cbda03b2c5f062fabbcee65b60f7722e9 Mon Sep 17 00:00:00 2001 From: alexklimaj Date: Sun, 22 Oct 2023 15:49:17 -0500 Subject: [PATCH] drivers: icm42688p fix AFSR register --- src/drivers/imu/invensense/icm42688p/ICM42688P.cpp | 2 +- src/drivers/imu/invensense/icm42688p/ICM42688P.hpp | 2 +- .../imu/invensense/icm42688p/InvenSense_ICM42688P_registers.hpp | 2 ++ 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/drivers/imu/invensense/icm42688p/ICM42688P.cpp b/src/drivers/imu/invensense/icm42688p/ICM42688P.cpp index b123768e0b..8619d87c89 100644 --- a/src/drivers/imu/invensense/icm42688p/ICM42688P.cpp +++ b/src/drivers/imu/invensense/icm42688p/ICM42688P.cpp @@ -356,7 +356,7 @@ void ICM42688P::ConfigureCLKIN() { for (auto &r0 : _register_bank0_cfg) { if (r0.reg == Register::BANK_0::INTF_CONFIG1) { - r0.set_bits = INTF_CONFIG1_BIT::RTC_MODE; + r0.set_bits = r0.set_bits | INTF_CONFIG1_BIT::RTC_MODE; } } diff --git a/src/drivers/imu/invensense/icm42688p/ICM42688P.hpp b/src/drivers/imu/invensense/icm42688p/ICM42688P.hpp index 67f456cdc7..f8c938a5cd 100644 --- a/src/drivers/imu/invensense/icm42688p/ICM42688P.hpp +++ b/src/drivers/imu/invensense/icm42688p/ICM42688P.hpp @@ -185,7 +185,7 @@ private: { Register::BANK_0::INT_CONFIG, INT_CONFIG_BIT::INT1_MODE | INT_CONFIG_BIT::INT1_DRIVE_CIRCUIT, INT_CONFIG_BIT::INT1_POLARITY }, { Register::BANK_0::FIFO_CONFIG, FIFO_CONFIG_BIT::FIFO_MODE_STOP_ON_FULL, 0 }, { Register::BANK_0::INTF_CONFIG0, INTF_CONFIG0_BIT::FIFO_COUNT_ENDIAN | INTF_CONFIG0_BIT::SENSOR_DATA_ENDIAN | INTF_CONFIG0_BIT::UI_SIFS_CFG_DISABLE_I2C, 0}, - { Register::BANK_0::INTF_CONFIG1, 0, 0}, // RTC_MODE[2] set at runtime + { Register::BANK_0::INTF_CONFIG1, INTF_CONFIG1_BIT::AFSR_SET, INTF_CONFIG1_BIT::AFSR_CLEAR}, // RTC_MODE[2] set at runtime { Register::BANK_0::PWR_MGMT0, PWR_MGMT0_BIT::GYRO_MODE_LOW_NOISE | PWR_MGMT0_BIT::ACCEL_MODE_LOW_NOISE, 0 }, { Register::BANK_0::GYRO_CONFIG0, GYRO_CONFIG0_BIT::GYRO_FS_SEL_2000_DPS | GYRO_CONFIG0_BIT::GYRO_ODR_8KHZ_SET, GYRO_CONFIG0_BIT::GYRO_ODR_8KHZ_CLEAR }, { Register::BANK_0::ACCEL_CONFIG0, ACCEL_CONFIG0_BIT::ACCEL_FS_SEL_16G | ACCEL_CONFIG0_BIT::ACCEL_ODR_8KHZ_SET, ACCEL_CONFIG0_BIT::ACCEL_ODR_8KHZ_CLEAR }, diff --git a/src/drivers/imu/invensense/icm42688p/InvenSense_ICM42688P_registers.hpp b/src/drivers/imu/invensense/icm42688p/InvenSense_ICM42688P_registers.hpp index 79971a1bdd..c6e9d6ca29 100644 --- a/src/drivers/imu/invensense/icm42688p/InvenSense_ICM42688P_registers.hpp +++ b/src/drivers/imu/invensense/icm42688p/InvenSense_ICM42688P_registers.hpp @@ -170,6 +170,8 @@ enum INTF_CONFIG0_BIT : uint8_t { // INTF_CONFIG1 enum INTF_CONFIG1_BIT : uint8_t { + AFSR_CLEAR = Bit7, // 10: adaptive full scale range on by default, 01: off + AFSR_SET = Bit6, RTC_MODE = Bit2, // 0: No input RTC clock is required, 1: RTC clock input is required CLKSEL = Bit0, CLKSEL_CLEAR = Bit1,