Mirrors_Framework/threadx
1
0
Fork 0
mirror of https://github.com/eclipse-threadx/threadx.git synced 2026-09-22 13:34:16 +08:00
Code Issues Actions 2 Packages Projects Releases Wiki Activity

add 'config' directory to risc-v iar to support simulator

Browse Source
This commit is contained in:
Scott Larson
2022-11-02 08:32:02 -07:00
parent 3e8e85cdc1
commit ee892502ec
4 changed files with 539 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
ports/risc-v32/iar/example_build/config/debugger/csr.sfr
+327
View File
File diff suppressed because one or more lines are too long
ports/risc-v32/iar/example_build/config/debugger/ioriscv.ddf
+113
View File
@@ -0,0 +1,113 @@
;;-------------------------------------------------------------------------
;; Declarations of SFR registers and bits, interrupt/exception vectors,
;; interrupt control registers, memory map information, and additional
;; configurations for a generic (non-existent) RISC-V device.
;;
;; This declaration file can be used by all flavors of the IAR C-SPY
;; Debugger for RISC-V (simulator and emulators).
;;
;; Copyright 2019 IAR Systems AB.
;;-------------------------------------------------------------------------
;;-------------------------------------------------------------------------
;; SFR declaration file
;;
;; Syntax: File = Filename
;;
;; Filename Name of SFR declaration file
;;-------------------------------------------------------------------------
;; CSR
#include weak "csr.sfr"
[SfrInclude]
File = ioriscv.sfr
;;-------------------------------------------------------------------------
;; Memory information
;;
;; Syntax: Memory[NN] = Name Zone StartAdr EndAdr AccType
;;
;; NN Optional counter
;; Name Name of address space (legal characters: A-Z, a-z, 0-9, _)
;; Zone Must be Memory
;; StartAdr Start address of memory address space
;; EndAdr End address of memory address space
;; AccType Type of access, read-only (R) or read-write (RW)
;; (W - noncached) for SFR areas and areas that are shared,
;; implemented as different core-specific physical memories
;; in a multicore device.
;;
;; Used to define named memory address spaces within the 'Memory' zone.
;;
;;-------------------------------------------------------------------------
;; Name Zone StartAdr EndAdr AccType
;;-------------------------------------------------------------------------
[Memory]
Memory = Peripherals Memory 0x02000000 0x1FFFFFFF W
Memory = Flash Memory 0x20000000 0x3FFFFFFF R
Memory = RAM Memory 0x80000000 0x8003FFFF RW
TrustedRanges = true
;;-------------------------------------------------------------------------
;; Device file
;;
;; Syntax: File = Filename
;;
;; Filename Name of device file
;;-------------------------------------------------------------------------
[DeviceFile]
File = <Undefined>
;;-------------------------------------------------------------------------
;; Device information
;;
;; Syntax: Item = Value
;;
;; Item Name of item
;; Value Value of item
;;-------------------------------------------------------------------------
[DeviceInfo]
DataFlash = YES
FlashSize = 0032
FlashType = CS Fixed2
StartAddress = 0x02000000
EndAddress = 0x80003FFF
BusSize = 00
IDCodeBitLength = 128
CodeFlashIDCode = NO
DataFlashIDCode = NO
CoreNumbers = 1
;;-------------------------------------------------------------------------
;; Interrupt declarations
;;
;; Syntax: InterruptNN = Id Vector Type
;;
;; NN Counter
;; Id Unique Interrupt 'name'
;; Vector Exception Code
;; Controller SiFive1
;; Core Core Number
;; Enable Enable bit
;; Pending Pending bit
;; Priority Priority level
;; UserLvl (M)achine/(S)upervisor/(U)ser
;; Trap '0' exception
;; '1' interrupt
;; Maskable '0' Non Maskable
;; '1' Maskable
;;-------------------------------------------------------------------------
[InterruptList]
Interrupt7 = TIMER 0x07 SiFive1 0x00 mie.mtie mip.mtip 0x00 M 0x01 0x00
;;-------------------------------------------------------------------------
;; End of file
;;-------------------------------------------------------------------------
ports/risc-v32/iar/example_build/config/debugger/ioriscv.sfr
+35
View File
@@ -0,0 +1,35 @@
;;-------------------------------------------------------------------------
;; Declarations of SFR registers and SFR groups
;;
;; This file is included by: ioriscv.ddf
;;
;; Copyright 2019 IAR Systems AB.
;;
;;-------------------------------------------------------------------------
;;-------------------------------------------------------------------------
;; NOTE:
;; This is an example file for a RISC-V derivative
;;-------------------------------------------------------------------------
;;-------------------------------------------------------------------------
;; SFR declarations
;;
;; Syntax: sfr = "sfr name", "zone name", address, size, base=viewbase, bitRange=bit[-bit](optional), readOnly/writeOnly(optional)
;;-------------------------------------------------------------------------
[Sfr]
;sfr = "FLMDPCMD", "Memory", FFA00004, 4, base=16 , writeOnly
;sfr = "FLMDPS", "Memory", FFA00008, 4, base=16 , readOnly
;;-------------------------------------------------------------------------
;; SFR group declarations
;;
;; Syntax: group = "group name", "sfr name", "sfr name", ...
;;-------------------------------------------------------------------------
[SfrGroupInfo]
;group = "Interrupt", "ICCSIH2IC_1", "ICCSIH3IC_1", "ICTAUD0I4", "ICTAUD0I6", "ICTAUD0I8", "ICCSIH3IR_1", "ICCSIH3IRE_1", "ICCSIH3IJC_1"
;group = "Interrupt", "ICCSIH1IC_1", "ICCSIH1IR_1", "ICADCA0I0", "ICADCA0I1", "ICADCA0I2", "ICDCUTDI", "ICRCANGERR", "ICRCANGRECC"
;;-------------------------------------------------------------------------
;; End of file
;;-------------------------------------------------------------------------
ports/risc-v32/iar/example_build/config/debugger/timer.mac
+64
View File
@@ -0,0 +1,64 @@
/*
* Copyright (C) 1996-2019 IAR Systems AB.
*
* Excerpt from IAR Embedded Workbench tutorial
*
* Macro package for the C-SPY debugger to simulate Fibonacci data input,
* including setting an immediate breakpoint and defining a simulated
* interrupt.
*
* See the file riscv/doc/licenses/IARSourceLicense.txt for detailed
* license information.
*
*/
__var _counter;
__var _interruptID;
__var _breakID;
execUserSetup()
{
__message "execUserSetup() called\n";
/* Call the simulation setup. */
SimulationSetup ();
}
execUserExit()
{
__message "execUserExit() called\n";
/* Call the Simulation shutdown. */
SimulationShutdown();
}
SimulationSetup()
{
/* Automatically setup the TIMER interrupt for the simulation */
_interruptID = __orderInterrupt("TIMER", 1000, 1000, 0, 1, 0, 100);
if( -1 == _interruptID )
{
__message "ERROR: failed to set up the interrupt";
}
/* Insert a breakpoint in the _tx_timer_interrupt entry point */
_breakID = __setCodeBreak( "_tx_timer_interrupt", 0, "1", "TRUE", "InterruptCSPYlogger()");
if( !_breakID )
{
__message "ERROR: could not set immediate breakpoint.\n" ;
}
}
InterruptCSPYlogger()
{
_counter++;
__message "Entered TIMER interrupt: ", _counter, "\n";
}
SimulationShutdown()
{
__cancelInterrupt(_interruptID);
__clearBreak(_breakID);
}