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README.md
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@@ -1,117 +1,189 @@
![cortex_m0](https://github.com/azure-rtos/threadx/workflows/cortex_m0/badge.svg)
![cortex_m3](https://github.com/azure-rtos/threadx/workflows/cortex_m3/badge.svg)
![cortex_m4](https://github.com/azure-rtos/threadx/workflows/cortex_m4/badge.svg)
![cortex_m7](https://github.com/azure-rtos/threadx/workflows/cortex_m7/badge.svg)
# Azure RTOS ThreadX
This advanced real-time operating system (RTOS) is designed specifically for deeply embedded applications. Among the multiple benefits it provides are advanced scheduling facilities, message passing, interrupt management, and messaging services. Azure RTOS ThreadX has many advanced features, including picokernel architecture, preemption threshold, event chaining, and a rich set of system services.
## Documentation
Here are the key features and modules of ThreadX:
Documentation for this library can be found here: http://docs.microsoft.com/azure/rtos/threadx
![ThreadX Key Features](./docs/threadx-features.png)
## Getting Started
Azure RTOS has been integrated to the semiconductor's SDKs and development environment. You can develop using the tools of choice from [STMicroelectronics](https://www.st.com/content/st_com/en/campaigns/x-cube-azrtos-azure-rtos-stm32.html), [NXP](https://www.nxp.com/design/software/embedded-software/azure-rtos-for-nxp-microcontrollers:AZURE-RTOS), [Renesas](https://github.com/renesas/azure-rtos) and [Microchip](https://mu.microchip.com/get-started-simplifying-your-iot-design-with-azure-rtos).
We also provide [getting started guide](https://github.com/azure-rtos/getting-started) and [samples](https://github.com/azure-rtos/samples) using hero development boards from semiconductors you can build and test with.
See [Overview of Azure RTOS ThreadX](https://learn.microsoft.com/en-us/azure/rtos/threadx/overview-threadx) for the high-level overview, and all documentation and APIs can be found in: [Azure RTOS ThreadX documentation](https://learn.microsoft.com/en-us/azure/rtos/threadx/).
Also there is dedicated [learning path of Azure RTOS ThreadX](https://learn.microsoft.com/training/paths/azure-rtos-threadx/) for learning systematically.
# Understanding inter-component dependencies
## Repository Structure and Usage
### Directory layout
The main components of Azure RTOS are each provided in their own repository, but there are dependencies between them--shown in the following graph--that are important to understand when setting up your builds.
.
├── cmake # CMakelist files for building the project
├── common # Core ThreadX files
├── common_modules # Core ThreadX module files
├── common_smp # Core ThreadX SMP files
├── docs # Documentation supplements
├── ports # Architecture and compiler specific files. See below for directory breakdown
│ ├── cortex_m7
│ │ ├── iar # Example IAR compiler sample project
│ │ │ ├── example build # IAR workspace and sample project files
│ │ │ ├── inc # tx_port.h for this architecture
│ │ │ └── src # Source files for this architecture
│ │ ├── ac6 # Example ac6/Keil sample project
│ │ ├── gnu # Example gnu sample project
│ │ └── ...
│ └── ...
├── ports_modules # Architecture and compiler specific files for threadX modules
├── ports_smp # Architecture and compiler specific files for threadX SMP
├── samples # demo_threadx.c
└── utility # Test cases and utilities
![dependency graph](docs/deps.png)
# Building and using the library
## Prerequisites
Install the following tools:
* [CMake](https://cmake.org/download/) version 3.0 or later
* [GCC compilers for arm-none-eabi](https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-rm/downloads)
* [Ninja](https://ninja-build.org/)
## Cloning the repo
```bash
$ git clone https://github.com/azure-rtos/threadx.git
```
## Building as a static library
Each component of Azure RTOS comes with a composable CMake-based build system that supports many different MCUs and host systems. Integrating any of these components into your device app code is as simple as adding a git submodule and then including it in your build using the CMake command `add_subdirectory()`.
While the typical usage pattern is to include threadx into your device code source tree to be built & linked with your code, you can compile this project as a standalone static library to confirm your build is set up correctly.
```bash
$ cmake -Bbuild -DCMAKE_TOOLCHAIN_FILE=cmake/cortex_m4.cmake -GNinja .
$ cmake --build ./build
```
NOTE: You will have to take the dependency graph above into account when building anything other than threadx itself.
# Repository Structure and Usage
## Branches & Releases
The master branch has the most recent code with all new features and bug fixes. It does not represent the latest General Availability (GA) release of the library.
The master branch has the most recent code with all new features and bug fixes. It does not represent the latest General Availability (GA) release of the library. Each official release (preview or GA) will be tagged to mark the commit and push it into the Github releases tab, e.g. `v6.2-rel`.
## Releases
Each official release (preview or GA) will be tagged to mark the commit and push it into the Github releases tab, e.g. `v6.0-rel`.
## Directory layout
## Supported Architecture Ports
### ThreadX
```
- cmake
- common
- inc
- src
- ports
- cortex_m0/gnu
- inc
- src
- cortex_m3/gnu
- inc
- src
- cortex_m4/gnu
- inc
- src
- cortex_m7/gnu
- inc
- src
- samples
arc_em cortex_a12 cortex_m0 cortex_r4
arc_hs cortex_a15 cortex_m23 cortex_r5
arm11 cortex_a17 cortex_m3 cortex_r7
arm9 cortex_a34 cortex_m33
c667x cortex_a35 cortex_m4
linux cortex_a5 cortex_m55
risc-v32 cortex_a53 cortex_m7
rxv1 cortex_a55 cortex_m85
rxv2 cortex_a57
rxv3 cortex_a5x
win32 cortex_a65
xtensa cortex_a65ae
cortex_a7
cortex_a72
cortex_a73
cortex_a75
cortex_a76
cortex_a76ae
cortex_a77
cortex_a8
cortex_a9
```
# Security
### ThreadX Modules
[Azure RTOS ThreadX Modules](https://learn.microsoft.com/azure/rtos/threadx-modules/chapter1) component provides an infrastructure for applications to dynamically load modules that are built separately from the resident portion of the application.
```
cortex_a35
cortex_a35_smp
cortex_a7
cortex_m0+
cortex_m23
cortex_m3
cortex_m33
cortex_m4
cortex_m7
cortex_r4
rxv2
```
Azure RTOS provides OEMs with components to secure communication and to create code and data isolation using underlying MCU/MPU hardware protection mechanisms. It is ultimately the responsibility of the device builder to ensure the device fully meets the evolving security requirements associated with its specific use case.
### ThreadX SMP
[Azure RTOS ThreadX SMP](https://learn.microsoft.com/azure/rtos/threadx/threadx-smp/chapter1) is a high-performance real-time SMP kernel designed specifically for embedded applications.
```
arc_hs_smp
cortex_a34_smp
cortex_a35_smp
cortex_a53_smp
cortex_a55_smp
cortex_a57_smp
cortex_a5x_smp
cortex_a5_smp
cortex_a65ae_smp
cortex_a65_smp
cortex_a72_smp
cortex_a73_smp
cortex_a75_smp
cortex_a76ae_smp
cortex_a76_smp
cortex_a77_smp
cortex_a78_smp
cortex_a7_smp
cortex_a9_smp
linux
```
# Adaptation layer for ThreadX
## Adaptation layer for ThreadX
Azure RTOS ThreadX is an advanced real-time operating system (RTOS) designed specifically for deeply embedded applications. To help ease application migration to Azure RTOS, ThreadX provides [adaption layers](https://github.com/azure-rtos/threadx/tree/master/utility/rtos_compatibility_layers) for various legacy RTOS APIs (FreeRTOS, POSIX, OSEK, etc.).
# Licensing
## Component dependencies
The main components of Azure RTOS are each provided in their own repository, but there are dependencies between them, as shown in the following graph. This is important to understand when setting up your builds.
![dependency graph](docs/deps.png)
> You will have to take the dependency graph above into account when building anything other than ThreadX itself.
### Building and using the library
Instruction for building the ThreadX as static library using Arm GNU Toolchain and CMake. If you are using toolchain and IDE from semiconductor, you might follow its own instructions to use Azure RTOS components as explained in the [Getting Started](#getting-started) section.
1. Install the following tools:
* [CMake](https://cmake.org/download/) version 3.0 or later
* [Arm GNU Toolchain for arm-none-eabi](https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads)
* [Ninja](https://ninja-build.org/)
1. Cloning the repo
```bash
$ git clone https://github.com/azure-rtos/threadx.git
```
1. Define the features and addons you need in `tx_user.h` and build together with the component source code. You can refer to [`tx_user_sample.h`](https://github.com/azure-rtos/threadx/blob/master/common/inc/tx_user_sample.h) as an example.
1. Building as a static library
Each component of Azure RTOS comes with a composable CMake-based build system that supports many different MCUs and host systems. Integrating any of these components into your device app code is as simple as adding a git submodule and then including it in your build using the CMake `add_subdirectory()`.
While the typical usage pattern is to include ThreadX into your device code source tree to be built & linked with your code, you can compile this project as a standalone static library to confirm your build is set up correctly.
An example of building the library for Cortex-M4:
```bash
$ cmake -Bbuild -GNinja -DCMAKE_TOOLCHAIN_FILE=cmake/cortex_m4.cmake .
$ cmake --build ./build
```
## Professional support
[Professional support plans](https://azure.microsoft.com/support/options/) are available from Microsoft. For community support and others, see the [Resources](#resources) section below.
## Licensing
License terms for using Azure RTOS are defined in the LICENSE.txt file of this repo. Please refer to this file for all definitive licensing information. No additional license fees are required for deploying Azure RTOS on hardware defined in the LICENSED-HARDWARE.txt file. If you are using hardware not defined in the LICENSED-HARDWARE.txt file or have licensing questions in general, please contact Microsoft directly at https://aka.ms/azrtos-license.
# Contribution, feedback, issues, and professional support
## Resources
If you encounter any bugs, have suggestions for new features, or if you would like to become an active contributor to this project, please follow the instructions provided in the contribution guideline for the corresponding repo.
The following are references to additional Azure RTOS resources:
For basic support, click Issues in the command bar or post a question to [Stack Overflow](http://stackoverflow.com/questions/tagged/azure-rtos+threadx) using the `threadx` and `azure-rtos` tags.
- **Product introduction and white papers**: https://azure.com/rtos
- **General technical questions**: https://aka.ms/QnA/azure-rtos
- **Product issues and bugs, or feature requests**: https://github.com/azure-rtos/threadx/issues
- **Licensing and sales questions**: https://aka.ms/azrtos-license
- **Product roadmap and support policy**: https://aka.ms/azrtos/lts
- **Blogs and videos**: http://msiotblog.com and https://aka.ms/iotshow
- **Azure RTOS TraceX Installer**: https://aka.ms/azrtos-tracex-installer
Professional support plans (https://azure.microsoft.com/en-us/support/options/) are available from Microsoft.
You can also check [previous questions](https://stackoverflow.com/questions/tagged/azure-rtos+threadx) or ask new ones on StackOverflow using the `azure-rtos` and `threadx` tags.
# Additional Resources
## Security
The following are references to additional Azure RTOS and Azure IoT in general:
| Content | Link |
|---|---|
| TraceX Installer | https://aka.ms/azrtos-tracex-installer |
| Azure RTOS Documentation and Guides: | https://docs.microsoft.com/azure/rtos |
| Azure RTOS Website: | https://azure.microsoft.com/services/rtos/ |
| Azure RTOS Sales Questions: | https://aka.ms/azrtos-license |
| Azure RTOS Product Support Policy | https://aka.ms/azrtos/lts |
| Azure RTOS Functional Safety Artifacts | https://aka.ms/azrtos/tuv |
| For technical questions check out Microsoft Q/A for Azure IoT | https://aka.ms/QnA/azure-rtos |
| Internet of Things Show for latest announcements and online training | https://aka.ms/iotshow |
| IoT Tech Community | https://aka.ms/community/azure-rtos |
Azure RTOS provides OEMs with components to secure communication and to create code and data isolation using underlying MCU/MPU hardware protection mechanisms. It is ultimately the responsibility of the device builder to ensure the device fully meets the evolving security requirements associated with its specific use case.
## Contribution
Please follow the instructions provided in the [CONTRIBUTING.md](./CONTRIBUTING.md) for the corresponding repository.
common/inc/tx_api.h
+83 -5
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@@ -26,7 +26,7 @@
/* APPLICATION INTERFACE DEFINITION RELEASE */
/* */
/* tx_api.h PORTABLE C */
/* 6.1.12 */
/* 6.2.0 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -89,6 +89,11 @@
/* 07-29-2022 Scott Larson Modified comment(s), */
/* update patch number, */
/* resulting in version 6.1.12 */
/* 10-31-2022 Scott Larson Modified comment(s), */
/* add extension macros, */
/* update EPK typedef, */
/* update version numbers, */
/* resulting in version 6.2.0 */
/* */
/**************************************************************************/
@@ -115,6 +120,9 @@ extern "C" {
#include "tx_port.h"
#if (defined(TX_EXECUTION_PROFILE_ENABLE) && !defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY))
#include "tx_execution_profile.h"
#endif
/* Define basic constants for the ThreadX kernel. */
@@ -124,8 +132,8 @@ extern "C" {
#define AZURE_RTOS_THREADX
#define THREADX_MAJOR_VERSION 6
#define THREADX_MINOR_VERSION 1
#define THREADX_PATCH_VERSION 12
#define THREADX_MINOR_VERSION 2
#define THREADX_PATCH_VERSION 0
/* Define the following symbol for backward compatibility */
#define EL_PRODUCT_THREADX
@@ -223,6 +231,76 @@ extern "C" {
#define TX_FEATURE_NOT_ENABLED ((UINT) 0xFF)
#ifdef TX_64_BIT
#ifndef TX_THREAD_EXTENSION_PTR_SET
#define TX_THREAD_EXTENSION_PTR_SET(a, b) { \
TX_THREAD *thread_ptr; \
thread_ptr = (TX_THREAD *) (a); \
(thread_ptr -> tx_thread_extension_ptr) = (VOID *)(b); \
}
#endif /* TX_THREAD_EXTENSION_PTR_SET */
#ifndef TX_THREAD_EXTENSION_PTR_GET
#define TX_THREAD_EXTENSION_PTR_GET(a, b, c) { \
TX_PARAMETER_NOT_USED(c); \
TX_THREAD *thread_ptr; \
thread_ptr = tx_thread_identify(); \
while(1)\
{ \
if (thread_ptr -> tx_thread_extension_ptr) \
{ \
(a) = (b *)(thread_ptr -> tx_thread_extension_ptr); \
break; \
} \
tx_thread_sleep(1); \
} \
}
#endif /* TX_THREAD_EXTENSION_PTR_GET */
#ifndef TX_TIMER_EXTENSION_PTR_SET
#define TX_TIMER_EXTENSION_PTR_SET(a, b) { \
TX_TIMER *timer_ptr; \
timer_ptr = (TX_TIMER *) (a); \
(timer_ptr -> tx_timer_internal.tx_timer_internal_extension_ptr) = (VOID *)(b); \
}
#endif /* TX_TIMER_EXTENSION_PTR_SET */
#ifndef TX_TIMER_EXTENSION_PTR_GET
#define TX_TIMER_EXTENSION_PTR_GET(a, b, c) { \
TX_PARAMETER_NOT_USED(c); \
if (!_tx_timer_expired_timer_ptr -> tx_timer_internal_extension_ptr) \
return; \
(a) = (b *)(_tx_timer_expired_timer_ptr -> tx_timer_internal_extension_ptr); \
}
#endif /* TX_TIMER_EXTENSION_PTR_GET */
#else /* not 64 bit */
#ifndef TX_THREAD_EXTENSION_PTR_SET
#define TX_THREAD_EXTENSION_PTR_SET(a, b)
#endif /* TX_THREAD_EXTENSION_PTR_SET */
#ifndef TX_THREAD_EXTENSION_PTR_GET
#define TX_THREAD_EXTENSION_PTR_GET(a, b, c) { \
(a) = (b *)(c); \
}
#endif /* TX_THREAD_EXTENSION_PTR_GET */
#ifndef TX_TIMER_EXTENSION_PTR_SET
#define TX_TIMER_EXTENSION_PTR_SET(a, b)
#endif /* TX_TIMER_EXTENSION_PTR_SET */
#ifndef TX_TIMER_EXTENSION_PTR_GET
#define TX_TIMER_EXTENSION_PTR_GET(a, b, c) { \
(a) = (b *)(c); \
}
#endif /* TX_TIMER_EXTENSION_PTR_GET */
#endif /* TX_64_BIT */
/* Define the common timer tick reference for use by other middleware components. The default
value is 10ms, but may be replaced by a port specific version in tx_port.h or by the user
as a compilation option. */
@@ -529,8 +607,8 @@ typedef struct TX_THREAD_STRUCT
For Azure RTOS 6, user shall use TX_EXECUTION_PROFILE_ENABLE instead of TX_ENABLE_EXECUTION_CHANGE_NOTIFY,
and SHALL NOT add variables to TX_THREAD_EXTENSION_3. */
#if (defined(TX_EXECUTION_PROFILE_ENABLE) && !defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY))
unsigned long long tx_thread_execution_time_total;
unsigned long long tx_thread_execution_time_last_start;
EXECUTION_TIME tx_thread_execution_time_total;
EXECUTION_TIME_SOURCE_TYPE tx_thread_execution_time_last_start;
#endif
/* Define suspension sequence number. This is used to ensure suspension is still valid when
common/src/tx_event_flags_get.c
+8 -8
View File
@@ -36,7 +36,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_event_flags_get PORTABLE C */
/* 6.1.11 */
/* 6.2.0 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -79,6 +79,9 @@
/* 04-25-2022 Scott Larson Modified comment(s), */
/* handle 0 flags case, */
/* resulting in version 6.1.11 */
/* 10-31-2022 Scott Larson Modified comment(s), always */
/* return actual flags, */
/* resulting in version 6.2.0 */
/* */
/**************************************************************************/
UINT _tx_event_flags_get(TX_EVENT_FLAGS_GROUP *group_ptr, ULONG requested_flags,
@@ -125,6 +128,9 @@ UINT interrupted_set_request;
/* Pickup current flags. */
current_flags = group_ptr -> tx_event_flags_group_current;
/* Return the actual event flags and apply delayed clearing. */
*actual_flags_ptr = current_flags & ~group_ptr -> tx_event_flags_group_delayed_clear;
/* Apply the event flag option mask. */
and_request = (get_option & TX_AND);
@@ -158,9 +164,6 @@ UINT interrupted_set_request;
if (flags_satisfied != ((ULONG) 0))
{
/* Return the actual event flags that satisfied the request. */
*actual_flags_ptr = current_flags;
/* Pickup the clear bit. */
clear_request = (get_option & TX_EVENT_FLAGS_CLEAR_MASK);
@@ -221,9 +224,6 @@ UINT interrupted_set_request;
/* Yes, this request can be handled immediately. */
/* Return the actual event flags that satisfied the request. */
*actual_flags_ptr = current_flags;
/* Pickup the clear bit. */
clear_request = (get_option & TX_EVENT_FLAGS_CLEAR_MASK);
@@ -274,7 +274,7 @@ UINT interrupted_set_request;
#endif
else
{
/* flags_satisfied is 0. */
/* Determine if the request specifies suspension. */
if (wait_option != TX_NO_WAIT)
{
common_smp/inc/tx_api.h
+77 -3
View File
@@ -26,7 +26,7 @@
/* APPLICATION INTERFACE DEFINITION RELEASE */
/* */
/* tx_api.h PORTABLE SMP */
/* 6.1.12 */
/* 6.2.0 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -78,6 +78,10 @@
/* 07-29-2022 Scott Larson Modified comment(s), */
/* update patch number, */
/* resulting in version 6.1.12 */
/* 10-31-2022 Scott Larson Modified comment(s), */
/* add extension macros, */
/* update version numbers, */
/* resulting in version 6.2.0 */
/* */
/**************************************************************************/
@@ -129,8 +133,8 @@ extern "C" {
#define AZURE_RTOS_THREADX
#define THREADX_MAJOR_VERSION 6
#define THREADX_MINOR_VERSION 1
#define THREADX_PATCH_VERSION 12
#define THREADX_MINOR_VERSION 2
#define THREADX_PATCH_VERSION 0
/* Define the following symbol for backward compatibility */
#define EL_PRODUCT_THREADX
@@ -228,6 +232,76 @@ extern "C" {
#define TX_FEATURE_NOT_ENABLED ((UINT) 0xFF)
#ifdef TX_64_BIT
#ifndef TX_THREAD_EXTENSION_PTR_SET
#define TX_THREAD_EXTENSION_PTR_SET(a, b) { \
TX_THREAD *thread_ptr; \
thread_ptr = (TX_THREAD *) (a); \
(thread_ptr -> tx_thread_extension_ptr) = (VOID *)(b); \
}
#endif /* TX_THREAD_EXTENSION_PTR_SET */
#ifndef TX_THREAD_EXTENSION_PTR_GET
#define TX_THREAD_EXTENSION_PTR_GET(a, b, c) { \
TX_PARAMETER_NOT_USED(c); \
TX_THREAD *thread_ptr; \
thread_ptr = tx_thread_identify(); \
while(1)\
{ \
if (thread_ptr -> tx_thread_extension_ptr) \
{ \
(a) = (b *)(thread_ptr -> tx_thread_extension_ptr); \
break; \
} \
tx_thread_sleep(1); \
} \
}
#endif /* TX_THREAD_EXTENSION_PTR_GET */
#ifndef TX_TIMER_EXTENSION_PTR_SET
#define TX_TIMER_EXTENSION_PTR_SET(a, b) { \
TX_TIMER *timer_ptr; \
timer_ptr = (TX_TIMER *) (a); \
(timer_ptr -> tx_timer_internal.tx_timer_internal_extension_ptr) = (VOID *)(b); \
}
#endif /* TX_TIMER_EXTENSION_PTR_SET */
#ifndef TX_TIMER_EXTENSION_PTR_GET
#define TX_TIMER_EXTENSION_PTR_GET(a, b, c) { \
TX_PARAMETER_NOT_USED(c); \
if (!_tx_timer_expired_timer_ptr -> tx_timer_internal_extension_ptr) \
return; \
(a) = (b *)(_tx_timer_expired_timer_ptr -> tx_timer_internal_extension_ptr); \
}
#endif /* TX_TIMER_EXTENSION_PTR_GET */
#else /* not 64 bit */
#ifndef TX_THREAD_EXTENSION_PTR_SET
#define TX_THREAD_EXTENSION_PTR_SET(a, b)
#endif /* TX_THREAD_EXTENSION_PTR_SET */
#ifndef TX_THREAD_EXTENSION_PTR_GET
#define TX_THREAD_EXTENSION_PTR_GET(a, b, c) { \
(a) = (b *)(c); \
}
#endif /* TX_THREAD_EXTENSION_PTR_GET */
#ifndef TX_TIMER_EXTENSION_PTR_SET
#define TX_TIMER_EXTENSION_PTR_SET(a, b)
#endif /* TX_TIMER_EXTENSION_PTR_SET */
#ifndef TX_TIMER_EXTENSION_PTR_GET
#define TX_TIMER_EXTENSION_PTR_GET(a, b, c) { \
(a) = (b *)(c); \
}
#endif /* TX_TIMER_EXTENSION_PTR_GET */
#endif /* TX_64_BIT */
/* Define the common timer tick reference for use by other middleware components. The default
value is 10ms, but may be replaced by a port specific version in tx_port.h or by the user
as a compilation option. */
common_smp/src/tx_event_flags_get.c
+8 -8
View File
@@ -36,7 +36,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_event_flags_get PORTABLE C */
/* 6.1.11 */
/* 6.2.0 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -79,6 +79,9 @@
/* 04-25-2022 Scott Larson Modified comment(s), */
/* handle 0 flags case, */
/* resulting in version 6.1.11 */
/* 10-31-2022 Scott Larson Modified comment(s), always */
/* return actual flags, */
/* resulting in version 6.2.0 */
/* */
/**************************************************************************/
UINT _tx_event_flags_get(TX_EVENT_FLAGS_GROUP *group_ptr, ULONG requested_flags,
@@ -125,6 +128,9 @@ UINT interrupted_set_request;
/* Pickup current flags. */
current_flags = group_ptr -> tx_event_flags_group_current;
/* Return the actual event flags and apply delayed clearing. */
*actual_flags_ptr = current_flags & ~group_ptr -> tx_event_flags_group_delayed_clear;
/* Apply the event flag option mask. */
and_request = (get_option & TX_AND);
@@ -158,9 +164,6 @@ UINT interrupted_set_request;
if (flags_satisfied != ((ULONG) 0))
{
/* Return the actual event flags that satisfied the request. */
*actual_flags_ptr = current_flags;
/* Pickup the clear bit. */
clear_request = (get_option & TX_EVENT_FLAGS_CLEAR_MASK);
@@ -221,9 +224,6 @@ UINT interrupted_set_request;
/* Yes, this request can be handled immediately. */
/* Return the actual event flags that satisfied the request. */
*actual_flags_ptr = current_flags;
/* Pickup the clear bit. */
clear_request = (get_option & TX_EVENT_FLAGS_CLEAR_MASK);
@@ -274,7 +274,7 @@ UINT interrupted_set_request;
#endif
else
{
/* flags_satisfied is 0. */
/* Determine if the request specifies suspension. */
if (wait_option != TX_NO_WAIT)
{
common_smp/src/tx_thread_create.c
+5 -4
View File
@@ -37,7 +37,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_create PORTABLE SMP */
/* 6.1.8 */
/* 6.2.0 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -85,6 +85,10 @@
/* resulting in version 6.1.3 */
/* 08-02-2021 Scott Larson Removed unneeded cast, */
/* resulting in version 6.1.8 */
/* 10-31-2022 Scott Larson Removed ifdef block to always */
/* restore interrupts at end */
/* of if block, */
/* resulting in version 6.2.0 */
/* */
/**************************************************************************/
UINT _tx_thread_create(TX_THREAD *thread_ptr, CHAR *name_ptr,
@@ -344,11 +348,8 @@ ALIGN_TYPE updated_stack_start;
#endif
}
#ifndef TX_NOT_INTERRUPTABLE
/* Restore interrupts. */
TX_RESTORE
#endif
}
else
{
docs/threadx-features.png
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ports/cortex_m23/iar/src/tx_misra.s
+3 -2
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@@ -111,9 +111,9 @@
PUBLIC _tx_misra_semaphore_put_notify_not_used
PUBLIC _tx_misra_thread_entry_exit_notify_not_used
PUBLIC _tx_misra_thread_not_used
PUBLIC _tx_version_id
#ifdef TX_MISRA_ENABLE
PUBLIC _tx_version_id
SECTION `.data`:DATA:REORDER:NOROOT(2)
DATA
@@ -130,6 +130,7 @@ _tx_version_id:
DC8 20H, 43H, 6FH, 6DH, 70H, 6CH, 69H, 61H
DC8 6EH, 74H, 20H, 2AH, 0
DC8 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
#endif //TX_MISRA_ENABLE
/**************************************************************************/
/**************************************************************************/
ports/cortex_m3/iar/src/tx_misra.s
+3 -2
View File
@@ -111,9 +111,9 @@
PUBLIC _tx_misra_semaphore_put_notify_not_used
PUBLIC _tx_misra_thread_entry_exit_notify_not_used
PUBLIC _tx_misra_thread_not_used
PUBLIC _tx_version_id
#ifdef TX_MISRA_ENABLE
PUBLIC _tx_version_id
SECTION `.data`:DATA:REORDER:NOROOT(2)
DATA
@@ -130,6 +130,7 @@ _tx_version_id:
DC8 20H, 43H, 6FH, 6DH, 70H, 6CH, 69H, 61H
DC8 6EH, 74H, 20H, 2AH, 0
DC8 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
#endif //TX_MISRA_ENABLE
/**************************************************************************/
/**************************************************************************/
ports/cortex_m33/iar/src/tx_misra.s
+3 -2
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@@ -111,9 +111,9 @@
PUBLIC _tx_misra_semaphore_put_notify_not_used
PUBLIC _tx_misra_thread_entry_exit_notify_not_used
PUBLIC _tx_misra_thread_not_used
PUBLIC _tx_version_id
#ifdef TX_MISRA_ENABLE
PUBLIC _tx_version_id
SECTION `.data`:DATA:REORDER:NOROOT(2)
DATA
@@ -130,6 +130,7 @@ _tx_version_id:
DC8 20H, 43H, 6FH, 6DH, 70H, 6CH, 69H, 61H
DC8 6EH, 74H, 20H, 2AH, 0
DC8 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
#endif //TX_MISRA_ENABLE
/**************************************************************************/
/**************************************************************************/
ports/cortex_m4/iar/src/tx_misra.s
+3 -2
View File
@@ -111,9 +111,9 @@
PUBLIC _tx_misra_semaphore_put_notify_not_used
PUBLIC _tx_misra_thread_entry_exit_notify_not_used
PUBLIC _tx_misra_thread_not_used
PUBLIC _tx_version_id
#ifdef TX_MISRA_ENABLE
PUBLIC _tx_version_id
SECTION `.data`:DATA:REORDER:NOROOT(2)
DATA
@@ -130,6 +130,7 @@ _tx_version_id:
DC8 20H, 43H, 6FH, 6DH, 70H, 6CH, 69H, 61H
DC8 6EH, 74H, 20H, 2AH, 0
DC8 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
#endif //TX_MISRA_ENABLE
/**************************************************************************/
/**************************************************************************/
ports/cortex_m55/ac6/example_build/AzureRTOS.uvmpw
+26
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@@ -0,0 +1,26 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectWorkspace xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_mpw.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<WorkspaceName>WorkSpace</WorkspaceName>
<project>
<PathAndName>.\demo_secure_zone\demo_secure_zone.uvprojx</PathAndName>
<NodeIsActive>1</NodeIsActive>
<NodeIsExpanded>1</NodeIsExpanded>
</project>
<project>
<PathAndName>.\demo_threadx_non-secure_zone\demo_threadx_non-secure_zone.uvprojx</PathAndName>
<NodeIsExpanded>1</NodeIsExpanded>
</project>
<project>
<PathAndName>.\ThreadX_Library.uvprojx</PathAndName>
<NodeIsExpanded>1</NodeIsExpanded>
</project>
</ProjectWorkspace>
ports/cortex_m55/ac6/example_build/CS300_ac6.sct
+137
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@@ -0,0 +1,137 @@
#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc
; command above MUST be in first line (no comment above!)
;Note: Add '-mcmse' to first line if your software model is "Secure Mode".
; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc -mcmse
/*
;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
*/
/*
ID From To Alias Security NSC
1 0x0000_0000 0x000F_FFFF 1MB Code ITCM 4 NS n/a
2 0x0010_0000 0x002F_FFFF 2MB Code SRAM (only 2MB) 5 NS n/a
4 0x1000_0000 0x100F_FFFF 1MB Code ITCM 1 S n/a
5 0x1100_0000 0x102F_FFFF 2MB Code SRAM (only 2MB) 2 S CODE NSC
7 0x2000_0000 0x203F_FFFF 4MB SRAM DTCM (4 x 1MB) 11 NS n/a
11 0x3000_0000 0x303F_FFFF 4MB SRAM DTCM (4 x 1MB) 7 S n/a
*/
/*--------------------- Flash Configuration ----------------------------------
; <h> Flash Configuration
; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __ROM_BASE 0x00080000
#define __ROM_SIZE 0x00080000
/*--------------------- Embedded RAM Configuration ---------------------------
; <h> RAM Configuration
; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __RAM_BASE 0x20080000
#define __RAM_SIZE 0x00080000
/*--------------------- Stack / Heap Configuration ---------------------------
; <h> Stack / Heap Configuration
; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __STACK_SIZE 0x00000400
#define __HEAP_SIZE 0x00000C00
/*--------------------- CMSE Veneer Configuration ---------------------------
; <h> CMSE Veneer Configuration
; <o0> CMSE VeneerBase Address <0x0-0xFFFFFFFF:8>
; <i> 0xFFFFFFFF: Place Veneers at the end of Flash (default)
; <o1> CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>
; </h>
*----------------------------------------------------------------------------*/
#define __CMSEVENEER_BASE 0x10100000
#define __CMSEVENEER_SIZE 0x00000400
/*
;------------- <<< end of configuration section >>> ---------------------------
*/
/*----------------------------------------------------------------------------
User Stack & Heap boundary definition
*----------------------------------------------------------------------------*/
#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */
#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
/* ----------------------------------------------------------------------------
Stack seal size definition
*----------------------------------------------------------------------------*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define __STACKSEAL_SIZE ( 8 )
#else
#define __STACKSEAL_SIZE ( 0 )
#endif
/*----------------------------------------------------------------------------
Region base & size definition
*----------------------------------------------------------------------------*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#if defined (__CMSEVENEER_BASE) && (__CMSEVENEER_BASE == 0xFFFFFFFF)
#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )
#else
#define __CV_BASE ( __CMSEVENEER_BASE )
#endif
#define __CV_SIZE ( __CMSEVENEER_SIZE )
#else
#define __CV_SIZE ( 0 )
#endif
#define __RO_BASE ( __ROM_BASE )
#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE )
#define __RW_BASE ( __RAM_BASE )
#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE )
/*----------------------------------------------------------------------------
Scatter Region definition
*----------------------------------------------------------------------------*/
LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_RAM __RW_BASE __RW_SIZE { ; RW data
.ANY (+RW +ZI)
}
#if __HEAP_SIZE > 0
ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
}
#endif
ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack
}
#endif
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers
ER_CMSE_VENEER __CV_BASE __CV_SIZE {
*(Veneer$$CMSE)
}
}
#endif
ports/cortex_m55/ac6/example_build/CS300_ac6_s.sct
+137
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@@ -0,0 +1,137 @@
#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse
; command above MUST be in first line (no comment above!)
;Note: Add '-mcmse' to first line if your software model is "Secure Mode".
; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc -mcmse
/*
;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
*/
/*
ID From To Alias Security NSC
1 0x0000_0000 0x000F_FFFF 1MB Code ITCM 4 NS n/a
2 0x0010_0000 0x002F_FFFF 2MB Code SRAM (only 2MB) 5 NS n/a
4 0x1000_0000 0x100F_FFFF 1MB Code ITCM 1 S n/a
5 0x1100_0000 0x102F_FFFF 2MB Code SRAM (only 2MB) 2 S CODE NSC
7 0x2000_0000 0x203F_FFFF 4MB SRAM DTCM (4 x 1MB) 11 NS n/a
11 0x3000_0000 0x303F_FFFF 4MB SRAM DTCM (4 x 1MB) 7 S n/a
*/
/*--------------------- Flash Configuration ----------------------------------
; <h> Flash Configuration
; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __ROM_BASE 0x10000000
#define __ROM_SIZE 0x00080000
/*--------------------- Embedded RAM Configuration ---------------------------
; <h> RAM Configuration
; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __RAM_BASE 0x30000000
#define __RAM_SIZE 0x00080000
/*--------------------- Stack / Heap Configuration ---------------------------
; <h> Stack / Heap Configuration
; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __STACK_SIZE 0x00000400
#define __HEAP_SIZE 0x00000C00
/*--------------------- CMSE Veneer Configuration ---------------------------
; <h> CMSE Veneer Configuration
; <o0> CMSE VeneerBase Address <0x0-0xFFFFFFFF:8>
; <i> 0xFFFFFFFF: Place Veneers at the end of Flash (default)
; <o1> CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>
; </h>
*----------------------------------------------------------------------------*/
#define __CMSEVENEER_BASE 0x11000000
#define __CMSEVENEER_SIZE 0x00000400
/*
;------------- <<< end of configuration section >>> ---------------------------
*/
/*----------------------------------------------------------------------------
User Stack & Heap boundary definition
*----------------------------------------------------------------------------*/
#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */
#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
/* ----------------------------------------------------------------------------
Stack seal size definition
*----------------------------------------------------------------------------*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define __STACKSEAL_SIZE ( 8 )
#else
#define __STACKSEAL_SIZE ( 0 )
#endif
/*----------------------------------------------------------------------------
Region base & size definition
*----------------------------------------------------------------------------*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#if defined (__CMSEVENEER_BASE) && (__CMSEVENEER_BASE == 0xFFFFFFFF)
#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )
#else
#define __CV_BASE ( __CMSEVENEER_BASE )
#endif
#define __CV_SIZE ( __CMSEVENEER_SIZE )
#else
#define __CV_SIZE ( 0 )
#endif
#define __RO_BASE ( __ROM_BASE )
#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE )
#define __RW_BASE ( __RAM_BASE )
#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE )
/*----------------------------------------------------------------------------
Scatter Region definition
*----------------------------------------------------------------------------*/
LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_RAM __RW_BASE __RW_SIZE { ; RW data
.ANY (+RW +ZI)
}
#if __HEAP_SIZE > 0
ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
}
#endif
ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack
}
#endif
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers
ER_CMSE_VENEER __CV_BASE __CV_SIZE {
*(Veneer$$CMSE)
}
}
#endif
ports/cortex_m55/ac6/example_build/CS300_config.txt
+19
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@@ -0,0 +1,19 @@
# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#------------------------------------------------------------------------------
cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
#cpu0.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction)
#cpu0.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction)
#cpu0.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)
cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support
cpu0.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included
#cpu0.SAU=8 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU)
#cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included
#cpu0.INITSVTOR=0x10000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset
#cpu0.INITNSVTOR=0x00000000 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset
#NSC_CFG_0=1 # (bool , init-time) default = '0' : Whether 0x10000000..0x1FFFFFFF is non-secure-callable
#NSC_CFG_1=0 # (bool , init-time) default = '0' : Whether 0x30000000..0x3FFFFFFF is non-secure-callable
#mps3_board.platform_type=1 # (int , init-time) default = '0x1' : 0:Original MPS3; 1:SSE-300
mps3_board.visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation
#cpu_core.mps3_board.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic
#------------------------------------------------------------------------------
ports/cortex_m55/ac6/example_build/Debug.ini
+4
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@@ -0,0 +1,4 @@
LOAD "..\\demo_threadx_non-secure_zone\\Objects\\demo_threadx_non-secure_zone.axf" incremental
LOAD "..\\demo_secure_zone\\Objects\\secure_app.axf" incremental
RESET
g, \\secure_app\main_s\main
ports/cortex_m55/ac6/example_build/RTE/_ThreadX_Library_Project/RTE_Components.h
+21
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@@ -0,0 +1,21 @@
/*
* Auto generated Run-Time-Environment Configuration File
* *** Do not modify ! ***
*
* Project: 'ThreadX_Library'
* Target: 'ThreadX_Library_Project'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
/*
* Define the Device Header File:
*/
#define CMSIS_device_header "ARMCM55.h"
#endif /* RTE_COMPONENTS_H */
ports/cortex_m55/ac6/example_build/RTOS.uvmpw.uvgui
+1777
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File diff suppressed because one or more lines are too long
ports/cortex_m55/ac6/example_build/ThreadX_Library.uvoptx
+2576
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File diff suppressed because it is too large Load Diff
ports/cortex_m55/ac6/example_build/ThreadX_Library.uvprojx
+1424
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ports/cortex_m55/ac6/example_build/demo_secure_zone/RTE/Device/SSE-300-MPS3/RTE_Device.h
+84
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@@ -0,0 +1,84 @@
/*
* Copyright (c) 2019-2022 Arm Limited. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __RTE_DEVICE_H
#define __RTE_DEVICE_H
// <q> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0]
// <i> Configuration settings for Driver_USART0 in component ::Drivers:USART
#define RTE_USART0 1
// <q> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1]
// <i> Configuration settings for Driver_USART1 in component ::Drivers:USART
#define RTE_USART1 1
// <q> MPC (Memory Protection Controller) [Driver_ISRAM0_MPC]
// <i> Configuration settings for Driver_ISRAM0_MPC in component ::Drivers:MPC
#define RTE_ISRAM0_MPC 1
// <q> MPC (Memory Protection Controller) [Driver_ISRAM1_MPC]
// <i> Configuration settings for Driver_ISRAM1_MPC in component ::Drivers:MPC
#define RTE_ISRAM1_MPC 1
// <q> MPC (Memory Protection Controller) [Driver_SRAM_MPC]
// <i> Configuration settings for Driver_SRAM_MPC in component ::Drivers:MPC
#define RTE_SRAM_MPC 1
// <q> MPC (Memory Protection Controller) [Driver_QSPI_MPC]
// <i> Configuration settings for Driver_QSPI_MPC in component ::Drivers:MPC
#define RTE_QSPI_MPC 1
// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN0]
// <i> Configuration settings for Driver_PPC_SSE300_MAIN0 in component ::Drivers:PPC
#define RTE_PPC_SSE300_MAIN0 1
// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP0]
// <i> Configuration settings for Driver_PPC_SSE300_MAIN_EXP0 in component ::Drivers:PPC
#define RTE_PPC_SSE300_MAIN_EXP0 1
// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP1]
// <i> Configuration settings for Driver_PPC_SSE300_MAIN_EXP1 in component ::Drivers:PPC
#define RTE_PPC_SSE300_MAIN_EXP1 1
// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH0]
// <i> Configuration settings for Driver_PPC_SSE300_PERIPH0 in component ::Drivers:PPC
#define RTE_PPC_SSE300_PERIPH0 1
// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH1]
// <i> Configuration settings for Driver_PPC_SSE300_PERIPH1 in component ::Drivers:PPC
#define RTE_PPC_SSE300_PERIPH1 1
// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP0]
// <i> Configuration settings for Driver_PPC_SSE300_PERIPH_EXP0 in component ::Drivers:PPC
#define RTE_PPC_SSE300_PERIPH_EXP0 1
// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP1]
// <i> Configuration settings for Driver_PPC_SSE300_PERIPH_EXP1 in component ::Drivers:PPC
#define RTE_PPC_SSE300_PERIPH_EXP1 1
// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP2]
// <i> Configuration settings for Driver_PPC_SSE300_PERIPH_EXP2 in component ::Drivers:PPC
#define RTE_PPC_SSE300_PERIPH_EXP2 1
// <q> Flash device emulated by SRAM [Driver_Flash0]
// <i> Configuration settings for Driver_Flash0 in component ::Drivers:Flash
#define RTE_FLASH0 1
// <q> I2C SBCon [Driver_I2C0]
// <i> Configuration settings for Driver_I2C0 in component ::Drivers:I2C
#define RTE_I2C0 1
#endif /* __RTE_DEVICE_H */
ports/cortex_m55/ac6/example_build/demo_secure_zone/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h
+25
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@@ -0,0 +1,25 @@
/*
* Copyright (c) 2019-2022 Arm Limited. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_DRIVER_CONFIG_H__
#define __CMSIS_DRIVER_CONFIG_H__
#include "system_SSE300MPS3.h"
#include "device_cfg.h"
#include "device_definition.h"
#include "platform_base_address.h"
#endif /* __CMSIS_DRIVER_CONFIG_H__ */
ports/cortex_m55/ac6/example_build/demo_secure_zone/RTE/Device/SSE-300-MPS3/device_cfg.h
+149
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@@ -0,0 +1,149 @@
/*
* Copyright (c) 2020-2022 Arm Limited. All rights reserved.
*
* Licensed under the Apache License Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing software
* distributed under the License is distributed on an "AS IS" BASIS
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __DEVICE_CFG_H__
#define __DEVICE_CFG_H__
/**
* \file device_cfg.h
* \brief Configuration file native driver re-targeting
*
* \details This file can be used to add native driver specific macro
* definitions to select which peripherals are available in the build.
*
* This is a default device configuration file with all peripherals enabled.
*/
/* Secure only peripheral configuration */
/* ARM MPS3 IO SCC */
#define MPS3_IO_S
#define MPS3_IO_DEV MPS3_IO_DEV_S
/* I2C_SBCon */
#define I2C0_SBCON_S
#define I2C0_SBCON_DEV I2C0_SBCON_DEV_S
/* I2S */
#define MPS3_I2S_S
#define MPS3_I2S_DEV MPS3_I2S_DEV_S
/* ARM UART Controller PL011 */
#define UART0_CMSDK_S
#define UART0_CMSDK_DEV UART0_CMSDK_DEV_S
#define UART1_CMSDK_S
#define UART1_CMSDK_DEV UART1_CMSDK_DEV_S
#define DEFAULT_UART_BAUDRATE 115200U
/* To be used as CODE and DATA sram */
#define MPC_ISRAM0_S
#define MPC_ISRAM0_DEV MPC_ISRAM0_DEV_S
#define MPC_ISRAM1_S
#define MPC_ISRAM1_DEV MPC_ISRAM0_DEV_S
#define MPC_SRAM_S
#define MPC_SRAM_DEV MPC_SRAM_DEV_S
#define MPC_QSPI_S
#define MPC_QSPI_DEV MPC_QSPI_DEV_S
/** System Counter Armv8-M */
#define SYSCOUNTER_CNTRL_ARMV8_M_S
#define SYSCOUNTER_CNTRL_ARMV8_M_DEV SYSCOUNTER_CNTRL_ARMV8_M_DEV_S
#define SYSCOUNTER_READ_ARMV8_M_S
#define SYSCOUNTER_READ_ARMV8_M_DEV SYSCOUNTER_READ_ARMV8_M_DEV_S
/**
* Arbitrary scaling values for test purposes
*/
#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT 1u
#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT 0u
#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT 1u
#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 0u
/* System timer */
#define SYSTIMER0_ARMV8_M_S
#define SYSTIMER0_ARMV8_M_DEV SYSTIMER0_ARMV8_M_DEV_S
#define SYSTIMER1_ARMV8_M_S
#define SYSTIMER1_ARMV8_M_DEV SYSTIMER1_ARMV8_M_DEV_S
#define SYSTIMER2_ARMV8_M_S
#define SYSTIMER2_ARMV8_M_DEV SYSTIMER2_ARMV8_M_DEV_S
#define SYSTIMER3_ARMV8_M_S
#define SYSTIMER3_ARMV8_M_DEV SYSTIMER3_ARMV8_M_DEV_S
#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ (25000000ul)
#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ (25000000ul)
#define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ (25000000ul)
#define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ (25000000ul)
/* CMSDK GPIO driver structures */
#define GPIO0_CMSDK_S
#define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S
#define GPIO1_CMSDK_S
#define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S
#define GPIO2_CMSDK_S
#define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S
#define GPIO3_CMSDK_S
#define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S
/* System Watchdogs */
#define SYSWDOG_ARMV8_M_S
#define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S
/* ARM MPC SIE 300 driver structures */
#define MPC_VM0_S
#define MPC_VM0_DEV MPC_VM0_DEV_S
#define MPC_VM1_S
#define MPC_VM1_DEV MPC_VM1_DEV_S
#define MPC_SSRAM2_S
#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S
#define MPC_SSRAM3_S
#define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S
/* ARM PPC driver structures */
#define PPC_SSE300_MAIN0_S
#define PPC_SSE300_MAIN0_DEV PPC_SSE300_MAIN0_DEV_S
#define PPC_SSE300_MAIN_EXP0_S
#define PPC_SSE300_MAIN_EXP0_DEV PPC_SSE300_MAIN_EXP0_DEV_S
#define PPC_SSE300_MAIN_EXP1_S
#define PPC_SSE300_MAIN_EXP1_DEV PPC_SSE300_MAIN_EXP1_DEV_S
#define PPC_SSE300_MAIN_EXP2_S
#define PPC_SSE300_MAIN_EXP2_DEV PPC_SSE300_MAIN_EXP2_DEV_S
#define PPC_SSE300_MAIN_EXP3_S
#define PPC_SSE300_MAIN_EXP3_DEV PPC_SSE300_MAIN_EXP3_DEV_S
#define PPC_SSE300_PERIPH0_S
#define PPC_SSE300_PERIPH0_DEV PPC_SSE300_PERIPH0_DEV_S
#define PPC_SSE300_PERIPH1_S
#define PPC_SSE300_PERIPH1_DEV PPC_SSE300_PERIPH1_DEV_S
#define PPC_SSE300_PERIPH_EXP0_S
#define PPC_SSE300_PERIPH_EXP0_DEV PPC_SSE300_PERIPH_EXP0_DEV_S
#define PPC_SSE300_PERIPH_EXP1_S
#define PPC_SSE300_PERIPH_EXP1_DEV PPC_SSE300_PERIPH_EXP1_DEV_S
#define PPC_SSE300_PERIPH_EXP2_S
#define PPC_SSE300_PERIPH_EXP2_DEV PPC_SSE300_PERIPH_EXP2_DEV_S
#define PPC_SSE300_PERIPH_EXP3_S
#define PPC_SSE300_PERIPH_EXP3_DEV PPC_SSE300_PERIPH_EXP3_DEV_S
/* ARM SPI PL022 */
/* Invalid device stubs are not defined */
#define DEFAULT_SPI_SPEED_HZ 4000000U /* 4MHz */
#define SPI1_PL022_S
#define SPI1_PL022_DEV SPI1_PL022_DEV_S
#endif /* __DEVICE_CFG_H__ */
ports/cortex_m55/ac6/example_build/demo_secure_zone/RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct
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#! armclang --target=arm-arm-none-eabi -march=armv8.1-m.main -E -xc
;/*
; * Copyright (c) 2018-2021 Arm Limited. All rights reserved.
; *
; * Licensed under the Apache License, Version 2.0 (the "License");
; * you may not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * http://www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an "AS IS" BASIS,
; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; *
; */
#include "region_defs.h"
LR_CODE S_CODE_START {
ER_CODE S_CODE_START {
*.o (RESET +First)
.ANY (+RO)
}
/*
* Place the CMSE Veneers (containing the SG instruction) after the code, in
* a separate 32 bytes aligned region so that the SAU can programmed to just
* set this region as Non-Secure Callable. The maximum size of this
* executable region makes it only used the space left over by the ER_CODE
* region so that you can rely on code+veneer size combined will not exceed
* the S_CODE_SIZE value. We also substract from the available space the
* area used to align this section on 32 bytes boundary (for SAU conf).
*/
ER_CODE_CMSE_VENEER +0 ALIGN 32 {
*(Veneer$$CMSE)
}
/*
* This dummy region ensures that the next one will be aligned on a 32 bytes
* boundary, so that the following region will not be mistakenly configured
* as Non-Secure Callable by the SAU.
*/
ER_CODE_CMSE_VENEER_DUMMY +0 ALIGN 32 EMPTY 0 {}
/* This empty, zero long execution region is here to mark the limit address
* of the last execution region that is allocated in SRAM.
*/
CODE_WATERMARK +0 EMPTY 0x0 {
}
/* Make sure that the sections allocated in the SRAM does not exceed the
* size of the SRAM available.
*/
ScatterAssert(ImageLimit(CODE_WATERMARK) <= S_CODE_START + S_CODE_SIZE)
ER_DATA S_DATA_START {
.ANY (+ZI +RW)
}
#if HEAP_SIZE > 0
ARM_LIB_HEAP +0 ALIGN 8 EMPTY HEAP_SIZE { ; Reserve empty region for heap
}
#endif
ARM_LIB_STACK +0 ALIGN 32 EMPTY STACK_SIZE { ; Reserve empty region for stack
}
/* This empty, zero long execution region is here to mark the limit address
* of the last execution region that is allocated in SRAM.
*/
SRAM_WATERMARK +0 EMPTY 0x0 {
}
/* Make sure that the sections allocated in the SRAM does not exceed the
* size of the SRAM available.
*/
ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE)
}
ports/cortex_m55/ac6/example_build/demo_secure_zone/RTE/Device/SSE-300-MPS3/partition_CS300.h
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ports/cortex_m55/ac6/example_build/demo_secure_zone/RTE/Device/SSE-300-MPS3/platform_base_address.h
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/*
* Copyright (c) 2019-2021 Arm Limited
*
* Licensed under the Apache License Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing software
* distributed under the License is distributed on an "AS IS" BASIS
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* \file platform_base_address.h
* \brief This file defines all the peripheral base addresses for AN552 MPS3 SSE-300 +
* Ethos-U55 platform.
*/
#ifndef __PLATFORM_BASE_ADDRESS_H__
#define __PLATFORM_BASE_ADDRESS_H__
/* ======= Defines peripherals memory map addresses ======= */
/* Non-secure memory map addresses */
#define ITCM_BASE_NS 0x00000000 /* Instruction TCM Non-Secure base address */
#define SRAM_BASE_NS 0x01000000 /* CODE SRAM Non-Secure base address */
#define DTCM0_BASE_NS 0x20000000 /* Data TCM block 0 Non-Secure base address */
#define DTCM1_BASE_NS 0x20020000 /* Data TCM block 1 Non-Secure base address */
#define DTCM2_BASE_NS 0x20040000 /* Data TCM block 2 Non-Secure base address */
#define DTCM3_BASE_NS 0x20060000 /* Data TCM block 3 Non-Secure base address */
#define ISRAM0_BASE_NS 0x21000000 /* Internal SRAM Area Non-Secure base address */
#define ISRAM1_BASE_NS 0x21100000 /* Internal SRAM Area Non-Secure base address */
#define QSPI_SRAM_BASE_NS 0x28000000 /* QSPI SRAM Non-Secure base address */
/* Non-Secure Subsystem peripheral region */
#define CPU0_PWRCTRL_BASE_NS 0x40012000 /* CPU 0 Power Control Block Non-Secure base address */
#define CPU0_IDENTITY_BASE_NS 0x4001F000 /* CPU 0 Identity Block Non-Secure base address */
#define SSE300_NSACFG_BASE_NS 0x40080000 /* SSE-300 Non-Secure Access Configuration Register Block Non-Secure base address */
/* Non-Secure MSTEXPPILL Peripheral region */
#define GPIO0_CMSDK_BASE_NS 0x41100000 /* GPIO 0 Non-Secure base address */
#define GPIO1_CMSDK_BASE_NS 0x41101000 /* GPIO 1 Non-Secure base address */
#define GPIO2_CMSDK_BASE_NS 0x41102000 /* GPIO 2 Non-Secure base address */
#define GPIO3_CMSDK_BASE_NS 0x41103000 /* GPIO 3 Non-Secure base address */
#define FMC_CMSDK_GPIO_0_BASE_NS 0x41104000 /* FMC CMSDK GPIO 0 Non-Secure base address */
#define FMC_CMSDK_GPIO_1_BASE_NS 0x41105000 /* FMC CMSDK GPIO 1 Non-Secure base address */
#define FMC_CMSDK_GPIO_2_BASE_NS 0x41106000 /* FMC CMSDK GPIO 2 Non-Secure base address */
#define FMC_CMSDK_GPIO_3_BASE_NS 0x41107000 /* FMC CMSDK GPIO 3 Non-Secure base address */
#define EXTERNAL_MANAGER_0_BASE_NS 0x41200000 /* External manager 0 (Unused) Non-Secure base address */
#define EXTERNAL_MANAGER_1_BASE_NS 0x41201000 /* External manager 1 (Unused) Non-Secure base address */
#define EXTERNAL_MANAGER_2_BASE_NS 0x41202000 /* External manager 2 (Unused) Non-Secure base address */
#define EXTERNAL_MANAGER_3_BASE_NS 0x41203000 /* External manager 3 (Unused) Non-Secure base address */
#define ETHERNET_BASE_NS 0x41400000 /* Ethernet Non-Secure base address */
#define USB_BASE_NS 0x41500000 /* USB Non-Secure base address */
#define USER_APB0_BASE_NS 0x41700000 /* User APB 0 Non-Secure base address */
#define USER_APB1_BASE_NS 0x41701000 /* User APB 1 Non-Secure base address */
#define USER_APB2_BASE_NS 0x41702000 /* User APB 2 Non-Secure base address */
#define USER_APB3_BASE_NS 0x41703000 /* User APB 3 Non-Secure base address */
#define QSPI_CONFIG_BASE_NS 0x41800000 /* QSPI Config Non-Secure base address */
#define QSPI_WRITE_BASE_NS 0x41801000 /* QSPI Write Non-Secure base address */
/* Non-Secure Subsystem peripheral region */
#define SYSTIMER0_ARMV8_M_BASE_NS 0x48000000 /* System Timer 0 Non-Secure base address */
#define SYSTIMER1_ARMV8_M_BASE_NS 0x48001000 /* System Timer 1 Non-Secure base address */
#define SYSTIMER2_ARMV8_M_BASE_NS 0x48002000 /* System Timer 2 Non-Secure base address */
#define SYSTIMER3_ARMV8_M_BASE_NS 0x48003000 /* System Timer 3 Non-Secure base address */
#define SSE300_SYSINFO_BASE_NS 0x48020000 /* SSE-300 System info Block Non-Secure base address */
#define SLOWCLK_TIMER_CMSDK_BASE_NS 0x4802F000 /* CMSDK based SLOWCLK Timer Non-Secure base address */
#define SYSWDOG_ARMV8_M_CNTRL_BASE_NS 0x48040000 /* Non-Secure Watchdog Timer control frame Non-Secure base address */
#define SYSWDOG_ARMV8_M_REFRESH_BASE_NS 0x48041000 /* Non-Secure Watchdog Timer refresh frame Non-Secure base address */
#define SYSCNTR_READ_BASE_NS 0x48101000 /* System Counter Read Secure base address */
/* Non-Secure MSTEXPPIHL Peripheral region */
#define ETHOS_U55_APB_BASE_NS 0x48102000 /* Ethos-U55 APB Non-Secure base address */
#define U55_TIMING_ADAPTER_0_BASE_NS 0x48103000 /* Ethos-U55 Timing Adapter 0 APB registers Non-Secure base address */
#define U55_TIMING_ADAPTER_1_BASE_NS 0x48103200 /* Ethos-U55 Timing Adapter 1 APB registers Non-Secure base address */
#define FPGA_SBCon_I2C_TOUCH_BASE_NS 0x49200000 /* FPGA - SBCon I2C (Touch) Non-Secure base address */
#define FPGA_SBCon_I2C_AUDIO_BASE_NS 0x49201000 /* FPGA - SBCon I2C (Audio Conf) Non-Secure base address */
#define FPGA_SPI_ADC_BASE_NS 0x49202000 /* FPGA - PL022 (SPI ADC) Non-Secure base address */
#define FPGA_SPI_SHIELD0_BASE_NS 0x49203000 /* FPGA - PL022 (SPI Shield0) Non-Secure base address */
#define FPGA_SPI_SHIELD1_BASE_NS 0x49204000 /* FPGA - PL022 (SPI Shield1) Non-Secure base address */
#define SBCon_I2C_SHIELD0_BASE_NS 0x49205000 /* SBCon (I2C - Shield0) Non-Secure base address */
#define SBCon_I2C_SHIELD1_BASE_NS 0x49206000 /* SBCon (I2C – Shield1) Non-Secure base address */
#define USER_APB_BASE_NS 0x49207000 /* USER APB Non-Secure base address */
#define FPGA_DDR4_EEPROM_BASE_NS 0x49208000 /* FPGA - SBCon I2C (DDR4 EEPROM) Non-Secure base address */
#define FMC_USER_APB0 0x4920C000 /* FMC User APB0 */
#define FMC_USER_APB1 0x4920D000 /* FMC User APB1 */
#define FMC_USER_APB2 0x4920E000 /* FMC User APB2 */
#define FMC_USER_APB3 0x4920F000 /* FMC User APB3 */
#define FPGA_SCC_BASE_NS 0x49300000 /* FPGA - SCC registers Non-Secure base address */
#define FPGA_I2S_BASE_NS 0x49301000 /* FPGA - I2S (Audio) Non-Secure base address */
#define FPGA_IO_BASE_NS 0x49302000 /* FPGA - IO (System Ctrl + I/O) Non-Secure base address */
#define UART0_BASE_NS 0x49303000 /* UART 0 Non-Secure base address */
#define UART1_BASE_NS 0x49304000 /* UART 1 Non-Secure base address */
#define UART2_BASE_NS 0x49305000 /* UART 2 Non-Secure base address */
#define UART3_BASE_NS 0x49306000 /* UART 3 Non-Secure base address */
#define UART4_BASE_NS 0x49307000 /* UART 4 Non-Secure base address */
#define UART5_BASE_NS 0x49308000 /* UART 5 Non-Secure base address */
#define CLCD_Config_Reg_BASE_NS 0x4930A000 /* CLCD Config Reg Non-Secure base address */
#define RTC_BASE_NS 0x4930B000 /* RTC Non-Secure base address */
#define DDR4_BLK0_BASE_NS 0x60000000 /* DDR4 block 0 Non-Secure base address */
#define DDR4_BLK2_BASE_NS 0x80000000 /* DDR4 block 2 Non-Secure base address */
#define DDR4_BLK4_BASE_NS 0xA0000000 /* DDR4 block 4 Non-Secure base address */
#define DDR4_BLK6_BASE_NS 0xC0000000 /* DDR4 block 6 Non-Secure base address */
/* Secure memory map addresses */
#define ITCM_BASE_S 0x10000000 /* Instruction TCM Secure base address */
#define SRAM_BASE_S 0x11000000 /* CODE SRAM Secure base address */
#define DTCM0_BASE_S 0x30000000 /* Data TCM block 0 Secure base address */
#define DTCM1_BASE_S 0x30020000 /* Data TCM block 1 Secure base address */
#define DTCM2_BASE_S 0x30040000 /* Data TCM block 2 Secure base address */
#define DTCM3_BASE_S 0x30060000 /* Data TCM block 3 Secure base address */
#define ISRAM0_BASE_S 0x31000000 /* Internal SRAM Area Secure base address */
#define ISRAM1_BASE_S 0x31100000 /* Internal SRAM Area Secure base address */
#define QSPI_SRAM_BASE_S 0x38000000 /* QSPI SRAM Secure base address */
/* Secure Subsystem peripheral region */
#define CPU0_SECCTRL_BASE_S 0x50011000 /* CPU 0 Local Security Control Block Secure base address */
#define CPU0_PWRCTRL_BASE_S 0x50012000 /* CPU 0 Power Control Block Secure base address */
#define CPU0_IDENTITY_BASE_S 0x5001F000 /* CPU 0 Identity Block Secure base address */
#define SSE300_SACFG_BASE_S 0x50080000 /* SSE-300 Secure Access Configuration Register Secure base address */
#define MPC_ISRAM0_BASE_S 0x50083000 /* Internal SRAM0 Memory Protection Controller Secure base address */
#define MPC_ISRAM1_BASE_S 0x50084000 /* Internal SRAM1 Memory Protection Controller Secure base address */
/* Secure MSTEXPPILL Peripheral region */
#define GPIO0_CMSDK_BASE_S 0x51100000 /* GPIO 0 Secure base address */
#define GPIO1_CMSDK_BASE_S 0x51101000 /* GPIO 1 Secure base address */
#define GPIO2_CMSDK_BASE_S 0x51102000 /* GPIO 2 Secure base address */
#define GPIO3_CMSDK_BASE_S 0x51103000 /* GPIO 3 Secure base address */
#define FMC_CMSDK_GPIO_0_BASE_S 0x51104000 /* FMC CMSDK GPIO 0 Secure base address */
#define FMC_CMSDK_GPIO_1_BASE_S 0x51105000 /* FMC CMSDK GPIO 1 Secure base address */
#define FMC_CMSDK_GPIO_2_BASE_S 0x51106000 /* FMC CMSDK GPIO 2 Secure base address */
#define FMC_CMSDK_GPIO_3_BASE_S 0x51107000 /* FMC CMSDK GPIO 3 Secure base address */
#define EXTERNAL_MANAGER0_BASE_S 0x51200000 /* External Manager 0 (Unused) Secure base address */
#define EXTERNAL_MANAGER1_BASE_S 0x51201000 /* External Manager 1 (Unused) Secure base address */
#define EXTERNAL_MANAGER2_BASE_S 0x51202000 /* External Manager 2 (Unused) Secure base address */
#define EXTERNAL_MANAGER3_BASE_S 0x51203000 /* External Manager 3 (Unused) Secure base address */
#define ETHERNET_BASE_S 0x51400000 /* Ethernet Secure base address */
#define USB_BASE_S 0x51500000 /* USB Secure base address */
#define USER_APB0_BASE_S 0x51700000 /* User APB 0 Secure base address */
#define USER_APB1_BASE_S 0x51701000 /* User APB 1 Secure base address */
#define USER_APB2_BASE_S 0x51702000 /* User APB 2 Secure base address */
#define USER_APB3_BASE_S 0x51703000 /* User APB 3 Secure base address */
#define QSPI_CONFIG_BASE_S 0x51800000 /* QSPI Config Secure base address */
#define QSPI_WRITE_BASE_S 0x51801000 /* QSPI Write Secure base address */
#define MPC_SRAM_BASE_S 0x57000000 /* SRAM Memory Protection Controller Secure base address */
#define MPC_QSPI_BASE_S 0x57001000 /* QSPI Memory Protection Controller Secure base address */
#define MPC_DDR4_BASE_S 0x57002000 /* DDR4 Memory Protection Controller Secure base address */
/* Secure Subsystem peripheral region */
#define SYSTIMER0_ARMV8_M_BASE_S 0x58000000 /* System Timer 0 Secure base address */
#define SYSTIMER1_ARMV8_M_BASE_S 0x58001000 /* System Timer 1 Secure base address */
#define SYSTIMER2_ARMV8_M_BASE_S 0x58002000 /* System Timer 0 Secure base address */
#define SYSTIMER3_ARMV8_M_BASE_S 0x58003000 /* System Timer 1 Secure base address */
#define SSE300_SYSINFO_BASE_S 0x58020000 /* SSE-300 System info Block Secure base address */
#define SSE300_SYSCTRL_BASE_S 0x58021000 /* SSE-300 System control Block Secure base address */
#define SSE300_SYSPPU_BASE_S 0x58022000 /* SSE-300 System Power Policy Unit Secure base address */
#define SSE300_CPU0PPU_BASE_S 0x58023000 /* SSE-300 CPU 0 Power Policy Unit Secure base address */
#define SSE300_MGMTPPU_BASE_S 0x58028000 /* SSE-300 Management Power Policy Unit Secure base address */
#define SSE300_DBGPPU_BASE_S 0x58029000 /* SSE-300 Debug Power Policy Unit Secure base address */
#define SLOWCLK_WDOG_CMSDK_BASE_S 0x5802E000 /* CMSDK based SLOWCLK Watchdog Secure base address */
#define SLOWCLK_TIMER_CMSDK_BASE_S 0x5802F000 /* CMSDK based SLOWCLK Timer Secure base address */
#define SYSWDOG_ARMV8_M_CNTRL_BASE_S 0x58040000 /* Secure Watchdog Timer control frame Secure base address */
#define SYSWDOG_ARMV8_M_REFRESH_BASE_S 0x58041000 /* Secure Watchdog Timer refresh frame Secure base address */
#define SYSCNTR_CNTRL_BASE_S 0x58100000 /* System Counter Control Secure base address */
#define SYSCNTR_READ_BASE_S 0x58101000 /* System Counter Read Secure base address */
/* Secure MSTEXPPIHL Peripheral region */
#define ETHOS_U55_APB_BASE_S 0x58102000 /* Ethos-U55 APB Secure base address */
#define U55_TIMING_ADAPTER_0_BASE_S 0x58103000 /* Ethos-U55 Timing Adapter 0 APB registers Secure base address */
#define U55_TIMING_ADAPTER_1_BASE_S 0x58103200 /* Ethos-U55 Timing Adapter 1 APB registers Secure base address */
#define FPGA_SBCon_I2C_TOUCH_BASE_S 0x59200000 /* FPGA - SBCon I2C (Touch) Secure base address */
#define FPGA_SBCon_I2C_AUDIO_BASE_S 0x59201000 /* FPGA - SBCon I2C (Audio Conf) Secure base address */
#define FPGA_SPI_ADC_BASE_S 0x59202000 /* FPGA - PL022 (SPI ADC) Secure base address */
#define FPGA_SPI_SHIELD0_BASE_S 0x59203000 /* FPGA - PL022 (SPI Shield0) Secure base address */
#define FPGA_SPI_SHIELD1_BASE_S 0x59204000 /* FPGA - PL022 (SPI Shield1) Secure base address */
#define SBCon_I2C_SHIELD0_BASE_S 0x59205000 /* SBCon (I2C - Shield0) Secure base address */
#define SBCon_I2C_SHIELD1_BASE_S 0x59206000 /* SBCon (I2C – Shield1) Secure base address */
#define USER_APB_BASE_S 0x59207000 /* USER APB Secure base address */
#define FPGA_DDR4_EEPROM_BASE_S 0x59208000 /* FPGA - SBCon I2C (DDR4 EEPROM) Secure base address */
#define FMC_USER_APB_0_BASE_S 0x5920C000 /* FMC User APB0 registers Secure base address */
#define FMC_USER_APB_1_BASE_S 0x5920D000 /* FMC User APB1 registers Secure base address */
#define FMC_USER_APB_2_BASE_S 0x5920E000 /* FMC User APB2 registers Secure base address */
#define FMC_USER_APB_3_BASE_S 0x5920F000 /* FMC User APB3 registers Secure base address */
#define FPGA_SCC_BASE_S 0x59300000 /* FPGA - SCC registers Secure base address */
#define FPGA_I2S_BASE_S 0x59301000 /* FPGA - I2S (Audio) Secure base address */
#define FPGA_IO_BASE_S 0x59302000 /* FPGA - IO (System Ctrl + I/O) Secure base address */
#define UART0_BASE_S 0x59303000 /* UART 0 Secure base address */
#define UART1_BASE_S 0x59304000 /* UART 1 Secure base address */
#define UART2_BASE_S 0x59305000 /* UART 2 Secure base address */
#define UART3_BASE_S 0x59306000 /* UART 3 Secure base address */
#define UART4_BASE_S 0x59307000 /* UART 4 Secure base address */
#define UART5_BASE_S 0x59308000 /* UART 5 Secure base address */
#define CLCD_Config_Reg_BASE_S 0x5930A000 /* CLCD Config Reg Secure base address */
#define RTC_BASE_S 0x5930B000 /* RTC Secure base address */
#define DDR4_BLK1_BASE_S 0x70000000 /* DDR4 block 1 Secure base address */
#define DDR4_BLK3_BASE_S 0x90000000 /* DDR4 block 3 Secure base address */
#define DDR4_BLK5_BASE_S 0xB0000000 /* DDR4 block 5 Secure base address */
#define DDR4_BLK7_BASE_S 0xD0000000 /* DDR4 block 7 Secure base address */
/* Memory map addresses exempt from memory attribution by both the SAU and IDAU */
#define SSE300_EWIC_BASE 0xE0047000 /* External Wakeup Interrupt Controller
* Access from Non-secure software is only allowed
* if AIRCR.BFHFNMINS is set to 1 */
/* Memory size definitions */
#define ITCM_SIZE (0x00080000) /* 512 kB */
#define DTCM_BLK_SIZE (0x00020000) /* 128 kB */
#define DTCM_BLK_NUM (0x4) /* Number of DTCM blocks */
#define SRAM_SIZE (0x00100000) /* 1 MB */
#define ISRAM0_SIZE (0x00100000) /* 1 MB */
#define ISRAM1_SIZE (0x00100000) /* 1 MB */
#define QSPI_SRAM_SIZE (0x00800000) /* 8 MB */
#define DDR4_BLK_SIZE (0x10000000) /* 256 MB */
#define DDR4_BLK_NUM (0x8) /* Number of DDR4 blocks */
/* Defines for Driver MPC's */
/* SRAM -- 2 MB */
#define MPC_SRAM_RANGE_BASE_NS (SRAM_BASE_NS)
#define MPC_SRAM_RANGE_LIMIT_NS (SRAM_BASE_NS + SRAM_SIZE-1)
#define MPC_SRAM_RANGE_OFFSET_NS (0x0)
#define MPC_SRAM_RANGE_BASE_S (SRAM_BASE_S)
#define MPC_SRAM_RANGE_LIMIT_S (SRAM_BASE_S + SRAM_SIZE-1)
#define MPC_SRAM_RANGE_OFFSET_S (0x0)
/* QSPI -- 8 MB*/
#define MPC_QSPI_RANGE_BASE_NS (QSPI_SRAM_BASE_NS)
#define MPC_QSPI_RANGE_LIMIT_NS (QSPI_SRAM_BASE_NS + QSPI_SRAM_SIZE-1)
#define MPC_QSPI_RANGE_OFFSET_NS (0x0)
#define MPC_QSPI_RANGE_BASE_S (QSPI_SRAM_BASE_S)
#define MPC_QSPI_RANGE_LIMIT_S (QSPI_SRAM_BASE_S + QSPI_SRAM_SIZE-1)
#define MPC_QSPI_RANGE_OFFSET_S (0x0)
/* ISRAM0 -- 2 MB*/
#define MPC_ISRAM0_RANGE_BASE_NS (ISRAM0_BASE_NS)
#define MPC_ISRAM0_RANGE_LIMIT_NS (ISRAM0_BASE_NS + ISRAM0_SIZE-1)
#define MPC_ISRAM0_RANGE_OFFSET_NS (0x0)
#define MPC_ISRAM0_RANGE_BASE_S (ISRAM0_BASE_S)
#define MPC_ISRAM0_RANGE_LIMIT_S (ISRAM0_BASE_S + ISRAM0_SIZE-1)
#define MPC_ISRAM0_RANGE_OFFSET_S (0x0)
/* ISRAM1 -- 2 MB*/
#define MPC_ISRAM1_RANGE_BASE_NS (ISRAM1_BASE_NS)
#define MPC_ISRAM1_RANGE_LIMIT_NS (ISRAM1_BASE_NS + ISRAM1_SIZE-1)
#define MPC_ISRAM1_RANGE_OFFSET_NS (0x0)
#define MPC_ISRAM1_RANGE_BASE_S (ISRAM1_BASE_S)
#define MPC_ISRAM1_RANGE_LIMIT_S (ISRAM1_BASE_S + ISRAM1_SIZE-1)
#define MPC_ISRAM1_RANGE_OFFSET_S (0x0)
/* DDR4 -- 2GB (8 * 256 MB) */
#define MPC_DDR4_BLK0_RANGE_BASE_NS (DDR4_BLK0_BASE_NS)
#define MPC_DDR4_BLK0_RANGE_LIMIT_NS (DDR4_BLK0_BASE_NS + ((DDR4_BLK_SIZE)-1))
#define MPC_DDR4_BLK0_RANGE_OFFSET_NS (0x0)
#define MPC_DDR4_BLK1_RANGE_BASE_S (DDR4_BLK1_BASE_S)
#define MPC_DDR4_BLK1_RANGE_LIMIT_S (DDR4_BLK1_BASE_S + ((DDR4_BLK_SIZE)-1))
#define MPC_DDR4_BLK1_RANGE_OFFSET_S (DDR4_BLK1_BASE_S - DDR4_BLK0_BASE_NS)
#define MPC_DDR4_BLK2_RANGE_BASE_NS (DDR4_BLK2_BASE_NS)
#define MPC_DDR4_BLK2_RANGE_LIMIT_NS (DDR4_BLK2_BASE_NS + ((DDR4_BLK_SIZE)-1))
#define MPC_DDR4_BLK2_RANGE_OFFSET_NS (DDR4_BLK2_BASE_NS - DDR4_BLK0_BASE_NS)
#define MPC_DDR4_BLK3_RANGE_BASE_S (DDR4_BLK3_BASE_S)
#define MPC_DDR4_BLK3_RANGE_LIMIT_S (DDR4_BLK3_BASE_S + ((DDR4_BLK_SIZE)-1))
#define MPC_DDR4_BLK3_RANGE_OFFSET_S (DDR4_BLK3_BASE_S - DDR4_BLK0_BASE_NS)
#define MPC_DDR4_BLK4_RANGE_BASE_NS (DDR4_BLK4_BASE_NS)
#define MPC_DDR4_BLK4_RANGE_LIMIT_NS (DDR4_BLK4_BASE_NS + ((DDR4_BLK_SIZE)-1))
#define MPC_DDR4_BLK4_RANGE_OFFSET_NS (DDR4_BLK4_BASE_NS - DDR4_BLK0_BASE_NS)
#define MPC_DDR4_BLK5_RANGE_BASE_S (DDR4_BLK5_BASE_S)
#define MPC_DDR4_BLK5_RANGE_LIMIT_S (DDR4_BLK5_BASE_S + ((DDR4_BLK_SIZE)-1))
#define MPC_DDR4_BLK5_RANGE_OFFSET_S (DDR4_BLK5_BASE_S - DDR4_BLK0_BASE_NS)
#define MPC_DDR4_BLK6_RANGE_BASE_NS (DDR4_BLK6_BASE_NS)
#define MPC_DDR4_BLK6_RANGE_LIMIT_NS (DDR4_BLK6_BASE_NS + ((DDR4_BLK_SIZE)-1))
#define MPC_DDR4_BLK6_RANGE_OFFSET_NS (DDR4_BLK6_BASE_NS - DDR4_BLK0_BASE_NS)
#define MPC_DDR4_BLK7_RANGE_BASE_S (DDR4_BLK7_BASE_S)
#define MPC_DDR4_BLK7_RANGE_LIMIT_S (DDR4_BLK7_BASE_S + ((DDR4_BLK_SIZE)-1))
#define MPC_DDR4_BLK7_RANGE_OFFSET_S (DDR4_BLK7_BASE_S - DDR4_BLK0_BASE_NS)
#endif /* __PLATFORM_BASE_ADDRESS_H__ */
ports/cortex_m55/ac6/example_build/demo_secure_zone/RTE/Device/SSE-300-MPS3/region_defs.h
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/*
* Copyright (c) 2016-2022 Arm Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __REGION_DEFS_H__
#define __REGION_DEFS_H__
#include "region_limits.h"
/* **************************************************************
* WARNING: this file is parsed both by the C/C++ compiler
* and the linker. As a result the syntax must be valid not only
* for C/C++ but for the linker scripts too.
* Beware of the following limitations:
* - LD (GCC linker) requires white space around operators.
* - UL postfix for macros is not suported by the linker script
****************************************************************/
/* Secure regions */
#define S_CODE_START ( S_ROM_ALIAS )
#define S_CODE_SIZE ( TOTAL_S_ROM_SIZE )
#define S_CODE_LIMIT ( S_CODE_START + S_CODE_SIZE )
#define S_DATA_START ( S_RAM_ALIAS )
#define S_DATA_SIZE ( TOTAL_S_RAM_SIZE )
#define S_DATA_LIMIT ( S_DATA_START + S_DATA_SIZE )
#define S_DDR4_START ( S_DDR4_ALIAS )
#define S_DDR4_SIZE ( TOTAL_S_DDR4_SIZE )
#define S_DDR4_LIMIT ( S_DDR4_START + S_DDR4_SIZE )
#endif /* __REGION_DEFS_H__ */
ports/cortex_m55/ac6/example_build/demo_secure_zone/RTE/Device/SSE-300-MPS3/region_limits.h
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@@ -0,0 +1,45 @@
/*
* Copyright (c) 2018-2022 Arm Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __REGION_LIMITS_H__
#define __REGION_LIMITS_H__
/* **************************************************************
* WARNING: this file is parsed both by the C/C++ compiler
* and the linker. As a result the syntax must be valid not only
* for C/C++ but for the linker scripts too.
* Beware of the following limitations:
* - LD (GCC linker) requires white space around operators.
* - UL postfix for macros is not suported by the linker script
****************************************************************/
/* Secure Code */
#define S_ROM_ALIAS (0x10000000) /* ITCM_BASE_S */
#define TOTAL_S_ROM_SIZE (0x00080000) /* 512 kB */
/* Secure Data */
#define S_RAM_ALIAS (0x30000000) /* DTCM_BASE_S */
#define TOTAL_S_RAM_SIZE (0x00080000) /* 512 kB */
/* Secure DDR4 */
#define S_DDR4_ALIAS (0x70000000) /* DDR4_BLK1_BASE_S */
#define TOTAL_S_DDR4_SIZE (0x10000000) /* 256 MB */
/* Heap and Stack sizes for secure and nonsecure applications */
#define HEAP_SIZE (0x00000400) /* 1 KiB */
#define STACK_SIZE (0x00000400) /* 1 KiB */
#endif /* __REGION_LIMITS_H__ */
ports/cortex_m55/ac6/example_build/demo_secure_zone/RTE/Device/SSE-300-MPS3/startup_fvp_sse300_mps3.c
+344
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/*
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* This file is derivative of CMSIS V5.6.0 startup_ARMv81MML.c
* Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b
*/
#include "SSE300MPS3.h"
/*----------------------------------------------------------------------------
Exception / Interrupt Handler Function Prototype
*----------------------------------------------------------------------------*/
typedef void( *pFunc )( void );
/*----------------------------------------------------------------------------
External References
*----------------------------------------------------------------------------*/
extern uint32_t __INITIAL_SP;
extern uint32_t __STACK_LIMIT;
extern void __PROGRAM_START(void) __NO_RETURN;
/*----------------------------------------------------------------------------
Internal References
*----------------------------------------------------------------------------*/
void Reset_Handler (void) __NO_RETURN;
/*----------------------------------------------------------------------------
Exception / Interrupt Handler
*----------------------------------------------------------------------------*/
#define DEFAULT_IRQ_HANDLER(handler_name) \
void __WEAK __NO_RETURN handler_name(void); \
void handler_name(void) { \
while(1); \
}
/* Exceptions */
DEFAULT_IRQ_HANDLER(NMI_Handler)
DEFAULT_IRQ_HANDLER(HardFault_Handler)
DEFAULT_IRQ_HANDLER(MemManage_Handler)
DEFAULT_IRQ_HANDLER(BusFault_Handler)
DEFAULT_IRQ_HANDLER(UsageFault_Handler)
DEFAULT_IRQ_HANDLER(SecureFault_Handler)
DEFAULT_IRQ_HANDLER(SVC_Handler)
DEFAULT_IRQ_HANDLER(DebugMon_Handler)
DEFAULT_IRQ_HANDLER(PendSV_Handler)
DEFAULT_IRQ_HANDLER(SysTick_Handler)
DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_Handler)
DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler)
DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler)
DEFAULT_IRQ_HANDLER(TIMER0_Handler)
DEFAULT_IRQ_HANDLER(TIMER1_Handler)
DEFAULT_IRQ_HANDLER(TIMER2_Handler)
DEFAULT_IRQ_HANDLER(MPC_Handler)
DEFAULT_IRQ_HANDLER(PPC_Handler)
DEFAULT_IRQ_HANDLER(MSC_Handler)
DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler)
DEFAULT_IRQ_HANDLER(MGMT_PPU_Handler)
DEFAULT_IRQ_HANDLER(SYS_PPU_Handler)
DEFAULT_IRQ_HANDLER(CPU0_PPU_Handler)
DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler)
DEFAULT_IRQ_HANDLER(TIMER3_Handler)
DEFAULT_IRQ_HANDLER(CTI_REQ0_IRQHandler)
DEFAULT_IRQ_HANDLER(CTI_REQ1_IRQHandler)
DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler)
DEFAULT_IRQ_HANDLER(UARTRX0_Handler)
DEFAULT_IRQ_HANDLER(UARTTX0_Handler)
DEFAULT_IRQ_HANDLER(UARTRX1_Handler)
DEFAULT_IRQ_HANDLER(UARTTX1_Handler)
DEFAULT_IRQ_HANDLER(UARTRX2_Handler)
DEFAULT_IRQ_HANDLER(UARTTX2_Handler)
DEFAULT_IRQ_HANDLER(UARTRX3_Handler)
DEFAULT_IRQ_HANDLER(UARTTX3_Handler)
DEFAULT_IRQ_HANDLER(UARTRX4_Handler)
DEFAULT_IRQ_HANDLER(UARTTX4_Handler)
DEFAULT_IRQ_HANDLER(UART0_Combined_Handler)
DEFAULT_IRQ_HANDLER(UART1_Combined_Handler)
DEFAULT_IRQ_HANDLER(UART2_Combined_Handler)
DEFAULT_IRQ_HANDLER(UART3_Combined_Handler)
DEFAULT_IRQ_HANDLER(UART4_Combined_Handler)
DEFAULT_IRQ_HANDLER(UARTOVF_Handler)
DEFAULT_IRQ_HANDLER(ETHERNET_Handler)
DEFAULT_IRQ_HANDLER(I2S_Handler)
DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler)
DEFAULT_IRQ_HANDLER(USB_Handler)
DEFAULT_IRQ_HANDLER(SPI_ADC_Handler)
DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler)
DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler)
DEFAULT_IRQ_HANDLER(ETHOS_U55_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler)
DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_0_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_1_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_2_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_3_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_4_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_5_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_6_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_7_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_8_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_9_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_10_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_11_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_12_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_13_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_14_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_15_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_0_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_1_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_2_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_3_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_4_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_5_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_6_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_7_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_8_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_9_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_10_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_11_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_12_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_13_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_14_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_15_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_0_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_1_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_2_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_3_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_4_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_5_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_6_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_7_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_8_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_9_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_10_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_11_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_12_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_13_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_14_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_15_Handler)
DEFAULT_IRQ_HANDLER(GPIO3_0_Handler)
DEFAULT_IRQ_HANDLER(GPIO3_1_Handler)
DEFAULT_IRQ_HANDLER(GPIO3_2_Handler)
DEFAULT_IRQ_HANDLER(GPIO3_3_Handler)
DEFAULT_IRQ_HANDLER(UARTRX5_Handler)
DEFAULT_IRQ_HANDLER(UARTTX5_Handler)
DEFAULT_IRQ_HANDLER(UART5_Handler)
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
#if defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
extern const pFunc __VECTOR_TABLE[496];
const pFunc __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
(pFunc)(&__INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14: NMI Handler */
HardFault_Handler, /* -13: Hard Fault Handler */
MemManage_Handler, /* -12: MPU Fault Handler */
BusFault_Handler, /* -11: Bus Fault Handler */
UsageFault_Handler, /* -10: Usage Fault Handler */
SecureFault_Handler, /* -9: Secure Fault Handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* -5: SVCall Handler */
DebugMon_Handler, /* -4: Debug Monitor Handler */
0, /* Reserved */
PendSV_Handler, /* -2: PendSV Handler */
SysTick_Handler, /* -1: SysTick Handler */
NONSEC_WATCHDOG_RESET_Handler, /* 0: Non-Secure Watchdog Reset Handler */
NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */
SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */
TIMER0_Handler, /* 3: TIMER 0 Handler */
TIMER1_Handler, /* 4: TIMER 1 Handler */
TIMER2_Handler, /* 5: TIMER 2 Handler */
0, /* 6: Reserved */
0, /* 7: Reserved */
0, /* 8: Reserved */
MPC_Handler, /* 9: MPC Combined (Secure) Handler */
PPC_Handler, /* 10: PPC Combined (Secure) Handler */
MSC_Handler, /* 11: MSC Combined (Secure) Handler */
BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */
0, /* 13: Reserved */
MGMT_PPU_Handler, /* 14: MGMT PPU Handler */
SYS_PPU_Handler, /* 15: SYS PPU Handler */
CPU0_PPU_Handler, /* 16: CPU0 PPU Handler */
0, /* 17: Reserved */
0, /* 18: Reserved */
0, /* 19: Reserved */
0, /* 20: Reserved */
0, /* 21: Reserved */
0, /* 22: Reserved */
0, /* 23: Reserved */
0, /* 24: Reserved */
0, /* 25: Reserved */
DEBUG_PPU_Handler, /* 26: DEBUG PPU Handler */
TIMER3_Handler, /* 27: TIMER 3 Handler */
CTI_REQ0_IRQHandler, /* 28: CTI request 0 IRQ Handler */
CTI_REQ1_IRQHandler, /* 29: CTI request 1 IRQ Handler */
0, /* 30: Reserved */
0, /* 31: Reserved */
/* External interrupts */
System_Timestamp_Counter_Handler, /* 32: System timestamp counter Handler */
UARTRX0_Handler, /* 33: UART 0 RX Handler */
UARTTX0_Handler, /* 34: UART 0 TX Handler */
UARTRX1_Handler, /* 35: UART 1 RX Handler */
UARTTX1_Handler, /* 36: UART 1 TX Handler */
UARTRX2_Handler, /* 37: UART 2 RX Handler */
UARTTX2_Handler, /* 38: UART 2 TX Handler */
UARTRX3_Handler, /* 39: UART 3 RX Handler */
UARTTX3_Handler, /* 40: UART 3 TX Handler */
UARTRX4_Handler, /* 41: UART 4 RX Handler */
UARTTX4_Handler, /* 42: UART 4 TX Handler */
UART0_Combined_Handler, /* 43: UART 0 Combined Handler */
UART1_Combined_Handler, /* 44: UART 1 Combined Handler */
UART2_Combined_Handler, /* 45: UART 2 Combined Handler */
UART3_Combined_Handler, /* 46: UART 3 Combined Handler */
UART4_Combined_Handler, /* 47: UART 4 Combined Handler */
UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */
ETHERNET_Handler, /* 49: Ethernet Handler */
I2S_Handler, /* 50: Audio I2S Handler */
TOUCH_SCREEN_Handler, /* 51: Touch Screen Handler */
USB_Handler, /* 52: USB Handler */
SPI_ADC_Handler, /* 53: SPI ADC Handler */
SPI_SHIELD0_Handler, /* 54: SPI (Shield 0) Handler */
SPI_SHIELD1_Handler, /* 55: SPI (Shield 0) Handler */
ETHOS_U55_Handler, /* 56: Ethos-U55 Handler */
0, /* 57: Reserved */
0, /* 58: Reserved */
0, /* 59: Reserved */
0, /* 60: Reserved */
0, /* 61: Reserved */
0, /* 62: Reserved */
0, /* 63: Reserved */
0, /* 64: Reserved */
0, /* 65: Reserved */
0, /* 66: Reserved */
0, /* 67: Reserved */
0, /* 68: Reserved */
GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */
GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */
GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */
GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */
GPIO0_0_Handler, /* 73: GPIO0 Pin 0 Handler */
GPIO0_1_Handler, /* 74: GPIO0 Pin 1 Handler */
GPIO0_2_Handler, /* 75: GPIO0 Pin 2 Handler */
GPIO0_3_Handler, /* 76: GPIO0 Pin 3 Handler */
GPIO0_4_Handler, /* 77: GPIO0 Pin 4 Handler */
GPIO0_5_Handler, /* 78: GPIO0 Pin 5 Handler */
GPIO0_6_Handler, /* 79: GPIO0 Pin 6 Handler */
GPIO0_7_Handler, /* 80: GPIO0 Pin 7 Handler */
GPIO0_8_Handler, /* 81: GPIO0 Pin 8 Handler */
GPIO0_9_Handler, /* 82: GPIO0 Pin 9 Handler */
GPIO0_10_Handler, /* 83: GPIO0 Pin 10 Handler */
GPIO0_11_Handler, /* 84: GPIO0 Pin 11 Handler */
GPIO0_12_Handler, /* 85: GPIO0 Pin 12 Handler */
GPIO0_13_Handler, /* 86: GPIO0 Pin 13 Handler */
GPIO0_14_Handler, /* 87: GPIO0 Pin 14 Handler */
GPIO0_15_Handler, /* 88: GPIO0 Pin 15 Handler */
GPIO1_0_Handler, /* 89: GPIO1 Pin 0 Handler */
GPIO1_1_Handler, /* 90: GPIO1 Pin 1 Handler */
GPIO1_2_Handler, /* 91: GPIO1 Pin 2 Handler */
GPIO1_3_Handler, /* 92: GPIO1 Pin 3 Handler */
GPIO1_4_Handler, /* 93: GPIO1 Pin 4 Handler */
GPIO1_5_Handler, /* 94: GPIO1 Pin 5 Handler */
GPIO1_6_Handler, /* 95: GPIO1 Pin 6 Handler */
GPIO1_7_Handler, /* 96: GPIO1 Pin 7 Handler */
GPIO1_8_Handler, /* 97: GPIO1 Pin 8 Handler */
GPIO1_9_Handler, /* 98: GPIO1 Pin 9 Handler */
GPIO1_10_Handler, /* 99: GPIO1 Pin 10 Handler */
GPIO1_11_Handler, /* 100: GPIO1 Pin 11 Handler */
GPIO1_12_Handler, /* 101: GPIO1 Pin 12 Handler */
GPIO1_13_Handler, /* 102: GPIO1 Pin 13 Handler */
GPIO1_14_Handler, /* 103: GPIO1 Pin 14 Handler */
GPIO1_15_Handler, /* 104: GPIO1 Pin 15 Handler */
GPIO2_0_Handler, /* 105: GPIO2 Pin 0 Handler */
GPIO2_1_Handler, /* 106: GPIO2 Pin 1 Handler */
GPIO2_2_Handler, /* 107: GPIO2 Pin 2 Handler */
GPIO2_3_Handler, /* 108: GPIO2 Pin 3 Handler */
GPIO2_4_Handler, /* 109: GPIO2 Pin 4 Handler */
GPIO2_5_Handler, /* 110: GPIO2 Pin 5 Handler */
GPIO2_6_Handler, /* 111: GPIO2 Pin 6 Handler */
GPIO2_7_Handler, /* 112: GPIO2 Pin 7 Handler */
GPIO2_8_Handler, /* 113: GPIO2 Pin 8 Handler */
GPIO2_9_Handler, /* 114: GPIO2 Pin 9 Handler */
GPIO2_10_Handler, /* 115: GPIO2 Pin 10 Handler */
GPIO2_11_Handler, /* 116: GPIO2 Pin 11 Handler */
GPIO2_12_Handler, /* 117: GPIO2 Pin 12 Handler */
GPIO2_13_Handler, /* 118: GPIO2 Pin 13 Handler */
GPIO2_14_Handler, /* 119: GPIO2 Pin 14 Handler */
GPIO2_15_Handler, /* 120: GPIO2 Pin 15 Handler */
GPIO3_0_Handler, /* 121: GPIO3 Pin 0 Handler */
GPIO3_1_Handler, /* 122: GPIO3 Pin 1 Handler */
GPIO3_2_Handler, /* 123: GPIO3 Pin 2 Handler */
GPIO3_3_Handler, /* 124: GPIO3 Pin 3 Handler */
UARTRX5_Handler, /* 125: UART 5 RX Interrupt */
UARTTX5_Handler, /* 126: UART 5 TX Interrupt */
UART5_Handler, /* 127: UART 5 combined Interrupt */
0, /* 128: Reserved */
0, /* 129: Reserved */
0, /* 130: Reserved */
};
#if defined ( __GNUC__ )
#pragma GCC diagnostic pop
#endif
/*----------------------------------------------------------------------------
Reset Handler called on controller reset
*----------------------------------------------------------------------------*/
void Reset_Handler(void)
{
__set_MSPLIM((uint32_t)(&__STACK_LIMIT));
SystemInit(); /* CMSIS System Initialization */
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
}
ports/cortex_m55/ac6/example_build/demo_secure_zone/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c
+186
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@@ -0,0 +1,186 @@
/*
* Copyright (c) 2009-2022 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* This file is derivative of CMSIS V5.6.0 system_ARMv81MML.c
* Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b
*/
#include "SSE300MPS3.h"
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#include "partition_CS300.h"
#endif
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define XTAL (32000000UL)
#define SYSTEM_CLOCK (XTAL)
#define PERIPHERAL_CLOCK (25000000UL)
/*----------------------------------------------------------------------------
Externals
*----------------------------------------------------------------------------*/
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
extern uint32_t __VECTOR_TABLE;
#endif
/*****************************************************************/
/*------------------- Memory Protection Controller -----------------------------*/
typedef struct
{
__IOM uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */
uint32_t RESERVED0[3];
__IM uint32_t BLK_MAX; /* Offset: 0x010 (R/ ) Block Maximum Register */
__IM uint32_t BLK_CFG; /* Offset: 0x014 (R/ ) Block Configuration Register */
__IOM uint32_t BLK_IDX; /* Offset: 0x018 (R/W) Block Index Register */
__IOM uint32_t BLK_LUT; /* Offset: 0x01C (R/W) Block Lookup Tabe Register */
__IM uint32_t INT_STAT; /* Offset: 0x020 (R/ ) Interrupt Status Register */
__OM uint32_t INT_CLEAR; /* Offset: 0x024 ( /W) Interrupt Clear Register */
__IOM uint32_t INT_EN; /* Offset: 0x028 (R/W) Interrupt Enable Register */
__IM uint32_t INT_INFO1; /* Offset: 0x02C (R/ ) Interrupt Info1 Register */
__IM uint32_t INT_INFO2; /* Offset: 0x030 (R/ ) Interrupt Info2 Register */
__OM uint32_t INT_SET; /* Offset: 0x034 ( /W) Interrupt Set Register */
} MPC_TypeDef;
#define MPC_SRAM ((MPC_TypeDef *) MPC_SRAM_BASE_S )
#define MPC_ISRAM0 ((MPC_TypeDef *) MPC_ISRAM0_BASE_S )
/*------------------- Secure Privilege Control Block -----------------------------*/
typedef struct
{
uint32_t RESERVED0[5U];
__IOM uint32_t NSCCFG; /* Offset: 0x014 (R/W) Non Secure Callable Configuration for IDAU */
} SAC_TypeDef;
#define SAC ((SAC_TypeDef *) SSE300_SACFG_BASE_S )
/*------------------- TCM Gating Unit --------------------------------------------*/
typedef struct /* see "Arm Cortex-Mxx Technical Reference Manual r0p1"
" */
{
__IOM uint32_t CTRL; /* Offset: 0x000 (R/W) Gate Control Register */
__IM uint32_t CFG; /* Offset: 0x004 (R/ ) Gate Configuration Register */
uint32_t RESERVED0[2];
__IOM uint32_t LUT[16]; /* Offset: 0x010 (R/W) Gate Look-up Table Register */
} TGU_TypeDef;
#define ITGU_BASE (0xE001E500UL) /* ITCM Gating Unit */
#define DTGU_BASE (0xE001E600UL) /* DTCM Gating Unit */
#define ITGU ((TGU_TypeDef *) ITGU_BASE)
#define DTGU ((TGU_TypeDef *) DTGU_BASE)
/*****************************************************************/
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK;
uint32_t PeripheralClock = PERIPHERAL_CLOCK;
/*----------------------------------------------------------------------------
System Core Clock update function
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
PeripheralClock = PERIPHERAL_CLOCK;
}
/*----------------------------------------------------------------------------
System initialization function
*----------------------------------------------------------------------------*/
void SystemInit (void)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
SCB->VTOR = (uint32_t)(&__VECTOR_TABLE);
#endif
#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \
(defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U))
SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
(3U << 11U*2U) ); /* enable CP11 Full Access */
/* Set low-power state for PDEPU */
/* 0b00 | ON, PDEPU is not in low-power state */
/* 0b01 | ON, but the clock is off */
/* 0b10 | RET(ention) */
/* 0b11 | OFF */
/* Clear ELPSTATE, value is 0b11 on Cold reset */
PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk);
/* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */
/* PDEPU ON, Clock OFF */
PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos;
#endif
#ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif
/* Enable Loop and branch info cache */
SCB->CCR |= SCB_CCR_LOB_Msk;
__DSB();
__ISB();
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/* Enable BusFault, UsageFault, MemManageFault and SecureFault to ease diagnostic */
SCB->SHCSR |= (SCB_SHCSR_USGFAULTENA_Msk |
SCB_SHCSR_BUSFAULTENA_Msk |
SCB_SHCSR_MEMFAULTENA_Msk |
SCB_SHCSR_SECUREFAULTENA_Msk);
/* BFSR register setting to enable precise errors */
SCB->CFSR |= SCB_CFSR_PRECISERR_Msk;
/* configure unsecure code area: ITCM 512K 0x00080000 - 0x00100000 */
// blk_cfg = ITGU->CFG & 0xF; /* = 0x7 */
// blk_size = 1UL << (blk_cfg + 5U); /* = 0x1000 (4K) */
ITGU->LUT[4] = 0xFFFFFFFF;
ITGU->LUT[5] = 0xFFFFFFFF;
ITGU->LUT[6] = 0xFFFFFFFF;
ITGU->LUT[7] = 0xFFFFFFFF;
/* configure unsecure data area: DTCM 512K 0x20080000 - 0x20100000 */
// blk_cfg = DTGU->CFG & 0xF; /* = 0x7 */
// blk_size = 1UL << (blk_cfg + 5U); /* = 0x1000 (4K) */
DTGU->LUT[4] = 0xFFFFFFFF;
DTGU->LUT[5] = 0xFFFFFFFF;
DTGU->LUT[6] = 0xFFFFFFFF;
DTGU->LUT[7] = 0xFFFFFFFF;
/* Non Secure Callable Configuration for IDAU (NSCCFG register) */
SAC->NSCCFG |= 1U; /* Configure CODE region (0x1000_0000 to 0x1FFF_FFFF) Non-secure Callable */
//SAC->NSCCFG |= 2U; /* Configure RAM region (0x3000_0000 to 0x3FFF_FFFF) Non-secure Callable */
TZ_SAU_Setup();
#endif
SystemCoreClock = SYSTEM_CLOCK;
}
ports/cortex_m55/ac6/example_build/demo_secure_zone/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.h
+48
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@@ -0,0 +1,48 @@
/*
* Copyright (c) 2009-2020 Arm Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* This file is derivative of CMSIS V5.6.0 system_ARMv81MML.h
* Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b
*/
#ifndef __SYSTEM_CORE_INIT_H__
#define __SYSTEM_CORE_INIT_H__
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern uint32_t PeripheralClock; /*!< Peripheral Clock Frequency */
/**
* \brief Initializes the system
*/
extern void SystemInit(void);
/**
* \brief Restores system core clock
*/
extern void SystemCoreClockUpdate(void);
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_CORE_INIT_H__ */
ports/cortex_m55/ac6/example_build/demo_secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h
+21
View File
@@ -0,0 +1,21 @@
/*
* Auto generated Run-Time-Environment Configuration File
* *** Do not modify ! ***
*
* Project: 'demo_secure_zone'
* Target: 'FVP Simulation Model'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
/*
* Define the Device Header File:
*/
#define CMSIS_device_header "SSE300MPS3.h"
#endif /* RTE_COMPONENTS_H */
ports/cortex_m55/ac6/example_build/demo_secure_zone/demo_secure_zone.uvoptx
+366
View File
@@ -0,0 +1,366 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>FVP Simulation Model</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\Listings\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>7</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
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<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
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<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>15</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile>..\Debug.ini</tIfile>
<pMon>BIN\DbgFMv8M.DLL</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2V8M</Key>
<Name>UL2V8M(-S0 -C0 -P0 -FC1000 -FD01000000</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DbgFMv8M</Key>
<Name>-I -S"System Generator:cpu_core" -L"cpu0" -O4102 -C0 -MC"$K\ARM\VHT\VHT_MPS3_Corstone_SSE-300.exe" -MF"..\CS300_config.txt" -PF -MA</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGTARM</Key>
<Name>(6010=-1,-1,-1,-1,0)(6018=-1,-1,-1,-1,0)(6019=-1,-1,-1,-1,0)(6008=-1,-1,-1,-1,0)(6009=-1,-1,-1,-1,0)(6014=4619,189,4877,920,0)(6015=3743,140,4001,762,0)(6003=-1,-1,-1,-1,0)(6000=4424,206,4877,538,0)(6020=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMDBGFLAGS</Key>
<Name></Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGUARM</Key>
<Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint>
<Bp>
<Number>0</Number>
<Type>0</Type>
<LineNumber>48</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>268439734</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>1</BreakIfRCount>
<Filename>&lt;1&gt;.\main_s.c</Filename>
<ExecCommand></ExecCommand>
<Expression>\\secure_app\main_s.c\48</Expression>
</Bp>
</Breakpoint>
<WatchWindow1>
<Ww>
<count>0</count>
<WinNumber>1</WinNumber>
<ItemText>thread_0_counter</ItemText>
</Ww>
<Ww>
<count>1</count>
<WinNumber>1</WinNumber>
<ItemText>thread_1_counter</ItemText>
</Ww>
<Ww>
<count>2</count>
<WinNumber>1</WinNumber>
<ItemText>thread_2_counter</ItemText>
</Ww>
<Ww>
<count>3</count>
<WinNumber>1</WinNumber>
<ItemText>thread_3_counter</ItemText>
</Ww>
<Ww>
<count>4</count>
<WinNumber>1</WinNumber>
<ItemText>thread_4_counter</ItemText>
</Ww>
<Ww>
<count>5</count>
<WinNumber>1</WinNumber>
<ItemText>thread_5_counter</ItemText>
</Ww>
<Ww>
<count>6</count>
<WinNumber>1</WinNumber>
<ItemText>thread_6_counter</ItemText>
</Ww>
<Ww>
<count>7</count>
<WinNumber>1</WinNumber>
<ItemText>thread_7_counter</ItemText>
</Ww>
</WatchWindow1>
<MemoryWindow1>
<Mm>
<WinNumber>1</WinNumber>
<SubType>2</SubType>
<ItemText>0x01000400</ItemText>
<AccSizeX>0</AccSizeX>
</Mm>
</MemoryWindow1>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>0</periodic>
<aLwin>1</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>1</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>0</bLintAuto>
<bAutoGenD>0</bAutoGenD>
<LntExFlags>0</LntExFlags>
<pMisraName></pMisraName>
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
<DebugDescription>
<Enable>1</Enable>
<EnableFlashSeq>1</EnableFlashSeq>
<EnableLog>0</EnableLog>
<Protocol>2</Protocol>
<DbgClock>10000000</DbgClock>
</DebugDescription>
</TargetOption>
</Target>
<Group>
<GroupName>Secure Code</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>1</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\main_s.c</PathWithFileName>
<FilenameWithoutPath>main_s.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>2</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\src\tx_thread_secure_stack.c</PathWithFileName>
<FilenameWithoutPath>tx_thread_secure_stack.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>3</FileNumber>
<FileType>2</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\src\tx_thread_interrupt_disable.S</PathWithFileName>
<FilenameWithoutPath>tx_thread_interrupt_disable.S</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>4</FileNumber>
<FileType>2</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\src\tx_thread_interrupt_restore.S</PathWithFileName>
<FilenameWithoutPath>tx_thread_interrupt_restore.S</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>Interface</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>5</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\interface.c</PathWithFileName>
<FilenameWithoutPath>interface.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>::CMSIS</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>1</RteFlg>
</Group>
<Group>
<GroupName>::Device</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>1</RteFlg>
</Group>
<Group>
<GroupName>::Native Driver</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>1</RteFlg>
</Group>
</ProjectOpt>
ports/cortex_m55/ac6/example_build/demo_secure_zone/demo_secure_zone.uvprojx
+580
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File diff suppressed because it is too large Load Diff
ports/cortex_m55/ac6/example_build/demo_secure_zone/interface.c
+49
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@@ -0,0 +1,49 @@
/*
* Copyright (c) 2013-2016 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* ----------------------------------------------------------------------
*
* interface.c Secure/non-secure callable application code
*
* Version 1.0
* Initial Release
*---------------------------------------------------------------------------*/
#include <arm_cmse.h> // CMSE definitions
#include "interface.h" // Header file with secure interface API
/* typedef for non-secure callback functions */
typedef funcptr funcptr_NS __attribute__((cmse_nonsecure_call));
/* Non-secure callable (entry) function */
int func1(int x) __attribute__((cmse_nonsecure_entry)) {
return x+3;
}
/* Non-secure callable (entry) function, calling a non-secure callback function */
int func2(funcptr callback, int x) __attribute__((cmse_nonsecure_entry)) {
funcptr_NS callback_NS; // non-secure callback function pointer
int y;
/* return function pointer with cleared LSB */
callback_NS = (funcptr_NS)cmse_nsfptr_create(callback);
y = callback_NS (x+1);
return (y+2);
}
ports/cortex_m55/ac6/example_build/demo_secure_zone/interface.h
+31
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@@ -0,0 +1,31 @@
/*
* Copyright (c) 2013-2016 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* ----------------------------------------------------------------------
*
* interface.h API definition for the non-secure state
*
* Version 1.0
* Initial Release
*---------------------------------------------------------------------------*/
/* Function pointer declaration */
typedef int (*funcptr)(int);
/* Non-secure callable functions */
extern int func1(int x);
extern int func2(funcptr callback, int x);
ports/cortex_m55/ac6/example_build/demo_secure_zone/main_s.c
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/*
* Copyright (c) 2013-2016 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* ----------------------------------------------------------------------
*
* $Date: 15. October 2016
* $Revision: 1.1.0
*
* Project: TrustZone for ARMv8-M
* Title: Code template for secure main function
*
*---------------------------------------------------------------------------*/
#include "region_limits.h"
#include "RTE_Components.h"
#include CMSIS_device_header
/* TZ_START_NS: Start address of non-secure application */
#ifndef TZ_START_NS
#define TZ_START_NS 0x00080000U
#endif
/* typedef for non-secure callback functions */
typedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call));
/* Secure main() */
int main(void) {
funcptr_void NonSecure_ResetHandler;
/* Add user setup code for secure part here*/
/* Set non-secure main stack (MSP_NS) */
__TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS)));
/* Get non-secure reset handler */
NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U)));
/* Start non-secure state software application */
NonSecure_ResetHandler();
/* Non-secure software does not return, this code is not executed */
while (1) {
__NOP();
}
}
ports/cortex_m55/ac6/example_build/demo_secure_zone/tz_context.c
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/*
* Copyright (c) 2015-2016 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* ----------------------------------------------------------------------------
*
* $Date: 15. October 2016
* $Revision: 1.1.0
*
* Project: TrustZone for ARMv8-M
* Title: Context Management for ARMv8-M TrustZone - Sample implementation
*
*---------------------------------------------------------------------------*/
#include "RTE_Components.h"
#include CMSIS_device_header
#include "tz_context.h"
/// Number of process slots (threads may call secure library code)
#ifndef TZ_PROCESS_STACK_SLOTS
#define TZ_PROCESS_STACK_SLOTS 8U
#endif
/// Stack size of the secure library code
#ifndef TZ_PROCESS_STACK_SIZE
#define TZ_PROCESS_STACK_SIZE 256U
#endif
typedef struct {
uint32_t sp_top; // stack space top
uint32_t sp_limit; // stack space limit
uint32_t sp; // current stack pointer
} stack_info_t;
static stack_info_t ProcessStackInfo [TZ_PROCESS_STACK_SLOTS];
static uint64_t ProcessStackMemory[TZ_PROCESS_STACK_SLOTS][TZ_PROCESS_STACK_SIZE/8U];
static uint32_t ProcessStackFreeSlot = 0xFFFFFFFFU;
/// Initialize secure context memory system
/// \return execution status (1: success, 0: error)
__attribute__((cmse_nonsecure_entry))
uint32_t TZ_InitContextSystem_S (void) {
uint32_t n;
if (__get_IPSR() == 0U) {
return 0U; // Thread Mode
}
for (n = 0U; n < TZ_PROCESS_STACK_SLOTS; n++) {
ProcessStackInfo[n].sp = 0U;
ProcessStackInfo[n].sp_limit = (uint32_t)&ProcessStackMemory[n];
ProcessStackInfo[n].sp_top = (uint32_t)&ProcessStackMemory[n] + TZ_PROCESS_STACK_SIZE;
*((uint32_t *)ProcessStackMemory[n]) = n + 1U;
}
*((uint32_t *)ProcessStackMemory[--n]) = 0xFFFFFFFFU;
ProcessStackFreeSlot = 0U;
// Default process stack pointer and stack limit
__set_PSPLIM((uint32_t)ProcessStackMemory);
__set_PSP ((uint32_t)ProcessStackMemory);
// Privileged Thread Mode using PSP
__set_CONTROL(0x02U);
return 1U; // Success
}
/// Allocate context memory for calling secure software modules in TrustZone
/// \param[in] module identifies software modules called from non-secure mode
/// \return value != 0 id TrustZone memory slot identifier
/// \return value 0 no memory available or internal error
__attribute__((cmse_nonsecure_entry))
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module) {
uint32_t slot;
(void)module; // Ignore (fixed Stack size)
if (__get_IPSR() == 0U) {
return 0U; // Thread Mode
}
if (ProcessStackFreeSlot == 0xFFFFFFFFU) {
return 0U; // No slot available
}
slot = ProcessStackFreeSlot;
ProcessStackFreeSlot = *((uint32_t *)ProcessStackMemory[slot]);
ProcessStackInfo[slot].sp = ProcessStackInfo[slot].sp_top;
return (slot + 1U);
}
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
__attribute__((cmse_nonsecure_entry))
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id) {
uint32_t slot;
if (__get_IPSR() == 0U) {
return 0U; // Thread Mode
}
if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
return 0U; // Invalid ID
}
slot = id - 1U;
if (ProcessStackInfo[slot].sp == 0U) {
return 0U; // Inactive slot
}
ProcessStackInfo[slot].sp = 0U;
*((uint32_t *)ProcessStackMemory[slot]) = ProcessStackFreeSlot;
ProcessStackFreeSlot = slot;
return 1U; // Success
}
/// Load secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
__attribute__((cmse_nonsecure_entry))
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id) {
uint32_t slot;
if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) {
return 0U; // Thread Mode or using Main Stack for threads
}
if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
return 0U; // Invalid ID
}
slot = id - 1U;
if (ProcessStackInfo[slot].sp == 0U) {
return 0U; // Inactive slot
}
// Setup process stack pointer and stack limit
__set_PSPLIM(ProcessStackInfo[slot].sp_limit);
__set_PSP (ProcessStackInfo[slot].sp);
return 1U; // Success
}
/// Store secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
__attribute__((cmse_nonsecure_entry))
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id) {
uint32_t slot;
uint32_t sp;
if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) {
return 0U; // Thread Mode or using Main Stack for threads
}
if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
return 0U; // Invalid ID
}
slot = id - 1U;
if (ProcessStackInfo[slot].sp == 0U) {
return 0U; // Inactive slot
}
sp = __get_PSP();
if ((sp < ProcessStackInfo[slot].sp_limit) ||
(sp > ProcessStackInfo[slot].sp_top)) {
return 0U; // SP out of range
}
ProcessStackInfo[slot].sp = sp;
// Default process stack pointer and stack limit
__set_PSPLIM((uint32_t)ProcessStackMemory);
__set_PSP ((uint32_t)ProcessStackMemory);
return 1U; // Success
}
ports/cortex_m55/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/SSE-300-MPS3/RTE_Device.h
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/*
* Copyright (c) 2019-2022 Arm Limited. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __RTE_DEVICE_H
#define __RTE_DEVICE_H
// <q> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0]
// <i> Configuration settings for Driver_USART0 in component ::Drivers:USART
#define RTE_USART0 1
// <q> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1]
// <i> Configuration settings for Driver_USART1 in component ::Drivers:USART
#define RTE_USART1 1
// <q> MPC (Memory Protection Controller) [Driver_ISRAM0_MPC]
// <i> Configuration settings for Driver_ISRAM0_MPC in component ::Drivers:MPC
#define RTE_ISRAM0_MPC 1
// <q> MPC (Memory Protection Controller) [Driver_ISRAM1_MPC]
// <i> Configuration settings for Driver_ISRAM1_MPC in component ::Drivers:MPC
#define RTE_ISRAM1_MPC 1
// <q> MPC (Memory Protection Controller) [Driver_SRAM_MPC]
// <i> Configuration settings for Driver_SRAM_MPC in component ::Drivers:MPC
#define RTE_SRAM_MPC 1
// <q> MPC (Memory Protection Controller) [Driver_QSPI_MPC]
// <i> Configuration settings for Driver_QSPI_MPC in component ::Drivers:MPC
#define RTE_QSPI_MPC 1
// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN0]
// <i> Configuration settings for Driver_PPC_SSE300_MAIN0 in component ::Drivers:PPC
#define RTE_PPC_SSE300_MAIN0 1
// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP0]
// <i> Configuration settings for Driver_PPC_SSE300_MAIN_EXP0 in component ::Drivers:PPC
#define RTE_PPC_SSE300_MAIN_EXP0 1
// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP1]
// <i> Configuration settings for Driver_PPC_SSE300_MAIN_EXP1 in component ::Drivers:PPC
#define RTE_PPC_SSE300_MAIN_EXP1 1
// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH0]
// <i> Configuration settings for Driver_PPC_SSE300_PERIPH0 in component ::Drivers:PPC
#define RTE_PPC_SSE300_PERIPH0 1
// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH1]
// <i> Configuration settings for Driver_PPC_SSE300_PERIPH1 in component ::Drivers:PPC
#define RTE_PPC_SSE300_PERIPH1 1
// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP0]
// <i> Configuration settings for Driver_PPC_SSE300_PERIPH_EXP0 in component ::Drivers:PPC
#define RTE_PPC_SSE300_PERIPH_EXP0 1
// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP1]
// <i> Configuration settings for Driver_PPC_SSE300_PERIPH_EXP1 in component ::Drivers:PPC
#define RTE_PPC_SSE300_PERIPH_EXP1 1
// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP2]
// <i> Configuration settings for Driver_PPC_SSE300_PERIPH_EXP2 in component ::Drivers:PPC
#define RTE_PPC_SSE300_PERIPH_EXP2 1
// <q> Flash device emulated by SRAM [Driver_Flash0]
// <i> Configuration settings for Driver_Flash0 in component ::Drivers:Flash
#define RTE_FLASH0 1
// <q> I2C SBCon [Driver_I2C0]
// <i> Configuration settings for Driver_I2C0 in component ::Drivers:I2C
#define RTE_I2C0 1
#endif /* __RTE_DEVICE_H */
ports/cortex_m55/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h
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/*
* Copyright (c) 2019-2022 Arm Limited. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_DRIVER_CONFIG_H__
#define __CMSIS_DRIVER_CONFIG_H__
#include "system_SSE300MPS3.h"
#include "device_cfg.h"
#include "device_definition.h"
#include "platform_base_address.h"
#endif /* __CMSIS_DRIVER_CONFIG_H__ */
ports/cortex_m55/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/SSE-300-MPS3/device_cfg.h
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/*
* Copyright (c) 2020-2022 Arm Limited. All rights reserved.
*
* Licensed under the Apache License Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing software
* distributed under the License is distributed on an "AS IS" BASIS
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __DEVICE_CFG_H__
#define __DEVICE_CFG_H__
/**
* \file device_cfg.h
* \brief Configuration file native driver re-targeting
*
* \details This file can be used to add native driver specific macro
* definitions to select which peripherals are available in the build.
*
* This is a default device configuration file with all peripherals enabled.
*/
/* Secure only peripheral configuration */
/* ARM MPS3 IO SCC */
#define MPS3_IO_S
#define MPS3_IO_DEV MPS3_IO_DEV_S
/* I2C_SBCon */
#define I2C0_SBCON_S
#define I2C0_SBCON_DEV I2C0_SBCON_DEV_S
/* I2S */
#define MPS3_I2S_S
#define MPS3_I2S_DEV MPS3_I2S_DEV_S
/* ARM UART Controller PL011 */
#define UART0_CMSDK_S
#define UART0_CMSDK_DEV UART0_CMSDK_DEV_S
#define UART1_CMSDK_S
#define UART1_CMSDK_DEV UART1_CMSDK_DEV_S
#define DEFAULT_UART_BAUDRATE 115200U
/* To be used as CODE and DATA sram */
#define MPC_ISRAM0_S
#define MPC_ISRAM0_DEV MPC_ISRAM0_DEV_S
#define MPC_ISRAM1_S
#define MPC_ISRAM1_DEV MPC_ISRAM0_DEV_S
#define MPC_SRAM_S
#define MPC_SRAM_DEV MPC_SRAM_DEV_S
#define MPC_QSPI_S
#define MPC_QSPI_DEV MPC_QSPI_DEV_S
/** System Counter Armv8-M */
#define SYSCOUNTER_CNTRL_ARMV8_M_S
#define SYSCOUNTER_CNTRL_ARMV8_M_DEV SYSCOUNTER_CNTRL_ARMV8_M_DEV_S
#define SYSCOUNTER_READ_ARMV8_M_S
#define SYSCOUNTER_READ_ARMV8_M_DEV SYSCOUNTER_READ_ARMV8_M_DEV_S
/**
* Arbitrary scaling values for test purposes
*/
#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT 1u
#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT 0u
#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT 1u
#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 0u
/* System timer */
#define SYSTIMER0_ARMV8_M_S
#define SYSTIMER0_ARMV8_M_DEV SYSTIMER0_ARMV8_M_DEV_S
#define SYSTIMER1_ARMV8_M_S
#define SYSTIMER1_ARMV8_M_DEV SYSTIMER1_ARMV8_M_DEV_S
#define SYSTIMER2_ARMV8_M_S
#define SYSTIMER2_ARMV8_M_DEV SYSTIMER2_ARMV8_M_DEV_S
#define SYSTIMER3_ARMV8_M_S
#define SYSTIMER3_ARMV8_M_DEV SYSTIMER3_ARMV8_M_DEV_S
#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ (25000000ul)
#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ (25000000ul)
#define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ (25000000ul)
#define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ (25000000ul)
/* CMSDK GPIO driver structures */
#define GPIO0_CMSDK_S
#define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S
#define GPIO1_CMSDK_S
#define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S
#define GPIO2_CMSDK_S
#define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S
#define GPIO3_CMSDK_S
#define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S
/* System Watchdogs */
#define SYSWDOG_ARMV8_M_S
#define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S
/* ARM MPC SIE 300 driver structures */
#define MPC_VM0_S
#define MPC_VM0_DEV MPC_VM0_DEV_S
#define MPC_VM1_S
#define MPC_VM1_DEV MPC_VM1_DEV_S
#define MPC_SSRAM2_S
#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S
#define MPC_SSRAM3_S
#define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S
/* ARM PPC driver structures */
#define PPC_SSE300_MAIN0_S
#define PPC_SSE300_MAIN0_DEV PPC_SSE300_MAIN0_DEV_S
#define PPC_SSE300_MAIN_EXP0_S
#define PPC_SSE300_MAIN_EXP0_DEV PPC_SSE300_MAIN_EXP0_DEV_S
#define PPC_SSE300_MAIN_EXP1_S
#define PPC_SSE300_MAIN_EXP1_DEV PPC_SSE300_MAIN_EXP1_DEV_S
#define PPC_SSE300_MAIN_EXP2_S
#define PPC_SSE300_MAIN_EXP2_DEV PPC_SSE300_MAIN_EXP2_DEV_S
#define PPC_SSE300_MAIN_EXP3_S
#define PPC_SSE300_MAIN_EXP3_DEV PPC_SSE300_MAIN_EXP3_DEV_S
#define PPC_SSE300_PERIPH0_S
#define PPC_SSE300_PERIPH0_DEV PPC_SSE300_PERIPH0_DEV_S
#define PPC_SSE300_PERIPH1_S
#define PPC_SSE300_PERIPH1_DEV PPC_SSE300_PERIPH1_DEV_S
#define PPC_SSE300_PERIPH_EXP0_S
#define PPC_SSE300_PERIPH_EXP0_DEV PPC_SSE300_PERIPH_EXP0_DEV_S
#define PPC_SSE300_PERIPH_EXP1_S
#define PPC_SSE300_PERIPH_EXP1_DEV PPC_SSE300_PERIPH_EXP1_DEV_S
#define PPC_SSE300_PERIPH_EXP2_S
#define PPC_SSE300_PERIPH_EXP2_DEV PPC_SSE300_PERIPH_EXP2_DEV_S
#define PPC_SSE300_PERIPH_EXP3_S
#define PPC_SSE300_PERIPH_EXP3_DEV PPC_SSE300_PERIPH_EXP3_DEV_S
/* ARM SPI PL022 */
/* Invalid device stubs are not defined */
#define DEFAULT_SPI_SPEED_HZ 4000000U /* 4MHz */
#define SPI1_PL022_S
#define SPI1_PL022_DEV SPI1_PL022_DEV_S
#endif /* __DEVICE_CFG_H__ */
ports/cortex_m55/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct
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#! armclang --target=arm-arm-none-eabi -march=armv8.1-m.main -E -xc
;/*
; * Copyright (c) 2018-2021 Arm Limited. All rights reserved.
; *
; * Licensed under the Apache License, Version 2.0 (the "License");
; * you may not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * http://www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an "AS IS" BASIS,
; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; *
; */
#include "region_defs.h"
LR_CODE S_CODE_START {
ER_CODE S_CODE_START {
*.o (RESET +First)
.ANY (+RO)
}
/*
* Place the CMSE Veneers (containing the SG instruction) after the code, in
* a separate 32 bytes aligned region so that the SAU can programmed to just
* set this region as Non-Secure Callable. The maximum size of this
* executable region makes it only used the space left over by the ER_CODE
* region so that you can rely on code+veneer size combined will not exceed
* the S_CODE_SIZE value. We also substract from the available space the
* area used to align this section on 32 bytes boundary (for SAU conf).
*/
ER_CODE_CMSE_VENEER +0 ALIGN 32 {
*(Veneer$$CMSE)
}
/*
* This dummy region ensures that the next one will be aligned on a 32 bytes
* boundary, so that the following region will not be mistakenly configured
* as Non-Secure Callable by the SAU.
*/
ER_CODE_CMSE_VENEER_DUMMY +0 ALIGN 32 EMPTY 0 {}
/* This empty, zero long execution region is here to mark the limit address
* of the last execution region that is allocated in SRAM.
*/
CODE_WATERMARK +0 EMPTY 0x0 {
}
/* Make sure that the sections allocated in the SRAM does not exceed the
* size of the SRAM available.
*/
ScatterAssert(ImageLimit(CODE_WATERMARK) <= S_CODE_START + S_CODE_SIZE)
ER_DATA S_DATA_START {
.ANY (+ZI +RW)
}
#if HEAP_SIZE > 0
ARM_LIB_HEAP +0 ALIGN 8 EMPTY HEAP_SIZE { ; Reserve empty region for heap
}
#endif
ARM_LIB_STACK +0 ALIGN 32 EMPTY STACK_SIZE { ; Reserve empty region for stack
}
/* This empty, zero long execution region is here to mark the limit address
* of the last execution region that is allocated in SRAM.
*/
SRAM_WATERMARK +0 EMPTY 0x0 {
}
/* Make sure that the sections allocated in the SRAM does not exceed the
* size of the SRAM available.
*/
ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE)
}
ports/cortex_m55/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/SSE-300-MPS3/platform_base_address.h
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/*
* Copyright (c) 2019-2021 Arm Limited
*
* Licensed under the Apache License Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing software
* distributed under the License is distributed on an "AS IS" BASIS
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* \file platform_base_address.h
* \brief This file defines all the peripheral base addresses for AN552 MPS3 SSE-300 +
* Ethos-U55 platform.
*/
#ifndef __PLATFORM_BASE_ADDRESS_H__
#define __PLATFORM_BASE_ADDRESS_H__
/* ======= Defines peripherals memory map addresses ======= */
/* Non-secure memory map addresses */
#define ITCM_BASE_NS 0x00000000 /* Instruction TCM Non-Secure base address */
#define SRAM_BASE_NS 0x01000000 /* CODE SRAM Non-Secure base address */
#define DTCM0_BASE_NS 0x20000000 /* Data TCM block 0 Non-Secure base address */
#define DTCM1_BASE_NS 0x20020000 /* Data TCM block 1 Non-Secure base address */
#define DTCM2_BASE_NS 0x20040000 /* Data TCM block 2 Non-Secure base address */
#define DTCM3_BASE_NS 0x20060000 /* Data TCM block 3 Non-Secure base address */
#define ISRAM0_BASE_NS 0x21000000 /* Internal SRAM Area Non-Secure base address */
#define ISRAM1_BASE_NS 0x21100000 /* Internal SRAM Area Non-Secure base address */
#define QSPI_SRAM_BASE_NS 0x28000000 /* QSPI SRAM Non-Secure base address */
/* Non-Secure Subsystem peripheral region */
#define CPU0_PWRCTRL_BASE_NS 0x40012000 /* CPU 0 Power Control Block Non-Secure base address */
#define CPU0_IDENTITY_BASE_NS 0x4001F000 /* CPU 0 Identity Block Non-Secure base address */
#define SSE300_NSACFG_BASE_NS 0x40080000 /* SSE-300 Non-Secure Access Configuration Register Block Non-Secure base address */
/* Non-Secure MSTEXPPILL Peripheral region */
#define GPIO0_CMSDK_BASE_NS 0x41100000 /* GPIO 0 Non-Secure base address */
#define GPIO1_CMSDK_BASE_NS 0x41101000 /* GPIO 1 Non-Secure base address */
#define GPIO2_CMSDK_BASE_NS 0x41102000 /* GPIO 2 Non-Secure base address */
#define GPIO3_CMSDK_BASE_NS 0x41103000 /* GPIO 3 Non-Secure base address */
#define FMC_CMSDK_GPIO_0_BASE_NS 0x41104000 /* FMC CMSDK GPIO 0 Non-Secure base address */
#define FMC_CMSDK_GPIO_1_BASE_NS 0x41105000 /* FMC CMSDK GPIO 1 Non-Secure base address */
#define FMC_CMSDK_GPIO_2_BASE_NS 0x41106000 /* FMC CMSDK GPIO 2 Non-Secure base address */
#define FMC_CMSDK_GPIO_3_BASE_NS 0x41107000 /* FMC CMSDK GPIO 3 Non-Secure base address */
#define EXTERNAL_MANAGER_0_BASE_NS 0x41200000 /* External manager 0 (Unused) Non-Secure base address */
#define EXTERNAL_MANAGER_1_BASE_NS 0x41201000 /* External manager 1 (Unused) Non-Secure base address */
#define EXTERNAL_MANAGER_2_BASE_NS 0x41202000 /* External manager 2 (Unused) Non-Secure base address */
#define EXTERNAL_MANAGER_3_BASE_NS 0x41203000 /* External manager 3 (Unused) Non-Secure base address */
#define ETHERNET_BASE_NS 0x41400000 /* Ethernet Non-Secure base address */
#define USB_BASE_NS 0x41500000 /* USB Non-Secure base address */
#define USER_APB0_BASE_NS 0x41700000 /* User APB 0 Non-Secure base address */
#define USER_APB1_BASE_NS 0x41701000 /* User APB 1 Non-Secure base address */
#define USER_APB2_BASE_NS 0x41702000 /* User APB 2 Non-Secure base address */
#define USER_APB3_BASE_NS 0x41703000 /* User APB 3 Non-Secure base address */
#define QSPI_CONFIG_BASE_NS 0x41800000 /* QSPI Config Non-Secure base address */
#define QSPI_WRITE_BASE_NS 0x41801000 /* QSPI Write Non-Secure base address */
/* Non-Secure Subsystem peripheral region */
#define SYSTIMER0_ARMV8_M_BASE_NS 0x48000000 /* System Timer 0 Non-Secure base address */
#define SYSTIMER1_ARMV8_M_BASE_NS 0x48001000 /* System Timer 1 Non-Secure base address */
#define SYSTIMER2_ARMV8_M_BASE_NS 0x48002000 /* System Timer 2 Non-Secure base address */
#define SYSTIMER3_ARMV8_M_BASE_NS 0x48003000 /* System Timer 3 Non-Secure base address */
#define SSE300_SYSINFO_BASE_NS 0x48020000 /* SSE-300 System info Block Non-Secure base address */
#define SLOWCLK_TIMER_CMSDK_BASE_NS 0x4802F000 /* CMSDK based SLOWCLK Timer Non-Secure base address */
#define SYSWDOG_ARMV8_M_CNTRL_BASE_NS 0x48040000 /* Non-Secure Watchdog Timer control frame Non-Secure base address */
#define SYSWDOG_ARMV8_M_REFRESH_BASE_NS 0x48041000 /* Non-Secure Watchdog Timer refresh frame Non-Secure base address */
#define SYSCNTR_READ_BASE_NS 0x48101000 /* System Counter Read Secure base address */
/* Non-Secure MSTEXPPIHL Peripheral region */
#define ETHOS_U55_APB_BASE_NS 0x48102000 /* Ethos-U55 APB Non-Secure base address */
#define U55_TIMING_ADAPTER_0_BASE_NS 0x48103000 /* Ethos-U55 Timing Adapter 0 APB registers Non-Secure base address */
#define U55_TIMING_ADAPTER_1_BASE_NS 0x48103200 /* Ethos-U55 Timing Adapter 1 APB registers Non-Secure base address */
#define FPGA_SBCon_I2C_TOUCH_BASE_NS 0x49200000 /* FPGA - SBCon I2C (Touch) Non-Secure base address */
#define FPGA_SBCon_I2C_AUDIO_BASE_NS 0x49201000 /* FPGA - SBCon I2C (Audio Conf) Non-Secure base address */
#define FPGA_SPI_ADC_BASE_NS 0x49202000 /* FPGA - PL022 (SPI ADC) Non-Secure base address */
#define FPGA_SPI_SHIELD0_BASE_NS 0x49203000 /* FPGA - PL022 (SPI Shield0) Non-Secure base address */
#define FPGA_SPI_SHIELD1_BASE_NS 0x49204000 /* FPGA - PL022 (SPI Shield1) Non-Secure base address */
#define SBCon_I2C_SHIELD0_BASE_NS 0x49205000 /* SBCon (I2C - Shield0) Non-Secure base address */
#define SBCon_I2C_SHIELD1_BASE_NS 0x49206000 /* SBCon (I2C – Shield1) Non-Secure base address */
#define USER_APB_BASE_NS 0x49207000 /* USER APB Non-Secure base address */
#define FPGA_DDR4_EEPROM_BASE_NS 0x49208000 /* FPGA - SBCon I2C (DDR4 EEPROM) Non-Secure base address */
#define FMC_USER_APB0 0x4920C000 /* FMC User APB0 */
#define FMC_USER_APB1 0x4920D000 /* FMC User APB1 */
#define FMC_USER_APB2 0x4920E000 /* FMC User APB2 */
#define FMC_USER_APB3 0x4920F000 /* FMC User APB3 */
#define FPGA_SCC_BASE_NS 0x49300000 /* FPGA - SCC registers Non-Secure base address */
#define FPGA_I2S_BASE_NS 0x49301000 /* FPGA - I2S (Audio) Non-Secure base address */
#define FPGA_IO_BASE_NS 0x49302000 /* FPGA - IO (System Ctrl + I/O) Non-Secure base address */
#define UART0_BASE_NS 0x49303000 /* UART 0 Non-Secure base address */
#define UART1_BASE_NS 0x49304000 /* UART 1 Non-Secure base address */
#define UART2_BASE_NS 0x49305000 /* UART 2 Non-Secure base address */
#define UART3_BASE_NS 0x49306000 /* UART 3 Non-Secure base address */
#define UART4_BASE_NS 0x49307000 /* UART 4 Non-Secure base address */
#define UART5_BASE_NS 0x49308000 /* UART 5 Non-Secure base address */
#define CLCD_Config_Reg_BASE_NS 0x4930A000 /* CLCD Config Reg Non-Secure base address */
#define RTC_BASE_NS 0x4930B000 /* RTC Non-Secure base address */
#define DDR4_BLK0_BASE_NS 0x60000000 /* DDR4 block 0 Non-Secure base address */
#define DDR4_BLK2_BASE_NS 0x80000000 /* DDR4 block 2 Non-Secure base address */
#define DDR4_BLK4_BASE_NS 0xA0000000 /* DDR4 block 4 Non-Secure base address */
#define DDR4_BLK6_BASE_NS 0xC0000000 /* DDR4 block 6 Non-Secure base address */
/* Secure memory map addresses */
#define ITCM_BASE_S 0x10000000 /* Instruction TCM Secure base address */
#define SRAM_BASE_S 0x11000000 /* CODE SRAM Secure base address */
#define DTCM0_BASE_S 0x30000000 /* Data TCM block 0 Secure base address */
#define DTCM1_BASE_S 0x30020000 /* Data TCM block 1 Secure base address */
#define DTCM2_BASE_S 0x30040000 /* Data TCM block 2 Secure base address */
#define DTCM3_BASE_S 0x30060000 /* Data TCM block 3 Secure base address */
#define ISRAM0_BASE_S 0x31000000 /* Internal SRAM Area Secure base address */
#define ISRAM1_BASE_S 0x31100000 /* Internal SRAM Area Secure base address */
#define QSPI_SRAM_BASE_S 0x38000000 /* QSPI SRAM Secure base address */
/* Secure Subsystem peripheral region */
#define CPU0_SECCTRL_BASE_S 0x50011000 /* CPU 0 Local Security Control Block Secure base address */
#define CPU0_PWRCTRL_BASE_S 0x50012000 /* CPU 0 Power Control Block Secure base address */
#define CPU0_IDENTITY_BASE_S 0x5001F000 /* CPU 0 Identity Block Secure base address */
#define SSE300_SACFG_BASE_S 0x50080000 /* SSE-300 Secure Access Configuration Register Secure base address */
#define MPC_ISRAM0_BASE_S 0x50083000 /* Internal SRAM0 Memory Protection Controller Secure base address */
#define MPC_ISRAM1_BASE_S 0x50084000 /* Internal SRAM1 Memory Protection Controller Secure base address */
/* Secure MSTEXPPILL Peripheral region */
#define GPIO0_CMSDK_BASE_S 0x51100000 /* GPIO 0 Secure base address */
#define GPIO1_CMSDK_BASE_S 0x51101000 /* GPIO 1 Secure base address */
#define GPIO2_CMSDK_BASE_S 0x51102000 /* GPIO 2 Secure base address */
#define GPIO3_CMSDK_BASE_S 0x51103000 /* GPIO 3 Secure base address */
#define FMC_CMSDK_GPIO_0_BASE_S 0x51104000 /* FMC CMSDK GPIO 0 Secure base address */
#define FMC_CMSDK_GPIO_1_BASE_S 0x51105000 /* FMC CMSDK GPIO 1 Secure base address */
#define FMC_CMSDK_GPIO_2_BASE_S 0x51106000 /* FMC CMSDK GPIO 2 Secure base address */
#define FMC_CMSDK_GPIO_3_BASE_S 0x51107000 /* FMC CMSDK GPIO 3 Secure base address */
#define EXTERNAL_MANAGER0_BASE_S 0x51200000 /* External Manager 0 (Unused) Secure base address */
#define EXTERNAL_MANAGER1_BASE_S 0x51201000 /* External Manager 1 (Unused) Secure base address */
#define EXTERNAL_MANAGER2_BASE_S 0x51202000 /* External Manager 2 (Unused) Secure base address */
#define EXTERNAL_MANAGER3_BASE_S 0x51203000 /* External Manager 3 (Unused) Secure base address */
#define ETHERNET_BASE_S 0x51400000 /* Ethernet Secure base address */
#define USB_BASE_S 0x51500000 /* USB Secure base address */
#define USER_APB0_BASE_S 0x51700000 /* User APB 0 Secure base address */
#define USER_APB1_BASE_S 0x51701000 /* User APB 1 Secure base address */
#define USER_APB2_BASE_S 0x51702000 /* User APB 2 Secure base address */
#define USER_APB3_BASE_S 0x51703000 /* User APB 3 Secure base address */
#define QSPI_CONFIG_BASE_S 0x51800000 /* QSPI Config Secure base address */
#define QSPI_WRITE_BASE_S 0x51801000 /* QSPI Write Secure base address */
#define MPC_SRAM_BASE_S 0x57000000 /* SRAM Memory Protection Controller Secure base address */
#define MPC_QSPI_BASE_S 0x57001000 /* QSPI Memory Protection Controller Secure base address */
#define MPC_DDR4_BASE_S 0x57002000 /* DDR4 Memory Protection Controller Secure base address */
/* Secure Subsystem peripheral region */
#define SYSTIMER0_ARMV8_M_BASE_S 0x58000000 /* System Timer 0 Secure base address */
#define SYSTIMER1_ARMV8_M_BASE_S 0x58001000 /* System Timer 1 Secure base address */
#define SYSTIMER2_ARMV8_M_BASE_S 0x58002000 /* System Timer 0 Secure base address */
#define SYSTIMER3_ARMV8_M_BASE_S 0x58003000 /* System Timer 1 Secure base address */
#define SSE300_SYSINFO_BASE_S 0x58020000 /* SSE-300 System info Block Secure base address */
#define SSE300_SYSCTRL_BASE_S 0x58021000 /* SSE-300 System control Block Secure base address */
#define SSE300_SYSPPU_BASE_S 0x58022000 /* SSE-300 System Power Policy Unit Secure base address */
#define SSE300_CPU0PPU_BASE_S 0x58023000 /* SSE-300 CPU 0 Power Policy Unit Secure base address */
#define SSE300_MGMTPPU_BASE_S 0x58028000 /* SSE-300 Management Power Policy Unit Secure base address */
#define SSE300_DBGPPU_BASE_S 0x58029000 /* SSE-300 Debug Power Policy Unit Secure base address */
#define SLOWCLK_WDOG_CMSDK_BASE_S 0x5802E000 /* CMSDK based SLOWCLK Watchdog Secure base address */
#define SLOWCLK_TIMER_CMSDK_BASE_S 0x5802F000 /* CMSDK based SLOWCLK Timer Secure base address */
#define SYSWDOG_ARMV8_M_CNTRL_BASE_S 0x58040000 /* Secure Watchdog Timer control frame Secure base address */
#define SYSWDOG_ARMV8_M_REFRESH_BASE_S 0x58041000 /* Secure Watchdog Timer refresh frame Secure base address */
#define SYSCNTR_CNTRL_BASE_S 0x58100000 /* System Counter Control Secure base address */
#define SYSCNTR_READ_BASE_S 0x58101000 /* System Counter Read Secure base address */
/* Secure MSTEXPPIHL Peripheral region */
#define ETHOS_U55_APB_BASE_S 0x58102000 /* Ethos-U55 APB Secure base address */
#define U55_TIMING_ADAPTER_0_BASE_S 0x58103000 /* Ethos-U55 Timing Adapter 0 APB registers Secure base address */
#define U55_TIMING_ADAPTER_1_BASE_S 0x58103200 /* Ethos-U55 Timing Adapter 1 APB registers Secure base address */
#define FPGA_SBCon_I2C_TOUCH_BASE_S 0x59200000 /* FPGA - SBCon I2C (Touch) Secure base address */
#define FPGA_SBCon_I2C_AUDIO_BASE_S 0x59201000 /* FPGA - SBCon I2C (Audio Conf) Secure base address */
#define FPGA_SPI_ADC_BASE_S 0x59202000 /* FPGA - PL022 (SPI ADC) Secure base address */
#define FPGA_SPI_SHIELD0_BASE_S 0x59203000 /* FPGA - PL022 (SPI Shield0) Secure base address */
#define FPGA_SPI_SHIELD1_BASE_S 0x59204000 /* FPGA - PL022 (SPI Shield1) Secure base address */
#define SBCon_I2C_SHIELD0_BASE_S 0x59205000 /* SBCon (I2C - Shield0) Secure base address */
#define SBCon_I2C_SHIELD1_BASE_S 0x59206000 /* SBCon (I2C – Shield1) Secure base address */
#define USER_APB_BASE_S 0x59207000 /* USER APB Secure base address */
#define FPGA_DDR4_EEPROM_BASE_S 0x59208000 /* FPGA - SBCon I2C (DDR4 EEPROM) Secure base address */
#define FMC_USER_APB_0_BASE_S 0x5920C000 /* FMC User APB0 registers Secure base address */
#define FMC_USER_APB_1_BASE_S 0x5920D000 /* FMC User APB1 registers Secure base address */
#define FMC_USER_APB_2_BASE_S 0x5920E000 /* FMC User APB2 registers Secure base address */
#define FMC_USER_APB_3_BASE_S 0x5920F000 /* FMC User APB3 registers Secure base address */
#define FPGA_SCC_BASE_S 0x59300000 /* FPGA - SCC registers Secure base address */
#define FPGA_I2S_BASE_S 0x59301000 /* FPGA - I2S (Audio) Secure base address */
#define FPGA_IO_BASE_S 0x59302000 /* FPGA - IO (System Ctrl + I/O) Secure base address */
#define UART0_BASE_S 0x59303000 /* UART 0 Secure base address */
#define UART1_BASE_S 0x59304000 /* UART 1 Secure base address */
#define UART2_BASE_S 0x59305000 /* UART 2 Secure base address */
#define UART3_BASE_S 0x59306000 /* UART 3 Secure base address */
#define UART4_BASE_S 0x59307000 /* UART 4 Secure base address */
#define UART5_BASE_S 0x59308000 /* UART 5 Secure base address */
#define CLCD_Config_Reg_BASE_S 0x5930A000 /* CLCD Config Reg Secure base address */
#define RTC_BASE_S 0x5930B000 /* RTC Secure base address */
#define DDR4_BLK1_BASE_S 0x70000000 /* DDR4 block 1 Secure base address */
#define DDR4_BLK3_BASE_S 0x90000000 /* DDR4 block 3 Secure base address */
#define DDR4_BLK5_BASE_S 0xB0000000 /* DDR4 block 5 Secure base address */
#define DDR4_BLK7_BASE_S 0xD0000000 /* DDR4 block 7 Secure base address */
/* Memory map addresses exempt from memory attribution by both the SAU and IDAU */
#define SSE300_EWIC_BASE 0xE0047000 /* External Wakeup Interrupt Controller
* Access from Non-secure software is only allowed
* if AIRCR.BFHFNMINS is set to 1 */
/* Memory size definitions */
#define ITCM_SIZE (0x00080000) /* 512 kB */
#define DTCM_BLK_SIZE (0x00020000) /* 128 kB */
#define DTCM_BLK_NUM (0x4) /* Number of DTCM blocks */
#define SRAM_SIZE (0x00100000) /* 1 MB */
#define ISRAM0_SIZE (0x00100000) /* 1 MB */
#define ISRAM1_SIZE (0x00100000) /* 1 MB */
#define QSPI_SRAM_SIZE (0x00800000) /* 8 MB */
#define DDR4_BLK_SIZE (0x10000000) /* 256 MB */
#define DDR4_BLK_NUM (0x8) /* Number of DDR4 blocks */
/* Defines for Driver MPC's */
/* SRAM -- 2 MB */
#define MPC_SRAM_RANGE_BASE_NS (SRAM_BASE_NS)
#define MPC_SRAM_RANGE_LIMIT_NS (SRAM_BASE_NS + SRAM_SIZE-1)
#define MPC_SRAM_RANGE_OFFSET_NS (0x0)
#define MPC_SRAM_RANGE_BASE_S (SRAM_BASE_S)
#define MPC_SRAM_RANGE_LIMIT_S (SRAM_BASE_S + SRAM_SIZE-1)
#define MPC_SRAM_RANGE_OFFSET_S (0x0)
/* QSPI -- 8 MB*/
#define MPC_QSPI_RANGE_BASE_NS (QSPI_SRAM_BASE_NS)
#define MPC_QSPI_RANGE_LIMIT_NS (QSPI_SRAM_BASE_NS + QSPI_SRAM_SIZE-1)
#define MPC_QSPI_RANGE_OFFSET_NS (0x0)
#define MPC_QSPI_RANGE_BASE_S (QSPI_SRAM_BASE_S)
#define MPC_QSPI_RANGE_LIMIT_S (QSPI_SRAM_BASE_S + QSPI_SRAM_SIZE-1)
#define MPC_QSPI_RANGE_OFFSET_S (0x0)
/* ISRAM0 -- 2 MB*/
#define MPC_ISRAM0_RANGE_BASE_NS (ISRAM0_BASE_NS)
#define MPC_ISRAM0_RANGE_LIMIT_NS (ISRAM0_BASE_NS + ISRAM0_SIZE-1)
#define MPC_ISRAM0_RANGE_OFFSET_NS (0x0)
#define MPC_ISRAM0_RANGE_BASE_S (ISRAM0_BASE_S)
#define MPC_ISRAM0_RANGE_LIMIT_S (ISRAM0_BASE_S + ISRAM0_SIZE-1)
#define MPC_ISRAM0_RANGE_OFFSET_S (0x0)
/* ISRAM1 -- 2 MB*/
#define MPC_ISRAM1_RANGE_BASE_NS (ISRAM1_BASE_NS)
#define MPC_ISRAM1_RANGE_LIMIT_NS (ISRAM1_BASE_NS + ISRAM1_SIZE-1)
#define MPC_ISRAM1_RANGE_OFFSET_NS (0x0)
#define MPC_ISRAM1_RANGE_BASE_S (ISRAM1_BASE_S)
#define MPC_ISRAM1_RANGE_LIMIT_S (ISRAM1_BASE_S + ISRAM1_SIZE-1)
#define MPC_ISRAM1_RANGE_OFFSET_S (0x0)
/* DDR4 -- 2GB (8 * 256 MB) */
#define MPC_DDR4_BLK0_RANGE_BASE_NS (DDR4_BLK0_BASE_NS)
#define MPC_DDR4_BLK0_RANGE_LIMIT_NS (DDR4_BLK0_BASE_NS + ((DDR4_BLK_SIZE)-1))
#define MPC_DDR4_BLK0_RANGE_OFFSET_NS (0x0)
#define MPC_DDR4_BLK1_RANGE_BASE_S (DDR4_BLK1_BASE_S)
#define MPC_DDR4_BLK1_RANGE_LIMIT_S (DDR4_BLK1_BASE_S + ((DDR4_BLK_SIZE)-1))
#define MPC_DDR4_BLK1_RANGE_OFFSET_S (DDR4_BLK1_BASE_S - DDR4_BLK0_BASE_NS)
#define MPC_DDR4_BLK2_RANGE_BASE_NS (DDR4_BLK2_BASE_NS)
#define MPC_DDR4_BLK2_RANGE_LIMIT_NS (DDR4_BLK2_BASE_NS + ((DDR4_BLK_SIZE)-1))
#define MPC_DDR4_BLK2_RANGE_OFFSET_NS (DDR4_BLK2_BASE_NS - DDR4_BLK0_BASE_NS)
#define MPC_DDR4_BLK3_RANGE_BASE_S (DDR4_BLK3_BASE_S)
#define MPC_DDR4_BLK3_RANGE_LIMIT_S (DDR4_BLK3_BASE_S + ((DDR4_BLK_SIZE)-1))
#define MPC_DDR4_BLK3_RANGE_OFFSET_S (DDR4_BLK3_BASE_S - DDR4_BLK0_BASE_NS)
#define MPC_DDR4_BLK4_RANGE_BASE_NS (DDR4_BLK4_BASE_NS)
#define MPC_DDR4_BLK4_RANGE_LIMIT_NS (DDR4_BLK4_BASE_NS + ((DDR4_BLK_SIZE)-1))
#define MPC_DDR4_BLK4_RANGE_OFFSET_NS (DDR4_BLK4_BASE_NS - DDR4_BLK0_BASE_NS)
#define MPC_DDR4_BLK5_RANGE_BASE_S (DDR4_BLK5_BASE_S)
#define MPC_DDR4_BLK5_RANGE_LIMIT_S (DDR4_BLK5_BASE_S + ((DDR4_BLK_SIZE)-1))
#define MPC_DDR4_BLK5_RANGE_OFFSET_S (DDR4_BLK5_BASE_S - DDR4_BLK0_BASE_NS)
#define MPC_DDR4_BLK6_RANGE_BASE_NS (DDR4_BLK6_BASE_NS)
#define MPC_DDR4_BLK6_RANGE_LIMIT_NS (DDR4_BLK6_BASE_NS + ((DDR4_BLK_SIZE)-1))
#define MPC_DDR4_BLK6_RANGE_OFFSET_NS (DDR4_BLK6_BASE_NS - DDR4_BLK0_BASE_NS)
#define MPC_DDR4_BLK7_RANGE_BASE_S (DDR4_BLK7_BASE_S)
#define MPC_DDR4_BLK7_RANGE_LIMIT_S (DDR4_BLK7_BASE_S + ((DDR4_BLK_SIZE)-1))
#define MPC_DDR4_BLK7_RANGE_OFFSET_S (DDR4_BLK7_BASE_S - DDR4_BLK0_BASE_NS)
#endif /* __PLATFORM_BASE_ADDRESS_H__ */
ports/cortex_m55/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/SSE-300-MPS3/region_defs.h
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/*
* Copyright (c) 2016-2022 Arm Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __REGION_DEFS_H__
#define __REGION_DEFS_H__
#include "region_limits.h"
/* **************************************************************
* WARNING: this file is parsed both by the C/C++ compiler
* and the linker. As a result the syntax must be valid not only
* for C/C++ but for the linker scripts too.
* Beware of the following limitations:
* - LD (GCC linker) requires white space around operators.
* - UL postfix for macros is not suported by the linker script
****************************************************************/
/* Secure regions */
#define S_CODE_START ( S_ROM_ALIAS )
#define S_CODE_SIZE ( TOTAL_S_ROM_SIZE )
#define S_CODE_LIMIT ( S_CODE_START + S_CODE_SIZE )
#define S_DATA_START ( S_RAM_ALIAS )
#define S_DATA_SIZE ( TOTAL_S_RAM_SIZE )
#define S_DATA_LIMIT ( S_DATA_START + S_DATA_SIZE )
#define S_DDR4_START ( S_DDR4_ALIAS )
#define S_DDR4_SIZE ( TOTAL_S_DDR4_SIZE )
#define S_DDR4_LIMIT ( S_DDR4_START + S_DDR4_SIZE )
#endif /* __REGION_DEFS_H__ */
ports/cortex_m55/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/SSE-300-MPS3/region_limits.h
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/*
* Copyright (c) 2018-2022 Arm Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __REGION_LIMITS_H__
#define __REGION_LIMITS_H__
/* **************************************************************
* WARNING: this file is parsed both by the C/C++ compiler
* and the linker. As a result the syntax must be valid not only
* for C/C++ but for the linker scripts too.
* Beware of the following limitations:
* - LD (GCC linker) requires white space around operators.
* - UL postfix for macros is not suported by the linker script
****************************************************************/
/* Secure Code */
#define S_ROM_ALIAS (0x10000000) /* ITCM_BASE_S */
#define TOTAL_S_ROM_SIZE (0x00080000) /* 512 kB */
/* Secure Data */
#define S_RAM_ALIAS (0x30000000) /* DTCM_BASE_S */
#define TOTAL_S_RAM_SIZE (0x00080000) /* 512 kB */
/* Secure DDR4 */
#define S_DDR4_ALIAS (0x70000000) /* DDR4_BLK1_BASE_S */
#define TOTAL_S_DDR4_SIZE (0x10000000) /* 256 MB */
/* Heap and Stack sizes for secure and nonsecure applications */
#define HEAP_SIZE (0x00000400) /* 1 KiB */
#define STACK_SIZE (0x00000400) /* 1 KiB */
#endif /* __REGION_LIMITS_H__ */
ports/cortex_m55/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/SSE-300-MPS3/startup_fvp_sse300_mps3.c
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/*
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* This file is derivative of CMSIS V5.6.0 startup_ARMv81MML.c
* Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b
*/
#include "SSE300MPS3.h"
/*----------------------------------------------------------------------------
Exception / Interrupt Handler Function Prototype
*----------------------------------------------------------------------------*/
typedef void( *pFunc )( void );
/*----------------------------------------------------------------------------
External References
*----------------------------------------------------------------------------*/
extern uint32_t __INITIAL_SP;
extern uint32_t __STACK_LIMIT;
extern void __PROGRAM_START(void) __NO_RETURN;
/*----------------------------------------------------------------------------
Internal References
*----------------------------------------------------------------------------*/
void Reset_Handler (void) __NO_RETURN;
/*----------------------------------------------------------------------------
Exception / Interrupt Handler
*----------------------------------------------------------------------------*/
#define DEFAULT_IRQ_HANDLER(handler_name) \
void __WEAK __NO_RETURN handler_name(void); \
void handler_name(void) { \
while(1); \
}
/* Exceptions */
DEFAULT_IRQ_HANDLER(NMI_Handler)
DEFAULT_IRQ_HANDLER(HardFault_Handler)
DEFAULT_IRQ_HANDLER(MemManage_Handler)
DEFAULT_IRQ_HANDLER(BusFault_Handler)
DEFAULT_IRQ_HANDLER(UsageFault_Handler)
DEFAULT_IRQ_HANDLER(SecureFault_Handler)
DEFAULT_IRQ_HANDLER(SVC_Handler)
DEFAULT_IRQ_HANDLER(DebugMon_Handler)
DEFAULT_IRQ_HANDLER(PendSV_Handler)
DEFAULT_IRQ_HANDLER(SysTick_Handler)
DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_Handler)
DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler)
DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler)
DEFAULT_IRQ_HANDLER(TIMER0_Handler)
DEFAULT_IRQ_HANDLER(TIMER1_Handler)
DEFAULT_IRQ_HANDLER(TIMER2_Handler)
DEFAULT_IRQ_HANDLER(MPC_Handler)
DEFAULT_IRQ_HANDLER(PPC_Handler)
DEFAULT_IRQ_HANDLER(MSC_Handler)
DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler)
DEFAULT_IRQ_HANDLER(MGMT_PPU_Handler)
DEFAULT_IRQ_HANDLER(SYS_PPU_Handler)
DEFAULT_IRQ_HANDLER(CPU0_PPU_Handler)
DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler)
DEFAULT_IRQ_HANDLER(TIMER3_Handler)
DEFAULT_IRQ_HANDLER(CTI_REQ0_IRQHandler)
DEFAULT_IRQ_HANDLER(CTI_REQ1_IRQHandler)
DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler)
DEFAULT_IRQ_HANDLER(UARTRX0_Handler)
DEFAULT_IRQ_HANDLER(UARTTX0_Handler)
DEFAULT_IRQ_HANDLER(UARTRX1_Handler)
DEFAULT_IRQ_HANDLER(UARTTX1_Handler)
DEFAULT_IRQ_HANDLER(UARTRX2_Handler)
DEFAULT_IRQ_HANDLER(UARTTX2_Handler)
DEFAULT_IRQ_HANDLER(UARTRX3_Handler)
DEFAULT_IRQ_HANDLER(UARTTX3_Handler)
DEFAULT_IRQ_HANDLER(UARTRX4_Handler)
DEFAULT_IRQ_HANDLER(UARTTX4_Handler)
DEFAULT_IRQ_HANDLER(UART0_Combined_Handler)
DEFAULT_IRQ_HANDLER(UART1_Combined_Handler)
DEFAULT_IRQ_HANDLER(UART2_Combined_Handler)
DEFAULT_IRQ_HANDLER(UART3_Combined_Handler)
DEFAULT_IRQ_HANDLER(UART4_Combined_Handler)
DEFAULT_IRQ_HANDLER(UARTOVF_Handler)
DEFAULT_IRQ_HANDLER(ETHERNET_Handler)
DEFAULT_IRQ_HANDLER(I2S_Handler)
DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler)
DEFAULT_IRQ_HANDLER(USB_Handler)
DEFAULT_IRQ_HANDLER(SPI_ADC_Handler)
DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler)
DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler)
DEFAULT_IRQ_HANDLER(ETHOS_U55_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler)
DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_0_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_1_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_2_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_3_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_4_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_5_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_6_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_7_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_8_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_9_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_10_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_11_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_12_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_13_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_14_Handler)
DEFAULT_IRQ_HANDLER(GPIO0_15_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_0_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_1_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_2_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_3_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_4_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_5_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_6_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_7_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_8_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_9_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_10_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_11_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_12_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_13_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_14_Handler)
DEFAULT_IRQ_HANDLER(GPIO1_15_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_0_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_1_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_2_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_3_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_4_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_5_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_6_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_7_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_8_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_9_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_10_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_11_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_12_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_13_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_14_Handler)
DEFAULT_IRQ_HANDLER(GPIO2_15_Handler)
DEFAULT_IRQ_HANDLER(GPIO3_0_Handler)
DEFAULT_IRQ_HANDLER(GPIO3_1_Handler)
DEFAULT_IRQ_HANDLER(GPIO3_2_Handler)
DEFAULT_IRQ_HANDLER(GPIO3_3_Handler)
DEFAULT_IRQ_HANDLER(UARTRX5_Handler)
DEFAULT_IRQ_HANDLER(UARTTX5_Handler)
DEFAULT_IRQ_HANDLER(UART5_Handler)
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
#if defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
extern const pFunc __VECTOR_TABLE[496];
const pFunc __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
(pFunc)(&__INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14: NMI Handler */
HardFault_Handler, /* -13: Hard Fault Handler */
MemManage_Handler, /* -12: MPU Fault Handler */
BusFault_Handler, /* -11: Bus Fault Handler */
UsageFault_Handler, /* -10: Usage Fault Handler */
SecureFault_Handler, /* -9: Secure Fault Handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* -5: SVCall Handler */
DebugMon_Handler, /* -4: Debug Monitor Handler */
0, /* Reserved */
PendSV_Handler, /* -2: PendSV Handler */
SysTick_Handler, /* -1: SysTick Handler */
NONSEC_WATCHDOG_RESET_Handler, /* 0: Non-Secure Watchdog Reset Handler */
NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */
SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */
TIMER0_Handler, /* 3: TIMER 0 Handler */
TIMER1_Handler, /* 4: TIMER 1 Handler */
TIMER2_Handler, /* 5: TIMER 2 Handler */
0, /* 6: Reserved */
0, /* 7: Reserved */
0, /* 8: Reserved */
MPC_Handler, /* 9: MPC Combined (Secure) Handler */
PPC_Handler, /* 10: PPC Combined (Secure) Handler */
MSC_Handler, /* 11: MSC Combined (Secure) Handler */
BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */
0, /* 13: Reserved */
MGMT_PPU_Handler, /* 14: MGMT PPU Handler */
SYS_PPU_Handler, /* 15: SYS PPU Handler */
CPU0_PPU_Handler, /* 16: CPU0 PPU Handler */
0, /* 17: Reserved */
0, /* 18: Reserved */
0, /* 19: Reserved */
0, /* 20: Reserved */
0, /* 21: Reserved */
0, /* 22: Reserved */
0, /* 23: Reserved */
0, /* 24: Reserved */
0, /* 25: Reserved */
DEBUG_PPU_Handler, /* 26: DEBUG PPU Handler */
TIMER3_Handler, /* 27: TIMER 3 Handler */
CTI_REQ0_IRQHandler, /* 28: CTI request 0 IRQ Handler */
CTI_REQ1_IRQHandler, /* 29: CTI request 1 IRQ Handler */
0, /* 30: Reserved */
0, /* 31: Reserved */
/* External interrupts */
System_Timestamp_Counter_Handler, /* 32: System timestamp counter Handler */
UARTRX0_Handler, /* 33: UART 0 RX Handler */
UARTTX0_Handler, /* 34: UART 0 TX Handler */
UARTRX1_Handler, /* 35: UART 1 RX Handler */
UARTTX1_Handler, /* 36: UART 1 TX Handler */
UARTRX2_Handler, /* 37: UART 2 RX Handler */
UARTTX2_Handler, /* 38: UART 2 TX Handler */
UARTRX3_Handler, /* 39: UART 3 RX Handler */
UARTTX3_Handler, /* 40: UART 3 TX Handler */
UARTRX4_Handler, /* 41: UART 4 RX Handler */
UARTTX4_Handler, /* 42: UART 4 TX Handler */
UART0_Combined_Handler, /* 43: UART 0 Combined Handler */
UART1_Combined_Handler, /* 44: UART 1 Combined Handler */
UART2_Combined_Handler, /* 45: UART 2 Combined Handler */
UART3_Combined_Handler, /* 46: UART 3 Combined Handler */
UART4_Combined_Handler, /* 47: UART 4 Combined Handler */
UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */
ETHERNET_Handler, /* 49: Ethernet Handler */
I2S_Handler, /* 50: Audio I2S Handler */
TOUCH_SCREEN_Handler, /* 51: Touch Screen Handler */
USB_Handler, /* 52: USB Handler */
SPI_ADC_Handler, /* 53: SPI ADC Handler */
SPI_SHIELD0_Handler, /* 54: SPI (Shield 0) Handler */
SPI_SHIELD1_Handler, /* 55: SPI (Shield 0) Handler */
ETHOS_U55_Handler, /* 56: Ethos-U55 Handler */
0, /* 57: Reserved */
0, /* 58: Reserved */
0, /* 59: Reserved */
0, /* 60: Reserved */
0, /* 61: Reserved */
0, /* 62: Reserved */
0, /* 63: Reserved */
0, /* 64: Reserved */
0, /* 65: Reserved */
0, /* 66: Reserved */
0, /* 67: Reserved */
0, /* 68: Reserved */
GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */
GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */
GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */
GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */
GPIO0_0_Handler, /* 73: GPIO0 Pin 0 Handler */
GPIO0_1_Handler, /* 74: GPIO0 Pin 1 Handler */
GPIO0_2_Handler, /* 75: GPIO0 Pin 2 Handler */
GPIO0_3_Handler, /* 76: GPIO0 Pin 3 Handler */
GPIO0_4_Handler, /* 77: GPIO0 Pin 4 Handler */
GPIO0_5_Handler, /* 78: GPIO0 Pin 5 Handler */
GPIO0_6_Handler, /* 79: GPIO0 Pin 6 Handler */
GPIO0_7_Handler, /* 80: GPIO0 Pin 7 Handler */
GPIO0_8_Handler, /* 81: GPIO0 Pin 8 Handler */
GPIO0_9_Handler, /* 82: GPIO0 Pin 9 Handler */
GPIO0_10_Handler, /* 83: GPIO0 Pin 10 Handler */
GPIO0_11_Handler, /* 84: GPIO0 Pin 11 Handler */
GPIO0_12_Handler, /* 85: GPIO0 Pin 12 Handler */
GPIO0_13_Handler, /* 86: GPIO0 Pin 13 Handler */
GPIO0_14_Handler, /* 87: GPIO0 Pin 14 Handler */
GPIO0_15_Handler, /* 88: GPIO0 Pin 15 Handler */
GPIO1_0_Handler, /* 89: GPIO1 Pin 0 Handler */
GPIO1_1_Handler, /* 90: GPIO1 Pin 1 Handler */
GPIO1_2_Handler, /* 91: GPIO1 Pin 2 Handler */
GPIO1_3_Handler, /* 92: GPIO1 Pin 3 Handler */
GPIO1_4_Handler, /* 93: GPIO1 Pin 4 Handler */
GPIO1_5_Handler, /* 94: GPIO1 Pin 5 Handler */
GPIO1_6_Handler, /* 95: GPIO1 Pin 6 Handler */
GPIO1_7_Handler, /* 96: GPIO1 Pin 7 Handler */
GPIO1_8_Handler, /* 97: GPIO1 Pin 8 Handler */
GPIO1_9_Handler, /* 98: GPIO1 Pin 9 Handler */
GPIO1_10_Handler, /* 99: GPIO1 Pin 10 Handler */
GPIO1_11_Handler, /* 100: GPIO1 Pin 11 Handler */
GPIO1_12_Handler, /* 101: GPIO1 Pin 12 Handler */
GPIO1_13_Handler, /* 102: GPIO1 Pin 13 Handler */
GPIO1_14_Handler, /* 103: GPIO1 Pin 14 Handler */
GPIO1_15_Handler, /* 104: GPIO1 Pin 15 Handler */
GPIO2_0_Handler, /* 105: GPIO2 Pin 0 Handler */
GPIO2_1_Handler, /* 106: GPIO2 Pin 1 Handler */
GPIO2_2_Handler, /* 107: GPIO2 Pin 2 Handler */
GPIO2_3_Handler, /* 108: GPIO2 Pin 3 Handler */
GPIO2_4_Handler, /* 109: GPIO2 Pin 4 Handler */
GPIO2_5_Handler, /* 110: GPIO2 Pin 5 Handler */
GPIO2_6_Handler, /* 111: GPIO2 Pin 6 Handler */
GPIO2_7_Handler, /* 112: GPIO2 Pin 7 Handler */
GPIO2_8_Handler, /* 113: GPIO2 Pin 8 Handler */
GPIO2_9_Handler, /* 114: GPIO2 Pin 9 Handler */
GPIO2_10_Handler, /* 115: GPIO2 Pin 10 Handler */
GPIO2_11_Handler, /* 116: GPIO2 Pin 11 Handler */
GPIO2_12_Handler, /* 117: GPIO2 Pin 12 Handler */
GPIO2_13_Handler, /* 118: GPIO2 Pin 13 Handler */
GPIO2_14_Handler, /* 119: GPIO2 Pin 14 Handler */
GPIO2_15_Handler, /* 120: GPIO2 Pin 15 Handler */
GPIO3_0_Handler, /* 121: GPIO3 Pin 0 Handler */
GPIO3_1_Handler, /* 122: GPIO3 Pin 1 Handler */
GPIO3_2_Handler, /* 123: GPIO3 Pin 2 Handler */
GPIO3_3_Handler, /* 124: GPIO3 Pin 3 Handler */
UARTRX5_Handler, /* 125: UART 5 RX Interrupt */
UARTTX5_Handler, /* 126: UART 5 TX Interrupt */
UART5_Handler, /* 127: UART 5 combined Interrupt */
0, /* 128: Reserved */
0, /* 129: Reserved */
0, /* 130: Reserved */
};
#if defined ( __GNUC__ )
#pragma GCC diagnostic pop
#endif
/*----------------------------------------------------------------------------
Reset Handler called on controller reset
*----------------------------------------------------------------------------*/
void Reset_Handler(void)
{
__set_MSPLIM((uint32_t)(&__STACK_LIMIT));
SystemInit(); /* CMSIS System Initialization */
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
}
ports/cortex_m55/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c
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/*
* Copyright (c) 2009-2022 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* This file is derivative of CMSIS V5.6.0 system_ARMv81MML.c
* Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b
*/
#include "SSE300MPS3.h"
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define XTAL (32000000UL)
#define SYSTEM_CLOCK (XTAL)
#define PERIPHERAL_CLOCK (25000000UL)
/*----------------------------------------------------------------------------
Externals
*----------------------------------------------------------------------------*/
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
extern uint32_t __VECTOR_TABLE;
#endif
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK;
uint32_t PeripheralClock = PERIPHERAL_CLOCK;
/*----------------------------------------------------------------------------
System Core Clock update function
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
PeripheralClock = PERIPHERAL_CLOCK;
}
/*----------------------------------------------------------------------------
System initialization function
*----------------------------------------------------------------------------*/
void SystemInit (void)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
SCB->VTOR = (uint32_t)(&__VECTOR_TABLE);
#endif
#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \
(defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE >= 1U))
SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
(3U << 11U*2U) ); /* enable CP11 Full Access */
/* Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. Set
* CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU
* into retention state
*/
PWRMODCTL->CPDLPSTATE &= 0xFFFFFF00UL;
#endif
#ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif
/* Enable Loop and branch info cache */
SCB->CCR |= SCB_CCR_LOB_Msk;
__DSB();
__ISB();
}
ports/cortex_m55/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.h
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/*
* Copyright (c) 2009-2020 Arm Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* This file is derivative of CMSIS V5.6.0 system_ARMv81MML.h
* Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b
*/
#ifndef __SYSTEM_CORE_INIT_H__
#define __SYSTEM_CORE_INIT_H__
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern uint32_t PeripheralClock; /*!< Peripheral Clock Frequency */
/**
* \brief Initializes the system
*/
extern void SystemInit(void);
/**
* \brief Restores system core clock
*/
extern void SystemCoreClockUpdate(void);
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_CORE_INIT_H__ */
ports/cortex_m55/ac6/example_build/demo_threadx_non-secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h
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/*
* Auto generated Run-Time-Environment Configuration File
* *** Do not modify ! ***
*
* Project: 'demo_threadx_non-secure_zone'
* Target: 'FVP Simulation Model'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
/*
* Define the Device Header File:
*/
#define CMSIS_device_header "SSE300MPS3.h"
#endif /* RTE_COMPONENTS_H */
ports/cortex_m55/ac6/example_build/demo_threadx_non-secure_zone/ThreadX_Demo.uvopt
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>ThreadX_Demo</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>1</RunSim>
<RunTarget>0</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>255</CpuCode>
<DebugOpt>
<uSim>1</uSim>
<uTrg>0</uTrg>
<sLdApp>1</sLdApp>
<sGomain>0</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>0</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>0</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>-1</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon></pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMRTXEVENTFLAGS</Key>
<Name>-L70 -Z18 -C0 -M0 -T1</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGDARM</Key>
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGUARM</Key>
<Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGTARM</Key>
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</SetRegEntry>
<SetRegEntry>
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</TargetDriverDllRegistry>
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</WatchWindow1>
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</DebugFlag>
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<pMisraName></pMisraName>
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</TargetOption>
</Target>
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<GroupName>Source Group</GroupName>
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<FilenameWithoutPath>demo_threadx.c</FilenameWithoutPath>
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<WindowPosition>
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</NormalPosition>
</WindowPosition>
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</File>
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</ProjectOpt>

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