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Update on 16 Dec 2022. Expand to see details.

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b5d5df511 #include tx_user.h in assembly files for cortex-m ports
33e04e3d5 initial port of MIPS SMP for GHS and GNU
2eda2c17d capitalize extensions for M23 asm files
21c354ccb Fix armv7-m MPU settings for corner case, unify txm_module_port.h files
4a1ff93f9 remove uneeded include for ac6
c823e91ff update riscv iar example for latest iar tools
5559d185d check module stack for overlap (not kernel stack)
efa9ce7b7 apply patch from mobileye to fix time slice processing
75fdcb722 Updated copy_armv7_cm.yml
de04b9904 initialize unused MPU settings so that aliasing will work
79b317b60 add config directory to IAR RISC-V port in order to use simulator
This commit is contained in:
Scott Larson
2022-12-16 08:16:32 +00:00
parent b42c5acd8b
commit 4e62226eea
148 changed files with 21660 additions and 50 deletions
Download Patch File Download Diff File Expand all files Collapse all files
common_modules/module_manager/src/txm_module_manager_thread_create.c
+6 -3
View File
@@ -39,7 +39,7 @@
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_thread_create PORTABLE C */
/* 6.1.3 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -91,6 +91,9 @@
/* added 64-bit support, */
/* added SMP support, */
/* resulting in version 6.1.3 */
/* xx-xx-xxxx Scott Larson Check module stack for */
/* overlap, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
UINT _txm_module_manager_thread_create(TX_THREAD *thread_ptr, CHAR *name_ptr,
@@ -158,8 +161,8 @@ ULONG i;
}
/* Check the stack pointer to see if it overlaps with this thread's stack. */
if ((((UCHAR *) ((VOID *) stack_start)) <= ((UCHAR *) ((VOID *) next_thread -> tx_thread_stack_end))) &&
(((UCHAR *) ((VOID *) stack_end)) >= ((UCHAR *) ((VOID *) next_thread -> tx_thread_stack_start))))
if ((((UCHAR *) ((VOID *) stack_start)) <= ((UCHAR *) ((VOID *) next_thread -> tx_thread_module_stack_end))) &&
(((UCHAR *) ((VOID *) stack_end)) >= ((UCHAR *) ((VOID *) next_thread -> tx_thread_module_stack_start))))
{
/* Stacks overlap, clear the stack pointer to force a stack error below. */
stack_start = TX_NULL;
ports/cortex_m0/ac6/src/tx_thread_context_restore.S
+4 -1
View File
@@ -20,6 +20,7 @@
@/**************************************************************************/
@/**************************************************************************/
@
#include "tx_user.h"
@
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
.global _tx_execution_isr_exit
@@ -41,7 +42,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_context_restore Cortex-M0/AC6 */
@/* 6.1 */
@/* 6.x */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -76,6 +77,8 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 09-30-2020 William E. Lamie Initial Version 6.1 */
@/* xx-xx-xxxx Scott Larson Include tx_user.h, */
@/* resulting in version 6.x */
@/* */
@/**************************************************************************/
@VOID _tx_thread_context_restore(VOID)
ports/cortex_m0/ac6/src/tx_thread_context_save.S
+4 -1
View File
@@ -20,6 +20,7 @@
@/**************************************************************************/
@/**************************************************************************/
@
#include "tx_user.h"
@
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
.global _tx_execution_isr_enter
@@ -36,7 +37,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_context_save Cortex-M0/AC6 */
@/* 6.1 */
@/* 6.x */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -70,6 +71,8 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 09-30-2020 William E. Lamie Initial Version 6.1 */
@/* xx-xx-xxxx Scott Larson Include tx_user.h, */
@/* resulting in version 6.x */
@/* */
@/**************************************************************************/
@VOID _tx_thread_context_save(VOID)
ports/cortex_m0/ac6/src/tx_thread_interrupt_control.S
+4 -1
View File
@@ -20,6 +20,7 @@
@/**************************************************************************/
@/**************************************************************************/
#include "tx_user.h"
.text 32
.align 4
@@ -30,7 +31,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_interrupt_control Cortex-M0/AC6 */
@/* 6.1 */
@/* 6.x */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -61,6 +62,8 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 09-30-2020 William E. Lamie Initial Version 6.1 */
@/* xx-xx-xxxx Scott Larson Include tx_user.h, */
@/* resulting in version 6.x */
@/* */
@/**************************************************************************/
@/* UINT _tx_thread_interrupt_control(UINT new_posture)
ports/cortex_m0/ac6/src/tx_thread_interrupt_disable.S
+4 -1
View File
@@ -20,6 +20,7 @@
@/**************************************************************************/
@/**************************************************************************/
#include "tx_user.h"
.text 32
.align 4
@@ -30,7 +31,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_interrupt_disable Cortex-M0/AC6 */
@/* 6.1 */
@/* 6.x */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -60,6 +61,8 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 09-30-2020 William E. Lamie Initial Version 6.1 */
@/* xx-xx-xxxx Scott Larson Include tx_user.h, */
@/* resulting in version 6.x */
@/* */
@/**************************************************************************/
@/* UINT _tx_thread_interrupt_disable(VOID)
ports/cortex_m0/ac6/src/tx_thread_interrupt_restore.S
+4 -1
View File
@@ -20,6 +20,7 @@
@/**************************************************************************/
@/**************************************************************************/
#include "tx_user.h"
.text 32
.align 4
@@ -30,7 +31,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_interrupt_restore Cortex-M0/AC6 */
@/* 6.1 */
@/* 6.x */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -61,6 +62,8 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 09-30-2020 William E. Lamie Initial Version 6.1 */
@/* xx-xx-xxxx Scott Larson Include tx_user.h, */
@/* resulting in version 6.x */
@/* */
@/**************************************************************************/
@/* VOID _tx_thread_interrupt_restore(UINT old_posture)
ports/cortex_m0/ac6/src/tx_thread_schedule.S
+4 -1
View File
@@ -20,6 +20,7 @@
@/**************************************************************************/
@/**************************************************************************/
@
#include "tx_user.h"
@
.global _tx_thread_current_ptr
.global _tx_thread_execute_ptr
@@ -43,7 +44,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_schedule Cortex-M0/AC6 */
@/* 6.1.5 */
@/* 6.x */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -80,6 +81,8 @@
@/* 03-02-2021 Scott Larson Modified comment(s), add */
@/* low power code, */
@/* resulting in version 6.1.5 */
@/* xx-xx-xxxx Scott Larson Include tx_user.h, */
@/* resulting in version 6.x */
@/* */
@/**************************************************************************/
@VOID _tx_thread_schedule(VOID)
ports/cortex_m0/ac6/src/tx_thread_stack_build.S
+4 -1
View File
@@ -20,6 +20,7 @@
@/**************************************************************************/
@/**************************************************************************/
@
#include "tx_user.h"
@
.text
.align 4
@@ -29,7 +30,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_stack_build Cortex-M0/AC6 */
@/* 6.1 */
@/* 6.x */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -62,6 +63,8 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 09-30-2020 William E. Lamie Initial Version 6.1 */
@/* xx-xx-xxxx Scott Larson Include tx_user.h, */
@/* resulting in version 6.x */
@/* */
@/**************************************************************************/
@VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
ports/cortex_m0/ac6/src/tx_thread_system_return.S
+4 -1
View File
@@ -20,6 +20,7 @@
@/**************************************************************************/
@/**************************************************************************/
#include "tx_user.h"
.text
.align 4
@@ -29,7 +30,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_system_return Cortex-M0/AC6 */
@/* 6.1 */
@/* 6.x */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -62,6 +63,8 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 09-30-2020 William E. Lamie Initial Version 6.1 */
@/* xx-xx-xxxx Scott Larson Include tx_user.h, */
@/* resulting in version 6.x */
@/* */
@/**************************************************************************/
@/* VOID _tx_thread_system_return(VOID)
ports/cortex_m0/ac6/src/tx_timer_interrupt.S
+4 -1
View File
@@ -20,6 +20,7 @@
@/**************************************************************************/
@/**************************************************************************/
@
#include "tx_user.h"
@
.global _tx_timer_time_slice
.global _tx_timer_system_clock
@@ -40,7 +41,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_timer_interrupt Cortex-M0/AC6 */
@/* 6.1 */
@/* 6.x */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -75,6 +76,8 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 09-30-2020 William E. Lamie Initial Version 6.1 */
@/* xx-xx-xxxx Scott Larson Include tx_user.h, */
@/* resulting in version 6.x */
@/* */
@/**************************************************************************/
@VOID _tx_timer_interrupt(VOID)
ports/cortex_m0/gnu/src/tx_thread_context_restore.S
+4 -1
View File
@@ -20,6 +20,7 @@
@/**************************************************************************/
@/**************************************************************************/
@
#include "tx_user.h"
@
.global _tx_thread_system_state
.global _tx_thread_current_ptr
@@ -42,7 +43,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_context_restore Cortex-M0/GNU */
@/* 6.1 */
@/* 6.x */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -80,6 +81,8 @@
@/* 09-30-2020 Scott Larson Modified comment(s), and */
@/* cleaned up whitespace, */
@/* resulting in version 6.1 */
@/* xx-xx-xxxx Scott Larson Include tx_user.h, */
@/* resulting in version 6.x */
@/* */
@/**************************************************************************/
@VOID _tx_thread_context_restore(VOID)
ports/cortex_m0/gnu/src/tx_thread_context_save.S
+4 -1
View File
@@ -20,6 +20,7 @@
@/**************************************************************************/
@/**************************************************************************/
@
#include "tx_user.h"
@
.global _tx_thread_system_state
.global _tx_thread_current_ptr
@@ -34,7 +35,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_context_save Cortex-M0/GNU */
@/* 6.1 */
@/* 6.x */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -71,6 +72,8 @@
@/* 09-30-2020 Scott Larson Modified comment(s), and */
@/* cleaned up whitespace, */
@/* resulting in version 6.1 */
@/* xx-xx-xxxx Scott Larson Include tx_user.h, */
@/* resulting in version 6.x */
@/* */
@/**************************************************************************/
@VOID _tx_thread_context_save(VOID)
ports/cortex_m0/gnu/src/tx_thread_interrupt_control.S
+5 -2
View File
@@ -20,6 +20,7 @@
@/**************************************************************************/
@/**************************************************************************/
#include "tx_user.h"
.text 32
.align 4
@@ -30,7 +31,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_interrupt_control Cortex-M0/GNU */
@/* 6.1 */
@/* 6.x */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -62,7 +63,9 @@
@/* */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 09-30-2020 William E. Lamie Modified comment(s), */
@/* resulting in version 6.1 */
@/* resulting in version 6.1 */
@/* xx-xx-xxxx Scott Larson Include tx_user.h, */
@/* resulting in version 6.x */
@/* */
@/**************************************************************************/
@/* UINT _tx_thread_interrupt_control(UINT new_posture)
ports/cortex_m0/gnu/src/tx_thread_interrupt_disable.S
+4 -1
View File
@@ -20,6 +20,7 @@
@/**************************************************************************/
@/**************************************************************************/
#include "tx_user.h"
.text 32
.align 4
@@ -30,7 +31,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_interrupt_disable Cortex-M0/GNU */
@/* 6.1 */
@/* 6.x */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -62,6 +63,8 @@
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 09-30-2020 William E. Lamie Modified comment(s), */
@/* resulting in version 6.1 */
@/* xx-xx-xxxx Scott Larson Include tx_user.h, */
@/* resulting in version 6.x */
@/* */
@/**************************************************************************/
@/* UINT _tx_thread_interrupt_disable(VOID)
ports/cortex_m0/gnu/src/tx_thread_interrupt_restore.S
+5 -2
View File
@@ -20,6 +20,7 @@
@/**************************************************************************/
@/**************************************************************************/
#include "tx_user.h"
.text 32
.align 4
@@ -30,7 +31,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_interrupt_restore Cortex-M0/GNU */
@/* 6.1 */
@/* 6.x */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -62,7 +63,9 @@
@/* */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 09-30-2020 William E. Lamie Modified comment(s), */
@/* resulting in version 6.1 */
@/* resulting in version 6.1 */
@/* xx-xx-xxxx Scott Larson Include tx_user.h, */
@/* resulting in version 6.x */
@/* */
@/**************************************************************************/
@/* VOID _tx_thread_interrupt_restore(UINT old_posture)
ports/cortex_m0/gnu/src/tx_thread_schedule.S
+4 -1
View File
@@ -20,6 +20,7 @@
@/**************************************************************************/
@/**************************************************************************/
@
#include "tx_user.h"
@
.global _tx_thread_current_ptr
.global _tx_thread_execute_ptr
@@ -41,7 +42,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_schedule Cortex-M0/GNU */
@/* 6.1.5 */
@/* 6.x */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -80,6 +81,8 @@
@/* 03-02-2021 Scott Larson Modified comment(s), add */
@/* low power code, */
@/* resulting in version 6.1.5 */
@/* xx-xx-xxxx Scott Larson Include tx_user.h, */
@/* resulting in version 6.x */
@/* */
@/**************************************************************************/
@VOID _tx_thread_schedule(VOID)
ports/cortex_m0/gnu/src/tx_thread_stack_build.S
+4 -1
View File
@@ -20,6 +20,7 @@
@/**************************************************************************/
@/**************************************************************************/
@
#include "tx_user.h"
@
.text
.align 4
@@ -29,7 +30,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_stack_build Cortex-M0/GNU */
@/* 6.1 */
@/* 6.x */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -68,6 +69,8 @@
@/* to stack frame, clean up */
@/* whitespace, resulting */
@/* in version 6.1 */
@/* xx-xx-xxxx Scott Larson Include tx_user.h, */
@/* resulting in version 6.x */
@/* */
@/**************************************************************************/
@VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
ports/cortex_m0/gnu/src/tx_thread_system_return.S
+4 -1
View File
@@ -20,6 +20,7 @@
@/**************************************************************************/
@/**************************************************************************/
#include "tx_user.h"
.text 32
.align 4
@@ -29,7 +30,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_system_return Cortex-M0/GNU */
@/* 6.1 */
@/* 6.x */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -64,6 +65,8 @@
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 09-30-2020 William E. Lamie Modified comment(s), */
@/* resulting in version 6.1 */
@/* xx-xx-xxxx Scott Larson Include tx_user.h, */
@/* resulting in version 6.x */
@/* */
@/**************************************************************************/
@/* VOID _tx_thread_system_return(VOID)
ports/cortex_m0/gnu/src/tx_timer_interrupt.S
+5 -2
View File
@@ -20,6 +20,7 @@
@/**************************************************************************/
@/**************************************************************************/
@
#include "tx_user.h"
@
.global _tx_timer_time_slice
.global _tx_timer_system_clock
@@ -40,7 +41,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_timer_interrupt Cortex-M0/GNU */
@/* 6.1 */
@/* 6.x */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -76,7 +77,9 @@
@/* */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 09-30-2020 William E. Lamie Modified comment(s), */
@/* resulting in version 6.1 */
@/* resulting in version 6.1 */
@/* xx-xx-xxxx Scott Larson Include tx_user.h, */
@/* resulting in version 6.x */
@/* */
@/**************************************************************************/
@VOID _tx_timer_interrupt(VOID)
ports/cortex_m23/ac6/example_build/tx_initialize_low_level.S
+4 -1
View File
@@ -20,6 +20,7 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
SYSTEM_CLOCK = 6000000
SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1)
@@ -34,7 +35,7 @@ HEAP_SIZE = 0x00000000
/* FUNCTION RELEASE */
/* */
/* _tx_initialize_low_level Cortex-M23/AC6 */
/* 6.1 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -68,6 +69,8 @@ HEAP_SIZE = 0x00000000
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// VOID _tx_initialize_low_level(VOID)
ports/cortex_m23/ac6/src/tx_misra.S
+2
View File
@@ -20,6 +20,8 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
#define SHT_PROGBITS 0x1
.global __aeabi_memset
ports/cortex_m23/ac6/src/tx_thread_context_restore.s → ports/cortex_m23/ac6/src/tx_thread_context_restore.S
+5 -1
View File
@@ -20,6 +20,8 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
.global _tx_execution_isr_exit
#endif
@@ -28,7 +30,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_restore Cortex-M23/AC6 */
/* 6.1 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -58,6 +60,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// VOID _tx_thread_context_restore(VOID)
ports/cortex_m23/ac6/src/tx_thread_context_save.s → ports/cortex_m23/ac6/src/tx_thread_context_save.S
+5 -1
View File
@@ -20,6 +20,8 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
.global _tx_execution_isr_enter
#endif
@@ -28,7 +30,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_save Cortex-M23/AC6 */
/* 6.1 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -58,6 +60,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// VOID _tx_thread_context_save(VOID)
ports/cortex_m23/ac6/src/tx_thread_interrupt_control.s → ports/cortex_m23/ac6/src/tx_thread_interrupt_control.S
+4 -1
View File
@@ -20,13 +20,14 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_control Cortex-M23/AC6 */
/* 6.1 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -57,6 +58,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// UINT _tx_thread_interrupt_control(UINT new_posture)
ports/cortex_m23/ac6/src/tx_thread_interrupt_disable.s → ports/cortex_m23/ac6/src/tx_thread_interrupt_disable.S
+4 -1
View File
@@ -20,13 +20,14 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_disable Cortex-M23/AC6 */
/* 6.1 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -57,6 +58,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// UINT _tx_thread_interrupt_disable(VOID)
ports/cortex_m23/ac6/src/tx_thread_interrupt_restore.s → ports/cortex_m23/ac6/src/tx_thread_interrupt_restore.S
+4 -1
View File
@@ -20,13 +20,14 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_restore Cortex-M23/AC6 */
/* 6.1 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -57,6 +58,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// VOID _tx_thread_interrupt_restore(UINT previous_posture)
ports/cortex_m23/ac6/src/tx_thread_schedule.s → ports/cortex_m23/ac6/src/tx_thread_schedule.S
+4 -1
View File
@@ -20,6 +20,7 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
.global _tx_execution_thread_enter
@@ -30,7 +31,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_schedule Cortex-M23/AC6 */
/* 6.1.6 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -69,6 +70,8 @@
/* 06-02-2021 Scott Larson Added secure stack initialize */
/* in SVC handler, */
/* resulting in version 6.1.7 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// VOID _tx_thread_schedule(VOID)
ports/cortex_m23/ac6/src/tx_thread_secure_stack_allocate.s → ports/cortex_m23/ac6/src/tx_thread_secure_stack_allocate.S
+4 -1
View File
@@ -20,13 +20,14 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_secure_stack_allocate Cortex-M23/AC6 */
/* 6.1 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -58,6 +59,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size)
ports/cortex_m23/ac6/src/tx_thread_secure_stack_free.s → ports/cortex_m23/ac6/src/tx_thread_secure_stack_free.S
+4 -1
View File
@@ -20,13 +20,14 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_secure_stack_free Cortex-M23/AC6 */
/* 6.1 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -56,6 +57,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr)
ports/cortex_m23/ac6/src/tx_thread_secure_stack_initialize.S
+4 -1
View File
@@ -20,13 +20,14 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_secure_stack_initialize Cortex-M23/AC6 */
/* 6.1.12 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -60,6 +61,8 @@
/* secure stack initialization */
/* macro to port-specific, */
/* resulting in version 6.1.12 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// VOID _tx_thread_secure_stack_initialize(VOID)
ports/cortex_m23/ac6/src/tx_thread_stack_build.s → ports/cortex_m23/ac6/src/tx_thread_stack_build.S
+4 -1
View File
@@ -20,13 +20,14 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_stack_build Cortex-M23/AC6 */
/* 6.1 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -59,6 +60,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
ports/cortex_m23/ac6/src/tx_thread_system_return.s → ports/cortex_m23/ac6/src/tx_thread_system_return.S
+4 -1
View File
@@ -20,13 +20,14 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_system_return Cortex-M23/AC6 */
/* 6.1 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -59,6 +60,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// VOID _tx_thread_system_return(VOID)
ports/cortex_m23/ac6/src/tx_timer_interrupt.s → ports/cortex_m23/ac6/src/tx_timer_interrupt.S
+4 -1
View File
@@ -20,13 +20,14 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_timer_interrupt Cortex-M23/AC6 */
/* 6.1 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -60,6 +61,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// VOID _tx_timer_interrupt(VOID)
ports/cortex_m23/gnu/src/tx_initialize_low_level.S
+4 -1
View File
@@ -20,6 +20,7 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
SYSTEM_CLOCK = 6000000
SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1)
@@ -34,7 +35,7 @@ HEAP_SIZE = 0x00000000
/* FUNCTION RELEASE */
/* */
/* _tx_initialize_low_level Cortex-M23/GNU */
/* 6.1 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -68,6 +69,8 @@ HEAP_SIZE = 0x00000000
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// VOID _tx_initialize_low_level(VOID)
ports/cortex_m23/gnu/src/tx_misra.S
+2
View File
@@ -20,6 +20,8 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
#define SHT_PROGBITS 0x1
.global __aeabi_memset
ports/cortex_m23/gnu/src/tx_thread_context_restore.s → ports/cortex_m23/gnu/src/tx_thread_context_restore.S
+5 -1
View File
@@ -20,6 +20,8 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
.global _tx_execution_isr_exit
#endif
@@ -28,7 +30,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_restore Cortex-M23/GNU */
/* 6.1 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -58,6 +60,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// VOID _tx_thread_context_restore(VOID)
ports/cortex_m23/gnu/src/tx_thread_context_save.s → ports/cortex_m23/gnu/src/tx_thread_context_save.S
+5 -1
View File
@@ -20,6 +20,8 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
.global _tx_execution_isr_enter
#endif
@@ -28,7 +30,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_save Cortex-M23/GNU */
/* 6.1 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -58,6 +60,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// VOID _tx_thread_context_save(VOID)
ports/cortex_m23/gnu/src/tx_thread_interrupt_control.s → ports/cortex_m23/gnu/src/tx_thread_interrupt_control.S
+4 -1
View File
@@ -20,13 +20,14 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_control Cortex-M23/GNU */
/* 6.1 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -57,6 +58,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// UINT _tx_thread_interrupt_control(UINT new_posture)
ports/cortex_m23/gnu/src/tx_thread_interrupt_disable.s → ports/cortex_m23/gnu/src/tx_thread_interrupt_disable.S
+4 -1
View File
@@ -20,13 +20,14 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_disable Cortex-M23/GNU */
/* 6.1 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -57,6 +58,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// UINT _tx_thread_interrupt_disable(VOID)
ports/cortex_m23/gnu/src/tx_thread_interrupt_restore.s → ports/cortex_m23/gnu/src/tx_thread_interrupt_restore.S
+4 -1
View File
@@ -20,13 +20,14 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_restore Cortex-M23/GNU */
/* 6.1 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -57,6 +58,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// VOID _tx_thread_interrupt_restore(UINT previous_posture)
ports/cortex_m23/gnu/src/tx_thread_schedule.s → ports/cortex_m23/gnu/src/tx_thread_schedule.S
+4 -1
View File
@@ -20,13 +20,14 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_schedule Cortex-M23/GNU */
/* 6.1.6 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -65,6 +66,8 @@
/* 06-02-2021 Scott Larson Added secure stack initialize */
/* in SVC handler, */
/* resulting in version 6.1.7 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// VOID _tx_thread_schedule(VOID)
ports/cortex_m23/gnu/src/tx_thread_secure_stack_allocate.s → ports/cortex_m23/gnu/src/tx_thread_secure_stack_allocate.S
+4 -1
View File
@@ -20,13 +20,14 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_secure_stack_allocate Cortex-M23/GNU */
/* 6.1 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -58,6 +59,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size)
ports/cortex_m23/gnu/src/tx_thread_secure_stack_free.s → ports/cortex_m23/gnu/src/tx_thread_secure_stack_free.S
+4 -1
View File
@@ -20,13 +20,14 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_secure_stack_free Cortex-M23/GNU */
/* 6.1 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -56,6 +57,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr)
ports/cortex_m23/gnu/src/tx_thread_secure_stack_initialize.S
+4 -1
View File
@@ -20,13 +20,14 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_secure_stack_initialize Cortex-M23/GNU */
/* 6.1.12 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -60,6 +61,8 @@
/* secure stack initialization */
/* macro to port-specific, */
/* resulting in version 6.1.12 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// VOID _tx_thread_secure_stack_initialize(VOID)
ports/cortex_m23/gnu/src/tx_thread_stack_build.s → ports/cortex_m23/gnu/src/tx_thread_stack_build.S
+4 -1
View File
@@ -20,13 +20,14 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_stack_build Cortex-M23/GNU */
/* 6.1 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -59,6 +60,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
ports/cortex_m23/gnu/src/tx_thread_system_return.s → ports/cortex_m23/gnu/src/tx_thread_system_return.S
+4 -1
View File
@@ -20,13 +20,14 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_system_return Cortex-M23/GNU */
/* 6.1 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -59,6 +60,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// VOID _tx_thread_system_return(VOID)
ports/cortex_m23/gnu/src/tx_timer_interrupt.s → ports/cortex_m23/gnu/src/tx_timer_interrupt.S
+4 -1
View File
@@ -20,13 +20,14 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_timer_interrupt Cortex-M23/GNU */
/* 6.1 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -60,6 +61,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// VOID _tx_timer_interrupt(VOID)
ports/xtensa/xcc/inc/xtensa_context.h
+2
View File
@@ -427,9 +427,11 @@ XSTRUCT_END(XtExcFrame)
addi a10, a1, -XT_STK_FRMSZ
s32i a10, a11, tx_thread_stack_ptr // save outgoing thread stack pointer
l32i a10, a12, 0 // a10 <- _tx_timer_time_slice
beqz a10, .Ldont_save_ts
s32i a10, a11, tx_thread_time_slice // save outgoing time slice value
movi a10, 0
s32i a10, a12, 0 // disable time slice
.Ldont_save_ts:
s32i a10, a11, tx_thread_solicited // mark as preempted
s32i a10, a8, 0 // Clear _tx_thread_current_ptr
#if XCHAL_CP_NUM > 0
ports_smp/mips32_interaptiv_smp/gnu/example_build/boot.h
+99
View File
@@ -0,0 +1,99 @@
/*
* boot.h
*
* Created on: Jan 12, 2011
* Author: MIPS TECHNOLOGIES, INC
*/
/*
Unpublished work (c) MIPS Technologies, Inc. All rights reserved. Unpublished rights reserved
under the copyright laws of the United States of America and other countries.
This code is confidential and proprietary to MIPS Technologies, Inc. ("MIPS Technologies") and
may be disclosed only as permitted in writing by MIPS Technologies or an authorized third party.
Any copying, reproducing, modifying, use or disclosure of this code (in whole or in part) that is
not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly
prohibited. At a minimum, this code is protected under trade secret, unfair competition, and
copyright laws. Violations thereof may result in criminal penalties and fines.
MIPS Technologies reserves the right to change this code to improve function, design or
otherwise. MIPS Technologies does not assume any liability arising out of the application or use
of this code, or of any error or omission in such code. Any warranties, whether express, statutory,
implied or otherwise, including but not limited to the implied warranties of merchantability or
fitness for a particular purpose, are excluded. Except as expressly provided in any written license
agreement from MIPS Technologies or an authorized third party, the furnishing of this code does
not give recipient any license to any intellectual property rights, including any patent rights, that
cover this code.
This code shall not be exported, reexported, transferred, or released, directly or indirectly, in
violation of the law of any country or international law, regulation, treaty, Executive Order,
statute, amendments or supplements thereto. Should a conflict arise regarding the export,
reexport, transfer, or release of this code, the laws of the United States of America shall be
the governing law.
This code may only be disclosed to the United States government ("Government"), or to
Government users, with prior written consent from MIPS Technologies or an authorized third
party. This code constitutes one or more of the following: commercial computer software,
commercial computer software documentation or other commercial items. If the user of this
code, or any related documentation of any kind, including related technical data or manuals, is an
agency, department, or other entity of the Government, the use, duplication, reproduction, release,
modification, disclosure, or transfer of this code, or any related documentation of any kind, is
restricted in accordance with Federal Acquisition Regulation 12.212 for civilian agencies and
Defense Federal Acquisition Regulation Supplement 227.7202 for military agencies. The use of
this code by the Government is further restricted in accordance with the terms of the license
agreement(s) and/or applicable contract terms and conditions covering this code from MIPS
Technologies or an authorized third party.
*/
#define LEAF(name)\
.##text;\
.##globl name;\
.##ent name;\
name:
#define END(name)\
.##size name,.-name;\
.##end name
#define GCR_CONFIG_ADDR 0xbfbf8000 // KSEG0 address of the GCR registers
#define GIC_P_BASE_ADDR 0x1bdc0000 // physical address of the GIC
#define GIC_BASE_ADDR 0xbbdc0000 // KSEG0 address address of the GIC
#define CPC_P_BASE_ADDR 0x1bde0001 // physical address of the CPC
#define CPC_BASE_ADDR 0xbbde0000 // KSEG0 address address of the CPC
#define DENALI_CTL_SECTION 0xbbc00000
#define MALTA_DISP_ADDR 0xbf000410
#define STACK_BASE_ADDR 0x82000000 /* Change: Base on memory size. */
#define STACK_SIZE_LOG2 22 /* 4Mbytes each */
/**************************************************************************************
Register use while executing in this file: ("GLOBAL" denotes a common value.)
**************************************************************************************/
#define r1_all_ones $1 /* at Will hold 0xffffffff to simplify bit insertion of 1's. GLOBAL! */
// $2 - $7 (v0, v1 a0 - a3) reserved for program use
#define r8_core_num $8 /* t0 Core number. Only core 0 is active after reset. */
#define r9_vpe_num $9 /* t1 MT ASE VPE number that this TC is bound to (0 if non-MT.) */
#define r10_has_mt_ase $10 /* t2 Core implements the MT ASE. */
#define r11_is_cps $11 /* t3 Core is part of a Coherent Processing System. */
// $12 - $15 (t4 - t7) are free to use
// $16, $17 (s0 and s1) reserved for program use
#define r18_tc_num $18 /* s2 MT ASE TC number (0 if non-MT.) */
#define r19_more_cores $19 /* s3 Number of cores in CPS in addition to core 0. GLOBAL! */
#define r20_more_vpes $20 /* s4 Number of vpes in this core in addition to vpe 0. */
#define r21_more_tcs $21 /* s5 Number of tcs in vpe in addition to the first. */
#define r22_gcr_addr $22 /* s6 Uncached (kseg1) base address of the Global Config Registers. */
#define r23_cpu_num $23 /* s7 Unique per vpe "cpu" identifier (CP0 EBase[CPUNUM]). */
#define r24_malta_word $24 /* t8 Uncached (kseg1) base address of Malta ascii display. GLOBAL! */
#define r25_coreid $25 /* t9 Copy of cp0 PRiD GLOBAL! */
#define r26_int_addr $26 /* k0 Interrupt handler scratch address. */
#define r27_int_data $27 /* k1 Interrupt handler scratch data. */
// $28 gp and $29 sp
#define r30_cpc_addr $30 /* s8 Address of CPC register block after cpc_init. 0 indicates no CPC. */
// $31 ra
ports_smp/mips32_interaptiv_smp/gnu/example_build/build_threadx.bat
+247
View File
File diff suppressed because it is too large Load Diff
ports_smp/mips32_interaptiv_smp/gnu/example_build/build_threadx_demo.bat
+20
View File
@@ -0,0 +1,20 @@
mips-sde-elf-gcc -c -g -mmt -EL -I. copy_c2_ram.S
mips-sde-elf-gcc -c -g -mmt -EL -I. demo_threadx.c
mips-sde-elf-gcc -c -g -mmt -EL -I. start.S
mips-sde-elf-gcc -c -g -mmt -EL -I. set_gpr_boot_values.S
mips-sde-elf-gcc -c -g -mmt -EL -I. init_gpr.S
mips-sde-elf-gcc -c -g -mmt -EL -I. init_tlb.S
mips-sde-elf-gcc -c -g -mmt -EL -I. init_itc.S
mips-sde-elf-gcc -c -g -mmt -EL -I. init_caches2.S
mips-sde-elf-gcc -c -g -mmt -EL -I. init_cp0.S
mips-sde-elf-gcc -c -g -mmt -EL -I. init_cm.S
mips-sde-elf-gcc -c -g -mmt -EL -I. release_mp.S
mips-sde-elf-gcc -c -g -mmt -EL -I. join_domain.S
mips-sde-elf-gcc -c -g -mmt -EL -I. init_gic.S
mips-sde-elf-gcc -c -g -mmt -EL -I. init_cpc.S
mips-sde-elf-gcc -c -g -mmt -EL -I. init_vpe1.S
mips-sde-elf-gcc -c -g -mmt -EL -I. init_CoreFPGA6_mem.S
mips-sde-elf-ld -EL copy_c2_ram.o start.o set_gpr_boot_values.o init_gpr.o init_tlb.o init_itc.o init_caches2.o init_cp0.o init_cm.o release_mp.o join_domain.o init_gic.o init_cpc.o init_vpe1.o demo_threadx.o libc.a tx.a -T demo_threadx.ld -o demo_threadx.out -M > demo_threadx.map
mips-sde-elf-objcopy -O srec demo_threadx.out demo_threadx.srec
ports_smp/mips32_interaptiv_smp/gnu/example_build/copy_c2_ram.S
+115
View File
@@ -0,0 +1,115 @@
/*
* copy_c2_ram.S
*
* Created on: Jan 12, 2011
* Author: MIPS TECHNOLOGIES, INC
* Copy code and data to ram then clear BSS
*/
/*
Unpublished work (c) MIPS Technologies, Inc. All rights reserved. Unpublished rights reserved
under the copyright laws of the United States of America and other countries.
This code is confidential and proprietary to MIPS Technologies, Inc. ("MIPS Technologies") and
may be disclosed only as permitted in writing by MIPS Technologies or an authorized third party.
Any copying, reproducing, modifying, use or disclosure of this code (in whole or in part) that is
not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly
prohibited. At a minimum, this code is protected under trade secret, unfair competition, and
copyright laws. Violations thereof may result in criminal penalties and fines.
MIPS Technologies reserves the right to change this code to improve function, design or
otherwise. MIPS Technologies does not assume any liability arising out of the application or use
of this code, or of any error or omission in such code. Any warranties, whether express, statutory,
implied or otherwise, including but not limited to the implied warranties of merchantability or
fitness for a particular purpose, are excluded. Except as expressly provided in any written license
agreement from MIPS Technologies or an authorized third party, the furnishing of this code does
not give recipient any license to any intellectual property rights, including any patent rights, that
cover this code.
This code shall not be exported, reexported, transferred, or released, directly or indirectly, in
violation of the law of any country or international law, regulation, treaty, Executive Order,
statute, amendments or supplements thereto. Should a conflict arise regarding the export,
reexport, transfer, or release of this code, the laws of the United States of America shall be
the governing law.
This code may only be disclosed to the United States government ("Government"), or to
Government users, with prior written consent from MIPS Technologies or an authorized third
party. This code constitutes one or more of the following: commercial computer software,
commercial computer software documentation or other commercial items. If the user of this
code, or any related documentation of any kind, including related technical data or manuals, is an
agency, department, or other entity of the Government, the use, duplication, reproduction, release,
modification, disclosure, or transfer of this code, or any related documentation of any kind, is
restricted in accordance with Federal Acquisition Regulation 12.212 for civilian agencies and
Defense Federal Acquisition Regulation Supplement 227.7202 for military agencies. The use of
this code by the Government is further restricted in accordance with the terms of the license
agreement(s) and/or applicable contract terms and conditions covering this code from MIPS
Technologies or an authorized third party.
*/
#include <regdef.h>
#include <boot.h>
#define s1_all_ones s1 /* at Will hold 0xffffffff to simplify bit insertion of 1's. */
#define a0_temp_data a0 /* a0 data to be moved */
#define a1_temp_addr a1 /* from address */
#define a2_temp_dest a2 /* to address */
#define a3_temp_mark a3 /* ending address */
.set noreorder # Don't allow the assembler to reorder instructions.
.set noat # Don't allow the assembler to use r1(at) for synthetic instr.
/**************************************************************************************
**************************************************************************************/
LEAF(copy_c2_ram)
li s1_all_ones, 0xffffffff
/* RAMHACK: Link addr == load addr. No copy of code from ROM to RAM required.
// Copy code and read-only/initialized data from FLASH to (uncached) RAM.
la a1_temp_addr, _zap1
ins a1_temp_addr, s1_all_ones, 29, 1
la a2_temp_dest, _ftext_ram
ins a2_temp_dest, s1_all_ones, 29, 1
la a3_temp_mark, _edata_ram
ins a3_temp_mark, s1_all_ones, 29, 1
beq a2_temp_dest, a3_temp_mark, zero_bss
nop
next_ram_word:
lw a0_temp_data, 0(a1_temp_addr)
sw a0_temp_data, 0(a2_temp_dest)
addiu a2_temp_dest, 4
bne a3_temp_mark, a2_temp_dest, next_ram_word
addiu a1_temp_addr, 4
*/
// RAMHACK: Zero sbss in addition to bss.
zero_sbss:
la a1_temp_addr, _start_sbss
ins a1_temp_addr, s1_all_ones, 29, 1
la a3_temp_mark, _end_sbss
ins a3_temp_mark, s1_all_ones, 29, 1
beq a1_temp_addr, a3_temp_mark, zero_bss
nop
next_sbss_word:
sw zero, 0(a1_temp_addr)
addiu a1_temp_addr, 4
bne a1_temp_addr, a3_temp_mark, next_sbss_word
nop
zero_bss:
la a1_temp_addr, _start_bss
ins a1_temp_addr, s1_all_ones, 29, 1
la a3_temp_mark, _end_bss
ins a3_temp_mark, s1_all_ones, 29, 1
beq a1_temp_addr, a3_temp_mark, copy_c2_ram_done
nop
next_bss_word:
sw zero, 0(a1_temp_addr)
addiu a1_temp_addr, 4
bne a1_temp_addr, a3_temp_mark, next_bss_word
nop
copy_c2_ram_done:
jr ra
nop
END(copy_c2_ram)
ports_smp/mips32_interaptiv_smp/gnu/example_build/cps.h
+883
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ports_smp/mips32_interaptiv_smp/gnu/example_build/demo_threadx.c
+514
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ports_smp/mips32_interaptiv_smp/gnu/example_build/demo_threadx.ld
+109
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@@ -0,0 +1,109 @@
OUTPUT_ARCH(mips)
/**** Start point ****/
ENTRY(_start) /* Entry point of application */
SECTIONS
{
/**** Code and read-only data ****/
.vector_0x000 0x80000000 :
{
}
.vector_0x100 0x80000100 :
{
}
.vector_0x180 0x80000180 :
{
}
.vector_0x200 0x80000200 :
{
}
.vector_0x280 0x80000280 :
{
}
.vector_0x300 0x80000300 :
{
}
.text 0x80100000 :
{
_ftext = ABSOLUTE(.) ; /* Start of code and read-only data */
start.o(.text) /* Reset entry point */
*(.text*)
_ecode = ABSOLUTE(.) ; /* End of code */
*(.rodata*)
. = ALIGN(8);
_etext = ABSOLUTE(.) ; /* End of code and read-only data */
} = 0
/**** Initialised data ****/
.data :
{
_fdata = ABSOLUTE(.); /* Start of initialised data */
*(.data*)
. = ALIGN(8);
_gp = ABSOLUTE(. + 0x7ff0); /* Base of small data */
LC8 = ABSOLUTE(. + 0x7ff0); /* Base of small data */
*(.lit8)
*(.lit4)
*(.sdata*)
. = ALIGN(8);
_edata = ABSOLUTE(.) ; /* End of initialised data */
}
/**** Uninitialised data ****/
.sbss :
{
_start_sbss = .;
*(.sbss*)
*(.scommon)
_end_sbss = .;
}
.bss :
{
_start_bss = .;
*(.bss*)
*(COMMON)
_ebss = ABSOLUTE(.) ;
_end_bss = .;
}
.stack _ebss :
{
/* Allocate room for stack */
. = ALIGN(8) ;
. += 4096 ;
_sp = . - 16 ;
_stack_top = ABSOLUTE(.) ;
}
_free_memory = _stack_top + 4 ;
.gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }
.gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }
/DISCARD/ :
{
*(.reginfo)
}
PROVIDE(etext = _etext);
PROVIDE (end = _stack_top);
}
ports_smp/mips32_interaptiv_smp/gnu/example_build/init_CoreFPGA6_mem.S
+69
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@@ -0,0 +1,69 @@
/*
* init_CoreFPGA5mem.S
*
* Created on: Jun 4, 2012
* Author: chrisr
*/
/*
Unpublished work (c) MIPS Technologies, Inc. All rights reserved. Unpublished rights reserved
under the copyright laws of the United States of America and other countries.
This code is confidential and proprietary to MIPS Technologies, Inc. ("MIPS Technologies") and
may be disclosed only as permitted in writing by MIPS Technologies or an authorized third party.
Any copying, reproducing, modifying, use or disclosure of this code (in whole or in part) that is
not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly
prohibited. At a minimum, this code is protected under trade secret, unfair competition, and
copyright laws. Violations thereof may result in criminal penalties and fines.
MIPS Technologies reserves the right to change this code to improve function, design or
otherwise. MIPS Technologies does not assume any liability arising out of the application or use
of this code, or of any error or omission in such code. Any warranties, whether express, statutory,
implied or otherwise, including but not limited to the implied warranties of merchantability or
fitness for a particular purpose, are excluded. Except as expressly provided in any written license
agreement from MIPS Technologies or an authorized third party, the furnishing of this code does
not give recipient any license to any intellectual property rights, including any patent rights, that
cover this code.
This code shall not be exported, reexported, transferred, or released, directly or indirectly, in
violation of the law of any country or international law, regulation, treaty, Executive Order,
statute, amendments or supplements thereto. Should a conflict arise regarding the export,
reexport, transfer, or release of this code, the laws of the United States of America shall be
the governing law.
This code may only be disclosed to the United States government ("Government"), or to
Government users, with prior written consent from MIPS Technologies or an authorized third
party. This code constitutes one or more of the following: commercial computer software,
commercial computer software documentation or other commercial items. If the user of this
code, or any related documentation of any kind, including related technical data or manuals, is an
agency, department, or other entity of the Government, the use, duplication, reproduction, release,
modification, disclosure, or transfer of this code, or any related documentation of any kind, is
restricted in accordance with Federal Acquisition Regulation 12.212 for civilian agencies and
Defense Federal Acquisition Regulation Supplement 227.7202 for military agencies. The use of
this code by the Government is further restricted in accordance with the terms of the license
agreement(s) and/or applicable contract terms and conditions covering this code from MIPS
Technologies or an authorized third party.
*/
#include <regdef.h>
#include <boot.h>
.set noreorder # Don't allow the assembler to reorder instructions.
/**************************************************************************************
Wait for the controller to startup. Then its good to go!
**************************************************************************************/
LEAF(init_CoreFPGA6_mem)
/* Wait for MIG to init */
la a0, 0xbbc00004
1:
/* RAMHACK: The read of Xilinx DRAM controller reg while executig from DRAM causing bad fetch?
lw a2, 0(a0)
andi a2, 0x1
beqz a2, 1b
nop
*/
jr ra
nop
END(init_CoreFPGA6_mem)
ports_smp/mips32_interaptiv_smp/gnu/example_build/init_L23caches.S
+215
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ports_smp/mips32_interaptiv_smp/gnu/example_build/init_caches2.S
+252
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ports_smp/mips32_interaptiv_smp/gnu/example_build/init_cm.S
+86
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@@ -0,0 +1,86 @@
/*
* init_cm.S
*
* Created on: Jan 12, 2011
* Author: MIPS TECHNOLOGIES, INC
* initializatoin of the Coherency Manager
*/
/*
Unpublished work (c) MIPS Technologies, Inc. All rights reserved. Unpublished rights reserved
under the copyright laws of the United States of America and other countries.
This code is confidential and proprietary to MIPS Technologies, Inc. ("MIPS Technologies") and
may be disclosed only as permitted in writing by MIPS Technologies or an authorized third party.
Any copying, reproducing, modifying, use or disclosure of this code (in whole or in part) that is
not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly
prohibited. At a minimum, this code is protected under trade secret, unfair competition, and
copyright laws. Violations thereof may result in criminal penalties and fines.
MIPS Technologies reserves the right to change this code to improve function, design or
otherwise. MIPS Technologies does not assume any liability arising out of the application or use
of this code, or of any error or omission in such code. Any warranties, whether express, statutory,
implied or otherwise, including but not limited to the implied warranties of merchantability or
fitness for a particular purpose, are excluded. Except as expressly provided in any written license
agreement from MIPS Technologies or an authorized third party, the furnishing of this code does
not give recipient any license to any intellectual property rights, including any patent rights, that
cover this code.
This code shall not be exported, reexported, transferred, or released, directly or indirectly, in
violation of the law of any country or international law, regulation, treaty, Executive Order,
statute, amendments or supplements thereto. Should a conflict arise regarding the export,
reexport, transfer, or release of this code, the laws of the United States of America shall be
the governing law.
This code may only be disclosed to the United States government ("Government"), or to
Government users, with prior written consent from MIPS Technologies or an authorized third
party. This code constitutes one or more of the following: commercial computer software,
commercial computer software documentation or other commercial items. If the user of this
code, or any related documentation of any kind, including related technical data or manuals, is an
agency, department, or other entity of the Government, the use, duplication, reproduction, release,
modification, disclosure, or transfer of this code, or any related documentation of any kind, is
restricted in accordance with Federal Acquisition Regulation 12.212 for civilian agencies and
Defense Federal Acquisition Regulation Supplement 227.7202 for military agencies. The use of
this code by the Government is further restricted in accordance with the terms of the license
agreement(s) and/or applicable contract terms and conditions covering this code from MIPS
Technologies or an authorized third party.
*/
#include <boot.h>
#include <regdef.h>
#include <cps.h>
.set noreorder // Don't allow the assembler to reorder instructions.
.set noat // Don't allow the assembler to use r1(at) for synthetic instr.
/**************************************************************************************
**************************************************************************************/
LEAF(init_cm)
beqz r11_is_cps, done_cm_init // skip if not a CPS or CM register verification failed.
nop
// Allow each core access to the CM registers (they should only access their local registers.)
li a0, 2 // Start building mask for cores in this cps.
sll a0, a0, r19_more_cores
addiu a0, -1 // Complete mask.
sw a0, GCR_ACCESS(r22_gcr_addr) // GCR_ACCESS
// Check to see if this CPS implements an IOCU.
lw a0, GCR_CONFIG(r22_gcr_addr) // Load GCR_CONFIG
ext a0, a0, NUMIOCU, NUMIOCU_S // Extract NUMIOCU.
beqz a0, done_cm_init
lui a0, 0xffff
// Disable the CM regions if there is an IOCU.
sw a0, GCR_REG0_BASE(r22_gcr_addr) // GCR_REG0_BASE
sw a0, GCR_REG0_MASK(r22_gcr_addr) // GCR_REG0_MASK
sw a0, GCR_REG1_BASE(r22_gcr_addr) // GCR_REG1_BASE
sw a0, GCR_REG1_MASK(r22_gcr_addr) // GCR_REG1_MASK
sw a0, GCR_REG2_BASE(r22_gcr_addr) // GCR_REG2_BASE
sw a0, GCR_REG2_MASK(r22_gcr_addr) // GCR_REG2_MASK
sw a0, GCR_REG3_BASE(r22_gcr_addr) // GCR_REG3_BASE
sw a0, GCR_REG3_MASK(r22_gcr_addr) // GCR_REG3_MASK
done_cm_init:
jr ra
nop
END(init_cm)
ports_smp/mips32_interaptiv_smp/gnu/example_build/init_cp0.S
+119
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@@ -0,0 +1,119 @@
/*
* initcp0.S
*
* Created on: Jan 12, 2011
* Author: MIPS TECHNOLOGIES, INC
* Common CP0 register initializations
*/
/*
Unpublished work (c) MIPS Technologies, Inc. All rights reserved. Unpublished rights reserved
under the copyright laws of the United States of America and other countries.
This code is confidential and proprietary to MIPS Technologies, Inc. ("MIPS Technologies") and
may be disclosed only as permitted in writing by MIPS Technologies or an authorized third party.
Any copying, reproducing, modifying, use or disclosure of this code (in whole or in part) that is
not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly
prohibited. At a minimum, this code is protected under trade secret, unfair competition, and
copyright laws. Violations thereof may result in criminal penalties and fines.
MIPS Technologies reserves the right to change this code to improve function, design or
otherwise. MIPS Technologies does not assume any liability arising out of the application or use
of this code, or of any error or omission in such code. Any warranties, whether express, statutory,
implied or otherwise, including but not limited to the implied warranties of merchantability or
fitness for a particular purpose, are excluded. Except as expressly provided in any written license
agreement from MIPS Technologies or an authorized third party, the furnishing of this code does
not give recipient any license to any intellectual property rights, including any patent rights, that
cover this code.
This code shall not be exported, reexported, transferred, or released, directly or indirectly, in
violation of the law of any country or international law, regulation, treaty, Executive Order,
statute, amendments or supplements thereto. Should a conflict arise regarding the export,
reexport, transfer, or release of this code, the laws of the United States of America shall be
the governing law.
This code may only be disclosed to the United States government ("Government"), or to
Government users, with prior written consent from MIPS Technologies or an authorized third
party. This code constitutes one or more of the following: commercial computer software,
commercial computer software documentation or other commercial items. If the user of this
code, or any related documentation of any kind, including related technical data or manuals, is an
agency, department, or other entity of the Government, the use, duplication, reproduction, release,
modification, disclosure, or transfer of this code, or any related documentation of any kind, is
restricted in accordance with Federal Acquisition Regulation 12.212 for civilian agencies and
Defense Federal Acquisition Regulation Supplement 227.7202 for military agencies. The use of
this code by the Government is further restricted in accordance with the terms of the license
agreement(s) and/or applicable contract terms and conditions covering this code from MIPS
Technologies or an authorized third party.
*/
#include <boot.h>
#include <regdef.h>
#include <m32c0.h>
.set noreorder // Don't allow the assembler to reorder instructions.
.set noat // Don't allow the assembler to use r1(at) for synthetic instr.
/**************************************************************************************
**************************************************************************************/
LEAF(init_cp0)
// Initialize Status
// RAMHACK: Use RAM (Status.BEV == 0) exception vectors.
// li v1, 0x00400404 // (M_StatusIM | M_StatusERL | M_StatusBEV)
li v1, 0x00000404 // (M_StatusIM | M_StatusERL)
mtc0 v1, C0_STATUS // write C0_Status
// Initialize Watch registers if implemented.
mfc0 v0, C0_CONFIG1 // read C0_Config1
ext v1, v0, 3, 1 // extract bit 3 WR (Watch registers implemented)
beq v1, zero, done_wr
li v1, 0x7 // (M_WatchHiI | M_WatchHiR | M_WatchHiW)
// Clear Watch Status bits and disable watch exceptions
mtc0 v1, C0_WATCHHI // write C0_WatchHi0
mfc0 v0, C0_WATCHHI // read C0_WatchHi0
bgez v0, done_wr // Check for bit 31 (sign bit) for more Watch registers
mtc0 zero, C0_WATCHLO // write C0_WatchLo0
mtc0 v1, C0_WATCHHI, 1 // write C0_WatchHi1
mfc0 v0, C0_WATCHHI, 1 // read C0_WatchHi1
bgez v0, done_wr // Check for bit 31 (sign bit) for more Watch registers
mtc0 zero, C0_WATCHLO, 1 // write C0_WatchLo1
mtc0 v1, C0_WATCHHI, 2 // write C0_WatchHi2
mfc0 v0, C0_WATCHHI, 2 // read C0_WatchHi2
bgez v0, done_wr // Check for bit 31 (sign bit) for more Watch registers
mtc0 zero, C0_WATCHLO, 2 // write C0_WatchLo2
mtc0 v1, C0_WATCHHI, 3 // write C0_WatchHi3
mfc0 v0, C0_WATCHHI, 3 // read C0_WatchHi3
bgez v0, done_wr // Check for bit 31 (sign bit) for more Watch registers
mtc0 zero, C0_WATCHLO, 3 // write C0_WatchLo3
mtc0 v1, C0_WATCHHI, 4 // write C0_WatchHi4
mfc0 v0, C0_WATCHHI, 4 // read C0_WatchHi4
bgez v0, done_wr // Check for bit 31 (sign bit) for more Watch registers
mtc0 zero, C0_WATCHLO, 4 // write C0_WatchLo4
mtc0 v1, C0_WATCHHI, 5 // write C0_WatchHi5
mfc0 v0, C0_WATCHHI, 5 // read C0_WatchHi5
bgez v0, done_wr // Check for bit 31 (sign bit) for more Watch registers
mtc0 zero, C0_WATCHLO, 5 // write C0_WatchLo5
mtc0 v1, C0_WATCHHI, 6 // write C0_WatchHi6
mfc0 v0, C0_WATCHHI, 6 // read C0_WatchHi6
bgez v0, done_wr // Check for bit 31 (sign bit) for more Watch registers
mtc0 zero, C0_WATCHLO, 6 // write C0_WatchLo6
mtc0 v1, C0_WATCHHI, 7 // write C0_WatchHi7
mtc0 zero, C0_WATCHLO, 7 // write C0_WatchLo7
done_wr:
// Clear WP bit to avoid watch exception upon user code entry, IV, and software interrupts.
// RAMHACK: Use vectored interrupts (Cause.IV) to isolate them from other exceptions.
lui v1, 0x0080 // Cause.IV = 1
mtc0 v1, C0_CAUSE // write C0_Cause: Init AFTER init of CP0 WatchHi/Lo registers.
// Clear timer interrupt. (Count was cleared at the reset vector to allow timing boot.)
mtc0 zero, C0_COMPARE // write C0_Compare
jr ra
nop
END(init_cp0)
ports_smp/mips32_interaptiv_smp/gnu/example_build/init_cpc.S
+73
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@@ -0,0 +1,73 @@
/*
* init_cpc.S
*
* Created on: Jan 12, 2011
* Author: MIPS TECHNOLOGIES, INC
* initializatoin of the Cluster Power Controler
*/
/*
Unpublished work (c) MIPS Technologies, Inc. All rights reserved. Unpublished rights reserved
under the copyright laws of the United States of America and other countries.
This code is confidential and proprietary to MIPS Technologies, Inc. ("MIPS Technologies") and
may be disclosed only as permitted in writing by MIPS Technologies or an authorized third party.
Any copying, reproducing, modifying, use or disclosure of this code (in whole or in part) that is
not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly
prohibited. At a minimum, this code is protected under trade secret, unfair competition, and
copyright laws. Violations thereof may result in criminal penalties and fines.
MIPS Technologies reserves the right to change this code to improve function, design or
otherwise. MIPS Technologies does not assume any liability arising out of the application or use
of this code, or of any error or omission in such code. Any warranties, whether express, statutory,
implied or otherwise, including but not limited to the implied warranties of merchantability or
fitness for a particular purpose, are excluded. Except as expressly provided in any written license
agreement from MIPS Technologies or an authorized third party, the furnishing of this code does
not give recipient any license to any intellectual property rights, including any patent rights, that
cover this code.
This code shall not be exported, reexported, transferred, or released, directly or indirectly, in
violation of the law of any country or international law, regulation, treaty, Executive Order,
statute, amendments or supplements thereto. Should a conflict arise regarding the export,
reexport, transfer, or release of this code, the laws of the United States of America shall be
the governing law.
This code may only be disclosed to the United States government ("Government"), or to
Government users, with prior written consent from MIPS Technologies or an authorized third
party. This code constitutes one or more of the following: commercial computer software,
commercial computer software documentation or other commercial items. If the user of this
code, or any related documentation of any kind, including related technical data or manuals, is an
agency, department, or other entity of the Government, the use, duplication, reproduction, release,
modification, disclosure, or transfer of this code, or any related documentation of any kind, is
restricted in accordance with Federal Acquisition Regulation 12.212 for civilian agencies and
Defense Federal Acquisition Regulation Supplement 227.7202 for military agencies. The use of
this code by the Government is further restricted in accordance with the terms of the license
agreement(s) and/or applicable contract terms and conditions covering this code from MIPS
Technologies or an authorized third party.
*/
#include <boot.h>
#include <regdef.h>
#include <cps.h>
.set noreorder // Don't allow the assembler to reorder instructions.
.set noat // Don't allow the assembler to use r1(at) for synthetic instr.
/**************************************************************************************
**************************************************************************************/
LEAF(init_cpc)
beqz r11_is_cps, done_init_cpc // Skip if non-CPS.
nop
lw a0, GCR_CPC_STATUS(r22_gcr_addr) // Read GCR_CPC_STATUS
andi a0, 1 // CPC_EX is bit 0
beqz a0, done_init_cpc // Skip if CPC is not implemented (CPC_EX not set)
move r30_cpc_addr, zero
li a0, CPC_P_BASE_ADDR // Locate CPC at same location YAMON does.
sw a0, GCR_CPC_BASE(r22_gcr_addr) // Write CPC_BASE address to GCR
li r30_cpc_addr, CPC_BASE_ADDR // Maintain address of CPC register block.
done_init_cpc:
jr ra
nop
END(init_cpc)
ports_smp/mips32_interaptiv_smp/gnu/example_build/init_gic.S
+155
View File
@@ -0,0 +1,155 @@
/*
* init_gic.S
*
* Created on: Jan 12, 2011
* Author: MIPS TECHNOLOGIES, INC
* Initialization of the Global Interrupt Conrtoller
*/
/*
Unpublished work (c) MIPS Technologies, Inc. All rights reserved. Unpublished rights reserved
under the copyright laws of the United States of America and other countries.
This code is confidential and proprietary to MIPS Technologies, Inc. ("MIPS Technologies") and
may be disclosed only as permitted in writing by MIPS Technologies or an authorized third party.
Any copying, reproducing, modifying, use or disclosure of this code (in whole or in part) that is
not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly
prohibited. At a minimum, this code is protected under trade secret, unfair competition, and
copyright laws. Violations thereof may result in criminal penalties and fines.
MIPS Technologies reserves the right to change this code to improve function, design or
otherwise. MIPS Technologies does not assume any liability arising out of the application or use
of this code, or of any error or omission in such code. Any warranties, whether express, statutory,
implied or otherwise, including but not limited to the implied warranties of merchantability or
fitness for a particular purpose, are excluded. Except as expressly provided in any written license
agreement from MIPS Technologies or an authorized third party, the furnishing of this code does
not give recipient any license to any intellectual property rights, including any patent rights, that
cover this code.
This code shall not be exported, reexported, transferred, or released, directly or indirectly, in
violation of the law of any country or international law, regulation, treaty, Executive Order,
statute, amendments or supplements thereto. Should a conflict arise regarding the export,
reexport, transfer, or release of this code, the laws of the United States of America shall be
the governing law.
This code may only be disclosed to the United States government ("Government"), or to
Government users, with prior written consent from MIPS Technologies or an authorized third
party. This code constitutes one or more of the following: commercial computer software,
commercial computer software documentation or other commercial items. If the user of this
code, or any related documentation of any kind, including related technical data or manuals, is an
agency, department, or other entity of the Government, the use, duplication, reproduction, release,
modification, disclosure, or transfer of this code, or any related documentation of any kind, is
restricted in accordance with Federal Acquisition Regulation 12.212 for civilian agencies and
Defense Federal Acquisition Regulation Supplement 227.7202 for military agencies. The use of
this code by the Government is further restricted in accordance with the terms of the license
agreement(s) and/or applicable contract terms and conditions covering this code from MIPS
Technologies or an authorized third party.
*/
#include <boot.h>
#include <regdef.h>
#include <cps.h>
.set noreorder // Don't allow the assembler to reorder instructions.
.set noat // Don't allow the assembler to use r1(at) for synthetic instr.
/**************************************************************************************
**************************************************************************************/
LEAF(init_gic)
beqz r11_is_cps, done_gic // Skip if non-CPS.
nop
la a1, GCR_GIC_STATUS + GCR_CONFIG_ADDR // Read GCR_GIC_STATUS
lw a0, 0(a1)
ext a0, a0, GIC_EX, GIC_EX_S // Isolate GCR_GIC_STATUS[GIC_EX].
beqz a0, done_gic // If no gic then skip.
nop
bnez r23_cpu_num, init_vpe_gic // Only core0 vpe0 inits shared portion.
nop
li a1, GCR_CONFIG_ADDR + GCR_GIC_BASE // Locate and enable GIC
li a0, GIC_P_BASE_ADDR | 1 // Physical address + enable bit
sw a0, 0(a1)
// Verify gic is 5 "slices" of 8 interrupts giving 40 interrupts.
li a1, GIC_BASE_ADDR // load GIC KSEG0 Address
lw a0, GIC_SH_CONFIG(a1) // GIC_SH_CONFIG
ext a0, a0, NUMINTERRUPTS, NUMINTERRUPTS_S // NUMINTERRUPTS (actually slices - 1)
li a3, 4
beq a0, a3, configure_slices
nop
sdbbp // Failed assertion that gic implements 40 external interrupts.
configure_slices:
// Hardcoded to set up the last 16 of 40 external interrupts (24..39) for IPI.
// First interrupts 24... 31 (top 8 bits of 31_0 registers)
li a0, 0xff000000
sw a0, GIC_SH_RMASK31_0(a1) // (disable 0..31)
sw a0, GIC_SH_POL31_0(a1) // (high/rise 24..31)
sw a0, GIC_SH_TRIG31_0(a1) // (edge 24..31)
sw a0, GIC_SH_SMASK31_00(a1) // (enable 24..31)
// Then interrupts 32...40 (lower 8 bits of 63_32 registers)
li a0, 0xff
sw a0, GIC_SH_RMASK63_32(a1) // (disable 32..63)
sw a0, GIC_SH_POL63_32(a1) // (high/rise 32..39)
sw a0, GIC_SH_TRIG63_32(a1) // (edge 32..39)
sw a0, GIC_SH_SMASK63_32(a1) // (enable 32..39)
// Initialize configuration of shared interrupts
// Direct GIC_int24..39 to vpe 0..7
// MIPS Linux convention that last 16 interrupts implemented be set aside for IPI signaling.
// (The actual interrupts are tied low and software sends interrupts via GIC_SH_WEDGE writes.)
li a0, 1 // set bit 0 for CORE0 or for MT vpe0
sw a0, GIC_SH_MAP0_VPE31_0 + (GIC_SH_MAP_SPACER * 24) (a1) // Source 24 to VPE 0
sw a0, GIC_SH_MAP0_VPE31_0 + (GIC_SH_MAP_SPACER * 32) (a1) // Source 32 to VPE 0
sll a0, a0, 1 // set bit 1 for CORE1 or for MT vpe1
sw a0, GIC_SH_MAP0_VPE31_0 + (GIC_SH_MAP_SPACER * 25) (a1) // Source 25 to VPE 1
sw a0, GIC_SH_MAP0_VPE31_0 + (GIC_SH_MAP_SPACER * 33) (a1) // Source 33 to VPE 1
sll a0, a0, 1 // set bit 2 for CORE2 or for MT vpe2
sw a0, GIC_SH_MAP0_VPE31_0 + (GIC_SH_MAP_SPACER * 26) (a1) // Source 26 to VPE 2
sw a0, GIC_SH_MAP0_VPE31_0 + (GIC_SH_MAP_SPACER * 34) (a1) // Source 34 to VPE 2
sll a0, a0, 1 // set bit 3 for CORE3 or for MT vpe3
sw a0, GIC_SH_MAP0_VPE31_0 + (GIC_SH_MAP_SPACER * 27) (a1) // Source 27 to VPE 3
sw a0, GIC_SH_MAP0_VPE31_0 + (GIC_SH_MAP_SPACER * 35) (a1) // Source 35 to VPE 3
sll a0, a0, 1 // set bit 4 for CORE4 or for MT vpe4
sw a0, GIC_SH_MAP0_VPE31_0 + (GIC_SH_MAP_SPACER * 28) (a1) // Source 28 to VPE 4
sw a0, GIC_SH_MAP0_VPE31_0 + (GIC_SH_MAP_SPACER * 36) (a1) // Source 36 to VPE 4
sll a0, a0, 1 // set bit 5 for CORE5 or for MT vpe5
sw a0, GIC_SH_MAP0_VPE31_0 + (GIC_SH_MAP_SPACER * 29) (a1) // Source 29 to VPE 5
sw a0, GIC_SH_MAP0_VPE31_0 + (GIC_SH_MAP_SPACER * 37) (a1) // Source 37 to VPE 5
sll a0, a0, 1 // set bit 6 for CORE6 or for MT vpe6
sw a0, GIC_SH_MAP0_VPE31_0 + (GIC_SH_MAP_SPACER * 30) (a1) // Source 30 to VPE 6
sw a0, GIC_SH_MAP0_VPE31_0 + (GIC_SH_MAP_SPACER * 38) (a1) // Source 38 to VPE 6
sll a0, a0, 1 // set bit 7 for CORE7 or for MT vpe7
sw a0, GIC_SH_MAP0_VPE31_0 + (GIC_SH_MAP_SPACER * 31) (a1) // Source 31 to VPE 7
sw a0, GIC_SH_MAP0_VPE31_0 + (GIC_SH_MAP_SPACER * 39) (a1) // Source 39 to VPE 7
init_vpe_gic:
// Initialize configuration of per Core or for MT vpe interrupts
li a1, (GIC_BASE_ADDR | GIC_CORE_LOCAL_SECTION_OFFSET)
lw a3, GIC_COREL_CTL(a1)
map_timer_int:
ext a0, a3, TIMER_ROUTABLE, TIMER_ROUTABLE_S
beqz a0, map_perfcount_int
nop
li a0, 0x80000005 // Int5 is selected for timer routing
sw a0, GIC_COREL_TIMER_MAP(a1)
map_perfcount_int:
ext a0, a3, PERFCOUNT_ROUTABLE, PERFCOUNT_ROUTABLE_S
beqz a0, done_gic
nop
li a0, 0x80000004 // Int4 is selected for performance routing
sw a0, GIC_COREL_PERFCTR_MAP(a1)
done_gic:
jr ra
nop
END(init_gic)
ports_smp/mips32_interaptiv_smp/gnu/example_build/init_gpr.S
+118
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/*
* init_gpr.S
*
* Created on: Jan 12, 2011
* Author: MIPS TECHNOLOGIES, INC
* Start of boot code for 24K Family of Cores
*/
/*
Unpublished work (c) MIPS Technologies, Inc. All rights reserved. Unpublished rights reserved
under the copyright laws of the United States of America and other countries.
This code is confidential and proprietary to MIPS Technologies, Inc. ("MIPS Technologies") and
may be disclosed only as permitted in writing by MIPS Technologies or an authorized third party.
Any copying, reproducing, modifying, use or disclosure of this code (in whole or in part) that is
not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly
prohibited. At a minimum, this code is protected under trade secret, unfair competition, and
copyright laws. Violations thereof may result in criminal penalties and fines.
MIPS Technologies reserves the right to change this code to improve function, design or
otherwise. MIPS Technologies does not assume any liability arising out of the application or use
of this code, or of any error or omission in such code. Any warranties, whether express, statutory,
implied or otherwise, including but not limited to the implied warranties of merchantability or
fitness for a particular purpose, are excluded. Except as expressly provided in any written license
agreement from MIPS Technologies or an authorized third party, the furnishing of this code does
not give recipient any license to any intellectual property rights, including any patent rights, that
cover this code.
This code shall not be exported, reexported, transferred, or released, directly or indirectly, in
violation of the law of any country or international law, regulation, treaty, Executive Order,
statute, amendments or supplements thereto. Should a conflict arise regarding the export,
reexport, transfer, or release of this code, the laws of the United States of America shall be
the governing law.
This code may only be disclosed to the United States government ("Government"), or to
Government users, with prior written consent from MIPS Technologies or an authorized third
party. This code constitutes one or more of the following: commercial computer software,
commercial computer software documentation or other commercial items. If the user of this
code, or any related documentation of any kind, including related technical data or manuals, is an
agency, department, or other entity of the Government, the use, duplication, reproduction, release,
modification, disclosure, or transfer of this code, or any related documentation of any kind, is
restricted in accordance with Federal Acquisition Regulation 12.212 for civilian agencies and
Defense Federal Acquisition Regulation Supplement 227.7202 for military agencies. The use of
this code by the Government is further restricted in accordance with the terms of the license
agreement(s) and/or applicable contract terms and conditions covering this code from MIPS
Technologies or an authorized third party.
*/
#include <boot.h>
#include <regdef.h>
#include <m32c0.h>
.set noreorder // Don't allow the assembler to reorder instructions.
.set noat // Don't allow the assembler to use r1(at) for synthetic instr.
/**************************************************************************************
**************************************************************************************/
LEAF(init_gpr)
// Initialize the general purpose registers and any shadow register sets.
// Although not necessary, register initialization may be useful during boot,
// debug, and simulation when certain ways of initializing registers may not work
// (xor rN, rN, rN for example.)
// Initialize register sets
li $1, 0xdeadbeef // (0xdeadbeef stands out, kseg2 mapped, odd.)
// Determine how many shadow sets are implemented (in addition to the base register set.)
// the first time thru the loop it will initialize using $1 set above.
// At the bottom og the loop, 1 is subtract from $30
// and loop back to next_shadow_set to start the next loop and the next lowest set number.
mfc0 $29, C0_SRSCTL // read C0_SRSCtl
ext $30, $29, 26, 4 // extract HSS
next_shadow_set:
// set PSS to shadow set to be initialized
ins $29, $30, 6, 4 // insert PSS
mtc0 $29, C0_SRSCTL // write C0_SRSCtl
wrpgpr $1, $1
wrpgpr $2, $1
wrpgpr $3, $1
wrpgpr $4, $1
wrpgpr $5, $1
wrpgpr $6, $1
wrpgpr $7, $1
wrpgpr $8, $1
wrpgpr $9, $1
wrpgpr $10, $1
wrpgpr $11, $1
wrpgpr $12, $1
wrpgpr $13, $1
wrpgpr $14, $1
wrpgpr $15, $1
wrpgpr $16, $1
wrpgpr $17, $1
wrpgpr $18, $1
wrpgpr $19, $1
wrpgpr $20, $1
wrpgpr $21, $1
wrpgpr $22, $1
wrpgpr $23, $1
wrpgpr $24, $1
wrpgpr $25, $1
wrpgpr $26, $1
wrpgpr $27, $1
wrpgpr $28, $1
wrpgpr $29, $1
beqz $30, done_init_gpr // early exit when we get to set 0 so we don't clobber return in $31
nop
wrpgpr $30, $1
wrpgpr $31, $1
b next_shadow_set
add $30, -1 // Since the code started with the highest set number this decrements to the next lower number
done_init_gpr:
jr ra
nop
END(init_gpr)
ports_smp/mips32_interaptiv_smp/gnu/example_build/init_itc.S
+62
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@@ -0,0 +1,62 @@
/*
* init_itc.S
*
* Created on: Jan 13, 2011
* Author: MIPS TECHNOLOGIES, INC
* Common Inter Thread Communicaton initialization
*/
/*
Unpublished work (c) MIPS Technologies, Inc. All rights reserved. Unpublished rights reserved
under the copyright laws of the United States of America and other countries.
This code is confidential and proprietary to MIPS Technologies, Inc. ("MIPS Technologies") and
may be disclosed only as permitted in writing by MIPS Technologies or an authorized third party.
Any copying, reproducing, modifying, use or disclosure of this code (in whole or in part) that is
not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly
prohibited. At a minimum, this code is protected under trade secret, unfair competition, and
copyright laws. Violations thereof may result in criminal penalties and fines.
MIPS Technologies reserves the right to change this code to improve function, design or
otherwise. MIPS Technologies does not assume any liability arising out of the application or use
of this code, or of any error or omission in such code. Any warranties, whether express, statutory,
implied or otherwise, including but not limited to the implied warranties of merchantability or
fitness for a particular purpose, are excluded. Except as expressly provided in any written license
agreement from MIPS Technologies or an authorized third party, the furnishing of this code does
not give recipient any license to any intellectual property rights, including any patent rights, that
cover this code.
This code shall not be exported, reexported, transferred, or released, directly or indirectly, in
violation of the law of any country or international law, regulation, treaty, Executive Order,
statute, amendments or supplements thereto. Should a conflict arise regarding the export,
reexport, transfer, or release of this code, the laws of the United States of America shall be
the governing law.
This code may only be disclosed to the United States government ("Government"), or to
Government users, with prior written consent from MIPS Technologies or an authorized third
party. This code constitutes one or more of the following: commercial computer software,
commercial computer software documentation or other commercial items. If the user of this
code, or any related documentation of any kind, including related technical data or manuals, is an
agency, department, or other entity of the Government, the use, duplication, reproduction, release,
modification, disclosure, or transfer of this code, or any related documentation of any kind, is
restricted in accordance with Federal Acquisition Regulation 12.212 for civilian agencies and
Defense Federal Acquisition Regulation Supplement 227.7202 for military agencies. The use of
this code by the Government is further restricted in accordance with the terms of the license
agreement(s) and/or applicable contract terms and conditions covering this code from MIPS
Technologies or an authorized third party.
*/
#include <boot.h>
#include <regdef.h>
.set noreorder # Don't allow the assembler to reorder instructions.
.set noat # Don't allow the assembler to use r1(at) for synthetic instr.
/**************************************************************************************
**************************************************************************************/
LEAF(init_itc)
nop
// enhanceme: Add ITC init.
done_init_itc:
jr ra
nop
END(init_itc)
ports_smp/mips32_interaptiv_smp/gnu/example_build/init_mc_denali.S
+254
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ports_smp/mips32_interaptiv_smp/gnu/example_build/init_tlb.S
+88
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/*
* init_tlb.S
*
* Created on: Jan 12, 2011
* Author: MIPS TECHNOLOGIES, INC
* Common TLB initialization for MIPS cores
*/
/*
Unpublished work (c) MIPS Technologies, Inc. All rights reserved. Unpublished rights reserved
under the copyright laws of the United States of America and other countries.
This code is confidential and proprietary to MIPS Technologies, Inc. ("MIPS Technologies") and
may be disclosed only as permitted in writing by MIPS Technologies or an authorized third party.
Any copying, reproducing, modifying, use or disclosure of this code (in whole or in part) that is
not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly
prohibited. At a minimum, this code is protected under trade secret, unfair competition, and
copyright laws. Violations thereof may result in criminal penalties and fines.
MIPS Technologies reserves the right to change this code to improve function, design or
otherwise. MIPS Technologies does not assume any liability arising out of the application or use
of this code, or of any error or omission in such code. Any warranties, whether express, statutory,
implied or otherwise, including but not limited to the implied warranties of merchantability or
fitness for a particular purpose, are excluded. Except as expressly provided in any written license
agreement from MIPS Technologies or an authorized third party, the furnishing of this code does
not give recipient any license to any intellectual property rights, including any patent rights, that
cover this code.
This code shall not be exported, reexported, transferred, or released, directly or indirectly, in
violation of the law of any country or international law, regulation, treaty, Executive Order,
statute, amendments or supplements thereto. Should a conflict arise regarding the export,
reexport, transfer, or release of this code, the laws of the United States of America shall be
the governing law.
This code may only be disclosed to the United States government ("Government"), or to
Government users, with prior written consent from MIPS Technologies or an authorized third
party. This code constitutes one or more of the following: commercial computer software,
commercial computer software documentation or other commercial items. If the user of this
code, or any related documentation of any kind, including related technical data or manuals, is an
agency, department, or other entity of the Government, the use, duplication, reproduction, release,
modification, disclosure, or transfer of this code, or any related documentation of any kind, is
restricted in accordance with Federal Acquisition Regulation 12.212 for civilian agencies and
Defense Federal Acquisition Regulation Supplement 227.7202 for military agencies. The use of
this code by the Government is further restricted in accordance with the terms of the license
agreement(s) and/or applicable contract terms and conditions covering this code from MIPS
Technologies or an authorized third party.
*/
#include <boot.h>
#include <regdef.h>
#include <m32c0.h>
.set noreorder // Don't allow the assembler to reorder instructions.
.set noat // Don't allow the assembler to use r1(at) for synthetic instr.
/**************************************************************************************
**************************************************************************************/
LEAF(init_tlb)
check_for_tlb:
// Determine if we have a TLB
mfc0 v1, C0_CONFIG // read C0_Config
ext v1, v1, 7, 3 // extract MT field
li a3, 0x1 // load a 1 to check against
bne v1, a3, done_init_tlb
mfc0 v0, C0_CONFIG1 // C0_Config1
nop
start_init_tlb:
// Config1MMUSize == Number of TLB entries - 1
ext v1, v0, CFG1_MMUSSHIFT, 6 // extract MMU Size
mtc0 zero, C0_ENTRYLO0 // write C0_EntryLo0
mtc0 zero, C0_ENTRYLO1 // write C0_EntryLo1
mtc0 zero, C0_PAGEMASK // write C0_PageMask
mtc0 zero, C0_WIRED // write C0_Wired
li a0, 0x80000000
next_tlb_entry_pair:
mtc0 v1, C0_INDEX // write C0_Index
mtc0 a0, C0_ENTRYHI // write C0_EntryHi
ehb
tlbwi
add a0, (2<<13) // Add 8K to the address to avoid TLB conflict with previous entry
bne v1, zero, next_tlb_entry_pair
add v1, -1
done_init_tlb:
jr ra
nop
END(init_tlb)
ports_smp/mips32_interaptiv_smp/gnu/example_build/init_vpe1.S
+262
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ports_smp/mips32_interaptiv_smp/gnu/example_build/join_domain.S
+87
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@@ -0,0 +1,87 @@
/*
* join_domain.S
*
* Created on: Jan 13, 2011
* Author: MIPS TECHNOLOGIES, INC
* For CPS cores join processing domain
*/
/*
Unpublished work (c) MIPS Technologies, Inc. All rights reserved. Unpublished rights reserved
under the copyright laws of the United States of America and other countries.
This code is confidential and proprietary to MIPS Technologies, Inc. ("MIPS Technologies") and
may be disclosed only as permitted in writing by MIPS Technologies or an authorized third party.
Any copying, reproducing, modifying, use or disclosure of this code (in whole or in part) that is
not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly
prohibited. At a minimum, this code is protected under trade secret, unfair competition, and
copyright laws. Violations thereof may result in criminal penalties and fines.
MIPS Technologies reserves the right to change this code to improve function, design or
otherwise. MIPS Technologies does not assume any liability arising out of the application or use
of this code, or of any error or omission in such code. Any warranties, whether express, statutory,
implied or otherwise, including but not limited to the implied warranties of merchantability or
fitness for a particular purpose, are excluded. Except as expressly provided in any written license
agreement from MIPS Technologies or an authorized third party, the furnishing of this code does
not give recipient any license to any intellectual property rights, including any patent rights, that
cover this code.
This code shall not be exported, reexported, transferred, or released, directly or indirectly, in
violation of the law of any country or international law, regulation, treaty, Executive Order,
statute, amendments or supplements thereto. Should a conflict arise regarding the export,
reexport, transfer, or release of this code, the laws of the United States of America shall be
the governing law.
This code may only be disclosed to the United States government ("Government"), or to
Government users, with prior written consent from MIPS Technologies or an authorized third
party. This code constitutes one or more of the following: commercial computer software,
commercial computer software documentation or other commercial items. If the user of this
code, or any related documentation of any kind, including related technical data or manuals, is an
agency, department, or other entity of the Government, the use, duplication, reproduction, release,
modification, disclosure, or transfer of this code, or any related documentation of any kind, is
restricted in accordance with Federal Acquisition Regulation 12.212 for civilian agencies and
Defense Federal Acquisition Regulation Supplement 227.7202 for military agencies. The use of
this code by the Government is further restricted in accordance with the terms of the license
agreement(s) and/or applicable contract terms and conditions covering this code from MIPS
Technologies or an authorized third party.
*/
#include <boot.h>
#include <regdef.h>
#include <cps.h>
.set noreorder // Don't allow the assembler to reorder instructions.
.set noat // Don't allow the assembler to use r1(at) for synthetic instr.
/**************************************************************************************
**************************************************************************************/
LEAF(join_domain)
beqz r11_is_cps, done_join_domain // If this is not a CPS then we are done.
nop
// Enable coherence and allow interventions from all other cores.
// (Write access enabled via GCR_ACCESS by core 0.)
li a0, 0x0f // Set Coherent domain enable for 4 cores
sw a0, (CORE_LOCAL_CONTROL_BLOCK | GCR_CL_COHERENCE)(r22_gcr_addr) // GCR_CL_COHERENCE
ehb
// Cores other than core 0 can relinquish write access to CM regs here.
move a3, zero
next_coherent_core:
sll a0, a3, 16
sw a0, (CORE_LOCAL_CONTROL_BLOCK | GCR_CL_OTHER)(r22_gcr_addr) // GCR_CL_OTHER[CoreNum]
busy_wait_coherent_core:
lw a0, (CORE_OTHER_CONTROL_BLOCK | GCR_CO_COHERENCE)(r22_gcr_addr) // GCR_CO_COHERENCE
beqz a0, busy_wait_coherent_core // Busy wait on cores joining.
nop
bne a3, r19_more_cores, next_coherent_core
addiu a3, 1
done_join_domain:
jr ra
nop
END(join_domain)
ports_smp/mips32_interaptiv_smp/gnu/example_build/m32c0.h
+798
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ports_smp/mips32_interaptiv_smp/gnu/example_build/regdef.h
+39
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@@ -0,0 +1,39 @@
#ifndef __REGDEF_H
#define __REGDEF_H
#define zero $0 /* wired zero */
//#define AT $1 /* assembler temp - uppercase because of ".set at" */
#define v0 $2 /* values for function returns */
#define v1 $3
#define a0 $4 /* argument registers */
#define a1 $5
#define a2 $6
#define a3 $7
#define t0 $8
#define t1 $9
#define t2 $10
#define t3 $11
#define t4 $12
#define t5 $13
#define t6 $14
#define t7 $15
#define s0 $16
#define s1 $17
#define s2 $18
#define s3 $19
#define s4 $20
#define s5 $21
#define s6 $22
#define s7 $23
#define t8 $24
#define t9 $25
#define jp $25
#define k0 $26 /* reserved for OS */
#define k1 $27 /* reserved for OS */
#define gp $28 /* global pointer */
#define sp $29 /* stack pointer */
#define fp $30 /* frame pointer */
#define s8 $30 /* frame pointer */
#define ra $31 /* return address */
#endif /* __REGDEF_H */
ports_smp/mips32_interaptiv_smp/gnu/example_build/release_mp.S
+89
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@@ -0,0 +1,89 @@
/*
* release_mp.S
*
* Created on: Jan 12, 2011
* Author: MIPS TECHNOLOGIES, INC
* Release other processors so they can boot
*/
/*
Unpublished work (c) MIPS Technologies, Inc. All rights reserved. Unpublished rights reserved
under the copyright laws of the United States of America and other countries.
This code is confidential and proprietary to MIPS Technologies, Inc. ("MIPS Technologies") and
may be disclosed only as permitted in writing by MIPS Technologies or an authorized third party.
Any copying, reproducing, modifying, use or disclosure of this code (in whole or in part) that is
not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly
prohibited. At a minimum, this code is protected under trade secret, unfair competition, and
copyright laws. Violations thereof may result in criminal penalties and fines.
MIPS Technologies reserves the right to change this code to improve function, design or
otherwise. MIPS Technologies does not assume any liability arising out of the application or use
of this code, or of any error or omission in such code. Any warranties, whether express, statutory,
implied or otherwise, including but not limited to the implied warranties of merchantability or
fitness for a particular purpose, are excluded. Except as expressly provided in any written license
agreement from MIPS Technologies or an authorized third party, the furnishing of this code does
not give recipient any license to any intellectual property rights, including any patent rights, that
cover this code.
This code shall not be exported, reexported, transferred, or released, directly or indirectly, in
violation of the law of any country or international law, regulation, treaty, Executive Order,
statute, amendments or supplements thereto. Should a conflict arise regarding the export,
reexport, transfer, or release of this code, the laws of the United States of America shall be
the governing law.
This code may only be disclosed to the United States government ("Government"), or to
Government users, with prior written consent from MIPS Technologies or an authorized third
party. This code constitutes one or more of the following: commercial computer software,
commercial computer software documentation or other commercial items. If the user of this
code, or any related documentation of any kind, including related technical data or manuals, is an
agency, department, or other entity of the Government, the use, duplication, reproduction, release,
modification, disclosure, or transfer of this code, or any related documentation of any kind, is
restricted in accordance with Federal Acquisition Regulation 12.212 for civilian agencies and
Defense Federal Acquisition Regulation Supplement 227.7202 for military agencies. The use of
this code by the Government is further restricted in accordance with the terms of the license
agreement(s) and/or applicable contract terms and conditions covering this code from MIPS
Technologies or an authorized third party.
*/
#include <boot.h>
#include <regdef.h>
#include <cps.h>
.set noreorder // Don't allow the assembler to reorder instructions.
.set noat // Don't allow the assembler to use r1(at) for synthetic instr.
/**************************************************************************************
**************************************************************************************/
LEAF(release_mp)
blez r19_more_cores, done_release_mp // If no more cores then we are done.
li a3, 1
beqz r30_cpc_addr, release_next_core // If no CPC then use GCR_CO_RESET_RELEASE
nop // else use CPC Power Up command.
powerup_next_core:
// Send PwrUp command to next core causing execution at their reset exception vector.
move a0, a3
sll a0, 16
sw a0, (CPS_CORE_LOCAL_CONTROL_BLOCK | CPC_OTHERL_REG)(r30_cpc_addr)
li a0, PWR_UP // "PwrUp" power domain command.
sw a0, (CPS_CORE_OTHER_CONTROL_BLOCK | CPC_CMDO_REG)(r30_cpc_addr)
bne r19_more_cores, a3, powerup_next_core
add a3, a3, 1
jr ra
nop
release_next_core:
// Release next core to execute at their reset exception vector.
move a0, a3
sll a0, 16
sw a0, (CORE_LOCAL_CONTROL_BLOCK | GCR_CL_OTHER)(r22_gcr_addr) // GCR_CL_OTHER
sw zero, 0x4000(r22_gcr_addr) // GCR_CO_RESET_RELEASE
bne r19_more_cores, a3, release_next_core
add a3, a3, 1
done_release_mp:
jr ra
nop
END(release_mp)
ports_smp/mips32_interaptiv_smp/gnu/example_build/set_gpr_boot_values.S
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/*
* interAptiv/set_gpr_boot_values.S
*
* Created on: May 9, 2012
* Author: MIPS TECHNOLOGIES, INC
* Set GPR values for interAptiv Family of Cores
*/
/*
Unpublished work (c) MIPS Technologies, Inc. All rights reserved. Unpublished rights reserved
under the copyright laws of the United States of America and other countries.
This code is confidential and proprietary to MIPS Technologies, Inc. ("MIPS Technologies") and
may be disclosed only as permitted in writing by MIPS Technologies or an authorized third party.
Any copying, reproducing, modifying, use or disclosure of this code (in whole or in part) that is
not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly
prohibited. At a minimum, this code is protected under trade secret, unfair competition, and
copyright laws. Violations thereof may result in criminal penalties and fines.
MIPS Technologies reserves the right to change this code to improve function, design or
otherwise. MIPS Technologies does not assume any liability arising out of the application or use
of this code, or of any error or omission in such code. Any warranties, whether express, statutory,
implied or otherwise, including but not limited to the implied warranties of merchantability or
fitness for a particular purpose, are excluded. Except as expressly provided in any written license
agreement from MIPS Technologies or an authorized third party, the furnishing of this code does
not give recipient any license to any intellectual property rights, including any patent rights, that
cover this code.
This code shall not be exported, reexported, transferred, or released, directly or indirectly, in
violation of the law of any country or international law, regulation, treaty, Executive Order,
statute, amendments or supplements thereto. Should a conflict arise regarding the export,
reexport, transfer, or release of this code, the laws of the United States of America shall be
the governing law.
This code may only be disclosed to the United States government ("Government"), or to
Government users, with prior written consent from MIPS Technologies or an authorized third
party. This code constitutes one or more of the following: commercial computer software,
commercial computer software documentation or other commercial items. If the user of this
code, or any related documentation of any kind, including related technical data or manuals, is an
agency, department, or other entity of the Government, the use, duplication, reproduction, release,
modification, disclosure, or transfer of this code, or any related documentation of any kind, is
restricted in accordance with Federal Acquisition Regulation 12.212 for civilian agencies and
Defense Federal Acquisition Regulation Supplement 227.7202 for military agencies. The use of
this code by the Government is further restricted in accordance with the terms of the license
agreement(s) and/or applicable contract terms and conditions covering this code from MIPS
Technologies or an authorized third party.
*/
#include <boot.h>
#include <m32c0.h>
#include <regdef.h>
#include <cps.h>
// defines not yet in m32c0.h
#define C0_MVPCTL $0, 1
#define C0_MVPCONF0 $0, 2
#define C0_VPECTL $1, 1
#define C0_VPECONF0 $1, 2
#define C0_TCSTATUS $2, 1
#define C0_TCRESTART $2, 3
#define C0_TCHALT $2, 4
#define C0_TCBIND $2, 2
.set noreorder // Don't allow the assembler to reorder instructions.
.set noat // Don't allow the assembler to use r1(at) for synthetic instr.
/**************************************************************************************
**************************************************************************************/
LEAF(set_gpr_boot_values)
li r1_all_ones, 0xffffffff // Simplify code and improve clarity
mfc0 a0, C0_EBASE // Read CP0 EBase
ext r23_cpu_num, a0, 0, 4 // Extract CPUNum
li r24_malta_word, MALTA_DISP_ADDR // Need for reporting failed assertions.
la gp, _gp // All vpe share globals.
li sp, STACK_BASE_ADDR // Each vpe gets it's own stack.
ins sp, r23_cpu_num, STACK_SIZE_LOG2, 3
check_mt_ase:
mfc0 a0, C0_CONFIG1 // C0_Config1
bgez a0, no_mt_ase // bit 31 sign bit set?
mfc0 a0, C0_CONFIG2 // C0_Config2
bgez a0, no_mt_ase // bit 31 sign bit set?
mfc0 a0, C0_CONFIG3 // C0_Config3
and a0, (1 << 2) // M_Config3MT
beqz a0, no_mt_ase
li r10_has_mt_ase, 0
has_mt_ase:
li r10_has_mt_ase, 1
// Every vpe will set up the following to simplify resource initialization.
mfc0 a0, C0_TCBIND // Read CP0 TCBind
ext r9_vpe_num, a0, 0, 4 // Extract CurVPE
ext r18_tc_num, a0, 21, 8 // Extract CurTC
mfc0 a0, C0_MVPCONF0 // C0_MVPConf0
ext r21_more_tcs, a0, 0, 8 // Extract PTC
b check_cps
ext r20_more_vpes, a0, 10, 4 // Extract VPE
no_mt_ase: // This processor does not implement the MIPS32 MT ASE. Set up defaults.
sdbbp // Failed assertion: not mt.
check_cps: // Determine if there is a coherency manager present. (Implementation Dependent.)
mfc0 r25_coreid, C0_PRID // CP0 PRId.
ext a0, r25_coreid, 8, 16 // Extract Manuf and Core.
li a3, 0x01A1 // interAptiv Multi core
beq a3, a0, is_cps
nop
is_not_interAptiv: // This processor is not a InterAptive Core so exit!
sdbbp // Failed assertion: not interAptiv.
is_cps:
li r11_is_cps, 1
// Verify that we can find the GCRs.
la a1, GCR_CONFIG_ADDR // KSEG1(GCRBASE)
lw a0, GCR_BASE(a1) // read GCR_BASE
ins a1, $0, 29, 3 // Convert KSEG1 to physical address.
ins a0, $0, 0, 15 // Isolate physical base address of GCR (Clear lower bits).
beq a1, a0, gcr_found
nop
sdbbp // Can't find GCR. RTL config override of MIPS default?
gcr_found:
// Every vpe will set up the following to simplify resource initialization.
li r22_gcr_addr, GCR_CONFIG_ADDR
lw r8_core_num, (CORE_LOCAL_CONTROL_BLOCK + GCR_CL_ID) (r22_gcr_addr) // Load GCR_CL_ID
lw a0, GCR_CONFIG(r22_gcr_addr) // Load GCR_CONFIG
ext r19_more_cores, a0, PCORES, PCORES_S // Extract PCORES
done_init_gpr:
jr ra
nop
END(set_gpr_boot_values)
ports_smp/mips32_interaptiv_smp/gnu/example_build/start.S
+461
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ports_smp/mips32_interaptiv_smp/gnu/inc/tx_port.h
+433
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ports_smp/mips32_interaptiv_smp/gnu/readme_threadx.txt
+262
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ports_smp/mips32_interaptiv_smp/gnu/src/tx_initialize_low_level.S
+335
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ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_context_restore.S
+409
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ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_context_save.S
+295
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ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_interrupt_control.S
+88
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@@ -0,0 +1,88 @@
/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
/**************************************************************************/
/**************************************************************************/
RETURN_MASK = 0x0001
SET_SR_MASK_U = 0xFFFF
SET_SR_MASK_L = 0xFFFE
.text
.set noreorder
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_control MIPS32_interAptiv/GNU */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function is responsible for changing the interrupt lockout */
/* posture of the system. */
/* */
/* INPUT */
/* */
/* new_posture New interrupt lockout posture */
/* */
/* OUTPUT */
/* */
/* old_posture Old interrupt lockout posture */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* Application Code */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* xx-xx-xxxx Scott Larson Initial Version 6.x */
/* */
/**************************************************************************/
/* UINT _tx_thread_interrupt_control(UINT new_posture)
{ */
.globl _tx_thread_interrupt_control
_tx_thread_interrupt_control:
/* Pickup current interrupt lockout posture. */
mfc0 $8, $12 # Pickup current SR
andi $2, $8, RETURN_MASK # Return value back to caller
/* Apply the new interrupt posture. */
lui $9, SET_SR_MASK_U # Build set SR mask
ori $9, $9, SET_SR_MASK_L #
and $8, $8, $9 # Isolate interrupt lockout bits
or $8, $8, $4 # Put new lockout bits in
mtc0 $8, $12 # Set new interrupt lockout
jr.hb $31 # Return to caller
nop # Delay slot
/* } */
ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_schedule.S
+369
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ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_core_get.S
+69
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@@ -0,0 +1,69 @@
/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
/**************************************************************************/
/**************************************************************************/
#define UserLocal $4,2
.text
.set noreorder
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_core_get MIPS32_interAptiv/GNU */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function gets the currently running core number and returns it.*/
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* Core ID */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* ThreadX Source */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* xx-xx-xxxx Scott Larson Initial Version 6.x */
/* */
/**************************************************************************/
.globl _tx_thread_smp_core_get
_tx_thread_smp_core_get:
mfc0 $2, UserLocal # Pickup VPE ID
j $31 # Return to caller
and $2, $2, 0xFF # Isolate the VPE number
ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_core_preempt.S
+79
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@@ -0,0 +1,79 @@
/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
/**************************************************************************/
/**************************************************************************/
#define GIC_SH_WEDGE 0xbbdc0280 /* For Inter-processor interrupts on MALTA board. */
#define GIC_SH_COUNTER_LO 0xbbdc0010 /* Lower 32-bits of GIC common counter */
.text
.set noreorder
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_core_preempt MIPS32_interAptiv/GNU */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function preempts the specified core in situations where the */
/* thread corresponding to this core is no longer ready or when the */
/* core must be used for a higher-priority thread. If the specified is */
/* the current core, this processing is skipped since the will give up */
/* control subsequently on its own. */
/* */
/* INPUT */
/* */
/* core The core to preempt */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* ThreadX Source */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* xx-xx-xxxx Scott Larson Initial Version 6.x */
/* */
/**************************************************************************/
.globl _tx_thread_smp_core_preempt
_tx_thread_smp_core_preempt:
sync
la $8, GIC_SH_WEDGE # Build address
li $9, 0x80000020 #
addu $9, $4, $9 # Build exact VPE to interrupt
sw $9, 0($8) # Interrupt the selected VPE
jr.hb $31 # Return to caller
nop # Delay slot
ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_current_state_get.S
+78
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@@ -0,0 +1,78 @@
/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
/**************************************************************************/
/**************************************************************************/
#define UserLocal $4,2
#define C0_Status $12
.text
.set noreorder
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_current_state_get MIPS32_interAptiv/GNU */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function is gets the current state of the calling core. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* ThreadX Components */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* xx-xx-xxxx Scott Larson Initial Version 6.x */
/* */
/**************************************************************************/
.globl _tx_thread_smp_current_state_get
_tx_thread_smp_current_state_get:
di $8 # Disable interrupts
ehb #
la $12, _tx_thread_system_state # Pickup start of the current state array
mfc0 $25, UserLocal # Pickup VPE ID
sll $25, $25, 2 # Build index based on VPE number
addu $12, $12, $25 # Build address of current state for this VPE
lw $2, ($12) # Pickup current state
mtc0 $8, C0_Status # Restore interrupts
jr.hb $31 # Return to caller
nop #
ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_current_thread_get.S
+77
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@@ -0,0 +1,77 @@
/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
/**************************************************************************/
/**************************************************************************/
#define UserLocal $4,2
#define C0_Status $12
.text
.set noreorder
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_current_thread_get MIPS32_interAptiv/GNU */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function is gets the current thread of the calling core. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* ThreadX Components */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* xx-xx-xxxx Scott Larson Initial Version 6.x */
/* */
/**************************************************************************/
.globl _tx_thread_smp_current_thread_get
_tx_thread_smp_current_thread_get:
di $10 # Disable interrupts
ehb #
mfc0 $25, UserLocal # Pickup VPE ID
la $12, _tx_thread_current_ptr # Pickup the current thread pointer
sll $25, $25, 2 # Build index based on VPE number
addu $12, $12, $25 # Build address of current thread pointer for this VPE
lw $2, ($12) # Pickup current thread pointer
mtc0 $10, C0_Status # Restore interrupt posture
jr.hb $31 # Return to caller
nop # Delay slot
ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_initialize_wait.S
+119
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@@ -0,0 +1,119 @@
/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
/**************************************************************************/
/**************************************************************************/
#define UserLocal $4,2
#define INITIAL_SR 0xFF00 /* All IM bits set */
.text
.set noreorder
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_initialize_wait MIPS32_interAptiv/GNU */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function is the place where additional cores wait until */
/* initialization is complete before they enter the thread scheduling */
/* loop. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* _tx_thread_schedule Thread scheduling loop */
/* */
/* CALLED BY */
/* */
/* Hardware */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* xx-xx-xxxx Scott Larson Initial Version 6.x */
/* */
/**************************************************************************/
.globl _tx_thread_smp_initialize_wait
_tx_thread_smp_initialize_wait:
#ifdef TX_ENABLE_64BIT_FPU_SUPPORT
cfc1 $8, $31 # Pickup current FPU control reg
la $9, _tx_thread_smp_initial_fpu_control_register
sw $8, ($9) # Save FPU control reg
#endif
/* Pickup the release cores flag. */
la $8, _tx_thread_smp_release_cores_flag # Build address of release cores flag
wait_for_release:
lw $9, ($8) # Pickup release cores flag
beq $9, $0, wait_for_release # Wait here until it is set
nop
/* Core 0 has released this core. */
/* Pickup the core ID. */
mfc0 $8, UserLocal # Pickup VPE ID
sll $8, $8, 2 # Build index based on VPE number
/* Clear this core's system state variable. */
la $9, _tx_thread_system_state # Build address of system state variable
addu $9, $9, $8 #
sw $0, ($9) # Clear this VPE's system state entry
/* Now wait for core 0 to finish it's initialization. */
di # Disable interrupts
ehb #
mfc0 $8, $12 # Pickup current SR
ori $8, $8, INITIAL_SR # Build initial SR
mtc0 $8, $12 # Setup SR
core_0_wait_loop:
la $8, _tx_thread_system_state # Build address of system state variable of logical VPE 0
lw $9, ($8) # Pickup system state
bne $9, $0, core_0_wait_loop # If non-zero, keep waiting
nop #
la $8, _tx_thread_schedule # Otherwise, initialization is done
jr $8 # Enter main scheduling loop
nop #
ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_low_level_initialize.S
+73
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@@ -0,0 +1,73 @@
/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Thread - Low Level SMP Support */
/** */
/**************************************************************************/
/**************************************************************************/
#define C0_Status $12
#define C0_Cause $13
.text
.set noreorder
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_low_level_initialize MIPS32_interAptiv/GNU */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function performs low-level initialization of the booting */
/* core. */
/* */
/* INPUT */
/* */
/* number_of_cores Number of cores */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* _tx_initialize_high_level ThreadX high-level init */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* xx-xx-xxxx Scott Larson Initial Version 6.x */
/* */
/**************************************************************************/
.globl _tx_thread_smp_low_level_initialize
_tx_thread_smp_low_level_initialize:
/* Nothing needed in this port. */
jr.hb $31 # Return to caller
nop # Clear hazards
ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_protect.S
+119
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@@ -0,0 +1,119 @@
/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Thread - Low Level SMP Support */
/** */
/**************************************************************************/
/**************************************************************************/
#define UserLocal $4,2
#define C0_Status $12
.text
.set noreorder
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_protect MIPS32_interAptiv/GNU */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function gets protection for running inside the ThreadX */
/* source. This is ccomplished by a combination of a test-and-set */
/* flag and periodically disabling interrupts. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* Previous Status Register */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* ThreadX Source */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* xx-xx-xxxx Scott Larson Initial Version 6.x */
/* */
/**************************************************************************/
.globl _tx_thread_smp_protect
_tx_thread_smp_protect:
di $2 # Disable interrupts
ehb #
sync
mfc0 $25, UserLocal # Pickup VPE ID
la $10, _tx_thread_smp_protection # Build address to protection structure
lw $9, ($10) # Pickup the protection
bne $9, $0, _already_owned # If non-zero, then the protection is already in force
nop #
ll $11, ($10) # Pickup the protection in force flag
bne $11, $0, _get_retry # Is the protection still available?
li $11, 1 # Build protection in force flag
sc $11, ($10) # Attempt to get the semaphore
beq $11, $0, _get_retry # If successful, we got the protection!
sync
sw $25, 8($10) # Save VPE
sw $11, 12($10) # Setup the initial count
#ifdef TX_THREAD_SMP_DEBUG_ENABLE
sll $13, $25, 2 # Build index based on VPE number
la $12, _tx_thread_current_ptr # Pickup the current thread pointer
addu $12, $12, $13 # Build address of current thread pointer for this VPE
lw $9, ($12) # Pickup current thread pointer
sw $31, 16($10) # Save caller info
sw $2, 20($10) # Save SR
sw $9, 4($10) # Save the current thread pointer
#endif
j $31 # Return to caller
nop
_get_retry:
mtc0 $2, C0_Status # Restore interrupt posture
ehb #
b _tx_thread_smp_protect # Try to get the protection again
nop #
_already_owned:
lw $9, 8($10) # Pickup the owned VPE
beq $9, $25, _have_the_protection # If equal, we already have the protection
lw $12, 12($10) # Pickup protection count
mtc0 $2, C0_Status # Restore interrupt posture
ehb #
b _tx_thread_smp_protect # Try to get the protection again
nop #
_have_the_protection:
addu $12, $12, 1 # Increment
j $31 # Return to caller
sw $12, 12($10) # Store back the protection count
ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_time_get.S
+80
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@@ -0,0 +1,80 @@
/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Thread - Low Level SMP Support */
/** */
/**************************************************************************/
/**************************************************************************/
#define GIC_SH_COUNTER_LO 0xbbdc0010 /* Lower 32-bits of GIC common counter */
.text
.set noreorder
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_time_get MIPS32_interAptiv/GNU */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function gets the global time value that is used for debug */
/* information and event tracing. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* 32-bit time stamp */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* ThreadX Source */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* xx-xx-xxxx Scott Larson Initial Version 6.x */
/* */
/**************************************************************************/
.globl _tx_thread_smp_time_get
_tx_thread_smp_time_get:
la $8, GIC_SH_COUNTER_LO # Pickup address of GIC_SH_COUNTER_LO
lw $2, 0($8) # Pickup 32-bit counter
jr $31
nop
.globl _tx_thread_smp_time_get_upper
_tx_thread_smp_time_get_upper:
addu $2, $0, 0 # Just return 0 for the upper, since the time in only 32-bits
jr $31
nop
ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_unprotect.S
+102
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@@ -0,0 +1,102 @@
/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Thread - Low Level SMP Support */
/** */
/**************************************************************************/
/**************************************************************************/
#define UserLocal $4,2
#define C0_Status $12
.text
.set noreorder
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_unprotect MIPS32_interAptiv/GNU */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function releases previously obtained protection. The supplied */
/* previous SR is restored. If the value of _tx_thread_system_state */
/* and _tx_thread_preempt_disable are both zero, then multithreading */
/* is enabled as well. */
/* */
/* INPUT */
/* */
/* Previous Status Register */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* ThreadX Source */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* xx-xx-xxxx Scott Larson Initial Version 6.x */
/* */
/**************************************************************************/
.globl _tx_thread_smp_unprotect
_tx_thread_smp_unprotect:
di # Disable interrupts
ehb #
sync
mfc0 $25, UserLocal # Pickup VPE ID
la $10, _tx_thread_smp_protection # Build address of protection structure
lw $9, 8($10) # Pickup owning VPE
bne $9, $25, _still_protected # Not the same VPE, protection is in force somewhere else
lw $12, 12($10) # Pickup protection count
beq $12, $0, _still_protected # If zero, protection is not in force anymore
subu $12, $12, 1 # Decrement
sw $12, 12($10) # Store back the protection count
bne $12, $0, _still_protected # If non-zero, nested protection condition
nop #
la $11, _tx_thread_preempt_disable # Build address of preempt disable flag
lw $12, ($11) # Pickup preempt disable flag
bne $12, $0, _still_protected # Don't release protection if preempt disable flag is set
li $8, 0xFFFFFFFF # Setup invalid value
sw $8, 8($10) # Mark VPE as invalid
#ifdef TX_THREAD_SMP_DEBUG_ENABLE
sw $31, 24($10) # Remember the caller of the unprotect
#endif
_release_protect_loop:
sync
sw $0, ($10) # Clear protection
sync
_still_protected:
mtc0 $4, C0_Status # Restore interrupt posture
jr.hb $31 # Return to caller
nop #
ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_stack_build.S
+279
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ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_system_return.S
+206
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ports_smp/mips32_interaptiv_smp/gnu/src/tx_timer_interrupt.S
+219
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ports_smp/mips32_interaptiv_smp/green/example_build/boot.h
+99
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@@ -0,0 +1,99 @@
/*
* boot.h
*
* Created on: Jan 12, 2011
* Author: MIPS TECHNOLOGIES, INC
*/
/*
Unpublished work (c) MIPS Technologies, Inc. All rights reserved. Unpublished rights reserved
under the copyright laws of the United States of America and other countries.
This code is confidential and proprietary to MIPS Technologies, Inc. ("MIPS Technologies") and
may be disclosed only as permitted in writing by MIPS Technologies or an authorized third party.
Any copying, reproducing, modifying, use or disclosure of this code (in whole or in part) that is
not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly
prohibited. At a minimum, this code is protected under trade secret, unfair competition, and
copyright laws. Violations thereof may result in criminal penalties and fines.
MIPS Technologies reserves the right to change this code to improve function, design or
otherwise. MIPS Technologies does not assume any liability arising out of the application or use
of this code, or of any error or omission in such code. Any warranties, whether express, statutory,
implied or otherwise, including but not limited to the implied warranties of merchantability or
fitness for a particular purpose, are excluded. Except as expressly provided in any written license
agreement from MIPS Technologies or an authorized third party, the furnishing of this code does
not give recipient any license to any intellectual property rights, including any patent rights, that
cover this code.
This code shall not be exported, reexported, transferred, or released, directly or indirectly, in
violation of the law of any country or international law, regulation, treaty, Executive Order,
statute, amendments or supplements thereto. Should a conflict arise regarding the export,
reexport, transfer, or release of this code, the laws of the United States of America shall be
the governing law.
This code may only be disclosed to the United States government ("Government"), or to
Government users, with prior written consent from MIPS Technologies or an authorized third
party. This code constitutes one or more of the following: commercial computer software,
commercial computer software documentation or other commercial items. If the user of this
code, or any related documentation of any kind, including related technical data or manuals, is an
agency, department, or other entity of the Government, the use, duplication, reproduction, release,
modification, disclosure, or transfer of this code, or any related documentation of any kind, is
restricted in accordance with Federal Acquisition Regulation 12.212 for civilian agencies and
Defense Federal Acquisition Regulation Supplement 227.7202 for military agencies. The use of
this code by the Government is further restricted in accordance with the terms of the license
agreement(s) and/or applicable contract terms and conditions covering this code from MIPS
Technologies or an authorized third party.
*/
#define LEAF(name)\
.##text;\
.##globl name;\
.##ent name;\
name:
#define END(name)\
.##size name,.-name;\
.##end name
#define GCR_CONFIG_ADDR 0xbfbf8000 // KSEG0 address of the GCR registers
#define GIC_P_BASE_ADDR 0x1bdc0000 // physical address of the GIC
#define GIC_BASE_ADDR 0xbbdc0000 // KSEG0 address address of the GIC
#define CPC_P_BASE_ADDR 0x1bde0001 // physical address of the CPC
#define CPC_BASE_ADDR 0xbbde0000 // KSEG0 address address of the CPC
#define DENALI_CTL_SECTION 0xbbc00000
#define MALTA_DISP_ADDR 0xbf000410
#define STACK_BASE_ADDR 0x82000000 /* Change: Base on memory size. */
#define STACK_SIZE_LOG2 22 /* 4Mbytes each */
/**************************************************************************************
Register use while executing in this file: ("GLOBAL" denotes a common value.)
**************************************************************************************/
#define r1_all_ones $1 /* at Will hold 0xffffffff to simplify bit insertion of 1's. GLOBAL! */
// $2 - $7 (v0, v1 a0 - a3) reserved for program use
#define r8_core_num $8 /* t0 Core number. Only core 0 is active after reset. */
#define r9_vpe_num $9 /* t1 MT ASE VPE number that this TC is bound to (0 if non-MT.) */
#define r10_has_mt_ase $10 /* t2 Core implements the MT ASE. */
#define r11_is_cps $11 /* t3 Core is part of a Coherent Processing System. */
// $12 - $15 (t4 - t7) are free to use
// $16, $17 (s0 and s1) reserved for program use
#define r18_tc_num $18 /* s2 MT ASE TC number (0 if non-MT.) */
#define r19_more_cores $19 /* s3 Number of cores in CPS in addition to core 0. GLOBAL! */
#define r20_more_vpes $20 /* s4 Number of vpes in this core in addition to vpe 0. */
#define r21_more_tcs $21 /* s5 Number of tcs in vpe in addition to the first. */
#define r22_gcr_addr $22 /* s6 Uncached (kseg1) base address of the Global Config Registers. */
#define r23_cpu_num $23 /* s7 Unique per vpe "cpu" identifier (CP0 EBase[CPUNUM]). */
#define r24_malta_word $24 /* t8 Uncached (kseg1) base address of Malta ascii display. GLOBAL! */
#define r25_coreid $25 /* t9 Copy of cp0 PRiD GLOBAL! */
#define r26_int_addr $26 /* k0 Interrupt handler scratch address. */
#define r27_int_data $27 /* k1 Interrupt handler scratch data. */
// $28 gp and $29 sp
#define r30_cpc_addr $30 /* s8 Address of CPC register block after cpc_init. 0 indicates no CPC. */
// $31 ra
ports_smp/mips32_interaptiv_smp/green/example_build/copy_c2_ram.mip
+115
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@@ -0,0 +1,115 @@
/*
* copy_c2_ram.S
*
* Created on: Jan 12, 2011
* Author: MIPS TECHNOLOGIES, INC
* Copy code and data to ram then clear BSS
*/
/*
Unpublished work (c) MIPS Technologies, Inc. All rights reserved. Unpublished rights reserved
under the copyright laws of the United States of America and other countries.
This code is confidential and proprietary to MIPS Technologies, Inc. ("MIPS Technologies") and
may be disclosed only as permitted in writing by MIPS Technologies or an authorized third party.
Any copying, reproducing, modifying, use or disclosure of this code (in whole or in part) that is
not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly
prohibited. At a minimum, this code is protected under trade secret, unfair competition, and
copyright laws. Violations thereof may result in criminal penalties and fines.
MIPS Technologies reserves the right to change this code to improve function, design or
otherwise. MIPS Technologies does not assume any liability arising out of the application or use
of this code, or of any error or omission in such code. Any warranties, whether express, statutory,
implied or otherwise, including but not limited to the implied warranties of merchantability or
fitness for a particular purpose, are excluded. Except as expressly provided in any written license
agreement from MIPS Technologies or an authorized third party, the furnishing of this code does
not give recipient any license to any intellectual property rights, including any patent rights, that
cover this code.
This code shall not be exported, reexported, transferred, or released, directly or indirectly, in
violation of the law of any country or international law, regulation, treaty, Executive Order,
statute, amendments or supplements thereto. Should a conflict arise regarding the export,
reexport, transfer, or release of this code, the laws of the United States of America shall be
the governing law.
This code may only be disclosed to the United States government ("Government"), or to
Government users, with prior written consent from MIPS Technologies or an authorized third
party. This code constitutes one or more of the following: commercial computer software,
commercial computer software documentation or other commercial items. If the user of this
code, or any related documentation of any kind, including related technical data or manuals, is an
agency, department, or other entity of the Government, the use, duplication, reproduction, release,
modification, disclosure, or transfer of this code, or any related documentation of any kind, is
restricted in accordance with Federal Acquisition Regulation 12.212 for civilian agencies and
Defense Federal Acquisition Regulation Supplement 227.7202 for military agencies. The use of
this code by the Government is further restricted in accordance with the terms of the license
agreement(s) and/or applicable contract terms and conditions covering this code from MIPS
Technologies or an authorized third party.
*/
#include <regdef.h>
#include <boot.h>
#define s1_all_ones s1 /* at Will hold 0xffffffff to simplify bit insertion of 1's. */
#define a0_temp_data a0 /* a0 data to be moved */
#define a1_temp_addr a1 /* from address */
#define a2_temp_dest a2 /* to address */
#define a3_temp_mark a3 /* ending address */
.set noreorder # Don't allow the assembler to reorder instructions.
.set noat # Don't allow the assembler to use r1(at) for synthetic instr.
/**************************************************************************************
**************************************************************************************/
LEAF(copy_c2_ram)
li s1_all_ones, 0xffffffff
/* RAMHACK: Link addr == load addr. No copy of code from ROM to RAM required.
// Copy code and read-only/initialized data from FLASH to (uncached) RAM.
la a1_temp_addr, _zap1
ins a1_temp_addr, s1_all_ones, 29, 1
la a2_temp_dest, _ftext_ram
ins a2_temp_dest, s1_all_ones, 29, 1
la a3_temp_mark, _edata_ram
ins a3_temp_mark, s1_all_ones, 29, 1
beq a2_temp_dest, a3_temp_mark, zero_bss
nop
next_ram_word:
lw a0_temp_data, 0(a1_temp_addr)
sw a0_temp_data, 0(a2_temp_dest)
addiu a2_temp_dest, 4
bne a3_temp_mark, a2_temp_dest, next_ram_word
addiu a1_temp_addr, 4
*/
// RAMHACK: Zero sbss in addition to bss.
zero_sbss:
la a1_temp_addr, _start_sbss
ins a1_temp_addr, s1_all_ones, 29, 1
la a3_temp_mark, _end_sbss
ins a3_temp_mark, s1_all_ones, 29, 1
beq a1_temp_addr, a3_temp_mark, zero_bss
nop
next_sbss_word:
sw zero, 0(a1_temp_addr)
addiu a1_temp_addr, 4
bne a1_temp_addr, a3_temp_mark, next_sbss_word
nop
zero_bss:
la a1_temp_addr, _start_bss
ins a1_temp_addr, s1_all_ones, 29, 1
la a3_temp_mark, _end_bss
ins a3_temp_mark, s1_all_ones, 29, 1
beq a1_temp_addr, a3_temp_mark, copy_c2_ram_done
nop
next_bss_word:
sw zero, 0(a1_temp_addr)
addiu a1_temp_addr, 4
bne a1_temp_addr, a3_temp_mark, next_bss_word
nop
copy_c2_ram_done:
jr ra
nop
END(copy_c2_ram)
ports_smp/mips32_interaptiv_smp/green/example_build/cps.h
+883
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File diff suppressed because it is too large Load Diff
ports_smp/mips32_interaptiv_smp/green/example_build/demo_threadx.c
+514
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File diff suppressed because it is too large Load Diff
ports_smp/mips32_interaptiv_smp/green/example_build/demo_threadx.gpj
+27
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@@ -0,0 +1,27 @@
#!gbuild
#component ThreadX Demo
[Program]
-I.
-o demo_threadx.elf
-nostdlib
-Onone
copy_c2_ram.mip
demo_threadx.c
tx_initialize_low_level.mip
start.mip
set_gpr_boot_values.mip
init_gpr.mip
init_tlb.mip
init_itc.mip
init_caches2.mip
init_cp0.mip
init_cm.mip
release_mp.mip
join_domain.mip
init_gic.mip
init_cpc.mip
init_vpe1.mip
init_CoreFPGA6_mem.mip
tx.a
demo_threadx_ram_interAptiv.ld
demo_threadx_interAptiv.con
ports_smp/mips32_interaptiv_smp/green/example_build/demo_threadx_el.gpj
+28
View File
@@ -0,0 +1,28 @@
#!gbuild
#component ThreadX Demo
[Program]
-DTX_ENABLE_EVENT_LOGGING
-I.
-o demo_threadx.elf
-nostdlib
-Onone
copy_c2_ram.mip
demo_threadx.c
tx_initialize_low_level.mip
start.mip
set_gpr_boot_values.mip
init_gpr.mip
init_tlb.mip
init_itc.mip
init_caches2.mip
init_cp0.mip
init_cm.mip
release_mp.mip
join_domain.mip
init_gic.mip
init_cpc.mip
init_vpe1.mip
init_CoreFPGA6_mem.mip
txe.a
demo_threadx_ram_interAptiv.ld
demo_threadx_interAptiv.con
ports_smp/mips32_interaptiv_smp/green/example_build/demo_threadx_interAptiv.con
+17
View File
@@ -0,0 +1,17 @@
target_connection {
{
title = "GHS_Probe_interAptiv_3c2v4t"
type = "Green Hills Debug Probe (mpserv)"
short_type = "mpserv"
args = " -usb"
command = "mpserv -usb"
logfile = ""
mode = ""
setup_script = "demo_threadx_ram_interAptiv_3c2v4t.mbs"
run_mode_partner = ""
run_mode_policy = ""
sane = "yes"
log = "no"
timestamp = "0"
}
}
ports_smp/mips32_interaptiv_smp/green/example_build/demo_threadx_ram_interAptiv.ld
+75
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@@ -0,0 +1,75 @@
MEMORY {
zero_memory : ORIGIN = 0xffff8000, LENGTH = 64K
dram_rsvd1 : ORIGIN = 0x80000000, LENGTH = 0
vector_0x000 : ORIGIN = . LENGTH = 0x100
vector_0x100 : ORIGIN = . LENGTH = 0x080
vector_0x180 : ORIGIN = . LENGTH = 0x080
vector_0x200 : ORIGIN = . LENGTH = 0x080
vector_0x280 : ORIGIN = . LENGTH = 0x080
vector_0x300 : ORIGIN = . LENGTH = 0x080
monitor : ORIGIN = . LENGTH = 1M - 0x380
dram_memory : ORIGIN = . LENGTH = 10M - 1M
dram_rsvd2 : ORIGIN = ., LENGTH = 0
flash_rsvd1 : ORIGIN = 0xbfc00000, LENGTH = 32K
flash_memory : ORIGIN = ., LENGTH = 10M - 32K
flash_rsvd2 : ORIGIN = ., LENGTH = 0
}
DEFAULTS {
heap_reserve = 2M
stack_reserve = 512K
}
//
// Program layout for running out of RAM.
//
//
SECTIONS
{
.zdata ABS : > zero_memory
.zbss ABS : > .
.rozdata ABS : > .
.vector_0x000 : > vector_0x000
.vector_0x100 : > vector_0x100
.vector_0x180 : > vector_0x180
.vector_0x200 : > vector_0x200
.vector_0x280 : > vector_0x280
.vector_0x300 : > vector_0x300
.text : { "start.o(.text) *(.text)" } > dram_memory
.syscall : > .
.secinfo : > .
.fixaddr : > .
.fixtype : > .
.robase ALIGN(8) : > .
.rodata ALIGN(8) : > .
.sdabase ALIGN(8) : > .
.sdata ALIGN(8) : > .
_start_sbss = . ;
.sbss ALIGN(8) : > .
_end_sbss = . ;
.rosdata ALIGN(8) : > .
.data ALIGN(8) : > .
.profile ALIGN(8) : > .
_start_bss = . ;
.bss ALIGN(8) : > .
_end_bss = . ;
.heap ALIGN(8) PAD(heap_reserve) : > .
.stack ALIGN(8) PAD(stack_reserve) : > .
.eventlog align(16) pad(0x10000) :
.free_mem align(16) pad(0x10000) :
//
// These special symbols mark the bounds of RAM and ROM memory.
// They are used by the MULTI debugger.
//
__ghs_ramstart = MEMADDR(dram_rsvd1);
__ghs_ramend = MEMENDADDR(dram_rsvd2);
__ghs_romstart = MEMADDR(flash_rsvd1);
__ghs_romend = MEMENDADDR(flash_rsvd2);
}

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