cpukit/score/cpu: Add the Doxygen file headers

Seventy-two files in the CPU ports had no Doxygen block.  Twenty-nine of
them are assembly files.  Twelve are the ELF definitions of an
architecture.  Doxygen listed none of them.

Give each file a block with @file, @ingroup and @brief.  The brief names
what the file implements and the architecture it belongs to.

Updates #5717.

Assisted-by: Claude:claude-opus-5 claude-code
Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>

cpukit/score/cpu/aarch64/include/machine/elf_machdep.h

@@ -1,3 +1,12 @@
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUAArch64
+ *
+ * @brief This header file provides the ELF definitions of the AArch64
+ *   architecture.
+ */
+
 /* $NetBSD: elf_machdep.h,v 1.4 2018/10/12 01:28:58 ryo Exp $ */
 
 /*-

cpukit/score/cpu/arm/arm-context-validate.S

@@ -1,5 +1,14 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUARM
+ *
+ * @brief This source file contains the implementation of
+ *   _CPU_Context_validate() for the ARM architecture.
+ */
+
 /*
  * Copyright (C) 2013, 2017 embedded brains GmbH & Co. KG
  *

cpukit/score/cpu/arm/arm-context-volatile-clobber.S

@@ -1,5 +1,14 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUARM
+ *
+ * @brief This source file contains the implementation of
+ *   _CPU_Context_volatile_clobber() for the ARM architecture.
+ */
+
 /*
  * Copyright (C) 2013, 2017 embedded brains GmbH & Co. KG
  *

cpukit/score/cpu/arm/armv4-exception-resume.S

@@ -1,5 +1,14 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUARM
+ *
+ * @brief This source file contains the exception resume support of the ARM
+ *   architecture.
+ */
+
 /*
  * Copyright (c) 2024 embedded brains GmbH & Co. KG
  *

cpukit/score/cpu/arm/include/machine/elf_machdep.h

@@ -1,3 +1,12 @@
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUARM
+ *
+ * @brief This header file provides the ELF definitions of the ARM
+ *   architecture.
+ */
+
 /*	$NetBSD: elf_machdep.h,v 1.19 2017/11/06 03:47:45 christos Exp $	*/
 
 #ifndef _ARM_ELF_MACHDEP_H_

cpukit/score/cpu/i386/include/machine/elf_machdep.h

@@ -1,3 +1,12 @@
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUi386
+ *
+ * @brief This header file provides the ELF definitions of the i386
+ *   architecture.
+ */
+
 /*	$NetBSD: elf_machdep.h,v 1.10 2009/05/30 05:56:52 skrll Exp $	*/
 
 #define	ELF32_MACHDEP_ENDIANNESS	ELFDATA2LSB

cpukit/score/cpu/m68k/__m68k_read_tp.c

@@ -1,5 +1,13 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUm68k
+ *
+ * @brief This source file contains the implementation of __m68k_read_tp().
+ */
+
 /*
  * Copyright (C) 2014, 2015 embedded brains GmbH & Co. KG
  *

cpukit/score/cpu/m68k/cpu_asm.S

@@ -1,5 +1,14 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUm68k
+ *
+ * @brief This source file contains the assembly language support of the
+ *   m68k CPU port.
+ */
+
 /*  cpu_asm.s
  *
  *  This file contains all assembly code for the MC68020 implementation

cpukit/score/cpu/m68k/include/machine/elf_machdep.h

@@ -1,3 +1,12 @@
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUm68k
+ *
+ * @brief This header file provides the ELF definitions of the m68k
+ *   architecture.
+ */
+
 /*	$NetBSD: elf_machdep.h,v 1.7 2002/01/28 21:34:48 thorpej Exp $	*/
 
 #define	ELF32_MACHDEP_ENDIANNESS	ELFDATA2MSB

cpukit/score/cpu/m68k/m68k-exception-frame-print.c

@@ -1,5 +1,14 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUm68k
+ *
+ * @brief This source file contains the implementation of
+ *   _CPU_Exception_frame_print() for the m68k architecture.
+ */
+
 /*
  * Copyright (c) 2012 embedded brains GmbH & Co. KG
  *

cpukit/score/cpu/microblaze/include/machine/elf_machdep.h

@@ -1,5 +1,14 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUMicroBlaze
+ *
+ * @brief This header file provides the ELF definitions of the MicroBlaze
+ *   architecture.
+ */
+
 /*
  * Copyright (C) 2023 On-Line Applications Research Corporation (OAR)
  *

cpukit/score/cpu/mips/cpu_asm.S

@@ -1,5 +1,14 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUMIPS
+ *
+ * @brief This source file contains the assembly language support of the
+ *   MIPS CPU port.
+ */
+
 /*
  *  This file contains the basic algorithms for all assembly code used
  *  in an specific CPU port of RTEMS.  These algorithms must be implemented

cpukit/score/cpu/mips/include/machine/elf_machdep.h

@@ -1,3 +1,12 @@
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUMIPS
+ *
+ * @brief This header file provides the ELF definitions of the MIPS
+ *   architecture.
+ */
+
 /*	$NetBSD: elf_machdep.h,v 1.15 2011/03/15 07:39:22 matt Exp $	*/
 
 #ifndef _MIPS_ELF_MACHDEP_H_

cpukit/score/cpu/moxie/cpu.c

@@ -1,5 +1,14 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUMoxie
+ *
+ * @brief This source file contains the implementation of the Moxie CPU
+ *   port.
+ */
+
 /*
  *  Moxie CPU Dependent Source
  *

cpukit/score/cpu/moxie/cpu_asm.S

@@ -1,5 +1,14 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUMoxie
+ *
+ * @brief This source file contains the assembly language support of the
+ *   Moxie CPU port.
+ */
+
 /*
  * Moxie CPU functions
  *   Copyright (C) 2011 Anthony Green

cpukit/score/cpu/moxie/include/machine/elf_machdep.h

@@ -1,3 +1,12 @@
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUMoxie
+ *
+ * @brief This header file provides the ELF definitions of the Moxie
+ *   architecture.
+ */
+
 #define ELF32_MACHDEP_ENDIANNESS		ELFDATA2MSB
 
 #define ELF32_MACHDEP_ID_CASES \

cpukit/score/cpu/moxie/moxie-exception-frame-print.c

@@ -1,5 +1,14 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUMoxie
+ *
+ * @brief This source file contains the implementation of
+ *   _CPU_Exception_frame_print() for the Moxie architecture.
+ */
+
 /*
  * Copyright (c) 2013  Anthony Green
  *

cpukit/score/cpu/nios2/include/machine/elf_machdep.h

@@ -1,3 +1,12 @@
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUnios2
+ *
+ * @brief This header file provides the ELF definitions of the Nios II
+ *   architecture.
+ */
+
 /*	$NetBSD: elf_machdep.h,v 1.7 2002/01/28 21:34:48 thorpej Exp $	*/
 
 #define	ELF32_MACHDEP_ENDIANNESS	ELFDATA2MSB

cpukit/score/cpu/nios2/include/rtems/score/nios2-count-zeros.h

@@ -1,5 +1,14 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUnios2
+ *
+ * @brief This header file provides the count zeros interfaces of the Nios
+ *   II CPU port.
+ */
+
 /*
  * Author: Jeffrey O. Hill
  *

cpukit/score/cpu/nios2/nios2-context-initialize.c

@@ -1,5 +1,14 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUnios2
+ *
+ * @brief This source file contains the implementation of
+ *   _CPU_Context_Initialize() for the Nios II architecture.
+ */
+
 /*
  * Copyright (C) 2011, 2021 embedded brains GmbH & Co. KG
  *

cpukit/score/cpu/nios2/nios2-context-switch.S

@@ -1,5 +1,14 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUnios2
+ *
+ * @brief This source file contains the implementation of
+ *   _CPU_Context_switch() for the Nios II architecture.
+ */
+
 /*
  * Copyright (c) 2011 embedded brains GmbH & Co. KG
  *

cpukit/score/cpu/nios2/nios2-context-validate.S

@@ -1,5 +1,14 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUnios2
+ *
+ * @brief This source file contains the implementation of
+ *   _CPU_Context_validate() for the Nios II architecture.
+ */
+
 /*
  * Copyright (c) 2013 embedded brains GmbH & Co. KG
  *

cpukit/score/cpu/nios2/nios2-context-volatile-clobber.S

@@ -1,5 +1,14 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUnios2
+ *
+ * @brief This source file contains the implementation of
+ *   _CPU_Context_volatile_clobber() for the Nios II architecture.
+ */
+
 /*
  * Copyright (c) 2013 embedded brains GmbH & Co. KG
  *

cpukit/score/cpu/nios2/nios2-eic-il-low-level.S

@@ -1,5 +1,14 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUnios2
+ *
+ * @brief This source file contains the external interrupt controller
+ *   dispatch of the Nios II CPU port.
+ */
+
 /*
  * Copyright (C) 2011, 2015 embedded brains GmbH & Co. KG
  *

cpukit/score/cpu/nios2/nios2-exception-frame-print.c

@@ -1,5 +1,14 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUnios2
+ *
+ * @brief This source file contains the implementation of
+ *   _CPU_Exception_frame_print() for the Nios II architecture.
+ */
+
 /*
  * Copyright (c) 2012 embedded brains GmbH & Co. KG
  *

cpukit/score/cpu/nios2/nios2-iic-low-level.S

@@ -1,5 +1,14 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUnios2
+ *
+ * @brief This source file contains the internal interrupt controller vector
+ *   of the Nios II CPU port.
+ */
+
 /*
  *  This file contains all assembly code for the
  *  NIOS2 implementation of RTEMS.

cpukit/score/cpu/nios2/nios2-isr-get-level.c

@@ -1,5 +1,15 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUnios2
+ *
+ * @brief This source file contains the implementation of
+ *   _CPU_ISR_Get_level() and _CPU_ISR_Is_enabled() for the Nios II
+ *   architecture.
+ */
+
 /*
  * Copyright (C) 2011, 2016 embedded brains GmbH & Co. KG
  *

cpukit/score/cpu/nios2/nios2-isr-is-in-progress.c

@@ -1,5 +1,14 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUnios2
+ *
+ * @brief This source file contains the implementation of
+ *   _ISR_Is_in_progress() for the Nios II architecture.
+ */
+
 /*
  * Copyright (c) 2011 embedded brains GmbH & Co. KG
  *

cpukit/score/cpu/nios2/nios2-mpu-add-region.c

@@ -1,5 +1,14 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUnios2
+ *
+ * @brief This source file contains the implementation which adds a Nios II
+ *   memory protection unit region.
+ */
+
 /*
  * Copyright (c) 2011 embedded brains GmbH & Co. KG
  *

cpukit/score/cpu/nios2/nios2-mpu-configuration.c

@@ -1,5 +1,14 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUnios2
+ *
+ * @brief This source file contains the memory protection unit configuration
+ *   of the Nios II CPU port.
+ */
+
 /*
  * Copyright (c) 2011 embedded brains GmbH & Co. KG
  *

cpukit/score/cpu/nios2/nios2-mpu-reset.c

@@ -1,5 +1,14 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUnios2
+ *
+ * @brief This source file contains the implementation of
+ *   _Nios2_MPU_Reset().
+ */
+
 /*
  * Copyright (c) 2011 embedded brains GmbH & Co. KG
  *

cpukit/score/cpu/no_cpu/cpucounterfrequency.c

@@ -1,5 +1,14 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUExample
+ *
+ * @brief This source file contains the implementation of
+ *   _CPU_Counter_frequency() of the example CPU port.
+ */
+
 /*
  * Copyright (c) 2018 embedded brains GmbH & Co. KG
  *

cpukit/score/cpu/no_cpu/cpucounterread.c

@@ -1,5 +1,14 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUExample
+ *
+ * @brief This source file contains the implementation of
+ *   _CPU_Counter_read() of the example CPU port.
+ */
+
 /*
  * Copyright (c) 2014 embedded brains GmbH & Co. KG
  *

cpukit/score/cpu/no_cpu/include/rtems/score/no_cpu.h

@@ -1,5 +1,14 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUExample
+ *
+ * @brief This header file provides the architecture definitions of the
+ *   example CPU port.
+ */
+
 /*  no_cpu.h
  *
  *  This file sets up basic CPU dependency settings based on

cpukit/score/cpu/or1k/cpu.c

@@ -1,5 +1,14 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUor1k
+ *
+ * @brief This source file contains the implementation of the OpenRISC 1000
+ *   CPU port.
+ */
+
 /*
  *  Opencore OR1K CPU Dependent Source
  *

cpukit/score/cpu/or1k/or1k-context-initialize.c

@@ -1,5 +1,14 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUor1k
+ *
+ * @brief This source file contains the implementation of
+ *   _CPU_Context_Initialize() for the OpenRISC 1000 architecture.
+ */
+
 /*
  * COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmatary@gmail.com>
  *

cpukit/score/cpu/or1k/or1k-context-switch.S

@@ -1,5 +1,14 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUor1k
+ *
+ * @brief This source file contains the implementation of
+ *   _CPU_Context_switch() for the OpenRISC 1000 architecture.
+ */
+
 /*
  * COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmatary@gmail.com>
  *

cpukit/score/cpu/or1k/or1k-context-validate.S

@@ -1,5 +1,14 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUor1k
+ *
+ * @brief This source file contains the implementation of
+ *   _CPU_Context_validate() for the OpenRISC 1000 architecture.
+ */
+
 /*
  * COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmatary@gmail.com>
  *

cpukit/score/cpu/or1k/or1k-context-volatile-clobber.S

@@ -1,5 +1,14 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUor1k
+ *
+ * @brief This source file contains the implementation of
+ *   _CPU_Context_volatile_clobber() for the OpenRISC 1000 architecture.
+ */
+
 /*
  * COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmatary@gmail.com>
  *

cpukit/score/cpu/or1k/or1k-exception-default.c

@@ -1,5 +1,14 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUor1k
+ *
+ * @brief This source file contains the default exception handler of the
+ *   OpenRISC 1000 architecture.
+ */
+
 /*
  * COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmatary@gmail.com>
  *

cpukit/score/cpu/or1k/or1k-exception-frame-print.c

@@ -1,5 +1,14 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUor1k
+ *
+ * @brief This source file contains the implementation of
+ *   _CPU_Exception_frame_print() for the OpenRISC 1000 architecture.
+ */
+
 /*
  * COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmatary@gmail.com>
  *

cpukit/score/cpu/powerpc/include/machine/elf_machdep.h

@@ -1,3 +1,12 @@
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUPowerPC
+ *
+ * @brief This header file provides the ELF definitions of the PowerPC
+ *   architecture.
+ */
+
 /*	$NetBSD: elf_machdep.h,v 1.9 2011/01/15 10:00:07 matt Exp $	*/
 
 #define	ELF32_MACHDEP_ENDIANNESS	ELFDATA2MSB

cpukit/score/cpu/powerpc/ppc-context-validate.S

@@ -1,5 +1,14 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUPowerPC
+ *
+ * @brief This source file contains the implementation of
+ *   _CPU_Context_validate() for the PowerPC architecture.
+ */
+
 /*
  * Copyright (C) 2013, 2020 embedded brains GmbH & Co. KG
  *

cpukit/score/cpu/powerpc/ppc-context-volatile-clobber.S

@@ -1,5 +1,14 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUPowerPC
+ *
+ * @brief This source file contains the implementation of
+ *   _CPU_Context_volatile_clobber() for the PowerPC architecture.
+ */
+
 /*
  * Copyright (C) 2013, 2017 embedded brains GmbH & Co. KG
  *

cpukit/score/cpu/powerpc/ppc-isr-disable-mask.S

@@ -1,5 +1,14 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUPowerPC
+ *
+ * @brief This source file contains the interrupt disable mask of the
+ *   PowerPC architecture.
+ */
+
 /*
  * Copyright (c) 2014 embedded brains GmbH & Co. KG
  *

cpukit/score/cpu/riscv/cpu.c

@@ -1,3 +1,12 @@
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPURISCV
+ *
+ * @brief This source file contains the implementation of the RISC-V CPU
+ *   port.
+ */
+
 /*
  * Copyright (c) 2018 embedded brains GmbH & Co. KG
  *

cpukit/score/cpu/riscv/include/libcpu/access.h

@@ -1,5 +1,14 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPURISCV
+ *
+ * @brief This header file provides the access function interfaces of the
+ *   RISC-V CPU port.
+ */
+
 /*
  *  access.h  - access routines for SPARC. SPARC is big endian only.
  *

cpukit/score/cpu/riscv/include/libcpu/byteorder.h

@@ -1,5 +1,14 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPURISCV
+ *
+ * @brief This header file provides the byte order access interfaces of the
+ *   RISC-V CPU port.
+ */
+
 /*
  * Copyright (C) 2019 Jiri Gaisler <jiri@gaisler.se>
  *

cpukit/score/cpu/riscv/include/machine/elf_machdep.h

@@ -1,3 +1,12 @@
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPURISCV
+ *
+ * @brief This header file provides the ELF definitions of the RISC-V
+ *   architecture.
+ */
+
 /* $NetBSD: elf_machdep.h,v 1.6 2017/11/06 03:47:48 christos Exp $ */
 
 /*-

cpukit/score/cpu/riscv/riscv-context-initialize.c

@@ -1,3 +1,12 @@
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPURISCV
+ *
+ * @brief This source file contains the implementation of
+ *   _CPU_Context_Initialize() for the RISC-V architecture.
+ */
+
 /*
  * Copyright (c) 2018 embedded brains GmbH & Co. KG
  *

cpukit/score/cpu/riscv/riscv-context-switch.S

@@ -1,3 +1,12 @@
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPURISCV
+ *
+ * @brief This source file contains the implementation of
+ *   _CPU_Context_switch() for the RISC-V architecture.
+ */
+
 /*
  * Copyright (c) 2018 embedded brains GmbH & Co. KG
  *

cpukit/score/cpu/riscv/riscv-context-validate.S

@@ -1,3 +1,12 @@
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPURISCV
+ *
+ * @brief This source file contains the implementation of
+ *   _CPU_Context_validate() for the RISC-V architecture.
+ */
+
 /*
  * Copyright (c) 2018 embedded brains GmbH & Co. KG
  * Copyright (c) 2015 Hesham Almatary <hesham@alumni.york.ac.uk>

cpukit/score/cpu/riscv/riscv-context-volatile-clobber.S

@@ -1,3 +1,12 @@
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPURISCV
+ *
+ * @brief This source file contains the implementation of
+ *   _CPU_Context_volatile_clobber() for the RISC-V architecture.
+ */
+
 /*
  * Copyright (c) 2018 embedded brains GmbH & Co. KG
  * Copyright (c) 2015 Hesham Almatary <hesham@alumni.york.ac.uk>

cpukit/score/cpu/riscv/riscv-counter.S

@@ -1,3 +1,11 @@
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPURISCV
+ *
+ * @brief This source file contains the CPU counter of the RISC-V CPU port.
+ */
+
 /*
  * Copyright (c) 2018 embedded brains GmbH & Co. KG
  *

cpukit/score/cpu/riscv/riscv-exception-frame-print.c

@@ -1,3 +1,12 @@
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPURISCV
+ *
+ * @brief This source file contains the implementation of
+ *   _CPU_Exception_frame_print() for the RISC-V architecture.
+ */
+
 /*
  * Copyright (c) 2018 embedded brains GmbH & Co. KG
  * Copyright (c) 2015 Hesham Almatary <hesham@alumni.york.ac.uk>

cpukit/score/cpu/sparc/access_le.c

@@ -1,5 +1,14 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUSPARC
+ *
+ * @brief This source file contains the little endian access functions of
+ *   the SPARC CPU port.
+ */
+
 /*
  *  Little-endian access routines for SPARC
  *

cpukit/score/cpu/sparc/cpu_asm.S

@@ -1,5 +1,14 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUSPARC
+ *
+ * @brief This source file contains the assembly language support of the
+ *   SPARC CPU port.
+ */
+
 /*  cpu_asm.s
  *
  *  This file contains the basic algorithms for all assembly code used

cpukit/score/cpu/sparc/include/libcpu/access.h

@@ -1,5 +1,14 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUSPARC
+ *
+ * @brief This header file provides the access function interfaces of the
+ *   SPARC CPU port.
+ */
+
 /*
  *  access.h  - access routines for SPARC. SPARC is big endian only.
  *

cpukit/score/cpu/sparc/include/libcpu/byteorder.h

@@ -1,5 +1,14 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUSPARC
+ *
+ * @brief This header file provides the byte order access interfaces of the
+ *   SPARC CPU port.
+ */
+
 /*
  *  byteorder.h  - Endian conversion for SPARC. SPARC is big endian only.
  *

cpukit/score/cpu/sparc/include/machine/elf_machdep.h

@@ -1,3 +1,12 @@
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUSPARC
+ *
+ * @brief This header file provides the ELF definitions of the SPARC
+ *   architecture.
+ */
+
 /*	$NetBSD: elf_machdep.h,v 1.7 2009/05/30 05:56:53 skrll Exp $	*/
 
 #define ELF32_MACHDEP_ENDIANNESS	ELFDATA2MSB

cpukit/score/cpu/sparc/sparc-access.S

@@ -1,5 +1,14 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUSPARC
+ *
+ * @brief This source file contains the assembly language access functions
+ *   of the SPARC CPU port.
+ */
+
 /*
  *  Optimized access routines for SPARC.
  *

cpukit/score/cpu/sparc/sparc-context-validate.S

@@ -1,5 +1,14 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUSPARC
+ *
+ * @brief This source file contains the implementation of
+ *   _CPU_Context_validate() for the SPARC architecture.
+ */
+
 /*
  * Copyright (C) 2015, 2017 embedded brains GmbH & Co. KG
  *

cpukit/score/cpu/sparc/sparc-context-volatile-clobber.S

@@ -1,5 +1,14 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUSPARC
+ *
+ * @brief This source file contains the implementation of
+ *   _CPU_Context_volatile_clobber() for the SPARC architecture.
+ */
+
 /*
  * Copyright (c) 2015 embedded brains GmbH & Co. KG
  *

cpukit/score/cpu/sparc/sparc-isr-handler.S

@@ -1,5 +1,14 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUSPARC
+ *
+ * @brief This source file contains the interrupt handler entry of the SPARC
+ *   architecture.
+ */
+
 /*
  *  This file contains the basic algorithms for all assembly code used
  *  in an specific CPU port of RTEMS.  These algorithms must be implemented

cpukit/score/cpu/sparc/syscall.S

@@ -1,3 +1,12 @@
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUSPARC
+ *
+ * @brief This source file contains the system call traps of the SPARC CPU
+ *   port.
+ */
+
 /*
  *  systrap.S
  *

cpukit/score/cpu/sparc/window.S

@@ -1,3 +1,12 @@
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUSPARC
+ *
+ * @brief This source file contains the register window flush support of the
+ *   SPARC CPU port.
+ */
+
 /*
  *  window.s
  *

cpukit/score/cpu/x86_64/include/machine/elf_machdep.h

@@ -1,3 +1,12 @@
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUx86_64
+ *
+ * @brief This header file provides the ELF definitions of the x86-64
+ *   architecture.
+ */
+
 /*	$NetBSD: elf_machdep.h,v 1.4.18.1 2017/12/03 11:35:47 jdolecek Exp $	*/
 
 #if !defined __i386__

cpukit/score/cpu/x86_64/include/rtems/score/cpu_asm.h

@@ -1,5 +1,14 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUx86_64
+ *
+ * @brief This header file provides the assembly language interfaces of the
+ *   x86-64 CPU port.
+ */
+
 /*
  * Copyright (c) 2018 Amaan Cheval <amaan.cheval@gmail.com>
  *

cpukit/score/cpu/x86_64/include/rtems/score/idt.h

@@ -1,5 +1,14 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUx86_64
+ *
+ * @brief This header file provides the interrupt descriptor table
+ *   interfaces of the x86-64 CPU port.
+ */
+
 /*
  * Copyright (c) 2018 Amaan Cheval <amaan.cheval@gmail.com>
  *

cpukit/score/cpu/x86_64/include/rtems/score/x86_64.h

@@ -1,3 +1,12 @@
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUx86_64
+ *
+ * @brief This header file provides the architecture definitions of the
+ *   x86-64 CPU port.
+ */
+
 /*
  * Copyright (c) 2018 Amaan Cheval <amaan.cheval@gmail.com>
  *

cpukit/score/cpu/x86_64/x86_64-context-initialize.c

@@ -1,3 +1,12 @@
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUx86_64
+ *
+ * @brief This source file contains the implementation of
+ *   _CPU_Context_Initialize() for the x86-64 architecture.
+ */
+
 /*
  * Copyright (c) 2018 Amaan Cheval <amaan.cheval@gmail.com>
  *

cpukit/score/cpu/x86_64/x86_64-context-switch.S

@@ -1,5 +1,14 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUx86_64
+ *
+ * @brief This source file contains the implementation of
+ *   _CPU_Context_switch() for the x86-64 architecture.
+ */
+
 /*
  * Copyright (C) 2024 Matheus Pecoraro
  * Copyright (c) 2018 Amaan Cheval <amaan.cheval@gmail.com>