From 8c4467758be0091ba1d3f90d76e2700752e0c4d0 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Wed, 19 Aug 2026 05:35:56 +0200 Subject: [PATCH] cpukit/score/cpu: Add the Doxygen file headers Seventy-two files in the CPU ports had no Doxygen block. Twenty-nine of them are assembly files. Twelve are the ELF definitions of an architecture. Doxygen listed none of them. Give each file a block with @file, @ingroup and @brief. The brief names what the file implements and the architecture it belongs to. Updates #5717. Assisted-by: Claude:claude-opus-5 claude-code Signed-off-by: Sebastian Huber --- cpukit/score/cpu/aarch64/include/machine/elf_machdep.h | 9 +++++++++ cpukit/score/cpu/arm/arm-context-validate.S | 9 +++++++++ cpukit/score/cpu/arm/arm-context-volatile-clobber.S | 9 +++++++++ cpukit/score/cpu/arm/armv4-exception-resume.S | 9 +++++++++ cpukit/score/cpu/arm/include/machine/elf_machdep.h | 9 +++++++++ cpukit/score/cpu/i386/include/machine/elf_machdep.h | 9 +++++++++ cpukit/score/cpu/m68k/__m68k_read_tp.c | 8 ++++++++ cpukit/score/cpu/m68k/cpu_asm.S | 9 +++++++++ cpukit/score/cpu/m68k/include/machine/elf_machdep.h | 9 +++++++++ cpukit/score/cpu/m68k/m68k-exception-frame-print.c | 9 +++++++++ .../score/cpu/microblaze/include/machine/elf_machdep.h | 9 +++++++++ cpukit/score/cpu/mips/cpu_asm.S | 9 +++++++++ cpukit/score/cpu/mips/include/machine/elf_machdep.h | 9 +++++++++ cpukit/score/cpu/moxie/cpu.c | 9 +++++++++ cpukit/score/cpu/moxie/cpu_asm.S | 9 +++++++++ cpukit/score/cpu/moxie/include/machine/elf_machdep.h | 9 +++++++++ cpukit/score/cpu/moxie/moxie-exception-frame-print.c | 9 +++++++++ cpukit/score/cpu/nios2/include/machine/elf_machdep.h | 9 +++++++++ .../cpu/nios2/include/rtems/score/nios2-count-zeros.h | 9 +++++++++ cpukit/score/cpu/nios2/nios2-context-initialize.c | 9 +++++++++ cpukit/score/cpu/nios2/nios2-context-switch.S | 9 +++++++++ cpukit/score/cpu/nios2/nios2-context-validate.S | 9 +++++++++ .../score/cpu/nios2/nios2-context-volatile-clobber.S | 9 +++++++++ cpukit/score/cpu/nios2/nios2-eic-il-low-level.S | 9 +++++++++ cpukit/score/cpu/nios2/nios2-exception-frame-print.c | 9 +++++++++ cpukit/score/cpu/nios2/nios2-iic-low-level.S | 9 +++++++++ cpukit/score/cpu/nios2/nios2-isr-get-level.c | 10 ++++++++++ cpukit/score/cpu/nios2/nios2-isr-is-in-progress.c | 9 +++++++++ cpukit/score/cpu/nios2/nios2-mpu-add-region.c | 9 +++++++++ cpukit/score/cpu/nios2/nios2-mpu-configuration.c | 9 +++++++++ cpukit/score/cpu/nios2/nios2-mpu-reset.c | 9 +++++++++ cpukit/score/cpu/no_cpu/cpucounterfrequency.c | 9 +++++++++ cpukit/score/cpu/no_cpu/cpucounterread.c | 9 +++++++++ cpukit/score/cpu/no_cpu/include/rtems/score/no_cpu.h | 9 +++++++++ cpukit/score/cpu/or1k/cpu.c | 9 +++++++++ cpukit/score/cpu/or1k/or1k-context-initialize.c | 9 +++++++++ cpukit/score/cpu/or1k/or1k-context-switch.S | 9 +++++++++ cpukit/score/cpu/or1k/or1k-context-validate.S | 9 +++++++++ cpukit/score/cpu/or1k/or1k-context-volatile-clobber.S | 9 +++++++++ cpukit/score/cpu/or1k/or1k-exception-default.c | 9 +++++++++ cpukit/score/cpu/or1k/or1k-exception-frame-print.c | 9 +++++++++ cpukit/score/cpu/powerpc/include/machine/elf_machdep.h | 9 +++++++++ cpukit/score/cpu/powerpc/ppc-context-validate.S | 9 +++++++++ .../score/cpu/powerpc/ppc-context-volatile-clobber.S | 9 +++++++++ cpukit/score/cpu/powerpc/ppc-isr-disable-mask.S | 9 +++++++++ cpukit/score/cpu/riscv/cpu.c | 9 +++++++++ cpukit/score/cpu/riscv/include/libcpu/access.h | 9 +++++++++ cpukit/score/cpu/riscv/include/libcpu/byteorder.h | 9 +++++++++ cpukit/score/cpu/riscv/include/machine/elf_machdep.h | 9 +++++++++ cpukit/score/cpu/riscv/riscv-context-initialize.c | 9 +++++++++ cpukit/score/cpu/riscv/riscv-context-switch.S | 9 +++++++++ cpukit/score/cpu/riscv/riscv-context-validate.S | 9 +++++++++ .../score/cpu/riscv/riscv-context-volatile-clobber.S | 9 +++++++++ cpukit/score/cpu/riscv/riscv-counter.S | 8 ++++++++ cpukit/score/cpu/riscv/riscv-exception-frame-print.c | 9 +++++++++ cpukit/score/cpu/sparc/access_le.c | 9 +++++++++ cpukit/score/cpu/sparc/cpu_asm.S | 9 +++++++++ cpukit/score/cpu/sparc/include/libcpu/access.h | 9 +++++++++ cpukit/score/cpu/sparc/include/libcpu/byteorder.h | 9 +++++++++ cpukit/score/cpu/sparc/include/machine/elf_machdep.h | 9 +++++++++ cpukit/score/cpu/sparc/sparc-access.S | 9 +++++++++ cpukit/score/cpu/sparc/sparc-context-validate.S | 9 +++++++++ .../score/cpu/sparc/sparc-context-volatile-clobber.S | 9 +++++++++ cpukit/score/cpu/sparc/sparc-isr-handler.S | 9 +++++++++ cpukit/score/cpu/sparc/syscall.S | 9 +++++++++ cpukit/score/cpu/sparc/window.S | 9 +++++++++ cpukit/score/cpu/x86_64/include/machine/elf_machdep.h | 9 +++++++++ cpukit/score/cpu/x86_64/include/rtems/score/cpu_asm.h | 9 +++++++++ cpukit/score/cpu/x86_64/include/rtems/score/idt.h | 9 +++++++++ cpukit/score/cpu/x86_64/include/rtems/score/x86_64.h | 9 +++++++++ cpukit/score/cpu/x86_64/x86_64-context-initialize.c | 9 +++++++++ cpukit/score/cpu/x86_64/x86_64-context-switch.S | 9 +++++++++ 72 files changed, 647 insertions(+) diff --git a/cpukit/score/cpu/aarch64/include/machine/elf_machdep.h b/cpukit/score/cpu/aarch64/include/machine/elf_machdep.h index c1d219d715..3bfb6faa50 100644 --- a/cpukit/score/cpu/aarch64/include/machine/elf_machdep.h +++ b/cpukit/score/cpu/aarch64/include/machine/elf_machdep.h @@ -1,3 +1,12 @@ +/** + * @file + * + * @ingroup RTEMSScoreCPUAArch64 + * + * @brief This header file provides the ELF definitions of the AArch64 + * architecture. + */ + /* $NetBSD: elf_machdep.h,v 1.4 2018/10/12 01:28:58 ryo Exp $ */ /*- diff --git a/cpukit/score/cpu/arm/arm-context-validate.S b/cpukit/score/cpu/arm/arm-context-validate.S index 51157071dd..316c138858 100644 --- a/cpukit/score/cpu/arm/arm-context-validate.S +++ b/cpukit/score/cpu/arm/arm-context-validate.S @@ -1,5 +1,14 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUARM + * + * @brief This source file contains the implementation of + * _CPU_Context_validate() for the ARM architecture. + */ + /* * Copyright (C) 2013, 2017 embedded brains GmbH & Co. KG * diff --git a/cpukit/score/cpu/arm/arm-context-volatile-clobber.S b/cpukit/score/cpu/arm/arm-context-volatile-clobber.S index 5cbbb27754..833d080ca8 100644 --- a/cpukit/score/cpu/arm/arm-context-volatile-clobber.S +++ b/cpukit/score/cpu/arm/arm-context-volatile-clobber.S @@ -1,5 +1,14 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUARM + * + * @brief This source file contains the implementation of + * _CPU_Context_volatile_clobber() for the ARM architecture. + */ + /* * Copyright (C) 2013, 2017 embedded brains GmbH & Co. KG * diff --git a/cpukit/score/cpu/arm/armv4-exception-resume.S b/cpukit/score/cpu/arm/armv4-exception-resume.S index 3fde2d04fd..93098f8866 100644 --- a/cpukit/score/cpu/arm/armv4-exception-resume.S +++ b/cpukit/score/cpu/arm/armv4-exception-resume.S @@ -1,5 +1,14 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUARM + * + * @brief This source file contains the exception resume support of the ARM + * architecture. + */ + /* * Copyright (c) 2024 embedded brains GmbH & Co. KG * diff --git a/cpukit/score/cpu/arm/include/machine/elf_machdep.h b/cpukit/score/cpu/arm/include/machine/elf_machdep.h index 6196879481..e36c4e2d84 100644 --- a/cpukit/score/cpu/arm/include/machine/elf_machdep.h +++ b/cpukit/score/cpu/arm/include/machine/elf_machdep.h @@ -1,3 +1,12 @@ +/** + * @file + * + * @ingroup RTEMSScoreCPUARM + * + * @brief This header file provides the ELF definitions of the ARM + * architecture. + */ + /* $NetBSD: elf_machdep.h,v 1.19 2017/11/06 03:47:45 christos Exp $ */ #ifndef _ARM_ELF_MACHDEP_H_ diff --git a/cpukit/score/cpu/i386/include/machine/elf_machdep.h b/cpukit/score/cpu/i386/include/machine/elf_machdep.h index 442c561a9c..5ea46fbb66 100644 --- a/cpukit/score/cpu/i386/include/machine/elf_machdep.h +++ b/cpukit/score/cpu/i386/include/machine/elf_machdep.h @@ -1,3 +1,12 @@ +/** + * @file + * + * @ingroup RTEMSScoreCPUi386 + * + * @brief This header file provides the ELF definitions of the i386 + * architecture. + */ + /* $NetBSD: elf_machdep.h,v 1.10 2009/05/30 05:56:52 skrll Exp $ */ #define ELF32_MACHDEP_ENDIANNESS ELFDATA2LSB diff --git a/cpukit/score/cpu/m68k/__m68k_read_tp.c b/cpukit/score/cpu/m68k/__m68k_read_tp.c index 8c73c96339..b158da530a 100644 --- a/cpukit/score/cpu/m68k/__m68k_read_tp.c +++ b/cpukit/score/cpu/m68k/__m68k_read_tp.c @@ -1,5 +1,13 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUm68k + * + * @brief This source file contains the implementation of __m68k_read_tp(). + */ + /* * Copyright (C) 2014, 2015 embedded brains GmbH & Co. KG * diff --git a/cpukit/score/cpu/m68k/cpu_asm.S b/cpukit/score/cpu/m68k/cpu_asm.S index 4e7c10e130..7112e8b3ec 100644 --- a/cpukit/score/cpu/m68k/cpu_asm.S +++ b/cpukit/score/cpu/m68k/cpu_asm.S @@ -1,5 +1,14 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUm68k + * + * @brief This source file contains the assembly language support of the + * m68k CPU port. + */ + /* cpu_asm.s * * This file contains all assembly code for the MC68020 implementation diff --git a/cpukit/score/cpu/m68k/include/machine/elf_machdep.h b/cpukit/score/cpu/m68k/include/machine/elf_machdep.h index 9a987c69b5..51b0574936 100644 --- a/cpukit/score/cpu/m68k/include/machine/elf_machdep.h +++ b/cpukit/score/cpu/m68k/include/machine/elf_machdep.h @@ -1,3 +1,12 @@ +/** + * @file + * + * @ingroup RTEMSScoreCPUm68k + * + * @brief This header file provides the ELF definitions of the m68k + * architecture. + */ + /* $NetBSD: elf_machdep.h,v 1.7 2002/01/28 21:34:48 thorpej Exp $ */ #define ELF32_MACHDEP_ENDIANNESS ELFDATA2MSB diff --git a/cpukit/score/cpu/m68k/m68k-exception-frame-print.c b/cpukit/score/cpu/m68k/m68k-exception-frame-print.c index c0c30379bd..35208fcde0 100644 --- a/cpukit/score/cpu/m68k/m68k-exception-frame-print.c +++ b/cpukit/score/cpu/m68k/m68k-exception-frame-print.c @@ -1,5 +1,14 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUm68k + * + * @brief This source file contains the implementation of + * _CPU_Exception_frame_print() for the m68k architecture. + */ + /* * Copyright (c) 2012 embedded brains GmbH & Co. KG * diff --git a/cpukit/score/cpu/microblaze/include/machine/elf_machdep.h b/cpukit/score/cpu/microblaze/include/machine/elf_machdep.h index e6d661c596..d275860aeb 100644 --- a/cpukit/score/cpu/microblaze/include/machine/elf_machdep.h +++ b/cpukit/score/cpu/microblaze/include/machine/elf_machdep.h @@ -1,5 +1,14 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUMicroBlaze + * + * @brief This header file provides the ELF definitions of the MicroBlaze + * architecture. + */ + /* * Copyright (C) 2023 On-Line Applications Research Corporation (OAR) * diff --git a/cpukit/score/cpu/mips/cpu_asm.S b/cpukit/score/cpu/mips/cpu_asm.S index 247e7ad202..8c068698df 100644 --- a/cpukit/score/cpu/mips/cpu_asm.S +++ b/cpukit/score/cpu/mips/cpu_asm.S @@ -1,5 +1,14 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUMIPS + * + * @brief This source file contains the assembly language support of the + * MIPS CPU port. + */ + /* * This file contains the basic algorithms for all assembly code used * in an specific CPU port of RTEMS. These algorithms must be implemented diff --git a/cpukit/score/cpu/mips/include/machine/elf_machdep.h b/cpukit/score/cpu/mips/include/machine/elf_machdep.h index 26700ce4ce..1edabc66cc 100644 --- a/cpukit/score/cpu/mips/include/machine/elf_machdep.h +++ b/cpukit/score/cpu/mips/include/machine/elf_machdep.h @@ -1,3 +1,12 @@ +/** + * @file + * + * @ingroup RTEMSScoreCPUMIPS + * + * @brief This header file provides the ELF definitions of the MIPS + * architecture. + */ + /* $NetBSD: elf_machdep.h,v 1.15 2011/03/15 07:39:22 matt Exp $ */ #ifndef _MIPS_ELF_MACHDEP_H_ diff --git a/cpukit/score/cpu/moxie/cpu.c b/cpukit/score/cpu/moxie/cpu.c index b3286c7ed9..46beceec1c 100644 --- a/cpukit/score/cpu/moxie/cpu.c +++ b/cpukit/score/cpu/moxie/cpu.c @@ -1,5 +1,14 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUMoxie + * + * @brief This source file contains the implementation of the Moxie CPU + * port. + */ + /* * Moxie CPU Dependent Source * diff --git a/cpukit/score/cpu/moxie/cpu_asm.S b/cpukit/score/cpu/moxie/cpu_asm.S index bcf0394475..5009fac308 100644 --- a/cpukit/score/cpu/moxie/cpu_asm.S +++ b/cpukit/score/cpu/moxie/cpu_asm.S @@ -1,5 +1,14 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUMoxie + * + * @brief This source file contains the assembly language support of the + * Moxie CPU port. + */ + /* * Moxie CPU functions * Copyright (C) 2011 Anthony Green diff --git a/cpukit/score/cpu/moxie/include/machine/elf_machdep.h b/cpukit/score/cpu/moxie/include/machine/elf_machdep.h index 3f0df23cdc..5cbe70a14e 100644 --- a/cpukit/score/cpu/moxie/include/machine/elf_machdep.h +++ b/cpukit/score/cpu/moxie/include/machine/elf_machdep.h @@ -1,3 +1,12 @@ +/** + * @file + * + * @ingroup RTEMSScoreCPUMoxie + * + * @brief This header file provides the ELF definitions of the Moxie + * architecture. + */ + #define ELF32_MACHDEP_ENDIANNESS ELFDATA2MSB #define ELF32_MACHDEP_ID_CASES \ diff --git a/cpukit/score/cpu/moxie/moxie-exception-frame-print.c b/cpukit/score/cpu/moxie/moxie-exception-frame-print.c index 113d83a78e..11588d6c3b 100644 --- a/cpukit/score/cpu/moxie/moxie-exception-frame-print.c +++ b/cpukit/score/cpu/moxie/moxie-exception-frame-print.c @@ -1,5 +1,14 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUMoxie + * + * @brief This source file contains the implementation of + * _CPU_Exception_frame_print() for the Moxie architecture. + */ + /* * Copyright (c) 2013 Anthony Green * diff --git a/cpukit/score/cpu/nios2/include/machine/elf_machdep.h b/cpukit/score/cpu/nios2/include/machine/elf_machdep.h index 3f3c108bf5..e933903062 100644 --- a/cpukit/score/cpu/nios2/include/machine/elf_machdep.h +++ b/cpukit/score/cpu/nios2/include/machine/elf_machdep.h @@ -1,3 +1,12 @@ +/** + * @file + * + * @ingroup RTEMSScoreCPUnios2 + * + * @brief This header file provides the ELF definitions of the Nios II + * architecture. + */ + /* $NetBSD: elf_machdep.h,v 1.7 2002/01/28 21:34:48 thorpej Exp $ */ #define ELF32_MACHDEP_ENDIANNESS ELFDATA2MSB diff --git a/cpukit/score/cpu/nios2/include/rtems/score/nios2-count-zeros.h b/cpukit/score/cpu/nios2/include/rtems/score/nios2-count-zeros.h index e0412412c6..428026ea43 100644 --- a/cpukit/score/cpu/nios2/include/rtems/score/nios2-count-zeros.h +++ b/cpukit/score/cpu/nios2/include/rtems/score/nios2-count-zeros.h @@ -1,5 +1,14 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUnios2 + * + * @brief This header file provides the count zeros interfaces of the Nios + * II CPU port. + */ + /* * Author: Jeffrey O. Hill * diff --git a/cpukit/score/cpu/nios2/nios2-context-initialize.c b/cpukit/score/cpu/nios2/nios2-context-initialize.c index 6de1b5c3ab..85bc29ce99 100644 --- a/cpukit/score/cpu/nios2/nios2-context-initialize.c +++ b/cpukit/score/cpu/nios2/nios2-context-initialize.c @@ -1,5 +1,14 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUnios2 + * + * @brief This source file contains the implementation of + * _CPU_Context_Initialize() for the Nios II architecture. + */ + /* * Copyright (C) 2011, 2021 embedded brains GmbH & Co. KG * diff --git a/cpukit/score/cpu/nios2/nios2-context-switch.S b/cpukit/score/cpu/nios2/nios2-context-switch.S index 687d8301c6..e8a01e0a71 100644 --- a/cpukit/score/cpu/nios2/nios2-context-switch.S +++ b/cpukit/score/cpu/nios2/nios2-context-switch.S @@ -1,5 +1,14 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUnios2 + * + * @brief This source file contains the implementation of + * _CPU_Context_switch() for the Nios II architecture. + */ + /* * Copyright (c) 2011 embedded brains GmbH & Co. KG * diff --git a/cpukit/score/cpu/nios2/nios2-context-validate.S b/cpukit/score/cpu/nios2/nios2-context-validate.S index a7fb6e646d..9607c46769 100644 --- a/cpukit/score/cpu/nios2/nios2-context-validate.S +++ b/cpukit/score/cpu/nios2/nios2-context-validate.S @@ -1,5 +1,14 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUnios2 + * + * @brief This source file contains the implementation of + * _CPU_Context_validate() for the Nios II architecture. + */ + /* * Copyright (c) 2013 embedded brains GmbH & Co. KG * diff --git a/cpukit/score/cpu/nios2/nios2-context-volatile-clobber.S b/cpukit/score/cpu/nios2/nios2-context-volatile-clobber.S index a5e181c3df..22d0b9b946 100644 --- a/cpukit/score/cpu/nios2/nios2-context-volatile-clobber.S +++ b/cpukit/score/cpu/nios2/nios2-context-volatile-clobber.S @@ -1,5 +1,14 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUnios2 + * + * @brief This source file contains the implementation of + * _CPU_Context_volatile_clobber() for the Nios II architecture. + */ + /* * Copyright (c) 2013 embedded brains GmbH & Co. KG * diff --git a/cpukit/score/cpu/nios2/nios2-eic-il-low-level.S b/cpukit/score/cpu/nios2/nios2-eic-il-low-level.S index 660c0add39..40b3d4c679 100644 --- a/cpukit/score/cpu/nios2/nios2-eic-il-low-level.S +++ b/cpukit/score/cpu/nios2/nios2-eic-il-low-level.S @@ -1,5 +1,14 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUnios2 + * + * @brief This source file contains the external interrupt controller + * dispatch of the Nios II CPU port. + */ + /* * Copyright (C) 2011, 2015 embedded brains GmbH & Co. KG * diff --git a/cpukit/score/cpu/nios2/nios2-exception-frame-print.c b/cpukit/score/cpu/nios2/nios2-exception-frame-print.c index c0c30379bd..af13146035 100644 --- a/cpukit/score/cpu/nios2/nios2-exception-frame-print.c +++ b/cpukit/score/cpu/nios2/nios2-exception-frame-print.c @@ -1,5 +1,14 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUnios2 + * + * @brief This source file contains the implementation of + * _CPU_Exception_frame_print() for the Nios II architecture. + */ + /* * Copyright (c) 2012 embedded brains GmbH & Co. KG * diff --git a/cpukit/score/cpu/nios2/nios2-iic-low-level.S b/cpukit/score/cpu/nios2/nios2-iic-low-level.S index b0b914f5c8..6021ba62fc 100644 --- a/cpukit/score/cpu/nios2/nios2-iic-low-level.S +++ b/cpukit/score/cpu/nios2/nios2-iic-low-level.S @@ -1,5 +1,14 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUnios2 + * + * @brief This source file contains the internal interrupt controller vector + * of the Nios II CPU port. + */ + /* * This file contains all assembly code for the * NIOS2 implementation of RTEMS. diff --git a/cpukit/score/cpu/nios2/nios2-isr-get-level.c b/cpukit/score/cpu/nios2/nios2-isr-get-level.c index 7b15ac93f5..ec8d886655 100644 --- a/cpukit/score/cpu/nios2/nios2-isr-get-level.c +++ b/cpukit/score/cpu/nios2/nios2-isr-get-level.c @@ -1,5 +1,15 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUnios2 + * + * @brief This source file contains the implementation of + * _CPU_ISR_Get_level() and _CPU_ISR_Is_enabled() for the Nios II + * architecture. + */ + /* * Copyright (C) 2011, 2016 embedded brains GmbH & Co. KG * diff --git a/cpukit/score/cpu/nios2/nios2-isr-is-in-progress.c b/cpukit/score/cpu/nios2/nios2-isr-is-in-progress.c index 5822ebf1f8..d9114dff23 100644 --- a/cpukit/score/cpu/nios2/nios2-isr-is-in-progress.c +++ b/cpukit/score/cpu/nios2/nios2-isr-is-in-progress.c @@ -1,5 +1,14 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUnios2 + * + * @brief This source file contains the implementation of + * _ISR_Is_in_progress() for the Nios II architecture. + */ + /* * Copyright (c) 2011 embedded brains GmbH & Co. KG * diff --git a/cpukit/score/cpu/nios2/nios2-mpu-add-region.c b/cpukit/score/cpu/nios2/nios2-mpu-add-region.c index dd04aa0a97..ad12e34f97 100644 --- a/cpukit/score/cpu/nios2/nios2-mpu-add-region.c +++ b/cpukit/score/cpu/nios2/nios2-mpu-add-region.c @@ -1,5 +1,14 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUnios2 + * + * @brief This source file contains the implementation which adds a Nios II + * memory protection unit region. + */ + /* * Copyright (c) 2011 embedded brains GmbH & Co. KG * diff --git a/cpukit/score/cpu/nios2/nios2-mpu-configuration.c b/cpukit/score/cpu/nios2/nios2-mpu-configuration.c index 640bbb1223..a898dd163e 100644 --- a/cpukit/score/cpu/nios2/nios2-mpu-configuration.c +++ b/cpukit/score/cpu/nios2/nios2-mpu-configuration.c @@ -1,5 +1,14 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUnios2 + * + * @brief This source file contains the memory protection unit configuration + * of the Nios II CPU port. + */ + /* * Copyright (c) 2011 embedded brains GmbH & Co. KG * diff --git a/cpukit/score/cpu/nios2/nios2-mpu-reset.c b/cpukit/score/cpu/nios2/nios2-mpu-reset.c index 85dbfb338b..b1bad563fb 100644 --- a/cpukit/score/cpu/nios2/nios2-mpu-reset.c +++ b/cpukit/score/cpu/nios2/nios2-mpu-reset.c @@ -1,5 +1,14 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUnios2 + * + * @brief This source file contains the implementation of + * _Nios2_MPU_Reset(). + */ + /* * Copyright (c) 2011 embedded brains GmbH & Co. KG * diff --git a/cpukit/score/cpu/no_cpu/cpucounterfrequency.c b/cpukit/score/cpu/no_cpu/cpucounterfrequency.c index 96a4078889..f01c5f47e7 100644 --- a/cpukit/score/cpu/no_cpu/cpucounterfrequency.c +++ b/cpukit/score/cpu/no_cpu/cpucounterfrequency.c @@ -1,5 +1,14 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUExample + * + * @brief This source file contains the implementation of + * _CPU_Counter_frequency() of the example CPU port. + */ + /* * Copyright (c) 2018 embedded brains GmbH & Co. KG * diff --git a/cpukit/score/cpu/no_cpu/cpucounterread.c b/cpukit/score/cpu/no_cpu/cpucounterread.c index f4e6e77fc1..341cf517e5 100644 --- a/cpukit/score/cpu/no_cpu/cpucounterread.c +++ b/cpukit/score/cpu/no_cpu/cpucounterread.c @@ -1,5 +1,14 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUExample + * + * @brief This source file contains the implementation of + * _CPU_Counter_read() of the example CPU port. + */ + /* * Copyright (c) 2014 embedded brains GmbH & Co. KG * diff --git a/cpukit/score/cpu/no_cpu/include/rtems/score/no_cpu.h b/cpukit/score/cpu/no_cpu/include/rtems/score/no_cpu.h index 23ad58a1bc..0ef472c364 100644 --- a/cpukit/score/cpu/no_cpu/include/rtems/score/no_cpu.h +++ b/cpukit/score/cpu/no_cpu/include/rtems/score/no_cpu.h @@ -1,5 +1,14 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUExample + * + * @brief This header file provides the architecture definitions of the + * example CPU port. + */ + /* no_cpu.h * * This file sets up basic CPU dependency settings based on diff --git a/cpukit/score/cpu/or1k/cpu.c b/cpukit/score/cpu/or1k/cpu.c index 68a7de0847..4d2efe48bd 100644 --- a/cpukit/score/cpu/or1k/cpu.c +++ b/cpukit/score/cpu/or1k/cpu.c @@ -1,5 +1,14 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUor1k + * + * @brief This source file contains the implementation of the OpenRISC 1000 + * CPU port. + */ + /* * Opencore OR1K CPU Dependent Source * diff --git a/cpukit/score/cpu/or1k/or1k-context-initialize.c b/cpukit/score/cpu/or1k/or1k-context-initialize.c index 4b85f4748f..738e600f39 100644 --- a/cpukit/score/cpu/or1k/or1k-context-initialize.c +++ b/cpukit/score/cpu/or1k/or1k-context-initialize.c @@ -1,5 +1,14 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUor1k + * + * @brief This source file contains the implementation of + * _CPU_Context_Initialize() for the OpenRISC 1000 architecture. + */ + /* * COPYRIGHT (c) 2014 Hesham ALMatary * diff --git a/cpukit/score/cpu/or1k/or1k-context-switch.S b/cpukit/score/cpu/or1k/or1k-context-switch.S index 6f4d4ac503..525319471d 100644 --- a/cpukit/score/cpu/or1k/or1k-context-switch.S +++ b/cpukit/score/cpu/or1k/or1k-context-switch.S @@ -1,5 +1,14 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUor1k + * + * @brief This source file contains the implementation of + * _CPU_Context_switch() for the OpenRISC 1000 architecture. + */ + /* * COPYRIGHT (c) 2014 Hesham ALMatary * diff --git a/cpukit/score/cpu/or1k/or1k-context-validate.S b/cpukit/score/cpu/or1k/or1k-context-validate.S index 7cdcd70921..8b0d71bc1e 100644 --- a/cpukit/score/cpu/or1k/or1k-context-validate.S +++ b/cpukit/score/cpu/or1k/or1k-context-validate.S @@ -1,5 +1,14 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUor1k + * + * @brief This source file contains the implementation of + * _CPU_Context_validate() for the OpenRISC 1000 architecture. + */ + /* * COPYRIGHT (c) 2014 Hesham ALMatary * diff --git a/cpukit/score/cpu/or1k/or1k-context-volatile-clobber.S b/cpukit/score/cpu/or1k/or1k-context-volatile-clobber.S index 356e51c061..adb9baa4b1 100644 --- a/cpukit/score/cpu/or1k/or1k-context-volatile-clobber.S +++ b/cpukit/score/cpu/or1k/or1k-context-volatile-clobber.S @@ -1,5 +1,14 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUor1k + * + * @brief This source file contains the implementation of + * _CPU_Context_volatile_clobber() for the OpenRISC 1000 architecture. + */ + /* * COPYRIGHT (c) 2014 Hesham ALMatary * diff --git a/cpukit/score/cpu/or1k/or1k-exception-default.c b/cpukit/score/cpu/or1k/or1k-exception-default.c index fe6d5f275e..4f695ac4d1 100644 --- a/cpukit/score/cpu/or1k/or1k-exception-default.c +++ b/cpukit/score/cpu/or1k/or1k-exception-default.c @@ -1,5 +1,14 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUor1k + * + * @brief This source file contains the default exception handler of the + * OpenRISC 1000 architecture. + */ + /* * COPYRIGHT (c) 2014 Hesham ALMatary * diff --git a/cpukit/score/cpu/or1k/or1k-exception-frame-print.c b/cpukit/score/cpu/or1k/or1k-exception-frame-print.c index dbeb5bab04..99d357a9f0 100644 --- a/cpukit/score/cpu/or1k/or1k-exception-frame-print.c +++ b/cpukit/score/cpu/or1k/or1k-exception-frame-print.c @@ -1,5 +1,14 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUor1k + * + * @brief This source file contains the implementation of + * _CPU_Exception_frame_print() for the OpenRISC 1000 architecture. + */ + /* * COPYRIGHT (c) 2014 Hesham ALMatary * diff --git a/cpukit/score/cpu/powerpc/include/machine/elf_machdep.h b/cpukit/score/cpu/powerpc/include/machine/elf_machdep.h index f0fdb3f33b..818659ad73 100644 --- a/cpukit/score/cpu/powerpc/include/machine/elf_machdep.h +++ b/cpukit/score/cpu/powerpc/include/machine/elf_machdep.h @@ -1,3 +1,12 @@ +/** + * @file + * + * @ingroup RTEMSScoreCPUPowerPC + * + * @brief This header file provides the ELF definitions of the PowerPC + * architecture. + */ + /* $NetBSD: elf_machdep.h,v 1.9 2011/01/15 10:00:07 matt Exp $ */ #define ELF32_MACHDEP_ENDIANNESS ELFDATA2MSB diff --git a/cpukit/score/cpu/powerpc/ppc-context-validate.S b/cpukit/score/cpu/powerpc/ppc-context-validate.S index 721633c642..59ef32bba0 100644 --- a/cpukit/score/cpu/powerpc/ppc-context-validate.S +++ b/cpukit/score/cpu/powerpc/ppc-context-validate.S @@ -1,5 +1,14 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUPowerPC + * + * @brief This source file contains the implementation of + * _CPU_Context_validate() for the PowerPC architecture. + */ + /* * Copyright (C) 2013, 2020 embedded brains GmbH & Co. KG * diff --git a/cpukit/score/cpu/powerpc/ppc-context-volatile-clobber.S b/cpukit/score/cpu/powerpc/ppc-context-volatile-clobber.S index d235929f7d..c7c40fe8e4 100644 --- a/cpukit/score/cpu/powerpc/ppc-context-volatile-clobber.S +++ b/cpukit/score/cpu/powerpc/ppc-context-volatile-clobber.S @@ -1,5 +1,14 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUPowerPC + * + * @brief This source file contains the implementation of + * _CPU_Context_volatile_clobber() for the PowerPC architecture. + */ + /* * Copyright (C) 2013, 2017 embedded brains GmbH & Co. KG * diff --git a/cpukit/score/cpu/powerpc/ppc-isr-disable-mask.S b/cpukit/score/cpu/powerpc/ppc-isr-disable-mask.S index 529b88bf3f..320ce10298 100644 --- a/cpukit/score/cpu/powerpc/ppc-isr-disable-mask.S +++ b/cpukit/score/cpu/powerpc/ppc-isr-disable-mask.S @@ -1,5 +1,14 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUPowerPC + * + * @brief This source file contains the interrupt disable mask of the + * PowerPC architecture. + */ + /* * Copyright (c) 2014 embedded brains GmbH & Co. KG * diff --git a/cpukit/score/cpu/riscv/cpu.c b/cpukit/score/cpu/riscv/cpu.c index 3a89c2a05a..7c7dcf1050 100644 --- a/cpukit/score/cpu/riscv/cpu.c +++ b/cpukit/score/cpu/riscv/cpu.c @@ -1,3 +1,12 @@ +/** + * @file + * + * @ingroup RTEMSScoreCPURISCV + * + * @brief This source file contains the implementation of the RISC-V CPU + * port. + */ + /* * Copyright (c) 2018 embedded brains GmbH & Co. KG * diff --git a/cpukit/score/cpu/riscv/include/libcpu/access.h b/cpukit/score/cpu/riscv/include/libcpu/access.h index f414d6f22f..8d3ea679eb 100644 --- a/cpukit/score/cpu/riscv/include/libcpu/access.h +++ b/cpukit/score/cpu/riscv/include/libcpu/access.h @@ -1,5 +1,14 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPURISCV + * + * @brief This header file provides the access function interfaces of the + * RISC-V CPU port. + */ + /* * access.h - access routines for SPARC. SPARC is big endian only. * diff --git a/cpukit/score/cpu/riscv/include/libcpu/byteorder.h b/cpukit/score/cpu/riscv/include/libcpu/byteorder.h index 90612bcc96..3cfe1f949e 100644 --- a/cpukit/score/cpu/riscv/include/libcpu/byteorder.h +++ b/cpukit/score/cpu/riscv/include/libcpu/byteorder.h @@ -1,5 +1,14 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPURISCV + * + * @brief This header file provides the byte order access interfaces of the + * RISC-V CPU port. + */ + /* * Copyright (C) 2019 Jiri Gaisler * diff --git a/cpukit/score/cpu/riscv/include/machine/elf_machdep.h b/cpukit/score/cpu/riscv/include/machine/elf_machdep.h index 772aecf702..27e5621f2a 100644 --- a/cpukit/score/cpu/riscv/include/machine/elf_machdep.h +++ b/cpukit/score/cpu/riscv/include/machine/elf_machdep.h @@ -1,3 +1,12 @@ +/** + * @file + * + * @ingroup RTEMSScoreCPURISCV + * + * @brief This header file provides the ELF definitions of the RISC-V + * architecture. + */ + /* $NetBSD: elf_machdep.h,v 1.6 2017/11/06 03:47:48 christos Exp $ */ /*- diff --git a/cpukit/score/cpu/riscv/riscv-context-initialize.c b/cpukit/score/cpu/riscv/riscv-context-initialize.c index 948221fab3..27c87d0637 100644 --- a/cpukit/score/cpu/riscv/riscv-context-initialize.c +++ b/cpukit/score/cpu/riscv/riscv-context-initialize.c @@ -1,3 +1,12 @@ +/** + * @file + * + * @ingroup RTEMSScoreCPURISCV + * + * @brief This source file contains the implementation of + * _CPU_Context_Initialize() for the RISC-V architecture. + */ + /* * Copyright (c) 2018 embedded brains GmbH & Co. KG * diff --git a/cpukit/score/cpu/riscv/riscv-context-switch.S b/cpukit/score/cpu/riscv/riscv-context-switch.S index 6e6041206d..46210cdd6e 100644 --- a/cpukit/score/cpu/riscv/riscv-context-switch.S +++ b/cpukit/score/cpu/riscv/riscv-context-switch.S @@ -1,3 +1,12 @@ +/** + * @file + * + * @ingroup RTEMSScoreCPURISCV + * + * @brief This source file contains the implementation of + * _CPU_Context_switch() for the RISC-V architecture. + */ + /* * Copyright (c) 2018 embedded brains GmbH & Co. KG * diff --git a/cpukit/score/cpu/riscv/riscv-context-validate.S b/cpukit/score/cpu/riscv/riscv-context-validate.S index 838803e809..08cdadbf27 100644 --- a/cpukit/score/cpu/riscv/riscv-context-validate.S +++ b/cpukit/score/cpu/riscv/riscv-context-validate.S @@ -1,3 +1,12 @@ +/** + * @file + * + * @ingroup RTEMSScoreCPURISCV + * + * @brief This source file contains the implementation of + * _CPU_Context_validate() for the RISC-V architecture. + */ + /* * Copyright (c) 2018 embedded brains GmbH & Co. KG * Copyright (c) 2015 Hesham Almatary diff --git a/cpukit/score/cpu/riscv/riscv-context-volatile-clobber.S b/cpukit/score/cpu/riscv/riscv-context-volatile-clobber.S index efea2afc72..1fcaf2619f 100644 --- a/cpukit/score/cpu/riscv/riscv-context-volatile-clobber.S +++ b/cpukit/score/cpu/riscv/riscv-context-volatile-clobber.S @@ -1,3 +1,12 @@ +/** + * @file + * + * @ingroup RTEMSScoreCPURISCV + * + * @brief This source file contains the implementation of + * _CPU_Context_volatile_clobber() for the RISC-V architecture. + */ + /* * Copyright (c) 2018 embedded brains GmbH & Co. KG * Copyright (c) 2015 Hesham Almatary diff --git a/cpukit/score/cpu/riscv/riscv-counter.S b/cpukit/score/cpu/riscv/riscv-counter.S index 96c68e6b13..b70ff0a990 100644 --- a/cpukit/score/cpu/riscv/riscv-counter.S +++ b/cpukit/score/cpu/riscv/riscv-counter.S @@ -1,3 +1,11 @@ +/** + * @file + * + * @ingroup RTEMSScoreCPURISCV + * + * @brief This source file contains the CPU counter of the RISC-V CPU port. + */ + /* * Copyright (c) 2018 embedded brains GmbH & Co. KG * diff --git a/cpukit/score/cpu/riscv/riscv-exception-frame-print.c b/cpukit/score/cpu/riscv/riscv-exception-frame-print.c index 133cec4ebc..b3a621c44d 100644 --- a/cpukit/score/cpu/riscv/riscv-exception-frame-print.c +++ b/cpukit/score/cpu/riscv/riscv-exception-frame-print.c @@ -1,3 +1,12 @@ +/** + * @file + * + * @ingroup RTEMSScoreCPURISCV + * + * @brief This source file contains the implementation of + * _CPU_Exception_frame_print() for the RISC-V architecture. + */ + /* * Copyright (c) 2018 embedded brains GmbH & Co. KG * Copyright (c) 2015 Hesham Almatary diff --git a/cpukit/score/cpu/sparc/access_le.c b/cpukit/score/cpu/sparc/access_le.c index b1bde6da4b..37cd5543cf 100644 --- a/cpukit/score/cpu/sparc/access_le.c +++ b/cpukit/score/cpu/sparc/access_le.c @@ -1,5 +1,14 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUSPARC + * + * @brief This source file contains the little endian access functions of + * the SPARC CPU port. + */ + /* * Little-endian access routines for SPARC * diff --git a/cpukit/score/cpu/sparc/cpu_asm.S b/cpukit/score/cpu/sparc/cpu_asm.S index fd7186b499..fff2aca881 100644 --- a/cpukit/score/cpu/sparc/cpu_asm.S +++ b/cpukit/score/cpu/sparc/cpu_asm.S @@ -1,5 +1,14 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUSPARC + * + * @brief This source file contains the assembly language support of the + * SPARC CPU port. + */ + /* cpu_asm.s * * This file contains the basic algorithms for all assembly code used diff --git a/cpukit/score/cpu/sparc/include/libcpu/access.h b/cpukit/score/cpu/sparc/include/libcpu/access.h index f414d6f22f..4a65dc6784 100644 --- a/cpukit/score/cpu/sparc/include/libcpu/access.h +++ b/cpukit/score/cpu/sparc/include/libcpu/access.h @@ -1,5 +1,14 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUSPARC + * + * @brief This header file provides the access function interfaces of the + * SPARC CPU port. + */ + /* * access.h - access routines for SPARC. SPARC is big endian only. * diff --git a/cpukit/score/cpu/sparc/include/libcpu/byteorder.h b/cpukit/score/cpu/sparc/include/libcpu/byteorder.h index 0c469ba36b..273df281ef 100644 --- a/cpukit/score/cpu/sparc/include/libcpu/byteorder.h +++ b/cpukit/score/cpu/sparc/include/libcpu/byteorder.h @@ -1,5 +1,14 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUSPARC + * + * @brief This header file provides the byte order access interfaces of the + * SPARC CPU port. + */ + /* * byteorder.h - Endian conversion for SPARC. SPARC is big endian only. * diff --git a/cpukit/score/cpu/sparc/include/machine/elf_machdep.h b/cpukit/score/cpu/sparc/include/machine/elf_machdep.h index e8f2b630c2..024155042c 100644 --- a/cpukit/score/cpu/sparc/include/machine/elf_machdep.h +++ b/cpukit/score/cpu/sparc/include/machine/elf_machdep.h @@ -1,3 +1,12 @@ +/** + * @file + * + * @ingroup RTEMSScoreCPUSPARC + * + * @brief This header file provides the ELF definitions of the SPARC + * architecture. + */ + /* $NetBSD: elf_machdep.h,v 1.7 2009/05/30 05:56:53 skrll Exp $ */ #define ELF32_MACHDEP_ENDIANNESS ELFDATA2MSB diff --git a/cpukit/score/cpu/sparc/sparc-access.S b/cpukit/score/cpu/sparc/sparc-access.S index e6628d9eb7..a92818ced2 100644 --- a/cpukit/score/cpu/sparc/sparc-access.S +++ b/cpukit/score/cpu/sparc/sparc-access.S @@ -1,5 +1,14 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUSPARC + * + * @brief This source file contains the assembly language access functions + * of the SPARC CPU port. + */ + /* * Optimized access routines for SPARC. * diff --git a/cpukit/score/cpu/sparc/sparc-context-validate.S b/cpukit/score/cpu/sparc/sparc-context-validate.S index ce1c738d7b..dc8fd7e62d 100644 --- a/cpukit/score/cpu/sparc/sparc-context-validate.S +++ b/cpukit/score/cpu/sparc/sparc-context-validate.S @@ -1,5 +1,14 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUSPARC + * + * @brief This source file contains the implementation of + * _CPU_Context_validate() for the SPARC architecture. + */ + /* * Copyright (C) 2015, 2017 embedded brains GmbH & Co. KG * diff --git a/cpukit/score/cpu/sparc/sparc-context-volatile-clobber.S b/cpukit/score/cpu/sparc/sparc-context-volatile-clobber.S index ebbaec59a6..5dc12fd9fe 100644 --- a/cpukit/score/cpu/sparc/sparc-context-volatile-clobber.S +++ b/cpukit/score/cpu/sparc/sparc-context-volatile-clobber.S @@ -1,5 +1,14 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUSPARC + * + * @brief This source file contains the implementation of + * _CPU_Context_volatile_clobber() for the SPARC architecture. + */ + /* * Copyright (c) 2015 embedded brains GmbH & Co. KG * diff --git a/cpukit/score/cpu/sparc/sparc-isr-handler.S b/cpukit/score/cpu/sparc/sparc-isr-handler.S index 9ecb44e870..0f938fb236 100644 --- a/cpukit/score/cpu/sparc/sparc-isr-handler.S +++ b/cpukit/score/cpu/sparc/sparc-isr-handler.S @@ -1,5 +1,14 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUSPARC + * + * @brief This source file contains the interrupt handler entry of the SPARC + * architecture. + */ + /* * This file contains the basic algorithms for all assembly code used * in an specific CPU port of RTEMS. These algorithms must be implemented diff --git a/cpukit/score/cpu/sparc/syscall.S b/cpukit/score/cpu/sparc/syscall.S index b13b030a9d..e4cb222ec6 100644 --- a/cpukit/score/cpu/sparc/syscall.S +++ b/cpukit/score/cpu/sparc/syscall.S @@ -1,3 +1,12 @@ +/** + * @file + * + * @ingroup RTEMSScoreCPUSPARC + * + * @brief This source file contains the system call traps of the SPARC CPU + * port. + */ + /* * systrap.S * diff --git a/cpukit/score/cpu/sparc/window.S b/cpukit/score/cpu/sparc/window.S index 4675248fe0..ded4529e7b 100644 --- a/cpukit/score/cpu/sparc/window.S +++ b/cpukit/score/cpu/sparc/window.S @@ -1,3 +1,12 @@ +/** + * @file + * + * @ingroup RTEMSScoreCPUSPARC + * + * @brief This source file contains the register window flush support of the + * SPARC CPU port. + */ + /* * window.s * diff --git a/cpukit/score/cpu/x86_64/include/machine/elf_machdep.h b/cpukit/score/cpu/x86_64/include/machine/elf_machdep.h index ee50640df2..74d9368683 100644 --- a/cpukit/score/cpu/x86_64/include/machine/elf_machdep.h +++ b/cpukit/score/cpu/x86_64/include/machine/elf_machdep.h @@ -1,3 +1,12 @@ +/** + * @file + * + * @ingroup RTEMSScoreCPUx86_64 + * + * @brief This header file provides the ELF definitions of the x86-64 + * architecture. + */ + /* $NetBSD: elf_machdep.h,v 1.4.18.1 2017/12/03 11:35:47 jdolecek Exp $ */ #if !defined __i386__ diff --git a/cpukit/score/cpu/x86_64/include/rtems/score/cpu_asm.h b/cpukit/score/cpu/x86_64/include/rtems/score/cpu_asm.h index 156385b669..8c603b86bc 100644 --- a/cpukit/score/cpu/x86_64/include/rtems/score/cpu_asm.h +++ b/cpukit/score/cpu/x86_64/include/rtems/score/cpu_asm.h @@ -1,5 +1,14 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUx86_64 + * + * @brief This header file provides the assembly language interfaces of the + * x86-64 CPU port. + */ + /* * Copyright (c) 2018 Amaan Cheval * diff --git a/cpukit/score/cpu/x86_64/include/rtems/score/idt.h b/cpukit/score/cpu/x86_64/include/rtems/score/idt.h index 3163a10c6c..3cff9ae2aa 100644 --- a/cpukit/score/cpu/x86_64/include/rtems/score/idt.h +++ b/cpukit/score/cpu/x86_64/include/rtems/score/idt.h @@ -1,5 +1,14 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUx86_64 + * + * @brief This header file provides the interrupt descriptor table + * interfaces of the x86-64 CPU port. + */ + /* * Copyright (c) 2018 Amaan Cheval * diff --git a/cpukit/score/cpu/x86_64/include/rtems/score/x86_64.h b/cpukit/score/cpu/x86_64/include/rtems/score/x86_64.h index c81e2d480f..e9ab81936d 100644 --- a/cpukit/score/cpu/x86_64/include/rtems/score/x86_64.h +++ b/cpukit/score/cpu/x86_64/include/rtems/score/x86_64.h @@ -1,3 +1,12 @@ +/** + * @file + * + * @ingroup RTEMSScoreCPUx86_64 + * + * @brief This header file provides the architecture definitions of the + * x86-64 CPU port. + */ + /* * Copyright (c) 2018 Amaan Cheval * diff --git a/cpukit/score/cpu/x86_64/x86_64-context-initialize.c b/cpukit/score/cpu/x86_64/x86_64-context-initialize.c index 1edc2bb9b9..264cb1f058 100644 --- a/cpukit/score/cpu/x86_64/x86_64-context-initialize.c +++ b/cpukit/score/cpu/x86_64/x86_64-context-initialize.c @@ -1,3 +1,12 @@ +/** + * @file + * + * @ingroup RTEMSScoreCPUx86_64 + * + * @brief This source file contains the implementation of + * _CPU_Context_Initialize() for the x86-64 architecture. + */ + /* * Copyright (c) 2018 Amaan Cheval * diff --git a/cpukit/score/cpu/x86_64/x86_64-context-switch.S b/cpukit/score/cpu/x86_64/x86_64-context-switch.S index c27cdee08d..f56b8cbb1d 100644 --- a/cpukit/score/cpu/x86_64/x86_64-context-switch.S +++ b/cpukit/score/cpu/x86_64/x86_64-context-switch.S @@ -1,5 +1,14 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUx86_64 + * + * @brief This source file contains the implementation of + * _CPU_Context_switch() for the x86-64 architecture. + */ + /* * Copyright (C) 2024 Matheus Pecoraro * Copyright (c) 2018 Amaan Cheval