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grlib: Reformat headers with clang-format

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This commit is contained in:
Matteo Concas
2026-06-03 12:13:16 -05:00
committed by Kinsey Moore
parent 7a2a99e0ef
commit 5e89997b25
83 changed files with 6857 additions and 7465 deletions
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bsps/include/grlib/ahbstat-regs.h
+15 -22
View File
@@ -96,30 +96,25 @@ extern "C" {
#define AHBSTAT_AHBS_HWRITE 0x80U
#define AHBSTAT_AHBS_HMASTER_SHIFT 3
#define AHBSTAT_AHBS_HMASTER_MASK 0x78U
#define AHBSTAT_AHBS_HMASTER_MASK 0x78U
#define AHBSTAT_AHBS_HMASTER_GET( _reg ) \
( ( ( _reg ) & AHBSTAT_AHBS_HMASTER_MASK ) >> \
AHBSTAT_AHBS_HMASTER_SHIFT )
#define AHBSTAT_AHBS_HMASTER_SET( _reg, _val ) \
( ( ( _reg ) & ~AHBSTAT_AHBS_HMASTER_MASK ) | \
( ( ( _reg ) & AHBSTAT_AHBS_HMASTER_MASK ) >> AHBSTAT_AHBS_HMASTER_SHIFT )
#define AHBSTAT_AHBS_HMASTER_SET( _reg, _val ) \
( ( ( _reg ) & ~AHBSTAT_AHBS_HMASTER_MASK ) | \
( ( ( _val ) << AHBSTAT_AHBS_HMASTER_SHIFT ) & \
AHBSTAT_AHBS_HMASTER_MASK ) )
#define AHBSTAT_AHBS_HMASTER( _val ) \
( ( ( _val ) << AHBSTAT_AHBS_HMASTER_SHIFT ) & \
AHBSTAT_AHBS_HMASTER_MASK )
( ( ( _val ) << AHBSTAT_AHBS_HMASTER_SHIFT ) & AHBSTAT_AHBS_HMASTER_MASK )
#define AHBSTAT_AHBS_HSIZE_SHIFT 0
#define AHBSTAT_AHBS_HSIZE_MASK 0x7U
#define AHBSTAT_AHBS_HSIZE_MASK 0x7U
#define AHBSTAT_AHBS_HSIZE_GET( _reg ) \
( ( ( _reg ) & AHBSTAT_AHBS_HSIZE_MASK ) >> \
AHBSTAT_AHBS_HSIZE_SHIFT )
#define AHBSTAT_AHBS_HSIZE_SET( _reg, _val ) \
( ( ( _reg ) & AHBSTAT_AHBS_HSIZE_MASK ) >> AHBSTAT_AHBS_HSIZE_SHIFT )
#define AHBSTAT_AHBS_HSIZE_SET( _reg, _val ) \
( ( ( _reg ) & ~AHBSTAT_AHBS_HSIZE_MASK ) | \
( ( ( _val ) << AHBSTAT_AHBS_HSIZE_SHIFT ) & \
AHBSTAT_AHBS_HSIZE_MASK ) )
( ( ( _val ) << AHBSTAT_AHBS_HSIZE_SHIFT ) & AHBSTAT_AHBS_HSIZE_MASK ) )
#define AHBSTAT_AHBS_HSIZE( _val ) \
( ( ( _val ) << AHBSTAT_AHBS_HSIZE_SHIFT ) & \
AHBSTAT_AHBS_HSIZE_MASK )
( ( ( _val ) << AHBSTAT_AHBS_HSIZE_SHIFT ) & AHBSTAT_AHBS_HSIZE_MASK )
/** @} */
@@ -133,17 +128,15 @@ extern "C" {
*/
#define AHBSTAT_AHBFAR_HADDR_SHIFT 0
#define AHBSTAT_AHBFAR_HADDR_MASK 0xffffffffU
#define AHBSTAT_AHBFAR_HADDR_MASK 0xffffffffU
#define AHBSTAT_AHBFAR_HADDR_GET( _reg ) \
( ( ( _reg ) & AHBSTAT_AHBFAR_HADDR_MASK ) >> \
AHBSTAT_AHBFAR_HADDR_SHIFT )
#define AHBSTAT_AHBFAR_HADDR_SET( _reg, _val ) \
( ( ( _reg ) & ~AHBSTAT_AHBFAR_HADDR_MASK ) | \
( ( ( _reg ) & AHBSTAT_AHBFAR_HADDR_MASK ) >> AHBSTAT_AHBFAR_HADDR_SHIFT )
#define AHBSTAT_AHBFAR_HADDR_SET( _reg, _val ) \
( ( ( _reg ) & ~AHBSTAT_AHBFAR_HADDR_MASK ) | \
( ( ( _val ) << AHBSTAT_AHBFAR_HADDR_SHIFT ) & \
AHBSTAT_AHBFAR_HADDR_MASK ) )
#define AHBSTAT_AHBFAR_HADDR( _val ) \
( ( ( _val ) << AHBSTAT_AHBFAR_HADDR_SHIFT ) & \
AHBSTAT_AHBFAR_HADDR_MASK )
( ( ( _val ) << AHBSTAT_AHBFAR_HADDR_SHIFT ) & AHBSTAT_AHBFAR_HADDR_MASK )
/** @} */
bsps/include/grlib/ahbstat.h
+17 -12
View File
@@ -38,10 +38,10 @@ extern "C" {
/* AHBSTAT Registers layout */
struct ahbstat_regs {
volatile uint32_t status;
volatile uint32_t failing;
volatile uint32_t status2;
volatile uint32_t failing2;
volatile uint32_t status;
volatile uint32_t failing;
volatile uint32_t status2;
volatile uint32_t failing2;
};
/* AHB fail interrupt callback to user. This function is declared weak so that
@@ -59,11 +59,12 @@ struct ahbstat_regs {
* 2: just print error
* 3: do nothing, let user do custom handling
*/
extern int (*ahbstat_error)(
int minor,
struct ahbstat_regs *regs,
uint32_t status,
uint32_t failing_address);
extern int ( *ahbstat_error )(
int minor,
struct ahbstat_regs *regs,
uint32_t status,
uint32_t failing_address
);
/* Get Last received AHB Error
*
@@ -76,7 +77,11 @@ extern int (*ahbstat_error)(
* 1: Error Received, last status and address stored into argument pointers
* -1: No such AHBSTAT device
*/
extern int ahbstat_last_error(int minor, uint32_t *status, uint32_t *address);
extern int ahbstat_last_error(
int minor,
uint32_t *status,
uint32_t *address
);
/* Get AHBSTAT registers address from minor. Can also be used to check if
* AHBSTAT hardware is present.
@@ -85,10 +90,10 @@ extern int ahbstat_last_error(int minor, uint32_t *status, uint32_t *address);
* NULL returned if no such device
* non-zero Address to AHBSTAT register
*/
extern struct ahbstat_regs *ahbstat_get_regs(int minor);
extern struct ahbstat_regs *ahbstat_get_regs( int minor );
/* Registers the AHBSTAT driver to the Driver Manager */
void ahbstat_register_drv (void);
void ahbstat_register_drv( void );
#ifdef __cplusplus
}
bsps/include/grlib/ahbtrace-regs.h
+40 -48
View File
@@ -82,32 +82,26 @@ extern "C" {
*/
#define AHBTRACE_CTRL_DCNT_SHIFT 16
#define AHBTRACE_CTRL_DCNT_MASK 0x7f0000U
#define AHBTRACE_CTRL_DCNT_MASK 0x7f0000U
#define AHBTRACE_CTRL_DCNT_GET( _reg ) \
( ( ( _reg ) & AHBTRACE_CTRL_DCNT_MASK ) >> \
AHBTRACE_CTRL_DCNT_SHIFT )
#define AHBTRACE_CTRL_DCNT_SET( _reg, _val ) \
( ( ( _reg ) & AHBTRACE_CTRL_DCNT_MASK ) >> AHBTRACE_CTRL_DCNT_SHIFT )
#define AHBTRACE_CTRL_DCNT_SET( _reg, _val ) \
( ( ( _reg ) & ~AHBTRACE_CTRL_DCNT_MASK ) | \
( ( ( _val ) << AHBTRACE_CTRL_DCNT_SHIFT ) & \
AHBTRACE_CTRL_DCNT_MASK ) )
( ( ( _val ) << AHBTRACE_CTRL_DCNT_SHIFT ) & AHBTRACE_CTRL_DCNT_MASK ) )
#define AHBTRACE_CTRL_DCNT( _val ) \
( ( ( _val ) << AHBTRACE_CTRL_DCNT_SHIFT ) & \
AHBTRACE_CTRL_DCNT_MASK )
( ( ( _val ) << AHBTRACE_CTRL_DCNT_SHIFT ) & AHBTRACE_CTRL_DCNT_MASK )
#define AHBTRACE_CTRL_PF 0x100U
#define AHBTRACE_CTRL_BW_SHIFT 6
#define AHBTRACE_CTRL_BW_MASK 0xc0U
#define AHBTRACE_CTRL_BW_MASK 0xc0U
#define AHBTRACE_CTRL_BW_GET( _reg ) \
( ( ( _reg ) & AHBTRACE_CTRL_BW_MASK ) >> \
AHBTRACE_CTRL_BW_SHIFT )
#define AHBTRACE_CTRL_BW_SET( _reg, _val ) \
( ( ( _reg ) & AHBTRACE_CTRL_BW_MASK ) >> AHBTRACE_CTRL_BW_SHIFT )
#define AHBTRACE_CTRL_BW_SET( _reg, _val ) \
( ( ( _reg ) & ~AHBTRACE_CTRL_BW_MASK ) | \
( ( ( _val ) << AHBTRACE_CTRL_BW_SHIFT ) & \
AHBTRACE_CTRL_BW_MASK ) )
( ( ( _val ) << AHBTRACE_CTRL_BW_SHIFT ) & AHBTRACE_CTRL_BW_MASK ) )
#define AHBTRACE_CTRL_BW( _val ) \
( ( ( _val ) << AHBTRACE_CTRL_BW_SHIFT ) & \
AHBTRACE_CTRL_BW_MASK )
( ( ( _val ) << AHBTRACE_CTRL_BW_SHIFT ) & AHBTRACE_CTRL_BW_MASK )
#define AHBTRACE_CTRL_RF 0x20U
@@ -132,17 +126,15 @@ extern "C" {
*/
#define AHBTRACE_INDEX_INDEX_SHIFT 4
#define AHBTRACE_INDEX_INDEX_MASK 0x7f0U
#define AHBTRACE_INDEX_INDEX_MASK 0x7f0U
#define AHBTRACE_INDEX_INDEX_GET( _reg ) \
( ( ( _reg ) & AHBTRACE_INDEX_INDEX_MASK ) >> \
AHBTRACE_INDEX_INDEX_SHIFT )
#define AHBTRACE_INDEX_INDEX_SET( _reg, _val ) \
( ( ( _reg ) & ~AHBTRACE_INDEX_INDEX_MASK ) | \
( ( ( _reg ) & AHBTRACE_INDEX_INDEX_MASK ) >> AHBTRACE_INDEX_INDEX_SHIFT )
#define AHBTRACE_INDEX_INDEX_SET( _reg, _val ) \
( ( ( _reg ) & ~AHBTRACE_INDEX_INDEX_MASK ) | \
( ( ( _val ) << AHBTRACE_INDEX_INDEX_SHIFT ) & \
AHBTRACE_INDEX_INDEX_MASK ) )
#define AHBTRACE_INDEX_INDEX( _val ) \
( ( ( _val ) << AHBTRACE_INDEX_INDEX_SHIFT ) & \
AHBTRACE_INDEX_INDEX_MASK )
( ( ( _val ) << AHBTRACE_INDEX_INDEX_SHIFT ) & AHBTRACE_INDEX_INDEX_MASK )
/** @} */
@@ -156,15 +148,15 @@ extern "C" {
*/
#define AHBTRACE_TIMETAG_TIMETAG_SHIFT 0
#define AHBTRACE_TIMETAG_TIMETAG_MASK 0xffffffffU
#define AHBTRACE_TIMETAG_TIMETAG_GET( _reg ) \
#define AHBTRACE_TIMETAG_TIMETAG_MASK 0xffffffffU
#define AHBTRACE_TIMETAG_TIMETAG_GET( _reg ) \
( ( ( _reg ) & AHBTRACE_TIMETAG_TIMETAG_MASK ) >> \
AHBTRACE_TIMETAG_TIMETAG_SHIFT )
#define AHBTRACE_TIMETAG_TIMETAG_SET( _reg, _val ) \
( ( ( _reg ) & ~AHBTRACE_TIMETAG_TIMETAG_MASK ) | \
#define AHBTRACE_TIMETAG_TIMETAG_SET( _reg, _val ) \
( ( ( _reg ) & ~AHBTRACE_TIMETAG_TIMETAG_MASK ) | \
( ( ( _val ) << AHBTRACE_TIMETAG_TIMETAG_SHIFT ) & \
AHBTRACE_TIMETAG_TIMETAG_MASK ) )
#define AHBTRACE_TIMETAG_TIMETAG( _val ) \
#define AHBTRACE_TIMETAG_TIMETAG( _val ) \
( ( ( _val ) << AHBTRACE_TIMETAG_TIMETAG_SHIFT ) & \
AHBTRACE_TIMETAG_TIMETAG_MASK )
@@ -180,28 +172,28 @@ extern "C" {
*/
#define AHBTRACE_MSFILT_SMASK_15_0_SHIFT 16
#define AHBTRACE_MSFILT_SMASK_15_0_MASK 0xffff0000U
#define AHBTRACE_MSFILT_SMASK_15_0_GET( _reg ) \
#define AHBTRACE_MSFILT_SMASK_15_0_MASK 0xffff0000U
#define AHBTRACE_MSFILT_SMASK_15_0_GET( _reg ) \
( ( ( _reg ) & AHBTRACE_MSFILT_SMASK_15_0_MASK ) >> \
AHBTRACE_MSFILT_SMASK_15_0_SHIFT )
#define AHBTRACE_MSFILT_SMASK_15_0_SET( _reg, _val ) \
( ( ( _reg ) & ~AHBTRACE_MSFILT_SMASK_15_0_MASK ) | \
#define AHBTRACE_MSFILT_SMASK_15_0_SET( _reg, _val ) \
( ( ( _reg ) & ~AHBTRACE_MSFILT_SMASK_15_0_MASK ) | \
( ( ( _val ) << AHBTRACE_MSFILT_SMASK_15_0_SHIFT ) & \
AHBTRACE_MSFILT_SMASK_15_0_MASK ) )
#define AHBTRACE_MSFILT_SMASK_15_0( _val ) \
#define AHBTRACE_MSFILT_SMASK_15_0( _val ) \
( ( ( _val ) << AHBTRACE_MSFILT_SMASK_15_0_SHIFT ) & \
AHBTRACE_MSFILT_SMASK_15_0_MASK )
#define AHBTRACE_MSFILT_MMASK_15_0_SHIFT 0
#define AHBTRACE_MSFILT_MMASK_15_0_MASK 0xffffU
#define AHBTRACE_MSFILT_MMASK_15_0_GET( _reg ) \
#define AHBTRACE_MSFILT_MMASK_15_0_MASK 0xffffU
#define AHBTRACE_MSFILT_MMASK_15_0_GET( _reg ) \
( ( ( _reg ) & AHBTRACE_MSFILT_MMASK_15_0_MASK ) >> \
AHBTRACE_MSFILT_MMASK_15_0_SHIFT )
#define AHBTRACE_MSFILT_MMASK_15_0_SET( _reg, _val ) \
( ( ( _reg ) & ~AHBTRACE_MSFILT_MMASK_15_0_MASK ) | \
#define AHBTRACE_MSFILT_MMASK_15_0_SET( _reg, _val ) \
( ( ( _reg ) & ~AHBTRACE_MSFILT_MMASK_15_0_MASK ) | \
( ( ( _val ) << AHBTRACE_MSFILT_MMASK_15_0_SHIFT ) & \
AHBTRACE_MSFILT_MMASK_15_0_MASK ) )
#define AHBTRACE_MSFILT_MMASK_15_0( _val ) \
#define AHBTRACE_MSFILT_MMASK_15_0( _val ) \
( ( ( _val ) << AHBTRACE_MSFILT_MMASK_15_0_SHIFT ) & \
AHBTRACE_MSFILT_MMASK_15_0_MASK )
@@ -217,15 +209,15 @@ extern "C" {
*/
#define AHBTRACE_TBBA_BADDR_31_2_SHIFT 2
#define AHBTRACE_TBBA_BADDR_31_2_MASK 0xfffffffcU
#define AHBTRACE_TBBA_BADDR_31_2_GET( _reg ) \
#define AHBTRACE_TBBA_BADDR_31_2_MASK 0xfffffffcU
#define AHBTRACE_TBBA_BADDR_31_2_GET( _reg ) \
( ( ( _reg ) & AHBTRACE_TBBA_BADDR_31_2_MASK ) >> \
AHBTRACE_TBBA_BADDR_31_2_SHIFT )
#define AHBTRACE_TBBA_BADDR_31_2_SET( _reg, _val ) \
( ( ( _reg ) & ~AHBTRACE_TBBA_BADDR_31_2_MASK ) | \
#define AHBTRACE_TBBA_BADDR_31_2_SET( _reg, _val ) \
( ( ( _reg ) & ~AHBTRACE_TBBA_BADDR_31_2_MASK ) | \
( ( ( _val ) << AHBTRACE_TBBA_BADDR_31_2_SHIFT ) & \
AHBTRACE_TBBA_BADDR_31_2_MASK ) )
#define AHBTRACE_TBBA_BADDR_31_2( _val ) \
#define AHBTRACE_TBBA_BADDR_31_2( _val ) \
( ( ( _val ) << AHBTRACE_TBBA_BADDR_31_2_SHIFT ) & \
AHBTRACE_TBBA_BADDR_31_2_MASK )
@@ -241,15 +233,15 @@ extern "C" {
*/
#define AHBTRACE_TBBM_BMASK_31_2_SHIFT 2
#define AHBTRACE_TBBM_BMASK_31_2_MASK 0xfffffffcU
#define AHBTRACE_TBBM_BMASK_31_2_GET( _reg ) \
#define AHBTRACE_TBBM_BMASK_31_2_MASK 0xfffffffcU
#define AHBTRACE_TBBM_BMASK_31_2_GET( _reg ) \
( ( ( _reg ) & AHBTRACE_TBBM_BMASK_31_2_MASK ) >> \
AHBTRACE_TBBM_BMASK_31_2_SHIFT )
#define AHBTRACE_TBBM_BMASK_31_2_SET( _reg, _val ) \
( ( ( _reg ) & ~AHBTRACE_TBBM_BMASK_31_2_MASK ) | \
#define AHBTRACE_TBBM_BMASK_31_2_SET( _reg, _val ) \
( ( ( _reg ) & ~AHBTRACE_TBBM_BMASK_31_2_MASK ) | \
( ( ( _val ) << AHBTRACE_TBBM_BMASK_31_2_SHIFT ) & \
AHBTRACE_TBBM_BMASK_31_2_MASK ) )
#define AHBTRACE_TBBM_BMASK_31_2( _val ) \
#define AHBTRACE_TBBM_BMASK_31_2( _val ) \
( ( ( _val ) << AHBTRACE_TBBM_BMASK_31_2_SHIFT ) & \
AHBTRACE_TBBM_BMASK_31_2_MASK )
bsps/include/grlib/ambapp.h
+183 -155
View File
@@ -58,84 +58,85 @@ extern "C" {
/* Max supported AHB buses */
#define AHB_BUS_MAX 6
#define AMBAPP_FLAG_FFACT_DIR 0x100 /* Frequency factor direction, 0=down, 1=up */
#define AMBAPP_FLAG_FFACT 0x0f0 /* Frequency factor against top bus */
#define AMBAPP_FLAG_MBUS 0x00c
#define AMBAPP_FLAG_SBUS 0x003
#define AMBAPP_FLAG_FFACT_DIR \
0x100 /* Frequency factor direction, 0=down, 1=up */
#define AMBAPP_FLAG_FFACT 0x0f0 /* Frequency factor against top bus */
#define AMBAPP_FLAG_MBUS 0x00c
#define AMBAPP_FLAG_SBUS 0x003
/* Get APB or AHB information from a AMBA device */
#define DEV_TO_APB(adev) ((struct ambapp_apb_info *)((adev)->devinfo))
#define DEV_TO_AHB(adev) ((struct ambapp_ahb_info *)((adev)->devinfo))
#define DEV_TO_COMMON(adev) (((adev)->devinfo))
#define DEV_TO_APB( adev ) ( (struct ambapp_apb_info *) ( ( adev )->devinfo ) )
#define DEV_TO_AHB( adev ) ( (struct ambapp_ahb_info *) ( ( adev )->devinfo ) )
#define DEV_TO_COMMON( adev ) (( ( adev )->devinfo ))
struct ambapp_common_info {
unsigned char irq;
unsigned char ver;
unsigned char ahbidx; /* AHB Bus Index */
unsigned char irq;
unsigned char ver;
unsigned char ahbidx; /* AHB Bus Index */
};
struct ambapp_apb_info {
struct ambapp_common_info common;
struct ambapp_common_info common;
/* APB SPECIFIC */
uint32_t start;
uint32_t mask;
/* APB SPECIFIC */
uint32_t start;
uint32_t mask;
};
struct ambapp_ahb_info {
struct ambapp_common_info common;
struct ambapp_common_info common;
/* AHB SPECIFIC */
unsigned int start[4];
unsigned int mask[4];
char type[4]; /* type[N] Determine type of start[N]-mask[N],
/* AHB SPECIFIC */
unsigned int start[ 4 ];
unsigned int mask[ 4 ];
char type[ 4 ]; /* type[N] Determine type of start[N]-mask[N],
* 2=AHB Memory Space, 3=AHB I/O Space */
unsigned int custom[3];
unsigned int custom[ 3 ];
};
struct ambapp_dev {
struct ambapp_dev *next; /* Next */
struct ambapp_dev *prev; /* Previous Device. If (this ==
struct ambapp_dev *next; /* Next */
struct ambapp_dev *prev; /* Previous Device. If (this ==
* rev->child) prev is bus bridge */
struct ambapp_dev *children; /* Points to first device on sub-bus */
void *owner; /* Owner of this AMBA device */
unsigned char dev_type; /* AHB MST, AHB SLV or APB SLV*/
unsigned char vendor; /* Vendor ID */
unsigned short device; /* Device ID */
struct ambapp_dev *children; /* Points to first device on sub-bus */
void *owner; /* Owner of this AMBA device */
unsigned char dev_type; /* AHB MST, AHB SLV or APB SLV*/
unsigned char vendor; /* Vendor ID */
unsigned short device; /* Device ID */
/* Device info (APB/AHB dep. on type) */
struct ambapp_common_info devinfo[RTEMS_ZERO_LENGTH_ARRAY];
/* Device info (APB/AHB dep. on type) */
struct ambapp_common_info devinfo[ RTEMS_ZERO_LENGTH_ARRAY ];
};
/* Describes a complete AMBA Core. Each device may consist of 3 interfaces */
struct ambapp_core {
char irq; /* irq=-1 indicate no IRQ */
unsigned char vendor;
unsigned short device;
int index; /* Core index */
struct ambapp_ahb_info *ahb_mst;
struct ambapp_ahb_info *ahb_slv;
struct ambapp_apb_info *apb_slv;
char irq; /* irq=-1 indicate no IRQ */
unsigned char vendor;
unsigned short device;
int index; /* Core index */
struct ambapp_ahb_info *ahb_mst;
struct ambapp_ahb_info *ahb_slv;
struct ambapp_apb_info *apb_slv;
};
struct ambapp_ahb_bus {
unsigned int ioarea; /* AHB Bus IOAREA */
unsigned int freq_hz; /* Frequency of AHB Bus */
struct ambapp_dev *bridge;/* Bridge Device on Parent AHB Bus */
struct ambapp_dev *dev; /* First Device on AHB Bus */
unsigned int ioarea; /* AHB Bus IOAREA */
unsigned int freq_hz; /* Frequency of AHB Bus */
struct ambapp_dev *bridge; /* Bridge Device on Parent AHB Bus */
struct ambapp_dev *dev; /* First Device on AHB Bus */
};
struct ambapp_mmap {
unsigned int size;
unsigned int local_adr;
unsigned int remote_adr;
unsigned int size;
unsigned int local_adr;
unsigned int remote_adr;
};
/* Complete AMBA PnP information */
struct ambapp_bus {
struct ambapp_dev *root; /* AHB/APB Device Tree*/
struct ambapp_mmap *mmaps; /* Memory MAP Array */
struct ambapp_ahb_bus ahbs[AHB_BUS_MAX]; /* AHB Buses */
struct ambapp_dev *root; /* AHB/APB Device Tree*/
struct ambapp_mmap *mmaps; /* Memory MAP Array */
struct ambapp_ahb_bus ahbs[ AHB_BUS_MAX ]; /* AHB Buses */
};
/*
@@ -143,76 +144,83 @@ struct ambapp_bus {
* 0 - continue
* 1 - stop scanning
*/
typedef int (*ambapp_func_t)(struct ambapp_dev *dev, int index, void *arg);
typedef int ( *ambapp_func_t )( struct ambapp_dev *dev, int index, void *arg );
#define DEV_IS_FREE(dev) (dev->owner == NULL)
#define DEV_IS_ALLOCATED(dev) (dev->owner != NULL)
#define DEV_IS_FREE( dev ) ( dev->owner == NULL )
#define DEV_IS_ALLOCATED( dev ) ( dev->owner != NULL )
/* Options to ambapp_for_each */
#define OPTIONS_AHB_MSTS 0x00000001
#define OPTIONS_AHB_SLVS 0x00000002
#define OPTIONS_APB_SLVS 0x00000004
#define OPTIONS_ALL_DEVS (OPTIONS_AHB_MSTS|OPTIONS_AHB_SLVS|OPTIONS_APB_SLVS)
#define OPTIONS_AHB_MSTS 0x00000001
#define OPTIONS_AHB_SLVS 0x00000002
#define OPTIONS_APB_SLVS 0x00000004
#define OPTIONS_ALL_DEVS \
( OPTIONS_AHB_MSTS | OPTIONS_AHB_SLVS | OPTIONS_APB_SLVS )
#define OPTIONS_FREE 0x00000010
#define OPTIONS_ALLOCATED 0x00000020
#define OPTIONS_ALL (OPTIONS_FREE|OPTIONS_ALLOCATED)
#define OPTIONS_FREE 0x00000010
#define OPTIONS_ALLOCATED 0x00000020
#define OPTIONS_ALL ( OPTIONS_FREE | OPTIONS_ALLOCATED )
/* Depth first search, Defualt is breath first search. */
#define OPTIONS_DEPTH_FIRST 0x00000100
#define OPTIONS_DEPTH_FIRST 0x00000100
#define DEV_AHB_NONE 0
#define DEV_AHB_MST 1
#define DEV_AHB_SLV 2
#define DEV_APB_SLV 3
#define DEV_APB_SLV 3
/* Structures used to access Plug&Play information directly */
struct ambapp_pnp_ahb {
const unsigned int id; /* VENDOR, DEVICE, VER, IRQ, */
const unsigned int custom[3];
const unsigned int mbar[4]; /* MASK, ADDRESS, TYPE, CACHABLE/PREFETCHABLE */
const unsigned int id; /* VENDOR, DEVICE, VER, IRQ, */
const unsigned int custom[ 3 ];
const unsigned int
mbar[ 4 ]; /* MASK, ADDRESS, TYPE, CACHABLE/PREFETCHABLE */
};
struct ambapp_pnp_apb {
const unsigned int id; /* VENDOR, DEVICE, VER, IRQ, */
const unsigned int iobar; /* MASK, ADDRESS, TYPE, CACHABLE/PREFETCHABLE */
const unsigned int id; /* VENDOR, DEVICE, VER, IRQ, */
const unsigned int iobar; /* MASK, ADDRESS, TYPE, CACHABLE/PREFETCHABLE */
};
#define ambapp_pnp_vendor(id) (((id) >> 24) & 0xff)
#define ambapp_pnp_device(id) (((id) >> 12) & 0xfff)
#define ambapp_pnp_ver(id) (((id)>>5) & 0x1f)
#define ambapp_pnp_irq(id) ((id) & 0x1f)
#define ambapp_pnp_vendor( id ) ( ( ( id ) >> 24 ) & 0xff )
#define ambapp_pnp_device( id ) ( ( ( id ) >> 12 ) & 0xfff )
#define ambapp_pnp_ver( id ) ( ( ( id ) >> 5 ) & 0x1f )
#define ambapp_pnp_irq( id ) ( ( id ) & 0x1f )
#define ambapp_pnp_start(mbar) (((mbar) & 0xfff00000) & (((mbar) & 0xfff0) << 16))
#define ambapp_pnp_mbar_mask(mbar) (((mbar)>>4) & 0xfff)
#define ambapp_pnp_mbar_type(mbar) ((mbar) & 0xf)
#define ambapp_pnp_start( mbar ) \
( ( ( mbar ) & 0xfff00000 ) & ( ( ( mbar ) & 0xfff0 ) << 16 ) )
#define ambapp_pnp_mbar_mask( mbar ) ( ( ( mbar ) >> 4 ) & 0xfff )
#define ambapp_pnp_mbar_type( mbar ) ( ( mbar ) & 0xf )
#define ambapp_pnp_apb_start(iobar, base) ((base) | ((((iobar) & 0xfff00000)>>12) & (((iobar) & 0xfff0)<<4)) )
#define ambapp_pnp_apb_mask(iobar) ((~(ambapp_pnp_mbar_mask(iobar)<<8) & 0x000fffff) + 1)
#define ambapp_pnp_apb_start( iobar, base ) \
( ( base ) | ( ( ( ( iobar ) & 0xfff00000 ) >> 12 ) & \
( ( ( iobar ) & 0xfff0 ) << 4 ) ) )
#define ambapp_pnp_apb_mask( iobar ) \
( ( ~( ambapp_pnp_mbar_mask( iobar ) << 8 ) & 0x000fffff ) + 1 )
#define AMBA_TYPE_AHBIO_ADDR(addr,base_ioarea) ((unsigned int)(base_ioarea) | ((addr) >> 12))
#define AMBA_TYPE_AHBIO_ADDR( addr, base_ioarea ) \
( (unsigned int) ( base_ioarea ) | ( ( addr ) >> 12 ) )
#define AMBA_TYPE_APBIO 0x1
#define AMBA_TYPE_MEM 0x2
#define AMBA_TYPE_AHBIO 0x3
/* Copy Data from AMBA PnP I/O Area */
typedef void *(*ambapp_memcpy_t)(
void *dest, /* Destination RAM copy */
const void *src, /* Source AMBA PnP Address to copy from */
int n, /* Number of bytes to be copied */
struct ambapp_bus *abus /* Optional AMBA Bus pointer */
);
typedef void *( *ambapp_memcpy_t )(
void *dest, /* Destination RAM copy */
const void *src, /* Source AMBA PnP Address to copy from */
int n, /* Number of bytes to be copied */
struct ambapp_bus *abus /* Optional AMBA Bus pointer */
);
struct ambapp_context {
ambapp_memcpy_t copy_from_device;
void *(*alloc)(size_t);
void *( *alloc )( size_t );
};
/**
* @brief Gets the fully scanned AMBA Plug & Play Processor Local Bus (PLB).
*/
extern struct ambapp_bus *ambapp_plb(void);
extern struct ambapp_bus *ambapp_plb( void );
/* Scan a AMBA Plug & Play bus and create all device structures describing the
* the devices. The devices will form a tree, where every node describes one
@@ -228,24 +236,26 @@ extern struct ambapp_bus *ambapp_plb(void);
*
*/
extern int ambapp_scan(
struct ambapp_bus *abus,
unsigned int ioarea,
const struct ambapp_context *ctx,
struct ambapp_mmap *mmaps
);
struct ambapp_bus *abus,
unsigned int ioarea,
const struct ambapp_context *ctx,
struct ambapp_mmap *mmaps
);
/* Initialize the frequency [Hz] of all AHB Buses from knowing the frequency
* of one particular APB/AHB Device.
*/
extern void ambapp_freq_init(
struct ambapp_bus *abus,
struct ambapp_dev *dev,
unsigned int freq);
struct ambapp_bus *abus,
struct ambapp_dev *dev,
unsigned int freq
);
/* Returns the frequency [Hz] of a AHB/APB device */
extern unsigned int ambapp_freq_get(
struct ambapp_bus *abus,
struct ambapp_dev *dev);
struct ambapp_bus *abus,
struct ambapp_dev *dev
);
/* Iterates through all AMBA devices previously found, it calls func
* once for every device that match the search arguments.
@@ -274,12 +284,13 @@ extern unsigned int ambapp_freq_get(
* non-zero - stopped by user function returning the non-zero value
*/
extern int ambapp_for_each(
struct ambapp_bus *abus,
unsigned int options,
int vendor,
int device,
ambapp_func_t func,
void *arg);
struct ambapp_bus *abus,
unsigned int options,
int vendor,
int device,
ambapp_func_t func,
void *arg
);
/* Helper function for ambapp_for_each(), find a device by index. If pcount
* is NULL the first device is returned, else pcount is interpreted as index
@@ -290,110 +301,127 @@ extern int ambapp_for_each(
* If zero is returned from ambapp_for_each no device matching the index was
* found
*/
extern int ambapp_find_by_idx(struct ambapp_dev *dev, int index, void *pcount);
extern int ambapp_find_by_idx(
struct ambapp_dev *dev,
int index,
void *pcount
);
/* Get number of devices matching the options/vendor/device arguments, the
* arguments are passed onto ambapp_for_each().
*/
extern int ambapp_dev_count(struct ambapp_bus *abus, unsigned int options,
int vendor, int device);
extern int ambapp_dev_count(
struct ambapp_bus *abus,
unsigned int options,
int vendor,
int device
);
/* Print short information about devices on the AMBA bus onto the console */
extern void ambapp_print(struct ambapp_bus *abus, int show_depth);
extern void ambapp_print( struct ambapp_bus *abus, int show_depth );
/* Mark a device taken (allocate), Owner field is set with owner Data. Returns
* -1 if device has already been allocated.
*/
extern int ambapp_alloc_dev(struct ambapp_dev *dev, void *owner);
extern int ambapp_alloc_dev( struct ambapp_dev *dev, void *owner );
/* Owner field is cleared, which indicates that device is not allocated */
extern void ambapp_free_dev(struct ambapp_dev *dev);
extern void ambapp_free_dev( struct ambapp_dev *dev );
/* Find AHB/APB Bridge or AHB/AHB Bridge Parent */
extern struct ambapp_dev *ambapp_find_parent(struct ambapp_dev *dev);
extern struct ambapp_dev *ambapp_find_parent( struct ambapp_dev *dev );
/* Returns bus depth (number of sub AHB buses) of device from root bus */
extern int ambapp_depth(struct ambapp_dev *dev);
extern int ambapp_depth( struct ambapp_dev *dev );
/* Get Device Name from AMBA PnP name database */
extern char *ambapp_device_id2str(unsigned int vendor, int id);
extern char *ambapp_device_id2str( unsigned int vendor, int id );
/* Get Vendor Name from AMBA PnP name database */
extern char *ambapp_vendor_id2str(unsigned int vendor);
extern char *ambapp_vendor_id2str( unsigned int vendor );
/* Set together VENDOR_DEVICE Name from AMBA PnP name database. Return length
* of C-string stored in buf not including string termination '\0'.
*/
extern int ambapp_vendev_id2str(unsigned int vendor, int id, char *buf);
extern int ambapp_vendev_id2str( unsigned int vendor, int id, char *buf );
/* Help functions for backwards compability */
extern int ambapp_find_apbslv(
struct ambapp_bus *abus,
int vendor,
int device,
struct ambapp_apb_info *dev);
struct ambapp_bus *abus,
int vendor,
int device,
struct ambapp_apb_info *dev
);
extern int ambapp_find_apbslv_next(
struct ambapp_bus *abus,
int vendor,
int device,
struct ambapp_apb_info *dev,
int index);
struct ambapp_bus *abus,
int vendor,
int device,
struct ambapp_apb_info *dev,
int index
);
extern int ambapp_find_apbslvs_next(
struct ambapp_bus *abus,
int vendor,
int device,
struct ambapp_apb_info *dev,
int index,
int maxno);
struct ambapp_bus *abus,
int vendor,
int device,
struct ambapp_apb_info *dev,
int index,
int maxno
);
extern int ambapp_find_apbslvs(
struct ambapp_bus *abus,
int vendor,
int device,
struct ambapp_apb_info *dev,
int maxno);
struct ambapp_bus *abus,
int vendor,
int device,
struct ambapp_apb_info *dev,
int maxno
);
extern int ambapp_find_ahbslv(
struct ambapp_bus *abus,
int vendor,
int device,
struct ambapp_ahb_info *dev);
struct ambapp_bus *abus,
int vendor,
int device,
struct ambapp_ahb_info *dev
);
extern int ambapp_find_ahbslv_next(
struct ambapp_bus *abus,
int vendor,
int device,
struct ambapp_ahb_info *dev,
int index);
struct ambapp_bus *abus,
int vendor,
int device,
struct ambapp_ahb_info *dev,
int index
);
extern int ambapp_find_ahbslvs_next(
struct ambapp_bus *abus,
int vendor,
int device,
struct ambapp_ahb_info *dev,
int index,
int maxno);
struct ambapp_bus *abus,
int vendor,
int device,
struct ambapp_ahb_info *dev,
int index,
int maxno
);
extern int ambapp_find_ahbslvs(
struct ambapp_bus *abus,
int vendor,
int device,
struct ambapp_ahb_info *dev,
int maxno);
struct ambapp_bus *abus,
int vendor,
int device,
struct ambapp_ahb_info *dev,
int maxno
);
extern int ambapp_get_number_ahbslv_devices(
struct ambapp_bus *abus,
int vendor,
int device);
struct ambapp_bus *abus,
int vendor,
int device
);
extern int ambapp_get_number_apbslv_devices(
struct ambapp_bus *abus,
int vendor,
int device);
struct ambapp_bus *abus,
int vendor,
int device
);
#ifdef __cplusplus
}
bsps/include/grlib/ambapp_bus.h
+128 -80
View File
@@ -43,117 +43,165 @@ extern "C" {
#endif
/* GRLIB AMBA Plug&Play Driver ID generation */
#define DRIVER_AMBAPP_ID(vendor, device) \
DRIVER_ID(DRVMGR_BUS_TYPE_AMBAPP, ((((vendor) & 0xff) << 16) | ((device) & 0xfff)))
#define DRIVER_AMBAPP_ID( vendor, device ) \
DRIVER_ID( \
DRVMGR_BUS_TYPE_AMBAPP, \
( ( ( ( vendor ) & 0xff ) << 16 ) | ( ( device ) & 0xfff ) ) \
)
/*** Gaisler Hardware Device Driver IDs ***/
#define DRIVER_AMBAPP_GAISLER_AHBSTAT_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_AHBSTAT)
#define DRIVER_AMBAPP_GAISLER_APBUART_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_APBUART)
#define DRIVER_AMBAPP_GAISLER_B1553BRM_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_B1553BRM)
#define DRIVER_AMBAPP_GAISLER_B1553RT_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_B1553RT)
#define DRIVER_AMBAPP_GAISLER_GPTIMER_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_GPTIMER)
#define DRIVER_AMBAPP_GAISLER_GR1553B_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_GR1553B)
#define DRIVER_AMBAPP_GAISLER_GRADCDAC_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_GRADCDAC)
#define DRIVER_AMBAPP_GAISLER_GRAES_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_GRAESDMA)
#define DRIVER_AMBAPP_GAISLER_GRCAN_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_GRCAN)
#define DRIVER_AMBAPP_GAISLER_GRCTM_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_GRCTM)
#define DRIVER_AMBAPP_GAISLER_GRETH_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_ETHMAC)
#define DRIVER_AMBAPP_GAISLER_GRGPIO_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_GPIO)
#define DRIVER_AMBAPP_GAISLER_GRPCI2_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_GRPCI2)
#define DRIVER_AMBAPP_GAISLER_GRIOMMU_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_GRIOMMU)
#define DRIVER_AMBAPP_GAISLER_GRPCI_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_PCIFBRG)
#define DRIVER_AMBAPP_GAISLER_GRPWM_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_GRPWM)
#define DRIVER_AMBAPP_GAISLER_GRPWRX_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_PW2APB)
#define DRIVER_AMBAPP_GAISLER_GRSPW_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_SPW)
#define DRIVER_AMBAPP_GAISLER_GRSPW2_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_SPW2)
#define DRIVER_AMBAPP_GAISLER_GRTC_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_GRTC)
#define DRIVER_AMBAPP_GAISLER_GRTM_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_GRTM)
#define DRIVER_AMBAPP_GAISLER_I2CMST_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_I2CMST)
#define DRIVER_AMBAPP_GAISLER_OCCAN_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_CANAHB)
#define DRIVER_AMBAPP_GAISLER_PCIF_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_PCIF)
#define DRIVER_AMBAPP_GAISLER_PCITRACE_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_PCITRACE)
#define DRIVER_AMBAPP_GAISLER_SPICTRL_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_SPICTRL)
#define DRIVER_AMBAPP_GAISLER_SPWCUC_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_SPWCUC)
#define DRIVER_AMBAPP_GAISLER_SPW_ROUTER_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_SPW_ROUTER)
#define DRIVER_AMBAPP_GAISLER_L2CACHE_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_L2CACHE)
#define DRIVER_AMBAPP_GAISLER_MEMSCRUB_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_MEMSCRUB)
#define DRIVER_AMBAPP_GAISLER_L4STAT_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_L4STAT)
#define DRIVER_AMBAPP_GAISLER_SPWTDP_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_SPWTDP)
#define DRIVER_AMBAPP_GAISLER_AHBSTAT_ID \
DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_AHBSTAT )
#define DRIVER_AMBAPP_GAISLER_APBUART_ID \
DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_APBUART )
#define DRIVER_AMBAPP_GAISLER_B1553BRM_ID \
DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_B1553BRM )
#define DRIVER_AMBAPP_GAISLER_B1553RT_ID \
DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_B1553RT )
#define DRIVER_AMBAPP_GAISLER_GPTIMER_ID \
DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_GPTIMER )
#define DRIVER_AMBAPP_GAISLER_GR1553B_ID \
DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_GR1553B )
#define DRIVER_AMBAPP_GAISLER_GRADCDAC_ID \
DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_GRADCDAC )
#define DRIVER_AMBAPP_GAISLER_GRAES_ID \
DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_GRAESDMA )
#define DRIVER_AMBAPP_GAISLER_GRCAN_ID \
DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_GRCAN )
#define DRIVER_AMBAPP_GAISLER_GRCTM_ID \
DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_GRCTM )
#define DRIVER_AMBAPP_GAISLER_GRETH_ID \
DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_ETHMAC )
#define DRIVER_AMBAPP_GAISLER_GRGPIO_ID \
DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_GPIO )
#define DRIVER_AMBAPP_GAISLER_GRPCI2_ID \
DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_GRPCI2 )
#define DRIVER_AMBAPP_GAISLER_GRIOMMU_ID \
DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_GRIOMMU )
#define DRIVER_AMBAPP_GAISLER_GRPCI_ID \
DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_PCIFBRG )
#define DRIVER_AMBAPP_GAISLER_GRPWM_ID \
DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_GRPWM )
#define DRIVER_AMBAPP_GAISLER_GRPWRX_ID \
DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_PW2APB )
#define DRIVER_AMBAPP_GAISLER_GRSPW_ID \
DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_SPW )
#define DRIVER_AMBAPP_GAISLER_GRSPW2_ID \
DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_SPW2 )
#define DRIVER_AMBAPP_GAISLER_GRTC_ID \
DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_GRTC )
#define DRIVER_AMBAPP_GAISLER_GRTM_ID \
DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_GRTM )
#define DRIVER_AMBAPP_GAISLER_I2CMST_ID \
DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_I2CMST )
#define DRIVER_AMBAPP_GAISLER_OCCAN_ID \
DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_CANAHB )
#define DRIVER_AMBAPP_GAISLER_PCIF_ID \
DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_PCIF )
#define DRIVER_AMBAPP_GAISLER_PCITRACE_ID \
DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_PCITRACE )
#define DRIVER_AMBAPP_GAISLER_SPICTRL_ID \
DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_SPICTRL )
#define DRIVER_AMBAPP_GAISLER_SPWCUC_ID \
DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_SPWCUC )
#define DRIVER_AMBAPP_GAISLER_SPW_ROUTER_ID \
DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_SPW_ROUTER )
#define DRIVER_AMBAPP_GAISLER_L2CACHE_ID \
DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_L2CACHE )
#define DRIVER_AMBAPP_GAISLER_MEMSCRUB_ID \
DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_MEMSCRUB )
#define DRIVER_AMBAPP_GAISLER_L4STAT_ID \
DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_L4STAT )
#define DRIVER_AMBAPP_GAISLER_SPWTDP_ID \
DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_SPWTDP )
/*** ESA Hardware Device Driver IDs ***/
#define DRIVER_AMBAPP_ESA_MCTRL_ID DRIVER_AMBAPP_ID(VENDOR_ESA, ESA_MCTRL)
#define DRIVER_AMBAPP_MCTRL_ID DRIVER_AMBAPP_ESA_MCTRL_ID
#define DRIVER_AMBAPP_ESA_MCTRL_ID DRIVER_AMBAPP_ID( VENDOR_ESA, ESA_MCTRL )
#define DRIVER_AMBAPP_MCTRL_ID DRIVER_AMBAPP_ESA_MCTRL_ID
struct amba_dev_id {
unsigned short vendor;
unsigned short device;
/* Version ? */
unsigned short vendor;
unsigned short device;
/* Version ? */
};
struct amba_drv_info {
struct drvmgr_drv general; /* General bus info */
/* AMBA specific bus information */
struct amba_dev_id *ids; /* Supported hardware */
struct drvmgr_drv general; /* General bus info */
/* AMBA specific bus information */
struct amba_dev_id *ids; /* Supported hardware */
};
struct amba_dev_info {
struct amba_dev_id id;
struct ambapp_core info;
struct amba_dev_id id;
struct ambapp_core info;
};
struct ambapp_ops {
int (*int_register)
(struct drvmgr_dev *dev, int index, const char *info, drvmgr_isr isr, void *arg);
int (*int_unregister)
(struct drvmgr_dev *dev, int index, drvmgr_isr isr, void *arg);
int (*int_clear)(struct drvmgr_dev *dev, int index);
int (*int_mask)(struct drvmgr_dev *dev, int index);
int (*int_unmask)(struct drvmgr_dev *dev, int index);
int ( *int_register )(
struct drvmgr_dev *dev,
int index,
const char *info,
drvmgr_isr isr,
void *arg
);
int ( *int_unregister )(
struct drvmgr_dev *dev,
int index,
drvmgr_isr isr,
void *arg
);
int ( *int_clear )( struct drvmgr_dev *dev, int index );
int ( *int_mask )( struct drvmgr_dev *dev, int index );
int ( *int_unmask )( struct drvmgr_dev *dev, int index );
#ifdef RTEMS_SMP
int (*int_set_affinity)(struct drvmgr_dev *dev, int index,
const Processor_mask *cpus);
int ( *int_set_affinity )(
struct drvmgr_dev *dev,
int index,
const Processor_mask *cpus
);
#endif
int (*get_params)
(struct drvmgr_dev *, struct drvmgr_bus_params *);
int ( *get_params )( struct drvmgr_dev *, struct drvmgr_bus_params * );
};
struct ambapp_config {
struct ambapp_bus *abus; /* Prescanned AMBA PnP bus */
struct ambapp_ops *ops; /* AMBA bus operations */
struct drvmgr_map_entry *maps_up; /* Bus memory map up-stream towards CPU */
struct drvmgr_map_entry *maps_down; /* Bus memory map down-stream towards HW */
struct drvmgr_bus_res *resources; /* Driver Resources */
int bus_type; /* Set DRVMGR_BUS_TYPE_AMBAPP_DIST if distributed AMBA Bus */
struct drvmgr_func *funcs; /* Custom functions */
struct ambapp_bus *abus; /* Prescanned AMBA PnP bus */
struct ambapp_ops *ops; /* AMBA bus operations */
struct drvmgr_map_entry *maps_up; /* Bus memory map up-stream towards CPU */
struct drvmgr_map_entry
*maps_down; /* Bus memory map down-stream towards HW */
struct drvmgr_bus_res *resources; /* Driver Resources */
int bus_type; /* Set DRVMGR_BUS_TYPE_AMBAPP_DIST if distributed AMBA Bus */
struct drvmgr_func *funcs; /* Custom functions */
};
/*** Bus operations with READ/WRITE access operations ***
*
* The functions are implemented using the standard drvmgr RW interface
*/
#define AMBAPP_R8 DRVMGR_RWFUNC(RW_SIZE_1|RW_READ|RW_REG)
#define AMBAPP_R16 DRVMGR_RWFUNC(RW_SIZE_2|RW_READ|RW_REG)
#define AMBAPP_R32 DRVMGR_RWFUNC(RW_SIZE_4|RW_READ|RW_REG)
#define AMBAPP_R64 DRVMGR_RWFUNC(RW_SIZE_8|RW_READ|RW_REG)
#define AMBAPP_W8 DRVMGR_RWFUNC(RW_SIZE_1|RW_WRITE|RW_REG)
#define AMBAPP_W16 DRVMGR_RWFUNC(RW_SIZE_2|RW_WRITE|RW_REG)
#define AMBAPP_W32 DRVMGR_RWFUNC(RW_SIZE_4|RW_WRITE|RW_REG)
#define AMBAPP_W64 DRVMGR_RWFUNC(RW_SIZE_8|RW_WRITE|RW_REG)
#define AMBAPP_RMEM DRVMGR_RWFUNC(RW_SIZE_ANY|RW_READ|RW_MEM)
#define AMBAPP_WMEM DRVMGR_RWFUNC(RW_SIZE_ANY|RW_WRITE|RW_MEM)
#define AMBAPP_MEMSET DRVMGR_RWFUNC(RW_SIZE_ANY|RW_SET|RW_MEM)
#define AMBAPP_RW_ARG DRVMGR_RWFUNC(RW_ARG)
#define AMBAPP_R8 DRVMGR_RWFUNC( RW_SIZE_1 | RW_READ | RW_REG )
#define AMBAPP_R16 DRVMGR_RWFUNC( RW_SIZE_2 | RW_READ | RW_REG )
#define AMBAPP_R32 DRVMGR_RWFUNC( RW_SIZE_4 | RW_READ | RW_REG )
#define AMBAPP_R64 DRVMGR_RWFUNC( RW_SIZE_8 | RW_READ | RW_REG )
#define AMBAPP_W8 DRVMGR_RWFUNC( RW_SIZE_1 | RW_WRITE | RW_REG )
#define AMBAPP_W16 DRVMGR_RWFUNC( RW_SIZE_2 | RW_WRITE | RW_REG )
#define AMBAPP_W32 DRVMGR_RWFUNC( RW_SIZE_4 | RW_WRITE | RW_REG )
#define AMBAPP_W64 DRVMGR_RWFUNC( RW_SIZE_8 | RW_WRITE | RW_REG )
#define AMBAPP_RMEM DRVMGR_RWFUNC( RW_SIZE_ANY | RW_READ | RW_MEM )
#define AMBAPP_WMEM DRVMGR_RWFUNC( RW_SIZE_ANY | RW_WRITE | RW_MEM )
#define AMBAPP_MEMSET DRVMGR_RWFUNC( RW_SIZE_ANY | RW_SET | RW_MEM )
#define AMBAPP_RW_ARG DRVMGR_RWFUNC( RW_ARG )
/* Register an ambapp bus on-top of a device */
extern int ambapp_bus_register(
struct drvmgr_dev *dev,
struct ambapp_config *config
);
struct drvmgr_dev *dev,
struct ambapp_config *config
);
extern void ambapp_bus_freq_register(
struct drvmgr_dev *dev,
int amba_interface,
unsigned int freq_hz);
struct drvmgr_dev *dev,
int amba_interface,
unsigned int freq_hz
);
#ifdef __cplusplus
}
bsps/include/grlib/ambapp_bus_grlib.h
+4 -4
View File
@@ -38,15 +38,15 @@ extern "C" {
#endif
struct grlib_config {
struct ambapp_bus *abus;
struct drvmgr_bus_res *resources;
struct ambapp_bus *abus;
struct drvmgr_bus_res *resources;
};
/* Register GRLIB AMBA PnP Bus as root bus at driver manager */
extern int ambapp_grlib_root_register(struct grlib_config *config);
extern int ambapp_grlib_root_register( struct grlib_config *config );
/* Register bus driver to Driver Manager */
void ambapp_grlib_register(void);
void ambapp_grlib_register( void );
#ifdef __cplusplus
}
bsps/include/grlib/ambapp_ids.h
+292 -293
View File
File diff suppressed because it is too large Load Diff
bsps/include/grlib/apbuart-regs.h
+25 -35
View File
@@ -82,17 +82,14 @@ extern "C" {
*/
#define APBUART_DATA_DATA_SHIFT 0
#define APBUART_DATA_DATA_MASK 0xffU
#define APBUART_DATA_DATA_MASK 0xffU
#define APBUART_DATA_DATA_GET( _reg ) \
( ( ( _reg ) & APBUART_DATA_DATA_MASK ) >> \
APBUART_DATA_DATA_SHIFT )
#define APBUART_DATA_DATA_SET( _reg, _val ) \
( ( ( _reg ) & APBUART_DATA_DATA_MASK ) >> APBUART_DATA_DATA_SHIFT )
#define APBUART_DATA_DATA_SET( _reg, _val ) \
( ( ( _reg ) & ~APBUART_DATA_DATA_MASK ) | \
( ( ( _val ) << APBUART_DATA_DATA_SHIFT ) & \
APBUART_DATA_DATA_MASK ) )
( ( ( _val ) << APBUART_DATA_DATA_SHIFT ) & APBUART_DATA_DATA_MASK ) )
#define APBUART_DATA_DATA( _val ) \
( ( ( _val ) << APBUART_DATA_DATA_SHIFT ) & \
APBUART_DATA_DATA_MASK )
( ( ( _val ) << APBUART_DATA_DATA_SHIFT ) & APBUART_DATA_DATA_MASK )
/** @} */
@@ -105,30 +102,26 @@ extern "C" {
*/
#define APBUART_STATUS_RCNT_SHIFT 26
#define APBUART_STATUS_RCNT_MASK 0xfc000000U
#define APBUART_STATUS_RCNT_MASK 0xfc000000U
#define APBUART_STATUS_RCNT_GET( _reg ) \
( ( ( _reg ) & APBUART_STATUS_RCNT_MASK ) >> \
APBUART_STATUS_RCNT_SHIFT )
#define APBUART_STATUS_RCNT_SET( _reg, _val ) \
( ( ( _reg ) & ~APBUART_STATUS_RCNT_MASK ) | \
( ( ( _reg ) & APBUART_STATUS_RCNT_MASK ) >> APBUART_STATUS_RCNT_SHIFT )
#define APBUART_STATUS_RCNT_SET( _reg, _val ) \
( ( ( _reg ) & ~APBUART_STATUS_RCNT_MASK ) | \
( ( ( _val ) << APBUART_STATUS_RCNT_SHIFT ) & \
APBUART_STATUS_RCNT_MASK ) )
#define APBUART_STATUS_RCNT( _val ) \
( ( ( _val ) << APBUART_STATUS_RCNT_SHIFT ) & \
APBUART_STATUS_RCNT_MASK )
( ( ( _val ) << APBUART_STATUS_RCNT_SHIFT ) & APBUART_STATUS_RCNT_MASK )
#define APBUART_STATUS_TCNT_SHIFT 20
#define APBUART_STATUS_TCNT_MASK 0x3f00000U
#define APBUART_STATUS_TCNT_MASK 0x3f00000U
#define APBUART_STATUS_TCNT_GET( _reg ) \
( ( ( _reg ) & APBUART_STATUS_TCNT_MASK ) >> \
APBUART_STATUS_TCNT_SHIFT )
#define APBUART_STATUS_TCNT_SET( _reg, _val ) \
( ( ( _reg ) & ~APBUART_STATUS_TCNT_MASK ) | \
( ( ( _reg ) & APBUART_STATUS_TCNT_MASK ) >> APBUART_STATUS_TCNT_SHIFT )
#define APBUART_STATUS_TCNT_SET( _reg, _val ) \
( ( ( _reg ) & ~APBUART_STATUS_TCNT_MASK ) | \
( ( ( _val ) << APBUART_STATUS_TCNT_SHIFT ) & \
APBUART_STATUS_TCNT_MASK ) )
#define APBUART_STATUS_TCNT( _val ) \
( ( ( _val ) << APBUART_STATUS_TCNT_SHIFT ) & \
APBUART_STATUS_TCNT_MASK )
( ( ( _val ) << APBUART_STATUS_TCNT_SHIFT ) & APBUART_STATUS_TCNT_MASK )
#define APBUART_STATUS_RF 0x400U
@@ -205,15 +198,15 @@ extern "C" {
*/
#define APBUART_SCALER_SCALER_RELOAD_VALUE_SHIFT 0
#define APBUART_SCALER_SCALER_RELOAD_VALUE_MASK 0xfffffU
#define APBUART_SCALER_SCALER_RELOAD_VALUE_GET( _reg ) \
#define APBUART_SCALER_SCALER_RELOAD_VALUE_MASK 0xfffffU
#define APBUART_SCALER_SCALER_RELOAD_VALUE_GET( _reg ) \
( ( ( _reg ) & APBUART_SCALER_SCALER_RELOAD_VALUE_MASK ) >> \
APBUART_SCALER_SCALER_RELOAD_VALUE_SHIFT )
#define APBUART_SCALER_SCALER_RELOAD_VALUE_SET( _reg, _val ) \
( ( ( _reg ) & ~APBUART_SCALER_SCALER_RELOAD_VALUE_MASK ) | \
#define APBUART_SCALER_SCALER_RELOAD_VALUE_SET( _reg, _val ) \
( ( ( _reg ) & ~APBUART_SCALER_SCALER_RELOAD_VALUE_MASK ) | \
( ( ( _val ) << APBUART_SCALER_SCALER_RELOAD_VALUE_SHIFT ) & \
APBUART_SCALER_SCALER_RELOAD_VALUE_MASK ) )
#define APBUART_SCALER_SCALER_RELOAD_VALUE( _val ) \
#define APBUART_SCALER_SCALER_RELOAD_VALUE( _val ) \
( ( ( _val ) << APBUART_SCALER_SCALER_RELOAD_VALUE_SHIFT ) & \
APBUART_SCALER_SCALER_RELOAD_VALUE_MASK )
@@ -228,17 +221,14 @@ extern "C" {
*/
#define APBUART_FIFO_DATA_SHIFT 0
#define APBUART_FIFO_DATA_MASK 0xffU
#define APBUART_FIFO_DATA_MASK 0xffU
#define APBUART_FIFO_DATA_GET( _reg ) \
( ( ( _reg ) & APBUART_FIFO_DATA_MASK ) >> \
APBUART_FIFO_DATA_SHIFT )
#define APBUART_FIFO_DATA_SET( _reg, _val ) \
( ( ( _reg ) & APBUART_FIFO_DATA_MASK ) >> APBUART_FIFO_DATA_SHIFT )
#define APBUART_FIFO_DATA_SET( _reg, _val ) \
( ( ( _reg ) & ~APBUART_FIFO_DATA_MASK ) | \
( ( ( _val ) << APBUART_FIFO_DATA_SHIFT ) & \
APBUART_FIFO_DATA_MASK ) )
( ( ( _val ) << APBUART_FIFO_DATA_SHIFT ) & APBUART_FIFO_DATA_MASK ) )
#define APBUART_FIFO_DATA( _val ) \
( ( ( _val ) << APBUART_FIFO_DATA_SHIFT ) & \
APBUART_FIFO_DATA_MASK )
( ( ( _val ) << APBUART_FIFO_DATA_SHIFT ) & APBUART_FIFO_DATA_MASK )
/** @} */
bsps/include/grlib/apbuart_cons.h
+1 -1
View File
@@ -30,6 +30,6 @@
#ifndef __APBUART_CONS_H__
#define __APBUART_CONS_H__
void apbuart_cons_register_drv (void);
void apbuart_cons_register_drv( void );
#endif
bsps/include/grlib/apbuart_termios.h
+5 -5
View File
@@ -42,11 +42,11 @@ extern "C" {
struct apbuart_context {
rtems_termios_device_context base;
apbuart *regs;
unsigned int freq_hz;
rtems_vector_number irq;
volatile int sending;
char *buf;
apbuart *regs;
unsigned int freq_hz;
rtems_vector_number irq;
volatile int sending;
char *buf;
};
extern const rtems_termios_device_handler apbuart_handler_interrupt;
bsps/include/grlib/b1553brm.h
+70 -73
View File
@@ -51,47 +51,47 @@ extern "C" {
#endif
struct brm_reg {
volatile uint32_t ctrl; /* 0x00 */
volatile uint32_t oper; /* 0x04 */
volatile uint32_t cur_cmd; /* 0x08 */
volatile uint32_t imask; /* 0x0C */
volatile uint32_t ipend; /* 0x10 */
volatile uint32_t ipoint; /* 0x14 */
volatile uint32_t bit_reg; /* 0x18 */
volatile uint32_t ttag; /* 0x1C */
volatile uint32_t dpoint; /* 0x20 */
volatile uint32_t sw; /* 0x24 */
volatile uint32_t initcount; /* 0x28 */
volatile uint32_t mcpoint; /* 0x2C */
volatile uint32_t mdpoint; /* 0x30 */
volatile uint32_t mbc; /* 0x34 */
volatile uint32_t mfilta; /* 0x38 */
volatile uint32_t mfiltb; /* 0x3C */
volatile uint32_t rt_cmd_leg[16]; /* 0x40-0x80 */
volatile uint32_t enhanced; /* 0x84 */
volatile uint32_t ctrl; /* 0x00 */
volatile uint32_t oper; /* 0x04 */
volatile uint32_t cur_cmd; /* 0x08 */
volatile uint32_t imask; /* 0x0C */
volatile uint32_t ipend; /* 0x10 */
volatile uint32_t ipoint; /* 0x14 */
volatile uint32_t bit_reg; /* 0x18 */
volatile uint32_t ttag; /* 0x1C */
volatile uint32_t dpoint; /* 0x20 */
volatile uint32_t sw; /* 0x24 */
volatile uint32_t initcount; /* 0x28 */
volatile uint32_t mcpoint; /* 0x2C */
volatile uint32_t mdpoint; /* 0x30 */
volatile uint32_t mbc; /* 0x34 */
volatile uint32_t mfilta; /* 0x38 */
volatile uint32_t mfiltb; /* 0x3C */
volatile uint32_t rt_cmd_leg[ 16 ]; /* 0x40-0x80 */
volatile uint32_t enhanced; /* 0x84 */
volatile uint32_t dummy[31];
volatile uint32_t dummy[ 31 ];
volatile uint32_t w_ctrl; /* 0x100 */
volatile uint32_t w_irqctrl; /* 0x104 */
volatile uint32_t w_ahbaddr; /* 0x108 */
volatile uint32_t w_ctrl; /* 0x100 */
volatile uint32_t w_irqctrl; /* 0x104 */
volatile uint32_t w_ahbaddr; /* 0x108 */
};
struct bm_msg {
unsigned short miw;
unsigned short cw1;
unsigned short cw2;
unsigned short sw1;
unsigned short sw2;
unsigned short time;
unsigned short data[32];
unsigned short miw;
unsigned short cw1;
unsigned short cw2;
unsigned short sw1;
unsigned short sw2;
unsigned short time;
unsigned short data[ 32 ];
};
struct rt_msg {
unsigned short miw;
unsigned short time;
unsigned short data[32];
unsigned short desc;
unsigned short miw;
unsigned short time;
unsigned short data[ 32 ];
unsigned short desc;
};
/*
@@ -114,37 +114,36 @@ struct rt_msg {
*
*/
struct bc_msg {
unsigned char rtaddr[2];
unsigned char subaddr[2];
unsigned short wc;
unsigned short ctrl;
unsigned short tsw[2];
unsigned short data[32];
unsigned char rtaddr[ 2 ];
unsigned char subaddr[ 2 ];
unsigned short wc;
unsigned short ctrl;
unsigned short tsw[ 2 ];
unsigned short data[ 32 ];
};
/* BC control bits */
#define BC_TR 0x0001
#define BC_RTRT 0x0002
#define BC_BUSA 0x0004
#define BC_EOL 0x0020
#define BC_SKIP 0x0040
#define BC_BAME 0x8000
#define BRM_MBC_IRQ 1 /* Monitor Block Counter irq */
#define BRM_CBA_IRQ 2 /* Command Block Accessed irq */
#define BRM_RTF_IRQ 4 /* Retry Fail irq */
#define BRM_ILLOP_IRQ 8 /* Illogical Opcode irq */
#define BRM_BC_ILLCMD_IRQ 16 /* BC Illocigal Command irq */
#define BRM_EOL_IRQ 32 /* End Of List irq */
#define BRM_RT_ILLCMD_IRQ 128 /* RT Illegal Command irq */
#define BRM_IXEQ0_IRQ 256 /* Index Equal Zero irq */
#define BRM_BDRCV_IRQ 512 /* Broadcast Command Received irq */
#define BRM_SUBAD_IRQ 1024 /* Subaddress Accessed irq */
#define BRM_MERR_IRQ 2048 /* Message Error irq */
#define BRM_TAPF_IRQ 8192 /* Terminal Address Parity Fail irq */
#define BRM_WRAPF_IRQ 16384 /* Wrap Fail irq */
#define BRM_DMAF_IRQ 32768 /* DMA Fail irq */
#define BC_TR 0x0001
#define BC_RTRT 0x0002
#define BC_BUSA 0x0004
#define BC_EOL 0x0020
#define BC_SKIP 0x0040
#define BC_BAME 0x8000
#define BRM_MBC_IRQ 1 /* Monitor Block Counter irq */
#define BRM_CBA_IRQ 2 /* Command Block Accessed irq */
#define BRM_RTF_IRQ 4 /* Retry Fail irq */
#define BRM_ILLOP_IRQ 8 /* Illogical Opcode irq */
#define BRM_BC_ILLCMD_IRQ 16 /* BC Illocigal Command irq */
#define BRM_EOL_IRQ 32 /* End Of List irq */
#define BRM_RT_ILLCMD_IRQ 128 /* RT Illegal Command irq */
#define BRM_IXEQ0_IRQ 256 /* Index Equal Zero irq */
#define BRM_BDRCV_IRQ 512 /* Broadcast Command Received irq */
#define BRM_SUBAD_IRQ 1024 /* Subaddress Accessed irq */
#define BRM_MERR_IRQ 2048 /* Message Error irq */
#define BRM_TAPF_IRQ 8192 /* Terminal Address Parity Fail irq */
#define BRM_WRAPF_IRQ 16384 /* Wrap Fail irq */
#define BRM_DMAF_IRQ 32768 /* DMA Fail irq */
#define BRM_SET_MODE 0
#define BRM_SET_BUS 1
@@ -155,32 +154,31 @@ struct bc_msg {
#define BRM_TX_BLOCK 7
#define BRM_RX_BLOCK 8
#define BRM_DO_LIST 10
#define BRM_LIST_DONE 11
#define BRM_DO_LIST 10
#define BRM_LIST_DONE 11
#define BRM_CLR_STATUS 12
#define BRM_GET_STATUS 13
#define BRM_SET_EVENTID 14
#define GET_ERROR_DESCRIPTOR(event_in) (event_in>>16)
#define GET_ERROR_DESCRIPTOR( event_in ) ( event_in >> 16 )
#define BRM_MODE_BC 0x0
#define BRM_MODE_RT 0x1
#define BRM_MODE_BM 0x2
#define BRM_MODE_BC 0x0
#define BRM_MODE_RT 0x1
#define BRM_MODE_BM 0x2
#define BRM_MODE_BM_RT 0x3 /* both RT and BM */
#define BRM_FREQ_12MHZ 0
#define BRM_FREQ_16MHZ 1
#define BRM_FREQ_20MHZ 2
#define BRM_FREQ_24MHZ 3
#define BRM_FREQ_MASK 0x3
#define BRM_FREQ_MASK 0x3
#define CLKDIV_MASK 0xf
#define CLKSEL_MASK 0x7
void b1553brm_register_drv(void);
void b1553brm_register_drv( void );
/* Default initialization of the RT legalization registers. The values in this
* array are written to the registers on boot driver initialization and when
@@ -188,13 +186,13 @@ void b1553brm_register_drv(void);
* update the array first then call ioctl(BRM_SET_MODE) for the changes to have
* an affect. Note that this affects all B1553BRM RTs in the system.
*/
extern unsigned short b1553brm_rt_cmd_legalize[16];
extern unsigned short b1553brm_rt_cmd_legalize[ 16 ];
/* Print information about all BRM devices handled by this driver */
void b1553brm_print(int options);
void b1553brm_print( int options );
/* Print information about one BRM device */
void b1553brm_print_dev(struct drvmgr_dev *dev, int options);
void b1553brm_print_dev( struct drvmgr_dev *dev, int options );
#ifdef __cplusplus
}
@@ -203,4 +201,3 @@ void b1553brm_print_dev(struct drvmgr_dev *dev, int options);
/** @} */
#endif /* __BRM_H__ */
bsps/include/grlib/b1553rt.h
+28 -30
View File
@@ -37,27 +37,26 @@ extern "C" {
#endif
struct rt_reg {
volatile uint32_t stat; /* 0x00 */
volatile uint32_t ctrl; /* 0x04 */
volatile uint32_t vword; /* 0x08 */
volatile uint32_t irq; /* 0x0C */
volatile uint32_t addr; /* 0x10 */
volatile uint32_t ipm; /* 0x14 */
volatile uint32_t stat; /* 0x00 */
volatile uint32_t ctrl; /* 0x04 */
volatile uint32_t vword; /* 0x08 */
volatile uint32_t irq; /* 0x0C */
volatile uint32_t addr; /* 0x10 */
volatile uint32_t ipm; /* 0x14 */
};
struct rt_msg {
unsigned short miw;
unsigned short time;
unsigned short data[32];
unsigned short desc;
unsigned short miw;
unsigned short time;
unsigned short data[ 32 ];
unsigned short desc;
};
#define RT_FREQ_12MHZ 0
#define RT_FREQ_16MHZ 1
#define RT_FREQ_20MHZ 2
#define RT_FREQ_24MHZ 3
#define RT_FREQ_MASK 0x3
#define RT_FREQ_MASK 0x3
/* IOCTLs */
#define RT_SET_ADDR 3
@@ -67,32 +66,31 @@ struct rt_msg {
#define RT_GET_STATUS 13
#define RT_SET_EVENTID 14
#define RT_SET_VECTORW 32
#define RT_SET_VECTORW 32
#define RT_SET_EXTMDATA 33
#define RT_ILLCMD_IRQ 128
#define RT_MERR_IRQ 2048
#define RT_DMAF_IRQ 32768 /* DMA Fail irq */
#define RT_ILLCMD_IRQ 128
#define RT_MERR_IRQ 2048
#define RT_DMAF_IRQ 32768 /* DMA Fail irq */
#define RT_TSW_OK (1<<14)
#define RT_TSW_BUS (1<<13)
#define RT_TSW_BC (1<<12)
#define RT_TSW_LPBKERRB (1<<11)
#define RT_TSW_LPBKERRA (1<<10)
#define RT_TSW_ILL (1<<9)
#define RT_TSW_MEM (1<<8)
#define RT_TSW_MAN (1<<7)
#define RT_TSW_PAR (1<<6)
#define RT_TSW_WC (1<<5)
#define RT_TSW_OK ( 1 << 14 )
#define RT_TSW_BUS ( 1 << 13 )
#define RT_TSW_BC ( 1 << 12 )
#define RT_TSW_LPBKERRB ( 1 << 11 )
#define RT_TSW_LPBKERRA ( 1 << 10 )
#define RT_TSW_ILL ( 1 << 9 )
#define RT_TSW_MEM ( 1 << 8 )
#define RT_TSW_MAN ( 1 << 7 )
#define RT_TSW_PAR ( 1 << 6 )
#define RT_TSW_WC ( 1 << 5 )
void b1553rt_print_dev(struct drvmgr_dev *dev, int options);
void b1553rt_print(int options);
void b1553rt_print_dev( struct drvmgr_dev *dev, int options );
void b1553rt_print( int options );
void b1553rt_register_drv(void);
void b1553rt_register_drv( void );
#ifdef __cplusplus
}
#endif
#endif /* __RT_H__ */
bsps/include/grlib/bspcommon.h
+1 -1
View File
@@ -38,7 +38,7 @@ extern "C" {
#endif
/* Count driver resource array length. Array must be terminated with a NULL */
int get_resarray_count(struct drvmgr_bus_res **array);
int get_resarray_count( struct drvmgr_bus_res **array );
#ifdef __cplusplus
}
bsps/include/grlib/canbtrs.h
+18 -18
View File
@@ -50,21 +50,21 @@ extern "C" {
/* CAN Baud-rate parameters, range of valid parameter values */
struct grlib_canbtrs_ranges {
unsigned int max_scaler;
char has_bpr;
unsigned char divfactor;
unsigned char min_tseg1;
unsigned char max_tseg1;
unsigned char min_tseg2;
unsigned char max_tseg2;
unsigned int max_scaler;
char has_bpr;
unsigned char divfactor;
unsigned char min_tseg1;
unsigned char max_tseg1;
unsigned char min_tseg2;
unsigned char max_tseg2;
};
struct grlib_canbtrs_timing {
unsigned char scaler;
unsigned char ps1;
unsigned char ps2;
unsigned char rsj;
unsigned char bpr;
unsigned char scaler;
unsigned char ps1;
unsigned char ps2;
unsigned char rsj;
unsigned char bpr;
};
/* @brief Calculate CAN baud-rate generation parameters from requested baud-rate
@@ -80,12 +80,12 @@ struct grlib_canbtrs_timing {
* margin from requested baud-rate
*/
int grlib_canbtrs_calc_timing(
unsigned int baud,
unsigned int core_hz,
unsigned int sampl_pt,
struct grlib_canbtrs_ranges *br,
struct grlib_canbtrs_timing *timing
);
unsigned int baud,
unsigned int core_hz,
unsigned int sampl_pt,
struct grlib_canbtrs_ranges *br,
struct grlib_canbtrs_timing *timing
);
#ifdef __cplusplus
}
bsps/include/grlib/canmux.h
+1 -1
View File
@@ -36,7 +36,7 @@ extern "C" {
#endif
/* Driver interface */
int canmux_register(void);
int canmux_register( void );
/* ioctl calls */
#define CANMUX_IOC_BUSA_SATCAN 1
bsps/include/grlib/cons.h
+8 -8
View File
@@ -39,21 +39,21 @@
struct console_dev;
#define CONSOLE_FLAG_SYSCON 0x01
#define CONSOLE_FLAG_SYSCON_GRANT 0x02
#define CONSOLE_FLAG_SYSCON 0x01
#define CONSOLE_FLAG_SYSCON_GRANT 0x02
struct console_dev {
rtems_termios_device_context base;
/* Set CONSOLE_FLAG_SYSCON to request this device to be system console
rtems_termios_device_context base;
/* Set CONSOLE_FLAG_SYSCON to request this device to be system console
* and/or debug console. CONSOLE_FLAG_SYSCON_GRANT will be set on the
* device which was selected as system console.
*/
int flags;
char *fsname; /* File system prefix */
const rtems_termios_device_handler *handler;
int flags;
char *fsname; /* File system prefix */
const rtems_termios_device_handler *handler;
};
extern void console_dev_register(struct console_dev *dev);
extern void console_dev_register( struct console_dev *dev );
#if 0
extern void console_dev_unregister(struct console_dev *dev);
#endif
bsps/include/grlib/debug_defs.h
+21 -8
View File
@@ -39,27 +39,40 @@
extern "C" {
#endif
#ifdef DEBUG
#ifndef DEBUG_FLAGS
#define DEBUG_FLAGS 0
#endif
#define DBG(fmt, args...) do { printk(" : %03d @ %18s()]:" fmt , __LINE__,__FUNCTION__,## args); } while(0)
#define DBG2(fmt) do { printk(" : %03d @ %18s()]:" fmt , __LINE__,__FUNCTION__); } while(0)
#define DBGC(c,fmt, args...) do { if (DEBUG_FLAGS & c) { printk(" : %03d @ %18s()]:" fmt , __LINE__,__FUNCTION__,## args); }} while(0)
#define DBG( fmt, args... ) \
do { \
printk( " : %03d @ %18s()]:" fmt, __LINE__, __FUNCTION__, ##args ); \
} while ( 0 )
#define DBG2( fmt ) \
do { \
printk( " : %03d @ %18s()]:" fmt, __LINE__, __FUNCTION__ ); \
} while ( 0 )
#define DBGC( c, fmt, args... ) \
do { \
if ( DEBUG_FLAGS & c ) { \
printk( " : %03d @ %18s()]:" fmt, __LINE__, __FUNCTION__, ##args ); \
} \
} while ( 0 )
#else
#define DBG(fmt, args...)
#define DBG2(fmt, args...)
#define DBGC(c, fmt, args...)
#define DBG( fmt, args... )
#define DBG2( fmt, args... )
#define DBGC( c, fmt, args... )
#endif
#ifdef DEBUGFUNCS
#define FUNCDBG() do { printk("%s\n\r",__FUNCTION__); } while(0)
#define FUNCDBG() \
do { \
printk( "%s\n\r", __FUNCTION__ ); \
} while ( 0 )
#else
#define FUNCDBG()
#endif
bsps/include/grlib/dsu4-regs.h
+110 -170
View File
@@ -116,17 +116,14 @@ extern "C" {
*/
#define DSU4_DTTC_TIMETAG_SHIFT 0
#define DSU4_DTTC_TIMETAG_MASK 0xffffffffU
#define DSU4_DTTC_TIMETAG_MASK 0xffffffffU
#define DSU4_DTTC_TIMETAG_GET( _reg ) \
( ( ( _reg ) & DSU4_DTTC_TIMETAG_MASK ) >> \
DSU4_DTTC_TIMETAG_SHIFT )
#define DSU4_DTTC_TIMETAG_SET( _reg, _val ) \
( ( ( _reg ) & DSU4_DTTC_TIMETAG_MASK ) >> DSU4_DTTC_TIMETAG_SHIFT )
#define DSU4_DTTC_TIMETAG_SET( _reg, _val ) \
( ( ( _reg ) & ~DSU4_DTTC_TIMETAG_MASK ) | \
( ( ( _val ) << DSU4_DTTC_TIMETAG_SHIFT ) & \
DSU4_DTTC_TIMETAG_MASK ) )
( ( ( _val ) << DSU4_DTTC_TIMETAG_SHIFT ) & DSU4_DTTC_TIMETAG_MASK ) )
#define DSU4_DTTC_TIMETAG( _val ) \
( ( ( _val ) << DSU4_DTTC_TIMETAG_SHIFT ) & \
DSU4_DTTC_TIMETAG_MASK )
( ( ( _val ) << DSU4_DTTC_TIMETAG_SHIFT ) & DSU4_DTTC_TIMETAG_MASK )
/** @} */
@@ -139,30 +136,24 @@ extern "C" {
*/
#define DSU4_BRSS_SS_3_0_SHIFT 16
#define DSU4_BRSS_SS_3_0_MASK 0xf0000U
#define DSU4_BRSS_SS_3_0_MASK 0xf0000U
#define DSU4_BRSS_SS_3_0_GET( _reg ) \
( ( ( _reg ) & DSU4_BRSS_SS_3_0_MASK ) >> \
DSU4_BRSS_SS_3_0_SHIFT )
#define DSU4_BRSS_SS_3_0_SET( _reg, _val ) \
( ( ( _reg ) & DSU4_BRSS_SS_3_0_MASK ) >> DSU4_BRSS_SS_3_0_SHIFT )
#define DSU4_BRSS_SS_3_0_SET( _reg, _val ) \
( ( ( _reg ) & ~DSU4_BRSS_SS_3_0_MASK ) | \
( ( ( _val ) << DSU4_BRSS_SS_3_0_SHIFT ) & \
DSU4_BRSS_SS_3_0_MASK ) )
( ( ( _val ) << DSU4_BRSS_SS_3_0_SHIFT ) & DSU4_BRSS_SS_3_0_MASK ) )
#define DSU4_BRSS_SS_3_0( _val ) \
( ( ( _val ) << DSU4_BRSS_SS_3_0_SHIFT ) & \
DSU4_BRSS_SS_3_0_MASK )
( ( ( _val ) << DSU4_BRSS_SS_3_0_SHIFT ) & DSU4_BRSS_SS_3_0_MASK )
#define DSU4_BRSS_BN_3_0_SHIFT 0
#define DSU4_BRSS_BN_3_0_MASK 0xfU
#define DSU4_BRSS_BN_3_0_MASK 0xfU
#define DSU4_BRSS_BN_3_0_GET( _reg ) \
( ( ( _reg ) & DSU4_BRSS_BN_3_0_MASK ) >> \
DSU4_BRSS_BN_3_0_SHIFT )
#define DSU4_BRSS_BN_3_0_SET( _reg, _val ) \
( ( ( _reg ) & DSU4_BRSS_BN_3_0_MASK ) >> DSU4_BRSS_BN_3_0_SHIFT )
#define DSU4_BRSS_BN_3_0_SET( _reg, _val ) \
( ( ( _reg ) & ~DSU4_BRSS_BN_3_0_MASK ) | \
( ( ( _val ) << DSU4_BRSS_BN_3_0_SHIFT ) & \
DSU4_BRSS_BN_3_0_MASK ) )
( ( ( _val ) << DSU4_BRSS_BN_3_0_SHIFT ) & DSU4_BRSS_BN_3_0_MASK ) )
#define DSU4_BRSS_BN_3_0( _val ) \
( ( ( _val ) << DSU4_BRSS_BN_3_0_SHIFT ) & \
DSU4_BRSS_BN_3_0_MASK )
( ( ( _val ) << DSU4_BRSS_BN_3_0_SHIFT ) & DSU4_BRSS_BN_3_0_MASK )
/** @} */
@@ -175,30 +166,24 @@ extern "C" {
*/
#define DSU4_DBGM_DM_3_0_SHIFT 16
#define DSU4_DBGM_DM_3_0_MASK 0xf0000U
#define DSU4_DBGM_DM_3_0_MASK 0xf0000U
#define DSU4_DBGM_DM_3_0_GET( _reg ) \
( ( ( _reg ) & DSU4_DBGM_DM_3_0_MASK ) >> \
DSU4_DBGM_DM_3_0_SHIFT )
#define DSU4_DBGM_DM_3_0_SET( _reg, _val ) \
( ( ( _reg ) & DSU4_DBGM_DM_3_0_MASK ) >> DSU4_DBGM_DM_3_0_SHIFT )
#define DSU4_DBGM_DM_3_0_SET( _reg, _val ) \
( ( ( _reg ) & ~DSU4_DBGM_DM_3_0_MASK ) | \
( ( ( _val ) << DSU4_DBGM_DM_3_0_SHIFT ) & \
DSU4_DBGM_DM_3_0_MASK ) )
( ( ( _val ) << DSU4_DBGM_DM_3_0_SHIFT ) & DSU4_DBGM_DM_3_0_MASK ) )
#define DSU4_DBGM_DM_3_0( _val ) \
( ( ( _val ) << DSU4_DBGM_DM_3_0_SHIFT ) & \
DSU4_DBGM_DM_3_0_MASK )
( ( ( _val ) << DSU4_DBGM_DM_3_0_SHIFT ) & DSU4_DBGM_DM_3_0_MASK )
#define DSU4_DBGM_ED_3_0_SHIFT 0
#define DSU4_DBGM_ED_3_0_MASK 0xfU
#define DSU4_DBGM_ED_3_0_MASK 0xfU
#define DSU4_DBGM_ED_3_0_GET( _reg ) \
( ( ( _reg ) & DSU4_DBGM_ED_3_0_MASK ) >> \
DSU4_DBGM_ED_3_0_SHIFT )
#define DSU4_DBGM_ED_3_0_SET( _reg, _val ) \
( ( ( _reg ) & DSU4_DBGM_ED_3_0_MASK ) >> DSU4_DBGM_ED_3_0_SHIFT )
#define DSU4_DBGM_ED_3_0_SET( _reg, _val ) \
( ( ( _reg ) & ~DSU4_DBGM_ED_3_0_MASK ) | \
( ( ( _val ) << DSU4_DBGM_ED_3_0_SHIFT ) & \
DSU4_DBGM_ED_3_0_MASK ) )
( ( ( _val ) << DSU4_DBGM_ED_3_0_SHIFT ) & DSU4_DBGM_ED_3_0_MASK ) )
#define DSU4_DBGM_ED_3_0( _val ) \
( ( ( _val ) << DSU4_DBGM_ED_3_0_SHIFT ) & \
DSU4_DBGM_ED_3_0_MASK )
( ( ( _val ) << DSU4_DBGM_ED_3_0_SHIFT ) & DSU4_DBGM_ED_3_0_MASK )
/** @} */
@@ -213,17 +198,14 @@ extern "C" {
#define DSU4_DTR_EM 0x1000U
#define DSU4_DTR_TRAPTYPE_SHIFT 4
#define DSU4_DTR_TRAPTYPE_MASK 0xff0U
#define DSU4_DTR_TRAPTYPE_MASK 0xff0U
#define DSU4_DTR_TRAPTYPE_GET( _reg ) \
( ( ( _reg ) & DSU4_DTR_TRAPTYPE_MASK ) >> \
DSU4_DTR_TRAPTYPE_SHIFT )
#define DSU4_DTR_TRAPTYPE_SET( _reg, _val ) \
( ( ( _reg ) & DSU4_DTR_TRAPTYPE_MASK ) >> DSU4_DTR_TRAPTYPE_SHIFT )
#define DSU4_DTR_TRAPTYPE_SET( _reg, _val ) \
( ( ( _reg ) & ~DSU4_DTR_TRAPTYPE_MASK ) | \
( ( ( _val ) << DSU4_DTR_TRAPTYPE_SHIFT ) & \
DSU4_DTR_TRAPTYPE_MASK ) )
( ( ( _val ) << DSU4_DTR_TRAPTYPE_SHIFT ) & DSU4_DTR_TRAPTYPE_MASK ) )
#define DSU4_DTR_TRAPTYPE( _val ) \
( ( ( _val ) << DSU4_DTR_TRAPTYPE_SHIFT ) & \
DSU4_DTR_TRAPTYPE_MASK )
( ( ( _val ) << DSU4_DTR_TRAPTYPE_SHIFT ) & DSU4_DTR_TRAPTYPE_MASK )
/** @} */
@@ -236,17 +218,14 @@ extern "C" {
*/
#define DSU4_DASI_ASI_SHIFT 0
#define DSU4_DASI_ASI_MASK 0xffU
#define DSU4_DASI_ASI_MASK 0xffU
#define DSU4_DASI_ASI_GET( _reg ) \
( ( ( _reg ) & DSU4_DASI_ASI_MASK ) >> \
DSU4_DASI_ASI_SHIFT )
#define DSU4_DASI_ASI_SET( _reg, _val ) \
( ( ( _reg ) & DSU4_DASI_ASI_MASK ) >> DSU4_DASI_ASI_SHIFT )
#define DSU4_DASI_ASI_SET( _reg, _val ) \
( ( ( _reg ) & ~DSU4_DASI_ASI_MASK ) | \
( ( ( _val ) << DSU4_DASI_ASI_SHIFT ) & \
DSU4_DASI_ASI_MASK ) )
( ( ( _val ) << DSU4_DASI_ASI_SHIFT ) & DSU4_DASI_ASI_MASK ) )
#define DSU4_DASI_ASI( _val ) \
( ( ( _val ) << DSU4_DASI_ASI_SHIFT ) & \
DSU4_DASI_ASI_MASK )
( ( ( _val ) << DSU4_DASI_ASI_SHIFT ) & DSU4_DASI_ASI_MASK )
/** @} */
@@ -259,17 +238,14 @@ extern "C" {
*/
#define DSU4_ATBC_DCNT_SHIFT 16
#define DSU4_ATBC_DCNT_MASK 0xff0000U
#define DSU4_ATBC_DCNT_MASK 0xff0000U
#define DSU4_ATBC_DCNT_GET( _reg ) \
( ( ( _reg ) & DSU4_ATBC_DCNT_MASK ) >> \
DSU4_ATBC_DCNT_SHIFT )
#define DSU4_ATBC_DCNT_SET( _reg, _val ) \
( ( ( _reg ) & DSU4_ATBC_DCNT_MASK ) >> DSU4_ATBC_DCNT_SHIFT )
#define DSU4_ATBC_DCNT_SET( _reg, _val ) \
( ( ( _reg ) & ~DSU4_ATBC_DCNT_MASK ) | \
( ( ( _val ) << DSU4_ATBC_DCNT_SHIFT ) & \
DSU4_ATBC_DCNT_MASK ) )
( ( ( _val ) << DSU4_ATBC_DCNT_SHIFT ) & DSU4_ATBC_DCNT_MASK ) )
#define DSU4_ATBC_DCNT( _val ) \
( ( ( _val ) << DSU4_ATBC_DCNT_SHIFT ) & \
DSU4_ATBC_DCNT_MASK )
( ( ( _val ) << DSU4_ATBC_DCNT_SHIFT ) & DSU4_ATBC_DCNT_MASK )
#define DSU4_ATBC_DF 0x100U
@@ -280,17 +256,14 @@ extern "C" {
#define DSU4_ATBC_TF 0x20U
#define DSU4_ATBC_BW_SHIFT 3
#define DSU4_ATBC_BW_MASK 0x18U
#define DSU4_ATBC_BW_MASK 0x18U
#define DSU4_ATBC_BW_GET( _reg ) \
( ( ( _reg ) & DSU4_ATBC_BW_MASK ) >> \
DSU4_ATBC_BW_SHIFT )
#define DSU4_ATBC_BW_SET( _reg, _val ) \
( ( ( _reg ) & DSU4_ATBC_BW_MASK ) >> DSU4_ATBC_BW_SHIFT )
#define DSU4_ATBC_BW_SET( _reg, _val ) \
( ( ( _reg ) & ~DSU4_ATBC_BW_MASK ) | \
( ( ( _val ) << DSU4_ATBC_BW_SHIFT ) & \
DSU4_ATBC_BW_MASK ) )
( ( ( _val ) << DSU4_ATBC_BW_SHIFT ) & DSU4_ATBC_BW_MASK ) )
#define DSU4_ATBC_BW( _val ) \
( ( ( _val ) << DSU4_ATBC_BW_SHIFT ) & \
DSU4_ATBC_BW_MASK )
( ( ( _val ) << DSU4_ATBC_BW_SHIFT ) & DSU4_ATBC_BW_MASK )
#define DSU4_ATBC_BR 0x4U
@@ -309,17 +282,14 @@ extern "C" {
*/
#define DSU4_ATBI_INDEX_SHIFT 4
#define DSU4_ATBI_INDEX_MASK 0xff0U
#define DSU4_ATBI_INDEX_MASK 0xff0U
#define DSU4_ATBI_INDEX_GET( _reg ) \
( ( ( _reg ) & DSU4_ATBI_INDEX_MASK ) >> \
DSU4_ATBI_INDEX_SHIFT )
#define DSU4_ATBI_INDEX_SET( _reg, _val ) \
( ( ( _reg ) & DSU4_ATBI_INDEX_MASK ) >> DSU4_ATBI_INDEX_SHIFT )
#define DSU4_ATBI_INDEX_SET( _reg, _val ) \
( ( ( _reg ) & ~DSU4_ATBI_INDEX_MASK ) | \
( ( ( _val ) << DSU4_ATBI_INDEX_SHIFT ) & \
DSU4_ATBI_INDEX_MASK ) )
( ( ( _val ) << DSU4_ATBI_INDEX_SHIFT ) & DSU4_ATBI_INDEX_MASK ) )
#define DSU4_ATBI_INDEX( _val ) \
( ( ( _val ) << DSU4_ATBI_INDEX_SHIFT ) & \
DSU4_ATBI_INDEX_MASK )
( ( ( _val ) << DSU4_ATBI_INDEX_SHIFT ) & DSU4_ATBI_INDEX_MASK )
/** @} */
@@ -333,30 +303,24 @@ extern "C" {
*/
#define DSU4_ATBFC_WPF_SHIFT 12
#define DSU4_ATBFC_WPF_MASK 0x3000U
#define DSU4_ATBFC_WPF_MASK 0x3000U
#define DSU4_ATBFC_WPF_GET( _reg ) \
( ( ( _reg ) & DSU4_ATBFC_WPF_MASK ) >> \
DSU4_ATBFC_WPF_SHIFT )
#define DSU4_ATBFC_WPF_SET( _reg, _val ) \
( ( ( _reg ) & DSU4_ATBFC_WPF_MASK ) >> DSU4_ATBFC_WPF_SHIFT )
#define DSU4_ATBFC_WPF_SET( _reg, _val ) \
( ( ( _reg ) & ~DSU4_ATBFC_WPF_MASK ) | \
( ( ( _val ) << DSU4_ATBFC_WPF_SHIFT ) & \
DSU4_ATBFC_WPF_MASK ) )
( ( ( _val ) << DSU4_ATBFC_WPF_SHIFT ) & DSU4_ATBFC_WPF_MASK ) )
#define DSU4_ATBFC_WPF( _val ) \
( ( ( _val ) << DSU4_ATBFC_WPF_SHIFT ) & \
DSU4_ATBFC_WPF_MASK )
( ( ( _val ) << DSU4_ATBFC_WPF_SHIFT ) & DSU4_ATBFC_WPF_MASK )
#define DSU4_ATBFC_BPF_SHIFT 8
#define DSU4_ATBFC_BPF_MASK 0x300U
#define DSU4_ATBFC_BPF_MASK 0x300U
#define DSU4_ATBFC_BPF_GET( _reg ) \
( ( ( _reg ) & DSU4_ATBFC_BPF_MASK ) >> \
DSU4_ATBFC_BPF_SHIFT )
#define DSU4_ATBFC_BPF_SET( _reg, _val ) \
( ( ( _reg ) & DSU4_ATBFC_BPF_MASK ) >> DSU4_ATBFC_BPF_SHIFT )
#define DSU4_ATBFC_BPF_SET( _reg, _val ) \
( ( ( _reg ) & ~DSU4_ATBFC_BPF_MASK ) | \
( ( ( _val ) << DSU4_ATBFC_BPF_SHIFT ) & \
DSU4_ATBFC_BPF_MASK ) )
( ( ( _val ) << DSU4_ATBFC_BPF_SHIFT ) & DSU4_ATBFC_BPF_MASK ) )
#define DSU4_ATBFC_BPF( _val ) \
( ( ( _val ) << DSU4_ATBFC_BPF_SHIFT ) & \
DSU4_ATBFC_BPF_MASK )
( ( ( _val ) << DSU4_ATBFC_BPF_SHIFT ) & DSU4_ATBFC_BPF_MASK )
#define DSU4_ATBFC_PF 0x8U
@@ -378,30 +342,26 @@ extern "C" {
*/
#define DSU4_ATBFM_SMASK_15_0_SHIFT 16
#define DSU4_ATBFM_SMASK_15_0_MASK 0xffff0000U
#define DSU4_ATBFM_SMASK_15_0_MASK 0xffff0000U
#define DSU4_ATBFM_SMASK_15_0_GET( _reg ) \
( ( ( _reg ) & DSU4_ATBFM_SMASK_15_0_MASK ) >> \
DSU4_ATBFM_SMASK_15_0_SHIFT )
#define DSU4_ATBFM_SMASK_15_0_SET( _reg, _val ) \
( ( ( _reg ) & ~DSU4_ATBFM_SMASK_15_0_MASK ) | \
( ( ( _reg ) & DSU4_ATBFM_SMASK_15_0_MASK ) >> DSU4_ATBFM_SMASK_15_0_SHIFT )
#define DSU4_ATBFM_SMASK_15_0_SET( _reg, _val ) \
( ( ( _reg ) & ~DSU4_ATBFM_SMASK_15_0_MASK ) | \
( ( ( _val ) << DSU4_ATBFM_SMASK_15_0_SHIFT ) & \
DSU4_ATBFM_SMASK_15_0_MASK ) )
#define DSU4_ATBFM_SMASK_15_0( _val ) \
( ( ( _val ) << DSU4_ATBFM_SMASK_15_0_SHIFT ) & \
DSU4_ATBFM_SMASK_15_0_MASK )
( ( ( _val ) << DSU4_ATBFM_SMASK_15_0_SHIFT ) & DSU4_ATBFM_SMASK_15_0_MASK )
#define DSU4_ATBFM_MMASK_15_0_SHIFT 0
#define DSU4_ATBFM_MMASK_15_0_MASK 0xffffU
#define DSU4_ATBFM_MMASK_15_0_MASK 0xffffU
#define DSU4_ATBFM_MMASK_15_0_GET( _reg ) \
( ( ( _reg ) & DSU4_ATBFM_MMASK_15_0_MASK ) >> \
DSU4_ATBFM_MMASK_15_0_SHIFT )
#define DSU4_ATBFM_MMASK_15_0_SET( _reg, _val ) \
( ( ( _reg ) & ~DSU4_ATBFM_MMASK_15_0_MASK ) | \
( ( ( _reg ) & DSU4_ATBFM_MMASK_15_0_MASK ) >> DSU4_ATBFM_MMASK_15_0_SHIFT )
#define DSU4_ATBFM_MMASK_15_0_SET( _reg, _val ) \
( ( ( _reg ) & ~DSU4_ATBFM_MMASK_15_0_MASK ) | \
( ( ( _val ) << DSU4_ATBFM_MMASK_15_0_SHIFT ) & \
DSU4_ATBFM_MMASK_15_0_MASK ) )
#define DSU4_ATBFM_MMASK_15_0( _val ) \
( ( ( _val ) << DSU4_ATBFM_MMASK_15_0_SHIFT ) & \
DSU4_ATBFM_MMASK_15_0_MASK )
( ( ( _val ) << DSU4_ATBFM_MMASK_15_0_SHIFT ) & DSU4_ATBFM_MMASK_15_0_MASK )
/** @} */
@@ -415,17 +375,15 @@ extern "C" {
*/
#define DSU4_ATBBA_BADDR_31_2_SHIFT 2
#define DSU4_ATBBA_BADDR_31_2_MASK 0xfffffffcU
#define DSU4_ATBBA_BADDR_31_2_MASK 0xfffffffcU
#define DSU4_ATBBA_BADDR_31_2_GET( _reg ) \
( ( ( _reg ) & DSU4_ATBBA_BADDR_31_2_MASK ) >> \
DSU4_ATBBA_BADDR_31_2_SHIFT )
#define DSU4_ATBBA_BADDR_31_2_SET( _reg, _val ) \
( ( ( _reg ) & ~DSU4_ATBBA_BADDR_31_2_MASK ) | \
( ( ( _reg ) & DSU4_ATBBA_BADDR_31_2_MASK ) >> DSU4_ATBBA_BADDR_31_2_SHIFT )
#define DSU4_ATBBA_BADDR_31_2_SET( _reg, _val ) \
( ( ( _reg ) & ~DSU4_ATBBA_BADDR_31_2_MASK ) | \
( ( ( _val ) << DSU4_ATBBA_BADDR_31_2_SHIFT ) & \
DSU4_ATBBA_BADDR_31_2_MASK ) )
#define DSU4_ATBBA_BADDR_31_2( _val ) \
( ( ( _val ) << DSU4_ATBBA_BADDR_31_2_SHIFT ) & \
DSU4_ATBBA_BADDR_31_2_MASK )
( ( ( _val ) << DSU4_ATBBA_BADDR_31_2_SHIFT ) & DSU4_ATBBA_BADDR_31_2_MASK )
/** @} */
@@ -439,17 +397,15 @@ extern "C" {
*/
#define DSU4_ATBBM_BMASK_31_2_SHIFT 2
#define DSU4_ATBBM_BMASK_31_2_MASK 0xfffffffcU
#define DSU4_ATBBM_BMASK_31_2_MASK 0xfffffffcU
#define DSU4_ATBBM_BMASK_31_2_GET( _reg ) \
( ( ( _reg ) & DSU4_ATBBM_BMASK_31_2_MASK ) >> \
DSU4_ATBBM_BMASK_31_2_SHIFT )
#define DSU4_ATBBM_BMASK_31_2_SET( _reg, _val ) \
( ( ( _reg ) & ~DSU4_ATBBM_BMASK_31_2_MASK ) | \
( ( ( _reg ) & DSU4_ATBBM_BMASK_31_2_MASK ) >> DSU4_ATBBM_BMASK_31_2_SHIFT )
#define DSU4_ATBBM_BMASK_31_2_SET( _reg, _val ) \
( ( ( _reg ) & ~DSU4_ATBBM_BMASK_31_2_MASK ) | \
( ( ( _val ) << DSU4_ATBBM_BMASK_31_2_SHIFT ) & \
DSU4_ATBBM_BMASK_31_2_MASK ) )
#define DSU4_ATBBM_BMASK_31_2( _val ) \
( ( ( _val ) << DSU4_ATBBM_BMASK_31_2_SHIFT ) & \
DSU4_ATBBM_BMASK_31_2_MASK )
( ( ( _val ) << DSU4_ATBBM_BMASK_31_2_SHIFT ) & DSU4_ATBBM_BMASK_31_2_MASK )
#define DSU4_ATBBM_LD 0x2U
@@ -472,17 +428,15 @@ extern "C" {
#define DSU4_ICNT_PE 0x20000000U
#define DSU4_ICNT_ICOUNT_28_0_SHIFT 0
#define DSU4_ICNT_ICOUNT_28_0_MASK 0x1fffffffU
#define DSU4_ICNT_ICOUNT_28_0_MASK 0x1fffffffU
#define DSU4_ICNT_ICOUNT_28_0_GET( _reg ) \
( ( ( _reg ) & DSU4_ICNT_ICOUNT_28_0_MASK ) >> \
DSU4_ICNT_ICOUNT_28_0_SHIFT )
#define DSU4_ICNT_ICOUNT_28_0_SET( _reg, _val ) \
( ( ( _reg ) & ~DSU4_ICNT_ICOUNT_28_0_MASK ) | \
( ( ( _reg ) & DSU4_ICNT_ICOUNT_28_0_MASK ) >> DSU4_ICNT_ICOUNT_28_0_SHIFT )
#define DSU4_ICNT_ICOUNT_28_0_SET( _reg, _val ) \
( ( ( _reg ) & ~DSU4_ICNT_ICOUNT_28_0_MASK ) | \
( ( ( _val ) << DSU4_ICNT_ICOUNT_28_0_SHIFT ) & \
DSU4_ICNT_ICOUNT_28_0_MASK ) )
#define DSU4_ICNT_ICOUNT_28_0( _val ) \
( ( ( _val ) << DSU4_ICNT_ICOUNT_28_0_SHIFT ) & \
DSU4_ICNT_ICOUNT_28_0_MASK )
( ( ( _val ) << DSU4_ICNT_ICOUNT_28_0_SHIFT ) & DSU4_ICNT_ICOUNT_28_0_MASK )
/** @} */
@@ -518,17 +472,14 @@ extern "C" {
*/
#define DSU4_AHBWPD_DATA_SHIFT 0
#define DSU4_AHBWPD_DATA_MASK 0xffffffffU
#define DSU4_AHBWPD_DATA_MASK 0xffffffffU
#define DSU4_AHBWPD_DATA_GET( _reg ) \
( ( ( _reg ) & DSU4_AHBWPD_DATA_MASK ) >> \
DSU4_AHBWPD_DATA_SHIFT )
#define DSU4_AHBWPD_DATA_SET( _reg, _val ) \
( ( ( _reg ) & DSU4_AHBWPD_DATA_MASK ) >> DSU4_AHBWPD_DATA_SHIFT )
#define DSU4_AHBWPD_DATA_SET( _reg, _val ) \
( ( ( _reg ) & ~DSU4_AHBWPD_DATA_MASK ) | \
( ( ( _val ) << DSU4_AHBWPD_DATA_SHIFT ) & \
DSU4_AHBWPD_DATA_MASK ) )
( ( ( _val ) << DSU4_AHBWPD_DATA_SHIFT ) & DSU4_AHBWPD_DATA_MASK ) )
#define DSU4_AHBWPD_DATA( _val ) \
( ( ( _val ) << DSU4_AHBWPD_DATA_SHIFT ) & \
DSU4_AHBWPD_DATA_MASK )
( ( ( _val ) << DSU4_AHBWPD_DATA_SHIFT ) & DSU4_AHBWPD_DATA_MASK )
/** @} */
@@ -541,17 +492,14 @@ extern "C" {
*/
#define DSU4_AHBWPM_MASK_SHIFT 0
#define DSU4_AHBWPM_MASK_MASK 0xffffffffU
#define DSU4_AHBWPM_MASK_MASK 0xffffffffU
#define DSU4_AHBWPM_MASK_GET( _reg ) \
( ( ( _reg ) & DSU4_AHBWPM_MASK_MASK ) >> \
DSU4_AHBWPM_MASK_SHIFT )
#define DSU4_AHBWPM_MASK_SET( _reg, _val ) \
( ( ( _reg ) & DSU4_AHBWPM_MASK_MASK ) >> DSU4_AHBWPM_MASK_SHIFT )
#define DSU4_AHBWPM_MASK_SET( _reg, _val ) \
( ( ( _reg ) & ~DSU4_AHBWPM_MASK_MASK ) | \
( ( ( _val ) << DSU4_AHBWPM_MASK_SHIFT ) & \
DSU4_AHBWPM_MASK_MASK ) )
( ( ( _val ) << DSU4_AHBWPM_MASK_SHIFT ) & DSU4_AHBWPM_MASK_MASK ) )
#define DSU4_AHBWPM_MASK( _val ) \
( ( ( _val ) << DSU4_AHBWPM_MASK_SHIFT ) & \
DSU4_AHBWPM_MASK_MASK )
( ( ( _val ) << DSU4_AHBWPM_MASK_SHIFT ) & DSU4_AHBWPM_MASK_MASK )
/** @} */
@@ -565,30 +513,25 @@ extern "C" {
*/
#define DSU4_ITBC0_TFILT_SHIFT 28
#define DSU4_ITBC0_TFILT_MASK 0xf0000000U
#define DSU4_ITBC0_TFILT_MASK 0xf0000000U
#define DSU4_ITBC0_TFILT_GET( _reg ) \
( ( ( _reg ) & DSU4_ITBC0_TFILT_MASK ) >> \
DSU4_ITBC0_TFILT_SHIFT )
#define DSU4_ITBC0_TFILT_SET( _reg, _val ) \
( ( ( _reg ) & DSU4_ITBC0_TFILT_MASK ) >> DSU4_ITBC0_TFILT_SHIFT )
#define DSU4_ITBC0_TFILT_SET( _reg, _val ) \
( ( ( _reg ) & ~DSU4_ITBC0_TFILT_MASK ) | \
( ( ( _val ) << DSU4_ITBC0_TFILT_SHIFT ) & \
DSU4_ITBC0_TFILT_MASK ) )
( ( ( _val ) << DSU4_ITBC0_TFILT_SHIFT ) & DSU4_ITBC0_TFILT_MASK ) )
#define DSU4_ITBC0_TFILT( _val ) \
( ( ( _val ) << DSU4_ITBC0_TFILT_SHIFT ) & \
DSU4_ITBC0_TFILT_MASK )
( ( ( _val ) << DSU4_ITBC0_TFILT_SHIFT ) & DSU4_ITBC0_TFILT_MASK )
#define DSU4_ITBC0_ITPOINTER_SHIFT 0
#define DSU4_ITBC0_ITPOINTER_MASK 0xffffU
#define DSU4_ITBC0_ITPOINTER_MASK 0xffffU
#define DSU4_ITBC0_ITPOINTER_GET( _reg ) \
( ( ( _reg ) & DSU4_ITBC0_ITPOINTER_MASK ) >> \
DSU4_ITBC0_ITPOINTER_SHIFT )
#define DSU4_ITBC0_ITPOINTER_SET( _reg, _val ) \
( ( ( _reg ) & ~DSU4_ITBC0_ITPOINTER_MASK ) | \
( ( ( _reg ) & DSU4_ITBC0_ITPOINTER_MASK ) >> DSU4_ITBC0_ITPOINTER_SHIFT )
#define DSU4_ITBC0_ITPOINTER_SET( _reg, _val ) \
( ( ( _reg ) & ~DSU4_ITBC0_ITPOINTER_MASK ) | \
( ( ( _val ) << DSU4_ITBC0_ITPOINTER_SHIFT ) & \
DSU4_ITBC0_ITPOINTER_MASK ) )
#define DSU4_ITBC0_ITPOINTER( _val ) \
( ( ( _val ) << DSU4_ITBC0_ITPOINTER_SHIFT ) & \
DSU4_ITBC0_ITPOINTER_MASK )
( ( ( _val ) << DSU4_ITBC0_ITPOINTER_SHIFT ) & DSU4_ITBC0_ITPOINTER_MASK )
/** @} */
@@ -604,17 +547,14 @@ extern "C" {
#define DSU4_ITBC1_WO 0x8000000U
#define DSU4_ITBC1_TLIM_SHIFT 24
#define DSU4_ITBC1_TLIM_MASK 0x7000000U
#define DSU4_ITBC1_TLIM_MASK 0x7000000U
#define DSU4_ITBC1_TLIM_GET( _reg ) \
( ( ( _reg ) & DSU4_ITBC1_TLIM_MASK ) >> \
DSU4_ITBC1_TLIM_SHIFT )
#define DSU4_ITBC1_TLIM_SET( _reg, _val ) \
( ( ( _reg ) & DSU4_ITBC1_TLIM_MASK ) >> DSU4_ITBC1_TLIM_SHIFT )
#define DSU4_ITBC1_TLIM_SET( _reg, _val ) \
( ( ( _reg ) & ~DSU4_ITBC1_TLIM_MASK ) | \
( ( ( _val ) << DSU4_ITBC1_TLIM_SHIFT ) & \
DSU4_ITBC1_TLIM_MASK ) )
( ( ( _val ) << DSU4_ITBC1_TLIM_SHIFT ) & DSU4_ITBC1_TLIM_MASK ) )
#define DSU4_ITBC1_TLIM( _val ) \
( ( ( _val ) << DSU4_ITBC1_TLIM_SHIFT ) & \
DSU4_ITBC1_TLIM_MASK )
( ( ( _val ) << DSU4_ITBC1_TLIM_SHIFT ) & DSU4_ITBC1_TLIM_MASK )
#define DSU4_ITBC1_TOV 0x800000U
bsps/include/grlib/ftmctrl-regs.h
+55 -64
View File
@@ -87,32 +87,30 @@ extern "C" {
#define FTMCTRL_MCFG1_ABRDY 0x20000000U
#define FTMCTRL_MCFG1_IOBUSW_SHIFT 27
#define FTMCTRL_MCFG1_IOBUSW_MASK 0x18000000U
#define FTMCTRL_MCFG1_IOBUSW_MASK 0x18000000U
#define FTMCTRL_MCFG1_IOBUSW_GET( _reg ) \
( ( ( _reg ) & FTMCTRL_MCFG1_IOBUSW_MASK ) >> \
FTMCTRL_MCFG1_IOBUSW_SHIFT )
#define FTMCTRL_MCFG1_IOBUSW_SET( _reg, _val ) \
( ( ( _reg ) & ~FTMCTRL_MCFG1_IOBUSW_MASK ) | \
( ( ( _reg ) & FTMCTRL_MCFG1_IOBUSW_MASK ) >> FTMCTRL_MCFG1_IOBUSW_SHIFT )
#define FTMCTRL_MCFG1_IOBUSW_SET( _reg, _val ) \
( ( ( _reg ) & ~FTMCTRL_MCFG1_IOBUSW_MASK ) | \
( ( ( _val ) << FTMCTRL_MCFG1_IOBUSW_SHIFT ) & \
FTMCTRL_MCFG1_IOBUSW_MASK ) )
#define FTMCTRL_MCFG1_IOBUSW( _val ) \
( ( ( _val ) << FTMCTRL_MCFG1_IOBUSW_SHIFT ) & \
FTMCTRL_MCFG1_IOBUSW_MASK )
( ( ( _val ) << FTMCTRL_MCFG1_IOBUSW_SHIFT ) & FTMCTRL_MCFG1_IOBUSW_MASK )
#define FTMCTRL_MCFG1_IBRDY 0x4000000U
#define FTMCTRL_MCFG1_BEXCN 0x2000000U
#define FTMCTRL_MCFG1_IO_WAITSTATES_SHIFT 20
#define FTMCTRL_MCFG1_IO_WAITSTATES_MASK 0xf00000U
#define FTMCTRL_MCFG1_IO_WAITSTATES_GET( _reg ) \
#define FTMCTRL_MCFG1_IO_WAITSTATES_MASK 0xf00000U
#define FTMCTRL_MCFG1_IO_WAITSTATES_GET( _reg ) \
( ( ( _reg ) & FTMCTRL_MCFG1_IO_WAITSTATES_MASK ) >> \
FTMCTRL_MCFG1_IO_WAITSTATES_SHIFT )
#define FTMCTRL_MCFG1_IO_WAITSTATES_SET( _reg, _val ) \
( ( ( _reg ) & ~FTMCTRL_MCFG1_IO_WAITSTATES_MASK ) | \
#define FTMCTRL_MCFG1_IO_WAITSTATES_SET( _reg, _val ) \
( ( ( _reg ) & ~FTMCTRL_MCFG1_IO_WAITSTATES_MASK ) | \
( ( ( _val ) << FTMCTRL_MCFG1_IO_WAITSTATES_SHIFT ) & \
FTMCTRL_MCFG1_IO_WAITSTATES_MASK ) )
#define FTMCTRL_MCFG1_IO_WAITSTATES( _val ) \
#define FTMCTRL_MCFG1_IO_WAITSTATES( _val ) \
( ( ( _val ) << FTMCTRL_MCFG1_IO_WAITSTATES_SHIFT ) & \
FTMCTRL_MCFG1_IO_WAITSTATES_MASK )
@@ -121,56 +119,56 @@ extern "C" {
#define FTMCTRL_MCFG1_R 0x40000U
#define FTMCTRL_MCFG1_ROMBANKSZ_SHIFT 14
#define FTMCTRL_MCFG1_ROMBANKSZ_MASK 0x3c000U
#define FTMCTRL_MCFG1_ROMBANKSZ_GET( _reg ) \
#define FTMCTRL_MCFG1_ROMBANKSZ_MASK 0x3c000U
#define FTMCTRL_MCFG1_ROMBANKSZ_GET( _reg ) \
( ( ( _reg ) & FTMCTRL_MCFG1_ROMBANKSZ_MASK ) >> \
FTMCTRL_MCFG1_ROMBANKSZ_SHIFT )
#define FTMCTRL_MCFG1_ROMBANKSZ_SET( _reg, _val ) \
( ( ( _reg ) & ~FTMCTRL_MCFG1_ROMBANKSZ_MASK ) | \
#define FTMCTRL_MCFG1_ROMBANKSZ_SET( _reg, _val ) \
( ( ( _reg ) & ~FTMCTRL_MCFG1_ROMBANKSZ_MASK ) | \
( ( ( _val ) << FTMCTRL_MCFG1_ROMBANKSZ_SHIFT ) & \
FTMCTRL_MCFG1_ROMBANKSZ_MASK ) )
#define FTMCTRL_MCFG1_ROMBANKSZ( _val ) \
#define FTMCTRL_MCFG1_ROMBANKSZ( _val ) \
( ( ( _val ) << FTMCTRL_MCFG1_ROMBANKSZ_SHIFT ) & \
FTMCTRL_MCFG1_ROMBANKSZ_MASK )
#define FTMCTRL_MCFG1_PWEN 0x800U
#define FTMCTRL_MCFG1_PROM_WIDTH_SHIFT 8
#define FTMCTRL_MCFG1_PROM_WIDTH_MASK 0x300U
#define FTMCTRL_MCFG1_PROM_WIDTH_GET( _reg ) \
#define FTMCTRL_MCFG1_PROM_WIDTH_MASK 0x300U
#define FTMCTRL_MCFG1_PROM_WIDTH_GET( _reg ) \
( ( ( _reg ) & FTMCTRL_MCFG1_PROM_WIDTH_MASK ) >> \
FTMCTRL_MCFG1_PROM_WIDTH_SHIFT )
#define FTMCTRL_MCFG1_PROM_WIDTH_SET( _reg, _val ) \
( ( ( _reg ) & ~FTMCTRL_MCFG1_PROM_WIDTH_MASK ) | \
#define FTMCTRL_MCFG1_PROM_WIDTH_SET( _reg, _val ) \
( ( ( _reg ) & ~FTMCTRL_MCFG1_PROM_WIDTH_MASK ) | \
( ( ( _val ) << FTMCTRL_MCFG1_PROM_WIDTH_SHIFT ) & \
FTMCTRL_MCFG1_PROM_WIDTH_MASK ) )
#define FTMCTRL_MCFG1_PROM_WIDTH( _val ) \
#define FTMCTRL_MCFG1_PROM_WIDTH( _val ) \
( ( ( _val ) << FTMCTRL_MCFG1_PROM_WIDTH_SHIFT ) & \
FTMCTRL_MCFG1_PROM_WIDTH_MASK )
#define FTMCTRL_MCFG1_PROM_WRITE_WS_SHIFT 4
#define FTMCTRL_MCFG1_PROM_WRITE_WS_MASK 0xf0U
#define FTMCTRL_MCFG1_PROM_WRITE_WS_GET( _reg ) \
#define FTMCTRL_MCFG1_PROM_WRITE_WS_MASK 0xf0U
#define FTMCTRL_MCFG1_PROM_WRITE_WS_GET( _reg ) \
( ( ( _reg ) & FTMCTRL_MCFG1_PROM_WRITE_WS_MASK ) >> \
FTMCTRL_MCFG1_PROM_WRITE_WS_SHIFT )
#define FTMCTRL_MCFG1_PROM_WRITE_WS_SET( _reg, _val ) \
( ( ( _reg ) & ~FTMCTRL_MCFG1_PROM_WRITE_WS_MASK ) | \
#define FTMCTRL_MCFG1_PROM_WRITE_WS_SET( _reg, _val ) \
( ( ( _reg ) & ~FTMCTRL_MCFG1_PROM_WRITE_WS_MASK ) | \
( ( ( _val ) << FTMCTRL_MCFG1_PROM_WRITE_WS_SHIFT ) & \
FTMCTRL_MCFG1_PROM_WRITE_WS_MASK ) )
#define FTMCTRL_MCFG1_PROM_WRITE_WS( _val ) \
#define FTMCTRL_MCFG1_PROM_WRITE_WS( _val ) \
( ( ( _val ) << FTMCTRL_MCFG1_PROM_WRITE_WS_SHIFT ) & \
FTMCTRL_MCFG1_PROM_WRITE_WS_MASK )
#define FTMCTRL_MCFG1_PROM_READ_WS_SHIFT 0
#define FTMCTRL_MCFG1_PROM_READ_WS_MASK 0xfU
#define FTMCTRL_MCFG1_PROM_READ_WS_GET( _reg ) \
#define FTMCTRL_MCFG1_PROM_READ_WS_MASK 0xfU
#define FTMCTRL_MCFG1_PROM_READ_WS_GET( _reg ) \
( ( ( _reg ) & FTMCTRL_MCFG1_PROM_READ_WS_MASK ) >> \
FTMCTRL_MCFG1_PROM_READ_WS_SHIFT )
#define FTMCTRL_MCFG1_PROM_READ_WS_SET( _reg, _val ) \
( ( ( _reg ) & ~FTMCTRL_MCFG1_PROM_READ_WS_MASK ) | \
#define FTMCTRL_MCFG1_PROM_READ_WS_SET( _reg, _val ) \
( ( ( _reg ) & ~FTMCTRL_MCFG1_PROM_READ_WS_MASK ) | \
( ( ( _val ) << FTMCTRL_MCFG1_PROM_READ_WS_SHIFT ) & \
FTMCTRL_MCFG1_PROM_READ_WS_MASK ) )
#define FTMCTRL_MCFG1_PROM_READ_WS( _val ) \
#define FTMCTRL_MCFG1_PROM_READ_WS( _val ) \
( ( ( _val ) << FTMCTRL_MCFG1_PROM_READ_WS_SHIFT ) & \
FTMCTRL_MCFG1_PROM_READ_WS_MASK )
@@ -194,17 +192,14 @@ extern "C" {
#define FTMCTRL_MCFG3_PE 0x100U
#define FTMCTRL_MCFG3_TCB_SHIFT 0
#define FTMCTRL_MCFG3_TCB_MASK 0xffU
#define FTMCTRL_MCFG3_TCB_MASK 0xffU
#define FTMCTRL_MCFG3_TCB_GET( _reg ) \
( ( ( _reg ) & FTMCTRL_MCFG3_TCB_MASK ) >> \
FTMCTRL_MCFG3_TCB_SHIFT )
#define FTMCTRL_MCFG3_TCB_SET( _reg, _val ) \
( ( ( _reg ) & FTMCTRL_MCFG3_TCB_MASK ) >> FTMCTRL_MCFG3_TCB_SHIFT )
#define FTMCTRL_MCFG3_TCB_SET( _reg, _val ) \
( ( ( _reg ) & ~FTMCTRL_MCFG3_TCB_MASK ) | \
( ( ( _val ) << FTMCTRL_MCFG3_TCB_SHIFT ) & \
FTMCTRL_MCFG3_TCB_MASK ) )
( ( ( _val ) << FTMCTRL_MCFG3_TCB_SHIFT ) & FTMCTRL_MCFG3_TCB_MASK ) )
#define FTMCTRL_MCFG3_TCB( _val ) \
( ( ( _val ) << FTMCTRL_MCFG3_TCB_SHIFT ) & \
FTMCTRL_MCFG3_TCB_MASK )
( ( ( _val ) << FTMCTRL_MCFG3_TCB_SHIFT ) & FTMCTRL_MCFG3_TCB_MASK )
/** @} */
@@ -218,30 +213,26 @@ extern "C" {
*/
#define FTMCTRL_MCFG5_IOHWS_SHIFT 23
#define FTMCTRL_MCFG5_IOHWS_MASK 0x3f800000U
#define FTMCTRL_MCFG5_IOHWS_MASK 0x3f800000U
#define FTMCTRL_MCFG5_IOHWS_GET( _reg ) \
( ( ( _reg ) & FTMCTRL_MCFG5_IOHWS_MASK ) >> \
FTMCTRL_MCFG5_IOHWS_SHIFT )
#define FTMCTRL_MCFG5_IOHWS_SET( _reg, _val ) \
( ( ( _reg ) & ~FTMCTRL_MCFG5_IOHWS_MASK ) | \
( ( ( _reg ) & FTMCTRL_MCFG5_IOHWS_MASK ) >> FTMCTRL_MCFG5_IOHWS_SHIFT )
#define FTMCTRL_MCFG5_IOHWS_SET( _reg, _val ) \
( ( ( _reg ) & ~FTMCTRL_MCFG5_IOHWS_MASK ) | \
( ( ( _val ) << FTMCTRL_MCFG5_IOHWS_SHIFT ) & \
FTMCTRL_MCFG5_IOHWS_MASK ) )
#define FTMCTRL_MCFG5_IOHWS( _val ) \
( ( ( _val ) << FTMCTRL_MCFG5_IOHWS_SHIFT ) & \
FTMCTRL_MCFG5_IOHWS_MASK )
( ( ( _val ) << FTMCTRL_MCFG5_IOHWS_SHIFT ) & FTMCTRL_MCFG5_IOHWS_MASK )
#define FTMCTRL_MCFG5_ROMHWS_SHIFT 7
#define FTMCTRL_MCFG5_ROMHWS_MASK 0x3f80U
#define FTMCTRL_MCFG5_ROMHWS_MASK 0x3f80U
#define FTMCTRL_MCFG5_ROMHWS_GET( _reg ) \
( ( ( _reg ) & FTMCTRL_MCFG5_ROMHWS_MASK ) >> \
FTMCTRL_MCFG5_ROMHWS_SHIFT )
#define FTMCTRL_MCFG5_ROMHWS_SET( _reg, _val ) \
( ( ( _reg ) & ~FTMCTRL_MCFG5_ROMHWS_MASK ) | \
( ( ( _reg ) & FTMCTRL_MCFG5_ROMHWS_MASK ) >> FTMCTRL_MCFG5_ROMHWS_SHIFT )
#define FTMCTRL_MCFG5_ROMHWS_SET( _reg, _val ) \
( ( ( _reg ) & ~FTMCTRL_MCFG5_ROMHWS_MASK ) | \
( ( ( _val ) << FTMCTRL_MCFG5_ROMHWS_SHIFT ) & \
FTMCTRL_MCFG5_ROMHWS_MASK ) )
#define FTMCTRL_MCFG5_ROMHWS( _val ) \
( ( ( _val ) << FTMCTRL_MCFG5_ROMHWS_SHIFT ) & \
FTMCTRL_MCFG5_ROMHWS_MASK )
( ( ( _val ) << FTMCTRL_MCFG5_ROMHWS_SHIFT ) & FTMCTRL_MCFG5_ROMHWS_MASK )
/** @} */
@@ -255,28 +246,28 @@ extern "C" {
*/
#define FTMCTRL_MCFG7_BRDYNCNT_SHIFT 16
#define FTMCTRL_MCFG7_BRDYNCNT_MASK 0xffff0000U
#define FTMCTRL_MCFG7_BRDYNCNT_GET( _reg ) \
#define FTMCTRL_MCFG7_BRDYNCNT_MASK 0xffff0000U
#define FTMCTRL_MCFG7_BRDYNCNT_GET( _reg ) \
( ( ( _reg ) & FTMCTRL_MCFG7_BRDYNCNT_MASK ) >> \
FTMCTRL_MCFG7_BRDYNCNT_SHIFT )
#define FTMCTRL_MCFG7_BRDYNCNT_SET( _reg, _val ) \
( ( ( _reg ) & ~FTMCTRL_MCFG7_BRDYNCNT_MASK ) | \
#define FTMCTRL_MCFG7_BRDYNCNT_SET( _reg, _val ) \
( ( ( _reg ) & ~FTMCTRL_MCFG7_BRDYNCNT_MASK ) | \
( ( ( _val ) << FTMCTRL_MCFG7_BRDYNCNT_SHIFT ) & \
FTMCTRL_MCFG7_BRDYNCNT_MASK ) )
#define FTMCTRL_MCFG7_BRDYNCNT( _val ) \
#define FTMCTRL_MCFG7_BRDYNCNT( _val ) \
( ( ( _val ) << FTMCTRL_MCFG7_BRDYNCNT_SHIFT ) & \
FTMCTRL_MCFG7_BRDYNCNT_MASK )
#define FTMCTRL_MCFG7_BRDYNRLD_SHIFT 0
#define FTMCTRL_MCFG7_BRDYNRLD_MASK 0xffffU
#define FTMCTRL_MCFG7_BRDYNRLD_GET( _reg ) \
#define FTMCTRL_MCFG7_BRDYNRLD_MASK 0xffffU
#define FTMCTRL_MCFG7_BRDYNRLD_GET( _reg ) \
( ( ( _reg ) & FTMCTRL_MCFG7_BRDYNRLD_MASK ) >> \
FTMCTRL_MCFG7_BRDYNRLD_SHIFT )
#define FTMCTRL_MCFG7_BRDYNRLD_SET( _reg, _val ) \
( ( ( _reg ) & ~FTMCTRL_MCFG7_BRDYNRLD_MASK ) | \
#define FTMCTRL_MCFG7_BRDYNRLD_SET( _reg, _val ) \
( ( ( _reg ) & ~FTMCTRL_MCFG7_BRDYNRLD_MASK ) | \
( ( ( _val ) << FTMCTRL_MCFG7_BRDYNRLD_SHIFT ) & \
FTMCTRL_MCFG7_BRDYNRLD_MASK ) )
#define FTMCTRL_MCFG7_BRDYNRLD( _val ) \
#define FTMCTRL_MCFG7_BRDYNRLD( _val ) \
( ( ( _val ) << FTMCTRL_MCFG7_BRDYNRLD_SHIFT ) & \
FTMCTRL_MCFG7_BRDYNRLD_MASK )
bsps/include/grlib/genirq.h
+23 -14
View File
@@ -39,11 +39,11 @@
extern "C" {
#endif
typedef void (*genirq_handler)(void *arg);
typedef void* genirq_t;
typedef void ( *genirq_handler )( void *arg );
typedef void *genirq_t;
struct genirq_stats {
unsigned int irq_cnt;
unsigned int irq_cnt;
};
/* Initialize the genirq interface. Must be the first function
@@ -51,20 +51,20 @@ struct genirq_stats {
*
* Returns zero on success, otherwise failure.
*/
extern genirq_t genirq_init(int number_of_irqs);
extern genirq_t genirq_init( int number_of_irqs );
/* Free the dynamically allocated memory that the genirq interface has
* allocated. Also the handlers will be freed.
*
* Returns zero on success, otherwise failure.
*/
extern void genirq_destroy(genirq_t d);
extern void genirq_destroy( genirq_t d );
/* Check IRQ number validity
*
* Returns zero for valid IRQ numbers, -1 of invalid IRQ numbers.
*/
extern int genirq_check(genirq_t d, int irq);
extern int genirq_check( genirq_t d, int irq );
/* Allocate one ISR handler and initialize it. Input to genirq_register().
*
@@ -73,10 +73,10 @@ extern int genirq_check(genirq_t d, int irq);
*
* Returns a pointer on success, on failure NULL is returned.
*/
extern void *genirq_alloc_handler(genirq_handler isr, void *arg);
extern void *genirq_alloc_handler( genirq_handler isr, void *arg );
/* Free handler memory */
#define genirq_free_handler(handler) free(handler)
#define genirq_free_handler( handler ) free( handler )
/* Register shared interrupt handler previously initialized with
* genirq_alloc_handler().
@@ -92,7 +92,7 @@ extern void *genirq_alloc_handler(genirq_handler isr, void *arg);
* 0 = Handler registered Successfully, first handler on this IRQ
* 1 = Handler registered Successfully, _not_ first handler on this IRQ
*/
extern int genirq_register(genirq_t d, int irq, void *handler);
extern int genirq_register( genirq_t d, int irq, void *handler );
/* Unregister an previous registered interrupt handler. It is the user's
* responsibility to free the handler returned by genirq_unregister().
@@ -105,8 +105,12 @@ extern int genirq_register(genirq_t d, int irq, void *handler);
* Pointer = ISR sucessfully unregistered. Returned is the handler pointer
* previously allocated with genirq_alloc_handler().
*/
extern void *genirq_unregister(genirq_t d, int irq,
genirq_handler isr, void *arg);
extern void *genirq_unregister(
genirq_t d,
int irq,
genirq_handler isr,
void *arg
);
/* Enables IRQ only for this isr[arg] combination. Records if this
* is the first interrupt enable, only then must interrupts be enabled
@@ -120,7 +124,7 @@ extern void *genirq_unregister(genirq_t d, int irq,
* 0 = IRQ must be enabled, it is the first IRQ handler to be enabled
* 1 = IRQ has already been enabled, either by isr[arg] or by another handler
*/
extern int genirq_enable(genirq_t d, int irq, genirq_handler isr, void *arg);
extern int genirq_enable( genirq_t d, int irq, genirq_handler isr, void *arg );
/* Disables IRQ only for this isr[arg] combination. Records if this
* is the only interrupt handler that is enabled on this IRQ, only then
@@ -134,7 +138,12 @@ extern int genirq_enable(genirq_t d, int irq, genirq_handler isr, void *arg);
* 0 = IRQ must be disabled, no ISR are enabled for this IRQ
* 1 = ISR has already been disabled, or other ISRs are still enabled
*/
extern int genirq_disable(genirq_t d, int irq, genirq_handler isr, void *arg);
extern int genirq_disable(
genirq_t d,
int irq,
genirq_handler isr,
void *arg
);
/* Must be called by user when an IRQ has fired, the argument 'irq'
* is the IRQ number of the IRQ which was fired.
@@ -142,7 +151,7 @@ extern int genirq_disable(genirq_t d, int irq, genirq_handler isr, void *arg);
* NOTE: internal list structures are accessed and needs to be protected by
* spin-locks/IRQ disable by the user to guarantee a correct behaviour.
*/
extern void genirq_doirq(genirq_t d, int irq);
extern void genirq_doirq( genirq_t d, int irq );
#ifdef __cplusplus
}
bsps/include/grlib/gpiolib.h
+31 -31
View File
@@ -36,25 +36,25 @@ extern "C" {
/* GPIO Config of one GPIO port */
struct gpiolib_config {
char mask; /* 0=Masked/1=Unmasked IRQ */
char irq_level; /* Edge or Level triggered IRQ */
char irq_polarity; /* Polarity of IRQ */
char mask; /* 0=Masked/1=Unmasked IRQ */
char irq_level; /* Edge or Level triggered IRQ */
char irq_polarity; /* Polarity of IRQ */
};
#define GPIOLIB_IRQ_EDGE 0
#define GPIOLIB_IRQ_EDGE 0
#define GPIOLIB_IRQ_LEVEL 1
#define GPIOLIB_IRQ_POL_LOW 0
#define GPIOLIB_IRQ_POL_LOW 0
#define GPIOLIB_IRQ_POL_HIGH 1
/* Libarary initialize function must be called befor any other */
extern int gpiolib_initialize(void);
extern int gpiolib_initialize( void );
/*** User Interface ***/
extern void *gpiolib_open(int port);
extern void *gpiolib_open_by_name(char *devName);
extern void gpiolib_close(void *handle);
extern void *gpiolib_open( int port );
extern void *gpiolib_open_by_name( char *devName );
extern void gpiolib_close( void *handle );
/* Show the current status one or all GPIO ports in the system.
* Int port is port nunber, if port = -1 selects all ports.
@@ -62,34 +62,34 @@ extern void gpiolib_close(void *handle);
* If port != -1, handle is used to get port.
* If port != -1, handle == NULL, then port is used as port number
*/
extern void gpiolib_show(int port, void *handle);
extern void gpiolib_show( int port, void *handle );
extern int gpiolib_set_config(void *handle, struct gpiolib_config *cfg);
extern int gpiolib_set(void *handle, int dir, int val);
extern int gpiolib_get(void *handle, int *inval);
extern int gpiolib_irq_clear(void *handle);
extern int gpiolib_irq_enable(void *handle);
extern int gpiolib_irq_disable(void *handle);
extern int gpiolib_irq_mask(void *handle);
extern int gpiolib_irq_unmask(void *handle);
extern int gpiolib_irq_force(void *handle);
extern int gpiolib_irq_register(void *handle, void *func, void *arg);
extern int gpiolib_set_config( void *handle, struct gpiolib_config *cfg );
extern int gpiolib_set( void *handle, int dir, int val );
extern int gpiolib_get( void *handle, int *inval );
extern int gpiolib_irq_clear( void *handle );
extern int gpiolib_irq_enable( void *handle );
extern int gpiolib_irq_disable( void *handle );
extern int gpiolib_irq_mask( void *handle );
extern int gpiolib_irq_unmask( void *handle );
extern int gpiolib_irq_force( void *handle );
extern int gpiolib_irq_register( void *handle, void *func, void *arg );
/*** Driver Interface ***/
struct gpiolib_info {
char devName[80];
char devName[ 80 ];
};
struct gpiolib_drv_ops {
int (*config)(void *handle, struct gpiolib_config *cfg);
int (*get)(void *handle, int *val);
int (*irq_opts)(void *handle, unsigned int options);
int (*irq_register)(void *handle, void *func, void *arg);
int (*open)(void *handle);
int (*set)(void *handle, int dir, int outval);
int (*show)(void *handle);
int (*get_info)(void *handle, struct gpiolib_info *pinfo);
int ( *config )( void *handle, struct gpiolib_config *cfg );
int ( *get )( void *handle, int *val );
int ( *irq_opts )( void *handle, unsigned int options );
int ( *irq_register )( void *handle, void *func, void *arg );
int ( *open )( void *handle );
int ( *set )( void *handle, int dir, int outval );
int ( *show )( void *handle );
int ( *get_info )( void *handle, struct gpiolib_info *pinfo );
};
#define GPIOLIB_IRQ_ENABLE 0x01
@@ -100,11 +100,11 @@ struct gpiolib_drv_ops {
#define GPIOLIB_IRQ_UNMASK 0x20
struct gpiolib_drv {
struct gpiolib_drv_ops *ops;
struct gpiolib_drv_ops *ops;
};
/* Register a GPIO port */
extern int gpiolib_drv_register(struct gpiolib_drv *drv, void *handle);
extern int gpiolib_drv_register( struct gpiolib_drv *drv, void *handle );
#ifdef __cplusplus
}
bsps/include/grlib/gptimer-regs.h
+40 -51
View File
@@ -93,17 +93,15 @@ extern "C" {
*/
#define GPTIMER_TCNTVAL_TCVAL_SHIFT 0
#define GPTIMER_TCNTVAL_TCVAL_MASK 0xffffffffU
#define GPTIMER_TCNTVAL_TCVAL_MASK 0xffffffffU
#define GPTIMER_TCNTVAL_TCVAL_GET( _reg ) \
( ( ( _reg ) & GPTIMER_TCNTVAL_TCVAL_MASK ) >> \
GPTIMER_TCNTVAL_TCVAL_SHIFT )
#define GPTIMER_TCNTVAL_TCVAL_SET( _reg, _val ) \
( ( ( _reg ) & ~GPTIMER_TCNTVAL_TCVAL_MASK ) | \
( ( ( _reg ) & GPTIMER_TCNTVAL_TCVAL_MASK ) >> GPTIMER_TCNTVAL_TCVAL_SHIFT )
#define GPTIMER_TCNTVAL_TCVAL_SET( _reg, _val ) \
( ( ( _reg ) & ~GPTIMER_TCNTVAL_TCVAL_MASK ) | \
( ( ( _val ) << GPTIMER_TCNTVAL_TCVAL_SHIFT ) & \
GPTIMER_TCNTVAL_TCVAL_MASK ) )
#define GPTIMER_TCNTVAL_TCVAL( _val ) \
( ( ( _val ) << GPTIMER_TCNTVAL_TCVAL_SHIFT ) & \
GPTIMER_TCNTVAL_TCVAL_MASK )
( ( ( _val ) << GPTIMER_TCNTVAL_TCVAL_SHIFT ) & GPTIMER_TCNTVAL_TCVAL_MASK )
/** @} */
@@ -117,15 +115,15 @@ extern "C" {
*/
#define GPTIMER_TRLDVAL_TRLDVAL_SHIFT 0
#define GPTIMER_TRLDVAL_TRLDVAL_MASK 0xffffffffU
#define GPTIMER_TRLDVAL_TRLDVAL_GET( _reg ) \
#define GPTIMER_TRLDVAL_TRLDVAL_MASK 0xffffffffU
#define GPTIMER_TRLDVAL_TRLDVAL_GET( _reg ) \
( ( ( _reg ) & GPTIMER_TRLDVAL_TRLDVAL_MASK ) >> \
GPTIMER_TRLDVAL_TRLDVAL_SHIFT )
#define GPTIMER_TRLDVAL_TRLDVAL_SET( _reg, _val ) \
( ( ( _reg ) & ~GPTIMER_TRLDVAL_TRLDVAL_MASK ) | \
#define GPTIMER_TRLDVAL_TRLDVAL_SET( _reg, _val ) \
( ( ( _reg ) & ~GPTIMER_TRLDVAL_TRLDVAL_MASK ) | \
( ( ( _val ) << GPTIMER_TRLDVAL_TRLDVAL_SHIFT ) & \
GPTIMER_TRLDVAL_TRLDVAL_MASK ) )
#define GPTIMER_TRLDVAL_TRLDVAL( _val ) \
#define GPTIMER_TRLDVAL_TRLDVAL( _val ) \
( ( ( _val ) << GPTIMER_TRLDVAL_TRLDVAL_SHIFT ) & \
GPTIMER_TRLDVAL_TRLDVAL_MASK )
@@ -168,17 +166,15 @@ extern "C" {
*/
#define GPTIMER_TLATCH_LTCV_SHIFT 0
#define GPTIMER_TLATCH_LTCV_MASK 0xffffffffU
#define GPTIMER_TLATCH_LTCV_MASK 0xffffffffU
#define GPTIMER_TLATCH_LTCV_GET( _reg ) \
( ( ( _reg ) & GPTIMER_TLATCH_LTCV_MASK ) >> \
GPTIMER_TLATCH_LTCV_SHIFT )
#define GPTIMER_TLATCH_LTCV_SET( _reg, _val ) \
( ( ( _reg ) & ~GPTIMER_TLATCH_LTCV_MASK ) | \
( ( ( _reg ) & GPTIMER_TLATCH_LTCV_MASK ) >> GPTIMER_TLATCH_LTCV_SHIFT )
#define GPTIMER_TLATCH_LTCV_SET( _reg, _val ) \
( ( ( _reg ) & ~GPTIMER_TLATCH_LTCV_MASK ) | \
( ( ( _val ) << GPTIMER_TLATCH_LTCV_SHIFT ) & \
GPTIMER_TLATCH_LTCV_MASK ) )
#define GPTIMER_TLATCH_LTCV( _val ) \
( ( ( _val ) << GPTIMER_TLATCH_LTCV_SHIFT ) & \
GPTIMER_TLATCH_LTCV_MASK )
( ( ( _val ) << GPTIMER_TLATCH_LTCV_SHIFT ) & GPTIMER_TLATCH_LTCV_MASK )
/** @} */
@@ -230,17 +226,15 @@ typedef struct gptimer_timer {
*/
#define GPTIMER_SCALER_SCALER_SHIFT 0
#define GPTIMER_SCALER_SCALER_MASK 0xffffU
#define GPTIMER_SCALER_SCALER_MASK 0xffffU
#define GPTIMER_SCALER_SCALER_GET( _reg ) \
( ( ( _reg ) & GPTIMER_SCALER_SCALER_MASK ) >> \
GPTIMER_SCALER_SCALER_SHIFT )
#define GPTIMER_SCALER_SCALER_SET( _reg, _val ) \
( ( ( _reg ) & ~GPTIMER_SCALER_SCALER_MASK ) | \
( ( ( _reg ) & GPTIMER_SCALER_SCALER_MASK ) >> GPTIMER_SCALER_SCALER_SHIFT )
#define GPTIMER_SCALER_SCALER_SET( _reg, _val ) \
( ( ( _reg ) & ~GPTIMER_SCALER_SCALER_MASK ) | \
( ( ( _val ) << GPTIMER_SCALER_SCALER_SHIFT ) & \
GPTIMER_SCALER_SCALER_MASK ) )
#define GPTIMER_SCALER_SCALER( _val ) \
( ( ( _val ) << GPTIMER_SCALER_SCALER_SHIFT ) & \
GPTIMER_SCALER_SCALER_MASK )
( ( ( _val ) << GPTIMER_SCALER_SCALER_SHIFT ) & GPTIMER_SCALER_SCALER_MASK )
/** @} */
@@ -254,15 +248,15 @@ typedef struct gptimer_timer {
*/
#define GPTIMER_SRELOAD_SRELOAD_SHIFT 0
#define GPTIMER_SRELOAD_SRELOAD_MASK 0xffffU
#define GPTIMER_SRELOAD_SRELOAD_GET( _reg ) \
#define GPTIMER_SRELOAD_SRELOAD_MASK 0xffffU
#define GPTIMER_SRELOAD_SRELOAD_GET( _reg ) \
( ( ( _reg ) & GPTIMER_SRELOAD_SRELOAD_MASK ) >> \
GPTIMER_SRELOAD_SRELOAD_SHIFT )
#define GPTIMER_SRELOAD_SRELOAD_SET( _reg, _val ) \
( ( ( _reg ) & ~GPTIMER_SRELOAD_SRELOAD_MASK ) | \
#define GPTIMER_SRELOAD_SRELOAD_SET( _reg, _val ) \
( ( ( _reg ) & ~GPTIMER_SRELOAD_SRELOAD_MASK ) | \
( ( ( _val ) << GPTIMER_SRELOAD_SRELOAD_SHIFT ) & \
GPTIMER_SRELOAD_SRELOAD_MASK ) )
#define GPTIMER_SRELOAD_SRELOAD( _val ) \
#define GPTIMER_SRELOAD_SRELOAD( _val ) \
( ( ( _val ) << GPTIMER_SRELOAD_SRELOAD_SHIFT ) & \
GPTIMER_SRELOAD_SRELOAD_MASK )
@@ -289,30 +283,25 @@ typedef struct gptimer_timer {
#define GPTIMER_CONFIG_SI 0x100U
#define GPTIMER_CONFIG_IRQ_SHIFT 3
#define GPTIMER_CONFIG_IRQ_MASK 0xf8U
#define GPTIMER_CONFIG_IRQ_MASK 0xf8U
#define GPTIMER_CONFIG_IRQ_GET( _reg ) \
( ( ( _reg ) & GPTIMER_CONFIG_IRQ_MASK ) >> \
GPTIMER_CONFIG_IRQ_SHIFT )
#define GPTIMER_CONFIG_IRQ_SET( _reg, _val ) \
( ( ( _reg ) & GPTIMER_CONFIG_IRQ_MASK ) >> GPTIMER_CONFIG_IRQ_SHIFT )
#define GPTIMER_CONFIG_IRQ_SET( _reg, _val ) \
( ( ( _reg ) & ~GPTIMER_CONFIG_IRQ_MASK ) | \
( ( ( _val ) << GPTIMER_CONFIG_IRQ_SHIFT ) & \
GPTIMER_CONFIG_IRQ_MASK ) )
( ( ( _val ) << GPTIMER_CONFIG_IRQ_SHIFT ) & GPTIMER_CONFIG_IRQ_MASK ) )
#define GPTIMER_CONFIG_IRQ( _val ) \
( ( ( _val ) << GPTIMER_CONFIG_IRQ_SHIFT ) & \
GPTIMER_CONFIG_IRQ_MASK )
( ( ( _val ) << GPTIMER_CONFIG_IRQ_SHIFT ) & GPTIMER_CONFIG_IRQ_MASK )
#define GPTIMER_CONFIG_TIMERS_SHIFT 0
#define GPTIMER_CONFIG_TIMERS_MASK 0x7U
#define GPTIMER_CONFIG_TIMERS_MASK 0x7U
#define GPTIMER_CONFIG_TIMERS_GET( _reg ) \
( ( ( _reg ) & GPTIMER_CONFIG_TIMERS_MASK ) >> \
GPTIMER_CONFIG_TIMERS_SHIFT )
#define GPTIMER_CONFIG_TIMERS_SET( _reg, _val ) \
( ( ( _reg ) & ~GPTIMER_CONFIG_TIMERS_MASK ) | \
( ( ( _reg ) & GPTIMER_CONFIG_TIMERS_MASK ) >> GPTIMER_CONFIG_TIMERS_SHIFT )
#define GPTIMER_CONFIG_TIMERS_SET( _reg, _val ) \
( ( ( _reg ) & ~GPTIMER_CONFIG_TIMERS_MASK ) | \
( ( ( _val ) << GPTIMER_CONFIG_TIMERS_SHIFT ) & \
GPTIMER_CONFIG_TIMERS_MASK ) )
#define GPTIMER_CONFIG_TIMERS( _val ) \
( ( ( _val ) << GPTIMER_CONFIG_TIMERS_SHIFT ) & \
GPTIMER_CONFIG_TIMERS_MASK )
( ( ( _val ) << GPTIMER_CONFIG_TIMERS_SHIFT ) & GPTIMER_CONFIG_TIMERS_MASK )
/** @} */
@@ -326,15 +315,15 @@ typedef struct gptimer_timer {
*/
#define GPTIMER_LATCHCFG_LATCHSEL_SHIFT 0
#define GPTIMER_LATCHCFG_LATCHSEL_MASK 0xffffffffU
#define GPTIMER_LATCHCFG_LATCHSEL_GET( _reg ) \
#define GPTIMER_LATCHCFG_LATCHSEL_MASK 0xffffffffU
#define GPTIMER_LATCHCFG_LATCHSEL_GET( _reg ) \
( ( ( _reg ) & GPTIMER_LATCHCFG_LATCHSEL_MASK ) >> \
GPTIMER_LATCHCFG_LATCHSEL_SHIFT )
#define GPTIMER_LATCHCFG_LATCHSEL_SET( _reg, _val ) \
( ( ( _reg ) & ~GPTIMER_LATCHCFG_LATCHSEL_MASK ) | \
#define GPTIMER_LATCHCFG_LATCHSEL_SET( _reg, _val ) \
( ( ( _reg ) & ~GPTIMER_LATCHCFG_LATCHSEL_MASK ) | \
( ( ( _val ) << GPTIMER_LATCHCFG_LATCHSEL_SHIFT ) & \
GPTIMER_LATCHCFG_LATCHSEL_MASK ) )
#define GPTIMER_LATCHCFG_LATCHSEL( _val ) \
#define GPTIMER_LATCHCFG_LATCHSEL( _val ) \
( ( ( _val ) << GPTIMER_LATCHCFG_LATCHSEL_SHIFT ) & \
GPTIMER_LATCHCFG_LATCHSEL_MASK )
bsps/include/grlib/gptimer.h
+1 -1
View File
@@ -40,7 +40,7 @@ extern "C" {
*/
/* Register GPTIMER and GRTIMER driver to Driver Manager */
void gptimer_register_drv (void);
void gptimer_register_drv( void );
#ifdef __cplusplus
}
bsps/include/grlib/gr1553b-regs.h
+250 -383
View File
File diff suppressed because it is too large Load Diff
bsps/include/grlib/gr1553b.h
+240 -241
View File
File diff suppressed because it is too large Load Diff
bsps/include/grlib/gr1553bc.h
+47 -55
View File
@@ -66,38 +66,38 @@ extern "C" {
#endif
/* Register GR1553B driver needed by BC driver */
extern void gr1553bc_register(void);
extern void gr1553bc_register( void );
/* A BC descriptor accessed as is */
struct gr1553bc_bd_raw {
volatile uint32_t words[4];
volatile uint32_t words[ 4 ];
};
/* A BC descriptor accessed as a transfer descriptor */
struct gr1553bc_bd_tr {
volatile uint32_t settings[2];
volatile uint32_t dptr;
volatile uint32_t status;
volatile uint32_t settings[ 2 ];
volatile uint32_t dptr;
volatile uint32_t status;
};
/* A BC descriptor accessed as a conditional descriptor */
struct gr1553bc_bd_cond {
volatile uint32_t cond;
volatile uint32_t bdptr;
volatile uint32_t padding[2];
volatile uint32_t cond;
volatile uint32_t bdptr;
volatile uint32_t padding[ 2 ];
};
/* A BC descriptor accessed any way */
union gr1553bc_bd {
struct gr1553bc_bd_raw raw;
struct gr1553bc_bd_tr tr;
struct gr1553bc_bd_cond cond;
struct gr1553bc_bd_raw raw;
struct gr1553bc_bd_tr tr;
struct gr1553bc_bd_cond cond;
};
/* Current state of the BC hardware */
struct gr1553bc_status {
unsigned int status;
unsigned int time;
unsigned int status;
unsigned int time;
};
#define KEEP_TIMESLOT 0x10
@@ -113,13 +113,13 @@ struct gr1553bc_status {
* descriptor.
*/
extern void gr1553bc_bd_init(
union gr1553bc_bd *bd,
unsigned int flags,
uint32_t word0,
uint32_t word1,
uint32_t word2,
uint32_t word3
);
union gr1553bc_bd *bd,
unsigned int flags,
uint32_t word0,
uint32_t word1,
uint32_t word2,
uint32_t word3
);
/* Initialize a Transfer descriptor
*
@@ -130,9 +130,8 @@ extern void gr1553bc_bd_init(
* uint32_t data
* uint32_t status
*/
#define gr1553bc_bd_tr_init(bd, set0, set1, data, status) \
gr1553bc_bd_init((union gr1553bc_bd *)bd,\
0xf, set0, set1, data, status)
#define gr1553bc_bd_tr_init( bd, set0, set1, data, status ) \
gr1553bc_bd_init( (union gr1553bc_bd *) bd, 0xf, set0, set1, data, status )
/* Initializa a Condition descriptor
*
* Arguments:
@@ -140,12 +139,11 @@ extern void gr1553bc_bd_init(
* uint32_t cond
* uint32_t jump_adr
*/
#define gr1553bc_bd_cond_init(bd, cond, jump_adr) \
gr1553bc_bd_init((union gr1553bc_bd *)bd, \
0xf, cond, jump_adr, 0, 0)
#define gr1553bc_bd_cond_init( bd, cond, jump_adr ) \
gr1553bc_bd_init( (union gr1553bc_bd *) bd, 0xf, cond, jump_adr, 0, 0 )
/* Size of a descriptor */
#define GR1553BC_BD_SIZE sizeof(struct gr1553bc_bd_raw)
#define GR1553BC_BD_SIZE sizeof( struct gr1553bc_bd_raw )
/* Alignment of a descriptor */
#define GR1553BC_BD_ALIGN 16
@@ -153,29 +151,29 @@ extern void gr1553bc_bd_init(
/* End of list marker */
#define GR1553BC_TR_EOL 0x80ffffff
#define GR1553BC_BD_TYPE 0x80000000
#define GR1553BC_BD_TYPE 0x80000000
/* Condition descriptor bits */
#define GR1553BC_UNCOND_JMP 0x820000ff
#define GR1553BC_UNCOND_IRQ 0x860000ff
#define GR1553BC_UNCOND_NOJMP 0x82000000
#define GR1553BC_UNCOND_JMP 0x820000ff
#define GR1553BC_UNCOND_IRQ 0x860000ff
#define GR1553BC_UNCOND_NOJMP 0x82000000
/* Transfer descriptor bits */
#define GR1553BC_TR_DUMMY_0 0x00000000
#define GR1553BC_TR_DUMMY_1 0x80000000
#define GR1553BC_TR_DUMMY_0 0x00000000
#define GR1553BC_TR_DUMMY_1 0x80000000
#define GR1553BC_TR_TIME 0x0000ffff
#define GR1553BC_TR_TIME 0x0000ffff
#define GR1553BC_TR_EXTTRIG 0x40000000
#define GR1553BC_TR_EXTTRIG 0x40000000
/* Take a GR1553BC hardware device identified by instance index (minor).
* A pointer is returned that is used internally by the GR1553BC
* driver, it is used as an input paramter 'bc' to all other
* functions that manipulate the hardware.
*/
extern void *gr1553bc_open(int minor);
extern void *gr1553bc_open( int minor );
extern void gr1553bc_close(void *bc);
extern void gr1553bc_close( void *bc );
/* Stores Current Major/Minor frame number and the Slot number executing
* into the location indicated by 'mid'. There may be two lists executing
@@ -184,7 +182,7 @@ extern void gr1553bc_close(void *bc);
* list.
*
*/
extern int gr1553bc_indication(void *bc, int async, int *mid);
extern int gr1553bc_indication( void *bc, int async, int *mid );
/* Trigger external time sync by writing to the BC action register.
* This may be good for debugging or if the time management is
@@ -193,7 +191,7 @@ extern int gr1553bc_indication(void *bc, int async, int *mid);
* if trig=0 the external trigger memory is cleared.
* if trig!=0 the external trigger memory is set.
*/
extern void gr1553bc_ext_trig(void *bc, int trig);
extern void gr1553bc_ext_trig( void *bc, int trig );
/* Configure the GR1553BC driver */
/*extern int gr1553bc_config(struct gr1553bc_config *cfg);*/
@@ -209,24 +207,23 @@ extern void gr1553bc_ext_trig(void *bc, int trig);
* list - Schedule Transfer List
* list_async - Asynchronous list
*/
extern int gr1553bc_start
(
void *bc,
struct gr1553bc_list *list,
struct gr1553bc_list *list_async
);
extern int gr1553bc_start(
void *bc,
struct gr1553bc_list *list,
struct gr1553bc_list *list_async
);
/* Pause GR1553B BC scheduled transfers.
*
* Does not affect asynchronous operation.
*/
extern int gr1553bc_pause(void *bc);
extern int gr1553bc_pause( void *bc );
/* Restart GR1553B BC scheduled transfers, after being paused
*
* Does not affect asynchronous operation.
*/
extern int gr1553bc_restart(void *bc);
extern int gr1553bc_restart( void *bc );
/* Stop BC transmission.
*
@@ -234,7 +231,7 @@ extern int gr1553bc_restart(void *bc);
* bit0 - 1=STOP schedule list
* bit1 - 1=STOP asynchronous list
*/
extern int gr1553bc_stop(void *bc, int options);
extern int gr1553bc_stop( void *bc, int options );
/* Standard IRQ function setup. IRQ can be generated by condition descriptors
* or by transfer descriptors or by errors.
@@ -249,18 +246,13 @@ extern int gr1553bc_stop(void *bc, int options);
* IRQs generated by transfer descriptors or by BC errors (DMA error etc.)
* is handled by this standard ISR handler.
*/
extern int gr1553bc_irq_setup
(
void *bc,
bcirq_func_t func,
void *data
);
extern int gr1553bc_irq_setup( void *bc, bcirq_func_t func, void *data );
/* Get Current BC hardware state/status. The Status is stored into the
* area pointed to by status. See "struct gr1553bc_status" for more
* info.
*/
extern void gr1553bc_status(void *bc, struct gr1553bc_status *status);
extern void gr1553bc_status( void *bc, struct gr1553bc_status *status );
#ifdef __cplusplus
}
bsps/include/grlib/gr1553bc_list.h
+191 -194
View File
File diff suppressed because it is too large Load Diff
bsps/include/grlib/gr1553bm.h
+47 -54
View File
@@ -35,11 +35,11 @@ extern "C" {
#endif
/* Register GR1553B driver needed by BM driver */
extern void gr1553bm_register(void);
extern void gr1553bm_register( void );
struct gr1553bm_entry {
uint32_t time; /* bit31=1, bit 30=0 */
uint32_t data; /* bit31=0, bit 30=0 */
uint32_t time; /* bit31=1, bit 30=0 */
uint32_t data; /* bit31=0, bit 30=0 */
};
#define GR1553BM_ERROPTS_MANL 0x02
@@ -56,29 +56,28 @@ struct gr1553bm_entry {
* \param nentires Number of entries to be processed.
* \param data Custom Data (set by config)
*/
typedef int (*bmcopy_func_t)(
unsigned int dst,
struct gr1553bm_entry *src,
int nentries,
void *data
);
typedef int ( *bmcopy_func_t )(
unsigned int dst,
struct gr1553bm_entry *src,
int nentries,
void *data
);
/* IRQ function callback, called on BM DMA error */
typedef void (*bmisr_func_t)(void *bm, void *data);
typedef void ( *bmisr_func_t )( void *bm, void *data );
/* BM driver configuration */
struct gr1553bm_config {
/*** Time options ***/
/*** Time options ***/
/* 8-bit time resolution, the BM will update the time according
/* 8-bit time resolution, the BM will update the time according
* to this setting. 0 will make the time tag be of highest
* resolution (no division), 1 will make the BM increment the
* time tag once for two time ticks (div with 2), etc.
*/
uint8_t time_resolution;
uint8_t time_resolution;
/* Enable Time Overflow IRQ handling. Setting this to 1
/* Enable Time Overflow IRQ handling. Setting this to 1
* makes the driver to update the 64-bit time by it self,
* it will use time overflow IRQ to detect when the 64-bit
* time counter must be incremented.
@@ -87,75 +86,69 @@ struct gr1553bm_config {
* gr1553bm_time() regularly, it must be called more often
* than the time overflows to avoid an incorrect time.
*/
int time_ovf_irq;
int time_ovf_irq;
/*** Filtering options ***/
/*** Filtering options ***/
/* Bus error log options
/* Bus error log options
*
* bit0,4-31 = reserved, set to zero
* Bit1 = Enables logging of Invalid mode code errors
* Bit2 = Enables logging of Unexpected Data errors
* Bit3 = Enables logging of Manchester/parity errors
*/
unsigned int filt_error_options;
unsigned int filt_error_options;
/* RT Address filtering bit mask. Each bit enables (if set)
/* RT Address filtering bit mask. Each bit enables (if set)
* logging of a certain RT sub address. Bit 31 enables logging
* of broadcast messages.
*/
unsigned int filt_rtadr;
unsigned int filt_rtadr;
/* RT Subaddress filtering bit mask, bit definition:
/* RT Subaddress filtering bit mask, bit definition:
* 31: Enables logging of mode commands on subadr 31
* 1..30: BitN enables/disables logging of RT subadr N
* 0: Enables logging of mode commands on subadr 0
*/
unsigned int filt_subadr;
unsigned int filt_subadr;
/* Mode code Filter, is written into "BM RT Mode code filter"
/* Mode code Filter, is written into "BM RT Mode code filter"
* register, please see hardware manual for bit declarations.
*/
unsigned int filt_mc;
unsigned int filt_mc;
/*** Buffer options ***/
/*** Buffer options ***/
/* Size of buffer in bytes, must be aligned to 8-byte
/* Size of buffer in bytes, must be aligned to 8-byte
* The size is limited to max 4Mb.
*/
unsigned int buffer_size;
unsigned int buffer_size;
/* Custom buffer, must be aligned to 8-byte and be of buffer_size
/* Custom buffer, must be aligned to 8-byte and be of buffer_size
* length. If NULL dynamic memory allocation is used.
*/
void *buffer_custom;
void *buffer_custom;
/* Custom Copy function, may be used to implement a more
/* Custom Copy function, may be used to implement a more
* effective way of copying the DMA buffer. For example
* the DMA log may need to be compressed before copied
* onto a storage, this function can be used to avoid an
* extra copy.
*/
bmcopy_func_t copy_func;
bmcopy_func_t copy_func;
/* Optional Custom Data passed on to copy_func() */
void *copy_func_arg;
/* Optional Custom Data passed on to copy_func() */
void *copy_func_arg;
/*** Interrupt options ***/
/*** Interrupt options ***/
/* Custom DMA error function, note that this function is called
/* Custom DMA error function, note that this function is called
* from Interrupt Context. Set to NULL to disable this callback.
*/
bmisr_func_t dma_error_isr;
bmisr_func_t dma_error_isr;
/* Optional Custom Data passed on to dma_error_isr() */
void *dma_error_arg;
/* Optional Custom Data passed on to dma_error_isr() */
void *dma_error_arg;
};
/* Open BM device by instance number (minor)
@@ -163,16 +156,16 @@ struct gr1553bm_config {
* The return value is used as input parameter in all other function calls
* in the A
*/
extern void *gr1553bm_open(int minor);
extern void *gr1553bm_open( int minor );
/* Close previously opened Bm device */
extern void gr1553bm_close(void *bm);
extern void gr1553bm_close( void *bm );
/* Configure the BM driver before starting */
extern int gr1553bm_config(void *bm, struct gr1553bm_config *cfg);
extern int gr1553bm_config( void *bm, struct gr1553bm_config *cfg );
/* Start logging */
extern int gr1553bm_start(void *bm);
extern int gr1553bm_start( void *bm );
/* Get 64-bit 1553 Time. Low 24-bit time is acquired from BM hardware,
* the MSB is taken from a software counter internal to the driver. The
@@ -187,18 +180,18 @@ extern int gr1553bm_start(void *bm);
*
* Update software time counters and return the current time.
*/
extern void gr1553bm_time(void *bm, uint64_t *time);
extern void gr1553bm_time( void *bm, uint64_t *time );
/* Return zero when logging has not been started, non-zero when logging
* has been started
*/
extern int gr1553bm_started(void *bm);
extern int gr1553bm_started( void *bm );
/* Check how many entries are currently stored in the BM Log DMA-area */
extern int gr1553bm_available(void *bm, int *nentries);
extern int gr1553bm_available( void *bm, int *nentries );
/* Stop logging */
extern void gr1553bm_stop(void *bm);
extern void gr1553bm_stop( void *bm );
/* Read a maximum number of entries from LOG buffer. This function
* must be
@@ -214,7 +207,7 @@ extern void gr1553bm_stop(void *bm);
* 0 = success
* -1 = fail. (may be due to BM logging not started)
*/
extern int gr1553bm_read(void *bm, struct gr1553bm_entry *dst, int *max);
extern int gr1553bm_read( void *bm, struct gr1553bm_entry *dst, int *max );
#ifdef __cplusplus
}
bsps/include/grlib/gr1553rt.h
+105 -109
View File
@@ -54,7 +54,7 @@ extern "C" {
#endif
/* Register GR1553B driver needed by RT driver */
extern void gr1553rt_register(void);
extern void gr1553rt_register( void );
struct gr1553rt_list;
@@ -63,37 +63,37 @@ struct gr1553rt_list;
* Must be aligned to 16 byte boundary
*/
struct gr1553rt_bd {
volatile uint32_t ctrl; /* 0x00 Control/Status word */
volatile uint32_t dptr; /* 0x04 Data Pointer */
volatile uint32_t next; /* 0x08 Next Descriptor in list */
volatile uint32_t unused; /* 0x0C UNUSED BY HARDWARE */
volatile uint32_t ctrl; /* 0x00 Control/Status word */
volatile uint32_t dptr; /* 0x04 Data Pointer */
volatile uint32_t next; /* 0x08 Next Descriptor in list */
volatile uint32_t unused; /* 0x0C UNUSED BY HARDWARE */
};
/* Sub address table entry, the hardware access */
struct gr1553rt_sa {
volatile uint32_t ctrl; /* 0x00 SUBADDRESS CONTROL WORD */
volatile uint32_t txptr; /* 0x04 TRANSMIT BD POINTER */
volatile uint32_t rxptr; /* 0x08 RECEIVE BD POINTER */
volatile uint32_t unused; /* 0x0C UNUSED BY HARDWARE */
volatile uint32_t ctrl; /* 0x00 SUBADDRESS CONTROL WORD */
volatile uint32_t txptr; /* 0x04 TRANSMIT BD POINTER */
volatile uint32_t rxptr; /* 0x08 RECEIVE BD POINTER */
volatile uint32_t unused; /* 0x0C UNUSED BY HARDWARE */
};
/* Configuration of a RT-SubAddress-List */
struct gr1553rt_list_cfg {
unsigned int bd_cnt; /* Number of hw-descriptors in list */
unsigned int bd_cnt; /* Number of hw-descriptors in list */
};
/* A TX or RX subaddress descriptor list */
struct gr1553rt_list {
short listid; /* ID/NUMBER of List. -1 unassigned */
short subadr; /* SubAddress. -1 when not scheduled */
void *rt; /* Scheduled on Device */
struct gr1553rt_list_cfg *cfg; /* List configuration */
int bd_cnt; /* Number of Descriptors */
short listid; /* ID/NUMBER of List. -1 unassigned */
short subadr; /* SubAddress. -1 when not scheduled */
void *rt; /* Scheduled on Device */
struct gr1553rt_list_cfg *cfg; /* List configuration */
int bd_cnt; /* Number of Descriptors */
/* !!Must be last in data structure!!
/* !!Must be last in data structure!!
* !!Array must at least be of length bd_cnt!!
*/
unsigned short bds[0]; /* Array of BDIDs */
unsigned short bds[ 0 ]; /* Array of BDIDs */
};
/* GR1553B-RT Driver configuration options used when calling gr1553rt_config().
@@ -105,35 +105,35 @@ struct gr1553rt_list {
* into an address used by CPU.
*/
struct gr1553rt_cfg {
unsigned char rtaddress; /* RT Address 0..30 */
unsigned char rtaddress; /* RT Address 0..30 */
/*** MODE CODE CONFIG ***/
unsigned int modecode; /* Mode codes enable/disable/IRQ/EV-Log.
/*** MODE CODE CONFIG ***/
unsigned int modecode; /* Mode codes enable/disable/IRQ/EV-Log.
* Each modecode has a 2-bit cfg field.
* See Mode Code Control Register in
* hardware manual.
*/
/*** TIME CONFIG ***/
unsigned short time_res; /* Time tag resolution in us */
/*** TIME CONFIG ***/
unsigned short time_res; /* Time tag resolution in us */
/*** SUBADDRESS TABLE CONFIG ***/
void *satab_buffer; /* Optional Custom buffer. Must be
/*** SUBADDRESS TABLE CONFIG ***/
void *satab_buffer; /* Optional Custom buffer. Must be
* At least 16*32 bytes, and be aligned
* to 10-bit (1KB) boundary. Set to NULL
* to make driver allocate buffer.
*/
/*** EVENT LOG CONFIG ***/
void *evlog_buffer; /* Optional Custom buffer */
int evlog_size; /* Length, must be a multiple of 2.
/*** EVENT LOG CONFIG ***/
void *evlog_buffer; /* Optional Custom buffer */
int evlog_size; /* Length, must be a multiple of 2.
* If set to ZERO event log is disabled
*/
/*** TRANSFER DESCRIPTOR CONFIG ***/
int bd_count; /* Number of transfer descriptors shared
/*** TRANSFER DESCRIPTOR CONFIG ***/
int bd_count; /* Number of transfer descriptors shared
* by all RX/TX sub-addresses */
void *bd_buffer; /* Optional Custom descriptor area.
void *bd_buffer; /* Optional Custom descriptor area.
* Must hold bd_count*32 bytes.
* If NULL, descriptors will be
* allocated dynamically. */
@@ -143,13 +143,13 @@ struct gr1553rt_cfg {
* here. Used when calling the gr1553rt_status() function.
*/
struct gr1553rt_status {
unsigned int status; /* RT Status word */
unsigned int bus_status; /* BUS Status */
unsigned short synctime; /* Time Tag of last sync with data */
unsigned short syncword; /* Data of last mode code synchronize
unsigned int status; /* RT Status word */
unsigned int bus_status; /* BUS Status */
unsigned short synctime; /* Time Tag of last sync with data */
unsigned short syncword; /* Data of last mode code synchronize
* with data. */
unsigned short time_res; /* Time resolution (set by config) */
unsigned short time; /* Current Time Tag */
unsigned short time_res; /* Time resolution (set by config) */
unsigned short time; /* Current Time Tag */
};
/* ISR callback definition for ERRORs detected in the GR1553B-RT interrupt
@@ -160,7 +160,7 @@ struct gr1553rt_status {
* Bit 10 - RT Table access error
* \param data Custom data assigned by user
*/
typedef void (*gr1553rt_irqerr_t)(int err, void *data);
typedef void ( *gr1553rt_irqerr_t )( int err, void *data );
/* ISR callback definition for modecodes that are configured to generate
* an IRQ. The callback is called from within the GR1553B-RT interrupt
@@ -170,7 +170,11 @@ typedef void (*gr1553rt_irqerr_t)(int err, void *data);
* \param entry The raw Eventlog Entry
* \param data Custom data assigned by user
*/
typedef void (*gr1553rt_irqmc_t)(int mcode, unsigned int entry, void *data);
typedef void ( *gr1553rt_irqmc_t )(
int mcode,
unsigned int entry,
void *data
);
/* Transfer ISR callback definition. Called from GR1553B-RT interrupt handler
* when an interrupt has been generated and a event logged due to a 1553
@@ -182,12 +186,12 @@ typedef void (*gr1553rt_irqmc_t)(int mcode, unsigned int entry, void *data);
* This can be used to process all descriptors upto entry_next.
* \param data Custom data assigned by user
*/
typedef void (*gr1553rt_irq_t)(
struct gr1553rt_list *list,
unsigned int entry,
int bd_next,
void *data
);
typedef void ( *gr1553rt_irq_t )(
struct gr1553rt_list *list,
unsigned int entry,
int bd_next,
void *data
);
/* Configure a list according to configuration. Assign the list
* to a device, however not to a RT sub address yet. The rt
@@ -198,12 +202,11 @@ typedef void (*gr1553rt_irq_t)(
* \param cfg Configuration for list. Pointer to configuration is
* stored within list for later use.
*/
extern int gr1553rt_list_init
(
void *rt,
struct gr1553rt_list **plist,
struct gr1553rt_list_cfg *cfg
);
extern int gr1553rt_list_init(
void *rt,
struct gr1553rt_list **plist,
struct gr1553rt_list_cfg *cfg
);
/* Assign an Error Interrupt handler. Before the handler is called the
* RT hardware is stopped/disabled. The handler is optional, if not assigned
@@ -216,12 +219,7 @@ extern int gr1553rt_list_init
* \param func ISR called when an error causes an interrupt.
* \param data Custom data given as an argument when calling ISR
*/
extern int gr1553rt_irq_err
(
void *rt,
gr1553rt_irqerr_t func,
void *data
);
extern int gr1553rt_irq_err( void *rt, gr1553rt_irqerr_t func, void *data );
/* Assign a ModeCode Interrupt handler callback. Called when a 1553 modecode
* transfer is logged and cause an IRQ. The modecode IRQ generation is
@@ -230,12 +228,7 @@ extern int gr1553rt_irq_err
* \param func ISR called when a modecode causes an interrupt.
* \param data Custom data given as an argument when calling ISR
*/
extern int gr1553rt_irq_mc
(
void *rt,
gr1553rt_irqmc_t func,
void *data
);
extern int gr1553rt_irq_mc( void *rt, gr1553rt_irqmc_t func, void *data );
/* Assign transfer interrupt handler callback. Called when a RX or TX
* transfer is logged and cause an interrupt, the function is called
@@ -250,16 +243,15 @@ extern int gr1553rt_irq_mc
* causes an interrupt.
* \param data Custom data given as an argument when calling ISR
*/
extern int gr1553rt_irq_sa
(
void *rt,
int subadr,
int tx,
gr1553rt_irq_t func,
void *data
);
extern int gr1553rt_irq_sa(
void *rt,
int subadr,
int tx,
gr1553rt_irq_t func,
void *data
);
#define GR1553RT_BD_FLAGS_IRQEN (1<<30)
#define GR1553RT_BD_FLAGS_IRQEN ( 1 << 30 )
/* Initialize a descriptor entry in a list. This is typically done
* prior to scheduling the list.
*
@@ -276,12 +268,12 @@ extern int gr1553rt_irq_sa
* zero if entry_no is last descriptor in list (circular).
*/
extern int gr1553rt_bd_init(
struct gr1553rt_list *list,
unsigned short entry_no,
unsigned int flags,
uint16_t *dptr,
unsigned short next
);
struct gr1553rt_list *list,
unsigned short entry_no,
unsigned int flags,
uint16_t *dptr,
unsigned short next
);
/* Manipulate/Read Control/Status and Data Pointer words of a buffer descriptor.
* If status is zero, the control/status word is accessed. If dptr is non-zero
@@ -304,11 +296,11 @@ extern int gr1553rt_bd_init(
* OUT: The old data pointer is stored here.
*/
extern int gr1553rt_bd_update(
struct gr1553rt_list *list,
int entry_no,
unsigned int *status,
uint16_t **dptr
);
struct gr1553rt_list *list,
int entry_no,
unsigned int *status,
uint16_t **dptr
);
/* Get the next/current descriptor processed of a RT sub-address.
*
@@ -316,7 +308,7 @@ extern int gr1553rt_bd_update(
* \param txeno Pointer to where TX descriptor number is stored.
* \param rxeno Pointer to where RX descriptor number is stored.
*/
extern int gr1553rt_indication(void *rt, int subadr, int *txeno, int *rxeno);
extern int gr1553rt_indication( void *rt, int subadr, int *txeno, int *rxeno );
/* Take a GR1553RT hardware device identified by minor.
* A pointer is returned that is used internally by the GR1553RT
@@ -325,10 +317,10 @@ extern int gr1553rt_indication(void *rt, int subadr, int *txeno, int *rxeno);
*
* This function initializes the RT hardware to a stopped/disable level.
*/
extern void *gr1553rt_open(int minor);
extern void *gr1553rt_open( int minor );
/* Close and stop/disable the RT hardware. */
extern void gr1553rt_close(void *rt);
extern void gr1553rt_close( void *rt );
/* Configure the RT. The RT device must be configured once before
* started. A started RT device can not be configured.
@@ -336,7 +328,7 @@ extern void gr1553rt_close(void *rt);
* \param rt The RT to configure
* \param cfg Configuration parameters
*/
extern int gr1553rt_config(void *rt, struct gr1553rt_cfg *cfg);
extern int gr1553rt_config( void *rt, struct gr1553rt_cfg *cfg );
/* Schedule a RX or TX list on a sub address. If a list has already been
* schduled on the subaddress and on the same transfer type (RX/TX), the
@@ -347,11 +339,11 @@ extern int gr1553rt_config(void *rt, struct gr1553rt_cfg *cfg);
* \param list Preconfigued RT list scheduled
*/
extern void gr1553rt_sa_schedule(
void *rt,
int subadr,
int tx,
struct gr1553rt_list *list
);
void *rt,
int subadr,
int tx,
struct gr1553rt_list *list
);
/* Set SubAdress options. One may for example Enable or Disable a sub
* address RX and/or TX. See hardware manual for SA-Table configuration
@@ -363,11 +355,11 @@ extern void gr1553rt_sa_schedule(
*
*/
extern void gr1553rt_sa_setopts(
void *rt,
int subadr,
unsigned int mask,
unsigned int options
);
void *rt,
int subadr,
unsigned int mask,
unsigned int options
);
/* Get The Subaddress and transfer type of a scheduled list. Normally the
* application knows which subaddress the list is for.
@@ -377,10 +369,10 @@ extern void gr1553rt_sa_setopts(
* \param tx Transfer type is stored here. 1=TX, 0=RX.
*/
extern void gr1553rt_list_sa(
struct gr1553rt_list *list,
int *subadr,
int *tx
);
struct gr1553rt_list *list,
int *subadr,
int *tx
);
/* Start RT Communication
*
@@ -389,7 +381,7 @@ extern void gr1553rt_list_sa(
* RT to be stopped are no longer available. After the RT has been
* started the configuration function can not be called.
*/
extern int gr1553rt_start(void *rt);
extern int gr1553rt_start( void *rt );
/* Get Status of the RT core. See data structure gr1553rt_status for more
* information about the result. It can be used to read out:
@@ -400,12 +392,12 @@ extern int gr1553rt_start(void *rt);
* \param status Pointer to where the status words will be stored. They
* are stored according to the gr1553rt_status data structure.
*/
extern void gr1553rt_status(void *rt, struct gr1553rt_status *status);
extern void gr1553rt_status( void *rt, struct gr1553rt_status *status );
/* Stop RT communication. Only possible to stop an already started RT device.
* Interrupts are disabled and the RT Enable bit cleared.
*/
extern void gr1553rt_stop(void *rt);
extern void gr1553rt_stop( void *rt );
/* Set RT vector and/or bit word.
*
@@ -421,10 +413,10 @@ extern void gr1553rt_stop(void *rt);
* hw_words = (hw_words & ~mask) | (words & mask)
*/
extern void gr1553rt_set_vecword(
void *rt,
unsigned int mask,
unsigned int words
);
void *rt,
unsigned int mask,
unsigned int words
);
/* Set selectable bits of the "Bus Status Register". The bits written
* is determined by the "mask" bit-mask. Operation:
@@ -432,7 +424,11 @@ extern void gr1553rt_set_vecword(
* bus_status = (bus_status & ~mask) | (sts & mask)
*
*/
extern void gr1553rt_set_bussts(void *rt, unsigned int mask, unsigned int sts);
extern void gr1553rt_set_bussts(
void *rt,
unsigned int mask,
unsigned int sts
);
/* Read up to MAX number of entries in eventlog log.
*
@@ -444,7 +440,7 @@ extern void gr1553rt_set_bussts(void *rt, unsigned int mask, unsigned int sts);
* zero No entries available at the moment
* positive Number of entries copied into dst
*/
extern int gr1553rt_evlog_read(void *rt, unsigned int *dst, int max);
extern int gr1553rt_evlog_read( void *rt, unsigned int *dst, int max );
#ifdef __cplusplus
}
bsps/include/grlib/gr_701.h
+5 -5
View File
@@ -51,17 +51,17 @@ extern "C" {
*/
extern struct drvmgr_bus_res *gr701_resources[];
#define GR701_OPTIONS_AMBA 0x01
#define GR701_OPTIONS_IRQ 0x02
#define GR701_OPTIONS_AMBA 0x01
#define GR701_OPTIONS_IRQ 0x02
/* Print information about all GR-701 PCI boards */
void gr701_print(int options);
void gr701_print( int options );
/* Print information about one GR-701 PCI board */
void gr701_print_dev(struct drvmgr_dev *dev, int options);
void gr701_print_dev( struct drvmgr_dev *dev, int options );
/* Register GR-701 driver */
void gr701_register_drv(void);
void gr701_register_drv( void );
#ifdef __cplusplus
}
bsps/include/grlib/gr_cpci_gr740.h
+4 -4
View File
@@ -62,16 +62,16 @@ extern "C" {
extern struct drvmgr_bus_res *gr_cpci_gr740_resources[];
/* Options to gr_cpci_gr740_print function */
#define GR_CPCI_GR740_OPTIONS_AMBA 0x01 /* Print AMBA bus devices */
#define GR_CPCI_GR740_OPTIONS_AMBA 0x01 /* Print AMBA bus devices */
/* Print information about all GR-CPCI-GR740 PCI boards */
void gr_cpci_gr740_print(int options);
void gr_cpci_gr740_print( int options );
/* Print information about one GR-CPCI-GR740 PCI board */
void gr_cpci_gr740_print_dev(struct drvmgr_dev *dev, int options);
void gr_cpci_gr740_print_dev( struct drvmgr_dev *dev, int options );
/* Register GR-CPCI-GR740 driver */
void gr_cpci_gr740_register_drv(void);
void gr_cpci_gr740_register_drv( void );
#ifdef __cplusplus
}
bsps/include/grlib/gr_rasta_adcdac.h
+5 -5
View File
@@ -52,17 +52,17 @@ extern "C" {
extern struct drvmgr_bus_res *gr_rasta_adcdac_resources[];
/* Options to gr_rasta_io_print function */
#define RASTA_ADCDAC_OPTIONS_AMBA 0x01 /* Print AMBA bus devices */
#define RASTA_ADCDAC_OPTIONS_IRQ 0x02 /* Print current IRQ setup */
#define RASTA_ADCDAC_OPTIONS_AMBA 0x01 /* Print AMBA bus devices */
#define RASTA_ADCDAC_OPTIONS_IRQ 0x02 /* Print current IRQ setup */
/* Print information about all GR-RASTA-IO PCI boards */
void gr_rasta_adcdac_print(int options);
void gr_rasta_adcdac_print( int options );
/* Print information about one GR-RASTA-IO PCI board */
void gr_rasta_adcdac_print_dev(struct drvmgr_dev *dev, int options);
void gr_rasta_adcdac_print_dev( struct drvmgr_dev *dev, int options );
/* Register GR-RASTA-IO driver */
void gr_rasta_adcdac_register_drv(void);
void gr_rasta_adcdac_register_drv( void );
#ifdef __cplusplus
}
bsps/include/grlib/gr_rasta_io.h
+5 -5
View File
@@ -52,17 +52,17 @@ extern "C" {
extern struct drvmgr_bus_res *gr_rasta_io_resources[];
/* Options to gr_rasta_io_print function */
#define RASTA_IO_OPTIONS_AMBA 0x01 /* Print AMBA bus devices */
#define RASTA_IO_OPTIONS_IRQ 0x02 /* Print current IRQ setup */
#define RASTA_IO_OPTIONS_AMBA 0x01 /* Print AMBA bus devices */
#define RASTA_IO_OPTIONS_IRQ 0x02 /* Print current IRQ setup */
/* Print information about GR-RASTA-IO PCI boards */
void gr_rasta_io_print(int options);
void gr_rasta_io_print( int options );
/* Print information about a GR-RASTA-IO PCI board */
void gr_rasta_io_print_dev(struct drvmgr_dev *dev, int options);
void gr_rasta_io_print_dev( struct drvmgr_dev *dev, int options );
/* Register GR-RASTA-IO driver */
void gr_rasta_io_register_drv(void);
void gr_rasta_io_register_drv( void );
#ifdef __cplusplus
}
bsps/include/grlib/gr_rasta_spw_router.h
+5 -5
View File
@@ -48,17 +48,17 @@ extern "C" {
extern struct drvmgr_bus_res *gr_rasta_spw_router_resources[];
/* Options to gr_rasta_spw_router_print function */
#define RASTA_SPW_ROUTER_OPTIONS_AMBA 0x01 /* Print AMBA bus devices */
#define RASTA_SPW_ROUTER_OPTIONS_IRQ 0x02 /* Print current IRQ setup */
#define RASTA_SPW_ROUTER_OPTIONS_AMBA 0x01 /* Print AMBA bus devices */
#define RASTA_SPW_ROUTER_OPTIONS_IRQ 0x02 /* Print current IRQ setup */
/* Print information about all GR-CPCI-LEON4-N2X PCI boards */
void gr_rasta_spw_router_print(int options);
void gr_rasta_spw_router_print( int options );
/* Print information about one GR-CPCI-LEON4-N2X PCI board */
void gr_rasta_spw_router_print_dev(struct drvmgr_dev *dev, int options);
void gr_rasta_spw_router_print_dev( struct drvmgr_dev *dev, int options );
/* Register GR-RASTA-SPW-ROUTER driver to Driver Manager */
void gr_rasta_spw_router_register_drv(void);
void gr_rasta_spw_router_register_drv( void );
#ifdef __cplusplus
}
bsps/include/grlib/gr_rasta_tmtc.h
+28 -28
View File
@@ -69,29 +69,29 @@ extern "C" {
* -- 9 : 0 SpaceCraft ID
*/
#define GR_TMTC_GPIO_PWRX (1<<31)
#define GR_TMTC_GPIO_PWTC (1<<30)
#define GR_TMTC_GPIO_RED_TM (1<<29)
#define GR_TMTC_GPIO_RED_TC (1<<28)
#define GR_TMTC_GPIO_GRTM_SEL (1<<27)
#define GR_TMTC_GPIO_LB_PW (1<<26)
#define GR_TMTC_GPIO_TRANSP_CLK (1<<25)
#define GR_TMTC_GPIO_PWTX_SEL (1<<24)
#define GR_TMTC_GPIO_PDEC_MAP (1<<23)
#define GR_TMTC_GPIO_PDEC_CPDU (1<<22)
#define GR_TMTC_GPIO_PDEC_SU (1<<21)
#define GR_TMTC_GPIO_PDEC_RM (1<<20)
#define GR_TMTC_GPIO_PDEC_AU (1<<19)
#define GR_TMTC_GPIO_PDEC_DYN_MODE (1<<18)
#define GR_TMTC_GPIO_PDEC_PRIO (1<<17)
#define GR_TMTC_GPIO_TC_PSS (1<<16)
#define GR_TMTC_GPIO_TC_MARK (1<<15)
#define GR_TMTC_GPIO_TC_PSEUDO (1<<14)
#define GR_TMTC_GPIO_TC_RISING_CLK (1<<13)
#define GR_TMTC_GPIO_TC_ACTIVE_HIGH (1<<12)
#define GR_TMTC_GPIO_TC_BIT_LOCK (1<<11)
#define GR_TMTC_GPIO_TC_RF_AVAIL (1<<10)
#define GR_TMTC_GPIO_SCID (0x000003ff)
#define GR_TMTC_GPIO_PWRX ( 1 << 31 )
#define GR_TMTC_GPIO_PWTC ( 1 << 30 )
#define GR_TMTC_GPIO_RED_TM ( 1 << 29 )
#define GR_TMTC_GPIO_RED_TC ( 1 << 28 )
#define GR_TMTC_GPIO_GRTM_SEL ( 1 << 27 )
#define GR_TMTC_GPIO_LB_PW ( 1 << 26 )
#define GR_TMTC_GPIO_TRANSP_CLK ( 1 << 25 )
#define GR_TMTC_GPIO_PWTX_SEL ( 1 << 24 )
#define GR_TMTC_GPIO_PDEC_MAP ( 1 << 23 )
#define GR_TMTC_GPIO_PDEC_CPDU ( 1 << 22 )
#define GR_TMTC_GPIO_PDEC_SU ( 1 << 21 )
#define GR_TMTC_GPIO_PDEC_RM ( 1 << 20 )
#define GR_TMTC_GPIO_PDEC_AU ( 1 << 19 )
#define GR_TMTC_GPIO_PDEC_DYN_MODE ( 1 << 18 )
#define GR_TMTC_GPIO_PDEC_PRIO ( 1 << 17 )
#define GR_TMTC_GPIO_TC_PSS ( 1 << 16 )
#define GR_TMTC_GPIO_TC_MARK ( 1 << 15 )
#define GR_TMTC_GPIO_TC_PSEUDO ( 1 << 14 )
#define GR_TMTC_GPIO_TC_RISING_CLK ( 1 << 13 )
#define GR_TMTC_GPIO_TC_ACTIVE_HIGH ( 1 << 12 )
#define GR_TMTC_GPIO_TC_BIT_LOCK ( 1 << 11 )
#define GR_TMTC_GPIO_TC_RF_AVAIL ( 1 << 10 )
#define GR_TMTC_GPIO_SCID ( 0x000003ff )
/* An array of pointers to GR-RASTA-TMTC bus resources. The resources will be
* used by the device drivers controlling the cores on the GR-RASTA-IO target
@@ -103,17 +103,17 @@ extern "C" {
extern struct drvmgr_bus_res *gr_rasta_tmtc_resources[];
/* Options to gr_rasta_io_print function */
#define RASTA_TMTC_OPTIONS_AMBA 0x01 /* Print AMBA bus devices */
#define RASTA_TMTC_OPTIONS_IRQ 0x02 /* Print current IRQ setup */
#define RASTA_TMTC_OPTIONS_AMBA 0x01 /* Print AMBA bus devices */
#define RASTA_TMTC_OPTIONS_IRQ 0x02 /* Print current IRQ setup */
/* Print information about GR-RASTA-TMTC PCI boards */
void gr_rasta_tmtc_print(int options);
void gr_rasta_tmtc_print( int options );
/* Print information about a GR-RASTA-TMTC PCI boards */
void gr_rasta_tmtc_print_dev(struct drvmgr_dev *dev, int options);
void gr_rasta_tmtc_print_dev( struct drvmgr_dev *dev, int options );
/* Register GR-RASTA-TMTC driver */
void gr_rasta_tmtc_register_drv(void);
void gr_rasta_tmtc_register_drv( void );
#ifdef __cplusplus
}
bsps/include/grlib/gr_tmtc_1553.h
+6 -6
View File
@@ -52,20 +52,20 @@ extern "C" {
extern struct drvmgr_bus_res *gr_tmtc_1553_resources[];
/* Options to gr_rasta_io_print function */
#define TMTC_1553_OPTIONS_AMBA 0x01 /* Print AMBA bus devices */
#define TMTC_1553_OPTIONS_IRQ 0x02 /* Print current IRQ setup */
#define TMTC_1553_OPTIONS_AMBA 0x01 /* Print AMBA bus devices */
#define TMTC_1553_OPTIONS_IRQ 0x02 /* Print current IRQ setup */
/* Print information about GR-RASTA-IO PCI board */
void gr_tmtc_1553_print(int options);
void gr_tmtc_1553_print( int options );
/* Register GR-RASTA-IO driver */
void gr_tmtc_1553_register_drv(void);
void gr_tmtc_1553_register_drv( void );
/* Print information about all GR-TMTC-1553 devices registered to this driver */
void gr_tmtc_1553_print(int options);
void gr_tmtc_1553_print( int options );
/* Print information about one GR-TMTC-1553 device */
void gr_tmtc_1553_print_dev(struct drvmgr_dev *dev, int options);
void gr_tmtc_1553_print_dev( struct drvmgr_dev *dev, int options );
#ifdef __cplusplus
}
bsps/include/grlib/gradcdac.h
+93 -83
View File
@@ -35,19 +35,19 @@ extern "C" {
#endif
struct gradcdac_regs {
volatile uint32_t config; /* 0x00 Configuration Register */
volatile uint32_t status; /* 0x04 Status Register */
uint32_t unused0[2];
volatile uint32_t adc_din; /* 0x10 ADC Data Input Register */
volatile uint32_t dac_dout; /* 0x14 DAC Data Output Register */
uint32_t unused1[2];
volatile uint32_t adrin; /* 0x20 Address Input Register */
volatile uint32_t adrout; /* 0x24 Address Output Register */
volatile uint32_t adrdir; /* 0x28 Address Direction Register */
uint32_t unused2[1];
volatile uint32_t data_in; /* 0x30 Data Input Register */
volatile uint32_t data_out; /* 0x34 Data Output Register */
volatile uint32_t data_dir; /* 0x38 Data Direction Register */
volatile uint32_t config; /* 0x00 Configuration Register */
volatile uint32_t status; /* 0x04 Status Register */
uint32_t unused0[ 2 ];
volatile uint32_t adc_din; /* 0x10 ADC Data Input Register */
volatile uint32_t dac_dout; /* 0x14 DAC Data Output Register */
uint32_t unused1[ 2 ];
volatile uint32_t adrin; /* 0x20 Address Input Register */
volatile uint32_t adrout; /* 0x24 Address Output Register */
volatile uint32_t adrdir; /* 0x28 Address Direction Register */
uint32_t unused2[ 1 ];
volatile uint32_t data_in; /* 0x30 Data Input Register */
volatile uint32_t data_out; /* 0x34 Data Output Register */
volatile uint32_t data_dir; /* 0x38 Data Direction Register */
};
#define GRADCDAC_CFG_DACWS 0x00f80000
@@ -68,21 +68,21 @@ struct gradcdac_regs {
#define GRADCDAC_CFG_DACDW_BIT 16
#define GRADCDAC_CFG_ADCWS_BIT 11
#define GRADCDAC_CFG_RCPOL_BIT 10
#define GRADCDAC_CFG_CSMODE_BIT 8
#define GRADCDAC_CFG_CSPOL_BIT 7
#define GRADCDAC_CFG_RDYMODE_BIT 6
#define GRADCDAC_CFG_RDYPOL_BIT 5
#define GRADCDAC_CFG_TRIGPOL_BIT 4
#define GRADCDAC_CFG_TRIGMODE_BIT 2
#define GRADCDAC_CFG_ADCDW_BIT 0
#define GRADCDAC_CFG_CSMODE_BIT 8
#define GRADCDAC_CFG_CSPOL_BIT 7
#define GRADCDAC_CFG_RDYMODE_BIT 6
#define GRADCDAC_CFG_RDYPOL_BIT 5
#define GRADCDAC_CFG_TRIGPOL_BIT 4
#define GRADCDAC_CFG_TRIGMODE_BIT 2
#define GRADCDAC_CFG_ADCDW_BIT 0
#define GRADCDAC_STATUS_DACNO 0x40
#define GRADCDAC_STATUS_DACRDY 0x20
#define GRADCDAC_STATUS_DACON 0x10
#define GRADCDAC_STATUS_ADCTO 0x08
#define GRADCDAC_STATUS_ADCNO 0x04
#define GRADCDAC_STATUS_ADCRDY 0x02
#define GRADCDAC_STATUS_ADCON 0x01
#define GRADCDAC_STATUS_DACNO 0x40
#define GRADCDAC_STATUS_DACRDY 0x20
#define GRADCDAC_STATUS_DACON 0x10
#define GRADCDAC_STATUS_ADCTO 0x08
#define GRADCDAC_STATUS_ADCNO 0x04
#define GRADCDAC_STATUS_ADCRDY 0x02
#define GRADCDAC_STATUS_ADCON 0x01
#define GRADCDAC_STATUS_DACNO_BIT 6
#define GRADCDAC_STATUS_DACRDY_BIT 5
@@ -96,70 +96,70 @@ struct gradcdac_regs {
#define GRADCDAC_IRQ_ADC 0
struct gradcdac_config {
unsigned char dac_ws;
char wr_pol;
unsigned char dac_dw;
unsigned char adc_ws;
char rc_pol;
unsigned char cs_mode;
char cs_pol;
char ready_mode;
char ready_pol;
char trigg_pol;
unsigned char trigg_mode;
unsigned char adc_dw;
unsigned char dac_ws;
char wr_pol;
unsigned char dac_dw;
unsigned char adc_ws;
char rc_pol;
unsigned char cs_mode;
char cs_pol;
char ready_mode;
char ready_pol;
char trigg_pol;
unsigned char trigg_mode;
unsigned char adc_dw;
};
extern void *gradcdac_open(char *devname);
extern void *gradcdac_open( char *devname );
extern void gradcdac_set_config(void *cookie, struct gradcdac_config *cfg);
extern void gradcdac_set_config( void *cookie, struct gradcdac_config *cfg );
extern void gradcdac_get_config(void *cookie, struct gradcdac_config *cfg);
extern void gradcdac_get_config( void *cookie, struct gradcdac_config *cfg );
extern void gradcdac_set_cfg(void *cookie, unsigned int config);
extern void gradcdac_set_cfg( void *cookie, unsigned int config );
extern unsigned int gradcdac_get_cfg(void *cookie);
extern unsigned int gradcdac_get_cfg( void *cookie );
extern unsigned int gradcdac_get_status(void *cookie);
extern unsigned int gradcdac_get_status( void *cookie );
static __inline__ int gradcdac_DAC_ReqRej(unsigned int status)
static __inline__ int gradcdac_DAC_ReqRej( unsigned int status )
{
return (status & GRADCDAC_STATUS_DACNO);
return ( status & GRADCDAC_STATUS_DACNO );
}
static __inline__ int gradcdac_DAC_isCompleted(unsigned int status)
static __inline__ int gradcdac_DAC_isCompleted( unsigned int status )
{
return (status & GRADCDAC_STATUS_DACRDY);
return ( status & GRADCDAC_STATUS_DACRDY );
}
static __inline__ int gradcdac_DAC_isOngoing(unsigned int status)
static __inline__ int gradcdac_DAC_isOngoing( unsigned int status )
{
return (status & GRADCDAC_STATUS_DACON);
return ( status & GRADCDAC_STATUS_DACON );
}
static __inline__ int gradcdac_ADC_isTimeouted(unsigned int status)
static __inline__ int gradcdac_ADC_isTimeouted( unsigned int status )
{
return (status & GRADCDAC_STATUS_ADCTO);
return ( status & GRADCDAC_STATUS_ADCTO );
}
static __inline__ int gradcdac_ADC_ReqRej(unsigned int status)
static __inline__ int gradcdac_ADC_ReqRej( unsigned int status )
{
return (status & GRADCDAC_STATUS_ADCNO);
return ( status & GRADCDAC_STATUS_ADCNO );
}
static __inline__ int gradcdac_ADC_isCompleted(unsigned int status)
static __inline__ int gradcdac_ADC_isCompleted( unsigned int status )
{
return (status & GRADCDAC_STATUS_ADCRDY);
return ( status & GRADCDAC_STATUS_ADCRDY );
}
static __inline__ int gradcdac_ADC_isOngoing(unsigned int status)
static __inline__ int gradcdac_ADC_isOngoing( unsigned int status )
{
return (status & GRADCDAC_STATUS_ADCON);
return ( status & GRADCDAC_STATUS_ADCON );
}
#define GRADCDAC_ISR_BOTH 3
#define GRADCDAC_ISR_DAC 2
#define GRADCDAC_ISR_ADC 1
#define GRADCDAC_ISR_DAC 2
#define GRADCDAC_ISR_ADC 1
/* Install IRQ handler for ADC and/or DAC interrupt.
* The installed IRQ handler(ISR) must read the status
@@ -170,16 +170,20 @@ static __inline__ int gradcdac_ADC_isOngoing(unsigned int status)
* \param isr Interrupt service routine called when IRQ is fired
* \param arg custom argument passed to ISR when called.
*/
extern int gradcdac_install_irq_handler
(void *cookie, int adc, void (*isr)(void *cookie, void *arg), void *arg);
extern int gradcdac_install_irq_handler(
void *cookie,
int adc,
void ( *isr )( void *cookie, void *arg ),
void *arg
);
extern void gradcdac_uninstall_irq_handler(void *cookie, int adc);
extern void gradcdac_uninstall_irq_handler( void *cookie, int adc );
/* Make the ADC circuitry initialize a analogue to digital
* conversion. The result can be read out by gradcdac_adc_convert_try
* or gradcdac_adc_convert.
*/
extern void gradcdac_adc_convert_start(void *cookie);
extern void gradcdac_adc_convert_start( void *cookie );
/* Tries to read the conversion result. If the circuitry is busy
* converting the function return a non-zero value, if the conversion
@@ -190,7 +194,10 @@ extern void gradcdac_adc_convert_start(void *cookie);
* positive = ADC busy, digital_value contain previous conversion result
* negative = Conversion request failed.
*/
extern int gradcdac_adc_convert_try(void *cookie, unsigned short *digital_value);
extern int gradcdac_adc_convert_try(
void *cookie,
unsigned short *digital_value
);
/* Waits until the ADC circuity has finished a digital to analogue
* conversion. The Waiting is implemented as a busy loop utilizing
@@ -199,45 +206,48 @@ extern int gradcdac_adc_convert_try(void *cookie, unsigned short *digital_value)
* \return zero = Conversion ok
* negative = Conversion request failed.
*/
extern int gradcdac_adc_convert(void *cookie, unsigned short *digital_value);
extern int gradcdac_adc_convert( void *cookie, unsigned short *digital_value );
/* Try to make the DAC circuitry initialize a digital to analogue
* conversion. If the circuitry is busy by a previous conversion
* the function return a non-zero value, if the conversion is
* successfully initialized the function return zero.
*/
extern int gradcdac_dac_convert_try(void *cookie, unsigned short digital_value);
extern int gradcdac_dac_convert_try(
void *cookie,
unsigned short digital_value
);
/* Initializes a digital to analogue conversion by waiting until
* previous conversions is finished before procceding with the
* conversion. The Waiting is implemented as a busy loop utilizing
* 100% CPU load.
*/
extern void gradcdac_dac_convert(void *cookie, unsigned short digital_value);
extern void gradcdac_dac_convert( void *cookie, unsigned short digital_value );
extern unsigned int gradcdac_get_adrinput(void *cookie);
extern void gradcdac_set_adrinput(void *cookie, unsigned int input);
extern unsigned int gradcdac_get_adrinput( void *cookie );
extern void gradcdac_set_adrinput( void *cookie, unsigned int input );
extern unsigned int gradcdac_get_adroutput(void *cookie);
extern void gradcdac_set_adroutput(void *cookie, unsigned int output);
extern unsigned int gradcdac_get_adroutput( void *cookie );
extern void gradcdac_set_adroutput( void *cookie, unsigned int output );
extern unsigned int gradcdac_get_adrdir(void *cookie);
extern void gradcdac_set_adrdir(void *cookie, unsigned int dir);
extern unsigned int gradcdac_get_adrdir( void *cookie );
extern void gradcdac_set_adrdir( void *cookie, unsigned int dir );
extern unsigned int gradcdac_get_datainput(void *cookie);
extern void gradcdac_set_datainput(void *cookie, unsigned int input);
extern unsigned int gradcdac_get_datainput( void *cookie );
extern void gradcdac_set_datainput( void *cookie, unsigned int input );
extern unsigned int gradcdac_get_dataoutput(void *cookie);
extern void gradcdac_set_dataoutput(void *cookie, unsigned int output);
extern unsigned int gradcdac_get_dataoutput( void *cookie );
extern void gradcdac_set_dataoutput( void *cookie, unsigned int output );
extern unsigned int gradcdac_get_datadir(void *cookie);
extern void gradcdac_set_datadir(void *cookie, unsigned int dir);
extern unsigned int gradcdac_get_datadir( void *cookie );
extern void gradcdac_set_datadir( void *cookie, unsigned int dir );
/* Show one or all GRADCDAC cores. If cookie is NULL all GRADCDAC's are shown */
extern void grAdcDacShow(void *cookie);
extern void grAdcDacShow( void *cookie );
/* Register Driver routine */
extern void gradcdac_register_drv (void);
extern void gradcdac_register_drv( void );
#ifdef __cplusplus
}
bsps/include/grlib/grascs.h
+36 -35
View File
@@ -41,68 +41,69 @@ extern "C" {
/* Default, minimum and maximum ETR pulse frequency */
#define GRASCS_DEFAULT_ETRFREQ 10
#define GRASCS_MIN_ETRFREQ 1
#define GRASCS_MAX_ETRFREQ 100
#define GRASCS_MIN_ETRFREQ 1
#define GRASCS_MAX_ETRFREQ 100
/* Maximum number of external time markers */
#define GRASCS_MAX_TMS 6
/* Error codes */
#define GRASCS_ERROR_STARTSTOP 1 /* Serial/synch interface is running/stopped */
#define GRASCS_ERROR_STARTSTOP \
1 /* Serial/synch interface is running/stopped */
#define GRASCS_ERROR_TRANSACTIVE 2 /* Busy with transaction */
#define GRASCS_ERROR_CAPFAULT 3 /* Core capabilities prohibit request */
#define GRASCS_ERROR_CAPFAULT 3 /* Core capabilities prohibit request */
/* Command register */
#define GRASCS_CMD_RESET (1 << 0)
#define GRASCS_CMD_STARTSTOP (1 << 1)
#define GRASCS_CMD_ESTARTSTOP (1 << 2)
#define GRASCS_CMD_SENDTM (1 << 3)
#define GRASCS_CMD_ETRCTRL (7 << 4)
#define GRASCS_CMD_ETRCTRL_BITS 4
#define GRASCS_CMD_SLAVESEL (15 << 8)
#define GRASCS_CMD_RESET ( 1 << 0 )
#define GRASCS_CMD_STARTSTOP ( 1 << 1 )
#define GRASCS_CMD_ESTARTSTOP ( 1 << 2 )
#define GRASCS_CMD_SENDTM ( 1 << 3 )
#define GRASCS_CMD_ETRCTRL ( 7 << 4 )
#define GRASCS_CMD_ETRCTRL_BITS 4
#define GRASCS_CMD_SLAVESEL ( 15 << 8 )
#define GRASCS_CMD_SLAVESEL_BITS 8
#define GRASCS_CMD_TCDONE (1 << 12)
#define GRASCS_CMD_TMDONE (1 << 13)
#define GRASCS_CMD_US1 (255 << 16)
#define GRASCS_CMD_US1_BITS 16
#define GRASCS_CMD_US1C (1 << 24)
#define GRASCS_CMD_TCDONE ( 1 << 12 )
#define GRASCS_CMD_TMDONE ( 1 << 13 )
#define GRASCS_CMD_US1 ( 255 << 16 )
#define GRASCS_CMD_US1_BITS 16
#define GRASCS_CMD_US1C ( 1 << 24 )
/* Clock scale register */
#define GRASCS_CLK_ETRFREQ_BITS 12
/* Status register */
#define GRASCS_STS_RUNNING (1 << 0)
#define GRASCS_STS_ERUNNING (1 << 1)
#define GRASCS_STS_TCDONE (1 << 4)
#define GRASCS_STS_TMDONE (1 << 5)
#define GRASCS_STS_DBITS_BITS 8
#define GRASCS_STS_RUNNING ( 1 << 0 )
#define GRASCS_STS_ERUNNING ( 1 << 1 )
#define GRASCS_STS_TCDONE ( 1 << 4 )
#define GRASCS_STS_TMDONE ( 1 << 5 )
#define GRASCS_STS_DBITS_BITS 8
#define GRASCS_STS_NSLAVES_BITS 13
#define GRASCS_STS_USCONF_BITS 18
#define GRASCS_STS_TMCONF_BITS 19
#define GRASCS_STS_USCONF_BITS 18
#define GRASCS_STS_TMCONF_BITS 19
extern int ASCS_init(void);
extern int ASCS_init( void );
extern int ASCS_input_select(int slave);
extern int ASCS_input_select( int slave );
extern int ASCS_etr_select(int etr, int freq);
extern int ASCS_etr_select( int etr, int freq );
extern void ASCS_start(void);
extern void ASCS_start( void );
extern void ASCS_stop(void);
extern void ASCS_stop( void );
extern int ASCS_iface_status(void);
extern int ASCS_iface_status( void );
extern int ASCS_TC_send(int *word);
extern int ASCS_TC_send( int *word );
extern int ASCS_TC_send_block(int *block, int ntrans);
extern int ASCS_TC_send_block( int *block, int ntrans );
extern void ASCS_TC_sync_start(void);
extern void ASCS_TC_sync_start( void );
extern void ASCS_TC_sync_stop(void);
extern void ASCS_TC_sync_stop( void );
extern int ASCS_TM_recv(int *word);
extern int ASCS_TM_recv( int *word );
extern int ASCS_TM_recv_block(int *block, int ntrans);
extern int ASCS_TM_recv_block( int *block, int ntrans );
#ifdef __cplusplus
}
bsps/include/grlib/grcan-regs.h
+115 -165
View File
@@ -82,69 +82,55 @@ extern "C" {
*/
#define GRCAN_CANCONF_SCALER_SHIFT 24
#define GRCAN_CANCONF_SCALER_MASK 0xff000000U
#define GRCAN_CANCONF_SCALER_MASK 0xff000000U
#define GRCAN_CANCONF_SCALER_GET( _reg ) \
( ( ( _reg ) & GRCAN_CANCONF_SCALER_MASK ) >> \
GRCAN_CANCONF_SCALER_SHIFT )
#define GRCAN_CANCONF_SCALER_SET( _reg, _val ) \
( ( ( _reg ) & ~GRCAN_CANCONF_SCALER_MASK ) | \
( ( ( _reg ) & GRCAN_CANCONF_SCALER_MASK ) >> GRCAN_CANCONF_SCALER_SHIFT )
#define GRCAN_CANCONF_SCALER_SET( _reg, _val ) \
( ( ( _reg ) & ~GRCAN_CANCONF_SCALER_MASK ) | \
( ( ( _val ) << GRCAN_CANCONF_SCALER_SHIFT ) & \
GRCAN_CANCONF_SCALER_MASK ) )
#define GRCAN_CANCONF_SCALER( _val ) \
( ( ( _val ) << GRCAN_CANCONF_SCALER_SHIFT ) & \
GRCAN_CANCONF_SCALER_MASK )
( ( ( _val ) << GRCAN_CANCONF_SCALER_SHIFT ) & GRCAN_CANCONF_SCALER_MASK )
#define GRCAN_CANCONF_PS1_SHIFT 20
#define GRCAN_CANCONF_PS1_MASK 0xf00000U
#define GRCAN_CANCONF_PS1_MASK 0xf00000U
#define GRCAN_CANCONF_PS1_GET( _reg ) \
( ( ( _reg ) & GRCAN_CANCONF_PS1_MASK ) >> \
GRCAN_CANCONF_PS1_SHIFT )
#define GRCAN_CANCONF_PS1_SET( _reg, _val ) \
( ( ( _reg ) & GRCAN_CANCONF_PS1_MASK ) >> GRCAN_CANCONF_PS1_SHIFT )
#define GRCAN_CANCONF_PS1_SET( _reg, _val ) \
( ( ( _reg ) & ~GRCAN_CANCONF_PS1_MASK ) | \
( ( ( _val ) << GRCAN_CANCONF_PS1_SHIFT ) & \
GRCAN_CANCONF_PS1_MASK ) )
( ( ( _val ) << GRCAN_CANCONF_PS1_SHIFT ) & GRCAN_CANCONF_PS1_MASK ) )
#define GRCAN_CANCONF_PS1( _val ) \
( ( ( _val ) << GRCAN_CANCONF_PS1_SHIFT ) & \
GRCAN_CANCONF_PS1_MASK )
( ( ( _val ) << GRCAN_CANCONF_PS1_SHIFT ) & GRCAN_CANCONF_PS1_MASK )
#define GRCAN_CANCONF_PS2_SHIFT 16
#define GRCAN_CANCONF_PS2_MASK 0xf0000U
#define GRCAN_CANCONF_PS2_MASK 0xf0000U
#define GRCAN_CANCONF_PS2_GET( _reg ) \
( ( ( _reg ) & GRCAN_CANCONF_PS2_MASK ) >> \
GRCAN_CANCONF_PS2_SHIFT )
#define GRCAN_CANCONF_PS2_SET( _reg, _val ) \
( ( ( _reg ) & GRCAN_CANCONF_PS2_MASK ) >> GRCAN_CANCONF_PS2_SHIFT )
#define GRCAN_CANCONF_PS2_SET( _reg, _val ) \
( ( ( _reg ) & ~GRCAN_CANCONF_PS2_MASK ) | \
( ( ( _val ) << GRCAN_CANCONF_PS2_SHIFT ) & \
GRCAN_CANCONF_PS2_MASK ) )
( ( ( _val ) << GRCAN_CANCONF_PS2_SHIFT ) & GRCAN_CANCONF_PS2_MASK ) )
#define GRCAN_CANCONF_PS2( _val ) \
( ( ( _val ) << GRCAN_CANCONF_PS2_SHIFT ) & \
GRCAN_CANCONF_PS2_MASK )
( ( ( _val ) << GRCAN_CANCONF_PS2_SHIFT ) & GRCAN_CANCONF_PS2_MASK )
#define GRCAN_CANCONF_RSJ_SHIFT 12
#define GRCAN_CANCONF_RSJ_MASK 0x7000U
#define GRCAN_CANCONF_RSJ_MASK 0x7000U
#define GRCAN_CANCONF_RSJ_GET( _reg ) \
( ( ( _reg ) & GRCAN_CANCONF_RSJ_MASK ) >> \
GRCAN_CANCONF_RSJ_SHIFT )
#define GRCAN_CANCONF_RSJ_SET( _reg, _val ) \
( ( ( _reg ) & GRCAN_CANCONF_RSJ_MASK ) >> GRCAN_CANCONF_RSJ_SHIFT )
#define GRCAN_CANCONF_RSJ_SET( _reg, _val ) \
( ( ( _reg ) & ~GRCAN_CANCONF_RSJ_MASK ) | \
( ( ( _val ) << GRCAN_CANCONF_RSJ_SHIFT ) & \
GRCAN_CANCONF_RSJ_MASK ) )
( ( ( _val ) << GRCAN_CANCONF_RSJ_SHIFT ) & GRCAN_CANCONF_RSJ_MASK ) )
#define GRCAN_CANCONF_RSJ( _val ) \
( ( ( _val ) << GRCAN_CANCONF_RSJ_SHIFT ) & \
GRCAN_CANCONF_RSJ_MASK )
( ( ( _val ) << GRCAN_CANCONF_RSJ_SHIFT ) & GRCAN_CANCONF_RSJ_MASK )
#define GRCAN_CANCONF_BPR_SHIFT 8
#define GRCAN_CANCONF_BPR_MASK 0x300U
#define GRCAN_CANCONF_BPR_MASK 0x300U
#define GRCAN_CANCONF_BPR_GET( _reg ) \
( ( ( _reg ) & GRCAN_CANCONF_BPR_MASK ) >> \
GRCAN_CANCONF_BPR_SHIFT )
#define GRCAN_CANCONF_BPR_SET( _reg, _val ) \
( ( ( _reg ) & GRCAN_CANCONF_BPR_MASK ) >> GRCAN_CANCONF_BPR_SHIFT )
#define GRCAN_CANCONF_BPR_SET( _reg, _val ) \
( ( ( _reg ) & ~GRCAN_CANCONF_BPR_MASK ) | \
( ( ( _val ) << GRCAN_CANCONF_BPR_SHIFT ) & \
GRCAN_CANCONF_BPR_MASK ) )
( ( ( _val ) << GRCAN_CANCONF_BPR_SHIFT ) & GRCAN_CANCONF_BPR_MASK ) )
#define GRCAN_CANCONF_BPR( _val ) \
( ( ( _val ) << GRCAN_CANCONF_BPR_SHIFT ) & \
GRCAN_CANCONF_BPR_MASK )
( ( ( _val ) << GRCAN_CANCONF_BPR_SHIFT ) & GRCAN_CANCONF_BPR_MASK )
#define GRCAN_CANCONF_SAM 0x20U
@@ -169,54 +155,54 @@ extern "C" {
*/
#define GRCAN_CANSTAT_TXCHANNELS_SHIFT 28
#define GRCAN_CANSTAT_TXCHANNELS_MASK 0xf0000000U
#define GRCAN_CANSTAT_TXCHANNELS_GET( _reg ) \
#define GRCAN_CANSTAT_TXCHANNELS_MASK 0xf0000000U
#define GRCAN_CANSTAT_TXCHANNELS_GET( _reg ) \
( ( ( _reg ) & GRCAN_CANSTAT_TXCHANNELS_MASK ) >> \
GRCAN_CANSTAT_TXCHANNELS_SHIFT )
#define GRCAN_CANSTAT_TXCHANNELS_SET( _reg, _val ) \
( ( ( _reg ) & ~GRCAN_CANSTAT_TXCHANNELS_MASK ) | \
#define GRCAN_CANSTAT_TXCHANNELS_SET( _reg, _val ) \
( ( ( _reg ) & ~GRCAN_CANSTAT_TXCHANNELS_MASK ) | \
( ( ( _val ) << GRCAN_CANSTAT_TXCHANNELS_SHIFT ) & \
GRCAN_CANSTAT_TXCHANNELS_MASK ) )
#define GRCAN_CANSTAT_TXCHANNELS( _val ) \
#define GRCAN_CANSTAT_TXCHANNELS( _val ) \
( ( ( _val ) << GRCAN_CANSTAT_TXCHANNELS_SHIFT ) & \
GRCAN_CANSTAT_TXCHANNELS_MASK )
#define GRCAN_CANSTAT_RXCHANNELS_SHIFT 24
#define GRCAN_CANSTAT_RXCHANNELS_MASK 0xf000000U
#define GRCAN_CANSTAT_RXCHANNELS_GET( _reg ) \
#define GRCAN_CANSTAT_RXCHANNELS_MASK 0xf000000U
#define GRCAN_CANSTAT_RXCHANNELS_GET( _reg ) \
( ( ( _reg ) & GRCAN_CANSTAT_RXCHANNELS_MASK ) >> \
GRCAN_CANSTAT_RXCHANNELS_SHIFT )
#define GRCAN_CANSTAT_RXCHANNELS_SET( _reg, _val ) \
( ( ( _reg ) & ~GRCAN_CANSTAT_RXCHANNELS_MASK ) | \
#define GRCAN_CANSTAT_RXCHANNELS_SET( _reg, _val ) \
( ( ( _reg ) & ~GRCAN_CANSTAT_RXCHANNELS_MASK ) | \
( ( ( _val ) << GRCAN_CANSTAT_RXCHANNELS_SHIFT ) & \
GRCAN_CANSTAT_RXCHANNELS_MASK ) )
#define GRCAN_CANSTAT_RXCHANNELS( _val ) \
#define GRCAN_CANSTAT_RXCHANNELS( _val ) \
( ( ( _val ) << GRCAN_CANSTAT_RXCHANNELS_SHIFT ) & \
GRCAN_CANSTAT_RXCHANNELS_MASK )
#define GRCAN_CANSTAT_TXERRCNT_SHIFT 16
#define GRCAN_CANSTAT_TXERRCNT_MASK 0xff0000U
#define GRCAN_CANSTAT_TXERRCNT_GET( _reg ) \
#define GRCAN_CANSTAT_TXERRCNT_MASK 0xff0000U
#define GRCAN_CANSTAT_TXERRCNT_GET( _reg ) \
( ( ( _reg ) & GRCAN_CANSTAT_TXERRCNT_MASK ) >> \
GRCAN_CANSTAT_TXERRCNT_SHIFT )
#define GRCAN_CANSTAT_TXERRCNT_SET( _reg, _val ) \
( ( ( _reg ) & ~GRCAN_CANSTAT_TXERRCNT_MASK ) | \
#define GRCAN_CANSTAT_TXERRCNT_SET( _reg, _val ) \
( ( ( _reg ) & ~GRCAN_CANSTAT_TXERRCNT_MASK ) | \
( ( ( _val ) << GRCAN_CANSTAT_TXERRCNT_SHIFT ) & \
GRCAN_CANSTAT_TXERRCNT_MASK ) )
#define GRCAN_CANSTAT_TXERRCNT( _val ) \
#define GRCAN_CANSTAT_TXERRCNT( _val ) \
( ( ( _val ) << GRCAN_CANSTAT_TXERRCNT_SHIFT ) & \
GRCAN_CANSTAT_TXERRCNT_MASK )
#define GRCAN_CANSTAT_RXERRCNT_SHIFT 8
#define GRCAN_CANSTAT_RXERRCNT_MASK 0xff00U
#define GRCAN_CANSTAT_RXERRCNT_GET( _reg ) \
#define GRCAN_CANSTAT_RXERRCNT_MASK 0xff00U
#define GRCAN_CANSTAT_RXERRCNT_GET( _reg ) \
( ( ( _reg ) & GRCAN_CANSTAT_RXERRCNT_MASK ) >> \
GRCAN_CANSTAT_RXERRCNT_SHIFT )
#define GRCAN_CANSTAT_RXERRCNT_SET( _reg, _val ) \
( ( ( _reg ) & ~GRCAN_CANSTAT_RXERRCNT_MASK ) | \
#define GRCAN_CANSTAT_RXERRCNT_SET( _reg, _val ) \
( ( ( _reg ) & ~GRCAN_CANSTAT_RXERRCNT_MASK ) | \
( ( ( _val ) << GRCAN_CANSTAT_RXERRCNT_SHIFT ) & \
GRCAN_CANSTAT_RXERRCNT_MASK ) )
#define GRCAN_CANSTAT_RXERRCNT( _val ) \
#define GRCAN_CANSTAT_RXERRCNT( _val ) \
( ( ( _val ) << GRCAN_CANSTAT_RXERRCNT_SHIFT ) & \
GRCAN_CANSTAT_RXERRCNT_MASK )
@@ -255,17 +241,14 @@ extern "C" {
*/
#define GRCAN_CANMASK_MASK_SHIFT 0
#define GRCAN_CANMASK_MASK_MASK 0x1fffffffU
#define GRCAN_CANMASK_MASK_MASK 0x1fffffffU
#define GRCAN_CANMASK_MASK_GET( _reg ) \
( ( ( _reg ) & GRCAN_CANMASK_MASK_MASK ) >> \
GRCAN_CANMASK_MASK_SHIFT )
#define GRCAN_CANMASK_MASK_SET( _reg, _val ) \
( ( ( _reg ) & GRCAN_CANMASK_MASK_MASK ) >> GRCAN_CANMASK_MASK_SHIFT )
#define GRCAN_CANMASK_MASK_SET( _reg, _val ) \
( ( ( _reg ) & ~GRCAN_CANMASK_MASK_MASK ) | \
( ( ( _val ) << GRCAN_CANMASK_MASK_SHIFT ) & \
GRCAN_CANMASK_MASK_MASK ) )
( ( ( _val ) << GRCAN_CANMASK_MASK_SHIFT ) & GRCAN_CANMASK_MASK_MASK ) )
#define GRCAN_CANMASK_MASK( _val ) \
( ( ( _val ) << GRCAN_CANMASK_MASK_SHIFT ) & \
GRCAN_CANMASK_MASK_MASK )
( ( ( _val ) << GRCAN_CANMASK_MASK_SHIFT ) & GRCAN_CANMASK_MASK_MASK )
/** @} */
@@ -278,17 +261,14 @@ extern "C" {
*/
#define GRCAN_CANCODE_SYNC_SHIFT 0
#define GRCAN_CANCODE_SYNC_MASK 0x1fffffffU
#define GRCAN_CANCODE_SYNC_MASK 0x1fffffffU
#define GRCAN_CANCODE_SYNC_GET( _reg ) \
( ( ( _reg ) & GRCAN_CANCODE_SYNC_MASK ) >> \
GRCAN_CANCODE_SYNC_SHIFT )
#define GRCAN_CANCODE_SYNC_SET( _reg, _val ) \
( ( ( _reg ) & GRCAN_CANCODE_SYNC_MASK ) >> GRCAN_CANCODE_SYNC_SHIFT )
#define GRCAN_CANCODE_SYNC_SET( _reg, _val ) \
( ( ( _reg ) & ~GRCAN_CANCODE_SYNC_MASK ) | \
( ( ( _val ) << GRCAN_CANCODE_SYNC_SHIFT ) & \
GRCAN_CANCODE_SYNC_MASK ) )
( ( ( _val ) << GRCAN_CANCODE_SYNC_SHIFT ) & GRCAN_CANCODE_SYNC_MASK ) )
#define GRCAN_CANCODE_SYNC( _val ) \
( ( ( _val ) << GRCAN_CANCODE_SYNC_SHIFT ) & \
GRCAN_CANCODE_SYNC_MASK )
( ( ( _val ) << GRCAN_CANCODE_SYNC_SHIFT ) & GRCAN_CANCODE_SYNC_MASK )
/** @} */
@@ -319,17 +299,15 @@ extern "C" {
*/
#define GRCAN_CANTXADDR_ADDR_SHIFT 10
#define GRCAN_CANTXADDR_ADDR_MASK 0xfffffc00U
#define GRCAN_CANTXADDR_ADDR_MASK 0xfffffc00U
#define GRCAN_CANTXADDR_ADDR_GET( _reg ) \
( ( ( _reg ) & GRCAN_CANTXADDR_ADDR_MASK ) >> \
GRCAN_CANTXADDR_ADDR_SHIFT )
#define GRCAN_CANTXADDR_ADDR_SET( _reg, _val ) \
( ( ( _reg ) & ~GRCAN_CANTXADDR_ADDR_MASK ) | \
( ( ( _reg ) & GRCAN_CANTXADDR_ADDR_MASK ) >> GRCAN_CANTXADDR_ADDR_SHIFT )
#define GRCAN_CANTXADDR_ADDR_SET( _reg, _val ) \
( ( ( _reg ) & ~GRCAN_CANTXADDR_ADDR_MASK ) | \
( ( ( _val ) << GRCAN_CANTXADDR_ADDR_SHIFT ) & \
GRCAN_CANTXADDR_ADDR_MASK ) )
#define GRCAN_CANTXADDR_ADDR( _val ) \
( ( ( _val ) << GRCAN_CANTXADDR_ADDR_SHIFT ) & \
GRCAN_CANTXADDR_ADDR_MASK )
( ( ( _val ) << GRCAN_CANTXADDR_ADDR_SHIFT ) & GRCAN_CANTXADDR_ADDR_MASK )
/** @} */
@@ -343,17 +321,15 @@ extern "C" {
*/
#define GRCAN_CANTXSIZE_SIZE_SHIFT 6
#define GRCAN_CANTXSIZE_SIZE_MASK 0x1fffc0U
#define GRCAN_CANTXSIZE_SIZE_MASK 0x1fffc0U
#define GRCAN_CANTXSIZE_SIZE_GET( _reg ) \
( ( ( _reg ) & GRCAN_CANTXSIZE_SIZE_MASK ) >> \
GRCAN_CANTXSIZE_SIZE_SHIFT )
#define GRCAN_CANTXSIZE_SIZE_SET( _reg, _val ) \
( ( ( _reg ) & ~GRCAN_CANTXSIZE_SIZE_MASK ) | \
( ( ( _reg ) & GRCAN_CANTXSIZE_SIZE_MASK ) >> GRCAN_CANTXSIZE_SIZE_SHIFT )
#define GRCAN_CANTXSIZE_SIZE_SET( _reg, _val ) \
( ( ( _reg ) & ~GRCAN_CANTXSIZE_SIZE_MASK ) | \
( ( ( _val ) << GRCAN_CANTXSIZE_SIZE_SHIFT ) & \
GRCAN_CANTXSIZE_SIZE_MASK ) )
#define GRCAN_CANTXSIZE_SIZE( _val ) \
( ( ( _val ) << GRCAN_CANTXSIZE_SIZE_SHIFT ) & \
GRCAN_CANTXSIZE_SIZE_MASK )
( ( ( _val ) << GRCAN_CANTXSIZE_SIZE_SHIFT ) & GRCAN_CANTXSIZE_SIZE_MASK )
/** @} */
@@ -366,17 +342,15 @@ extern "C" {
*/
#define GRCAN_CANTXWR_WRITE_SHIFT 4
#define GRCAN_CANTXWR_WRITE_MASK 0xffff0U
#define GRCAN_CANTXWR_WRITE_MASK 0xffff0U
#define GRCAN_CANTXWR_WRITE_GET( _reg ) \
( ( ( _reg ) & GRCAN_CANTXWR_WRITE_MASK ) >> \
GRCAN_CANTXWR_WRITE_SHIFT )
#define GRCAN_CANTXWR_WRITE_SET( _reg, _val ) \
( ( ( _reg ) & ~GRCAN_CANTXWR_WRITE_MASK ) | \
( ( ( _reg ) & GRCAN_CANTXWR_WRITE_MASK ) >> GRCAN_CANTXWR_WRITE_SHIFT )
#define GRCAN_CANTXWR_WRITE_SET( _reg, _val ) \
( ( ( _reg ) & ~GRCAN_CANTXWR_WRITE_MASK ) | \
( ( ( _val ) << GRCAN_CANTXWR_WRITE_SHIFT ) & \
GRCAN_CANTXWR_WRITE_MASK ) )
#define GRCAN_CANTXWR_WRITE( _val ) \
( ( ( _val ) << GRCAN_CANTXWR_WRITE_SHIFT ) & \
GRCAN_CANTXWR_WRITE_MASK )
( ( ( _val ) << GRCAN_CANTXWR_WRITE_SHIFT ) & GRCAN_CANTXWR_WRITE_MASK )
/** @} */
@@ -389,17 +363,14 @@ extern "C" {
*/
#define GRCAN_CANTXRD_READ_SHIFT 4
#define GRCAN_CANTXRD_READ_MASK 0xffff0U
#define GRCAN_CANTXRD_READ_MASK 0xffff0U
#define GRCAN_CANTXRD_READ_GET( _reg ) \
( ( ( _reg ) & GRCAN_CANTXRD_READ_MASK ) >> \
GRCAN_CANTXRD_READ_SHIFT )
#define GRCAN_CANTXRD_READ_SET( _reg, _val ) \
( ( ( _reg ) & GRCAN_CANTXRD_READ_MASK ) >> GRCAN_CANTXRD_READ_SHIFT )
#define GRCAN_CANTXRD_READ_SET( _reg, _val ) \
( ( ( _reg ) & ~GRCAN_CANTXRD_READ_MASK ) | \
( ( ( _val ) << GRCAN_CANTXRD_READ_SHIFT ) & \
GRCAN_CANTXRD_READ_MASK ) )
( ( ( _val ) << GRCAN_CANTXRD_READ_SHIFT ) & GRCAN_CANTXRD_READ_MASK ) )
#define GRCAN_CANTXRD_READ( _val ) \
( ( ( _val ) << GRCAN_CANTXRD_READ_SHIFT ) & \
GRCAN_CANTXRD_READ_MASK )
( ( ( _val ) << GRCAN_CANTXRD_READ_SHIFT ) & GRCAN_CANTXRD_READ_MASK )
/** @} */
@@ -413,17 +384,14 @@ extern "C" {
*/
#define GRCAN_CANTXIRQ_IRQ_SHIFT 4
#define GRCAN_CANTXIRQ_IRQ_MASK 0xffff0U
#define GRCAN_CANTXIRQ_IRQ_MASK 0xffff0U
#define GRCAN_CANTXIRQ_IRQ_GET( _reg ) \
( ( ( _reg ) & GRCAN_CANTXIRQ_IRQ_MASK ) >> \
GRCAN_CANTXIRQ_IRQ_SHIFT )
#define GRCAN_CANTXIRQ_IRQ_SET( _reg, _val ) \
( ( ( _reg ) & GRCAN_CANTXIRQ_IRQ_MASK ) >> GRCAN_CANTXIRQ_IRQ_SHIFT )
#define GRCAN_CANTXIRQ_IRQ_SET( _reg, _val ) \
( ( ( _reg ) & ~GRCAN_CANTXIRQ_IRQ_MASK ) | \
( ( ( _val ) << GRCAN_CANTXIRQ_IRQ_SHIFT ) & \
GRCAN_CANTXIRQ_IRQ_MASK ) )
( ( ( _val ) << GRCAN_CANTXIRQ_IRQ_SHIFT ) & GRCAN_CANTXIRQ_IRQ_MASK ) )
#define GRCAN_CANTXIRQ_IRQ( _val ) \
( ( ( _val ) << GRCAN_CANTXIRQ_IRQ_SHIFT ) & \
GRCAN_CANTXIRQ_IRQ_MASK )
( ( ( _val ) << GRCAN_CANTXIRQ_IRQ_SHIFT ) & GRCAN_CANTXIRQ_IRQ_MASK )
/** @} */
@@ -452,17 +420,15 @@ extern "C" {
*/
#define GRCAN_CANRXADDR_ADDR_SHIFT 10
#define GRCAN_CANRXADDR_ADDR_MASK 0xfffffc00U
#define GRCAN_CANRXADDR_ADDR_MASK 0xfffffc00U
#define GRCAN_CANRXADDR_ADDR_GET( _reg ) \
( ( ( _reg ) & GRCAN_CANRXADDR_ADDR_MASK ) >> \
GRCAN_CANRXADDR_ADDR_SHIFT )
#define GRCAN_CANRXADDR_ADDR_SET( _reg, _val ) \
( ( ( _reg ) & ~GRCAN_CANRXADDR_ADDR_MASK ) | \
( ( ( _reg ) & GRCAN_CANRXADDR_ADDR_MASK ) >> GRCAN_CANRXADDR_ADDR_SHIFT )
#define GRCAN_CANRXADDR_ADDR_SET( _reg, _val ) \
( ( ( _reg ) & ~GRCAN_CANRXADDR_ADDR_MASK ) | \
( ( ( _val ) << GRCAN_CANRXADDR_ADDR_SHIFT ) & \
GRCAN_CANRXADDR_ADDR_MASK ) )
#define GRCAN_CANRXADDR_ADDR( _val ) \
( ( ( _val ) << GRCAN_CANRXADDR_ADDR_SHIFT ) & \
GRCAN_CANRXADDR_ADDR_MASK )
( ( ( _val ) << GRCAN_CANRXADDR_ADDR_SHIFT ) & GRCAN_CANRXADDR_ADDR_MASK )
/** @} */
@@ -476,17 +442,15 @@ extern "C" {
*/
#define GRCAN_CANRXSIZE_SIZE_SHIFT 6
#define GRCAN_CANRXSIZE_SIZE_MASK 0x1fffc0U
#define GRCAN_CANRXSIZE_SIZE_MASK 0x1fffc0U
#define GRCAN_CANRXSIZE_SIZE_GET( _reg ) \
( ( ( _reg ) & GRCAN_CANRXSIZE_SIZE_MASK ) >> \
GRCAN_CANRXSIZE_SIZE_SHIFT )
#define GRCAN_CANRXSIZE_SIZE_SET( _reg, _val ) \
( ( ( _reg ) & ~GRCAN_CANRXSIZE_SIZE_MASK ) | \
( ( ( _reg ) & GRCAN_CANRXSIZE_SIZE_MASK ) >> GRCAN_CANRXSIZE_SIZE_SHIFT )
#define GRCAN_CANRXSIZE_SIZE_SET( _reg, _val ) \
( ( ( _reg ) & ~GRCAN_CANRXSIZE_SIZE_MASK ) | \
( ( ( _val ) << GRCAN_CANRXSIZE_SIZE_SHIFT ) & \
GRCAN_CANRXSIZE_SIZE_MASK ) )
#define GRCAN_CANRXSIZE_SIZE( _val ) \
( ( ( _val ) << GRCAN_CANRXSIZE_SIZE_SHIFT ) & \
GRCAN_CANRXSIZE_SIZE_MASK )
( ( ( _val ) << GRCAN_CANRXSIZE_SIZE_SHIFT ) & GRCAN_CANRXSIZE_SIZE_MASK )
/** @} */
@@ -499,17 +463,15 @@ extern "C" {
*/
#define GRCAN_CANRXWR_WRITE_SHIFT 4
#define GRCAN_CANRXWR_WRITE_MASK 0xffff0U
#define GRCAN_CANRXWR_WRITE_MASK 0xffff0U
#define GRCAN_CANRXWR_WRITE_GET( _reg ) \
( ( ( _reg ) & GRCAN_CANRXWR_WRITE_MASK ) >> \
GRCAN_CANRXWR_WRITE_SHIFT )
#define GRCAN_CANRXWR_WRITE_SET( _reg, _val ) \
( ( ( _reg ) & ~GRCAN_CANRXWR_WRITE_MASK ) | \
( ( ( _reg ) & GRCAN_CANRXWR_WRITE_MASK ) >> GRCAN_CANRXWR_WRITE_SHIFT )
#define GRCAN_CANRXWR_WRITE_SET( _reg, _val ) \
( ( ( _reg ) & ~GRCAN_CANRXWR_WRITE_MASK ) | \
( ( ( _val ) << GRCAN_CANRXWR_WRITE_SHIFT ) & \
GRCAN_CANRXWR_WRITE_MASK ) )
#define GRCAN_CANRXWR_WRITE( _val ) \
( ( ( _val ) << GRCAN_CANRXWR_WRITE_SHIFT ) & \
GRCAN_CANRXWR_WRITE_MASK )
( ( ( _val ) << GRCAN_CANRXWR_WRITE_SHIFT ) & GRCAN_CANRXWR_WRITE_MASK )
/** @} */
@@ -522,17 +484,14 @@ extern "C" {
*/
#define GRCAN_CANRXRD_READ_SHIFT 4
#define GRCAN_CANRXRD_READ_MASK 0xffff0U
#define GRCAN_CANRXRD_READ_MASK 0xffff0U
#define GRCAN_CANRXRD_READ_GET( _reg ) \
( ( ( _reg ) & GRCAN_CANRXRD_READ_MASK ) >> \
GRCAN_CANRXRD_READ_SHIFT )
#define GRCAN_CANRXRD_READ_SET( _reg, _val ) \
( ( ( _reg ) & GRCAN_CANRXRD_READ_MASK ) >> GRCAN_CANRXRD_READ_SHIFT )
#define GRCAN_CANRXRD_READ_SET( _reg, _val ) \
( ( ( _reg ) & ~GRCAN_CANRXRD_READ_MASK ) | \
( ( ( _val ) << GRCAN_CANRXRD_READ_SHIFT ) & \
GRCAN_CANRXRD_READ_MASK ) )
( ( ( _val ) << GRCAN_CANRXRD_READ_SHIFT ) & GRCAN_CANRXRD_READ_MASK ) )
#define GRCAN_CANRXRD_READ( _val ) \
( ( ( _val ) << GRCAN_CANRXRD_READ_SHIFT ) & \
GRCAN_CANRXRD_READ_MASK )
( ( ( _val ) << GRCAN_CANRXRD_READ_SHIFT ) & GRCAN_CANRXRD_READ_MASK )
/** @} */
@@ -546,17 +505,14 @@ extern "C" {
*/
#define GRCAN_CANRXIRQ_IRQ_SHIFT 4
#define GRCAN_CANRXIRQ_IRQ_MASK 0xffff0U
#define GRCAN_CANRXIRQ_IRQ_MASK 0xffff0U
#define GRCAN_CANRXIRQ_IRQ_GET( _reg ) \
( ( ( _reg ) & GRCAN_CANRXIRQ_IRQ_MASK ) >> \
GRCAN_CANRXIRQ_IRQ_SHIFT )
#define GRCAN_CANRXIRQ_IRQ_SET( _reg, _val ) \
( ( ( _reg ) & GRCAN_CANRXIRQ_IRQ_MASK ) >> GRCAN_CANRXIRQ_IRQ_SHIFT )
#define GRCAN_CANRXIRQ_IRQ_SET( _reg, _val ) \
( ( ( _reg ) & ~GRCAN_CANRXIRQ_IRQ_MASK ) | \
( ( ( _val ) << GRCAN_CANRXIRQ_IRQ_SHIFT ) & \
GRCAN_CANRXIRQ_IRQ_MASK ) )
( ( ( _val ) << GRCAN_CANRXIRQ_IRQ_SHIFT ) & GRCAN_CANRXIRQ_IRQ_MASK ) )
#define GRCAN_CANRXIRQ_IRQ( _val ) \
( ( ( _val ) << GRCAN_CANRXIRQ_IRQ_SHIFT ) & \
GRCAN_CANRXIRQ_IRQ_MASK )
( ( ( _val ) << GRCAN_CANRXIRQ_IRQ_SHIFT ) & GRCAN_CANRXIRQ_IRQ_MASK )
/** @} */
@@ -570,17 +526,14 @@ extern "C" {
*/
#define GRCAN_CANRXMASK_AM_SHIFT 0
#define GRCAN_CANRXMASK_AM_MASK 0x1fffffffU
#define GRCAN_CANRXMASK_AM_MASK 0x1fffffffU
#define GRCAN_CANRXMASK_AM_GET( _reg ) \
( ( ( _reg ) & GRCAN_CANRXMASK_AM_MASK ) >> \
GRCAN_CANRXMASK_AM_SHIFT )
#define GRCAN_CANRXMASK_AM_SET( _reg, _val ) \
( ( ( _reg ) & GRCAN_CANRXMASK_AM_MASK ) >> GRCAN_CANRXMASK_AM_SHIFT )
#define GRCAN_CANRXMASK_AM_SET( _reg, _val ) \
( ( ( _reg ) & ~GRCAN_CANRXMASK_AM_MASK ) | \
( ( ( _val ) << GRCAN_CANRXMASK_AM_SHIFT ) & \
GRCAN_CANRXMASK_AM_MASK ) )
( ( ( _val ) << GRCAN_CANRXMASK_AM_SHIFT ) & GRCAN_CANRXMASK_AM_MASK ) )
#define GRCAN_CANRXMASK_AM( _val ) \
( ( ( _val ) << GRCAN_CANRXMASK_AM_SHIFT ) & \
GRCAN_CANRXMASK_AM_MASK )
( ( ( _val ) << GRCAN_CANRXMASK_AM_SHIFT ) & GRCAN_CANRXMASK_AM_MASK )
/** @} */
@@ -594,17 +547,14 @@ extern "C" {
*/
#define GRCAN_CANRXCODE_AC_SHIFT 0
#define GRCAN_CANRXCODE_AC_MASK 0x1fffffffU
#define GRCAN_CANRXCODE_AC_MASK 0x1fffffffU
#define GRCAN_CANRXCODE_AC_GET( _reg ) \
( ( ( _reg ) & GRCAN_CANRXCODE_AC_MASK ) >> \
GRCAN_CANRXCODE_AC_SHIFT )
#define GRCAN_CANRXCODE_AC_SET( _reg, _val ) \
( ( ( _reg ) & GRCAN_CANRXCODE_AC_MASK ) >> GRCAN_CANRXCODE_AC_SHIFT )
#define GRCAN_CANRXCODE_AC_SET( _reg, _val ) \
( ( ( _reg ) & ~GRCAN_CANRXCODE_AC_MASK ) | \
( ( ( _val ) << GRCAN_CANRXCODE_AC_SHIFT ) & \
GRCAN_CANRXCODE_AC_MASK ) )
( ( ( _val ) << GRCAN_CANRXCODE_AC_SHIFT ) & GRCAN_CANRXCODE_AC_MASK ) )
#define GRCAN_CANRXCODE_AC( _val ) \
( ( ( _val ) << GRCAN_CANRXCODE_AC_SHIFT ) & \
GRCAN_CANRXCODE_AC_MASK )
( ( ( _val ) << GRCAN_CANRXCODE_AC_SHIFT ) & GRCAN_CANRXCODE_AC_MASK )
/** @} */
bsps/include/grlib/grcan.h
+170 -181
View File
File diff suppressed because it is too large Load Diff
bsps/include/grlib/grclkgate-regs.h
+25 -27
View File
@@ -82,15 +82,15 @@ extern "C" {
*/
#define GRCLKGATE_UNLOCK_UNLOCK_SHIFT 0
#define GRCLKGATE_UNLOCK_UNLOCK_MASK 0xffffffffU
#define GRCLKGATE_UNLOCK_UNLOCK_GET( _reg ) \
#define GRCLKGATE_UNLOCK_UNLOCK_MASK 0xffffffffU
#define GRCLKGATE_UNLOCK_UNLOCK_GET( _reg ) \
( ( ( _reg ) & GRCLKGATE_UNLOCK_UNLOCK_MASK ) >> \
GRCLKGATE_UNLOCK_UNLOCK_SHIFT )
#define GRCLKGATE_UNLOCK_UNLOCK_SET( _reg, _val ) \
( ( ( _reg ) & ~GRCLKGATE_UNLOCK_UNLOCK_MASK ) | \
#define GRCLKGATE_UNLOCK_UNLOCK_SET( _reg, _val ) \
( ( ( _reg ) & ~GRCLKGATE_UNLOCK_UNLOCK_MASK ) | \
( ( ( _val ) << GRCLKGATE_UNLOCK_UNLOCK_SHIFT ) & \
GRCLKGATE_UNLOCK_UNLOCK_MASK ) )
#define GRCLKGATE_UNLOCK_UNLOCK( _val ) \
#define GRCLKGATE_UNLOCK_UNLOCK( _val ) \
( ( ( _val ) << GRCLKGATE_UNLOCK_UNLOCK_SHIFT ) & \
GRCLKGATE_UNLOCK_UNLOCK_MASK )
@@ -105,15 +105,15 @@ extern "C" {
*/
#define GRCLKGATE_CLKEN_ENABLE_SHIFT 0
#define GRCLKGATE_CLKEN_ENABLE_MASK 0xffffffffU
#define GRCLKGATE_CLKEN_ENABLE_GET( _reg ) \
#define GRCLKGATE_CLKEN_ENABLE_MASK 0xffffffffU
#define GRCLKGATE_CLKEN_ENABLE_GET( _reg ) \
( ( ( _reg ) & GRCLKGATE_CLKEN_ENABLE_MASK ) >> \
GRCLKGATE_CLKEN_ENABLE_SHIFT )
#define GRCLKGATE_CLKEN_ENABLE_SET( _reg, _val ) \
( ( ( _reg ) & ~GRCLKGATE_CLKEN_ENABLE_MASK ) | \
#define GRCLKGATE_CLKEN_ENABLE_SET( _reg, _val ) \
( ( ( _reg ) & ~GRCLKGATE_CLKEN_ENABLE_MASK ) | \
( ( ( _val ) << GRCLKGATE_CLKEN_ENABLE_SHIFT ) & \
GRCLKGATE_CLKEN_ENABLE_MASK ) )
#define GRCLKGATE_CLKEN_ENABLE( _val ) \
#define GRCLKGATE_CLKEN_ENABLE( _val ) \
( ( ( _val ) << GRCLKGATE_CLKEN_ENABLE_SHIFT ) & \
GRCLKGATE_CLKEN_ENABLE_MASK )
@@ -128,17 +128,15 @@ extern "C" {
*/
#define GRCLKGATE_RESET_RESET_SHIFT 0
#define GRCLKGATE_RESET_RESET_MASK 0xffffffffU
#define GRCLKGATE_RESET_RESET_MASK 0xffffffffU
#define GRCLKGATE_RESET_RESET_GET( _reg ) \
( ( ( _reg ) & GRCLKGATE_RESET_RESET_MASK ) >> \
GRCLKGATE_RESET_RESET_SHIFT )
#define GRCLKGATE_RESET_RESET_SET( _reg, _val ) \
( ( ( _reg ) & ~GRCLKGATE_RESET_RESET_MASK ) | \
( ( ( _reg ) & GRCLKGATE_RESET_RESET_MASK ) >> GRCLKGATE_RESET_RESET_SHIFT )
#define GRCLKGATE_RESET_RESET_SET( _reg, _val ) \
( ( ( _reg ) & ~GRCLKGATE_RESET_RESET_MASK ) | \
( ( ( _val ) << GRCLKGATE_RESET_RESET_SHIFT ) & \
GRCLKGATE_RESET_RESET_MASK ) )
#define GRCLKGATE_RESET_RESET( _val ) \
( ( ( _val ) << GRCLKGATE_RESET_RESET_SHIFT ) & \
GRCLKGATE_RESET_RESET_MASK )
( ( ( _val ) << GRCLKGATE_RESET_RESET_SHIFT ) & GRCLKGATE_RESET_RESET_MASK )
/** @} */
@@ -151,28 +149,28 @@ extern "C" {
*/
#define GRCLKGATE_OVERRIDE_FOVERRIDE_SHIFT 16
#define GRCLKGATE_OVERRIDE_FOVERRIDE_MASK 0xf0000U
#define GRCLKGATE_OVERRIDE_FOVERRIDE_GET( _reg ) \
#define GRCLKGATE_OVERRIDE_FOVERRIDE_MASK 0xf0000U
#define GRCLKGATE_OVERRIDE_FOVERRIDE_GET( _reg ) \
( ( ( _reg ) & GRCLKGATE_OVERRIDE_FOVERRIDE_MASK ) >> \
GRCLKGATE_OVERRIDE_FOVERRIDE_SHIFT )
#define GRCLKGATE_OVERRIDE_FOVERRIDE_SET( _reg, _val ) \
( ( ( _reg ) & ~GRCLKGATE_OVERRIDE_FOVERRIDE_MASK ) | \
#define GRCLKGATE_OVERRIDE_FOVERRIDE_SET( _reg, _val ) \
( ( ( _reg ) & ~GRCLKGATE_OVERRIDE_FOVERRIDE_MASK ) | \
( ( ( _val ) << GRCLKGATE_OVERRIDE_FOVERRIDE_SHIFT ) & \
GRCLKGATE_OVERRIDE_FOVERRIDE_MASK ) )
#define GRCLKGATE_OVERRIDE_FOVERRIDE( _val ) \
#define GRCLKGATE_OVERRIDE_FOVERRIDE( _val ) \
( ( ( _val ) << GRCLKGATE_OVERRIDE_FOVERRIDE_SHIFT ) & \
GRCLKGATE_OVERRIDE_FOVERRIDE_MASK )
#define GRCLKGATE_OVERRIDE_OVERRIDE_SHIFT 0
#define GRCLKGATE_OVERRIDE_OVERRIDE_MASK 0xfU
#define GRCLKGATE_OVERRIDE_OVERRIDE_GET( _reg ) \
#define GRCLKGATE_OVERRIDE_OVERRIDE_MASK 0xfU
#define GRCLKGATE_OVERRIDE_OVERRIDE_GET( _reg ) \
( ( ( _reg ) & GRCLKGATE_OVERRIDE_OVERRIDE_MASK ) >> \
GRCLKGATE_OVERRIDE_OVERRIDE_SHIFT )
#define GRCLKGATE_OVERRIDE_OVERRIDE_SET( _reg, _val ) \
( ( ( _reg ) & ~GRCLKGATE_OVERRIDE_OVERRIDE_MASK ) | \
#define GRCLKGATE_OVERRIDE_OVERRIDE_SET( _reg, _val ) \
( ( ( _reg ) & ~GRCLKGATE_OVERRIDE_OVERRIDE_MASK ) | \
( ( ( _val ) << GRCLKGATE_OVERRIDE_OVERRIDE_SHIFT ) & \
GRCLKGATE_OVERRIDE_OVERRIDE_MASK ) )
#define GRCLKGATE_OVERRIDE_OVERRIDE( _val ) \
#define GRCLKGATE_OVERRIDE_OVERRIDE( _val ) \
( ( ( _val ) << GRCLKGATE_OVERRIDE_OVERRIDE_SHIFT ) & \
GRCLKGATE_OVERRIDE_OVERRIDE_MASK )
bsps/include/grlib/grctm.h
+86 -80
View File
@@ -30,161 +30,167 @@
#ifndef __GRCTM_H__
#define __GRCTM_H__
#define DAT0_IRQ 0x1
#define DAT1_IRQ 0x2
#define DAT2_IRQ 0x4
#define PULSE0_IRQ 0x10
#define PULSE1_IRQ 0x20
#define PULSE2_IRQ 0x40
#define PULSE3_IRQ 0x80
#define PULSE4_IRQ 0x100
#define PULSE5_IRQ 0x200
#define PULSE6_IRQ 0x400
#define PULSE7_IRQ 0x800
#define DAT0_IRQ 0x1
#define DAT1_IRQ 0x2
#define DAT2_IRQ 0x4
#define PULSE0_IRQ 0x10
#define PULSE1_IRQ 0x20
#define PULSE2_IRQ 0x40
#define PULSE3_IRQ 0x80
#define PULSE4_IRQ 0x100
#define PULSE5_IRQ 0x200
#define PULSE6_IRQ 0x400
#define PULSE7_IRQ 0x800
struct grctm_regs {
volatile uint32_t grr;
volatile uint32_t gcr;
volatile uint32_t gsr;
volatile uint32_t unused[2];
volatile uint32_t pfr;
volatile uint32_t etcr;
volatile uint32_t etfr;
volatile uint32_t dcr0;
volatile uint32_t dfr0;
volatile uint32_t dcr1;
volatile uint32_t dfr1;
volatile uint32_t dcr2;
volatile uint32_t dfr2;
volatile uint32_t stcr;
volatile uint32_t stfr;
volatile uint32_t pdr[8];
volatile uint32_t pimsr;
volatile uint32_t pimr;
volatile uint32_t pisr;
volatile uint32_t pir;
volatile uint32_t imr;
volatile uint32_t picr;
volatile uint32_t unused1[2];
volatile uint32_t etir;
volatile uint32_t fsir;
volatile uint32_t serconf;
volatile uint32_t unused2;
volatile uint32_t twsc;
volatile uint32_t twadj;
volatile uint32_t twtx;
volatile uint32_t twrx;
volatile uint32_t grr;
volatile uint32_t gcr;
volatile uint32_t gsr;
volatile uint32_t unused[ 2 ];
volatile uint32_t pfr;
volatile uint32_t etcr;
volatile uint32_t etfr;
volatile uint32_t dcr0;
volatile uint32_t dfr0;
volatile uint32_t dcr1;
volatile uint32_t dfr1;
volatile uint32_t dcr2;
volatile uint32_t dfr2;
volatile uint32_t stcr;
volatile uint32_t stfr;
volatile uint32_t pdr[ 8 ];
volatile uint32_t pimsr;
volatile uint32_t pimr;
volatile uint32_t pisr;
volatile uint32_t pir;
volatile uint32_t imr;
volatile uint32_t picr;
volatile uint32_t unused1[ 2 ];
volatile uint32_t etir;
volatile uint32_t fsir;
volatile uint32_t serconf;
volatile uint32_t unused2;
volatile uint32_t twsc;
volatile uint32_t twadj;
volatile uint32_t twtx;
volatile uint32_t twrx;
};
struct grctm_stats {
/* IRQ Stats */
unsigned int nirqs;
unsigned int pulse;
/* IRQ Stats */
unsigned int nirqs;
unsigned int pulse;
};
/* Function ISR callback prototype */
typedef void (*grctm_isr_t)(unsigned int pimr, void *data);
typedef void ( *grctm_isr_t )( unsigned int pimr, void *data );
/* Open a GRCTM device by minor number. */
extern void *grctm_open(int minor);
extern void *grctm_open( int minor );
/* Close a previously opened GRCTM device */
extern void grctm_close(void *spwcuc);
extern void grctm_close( void *spwcuc );
/* Hardware Reset of GRCTM */
extern int grctm_reset(void *grctm);
extern int grctm_reset( void *grctm );
/* Enable Interrupts at Interrupt controller */
extern void grctm_int_enable(void *grctm);
extern void grctm_int_enable( void *grctm );
/* Disable Interrupts at Interrupt controller */
extern void grctm_int_disable(void *grctm);
extern void grctm_int_disable( void *grctm );
/* Clear Statistics gathered by the driver */
extern void grctm_clr_stats(void *grctm);
extern void grctm_clr_stats( void *grctm );
/* Get Statistics gathered by the driver */
extern void grctm_get_stats(void *grctm, struct grctm_stats *stats);
extern void grctm_get_stats( void *grctm, struct grctm_stats *stats );
/* Register an Interrupt handler and custom data, the function call is
* removed by setting func to NULL.
*/
extern void grctm_int_register(void *grctm, grctm_isr_t func, void *data);
extern void grctm_int_register( void *grctm, grctm_isr_t func, void *data );
/* Enable external synchronisation (from spwcuc) */
extern void grctm_enable_ext_sync(void *grctm);
extern void grctm_enable_ext_sync( void *grctm );
/* Disable external synchronisation (from spwcuc) */
extern void grctm_disable_ext_sync(void *grctm);
extern void grctm_disable_ext_sync( void *grctm );
/* Enable TimeWire synchronisation */
extern void grctm_enable_tw_sync(void *grctm);
extern void grctm_enable_tw_sync( void *grctm );
/* Disable TimeWire synchronisation */
extern void grctm_disable_tw_sync(void *grctm);
extern void grctm_disable_tw_sync( void *grctm );
/* Disable frequency synthesizer from driving ET */
extern void grctm_disable_fs(void *grctm);
extern void grctm_disable_fs( void *grctm );
/* Enable frequency synthesizer to drive ET */
extern void grctm_enable_fs(void *grctm);
extern void grctm_enable_fs( void *grctm );
/* Return elapsed coarse time */
extern unsigned int grctm_get_et_coarse(void *grctm);
extern unsigned int grctm_get_et_coarse( void *grctm );
/* Return elapsed fine time */
extern unsigned int grctm_get_et_fine(void *grctm);
extern unsigned int grctm_get_et_fine( void *grctm );
/* Return elapsed time (coarse and fine) */
extern unsigned long long grctm_get_et(void *grctm);
extern unsigned long long grctm_get_et( void *grctm );
/* Return 1 if specified datation has been latched */
extern int grctm_is_dat_latched(void *grctm, int dat);
extern int grctm_is_dat_latched( void *grctm, int dat );
/* Set triggering edge of datation input */
extern void grctm_set_dat_edge(void *grctm, int dat, int edge);
extern void grctm_set_dat_edge( void *grctm, int dat, int edge );
/* Return latched datation coarse time */
extern unsigned int grctm_get_dat_coarse(void *grctm, int dat);
extern unsigned int grctm_get_dat_coarse( void *grctm, int dat );
/* Return latched datation fine time */
extern unsigned int grctm_get_dat_fine(void *grctm, int dat);
extern unsigned int grctm_get_dat_fine( void *grctm, int dat );
/* Return latched datation ET */
extern unsigned long long grctm_get_dat_et(void *grctm, int dat);
extern unsigned long long grctm_get_dat_et( void *grctm, int dat );
/* Return current pulse configuration */
extern unsigned int grctm_get_pulse_reg(void *grctm, int pulse);
extern unsigned int grctm_get_pulse_reg( void *grctm, int pulse );
/* Set pulse register */
extern void grctm_set_pulse_reg(void *grctm, int pulse, unsigned int val);
extern void grctm_set_pulse_reg( void *grctm, int pulse, unsigned int val );
/* Configure pulse: pp = period, pw = width, pl = level, en = enable */
extern void grctm_cfg_pulse(void *grctm, int pulse, int pp, int pw, int pl, int en);
extern void grctm_cfg_pulse(
void *grctm,
int pulse,
int pp,
int pw,
int pl,
int en
);
/* Enable pulse output */
extern void grctm_enable_pulse(void *grctm, int pulse);
extern void grctm_enable_pulse( void *grctm, int pulse );
/* Disable pulse output */
extern void grctm_disable_pulse(void *grctm, int pulse);
extern void grctm_disable_pulse( void *grctm, int pulse );
/* Clear interrupts */
extern void grctm_clear_irqs(void *grctm, int irqs);
extern void grctm_clear_irqs( void *grctm, int irqs );
/* Enable interrupts */
extern void grctm_enable_irqs(void *grctm, int irqs);
extern void grctm_enable_irqs( void *grctm, int irqs );
/* Set Frequency synthesizer increment */
void grctm_set_fs_incr(void *grctm, int incr);
void grctm_set_fs_incr( void *grctm, int incr );
/* Set ET increment */
void grctm_set_et_incr(void *grctm, int incr);
void grctm_set_et_incr( void *grctm, int incr );
/* Get register base address */
struct grctm_regs *grctm_get_regs(void *grctm);
struct grctm_regs *grctm_get_regs( void *grctm );
/* Register the GRCTM driver to Driver Manager */
extern void grctm_register(void);
extern void grctm_register( void );
#endif
bsps/include/grlib/grethgbit-regs.h
+60 -69
View File
@@ -84,17 +84,14 @@ extern "C" {
#define GRETHGBIT_CR_EA 0x80000000U
#define GRETHGBIT_CR_BS_SHIFT 28
#define GRETHGBIT_CR_BS_MASK 0x70000000U
#define GRETHGBIT_CR_BS_MASK 0x70000000U
#define GRETHGBIT_CR_BS_GET( _reg ) \
( ( ( _reg ) & GRETHGBIT_CR_BS_MASK ) >> \
GRETHGBIT_CR_BS_SHIFT )
#define GRETHGBIT_CR_BS_SET( _reg, _val ) \
( ( ( _reg ) & GRETHGBIT_CR_BS_MASK ) >> GRETHGBIT_CR_BS_SHIFT )
#define GRETHGBIT_CR_BS_SET( _reg, _val ) \
( ( ( _reg ) & ~GRETHGBIT_CR_BS_MASK ) | \
( ( ( _val ) << GRETHGBIT_CR_BS_SHIFT ) & \
GRETHGBIT_CR_BS_MASK ) )
( ( ( _val ) << GRETHGBIT_CR_BS_SHIFT ) & GRETHGBIT_CR_BS_MASK ) )
#define GRETHGBIT_CR_BS( _val ) \
( ( ( _val ) << GRETHGBIT_CR_BS_SHIFT ) & \
GRETHGBIT_CR_BS_MASK )
( ( ( _val ) << GRETHGBIT_CR_BS_SHIFT ) & GRETHGBIT_CR_BS_MASK )
#define GRETHGBIT_CR_GA 0x8000000U
@@ -171,17 +168,15 @@ extern "C" {
*/
#define GRETHGBIT_MACMSB_MSB_SHIFT 0
#define GRETHGBIT_MACMSB_MSB_MASK 0xffffU
#define GRETHGBIT_MACMSB_MSB_MASK 0xffffU
#define GRETHGBIT_MACMSB_MSB_GET( _reg ) \
( ( ( _reg ) & GRETHGBIT_MACMSB_MSB_MASK ) >> \
GRETHGBIT_MACMSB_MSB_SHIFT )
#define GRETHGBIT_MACMSB_MSB_SET( _reg, _val ) \
( ( ( _reg ) & ~GRETHGBIT_MACMSB_MSB_MASK ) | \
( ( ( _reg ) & GRETHGBIT_MACMSB_MSB_MASK ) >> GRETHGBIT_MACMSB_MSB_SHIFT )
#define GRETHGBIT_MACMSB_MSB_SET( _reg, _val ) \
( ( ( _reg ) & ~GRETHGBIT_MACMSB_MSB_MASK ) | \
( ( ( _val ) << GRETHGBIT_MACMSB_MSB_SHIFT ) & \
GRETHGBIT_MACMSB_MSB_MASK ) )
#define GRETHGBIT_MACMSB_MSB( _val ) \
( ( ( _val ) << GRETHGBIT_MACMSB_MSB_SHIFT ) & \
GRETHGBIT_MACMSB_MSB_MASK )
( ( ( _val ) << GRETHGBIT_MACMSB_MSB_SHIFT ) & GRETHGBIT_MACMSB_MSB_MASK )
/** @} */
@@ -194,17 +189,15 @@ extern "C" {
*/
#define GRETHGBIT_MACLSB_LSB_SHIFT 0
#define GRETHGBIT_MACLSB_LSB_MASK 0xffffffffU
#define GRETHGBIT_MACLSB_LSB_MASK 0xffffffffU
#define GRETHGBIT_MACLSB_LSB_GET( _reg ) \
( ( ( _reg ) & GRETHGBIT_MACLSB_LSB_MASK ) >> \
GRETHGBIT_MACLSB_LSB_SHIFT )
#define GRETHGBIT_MACLSB_LSB_SET( _reg, _val ) \
( ( ( _reg ) & ~GRETHGBIT_MACLSB_LSB_MASK ) | \
( ( ( _reg ) & GRETHGBIT_MACLSB_LSB_MASK ) >> GRETHGBIT_MACLSB_LSB_SHIFT )
#define GRETHGBIT_MACLSB_LSB_SET( _reg, _val ) \
( ( ( _reg ) & ~GRETHGBIT_MACLSB_LSB_MASK ) | \
( ( ( _val ) << GRETHGBIT_MACLSB_LSB_SHIFT ) & \
GRETHGBIT_MACLSB_LSB_MASK ) )
#define GRETHGBIT_MACLSB_LSB( _val ) \
( ( ( _val ) << GRETHGBIT_MACLSB_LSB_SHIFT ) & \
GRETHGBIT_MACLSB_LSB_MASK )
( ( ( _val ) << GRETHGBIT_MACLSB_LSB_SHIFT ) & GRETHGBIT_MACLSB_LSB_MASK )
/** @} */
@@ -217,41 +210,39 @@ extern "C" {
*/
#define GRETHGBIT_MDIO_DATA_SHIFT 16
#define GRETHGBIT_MDIO_DATA_MASK 0xffff0000U
#define GRETHGBIT_MDIO_DATA_MASK 0xffff0000U
#define GRETHGBIT_MDIO_DATA_GET( _reg ) \
( ( ( _reg ) & GRETHGBIT_MDIO_DATA_MASK ) >> \
GRETHGBIT_MDIO_DATA_SHIFT )
#define GRETHGBIT_MDIO_DATA_SET( _reg, _val ) \
( ( ( _reg ) & ~GRETHGBIT_MDIO_DATA_MASK ) | \
( ( ( _reg ) & GRETHGBIT_MDIO_DATA_MASK ) >> GRETHGBIT_MDIO_DATA_SHIFT )
#define GRETHGBIT_MDIO_DATA_SET( _reg, _val ) \
( ( ( _reg ) & ~GRETHGBIT_MDIO_DATA_MASK ) | \
( ( ( _val ) << GRETHGBIT_MDIO_DATA_SHIFT ) & \
GRETHGBIT_MDIO_DATA_MASK ) )
#define GRETHGBIT_MDIO_DATA( _val ) \
( ( ( _val ) << GRETHGBIT_MDIO_DATA_SHIFT ) & \
GRETHGBIT_MDIO_DATA_MASK )
( ( ( _val ) << GRETHGBIT_MDIO_DATA_SHIFT ) & GRETHGBIT_MDIO_DATA_MASK )
#define GRETHGBIT_MDIO_PHYADDR_SHIFT 11
#define GRETHGBIT_MDIO_PHYADDR_MASK 0xf800U
#define GRETHGBIT_MDIO_PHYADDR_GET( _reg ) \
#define GRETHGBIT_MDIO_PHYADDR_MASK 0xf800U
#define GRETHGBIT_MDIO_PHYADDR_GET( _reg ) \
( ( ( _reg ) & GRETHGBIT_MDIO_PHYADDR_MASK ) >> \
GRETHGBIT_MDIO_PHYADDR_SHIFT )
#define GRETHGBIT_MDIO_PHYADDR_SET( _reg, _val ) \
( ( ( _reg ) & ~GRETHGBIT_MDIO_PHYADDR_MASK ) | \
#define GRETHGBIT_MDIO_PHYADDR_SET( _reg, _val ) \
( ( ( _reg ) & ~GRETHGBIT_MDIO_PHYADDR_MASK ) | \
( ( ( _val ) << GRETHGBIT_MDIO_PHYADDR_SHIFT ) & \
GRETHGBIT_MDIO_PHYADDR_MASK ) )
#define GRETHGBIT_MDIO_PHYADDR( _val ) \
#define GRETHGBIT_MDIO_PHYADDR( _val ) \
( ( ( _val ) << GRETHGBIT_MDIO_PHYADDR_SHIFT ) & \
GRETHGBIT_MDIO_PHYADDR_MASK )
#define GRETHGBIT_MDIO_REGADDR_SHIFT 6
#define GRETHGBIT_MDIO_REGADDR_MASK 0x7c0U
#define GRETHGBIT_MDIO_REGADDR_GET( _reg ) \
#define GRETHGBIT_MDIO_REGADDR_MASK 0x7c0U
#define GRETHGBIT_MDIO_REGADDR_GET( _reg ) \
( ( ( _reg ) & GRETHGBIT_MDIO_REGADDR_MASK ) >> \
GRETHGBIT_MDIO_REGADDR_SHIFT )
#define GRETHGBIT_MDIO_REGADDR_SET( _reg, _val ) \
( ( ( _reg ) & ~GRETHGBIT_MDIO_REGADDR_MASK ) | \
#define GRETHGBIT_MDIO_REGADDR_SET( _reg, _val ) \
( ( ( _reg ) & ~GRETHGBIT_MDIO_REGADDR_MASK ) | \
( ( ( _val ) << GRETHGBIT_MDIO_REGADDR_SHIFT ) & \
GRETHGBIT_MDIO_REGADDR_MASK ) )
#define GRETHGBIT_MDIO_REGADDR( _val ) \
#define GRETHGBIT_MDIO_REGADDR( _val ) \
( ( ( _val ) << GRETHGBIT_MDIO_REGADDR_SHIFT ) & \
GRETHGBIT_MDIO_REGADDR_MASK )
@@ -275,28 +266,28 @@ extern "C" {
*/
#define GRETHGBIT_TDTBA_BASEADDR_SHIFT 10
#define GRETHGBIT_TDTBA_BASEADDR_MASK 0xfffffc00U
#define GRETHGBIT_TDTBA_BASEADDR_GET( _reg ) \
#define GRETHGBIT_TDTBA_BASEADDR_MASK 0xfffffc00U
#define GRETHGBIT_TDTBA_BASEADDR_GET( _reg ) \
( ( ( _reg ) & GRETHGBIT_TDTBA_BASEADDR_MASK ) >> \
GRETHGBIT_TDTBA_BASEADDR_SHIFT )
#define GRETHGBIT_TDTBA_BASEADDR_SET( _reg, _val ) \
( ( ( _reg ) & ~GRETHGBIT_TDTBA_BASEADDR_MASK ) | \
#define GRETHGBIT_TDTBA_BASEADDR_SET( _reg, _val ) \
( ( ( _reg ) & ~GRETHGBIT_TDTBA_BASEADDR_MASK ) | \
( ( ( _val ) << GRETHGBIT_TDTBA_BASEADDR_SHIFT ) & \
GRETHGBIT_TDTBA_BASEADDR_MASK ) )
#define GRETHGBIT_TDTBA_BASEADDR( _val ) \
#define GRETHGBIT_TDTBA_BASEADDR( _val ) \
( ( ( _val ) << GRETHGBIT_TDTBA_BASEADDR_SHIFT ) & \
GRETHGBIT_TDTBA_BASEADDR_MASK )
#define GRETHGBIT_TDTBA_DESCPNT_SHIFT 3
#define GRETHGBIT_TDTBA_DESCPNT_MASK 0x3f8U
#define GRETHGBIT_TDTBA_DESCPNT_GET( _reg ) \
#define GRETHGBIT_TDTBA_DESCPNT_MASK 0x3f8U
#define GRETHGBIT_TDTBA_DESCPNT_GET( _reg ) \
( ( ( _reg ) & GRETHGBIT_TDTBA_DESCPNT_MASK ) >> \
GRETHGBIT_TDTBA_DESCPNT_SHIFT )
#define GRETHGBIT_TDTBA_DESCPNT_SET( _reg, _val ) \
( ( ( _reg ) & ~GRETHGBIT_TDTBA_DESCPNT_MASK ) | \
#define GRETHGBIT_TDTBA_DESCPNT_SET( _reg, _val ) \
( ( ( _reg ) & ~GRETHGBIT_TDTBA_DESCPNT_MASK ) | \
( ( ( _val ) << GRETHGBIT_TDTBA_DESCPNT_SHIFT ) & \
GRETHGBIT_TDTBA_DESCPNT_MASK ) )
#define GRETHGBIT_TDTBA_DESCPNT( _val ) \
#define GRETHGBIT_TDTBA_DESCPNT( _val ) \
( ( ( _val ) << GRETHGBIT_TDTBA_DESCPNT_SHIFT ) & \
GRETHGBIT_TDTBA_DESCPNT_MASK )
@@ -312,28 +303,28 @@ extern "C" {
*/
#define GRETHGBIT_RDTBA_BASEADDR_SHIFT 10
#define GRETHGBIT_RDTBA_BASEADDR_MASK 0xfffffc00U
#define GRETHGBIT_RDTBA_BASEADDR_GET( _reg ) \
#define GRETHGBIT_RDTBA_BASEADDR_MASK 0xfffffc00U
#define GRETHGBIT_RDTBA_BASEADDR_GET( _reg ) \
( ( ( _reg ) & GRETHGBIT_RDTBA_BASEADDR_MASK ) >> \
GRETHGBIT_RDTBA_BASEADDR_SHIFT )
#define GRETHGBIT_RDTBA_BASEADDR_SET( _reg, _val ) \
( ( ( _reg ) & ~GRETHGBIT_RDTBA_BASEADDR_MASK ) | \
#define GRETHGBIT_RDTBA_BASEADDR_SET( _reg, _val ) \
( ( ( _reg ) & ~GRETHGBIT_RDTBA_BASEADDR_MASK ) | \
( ( ( _val ) << GRETHGBIT_RDTBA_BASEADDR_SHIFT ) & \
GRETHGBIT_RDTBA_BASEADDR_MASK ) )
#define GRETHGBIT_RDTBA_BASEADDR( _val ) \
#define GRETHGBIT_RDTBA_BASEADDR( _val ) \
( ( ( _val ) << GRETHGBIT_RDTBA_BASEADDR_SHIFT ) & \
GRETHGBIT_RDTBA_BASEADDR_MASK )
#define GRETHGBIT_RDTBA_DESCPNT_SHIFT 3
#define GRETHGBIT_RDTBA_DESCPNT_MASK 0x3f8U
#define GRETHGBIT_RDTBA_DESCPNT_GET( _reg ) \
#define GRETHGBIT_RDTBA_DESCPNT_MASK 0x3f8U
#define GRETHGBIT_RDTBA_DESCPNT_GET( _reg ) \
( ( ( _reg ) & GRETHGBIT_RDTBA_DESCPNT_MASK ) >> \
GRETHGBIT_RDTBA_DESCPNT_SHIFT )
#define GRETHGBIT_RDTBA_DESCPNT_SET( _reg, _val ) \
( ( ( _reg ) & ~GRETHGBIT_RDTBA_DESCPNT_MASK ) | \
#define GRETHGBIT_RDTBA_DESCPNT_SET( _reg, _val ) \
( ( ( _reg ) & ~GRETHGBIT_RDTBA_DESCPNT_MASK ) | \
( ( ( _val ) << GRETHGBIT_RDTBA_DESCPNT_SHIFT ) & \
GRETHGBIT_RDTBA_DESCPNT_MASK ) )
#define GRETHGBIT_RDTBA_DESCPNT( _val ) \
#define GRETHGBIT_RDTBA_DESCPNT( _val ) \
( ( ( _val ) << GRETHGBIT_RDTBA_DESCPNT_SHIFT ) & \
GRETHGBIT_RDTBA_DESCPNT_MASK )
@@ -348,15 +339,15 @@ extern "C" {
*/
#define GRETHGBIT_EDCLMACMSB_MSB_SHIFT 0
#define GRETHGBIT_EDCLMACMSB_MSB_MASK 0xffffU
#define GRETHGBIT_EDCLMACMSB_MSB_GET( _reg ) \
#define GRETHGBIT_EDCLMACMSB_MSB_MASK 0xffffU
#define GRETHGBIT_EDCLMACMSB_MSB_GET( _reg ) \
( ( ( _reg ) & GRETHGBIT_EDCLMACMSB_MSB_MASK ) >> \
GRETHGBIT_EDCLMACMSB_MSB_SHIFT )
#define GRETHGBIT_EDCLMACMSB_MSB_SET( _reg, _val ) \
( ( ( _reg ) & ~GRETHGBIT_EDCLMACMSB_MSB_MASK ) | \
#define GRETHGBIT_EDCLMACMSB_MSB_SET( _reg, _val ) \
( ( ( _reg ) & ~GRETHGBIT_EDCLMACMSB_MSB_MASK ) | \
( ( ( _val ) << GRETHGBIT_EDCLMACMSB_MSB_SHIFT ) & \
GRETHGBIT_EDCLMACMSB_MSB_MASK ) )
#define GRETHGBIT_EDCLMACMSB_MSB( _val ) \
#define GRETHGBIT_EDCLMACMSB_MSB( _val ) \
( ( ( _val ) << GRETHGBIT_EDCLMACMSB_MSB_SHIFT ) & \
GRETHGBIT_EDCLMACMSB_MSB_MASK )
@@ -371,15 +362,15 @@ extern "C" {
*/
#define GRETHGBIT_EDCLMACLSB_LSB_SHIFT 0
#define GRETHGBIT_EDCLMACLSB_LSB_MASK 0xffffffffU
#define GRETHGBIT_EDCLMACLSB_LSB_GET( _reg ) \
#define GRETHGBIT_EDCLMACLSB_LSB_MASK 0xffffffffU
#define GRETHGBIT_EDCLMACLSB_LSB_GET( _reg ) \
( ( ( _reg ) & GRETHGBIT_EDCLMACLSB_LSB_MASK ) >> \
GRETHGBIT_EDCLMACLSB_LSB_SHIFT )
#define GRETHGBIT_EDCLMACLSB_LSB_SET( _reg, _val ) \
( ( ( _reg ) & ~GRETHGBIT_EDCLMACLSB_LSB_MASK ) | \
#define GRETHGBIT_EDCLMACLSB_LSB_SET( _reg, _val ) \
( ( ( _reg ) & ~GRETHGBIT_EDCLMACLSB_LSB_MASK ) | \
( ( ( _val ) << GRETHGBIT_EDCLMACLSB_LSB_SHIFT ) & \
GRETHGBIT_EDCLMACLSB_LSB_MASK ) )
#define GRETHGBIT_EDCLMACLSB_LSB( _val ) \
#define GRETHGBIT_EDCLMACLSB_LSB( _val ) \
( ( ( _val ) << GRETHGBIT_EDCLMACLSB_LSB_SHIFT ) & \
GRETHGBIT_EDCLMACLSB_LSB_MASK )
bsps/include/grlib/grgpio-regs.h
+100 -145
View File
@@ -82,17 +82,14 @@ extern "C" {
*/
#define GRGPIO_DATA_DATA_SHIFT 0
#define GRGPIO_DATA_DATA_MASK 0xffffffffU
#define GRGPIO_DATA_DATA_MASK 0xffffffffU
#define GRGPIO_DATA_DATA_GET( _reg ) \
( ( ( _reg ) & GRGPIO_DATA_DATA_MASK ) >> \
GRGPIO_DATA_DATA_SHIFT )
#define GRGPIO_DATA_DATA_SET( _reg, _val ) \
( ( ( _reg ) & GRGPIO_DATA_DATA_MASK ) >> GRGPIO_DATA_DATA_SHIFT )
#define GRGPIO_DATA_DATA_SET( _reg, _val ) \
( ( ( _reg ) & ~GRGPIO_DATA_DATA_MASK ) | \
( ( ( _val ) << GRGPIO_DATA_DATA_SHIFT ) & \
GRGPIO_DATA_DATA_MASK ) )
( ( ( _val ) << GRGPIO_DATA_DATA_SHIFT ) & GRGPIO_DATA_DATA_MASK ) )
#define GRGPIO_DATA_DATA( _val ) \
( ( ( _val ) << GRGPIO_DATA_DATA_SHIFT ) & \
GRGPIO_DATA_DATA_MASK )
( ( ( _val ) << GRGPIO_DATA_DATA_SHIFT ) & GRGPIO_DATA_DATA_MASK )
/** @} */
@@ -105,17 +102,14 @@ extern "C" {
*/
#define GRGPIO_OUTPUT_DATA_SHIFT 0
#define GRGPIO_OUTPUT_DATA_MASK 0xffffffffU
#define GRGPIO_OUTPUT_DATA_MASK 0xffffffffU
#define GRGPIO_OUTPUT_DATA_GET( _reg ) \
( ( ( _reg ) & GRGPIO_OUTPUT_DATA_MASK ) >> \
GRGPIO_OUTPUT_DATA_SHIFT )
#define GRGPIO_OUTPUT_DATA_SET( _reg, _val ) \
( ( ( _reg ) & GRGPIO_OUTPUT_DATA_MASK ) >> GRGPIO_OUTPUT_DATA_SHIFT )
#define GRGPIO_OUTPUT_DATA_SET( _reg, _val ) \
( ( ( _reg ) & ~GRGPIO_OUTPUT_DATA_MASK ) | \
( ( ( _val ) << GRGPIO_OUTPUT_DATA_SHIFT ) & \
GRGPIO_OUTPUT_DATA_MASK ) )
( ( ( _val ) << GRGPIO_OUTPUT_DATA_SHIFT ) & GRGPIO_OUTPUT_DATA_MASK ) )
#define GRGPIO_OUTPUT_DATA( _val ) \
( ( ( _val ) << GRGPIO_OUTPUT_DATA_SHIFT ) & \
GRGPIO_OUTPUT_DATA_MASK )
( ( ( _val ) << GRGPIO_OUTPUT_DATA_SHIFT ) & GRGPIO_OUTPUT_DATA_MASK )
/** @} */
@@ -128,17 +122,15 @@ extern "C" {
*/
#define GRGPIO_DIRECTION_DIR_SHIFT 0
#define GRGPIO_DIRECTION_DIR_MASK 0xffffffffU
#define GRGPIO_DIRECTION_DIR_MASK 0xffffffffU
#define GRGPIO_DIRECTION_DIR_GET( _reg ) \
( ( ( _reg ) & GRGPIO_DIRECTION_DIR_MASK ) >> \
GRGPIO_DIRECTION_DIR_SHIFT )
#define GRGPIO_DIRECTION_DIR_SET( _reg, _val ) \
( ( ( _reg ) & ~GRGPIO_DIRECTION_DIR_MASK ) | \
( ( ( _reg ) & GRGPIO_DIRECTION_DIR_MASK ) >> GRGPIO_DIRECTION_DIR_SHIFT )
#define GRGPIO_DIRECTION_DIR_SET( _reg, _val ) \
( ( ( _reg ) & ~GRGPIO_DIRECTION_DIR_MASK ) | \
( ( ( _val ) << GRGPIO_DIRECTION_DIR_SHIFT ) & \
GRGPIO_DIRECTION_DIR_MASK ) )
#define GRGPIO_DIRECTION_DIR( _val ) \
( ( ( _val ) << GRGPIO_DIRECTION_DIR_SHIFT ) & \
GRGPIO_DIRECTION_DIR_MASK )
( ( ( _val ) << GRGPIO_DIRECTION_DIR_SHIFT ) & GRGPIO_DIRECTION_DIR_MASK )
/** @} */
@@ -151,17 +143,14 @@ extern "C" {
*/
#define GRGPIO_IMASK_MASK_SHIFT 0
#define GRGPIO_IMASK_MASK_MASK 0xffffffffU
#define GRGPIO_IMASK_MASK_MASK 0xffffffffU
#define GRGPIO_IMASK_MASK_GET( _reg ) \
( ( ( _reg ) & GRGPIO_IMASK_MASK_MASK ) >> \
GRGPIO_IMASK_MASK_SHIFT )
#define GRGPIO_IMASK_MASK_SET( _reg, _val ) \
( ( ( _reg ) & GRGPIO_IMASK_MASK_MASK ) >> GRGPIO_IMASK_MASK_SHIFT )
#define GRGPIO_IMASK_MASK_SET( _reg, _val ) \
( ( ( _reg ) & ~GRGPIO_IMASK_MASK_MASK ) | \
( ( ( _val ) << GRGPIO_IMASK_MASK_SHIFT ) & \
GRGPIO_IMASK_MASK_MASK ) )
( ( ( _val ) << GRGPIO_IMASK_MASK_SHIFT ) & GRGPIO_IMASK_MASK_MASK ) )
#define GRGPIO_IMASK_MASK( _val ) \
( ( ( _val ) << GRGPIO_IMASK_MASK_SHIFT ) & \
GRGPIO_IMASK_MASK_MASK )
( ( ( _val ) << GRGPIO_IMASK_MASK_SHIFT ) & GRGPIO_IMASK_MASK_MASK )
/** @} */
@@ -174,17 +163,14 @@ extern "C" {
*/
#define GRGPIO_IPOL_POL_SHIFT 0
#define GRGPIO_IPOL_POL_MASK 0xffffffffU
#define GRGPIO_IPOL_POL_MASK 0xffffffffU
#define GRGPIO_IPOL_POL_GET( _reg ) \
( ( ( _reg ) & GRGPIO_IPOL_POL_MASK ) >> \
GRGPIO_IPOL_POL_SHIFT )
#define GRGPIO_IPOL_POL_SET( _reg, _val ) \
( ( ( _reg ) & GRGPIO_IPOL_POL_MASK ) >> GRGPIO_IPOL_POL_SHIFT )
#define GRGPIO_IPOL_POL_SET( _reg, _val ) \
( ( ( _reg ) & ~GRGPIO_IPOL_POL_MASK ) | \
( ( ( _val ) << GRGPIO_IPOL_POL_SHIFT ) & \
GRGPIO_IPOL_POL_MASK ) )
( ( ( _val ) << GRGPIO_IPOL_POL_SHIFT ) & GRGPIO_IPOL_POL_MASK ) )
#define GRGPIO_IPOL_POL( _val ) \
( ( ( _val ) << GRGPIO_IPOL_POL_SHIFT ) & \
GRGPIO_IPOL_POL_MASK )
( ( ( _val ) << GRGPIO_IPOL_POL_SHIFT ) & GRGPIO_IPOL_POL_MASK )
/** @} */
@@ -197,17 +183,14 @@ extern "C" {
*/
#define GRGPIO_IEDGE_EDGE_SHIFT 0
#define GRGPIO_IEDGE_EDGE_MASK 0xffffffffU
#define GRGPIO_IEDGE_EDGE_MASK 0xffffffffU
#define GRGPIO_IEDGE_EDGE_GET( _reg ) \
( ( ( _reg ) & GRGPIO_IEDGE_EDGE_MASK ) >> \
GRGPIO_IEDGE_EDGE_SHIFT )
#define GRGPIO_IEDGE_EDGE_SET( _reg, _val ) \
( ( ( _reg ) & GRGPIO_IEDGE_EDGE_MASK ) >> GRGPIO_IEDGE_EDGE_SHIFT )
#define GRGPIO_IEDGE_EDGE_SET( _reg, _val ) \
( ( ( _reg ) & ~GRGPIO_IEDGE_EDGE_MASK ) | \
( ( ( _val ) << GRGPIO_IEDGE_EDGE_SHIFT ) & \
GRGPIO_IEDGE_EDGE_MASK ) )
( ( ( _val ) << GRGPIO_IEDGE_EDGE_SHIFT ) & GRGPIO_IEDGE_EDGE_MASK ) )
#define GRGPIO_IEDGE_EDGE( _val ) \
( ( ( _val ) << GRGPIO_IEDGE_EDGE_SHIFT ) & \
GRGPIO_IEDGE_EDGE_MASK )
( ( ( _val ) << GRGPIO_IEDGE_EDGE_SHIFT ) & GRGPIO_IEDGE_EDGE_MASK )
/** @} */
@@ -220,17 +203,15 @@ extern "C" {
*/
#define GRGPIO_BYPASS_BYPASS_SHIFT 0
#define GRGPIO_BYPASS_BYPASS_MASK 0xffffffffU
#define GRGPIO_BYPASS_BYPASS_MASK 0xffffffffU
#define GRGPIO_BYPASS_BYPASS_GET( _reg ) \
( ( ( _reg ) & GRGPIO_BYPASS_BYPASS_MASK ) >> \
GRGPIO_BYPASS_BYPASS_SHIFT )
#define GRGPIO_BYPASS_BYPASS_SET( _reg, _val ) \
( ( ( _reg ) & ~GRGPIO_BYPASS_BYPASS_MASK ) | \
( ( ( _reg ) & GRGPIO_BYPASS_BYPASS_MASK ) >> GRGPIO_BYPASS_BYPASS_SHIFT )
#define GRGPIO_BYPASS_BYPASS_SET( _reg, _val ) \
( ( ( _reg ) & ~GRGPIO_BYPASS_BYPASS_MASK ) | \
( ( ( _val ) << GRGPIO_BYPASS_BYPASS_SHIFT ) & \
GRGPIO_BYPASS_BYPASS_MASK ) )
#define GRGPIO_BYPASS_BYPASS( _val ) \
( ( ( _val ) << GRGPIO_BYPASS_BYPASS_SHIFT ) & \
GRGPIO_BYPASS_BYPASS_MASK )
( ( ( _val ) << GRGPIO_BYPASS_BYPASS_SHIFT ) & GRGPIO_BYPASS_BYPASS_MASK )
/** @} */
@@ -249,30 +230,24 @@ extern "C" {
#define GRGPIO_CAP_IFL 0x10000U
#define GRGPIO_CAP_IRQGEN_SHIFT 8
#define GRGPIO_CAP_IRQGEN_MASK 0x1f00U
#define GRGPIO_CAP_IRQGEN_MASK 0x1f00U
#define GRGPIO_CAP_IRQGEN_GET( _reg ) \
( ( ( _reg ) & GRGPIO_CAP_IRQGEN_MASK ) >> \
GRGPIO_CAP_IRQGEN_SHIFT )
#define GRGPIO_CAP_IRQGEN_SET( _reg, _val ) \
( ( ( _reg ) & GRGPIO_CAP_IRQGEN_MASK ) >> GRGPIO_CAP_IRQGEN_SHIFT )
#define GRGPIO_CAP_IRQGEN_SET( _reg, _val ) \
( ( ( _reg ) & ~GRGPIO_CAP_IRQGEN_MASK ) | \
( ( ( _val ) << GRGPIO_CAP_IRQGEN_SHIFT ) & \
GRGPIO_CAP_IRQGEN_MASK ) )
( ( ( _val ) << GRGPIO_CAP_IRQGEN_SHIFT ) & GRGPIO_CAP_IRQGEN_MASK ) )
#define GRGPIO_CAP_IRQGEN( _val ) \
( ( ( _val ) << GRGPIO_CAP_IRQGEN_SHIFT ) & \
GRGPIO_CAP_IRQGEN_MASK )
( ( ( _val ) << GRGPIO_CAP_IRQGEN_SHIFT ) & GRGPIO_CAP_IRQGEN_MASK )
#define GRGPIO_CAP_NLINES_SHIFT 0
#define GRGPIO_CAP_NLINES_MASK 0x1fU
#define GRGPIO_CAP_NLINES_MASK 0x1fU
#define GRGPIO_CAP_NLINES_GET( _reg ) \
( ( ( _reg ) & GRGPIO_CAP_NLINES_MASK ) >> \
GRGPIO_CAP_NLINES_SHIFT )
#define GRGPIO_CAP_NLINES_SET( _reg, _val ) \
( ( ( _reg ) & GRGPIO_CAP_NLINES_MASK ) >> GRGPIO_CAP_NLINES_SHIFT )
#define GRGPIO_CAP_NLINES_SET( _reg, _val ) \
( ( ( _reg ) & ~GRGPIO_CAP_NLINES_MASK ) | \
( ( ( _val ) << GRGPIO_CAP_NLINES_SHIFT ) & \
GRGPIO_CAP_NLINES_MASK ) )
( ( ( _val ) << GRGPIO_CAP_NLINES_SHIFT ) & GRGPIO_CAP_NLINES_MASK ) )
#define GRGPIO_CAP_NLINES( _val ) \
( ( ( _val ) << GRGPIO_CAP_NLINES_SHIFT ) & \
GRGPIO_CAP_NLINES_MASK )
( ( ( _val ) << GRGPIO_CAP_NLINES_SHIFT ) & GRGPIO_CAP_NLINES_MASK )
/** @} */
@@ -286,54 +261,54 @@ extern "C" {
*/
#define GRGPIO_IRQMAPR_IRQMAP_I_0_SHIFT 24
#define GRGPIO_IRQMAPR_IRQMAP_I_0_MASK 0x1f000000U
#define GRGPIO_IRQMAPR_IRQMAP_I_0_GET( _reg ) \
#define GRGPIO_IRQMAPR_IRQMAP_I_0_MASK 0x1f000000U
#define GRGPIO_IRQMAPR_IRQMAP_I_0_GET( _reg ) \
( ( ( _reg ) & GRGPIO_IRQMAPR_IRQMAP_I_0_MASK ) >> \
GRGPIO_IRQMAPR_IRQMAP_I_0_SHIFT )
#define GRGPIO_IRQMAPR_IRQMAP_I_0_SET( _reg, _val ) \
( ( ( _reg ) & ~GRGPIO_IRQMAPR_IRQMAP_I_0_MASK ) | \
#define GRGPIO_IRQMAPR_IRQMAP_I_0_SET( _reg, _val ) \
( ( ( _reg ) & ~GRGPIO_IRQMAPR_IRQMAP_I_0_MASK ) | \
( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_0_SHIFT ) & \
GRGPIO_IRQMAPR_IRQMAP_I_0_MASK ) )
#define GRGPIO_IRQMAPR_IRQMAP_I_0( _val ) \
#define GRGPIO_IRQMAPR_IRQMAP_I_0( _val ) \
( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_0_SHIFT ) & \
GRGPIO_IRQMAPR_IRQMAP_I_0_MASK )
#define GRGPIO_IRQMAPR_IRQMAP_I_1_SHIFT 16
#define GRGPIO_IRQMAPR_IRQMAP_I_1_MASK 0x1f0000U
#define GRGPIO_IRQMAPR_IRQMAP_I_1_GET( _reg ) \
#define GRGPIO_IRQMAPR_IRQMAP_I_1_MASK 0x1f0000U
#define GRGPIO_IRQMAPR_IRQMAP_I_1_GET( _reg ) \
( ( ( _reg ) & GRGPIO_IRQMAPR_IRQMAP_I_1_MASK ) >> \
GRGPIO_IRQMAPR_IRQMAP_I_1_SHIFT )
#define GRGPIO_IRQMAPR_IRQMAP_I_1_SET( _reg, _val ) \
( ( ( _reg ) & ~GRGPIO_IRQMAPR_IRQMAP_I_1_MASK ) | \
#define GRGPIO_IRQMAPR_IRQMAP_I_1_SET( _reg, _val ) \
( ( ( _reg ) & ~GRGPIO_IRQMAPR_IRQMAP_I_1_MASK ) | \
( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_1_SHIFT ) & \
GRGPIO_IRQMAPR_IRQMAP_I_1_MASK ) )
#define GRGPIO_IRQMAPR_IRQMAP_I_1( _val ) \
#define GRGPIO_IRQMAPR_IRQMAP_I_1( _val ) \
( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_1_SHIFT ) & \
GRGPIO_IRQMAPR_IRQMAP_I_1_MASK )
#define GRGPIO_IRQMAPR_IRQMAP_I_2_SHIFT 8
#define GRGPIO_IRQMAPR_IRQMAP_I_2_MASK 0x1f00U
#define GRGPIO_IRQMAPR_IRQMAP_I_2_GET( _reg ) \
#define GRGPIO_IRQMAPR_IRQMAP_I_2_MASK 0x1f00U
#define GRGPIO_IRQMAPR_IRQMAP_I_2_GET( _reg ) \
( ( ( _reg ) & GRGPIO_IRQMAPR_IRQMAP_I_2_MASK ) >> \
GRGPIO_IRQMAPR_IRQMAP_I_2_SHIFT )
#define GRGPIO_IRQMAPR_IRQMAP_I_2_SET( _reg, _val ) \
( ( ( _reg ) & ~GRGPIO_IRQMAPR_IRQMAP_I_2_MASK ) | \
#define GRGPIO_IRQMAPR_IRQMAP_I_2_SET( _reg, _val ) \
( ( ( _reg ) & ~GRGPIO_IRQMAPR_IRQMAP_I_2_MASK ) | \
( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_2_SHIFT ) & \
GRGPIO_IRQMAPR_IRQMAP_I_2_MASK ) )
#define GRGPIO_IRQMAPR_IRQMAP_I_2( _val ) \
#define GRGPIO_IRQMAPR_IRQMAP_I_2( _val ) \
( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_2_SHIFT ) & \
GRGPIO_IRQMAPR_IRQMAP_I_2_MASK )
#define GRGPIO_IRQMAPR_IRQMAP_I_3_SHIFT 0
#define GRGPIO_IRQMAPR_IRQMAP_I_3_MASK 0x1fU
#define GRGPIO_IRQMAPR_IRQMAP_I_3_GET( _reg ) \
#define GRGPIO_IRQMAPR_IRQMAP_I_3_MASK 0x1fU
#define GRGPIO_IRQMAPR_IRQMAP_I_3_GET( _reg ) \
( ( ( _reg ) & GRGPIO_IRQMAPR_IRQMAP_I_3_MASK ) >> \
GRGPIO_IRQMAPR_IRQMAP_I_3_SHIFT )
#define GRGPIO_IRQMAPR_IRQMAP_I_3_SET( _reg, _val ) \
( ( ( _reg ) & ~GRGPIO_IRQMAPR_IRQMAP_I_3_MASK ) | \
#define GRGPIO_IRQMAPR_IRQMAP_I_3_SET( _reg, _val ) \
( ( ( _reg ) & ~GRGPIO_IRQMAPR_IRQMAP_I_3_MASK ) | \
( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_3_SHIFT ) & \
GRGPIO_IRQMAPR_IRQMAP_I_3_MASK ) )
#define GRGPIO_IRQMAPR_IRQMAP_I_3( _val ) \
#define GRGPIO_IRQMAPR_IRQMAP_I_3( _val ) \
( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_3_SHIFT ) & \
GRGPIO_IRQMAPR_IRQMAP_I_3_MASK )
@@ -348,17 +323,15 @@ extern "C" {
*/
#define GRGPIO_IAVAIL_IMASK_SHIFT 0
#define GRGPIO_IAVAIL_IMASK_MASK 0xffffffffU
#define GRGPIO_IAVAIL_IMASK_MASK 0xffffffffU
#define GRGPIO_IAVAIL_IMASK_GET( _reg ) \
( ( ( _reg ) & GRGPIO_IAVAIL_IMASK_MASK ) >> \
GRGPIO_IAVAIL_IMASK_SHIFT )
#define GRGPIO_IAVAIL_IMASK_SET( _reg, _val ) \
( ( ( _reg ) & ~GRGPIO_IAVAIL_IMASK_MASK ) | \
( ( ( _reg ) & GRGPIO_IAVAIL_IMASK_MASK ) >> GRGPIO_IAVAIL_IMASK_SHIFT )
#define GRGPIO_IAVAIL_IMASK_SET( _reg, _val ) \
( ( ( _reg ) & ~GRGPIO_IAVAIL_IMASK_MASK ) | \
( ( ( _val ) << GRGPIO_IAVAIL_IMASK_SHIFT ) & \
GRGPIO_IAVAIL_IMASK_MASK ) )
#define GRGPIO_IAVAIL_IMASK( _val ) \
( ( ( _val ) << GRGPIO_IAVAIL_IMASK_SHIFT ) & \
GRGPIO_IAVAIL_IMASK_MASK )
( ( ( _val ) << GRGPIO_IAVAIL_IMASK_SHIFT ) & GRGPIO_IAVAIL_IMASK_MASK )
/** @} */
@@ -371,17 +344,14 @@ extern "C" {
*/
#define GRGPIO_IFLAG_IFLAG_SHIFT 0
#define GRGPIO_IFLAG_IFLAG_MASK 0xffffffffU
#define GRGPIO_IFLAG_IFLAG_MASK 0xffffffffU
#define GRGPIO_IFLAG_IFLAG_GET( _reg ) \
( ( ( _reg ) & GRGPIO_IFLAG_IFLAG_MASK ) >> \
GRGPIO_IFLAG_IFLAG_SHIFT )
#define GRGPIO_IFLAG_IFLAG_SET( _reg, _val ) \
( ( ( _reg ) & GRGPIO_IFLAG_IFLAG_MASK ) >> GRGPIO_IFLAG_IFLAG_SHIFT )
#define GRGPIO_IFLAG_IFLAG_SET( _reg, _val ) \
( ( ( _reg ) & ~GRGPIO_IFLAG_IFLAG_MASK ) | \
( ( ( _val ) << GRGPIO_IFLAG_IFLAG_SHIFT ) & \
GRGPIO_IFLAG_IFLAG_MASK ) )
( ( ( _val ) << GRGPIO_IFLAG_IFLAG_SHIFT ) & GRGPIO_IFLAG_IFLAG_MASK ) )
#define GRGPIO_IFLAG_IFLAG( _val ) \
( ( ( _val ) << GRGPIO_IFLAG_IFLAG_SHIFT ) & \
GRGPIO_IFLAG_IFLAG_MASK )
( ( ( _val ) << GRGPIO_IFLAG_IFLAG_SHIFT ) & GRGPIO_IFLAG_IFLAG_MASK )
/** @} */
@@ -394,17 +364,14 @@ extern "C" {
*/
#define GRGPIO_IPEN_IPEN_SHIFT 0
#define GRGPIO_IPEN_IPEN_MASK 0xffffffffU
#define GRGPIO_IPEN_IPEN_MASK 0xffffffffU
#define GRGPIO_IPEN_IPEN_GET( _reg ) \
( ( ( _reg ) & GRGPIO_IPEN_IPEN_MASK ) >> \
GRGPIO_IPEN_IPEN_SHIFT )
#define GRGPIO_IPEN_IPEN_SET( _reg, _val ) \
( ( ( _reg ) & GRGPIO_IPEN_IPEN_MASK ) >> GRGPIO_IPEN_IPEN_SHIFT )
#define GRGPIO_IPEN_IPEN_SET( _reg, _val ) \
( ( ( _reg ) & ~GRGPIO_IPEN_IPEN_MASK ) | \
( ( ( _val ) << GRGPIO_IPEN_IPEN_SHIFT ) & \
GRGPIO_IPEN_IPEN_MASK ) )
( ( ( _val ) << GRGPIO_IPEN_IPEN_SHIFT ) & GRGPIO_IPEN_IPEN_MASK ) )
#define GRGPIO_IPEN_IPEN( _val ) \
( ( ( _val ) << GRGPIO_IPEN_IPEN_SHIFT ) & \
GRGPIO_IPEN_IPEN_MASK )
( ( ( _val ) << GRGPIO_IPEN_IPEN_SHIFT ) & GRGPIO_IPEN_IPEN_MASK )
/** @} */
@@ -417,17 +384,14 @@ extern "C" {
*/
#define GRGPIO_PULSE_PULSE_SHIFT 0
#define GRGPIO_PULSE_PULSE_MASK 0xffffffffU
#define GRGPIO_PULSE_PULSE_MASK 0xffffffffU
#define GRGPIO_PULSE_PULSE_GET( _reg ) \
( ( ( _reg ) & GRGPIO_PULSE_PULSE_MASK ) >> \
GRGPIO_PULSE_PULSE_SHIFT )
#define GRGPIO_PULSE_PULSE_SET( _reg, _val ) \
( ( ( _reg ) & GRGPIO_PULSE_PULSE_MASK ) >> GRGPIO_PULSE_PULSE_SHIFT )
#define GRGPIO_PULSE_PULSE_SET( _reg, _val ) \
( ( ( _reg ) & ~GRGPIO_PULSE_PULSE_MASK ) | \
( ( ( _val ) << GRGPIO_PULSE_PULSE_SHIFT ) & \
GRGPIO_PULSE_PULSE_MASK ) )
( ( ( _val ) << GRGPIO_PULSE_PULSE_SHIFT ) & GRGPIO_PULSE_PULSE_MASK ) )
#define GRGPIO_PULSE_PULSE( _val ) \
( ( ( _val ) << GRGPIO_PULSE_PULSE_SHIFT ) & \
GRGPIO_PULSE_PULSE_MASK )
( ( ( _val ) << GRGPIO_PULSE_PULSE_SHIFT ) & GRGPIO_PULSE_PULSE_MASK )
/** @} */
@@ -440,17 +404,14 @@ extern "C" {
*/
#define GRGPIO_LOR_DATA_SHIFT 0
#define GRGPIO_LOR_DATA_MASK 0xffffffffU
#define GRGPIO_LOR_DATA_MASK 0xffffffffU
#define GRGPIO_LOR_DATA_GET( _reg ) \
( ( ( _reg ) & GRGPIO_LOR_DATA_MASK ) >> \
GRGPIO_LOR_DATA_SHIFT )
#define GRGPIO_LOR_DATA_SET( _reg, _val ) \
( ( ( _reg ) & GRGPIO_LOR_DATA_MASK ) >> GRGPIO_LOR_DATA_SHIFT )
#define GRGPIO_LOR_DATA_SET( _reg, _val ) \
( ( ( _reg ) & ~GRGPIO_LOR_DATA_MASK ) | \
( ( ( _val ) << GRGPIO_LOR_DATA_SHIFT ) & \
GRGPIO_LOR_DATA_MASK ) )
( ( ( _val ) << GRGPIO_LOR_DATA_SHIFT ) & GRGPIO_LOR_DATA_MASK ) )
#define GRGPIO_LOR_DATA( _val ) \
( ( ( _val ) << GRGPIO_LOR_DATA_SHIFT ) & \
GRGPIO_LOR_DATA_MASK )
( ( ( _val ) << GRGPIO_LOR_DATA_SHIFT ) & GRGPIO_LOR_DATA_MASK )
/** @} */
@@ -463,17 +424,14 @@ extern "C" {
*/
#define GRGPIO_LAND_DATA_SHIFT 0
#define GRGPIO_LAND_DATA_MASK 0xffffffffU
#define GRGPIO_LAND_DATA_MASK 0xffffffffU
#define GRGPIO_LAND_DATA_GET( _reg ) \
( ( ( _reg ) & GRGPIO_LAND_DATA_MASK ) >> \
GRGPIO_LAND_DATA_SHIFT )
#define GRGPIO_LAND_DATA_SET( _reg, _val ) \
( ( ( _reg ) & GRGPIO_LAND_DATA_MASK ) >> GRGPIO_LAND_DATA_SHIFT )
#define GRGPIO_LAND_DATA_SET( _reg, _val ) \
( ( ( _reg ) & ~GRGPIO_LAND_DATA_MASK ) | \
( ( ( _val ) << GRGPIO_LAND_DATA_SHIFT ) & \
GRGPIO_LAND_DATA_MASK ) )
( ( ( _val ) << GRGPIO_LAND_DATA_SHIFT ) & GRGPIO_LAND_DATA_MASK ) )
#define GRGPIO_LAND_DATA( _val ) \
( ( ( _val ) << GRGPIO_LAND_DATA_SHIFT ) & \
GRGPIO_LAND_DATA_MASK )
( ( ( _val ) << GRGPIO_LAND_DATA_SHIFT ) & GRGPIO_LAND_DATA_MASK )
/** @} */
@@ -486,17 +444,14 @@ extern "C" {
*/
#define GRGPIO_LXOR_DATA_SHIFT 0
#define GRGPIO_LXOR_DATA_MASK 0xffffffffU
#define GRGPIO_LXOR_DATA_MASK 0xffffffffU
#define GRGPIO_LXOR_DATA_GET( _reg ) \
( ( ( _reg ) & GRGPIO_LXOR_DATA_MASK ) >> \
GRGPIO_LXOR_DATA_SHIFT )
#define GRGPIO_LXOR_DATA_SET( _reg, _val ) \
( ( ( _reg ) & GRGPIO_LXOR_DATA_MASK ) >> GRGPIO_LXOR_DATA_SHIFT )
#define GRGPIO_LXOR_DATA_SET( _reg, _val ) \
( ( ( _reg ) & ~GRGPIO_LXOR_DATA_MASK ) | \
( ( ( _val ) << GRGPIO_LXOR_DATA_SHIFT ) & \
GRGPIO_LXOR_DATA_MASK ) )
( ( ( _val ) << GRGPIO_LXOR_DATA_SHIFT ) & GRGPIO_LXOR_DATA_MASK ) )
#define GRGPIO_LXOR_DATA( _val ) \
( ( ( _val ) << GRGPIO_LXOR_DATA_SHIFT ) & \
GRGPIO_LXOR_DATA_MASK )
( ( ( _val ) << GRGPIO_LXOR_DATA_SHIFT ) & GRGPIO_LXOR_DATA_MASK )
/** @} */
bsps/include/grlib/grgpio.h
+1 -1
View File
@@ -35,7 +35,7 @@
extern "C" {
#endif
extern void grgpio_register_drv (void);
extern void grgpio_register_drv( void );
#ifdef __cplusplus
}
bsps/include/grlib/griommu-regs.h
+160 -226
View File
File diff suppressed because it is too large Load Diff
bsps/include/grlib/griommu.h
+118 -106
View File
@@ -43,13 +43,13 @@
extern "C" {
#endif
extern void griommu_register_drv(void);
extern void griommu_register_drv( void );
#define GRIOMMU_ERR_OK 0
#define GRIOMMU_ERR_NOINIT -1
#define GRIOMMU_ERR_EINVAL -2
#define GRIOMMU_ERR_OK 0
#define GRIOMMU_ERR_NOINIT -1
#define GRIOMMU_ERR_EINVAL -2
#define GRIOMMU_ERR_IMPLEMENTED -3
#define GRIOMMU_ERR_NOTFOUND -4
#define GRIOMMU_ERR_NOTFOUND -4
/* Size of APV (has to be divided by page size in bytes) */
#define GRIOMMU_APV_SIZE 0x20000000
@@ -58,8 +58,8 @@ extern void griommu_register_drv(void);
#define GRIOMMU_APV_ALIGN 0x10
/* IOMMU APV allocation helper functions */
extern void * griommu_apv_new(void);
extern void griommu_apv_delete(void * apv);
extern void *griommu_apv_new( void );
extern void griommu_apv_delete( void *apv );
/* IOMMU Master Setup */
@@ -67,115 +67,127 @@ extern void griommu_apv_delete(void * apv);
/*
* GRIOMMU MASTER register fields
*/
#define MASTER_VENDOR (0xff << MASTER_VENDOR_BIT)
#define MASTER_DEVICE (0xfff << MASTER_DEVICE_BIT)
#define MASTER_BS (0x1 << MASTER_BS_BIT)
#define MASTER_GROUP (0xf << MASTER_GROUP_BIT)
#define MASTER_VENDOR ( 0xff << MASTER_VENDOR_BIT )
#define MASTER_DEVICE ( 0xfff << MASTER_DEVICE_BIT )
#define MASTER_BS ( 0x1 << MASTER_BS_BIT )
#define MASTER_GROUP ( 0xf << MASTER_GROUP_BIT )
#define MASTER_VENDOR_BIT 24
#define MASTER_DEVICE_BIT 12
#define MASTER_BS_BIT 4
#define MASTER_GROUP_BIT 0
#define MASTER_BS_BIT 4
#define MASTER_GROUP_BIT 0
#define GRIOMMU_OPTIONS_BUS0 0
#define GRIOMMU_OPTIONS_BUS1 1
extern int griommu_master_setup(int master, int group, int options);
extern int griommu_master_find(int vendor, int device, int instance);
extern int griommu_master_info(int master, uint32_t * info);
#define griommu_get_master_vendor(info) \
((info & MASTER_VENDOR) >> MASTER_VENDOR_BIT)
#define griommu_get_master_device(info) \
((info & MASTER_DEVICE) >> MASTER_DEVICE_BIT)
#define griommu_get_master_routing(info) \
((info & MASTER_BS) >> MASTER_BS_BIT)
#define griommu_get_master_group(info) \
((info & MASTER_GROUP) >> MASTER_GROUP_BIT)
extern int griommu_master_setup( int master, int group, int options );
extern int griommu_master_find( int vendor, int device, int instance );
extern int griommu_master_info( int master, uint32_t *info );
#define griommu_get_master_vendor( info ) \
( ( info & MASTER_VENDOR ) >> MASTER_VENDOR_BIT )
#define griommu_get_master_device( info ) \
( ( info & MASTER_DEVICE ) >> MASTER_DEVICE_BIT )
#define griommu_get_master_routing( info ) \
( ( info & MASTER_BS ) >> MASTER_BS_BIT )
#define griommu_get_master_group( info ) \
( ( info & MASTER_GROUP ) >> MASTER_GROUP_BIT )
/* IOMMU Group Setup */
#define GRIOMMU_OPTIONS_GROUP_PASSTHROUGH 2
#define GRIOMMU_OPTIONS_GROUP_ENABLE 1
#define GRIOMMU_OPTIONS_GROUP_DISABLE 0
extern int griommu_group_setup(int group, void * apv, int options);
extern int griommu_group_info(int group, uint32_t * info);
#define GRIOMMU_OPTIONS_APV_ALLOW 0x1
#define GRIOMMU_OPTIONS_GROUP_ENABLE 1
#define GRIOMMU_OPTIONS_GROUP_DISABLE 0
extern int griommu_group_setup( int group, void *apv, int options );
extern int griommu_group_info( int group, uint32_t *info );
#define GRIOMMU_OPTIONS_APV_ALLOW 0x1
#define GRIOMMU_OPTIONS_APV_DONTALLOW 0x0
extern int griommu_group_apv_init(int group, int options);
extern int griommu_group_apv_address_set(int group, uint32_t addr, int size,
int options);
extern int griommu_group_apv_page_set(int group, int index, int size,
int options);
extern int griommu_group_apv_flush(int group);
extern int griommu_group_apv_init( int group, int options );
extern int griommu_group_apv_address_set(
int group,
uint32_t addr,
int size,
int options
);
extern int griommu_group_apv_page_set(
int group,
int index,
int size,
int options
);
extern int griommu_group_apv_flush( int group );
/* IOMMU Setup */
/*
* GRIOMMU CTRL register fields
*/
#define CTRL_PGSZ (0x7 << CTRL_PGSZ_BIT)
#define CTRL_LB (0x1 << CTRL_LB_BIT)
#define CTRL_SP (0x1 << CTRL_SP_BIT)
#define CTRL_ITR (0xf << CTRL_ITR_BIT)
#define CTRL_DP (0x1 << CTRL_DP_BIT)
#define CTRL_SIV (0x1 << CTRL_SIV_BIT)
#define CTRL_HPROT (0x3 << CTRL_HPROT_BIT)
#define CTRL_AU (0x1 << CTRL_AU_BIT)
#define CTRL_WP (0x1 << CTRL_WP_BIT)
#define CTRL_DM (0x1 << CTRL_DM_BIT)
#define CTRL_GS (0x1 << CTRL_GS_BIT)
#define CTRL_CE (0x1 << CTRL_CE_BIT)
#define CTRL_PM (0x3 << CTRL_PM_BIT)
#define CTRL_PM_APV (0x0 << CTRL_PM_BIT)
#define CTRL_PM_IOMMU (0x1 << CTRL_PM_BIT)
#define CTRL_EN (0x1 << CTRL_EN_BIT)
#define CTRL_PGSZ ( 0x7 << CTRL_PGSZ_BIT )
#define CTRL_LB ( 0x1 << CTRL_LB_BIT )
#define CTRL_SP ( 0x1 << CTRL_SP_BIT )
#define CTRL_ITR ( 0xf << CTRL_ITR_BIT )
#define CTRL_DP ( 0x1 << CTRL_DP_BIT )
#define CTRL_SIV ( 0x1 << CTRL_SIV_BIT )
#define CTRL_HPROT ( 0x3 << CTRL_HPROT_BIT )
#define CTRL_AU ( 0x1 << CTRL_AU_BIT )
#define CTRL_WP ( 0x1 << CTRL_WP_BIT )
#define CTRL_DM ( 0x1 << CTRL_DM_BIT )
#define CTRL_GS ( 0x1 << CTRL_GS_BIT )
#define CTRL_CE ( 0x1 << CTRL_CE_BIT )
#define CTRL_PM ( 0x3 << CTRL_PM_BIT )
#define CTRL_PM_APV ( 0x0 << CTRL_PM_BIT )
#define CTRL_PM_IOMMU ( 0x1 << CTRL_PM_BIT )
#define CTRL_EN ( 0x1 << CTRL_EN_BIT )
#define CTRL_PGSZ_BIT 18
#define CTRL_LB_BIT 17
#define CTRL_SP_BIT 16
#define CTRL_ITR_BIT 12
#define CTRL_DP_BIT 11
#define CTRL_SIV_BIT 10
#define CTRL_PGSZ_BIT 18
#define CTRL_LB_BIT 17
#define CTRL_SP_BIT 16
#define CTRL_ITR_BIT 12
#define CTRL_DP_BIT 11
#define CTRL_SIV_BIT 10
#define CTRL_HPROT_BIT 8
#define CTRL_AU_BIT 7
#define CTRL_WP_BIT 6
#define CTRL_DM_BIT 5
#define CTRL_GS_BIT 4
#define CTRL_CE_BIT 3
#define CTRL_PM_BIT 1
#define CTRL_EN_BIT 0
#define CTRL_AU_BIT 7
#define CTRL_WP_BIT 6
#define CTRL_DM_BIT 5
#define CTRL_GS_BIT 4
#define CTRL_CE_BIT 3
#define CTRL_PM_BIT 1
#define CTRL_EN_BIT 0
#define GRIOMMU_OPTIONS_LOOKUPBUS_BUS0 0
#define GRIOMMU_OPTIONS_LOOKUPBUS_BUS1 CTRL_LB
#define GRIOMMU_OPTIONS_CACHE_DISABLE 0
#define GRIOMMU_OPTIONS_CACHE_ENABLE CTRL_CE
#define GRIOMMU_OPTIONS_LOOKUPBUS_BUS0 0
#define GRIOMMU_OPTIONS_LOOKUPBUS_BUS1 CTRL_LB
#define GRIOMMU_OPTIONS_CACHE_DISABLE 0
#define GRIOMMU_OPTIONS_CACHE_ENABLE CTRL_CE
#define GRIOMMU_OPTIONS_GROUPADDRESSING_DISABLE 0
#define GRIOMMU_OPTIONS_GROUPADDRESSING_ENABLE CTRL_GS
#define GRIOMMU_OPTIONS_WPROTONLY_DISABLE 0
#define GRIOMMU_OPTIONS_WPROTONLY_ENABLE CTRL_WP
#define GRIOMMU_OPTIONS_AHBUPDATE_DISABLE 0
#define GRIOMMU_OPTIONS_AHBUPDATE_ENABLE CTRL_AU
#define GRIOMMU_OPTIONS_PREFETCH_DISABLE CTRL_DP
#define GRIOMMU_OPTIONS_PREFETCH_ENABLE 0
#define GRIOMMU_OPTIONS_PAGESIZE_4KIB 0
#define GRIOMMU_OPTIONS_PAGESIZE_8KIB (0x1 << CTRL_PGSZ_BIT)
#define GRIOMMU_OPTIONS_PAGESIZE_16KIB (0x2 << CTRL_PGSZ_BIT)
#define GRIOMMU_OPTIONS_PAGESIZE_32KIB (0x3 << CTRL_PGSZ_BIT)
#define GRIOMMU_OPTIONS_PAGESIZE_64KIB (0x4 << CTRL_PGSZ_BIT)
#define GRIOMMU_OPTIONS_PAGESIZE_128KIB (0x5 << CTRL_PGSZ_BIT)
#define GRIOMMU_OPTIONS_PAGESIZE_256KIB (0x6 << CTRL_PGSZ_BIT)
#define GRIOMMU_OPTIONS_PAGESIZE_512KIB (0x7 << CTRL_PGSZ_BIT)
extern int griommu_setup(int options);
extern int griommu_status(void);
#define GRIOMMU_OPTIONS_GROUPADDRESSING_ENABLE CTRL_GS
#define GRIOMMU_OPTIONS_WPROTONLY_DISABLE 0
#define GRIOMMU_OPTIONS_WPROTONLY_ENABLE CTRL_WP
#define GRIOMMU_OPTIONS_AHBUPDATE_DISABLE 0
#define GRIOMMU_OPTIONS_AHBUPDATE_ENABLE CTRL_AU
#define GRIOMMU_OPTIONS_PREFETCH_DISABLE CTRL_DP
#define GRIOMMU_OPTIONS_PREFETCH_ENABLE 0
#define GRIOMMU_OPTIONS_PAGESIZE_4KIB 0
#define GRIOMMU_OPTIONS_PAGESIZE_8KIB ( 0x1 << CTRL_PGSZ_BIT )
#define GRIOMMU_OPTIONS_PAGESIZE_16KIB ( 0x2 << CTRL_PGSZ_BIT )
#define GRIOMMU_OPTIONS_PAGESIZE_32KIB ( 0x3 << CTRL_PGSZ_BIT )
#define GRIOMMU_OPTIONS_PAGESIZE_64KIB ( 0x4 << CTRL_PGSZ_BIT )
#define GRIOMMU_OPTIONS_PAGESIZE_128KIB ( 0x5 << CTRL_PGSZ_BIT )
#define GRIOMMU_OPTIONS_PAGESIZE_256KIB ( 0x6 << CTRL_PGSZ_BIT )
#define GRIOMMU_OPTIONS_PAGESIZE_512KIB ( 0x7 << CTRL_PGSZ_BIT )
extern int griommu_setup( int options );
extern int griommu_status( void );
#define GRIOMMU_MODE_IOMMU 1
#define GRIOMMU_MODE_IOMMU 1
#define GRIOMMU_MODE_GROUPAPV 0
extern int griommu_enable(int mode);
extern int griommu_disable(void);
extern int griommu_enable( int mode );
extern int griommu_disable( void );
/* IOMMU APV setup */
extern int griommu_apv_flush(void);
extern int griommu_apv_init(void * apv, int options);
extern int griommu_apv_address_set(void * apv, uint32_t addr, int size,
int options);
extern int griommu_apv_page_set(void * apv, int index, int size, int options);
extern int griommu_apv_flush( void );
extern int griommu_apv_init( void *apv, int options );
extern int griommu_apv_address_set(
void *apv,
uint32_t addr,
int size,
int options
);
extern int griommu_apv_page_set( void *apv, int index, int size, int options );
/* GRIOMMU Interrupts */
/* Function Interrupt-Code ISR callback prototype.
@@ -183,21 +195,21 @@ extern int griommu_apv_page_set(void * apv, int index, int size, int options);
* access - AHB Access that failed
* status - Error status register of the GRIOMMU core
*/
typedef void (*griommu_isr_t)(void *arg, uint32_t access, uint32_t status);
#define GRIOMMU_INTERRUPT_ALL (0x2f << 0)
#define GRIOMMU_INTERRUPT_PARITY_ERROR (0x1 << 5)
#define GRIOMMU_INTERRUPT_FLUSH_COMPLETED (0x1 << 3)
#define GRIOMMU_INTERRUPT_FLUSH_START (0x1 << 2)
#define GRIOMMU_INTERRUPT_ACCESS_DENIED (0x1 << 1)
#define GRIOMMU_INTERRUPT_TRANSLATION_ERROR (0x1 << 0)
extern int griommu_isr_register(griommu_isr_t isr, void * arg, int options);
extern int griommu_isr_unregister(void);
extern int griommu_interrupt_unmask(int options);
extern int griommu_interrupt_mask(int options);
typedef void ( *griommu_isr_t )( void *arg, uint32_t access, uint32_t status );
#define GRIOMMU_INTERRUPT_ALL ( 0x2f << 0 )
#define GRIOMMU_INTERRUPT_PARITY_ERROR ( 0x1 << 5 )
#define GRIOMMU_INTERRUPT_FLUSH_COMPLETED ( 0x1 << 3 )
#define GRIOMMU_INTERRUPT_FLUSH_START ( 0x1 << 2 )
#define GRIOMMU_INTERRUPT_ACCESS_DENIED ( 0x1 << 1 )
#define GRIOMMU_INTERRUPT_TRANSLATION_ERROR ( 0x1 << 0 )
extern int griommu_isr_register( griommu_isr_t isr, void *arg, int options );
extern int griommu_isr_unregister( void );
extern int griommu_interrupt_unmask( int options );
extern int griommu_interrupt_mask( int options );
extern int griommu_error_status(uint32_t * access);
extern int griommu_error_status( uint32_t *access );
extern int griommu_print(void);
extern int griommu_print( void );
#ifdef __cplusplus
}
bsps/include/grlib/grlib.h
+59 -53
View File
@@ -67,47 +67,47 @@ struct apbuart_regs {
/* IRQMP and IRQAMP interrupt controller timestamps */
struct irqmp_timestamp_regs {
volatile uint32_t counter; /* 0x00 */
volatile uint32_t control; /* 0x04 */
volatile uint32_t assertion; /* 0x08 */
volatile uint32_t ack; /* 0x0c */
volatile uint32_t counter; /* 0x00 */
volatile uint32_t control; /* 0x04 */
volatile uint32_t assertion; /* 0x08 */
volatile uint32_t ack; /* 0x0c */
};
static inline bool irqmp_has_timestamp(
volatile struct irqmp_timestamp_regs *irqmp_ts
)
{
return (irqmp_ts->control >> 27) > 0;
return ( irqmp_ts->control >> 27 ) > 0;
}
/* IRQMP and IRQAMP interrupt controllers */
struct irqmp_regs {
volatile uint32_t ilevel; /* 0x00 */
volatile uint32_t ipend; /* 0x04 */
volatile uint32_t iforce; /* 0x08 */
volatile uint32_t iclear; /* 0x0c */
volatile uint32_t mpstat; /* 0x10 */
volatile uint32_t bcast; /* 0x14 */
volatile uint32_t notused02; /* 0x18 */
volatile uint32_t wdgctrl; /* 0x1c */
volatile uint32_t ampctrl; /* 0x20 */
volatile uint32_t icsel[2]; /* 0x24,0x28 */
volatile uint32_t notused13; /* 0x2c */
volatile uint32_t notused20; /* 0x30 */
volatile uint32_t notused21; /* 0x34 */
volatile uint32_t notused22; /* 0x38 */
volatile uint32_t notused23; /* 0x3c */
volatile uint32_t mask[16]; /* 0x40 */
volatile uint32_t force[16]; /* 0x80 */
volatile uint32_t ilevel; /* 0x00 */
volatile uint32_t ipend; /* 0x04 */
volatile uint32_t iforce; /* 0x08 */
volatile uint32_t iclear; /* 0x0c */
volatile uint32_t mpstat; /* 0x10 */
volatile uint32_t bcast; /* 0x14 */
volatile uint32_t notused02; /* 0x18 */
volatile uint32_t wdgctrl; /* 0x1c */
volatile uint32_t ampctrl; /* 0x20 */
volatile uint32_t icsel[ 2 ]; /* 0x24,0x28 */
volatile uint32_t notused13; /* 0x2c */
volatile uint32_t notused20; /* 0x30 */
volatile uint32_t notused21; /* 0x34 */
volatile uint32_t notused22; /* 0x38 */
volatile uint32_t notused23; /* 0x3c */
volatile uint32_t mask[ 16 ]; /* 0x40 */
volatile uint32_t force[ 16 ]; /* 0x80 */
/* Extended IRQ registers */
volatile uint32_t intid[16]; /* 0xc0 */
volatile struct irqmp_timestamp_regs timestamp[16]; /* 0x100 */
volatile uint32_t resetaddr[4]; /* 0x200 */
volatile uint32_t resv0[12]; /* 0x210 - 0x23C */
volatile uint32_t pboot; /* 0x240 */
volatile uint32_t resv1[47]; /* 0x244 - 0x2FC */
volatile uint32_t irqmap[8]; /* 0x300 - 0x31C */
volatile uint32_t resv2[824]; /* 0x320 - 0x1000 */
volatile uint32_t intid[ 16 ]; /* 0xc0 */
volatile struct irqmp_timestamp_regs timestamp[ 16 ]; /* 0x100 */
volatile uint32_t resetaddr[ 4 ]; /* 0x200 */
volatile uint32_t resv0[ 12 ]; /* 0x210 - 0x23C */
volatile uint32_t pboot; /* 0x240 */
volatile uint32_t resv1[ 47 ]; /* 0x244 - 0x2FC */
volatile uint32_t irqmap[ 8 ]; /* 0x300 - 0x31C */
volatile uint32_t resv2[ 824 ]; /* 0x320 - 0x1000 */
};
/* GPTIMER Timer instance */
@@ -128,11 +128,11 @@ struct gptimer_timer_regs {
/* GPTIMER common registers */
struct gptimer_regs {
volatile uint32_t scaler_value; /* common timer registers */
volatile uint32_t scaler_reload;
volatile uint32_t cfg;
volatile uint32_t notused;
struct gptimer_timer_regs timer[7];
volatile uint32_t scaler_value; /* common timer registers */
volatile uint32_t scaler_reload;
volatile uint32_t cfg;
volatile uint32_t notused;
struct gptimer_timer_regs timer[ 7 ];
};
/* GRGPIO GPIO */
@@ -145,7 +145,7 @@ struct grgpio_regs {
volatile uint32_t iedge; /* 0x14 Interrupt edge register */
volatile uint32_t bypass; /* 0x18 Bypass register */
volatile uint32_t cap; /* 0x1C Capability register */
volatile uint32_t irqmap[4]; /* 0x20 - 0x2C Interrupt map registers */
volatile uint32_t irqmap[ 4 ]; /* 0x20 - 0x2C Interrupt map registers */
volatile uint32_t res_30; /* 0x30 Reserved */
volatile uint32_t res_34; /* 0x34 Reserved */
volatile uint32_t res_38; /* 0x38 Reserved */
@@ -155,17 +155,21 @@ struct grgpio_regs {
volatile uint32_t res_48; /* 0x48 Reserved */
volatile uint32_t pulse; /* 0x4C Pulse register */
volatile uint32_t res_50; /* 0x50 Reserved */
volatile uint32_t output_or; /* 0x54 I/O port output register, logical-OR */
volatile uint32_t dir_or; /* 0x58 I/O port direction register, logical-OR */
volatile uint32_t imask_or; /* 0x5C Interrupt mask register, logical-OR */
volatile uint32_t res_60; /* 0x60 Reserved */
volatile uint32_t output_and; /* 0x64 I/O port output register, logical-AND */
volatile uint32_t dir_and; /* 0x68 I/O port direction register, logical-AND */
volatile uint32_t imask_and; /* 0x6C Interrupt mask register, logical-AND */
volatile uint32_t res_70; /* 0x70 Reserved */
volatile uint32_t output_xor; /* 0x74 I/O port output register, logical-XOR */
volatile uint32_t dir_xor; /* 0x78 I/O port direction register, logical-XOR */
volatile uint32_t imask_xor; /* 0x7C Interrupt mask register, logical-XOR */
volatile uint32_t output_or; /* 0x54 I/O port output register, logical-OR */
volatile uint32_t dir_or; /* 0x58 I/O port direction register, logical-OR */
volatile uint32_t imask_or; /* 0x5C Interrupt mask register, logical-OR */
volatile uint32_t res_60; /* 0x60 Reserved */
volatile uint32_t
output_and; /* 0x64 I/O port output register, logical-AND */
volatile uint32_t
dir_and; /* 0x68 I/O port direction register, logical-AND */
volatile uint32_t imask_and; /* 0x6C Interrupt mask register, logical-AND */
volatile uint32_t res_70; /* 0x70 Reserved */
volatile uint32_t
output_xor; /* 0x74 I/O port output register, logical-XOR */
volatile uint32_t
dir_xor; /* 0x78 I/O port direction register, logical-XOR */
volatile uint32_t imask_xor; /* 0x7C Interrupt mask register, logical-XOR */
};
/* L2C - Level 2 Cache Controller registers */
@@ -186,12 +190,14 @@ struct l2c_regs {
volatile uint32_t scrub_delay; /* 0x34 Scrub Delay */
volatile uint32_t error_injection; /* 0x38 Error injection */
volatile uint32_t access_control; /* 0x3c Access control */
volatile uint32_t reserved_40[16]; /* 0x40 Reserved */
volatile uint32_t mtrr[32]; /* 0x80 - 0xFC MTRR registers */
volatile uint32_t reserved_100[131008]; /* 0x100 Reserved */
volatile uint32_t diag_iface_tag[16384]; /* 0x80000 - 0x8FFFC Diagnostic interface (Tag) */
volatile uint32_t reserved_90000[376832]; /* 0x90000 Reserved */
volatile uint32_t diag_iface_data[524288];/* 0x200000 - 0x3FFFFC Diagnostic interface (Data) */
volatile uint32_t reserved_40[ 16 ]; /* 0x40 Reserved */
volatile uint32_t mtrr[ 32 ]; /* 0x80 - 0xFC MTRR registers */
volatile uint32_t reserved_100[ 131008 ]; /* 0x100 Reserved */
volatile uint32_t
diag_iface_tag[ 16384 ]; /* 0x80000 - 0x8FFFC Diagnostic interface (Tag) */
volatile uint32_t reserved_90000[ 376832 ]; /* 0x90000 Reserved */
volatile uint32_t diag_iface_data
[ 524288 ]; /* 0x200000 - 0x3FFFFC Diagnostic interface (Data) */
};
#ifdef __cplusplus
bsps/include/grlib/grlib_impl.h
+82 -75
View File
@@ -36,25 +36,32 @@
* Use interrupt lock primitives compatible with SMP defined in RTEMS 4.11.99
* and higher.
*/
#if (((__RTEMS_MAJOR__ << 16) | (__RTEMS_MINOR__ << 8) | __RTEMS_REVISION__) >= 0x040b63)
#if ( \
( ( __RTEMS_MAJOR__ << 16 ) | ( __RTEMS_MINOR__ << 8 ) | \
__RTEMS_REVISION__ ) >= 0x040b63 \
)
#include <rtems/score/isrlock.h>
/* map via rtems_interrupt_lock_* API: */
#define SPIN_DECLARE(lock) RTEMS_INTERRUPT_LOCK_MEMBER(lock)
#define SPIN_INIT(lock, name) rtems_interrupt_lock_initialize(lock, name)
#define SPIN_LOCK(lock, level) rtems_interrupt_lock_acquire_isr(lock, &level)
#define SPIN_LOCK_IRQ(lock, level) rtems_interrupt_lock_acquire(lock, &level)
#define SPIN_UNLOCK(lock, level) rtems_interrupt_lock_release_isr(lock, &level)
#define SPIN_UNLOCK_IRQ(lock, level) rtems_interrupt_lock_release(lock, &level)
#define SPIN_IRQFLAGS(k) rtems_interrupt_lock_context k
#define SPIN_ISR_IRQFLAGS(k) SPIN_IRQFLAGS(k)
#define SPIN_FREE(lock) rtems_interrupt_lock_destroy(lock)
#define SPIN_DECLARE( lock ) RTEMS_INTERRUPT_LOCK_MEMBER( lock )
#define SPIN_INIT( lock, name ) rtems_interrupt_lock_initialize( lock, name )
#define SPIN_LOCK( lock, level ) \
rtems_interrupt_lock_acquire_isr( lock, &level )
#define SPIN_LOCK_IRQ( lock, level ) \
rtems_interrupt_lock_acquire( lock, &level )
#define SPIN_UNLOCK( lock, level ) \
rtems_interrupt_lock_release_isr( lock, &level )
#define SPIN_UNLOCK_IRQ( lock, level ) \
rtems_interrupt_lock_release( lock, &level )
#define SPIN_IRQFLAGS( k ) rtems_interrupt_lock_context k
#define SPIN_ISR_IRQFLAGS( k ) SPIN_IRQFLAGS( k )
#define SPIN_FREE( lock ) rtems_interrupt_lock_destroy( lock )
/* turn on/off local CPU's interrupt to ensure HW timing - not SMP safe. */
#define IRQ_LOCAL_DECLARE(_level) rtems_interrupt_level _level
#define IRQ_LOCAL_DISABLE(_level) rtems_interrupt_local_disable(_level)
#define IRQ_LOCAL_ENABLE(_level) rtems_interrupt_local_enable(_level)
#define IRQ_LOCAL_DECLARE( _level ) rtems_interrupt_level _level
#define IRQ_LOCAL_DISABLE( _level ) rtems_interrupt_local_disable( _level )
#define IRQ_LOCAL_ENABLE( _level ) rtems_interrupt_local_enable( _level )
#else
@@ -63,20 +70,20 @@
#endif
/* maintain single-core compatibility with older versions of RTEMS: */
#define SPIN_DECLARE(name)
#define SPIN_INIT(lock, name)
#define SPIN_LOCK(lock, level)
#define SPIN_LOCK_IRQ(lock, level) rtems_interrupt_disable(level)
#define SPIN_UNLOCK(lock, level)
#define SPIN_UNLOCK_IRQ(lock, level) rtems_interrupt_enable(level)
#define SPIN_IRQFLAGS(k) rtems_interrupt_level k
#define SPIN_ISR_IRQFLAGS(k)
#define SPIN_FREE(lock)
#define SPIN_DECLARE( name )
#define SPIN_INIT( lock, name )
#define SPIN_LOCK( lock, level )
#define SPIN_LOCK_IRQ( lock, level ) rtems_interrupt_disable( level )
#define SPIN_UNLOCK( lock, level )
#define SPIN_UNLOCK_IRQ( lock, level ) rtems_interrupt_enable( level )
#define SPIN_IRQFLAGS( k ) rtems_interrupt_level k
#define SPIN_ISR_IRQFLAGS( k )
#define SPIN_FREE( lock )
/* turn on/off local CPU's interrupt to ensure HW timing - not SMP safe. */
#define IRQ_LOCAL_DECLARE(_level) rtems_interrupt_level _level
#define IRQ_LOCAL_DISABLE(_level) rtems_interrupt_disable(_level)
#define IRQ_LOCAL_ENABLE(_level) rtems_interrupt_enable(_level)
#define IRQ_LOCAL_DECLARE( _level ) rtems_interrupt_level _level
#define IRQ_LOCAL_DISABLE( _level ) rtems_interrupt_disable( _level )
#define IRQ_LOCAL_ENABLE( _level ) rtems_interrupt_enable( _level )
#endif
@@ -84,99 +91,99 @@
extern "C" {
#endif
#if (((__RTEMS_MAJOR__ << 16) | (__RTEMS_MINOR__ << 8) | __RTEMS_REVISION__) >= 0x050000)
#if ( \
( ( __RTEMS_MAJOR__ << 16 ) | ( __RTEMS_MINOR__ << 8 ) | \
__RTEMS_REVISION__ ) >= 0x050000 \
)
static inline void *grlib_malloc(size_t size)
static inline void *grlib_malloc( size_t size )
{
return rtems_malloc(size);
return rtems_malloc( size );
}
static inline void *grlib_calloc(size_t nelem, size_t elsize)
static inline void *grlib_calloc( size_t nelem, size_t elsize )
{
return rtems_calloc(nelem, elsize);
return rtems_calloc( nelem, elsize );
}
#else
static inline void *grlib_malloc(size_t size)
static inline void *grlib_malloc( size_t size )
{
return malloc(size);
return malloc( size );
}
static inline void *grlib_calloc(size_t nelem, size_t elsize)
static inline void *grlib_calloc( size_t nelem, size_t elsize )
{
return calloc(nelem, elsize);
return calloc( nelem, elsize );
}
#endif
#ifdef __sparc__
static inline uint8_t grlib_read_uncached8(uintptr_t address)
static inline uint8_t grlib_read_uncached8( uintptr_t address )
{
uint8_t tmp;
__asm__ (" lduba [%1]1, %0 "
: "=r"(tmp)
: "r"(address)
);
return tmp;
uint8_t tmp;
__asm__( " lduba [%1]1, %0 "
: "=r"( tmp )
: "r"( address ) );
return tmp;
}
static inline uint16_t grlib_read_uncached16(uintptr_t addr) {
uint16_t tmp;
__asm__ (" lduha [%1]1, %0 "
: "=r"(tmp)
: "r"(addr)
);
return tmp;
static inline uint16_t grlib_read_uncached16( uintptr_t addr )
{
uint16_t tmp;
__asm__( " lduha [%1]1, %0 "
: "=r"( tmp )
: "r"( addr ) );
return tmp;
}
static inline uint32_t grlib_read_uncached32(uintptr_t address)
static inline uint32_t grlib_read_uncached32( uintptr_t address )
{
uint32_t tmp;
__asm__ (" lda [%1]1, %0 "
: "=r"(tmp)
: "r"(address)
);
return tmp;
uint32_t tmp;
__asm__( " lda [%1]1, %0 "
: "=r"( tmp )
: "r"( address ) );
return tmp;
}
static inline uint64_t grlib_read_uncached64(uint64_t *address)
static inline uint64_t grlib_read_uncached64( uint64_t *address )
{
uint64_t tmp;
__asm__ (" ldda [%1]1, %0 "
: "=r"(tmp)
: "r"(address)
);
return tmp;
uint64_t tmp;
__asm__( " ldda [%1]1, %0 "
: "=r"( tmp )
: "r"( address ) );
return tmp;
}
#define GRLIB_DMA_IS_CACHE_COHERENT CPU_SPARC_HAS_SNOOPING
#else
static inline uint8_t grlib_read_uncached8(uintptr_t address)
static inline uint8_t grlib_read_uncached8( uintptr_t address )
{
uint8_t tmp = (*(volatile uint8_t *)(address));
return tmp;
uint8_t tmp = ( *(volatile uint8_t *) ( address ) );
return tmp;
}
static inline uint16_t grlib_read_uncached16(uintptr_t address) {
uint16_t tmp = (*(volatile uint16_t *)(address));
return tmp;
static inline uint16_t grlib_read_uncached16( uintptr_t address )
{
uint16_t tmp = ( *(volatile uint16_t *) ( address ) );
return tmp;
}
static inline uint32_t grlib_read_uncached32(uintptr_t address)
static inline uint32_t grlib_read_uncached32( uintptr_t address )
{
uint32_t tmp = (*(volatile uint32_t *)(address));
return tmp;
uint32_t tmp = ( *(volatile uint32_t *) ( address ) );
return tmp;
}
static inline uint64_t grlib_read_uncached64(uintptr_t address)
static inline uint64_t grlib_read_uncached64( uintptr_t address )
{
uint64_t tmp = (*(volatile uint64_t *)(address));
return tmp;
uint64_t tmp = ( *(volatile uint64_t *) ( address ) );
return tmp;
}
#define GRLIB_DMA_IS_CACHE_COHERENT 1
bsps/include/grlib/grpci.h
+9 -7
View File
@@ -35,23 +35,25 @@ extern "C" {
#endif
/* Register the GRPCI driver to the Driver Manager */
extern void grpci_register_drv(void);
extern void grpci_register_drv( void );
/* Transfer data using GRPCI DMA unit from AMBA to PCI space. Blocks until
* operation completes.
*/
int grpci_dma_to_pci(
unsigned int ahb_addr,
unsigned int pci_addr,
unsigned int len);
unsigned int ahb_addr,
unsigned int pci_addr,
unsigned int len
);
/* Transfer data using GRPCI DMA unit from PCI to AMBA space. Blocks until
* operation completes.
*/
int grpci_dma_from_pci(
unsigned int ahb_addr,
unsigned int pci_addr,
unsigned int len);
unsigned int ahb_addr,
unsigned int pci_addr,
unsigned int len
);
#ifdef __cplusplus
}

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