diff --git a/bsps/include/grlib/ahbstat-regs.h b/bsps/include/grlib/ahbstat-regs.h index 6e50814da7..16daa55976 100644 --- a/bsps/include/grlib/ahbstat-regs.h +++ b/bsps/include/grlib/ahbstat-regs.h @@ -96,30 +96,25 @@ extern "C" { #define AHBSTAT_AHBS_HWRITE 0x80U #define AHBSTAT_AHBS_HMASTER_SHIFT 3 -#define AHBSTAT_AHBS_HMASTER_MASK 0x78U +#define AHBSTAT_AHBS_HMASTER_MASK 0x78U #define AHBSTAT_AHBS_HMASTER_GET( _reg ) \ - ( ( ( _reg ) & AHBSTAT_AHBS_HMASTER_MASK ) >> \ - AHBSTAT_AHBS_HMASTER_SHIFT ) -#define AHBSTAT_AHBS_HMASTER_SET( _reg, _val ) \ - ( ( ( _reg ) & ~AHBSTAT_AHBS_HMASTER_MASK ) | \ + ( ( ( _reg ) & AHBSTAT_AHBS_HMASTER_MASK ) >> AHBSTAT_AHBS_HMASTER_SHIFT ) +#define AHBSTAT_AHBS_HMASTER_SET( _reg, _val ) \ + ( ( ( _reg ) & ~AHBSTAT_AHBS_HMASTER_MASK ) | \ ( ( ( _val ) << AHBSTAT_AHBS_HMASTER_SHIFT ) & \ AHBSTAT_AHBS_HMASTER_MASK ) ) #define AHBSTAT_AHBS_HMASTER( _val ) \ - ( ( ( _val ) << AHBSTAT_AHBS_HMASTER_SHIFT ) & \ - AHBSTAT_AHBS_HMASTER_MASK ) + ( ( ( _val ) << AHBSTAT_AHBS_HMASTER_SHIFT ) & AHBSTAT_AHBS_HMASTER_MASK ) #define AHBSTAT_AHBS_HSIZE_SHIFT 0 -#define AHBSTAT_AHBS_HSIZE_MASK 0x7U +#define AHBSTAT_AHBS_HSIZE_MASK 0x7U #define AHBSTAT_AHBS_HSIZE_GET( _reg ) \ - ( ( ( _reg ) & AHBSTAT_AHBS_HSIZE_MASK ) >> \ - AHBSTAT_AHBS_HSIZE_SHIFT ) -#define AHBSTAT_AHBS_HSIZE_SET( _reg, _val ) \ + ( ( ( _reg ) & AHBSTAT_AHBS_HSIZE_MASK ) >> AHBSTAT_AHBS_HSIZE_SHIFT ) +#define AHBSTAT_AHBS_HSIZE_SET( _reg, _val ) \ ( ( ( _reg ) & ~AHBSTAT_AHBS_HSIZE_MASK ) | \ - ( ( ( _val ) << AHBSTAT_AHBS_HSIZE_SHIFT ) & \ - AHBSTAT_AHBS_HSIZE_MASK ) ) + ( ( ( _val ) << AHBSTAT_AHBS_HSIZE_SHIFT ) & AHBSTAT_AHBS_HSIZE_MASK ) ) #define AHBSTAT_AHBS_HSIZE( _val ) \ - ( ( ( _val ) << AHBSTAT_AHBS_HSIZE_SHIFT ) & \ - AHBSTAT_AHBS_HSIZE_MASK ) + ( ( ( _val ) << AHBSTAT_AHBS_HSIZE_SHIFT ) & AHBSTAT_AHBS_HSIZE_MASK ) /** @} */ @@ -133,17 +128,15 @@ extern "C" { */ #define AHBSTAT_AHBFAR_HADDR_SHIFT 0 -#define AHBSTAT_AHBFAR_HADDR_MASK 0xffffffffU +#define AHBSTAT_AHBFAR_HADDR_MASK 0xffffffffU #define AHBSTAT_AHBFAR_HADDR_GET( _reg ) \ - ( ( ( _reg ) & AHBSTAT_AHBFAR_HADDR_MASK ) >> \ - AHBSTAT_AHBFAR_HADDR_SHIFT ) -#define AHBSTAT_AHBFAR_HADDR_SET( _reg, _val ) \ - ( ( ( _reg ) & ~AHBSTAT_AHBFAR_HADDR_MASK ) | \ + ( ( ( _reg ) & AHBSTAT_AHBFAR_HADDR_MASK ) >> AHBSTAT_AHBFAR_HADDR_SHIFT ) +#define AHBSTAT_AHBFAR_HADDR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~AHBSTAT_AHBFAR_HADDR_MASK ) | \ ( ( ( _val ) << AHBSTAT_AHBFAR_HADDR_SHIFT ) & \ AHBSTAT_AHBFAR_HADDR_MASK ) ) #define AHBSTAT_AHBFAR_HADDR( _val ) \ - ( ( ( _val ) << AHBSTAT_AHBFAR_HADDR_SHIFT ) & \ - AHBSTAT_AHBFAR_HADDR_MASK ) + ( ( ( _val ) << AHBSTAT_AHBFAR_HADDR_SHIFT ) & AHBSTAT_AHBFAR_HADDR_MASK ) /** @} */ diff --git a/bsps/include/grlib/ahbstat.h b/bsps/include/grlib/ahbstat.h index c6502ab4b0..fbd0ddc9c4 100644 --- a/bsps/include/grlib/ahbstat.h +++ b/bsps/include/grlib/ahbstat.h @@ -38,10 +38,10 @@ extern "C" { /* AHBSTAT Registers layout */ struct ahbstat_regs { - volatile uint32_t status; - volatile uint32_t failing; - volatile uint32_t status2; - volatile uint32_t failing2; + volatile uint32_t status; + volatile uint32_t failing; + volatile uint32_t status2; + volatile uint32_t failing2; }; /* AHB fail interrupt callback to user. This function is declared weak so that @@ -59,11 +59,12 @@ struct ahbstat_regs { * 2: just print error * 3: do nothing, let user do custom handling */ -extern int (*ahbstat_error)( - int minor, - struct ahbstat_regs *regs, - uint32_t status, - uint32_t failing_address); +extern int ( *ahbstat_error )( + int minor, + struct ahbstat_regs *regs, + uint32_t status, + uint32_t failing_address +); /* Get Last received AHB Error * @@ -76,7 +77,11 @@ extern int (*ahbstat_error)( * 1: Error Received, last status and address stored into argument pointers * -1: No such AHBSTAT device */ -extern int ahbstat_last_error(int minor, uint32_t *status, uint32_t *address); +extern int ahbstat_last_error( + int minor, + uint32_t *status, + uint32_t *address +); /* Get AHBSTAT registers address from minor. Can also be used to check if * AHBSTAT hardware is present. @@ -85,10 +90,10 @@ extern int ahbstat_last_error(int minor, uint32_t *status, uint32_t *address); * NULL returned if no such device * non-zero Address to AHBSTAT register */ -extern struct ahbstat_regs *ahbstat_get_regs(int minor); +extern struct ahbstat_regs *ahbstat_get_regs( int minor ); /* Registers the AHBSTAT driver to the Driver Manager */ -void ahbstat_register_drv (void); +void ahbstat_register_drv( void ); #ifdef __cplusplus } diff --git a/bsps/include/grlib/ahbtrace-regs.h b/bsps/include/grlib/ahbtrace-regs.h index 4526326894..a18b2b0ef7 100644 --- a/bsps/include/grlib/ahbtrace-regs.h +++ b/bsps/include/grlib/ahbtrace-regs.h @@ -82,32 +82,26 @@ extern "C" { */ #define AHBTRACE_CTRL_DCNT_SHIFT 16 -#define AHBTRACE_CTRL_DCNT_MASK 0x7f0000U +#define AHBTRACE_CTRL_DCNT_MASK 0x7f0000U #define AHBTRACE_CTRL_DCNT_GET( _reg ) \ - ( ( ( _reg ) & AHBTRACE_CTRL_DCNT_MASK ) >> \ - AHBTRACE_CTRL_DCNT_SHIFT ) -#define AHBTRACE_CTRL_DCNT_SET( _reg, _val ) \ + ( ( ( _reg ) & AHBTRACE_CTRL_DCNT_MASK ) >> AHBTRACE_CTRL_DCNT_SHIFT ) +#define AHBTRACE_CTRL_DCNT_SET( _reg, _val ) \ ( ( ( _reg ) & ~AHBTRACE_CTRL_DCNT_MASK ) | \ - ( ( ( _val ) << AHBTRACE_CTRL_DCNT_SHIFT ) & \ - AHBTRACE_CTRL_DCNT_MASK ) ) + ( ( ( _val ) << AHBTRACE_CTRL_DCNT_SHIFT ) & AHBTRACE_CTRL_DCNT_MASK ) ) #define AHBTRACE_CTRL_DCNT( _val ) \ - ( ( ( _val ) << AHBTRACE_CTRL_DCNT_SHIFT ) & \ - AHBTRACE_CTRL_DCNT_MASK ) + ( ( ( _val ) << AHBTRACE_CTRL_DCNT_SHIFT ) & AHBTRACE_CTRL_DCNT_MASK ) #define AHBTRACE_CTRL_PF 0x100U #define AHBTRACE_CTRL_BW_SHIFT 6 -#define AHBTRACE_CTRL_BW_MASK 0xc0U +#define AHBTRACE_CTRL_BW_MASK 0xc0U #define AHBTRACE_CTRL_BW_GET( _reg ) \ - ( ( ( _reg ) & AHBTRACE_CTRL_BW_MASK ) >> \ - AHBTRACE_CTRL_BW_SHIFT ) -#define AHBTRACE_CTRL_BW_SET( _reg, _val ) \ + ( ( ( _reg ) & AHBTRACE_CTRL_BW_MASK ) >> AHBTRACE_CTRL_BW_SHIFT ) +#define AHBTRACE_CTRL_BW_SET( _reg, _val ) \ ( ( ( _reg ) & ~AHBTRACE_CTRL_BW_MASK ) | \ - ( ( ( _val ) << AHBTRACE_CTRL_BW_SHIFT ) & \ - AHBTRACE_CTRL_BW_MASK ) ) + ( ( ( _val ) << AHBTRACE_CTRL_BW_SHIFT ) & AHBTRACE_CTRL_BW_MASK ) ) #define AHBTRACE_CTRL_BW( _val ) \ - ( ( ( _val ) << AHBTRACE_CTRL_BW_SHIFT ) & \ - AHBTRACE_CTRL_BW_MASK ) + ( ( ( _val ) << AHBTRACE_CTRL_BW_SHIFT ) & AHBTRACE_CTRL_BW_MASK ) #define AHBTRACE_CTRL_RF 0x20U @@ -132,17 +126,15 @@ extern "C" { */ #define AHBTRACE_INDEX_INDEX_SHIFT 4 -#define AHBTRACE_INDEX_INDEX_MASK 0x7f0U +#define AHBTRACE_INDEX_INDEX_MASK 0x7f0U #define AHBTRACE_INDEX_INDEX_GET( _reg ) \ - ( ( ( _reg ) & AHBTRACE_INDEX_INDEX_MASK ) >> \ - AHBTRACE_INDEX_INDEX_SHIFT ) -#define AHBTRACE_INDEX_INDEX_SET( _reg, _val ) \ - ( ( ( _reg ) & ~AHBTRACE_INDEX_INDEX_MASK ) | \ + ( ( ( _reg ) & AHBTRACE_INDEX_INDEX_MASK ) >> AHBTRACE_INDEX_INDEX_SHIFT ) +#define AHBTRACE_INDEX_INDEX_SET( _reg, _val ) \ + ( ( ( _reg ) & ~AHBTRACE_INDEX_INDEX_MASK ) | \ ( ( ( _val ) << AHBTRACE_INDEX_INDEX_SHIFT ) & \ AHBTRACE_INDEX_INDEX_MASK ) ) #define AHBTRACE_INDEX_INDEX( _val ) \ - ( ( ( _val ) << AHBTRACE_INDEX_INDEX_SHIFT ) & \ - AHBTRACE_INDEX_INDEX_MASK ) + ( ( ( _val ) << AHBTRACE_INDEX_INDEX_SHIFT ) & AHBTRACE_INDEX_INDEX_MASK ) /** @} */ @@ -156,15 +148,15 @@ extern "C" { */ #define AHBTRACE_TIMETAG_TIMETAG_SHIFT 0 -#define AHBTRACE_TIMETAG_TIMETAG_MASK 0xffffffffU -#define AHBTRACE_TIMETAG_TIMETAG_GET( _reg ) \ +#define AHBTRACE_TIMETAG_TIMETAG_MASK 0xffffffffU +#define AHBTRACE_TIMETAG_TIMETAG_GET( _reg ) \ ( ( ( _reg ) & AHBTRACE_TIMETAG_TIMETAG_MASK ) >> \ AHBTRACE_TIMETAG_TIMETAG_SHIFT ) -#define AHBTRACE_TIMETAG_TIMETAG_SET( _reg, _val ) \ - ( ( ( _reg ) & ~AHBTRACE_TIMETAG_TIMETAG_MASK ) | \ +#define AHBTRACE_TIMETAG_TIMETAG_SET( _reg, _val ) \ + ( ( ( _reg ) & ~AHBTRACE_TIMETAG_TIMETAG_MASK ) | \ ( ( ( _val ) << AHBTRACE_TIMETAG_TIMETAG_SHIFT ) & \ AHBTRACE_TIMETAG_TIMETAG_MASK ) ) -#define AHBTRACE_TIMETAG_TIMETAG( _val ) \ +#define AHBTRACE_TIMETAG_TIMETAG( _val ) \ ( ( ( _val ) << AHBTRACE_TIMETAG_TIMETAG_SHIFT ) & \ AHBTRACE_TIMETAG_TIMETAG_MASK ) @@ -180,28 +172,28 @@ extern "C" { */ #define AHBTRACE_MSFILT_SMASK_15_0_SHIFT 16 -#define AHBTRACE_MSFILT_SMASK_15_0_MASK 0xffff0000U -#define AHBTRACE_MSFILT_SMASK_15_0_GET( _reg ) \ +#define AHBTRACE_MSFILT_SMASK_15_0_MASK 0xffff0000U +#define AHBTRACE_MSFILT_SMASK_15_0_GET( _reg ) \ ( ( ( _reg ) & AHBTRACE_MSFILT_SMASK_15_0_MASK ) >> \ AHBTRACE_MSFILT_SMASK_15_0_SHIFT ) -#define AHBTRACE_MSFILT_SMASK_15_0_SET( _reg, _val ) \ - ( ( ( _reg ) & ~AHBTRACE_MSFILT_SMASK_15_0_MASK ) | \ +#define AHBTRACE_MSFILT_SMASK_15_0_SET( _reg, _val ) \ + ( ( ( _reg ) & ~AHBTRACE_MSFILT_SMASK_15_0_MASK ) | \ ( ( ( _val ) << AHBTRACE_MSFILT_SMASK_15_0_SHIFT ) & \ AHBTRACE_MSFILT_SMASK_15_0_MASK ) ) -#define AHBTRACE_MSFILT_SMASK_15_0( _val ) \ +#define AHBTRACE_MSFILT_SMASK_15_0( _val ) \ ( ( ( _val ) << AHBTRACE_MSFILT_SMASK_15_0_SHIFT ) & \ AHBTRACE_MSFILT_SMASK_15_0_MASK ) #define AHBTRACE_MSFILT_MMASK_15_0_SHIFT 0 -#define AHBTRACE_MSFILT_MMASK_15_0_MASK 0xffffU -#define AHBTRACE_MSFILT_MMASK_15_0_GET( _reg ) \ +#define AHBTRACE_MSFILT_MMASK_15_0_MASK 0xffffU +#define AHBTRACE_MSFILT_MMASK_15_0_GET( _reg ) \ ( ( ( _reg ) & AHBTRACE_MSFILT_MMASK_15_0_MASK ) >> \ AHBTRACE_MSFILT_MMASK_15_0_SHIFT ) -#define AHBTRACE_MSFILT_MMASK_15_0_SET( _reg, _val ) \ - ( ( ( _reg ) & ~AHBTRACE_MSFILT_MMASK_15_0_MASK ) | \ +#define AHBTRACE_MSFILT_MMASK_15_0_SET( _reg, _val ) \ + ( ( ( _reg ) & ~AHBTRACE_MSFILT_MMASK_15_0_MASK ) | \ ( ( ( _val ) << AHBTRACE_MSFILT_MMASK_15_0_SHIFT ) & \ AHBTRACE_MSFILT_MMASK_15_0_MASK ) ) -#define AHBTRACE_MSFILT_MMASK_15_0( _val ) \ +#define AHBTRACE_MSFILT_MMASK_15_0( _val ) \ ( ( ( _val ) << AHBTRACE_MSFILT_MMASK_15_0_SHIFT ) & \ AHBTRACE_MSFILT_MMASK_15_0_MASK ) @@ -217,15 +209,15 @@ extern "C" { */ #define AHBTRACE_TBBA_BADDR_31_2_SHIFT 2 -#define AHBTRACE_TBBA_BADDR_31_2_MASK 0xfffffffcU -#define AHBTRACE_TBBA_BADDR_31_2_GET( _reg ) \ +#define AHBTRACE_TBBA_BADDR_31_2_MASK 0xfffffffcU +#define AHBTRACE_TBBA_BADDR_31_2_GET( _reg ) \ ( ( ( _reg ) & AHBTRACE_TBBA_BADDR_31_2_MASK ) >> \ AHBTRACE_TBBA_BADDR_31_2_SHIFT ) -#define AHBTRACE_TBBA_BADDR_31_2_SET( _reg, _val ) \ - ( ( ( _reg ) & ~AHBTRACE_TBBA_BADDR_31_2_MASK ) | \ +#define AHBTRACE_TBBA_BADDR_31_2_SET( _reg, _val ) \ + ( ( ( _reg ) & ~AHBTRACE_TBBA_BADDR_31_2_MASK ) | \ ( ( ( _val ) << AHBTRACE_TBBA_BADDR_31_2_SHIFT ) & \ AHBTRACE_TBBA_BADDR_31_2_MASK ) ) -#define AHBTRACE_TBBA_BADDR_31_2( _val ) \ +#define AHBTRACE_TBBA_BADDR_31_2( _val ) \ ( ( ( _val ) << AHBTRACE_TBBA_BADDR_31_2_SHIFT ) & \ AHBTRACE_TBBA_BADDR_31_2_MASK ) @@ -241,15 +233,15 @@ extern "C" { */ #define AHBTRACE_TBBM_BMASK_31_2_SHIFT 2 -#define AHBTRACE_TBBM_BMASK_31_2_MASK 0xfffffffcU -#define AHBTRACE_TBBM_BMASK_31_2_GET( _reg ) \ +#define AHBTRACE_TBBM_BMASK_31_2_MASK 0xfffffffcU +#define AHBTRACE_TBBM_BMASK_31_2_GET( _reg ) \ ( ( ( _reg ) & AHBTRACE_TBBM_BMASK_31_2_MASK ) >> \ AHBTRACE_TBBM_BMASK_31_2_SHIFT ) -#define AHBTRACE_TBBM_BMASK_31_2_SET( _reg, _val ) \ - ( ( ( _reg ) & ~AHBTRACE_TBBM_BMASK_31_2_MASK ) | \ +#define AHBTRACE_TBBM_BMASK_31_2_SET( _reg, _val ) \ + ( ( ( _reg ) & ~AHBTRACE_TBBM_BMASK_31_2_MASK ) | \ ( ( ( _val ) << AHBTRACE_TBBM_BMASK_31_2_SHIFT ) & \ AHBTRACE_TBBM_BMASK_31_2_MASK ) ) -#define AHBTRACE_TBBM_BMASK_31_2( _val ) \ +#define AHBTRACE_TBBM_BMASK_31_2( _val ) \ ( ( ( _val ) << AHBTRACE_TBBM_BMASK_31_2_SHIFT ) & \ AHBTRACE_TBBM_BMASK_31_2_MASK ) diff --git a/bsps/include/grlib/ambapp.h b/bsps/include/grlib/ambapp.h index 4031757d47..a8e196a9f0 100644 --- a/bsps/include/grlib/ambapp.h +++ b/bsps/include/grlib/ambapp.h @@ -58,84 +58,85 @@ extern "C" { /* Max supported AHB buses */ #define AHB_BUS_MAX 6 -#define AMBAPP_FLAG_FFACT_DIR 0x100 /* Frequency factor direction, 0=down, 1=up */ -#define AMBAPP_FLAG_FFACT 0x0f0 /* Frequency factor against top bus */ -#define AMBAPP_FLAG_MBUS 0x00c -#define AMBAPP_FLAG_SBUS 0x003 +#define AMBAPP_FLAG_FFACT_DIR \ + 0x100 /* Frequency factor direction, 0=down, 1=up */ +#define AMBAPP_FLAG_FFACT 0x0f0 /* Frequency factor against top bus */ +#define AMBAPP_FLAG_MBUS 0x00c +#define AMBAPP_FLAG_SBUS 0x003 /* Get APB or AHB information from a AMBA device */ -#define DEV_TO_APB(adev) ((struct ambapp_apb_info *)((adev)->devinfo)) -#define DEV_TO_AHB(adev) ((struct ambapp_ahb_info *)((adev)->devinfo)) -#define DEV_TO_COMMON(adev) (((adev)->devinfo)) +#define DEV_TO_APB( adev ) ( (struct ambapp_apb_info *) ( ( adev )->devinfo ) ) +#define DEV_TO_AHB( adev ) ( (struct ambapp_ahb_info *) ( ( adev )->devinfo ) ) +#define DEV_TO_COMMON( adev ) (( ( adev )->devinfo )) struct ambapp_common_info { - unsigned char irq; - unsigned char ver; - unsigned char ahbidx; /* AHB Bus Index */ + unsigned char irq; + unsigned char ver; + unsigned char ahbidx; /* AHB Bus Index */ }; struct ambapp_apb_info { - struct ambapp_common_info common; + struct ambapp_common_info common; - /* APB SPECIFIC */ - uint32_t start; - uint32_t mask; + /* APB SPECIFIC */ + uint32_t start; + uint32_t mask; }; struct ambapp_ahb_info { - struct ambapp_common_info common; + struct ambapp_common_info common; - /* AHB SPECIFIC */ - unsigned int start[4]; - unsigned int mask[4]; - char type[4]; /* type[N] Determine type of start[N]-mask[N], + /* AHB SPECIFIC */ + unsigned int start[ 4 ]; + unsigned int mask[ 4 ]; + char type[ 4 ]; /* type[N] Determine type of start[N]-mask[N], * 2=AHB Memory Space, 3=AHB I/O Space */ - unsigned int custom[3]; + unsigned int custom[ 3 ]; }; struct ambapp_dev { - struct ambapp_dev *next; /* Next */ - struct ambapp_dev *prev; /* Previous Device. If (this == + struct ambapp_dev *next; /* Next */ + struct ambapp_dev *prev; /* Previous Device. If (this == * rev->child) prev is bus bridge */ - struct ambapp_dev *children; /* Points to first device on sub-bus */ - void *owner; /* Owner of this AMBA device */ - unsigned char dev_type; /* AHB MST, AHB SLV or APB SLV*/ - unsigned char vendor; /* Vendor ID */ - unsigned short device; /* Device ID */ + struct ambapp_dev *children; /* Points to first device on sub-bus */ + void *owner; /* Owner of this AMBA device */ + unsigned char dev_type; /* AHB MST, AHB SLV or APB SLV*/ + unsigned char vendor; /* Vendor ID */ + unsigned short device; /* Device ID */ - /* Device info (APB/AHB dep. on type) */ - struct ambapp_common_info devinfo[RTEMS_ZERO_LENGTH_ARRAY]; + /* Device info (APB/AHB dep. on type) */ + struct ambapp_common_info devinfo[ RTEMS_ZERO_LENGTH_ARRAY ]; }; /* Describes a complete AMBA Core. Each device may consist of 3 interfaces */ struct ambapp_core { - char irq; /* irq=-1 indicate no IRQ */ - unsigned char vendor; - unsigned short device; - int index; /* Core index */ - struct ambapp_ahb_info *ahb_mst; - struct ambapp_ahb_info *ahb_slv; - struct ambapp_apb_info *apb_slv; + char irq; /* irq=-1 indicate no IRQ */ + unsigned char vendor; + unsigned short device; + int index; /* Core index */ + struct ambapp_ahb_info *ahb_mst; + struct ambapp_ahb_info *ahb_slv; + struct ambapp_apb_info *apb_slv; }; struct ambapp_ahb_bus { - unsigned int ioarea; /* AHB Bus IOAREA */ - unsigned int freq_hz; /* Frequency of AHB Bus */ - struct ambapp_dev *bridge;/* Bridge Device on Parent AHB Bus */ - struct ambapp_dev *dev; /* First Device on AHB Bus */ + unsigned int ioarea; /* AHB Bus IOAREA */ + unsigned int freq_hz; /* Frequency of AHB Bus */ + struct ambapp_dev *bridge; /* Bridge Device on Parent AHB Bus */ + struct ambapp_dev *dev; /* First Device on AHB Bus */ }; struct ambapp_mmap { - unsigned int size; - unsigned int local_adr; - unsigned int remote_adr; + unsigned int size; + unsigned int local_adr; + unsigned int remote_adr; }; /* Complete AMBA PnP information */ struct ambapp_bus { - struct ambapp_dev *root; /* AHB/APB Device Tree*/ - struct ambapp_mmap *mmaps; /* Memory MAP Array */ - struct ambapp_ahb_bus ahbs[AHB_BUS_MAX]; /* AHB Buses */ + struct ambapp_dev *root; /* AHB/APB Device Tree*/ + struct ambapp_mmap *mmaps; /* Memory MAP Array */ + struct ambapp_ahb_bus ahbs[ AHB_BUS_MAX ]; /* AHB Buses */ }; /* @@ -143,76 +144,83 @@ struct ambapp_bus { * 0 - continue * 1 - stop scanning */ -typedef int (*ambapp_func_t)(struct ambapp_dev *dev, int index, void *arg); +typedef int ( *ambapp_func_t )( struct ambapp_dev *dev, int index, void *arg ); -#define DEV_IS_FREE(dev) (dev->owner == NULL) -#define DEV_IS_ALLOCATED(dev) (dev->owner != NULL) +#define DEV_IS_FREE( dev ) ( dev->owner == NULL ) +#define DEV_IS_ALLOCATED( dev ) ( dev->owner != NULL ) /* Options to ambapp_for_each */ -#define OPTIONS_AHB_MSTS 0x00000001 -#define OPTIONS_AHB_SLVS 0x00000002 -#define OPTIONS_APB_SLVS 0x00000004 -#define OPTIONS_ALL_DEVS (OPTIONS_AHB_MSTS|OPTIONS_AHB_SLVS|OPTIONS_APB_SLVS) +#define OPTIONS_AHB_MSTS 0x00000001 +#define OPTIONS_AHB_SLVS 0x00000002 +#define OPTIONS_APB_SLVS 0x00000004 +#define OPTIONS_ALL_DEVS \ + ( OPTIONS_AHB_MSTS | OPTIONS_AHB_SLVS | OPTIONS_APB_SLVS ) -#define OPTIONS_FREE 0x00000010 -#define OPTIONS_ALLOCATED 0x00000020 -#define OPTIONS_ALL (OPTIONS_FREE|OPTIONS_ALLOCATED) +#define OPTIONS_FREE 0x00000010 +#define OPTIONS_ALLOCATED 0x00000020 +#define OPTIONS_ALL ( OPTIONS_FREE | OPTIONS_ALLOCATED ) /* Depth first search, Defualt is breath first search. */ -#define OPTIONS_DEPTH_FIRST 0x00000100 +#define OPTIONS_DEPTH_FIRST 0x00000100 #define DEV_AHB_NONE 0 #define DEV_AHB_MST 1 #define DEV_AHB_SLV 2 -#define DEV_APB_SLV 3 +#define DEV_APB_SLV 3 /* Structures used to access Plug&Play information directly */ struct ambapp_pnp_ahb { - const unsigned int id; /* VENDOR, DEVICE, VER, IRQ, */ - const unsigned int custom[3]; - const unsigned int mbar[4]; /* MASK, ADDRESS, TYPE, CACHABLE/PREFETCHABLE */ + const unsigned int id; /* VENDOR, DEVICE, VER, IRQ, */ + const unsigned int custom[ 3 ]; + const unsigned int + mbar[ 4 ]; /* MASK, ADDRESS, TYPE, CACHABLE/PREFETCHABLE */ }; struct ambapp_pnp_apb { - const unsigned int id; /* VENDOR, DEVICE, VER, IRQ, */ - const unsigned int iobar; /* MASK, ADDRESS, TYPE, CACHABLE/PREFETCHABLE */ + const unsigned int id; /* VENDOR, DEVICE, VER, IRQ, */ + const unsigned int iobar; /* MASK, ADDRESS, TYPE, CACHABLE/PREFETCHABLE */ }; -#define ambapp_pnp_vendor(id) (((id) >> 24) & 0xff) -#define ambapp_pnp_device(id) (((id) >> 12) & 0xfff) -#define ambapp_pnp_ver(id) (((id)>>5) & 0x1f) -#define ambapp_pnp_irq(id) ((id) & 0x1f) +#define ambapp_pnp_vendor( id ) ( ( ( id ) >> 24 ) & 0xff ) +#define ambapp_pnp_device( id ) ( ( ( id ) >> 12 ) & 0xfff ) +#define ambapp_pnp_ver( id ) ( ( ( id ) >> 5 ) & 0x1f ) +#define ambapp_pnp_irq( id ) ( ( id ) & 0x1f ) -#define ambapp_pnp_start(mbar) (((mbar) & 0xfff00000) & (((mbar) & 0xfff0) << 16)) -#define ambapp_pnp_mbar_mask(mbar) (((mbar)>>4) & 0xfff) -#define ambapp_pnp_mbar_type(mbar) ((mbar) & 0xf) +#define ambapp_pnp_start( mbar ) \ + ( ( ( mbar ) & 0xfff00000 ) & ( ( ( mbar ) & 0xfff0 ) << 16 ) ) +#define ambapp_pnp_mbar_mask( mbar ) ( ( ( mbar ) >> 4 ) & 0xfff ) +#define ambapp_pnp_mbar_type( mbar ) ( ( mbar ) & 0xf ) -#define ambapp_pnp_apb_start(iobar, base) ((base) | ((((iobar) & 0xfff00000)>>12) & (((iobar) & 0xfff0)<<4)) ) -#define ambapp_pnp_apb_mask(iobar) ((~(ambapp_pnp_mbar_mask(iobar)<<8) & 0x000fffff) + 1) +#define ambapp_pnp_apb_start( iobar, base ) \ + ( ( base ) | ( ( ( ( iobar ) & 0xfff00000 ) >> 12 ) & \ + ( ( ( iobar ) & 0xfff0 ) << 4 ) ) ) +#define ambapp_pnp_apb_mask( iobar ) \ + ( ( ~( ambapp_pnp_mbar_mask( iobar ) << 8 ) & 0x000fffff ) + 1 ) -#define AMBA_TYPE_AHBIO_ADDR(addr,base_ioarea) ((unsigned int)(base_ioarea) | ((addr) >> 12)) +#define AMBA_TYPE_AHBIO_ADDR( addr, base_ioarea ) \ + ( (unsigned int) ( base_ioarea ) | ( ( addr ) >> 12 ) ) #define AMBA_TYPE_APBIO 0x1 #define AMBA_TYPE_MEM 0x2 #define AMBA_TYPE_AHBIO 0x3 /* Copy Data from AMBA PnP I/O Area */ -typedef void *(*ambapp_memcpy_t)( - void *dest, /* Destination RAM copy */ - const void *src, /* Source AMBA PnP Address to copy from */ - int n, /* Number of bytes to be copied */ - struct ambapp_bus *abus /* Optional AMBA Bus pointer */ - ); +typedef void *( *ambapp_memcpy_t )( + void *dest, /* Destination RAM copy */ + const void *src, /* Source AMBA PnP Address to copy from */ + int n, /* Number of bytes to be copied */ + struct ambapp_bus *abus /* Optional AMBA Bus pointer */ +); struct ambapp_context { ambapp_memcpy_t copy_from_device; - void *(*alloc)(size_t); + void *( *alloc )( size_t ); }; /** * @brief Gets the fully scanned AMBA Plug & Play Processor Local Bus (PLB). */ -extern struct ambapp_bus *ambapp_plb(void); +extern struct ambapp_bus *ambapp_plb( void ); /* Scan a AMBA Plug & Play bus and create all device structures describing the * the devices. The devices will form a tree, where every node describes one @@ -228,24 +236,26 @@ extern struct ambapp_bus *ambapp_plb(void); * */ extern int ambapp_scan( - struct ambapp_bus *abus, - unsigned int ioarea, - const struct ambapp_context *ctx, - struct ambapp_mmap *mmaps - ); + struct ambapp_bus *abus, + unsigned int ioarea, + const struct ambapp_context *ctx, + struct ambapp_mmap *mmaps +); /* Initialize the frequency [Hz] of all AHB Buses from knowing the frequency * of one particular APB/AHB Device. */ extern void ambapp_freq_init( - struct ambapp_bus *abus, - struct ambapp_dev *dev, - unsigned int freq); + struct ambapp_bus *abus, + struct ambapp_dev *dev, + unsigned int freq +); /* Returns the frequency [Hz] of a AHB/APB device */ extern unsigned int ambapp_freq_get( - struct ambapp_bus *abus, - struct ambapp_dev *dev); + struct ambapp_bus *abus, + struct ambapp_dev *dev +); /* Iterates through all AMBA devices previously found, it calls func * once for every device that match the search arguments. @@ -274,12 +284,13 @@ extern unsigned int ambapp_freq_get( * non-zero - stopped by user function returning the non-zero value */ extern int ambapp_for_each( - struct ambapp_bus *abus, - unsigned int options, - int vendor, - int device, - ambapp_func_t func, - void *arg); + struct ambapp_bus *abus, + unsigned int options, + int vendor, + int device, + ambapp_func_t func, + void *arg +); /* Helper function for ambapp_for_each(), find a device by index. If pcount * is NULL the first device is returned, else pcount is interpreted as index @@ -290,110 +301,127 @@ extern int ambapp_for_each( * If zero is returned from ambapp_for_each no device matching the index was * found */ -extern int ambapp_find_by_idx(struct ambapp_dev *dev, int index, void *pcount); +extern int ambapp_find_by_idx( + struct ambapp_dev *dev, + int index, + void *pcount +); /* Get number of devices matching the options/vendor/device arguments, the * arguments are passed onto ambapp_for_each(). */ -extern int ambapp_dev_count(struct ambapp_bus *abus, unsigned int options, - int vendor, int device); +extern int ambapp_dev_count( + struct ambapp_bus *abus, + unsigned int options, + int vendor, + int device +); /* Print short information about devices on the AMBA bus onto the console */ -extern void ambapp_print(struct ambapp_bus *abus, int show_depth); +extern void ambapp_print( struct ambapp_bus *abus, int show_depth ); /* Mark a device taken (allocate), Owner field is set with owner Data. Returns * -1 if device has already been allocated. */ -extern int ambapp_alloc_dev(struct ambapp_dev *dev, void *owner); +extern int ambapp_alloc_dev( struct ambapp_dev *dev, void *owner ); /* Owner field is cleared, which indicates that device is not allocated */ -extern void ambapp_free_dev(struct ambapp_dev *dev); +extern void ambapp_free_dev( struct ambapp_dev *dev ); /* Find AHB/APB Bridge or AHB/AHB Bridge Parent */ -extern struct ambapp_dev *ambapp_find_parent(struct ambapp_dev *dev); +extern struct ambapp_dev *ambapp_find_parent( struct ambapp_dev *dev ); /* Returns bus depth (number of sub AHB buses) of device from root bus */ -extern int ambapp_depth(struct ambapp_dev *dev); +extern int ambapp_depth( struct ambapp_dev *dev ); /* Get Device Name from AMBA PnP name database */ -extern char *ambapp_device_id2str(unsigned int vendor, int id); +extern char *ambapp_device_id2str( unsigned int vendor, int id ); /* Get Vendor Name from AMBA PnP name database */ -extern char *ambapp_vendor_id2str(unsigned int vendor); +extern char *ambapp_vendor_id2str( unsigned int vendor ); /* Set together VENDOR_DEVICE Name from AMBA PnP name database. Return length * of C-string stored in buf not including string termination '\0'. */ -extern int ambapp_vendev_id2str(unsigned int vendor, int id, char *buf); +extern int ambapp_vendev_id2str( unsigned int vendor, int id, char *buf ); /* Help functions for backwards compability */ extern int ambapp_find_apbslv( - struct ambapp_bus *abus, - int vendor, - int device, - struct ambapp_apb_info *dev); + struct ambapp_bus *abus, + int vendor, + int device, + struct ambapp_apb_info *dev +); extern int ambapp_find_apbslv_next( - struct ambapp_bus *abus, - int vendor, - int device, - struct ambapp_apb_info *dev, - int index); + struct ambapp_bus *abus, + int vendor, + int device, + struct ambapp_apb_info *dev, + int index +); extern int ambapp_find_apbslvs_next( - struct ambapp_bus *abus, - int vendor, - int device, - struct ambapp_apb_info *dev, - int index, - int maxno); + struct ambapp_bus *abus, + int vendor, + int device, + struct ambapp_apb_info *dev, + int index, + int maxno +); extern int ambapp_find_apbslvs( - struct ambapp_bus *abus, - int vendor, - int device, - struct ambapp_apb_info *dev, - int maxno); + struct ambapp_bus *abus, + int vendor, + int device, + struct ambapp_apb_info *dev, + int maxno +); extern int ambapp_find_ahbslv( - struct ambapp_bus *abus, - int vendor, - int device, - struct ambapp_ahb_info *dev); + struct ambapp_bus *abus, + int vendor, + int device, + struct ambapp_ahb_info *dev +); extern int ambapp_find_ahbslv_next( - struct ambapp_bus *abus, - int vendor, - int device, - struct ambapp_ahb_info *dev, - int index); + struct ambapp_bus *abus, + int vendor, + int device, + struct ambapp_ahb_info *dev, + int index +); extern int ambapp_find_ahbslvs_next( - struct ambapp_bus *abus, - int vendor, - int device, - struct ambapp_ahb_info *dev, - int index, - int maxno); + struct ambapp_bus *abus, + int vendor, + int device, + struct ambapp_ahb_info *dev, + int index, + int maxno +); extern int ambapp_find_ahbslvs( - struct ambapp_bus *abus, - int vendor, - int device, - struct ambapp_ahb_info *dev, - int maxno); - + struct ambapp_bus *abus, + int vendor, + int device, + struct ambapp_ahb_info *dev, + int maxno +); extern int ambapp_get_number_ahbslv_devices( - struct ambapp_bus *abus, - int vendor, - int device); + struct ambapp_bus *abus, + int vendor, + int device +); extern int ambapp_get_number_apbslv_devices( - struct ambapp_bus *abus, - int vendor, - int device); + struct ambapp_bus *abus, + int vendor, + int device +); #ifdef __cplusplus } diff --git a/bsps/include/grlib/ambapp_bus.h b/bsps/include/grlib/ambapp_bus.h index b62ebc0fa3..2bc6f7d27a 100644 --- a/bsps/include/grlib/ambapp_bus.h +++ b/bsps/include/grlib/ambapp_bus.h @@ -43,117 +43,165 @@ extern "C" { #endif /* GRLIB AMBA Plug&Play Driver ID generation */ -#define DRIVER_AMBAPP_ID(vendor, device) \ - DRIVER_ID(DRVMGR_BUS_TYPE_AMBAPP, ((((vendor) & 0xff) << 16) | ((device) & 0xfff))) +#define DRIVER_AMBAPP_ID( vendor, device ) \ + DRIVER_ID( \ + DRVMGR_BUS_TYPE_AMBAPP, \ + ( ( ( ( vendor ) & 0xff ) << 16 ) | ( ( device ) & 0xfff ) ) \ + ) /*** Gaisler Hardware Device Driver IDs ***/ -#define DRIVER_AMBAPP_GAISLER_AHBSTAT_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_AHBSTAT) -#define DRIVER_AMBAPP_GAISLER_APBUART_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_APBUART) -#define DRIVER_AMBAPP_GAISLER_B1553BRM_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_B1553BRM) -#define DRIVER_AMBAPP_GAISLER_B1553RT_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_B1553RT) -#define DRIVER_AMBAPP_GAISLER_GPTIMER_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_GPTIMER) -#define DRIVER_AMBAPP_GAISLER_GR1553B_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_GR1553B) -#define DRIVER_AMBAPP_GAISLER_GRADCDAC_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_GRADCDAC) -#define DRIVER_AMBAPP_GAISLER_GRAES_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_GRAESDMA) -#define DRIVER_AMBAPP_GAISLER_GRCAN_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_GRCAN) -#define DRIVER_AMBAPP_GAISLER_GRCTM_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_GRCTM) -#define DRIVER_AMBAPP_GAISLER_GRETH_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_ETHMAC) -#define DRIVER_AMBAPP_GAISLER_GRGPIO_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_GPIO) -#define DRIVER_AMBAPP_GAISLER_GRPCI2_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_GRPCI2) -#define DRIVER_AMBAPP_GAISLER_GRIOMMU_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_GRIOMMU) -#define DRIVER_AMBAPP_GAISLER_GRPCI_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_PCIFBRG) -#define DRIVER_AMBAPP_GAISLER_GRPWM_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_GRPWM) -#define DRIVER_AMBAPP_GAISLER_GRPWRX_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_PW2APB) -#define DRIVER_AMBAPP_GAISLER_GRSPW_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_SPW) -#define DRIVER_AMBAPP_GAISLER_GRSPW2_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_SPW2) -#define DRIVER_AMBAPP_GAISLER_GRTC_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_GRTC) -#define DRIVER_AMBAPP_GAISLER_GRTM_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_GRTM) -#define DRIVER_AMBAPP_GAISLER_I2CMST_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_I2CMST) -#define DRIVER_AMBAPP_GAISLER_OCCAN_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_CANAHB) -#define DRIVER_AMBAPP_GAISLER_PCIF_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_PCIF) -#define DRIVER_AMBAPP_GAISLER_PCITRACE_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_PCITRACE) -#define DRIVER_AMBAPP_GAISLER_SPICTRL_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_SPICTRL) -#define DRIVER_AMBAPP_GAISLER_SPWCUC_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_SPWCUC) -#define DRIVER_AMBAPP_GAISLER_SPW_ROUTER_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_SPW_ROUTER) -#define DRIVER_AMBAPP_GAISLER_L2CACHE_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_L2CACHE) -#define DRIVER_AMBAPP_GAISLER_MEMSCRUB_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_MEMSCRUB) -#define DRIVER_AMBAPP_GAISLER_L4STAT_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_L4STAT) -#define DRIVER_AMBAPP_GAISLER_SPWTDP_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_SPWTDP) +#define DRIVER_AMBAPP_GAISLER_AHBSTAT_ID \ + DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_AHBSTAT ) +#define DRIVER_AMBAPP_GAISLER_APBUART_ID \ + DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_APBUART ) +#define DRIVER_AMBAPP_GAISLER_B1553BRM_ID \ + DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_B1553BRM ) +#define DRIVER_AMBAPP_GAISLER_B1553RT_ID \ + DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_B1553RT ) +#define DRIVER_AMBAPP_GAISLER_GPTIMER_ID \ + DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_GPTIMER ) +#define DRIVER_AMBAPP_GAISLER_GR1553B_ID \ + DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_GR1553B ) +#define DRIVER_AMBAPP_GAISLER_GRADCDAC_ID \ + DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_GRADCDAC ) +#define DRIVER_AMBAPP_GAISLER_GRAES_ID \ + DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_GRAESDMA ) +#define DRIVER_AMBAPP_GAISLER_GRCAN_ID \ + DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_GRCAN ) +#define DRIVER_AMBAPP_GAISLER_GRCTM_ID \ + DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_GRCTM ) +#define DRIVER_AMBAPP_GAISLER_GRETH_ID \ + DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_ETHMAC ) +#define DRIVER_AMBAPP_GAISLER_GRGPIO_ID \ + DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_GPIO ) +#define DRIVER_AMBAPP_GAISLER_GRPCI2_ID \ + DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_GRPCI2 ) +#define DRIVER_AMBAPP_GAISLER_GRIOMMU_ID \ + DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_GRIOMMU ) +#define DRIVER_AMBAPP_GAISLER_GRPCI_ID \ + DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_PCIFBRG ) +#define DRIVER_AMBAPP_GAISLER_GRPWM_ID \ + DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_GRPWM ) +#define DRIVER_AMBAPP_GAISLER_GRPWRX_ID \ + DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_PW2APB ) +#define DRIVER_AMBAPP_GAISLER_GRSPW_ID \ + DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_SPW ) +#define DRIVER_AMBAPP_GAISLER_GRSPW2_ID \ + DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_SPW2 ) +#define DRIVER_AMBAPP_GAISLER_GRTC_ID \ + DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_GRTC ) +#define DRIVER_AMBAPP_GAISLER_GRTM_ID \ + DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_GRTM ) +#define DRIVER_AMBAPP_GAISLER_I2CMST_ID \ + DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_I2CMST ) +#define DRIVER_AMBAPP_GAISLER_OCCAN_ID \ + DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_CANAHB ) +#define DRIVER_AMBAPP_GAISLER_PCIF_ID \ + DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_PCIF ) +#define DRIVER_AMBAPP_GAISLER_PCITRACE_ID \ + DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_PCITRACE ) +#define DRIVER_AMBAPP_GAISLER_SPICTRL_ID \ + DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_SPICTRL ) +#define DRIVER_AMBAPP_GAISLER_SPWCUC_ID \ + DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_SPWCUC ) +#define DRIVER_AMBAPP_GAISLER_SPW_ROUTER_ID \ + DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_SPW_ROUTER ) +#define DRIVER_AMBAPP_GAISLER_L2CACHE_ID \ + DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_L2CACHE ) +#define DRIVER_AMBAPP_GAISLER_MEMSCRUB_ID \ + DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_MEMSCRUB ) +#define DRIVER_AMBAPP_GAISLER_L4STAT_ID \ + DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_L4STAT ) +#define DRIVER_AMBAPP_GAISLER_SPWTDP_ID \ + DRIVER_AMBAPP_ID( VENDOR_GAISLER, GAISLER_SPWTDP ) /*** ESA Hardware Device Driver IDs ***/ -#define DRIVER_AMBAPP_ESA_MCTRL_ID DRIVER_AMBAPP_ID(VENDOR_ESA, ESA_MCTRL) -#define DRIVER_AMBAPP_MCTRL_ID DRIVER_AMBAPP_ESA_MCTRL_ID +#define DRIVER_AMBAPP_ESA_MCTRL_ID DRIVER_AMBAPP_ID( VENDOR_ESA, ESA_MCTRL ) +#define DRIVER_AMBAPP_MCTRL_ID DRIVER_AMBAPP_ESA_MCTRL_ID struct amba_dev_id { - unsigned short vendor; - unsigned short device; - /* Version ? */ + unsigned short vendor; + unsigned short device; + /* Version ? */ }; struct amba_drv_info { - struct drvmgr_drv general; /* General bus info */ - /* AMBA specific bus information */ - struct amba_dev_id *ids; /* Supported hardware */ + struct drvmgr_drv general; /* General bus info */ + /* AMBA specific bus information */ + struct amba_dev_id *ids; /* Supported hardware */ }; struct amba_dev_info { - struct amba_dev_id id; - struct ambapp_core info; + struct amba_dev_id id; + struct ambapp_core info; }; struct ambapp_ops { - int (*int_register) - (struct drvmgr_dev *dev, int index, const char *info, drvmgr_isr isr, void *arg); - int (*int_unregister) - (struct drvmgr_dev *dev, int index, drvmgr_isr isr, void *arg); - int (*int_clear)(struct drvmgr_dev *dev, int index); - int (*int_mask)(struct drvmgr_dev *dev, int index); - int (*int_unmask)(struct drvmgr_dev *dev, int index); + int ( *int_register )( + struct drvmgr_dev *dev, + int index, + const char *info, + drvmgr_isr isr, + void *arg + ); + int ( *int_unregister )( + struct drvmgr_dev *dev, + int index, + drvmgr_isr isr, + void *arg + ); + int ( *int_clear )( struct drvmgr_dev *dev, int index ); + int ( *int_mask )( struct drvmgr_dev *dev, int index ); + int ( *int_unmask )( struct drvmgr_dev *dev, int index ); #ifdef RTEMS_SMP - int (*int_set_affinity)(struct drvmgr_dev *dev, int index, - const Processor_mask *cpus); + int ( *int_set_affinity )( + struct drvmgr_dev *dev, + int index, + const Processor_mask *cpus + ); #endif - int (*get_params) - (struct drvmgr_dev *, struct drvmgr_bus_params *); + int ( *get_params )( struct drvmgr_dev *, struct drvmgr_bus_params * ); }; struct ambapp_config { - struct ambapp_bus *abus; /* Prescanned AMBA PnP bus */ - struct ambapp_ops *ops; /* AMBA bus operations */ - struct drvmgr_map_entry *maps_up; /* Bus memory map up-stream towards CPU */ - struct drvmgr_map_entry *maps_down; /* Bus memory map down-stream towards HW */ - struct drvmgr_bus_res *resources; /* Driver Resources */ - int bus_type; /* Set DRVMGR_BUS_TYPE_AMBAPP_DIST if distributed AMBA Bus */ - struct drvmgr_func *funcs; /* Custom functions */ + struct ambapp_bus *abus; /* Prescanned AMBA PnP bus */ + struct ambapp_ops *ops; /* AMBA bus operations */ + struct drvmgr_map_entry *maps_up; /* Bus memory map up-stream towards CPU */ + struct drvmgr_map_entry + *maps_down; /* Bus memory map down-stream towards HW */ + struct drvmgr_bus_res *resources; /* Driver Resources */ + int bus_type; /* Set DRVMGR_BUS_TYPE_AMBAPP_DIST if distributed AMBA Bus */ + struct drvmgr_func *funcs; /* Custom functions */ }; /*** Bus operations with READ/WRITE access operations *** * * The functions are implemented using the standard drvmgr RW interface */ -#define AMBAPP_R8 DRVMGR_RWFUNC(RW_SIZE_1|RW_READ|RW_REG) -#define AMBAPP_R16 DRVMGR_RWFUNC(RW_SIZE_2|RW_READ|RW_REG) -#define AMBAPP_R32 DRVMGR_RWFUNC(RW_SIZE_4|RW_READ|RW_REG) -#define AMBAPP_R64 DRVMGR_RWFUNC(RW_SIZE_8|RW_READ|RW_REG) -#define AMBAPP_W8 DRVMGR_RWFUNC(RW_SIZE_1|RW_WRITE|RW_REG) -#define AMBAPP_W16 DRVMGR_RWFUNC(RW_SIZE_2|RW_WRITE|RW_REG) -#define AMBAPP_W32 DRVMGR_RWFUNC(RW_SIZE_4|RW_WRITE|RW_REG) -#define AMBAPP_W64 DRVMGR_RWFUNC(RW_SIZE_8|RW_WRITE|RW_REG) -#define AMBAPP_RMEM DRVMGR_RWFUNC(RW_SIZE_ANY|RW_READ|RW_MEM) -#define AMBAPP_WMEM DRVMGR_RWFUNC(RW_SIZE_ANY|RW_WRITE|RW_MEM) -#define AMBAPP_MEMSET DRVMGR_RWFUNC(RW_SIZE_ANY|RW_SET|RW_MEM) -#define AMBAPP_RW_ARG DRVMGR_RWFUNC(RW_ARG) +#define AMBAPP_R8 DRVMGR_RWFUNC( RW_SIZE_1 | RW_READ | RW_REG ) +#define AMBAPP_R16 DRVMGR_RWFUNC( RW_SIZE_2 | RW_READ | RW_REG ) +#define AMBAPP_R32 DRVMGR_RWFUNC( RW_SIZE_4 | RW_READ | RW_REG ) +#define AMBAPP_R64 DRVMGR_RWFUNC( RW_SIZE_8 | RW_READ | RW_REG ) +#define AMBAPP_W8 DRVMGR_RWFUNC( RW_SIZE_1 | RW_WRITE | RW_REG ) +#define AMBAPP_W16 DRVMGR_RWFUNC( RW_SIZE_2 | RW_WRITE | RW_REG ) +#define AMBAPP_W32 DRVMGR_RWFUNC( RW_SIZE_4 | RW_WRITE | RW_REG ) +#define AMBAPP_W64 DRVMGR_RWFUNC( RW_SIZE_8 | RW_WRITE | RW_REG ) +#define AMBAPP_RMEM DRVMGR_RWFUNC( RW_SIZE_ANY | RW_READ | RW_MEM ) +#define AMBAPP_WMEM DRVMGR_RWFUNC( RW_SIZE_ANY | RW_WRITE | RW_MEM ) +#define AMBAPP_MEMSET DRVMGR_RWFUNC( RW_SIZE_ANY | RW_SET | RW_MEM ) +#define AMBAPP_RW_ARG DRVMGR_RWFUNC( RW_ARG ) /* Register an ambapp bus on-top of a device */ extern int ambapp_bus_register( - struct drvmgr_dev *dev, - struct ambapp_config *config - ); + struct drvmgr_dev *dev, + struct ambapp_config *config +); extern void ambapp_bus_freq_register( - struct drvmgr_dev *dev, - int amba_interface, - unsigned int freq_hz); + struct drvmgr_dev *dev, + int amba_interface, + unsigned int freq_hz +); #ifdef __cplusplus } diff --git a/bsps/include/grlib/ambapp_bus_grlib.h b/bsps/include/grlib/ambapp_bus_grlib.h index b6e5ddfb06..dc9ed27cd0 100644 --- a/bsps/include/grlib/ambapp_bus_grlib.h +++ b/bsps/include/grlib/ambapp_bus_grlib.h @@ -38,15 +38,15 @@ extern "C" { #endif struct grlib_config { - struct ambapp_bus *abus; - struct drvmgr_bus_res *resources; + struct ambapp_bus *abus; + struct drvmgr_bus_res *resources; }; /* Register GRLIB AMBA PnP Bus as root bus at driver manager */ -extern int ambapp_grlib_root_register(struct grlib_config *config); +extern int ambapp_grlib_root_register( struct grlib_config *config ); /* Register bus driver to Driver Manager */ -void ambapp_grlib_register(void); +void ambapp_grlib_register( void ); #ifdef __cplusplus } diff --git a/bsps/include/grlib/ambapp_ids.h b/bsps/include/grlib/ambapp_ids.h index df578d093a..1c3b85f32c 100644 --- a/bsps/include/grlib/ambapp_ids.h +++ b/bsps/include/grlib/ambapp_ids.h @@ -40,313 +40,312 @@ #define __AMBAPP_DEVS_H__ /* Vendor codes */ -#define VENDOR_RESERVED 0x00 -#define VENDOR_GAISLER 0x01 -#define VENDOR_PENDER 0x02 -#define VENDOR_ESA 0x04 -#define VENDOR_ASTRIUM 0x06 -#define VENDOR_OPENCHIP 0x07 -#define VENDOR_OPENCORES 0x08 -#define VENDOR_CONTRIB 0x09 -#define VENDOR_DLR 0x0a -#define VENDOR_EONIC 0x0b -#define VENDOR_TELECOMPT 0x0c -#define VENDOR_DTU 0x0d -#define VENDOR_BSC 0x0e -#define VENDOR_RADIONOR 0x0f -#define VENDOR_GLEICHMANN 0x10 -#define VENDOR_MENTA 0x11 -#define VENDOR_SUN 0x13 -#define VENDOR_MOVIDIA 0x14 -#define VENDOR_ORBITA 0x17 -#define VENDOR_SIEMENS 0x1a -#define VENDOR_SYNOPSYS 0x21 -#define VENDOR_NASA 0x22 -#define VENDOR_NIIET 0x23 -#define VENDOR_S3 0x31 -#define VENDOR_ACTEL 0xac -#define VENDOR_APPLECORE 0xae -#define VENDOR_C3E 0xc3 -#define VENDOR_CBKPAN 0xc8 -#define VENDOR_CAL 0xca -#define VENDOR_CETON 0xcb -#define VENDOR_EMBEDDIT 0xea -#define VENDOR_NASA_GSFC 0xfc -#define VENDOR_AZST 0xfe +#define VENDOR_RESERVED 0x00 +#define VENDOR_GAISLER 0x01 +#define VENDOR_PENDER 0x02 +#define VENDOR_ESA 0x04 +#define VENDOR_ASTRIUM 0x06 +#define VENDOR_OPENCHIP 0x07 +#define VENDOR_OPENCORES 0x08 +#define VENDOR_CONTRIB 0x09 +#define VENDOR_DLR 0x0a +#define VENDOR_EONIC 0x0b +#define VENDOR_TELECOMPT 0x0c +#define VENDOR_DTU 0x0d +#define VENDOR_BSC 0x0e +#define VENDOR_RADIONOR 0x0f +#define VENDOR_GLEICHMANN 0x10 +#define VENDOR_MENTA 0x11 +#define VENDOR_SUN 0x13 +#define VENDOR_MOVIDIA 0x14 +#define VENDOR_ORBITA 0x17 +#define VENDOR_SIEMENS 0x1a +#define VENDOR_SYNOPSYS 0x21 +#define VENDOR_NASA 0x22 +#define VENDOR_NIIET 0x23 +#define VENDOR_S3 0x31 +#define VENDOR_ACTEL 0xac +#define VENDOR_APPLECORE 0xae +#define VENDOR_C3E 0xc3 +#define VENDOR_CBKPAN 0xc8 +#define VENDOR_CAL 0xca +#define VENDOR_CETON 0xcb +#define VENDOR_EMBEDDIT 0xea +#define VENDOR_NASA_GSFC 0xfc +#define VENDOR_AZST 0xfe /* Gaisler Research device id's */ -#define GAISLER_LEON2DSU 0x002 -#define GAISLER_LEON3 0x003 -#define GAISLER_LEON3DSU 0x004 -#define GAISLER_ETHAHB 0x005 -#define GAISLER_APBMST 0x006 -#define GAISLER_AHBUART 0x007 -#define GAISLER_SRCTRL 0x008 -#define GAISLER_SDCTRL 0x009 -#define GAISLER_SSRCTRL 0x00a -#define GAISLER_I2C2AHB 0x00b -#define GAISLER_APBUART 0x00c -#define GAISLER_IRQMP 0x00d -#define GAISLER_AHBRAM 0x00e -#define GAISLER_AHBDPRAM 0x00f -#define GAISLER_GRIOMMU2 0x010 -#define GAISLER_GPTIMER 0x011 -#define GAISLER_PCITRG 0x012 -#define GAISLER_PCISBRG 0x013 -#define GAISLER_PCIFBRG 0x014 -#define GAISLER_PCITRACE 0x015 -#define GAISLER_DMACTRL 0x016 -#define GAISLER_AHBTRACE 0x017 -#define GAISLER_DSUCTRL 0x018 -#define GAISLER_CANAHB 0x019 -#define GAISLER_GPIO 0x01a -#define GAISLER_AHBROM 0x01b -#define GAISLER_AHBJTAG 0x01c -#define GAISLER_ETHMAC 0x01d -#define GAISLER_SWNODE 0x01e -#define GAISLER_SPW 0x01f -#define GAISLER_AHB2AHB 0x020 -#define GAISLER_USBDC 0x021 -#define GAISLER_USB_DCL 0x022 -#define GAISLER_DDRMP 0x023 -#define GAISLER_ATACTRL 0x024 -#define GAISLER_DDRSP 0x025 -#define GAISLER_EHCI 0x026 -#define GAISLER_UHCI 0x027 -#define GAISLER_I2CMST 0x028 -#define GAISLER_SPW2 0x029 -#define GAISLER_AHBDMA 0x02a -#define GAISLER_NUHOSP3 0x02b -#define GAISLER_CLKGATE 0x02c -#define GAISLER_SPICTRL 0x02d -#define GAISLER_DDR2SP 0x02e -#define GAISLER_SLINK 0x02f -#define GAISLER_GRTM 0x030 -#define GAISLER_GRTC 0x031 -#define GAISLER_GRPW 0x032 -#define GAISLER_GRCTM 0x033 -#define GAISLER_GRHCAN 0x034 -#define GAISLER_GRFIFO 0x035 -#define GAISLER_GRADCDAC 0x036 -#define GAISLER_GRPULSE 0x037 -#define GAISLER_GRTIMER 0x038 -#define GAISLER_AHB2PP 0x039 -#define GAISLER_GRVERSION 0x03a -#define GAISLER_APB2PW 0x03b -#define GAISLER_PW2APB 0x03c -#define GAISLER_GRCAN 0x03d -#define GAISLER_I2CSLV 0x03e -#define GAISLER_U16550 0x03f -#define GAISLER_AHBMST_EM 0x040 -#define GAISLER_AHBSLV_EM 0x041 -#define GAISLER_GRTESTMOD 0x042 -#define GAISLER_ASCS 0x043 -#define GAISLER_IPMVBCTRL 0x044 -#define GAISLER_SPIMCTRL 0x045 -#define GAISLER_L4STAT 0x047 -#define GAISLER_LEON4 0x048 -#define GAISLER_LEON4DSU 0x049 -#define GAISLER_GRPWM 0x04a -#define GAISLER_PWM 0x04a -#define GAISLER_L2CACHE 0x04b -#define GAISLER_SDCTRL64 0x04c -#define GAISLER_GR1553B 0x04d -#define GAISLER_1553TST 0x04e -#define GAISLER_GRIOMMU 0x04f -#define GAISLER_FTAHBRAM 0x050 -#define GAISLER_FTSRCTRL 0x051 -#define GAISLER_AHBSTAT 0x052 -#define GAISLER_LEON3FT 0x053 -#define GAISLER_FTMCTRL 0x054 -#define GAISLER_FTSDCTRL 0x055 -#define GAISLER_FTSRCTRL8 0x056 -#define GAISLER_MEMSCRUB 0x057 -#define GAISLER_FTSDCTRL64 0x058 -#define GAISLER_NANDFCTRL 0x059 -#define GAISLER_N2DLLCTRL 0x05a -#define GAISLER_N2PLLCTRL 0x05b -#define GAISLER_SPI2AHB 0x05c -#define GAISLER_DDRSDMUX 0x05d -#define GAISLER_AHBFROM 0x05e -#define GAISLER_PCIEXP 0x05f -#define GAISLER_APBPS2 0x060 -#define GAISLER_VGACTRL 0x061 -#define GAISLER_LOGAN 0x062 -#define GAISLER_SVGACTRL 0x063 -#define GAISLER_T1AHB 0x064 -#define GAISLER_MP7WRAP 0x065 -#define GAISLER_GRSYSMON 0x066 -#define GAISLER_GRACECTRL 0x067 -#define GAISLER_ATAHBSLV 0x068 -#define GAISLER_ATAHBMST 0x069 -#define GAISLER_ATAPBSLV 0x06a -#define GAISLER_MIGDDR2 0x06b -#define GAISLER_LCDCTRL 0x06c -#define GAISLER_SWITCHOVER 0x06d -#define GAISLER_FIFOUART 0x06e -#define GAISLER_MUXCTRL 0x06f -#define GAISLER_B1553BC 0x070 -#define GAISLER_B1553RT 0x071 -#define GAISLER_B1553BRM 0x072 -#define GAISLER_GRAES 0x073 -#define GAISLER_AES 0x073 -#define GAISLER_ECC 0x074 -#define GAISLER_PCIF 0x075 -#define GAISLER_CLKMOD 0x076 -#define GAISLER_HAPSTRAK 0x077 -#define GAISLER_TEST_1X2 0x078 -#define GAISLER_WILD2AHB 0x079 -#define GAISLER_BIO1 0x07a -#define GAISLER_GRAESDMA 0x07b -#define GAISLER_AESDMA 0x07b -#define GAISLER_GRPCI2 0x07c -#define GAISLER_GRPCI2_DMA 0x07d -#define GAISLER_GRPCI2_TB 0x07e -#define GAISLER_MMA 0x07f -#define GAISLER_SATCAN 0x080 -#define GAISLER_CANMUX 0x081 -#define GAISLER_GRTMRX 0x082 -#define GAISLER_GRTCTX 0x083 -#define GAISLER_GRTMDESC 0x084 -#define GAISLER_GRTMVC 0x085 -#define GAISLER_GEFFE 0x086 -#define GAISLER_GPREG 0x087 -#define GAISLER_GRTMPAHB 0x088 -#define GAISLER_SPWCUC 0x089 -#define GAISLER_SPW2_DMA 0x08a -#define GAISLER_SPW_ROUTER 0x08b -#define GAISLER_SPWROUTER 0x08b -#define GAISLER_EDCLMST 0x08c -#define GAISLER_GRPWTX 0x08d -#define GAISLER_GRPWRX 0x08e -#define GAISLER_GPREGBANK 0x08f -#define GAISLER_MIG_7SERIES 0x090 -#define GAISLER_GRSPW2_SIST 0x091 -#define GAISLER_SGMII 0x092 -#define GAISLER_RGMII 0x093 -#define GAISLER_IRQGEN 0x094 -#define GAISLER_GRDMAC 0x095 -#define GAISLER_AHB2AVLA 0x096 -#define GAISLER_SPWTDP 0x097 -#define GAISLER_L3STAT 0x098 -#define GAISLER_GR740THS 0x099 -#define GAISLER_GRRM 0x09a -#define GAISLER_CMAP 0x09b -#define GAISLER_CPGEN 0x09c -#define GAISLER_AMBAPROT 0x09d +#define GAISLER_LEON2DSU 0x002 +#define GAISLER_LEON3 0x003 +#define GAISLER_LEON3DSU 0x004 +#define GAISLER_ETHAHB 0x005 +#define GAISLER_APBMST 0x006 +#define GAISLER_AHBUART 0x007 +#define GAISLER_SRCTRL 0x008 +#define GAISLER_SDCTRL 0x009 +#define GAISLER_SSRCTRL 0x00a +#define GAISLER_I2C2AHB 0x00b +#define GAISLER_APBUART 0x00c +#define GAISLER_IRQMP 0x00d +#define GAISLER_AHBRAM 0x00e +#define GAISLER_AHBDPRAM 0x00f +#define GAISLER_GRIOMMU2 0x010 +#define GAISLER_GPTIMER 0x011 +#define GAISLER_PCITRG 0x012 +#define GAISLER_PCISBRG 0x013 +#define GAISLER_PCIFBRG 0x014 +#define GAISLER_PCITRACE 0x015 +#define GAISLER_DMACTRL 0x016 +#define GAISLER_AHBTRACE 0x017 +#define GAISLER_DSUCTRL 0x018 +#define GAISLER_CANAHB 0x019 +#define GAISLER_GPIO 0x01a +#define GAISLER_AHBROM 0x01b +#define GAISLER_AHBJTAG 0x01c +#define GAISLER_ETHMAC 0x01d +#define GAISLER_SWNODE 0x01e +#define GAISLER_SPW 0x01f +#define GAISLER_AHB2AHB 0x020 +#define GAISLER_USBDC 0x021 +#define GAISLER_USB_DCL 0x022 +#define GAISLER_DDRMP 0x023 +#define GAISLER_ATACTRL 0x024 +#define GAISLER_DDRSP 0x025 +#define GAISLER_EHCI 0x026 +#define GAISLER_UHCI 0x027 +#define GAISLER_I2CMST 0x028 +#define GAISLER_SPW2 0x029 +#define GAISLER_AHBDMA 0x02a +#define GAISLER_NUHOSP3 0x02b +#define GAISLER_CLKGATE 0x02c +#define GAISLER_SPICTRL 0x02d +#define GAISLER_DDR2SP 0x02e +#define GAISLER_SLINK 0x02f +#define GAISLER_GRTM 0x030 +#define GAISLER_GRTC 0x031 +#define GAISLER_GRPW 0x032 +#define GAISLER_GRCTM 0x033 +#define GAISLER_GRHCAN 0x034 +#define GAISLER_GRFIFO 0x035 +#define GAISLER_GRADCDAC 0x036 +#define GAISLER_GRPULSE 0x037 +#define GAISLER_GRTIMER 0x038 +#define GAISLER_AHB2PP 0x039 +#define GAISLER_GRVERSION 0x03a +#define GAISLER_APB2PW 0x03b +#define GAISLER_PW2APB 0x03c +#define GAISLER_GRCAN 0x03d +#define GAISLER_I2CSLV 0x03e +#define GAISLER_U16550 0x03f +#define GAISLER_AHBMST_EM 0x040 +#define GAISLER_AHBSLV_EM 0x041 +#define GAISLER_GRTESTMOD 0x042 +#define GAISLER_ASCS 0x043 +#define GAISLER_IPMVBCTRL 0x044 +#define GAISLER_SPIMCTRL 0x045 +#define GAISLER_L4STAT 0x047 +#define GAISLER_LEON4 0x048 +#define GAISLER_LEON4DSU 0x049 +#define GAISLER_GRPWM 0x04a +#define GAISLER_PWM 0x04a +#define GAISLER_L2CACHE 0x04b +#define GAISLER_SDCTRL64 0x04c +#define GAISLER_GR1553B 0x04d +#define GAISLER_1553TST 0x04e +#define GAISLER_GRIOMMU 0x04f +#define GAISLER_FTAHBRAM 0x050 +#define GAISLER_FTSRCTRL 0x051 +#define GAISLER_AHBSTAT 0x052 +#define GAISLER_LEON3FT 0x053 +#define GAISLER_FTMCTRL 0x054 +#define GAISLER_FTSDCTRL 0x055 +#define GAISLER_FTSRCTRL8 0x056 +#define GAISLER_MEMSCRUB 0x057 +#define GAISLER_FTSDCTRL64 0x058 +#define GAISLER_NANDFCTRL 0x059 +#define GAISLER_N2DLLCTRL 0x05a +#define GAISLER_N2PLLCTRL 0x05b +#define GAISLER_SPI2AHB 0x05c +#define GAISLER_DDRSDMUX 0x05d +#define GAISLER_AHBFROM 0x05e +#define GAISLER_PCIEXP 0x05f +#define GAISLER_APBPS2 0x060 +#define GAISLER_VGACTRL 0x061 +#define GAISLER_LOGAN 0x062 +#define GAISLER_SVGACTRL 0x063 +#define GAISLER_T1AHB 0x064 +#define GAISLER_MP7WRAP 0x065 +#define GAISLER_GRSYSMON 0x066 +#define GAISLER_GRACECTRL 0x067 +#define GAISLER_ATAHBSLV 0x068 +#define GAISLER_ATAHBMST 0x069 +#define GAISLER_ATAPBSLV 0x06a +#define GAISLER_MIGDDR2 0x06b +#define GAISLER_LCDCTRL 0x06c +#define GAISLER_SWITCHOVER 0x06d +#define GAISLER_FIFOUART 0x06e +#define GAISLER_MUXCTRL 0x06f +#define GAISLER_B1553BC 0x070 +#define GAISLER_B1553RT 0x071 +#define GAISLER_B1553BRM 0x072 +#define GAISLER_GRAES 0x073 +#define GAISLER_AES 0x073 +#define GAISLER_ECC 0x074 +#define GAISLER_PCIF 0x075 +#define GAISLER_CLKMOD 0x076 +#define GAISLER_HAPSTRAK 0x077 +#define GAISLER_TEST_1X2 0x078 +#define GAISLER_WILD2AHB 0x079 +#define GAISLER_BIO1 0x07a +#define GAISLER_GRAESDMA 0x07b +#define GAISLER_AESDMA 0x07b +#define GAISLER_GRPCI2 0x07c +#define GAISLER_GRPCI2_DMA 0x07d +#define GAISLER_GRPCI2_TB 0x07e +#define GAISLER_MMA 0x07f +#define GAISLER_SATCAN 0x080 +#define GAISLER_CANMUX 0x081 +#define GAISLER_GRTMRX 0x082 +#define GAISLER_GRTCTX 0x083 +#define GAISLER_GRTMDESC 0x084 +#define GAISLER_GRTMVC 0x085 +#define GAISLER_GEFFE 0x086 +#define GAISLER_GPREG 0x087 +#define GAISLER_GRTMPAHB 0x088 +#define GAISLER_SPWCUC 0x089 +#define GAISLER_SPW2_DMA 0x08a +#define GAISLER_SPW_ROUTER 0x08b +#define GAISLER_SPWROUTER 0x08b +#define GAISLER_EDCLMST 0x08c +#define GAISLER_GRPWTX 0x08d +#define GAISLER_GRPWRX 0x08e +#define GAISLER_GPREGBANK 0x08f +#define GAISLER_MIG_7SERIES 0x090 +#define GAISLER_GRSPW2_SIST 0x091 +#define GAISLER_SGMII 0x092 +#define GAISLER_RGMII 0x093 +#define GAISLER_IRQGEN 0x094 +#define GAISLER_GRDMAC 0x095 +#define GAISLER_AHB2AVLA 0x096 +#define GAISLER_SPWTDP 0x097 +#define GAISLER_L3STAT 0x098 +#define GAISLER_GR740THS 0x099 +#define GAISLER_GRRM 0x09a +#define GAISLER_CMAP 0x09b +#define GAISLER_CPGEN 0x09c +#define GAISLER_AMBAPROT 0x09d #define GAISLER_IGLOO2_BRIDGE 0x09e -#define GAISLER_AHB2AXI 0x09f -#define GAISLER_AXI2AHB 0x0a0 -#define GAISLER_FDIR_RSTCTRL 0x0a1 -#define GAISLER_APB3MST 0x0a2 -#define GAISLER_LRAM 0x0a3 -#define GAISLER_BOOTSEQ 0x0a4 -#define GAISLER_TCCOP 0x0a5 -#define GAISLER_SPIMASTER 0x0a6 -#define GAISLER_SPISLAVE 0x0a7 -#define GAISLER_GRSRIO 0x0a8 -#define GAISLER_AHBLM2AHB 0x0a9 -#define GAISLER_AHBS2NOC 0x0aa -#define GAISLER_TCAU 0x0ab -#define GAISLER_GRTMDYNVCID 0x0ac -#define GAISLER_RNOCIRQPROP 0x0ad -#define GAISLER_FTADDR 0x0ae -#define GAISLER_ATG 0x0b0 -#define GAISLER_DFITRACE 0x0b1 -#define GAISLER_SELFTEST 0x0b2 -#define GAISLER_DFIERRINJ 0x0b3 -#define GAISLER_DFICHECK 0x0b4 -#define GAISLER_GRCANFD 0x0b5 -#define GAISLER_NIM 0x0b6 -#define GAISLER_BANDGAP 0x1f0 -#define GAISLER_MPROT 0x1f1 -#define GAISLER_ADC 0x1f2 -#define GAISLER_BO 0x1f3 -#define GAISLER_DAC 0x1f4 -#define GAISLER_PLL 0x1f6 +#define GAISLER_AHB2AXI 0x09f +#define GAISLER_AXI2AHB 0x0a0 +#define GAISLER_FDIR_RSTCTRL 0x0a1 +#define GAISLER_APB3MST 0x0a2 +#define GAISLER_LRAM 0x0a3 +#define GAISLER_BOOTSEQ 0x0a4 +#define GAISLER_TCCOP 0x0a5 +#define GAISLER_SPIMASTER 0x0a6 +#define GAISLER_SPISLAVE 0x0a7 +#define GAISLER_GRSRIO 0x0a8 +#define GAISLER_AHBLM2AHB 0x0a9 +#define GAISLER_AHBS2NOC 0x0aa +#define GAISLER_TCAU 0x0ab +#define GAISLER_GRTMDYNVCID 0x0ac +#define GAISLER_RNOCIRQPROP 0x0ad +#define GAISLER_FTADDR 0x0ae +#define GAISLER_ATG 0x0b0 +#define GAISLER_DFITRACE 0x0b1 +#define GAISLER_SELFTEST 0x0b2 +#define GAISLER_DFIERRINJ 0x0b3 +#define GAISLER_DFICHECK 0x0b4 +#define GAISLER_GRCANFD 0x0b5 +#define GAISLER_NIM 0x0b6 +#define GAISLER_BANDGAP 0x1f0 +#define GAISLER_MPROT 0x1f1 +#define GAISLER_ADC 0x1f2 +#define GAISLER_BO 0x1f3 +#define GAISLER_DAC 0x1f4 +#define GAISLER_PLL 0x1f6 -#define GAISLER_PIPEWRAPPER 0xffa -#define GAISLER_L2TIME 0xffd /* internal device: leon2 timer */ -#define GAISLER_L2C 0xffe /* internal device: leon2compat */ -#define GAISLER_PLUGPLAY 0xfff /* internal device: plug & play configarea */ +#define GAISLER_PIPEWRAPPER 0xffa +#define GAISLER_L2TIME 0xffd /* internal device: leon2 timer */ +#define GAISLER_L2C 0xffe /* internal device: leon2compat */ +#define GAISLER_PLUGPLAY 0xfff /* internal device: plug & play configarea */ /* European Space Agency device id's */ -#define ESA_LEON2 0x002 -#define ESA_LEON2APB 0x003 -#define ESA_IRQ 0x005 -#define ESA_TIMER 0x006 -#define ESA_UART 0x007 -#define ESA_CFG 0x008 -#define ESA_IO 0x009 -#define ESA_MCTRL 0x00f -#define ESA_PCIARB 0x010 -#define ESA_HURRICANE 0x011 -#define ESA_SPW_RMAP 0x012 -#define ESA_SPW2 0x012 -#define ESA_AHBUART 0x013 -#define ESA_SPWA 0x014 -#define ESA_BOSCHCAN 0x015 -#define ESA_IRQ2 0x016 -#define ESA_AHBSTAT 0x017 -#define ESA_WPROT 0x018 -#define ESA_WPROT2 0x019 -#define ESA_PDEC3AMBA 0x020 -#define ESA_PTME3AMBA 0x021 +#define ESA_LEON2 0x002 +#define ESA_LEON2APB 0x003 +#define ESA_IRQ 0x005 +#define ESA_TIMER 0x006 +#define ESA_UART 0x007 +#define ESA_CFG 0x008 +#define ESA_IO 0x009 +#define ESA_MCTRL 0x00f +#define ESA_PCIARB 0x010 +#define ESA_HURRICANE 0x011 +#define ESA_SPW_RMAP 0x012 +#define ESA_SPW2 0x012 +#define ESA_AHBUART 0x013 +#define ESA_SPWA 0x014 +#define ESA_BOSCHCAN 0x015 +#define ESA_IRQ2 0x016 +#define ESA_AHBSTAT 0x017 +#define ESA_WPROT 0x018 +#define ESA_WPROT2 0x019 +#define ESA_PDEC3AMBA 0x020 +#define ESA_PTME3AMBA 0x021 -#define OPENCHIP_APBGPIO 0x001 -#define OPENCHIP_APBI2C 0x002 -#define OPENCHIP_APBSPI 0x003 -#define OPENCHIP_APBCHARLCD 0x004 -#define OPENCHIP_APBPWM 0x005 -#define OPENCHIP_APBPS2 0x006 -#define OPENCHIP_APBMMCSD 0x007 -#define OPENCHIP_APBNAND 0x008 -#define OPENCHIP_APBLPC 0x009 -#define OPENCHIP_APBCF 0x00a -#define OPENCHIP_APBSYSACE 0x00b -#define OPENCHIP_APB1WIRE 0x00c -#define OPENCHIP_APBJTAG 0x00d -#define OPENCHIP_APBSUI 0x00e +#define OPENCHIP_APBGPIO 0x001 +#define OPENCHIP_APBI2C 0x002 +#define OPENCHIP_APBSPI 0x003 +#define OPENCHIP_APBCHARLCD 0x004 +#define OPENCHIP_APBPWM 0x005 +#define OPENCHIP_APBPS2 0x006 +#define OPENCHIP_APBMMCSD 0x007 +#define OPENCHIP_APBNAND 0x008 +#define OPENCHIP_APBLPC 0x009 +#define OPENCHIP_APBCF 0x00a +#define OPENCHIP_APBSYSACE 0x00b +#define OPENCHIP_APB1WIRE 0x00c +#define OPENCHIP_APBJTAG 0x00d +#define OPENCHIP_APBSUI 0x00e +#define CONTRIB_CORE1 0x001 +#define CONTRIB_CORE2 0x002 -#define CONTRIB_CORE1 0x001 -#define CONTRIB_CORE2 0x002 +#define GLEICHMANN_CUSTOM 0x001 +#define GLEICHMANN_GEOLCD01 0x002 +#define GLEICHMANN_DAC 0x003 +#define GLEICHMANN_HPI 0x004 +#define GLEICHMANN_SPI 0x005 +#define GLEICHMANN_HIFC 0x006 +#define GLEICHMANN_ADCDAC 0x007 +#define GLEICHMANN_SPIOC 0x008 +#define GLEICHMANN_AC97 0x009 -#define GLEICHMANN_CUSTOM 0x001 -#define GLEICHMANN_GEOLCD01 0x002 -#define GLEICHMANN_DAC 0x003 -#define GLEICHMANN_HPI 0x004 -#define GLEICHMANN_SPI 0x005 -#define GLEICHMANN_HIFC 0x006 -#define GLEICHMANN_ADCDAC 0x007 -#define GLEICHMANN_SPIOC 0x008 -#define GLEICHMANN_AC97 0x009 +#define SUN_T1 0x001 +#define SUN_S1 0x011 -#define SUN_T1 0x001 -#define SUN_S1 0x011 +#define ORBITA_1553B 0x001 +#define ORBITA_429 0x002 +#define ORBITA_SPI 0x003 +#define ORBITA_I2C 0x004 +#define ORBITA_SMARTCARD 0x064 +#define ORBITA_SDCARD 0x065 +#define ORBITA_UART16550 0x066 +#define ORBITA_CRYPTO 0x067 +#define ORBITA_SYSIF 0x068 +#define ORBITA_PIO 0x069 +#define ORBITA_RTC 0x0c8 +#define ORBITA_COLORLCD 0x12c +#define ORBITA_PCI 0x190 +#define ORBITA_DSP 0x1f4 +#define ORBITA_USBHOST 0x258 +#define ORBITA_USBDEV 0x2bc -#define ORBITA_1553B 0x001 -#define ORBITA_429 0x002 -#define ORBITA_SPI 0x003 -#define ORBITA_I2C 0x004 -#define ORBITA_SMARTCARD 0x064 -#define ORBITA_SDCARD 0x065 -#define ORBITA_UART16550 0x066 -#define ORBITA_CRYPTO 0x067 -#define ORBITA_SYSIF 0x068 -#define ORBITA_PIO 0x069 -#define ORBITA_RTC 0x0c8 -#define ORBITA_COLORLCD 0x12c -#define ORBITA_PCI 0x190 -#define ORBITA_DSP 0x1f4 -#define ORBITA_USBHOST 0x258 -#define ORBITA_USBDEV 0x2bc +#define NASA_EP32 0x001 -#define NASA_EP32 0x001 +#define CAL_DDRCTRL 0x188 -#define CAL_DDRCTRL 0x188 - -#define ACTEL_COREMP7 0x001 +#define ACTEL_COREMP7 0x001 /* Opencores device id's */ #define OPENCORES_PCIBR 0x4 diff --git a/bsps/include/grlib/apbuart-regs.h b/bsps/include/grlib/apbuart-regs.h index c3ea2d0f8e..61e06a9e0d 100644 --- a/bsps/include/grlib/apbuart-regs.h +++ b/bsps/include/grlib/apbuart-regs.h @@ -82,17 +82,14 @@ extern "C" { */ #define APBUART_DATA_DATA_SHIFT 0 -#define APBUART_DATA_DATA_MASK 0xffU +#define APBUART_DATA_DATA_MASK 0xffU #define APBUART_DATA_DATA_GET( _reg ) \ - ( ( ( _reg ) & APBUART_DATA_DATA_MASK ) >> \ - APBUART_DATA_DATA_SHIFT ) -#define APBUART_DATA_DATA_SET( _reg, _val ) \ + ( ( ( _reg ) & APBUART_DATA_DATA_MASK ) >> APBUART_DATA_DATA_SHIFT ) +#define APBUART_DATA_DATA_SET( _reg, _val ) \ ( ( ( _reg ) & ~APBUART_DATA_DATA_MASK ) | \ - ( ( ( _val ) << APBUART_DATA_DATA_SHIFT ) & \ - APBUART_DATA_DATA_MASK ) ) + ( ( ( _val ) << APBUART_DATA_DATA_SHIFT ) & APBUART_DATA_DATA_MASK ) ) #define APBUART_DATA_DATA( _val ) \ - ( ( ( _val ) << APBUART_DATA_DATA_SHIFT ) & \ - APBUART_DATA_DATA_MASK ) + ( ( ( _val ) << APBUART_DATA_DATA_SHIFT ) & APBUART_DATA_DATA_MASK ) /** @} */ @@ -105,30 +102,26 @@ extern "C" { */ #define APBUART_STATUS_RCNT_SHIFT 26 -#define APBUART_STATUS_RCNT_MASK 0xfc000000U +#define APBUART_STATUS_RCNT_MASK 0xfc000000U #define APBUART_STATUS_RCNT_GET( _reg ) \ - ( ( ( _reg ) & APBUART_STATUS_RCNT_MASK ) >> \ - APBUART_STATUS_RCNT_SHIFT ) -#define APBUART_STATUS_RCNT_SET( _reg, _val ) \ - ( ( ( _reg ) & ~APBUART_STATUS_RCNT_MASK ) | \ + ( ( ( _reg ) & APBUART_STATUS_RCNT_MASK ) >> APBUART_STATUS_RCNT_SHIFT ) +#define APBUART_STATUS_RCNT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~APBUART_STATUS_RCNT_MASK ) | \ ( ( ( _val ) << APBUART_STATUS_RCNT_SHIFT ) & \ APBUART_STATUS_RCNT_MASK ) ) #define APBUART_STATUS_RCNT( _val ) \ - ( ( ( _val ) << APBUART_STATUS_RCNT_SHIFT ) & \ - APBUART_STATUS_RCNT_MASK ) + ( ( ( _val ) << APBUART_STATUS_RCNT_SHIFT ) & APBUART_STATUS_RCNT_MASK ) #define APBUART_STATUS_TCNT_SHIFT 20 -#define APBUART_STATUS_TCNT_MASK 0x3f00000U +#define APBUART_STATUS_TCNT_MASK 0x3f00000U #define APBUART_STATUS_TCNT_GET( _reg ) \ - ( ( ( _reg ) & APBUART_STATUS_TCNT_MASK ) >> \ - APBUART_STATUS_TCNT_SHIFT ) -#define APBUART_STATUS_TCNT_SET( _reg, _val ) \ - ( ( ( _reg ) & ~APBUART_STATUS_TCNT_MASK ) | \ + ( ( ( _reg ) & APBUART_STATUS_TCNT_MASK ) >> APBUART_STATUS_TCNT_SHIFT ) +#define APBUART_STATUS_TCNT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~APBUART_STATUS_TCNT_MASK ) | \ ( ( ( _val ) << APBUART_STATUS_TCNT_SHIFT ) & \ APBUART_STATUS_TCNT_MASK ) ) #define APBUART_STATUS_TCNT( _val ) \ - ( ( ( _val ) << APBUART_STATUS_TCNT_SHIFT ) & \ - APBUART_STATUS_TCNT_MASK ) + ( ( ( _val ) << APBUART_STATUS_TCNT_SHIFT ) & APBUART_STATUS_TCNT_MASK ) #define APBUART_STATUS_RF 0x400U @@ -205,15 +198,15 @@ extern "C" { */ #define APBUART_SCALER_SCALER_RELOAD_VALUE_SHIFT 0 -#define APBUART_SCALER_SCALER_RELOAD_VALUE_MASK 0xfffffU -#define APBUART_SCALER_SCALER_RELOAD_VALUE_GET( _reg ) \ +#define APBUART_SCALER_SCALER_RELOAD_VALUE_MASK 0xfffffU +#define APBUART_SCALER_SCALER_RELOAD_VALUE_GET( _reg ) \ ( ( ( _reg ) & APBUART_SCALER_SCALER_RELOAD_VALUE_MASK ) >> \ APBUART_SCALER_SCALER_RELOAD_VALUE_SHIFT ) -#define APBUART_SCALER_SCALER_RELOAD_VALUE_SET( _reg, _val ) \ - ( ( ( _reg ) & ~APBUART_SCALER_SCALER_RELOAD_VALUE_MASK ) | \ +#define APBUART_SCALER_SCALER_RELOAD_VALUE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~APBUART_SCALER_SCALER_RELOAD_VALUE_MASK ) | \ ( ( ( _val ) << APBUART_SCALER_SCALER_RELOAD_VALUE_SHIFT ) & \ APBUART_SCALER_SCALER_RELOAD_VALUE_MASK ) ) -#define APBUART_SCALER_SCALER_RELOAD_VALUE( _val ) \ +#define APBUART_SCALER_SCALER_RELOAD_VALUE( _val ) \ ( ( ( _val ) << APBUART_SCALER_SCALER_RELOAD_VALUE_SHIFT ) & \ APBUART_SCALER_SCALER_RELOAD_VALUE_MASK ) @@ -228,17 +221,14 @@ extern "C" { */ #define APBUART_FIFO_DATA_SHIFT 0 -#define APBUART_FIFO_DATA_MASK 0xffU +#define APBUART_FIFO_DATA_MASK 0xffU #define APBUART_FIFO_DATA_GET( _reg ) \ - ( ( ( _reg ) & APBUART_FIFO_DATA_MASK ) >> \ - APBUART_FIFO_DATA_SHIFT ) -#define APBUART_FIFO_DATA_SET( _reg, _val ) \ + ( ( ( _reg ) & APBUART_FIFO_DATA_MASK ) >> APBUART_FIFO_DATA_SHIFT ) +#define APBUART_FIFO_DATA_SET( _reg, _val ) \ ( ( ( _reg ) & ~APBUART_FIFO_DATA_MASK ) | \ - ( ( ( _val ) << APBUART_FIFO_DATA_SHIFT ) & \ - APBUART_FIFO_DATA_MASK ) ) + ( ( ( _val ) << APBUART_FIFO_DATA_SHIFT ) & APBUART_FIFO_DATA_MASK ) ) #define APBUART_FIFO_DATA( _val ) \ - ( ( ( _val ) << APBUART_FIFO_DATA_SHIFT ) & \ - APBUART_FIFO_DATA_MASK ) + ( ( ( _val ) << APBUART_FIFO_DATA_SHIFT ) & APBUART_FIFO_DATA_MASK ) /** @} */ diff --git a/bsps/include/grlib/apbuart_cons.h b/bsps/include/grlib/apbuart_cons.h index a2846580cc..ba918280a1 100644 --- a/bsps/include/grlib/apbuart_cons.h +++ b/bsps/include/grlib/apbuart_cons.h @@ -30,6 +30,6 @@ #ifndef __APBUART_CONS_H__ #define __APBUART_CONS_H__ -void apbuart_cons_register_drv (void); +void apbuart_cons_register_drv( void ); #endif diff --git a/bsps/include/grlib/apbuart_termios.h b/bsps/include/grlib/apbuart_termios.h index a19b99b609..0340318624 100644 --- a/bsps/include/grlib/apbuart_termios.h +++ b/bsps/include/grlib/apbuart_termios.h @@ -42,11 +42,11 @@ extern "C" { struct apbuart_context { rtems_termios_device_context base; - apbuart *regs; - unsigned int freq_hz; - rtems_vector_number irq; - volatile int sending; - char *buf; + apbuart *regs; + unsigned int freq_hz; + rtems_vector_number irq; + volatile int sending; + char *buf; }; extern const rtems_termios_device_handler apbuart_handler_interrupt; diff --git a/bsps/include/grlib/b1553brm.h b/bsps/include/grlib/b1553brm.h index 1f5d5c66ad..5804939c5a 100644 --- a/bsps/include/grlib/b1553brm.h +++ b/bsps/include/grlib/b1553brm.h @@ -51,47 +51,47 @@ extern "C" { #endif struct brm_reg { - volatile uint32_t ctrl; /* 0x00 */ - volatile uint32_t oper; /* 0x04 */ - volatile uint32_t cur_cmd; /* 0x08 */ - volatile uint32_t imask; /* 0x0C */ - volatile uint32_t ipend; /* 0x10 */ - volatile uint32_t ipoint; /* 0x14 */ - volatile uint32_t bit_reg; /* 0x18 */ - volatile uint32_t ttag; /* 0x1C */ - volatile uint32_t dpoint; /* 0x20 */ - volatile uint32_t sw; /* 0x24 */ - volatile uint32_t initcount; /* 0x28 */ - volatile uint32_t mcpoint; /* 0x2C */ - volatile uint32_t mdpoint; /* 0x30 */ - volatile uint32_t mbc; /* 0x34 */ - volatile uint32_t mfilta; /* 0x38 */ - volatile uint32_t mfiltb; /* 0x3C */ - volatile uint32_t rt_cmd_leg[16]; /* 0x40-0x80 */ - volatile uint32_t enhanced; /* 0x84 */ + volatile uint32_t ctrl; /* 0x00 */ + volatile uint32_t oper; /* 0x04 */ + volatile uint32_t cur_cmd; /* 0x08 */ + volatile uint32_t imask; /* 0x0C */ + volatile uint32_t ipend; /* 0x10 */ + volatile uint32_t ipoint; /* 0x14 */ + volatile uint32_t bit_reg; /* 0x18 */ + volatile uint32_t ttag; /* 0x1C */ + volatile uint32_t dpoint; /* 0x20 */ + volatile uint32_t sw; /* 0x24 */ + volatile uint32_t initcount; /* 0x28 */ + volatile uint32_t mcpoint; /* 0x2C */ + volatile uint32_t mdpoint; /* 0x30 */ + volatile uint32_t mbc; /* 0x34 */ + volatile uint32_t mfilta; /* 0x38 */ + volatile uint32_t mfiltb; /* 0x3C */ + volatile uint32_t rt_cmd_leg[ 16 ]; /* 0x40-0x80 */ + volatile uint32_t enhanced; /* 0x84 */ - volatile uint32_t dummy[31]; + volatile uint32_t dummy[ 31 ]; - volatile uint32_t w_ctrl; /* 0x100 */ - volatile uint32_t w_irqctrl; /* 0x104 */ - volatile uint32_t w_ahbaddr; /* 0x108 */ + volatile uint32_t w_ctrl; /* 0x100 */ + volatile uint32_t w_irqctrl; /* 0x104 */ + volatile uint32_t w_ahbaddr; /* 0x108 */ }; struct bm_msg { - unsigned short miw; - unsigned short cw1; - unsigned short cw2; - unsigned short sw1; - unsigned short sw2; - unsigned short time; - unsigned short data[32]; + unsigned short miw; + unsigned short cw1; + unsigned short cw2; + unsigned short sw1; + unsigned short sw2; + unsigned short time; + unsigned short data[ 32 ]; }; struct rt_msg { - unsigned short miw; - unsigned short time; - unsigned short data[32]; - unsigned short desc; + unsigned short miw; + unsigned short time; + unsigned short data[ 32 ]; + unsigned short desc; }; /* @@ -114,37 +114,36 @@ struct rt_msg { * */ struct bc_msg { - unsigned char rtaddr[2]; - unsigned char subaddr[2]; - unsigned short wc; - unsigned short ctrl; - unsigned short tsw[2]; - unsigned short data[32]; + unsigned char rtaddr[ 2 ]; + unsigned char subaddr[ 2 ]; + unsigned short wc; + unsigned short ctrl; + unsigned short tsw[ 2 ]; + unsigned short data[ 32 ]; }; /* BC control bits */ -#define BC_TR 0x0001 -#define BC_RTRT 0x0002 -#define BC_BUSA 0x0004 -#define BC_EOL 0x0020 -#define BC_SKIP 0x0040 -#define BC_BAME 0x8000 - -#define BRM_MBC_IRQ 1 /* Monitor Block Counter irq */ -#define BRM_CBA_IRQ 2 /* Command Block Accessed irq */ -#define BRM_RTF_IRQ 4 /* Retry Fail irq */ -#define BRM_ILLOP_IRQ 8 /* Illogical Opcode irq */ -#define BRM_BC_ILLCMD_IRQ 16 /* BC Illocigal Command irq */ -#define BRM_EOL_IRQ 32 /* End Of List irq */ -#define BRM_RT_ILLCMD_IRQ 128 /* RT Illegal Command irq */ -#define BRM_IXEQ0_IRQ 256 /* Index Equal Zero irq */ -#define BRM_BDRCV_IRQ 512 /* Broadcast Command Received irq */ -#define BRM_SUBAD_IRQ 1024 /* Subaddress Accessed irq */ -#define BRM_MERR_IRQ 2048 /* Message Error irq */ -#define BRM_TAPF_IRQ 8192 /* Terminal Address Parity Fail irq */ -#define BRM_WRAPF_IRQ 16384 /* Wrap Fail irq */ -#define BRM_DMAF_IRQ 32768 /* DMA Fail irq */ +#define BC_TR 0x0001 +#define BC_RTRT 0x0002 +#define BC_BUSA 0x0004 +#define BC_EOL 0x0020 +#define BC_SKIP 0x0040 +#define BC_BAME 0x8000 +#define BRM_MBC_IRQ 1 /* Monitor Block Counter irq */ +#define BRM_CBA_IRQ 2 /* Command Block Accessed irq */ +#define BRM_RTF_IRQ 4 /* Retry Fail irq */ +#define BRM_ILLOP_IRQ 8 /* Illogical Opcode irq */ +#define BRM_BC_ILLCMD_IRQ 16 /* BC Illocigal Command irq */ +#define BRM_EOL_IRQ 32 /* End Of List irq */ +#define BRM_RT_ILLCMD_IRQ 128 /* RT Illegal Command irq */ +#define BRM_IXEQ0_IRQ 256 /* Index Equal Zero irq */ +#define BRM_BDRCV_IRQ 512 /* Broadcast Command Received irq */ +#define BRM_SUBAD_IRQ 1024 /* Subaddress Accessed irq */ +#define BRM_MERR_IRQ 2048 /* Message Error irq */ +#define BRM_TAPF_IRQ 8192 /* Terminal Address Parity Fail irq */ +#define BRM_WRAPF_IRQ 16384 /* Wrap Fail irq */ +#define BRM_DMAF_IRQ 32768 /* DMA Fail irq */ #define BRM_SET_MODE 0 #define BRM_SET_BUS 1 @@ -155,32 +154,31 @@ struct bc_msg { #define BRM_TX_BLOCK 7 #define BRM_RX_BLOCK 8 -#define BRM_DO_LIST 10 -#define BRM_LIST_DONE 11 +#define BRM_DO_LIST 10 +#define BRM_LIST_DONE 11 #define BRM_CLR_STATUS 12 #define BRM_GET_STATUS 13 #define BRM_SET_EVENTID 14 -#define GET_ERROR_DESCRIPTOR(event_in) (event_in>>16) +#define GET_ERROR_DESCRIPTOR( event_in ) ( event_in >> 16 ) - -#define BRM_MODE_BC 0x0 -#define BRM_MODE_RT 0x1 -#define BRM_MODE_BM 0x2 +#define BRM_MODE_BC 0x0 +#define BRM_MODE_RT 0x1 +#define BRM_MODE_BM 0x2 #define BRM_MODE_BM_RT 0x3 /* both RT and BM */ #define BRM_FREQ_12MHZ 0 #define BRM_FREQ_16MHZ 1 #define BRM_FREQ_20MHZ 2 #define BRM_FREQ_24MHZ 3 -#define BRM_FREQ_MASK 0x3 +#define BRM_FREQ_MASK 0x3 #define CLKDIV_MASK 0xf #define CLKSEL_MASK 0x7 -void b1553brm_register_drv(void); +void b1553brm_register_drv( void ); /* Default initialization of the RT legalization registers. The values in this * array are written to the registers on boot driver initialization and when @@ -188,13 +186,13 @@ void b1553brm_register_drv(void); * update the array first then call ioctl(BRM_SET_MODE) for the changes to have * an affect. Note that this affects all B1553BRM RTs in the system. */ -extern unsigned short b1553brm_rt_cmd_legalize[16]; +extern unsigned short b1553brm_rt_cmd_legalize[ 16 ]; /* Print information about all BRM devices handled by this driver */ -void b1553brm_print(int options); +void b1553brm_print( int options ); /* Print information about one BRM device */ -void b1553brm_print_dev(struct drvmgr_dev *dev, int options); +void b1553brm_print_dev( struct drvmgr_dev *dev, int options ); #ifdef __cplusplus } @@ -203,4 +201,3 @@ void b1553brm_print_dev(struct drvmgr_dev *dev, int options); /** @} */ #endif /* __BRM_H__ */ - diff --git a/bsps/include/grlib/b1553rt.h b/bsps/include/grlib/b1553rt.h index b792c33a96..7c49795ada 100644 --- a/bsps/include/grlib/b1553rt.h +++ b/bsps/include/grlib/b1553rt.h @@ -37,27 +37,26 @@ extern "C" { #endif struct rt_reg { - volatile uint32_t stat; /* 0x00 */ - volatile uint32_t ctrl; /* 0x04 */ - volatile uint32_t vword; /* 0x08 */ - volatile uint32_t irq; /* 0x0C */ - volatile uint32_t addr; /* 0x10 */ - volatile uint32_t ipm; /* 0x14 */ + volatile uint32_t stat; /* 0x00 */ + volatile uint32_t ctrl; /* 0x04 */ + volatile uint32_t vword; /* 0x08 */ + volatile uint32_t irq; /* 0x0C */ + volatile uint32_t addr; /* 0x10 */ + volatile uint32_t ipm; /* 0x14 */ }; - struct rt_msg { - unsigned short miw; - unsigned short time; - unsigned short data[32]; - unsigned short desc; + unsigned short miw; + unsigned short time; + unsigned short data[ 32 ]; + unsigned short desc; }; #define RT_FREQ_12MHZ 0 #define RT_FREQ_16MHZ 1 #define RT_FREQ_20MHZ 2 #define RT_FREQ_24MHZ 3 -#define RT_FREQ_MASK 0x3 +#define RT_FREQ_MASK 0x3 /* IOCTLs */ #define RT_SET_ADDR 3 @@ -67,32 +66,31 @@ struct rt_msg { #define RT_GET_STATUS 13 #define RT_SET_EVENTID 14 -#define RT_SET_VECTORW 32 +#define RT_SET_VECTORW 32 #define RT_SET_EXTMDATA 33 -#define RT_ILLCMD_IRQ 128 -#define RT_MERR_IRQ 2048 -#define RT_DMAF_IRQ 32768 /* DMA Fail irq */ +#define RT_ILLCMD_IRQ 128 +#define RT_MERR_IRQ 2048 +#define RT_DMAF_IRQ 32768 /* DMA Fail irq */ -#define RT_TSW_OK (1<<14) -#define RT_TSW_BUS (1<<13) -#define RT_TSW_BC (1<<12) -#define RT_TSW_LPBKERRB (1<<11) -#define RT_TSW_LPBKERRA (1<<10) -#define RT_TSW_ILL (1<<9) -#define RT_TSW_MEM (1<<8) -#define RT_TSW_MAN (1<<7) -#define RT_TSW_PAR (1<<6) -#define RT_TSW_WC (1<<5) +#define RT_TSW_OK ( 1 << 14 ) +#define RT_TSW_BUS ( 1 << 13 ) +#define RT_TSW_BC ( 1 << 12 ) +#define RT_TSW_LPBKERRB ( 1 << 11 ) +#define RT_TSW_LPBKERRA ( 1 << 10 ) +#define RT_TSW_ILL ( 1 << 9 ) +#define RT_TSW_MEM ( 1 << 8 ) +#define RT_TSW_MAN ( 1 << 7 ) +#define RT_TSW_PAR ( 1 << 6 ) +#define RT_TSW_WC ( 1 << 5 ) -void b1553rt_print_dev(struct drvmgr_dev *dev, int options); -void b1553rt_print(int options); +void b1553rt_print_dev( struct drvmgr_dev *dev, int options ); +void b1553rt_print( int options ); -void b1553rt_register_drv(void); +void b1553rt_register_drv( void ); #ifdef __cplusplus } #endif #endif /* __RT_H__ */ - diff --git a/bsps/include/grlib/bspcommon.h b/bsps/include/grlib/bspcommon.h index 996fe6e80b..8f320e34ea 100644 --- a/bsps/include/grlib/bspcommon.h +++ b/bsps/include/grlib/bspcommon.h @@ -38,7 +38,7 @@ extern "C" { #endif /* Count driver resource array length. Array must be terminated with a NULL */ -int get_resarray_count(struct drvmgr_bus_res **array); +int get_resarray_count( struct drvmgr_bus_res **array ); #ifdef __cplusplus } diff --git a/bsps/include/grlib/canbtrs.h b/bsps/include/grlib/canbtrs.h index 7369136931..0860d81b08 100644 --- a/bsps/include/grlib/canbtrs.h +++ b/bsps/include/grlib/canbtrs.h @@ -50,21 +50,21 @@ extern "C" { /* CAN Baud-rate parameters, range of valid parameter values */ struct grlib_canbtrs_ranges { - unsigned int max_scaler; - char has_bpr; - unsigned char divfactor; - unsigned char min_tseg1; - unsigned char max_tseg1; - unsigned char min_tseg2; - unsigned char max_tseg2; + unsigned int max_scaler; + char has_bpr; + unsigned char divfactor; + unsigned char min_tseg1; + unsigned char max_tseg1; + unsigned char min_tseg2; + unsigned char max_tseg2; }; struct grlib_canbtrs_timing { - unsigned char scaler; - unsigned char ps1; - unsigned char ps2; - unsigned char rsj; - unsigned char bpr; + unsigned char scaler; + unsigned char ps1; + unsigned char ps2; + unsigned char rsj; + unsigned char bpr; }; /* @brief Calculate CAN baud-rate generation parameters from requested baud-rate @@ -80,12 +80,12 @@ struct grlib_canbtrs_timing { * margin from requested baud-rate */ int grlib_canbtrs_calc_timing( - unsigned int baud, - unsigned int core_hz, - unsigned int sampl_pt, - struct grlib_canbtrs_ranges *br, - struct grlib_canbtrs_timing *timing - ); + unsigned int baud, + unsigned int core_hz, + unsigned int sampl_pt, + struct grlib_canbtrs_ranges *br, + struct grlib_canbtrs_timing *timing +); #ifdef __cplusplus } diff --git a/bsps/include/grlib/canmux.h b/bsps/include/grlib/canmux.h index 1b59f7d468..d0aca82bcf 100644 --- a/bsps/include/grlib/canmux.h +++ b/bsps/include/grlib/canmux.h @@ -36,7 +36,7 @@ extern "C" { #endif /* Driver interface */ -int canmux_register(void); +int canmux_register( void ); /* ioctl calls */ #define CANMUX_IOC_BUSA_SATCAN 1 diff --git a/bsps/include/grlib/cons.h b/bsps/include/grlib/cons.h index 6f1f7ed44f..5418b9fd05 100644 --- a/bsps/include/grlib/cons.h +++ b/bsps/include/grlib/cons.h @@ -39,21 +39,21 @@ struct console_dev; -#define CONSOLE_FLAG_SYSCON 0x01 -#define CONSOLE_FLAG_SYSCON_GRANT 0x02 +#define CONSOLE_FLAG_SYSCON 0x01 +#define CONSOLE_FLAG_SYSCON_GRANT 0x02 struct console_dev { - rtems_termios_device_context base; - /* Set CONSOLE_FLAG_SYSCON to request this device to be system console + rtems_termios_device_context base; + /* Set CONSOLE_FLAG_SYSCON to request this device to be system console * and/or debug console. CONSOLE_FLAG_SYSCON_GRANT will be set on the * device which was selected as system console. */ - int flags; - char *fsname; /* File system prefix */ - const rtems_termios_device_handler *handler; + int flags; + char *fsname; /* File system prefix */ + const rtems_termios_device_handler *handler; }; -extern void console_dev_register(struct console_dev *dev); +extern void console_dev_register( struct console_dev *dev ); #if 0 extern void console_dev_unregister(struct console_dev *dev); #endif diff --git a/bsps/include/grlib/debug_defs.h b/bsps/include/grlib/debug_defs.h index bd425de152..e9efdd61ec 100644 --- a/bsps/include/grlib/debug_defs.h +++ b/bsps/include/grlib/debug_defs.h @@ -39,27 +39,40 @@ extern "C" { #endif - #ifdef DEBUG #ifndef DEBUG_FLAGS #define DEBUG_FLAGS 0 #endif - #define DBG(fmt, args...) do { printk(" : %03d @ %18s()]:" fmt , __LINE__,__FUNCTION__,## args); } while(0) - #define DBG2(fmt) do { printk(" : %03d @ %18s()]:" fmt , __LINE__,__FUNCTION__); } while(0) - #define DBGC(c,fmt, args...) do { if (DEBUG_FLAGS & c) { printk(" : %03d @ %18s()]:" fmt , __LINE__,__FUNCTION__,## args); }} while(0) + #define DBG( fmt, args... ) \ + do { \ + printk( " : %03d @ %18s()]:" fmt, __LINE__, __FUNCTION__, ##args ); \ + } while ( 0 ) + #define DBG2( fmt ) \ + do { \ + printk( " : %03d @ %18s()]:" fmt, __LINE__, __FUNCTION__ ); \ + } while ( 0 ) + #define DBGC( c, fmt, args... ) \ + do { \ + if ( DEBUG_FLAGS & c ) { \ + printk( " : %03d @ %18s()]:" fmt, __LINE__, __FUNCTION__, ##args ); \ + } \ + } while ( 0 ) #else - #define DBG(fmt, args...) - #define DBG2(fmt, args...) - #define DBGC(c, fmt, args...) + #define DBG( fmt, args... ) + #define DBG2( fmt, args... ) + #define DBGC( c, fmt, args... ) #endif #ifdef DEBUGFUNCS - #define FUNCDBG() do { printk("%s\n\r",__FUNCTION__); } while(0) + #define FUNCDBG() \ + do { \ + printk( "%s\n\r", __FUNCTION__ ); \ + } while ( 0 ) #else #define FUNCDBG() #endif diff --git a/bsps/include/grlib/dsu4-regs.h b/bsps/include/grlib/dsu4-regs.h index 3695430198..45f9d36baa 100644 --- a/bsps/include/grlib/dsu4-regs.h +++ b/bsps/include/grlib/dsu4-regs.h @@ -116,17 +116,14 @@ extern "C" { */ #define DSU4_DTTC_TIMETAG_SHIFT 0 -#define DSU4_DTTC_TIMETAG_MASK 0xffffffffU +#define DSU4_DTTC_TIMETAG_MASK 0xffffffffU #define DSU4_DTTC_TIMETAG_GET( _reg ) \ - ( ( ( _reg ) & DSU4_DTTC_TIMETAG_MASK ) >> \ - DSU4_DTTC_TIMETAG_SHIFT ) -#define DSU4_DTTC_TIMETAG_SET( _reg, _val ) \ + ( ( ( _reg ) & DSU4_DTTC_TIMETAG_MASK ) >> DSU4_DTTC_TIMETAG_SHIFT ) +#define DSU4_DTTC_TIMETAG_SET( _reg, _val ) \ ( ( ( _reg ) & ~DSU4_DTTC_TIMETAG_MASK ) | \ - ( ( ( _val ) << DSU4_DTTC_TIMETAG_SHIFT ) & \ - DSU4_DTTC_TIMETAG_MASK ) ) + ( ( ( _val ) << DSU4_DTTC_TIMETAG_SHIFT ) & DSU4_DTTC_TIMETAG_MASK ) ) #define DSU4_DTTC_TIMETAG( _val ) \ - ( ( ( _val ) << DSU4_DTTC_TIMETAG_SHIFT ) & \ - DSU4_DTTC_TIMETAG_MASK ) + ( ( ( _val ) << DSU4_DTTC_TIMETAG_SHIFT ) & DSU4_DTTC_TIMETAG_MASK ) /** @} */ @@ -139,30 +136,24 @@ extern "C" { */ #define DSU4_BRSS_SS_3_0_SHIFT 16 -#define DSU4_BRSS_SS_3_0_MASK 0xf0000U +#define DSU4_BRSS_SS_3_0_MASK 0xf0000U #define DSU4_BRSS_SS_3_0_GET( _reg ) \ - ( ( ( _reg ) & DSU4_BRSS_SS_3_0_MASK ) >> \ - DSU4_BRSS_SS_3_0_SHIFT ) -#define DSU4_BRSS_SS_3_0_SET( _reg, _val ) \ + ( ( ( _reg ) & DSU4_BRSS_SS_3_0_MASK ) >> DSU4_BRSS_SS_3_0_SHIFT ) +#define DSU4_BRSS_SS_3_0_SET( _reg, _val ) \ ( ( ( _reg ) & ~DSU4_BRSS_SS_3_0_MASK ) | \ - ( ( ( _val ) << DSU4_BRSS_SS_3_0_SHIFT ) & \ - DSU4_BRSS_SS_3_0_MASK ) ) + ( ( ( _val ) << DSU4_BRSS_SS_3_0_SHIFT ) & DSU4_BRSS_SS_3_0_MASK ) ) #define DSU4_BRSS_SS_3_0( _val ) \ - ( ( ( _val ) << DSU4_BRSS_SS_3_0_SHIFT ) & \ - DSU4_BRSS_SS_3_0_MASK ) + ( ( ( _val ) << DSU4_BRSS_SS_3_0_SHIFT ) & DSU4_BRSS_SS_3_0_MASK ) #define DSU4_BRSS_BN_3_0_SHIFT 0 -#define DSU4_BRSS_BN_3_0_MASK 0xfU +#define DSU4_BRSS_BN_3_0_MASK 0xfU #define DSU4_BRSS_BN_3_0_GET( _reg ) \ - ( ( ( _reg ) & DSU4_BRSS_BN_3_0_MASK ) >> \ - DSU4_BRSS_BN_3_0_SHIFT ) -#define DSU4_BRSS_BN_3_0_SET( _reg, _val ) \ + ( ( ( _reg ) & DSU4_BRSS_BN_3_0_MASK ) >> DSU4_BRSS_BN_3_0_SHIFT ) +#define DSU4_BRSS_BN_3_0_SET( _reg, _val ) \ ( ( ( _reg ) & ~DSU4_BRSS_BN_3_0_MASK ) | \ - ( ( ( _val ) << DSU4_BRSS_BN_3_0_SHIFT ) & \ - DSU4_BRSS_BN_3_0_MASK ) ) + ( ( ( _val ) << DSU4_BRSS_BN_3_0_SHIFT ) & DSU4_BRSS_BN_3_0_MASK ) ) #define DSU4_BRSS_BN_3_0( _val ) \ - ( ( ( _val ) << DSU4_BRSS_BN_3_0_SHIFT ) & \ - DSU4_BRSS_BN_3_0_MASK ) + ( ( ( _val ) << DSU4_BRSS_BN_3_0_SHIFT ) & DSU4_BRSS_BN_3_0_MASK ) /** @} */ @@ -175,30 +166,24 @@ extern "C" { */ #define DSU4_DBGM_DM_3_0_SHIFT 16 -#define DSU4_DBGM_DM_3_0_MASK 0xf0000U +#define DSU4_DBGM_DM_3_0_MASK 0xf0000U #define DSU4_DBGM_DM_3_0_GET( _reg ) \ - ( ( ( _reg ) & DSU4_DBGM_DM_3_0_MASK ) >> \ - DSU4_DBGM_DM_3_0_SHIFT ) -#define DSU4_DBGM_DM_3_0_SET( _reg, _val ) \ + ( ( ( _reg ) & DSU4_DBGM_DM_3_0_MASK ) >> DSU4_DBGM_DM_3_0_SHIFT ) +#define DSU4_DBGM_DM_3_0_SET( _reg, _val ) \ ( ( ( _reg ) & ~DSU4_DBGM_DM_3_0_MASK ) | \ - ( ( ( _val ) << DSU4_DBGM_DM_3_0_SHIFT ) & \ - DSU4_DBGM_DM_3_0_MASK ) ) + ( ( ( _val ) << DSU4_DBGM_DM_3_0_SHIFT ) & DSU4_DBGM_DM_3_0_MASK ) ) #define DSU4_DBGM_DM_3_0( _val ) \ - ( ( ( _val ) << DSU4_DBGM_DM_3_0_SHIFT ) & \ - DSU4_DBGM_DM_3_0_MASK ) + ( ( ( _val ) << DSU4_DBGM_DM_3_0_SHIFT ) & DSU4_DBGM_DM_3_0_MASK ) #define DSU4_DBGM_ED_3_0_SHIFT 0 -#define DSU4_DBGM_ED_3_0_MASK 0xfU +#define DSU4_DBGM_ED_3_0_MASK 0xfU #define DSU4_DBGM_ED_3_0_GET( _reg ) \ - ( ( ( _reg ) & DSU4_DBGM_ED_3_0_MASK ) >> \ - DSU4_DBGM_ED_3_0_SHIFT ) -#define DSU4_DBGM_ED_3_0_SET( _reg, _val ) \ + ( ( ( _reg ) & DSU4_DBGM_ED_3_0_MASK ) >> DSU4_DBGM_ED_3_0_SHIFT ) +#define DSU4_DBGM_ED_3_0_SET( _reg, _val ) \ ( ( ( _reg ) & ~DSU4_DBGM_ED_3_0_MASK ) | \ - ( ( ( _val ) << DSU4_DBGM_ED_3_0_SHIFT ) & \ - DSU4_DBGM_ED_3_0_MASK ) ) + ( ( ( _val ) << DSU4_DBGM_ED_3_0_SHIFT ) & DSU4_DBGM_ED_3_0_MASK ) ) #define DSU4_DBGM_ED_3_0( _val ) \ - ( ( ( _val ) << DSU4_DBGM_ED_3_0_SHIFT ) & \ - DSU4_DBGM_ED_3_0_MASK ) + ( ( ( _val ) << DSU4_DBGM_ED_3_0_SHIFT ) & DSU4_DBGM_ED_3_0_MASK ) /** @} */ @@ -213,17 +198,14 @@ extern "C" { #define DSU4_DTR_EM 0x1000U #define DSU4_DTR_TRAPTYPE_SHIFT 4 -#define DSU4_DTR_TRAPTYPE_MASK 0xff0U +#define DSU4_DTR_TRAPTYPE_MASK 0xff0U #define DSU4_DTR_TRAPTYPE_GET( _reg ) \ - ( ( ( _reg ) & DSU4_DTR_TRAPTYPE_MASK ) >> \ - DSU4_DTR_TRAPTYPE_SHIFT ) -#define DSU4_DTR_TRAPTYPE_SET( _reg, _val ) \ + ( ( ( _reg ) & DSU4_DTR_TRAPTYPE_MASK ) >> DSU4_DTR_TRAPTYPE_SHIFT ) +#define DSU4_DTR_TRAPTYPE_SET( _reg, _val ) \ ( ( ( _reg ) & ~DSU4_DTR_TRAPTYPE_MASK ) | \ - ( ( ( _val ) << DSU4_DTR_TRAPTYPE_SHIFT ) & \ - DSU4_DTR_TRAPTYPE_MASK ) ) + ( ( ( _val ) << DSU4_DTR_TRAPTYPE_SHIFT ) & DSU4_DTR_TRAPTYPE_MASK ) ) #define DSU4_DTR_TRAPTYPE( _val ) \ - ( ( ( _val ) << DSU4_DTR_TRAPTYPE_SHIFT ) & \ - DSU4_DTR_TRAPTYPE_MASK ) + ( ( ( _val ) << DSU4_DTR_TRAPTYPE_SHIFT ) & DSU4_DTR_TRAPTYPE_MASK ) /** @} */ @@ -236,17 +218,14 @@ extern "C" { */ #define DSU4_DASI_ASI_SHIFT 0 -#define DSU4_DASI_ASI_MASK 0xffU +#define DSU4_DASI_ASI_MASK 0xffU #define DSU4_DASI_ASI_GET( _reg ) \ - ( ( ( _reg ) & DSU4_DASI_ASI_MASK ) >> \ - DSU4_DASI_ASI_SHIFT ) -#define DSU4_DASI_ASI_SET( _reg, _val ) \ + ( ( ( _reg ) & DSU4_DASI_ASI_MASK ) >> DSU4_DASI_ASI_SHIFT ) +#define DSU4_DASI_ASI_SET( _reg, _val ) \ ( ( ( _reg ) & ~DSU4_DASI_ASI_MASK ) | \ - ( ( ( _val ) << DSU4_DASI_ASI_SHIFT ) & \ - DSU4_DASI_ASI_MASK ) ) + ( ( ( _val ) << DSU4_DASI_ASI_SHIFT ) & DSU4_DASI_ASI_MASK ) ) #define DSU4_DASI_ASI( _val ) \ - ( ( ( _val ) << DSU4_DASI_ASI_SHIFT ) & \ - DSU4_DASI_ASI_MASK ) + ( ( ( _val ) << DSU4_DASI_ASI_SHIFT ) & DSU4_DASI_ASI_MASK ) /** @} */ @@ -259,17 +238,14 @@ extern "C" { */ #define DSU4_ATBC_DCNT_SHIFT 16 -#define DSU4_ATBC_DCNT_MASK 0xff0000U +#define DSU4_ATBC_DCNT_MASK 0xff0000U #define DSU4_ATBC_DCNT_GET( _reg ) \ - ( ( ( _reg ) & DSU4_ATBC_DCNT_MASK ) >> \ - DSU4_ATBC_DCNT_SHIFT ) -#define DSU4_ATBC_DCNT_SET( _reg, _val ) \ + ( ( ( _reg ) & DSU4_ATBC_DCNT_MASK ) >> DSU4_ATBC_DCNT_SHIFT ) +#define DSU4_ATBC_DCNT_SET( _reg, _val ) \ ( ( ( _reg ) & ~DSU4_ATBC_DCNT_MASK ) | \ - ( ( ( _val ) << DSU4_ATBC_DCNT_SHIFT ) & \ - DSU4_ATBC_DCNT_MASK ) ) + ( ( ( _val ) << DSU4_ATBC_DCNT_SHIFT ) & DSU4_ATBC_DCNT_MASK ) ) #define DSU4_ATBC_DCNT( _val ) \ - ( ( ( _val ) << DSU4_ATBC_DCNT_SHIFT ) & \ - DSU4_ATBC_DCNT_MASK ) + ( ( ( _val ) << DSU4_ATBC_DCNT_SHIFT ) & DSU4_ATBC_DCNT_MASK ) #define DSU4_ATBC_DF 0x100U @@ -280,17 +256,14 @@ extern "C" { #define DSU4_ATBC_TF 0x20U #define DSU4_ATBC_BW_SHIFT 3 -#define DSU4_ATBC_BW_MASK 0x18U +#define DSU4_ATBC_BW_MASK 0x18U #define DSU4_ATBC_BW_GET( _reg ) \ - ( ( ( _reg ) & DSU4_ATBC_BW_MASK ) >> \ - DSU4_ATBC_BW_SHIFT ) -#define DSU4_ATBC_BW_SET( _reg, _val ) \ + ( ( ( _reg ) & DSU4_ATBC_BW_MASK ) >> DSU4_ATBC_BW_SHIFT ) +#define DSU4_ATBC_BW_SET( _reg, _val ) \ ( ( ( _reg ) & ~DSU4_ATBC_BW_MASK ) | \ - ( ( ( _val ) << DSU4_ATBC_BW_SHIFT ) & \ - DSU4_ATBC_BW_MASK ) ) + ( ( ( _val ) << DSU4_ATBC_BW_SHIFT ) & DSU4_ATBC_BW_MASK ) ) #define DSU4_ATBC_BW( _val ) \ - ( ( ( _val ) << DSU4_ATBC_BW_SHIFT ) & \ - DSU4_ATBC_BW_MASK ) + ( ( ( _val ) << DSU4_ATBC_BW_SHIFT ) & DSU4_ATBC_BW_MASK ) #define DSU4_ATBC_BR 0x4U @@ -309,17 +282,14 @@ extern "C" { */ #define DSU4_ATBI_INDEX_SHIFT 4 -#define DSU4_ATBI_INDEX_MASK 0xff0U +#define DSU4_ATBI_INDEX_MASK 0xff0U #define DSU4_ATBI_INDEX_GET( _reg ) \ - ( ( ( _reg ) & DSU4_ATBI_INDEX_MASK ) >> \ - DSU4_ATBI_INDEX_SHIFT ) -#define DSU4_ATBI_INDEX_SET( _reg, _val ) \ + ( ( ( _reg ) & DSU4_ATBI_INDEX_MASK ) >> DSU4_ATBI_INDEX_SHIFT ) +#define DSU4_ATBI_INDEX_SET( _reg, _val ) \ ( ( ( _reg ) & ~DSU4_ATBI_INDEX_MASK ) | \ - ( ( ( _val ) << DSU4_ATBI_INDEX_SHIFT ) & \ - DSU4_ATBI_INDEX_MASK ) ) + ( ( ( _val ) << DSU4_ATBI_INDEX_SHIFT ) & DSU4_ATBI_INDEX_MASK ) ) #define DSU4_ATBI_INDEX( _val ) \ - ( ( ( _val ) << DSU4_ATBI_INDEX_SHIFT ) & \ - DSU4_ATBI_INDEX_MASK ) + ( ( ( _val ) << DSU4_ATBI_INDEX_SHIFT ) & DSU4_ATBI_INDEX_MASK ) /** @} */ @@ -333,30 +303,24 @@ extern "C" { */ #define DSU4_ATBFC_WPF_SHIFT 12 -#define DSU4_ATBFC_WPF_MASK 0x3000U +#define DSU4_ATBFC_WPF_MASK 0x3000U #define DSU4_ATBFC_WPF_GET( _reg ) \ - ( ( ( _reg ) & DSU4_ATBFC_WPF_MASK ) >> \ - DSU4_ATBFC_WPF_SHIFT ) -#define DSU4_ATBFC_WPF_SET( _reg, _val ) \ + ( ( ( _reg ) & DSU4_ATBFC_WPF_MASK ) >> DSU4_ATBFC_WPF_SHIFT ) +#define DSU4_ATBFC_WPF_SET( _reg, _val ) \ ( ( ( _reg ) & ~DSU4_ATBFC_WPF_MASK ) | \ - ( ( ( _val ) << DSU4_ATBFC_WPF_SHIFT ) & \ - DSU4_ATBFC_WPF_MASK ) ) + ( ( ( _val ) << DSU4_ATBFC_WPF_SHIFT ) & DSU4_ATBFC_WPF_MASK ) ) #define DSU4_ATBFC_WPF( _val ) \ - ( ( ( _val ) << DSU4_ATBFC_WPF_SHIFT ) & \ - DSU4_ATBFC_WPF_MASK ) + ( ( ( _val ) << DSU4_ATBFC_WPF_SHIFT ) & DSU4_ATBFC_WPF_MASK ) #define DSU4_ATBFC_BPF_SHIFT 8 -#define DSU4_ATBFC_BPF_MASK 0x300U +#define DSU4_ATBFC_BPF_MASK 0x300U #define DSU4_ATBFC_BPF_GET( _reg ) \ - ( ( ( _reg ) & DSU4_ATBFC_BPF_MASK ) >> \ - DSU4_ATBFC_BPF_SHIFT ) -#define DSU4_ATBFC_BPF_SET( _reg, _val ) \ + ( ( ( _reg ) & DSU4_ATBFC_BPF_MASK ) >> DSU4_ATBFC_BPF_SHIFT ) +#define DSU4_ATBFC_BPF_SET( _reg, _val ) \ ( ( ( _reg ) & ~DSU4_ATBFC_BPF_MASK ) | \ - ( ( ( _val ) << DSU4_ATBFC_BPF_SHIFT ) & \ - DSU4_ATBFC_BPF_MASK ) ) + ( ( ( _val ) << DSU4_ATBFC_BPF_SHIFT ) & DSU4_ATBFC_BPF_MASK ) ) #define DSU4_ATBFC_BPF( _val ) \ - ( ( ( _val ) << DSU4_ATBFC_BPF_SHIFT ) & \ - DSU4_ATBFC_BPF_MASK ) + ( ( ( _val ) << DSU4_ATBFC_BPF_SHIFT ) & DSU4_ATBFC_BPF_MASK ) #define DSU4_ATBFC_PF 0x8U @@ -378,30 +342,26 @@ extern "C" { */ #define DSU4_ATBFM_SMASK_15_0_SHIFT 16 -#define DSU4_ATBFM_SMASK_15_0_MASK 0xffff0000U +#define DSU4_ATBFM_SMASK_15_0_MASK 0xffff0000U #define DSU4_ATBFM_SMASK_15_0_GET( _reg ) \ - ( ( ( _reg ) & DSU4_ATBFM_SMASK_15_0_MASK ) >> \ - DSU4_ATBFM_SMASK_15_0_SHIFT ) -#define DSU4_ATBFM_SMASK_15_0_SET( _reg, _val ) \ - ( ( ( _reg ) & ~DSU4_ATBFM_SMASK_15_0_MASK ) | \ + ( ( ( _reg ) & DSU4_ATBFM_SMASK_15_0_MASK ) >> DSU4_ATBFM_SMASK_15_0_SHIFT ) +#define DSU4_ATBFM_SMASK_15_0_SET( _reg, _val ) \ + ( ( ( _reg ) & ~DSU4_ATBFM_SMASK_15_0_MASK ) | \ ( ( ( _val ) << DSU4_ATBFM_SMASK_15_0_SHIFT ) & \ DSU4_ATBFM_SMASK_15_0_MASK ) ) #define DSU4_ATBFM_SMASK_15_0( _val ) \ - ( ( ( _val ) << DSU4_ATBFM_SMASK_15_0_SHIFT ) & \ - DSU4_ATBFM_SMASK_15_0_MASK ) + ( ( ( _val ) << DSU4_ATBFM_SMASK_15_0_SHIFT ) & DSU4_ATBFM_SMASK_15_0_MASK ) #define DSU4_ATBFM_MMASK_15_0_SHIFT 0 -#define DSU4_ATBFM_MMASK_15_0_MASK 0xffffU +#define DSU4_ATBFM_MMASK_15_0_MASK 0xffffU #define DSU4_ATBFM_MMASK_15_0_GET( _reg ) \ - ( ( ( _reg ) & DSU4_ATBFM_MMASK_15_0_MASK ) >> \ - DSU4_ATBFM_MMASK_15_0_SHIFT ) -#define DSU4_ATBFM_MMASK_15_0_SET( _reg, _val ) \ - ( ( ( _reg ) & ~DSU4_ATBFM_MMASK_15_0_MASK ) | \ + ( ( ( _reg ) & DSU4_ATBFM_MMASK_15_0_MASK ) >> DSU4_ATBFM_MMASK_15_0_SHIFT ) +#define DSU4_ATBFM_MMASK_15_0_SET( _reg, _val ) \ + ( ( ( _reg ) & ~DSU4_ATBFM_MMASK_15_0_MASK ) | \ ( ( ( _val ) << DSU4_ATBFM_MMASK_15_0_SHIFT ) & \ DSU4_ATBFM_MMASK_15_0_MASK ) ) #define DSU4_ATBFM_MMASK_15_0( _val ) \ - ( ( ( _val ) << DSU4_ATBFM_MMASK_15_0_SHIFT ) & \ - DSU4_ATBFM_MMASK_15_0_MASK ) + ( ( ( _val ) << DSU4_ATBFM_MMASK_15_0_SHIFT ) & DSU4_ATBFM_MMASK_15_0_MASK ) /** @} */ @@ -415,17 +375,15 @@ extern "C" { */ #define DSU4_ATBBA_BADDR_31_2_SHIFT 2 -#define DSU4_ATBBA_BADDR_31_2_MASK 0xfffffffcU +#define DSU4_ATBBA_BADDR_31_2_MASK 0xfffffffcU #define DSU4_ATBBA_BADDR_31_2_GET( _reg ) \ - ( ( ( _reg ) & DSU4_ATBBA_BADDR_31_2_MASK ) >> \ - DSU4_ATBBA_BADDR_31_2_SHIFT ) -#define DSU4_ATBBA_BADDR_31_2_SET( _reg, _val ) \ - ( ( ( _reg ) & ~DSU4_ATBBA_BADDR_31_2_MASK ) | \ + ( ( ( _reg ) & DSU4_ATBBA_BADDR_31_2_MASK ) >> DSU4_ATBBA_BADDR_31_2_SHIFT ) +#define DSU4_ATBBA_BADDR_31_2_SET( _reg, _val ) \ + ( ( ( _reg ) & ~DSU4_ATBBA_BADDR_31_2_MASK ) | \ ( ( ( _val ) << DSU4_ATBBA_BADDR_31_2_SHIFT ) & \ DSU4_ATBBA_BADDR_31_2_MASK ) ) #define DSU4_ATBBA_BADDR_31_2( _val ) \ - ( ( ( _val ) << DSU4_ATBBA_BADDR_31_2_SHIFT ) & \ - DSU4_ATBBA_BADDR_31_2_MASK ) + ( ( ( _val ) << DSU4_ATBBA_BADDR_31_2_SHIFT ) & DSU4_ATBBA_BADDR_31_2_MASK ) /** @} */ @@ -439,17 +397,15 @@ extern "C" { */ #define DSU4_ATBBM_BMASK_31_2_SHIFT 2 -#define DSU4_ATBBM_BMASK_31_2_MASK 0xfffffffcU +#define DSU4_ATBBM_BMASK_31_2_MASK 0xfffffffcU #define DSU4_ATBBM_BMASK_31_2_GET( _reg ) \ - ( ( ( _reg ) & DSU4_ATBBM_BMASK_31_2_MASK ) >> \ - DSU4_ATBBM_BMASK_31_2_SHIFT ) -#define DSU4_ATBBM_BMASK_31_2_SET( _reg, _val ) \ - ( ( ( _reg ) & ~DSU4_ATBBM_BMASK_31_2_MASK ) | \ + ( ( ( _reg ) & DSU4_ATBBM_BMASK_31_2_MASK ) >> DSU4_ATBBM_BMASK_31_2_SHIFT ) +#define DSU4_ATBBM_BMASK_31_2_SET( _reg, _val ) \ + ( ( ( _reg ) & ~DSU4_ATBBM_BMASK_31_2_MASK ) | \ ( ( ( _val ) << DSU4_ATBBM_BMASK_31_2_SHIFT ) & \ DSU4_ATBBM_BMASK_31_2_MASK ) ) #define DSU4_ATBBM_BMASK_31_2( _val ) \ - ( ( ( _val ) << DSU4_ATBBM_BMASK_31_2_SHIFT ) & \ - DSU4_ATBBM_BMASK_31_2_MASK ) + ( ( ( _val ) << DSU4_ATBBM_BMASK_31_2_SHIFT ) & DSU4_ATBBM_BMASK_31_2_MASK ) #define DSU4_ATBBM_LD 0x2U @@ -472,17 +428,15 @@ extern "C" { #define DSU4_ICNT_PE 0x20000000U #define DSU4_ICNT_ICOUNT_28_0_SHIFT 0 -#define DSU4_ICNT_ICOUNT_28_0_MASK 0x1fffffffU +#define DSU4_ICNT_ICOUNT_28_0_MASK 0x1fffffffU #define DSU4_ICNT_ICOUNT_28_0_GET( _reg ) \ - ( ( ( _reg ) & DSU4_ICNT_ICOUNT_28_0_MASK ) >> \ - DSU4_ICNT_ICOUNT_28_0_SHIFT ) -#define DSU4_ICNT_ICOUNT_28_0_SET( _reg, _val ) \ - ( ( ( _reg ) & ~DSU4_ICNT_ICOUNT_28_0_MASK ) | \ + ( ( ( _reg ) & DSU4_ICNT_ICOUNT_28_0_MASK ) >> DSU4_ICNT_ICOUNT_28_0_SHIFT ) +#define DSU4_ICNT_ICOUNT_28_0_SET( _reg, _val ) \ + ( ( ( _reg ) & ~DSU4_ICNT_ICOUNT_28_0_MASK ) | \ ( ( ( _val ) << DSU4_ICNT_ICOUNT_28_0_SHIFT ) & \ DSU4_ICNT_ICOUNT_28_0_MASK ) ) #define DSU4_ICNT_ICOUNT_28_0( _val ) \ - ( ( ( _val ) << DSU4_ICNT_ICOUNT_28_0_SHIFT ) & \ - DSU4_ICNT_ICOUNT_28_0_MASK ) + ( ( ( _val ) << DSU4_ICNT_ICOUNT_28_0_SHIFT ) & DSU4_ICNT_ICOUNT_28_0_MASK ) /** @} */ @@ -518,17 +472,14 @@ extern "C" { */ #define DSU4_AHBWPD_DATA_SHIFT 0 -#define DSU4_AHBWPD_DATA_MASK 0xffffffffU +#define DSU4_AHBWPD_DATA_MASK 0xffffffffU #define DSU4_AHBWPD_DATA_GET( _reg ) \ - ( ( ( _reg ) & DSU4_AHBWPD_DATA_MASK ) >> \ - DSU4_AHBWPD_DATA_SHIFT ) -#define DSU4_AHBWPD_DATA_SET( _reg, _val ) \ + ( ( ( _reg ) & DSU4_AHBWPD_DATA_MASK ) >> DSU4_AHBWPD_DATA_SHIFT ) +#define DSU4_AHBWPD_DATA_SET( _reg, _val ) \ ( ( ( _reg ) & ~DSU4_AHBWPD_DATA_MASK ) | \ - ( ( ( _val ) << DSU4_AHBWPD_DATA_SHIFT ) & \ - DSU4_AHBWPD_DATA_MASK ) ) + ( ( ( _val ) << DSU4_AHBWPD_DATA_SHIFT ) & DSU4_AHBWPD_DATA_MASK ) ) #define DSU4_AHBWPD_DATA( _val ) \ - ( ( ( _val ) << DSU4_AHBWPD_DATA_SHIFT ) & \ - DSU4_AHBWPD_DATA_MASK ) + ( ( ( _val ) << DSU4_AHBWPD_DATA_SHIFT ) & DSU4_AHBWPD_DATA_MASK ) /** @} */ @@ -541,17 +492,14 @@ extern "C" { */ #define DSU4_AHBWPM_MASK_SHIFT 0 -#define DSU4_AHBWPM_MASK_MASK 0xffffffffU +#define DSU4_AHBWPM_MASK_MASK 0xffffffffU #define DSU4_AHBWPM_MASK_GET( _reg ) \ - ( ( ( _reg ) & DSU4_AHBWPM_MASK_MASK ) >> \ - DSU4_AHBWPM_MASK_SHIFT ) -#define DSU4_AHBWPM_MASK_SET( _reg, _val ) \ + ( ( ( _reg ) & DSU4_AHBWPM_MASK_MASK ) >> DSU4_AHBWPM_MASK_SHIFT ) +#define DSU4_AHBWPM_MASK_SET( _reg, _val ) \ ( ( ( _reg ) & ~DSU4_AHBWPM_MASK_MASK ) | \ - ( ( ( _val ) << DSU4_AHBWPM_MASK_SHIFT ) & \ - DSU4_AHBWPM_MASK_MASK ) ) + ( ( ( _val ) << DSU4_AHBWPM_MASK_SHIFT ) & DSU4_AHBWPM_MASK_MASK ) ) #define DSU4_AHBWPM_MASK( _val ) \ - ( ( ( _val ) << DSU4_AHBWPM_MASK_SHIFT ) & \ - DSU4_AHBWPM_MASK_MASK ) + ( ( ( _val ) << DSU4_AHBWPM_MASK_SHIFT ) & DSU4_AHBWPM_MASK_MASK ) /** @} */ @@ -565,30 +513,25 @@ extern "C" { */ #define DSU4_ITBC0_TFILT_SHIFT 28 -#define DSU4_ITBC0_TFILT_MASK 0xf0000000U +#define DSU4_ITBC0_TFILT_MASK 0xf0000000U #define DSU4_ITBC0_TFILT_GET( _reg ) \ - ( ( ( _reg ) & DSU4_ITBC0_TFILT_MASK ) >> \ - DSU4_ITBC0_TFILT_SHIFT ) -#define DSU4_ITBC0_TFILT_SET( _reg, _val ) \ + ( ( ( _reg ) & DSU4_ITBC0_TFILT_MASK ) >> DSU4_ITBC0_TFILT_SHIFT ) +#define DSU4_ITBC0_TFILT_SET( _reg, _val ) \ ( ( ( _reg ) & ~DSU4_ITBC0_TFILT_MASK ) | \ - ( ( ( _val ) << DSU4_ITBC0_TFILT_SHIFT ) & \ - DSU4_ITBC0_TFILT_MASK ) ) + ( ( ( _val ) << DSU4_ITBC0_TFILT_SHIFT ) & DSU4_ITBC0_TFILT_MASK ) ) #define DSU4_ITBC0_TFILT( _val ) \ - ( ( ( _val ) << DSU4_ITBC0_TFILT_SHIFT ) & \ - DSU4_ITBC0_TFILT_MASK ) + ( ( ( _val ) << DSU4_ITBC0_TFILT_SHIFT ) & DSU4_ITBC0_TFILT_MASK ) #define DSU4_ITBC0_ITPOINTER_SHIFT 0 -#define DSU4_ITBC0_ITPOINTER_MASK 0xffffU +#define DSU4_ITBC0_ITPOINTER_MASK 0xffffU #define DSU4_ITBC0_ITPOINTER_GET( _reg ) \ - ( ( ( _reg ) & DSU4_ITBC0_ITPOINTER_MASK ) >> \ - DSU4_ITBC0_ITPOINTER_SHIFT ) -#define DSU4_ITBC0_ITPOINTER_SET( _reg, _val ) \ - ( ( ( _reg ) & ~DSU4_ITBC0_ITPOINTER_MASK ) | \ + ( ( ( _reg ) & DSU4_ITBC0_ITPOINTER_MASK ) >> DSU4_ITBC0_ITPOINTER_SHIFT ) +#define DSU4_ITBC0_ITPOINTER_SET( _reg, _val ) \ + ( ( ( _reg ) & ~DSU4_ITBC0_ITPOINTER_MASK ) | \ ( ( ( _val ) << DSU4_ITBC0_ITPOINTER_SHIFT ) & \ DSU4_ITBC0_ITPOINTER_MASK ) ) #define DSU4_ITBC0_ITPOINTER( _val ) \ - ( ( ( _val ) << DSU4_ITBC0_ITPOINTER_SHIFT ) & \ - DSU4_ITBC0_ITPOINTER_MASK ) + ( ( ( _val ) << DSU4_ITBC0_ITPOINTER_SHIFT ) & DSU4_ITBC0_ITPOINTER_MASK ) /** @} */ @@ -604,17 +547,14 @@ extern "C" { #define DSU4_ITBC1_WO 0x8000000U #define DSU4_ITBC1_TLIM_SHIFT 24 -#define DSU4_ITBC1_TLIM_MASK 0x7000000U +#define DSU4_ITBC1_TLIM_MASK 0x7000000U #define DSU4_ITBC1_TLIM_GET( _reg ) \ - ( ( ( _reg ) & DSU4_ITBC1_TLIM_MASK ) >> \ - DSU4_ITBC1_TLIM_SHIFT ) -#define DSU4_ITBC1_TLIM_SET( _reg, _val ) \ + ( ( ( _reg ) & DSU4_ITBC1_TLIM_MASK ) >> DSU4_ITBC1_TLIM_SHIFT ) +#define DSU4_ITBC1_TLIM_SET( _reg, _val ) \ ( ( ( _reg ) & ~DSU4_ITBC1_TLIM_MASK ) | \ - ( ( ( _val ) << DSU4_ITBC1_TLIM_SHIFT ) & \ - DSU4_ITBC1_TLIM_MASK ) ) + ( ( ( _val ) << DSU4_ITBC1_TLIM_SHIFT ) & DSU4_ITBC1_TLIM_MASK ) ) #define DSU4_ITBC1_TLIM( _val ) \ - ( ( ( _val ) << DSU4_ITBC1_TLIM_SHIFT ) & \ - DSU4_ITBC1_TLIM_MASK ) + ( ( ( _val ) << DSU4_ITBC1_TLIM_SHIFT ) & DSU4_ITBC1_TLIM_MASK ) #define DSU4_ITBC1_TOV 0x800000U diff --git a/bsps/include/grlib/ftmctrl-regs.h b/bsps/include/grlib/ftmctrl-regs.h index fb4203270c..fc98548fcf 100644 --- a/bsps/include/grlib/ftmctrl-regs.h +++ b/bsps/include/grlib/ftmctrl-regs.h @@ -87,32 +87,30 @@ extern "C" { #define FTMCTRL_MCFG1_ABRDY 0x20000000U #define FTMCTRL_MCFG1_IOBUSW_SHIFT 27 -#define FTMCTRL_MCFG1_IOBUSW_MASK 0x18000000U +#define FTMCTRL_MCFG1_IOBUSW_MASK 0x18000000U #define FTMCTRL_MCFG1_IOBUSW_GET( _reg ) \ - ( ( ( _reg ) & FTMCTRL_MCFG1_IOBUSW_MASK ) >> \ - FTMCTRL_MCFG1_IOBUSW_SHIFT ) -#define FTMCTRL_MCFG1_IOBUSW_SET( _reg, _val ) \ - ( ( ( _reg ) & ~FTMCTRL_MCFG1_IOBUSW_MASK ) | \ + ( ( ( _reg ) & FTMCTRL_MCFG1_IOBUSW_MASK ) >> FTMCTRL_MCFG1_IOBUSW_SHIFT ) +#define FTMCTRL_MCFG1_IOBUSW_SET( _reg, _val ) \ + ( ( ( _reg ) & ~FTMCTRL_MCFG1_IOBUSW_MASK ) | \ ( ( ( _val ) << FTMCTRL_MCFG1_IOBUSW_SHIFT ) & \ FTMCTRL_MCFG1_IOBUSW_MASK ) ) #define FTMCTRL_MCFG1_IOBUSW( _val ) \ - ( ( ( _val ) << FTMCTRL_MCFG1_IOBUSW_SHIFT ) & \ - FTMCTRL_MCFG1_IOBUSW_MASK ) + ( ( ( _val ) << FTMCTRL_MCFG1_IOBUSW_SHIFT ) & FTMCTRL_MCFG1_IOBUSW_MASK ) #define FTMCTRL_MCFG1_IBRDY 0x4000000U #define FTMCTRL_MCFG1_BEXCN 0x2000000U #define FTMCTRL_MCFG1_IO_WAITSTATES_SHIFT 20 -#define FTMCTRL_MCFG1_IO_WAITSTATES_MASK 0xf00000U -#define FTMCTRL_MCFG1_IO_WAITSTATES_GET( _reg ) \ +#define FTMCTRL_MCFG1_IO_WAITSTATES_MASK 0xf00000U +#define FTMCTRL_MCFG1_IO_WAITSTATES_GET( _reg ) \ ( ( ( _reg ) & FTMCTRL_MCFG1_IO_WAITSTATES_MASK ) >> \ FTMCTRL_MCFG1_IO_WAITSTATES_SHIFT ) -#define FTMCTRL_MCFG1_IO_WAITSTATES_SET( _reg, _val ) \ - ( ( ( _reg ) & ~FTMCTRL_MCFG1_IO_WAITSTATES_MASK ) | \ +#define FTMCTRL_MCFG1_IO_WAITSTATES_SET( _reg, _val ) \ + ( ( ( _reg ) & ~FTMCTRL_MCFG1_IO_WAITSTATES_MASK ) | \ ( ( ( _val ) << FTMCTRL_MCFG1_IO_WAITSTATES_SHIFT ) & \ FTMCTRL_MCFG1_IO_WAITSTATES_MASK ) ) -#define FTMCTRL_MCFG1_IO_WAITSTATES( _val ) \ +#define FTMCTRL_MCFG1_IO_WAITSTATES( _val ) \ ( ( ( _val ) << FTMCTRL_MCFG1_IO_WAITSTATES_SHIFT ) & \ FTMCTRL_MCFG1_IO_WAITSTATES_MASK ) @@ -121,56 +119,56 @@ extern "C" { #define FTMCTRL_MCFG1_R 0x40000U #define FTMCTRL_MCFG1_ROMBANKSZ_SHIFT 14 -#define FTMCTRL_MCFG1_ROMBANKSZ_MASK 0x3c000U -#define FTMCTRL_MCFG1_ROMBANKSZ_GET( _reg ) \ +#define FTMCTRL_MCFG1_ROMBANKSZ_MASK 0x3c000U +#define FTMCTRL_MCFG1_ROMBANKSZ_GET( _reg ) \ ( ( ( _reg ) & FTMCTRL_MCFG1_ROMBANKSZ_MASK ) >> \ FTMCTRL_MCFG1_ROMBANKSZ_SHIFT ) -#define FTMCTRL_MCFG1_ROMBANKSZ_SET( _reg, _val ) \ - ( ( ( _reg ) & ~FTMCTRL_MCFG1_ROMBANKSZ_MASK ) | \ +#define FTMCTRL_MCFG1_ROMBANKSZ_SET( _reg, _val ) \ + ( ( ( _reg ) & ~FTMCTRL_MCFG1_ROMBANKSZ_MASK ) | \ ( ( ( _val ) << FTMCTRL_MCFG1_ROMBANKSZ_SHIFT ) & \ FTMCTRL_MCFG1_ROMBANKSZ_MASK ) ) -#define FTMCTRL_MCFG1_ROMBANKSZ( _val ) \ +#define FTMCTRL_MCFG1_ROMBANKSZ( _val ) \ ( ( ( _val ) << FTMCTRL_MCFG1_ROMBANKSZ_SHIFT ) & \ FTMCTRL_MCFG1_ROMBANKSZ_MASK ) #define FTMCTRL_MCFG1_PWEN 0x800U #define FTMCTRL_MCFG1_PROM_WIDTH_SHIFT 8 -#define FTMCTRL_MCFG1_PROM_WIDTH_MASK 0x300U -#define FTMCTRL_MCFG1_PROM_WIDTH_GET( _reg ) \ +#define FTMCTRL_MCFG1_PROM_WIDTH_MASK 0x300U +#define FTMCTRL_MCFG1_PROM_WIDTH_GET( _reg ) \ ( ( ( _reg ) & FTMCTRL_MCFG1_PROM_WIDTH_MASK ) >> \ FTMCTRL_MCFG1_PROM_WIDTH_SHIFT ) -#define FTMCTRL_MCFG1_PROM_WIDTH_SET( _reg, _val ) \ - ( ( ( _reg ) & ~FTMCTRL_MCFG1_PROM_WIDTH_MASK ) | \ +#define FTMCTRL_MCFG1_PROM_WIDTH_SET( _reg, _val ) \ + ( ( ( _reg ) & ~FTMCTRL_MCFG1_PROM_WIDTH_MASK ) | \ ( ( ( _val ) << FTMCTRL_MCFG1_PROM_WIDTH_SHIFT ) & \ FTMCTRL_MCFG1_PROM_WIDTH_MASK ) ) -#define FTMCTRL_MCFG1_PROM_WIDTH( _val ) \ +#define FTMCTRL_MCFG1_PROM_WIDTH( _val ) \ ( ( ( _val ) << FTMCTRL_MCFG1_PROM_WIDTH_SHIFT ) & \ FTMCTRL_MCFG1_PROM_WIDTH_MASK ) #define FTMCTRL_MCFG1_PROM_WRITE_WS_SHIFT 4 -#define FTMCTRL_MCFG1_PROM_WRITE_WS_MASK 0xf0U -#define FTMCTRL_MCFG1_PROM_WRITE_WS_GET( _reg ) \ +#define FTMCTRL_MCFG1_PROM_WRITE_WS_MASK 0xf0U +#define FTMCTRL_MCFG1_PROM_WRITE_WS_GET( _reg ) \ ( ( ( _reg ) & FTMCTRL_MCFG1_PROM_WRITE_WS_MASK ) >> \ FTMCTRL_MCFG1_PROM_WRITE_WS_SHIFT ) -#define FTMCTRL_MCFG1_PROM_WRITE_WS_SET( _reg, _val ) \ - ( ( ( _reg ) & ~FTMCTRL_MCFG1_PROM_WRITE_WS_MASK ) | \ +#define FTMCTRL_MCFG1_PROM_WRITE_WS_SET( _reg, _val ) \ + ( ( ( _reg ) & ~FTMCTRL_MCFG1_PROM_WRITE_WS_MASK ) | \ ( ( ( _val ) << FTMCTRL_MCFG1_PROM_WRITE_WS_SHIFT ) & \ FTMCTRL_MCFG1_PROM_WRITE_WS_MASK ) ) -#define FTMCTRL_MCFG1_PROM_WRITE_WS( _val ) \ +#define FTMCTRL_MCFG1_PROM_WRITE_WS( _val ) \ ( ( ( _val ) << FTMCTRL_MCFG1_PROM_WRITE_WS_SHIFT ) & \ FTMCTRL_MCFG1_PROM_WRITE_WS_MASK ) #define FTMCTRL_MCFG1_PROM_READ_WS_SHIFT 0 -#define FTMCTRL_MCFG1_PROM_READ_WS_MASK 0xfU -#define FTMCTRL_MCFG1_PROM_READ_WS_GET( _reg ) \ +#define FTMCTRL_MCFG1_PROM_READ_WS_MASK 0xfU +#define FTMCTRL_MCFG1_PROM_READ_WS_GET( _reg ) \ ( ( ( _reg ) & FTMCTRL_MCFG1_PROM_READ_WS_MASK ) >> \ FTMCTRL_MCFG1_PROM_READ_WS_SHIFT ) -#define FTMCTRL_MCFG1_PROM_READ_WS_SET( _reg, _val ) \ - ( ( ( _reg ) & ~FTMCTRL_MCFG1_PROM_READ_WS_MASK ) | \ +#define FTMCTRL_MCFG1_PROM_READ_WS_SET( _reg, _val ) \ + ( ( ( _reg ) & ~FTMCTRL_MCFG1_PROM_READ_WS_MASK ) | \ ( ( ( _val ) << FTMCTRL_MCFG1_PROM_READ_WS_SHIFT ) & \ FTMCTRL_MCFG1_PROM_READ_WS_MASK ) ) -#define FTMCTRL_MCFG1_PROM_READ_WS( _val ) \ +#define FTMCTRL_MCFG1_PROM_READ_WS( _val ) \ ( ( ( _val ) << FTMCTRL_MCFG1_PROM_READ_WS_SHIFT ) & \ FTMCTRL_MCFG1_PROM_READ_WS_MASK ) @@ -194,17 +192,14 @@ extern "C" { #define FTMCTRL_MCFG3_PE 0x100U #define FTMCTRL_MCFG3_TCB_SHIFT 0 -#define FTMCTRL_MCFG3_TCB_MASK 0xffU +#define FTMCTRL_MCFG3_TCB_MASK 0xffU #define FTMCTRL_MCFG3_TCB_GET( _reg ) \ - ( ( ( _reg ) & FTMCTRL_MCFG3_TCB_MASK ) >> \ - FTMCTRL_MCFG3_TCB_SHIFT ) -#define FTMCTRL_MCFG3_TCB_SET( _reg, _val ) \ + ( ( ( _reg ) & FTMCTRL_MCFG3_TCB_MASK ) >> FTMCTRL_MCFG3_TCB_SHIFT ) +#define FTMCTRL_MCFG3_TCB_SET( _reg, _val ) \ ( ( ( _reg ) & ~FTMCTRL_MCFG3_TCB_MASK ) | \ - ( ( ( _val ) << FTMCTRL_MCFG3_TCB_SHIFT ) & \ - FTMCTRL_MCFG3_TCB_MASK ) ) + ( ( ( _val ) << FTMCTRL_MCFG3_TCB_SHIFT ) & FTMCTRL_MCFG3_TCB_MASK ) ) #define FTMCTRL_MCFG3_TCB( _val ) \ - ( ( ( _val ) << FTMCTRL_MCFG3_TCB_SHIFT ) & \ - FTMCTRL_MCFG3_TCB_MASK ) + ( ( ( _val ) << FTMCTRL_MCFG3_TCB_SHIFT ) & FTMCTRL_MCFG3_TCB_MASK ) /** @} */ @@ -218,30 +213,26 @@ extern "C" { */ #define FTMCTRL_MCFG5_IOHWS_SHIFT 23 -#define FTMCTRL_MCFG5_IOHWS_MASK 0x3f800000U +#define FTMCTRL_MCFG5_IOHWS_MASK 0x3f800000U #define FTMCTRL_MCFG5_IOHWS_GET( _reg ) \ - ( ( ( _reg ) & FTMCTRL_MCFG5_IOHWS_MASK ) >> \ - FTMCTRL_MCFG5_IOHWS_SHIFT ) -#define FTMCTRL_MCFG5_IOHWS_SET( _reg, _val ) \ - ( ( ( _reg ) & ~FTMCTRL_MCFG5_IOHWS_MASK ) | \ + ( ( ( _reg ) & FTMCTRL_MCFG5_IOHWS_MASK ) >> FTMCTRL_MCFG5_IOHWS_SHIFT ) +#define FTMCTRL_MCFG5_IOHWS_SET( _reg, _val ) \ + ( ( ( _reg ) & ~FTMCTRL_MCFG5_IOHWS_MASK ) | \ ( ( ( _val ) << FTMCTRL_MCFG5_IOHWS_SHIFT ) & \ FTMCTRL_MCFG5_IOHWS_MASK ) ) #define FTMCTRL_MCFG5_IOHWS( _val ) \ - ( ( ( _val ) << FTMCTRL_MCFG5_IOHWS_SHIFT ) & \ - FTMCTRL_MCFG5_IOHWS_MASK ) + ( ( ( _val ) << FTMCTRL_MCFG5_IOHWS_SHIFT ) & FTMCTRL_MCFG5_IOHWS_MASK ) #define FTMCTRL_MCFG5_ROMHWS_SHIFT 7 -#define FTMCTRL_MCFG5_ROMHWS_MASK 0x3f80U +#define FTMCTRL_MCFG5_ROMHWS_MASK 0x3f80U #define FTMCTRL_MCFG5_ROMHWS_GET( _reg ) \ - ( ( ( _reg ) & FTMCTRL_MCFG5_ROMHWS_MASK ) >> \ - FTMCTRL_MCFG5_ROMHWS_SHIFT ) -#define FTMCTRL_MCFG5_ROMHWS_SET( _reg, _val ) \ - ( ( ( _reg ) & ~FTMCTRL_MCFG5_ROMHWS_MASK ) | \ + ( ( ( _reg ) & FTMCTRL_MCFG5_ROMHWS_MASK ) >> FTMCTRL_MCFG5_ROMHWS_SHIFT ) +#define FTMCTRL_MCFG5_ROMHWS_SET( _reg, _val ) \ + ( ( ( _reg ) & ~FTMCTRL_MCFG5_ROMHWS_MASK ) | \ ( ( ( _val ) << FTMCTRL_MCFG5_ROMHWS_SHIFT ) & \ FTMCTRL_MCFG5_ROMHWS_MASK ) ) #define FTMCTRL_MCFG5_ROMHWS( _val ) \ - ( ( ( _val ) << FTMCTRL_MCFG5_ROMHWS_SHIFT ) & \ - FTMCTRL_MCFG5_ROMHWS_MASK ) + ( ( ( _val ) << FTMCTRL_MCFG5_ROMHWS_SHIFT ) & FTMCTRL_MCFG5_ROMHWS_MASK ) /** @} */ @@ -255,28 +246,28 @@ extern "C" { */ #define FTMCTRL_MCFG7_BRDYNCNT_SHIFT 16 -#define FTMCTRL_MCFG7_BRDYNCNT_MASK 0xffff0000U -#define FTMCTRL_MCFG7_BRDYNCNT_GET( _reg ) \ +#define FTMCTRL_MCFG7_BRDYNCNT_MASK 0xffff0000U +#define FTMCTRL_MCFG7_BRDYNCNT_GET( _reg ) \ ( ( ( _reg ) & FTMCTRL_MCFG7_BRDYNCNT_MASK ) >> \ FTMCTRL_MCFG7_BRDYNCNT_SHIFT ) -#define FTMCTRL_MCFG7_BRDYNCNT_SET( _reg, _val ) \ - ( ( ( _reg ) & ~FTMCTRL_MCFG7_BRDYNCNT_MASK ) | \ +#define FTMCTRL_MCFG7_BRDYNCNT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~FTMCTRL_MCFG7_BRDYNCNT_MASK ) | \ ( ( ( _val ) << FTMCTRL_MCFG7_BRDYNCNT_SHIFT ) & \ FTMCTRL_MCFG7_BRDYNCNT_MASK ) ) -#define FTMCTRL_MCFG7_BRDYNCNT( _val ) \ +#define FTMCTRL_MCFG7_BRDYNCNT( _val ) \ ( ( ( _val ) << FTMCTRL_MCFG7_BRDYNCNT_SHIFT ) & \ FTMCTRL_MCFG7_BRDYNCNT_MASK ) #define FTMCTRL_MCFG7_BRDYNRLD_SHIFT 0 -#define FTMCTRL_MCFG7_BRDYNRLD_MASK 0xffffU -#define FTMCTRL_MCFG7_BRDYNRLD_GET( _reg ) \ +#define FTMCTRL_MCFG7_BRDYNRLD_MASK 0xffffU +#define FTMCTRL_MCFG7_BRDYNRLD_GET( _reg ) \ ( ( ( _reg ) & FTMCTRL_MCFG7_BRDYNRLD_MASK ) >> \ FTMCTRL_MCFG7_BRDYNRLD_SHIFT ) -#define FTMCTRL_MCFG7_BRDYNRLD_SET( _reg, _val ) \ - ( ( ( _reg ) & ~FTMCTRL_MCFG7_BRDYNRLD_MASK ) | \ +#define FTMCTRL_MCFG7_BRDYNRLD_SET( _reg, _val ) \ + ( ( ( _reg ) & ~FTMCTRL_MCFG7_BRDYNRLD_MASK ) | \ ( ( ( _val ) << FTMCTRL_MCFG7_BRDYNRLD_SHIFT ) & \ FTMCTRL_MCFG7_BRDYNRLD_MASK ) ) -#define FTMCTRL_MCFG7_BRDYNRLD( _val ) \ +#define FTMCTRL_MCFG7_BRDYNRLD( _val ) \ ( ( ( _val ) << FTMCTRL_MCFG7_BRDYNRLD_SHIFT ) & \ FTMCTRL_MCFG7_BRDYNRLD_MASK ) diff --git a/bsps/include/grlib/genirq.h b/bsps/include/grlib/genirq.h index 3c99b5a704..be56384cb9 100644 --- a/bsps/include/grlib/genirq.h +++ b/bsps/include/grlib/genirq.h @@ -39,11 +39,11 @@ extern "C" { #endif -typedef void (*genirq_handler)(void *arg); -typedef void* genirq_t; +typedef void ( *genirq_handler )( void *arg ); +typedef void *genirq_t; struct genirq_stats { - unsigned int irq_cnt; + unsigned int irq_cnt; }; /* Initialize the genirq interface. Must be the first function @@ -51,20 +51,20 @@ struct genirq_stats { * * Returns zero on success, otherwise failure. */ -extern genirq_t genirq_init(int number_of_irqs); +extern genirq_t genirq_init( int number_of_irqs ); /* Free the dynamically allocated memory that the genirq interface has * allocated. Also the handlers will be freed. * * Returns zero on success, otherwise failure. */ -extern void genirq_destroy(genirq_t d); +extern void genirq_destroy( genirq_t d ); /* Check IRQ number validity * * Returns zero for valid IRQ numbers, -1 of invalid IRQ numbers. */ -extern int genirq_check(genirq_t d, int irq); +extern int genirq_check( genirq_t d, int irq ); /* Allocate one ISR handler and initialize it. Input to genirq_register(). * @@ -73,10 +73,10 @@ extern int genirq_check(genirq_t d, int irq); * * Returns a pointer on success, on failure NULL is returned. */ -extern void *genirq_alloc_handler(genirq_handler isr, void *arg); +extern void *genirq_alloc_handler( genirq_handler isr, void *arg ); /* Free handler memory */ -#define genirq_free_handler(handler) free(handler) +#define genirq_free_handler( handler ) free( handler ) /* Register shared interrupt handler previously initialized with * genirq_alloc_handler(). @@ -92,7 +92,7 @@ extern void *genirq_alloc_handler(genirq_handler isr, void *arg); * 0 = Handler registered Successfully, first handler on this IRQ * 1 = Handler registered Successfully, _not_ first handler on this IRQ */ -extern int genirq_register(genirq_t d, int irq, void *handler); +extern int genirq_register( genirq_t d, int irq, void *handler ); /* Unregister an previous registered interrupt handler. It is the user's * responsibility to free the handler returned by genirq_unregister(). @@ -105,8 +105,12 @@ extern int genirq_register(genirq_t d, int irq, void *handler); * Pointer = ISR sucessfully unregistered. Returned is the handler pointer * previously allocated with genirq_alloc_handler(). */ -extern void *genirq_unregister(genirq_t d, int irq, - genirq_handler isr, void *arg); +extern void *genirq_unregister( + genirq_t d, + int irq, + genirq_handler isr, + void *arg +); /* Enables IRQ only for this isr[arg] combination. Records if this * is the first interrupt enable, only then must interrupts be enabled @@ -120,7 +124,7 @@ extern void *genirq_unregister(genirq_t d, int irq, * 0 = IRQ must be enabled, it is the first IRQ handler to be enabled * 1 = IRQ has already been enabled, either by isr[arg] or by another handler */ -extern int genirq_enable(genirq_t d, int irq, genirq_handler isr, void *arg); +extern int genirq_enable( genirq_t d, int irq, genirq_handler isr, void *arg ); /* Disables IRQ only for this isr[arg] combination. Records if this * is the only interrupt handler that is enabled on this IRQ, only then @@ -134,7 +138,12 @@ extern int genirq_enable(genirq_t d, int irq, genirq_handler isr, void *arg); * 0 = IRQ must be disabled, no ISR are enabled for this IRQ * 1 = ISR has already been disabled, or other ISRs are still enabled */ -extern int genirq_disable(genirq_t d, int irq, genirq_handler isr, void *arg); +extern int genirq_disable( + genirq_t d, + int irq, + genirq_handler isr, + void *arg +); /* Must be called by user when an IRQ has fired, the argument 'irq' * is the IRQ number of the IRQ which was fired. @@ -142,7 +151,7 @@ extern int genirq_disable(genirq_t d, int irq, genirq_handler isr, void *arg); * NOTE: internal list structures are accessed and needs to be protected by * spin-locks/IRQ disable by the user to guarantee a correct behaviour. */ -extern void genirq_doirq(genirq_t d, int irq); +extern void genirq_doirq( genirq_t d, int irq ); #ifdef __cplusplus } diff --git a/bsps/include/grlib/gpiolib.h b/bsps/include/grlib/gpiolib.h index c0f865fff2..85e76cbdf2 100644 --- a/bsps/include/grlib/gpiolib.h +++ b/bsps/include/grlib/gpiolib.h @@ -36,25 +36,25 @@ extern "C" { /* GPIO Config of one GPIO port */ struct gpiolib_config { - char mask; /* 0=Masked/1=Unmasked IRQ */ - char irq_level; /* Edge or Level triggered IRQ */ - char irq_polarity; /* Polarity of IRQ */ + char mask; /* 0=Masked/1=Unmasked IRQ */ + char irq_level; /* Edge or Level triggered IRQ */ + char irq_polarity; /* Polarity of IRQ */ }; -#define GPIOLIB_IRQ_EDGE 0 +#define GPIOLIB_IRQ_EDGE 0 #define GPIOLIB_IRQ_LEVEL 1 -#define GPIOLIB_IRQ_POL_LOW 0 +#define GPIOLIB_IRQ_POL_LOW 0 #define GPIOLIB_IRQ_POL_HIGH 1 /* Libarary initialize function must be called befor any other */ -extern int gpiolib_initialize(void); +extern int gpiolib_initialize( void ); /*** User Interface ***/ -extern void *gpiolib_open(int port); -extern void *gpiolib_open_by_name(char *devName); -extern void gpiolib_close(void *handle); +extern void *gpiolib_open( int port ); +extern void *gpiolib_open_by_name( char *devName ); +extern void gpiolib_close( void *handle ); /* Show the current status one or all GPIO ports in the system. * Int port is port nunber, if port = -1 selects all ports. @@ -62,34 +62,34 @@ extern void gpiolib_close(void *handle); * If port != -1, handle is used to get port. * If port != -1, handle == NULL, then port is used as port number */ -extern void gpiolib_show(int port, void *handle); +extern void gpiolib_show( int port, void *handle ); -extern int gpiolib_set_config(void *handle, struct gpiolib_config *cfg); -extern int gpiolib_set(void *handle, int dir, int val); -extern int gpiolib_get(void *handle, int *inval); -extern int gpiolib_irq_clear(void *handle); -extern int gpiolib_irq_enable(void *handle); -extern int gpiolib_irq_disable(void *handle); -extern int gpiolib_irq_mask(void *handle); -extern int gpiolib_irq_unmask(void *handle); -extern int gpiolib_irq_force(void *handle); -extern int gpiolib_irq_register(void *handle, void *func, void *arg); +extern int gpiolib_set_config( void *handle, struct gpiolib_config *cfg ); +extern int gpiolib_set( void *handle, int dir, int val ); +extern int gpiolib_get( void *handle, int *inval ); +extern int gpiolib_irq_clear( void *handle ); +extern int gpiolib_irq_enable( void *handle ); +extern int gpiolib_irq_disable( void *handle ); +extern int gpiolib_irq_mask( void *handle ); +extern int gpiolib_irq_unmask( void *handle ); +extern int gpiolib_irq_force( void *handle ); +extern int gpiolib_irq_register( void *handle, void *func, void *arg ); /*** Driver Interface ***/ struct gpiolib_info { - char devName[80]; + char devName[ 80 ]; }; struct gpiolib_drv_ops { - int (*config)(void *handle, struct gpiolib_config *cfg); - int (*get)(void *handle, int *val); - int (*irq_opts)(void *handle, unsigned int options); - int (*irq_register)(void *handle, void *func, void *arg); - int (*open)(void *handle); - int (*set)(void *handle, int dir, int outval); - int (*show)(void *handle); - int (*get_info)(void *handle, struct gpiolib_info *pinfo); + int ( *config )( void *handle, struct gpiolib_config *cfg ); + int ( *get )( void *handle, int *val ); + int ( *irq_opts )( void *handle, unsigned int options ); + int ( *irq_register )( void *handle, void *func, void *arg ); + int ( *open )( void *handle ); + int ( *set )( void *handle, int dir, int outval ); + int ( *show )( void *handle ); + int ( *get_info )( void *handle, struct gpiolib_info *pinfo ); }; #define GPIOLIB_IRQ_ENABLE 0x01 @@ -100,11 +100,11 @@ struct gpiolib_drv_ops { #define GPIOLIB_IRQ_UNMASK 0x20 struct gpiolib_drv { - struct gpiolib_drv_ops *ops; + struct gpiolib_drv_ops *ops; }; /* Register a GPIO port */ -extern int gpiolib_drv_register(struct gpiolib_drv *drv, void *handle); +extern int gpiolib_drv_register( struct gpiolib_drv *drv, void *handle ); #ifdef __cplusplus } diff --git a/bsps/include/grlib/gptimer-regs.h b/bsps/include/grlib/gptimer-regs.h index f71343a442..7fa3ee87f2 100644 --- a/bsps/include/grlib/gptimer-regs.h +++ b/bsps/include/grlib/gptimer-regs.h @@ -93,17 +93,15 @@ extern "C" { */ #define GPTIMER_TCNTVAL_TCVAL_SHIFT 0 -#define GPTIMER_TCNTVAL_TCVAL_MASK 0xffffffffU +#define GPTIMER_TCNTVAL_TCVAL_MASK 0xffffffffU #define GPTIMER_TCNTVAL_TCVAL_GET( _reg ) \ - ( ( ( _reg ) & GPTIMER_TCNTVAL_TCVAL_MASK ) >> \ - GPTIMER_TCNTVAL_TCVAL_SHIFT ) -#define GPTIMER_TCNTVAL_TCVAL_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GPTIMER_TCNTVAL_TCVAL_MASK ) | \ + ( ( ( _reg ) & GPTIMER_TCNTVAL_TCVAL_MASK ) >> GPTIMER_TCNTVAL_TCVAL_SHIFT ) +#define GPTIMER_TCNTVAL_TCVAL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GPTIMER_TCNTVAL_TCVAL_MASK ) | \ ( ( ( _val ) << GPTIMER_TCNTVAL_TCVAL_SHIFT ) & \ GPTIMER_TCNTVAL_TCVAL_MASK ) ) #define GPTIMER_TCNTVAL_TCVAL( _val ) \ - ( ( ( _val ) << GPTIMER_TCNTVAL_TCVAL_SHIFT ) & \ - GPTIMER_TCNTVAL_TCVAL_MASK ) + ( ( ( _val ) << GPTIMER_TCNTVAL_TCVAL_SHIFT ) & GPTIMER_TCNTVAL_TCVAL_MASK ) /** @} */ @@ -117,15 +115,15 @@ extern "C" { */ #define GPTIMER_TRLDVAL_TRLDVAL_SHIFT 0 -#define GPTIMER_TRLDVAL_TRLDVAL_MASK 0xffffffffU -#define GPTIMER_TRLDVAL_TRLDVAL_GET( _reg ) \ +#define GPTIMER_TRLDVAL_TRLDVAL_MASK 0xffffffffU +#define GPTIMER_TRLDVAL_TRLDVAL_GET( _reg ) \ ( ( ( _reg ) & GPTIMER_TRLDVAL_TRLDVAL_MASK ) >> \ GPTIMER_TRLDVAL_TRLDVAL_SHIFT ) -#define GPTIMER_TRLDVAL_TRLDVAL_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GPTIMER_TRLDVAL_TRLDVAL_MASK ) | \ +#define GPTIMER_TRLDVAL_TRLDVAL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GPTIMER_TRLDVAL_TRLDVAL_MASK ) | \ ( ( ( _val ) << GPTIMER_TRLDVAL_TRLDVAL_SHIFT ) & \ GPTIMER_TRLDVAL_TRLDVAL_MASK ) ) -#define GPTIMER_TRLDVAL_TRLDVAL( _val ) \ +#define GPTIMER_TRLDVAL_TRLDVAL( _val ) \ ( ( ( _val ) << GPTIMER_TRLDVAL_TRLDVAL_SHIFT ) & \ GPTIMER_TRLDVAL_TRLDVAL_MASK ) @@ -168,17 +166,15 @@ extern "C" { */ #define GPTIMER_TLATCH_LTCV_SHIFT 0 -#define GPTIMER_TLATCH_LTCV_MASK 0xffffffffU +#define GPTIMER_TLATCH_LTCV_MASK 0xffffffffU #define GPTIMER_TLATCH_LTCV_GET( _reg ) \ - ( ( ( _reg ) & GPTIMER_TLATCH_LTCV_MASK ) >> \ - GPTIMER_TLATCH_LTCV_SHIFT ) -#define GPTIMER_TLATCH_LTCV_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GPTIMER_TLATCH_LTCV_MASK ) | \ + ( ( ( _reg ) & GPTIMER_TLATCH_LTCV_MASK ) >> GPTIMER_TLATCH_LTCV_SHIFT ) +#define GPTIMER_TLATCH_LTCV_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GPTIMER_TLATCH_LTCV_MASK ) | \ ( ( ( _val ) << GPTIMER_TLATCH_LTCV_SHIFT ) & \ GPTIMER_TLATCH_LTCV_MASK ) ) #define GPTIMER_TLATCH_LTCV( _val ) \ - ( ( ( _val ) << GPTIMER_TLATCH_LTCV_SHIFT ) & \ - GPTIMER_TLATCH_LTCV_MASK ) + ( ( ( _val ) << GPTIMER_TLATCH_LTCV_SHIFT ) & GPTIMER_TLATCH_LTCV_MASK ) /** @} */ @@ -230,17 +226,15 @@ typedef struct gptimer_timer { */ #define GPTIMER_SCALER_SCALER_SHIFT 0 -#define GPTIMER_SCALER_SCALER_MASK 0xffffU +#define GPTIMER_SCALER_SCALER_MASK 0xffffU #define GPTIMER_SCALER_SCALER_GET( _reg ) \ - ( ( ( _reg ) & GPTIMER_SCALER_SCALER_MASK ) >> \ - GPTIMER_SCALER_SCALER_SHIFT ) -#define GPTIMER_SCALER_SCALER_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GPTIMER_SCALER_SCALER_MASK ) | \ + ( ( ( _reg ) & GPTIMER_SCALER_SCALER_MASK ) >> GPTIMER_SCALER_SCALER_SHIFT ) +#define GPTIMER_SCALER_SCALER_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GPTIMER_SCALER_SCALER_MASK ) | \ ( ( ( _val ) << GPTIMER_SCALER_SCALER_SHIFT ) & \ GPTIMER_SCALER_SCALER_MASK ) ) #define GPTIMER_SCALER_SCALER( _val ) \ - ( ( ( _val ) << GPTIMER_SCALER_SCALER_SHIFT ) & \ - GPTIMER_SCALER_SCALER_MASK ) + ( ( ( _val ) << GPTIMER_SCALER_SCALER_SHIFT ) & GPTIMER_SCALER_SCALER_MASK ) /** @} */ @@ -254,15 +248,15 @@ typedef struct gptimer_timer { */ #define GPTIMER_SRELOAD_SRELOAD_SHIFT 0 -#define GPTIMER_SRELOAD_SRELOAD_MASK 0xffffU -#define GPTIMER_SRELOAD_SRELOAD_GET( _reg ) \ +#define GPTIMER_SRELOAD_SRELOAD_MASK 0xffffU +#define GPTIMER_SRELOAD_SRELOAD_GET( _reg ) \ ( ( ( _reg ) & GPTIMER_SRELOAD_SRELOAD_MASK ) >> \ GPTIMER_SRELOAD_SRELOAD_SHIFT ) -#define GPTIMER_SRELOAD_SRELOAD_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GPTIMER_SRELOAD_SRELOAD_MASK ) | \ +#define GPTIMER_SRELOAD_SRELOAD_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GPTIMER_SRELOAD_SRELOAD_MASK ) | \ ( ( ( _val ) << GPTIMER_SRELOAD_SRELOAD_SHIFT ) & \ GPTIMER_SRELOAD_SRELOAD_MASK ) ) -#define GPTIMER_SRELOAD_SRELOAD( _val ) \ +#define GPTIMER_SRELOAD_SRELOAD( _val ) \ ( ( ( _val ) << GPTIMER_SRELOAD_SRELOAD_SHIFT ) & \ GPTIMER_SRELOAD_SRELOAD_MASK ) @@ -289,30 +283,25 @@ typedef struct gptimer_timer { #define GPTIMER_CONFIG_SI 0x100U #define GPTIMER_CONFIG_IRQ_SHIFT 3 -#define GPTIMER_CONFIG_IRQ_MASK 0xf8U +#define GPTIMER_CONFIG_IRQ_MASK 0xf8U #define GPTIMER_CONFIG_IRQ_GET( _reg ) \ - ( ( ( _reg ) & GPTIMER_CONFIG_IRQ_MASK ) >> \ - GPTIMER_CONFIG_IRQ_SHIFT ) -#define GPTIMER_CONFIG_IRQ_SET( _reg, _val ) \ + ( ( ( _reg ) & GPTIMER_CONFIG_IRQ_MASK ) >> GPTIMER_CONFIG_IRQ_SHIFT ) +#define GPTIMER_CONFIG_IRQ_SET( _reg, _val ) \ ( ( ( _reg ) & ~GPTIMER_CONFIG_IRQ_MASK ) | \ - ( ( ( _val ) << GPTIMER_CONFIG_IRQ_SHIFT ) & \ - GPTIMER_CONFIG_IRQ_MASK ) ) + ( ( ( _val ) << GPTIMER_CONFIG_IRQ_SHIFT ) & GPTIMER_CONFIG_IRQ_MASK ) ) #define GPTIMER_CONFIG_IRQ( _val ) \ - ( ( ( _val ) << GPTIMER_CONFIG_IRQ_SHIFT ) & \ - GPTIMER_CONFIG_IRQ_MASK ) + ( ( ( _val ) << GPTIMER_CONFIG_IRQ_SHIFT ) & GPTIMER_CONFIG_IRQ_MASK ) #define GPTIMER_CONFIG_TIMERS_SHIFT 0 -#define GPTIMER_CONFIG_TIMERS_MASK 0x7U +#define GPTIMER_CONFIG_TIMERS_MASK 0x7U #define GPTIMER_CONFIG_TIMERS_GET( _reg ) \ - ( ( ( _reg ) & GPTIMER_CONFIG_TIMERS_MASK ) >> \ - GPTIMER_CONFIG_TIMERS_SHIFT ) -#define GPTIMER_CONFIG_TIMERS_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GPTIMER_CONFIG_TIMERS_MASK ) | \ + ( ( ( _reg ) & GPTIMER_CONFIG_TIMERS_MASK ) >> GPTIMER_CONFIG_TIMERS_SHIFT ) +#define GPTIMER_CONFIG_TIMERS_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GPTIMER_CONFIG_TIMERS_MASK ) | \ ( ( ( _val ) << GPTIMER_CONFIG_TIMERS_SHIFT ) & \ GPTIMER_CONFIG_TIMERS_MASK ) ) #define GPTIMER_CONFIG_TIMERS( _val ) \ - ( ( ( _val ) << GPTIMER_CONFIG_TIMERS_SHIFT ) & \ - GPTIMER_CONFIG_TIMERS_MASK ) + ( ( ( _val ) << GPTIMER_CONFIG_TIMERS_SHIFT ) & GPTIMER_CONFIG_TIMERS_MASK ) /** @} */ @@ -326,15 +315,15 @@ typedef struct gptimer_timer { */ #define GPTIMER_LATCHCFG_LATCHSEL_SHIFT 0 -#define GPTIMER_LATCHCFG_LATCHSEL_MASK 0xffffffffU -#define GPTIMER_LATCHCFG_LATCHSEL_GET( _reg ) \ +#define GPTIMER_LATCHCFG_LATCHSEL_MASK 0xffffffffU +#define GPTIMER_LATCHCFG_LATCHSEL_GET( _reg ) \ ( ( ( _reg ) & GPTIMER_LATCHCFG_LATCHSEL_MASK ) >> \ GPTIMER_LATCHCFG_LATCHSEL_SHIFT ) -#define GPTIMER_LATCHCFG_LATCHSEL_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GPTIMER_LATCHCFG_LATCHSEL_MASK ) | \ +#define GPTIMER_LATCHCFG_LATCHSEL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GPTIMER_LATCHCFG_LATCHSEL_MASK ) | \ ( ( ( _val ) << GPTIMER_LATCHCFG_LATCHSEL_SHIFT ) & \ GPTIMER_LATCHCFG_LATCHSEL_MASK ) ) -#define GPTIMER_LATCHCFG_LATCHSEL( _val ) \ +#define GPTIMER_LATCHCFG_LATCHSEL( _val ) \ ( ( ( _val ) << GPTIMER_LATCHCFG_LATCHSEL_SHIFT ) & \ GPTIMER_LATCHCFG_LATCHSEL_MASK ) diff --git a/bsps/include/grlib/gptimer.h b/bsps/include/grlib/gptimer.h index b5e2c13cbe..1cc9bfcdc3 100644 --- a/bsps/include/grlib/gptimer.h +++ b/bsps/include/grlib/gptimer.h @@ -40,7 +40,7 @@ extern "C" { */ /* Register GPTIMER and GRTIMER driver to Driver Manager */ -void gptimer_register_drv (void); +void gptimer_register_drv( void ); #ifdef __cplusplus } diff --git a/bsps/include/grlib/gr1553b-regs.h b/bsps/include/grlib/gr1553b-regs.h index 9003a9036c..ceb8c62466 100644 --- a/bsps/include/grlib/gr1553b-regs.h +++ b/bsps/include/grlib/gr1553b-regs.h @@ -140,32 +140,26 @@ extern "C" { #define GR1553B_HC_XKEYS 0x800U #define GR1553B_HC_ENDIAN_SHIFT 9 -#define GR1553B_HC_ENDIAN_MASK 0x600U +#define GR1553B_HC_ENDIAN_MASK 0x600U #define GR1553B_HC_ENDIAN_GET( _reg ) \ - ( ( ( _reg ) & GR1553B_HC_ENDIAN_MASK ) >> \ - GR1553B_HC_ENDIAN_SHIFT ) -#define GR1553B_HC_ENDIAN_SET( _reg, _val ) \ + ( ( ( _reg ) & GR1553B_HC_ENDIAN_MASK ) >> GR1553B_HC_ENDIAN_SHIFT ) +#define GR1553B_HC_ENDIAN_SET( _reg, _val ) \ ( ( ( _reg ) & ~GR1553B_HC_ENDIAN_MASK ) | \ - ( ( ( _val ) << GR1553B_HC_ENDIAN_SHIFT ) & \ - GR1553B_HC_ENDIAN_MASK ) ) + ( ( ( _val ) << GR1553B_HC_ENDIAN_SHIFT ) & GR1553B_HC_ENDIAN_MASK ) ) #define GR1553B_HC_ENDIAN( _val ) \ - ( ( ( _val ) << GR1553B_HC_ENDIAN_SHIFT ) & \ - GR1553B_HC_ENDIAN_MASK ) + ( ( ( _val ) << GR1553B_HC_ENDIAN_SHIFT ) & GR1553B_HC_ENDIAN_MASK ) #define GR1553B_HC_SCLK 0x100U #define GR1553B_HC_CCFREQ_SHIFT 0 -#define GR1553B_HC_CCFREQ_MASK 0xffU +#define GR1553B_HC_CCFREQ_MASK 0xffU #define GR1553B_HC_CCFREQ_GET( _reg ) \ - ( ( ( _reg ) & GR1553B_HC_CCFREQ_MASK ) >> \ - GR1553B_HC_CCFREQ_SHIFT ) -#define GR1553B_HC_CCFREQ_SET( _reg, _val ) \ + ( ( ( _reg ) & GR1553B_HC_CCFREQ_MASK ) >> GR1553B_HC_CCFREQ_SHIFT ) +#define GR1553B_HC_CCFREQ_SET( _reg, _val ) \ ( ( ( _reg ) & ~GR1553B_HC_CCFREQ_MASK ) | \ - ( ( ( _val ) << GR1553B_HC_CCFREQ_SHIFT ) & \ - GR1553B_HC_CCFREQ_MASK ) ) + ( ( ( _val ) << GR1553B_HC_CCFREQ_SHIFT ) & GR1553B_HC_CCFREQ_MASK ) ) #define GR1553B_HC_CCFREQ( _val ) \ - ( ( ( _val ) << GR1553B_HC_CCFREQ_SHIFT ) & \ - GR1553B_HC_CCFREQ_MASK ) + ( ( ( _val ) << GR1553B_HC_CCFREQ_SHIFT ) & GR1553B_HC_CCFREQ_MASK ) /** @} */ @@ -181,71 +175,57 @@ extern "C" { #define GR1553B_BCSC_BCSUP 0x80000000U #define GR1553B_BCSC_BCFEAT_SHIFT 28 -#define GR1553B_BCSC_BCFEAT_MASK 0x70000000U +#define GR1553B_BCSC_BCFEAT_MASK 0x70000000U #define GR1553B_BCSC_BCFEAT_GET( _reg ) \ - ( ( ( _reg ) & GR1553B_BCSC_BCFEAT_MASK ) >> \ - GR1553B_BCSC_BCFEAT_SHIFT ) -#define GR1553B_BCSC_BCFEAT_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GR1553B_BCSC_BCFEAT_MASK ) | \ + ( ( ( _reg ) & GR1553B_BCSC_BCFEAT_MASK ) >> GR1553B_BCSC_BCFEAT_SHIFT ) +#define GR1553B_BCSC_BCFEAT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_BCSC_BCFEAT_MASK ) | \ ( ( ( _val ) << GR1553B_BCSC_BCFEAT_SHIFT ) & \ GR1553B_BCSC_BCFEAT_MASK ) ) #define GR1553B_BCSC_BCFEAT( _val ) \ - ( ( ( _val ) << GR1553B_BCSC_BCFEAT_SHIFT ) & \ - GR1553B_BCSC_BCFEAT_MASK ) + ( ( ( _val ) << GR1553B_BCSC_BCFEAT_SHIFT ) & GR1553B_BCSC_BCFEAT_MASK ) #define GR1553B_BCSC_BCCHK 0x10000U #define GR1553B_BCSC_ASADL_SHIFT 11 -#define GR1553B_BCSC_ASADL_MASK 0xf800U +#define GR1553B_BCSC_ASADL_MASK 0xf800U #define GR1553B_BCSC_ASADL_GET( _reg ) \ - ( ( ( _reg ) & GR1553B_BCSC_ASADL_MASK ) >> \ - GR1553B_BCSC_ASADL_SHIFT ) -#define GR1553B_BCSC_ASADL_SET( _reg, _val ) \ + ( ( ( _reg ) & GR1553B_BCSC_ASADL_MASK ) >> GR1553B_BCSC_ASADL_SHIFT ) +#define GR1553B_BCSC_ASADL_SET( _reg, _val ) \ ( ( ( _reg ) & ~GR1553B_BCSC_ASADL_MASK ) | \ - ( ( ( _val ) << GR1553B_BCSC_ASADL_SHIFT ) & \ - GR1553B_BCSC_ASADL_MASK ) ) + ( ( ( _val ) << GR1553B_BCSC_ASADL_SHIFT ) & GR1553B_BCSC_ASADL_MASK ) ) #define GR1553B_BCSC_ASADL( _val ) \ - ( ( ( _val ) << GR1553B_BCSC_ASADL_SHIFT ) & \ - GR1553B_BCSC_ASADL_MASK ) + ( ( ( _val ) << GR1553B_BCSC_ASADL_SHIFT ) & GR1553B_BCSC_ASADL_MASK ) #define GR1553B_BCSC_ASST_SHIFT 8 -#define GR1553B_BCSC_ASST_MASK 0x300U +#define GR1553B_BCSC_ASST_MASK 0x300U #define GR1553B_BCSC_ASST_GET( _reg ) \ - ( ( ( _reg ) & GR1553B_BCSC_ASST_MASK ) >> \ - GR1553B_BCSC_ASST_SHIFT ) -#define GR1553B_BCSC_ASST_SET( _reg, _val ) \ + ( ( ( _reg ) & GR1553B_BCSC_ASST_MASK ) >> GR1553B_BCSC_ASST_SHIFT ) +#define GR1553B_BCSC_ASST_SET( _reg, _val ) \ ( ( ( _reg ) & ~GR1553B_BCSC_ASST_MASK ) | \ - ( ( ( _val ) << GR1553B_BCSC_ASST_SHIFT ) & \ - GR1553B_BCSC_ASST_MASK ) ) + ( ( ( _val ) << GR1553B_BCSC_ASST_SHIFT ) & GR1553B_BCSC_ASST_MASK ) ) #define GR1553B_BCSC_ASST( _val ) \ - ( ( ( _val ) << GR1553B_BCSC_ASST_SHIFT ) & \ - GR1553B_BCSC_ASST_MASK ) + ( ( ( _val ) << GR1553B_BCSC_ASST_SHIFT ) & GR1553B_BCSC_ASST_MASK ) #define GR1553B_BCSC_SCADL_SHIFT 3 -#define GR1553B_BCSC_SCADL_MASK 0xf8U +#define GR1553B_BCSC_SCADL_MASK 0xf8U #define GR1553B_BCSC_SCADL_GET( _reg ) \ - ( ( ( _reg ) & GR1553B_BCSC_SCADL_MASK ) >> \ - GR1553B_BCSC_SCADL_SHIFT ) -#define GR1553B_BCSC_SCADL_SET( _reg, _val ) \ + ( ( ( _reg ) & GR1553B_BCSC_SCADL_MASK ) >> GR1553B_BCSC_SCADL_SHIFT ) +#define GR1553B_BCSC_SCADL_SET( _reg, _val ) \ ( ( ( _reg ) & ~GR1553B_BCSC_SCADL_MASK ) | \ - ( ( ( _val ) << GR1553B_BCSC_SCADL_SHIFT ) & \ - GR1553B_BCSC_SCADL_MASK ) ) + ( ( ( _val ) << GR1553B_BCSC_SCADL_SHIFT ) & GR1553B_BCSC_SCADL_MASK ) ) #define GR1553B_BCSC_SCADL( _val ) \ - ( ( ( _val ) << GR1553B_BCSC_SCADL_SHIFT ) & \ - GR1553B_BCSC_SCADL_MASK ) + ( ( ( _val ) << GR1553B_BCSC_SCADL_SHIFT ) & GR1553B_BCSC_SCADL_MASK ) #define GR1553B_BCSC_SCST_SHIFT 0 -#define GR1553B_BCSC_SCST_MASK 0x7U +#define GR1553B_BCSC_SCST_MASK 0x7U #define GR1553B_BCSC_SCST_GET( _reg ) \ - ( ( ( _reg ) & GR1553B_BCSC_SCST_MASK ) >> \ - GR1553B_BCSC_SCST_SHIFT ) -#define GR1553B_BCSC_SCST_SET( _reg, _val ) \ + ( ( ( _reg ) & GR1553B_BCSC_SCST_MASK ) >> GR1553B_BCSC_SCST_SHIFT ) +#define GR1553B_BCSC_SCST_SET( _reg, _val ) \ ( ( ( _reg ) & ~GR1553B_BCSC_SCST_MASK ) | \ - ( ( ( _val ) << GR1553B_BCSC_SCST_SHIFT ) & \ - GR1553B_BCSC_SCST_MASK ) ) + ( ( ( _val ) << GR1553B_BCSC_SCST_SHIFT ) & GR1553B_BCSC_SCST_MASK ) ) #define GR1553B_BCSC_SCST( _val ) \ - ( ( ( _val ) << GR1553B_BCSC_SCST_SHIFT ) & \ - GR1553B_BCSC_SCST_MASK ) + ( ( ( _val ) << GR1553B_BCSC_SCST_SHIFT ) & GR1553B_BCSC_SCST_MASK ) /** @} */ @@ -258,17 +238,14 @@ extern "C" { */ #define GR1553B_BCA_BCKEY_SHIFT 16 -#define GR1553B_BCA_BCKEY_MASK 0xffff0000U +#define GR1553B_BCA_BCKEY_MASK 0xffff0000U #define GR1553B_BCA_BCKEY_GET( _reg ) \ - ( ( ( _reg ) & GR1553B_BCA_BCKEY_MASK ) >> \ - GR1553B_BCA_BCKEY_SHIFT ) -#define GR1553B_BCA_BCKEY_SET( _reg, _val ) \ + ( ( ( _reg ) & GR1553B_BCA_BCKEY_MASK ) >> GR1553B_BCA_BCKEY_SHIFT ) +#define GR1553B_BCA_BCKEY_SET( _reg, _val ) \ ( ( ( _reg ) & ~GR1553B_BCA_BCKEY_MASK ) | \ - ( ( ( _val ) << GR1553B_BCA_BCKEY_SHIFT ) & \ - GR1553B_BCA_BCKEY_MASK ) ) + ( ( ( _val ) << GR1553B_BCA_BCKEY_SHIFT ) & GR1553B_BCA_BCKEY_MASK ) ) #define GR1553B_BCA_BCKEY( _val ) \ - ( ( ( _val ) << GR1553B_BCA_BCKEY_SHIFT ) & \ - GR1553B_BCA_BCKEY_MASK ) + ( ( ( _val ) << GR1553B_BCA_BCKEY_SHIFT ) & GR1553B_BCA_BCKEY_MASK ) #define GR1553B_BCA_ASSTP 0x200U @@ -296,17 +273,15 @@ extern "C" { */ #define GR1553B_BCTNP_POINTER_SHIFT 0 -#define GR1553B_BCTNP_POINTER_MASK 0xffffffffU +#define GR1553B_BCTNP_POINTER_MASK 0xffffffffU #define GR1553B_BCTNP_POINTER_GET( _reg ) \ - ( ( ( _reg ) & GR1553B_BCTNP_POINTER_MASK ) >> \ - GR1553B_BCTNP_POINTER_SHIFT ) -#define GR1553B_BCTNP_POINTER_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GR1553B_BCTNP_POINTER_MASK ) | \ + ( ( ( _reg ) & GR1553B_BCTNP_POINTER_MASK ) >> GR1553B_BCTNP_POINTER_SHIFT ) +#define GR1553B_BCTNP_POINTER_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_BCTNP_POINTER_MASK ) | \ ( ( ( _val ) << GR1553B_BCTNP_POINTER_SHIFT ) & \ GR1553B_BCTNP_POINTER_MASK ) ) #define GR1553B_BCTNP_POINTER( _val ) \ - ( ( ( _val ) << GR1553B_BCTNP_POINTER_SHIFT ) & \ - GR1553B_BCTNP_POINTER_MASK ) + ( ( ( _val ) << GR1553B_BCTNP_POINTER_SHIFT ) & GR1553B_BCTNP_POINTER_MASK ) /** @} */ @@ -320,17 +295,15 @@ extern "C" { */ #define GR1553B_BCANP_POINTER_SHIFT 0 -#define GR1553B_BCANP_POINTER_MASK 0xffffffffU +#define GR1553B_BCANP_POINTER_MASK 0xffffffffU #define GR1553B_BCANP_POINTER_GET( _reg ) \ - ( ( ( _reg ) & GR1553B_BCANP_POINTER_MASK ) >> \ - GR1553B_BCANP_POINTER_SHIFT ) -#define GR1553B_BCANP_POINTER_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GR1553B_BCANP_POINTER_MASK ) | \ + ( ( ( _reg ) & GR1553B_BCANP_POINTER_MASK ) >> GR1553B_BCANP_POINTER_SHIFT ) +#define GR1553B_BCANP_POINTER_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_BCANP_POINTER_MASK ) | \ ( ( ( _val ) << GR1553B_BCANP_POINTER_SHIFT ) & \ GR1553B_BCANP_POINTER_MASK ) ) #define GR1553B_BCANP_POINTER( _val ) \ - ( ( ( _val ) << GR1553B_BCANP_POINTER_SHIFT ) & \ - GR1553B_BCANP_POINTER_MASK ) + ( ( ( _val ) << GR1553B_BCANP_POINTER_SHIFT ) & GR1553B_BCANP_POINTER_MASK ) /** @} */ @@ -343,17 +316,14 @@ extern "C" { */ #define GR1553B_BCT_SCTM_SHIFT 0 -#define GR1553B_BCT_SCTM_MASK 0xffffffU +#define GR1553B_BCT_SCTM_MASK 0xffffffU #define GR1553B_BCT_SCTM_GET( _reg ) \ - ( ( ( _reg ) & GR1553B_BCT_SCTM_MASK ) >> \ - GR1553B_BCT_SCTM_SHIFT ) -#define GR1553B_BCT_SCTM_SET( _reg, _val ) \ + ( ( ( _reg ) & GR1553B_BCT_SCTM_MASK ) >> GR1553B_BCT_SCTM_SHIFT ) +#define GR1553B_BCT_SCTM_SET( _reg, _val ) \ ( ( ( _reg ) & ~GR1553B_BCT_SCTM_MASK ) | \ - ( ( ( _val ) << GR1553B_BCT_SCTM_SHIFT ) & \ - GR1553B_BCT_SCTM_MASK ) ) + ( ( ( _val ) << GR1553B_BCT_SCTM_SHIFT ) & GR1553B_BCT_SCTM_MASK ) ) #define GR1553B_BCT_SCTM( _val ) \ - ( ( ( _val ) << GR1553B_BCT_SCTM_SHIFT ) & \ - GR1553B_BCT_SCTM_MASK ) + ( ( ( _val ) << GR1553B_BCT_SCTM_SHIFT ) & GR1553B_BCT_SCTM_MASK ) /** @} */ @@ -367,17 +337,15 @@ extern "C" { */ #define GR1553B_BCRP_POSITION_SHIFT 0 -#define GR1553B_BCRP_POSITION_MASK 0xffffffffU +#define GR1553B_BCRP_POSITION_MASK 0xffffffffU #define GR1553B_BCRP_POSITION_GET( _reg ) \ - ( ( ( _reg ) & GR1553B_BCRP_POSITION_MASK ) >> \ - GR1553B_BCRP_POSITION_SHIFT ) -#define GR1553B_BCRP_POSITION_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GR1553B_BCRP_POSITION_MASK ) | \ + ( ( ( _reg ) & GR1553B_BCRP_POSITION_MASK ) >> GR1553B_BCRP_POSITION_SHIFT ) +#define GR1553B_BCRP_POSITION_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_BCRP_POSITION_MASK ) | \ ( ( ( _val ) << GR1553B_BCRP_POSITION_SHIFT ) & \ GR1553B_BCRP_POSITION_MASK ) ) #define GR1553B_BCRP_POSITION( _val ) \ - ( ( ( _val ) << GR1553B_BCRP_POSITION_SHIFT ) & \ - GR1553B_BCRP_POSITION_MASK ) + ( ( ( _val ) << GR1553B_BCRP_POSITION_SHIFT ) & GR1553B_BCRP_POSITION_MASK ) /** @} */ @@ -390,17 +358,14 @@ extern "C" { */ #define GR1553B_BCBS_SWAP_SHIFT 0 -#define GR1553B_BCBS_SWAP_MASK 0xffffffffU +#define GR1553B_BCBS_SWAP_MASK 0xffffffffU #define GR1553B_BCBS_SWAP_GET( _reg ) \ - ( ( ( _reg ) & GR1553B_BCBS_SWAP_MASK ) >> \ - GR1553B_BCBS_SWAP_SHIFT ) -#define GR1553B_BCBS_SWAP_SET( _reg, _val ) \ + ( ( ( _reg ) & GR1553B_BCBS_SWAP_MASK ) >> GR1553B_BCBS_SWAP_SHIFT ) +#define GR1553B_BCBS_SWAP_SET( _reg, _val ) \ ( ( ( _reg ) & ~GR1553B_BCBS_SWAP_MASK ) | \ - ( ( ( _val ) << GR1553B_BCBS_SWAP_SHIFT ) & \ - GR1553B_BCBS_SWAP_MASK ) ) + ( ( ( _val ) << GR1553B_BCBS_SWAP_SHIFT ) & GR1553B_BCBS_SWAP_MASK ) ) #define GR1553B_BCBS_SWAP( _val ) \ - ( ( ( _val ) << GR1553B_BCBS_SWAP_SHIFT ) & \ - GR1553B_BCBS_SWAP_MASK ) + ( ( ( _val ) << GR1553B_BCBS_SWAP_SHIFT ) & GR1553B_BCBS_SWAP_MASK ) /** @} */ @@ -414,17 +379,15 @@ extern "C" { */ #define GR1553B_BCTCP_POINTER_SHIFT 0 -#define GR1553B_BCTCP_POINTER_MASK 0xffffffffU +#define GR1553B_BCTCP_POINTER_MASK 0xffffffffU #define GR1553B_BCTCP_POINTER_GET( _reg ) \ - ( ( ( _reg ) & GR1553B_BCTCP_POINTER_MASK ) >> \ - GR1553B_BCTCP_POINTER_SHIFT ) -#define GR1553B_BCTCP_POINTER_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GR1553B_BCTCP_POINTER_MASK ) | \ + ( ( ( _reg ) & GR1553B_BCTCP_POINTER_MASK ) >> GR1553B_BCTCP_POINTER_SHIFT ) +#define GR1553B_BCTCP_POINTER_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_BCTCP_POINTER_MASK ) | \ ( ( ( _val ) << GR1553B_BCTCP_POINTER_SHIFT ) & \ GR1553B_BCTCP_POINTER_MASK ) ) #define GR1553B_BCTCP_POINTER( _val ) \ - ( ( ( _val ) << GR1553B_BCTCP_POINTER_SHIFT ) & \ - GR1553B_BCTCP_POINTER_MASK ) + ( ( ( _val ) << GR1553B_BCTCP_POINTER_SHIFT ) & GR1553B_BCTCP_POINTER_MASK ) /** @} */ @@ -438,17 +401,15 @@ extern "C" { */ #define GR1553B_BCACP_POINTER_SHIFT 0 -#define GR1553B_BCACP_POINTER_MASK 0xffffffffU +#define GR1553B_BCACP_POINTER_MASK 0xffffffffU #define GR1553B_BCACP_POINTER_GET( _reg ) \ - ( ( ( _reg ) & GR1553B_BCACP_POINTER_MASK ) >> \ - GR1553B_BCACP_POINTER_SHIFT ) -#define GR1553B_BCACP_POINTER_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GR1553B_BCACP_POINTER_MASK ) | \ + ( ( ( _reg ) & GR1553B_BCACP_POINTER_MASK ) >> GR1553B_BCACP_POINTER_SHIFT ) +#define GR1553B_BCACP_POINTER_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_BCACP_POINTER_MASK ) | \ ( ( ( _val ) << GR1553B_BCACP_POINTER_SHIFT ) & \ GR1553B_BCACP_POINTER_MASK ) ) #define GR1553B_BCACP_POINTER( _val ) \ - ( ( ( _val ) << GR1553B_BCACP_POINTER_SHIFT ) & \ - GR1553B_BCACP_POINTER_MASK ) + ( ( ( _val ) << GR1553B_BCACP_POINTER_SHIFT ) & GR1553B_BCACP_POINTER_MASK ) /** @} */ @@ -481,17 +442,14 @@ extern "C" { */ #define GR1553B_RTC_RTKEY_SHIFT 16 -#define GR1553B_RTC_RTKEY_MASK 0xffff0000U +#define GR1553B_RTC_RTKEY_MASK 0xffff0000U #define GR1553B_RTC_RTKEY_GET( _reg ) \ - ( ( ( _reg ) & GR1553B_RTC_RTKEY_MASK ) >> \ - GR1553B_RTC_RTKEY_SHIFT ) -#define GR1553B_RTC_RTKEY_SET( _reg, _val ) \ + ( ( ( _reg ) & GR1553B_RTC_RTKEY_MASK ) >> GR1553B_RTC_RTKEY_SHIFT ) +#define GR1553B_RTC_RTKEY_SET( _reg, _val ) \ ( ( ( _reg ) & ~GR1553B_RTC_RTKEY_MASK ) | \ - ( ( ( _val ) << GR1553B_RTC_RTKEY_SHIFT ) & \ - GR1553B_RTC_RTKEY_MASK ) ) + ( ( ( _val ) << GR1553B_RTC_RTKEY_SHIFT ) & GR1553B_RTC_RTKEY_MASK ) ) #define GR1553B_RTC_RTKEY( _val ) \ - ( ( ( _val ) << GR1553B_RTC_RTKEY_SHIFT ) & \ - GR1553B_RTC_RTKEY_MASK ) + ( ( ( _val ) << GR1553B_RTC_RTKEY_SHIFT ) & GR1553B_RTC_RTKEY_MASK ) #define GR1553B_RTC_SYS 0x8000U @@ -502,17 +460,14 @@ extern "C" { #define GR1553B_RTC_RTEIS 0x40U #define GR1553B_RTC_RTADDR_SHIFT 1 -#define GR1553B_RTC_RTADDR_MASK 0x3eU +#define GR1553B_RTC_RTADDR_MASK 0x3eU #define GR1553B_RTC_RTADDR_GET( _reg ) \ - ( ( ( _reg ) & GR1553B_RTC_RTADDR_MASK ) >> \ - GR1553B_RTC_RTADDR_SHIFT ) -#define GR1553B_RTC_RTADDR_SET( _reg, _val ) \ + ( ( ( _reg ) & GR1553B_RTC_RTADDR_MASK ) >> GR1553B_RTC_RTADDR_SHIFT ) +#define GR1553B_RTC_RTADDR_SET( _reg, _val ) \ ( ( ( _reg ) & ~GR1553B_RTC_RTADDR_MASK ) | \ - ( ( ( _val ) << GR1553B_RTC_RTADDR_SHIFT ) & \ - GR1553B_RTC_RTADDR_MASK ) ) + ( ( ( _val ) << GR1553B_RTC_RTADDR_SHIFT ) & GR1553B_RTC_RTADDR_MASK ) ) #define GR1553B_RTC_RTADDR( _val ) \ - ( ( ( _val ) << GR1553B_RTC_RTADDR_SHIFT ) & \ - GR1553B_RTC_RTADDR_MASK ) + ( ( ( _val ) << GR1553B_RTC_RTADDR_SHIFT ) & GR1553B_RTC_RTADDR_MASK ) #define GR1553B_RTC_RTEN 0x1U @@ -549,30 +504,24 @@ extern "C" { */ #define GR1553B_RTSW_BITW_SHIFT 16 -#define GR1553B_RTSW_BITW_MASK 0xffff0000U +#define GR1553B_RTSW_BITW_MASK 0xffff0000U #define GR1553B_RTSW_BITW_GET( _reg ) \ - ( ( ( _reg ) & GR1553B_RTSW_BITW_MASK ) >> \ - GR1553B_RTSW_BITW_SHIFT ) -#define GR1553B_RTSW_BITW_SET( _reg, _val ) \ + ( ( ( _reg ) & GR1553B_RTSW_BITW_MASK ) >> GR1553B_RTSW_BITW_SHIFT ) +#define GR1553B_RTSW_BITW_SET( _reg, _val ) \ ( ( ( _reg ) & ~GR1553B_RTSW_BITW_MASK ) | \ - ( ( ( _val ) << GR1553B_RTSW_BITW_SHIFT ) & \ - GR1553B_RTSW_BITW_MASK ) ) + ( ( ( _val ) << GR1553B_RTSW_BITW_SHIFT ) & GR1553B_RTSW_BITW_MASK ) ) #define GR1553B_RTSW_BITW( _val ) \ - ( ( ( _val ) << GR1553B_RTSW_BITW_SHIFT ) & \ - GR1553B_RTSW_BITW_MASK ) + ( ( ( _val ) << GR1553B_RTSW_BITW_SHIFT ) & GR1553B_RTSW_BITW_MASK ) #define GR1553B_RTSW_VECW_SHIFT 0 -#define GR1553B_RTSW_VECW_MASK 0xffffU +#define GR1553B_RTSW_VECW_MASK 0xffffU #define GR1553B_RTSW_VECW_GET( _reg ) \ - ( ( ( _reg ) & GR1553B_RTSW_VECW_MASK ) >> \ - GR1553B_RTSW_VECW_SHIFT ) -#define GR1553B_RTSW_VECW_SET( _reg, _val ) \ + ( ( ( _reg ) & GR1553B_RTSW_VECW_MASK ) >> GR1553B_RTSW_VECW_SHIFT ) +#define GR1553B_RTSW_VECW_SET( _reg, _val ) \ ( ( ( _reg ) & ~GR1553B_RTSW_VECW_MASK ) | \ - ( ( ( _val ) << GR1553B_RTSW_VECW_SHIFT ) & \ - GR1553B_RTSW_VECW_MASK ) ) + ( ( ( _val ) << GR1553B_RTSW_VECW_SHIFT ) & GR1553B_RTSW_VECW_MASK ) ) #define GR1553B_RTSW_VECW( _val ) \ - ( ( ( _val ) << GR1553B_RTSW_VECW_SHIFT ) & \ - GR1553B_RTSW_VECW_MASK ) + ( ( ( _val ) << GR1553B_RTSW_VECW_SHIFT ) & GR1553B_RTSW_VECW_MASK ) /** @} */ @@ -585,30 +534,24 @@ extern "C" { */ #define GR1553B_RTSY_SYTM_SHIFT 16 -#define GR1553B_RTSY_SYTM_MASK 0xffff0000U +#define GR1553B_RTSY_SYTM_MASK 0xffff0000U #define GR1553B_RTSY_SYTM_GET( _reg ) \ - ( ( ( _reg ) & GR1553B_RTSY_SYTM_MASK ) >> \ - GR1553B_RTSY_SYTM_SHIFT ) -#define GR1553B_RTSY_SYTM_SET( _reg, _val ) \ + ( ( ( _reg ) & GR1553B_RTSY_SYTM_MASK ) >> GR1553B_RTSY_SYTM_SHIFT ) +#define GR1553B_RTSY_SYTM_SET( _reg, _val ) \ ( ( ( _reg ) & ~GR1553B_RTSY_SYTM_MASK ) | \ - ( ( ( _val ) << GR1553B_RTSY_SYTM_SHIFT ) & \ - GR1553B_RTSY_SYTM_MASK ) ) + ( ( ( _val ) << GR1553B_RTSY_SYTM_SHIFT ) & GR1553B_RTSY_SYTM_MASK ) ) #define GR1553B_RTSY_SYTM( _val ) \ - ( ( ( _val ) << GR1553B_RTSY_SYTM_SHIFT ) & \ - GR1553B_RTSY_SYTM_MASK ) + ( ( ( _val ) << GR1553B_RTSY_SYTM_SHIFT ) & GR1553B_RTSY_SYTM_MASK ) #define GR1553B_RTSY_SYD_SHIFT 0 -#define GR1553B_RTSY_SYD_MASK 0xffffU +#define GR1553B_RTSY_SYD_MASK 0xffffU #define GR1553B_RTSY_SYD_GET( _reg ) \ - ( ( ( _reg ) & GR1553B_RTSY_SYD_MASK ) >> \ - GR1553B_RTSY_SYD_SHIFT ) -#define GR1553B_RTSY_SYD_SET( _reg, _val ) \ + ( ( ( _reg ) & GR1553B_RTSY_SYD_MASK ) >> GR1553B_RTSY_SYD_SHIFT ) +#define GR1553B_RTSY_SYD_SET( _reg, _val ) \ ( ( ( _reg ) & ~GR1553B_RTSY_SYD_MASK ) | \ - ( ( ( _val ) << GR1553B_RTSY_SYD_SHIFT ) & \ - GR1553B_RTSY_SYD_MASK ) ) + ( ( ( _val ) << GR1553B_RTSY_SYD_SHIFT ) & GR1553B_RTSY_SYD_MASK ) ) #define GR1553B_RTSY_SYD( _val ) \ - ( ( ( _val ) << GR1553B_RTSY_SYD_SHIFT ) & \ - GR1553B_RTSY_SYD_MASK ) + ( ( ( _val ) << GR1553B_RTSY_SYD_SHIFT ) & GR1553B_RTSY_SYD_MASK ) /** @} */ @@ -622,17 +565,15 @@ extern "C" { */ #define GR1553B_RTSTBA_SATB_SHIFT 9 -#define GR1553B_RTSTBA_SATB_MASK 0xfffffe00U +#define GR1553B_RTSTBA_SATB_MASK 0xfffffe00U #define GR1553B_RTSTBA_SATB_GET( _reg ) \ - ( ( ( _reg ) & GR1553B_RTSTBA_SATB_MASK ) >> \ - GR1553B_RTSTBA_SATB_SHIFT ) -#define GR1553B_RTSTBA_SATB_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GR1553B_RTSTBA_SATB_MASK ) | \ + ( ( ( _reg ) & GR1553B_RTSTBA_SATB_MASK ) >> GR1553B_RTSTBA_SATB_SHIFT ) +#define GR1553B_RTSTBA_SATB_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_RTSTBA_SATB_MASK ) | \ ( ( ( _val ) << GR1553B_RTSTBA_SATB_SHIFT ) & \ GR1553B_RTSTBA_SATB_MASK ) ) #define GR1553B_RTSTBA_SATB( _val ) \ - ( ( ( _val ) << GR1553B_RTSTBA_SATB_SHIFT ) & \ - GR1553B_RTSTBA_SATB_MASK ) + ( ( ( _val ) << GR1553B_RTSTBA_SATB_SHIFT ) & GR1553B_RTSTBA_SATB_MASK ) /** @} */ @@ -646,199 +587,154 @@ extern "C" { */ #define GR1553B_RTMCC_RRTB_SHIFT 28 -#define GR1553B_RTMCC_RRTB_MASK 0x30000000U +#define GR1553B_RTMCC_RRTB_MASK 0x30000000U #define GR1553B_RTMCC_RRTB_GET( _reg ) \ - ( ( ( _reg ) & GR1553B_RTMCC_RRTB_MASK ) >> \ - GR1553B_RTMCC_RRTB_SHIFT ) -#define GR1553B_RTMCC_RRTB_SET( _reg, _val ) \ + ( ( ( _reg ) & GR1553B_RTMCC_RRTB_MASK ) >> GR1553B_RTMCC_RRTB_SHIFT ) +#define GR1553B_RTMCC_RRTB_SET( _reg, _val ) \ ( ( ( _reg ) & ~GR1553B_RTMCC_RRTB_MASK ) | \ - ( ( ( _val ) << GR1553B_RTMCC_RRTB_SHIFT ) & \ - GR1553B_RTMCC_RRTB_MASK ) ) + ( ( ( _val ) << GR1553B_RTMCC_RRTB_SHIFT ) & GR1553B_RTMCC_RRTB_MASK ) ) #define GR1553B_RTMCC_RRTB( _val ) \ - ( ( ( _val ) << GR1553B_RTMCC_RRTB_SHIFT ) & \ - GR1553B_RTMCC_RRTB_MASK ) + ( ( ( _val ) << GR1553B_RTMCC_RRTB_SHIFT ) & GR1553B_RTMCC_RRTB_MASK ) #define GR1553B_RTMCC_RRT_SHIFT 26 -#define GR1553B_RTMCC_RRT_MASK 0xc000000U +#define GR1553B_RTMCC_RRT_MASK 0xc000000U #define GR1553B_RTMCC_RRT_GET( _reg ) \ - ( ( ( _reg ) & GR1553B_RTMCC_RRT_MASK ) >> \ - GR1553B_RTMCC_RRT_SHIFT ) -#define GR1553B_RTMCC_RRT_SET( _reg, _val ) \ + ( ( ( _reg ) & GR1553B_RTMCC_RRT_MASK ) >> GR1553B_RTMCC_RRT_SHIFT ) +#define GR1553B_RTMCC_RRT_SET( _reg, _val ) \ ( ( ( _reg ) & ~GR1553B_RTMCC_RRT_MASK ) | \ - ( ( ( _val ) << GR1553B_RTMCC_RRT_SHIFT ) & \ - GR1553B_RTMCC_RRT_MASK ) ) + ( ( ( _val ) << GR1553B_RTMCC_RRT_SHIFT ) & GR1553B_RTMCC_RRT_MASK ) ) #define GR1553B_RTMCC_RRT( _val ) \ - ( ( ( _val ) << GR1553B_RTMCC_RRT_SHIFT ) & \ - GR1553B_RTMCC_RRT_MASK ) + ( ( ( _val ) << GR1553B_RTMCC_RRT_SHIFT ) & GR1553B_RTMCC_RRT_MASK ) #define GR1553B_RTMCC_ITFB_SHIFT 24 -#define GR1553B_RTMCC_ITFB_MASK 0x3000000U +#define GR1553B_RTMCC_ITFB_MASK 0x3000000U #define GR1553B_RTMCC_ITFB_GET( _reg ) \ - ( ( ( _reg ) & GR1553B_RTMCC_ITFB_MASK ) >> \ - GR1553B_RTMCC_ITFB_SHIFT ) -#define GR1553B_RTMCC_ITFB_SET( _reg, _val ) \ + ( ( ( _reg ) & GR1553B_RTMCC_ITFB_MASK ) >> GR1553B_RTMCC_ITFB_SHIFT ) +#define GR1553B_RTMCC_ITFB_SET( _reg, _val ) \ ( ( ( _reg ) & ~GR1553B_RTMCC_ITFB_MASK ) | \ - ( ( ( _val ) << GR1553B_RTMCC_ITFB_SHIFT ) & \ - GR1553B_RTMCC_ITFB_MASK ) ) + ( ( ( _val ) << GR1553B_RTMCC_ITFB_SHIFT ) & GR1553B_RTMCC_ITFB_MASK ) ) #define GR1553B_RTMCC_ITFB( _val ) \ - ( ( ( _val ) << GR1553B_RTMCC_ITFB_SHIFT ) & \ - GR1553B_RTMCC_ITFB_MASK ) + ( ( ( _val ) << GR1553B_RTMCC_ITFB_SHIFT ) & GR1553B_RTMCC_ITFB_MASK ) #define GR1553B_RTMCC_ITF_SHIFT 22 -#define GR1553B_RTMCC_ITF_MASK 0xc00000U +#define GR1553B_RTMCC_ITF_MASK 0xc00000U #define GR1553B_RTMCC_ITF_GET( _reg ) \ - ( ( ( _reg ) & GR1553B_RTMCC_ITF_MASK ) >> \ - GR1553B_RTMCC_ITF_SHIFT ) -#define GR1553B_RTMCC_ITF_SET( _reg, _val ) \ + ( ( ( _reg ) & GR1553B_RTMCC_ITF_MASK ) >> GR1553B_RTMCC_ITF_SHIFT ) +#define GR1553B_RTMCC_ITF_SET( _reg, _val ) \ ( ( ( _reg ) & ~GR1553B_RTMCC_ITF_MASK ) | \ - ( ( ( _val ) << GR1553B_RTMCC_ITF_SHIFT ) & \ - GR1553B_RTMCC_ITF_MASK ) ) + ( ( ( _val ) << GR1553B_RTMCC_ITF_SHIFT ) & GR1553B_RTMCC_ITF_MASK ) ) #define GR1553B_RTMCC_ITF( _val ) \ - ( ( ( _val ) << GR1553B_RTMCC_ITF_SHIFT ) & \ - GR1553B_RTMCC_ITF_MASK ) + ( ( ( _val ) << GR1553B_RTMCC_ITF_SHIFT ) & GR1553B_RTMCC_ITF_MASK ) #define GR1553B_RTMCC_ISTB_SHIFT 20 -#define GR1553B_RTMCC_ISTB_MASK 0x300000U +#define GR1553B_RTMCC_ISTB_MASK 0x300000U #define GR1553B_RTMCC_ISTB_GET( _reg ) \ - ( ( ( _reg ) & GR1553B_RTMCC_ISTB_MASK ) >> \ - GR1553B_RTMCC_ISTB_SHIFT ) -#define GR1553B_RTMCC_ISTB_SET( _reg, _val ) \ + ( ( ( _reg ) & GR1553B_RTMCC_ISTB_MASK ) >> GR1553B_RTMCC_ISTB_SHIFT ) +#define GR1553B_RTMCC_ISTB_SET( _reg, _val ) \ ( ( ( _reg ) & ~GR1553B_RTMCC_ISTB_MASK ) | \ - ( ( ( _val ) << GR1553B_RTMCC_ISTB_SHIFT ) & \ - GR1553B_RTMCC_ISTB_MASK ) ) + ( ( ( _val ) << GR1553B_RTMCC_ISTB_SHIFT ) & GR1553B_RTMCC_ISTB_MASK ) ) #define GR1553B_RTMCC_ISTB( _val ) \ - ( ( ( _val ) << GR1553B_RTMCC_ISTB_SHIFT ) & \ - GR1553B_RTMCC_ISTB_MASK ) + ( ( ( _val ) << GR1553B_RTMCC_ISTB_SHIFT ) & GR1553B_RTMCC_ISTB_MASK ) #define GR1553B_RTMCC_IST_SHIFT 18 -#define GR1553B_RTMCC_IST_MASK 0xc0000U +#define GR1553B_RTMCC_IST_MASK 0xc0000U #define GR1553B_RTMCC_IST_GET( _reg ) \ - ( ( ( _reg ) & GR1553B_RTMCC_IST_MASK ) >> \ - GR1553B_RTMCC_IST_SHIFT ) -#define GR1553B_RTMCC_IST_SET( _reg, _val ) \ + ( ( ( _reg ) & GR1553B_RTMCC_IST_MASK ) >> GR1553B_RTMCC_IST_SHIFT ) +#define GR1553B_RTMCC_IST_SET( _reg, _val ) \ ( ( ( _reg ) & ~GR1553B_RTMCC_IST_MASK ) | \ - ( ( ( _val ) << GR1553B_RTMCC_IST_SHIFT ) & \ - GR1553B_RTMCC_IST_MASK ) ) + ( ( ( _val ) << GR1553B_RTMCC_IST_SHIFT ) & GR1553B_RTMCC_IST_MASK ) ) #define GR1553B_RTMCC_IST( _val ) \ - ( ( ( _val ) << GR1553B_RTMCC_IST_SHIFT ) & \ - GR1553B_RTMCC_IST_MASK ) + ( ( ( _val ) << GR1553B_RTMCC_IST_SHIFT ) & GR1553B_RTMCC_IST_MASK ) #define GR1553B_RTMCC_DBC_SHIFT 16 -#define GR1553B_RTMCC_DBC_MASK 0x30000U +#define GR1553B_RTMCC_DBC_MASK 0x30000U #define GR1553B_RTMCC_DBC_GET( _reg ) \ - ( ( ( _reg ) & GR1553B_RTMCC_DBC_MASK ) >> \ - GR1553B_RTMCC_DBC_SHIFT ) -#define GR1553B_RTMCC_DBC_SET( _reg, _val ) \ + ( ( ( _reg ) & GR1553B_RTMCC_DBC_MASK ) >> GR1553B_RTMCC_DBC_SHIFT ) +#define GR1553B_RTMCC_DBC_SET( _reg, _val ) \ ( ( ( _reg ) & ~GR1553B_RTMCC_DBC_MASK ) | \ - ( ( ( _val ) << GR1553B_RTMCC_DBC_SHIFT ) & \ - GR1553B_RTMCC_DBC_MASK ) ) + ( ( ( _val ) << GR1553B_RTMCC_DBC_SHIFT ) & GR1553B_RTMCC_DBC_MASK ) ) #define GR1553B_RTMCC_DBC( _val ) \ - ( ( ( _val ) << GR1553B_RTMCC_DBC_SHIFT ) & \ - GR1553B_RTMCC_DBC_MASK ) + ( ( ( _val ) << GR1553B_RTMCC_DBC_SHIFT ) & GR1553B_RTMCC_DBC_MASK ) #define GR1553B_RTMCC_TBW_SHIFT 14 -#define GR1553B_RTMCC_TBW_MASK 0xc000U +#define GR1553B_RTMCC_TBW_MASK 0xc000U #define GR1553B_RTMCC_TBW_GET( _reg ) \ - ( ( ( _reg ) & GR1553B_RTMCC_TBW_MASK ) >> \ - GR1553B_RTMCC_TBW_SHIFT ) -#define GR1553B_RTMCC_TBW_SET( _reg, _val ) \ + ( ( ( _reg ) & GR1553B_RTMCC_TBW_MASK ) >> GR1553B_RTMCC_TBW_SHIFT ) +#define GR1553B_RTMCC_TBW_SET( _reg, _val ) \ ( ( ( _reg ) & ~GR1553B_RTMCC_TBW_MASK ) | \ - ( ( ( _val ) << GR1553B_RTMCC_TBW_SHIFT ) & \ - GR1553B_RTMCC_TBW_MASK ) ) + ( ( ( _val ) << GR1553B_RTMCC_TBW_SHIFT ) & GR1553B_RTMCC_TBW_MASK ) ) #define GR1553B_RTMCC_TBW( _val ) \ - ( ( ( _val ) << GR1553B_RTMCC_TBW_SHIFT ) & \ - GR1553B_RTMCC_TBW_MASK ) + ( ( ( _val ) << GR1553B_RTMCC_TBW_SHIFT ) & GR1553B_RTMCC_TBW_MASK ) #define GR1553B_RTMCC_TVW_SHIFT 12 -#define GR1553B_RTMCC_TVW_MASK 0x3000U +#define GR1553B_RTMCC_TVW_MASK 0x3000U #define GR1553B_RTMCC_TVW_GET( _reg ) \ - ( ( ( _reg ) & GR1553B_RTMCC_TVW_MASK ) >> \ - GR1553B_RTMCC_TVW_SHIFT ) -#define GR1553B_RTMCC_TVW_SET( _reg, _val ) \ + ( ( ( _reg ) & GR1553B_RTMCC_TVW_MASK ) >> GR1553B_RTMCC_TVW_SHIFT ) +#define GR1553B_RTMCC_TVW_SET( _reg, _val ) \ ( ( ( _reg ) & ~GR1553B_RTMCC_TVW_MASK ) | \ - ( ( ( _val ) << GR1553B_RTMCC_TVW_SHIFT ) & \ - GR1553B_RTMCC_TVW_MASK ) ) + ( ( ( _val ) << GR1553B_RTMCC_TVW_SHIFT ) & GR1553B_RTMCC_TVW_MASK ) ) #define GR1553B_RTMCC_TVW( _val ) \ - ( ( ( _val ) << GR1553B_RTMCC_TVW_SHIFT ) & \ - GR1553B_RTMCC_TVW_MASK ) + ( ( ( _val ) << GR1553B_RTMCC_TVW_SHIFT ) & GR1553B_RTMCC_TVW_MASK ) #define GR1553B_RTMCC_TSB_SHIFT 10 -#define GR1553B_RTMCC_TSB_MASK 0xc00U +#define GR1553B_RTMCC_TSB_MASK 0xc00U #define GR1553B_RTMCC_TSB_GET( _reg ) \ - ( ( ( _reg ) & GR1553B_RTMCC_TSB_MASK ) >> \ - GR1553B_RTMCC_TSB_SHIFT ) -#define GR1553B_RTMCC_TSB_SET( _reg, _val ) \ + ( ( ( _reg ) & GR1553B_RTMCC_TSB_MASK ) >> GR1553B_RTMCC_TSB_SHIFT ) +#define GR1553B_RTMCC_TSB_SET( _reg, _val ) \ ( ( ( _reg ) & ~GR1553B_RTMCC_TSB_MASK ) | \ - ( ( ( _val ) << GR1553B_RTMCC_TSB_SHIFT ) & \ - GR1553B_RTMCC_TSB_MASK ) ) + ( ( ( _val ) << GR1553B_RTMCC_TSB_SHIFT ) & GR1553B_RTMCC_TSB_MASK ) ) #define GR1553B_RTMCC_TSB( _val ) \ - ( ( ( _val ) << GR1553B_RTMCC_TSB_SHIFT ) & \ - GR1553B_RTMCC_TSB_MASK ) + ( ( ( _val ) << GR1553B_RTMCC_TSB_SHIFT ) & GR1553B_RTMCC_TSB_MASK ) #define GR1553B_RTMCC_TS_SHIFT 8 -#define GR1553B_RTMCC_TS_MASK 0x300U +#define GR1553B_RTMCC_TS_MASK 0x300U #define GR1553B_RTMCC_TS_GET( _reg ) \ - ( ( ( _reg ) & GR1553B_RTMCC_TS_MASK ) >> \ - GR1553B_RTMCC_TS_SHIFT ) -#define GR1553B_RTMCC_TS_SET( _reg, _val ) \ + ( ( ( _reg ) & GR1553B_RTMCC_TS_MASK ) >> GR1553B_RTMCC_TS_SHIFT ) +#define GR1553B_RTMCC_TS_SET( _reg, _val ) \ ( ( ( _reg ) & ~GR1553B_RTMCC_TS_MASK ) | \ - ( ( ( _val ) << GR1553B_RTMCC_TS_SHIFT ) & \ - GR1553B_RTMCC_TS_MASK ) ) + ( ( ( _val ) << GR1553B_RTMCC_TS_SHIFT ) & GR1553B_RTMCC_TS_MASK ) ) #define GR1553B_RTMCC_TS( _val ) \ - ( ( ( _val ) << GR1553B_RTMCC_TS_SHIFT ) & \ - GR1553B_RTMCC_TS_MASK ) + ( ( ( _val ) << GR1553B_RTMCC_TS_SHIFT ) & GR1553B_RTMCC_TS_MASK ) #define GR1553B_RTMCC_SDB_SHIFT 6 -#define GR1553B_RTMCC_SDB_MASK 0xc0U +#define GR1553B_RTMCC_SDB_MASK 0xc0U #define GR1553B_RTMCC_SDB_GET( _reg ) \ - ( ( ( _reg ) & GR1553B_RTMCC_SDB_MASK ) >> \ - GR1553B_RTMCC_SDB_SHIFT ) -#define GR1553B_RTMCC_SDB_SET( _reg, _val ) \ + ( ( ( _reg ) & GR1553B_RTMCC_SDB_MASK ) >> GR1553B_RTMCC_SDB_SHIFT ) +#define GR1553B_RTMCC_SDB_SET( _reg, _val ) \ ( ( ( _reg ) & ~GR1553B_RTMCC_SDB_MASK ) | \ - ( ( ( _val ) << GR1553B_RTMCC_SDB_SHIFT ) & \ - GR1553B_RTMCC_SDB_MASK ) ) + ( ( ( _val ) << GR1553B_RTMCC_SDB_SHIFT ) & GR1553B_RTMCC_SDB_MASK ) ) #define GR1553B_RTMCC_SDB( _val ) \ - ( ( ( _val ) << GR1553B_RTMCC_SDB_SHIFT ) & \ - GR1553B_RTMCC_SDB_MASK ) + ( ( ( _val ) << GR1553B_RTMCC_SDB_SHIFT ) & GR1553B_RTMCC_SDB_MASK ) #define GR1553B_RTMCC_SD_SHIFT 4 -#define GR1553B_RTMCC_SD_MASK 0x30U +#define GR1553B_RTMCC_SD_MASK 0x30U #define GR1553B_RTMCC_SD_GET( _reg ) \ - ( ( ( _reg ) & GR1553B_RTMCC_SD_MASK ) >> \ - GR1553B_RTMCC_SD_SHIFT ) -#define GR1553B_RTMCC_SD_SET( _reg, _val ) \ + ( ( ( _reg ) & GR1553B_RTMCC_SD_MASK ) >> GR1553B_RTMCC_SD_SHIFT ) +#define GR1553B_RTMCC_SD_SET( _reg, _val ) \ ( ( ( _reg ) & ~GR1553B_RTMCC_SD_MASK ) | \ - ( ( ( _val ) << GR1553B_RTMCC_SD_SHIFT ) & \ - GR1553B_RTMCC_SD_MASK ) ) + ( ( ( _val ) << GR1553B_RTMCC_SD_SHIFT ) & GR1553B_RTMCC_SD_MASK ) ) #define GR1553B_RTMCC_SD( _val ) \ - ( ( ( _val ) << GR1553B_RTMCC_SD_SHIFT ) & \ - GR1553B_RTMCC_SD_MASK ) + ( ( ( _val ) << GR1553B_RTMCC_SD_SHIFT ) & GR1553B_RTMCC_SD_MASK ) #define GR1553B_RTMCC_SB_SHIFT 2 -#define GR1553B_RTMCC_SB_MASK 0xcU +#define GR1553B_RTMCC_SB_MASK 0xcU #define GR1553B_RTMCC_SB_GET( _reg ) \ - ( ( ( _reg ) & GR1553B_RTMCC_SB_MASK ) >> \ - GR1553B_RTMCC_SB_SHIFT ) -#define GR1553B_RTMCC_SB_SET( _reg, _val ) \ + ( ( ( _reg ) & GR1553B_RTMCC_SB_MASK ) >> GR1553B_RTMCC_SB_SHIFT ) +#define GR1553B_RTMCC_SB_SET( _reg, _val ) \ ( ( ( _reg ) & ~GR1553B_RTMCC_SB_MASK ) | \ - ( ( ( _val ) << GR1553B_RTMCC_SB_SHIFT ) & \ - GR1553B_RTMCC_SB_MASK ) ) + ( ( ( _val ) << GR1553B_RTMCC_SB_SHIFT ) & GR1553B_RTMCC_SB_MASK ) ) #define GR1553B_RTMCC_SB( _val ) \ - ( ( ( _val ) << GR1553B_RTMCC_SB_SHIFT ) & \ - GR1553B_RTMCC_SB_MASK ) + ( ( ( _val ) << GR1553B_RTMCC_SB_SHIFT ) & GR1553B_RTMCC_SB_MASK ) #define GR1553B_RTMCC_S_SHIFT 0 -#define GR1553B_RTMCC_S_MASK 0x3U +#define GR1553B_RTMCC_S_MASK 0x3U #define GR1553B_RTMCC_S_GET( _reg ) \ - ( ( ( _reg ) & GR1553B_RTMCC_S_MASK ) >> \ - GR1553B_RTMCC_S_SHIFT ) -#define GR1553B_RTMCC_S_SET( _reg, _val ) \ + ( ( ( _reg ) & GR1553B_RTMCC_S_MASK ) >> GR1553B_RTMCC_S_SHIFT ) +#define GR1553B_RTMCC_S_SET( _reg, _val ) \ ( ( ( _reg ) & ~GR1553B_RTMCC_S_MASK ) | \ - ( ( ( _val ) << GR1553B_RTMCC_S_SHIFT ) & \ - GR1553B_RTMCC_S_MASK ) ) + ( ( ( _val ) << GR1553B_RTMCC_S_SHIFT ) & GR1553B_RTMCC_S_MASK ) ) #define GR1553B_RTMCC_S( _val ) \ - ( ( ( _val ) << GR1553B_RTMCC_S_SHIFT ) & \ - GR1553B_RTMCC_S_MASK ) + ( ( ( _val ) << GR1553B_RTMCC_S_SHIFT ) & GR1553B_RTMCC_S_MASK ) /** @} */ @@ -852,30 +748,24 @@ extern "C" { */ #define GR1553B_RTTTC_TRES_SHIFT 16 -#define GR1553B_RTTTC_TRES_MASK 0xffff0000U +#define GR1553B_RTTTC_TRES_MASK 0xffff0000U #define GR1553B_RTTTC_TRES_GET( _reg ) \ - ( ( ( _reg ) & GR1553B_RTTTC_TRES_MASK ) >> \ - GR1553B_RTTTC_TRES_SHIFT ) -#define GR1553B_RTTTC_TRES_SET( _reg, _val ) \ + ( ( ( _reg ) & GR1553B_RTTTC_TRES_MASK ) >> GR1553B_RTTTC_TRES_SHIFT ) +#define GR1553B_RTTTC_TRES_SET( _reg, _val ) \ ( ( ( _reg ) & ~GR1553B_RTTTC_TRES_MASK ) | \ - ( ( ( _val ) << GR1553B_RTTTC_TRES_SHIFT ) & \ - GR1553B_RTTTC_TRES_MASK ) ) + ( ( ( _val ) << GR1553B_RTTTC_TRES_SHIFT ) & GR1553B_RTTTC_TRES_MASK ) ) #define GR1553B_RTTTC_TRES( _val ) \ - ( ( ( _val ) << GR1553B_RTTTC_TRES_SHIFT ) & \ - GR1553B_RTTTC_TRES_MASK ) + ( ( ( _val ) << GR1553B_RTTTC_TRES_SHIFT ) & GR1553B_RTTTC_TRES_MASK ) #define GR1553B_RTTTC_TVAL_SHIFT 0 -#define GR1553B_RTTTC_TVAL_MASK 0xffffU +#define GR1553B_RTTTC_TVAL_MASK 0xffffU #define GR1553B_RTTTC_TVAL_GET( _reg ) \ - ( ( ( _reg ) & GR1553B_RTTTC_TVAL_MASK ) >> \ - GR1553B_RTTTC_TVAL_SHIFT ) -#define GR1553B_RTTTC_TVAL_SET( _reg, _val ) \ + ( ( ( _reg ) & GR1553B_RTTTC_TVAL_MASK ) >> GR1553B_RTTTC_TVAL_SHIFT ) +#define GR1553B_RTTTC_TVAL_SET( _reg, _val ) \ ( ( ( _reg ) & ~GR1553B_RTTTC_TVAL_MASK ) | \ - ( ( ( _val ) << GR1553B_RTTTC_TVAL_SHIFT ) & \ - GR1553B_RTTTC_TVAL_MASK ) ) + ( ( ( _val ) << GR1553B_RTTTC_TVAL_SHIFT ) & GR1553B_RTTTC_TVAL_MASK ) ) #define GR1553B_RTTTC_TVAL( _val ) \ - ( ( ( _val ) << GR1553B_RTTTC_TVAL_SHIFT ) & \ - GR1553B_RTTTC_TVAL_MASK ) + ( ( ( _val ) << GR1553B_RTTTC_TVAL_SHIFT ) & GR1553B_RTTTC_TVAL_MASK ) /** @} */ @@ -889,17 +779,14 @@ extern "C" { */ #define GR1553B_RTELM_MASK_SHIFT 0 -#define GR1553B_RTELM_MASK_MASK 0xffffffffU +#define GR1553B_RTELM_MASK_MASK 0xffffffffU #define GR1553B_RTELM_MASK_GET( _reg ) \ - ( ( ( _reg ) & GR1553B_RTELM_MASK_MASK ) >> \ - GR1553B_RTELM_MASK_SHIFT ) -#define GR1553B_RTELM_MASK_SET( _reg, _val ) \ + ( ( ( _reg ) & GR1553B_RTELM_MASK_MASK ) >> GR1553B_RTELM_MASK_SHIFT ) +#define GR1553B_RTELM_MASK_SET( _reg, _val ) \ ( ( ( _reg ) & ~GR1553B_RTELM_MASK_MASK ) | \ - ( ( ( _val ) << GR1553B_RTELM_MASK_SHIFT ) & \ - GR1553B_RTELM_MASK_MASK ) ) + ( ( ( _val ) << GR1553B_RTELM_MASK_SHIFT ) & GR1553B_RTELM_MASK_MASK ) ) #define GR1553B_RTELM_MASK( _val ) \ - ( ( ( _val ) << GR1553B_RTELM_MASK_SHIFT ) & \ - GR1553B_RTELM_MASK_MASK ) + ( ( ( _val ) << GR1553B_RTELM_MASK_SHIFT ) & GR1553B_RTELM_MASK_MASK ) /** @} */ @@ -913,17 +800,15 @@ extern "C" { */ #define GR1553B_RTELP_POINTER_SHIFT 0 -#define GR1553B_RTELP_POINTER_MASK 0xffffffffU +#define GR1553B_RTELP_POINTER_MASK 0xffffffffU #define GR1553B_RTELP_POINTER_GET( _reg ) \ - ( ( ( _reg ) & GR1553B_RTELP_POINTER_MASK ) >> \ - GR1553B_RTELP_POINTER_SHIFT ) -#define GR1553B_RTELP_POINTER_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GR1553B_RTELP_POINTER_MASK ) | \ + ( ( ( _reg ) & GR1553B_RTELP_POINTER_MASK ) >> GR1553B_RTELP_POINTER_SHIFT ) +#define GR1553B_RTELP_POINTER_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_RTELP_POINTER_MASK ) | \ ( ( ( _val ) << GR1553B_RTELP_POINTER_SHIFT ) & \ GR1553B_RTELP_POINTER_MASK ) ) #define GR1553B_RTELP_POINTER( _val ) \ - ( ( ( _val ) << GR1553B_RTELP_POINTER_SHIFT ) & \ - GR1553B_RTELP_POINTER_MASK ) + ( ( ( _val ) << GR1553B_RTELP_POINTER_SHIFT ) & GR1553B_RTELP_POINTER_MASK ) /** @} */ @@ -937,15 +822,15 @@ extern "C" { */ #define GR1553B_RTELIP_POINTER_SHIFT 0 -#define GR1553B_RTELIP_POINTER_MASK 0xffffffffU -#define GR1553B_RTELIP_POINTER_GET( _reg ) \ +#define GR1553B_RTELIP_POINTER_MASK 0xffffffffU +#define GR1553B_RTELIP_POINTER_GET( _reg ) \ ( ( ( _reg ) & GR1553B_RTELIP_POINTER_MASK ) >> \ GR1553B_RTELIP_POINTER_SHIFT ) -#define GR1553B_RTELIP_POINTER_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GR1553B_RTELIP_POINTER_MASK ) | \ +#define GR1553B_RTELIP_POINTER_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_RTELIP_POINTER_MASK ) | \ ( ( ( _val ) << GR1553B_RTELIP_POINTER_SHIFT ) & \ GR1553B_RTELIP_POINTER_MASK ) ) -#define GR1553B_RTELIP_POINTER( _val ) \ +#define GR1553B_RTELIP_POINTER( _val ) \ ( ( ( _val ) << GR1553B_RTELIP_POINTER_SHIFT ) & \ GR1553B_RTELIP_POINTER_MASK ) @@ -974,17 +859,14 @@ extern "C" { */ #define GR1553B_BMC_BMKEY_SHIFT 16 -#define GR1553B_BMC_BMKEY_MASK 0xffff0000U +#define GR1553B_BMC_BMKEY_MASK 0xffff0000U #define GR1553B_BMC_BMKEY_GET( _reg ) \ - ( ( ( _reg ) & GR1553B_BMC_BMKEY_MASK ) >> \ - GR1553B_BMC_BMKEY_SHIFT ) -#define GR1553B_BMC_BMKEY_SET( _reg, _val ) \ + ( ( ( _reg ) & GR1553B_BMC_BMKEY_MASK ) >> GR1553B_BMC_BMKEY_SHIFT ) +#define GR1553B_BMC_BMKEY_SET( _reg, _val ) \ ( ( ( _reg ) & ~GR1553B_BMC_BMKEY_MASK ) | \ - ( ( ( _val ) << GR1553B_BMC_BMKEY_SHIFT ) & \ - GR1553B_BMC_BMKEY_MASK ) ) + ( ( ( _val ) << GR1553B_BMC_BMKEY_SHIFT ) & GR1553B_BMC_BMKEY_MASK ) ) #define GR1553B_BMC_BMKEY( _val ) \ - ( ( ( _val ) << GR1553B_BMC_BMKEY_SHIFT ) & \ - GR1553B_BMC_BMKEY_MASK ) + ( ( ( _val ) << GR1553B_BMC_BMKEY_SHIFT ) & GR1553B_BMC_BMKEY_MASK ) #define GR1553B_BMC_WRSTP 0x20U @@ -1010,17 +892,15 @@ extern "C" { */ #define GR1553B_BMRTAF_MASK_SHIFT 0 -#define GR1553B_BMRTAF_MASK_MASK 0xffffffffU +#define GR1553B_BMRTAF_MASK_MASK 0xffffffffU #define GR1553B_BMRTAF_MASK_GET( _reg ) \ - ( ( ( _reg ) & GR1553B_BMRTAF_MASK_MASK ) >> \ - GR1553B_BMRTAF_MASK_SHIFT ) -#define GR1553B_BMRTAF_MASK_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GR1553B_BMRTAF_MASK_MASK ) | \ + ( ( ( _reg ) & GR1553B_BMRTAF_MASK_MASK ) >> GR1553B_BMRTAF_MASK_SHIFT ) +#define GR1553B_BMRTAF_MASK_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_BMRTAF_MASK_MASK ) | \ ( ( ( _val ) << GR1553B_BMRTAF_MASK_SHIFT ) & \ GR1553B_BMRTAF_MASK_MASK ) ) #define GR1553B_BMRTAF_MASK( _val ) \ - ( ( ( _val ) << GR1553B_BMRTAF_MASK_SHIFT ) & \ - GR1553B_BMRTAF_MASK_MASK ) + ( ( ( _val ) << GR1553B_BMRTAF_MASK_SHIFT ) & GR1553B_BMRTAF_MASK_MASK ) /** @} */ @@ -1034,17 +914,15 @@ extern "C" { */ #define GR1553B_BMRTSF_MASK_SHIFT 0 -#define GR1553B_BMRTSF_MASK_MASK 0xffffffffU +#define GR1553B_BMRTSF_MASK_MASK 0xffffffffU #define GR1553B_BMRTSF_MASK_GET( _reg ) \ - ( ( ( _reg ) & GR1553B_BMRTSF_MASK_MASK ) >> \ - GR1553B_BMRTSF_MASK_SHIFT ) -#define GR1553B_BMRTSF_MASK_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GR1553B_BMRTSF_MASK_MASK ) | \ + ( ( ( _reg ) & GR1553B_BMRTSF_MASK_MASK ) >> GR1553B_BMRTSF_MASK_SHIFT ) +#define GR1553B_BMRTSF_MASK_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_BMRTSF_MASK_MASK ) | \ ( ( ( _val ) << GR1553B_BMRTSF_MASK_SHIFT ) & \ GR1553B_BMRTSF_MASK_MASK ) ) #define GR1553B_BMRTSF_MASK( _val ) \ - ( ( ( _val ) << GR1553B_BMRTSF_MASK_SHIFT ) & \ - GR1553B_BMRTSF_MASK_MASK ) + ( ( ( _val ) << GR1553B_BMRTSF_MASK_SHIFT ) & GR1553B_BMRTSF_MASK_MASK ) /** @} */ @@ -1106,17 +984,15 @@ extern "C" { */ #define GR1553B_BMLBS_START_SHIFT 0 -#define GR1553B_BMLBS_START_MASK 0xffffffffU +#define GR1553B_BMLBS_START_MASK 0xffffffffU #define GR1553B_BMLBS_START_GET( _reg ) \ - ( ( ( _reg ) & GR1553B_BMLBS_START_MASK ) >> \ - GR1553B_BMLBS_START_SHIFT ) -#define GR1553B_BMLBS_START_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GR1553B_BMLBS_START_MASK ) | \ + ( ( ( _reg ) & GR1553B_BMLBS_START_MASK ) >> GR1553B_BMLBS_START_SHIFT ) +#define GR1553B_BMLBS_START_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_BMLBS_START_MASK ) | \ ( ( ( _val ) << GR1553B_BMLBS_START_SHIFT ) & \ GR1553B_BMLBS_START_MASK ) ) #define GR1553B_BMLBS_START( _val ) \ - ( ( ( _val ) << GR1553B_BMLBS_START_SHIFT ) & \ - GR1553B_BMLBS_START_MASK ) + ( ( ( _val ) << GR1553B_BMLBS_START_SHIFT ) & GR1553B_BMLBS_START_MASK ) /** @} */ @@ -1129,17 +1005,14 @@ extern "C" { */ #define GR1553B_BMLBE_END_SHIFT 0 -#define GR1553B_BMLBE_END_MASK 0xffffffffU +#define GR1553B_BMLBE_END_MASK 0xffffffffU #define GR1553B_BMLBE_END_GET( _reg ) \ - ( ( ( _reg ) & GR1553B_BMLBE_END_MASK ) >> \ - GR1553B_BMLBE_END_SHIFT ) -#define GR1553B_BMLBE_END_SET( _reg, _val ) \ + ( ( ( _reg ) & GR1553B_BMLBE_END_MASK ) >> GR1553B_BMLBE_END_SHIFT ) +#define GR1553B_BMLBE_END_SET( _reg, _val ) \ ( ( ( _reg ) & ~GR1553B_BMLBE_END_MASK ) | \ - ( ( ( _val ) << GR1553B_BMLBE_END_SHIFT ) & \ - GR1553B_BMLBE_END_MASK ) ) + ( ( ( _val ) << GR1553B_BMLBE_END_SHIFT ) & GR1553B_BMLBE_END_MASK ) ) #define GR1553B_BMLBE_END( _val ) \ - ( ( ( _val ) << GR1553B_BMLBE_END_SHIFT ) & \ - GR1553B_BMLBE_END_MASK ) + ( ( ( _val ) << GR1553B_BMLBE_END_SHIFT ) & GR1553B_BMLBE_END_MASK ) /** @} */ @@ -1152,15 +1025,15 @@ extern "C" { */ #define GR1553B_BMLBP_POSITION_SHIFT 0 -#define GR1553B_BMLBP_POSITION_MASK 0xffffffffU -#define GR1553B_BMLBP_POSITION_GET( _reg ) \ +#define GR1553B_BMLBP_POSITION_MASK 0xffffffffU +#define GR1553B_BMLBP_POSITION_GET( _reg ) \ ( ( ( _reg ) & GR1553B_BMLBP_POSITION_MASK ) >> \ GR1553B_BMLBP_POSITION_SHIFT ) -#define GR1553B_BMLBP_POSITION_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GR1553B_BMLBP_POSITION_MASK ) | \ +#define GR1553B_BMLBP_POSITION_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_BMLBP_POSITION_MASK ) | \ ( ( ( _val ) << GR1553B_BMLBP_POSITION_SHIFT ) & \ GR1553B_BMLBP_POSITION_MASK ) ) -#define GR1553B_BMLBP_POSITION( _val ) \ +#define GR1553B_BMLBP_POSITION( _val ) \ ( ( ( _val ) << GR1553B_BMLBP_POSITION_SHIFT ) & \ GR1553B_BMLBP_POSITION_MASK ) @@ -1176,30 +1049,24 @@ extern "C" { */ #define GR1553B_BMTTC_TRES_SHIFT 24 -#define GR1553B_BMTTC_TRES_MASK 0xff000000U +#define GR1553B_BMTTC_TRES_MASK 0xff000000U #define GR1553B_BMTTC_TRES_GET( _reg ) \ - ( ( ( _reg ) & GR1553B_BMTTC_TRES_MASK ) >> \ - GR1553B_BMTTC_TRES_SHIFT ) -#define GR1553B_BMTTC_TRES_SET( _reg, _val ) \ + ( ( ( _reg ) & GR1553B_BMTTC_TRES_MASK ) >> GR1553B_BMTTC_TRES_SHIFT ) +#define GR1553B_BMTTC_TRES_SET( _reg, _val ) \ ( ( ( _reg ) & ~GR1553B_BMTTC_TRES_MASK ) | \ - ( ( ( _val ) << GR1553B_BMTTC_TRES_SHIFT ) & \ - GR1553B_BMTTC_TRES_MASK ) ) + ( ( ( _val ) << GR1553B_BMTTC_TRES_SHIFT ) & GR1553B_BMTTC_TRES_MASK ) ) #define GR1553B_BMTTC_TRES( _val ) \ - ( ( ( _val ) << GR1553B_BMTTC_TRES_SHIFT ) & \ - GR1553B_BMTTC_TRES_MASK ) + ( ( ( _val ) << GR1553B_BMTTC_TRES_SHIFT ) & GR1553B_BMTTC_TRES_MASK ) #define GR1553B_BMTTC_TVAL_SHIFT 0 -#define GR1553B_BMTTC_TVAL_MASK 0xffffffU +#define GR1553B_BMTTC_TVAL_MASK 0xffffffU #define GR1553B_BMTTC_TVAL_GET( _reg ) \ - ( ( ( _reg ) & GR1553B_BMTTC_TVAL_MASK ) >> \ - GR1553B_BMTTC_TVAL_SHIFT ) -#define GR1553B_BMTTC_TVAL_SET( _reg, _val ) \ + ( ( ( _reg ) & GR1553B_BMTTC_TVAL_MASK ) >> GR1553B_BMTTC_TVAL_SHIFT ) +#define GR1553B_BMTTC_TVAL_SET( _reg, _val ) \ ( ( ( _reg ) & ~GR1553B_BMTTC_TVAL_MASK ) | \ - ( ( ( _val ) << GR1553B_BMTTC_TVAL_SHIFT ) & \ - GR1553B_BMTTC_TVAL_MASK ) ) + ( ( ( _val ) << GR1553B_BMTTC_TVAL_SHIFT ) & GR1553B_BMTTC_TVAL_MASK ) ) #define GR1553B_BMTTC_TVAL( _val ) \ - ( ( ( _val ) << GR1553B_BMTTC_TVAL_SHIFT ) & \ - GR1553B_BMTTC_TVAL_MASK ) + ( ( ( _val ) << GR1553B_BMTTC_TVAL_SHIFT ) & GR1553B_BMTTC_TVAL_MASK ) /** @} */ diff --git a/bsps/include/grlib/gr1553b.h b/bsps/include/grlib/gr1553b.h index 178a0ae19d..73330fbd53 100644 --- a/bsps/include/grlib/gr1553b.h +++ b/bsps/include/grlib/gr1553b.h @@ -50,58 +50,58 @@ extern "C" { /* The GR1553B registers */ struct gr1553b_regs { - /* Common Registers */ - volatile uint32_t irq; /* 0x00 IRQ register */ - volatile uint32_t imask; /* 0x04 IRQ enable mask */ - int unused0[(0x10-0x08)/4]; - volatile uint32_t hwcfg; /* 0x10 HW config register */ + /* Common Registers */ + volatile uint32_t irq; /* 0x00 IRQ register */ + volatile uint32_t imask; /* 0x04 IRQ enable mask */ + int unused0[ ( 0x10 - 0x08 ) / 4 ]; + volatile uint32_t hwcfg; /* 0x10 HW config register */ - int unused1[(0x40-0x14)/4]; /* Padding */ + int unused1[ ( 0x40 - 0x14 ) / 4 ]; /* Padding */ - /* BC Registers */ - volatile uint32_t bc_stat; /* 0x40 BC status */ - volatile uint32_t bc_ctrl; /* 0x44 BC Action register */ - volatile uint32_t bc_bd; /* 0x48 BC transfer list pointer */ - volatile uint32_t bc_abd; /* 0x4c BC async list pointer */ - volatile uint32_t bc_timer; /* 0x50 BC timer register */ - volatile uint32_t bc_wake; /* 0x54 BC wakeup control register */ - volatile uint32_t bc_irqptr; /* 0x58 BC transfer IRQ pointer */ - volatile uint32_t bc_busmsk; /* 0x5C BC per-RT bus mask register */ + /* BC Registers */ + volatile uint32_t bc_stat; /* 0x40 BC status */ + volatile uint32_t bc_ctrl; /* 0x44 BC Action register */ + volatile uint32_t bc_bd; /* 0x48 BC transfer list pointer */ + volatile uint32_t bc_abd; /* 0x4c BC async list pointer */ + volatile uint32_t bc_timer; /* 0x50 BC timer register */ + volatile uint32_t bc_wake; /* 0x54 BC wakeup control register */ + volatile uint32_t bc_irqptr; /* 0x58 BC transfer IRQ pointer */ + volatile uint32_t bc_busmsk; /* 0x5C BC per-RT bus mask register */ - int unused2[(0x68-0x60)/4]; /* Padding */ + int unused2[ ( 0x68 - 0x60 ) / 4 ]; /* Padding */ - volatile uint32_t bc_slot; /* 0x68 BC Current BD pointer */ - volatile uint32_t bc_aslot; /* 0x6c BC Current async BD pointer */ + volatile uint32_t bc_slot; /* 0x68 BC Current BD pointer */ + volatile uint32_t bc_aslot; /* 0x6c BC Current async BD pointer */ - int unused3[(0x80-0x70)/4]; /* Padding */ + int unused3[ ( 0x80 - 0x70 ) / 4 ]; /* Padding */ - /* RT Registers */ - volatile uint32_t rt_stat; /* 0x80 RT status */ - volatile uint32_t rt_cfg; /* 0x84 RT config register */ - volatile uint32_t rt_stat2; /* 0x88 RT bus status bits */ - volatile uint32_t rt_statw; /* 0x8c RT status words */ - volatile uint32_t rt_sync; /* 0x90 RT bus synchronize */ - volatile uint32_t rt_tab; /* 0x94 RT subaddress table base */ - volatile uint32_t rt_mcctrl; /* 0x98 RT valid mode code mask */ - int unused4[(0xa4-0x9c)/4]; - volatile uint32_t rt_ttag; /* 0xa4 RT time tag register */ - int unused5; /* 0xa8 RESERVED */ - volatile uint32_t rt_evsz; /* 0xac RT event log end pointer */ - volatile uint32_t rt_evlog; /* 0xb0 RT event log position */ - volatile uint32_t rt_evirq; /* 0xb4 RT event log IRQ position */ + /* RT Registers */ + volatile uint32_t rt_stat; /* 0x80 RT status */ + volatile uint32_t rt_cfg; /* 0x84 RT config register */ + volatile uint32_t rt_stat2; /* 0x88 RT bus status bits */ + volatile uint32_t rt_statw; /* 0x8c RT status words */ + volatile uint32_t rt_sync; /* 0x90 RT bus synchronize */ + volatile uint32_t rt_tab; /* 0x94 RT subaddress table base */ + volatile uint32_t rt_mcctrl; /* 0x98 RT valid mode code mask */ + int unused4[ ( 0xa4 - 0x9c ) / 4 ]; + volatile uint32_t rt_ttag; /* 0xa4 RT time tag register */ + int unused5; /* 0xa8 RESERVED */ + volatile uint32_t rt_evsz; /* 0xac RT event log end pointer */ + volatile uint32_t rt_evlog; /* 0xb0 RT event log position */ + volatile uint32_t rt_evirq; /* 0xb4 RT event log IRQ position */ - int unused6[(0xc0-0xb8)/4]; /* Padding */ + int unused6[ ( 0xc0 - 0xb8 ) / 4 ]; /* Padding */ - /* BM Registers */ - volatile uint32_t bm_stat; /* 0xc0 BM status */ - volatile uint32_t bm_ctrl; /* 0xc4 BM control register */ - volatile uint32_t bm_adr; /* 0xc8 BM address filter */ - volatile uint32_t bm_subadr; /* 0xcc BM subaddress filter */ - volatile uint32_t bm_mc; /* 0xd0 BM mode code filter */ - volatile uint32_t bm_start; /* 0xd4 BM log start address */ - volatile uint32_t bm_end; /* 0xd8 BM log size/alignment mask */ - volatile uint32_t bm_pos; /* 0xdc BM log position */ - volatile uint32_t bm_ttag; /* 0xe0 BM time tag register */ + /* BM Registers */ + volatile uint32_t bm_stat; /* 0xc0 BM status */ + volatile uint32_t bm_ctrl; /* 0xc4 BM control register */ + volatile uint32_t bm_adr; /* 0xc8 BM address filter */ + volatile uint32_t bm_subadr; /* 0xcc BM subaddress filter */ + volatile uint32_t bm_mc; /* 0xd0 BM mode code filter */ + volatile uint32_t bm_start; /* 0xd4 BM log start address */ + volatile uint32_t bm_end; /* 0xd8 BM log size/alignment mask */ + volatile uint32_t bm_pos; /* 0xdc BM log position */ + volatile uint32_t bm_ttag; /* 0xe0 BM time tag register */ }; #define GR1553BC_KEY 0x15520000 @@ -109,277 +109,276 @@ struct gr1553b_regs { /* IRQ Definitions */ #define GR1553BC_IRQLOG_SIZE 64 -#define GR1553BC_IRQLOG_CNT (GR1553BC_IRQLOG_SIZE/sizeof(uint32_t)) +#define GR1553BC_IRQLOG_CNT ( GR1553BC_IRQLOG_SIZE / sizeof( uint32_t ) ) /*** IRQ Flag Register ***/ -#define GR1553B_IRQ_BCEV_BIT 0 -#define GR1553B_IRQ_BCD_BIT 1 -#define GR1553B_IRQ_BCWK_BIT 2 -#define GR1553B_IRQ_RTEV_BIT 8 -#define GR1553B_IRQ_RTD_BIT 9 -#define GR1553B_IRQ_RTTE_BIT 10 -#define GR1553B_IRQ_BMD_BIT 16 -#define GR1553B_IRQ_BMTOF_BIT 17 +#define GR1553B_IRQ_BCEV_BIT 0 +#define GR1553B_IRQ_BCD_BIT 1 +#define GR1553B_IRQ_BCWK_BIT 2 +#define GR1553B_IRQ_RTEV_BIT 8 +#define GR1553B_IRQ_RTD_BIT 9 +#define GR1553B_IRQ_RTTE_BIT 10 +#define GR1553B_IRQ_BMD_BIT 16 +#define GR1553B_IRQ_BMTOF_BIT 17 -#define GR1553B_IRQ_BCEV (1<minor[LAST]->next */ extern void gr1553bc_list_link_major( - struct gr1553bc_major *major, - struct gr1553bc_major *next - ); + struct gr1553bc_major *major, + struct gr1553bc_major *next +); /* Link in a Major frame into a BC list. * Calls gr1553bc_list_link_major() to link major frame with major-1 and * major+1. If ending or starting major frame the frame is wrapped around. */ extern int gr1553bc_list_set_major( - struct gr1553bc_list *list, - struct gr1553bc_major *major, - int no); + struct gr1553bc_list *list, + struct gr1553bc_major *major, + int no +); /* Calculate the size required in the descriptor table by one minor frame. */ -extern int gr1553bc_minor_table_size(struct gr1553bc_minor *minor); +extern int gr1553bc_minor_table_size( struct gr1553bc_minor *minor ); /* Calculate the size required for the descriptor table. */ -extern int gr1553bc_list_table_size(struct gr1553bc_list *list); +extern int gr1553bc_list_table_size( struct gr1553bc_list *list ); /* Allocate an empty descriptor table from list description suitable for * the BC given by 'bc'. @@ -334,45 +334,43 @@ extern int gr1553bc_list_table_size(struct gr1553bc_list *list); * is given as HW address (used with AMBA-over-PCI to * to specify RAM location on PCI board). */ -extern int gr1553bc_list_table_alloc - ( - struct gr1553bc_list *list, - void *bdtab_custom - ); +extern int gr1553bc_list_table_alloc( + struct gr1553bc_list *list, + void *bdtab_custom +); /* Free descriptor table allocated with gr1553bc_list_table_alloc() */ -extern void gr1553bc_list_table_free(struct gr1553bc_list *list); +extern void gr1553bc_list_table_free( struct gr1553bc_list *list ); /* Build an empty descriptor table from list description, * the minor frames will be linked together. */ -extern int gr1553bc_list_table_build(struct gr1553bc_list *list); +extern int gr1553bc_list_table_build( struct gr1553bc_list *list ); /* Major Frame */ struct gr1553bc_major { - struct gr1553bc_major *next; /* Next Major Frame */ - struct gr1553bc_major_cfg *cfg; /* User Config of Major frame */ - struct gr1553bc_minor *minors[1]; /* Minor frames */ + struct gr1553bc_major *next; /* Next Major Frame */ + struct gr1553bc_major_cfg *cfg; /* User Config of Major frame */ + struct gr1553bc_minor *minors[ 1 ]; /* Minor frames */ }; /* Minor Frame */ struct gr1553bc_minor { - struct gr1553bc_minor *next; /* Next Minor Frame */ - struct gr1553bc_minor_cfg *cfg; /* User Config of Minor frame */ - uint32_t alloc; /* Descripts allocated */ + struct gr1553bc_minor *next; /* Next Minor Frame */ + struct gr1553bc_minor_cfg *cfg; /* User Config of Minor frame */ + uint32_t alloc; /* Descripts allocated */ - /* Note: THIS POINTER MUST BE ALIGNED ON A 128-bit BOUNDARY */ - union gr1553bc_bd *bds; /* Descriptors for this minor frame (CPU ADRS)*/ + /* Note: THIS POINTER MUST BE ALIGNED ON A 128-bit BOUNDARY */ + union gr1553bc_bd *bds; /* Descriptors for this minor frame (CPU ADRS)*/ }; /* Alloc a Major/Minor frame skeleton according to the configuration structure. * The descriptor table is not allocated. */ -extern int gr1553bc_major_alloc_skel - ( - struct gr1553bc_major **major, - struct gr1553bc_major_cfg *cfg - ); +extern int gr1553bc_major_alloc_skel( + struct gr1553bc_major **major, + struct gr1553bc_major_cfg *cfg +); /* Unique Message/Descriptor ID. Can be used to identify a Major or Minor * Frame, or a Slot. @@ -381,36 +379,34 @@ extern int gr1553bc_major_alloc_skel * - If slot_num is 0xff, the ID identifies a Minor Frame * - If non of the above is true, the ID identifies a specific Slot */ -#define GR1553BC_ID(major_num, minor_num, slot_num) \ - ((((major_num)<<16)&0xff0000) | (((minor_num)<<8)&0xff00) | \ - ((slot_num) & 0xff)) -#define GR1553BC_MINOR_ID(major_num, minor_num) \ - GR1553BC_ID(major_num, minor_num, 0xff) -#define GR1553BC_MAJOR_ID(major_num) \ - GR1553BC_ID(major_num, 0xff, 0xff) +#define GR1553BC_ID( major_num, minor_num, slot_num ) \ + ( ( ( ( major_num ) << 16 ) & 0xff0000 ) | \ + ( ( ( minor_num ) << 8 ) & 0xff00 ) | ( ( slot_num ) & 0xff ) ) +#define GR1553BC_MINOR_ID( major_num, minor_num ) \ + GR1553BC_ID( major_num, minor_num, 0xff ) +#define GR1553BC_MAJOR_ID( major_num ) GR1553BC_ID( major_num, 0xff, 0xff ) -#define GR1553BC_MAJID_FROM_ID(mid) (((mid) >> 16) & 0xff) -#define GR1553BC_MINID_FROM_ID(mid) (((mid) >> 8) & 0xff) -#define GR1553BC_SLOTID_FROM_ID(mid) ((mid) & 0xff) -#define GR1553BC_ID_SET_SLOT(mid, slot_num) (((mid) & ~0xff) | ((slot_num) & 0xff)) +#define GR1553BC_MAJID_FROM_ID( mid ) ( ( ( mid ) >> 16 ) & 0xff ) +#define GR1553BC_MINID_FROM_ID( mid ) ( ( ( mid ) >> 8 ) & 0xff ) +#define GR1553BC_SLOTID_FROM_ID( mid ) ( ( mid ) & 0xff ) +#define GR1553BC_ID_SET_SLOT( mid, slot_num ) \ + ( ( ( mid ) & ~0xff ) | ( ( slot_num ) & 0xff ) ) -extern struct gr1553bc_major *gr1553bc_major_from_id - ( - struct gr1553bc_list *list, - int mid - ); +extern struct gr1553bc_major *gr1553bc_major_from_id( + struct gr1553bc_list *list, + int mid +); -extern struct gr1553bc_minor *gr1553bc_minor_from_id - ( - struct gr1553bc_list *list, - int mid - ); +extern struct gr1553bc_minor *gr1553bc_minor_from_id( + struct gr1553bc_list *list, + int mid +); /* Get free time left of minor frame identified by MID 'mid' */ -extern int gr1553bc_list_freetime(struct gr1553bc_list *list, int mid); +extern int gr1553bc_list_freetime( struct gr1553bc_list *list, int mid ); /* Get free time left of minor frame */ -extern int gr1553bc_minor_freetime(struct gr1553bc_minor *minor); +extern int gr1553bc_minor_freetime( struct gr1553bc_minor *minor ); /* Allocate a time slot on a minor frame, major/minor frame is identified * by MID. The 'mid' is a input/ouput parameter, the resulting slot taken @@ -425,27 +421,27 @@ extern int gr1553bc_minor_freetime(struct gr1553bc_minor *minor); * MID points to a bad major/minor or major/minor/slot. */ extern int gr1553bc_slot_alloc( - struct gr1553bc_list *list, - int *mid, - int timeslot, - union gr1553bc_bd **bd - ); + struct gr1553bc_list *list, + int *mid, + int timeslot, + union gr1553bc_bd **bd +); /* Same as gr1553bc_slot_alloc but identifies a minor instead of list. * The major/minor part of MID is ignored. */ extern int gr1553bc_slot_alloc2( - struct gr1553bc_minor *minor, - int *mid, - int timeslot, - union gr1553bc_bd **bd - ); + struct gr1553bc_minor *minor, + int *mid, + int timeslot, + union gr1553bc_bd **bd +); /* Free message slot and the time associated with it. The time taken by the * message slot is added to the END TIME descriptor, if managed by the driver * for this minor frame. The descriptor will be */ -extern int gr1553bc_slot_free(struct gr1553bc_list *list, int mid); -extern int gr1553bc_slot_free2(struct gr1553bc_minor *minor, int mid); +extern int gr1553bc_slot_free( struct gr1553bc_list *list, int mid ); +extern int gr1553bc_slot_free2( struct gr1553bc_minor *minor, int mid ); /* Find MID from Descriptor pointer * @@ -466,61 +462,54 @@ extern int gr1553bc_slot_free2(struct gr1553bc_minor *minor, int mid); * \param async OUT: Function will store non-zero value if BD belogs to * async list. */ -extern int gr1553bc_mid_from_bd( - union gr1553bc_bd *bd, - int *mid, - int *async - ); +extern int gr1553bc_mid_from_bd( union gr1553bc_bd *bd, int *mid, int *async ); /********** TRANSFER DESCRIPTOR MANIPULATION **********/ /* Get pointer to descriptor entry from MID. */ -extern union gr1553bc_bd *gr1553bc_slot_bd - ( - struct gr1553bc_list *list, - int mid - ); +extern union gr1553bc_bd *gr1553bc_slot_bd( + struct gr1553bc_list *list, + int mid +); /* IRQ function */ -typedef void (*bcirq_func_t)(union gr1553bc_bd *bd, void *data); +typedef void ( *bcirq_func_t )( union gr1553bc_bd *bd, void *data ); /* Create unconditional IRQ customly defined location. * The IRQ is disabled, enable it with gr1553bc_slot_irq_enable(). */ -extern int gr1553bc_slot_irq_prepare - ( - struct gr1553bc_list *list, - int mid, - bcirq_func_t func, - void *data - ); +extern int gr1553bc_slot_irq_prepare( + struct gr1553bc_list *list, + int mid, + bcirq_func_t func, + void *data +); /* Enable previously prepared unconditional IRQ */ -extern int gr1553bc_slot_irq_enable(struct gr1553bc_list *list, int mid); +extern int gr1553bc_slot_irq_enable( struct gr1553bc_list *list, int mid ); /* Disable unconditional IRQ point, changed to unconditional JUMP * to descriptor following. * After disabling it it can be enabled again, or freed. */ -extern int gr1553bc_slot_irq_disable(struct gr1553bc_list *list, int mid); +extern int gr1553bc_slot_irq_disable( struct gr1553bc_list *list, int mid ); /* Create custom jump to descriptor, conditional or unconditional, see * hardware manual for conditions. * * set conditional to GR1553BC_UNCOND_JMP for unconditional jump. */ -extern int gr1553bc_slot_jump - ( - struct gr1553bc_list *list, - int mid, - uint32_t condition, - int to_mid - ); +extern int gr1553bc_slot_jump( + struct gr1553bc_list *list, + int mid, + uint32_t condition, + int to_mid +); /* Create a dummy transfer, paused until external trigger is set. The * Slot is will have the dummy bit set, no transfer will take place. */ -extern int gr1553bc_slot_exttrig(struct gr1553bc_list *list, int mid); +extern int gr1553bc_slot_exttrig( struct gr1553bc_list *list, int mid ); /* Create a transfer on a previous allocated descriptor. It is assumed * that the descriptor has been initialized empty before calling this @@ -559,25 +548,27 @@ extern int gr1553bc_slot_exttrig(struct gr1553bc_list *list, int mid); * 1553 core. This is an option only for AMBA-over-PCI. */ extern int gr1553bc_slot_transfer( - struct gr1553bc_list *list, - int mid, - int options, - int tt, - uint16_t *dptr); + struct gr1553bc_list *list, + int mid, + int options, + int tt, + uint16_t *dptr +); /* Remove or set dummy bit of a transfer descriptor * Bit31 of *dummy is written to the dummy bit, the * old descriptor value is stored into *dummy. */ extern int gr1553bc_slot_dummy( - struct gr1553bc_list *list, - int mid, - unsigned int *dummy); + struct gr1553bc_list *list, + int mid, + unsigned int *dummy +); /* Make a slot empty (BC will not generate bus transfers), time slot * allocated is untouched (if assigned). */ -extern int gr1553bc_slot_empty(struct gr1553bc_list *list, int mid); +extern int gr1553bc_slot_empty( struct gr1553bc_list *list, int mid ); /* Transfer descriptor status and/or update Transfer descriptor data pointer. * @@ -597,10 +588,11 @@ extern int gr1553bc_slot_empty(struct gr1553bc_list *list, int mid); * 1553 core. This is an option only for AMBA-over-PCI. */ extern int gr1553bc_slot_update( - struct gr1553bc_list *list, - int mid, - uint16_t *dptr, - unsigned int *stat); + struct gr1553bc_list *list, + int mid, + uint16_t *dptr, + unsigned int *stat +); /* Modify a transfer descriptor in any way, * @@ -608,116 +600,121 @@ extern int gr1553bc_slot_update( * bit[N=0..3]: 1 = set BD wordN according to argument wordN, * 0 = do not modify BD wordN */ -extern int gr1553bc_slot_raw - ( - struct gr1553bc_list *list, - int mid, - unsigned int flags, - uint32_t word0, - uint32_t word1, - uint32_t word2, - uint32_t word3 - ); - +extern int gr1553bc_slot_raw( + struct gr1553bc_list *list, + int mid, + unsigned int flags, + uint32_t word0, + uint32_t word1, + uint32_t word2, + uint32_t word3 +); /***** Macros to create BC Transfer Types (tt) for gr1553bc_slot_transfer() *****/ /* WRITE TO RT (BC-to-RT) */ -#define GR1553BC_BC2RT(rtadr, subadr, word_count) \ - ((rtadr<<11) | (subadr<<5) | (0x1f<<21) | (0<<10) | \ - ((word_count>=32) ? 0 : word_count)) +#define GR1553BC_BC2RT( rtadr, subadr, word_count ) \ + ( ( rtadr << 11 ) | ( subadr << 5 ) | ( 0x1f << 21 ) | ( 0 << 10 ) | \ + ( ( word_count >= 32 ) ? 0 : word_count ) ) /* READ FROM RT (RT-to-BC) */ -#define GR1553BC_RT2BC(rtadr, subadr, word_count) \ - ((rtadr<<11) | (subadr<<5) | (0x1f<<21) | (1<<10) | \ - ((word_count>=32) ? 0 : word_count)) +#define GR1553BC_RT2BC( rtadr, subadr, word_count ) \ + ( ( rtadr << 11 ) | ( subadr << 5 ) | ( 0x1f << 21 ) | ( 1 << 10 ) | \ + ( ( word_count >= 32 ) ? 0 : word_count ) ) /* RT(TX) WRITE TO RT(RX) (RT-to-RT) */ -#define GR1553BC_RT2RT(tx_rtadr, tx_subadr, rx_rtadr, rx_subadr, word_count) \ - ((rx_rtadr<<11) | (rx_subadr<<5) | \ - (tx_rtadr<<21) | (tx_subadr<<16) | \ - (0<<10) | \ - ((word_count>=32) ? 0 : word_count)) +#define GR1553BC_RT2RT( \ + tx_rtadr, \ + tx_subadr, \ + rx_rtadr, \ + rx_subadr, \ + word_count \ +) \ + ( ( rx_rtadr << 11 ) | ( rx_subadr << 5 ) | ( tx_rtadr << 21 ) | \ + ( tx_subadr << 16 ) | ( 0 << 10 ) | \ + ( ( word_count >= 32 ) ? 0 : word_count ) ) /* Mode command without data. (BC-to-RT) * Mode code: 0,1,2,3,4,5,6,7 or 8. */ -#define GR1553BC_MC_NODATA(rtadr, modecode) \ - ((rtadr<<11) | (0x1f<<5) | (0x1f<<21) | \ - (modecode<<0) | (1<<10)) +#define GR1553BC_MC_NODATA( rtadr, modecode ) \ + ( ( rtadr << 11 ) | ( 0x1f << 5 ) | ( 0x1f << 21 ) | ( modecode << 0 ) | \ + ( 1 << 10 ) ) /* Mode command with 4 byte data (RT-to-BC) * Mode code: 16, 18 or 19. */ -#define GR1553BC_MC_RT2BC(rtadr, modecode) \ - ((rtadr<<11) | (0x1f<<5) | (0x1f<<21) | \ - (modecode<<0) | (1<<10)) +#define GR1553BC_MC_RT2BC( rtadr, modecode ) \ + ( ( rtadr << 11 ) | ( 0x1f << 5 ) | ( 0x1f << 21 ) | ( modecode << 0 ) | \ + ( 1 << 10 ) ) /* Mode command with 4 byte data (BC-to-RT) * Mode code: 17, 20 or 21. */ -#define GR1553BC_MC_BC2RT(rtadr, modecode) \ - ((rtadr<<11) | (0x1f<<5) | (0x1f<<21) | \ - (modecode<<0) | (0<<10)) +#define GR1553BC_MC_BC2RT( rtadr, modecode ) \ + ( ( rtadr << 11 ) | ( 0x1f << 5 ) | ( 0x1f << 21 ) | ( modecode << 0 ) | \ + ( 0 << 10 ) ) /* Broadcast to all RTs, to a specific subaddress (BC-to-RTs) */ -#define GR1553BC_BC_BC2RT(subadr, word_count) \ - ((0x1f<<11) | (subadr<<5) | (0x1f<<21) | \ - (0<<10) | \ - ((word_count>=32) ? 0 : word_count)) +#define GR1553BC_BC_BC2RT( subadr, word_count ) \ + ( ( 0x1f << 11 ) | ( subadr << 5 ) | ( 0x1f << 21 ) | ( 0 << 10 ) | \ + ( ( word_count >= 32 ) ? 0 : word_count ) ) /* Request RT to broadcast to all RTs, to a specific subaddress (RT-to-RTs) */ -#define GR1553BC_BC_RT2RT(tx_rtadr, tx_subadr, rx_subadr, word_count) \ - ((0x1f<<11) | (rx_subadr<<5) | \ - (tx_rtadr<<21) | (tx_subadr<<16) | \ - (0<<10) | \ - ((word_count>=32) ? 0 : word_count)) +#define GR1553BC_BC_RT2RT( tx_rtadr, tx_subadr, rx_subadr, word_count ) \ + ( ( 0x1f << 11 ) | ( rx_subadr << 5 ) | ( tx_rtadr << 21 ) | \ + ( tx_subadr << 16 ) | ( 0 << 10 ) | \ + ( ( word_count >= 32 ) ? 0 : word_count ) ) /* Broadcast mode command without data (BC-to-RTs) * Mode code: 1,3,4,5,6,7 or 8 */ -#define GR1553BC_BC_MC_NODATA(modecode) \ - ((0x1f<<11) | (0x1f<<5) | (0x1f<<21) | \ - ((modecode)<<0) | (1<<10)) +#define GR1553BC_BC_MC_NODATA( modecode ) \ + ( ( 0x1f << 11 ) | ( 0x1f << 5 ) | ( 0x1f << 21 ) | ( ( modecode ) << 0 ) | \ + ( 1 << 10 ) ) /* Broadcast mode command with 4 byte data (BC-to-RTs) * Mode code: 17, 20 or 21 */ -#define GR1553BC_BC_MC_BC2RT(modecode) \ - ((0x1f<<11) | (0x1f<<5) | (0x1f<<21) | \ - ((modecode)<<0) | (0<<10)) - +#define GR1553BC_BC_MC_BC2RT( modecode ) \ + ( ( 0x1f << 11 ) | ( 0x1f << 5 ) | ( 0x1f << 21 ) | ( ( modecode ) << 0 ) | \ + ( 0 << 10 ) ) /***** Macros to create BC options (options) for gr1553bc_slot_transfer() *****/ /* Dummy (BC does no bus trasactions) */ -#define GR1553BC_OPT_DUMMY (1<<1) +#define GR1553BC_OPT_DUMMY ( 1 << 1 ) /* Retry modes */ -#define GR1553BC_RETRY_SAME 0x0 /* Retry on the same bus only */ -#define GR1553BC_RETRY_ALTER 0x1 /* Retry alternating on both busses */ -#define GR1553BC_RETRY_ATTEMPT 0x2 /* Many attepts first on original +#define GR1553BC_RETRY_SAME 0x0 /* Retry on the same bus only */ +#define GR1553BC_RETRY_ALTER 0x1 /* Retry alternating on both busses */ +#define GR1553BC_RETRY_ATTEMPT \ + 0x2 /* Many attepts first on original * bus then on other bus */ /* Number of retires supported */ -#define GR1553BC_RETRY_CNT_MAX 6 +#define GR1553BC_RETRY_CNT_MAX 6 /* Dummy bit: No transfer * Bus bit: 0=A, 1=B * Exttrig bit: Wait for external trigger (used for timesync) * Exclusive bit: 1=Don't allow other messages in this time slot. */ -#define GR1553BC_OPTIONS(dummy, exttrig, exclusive, retrymode, nretry, bus) \ - ((((exttrig) & 0x1) << 30) | (((exclusive) & 0x1) << 29) | \ - ((retrymode) << 23) | ((nretry) << 20) | \ - ((bus) & 1) | (((dummy) & 0x1) << 1)) +#define GR1553BC_OPTIONS( dummy, exttrig, exclusive, retrymode, nretry, bus ) \ + ( ( ( ( exttrig ) & 0x1 ) << 30 ) | ( ( ( exclusive ) & 0x1 ) << 29 ) | \ + ( ( retrymode ) << 23 ) | ( ( nretry ) << 20 ) | ( ( bus ) & 1 ) | \ + ( ( ( dummy ) & 0x1 ) << 1 ) ) -#define GR1553BC_OPTIONS_BUSA GR1553BC_OPTIONS(0,0,0,GR1553BC_RETRY_SAME,0,0) -#define GR1553BC_OPTIONS_BUSB GR1553BC_OPTIONS(0,0,0,GR1553BC_RETRY_SAME,0,1) -#define GR1553BC_OPTIONS_BUSA_DUM GR1553BC_OPTIONS(1,0,0,GR1553BC_RETRY_SAME,0,0) -#define GR1553BC_OPTIONS_BUSB_DUM GR1553BC_OPTIONS(1,0,0,GR1553BC_RETRY_SAME,0,1) +#define GR1553BC_OPTIONS_BUSA \ + GR1553BC_OPTIONS( 0, 0, 0, GR1553BC_RETRY_SAME, 0, 0 ) +#define GR1553BC_OPTIONS_BUSB \ + GR1553BC_OPTIONS( 0, 0, 0, GR1553BC_RETRY_SAME, 0, 1 ) +#define GR1553BC_OPTIONS_BUSA_DUM \ + GR1553BC_OPTIONS( 1, 0, 0, GR1553BC_RETRY_SAME, 0, 0 ) +#define GR1553BC_OPTIONS_BUSB_DUM \ + GR1553BC_OPTIONS( 1, 0, 0, GR1553BC_RETRY_SAME, 0, 1 ) /* Show parts of a list - this is for debugging only */ -extern void gr1553bc_show_list(struct gr1553bc_list *list, int options); +extern void gr1553bc_show_list( struct gr1553bc_list *list, int options ); #ifdef __cplusplus } diff --git a/bsps/include/grlib/gr1553bm.h b/bsps/include/grlib/gr1553bm.h index 6cb15fd1e5..b5413f65b2 100644 --- a/bsps/include/grlib/gr1553bm.h +++ b/bsps/include/grlib/gr1553bm.h @@ -35,11 +35,11 @@ extern "C" { #endif /* Register GR1553B driver needed by BM driver */ -extern void gr1553bm_register(void); +extern void gr1553bm_register( void ); struct gr1553bm_entry { - uint32_t time; /* bit31=1, bit 30=0 */ - uint32_t data; /* bit31=0, bit 30=0 */ + uint32_t time; /* bit31=1, bit 30=0 */ + uint32_t data; /* bit31=0, bit 30=0 */ }; #define GR1553BM_ERROPTS_MANL 0x02 @@ -56,29 +56,28 @@ struct gr1553bm_entry { * \param nentires Number of entries to be processed. * \param data Custom Data (set by config) */ -typedef int (*bmcopy_func_t)( - unsigned int dst, - struct gr1553bm_entry *src, - int nentries, - void *data - ); +typedef int ( *bmcopy_func_t )( + unsigned int dst, + struct gr1553bm_entry *src, + int nentries, + void *data +); /* IRQ function callback, called on BM DMA error */ -typedef void (*bmisr_func_t)(void *bm, void *data); +typedef void ( *bmisr_func_t )( void *bm, void *data ); /* BM driver configuration */ struct gr1553bm_config { + /*** Time options ***/ - /*** Time options ***/ - - /* 8-bit time resolution, the BM will update the time according + /* 8-bit time resolution, the BM will update the time according * to this setting. 0 will make the time tag be of highest * resolution (no division), 1 will make the BM increment the * time tag once for two time ticks (div with 2), etc. */ - uint8_t time_resolution; + uint8_t time_resolution; - /* Enable Time Overflow IRQ handling. Setting this to 1 + /* Enable Time Overflow IRQ handling. Setting this to 1 * makes the driver to update the 64-bit time by it self, * it will use time overflow IRQ to detect when the 64-bit * time counter must be incremented. @@ -87,75 +86,69 @@ struct gr1553bm_config { * gr1553bm_time() regularly, it must be called more often * than the time overflows to avoid an incorrect time. */ - int time_ovf_irq; + int time_ovf_irq; + /*** Filtering options ***/ - - /*** Filtering options ***/ - - /* Bus error log options + /* Bus error log options * * bit0,4-31 = reserved, set to zero * Bit1 = Enables logging of Invalid mode code errors * Bit2 = Enables logging of Unexpected Data errors * Bit3 = Enables logging of Manchester/parity errors */ - unsigned int filt_error_options; + unsigned int filt_error_options; - /* RT Address filtering bit mask. Each bit enables (if set) + /* RT Address filtering bit mask. Each bit enables (if set) * logging of a certain RT sub address. Bit 31 enables logging * of broadcast messages. */ - unsigned int filt_rtadr; + unsigned int filt_rtadr; - /* RT Subaddress filtering bit mask, bit definition: + /* RT Subaddress filtering bit mask, bit definition: * 31: Enables logging of mode commands on subadr 31 * 1..30: BitN enables/disables logging of RT subadr N * 0: Enables logging of mode commands on subadr 0 */ - unsigned int filt_subadr; + unsigned int filt_subadr; - /* Mode code Filter, is written into "BM RT Mode code filter" + /* Mode code Filter, is written into "BM RT Mode code filter" * register, please see hardware manual for bit declarations. */ - unsigned int filt_mc; + unsigned int filt_mc; + /*** Buffer options ***/ - - /*** Buffer options ***/ - - /* Size of buffer in bytes, must be aligned to 8-byte + /* Size of buffer in bytes, must be aligned to 8-byte * The size is limited to max 4Mb. */ - unsigned int buffer_size; + unsigned int buffer_size; - /* Custom buffer, must be aligned to 8-byte and be of buffer_size + /* Custom buffer, must be aligned to 8-byte and be of buffer_size * length. If NULL dynamic memory allocation is used. */ - void *buffer_custom; + void *buffer_custom; - /* Custom Copy function, may be used to implement a more + /* Custom Copy function, may be used to implement a more * effective way of copying the DMA buffer. For example * the DMA log may need to be compressed before copied * onto a storage, this function can be used to avoid an * extra copy. */ - bmcopy_func_t copy_func; + bmcopy_func_t copy_func; - /* Optional Custom Data passed on to copy_func() */ - void *copy_func_arg; + /* Optional Custom Data passed on to copy_func() */ + void *copy_func_arg; + /*** Interrupt options ***/ - - /*** Interrupt options ***/ - - /* Custom DMA error function, note that this function is called + /* Custom DMA error function, note that this function is called * from Interrupt Context. Set to NULL to disable this callback. */ - bmisr_func_t dma_error_isr; + bmisr_func_t dma_error_isr; - /* Optional Custom Data passed on to dma_error_isr() */ - void *dma_error_arg; + /* Optional Custom Data passed on to dma_error_isr() */ + void *dma_error_arg; }; /* Open BM device by instance number (minor) @@ -163,16 +156,16 @@ struct gr1553bm_config { * The return value is used as input parameter in all other function calls * in the A */ -extern void *gr1553bm_open(int minor); +extern void *gr1553bm_open( int minor ); /* Close previously opened Bm device */ -extern void gr1553bm_close(void *bm); +extern void gr1553bm_close( void *bm ); /* Configure the BM driver before starting */ -extern int gr1553bm_config(void *bm, struct gr1553bm_config *cfg); +extern int gr1553bm_config( void *bm, struct gr1553bm_config *cfg ); /* Start logging */ -extern int gr1553bm_start(void *bm); +extern int gr1553bm_start( void *bm ); /* Get 64-bit 1553 Time. Low 24-bit time is acquired from BM hardware, * the MSB is taken from a software counter internal to the driver. The @@ -187,18 +180,18 @@ extern int gr1553bm_start(void *bm); * * Update software time counters and return the current time. */ -extern void gr1553bm_time(void *bm, uint64_t *time); +extern void gr1553bm_time( void *bm, uint64_t *time ); /* Return zero when logging has not been started, non-zero when logging * has been started */ -extern int gr1553bm_started(void *bm); +extern int gr1553bm_started( void *bm ); /* Check how many entries are currently stored in the BM Log DMA-area */ -extern int gr1553bm_available(void *bm, int *nentries); +extern int gr1553bm_available( void *bm, int *nentries ); /* Stop logging */ -extern void gr1553bm_stop(void *bm); +extern void gr1553bm_stop( void *bm ); /* Read a maximum number of entries from LOG buffer. This function * must be @@ -214,7 +207,7 @@ extern void gr1553bm_stop(void *bm); * 0 = success * -1 = fail. (may be due to BM logging not started) */ -extern int gr1553bm_read(void *bm, struct gr1553bm_entry *dst, int *max); +extern int gr1553bm_read( void *bm, struct gr1553bm_entry *dst, int *max ); #ifdef __cplusplus } diff --git a/bsps/include/grlib/gr1553rt.h b/bsps/include/grlib/gr1553rt.h index bb1f4b0b82..6e8a7c20c3 100644 --- a/bsps/include/grlib/gr1553rt.h +++ b/bsps/include/grlib/gr1553rt.h @@ -54,7 +54,7 @@ extern "C" { #endif /* Register GR1553B driver needed by RT driver */ -extern void gr1553rt_register(void); +extern void gr1553rt_register( void ); struct gr1553rt_list; @@ -63,37 +63,37 @@ struct gr1553rt_list; * Must be aligned to 16 byte boundary */ struct gr1553rt_bd { - volatile uint32_t ctrl; /* 0x00 Control/Status word */ - volatile uint32_t dptr; /* 0x04 Data Pointer */ - volatile uint32_t next; /* 0x08 Next Descriptor in list */ - volatile uint32_t unused; /* 0x0C UNUSED BY HARDWARE */ + volatile uint32_t ctrl; /* 0x00 Control/Status word */ + volatile uint32_t dptr; /* 0x04 Data Pointer */ + volatile uint32_t next; /* 0x08 Next Descriptor in list */ + volatile uint32_t unused; /* 0x0C UNUSED BY HARDWARE */ }; /* Sub address table entry, the hardware access */ struct gr1553rt_sa { - volatile uint32_t ctrl; /* 0x00 SUBADDRESS CONTROL WORD */ - volatile uint32_t txptr; /* 0x04 TRANSMIT BD POINTER */ - volatile uint32_t rxptr; /* 0x08 RECEIVE BD POINTER */ - volatile uint32_t unused; /* 0x0C UNUSED BY HARDWARE */ + volatile uint32_t ctrl; /* 0x00 SUBADDRESS CONTROL WORD */ + volatile uint32_t txptr; /* 0x04 TRANSMIT BD POINTER */ + volatile uint32_t rxptr; /* 0x08 RECEIVE BD POINTER */ + volatile uint32_t unused; /* 0x0C UNUSED BY HARDWARE */ }; /* Configuration of a RT-SubAddress-List */ struct gr1553rt_list_cfg { - unsigned int bd_cnt; /* Number of hw-descriptors in list */ + unsigned int bd_cnt; /* Number of hw-descriptors in list */ }; /* A TX or RX subaddress descriptor list */ struct gr1553rt_list { - short listid; /* ID/NUMBER of List. -1 unassigned */ - short subadr; /* SubAddress. -1 when not scheduled */ - void *rt; /* Scheduled on Device */ - struct gr1553rt_list_cfg *cfg; /* List configuration */ - int bd_cnt; /* Number of Descriptors */ + short listid; /* ID/NUMBER of List. -1 unassigned */ + short subadr; /* SubAddress. -1 when not scheduled */ + void *rt; /* Scheduled on Device */ + struct gr1553rt_list_cfg *cfg; /* List configuration */ + int bd_cnt; /* Number of Descriptors */ - /* !!Must be last in data structure!! + /* !!Must be last in data structure!! * !!Array must at least be of length bd_cnt!! */ - unsigned short bds[0]; /* Array of BDIDs */ + unsigned short bds[ 0 ]; /* Array of BDIDs */ }; /* GR1553B-RT Driver configuration options used when calling gr1553rt_config(). @@ -105,35 +105,35 @@ struct gr1553rt_list { * into an address used by CPU. */ struct gr1553rt_cfg { - unsigned char rtaddress; /* RT Address 0..30 */ + unsigned char rtaddress; /* RT Address 0..30 */ - /*** MODE CODE CONFIG ***/ - unsigned int modecode; /* Mode codes enable/disable/IRQ/EV-Log. + /*** MODE CODE CONFIG ***/ + unsigned int modecode; /* Mode codes enable/disable/IRQ/EV-Log. * Each modecode has a 2-bit cfg field. * See Mode Code Control Register in * hardware manual. */ - /*** TIME CONFIG ***/ - unsigned short time_res; /* Time tag resolution in us */ + /*** TIME CONFIG ***/ + unsigned short time_res; /* Time tag resolution in us */ - /*** SUBADDRESS TABLE CONFIG ***/ - void *satab_buffer; /* Optional Custom buffer. Must be + /*** SUBADDRESS TABLE CONFIG ***/ + void *satab_buffer; /* Optional Custom buffer. Must be * At least 16*32 bytes, and be aligned * to 10-bit (1KB) boundary. Set to NULL * to make driver allocate buffer. */ - /*** EVENT LOG CONFIG ***/ - void *evlog_buffer; /* Optional Custom buffer */ - int evlog_size; /* Length, must be a multiple of 2. + /*** EVENT LOG CONFIG ***/ + void *evlog_buffer; /* Optional Custom buffer */ + int evlog_size; /* Length, must be a multiple of 2. * If set to ZERO event log is disabled */ - /*** TRANSFER DESCRIPTOR CONFIG ***/ - int bd_count; /* Number of transfer descriptors shared + /*** TRANSFER DESCRIPTOR CONFIG ***/ + int bd_count; /* Number of transfer descriptors shared * by all RX/TX sub-addresses */ - void *bd_buffer; /* Optional Custom descriptor area. + void *bd_buffer; /* Optional Custom descriptor area. * Must hold bd_count*32 bytes. * If NULL, descriptors will be * allocated dynamically. */ @@ -143,13 +143,13 @@ struct gr1553rt_cfg { * here. Used when calling the gr1553rt_status() function. */ struct gr1553rt_status { - unsigned int status; /* RT Status word */ - unsigned int bus_status; /* BUS Status */ - unsigned short synctime; /* Time Tag of last sync with data */ - unsigned short syncword; /* Data of last mode code synchronize + unsigned int status; /* RT Status word */ + unsigned int bus_status; /* BUS Status */ + unsigned short synctime; /* Time Tag of last sync with data */ + unsigned short syncword; /* Data of last mode code synchronize * with data. */ - unsigned short time_res; /* Time resolution (set by config) */ - unsigned short time; /* Current Time Tag */ + unsigned short time_res; /* Time resolution (set by config) */ + unsigned short time; /* Current Time Tag */ }; /* ISR callback definition for ERRORs detected in the GR1553B-RT interrupt @@ -160,7 +160,7 @@ struct gr1553rt_status { * Bit 10 - RT Table access error * \param data Custom data assigned by user */ -typedef void (*gr1553rt_irqerr_t)(int err, void *data); +typedef void ( *gr1553rt_irqerr_t )( int err, void *data ); /* ISR callback definition for modecodes that are configured to generate * an IRQ. The callback is called from within the GR1553B-RT interrupt @@ -170,7 +170,11 @@ typedef void (*gr1553rt_irqerr_t)(int err, void *data); * \param entry The raw Eventlog Entry * \param data Custom data assigned by user */ -typedef void (*gr1553rt_irqmc_t)(int mcode, unsigned int entry, void *data); +typedef void ( *gr1553rt_irqmc_t )( + int mcode, + unsigned int entry, + void *data +); /* Transfer ISR callback definition. Called from GR1553B-RT interrupt handler * when an interrupt has been generated and a event logged due to a 1553 @@ -182,12 +186,12 @@ typedef void (*gr1553rt_irqmc_t)(int mcode, unsigned int entry, void *data); * This can be used to process all descriptors upto entry_next. * \param data Custom data assigned by user */ -typedef void (*gr1553rt_irq_t)( - struct gr1553rt_list *list, - unsigned int entry, - int bd_next, - void *data - ); +typedef void ( *gr1553rt_irq_t )( + struct gr1553rt_list *list, + unsigned int entry, + int bd_next, + void *data +); /* Configure a list according to configuration. Assign the list * to a device, however not to a RT sub address yet. The rt @@ -198,12 +202,11 @@ typedef void (*gr1553rt_irq_t)( * \param cfg Configuration for list. Pointer to configuration is * stored within list for later use. */ -extern int gr1553rt_list_init - ( - void *rt, - struct gr1553rt_list **plist, - struct gr1553rt_list_cfg *cfg - ); +extern int gr1553rt_list_init( + void *rt, + struct gr1553rt_list **plist, + struct gr1553rt_list_cfg *cfg +); /* Assign an Error Interrupt handler. Before the handler is called the * RT hardware is stopped/disabled. The handler is optional, if not assigned @@ -216,12 +219,7 @@ extern int gr1553rt_list_init * \param func ISR called when an error causes an interrupt. * \param data Custom data given as an argument when calling ISR */ -extern int gr1553rt_irq_err - ( - void *rt, - gr1553rt_irqerr_t func, - void *data - ); +extern int gr1553rt_irq_err( void *rt, gr1553rt_irqerr_t func, void *data ); /* Assign a ModeCode Interrupt handler callback. Called when a 1553 modecode * transfer is logged and cause an IRQ. The modecode IRQ generation is @@ -230,12 +228,7 @@ extern int gr1553rt_irq_err * \param func ISR called when a modecode causes an interrupt. * \param data Custom data given as an argument when calling ISR */ -extern int gr1553rt_irq_mc - ( - void *rt, - gr1553rt_irqmc_t func, - void *data - ); +extern int gr1553rt_irq_mc( void *rt, gr1553rt_irqmc_t func, void *data ); /* Assign transfer interrupt handler callback. Called when a RX or TX * transfer is logged and cause an interrupt, the function is called @@ -250,16 +243,15 @@ extern int gr1553rt_irq_mc * causes an interrupt. * \param data Custom data given as an argument when calling ISR */ -extern int gr1553rt_irq_sa - ( - void *rt, - int subadr, - int tx, - gr1553rt_irq_t func, - void *data - ); +extern int gr1553rt_irq_sa( + void *rt, + int subadr, + int tx, + gr1553rt_irq_t func, + void *data +); -#define GR1553RT_BD_FLAGS_IRQEN (1<<30) +#define GR1553RT_BD_FLAGS_IRQEN ( 1 << 30 ) /* Initialize a descriptor entry in a list. This is typically done * prior to scheduling the list. * @@ -276,12 +268,12 @@ extern int gr1553rt_irq_sa * zero if entry_no is last descriptor in list (circular). */ extern int gr1553rt_bd_init( - struct gr1553rt_list *list, - unsigned short entry_no, - unsigned int flags, - uint16_t *dptr, - unsigned short next - ); + struct gr1553rt_list *list, + unsigned short entry_no, + unsigned int flags, + uint16_t *dptr, + unsigned short next +); /* Manipulate/Read Control/Status and Data Pointer words of a buffer descriptor. * If status is zero, the control/status word is accessed. If dptr is non-zero @@ -304,11 +296,11 @@ extern int gr1553rt_bd_init( * OUT: The old data pointer is stored here. */ extern int gr1553rt_bd_update( - struct gr1553rt_list *list, - int entry_no, - unsigned int *status, - uint16_t **dptr - ); + struct gr1553rt_list *list, + int entry_no, + unsigned int *status, + uint16_t **dptr +); /* Get the next/current descriptor processed of a RT sub-address. * @@ -316,7 +308,7 @@ extern int gr1553rt_bd_update( * \param txeno Pointer to where TX descriptor number is stored. * \param rxeno Pointer to where RX descriptor number is stored. */ -extern int gr1553rt_indication(void *rt, int subadr, int *txeno, int *rxeno); +extern int gr1553rt_indication( void *rt, int subadr, int *txeno, int *rxeno ); /* Take a GR1553RT hardware device identified by minor. * A pointer is returned that is used internally by the GR1553RT @@ -325,10 +317,10 @@ extern int gr1553rt_indication(void *rt, int subadr, int *txeno, int *rxeno); * * This function initializes the RT hardware to a stopped/disable level. */ -extern void *gr1553rt_open(int minor); +extern void *gr1553rt_open( int minor ); /* Close and stop/disable the RT hardware. */ -extern void gr1553rt_close(void *rt); +extern void gr1553rt_close( void *rt ); /* Configure the RT. The RT device must be configured once before * started. A started RT device can not be configured. @@ -336,7 +328,7 @@ extern void gr1553rt_close(void *rt); * \param rt The RT to configure * \param cfg Configuration parameters */ -extern int gr1553rt_config(void *rt, struct gr1553rt_cfg *cfg); +extern int gr1553rt_config( void *rt, struct gr1553rt_cfg *cfg ); /* Schedule a RX or TX list on a sub address. If a list has already been * schduled on the subaddress and on the same transfer type (RX/TX), the @@ -347,11 +339,11 @@ extern int gr1553rt_config(void *rt, struct gr1553rt_cfg *cfg); * \param list Preconfigued RT list scheduled */ extern void gr1553rt_sa_schedule( - void *rt, - int subadr, - int tx, - struct gr1553rt_list *list - ); + void *rt, + int subadr, + int tx, + struct gr1553rt_list *list +); /* Set SubAdress options. One may for example Enable or Disable a sub * address RX and/or TX. See hardware manual for SA-Table configuration @@ -363,11 +355,11 @@ extern void gr1553rt_sa_schedule( * */ extern void gr1553rt_sa_setopts( - void *rt, - int subadr, - unsigned int mask, - unsigned int options - ); + void *rt, + int subadr, + unsigned int mask, + unsigned int options +); /* Get The Subaddress and transfer type of a scheduled list. Normally the * application knows which subaddress the list is for. @@ -377,10 +369,10 @@ extern void gr1553rt_sa_setopts( * \param tx Transfer type is stored here. 1=TX, 0=RX. */ extern void gr1553rt_list_sa( - struct gr1553rt_list *list, - int *subadr, - int *tx - ); + struct gr1553rt_list *list, + int *subadr, + int *tx +); /* Start RT Communication * @@ -389,7 +381,7 @@ extern void gr1553rt_list_sa( * RT to be stopped are no longer available. After the RT has been * started the configuration function can not be called. */ -extern int gr1553rt_start(void *rt); +extern int gr1553rt_start( void *rt ); /* Get Status of the RT core. See data structure gr1553rt_status for more * information about the result. It can be used to read out: @@ -400,12 +392,12 @@ extern int gr1553rt_start(void *rt); * \param status Pointer to where the status words will be stored. They * are stored according to the gr1553rt_status data structure. */ -extern void gr1553rt_status(void *rt, struct gr1553rt_status *status); +extern void gr1553rt_status( void *rt, struct gr1553rt_status *status ); /* Stop RT communication. Only possible to stop an already started RT device. * Interrupts are disabled and the RT Enable bit cleared. */ -extern void gr1553rt_stop(void *rt); +extern void gr1553rt_stop( void *rt ); /* Set RT vector and/or bit word. * @@ -421,10 +413,10 @@ extern void gr1553rt_stop(void *rt); * hw_words = (hw_words & ~mask) | (words & mask) */ extern void gr1553rt_set_vecword( - void *rt, - unsigned int mask, - unsigned int words - ); + void *rt, + unsigned int mask, + unsigned int words +); /* Set selectable bits of the "Bus Status Register". The bits written * is determined by the "mask" bit-mask. Operation: @@ -432,7 +424,11 @@ extern void gr1553rt_set_vecword( * bus_status = (bus_status & ~mask) | (sts & mask) * */ -extern void gr1553rt_set_bussts(void *rt, unsigned int mask, unsigned int sts); +extern void gr1553rt_set_bussts( + void *rt, + unsigned int mask, + unsigned int sts +); /* Read up to MAX number of entries in eventlog log. * @@ -444,7 +440,7 @@ extern void gr1553rt_set_bussts(void *rt, unsigned int mask, unsigned int sts); * zero No entries available at the moment * positive Number of entries copied into dst */ -extern int gr1553rt_evlog_read(void *rt, unsigned int *dst, int max); +extern int gr1553rt_evlog_read( void *rt, unsigned int *dst, int max ); #ifdef __cplusplus } diff --git a/bsps/include/grlib/gr_701.h b/bsps/include/grlib/gr_701.h index bee42fbe96..014aad02cd 100644 --- a/bsps/include/grlib/gr_701.h +++ b/bsps/include/grlib/gr_701.h @@ -51,17 +51,17 @@ extern "C" { */ extern struct drvmgr_bus_res *gr701_resources[]; -#define GR701_OPTIONS_AMBA 0x01 -#define GR701_OPTIONS_IRQ 0x02 +#define GR701_OPTIONS_AMBA 0x01 +#define GR701_OPTIONS_IRQ 0x02 /* Print information about all GR-701 PCI boards */ -void gr701_print(int options); +void gr701_print( int options ); /* Print information about one GR-701 PCI board */ -void gr701_print_dev(struct drvmgr_dev *dev, int options); +void gr701_print_dev( struct drvmgr_dev *dev, int options ); /* Register GR-701 driver */ -void gr701_register_drv(void); +void gr701_register_drv( void ); #ifdef __cplusplus } diff --git a/bsps/include/grlib/gr_cpci_gr740.h b/bsps/include/grlib/gr_cpci_gr740.h index 6402bf6c6d..691ff4c7a3 100644 --- a/bsps/include/grlib/gr_cpci_gr740.h +++ b/bsps/include/grlib/gr_cpci_gr740.h @@ -62,16 +62,16 @@ extern "C" { extern struct drvmgr_bus_res *gr_cpci_gr740_resources[]; /* Options to gr_cpci_gr740_print function */ -#define GR_CPCI_GR740_OPTIONS_AMBA 0x01 /* Print AMBA bus devices */ +#define GR_CPCI_GR740_OPTIONS_AMBA 0x01 /* Print AMBA bus devices */ /* Print information about all GR-CPCI-GR740 PCI boards */ -void gr_cpci_gr740_print(int options); +void gr_cpci_gr740_print( int options ); /* Print information about one GR-CPCI-GR740 PCI board */ -void gr_cpci_gr740_print_dev(struct drvmgr_dev *dev, int options); +void gr_cpci_gr740_print_dev( struct drvmgr_dev *dev, int options ); /* Register GR-CPCI-GR740 driver */ -void gr_cpci_gr740_register_drv(void); +void gr_cpci_gr740_register_drv( void ); #ifdef __cplusplus } diff --git a/bsps/include/grlib/gr_rasta_adcdac.h b/bsps/include/grlib/gr_rasta_adcdac.h index e1512f2fb0..cbcdda624d 100644 --- a/bsps/include/grlib/gr_rasta_adcdac.h +++ b/bsps/include/grlib/gr_rasta_adcdac.h @@ -52,17 +52,17 @@ extern "C" { extern struct drvmgr_bus_res *gr_rasta_adcdac_resources[]; /* Options to gr_rasta_io_print function */ -#define RASTA_ADCDAC_OPTIONS_AMBA 0x01 /* Print AMBA bus devices */ -#define RASTA_ADCDAC_OPTIONS_IRQ 0x02 /* Print current IRQ setup */ +#define RASTA_ADCDAC_OPTIONS_AMBA 0x01 /* Print AMBA bus devices */ +#define RASTA_ADCDAC_OPTIONS_IRQ 0x02 /* Print current IRQ setup */ /* Print information about all GR-RASTA-IO PCI boards */ -void gr_rasta_adcdac_print(int options); +void gr_rasta_adcdac_print( int options ); /* Print information about one GR-RASTA-IO PCI board */ -void gr_rasta_adcdac_print_dev(struct drvmgr_dev *dev, int options); +void gr_rasta_adcdac_print_dev( struct drvmgr_dev *dev, int options ); /* Register GR-RASTA-IO driver */ -void gr_rasta_adcdac_register_drv(void); +void gr_rasta_adcdac_register_drv( void ); #ifdef __cplusplus } diff --git a/bsps/include/grlib/gr_rasta_io.h b/bsps/include/grlib/gr_rasta_io.h index ffadf93c9e..fa28c09cfd 100644 --- a/bsps/include/grlib/gr_rasta_io.h +++ b/bsps/include/grlib/gr_rasta_io.h @@ -52,17 +52,17 @@ extern "C" { extern struct drvmgr_bus_res *gr_rasta_io_resources[]; /* Options to gr_rasta_io_print function */ -#define RASTA_IO_OPTIONS_AMBA 0x01 /* Print AMBA bus devices */ -#define RASTA_IO_OPTIONS_IRQ 0x02 /* Print current IRQ setup */ +#define RASTA_IO_OPTIONS_AMBA 0x01 /* Print AMBA bus devices */ +#define RASTA_IO_OPTIONS_IRQ 0x02 /* Print current IRQ setup */ /* Print information about GR-RASTA-IO PCI boards */ -void gr_rasta_io_print(int options); +void gr_rasta_io_print( int options ); /* Print information about a GR-RASTA-IO PCI board */ -void gr_rasta_io_print_dev(struct drvmgr_dev *dev, int options); +void gr_rasta_io_print_dev( struct drvmgr_dev *dev, int options ); /* Register GR-RASTA-IO driver */ -void gr_rasta_io_register_drv(void); +void gr_rasta_io_register_drv( void ); #ifdef __cplusplus } diff --git a/bsps/include/grlib/gr_rasta_spw_router.h b/bsps/include/grlib/gr_rasta_spw_router.h index 15deacd7a2..9b74cd5708 100644 --- a/bsps/include/grlib/gr_rasta_spw_router.h +++ b/bsps/include/grlib/gr_rasta_spw_router.h @@ -48,17 +48,17 @@ extern "C" { extern struct drvmgr_bus_res *gr_rasta_spw_router_resources[]; /* Options to gr_rasta_spw_router_print function */ -#define RASTA_SPW_ROUTER_OPTIONS_AMBA 0x01 /* Print AMBA bus devices */ -#define RASTA_SPW_ROUTER_OPTIONS_IRQ 0x02 /* Print current IRQ setup */ +#define RASTA_SPW_ROUTER_OPTIONS_AMBA 0x01 /* Print AMBA bus devices */ +#define RASTA_SPW_ROUTER_OPTIONS_IRQ 0x02 /* Print current IRQ setup */ /* Print information about all GR-CPCI-LEON4-N2X PCI boards */ -void gr_rasta_spw_router_print(int options); +void gr_rasta_spw_router_print( int options ); /* Print information about one GR-CPCI-LEON4-N2X PCI board */ -void gr_rasta_spw_router_print_dev(struct drvmgr_dev *dev, int options); +void gr_rasta_spw_router_print_dev( struct drvmgr_dev *dev, int options ); /* Register GR-RASTA-SPW-ROUTER driver to Driver Manager */ -void gr_rasta_spw_router_register_drv(void); +void gr_rasta_spw_router_register_drv( void ); #ifdef __cplusplus } diff --git a/bsps/include/grlib/gr_rasta_tmtc.h b/bsps/include/grlib/gr_rasta_tmtc.h index 9feeab3479..690a8df728 100644 --- a/bsps/include/grlib/gr_rasta_tmtc.h +++ b/bsps/include/grlib/gr_rasta_tmtc.h @@ -69,29 +69,29 @@ extern "C" { * -- 9 : 0 SpaceCraft ID */ -#define GR_TMTC_GPIO_PWRX (1<<31) -#define GR_TMTC_GPIO_PWTC (1<<30) -#define GR_TMTC_GPIO_RED_TM (1<<29) -#define GR_TMTC_GPIO_RED_TC (1<<28) -#define GR_TMTC_GPIO_GRTM_SEL (1<<27) -#define GR_TMTC_GPIO_LB_PW (1<<26) -#define GR_TMTC_GPIO_TRANSP_CLK (1<<25) -#define GR_TMTC_GPIO_PWTX_SEL (1<<24) -#define GR_TMTC_GPIO_PDEC_MAP (1<<23) -#define GR_TMTC_GPIO_PDEC_CPDU (1<<22) -#define GR_TMTC_GPIO_PDEC_SU (1<<21) -#define GR_TMTC_GPIO_PDEC_RM (1<<20) -#define GR_TMTC_GPIO_PDEC_AU (1<<19) -#define GR_TMTC_GPIO_PDEC_DYN_MODE (1<<18) -#define GR_TMTC_GPIO_PDEC_PRIO (1<<17) -#define GR_TMTC_GPIO_TC_PSS (1<<16) -#define GR_TMTC_GPIO_TC_MARK (1<<15) -#define GR_TMTC_GPIO_TC_PSEUDO (1<<14) -#define GR_TMTC_GPIO_TC_RISING_CLK (1<<13) -#define GR_TMTC_GPIO_TC_ACTIVE_HIGH (1<<12) -#define GR_TMTC_GPIO_TC_BIT_LOCK (1<<11) -#define GR_TMTC_GPIO_TC_RF_AVAIL (1<<10) -#define GR_TMTC_GPIO_SCID (0x000003ff) +#define GR_TMTC_GPIO_PWRX ( 1 << 31 ) +#define GR_TMTC_GPIO_PWTC ( 1 << 30 ) +#define GR_TMTC_GPIO_RED_TM ( 1 << 29 ) +#define GR_TMTC_GPIO_RED_TC ( 1 << 28 ) +#define GR_TMTC_GPIO_GRTM_SEL ( 1 << 27 ) +#define GR_TMTC_GPIO_LB_PW ( 1 << 26 ) +#define GR_TMTC_GPIO_TRANSP_CLK ( 1 << 25 ) +#define GR_TMTC_GPIO_PWTX_SEL ( 1 << 24 ) +#define GR_TMTC_GPIO_PDEC_MAP ( 1 << 23 ) +#define GR_TMTC_GPIO_PDEC_CPDU ( 1 << 22 ) +#define GR_TMTC_GPIO_PDEC_SU ( 1 << 21 ) +#define GR_TMTC_GPIO_PDEC_RM ( 1 << 20 ) +#define GR_TMTC_GPIO_PDEC_AU ( 1 << 19 ) +#define GR_TMTC_GPIO_PDEC_DYN_MODE ( 1 << 18 ) +#define GR_TMTC_GPIO_PDEC_PRIO ( 1 << 17 ) +#define GR_TMTC_GPIO_TC_PSS ( 1 << 16 ) +#define GR_TMTC_GPIO_TC_MARK ( 1 << 15 ) +#define GR_TMTC_GPIO_TC_PSEUDO ( 1 << 14 ) +#define GR_TMTC_GPIO_TC_RISING_CLK ( 1 << 13 ) +#define GR_TMTC_GPIO_TC_ACTIVE_HIGH ( 1 << 12 ) +#define GR_TMTC_GPIO_TC_BIT_LOCK ( 1 << 11 ) +#define GR_TMTC_GPIO_TC_RF_AVAIL ( 1 << 10 ) +#define GR_TMTC_GPIO_SCID ( 0x000003ff ) /* An array of pointers to GR-RASTA-TMTC bus resources. The resources will be * used by the device drivers controlling the cores on the GR-RASTA-IO target @@ -103,17 +103,17 @@ extern "C" { extern struct drvmgr_bus_res *gr_rasta_tmtc_resources[]; /* Options to gr_rasta_io_print function */ -#define RASTA_TMTC_OPTIONS_AMBA 0x01 /* Print AMBA bus devices */ -#define RASTA_TMTC_OPTIONS_IRQ 0x02 /* Print current IRQ setup */ +#define RASTA_TMTC_OPTIONS_AMBA 0x01 /* Print AMBA bus devices */ +#define RASTA_TMTC_OPTIONS_IRQ 0x02 /* Print current IRQ setup */ /* Print information about GR-RASTA-TMTC PCI boards */ -void gr_rasta_tmtc_print(int options); +void gr_rasta_tmtc_print( int options ); /* Print information about a GR-RASTA-TMTC PCI boards */ -void gr_rasta_tmtc_print_dev(struct drvmgr_dev *dev, int options); +void gr_rasta_tmtc_print_dev( struct drvmgr_dev *dev, int options ); /* Register GR-RASTA-TMTC driver */ -void gr_rasta_tmtc_register_drv(void); +void gr_rasta_tmtc_register_drv( void ); #ifdef __cplusplus } diff --git a/bsps/include/grlib/gr_tmtc_1553.h b/bsps/include/grlib/gr_tmtc_1553.h index faa8e4f6fe..0169b29045 100644 --- a/bsps/include/grlib/gr_tmtc_1553.h +++ b/bsps/include/grlib/gr_tmtc_1553.h @@ -52,20 +52,20 @@ extern "C" { extern struct drvmgr_bus_res *gr_tmtc_1553_resources[]; /* Options to gr_rasta_io_print function */ -#define TMTC_1553_OPTIONS_AMBA 0x01 /* Print AMBA bus devices */ -#define TMTC_1553_OPTIONS_IRQ 0x02 /* Print current IRQ setup */ +#define TMTC_1553_OPTIONS_AMBA 0x01 /* Print AMBA bus devices */ +#define TMTC_1553_OPTIONS_IRQ 0x02 /* Print current IRQ setup */ /* Print information about GR-RASTA-IO PCI board */ -void gr_tmtc_1553_print(int options); +void gr_tmtc_1553_print( int options ); /* Register GR-RASTA-IO driver */ -void gr_tmtc_1553_register_drv(void); +void gr_tmtc_1553_register_drv( void ); /* Print information about all GR-TMTC-1553 devices registered to this driver */ -void gr_tmtc_1553_print(int options); +void gr_tmtc_1553_print( int options ); /* Print information about one GR-TMTC-1553 device */ -void gr_tmtc_1553_print_dev(struct drvmgr_dev *dev, int options); +void gr_tmtc_1553_print_dev( struct drvmgr_dev *dev, int options ); #ifdef __cplusplus } diff --git a/bsps/include/grlib/gradcdac.h b/bsps/include/grlib/gradcdac.h index 270e6414db..c756ea7521 100644 --- a/bsps/include/grlib/gradcdac.h +++ b/bsps/include/grlib/gradcdac.h @@ -35,19 +35,19 @@ extern "C" { #endif struct gradcdac_regs { - volatile uint32_t config; /* 0x00 Configuration Register */ - volatile uint32_t status; /* 0x04 Status Register */ - uint32_t unused0[2]; - volatile uint32_t adc_din; /* 0x10 ADC Data Input Register */ - volatile uint32_t dac_dout; /* 0x14 DAC Data Output Register */ - uint32_t unused1[2]; - volatile uint32_t adrin; /* 0x20 Address Input Register */ - volatile uint32_t adrout; /* 0x24 Address Output Register */ - volatile uint32_t adrdir; /* 0x28 Address Direction Register */ - uint32_t unused2[1]; - volatile uint32_t data_in; /* 0x30 Data Input Register */ - volatile uint32_t data_out; /* 0x34 Data Output Register */ - volatile uint32_t data_dir; /* 0x38 Data Direction Register */ + volatile uint32_t config; /* 0x00 Configuration Register */ + volatile uint32_t status; /* 0x04 Status Register */ + uint32_t unused0[ 2 ]; + volatile uint32_t adc_din; /* 0x10 ADC Data Input Register */ + volatile uint32_t dac_dout; /* 0x14 DAC Data Output Register */ + uint32_t unused1[ 2 ]; + volatile uint32_t adrin; /* 0x20 Address Input Register */ + volatile uint32_t adrout; /* 0x24 Address Output Register */ + volatile uint32_t adrdir; /* 0x28 Address Direction Register */ + uint32_t unused2[ 1 ]; + volatile uint32_t data_in; /* 0x30 Data Input Register */ + volatile uint32_t data_out; /* 0x34 Data Output Register */ + volatile uint32_t data_dir; /* 0x38 Data Direction Register */ }; #define GRADCDAC_CFG_DACWS 0x00f80000 @@ -68,21 +68,21 @@ struct gradcdac_regs { #define GRADCDAC_CFG_DACDW_BIT 16 #define GRADCDAC_CFG_ADCWS_BIT 11 #define GRADCDAC_CFG_RCPOL_BIT 10 -#define GRADCDAC_CFG_CSMODE_BIT 8 -#define GRADCDAC_CFG_CSPOL_BIT 7 -#define GRADCDAC_CFG_RDYMODE_BIT 6 -#define GRADCDAC_CFG_RDYPOL_BIT 5 -#define GRADCDAC_CFG_TRIGPOL_BIT 4 -#define GRADCDAC_CFG_TRIGMODE_BIT 2 -#define GRADCDAC_CFG_ADCDW_BIT 0 +#define GRADCDAC_CFG_CSMODE_BIT 8 +#define GRADCDAC_CFG_CSPOL_BIT 7 +#define GRADCDAC_CFG_RDYMODE_BIT 6 +#define GRADCDAC_CFG_RDYPOL_BIT 5 +#define GRADCDAC_CFG_TRIGPOL_BIT 4 +#define GRADCDAC_CFG_TRIGMODE_BIT 2 +#define GRADCDAC_CFG_ADCDW_BIT 0 -#define GRADCDAC_STATUS_DACNO 0x40 -#define GRADCDAC_STATUS_DACRDY 0x20 -#define GRADCDAC_STATUS_DACON 0x10 -#define GRADCDAC_STATUS_ADCTO 0x08 -#define GRADCDAC_STATUS_ADCNO 0x04 -#define GRADCDAC_STATUS_ADCRDY 0x02 -#define GRADCDAC_STATUS_ADCON 0x01 +#define GRADCDAC_STATUS_DACNO 0x40 +#define GRADCDAC_STATUS_DACRDY 0x20 +#define GRADCDAC_STATUS_DACON 0x10 +#define GRADCDAC_STATUS_ADCTO 0x08 +#define GRADCDAC_STATUS_ADCNO 0x04 +#define GRADCDAC_STATUS_ADCRDY 0x02 +#define GRADCDAC_STATUS_ADCON 0x01 #define GRADCDAC_STATUS_DACNO_BIT 6 #define GRADCDAC_STATUS_DACRDY_BIT 5 @@ -96,70 +96,70 @@ struct gradcdac_regs { #define GRADCDAC_IRQ_ADC 0 struct gradcdac_config { - unsigned char dac_ws; - char wr_pol; - unsigned char dac_dw; - unsigned char adc_ws; - char rc_pol; - unsigned char cs_mode; - char cs_pol; - char ready_mode; - char ready_pol; - char trigg_pol; - unsigned char trigg_mode; - unsigned char adc_dw; + unsigned char dac_ws; + char wr_pol; + unsigned char dac_dw; + unsigned char adc_ws; + char rc_pol; + unsigned char cs_mode; + char cs_pol; + char ready_mode; + char ready_pol; + char trigg_pol; + unsigned char trigg_mode; + unsigned char adc_dw; }; -extern void *gradcdac_open(char *devname); +extern void *gradcdac_open( char *devname ); -extern void gradcdac_set_config(void *cookie, struct gradcdac_config *cfg); +extern void gradcdac_set_config( void *cookie, struct gradcdac_config *cfg ); -extern void gradcdac_get_config(void *cookie, struct gradcdac_config *cfg); +extern void gradcdac_get_config( void *cookie, struct gradcdac_config *cfg ); -extern void gradcdac_set_cfg(void *cookie, unsigned int config); +extern void gradcdac_set_cfg( void *cookie, unsigned int config ); -extern unsigned int gradcdac_get_cfg(void *cookie); +extern unsigned int gradcdac_get_cfg( void *cookie ); -extern unsigned int gradcdac_get_status(void *cookie); +extern unsigned int gradcdac_get_status( void *cookie ); -static __inline__ int gradcdac_DAC_ReqRej(unsigned int status) +static __inline__ int gradcdac_DAC_ReqRej( unsigned int status ) { - return (status & GRADCDAC_STATUS_DACNO); + return ( status & GRADCDAC_STATUS_DACNO ); } -static __inline__ int gradcdac_DAC_isCompleted(unsigned int status) +static __inline__ int gradcdac_DAC_isCompleted( unsigned int status ) { - return (status & GRADCDAC_STATUS_DACRDY); + return ( status & GRADCDAC_STATUS_DACRDY ); } -static __inline__ int gradcdac_DAC_isOngoing(unsigned int status) +static __inline__ int gradcdac_DAC_isOngoing( unsigned int status ) { - return (status & GRADCDAC_STATUS_DACON); + return ( status & GRADCDAC_STATUS_DACON ); } -static __inline__ int gradcdac_ADC_isTimeouted(unsigned int status) +static __inline__ int gradcdac_ADC_isTimeouted( unsigned int status ) { - return (status & GRADCDAC_STATUS_ADCTO); + return ( status & GRADCDAC_STATUS_ADCTO ); } -static __inline__ int gradcdac_ADC_ReqRej(unsigned int status) +static __inline__ int gradcdac_ADC_ReqRej( unsigned int status ) { - return (status & GRADCDAC_STATUS_ADCNO); + return ( status & GRADCDAC_STATUS_ADCNO ); } -static __inline__ int gradcdac_ADC_isCompleted(unsigned int status) +static __inline__ int gradcdac_ADC_isCompleted( unsigned int status ) { - return (status & GRADCDAC_STATUS_ADCRDY); + return ( status & GRADCDAC_STATUS_ADCRDY ); } -static __inline__ int gradcdac_ADC_isOngoing(unsigned int status) +static __inline__ int gradcdac_ADC_isOngoing( unsigned int status ) { - return (status & GRADCDAC_STATUS_ADCON); + return ( status & GRADCDAC_STATUS_ADCON ); } #define GRADCDAC_ISR_BOTH 3 -#define GRADCDAC_ISR_DAC 2 -#define GRADCDAC_ISR_ADC 1 +#define GRADCDAC_ISR_DAC 2 +#define GRADCDAC_ISR_ADC 1 /* Install IRQ handler for ADC and/or DAC interrupt. * The installed IRQ handler(ISR) must read the status @@ -170,16 +170,20 @@ static __inline__ int gradcdac_ADC_isOngoing(unsigned int status) * \param isr Interrupt service routine called when IRQ is fired * \param arg custom argument passed to ISR when called. */ -extern int gradcdac_install_irq_handler - (void *cookie, int adc, void (*isr)(void *cookie, void *arg), void *arg); +extern int gradcdac_install_irq_handler( + void *cookie, + int adc, + void ( *isr )( void *cookie, void *arg ), + void *arg +); -extern void gradcdac_uninstall_irq_handler(void *cookie, int adc); +extern void gradcdac_uninstall_irq_handler( void *cookie, int adc ); /* Make the ADC circuitry initialize a analogue to digital * conversion. The result can be read out by gradcdac_adc_convert_try * or gradcdac_adc_convert. */ -extern void gradcdac_adc_convert_start(void *cookie); +extern void gradcdac_adc_convert_start( void *cookie ); /* Tries to read the conversion result. If the circuitry is busy * converting the function return a non-zero value, if the conversion @@ -190,7 +194,10 @@ extern void gradcdac_adc_convert_start(void *cookie); * positive = ADC busy, digital_value contain previous conversion result * negative = Conversion request failed. */ -extern int gradcdac_adc_convert_try(void *cookie, unsigned short *digital_value); +extern int gradcdac_adc_convert_try( + void *cookie, + unsigned short *digital_value +); /* Waits until the ADC circuity has finished a digital to analogue * conversion. The Waiting is implemented as a busy loop utilizing @@ -199,45 +206,48 @@ extern int gradcdac_adc_convert_try(void *cookie, unsigned short *digital_value) * \return zero = Conversion ok * negative = Conversion request failed. */ -extern int gradcdac_adc_convert(void *cookie, unsigned short *digital_value); +extern int gradcdac_adc_convert( void *cookie, unsigned short *digital_value ); /* Try to make the DAC circuitry initialize a digital to analogue * conversion. If the circuitry is busy by a previous conversion * the function return a non-zero value, if the conversion is * successfully initialized the function return zero. */ -extern int gradcdac_dac_convert_try(void *cookie, unsigned short digital_value); +extern int gradcdac_dac_convert_try( + void *cookie, + unsigned short digital_value +); /* Initializes a digital to analogue conversion by waiting until * previous conversions is finished before procceding with the * conversion. The Waiting is implemented as a busy loop utilizing * 100% CPU load. */ -extern void gradcdac_dac_convert(void *cookie, unsigned short digital_value); +extern void gradcdac_dac_convert( void *cookie, unsigned short digital_value ); -extern unsigned int gradcdac_get_adrinput(void *cookie); -extern void gradcdac_set_adrinput(void *cookie, unsigned int input); +extern unsigned int gradcdac_get_adrinput( void *cookie ); +extern void gradcdac_set_adrinput( void *cookie, unsigned int input ); -extern unsigned int gradcdac_get_adroutput(void *cookie); -extern void gradcdac_set_adroutput(void *cookie, unsigned int output); +extern unsigned int gradcdac_get_adroutput( void *cookie ); +extern void gradcdac_set_adroutput( void *cookie, unsigned int output ); -extern unsigned int gradcdac_get_adrdir(void *cookie); -extern void gradcdac_set_adrdir(void *cookie, unsigned int dir); +extern unsigned int gradcdac_get_adrdir( void *cookie ); +extern void gradcdac_set_adrdir( void *cookie, unsigned int dir ); -extern unsigned int gradcdac_get_datainput(void *cookie); -extern void gradcdac_set_datainput(void *cookie, unsigned int input); +extern unsigned int gradcdac_get_datainput( void *cookie ); +extern void gradcdac_set_datainput( void *cookie, unsigned int input ); -extern unsigned int gradcdac_get_dataoutput(void *cookie); -extern void gradcdac_set_dataoutput(void *cookie, unsigned int output); +extern unsigned int gradcdac_get_dataoutput( void *cookie ); +extern void gradcdac_set_dataoutput( void *cookie, unsigned int output ); -extern unsigned int gradcdac_get_datadir(void *cookie); -extern void gradcdac_set_datadir(void *cookie, unsigned int dir); +extern unsigned int gradcdac_get_datadir( void *cookie ); +extern void gradcdac_set_datadir( void *cookie, unsigned int dir ); /* Show one or all GRADCDAC cores. If cookie is NULL all GRADCDAC's are shown */ -extern void grAdcDacShow(void *cookie); +extern void grAdcDacShow( void *cookie ); /* Register Driver routine */ -extern void gradcdac_register_drv (void); +extern void gradcdac_register_drv( void ); #ifdef __cplusplus } diff --git a/bsps/include/grlib/grascs.h b/bsps/include/grlib/grascs.h index e0c14089fb..106692cb88 100644 --- a/bsps/include/grlib/grascs.h +++ b/bsps/include/grlib/grascs.h @@ -41,68 +41,69 @@ extern "C" { /* Default, minimum and maximum ETR pulse frequency */ #define GRASCS_DEFAULT_ETRFREQ 10 -#define GRASCS_MIN_ETRFREQ 1 -#define GRASCS_MAX_ETRFREQ 100 +#define GRASCS_MIN_ETRFREQ 1 +#define GRASCS_MAX_ETRFREQ 100 /* Maximum number of external time markers */ #define GRASCS_MAX_TMS 6 /* Error codes */ -#define GRASCS_ERROR_STARTSTOP 1 /* Serial/synch interface is running/stopped */ +#define GRASCS_ERROR_STARTSTOP \ + 1 /* Serial/synch interface is running/stopped */ #define GRASCS_ERROR_TRANSACTIVE 2 /* Busy with transaction */ -#define GRASCS_ERROR_CAPFAULT 3 /* Core capabilities prohibit request */ +#define GRASCS_ERROR_CAPFAULT 3 /* Core capabilities prohibit request */ /* Command register */ -#define GRASCS_CMD_RESET (1 << 0) -#define GRASCS_CMD_STARTSTOP (1 << 1) -#define GRASCS_CMD_ESTARTSTOP (1 << 2) -#define GRASCS_CMD_SENDTM (1 << 3) -#define GRASCS_CMD_ETRCTRL (7 << 4) -#define GRASCS_CMD_ETRCTRL_BITS 4 -#define GRASCS_CMD_SLAVESEL (15 << 8) +#define GRASCS_CMD_RESET ( 1 << 0 ) +#define GRASCS_CMD_STARTSTOP ( 1 << 1 ) +#define GRASCS_CMD_ESTARTSTOP ( 1 << 2 ) +#define GRASCS_CMD_SENDTM ( 1 << 3 ) +#define GRASCS_CMD_ETRCTRL ( 7 << 4 ) +#define GRASCS_CMD_ETRCTRL_BITS 4 +#define GRASCS_CMD_SLAVESEL ( 15 << 8 ) #define GRASCS_CMD_SLAVESEL_BITS 8 -#define GRASCS_CMD_TCDONE (1 << 12) -#define GRASCS_CMD_TMDONE (1 << 13) -#define GRASCS_CMD_US1 (255 << 16) -#define GRASCS_CMD_US1_BITS 16 -#define GRASCS_CMD_US1C (1 << 24) +#define GRASCS_CMD_TCDONE ( 1 << 12 ) +#define GRASCS_CMD_TMDONE ( 1 << 13 ) +#define GRASCS_CMD_US1 ( 255 << 16 ) +#define GRASCS_CMD_US1_BITS 16 +#define GRASCS_CMD_US1C ( 1 << 24 ) /* Clock scale register */ #define GRASCS_CLK_ETRFREQ_BITS 12 /* Status register */ -#define GRASCS_STS_RUNNING (1 << 0) -#define GRASCS_STS_ERUNNING (1 << 1) -#define GRASCS_STS_TCDONE (1 << 4) -#define GRASCS_STS_TMDONE (1 << 5) -#define GRASCS_STS_DBITS_BITS 8 +#define GRASCS_STS_RUNNING ( 1 << 0 ) +#define GRASCS_STS_ERUNNING ( 1 << 1 ) +#define GRASCS_STS_TCDONE ( 1 << 4 ) +#define GRASCS_STS_TMDONE ( 1 << 5 ) +#define GRASCS_STS_DBITS_BITS 8 #define GRASCS_STS_NSLAVES_BITS 13 -#define GRASCS_STS_USCONF_BITS 18 -#define GRASCS_STS_TMCONF_BITS 19 +#define GRASCS_STS_USCONF_BITS 18 +#define GRASCS_STS_TMCONF_BITS 19 -extern int ASCS_init(void); +extern int ASCS_init( void ); -extern int ASCS_input_select(int slave); +extern int ASCS_input_select( int slave ); -extern int ASCS_etr_select(int etr, int freq); +extern int ASCS_etr_select( int etr, int freq ); -extern void ASCS_start(void); +extern void ASCS_start( void ); -extern void ASCS_stop(void); +extern void ASCS_stop( void ); -extern int ASCS_iface_status(void); +extern int ASCS_iface_status( void ); -extern int ASCS_TC_send(int *word); +extern int ASCS_TC_send( int *word ); -extern int ASCS_TC_send_block(int *block, int ntrans); +extern int ASCS_TC_send_block( int *block, int ntrans ); -extern void ASCS_TC_sync_start(void); +extern void ASCS_TC_sync_start( void ); -extern void ASCS_TC_sync_stop(void); +extern void ASCS_TC_sync_stop( void ); -extern int ASCS_TM_recv(int *word); +extern int ASCS_TM_recv( int *word ); -extern int ASCS_TM_recv_block(int *block, int ntrans); +extern int ASCS_TM_recv_block( int *block, int ntrans ); #ifdef __cplusplus } diff --git a/bsps/include/grlib/grcan-regs.h b/bsps/include/grlib/grcan-regs.h index 85a5e56367..a6e727e939 100644 --- a/bsps/include/grlib/grcan-regs.h +++ b/bsps/include/grlib/grcan-regs.h @@ -82,69 +82,55 @@ extern "C" { */ #define GRCAN_CANCONF_SCALER_SHIFT 24 -#define GRCAN_CANCONF_SCALER_MASK 0xff000000U +#define GRCAN_CANCONF_SCALER_MASK 0xff000000U #define GRCAN_CANCONF_SCALER_GET( _reg ) \ - ( ( ( _reg ) & GRCAN_CANCONF_SCALER_MASK ) >> \ - GRCAN_CANCONF_SCALER_SHIFT ) -#define GRCAN_CANCONF_SCALER_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRCAN_CANCONF_SCALER_MASK ) | \ + ( ( ( _reg ) & GRCAN_CANCONF_SCALER_MASK ) >> GRCAN_CANCONF_SCALER_SHIFT ) +#define GRCAN_CANCONF_SCALER_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRCAN_CANCONF_SCALER_MASK ) | \ ( ( ( _val ) << GRCAN_CANCONF_SCALER_SHIFT ) & \ GRCAN_CANCONF_SCALER_MASK ) ) #define GRCAN_CANCONF_SCALER( _val ) \ - ( ( ( _val ) << GRCAN_CANCONF_SCALER_SHIFT ) & \ - GRCAN_CANCONF_SCALER_MASK ) + ( ( ( _val ) << GRCAN_CANCONF_SCALER_SHIFT ) & GRCAN_CANCONF_SCALER_MASK ) #define GRCAN_CANCONF_PS1_SHIFT 20 -#define GRCAN_CANCONF_PS1_MASK 0xf00000U +#define GRCAN_CANCONF_PS1_MASK 0xf00000U #define GRCAN_CANCONF_PS1_GET( _reg ) \ - ( ( ( _reg ) & GRCAN_CANCONF_PS1_MASK ) >> \ - GRCAN_CANCONF_PS1_SHIFT ) -#define GRCAN_CANCONF_PS1_SET( _reg, _val ) \ + ( ( ( _reg ) & GRCAN_CANCONF_PS1_MASK ) >> GRCAN_CANCONF_PS1_SHIFT ) +#define GRCAN_CANCONF_PS1_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRCAN_CANCONF_PS1_MASK ) | \ - ( ( ( _val ) << GRCAN_CANCONF_PS1_SHIFT ) & \ - GRCAN_CANCONF_PS1_MASK ) ) + ( ( ( _val ) << GRCAN_CANCONF_PS1_SHIFT ) & GRCAN_CANCONF_PS1_MASK ) ) #define GRCAN_CANCONF_PS1( _val ) \ - ( ( ( _val ) << GRCAN_CANCONF_PS1_SHIFT ) & \ - GRCAN_CANCONF_PS1_MASK ) + ( ( ( _val ) << GRCAN_CANCONF_PS1_SHIFT ) & GRCAN_CANCONF_PS1_MASK ) #define GRCAN_CANCONF_PS2_SHIFT 16 -#define GRCAN_CANCONF_PS2_MASK 0xf0000U +#define GRCAN_CANCONF_PS2_MASK 0xf0000U #define GRCAN_CANCONF_PS2_GET( _reg ) \ - ( ( ( _reg ) & GRCAN_CANCONF_PS2_MASK ) >> \ - GRCAN_CANCONF_PS2_SHIFT ) -#define GRCAN_CANCONF_PS2_SET( _reg, _val ) \ + ( ( ( _reg ) & GRCAN_CANCONF_PS2_MASK ) >> GRCAN_CANCONF_PS2_SHIFT ) +#define GRCAN_CANCONF_PS2_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRCAN_CANCONF_PS2_MASK ) | \ - ( ( ( _val ) << GRCAN_CANCONF_PS2_SHIFT ) & \ - GRCAN_CANCONF_PS2_MASK ) ) + ( ( ( _val ) << GRCAN_CANCONF_PS2_SHIFT ) & GRCAN_CANCONF_PS2_MASK ) ) #define GRCAN_CANCONF_PS2( _val ) \ - ( ( ( _val ) << GRCAN_CANCONF_PS2_SHIFT ) & \ - GRCAN_CANCONF_PS2_MASK ) + ( ( ( _val ) << GRCAN_CANCONF_PS2_SHIFT ) & GRCAN_CANCONF_PS2_MASK ) #define GRCAN_CANCONF_RSJ_SHIFT 12 -#define GRCAN_CANCONF_RSJ_MASK 0x7000U +#define GRCAN_CANCONF_RSJ_MASK 0x7000U #define GRCAN_CANCONF_RSJ_GET( _reg ) \ - ( ( ( _reg ) & GRCAN_CANCONF_RSJ_MASK ) >> \ - GRCAN_CANCONF_RSJ_SHIFT ) -#define GRCAN_CANCONF_RSJ_SET( _reg, _val ) \ + ( ( ( _reg ) & GRCAN_CANCONF_RSJ_MASK ) >> GRCAN_CANCONF_RSJ_SHIFT ) +#define GRCAN_CANCONF_RSJ_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRCAN_CANCONF_RSJ_MASK ) | \ - ( ( ( _val ) << GRCAN_CANCONF_RSJ_SHIFT ) & \ - GRCAN_CANCONF_RSJ_MASK ) ) + ( ( ( _val ) << GRCAN_CANCONF_RSJ_SHIFT ) & GRCAN_CANCONF_RSJ_MASK ) ) #define GRCAN_CANCONF_RSJ( _val ) \ - ( ( ( _val ) << GRCAN_CANCONF_RSJ_SHIFT ) & \ - GRCAN_CANCONF_RSJ_MASK ) + ( ( ( _val ) << GRCAN_CANCONF_RSJ_SHIFT ) & GRCAN_CANCONF_RSJ_MASK ) #define GRCAN_CANCONF_BPR_SHIFT 8 -#define GRCAN_CANCONF_BPR_MASK 0x300U +#define GRCAN_CANCONF_BPR_MASK 0x300U #define GRCAN_CANCONF_BPR_GET( _reg ) \ - ( ( ( _reg ) & GRCAN_CANCONF_BPR_MASK ) >> \ - GRCAN_CANCONF_BPR_SHIFT ) -#define GRCAN_CANCONF_BPR_SET( _reg, _val ) \ + ( ( ( _reg ) & GRCAN_CANCONF_BPR_MASK ) >> GRCAN_CANCONF_BPR_SHIFT ) +#define GRCAN_CANCONF_BPR_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRCAN_CANCONF_BPR_MASK ) | \ - ( ( ( _val ) << GRCAN_CANCONF_BPR_SHIFT ) & \ - GRCAN_CANCONF_BPR_MASK ) ) + ( ( ( _val ) << GRCAN_CANCONF_BPR_SHIFT ) & GRCAN_CANCONF_BPR_MASK ) ) #define GRCAN_CANCONF_BPR( _val ) \ - ( ( ( _val ) << GRCAN_CANCONF_BPR_SHIFT ) & \ - GRCAN_CANCONF_BPR_MASK ) + ( ( ( _val ) << GRCAN_CANCONF_BPR_SHIFT ) & GRCAN_CANCONF_BPR_MASK ) #define GRCAN_CANCONF_SAM 0x20U @@ -169,54 +155,54 @@ extern "C" { */ #define GRCAN_CANSTAT_TXCHANNELS_SHIFT 28 -#define GRCAN_CANSTAT_TXCHANNELS_MASK 0xf0000000U -#define GRCAN_CANSTAT_TXCHANNELS_GET( _reg ) \ +#define GRCAN_CANSTAT_TXCHANNELS_MASK 0xf0000000U +#define GRCAN_CANSTAT_TXCHANNELS_GET( _reg ) \ ( ( ( _reg ) & GRCAN_CANSTAT_TXCHANNELS_MASK ) >> \ GRCAN_CANSTAT_TXCHANNELS_SHIFT ) -#define GRCAN_CANSTAT_TXCHANNELS_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRCAN_CANSTAT_TXCHANNELS_MASK ) | \ +#define GRCAN_CANSTAT_TXCHANNELS_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRCAN_CANSTAT_TXCHANNELS_MASK ) | \ ( ( ( _val ) << GRCAN_CANSTAT_TXCHANNELS_SHIFT ) & \ GRCAN_CANSTAT_TXCHANNELS_MASK ) ) -#define GRCAN_CANSTAT_TXCHANNELS( _val ) \ +#define GRCAN_CANSTAT_TXCHANNELS( _val ) \ ( ( ( _val ) << GRCAN_CANSTAT_TXCHANNELS_SHIFT ) & \ GRCAN_CANSTAT_TXCHANNELS_MASK ) #define GRCAN_CANSTAT_RXCHANNELS_SHIFT 24 -#define GRCAN_CANSTAT_RXCHANNELS_MASK 0xf000000U -#define GRCAN_CANSTAT_RXCHANNELS_GET( _reg ) \ +#define GRCAN_CANSTAT_RXCHANNELS_MASK 0xf000000U +#define GRCAN_CANSTAT_RXCHANNELS_GET( _reg ) \ ( ( ( _reg ) & GRCAN_CANSTAT_RXCHANNELS_MASK ) >> \ GRCAN_CANSTAT_RXCHANNELS_SHIFT ) -#define GRCAN_CANSTAT_RXCHANNELS_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRCAN_CANSTAT_RXCHANNELS_MASK ) | \ +#define GRCAN_CANSTAT_RXCHANNELS_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRCAN_CANSTAT_RXCHANNELS_MASK ) | \ ( ( ( _val ) << GRCAN_CANSTAT_RXCHANNELS_SHIFT ) & \ GRCAN_CANSTAT_RXCHANNELS_MASK ) ) -#define GRCAN_CANSTAT_RXCHANNELS( _val ) \ +#define GRCAN_CANSTAT_RXCHANNELS( _val ) \ ( ( ( _val ) << GRCAN_CANSTAT_RXCHANNELS_SHIFT ) & \ GRCAN_CANSTAT_RXCHANNELS_MASK ) #define GRCAN_CANSTAT_TXERRCNT_SHIFT 16 -#define GRCAN_CANSTAT_TXERRCNT_MASK 0xff0000U -#define GRCAN_CANSTAT_TXERRCNT_GET( _reg ) \ +#define GRCAN_CANSTAT_TXERRCNT_MASK 0xff0000U +#define GRCAN_CANSTAT_TXERRCNT_GET( _reg ) \ ( ( ( _reg ) & GRCAN_CANSTAT_TXERRCNT_MASK ) >> \ GRCAN_CANSTAT_TXERRCNT_SHIFT ) -#define GRCAN_CANSTAT_TXERRCNT_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRCAN_CANSTAT_TXERRCNT_MASK ) | \ +#define GRCAN_CANSTAT_TXERRCNT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRCAN_CANSTAT_TXERRCNT_MASK ) | \ ( ( ( _val ) << GRCAN_CANSTAT_TXERRCNT_SHIFT ) & \ GRCAN_CANSTAT_TXERRCNT_MASK ) ) -#define GRCAN_CANSTAT_TXERRCNT( _val ) \ +#define GRCAN_CANSTAT_TXERRCNT( _val ) \ ( ( ( _val ) << GRCAN_CANSTAT_TXERRCNT_SHIFT ) & \ GRCAN_CANSTAT_TXERRCNT_MASK ) #define GRCAN_CANSTAT_RXERRCNT_SHIFT 8 -#define GRCAN_CANSTAT_RXERRCNT_MASK 0xff00U -#define GRCAN_CANSTAT_RXERRCNT_GET( _reg ) \ +#define GRCAN_CANSTAT_RXERRCNT_MASK 0xff00U +#define GRCAN_CANSTAT_RXERRCNT_GET( _reg ) \ ( ( ( _reg ) & GRCAN_CANSTAT_RXERRCNT_MASK ) >> \ GRCAN_CANSTAT_RXERRCNT_SHIFT ) -#define GRCAN_CANSTAT_RXERRCNT_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRCAN_CANSTAT_RXERRCNT_MASK ) | \ +#define GRCAN_CANSTAT_RXERRCNT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRCAN_CANSTAT_RXERRCNT_MASK ) | \ ( ( ( _val ) << GRCAN_CANSTAT_RXERRCNT_SHIFT ) & \ GRCAN_CANSTAT_RXERRCNT_MASK ) ) -#define GRCAN_CANSTAT_RXERRCNT( _val ) \ +#define GRCAN_CANSTAT_RXERRCNT( _val ) \ ( ( ( _val ) << GRCAN_CANSTAT_RXERRCNT_SHIFT ) & \ GRCAN_CANSTAT_RXERRCNT_MASK ) @@ -255,17 +241,14 @@ extern "C" { */ #define GRCAN_CANMASK_MASK_SHIFT 0 -#define GRCAN_CANMASK_MASK_MASK 0x1fffffffU +#define GRCAN_CANMASK_MASK_MASK 0x1fffffffU #define GRCAN_CANMASK_MASK_GET( _reg ) \ - ( ( ( _reg ) & GRCAN_CANMASK_MASK_MASK ) >> \ - GRCAN_CANMASK_MASK_SHIFT ) -#define GRCAN_CANMASK_MASK_SET( _reg, _val ) \ + ( ( ( _reg ) & GRCAN_CANMASK_MASK_MASK ) >> GRCAN_CANMASK_MASK_SHIFT ) +#define GRCAN_CANMASK_MASK_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRCAN_CANMASK_MASK_MASK ) | \ - ( ( ( _val ) << GRCAN_CANMASK_MASK_SHIFT ) & \ - GRCAN_CANMASK_MASK_MASK ) ) + ( ( ( _val ) << GRCAN_CANMASK_MASK_SHIFT ) & GRCAN_CANMASK_MASK_MASK ) ) #define GRCAN_CANMASK_MASK( _val ) \ - ( ( ( _val ) << GRCAN_CANMASK_MASK_SHIFT ) & \ - GRCAN_CANMASK_MASK_MASK ) + ( ( ( _val ) << GRCAN_CANMASK_MASK_SHIFT ) & GRCAN_CANMASK_MASK_MASK ) /** @} */ @@ -278,17 +261,14 @@ extern "C" { */ #define GRCAN_CANCODE_SYNC_SHIFT 0 -#define GRCAN_CANCODE_SYNC_MASK 0x1fffffffU +#define GRCAN_CANCODE_SYNC_MASK 0x1fffffffU #define GRCAN_CANCODE_SYNC_GET( _reg ) \ - ( ( ( _reg ) & GRCAN_CANCODE_SYNC_MASK ) >> \ - GRCAN_CANCODE_SYNC_SHIFT ) -#define GRCAN_CANCODE_SYNC_SET( _reg, _val ) \ + ( ( ( _reg ) & GRCAN_CANCODE_SYNC_MASK ) >> GRCAN_CANCODE_SYNC_SHIFT ) +#define GRCAN_CANCODE_SYNC_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRCAN_CANCODE_SYNC_MASK ) | \ - ( ( ( _val ) << GRCAN_CANCODE_SYNC_SHIFT ) & \ - GRCAN_CANCODE_SYNC_MASK ) ) + ( ( ( _val ) << GRCAN_CANCODE_SYNC_SHIFT ) & GRCAN_CANCODE_SYNC_MASK ) ) #define GRCAN_CANCODE_SYNC( _val ) \ - ( ( ( _val ) << GRCAN_CANCODE_SYNC_SHIFT ) & \ - GRCAN_CANCODE_SYNC_MASK ) + ( ( ( _val ) << GRCAN_CANCODE_SYNC_SHIFT ) & GRCAN_CANCODE_SYNC_MASK ) /** @} */ @@ -319,17 +299,15 @@ extern "C" { */ #define GRCAN_CANTXADDR_ADDR_SHIFT 10 -#define GRCAN_CANTXADDR_ADDR_MASK 0xfffffc00U +#define GRCAN_CANTXADDR_ADDR_MASK 0xfffffc00U #define GRCAN_CANTXADDR_ADDR_GET( _reg ) \ - ( ( ( _reg ) & GRCAN_CANTXADDR_ADDR_MASK ) >> \ - GRCAN_CANTXADDR_ADDR_SHIFT ) -#define GRCAN_CANTXADDR_ADDR_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRCAN_CANTXADDR_ADDR_MASK ) | \ + ( ( ( _reg ) & GRCAN_CANTXADDR_ADDR_MASK ) >> GRCAN_CANTXADDR_ADDR_SHIFT ) +#define GRCAN_CANTXADDR_ADDR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRCAN_CANTXADDR_ADDR_MASK ) | \ ( ( ( _val ) << GRCAN_CANTXADDR_ADDR_SHIFT ) & \ GRCAN_CANTXADDR_ADDR_MASK ) ) #define GRCAN_CANTXADDR_ADDR( _val ) \ - ( ( ( _val ) << GRCAN_CANTXADDR_ADDR_SHIFT ) & \ - GRCAN_CANTXADDR_ADDR_MASK ) + ( ( ( _val ) << GRCAN_CANTXADDR_ADDR_SHIFT ) & GRCAN_CANTXADDR_ADDR_MASK ) /** @} */ @@ -343,17 +321,15 @@ extern "C" { */ #define GRCAN_CANTXSIZE_SIZE_SHIFT 6 -#define GRCAN_CANTXSIZE_SIZE_MASK 0x1fffc0U +#define GRCAN_CANTXSIZE_SIZE_MASK 0x1fffc0U #define GRCAN_CANTXSIZE_SIZE_GET( _reg ) \ - ( ( ( _reg ) & GRCAN_CANTXSIZE_SIZE_MASK ) >> \ - GRCAN_CANTXSIZE_SIZE_SHIFT ) -#define GRCAN_CANTXSIZE_SIZE_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRCAN_CANTXSIZE_SIZE_MASK ) | \ + ( ( ( _reg ) & GRCAN_CANTXSIZE_SIZE_MASK ) >> GRCAN_CANTXSIZE_SIZE_SHIFT ) +#define GRCAN_CANTXSIZE_SIZE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRCAN_CANTXSIZE_SIZE_MASK ) | \ ( ( ( _val ) << GRCAN_CANTXSIZE_SIZE_SHIFT ) & \ GRCAN_CANTXSIZE_SIZE_MASK ) ) #define GRCAN_CANTXSIZE_SIZE( _val ) \ - ( ( ( _val ) << GRCAN_CANTXSIZE_SIZE_SHIFT ) & \ - GRCAN_CANTXSIZE_SIZE_MASK ) + ( ( ( _val ) << GRCAN_CANTXSIZE_SIZE_SHIFT ) & GRCAN_CANTXSIZE_SIZE_MASK ) /** @} */ @@ -366,17 +342,15 @@ extern "C" { */ #define GRCAN_CANTXWR_WRITE_SHIFT 4 -#define GRCAN_CANTXWR_WRITE_MASK 0xffff0U +#define GRCAN_CANTXWR_WRITE_MASK 0xffff0U #define GRCAN_CANTXWR_WRITE_GET( _reg ) \ - ( ( ( _reg ) & GRCAN_CANTXWR_WRITE_MASK ) >> \ - GRCAN_CANTXWR_WRITE_SHIFT ) -#define GRCAN_CANTXWR_WRITE_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRCAN_CANTXWR_WRITE_MASK ) | \ + ( ( ( _reg ) & GRCAN_CANTXWR_WRITE_MASK ) >> GRCAN_CANTXWR_WRITE_SHIFT ) +#define GRCAN_CANTXWR_WRITE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRCAN_CANTXWR_WRITE_MASK ) | \ ( ( ( _val ) << GRCAN_CANTXWR_WRITE_SHIFT ) & \ GRCAN_CANTXWR_WRITE_MASK ) ) #define GRCAN_CANTXWR_WRITE( _val ) \ - ( ( ( _val ) << GRCAN_CANTXWR_WRITE_SHIFT ) & \ - GRCAN_CANTXWR_WRITE_MASK ) + ( ( ( _val ) << GRCAN_CANTXWR_WRITE_SHIFT ) & GRCAN_CANTXWR_WRITE_MASK ) /** @} */ @@ -389,17 +363,14 @@ extern "C" { */ #define GRCAN_CANTXRD_READ_SHIFT 4 -#define GRCAN_CANTXRD_READ_MASK 0xffff0U +#define GRCAN_CANTXRD_READ_MASK 0xffff0U #define GRCAN_CANTXRD_READ_GET( _reg ) \ - ( ( ( _reg ) & GRCAN_CANTXRD_READ_MASK ) >> \ - GRCAN_CANTXRD_READ_SHIFT ) -#define GRCAN_CANTXRD_READ_SET( _reg, _val ) \ + ( ( ( _reg ) & GRCAN_CANTXRD_READ_MASK ) >> GRCAN_CANTXRD_READ_SHIFT ) +#define GRCAN_CANTXRD_READ_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRCAN_CANTXRD_READ_MASK ) | \ - ( ( ( _val ) << GRCAN_CANTXRD_READ_SHIFT ) & \ - GRCAN_CANTXRD_READ_MASK ) ) + ( ( ( _val ) << GRCAN_CANTXRD_READ_SHIFT ) & GRCAN_CANTXRD_READ_MASK ) ) #define GRCAN_CANTXRD_READ( _val ) \ - ( ( ( _val ) << GRCAN_CANTXRD_READ_SHIFT ) & \ - GRCAN_CANTXRD_READ_MASK ) + ( ( ( _val ) << GRCAN_CANTXRD_READ_SHIFT ) & GRCAN_CANTXRD_READ_MASK ) /** @} */ @@ -413,17 +384,14 @@ extern "C" { */ #define GRCAN_CANTXIRQ_IRQ_SHIFT 4 -#define GRCAN_CANTXIRQ_IRQ_MASK 0xffff0U +#define GRCAN_CANTXIRQ_IRQ_MASK 0xffff0U #define GRCAN_CANTXIRQ_IRQ_GET( _reg ) \ - ( ( ( _reg ) & GRCAN_CANTXIRQ_IRQ_MASK ) >> \ - GRCAN_CANTXIRQ_IRQ_SHIFT ) -#define GRCAN_CANTXIRQ_IRQ_SET( _reg, _val ) \ + ( ( ( _reg ) & GRCAN_CANTXIRQ_IRQ_MASK ) >> GRCAN_CANTXIRQ_IRQ_SHIFT ) +#define GRCAN_CANTXIRQ_IRQ_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRCAN_CANTXIRQ_IRQ_MASK ) | \ - ( ( ( _val ) << GRCAN_CANTXIRQ_IRQ_SHIFT ) & \ - GRCAN_CANTXIRQ_IRQ_MASK ) ) + ( ( ( _val ) << GRCAN_CANTXIRQ_IRQ_SHIFT ) & GRCAN_CANTXIRQ_IRQ_MASK ) ) #define GRCAN_CANTXIRQ_IRQ( _val ) \ - ( ( ( _val ) << GRCAN_CANTXIRQ_IRQ_SHIFT ) & \ - GRCAN_CANTXIRQ_IRQ_MASK ) + ( ( ( _val ) << GRCAN_CANTXIRQ_IRQ_SHIFT ) & GRCAN_CANTXIRQ_IRQ_MASK ) /** @} */ @@ -452,17 +420,15 @@ extern "C" { */ #define GRCAN_CANRXADDR_ADDR_SHIFT 10 -#define GRCAN_CANRXADDR_ADDR_MASK 0xfffffc00U +#define GRCAN_CANRXADDR_ADDR_MASK 0xfffffc00U #define GRCAN_CANRXADDR_ADDR_GET( _reg ) \ - ( ( ( _reg ) & GRCAN_CANRXADDR_ADDR_MASK ) >> \ - GRCAN_CANRXADDR_ADDR_SHIFT ) -#define GRCAN_CANRXADDR_ADDR_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRCAN_CANRXADDR_ADDR_MASK ) | \ + ( ( ( _reg ) & GRCAN_CANRXADDR_ADDR_MASK ) >> GRCAN_CANRXADDR_ADDR_SHIFT ) +#define GRCAN_CANRXADDR_ADDR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRCAN_CANRXADDR_ADDR_MASK ) | \ ( ( ( _val ) << GRCAN_CANRXADDR_ADDR_SHIFT ) & \ GRCAN_CANRXADDR_ADDR_MASK ) ) #define GRCAN_CANRXADDR_ADDR( _val ) \ - ( ( ( _val ) << GRCAN_CANRXADDR_ADDR_SHIFT ) & \ - GRCAN_CANRXADDR_ADDR_MASK ) + ( ( ( _val ) << GRCAN_CANRXADDR_ADDR_SHIFT ) & GRCAN_CANRXADDR_ADDR_MASK ) /** @} */ @@ -476,17 +442,15 @@ extern "C" { */ #define GRCAN_CANRXSIZE_SIZE_SHIFT 6 -#define GRCAN_CANRXSIZE_SIZE_MASK 0x1fffc0U +#define GRCAN_CANRXSIZE_SIZE_MASK 0x1fffc0U #define GRCAN_CANRXSIZE_SIZE_GET( _reg ) \ - ( ( ( _reg ) & GRCAN_CANRXSIZE_SIZE_MASK ) >> \ - GRCAN_CANRXSIZE_SIZE_SHIFT ) -#define GRCAN_CANRXSIZE_SIZE_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRCAN_CANRXSIZE_SIZE_MASK ) | \ + ( ( ( _reg ) & GRCAN_CANRXSIZE_SIZE_MASK ) >> GRCAN_CANRXSIZE_SIZE_SHIFT ) +#define GRCAN_CANRXSIZE_SIZE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRCAN_CANRXSIZE_SIZE_MASK ) | \ ( ( ( _val ) << GRCAN_CANRXSIZE_SIZE_SHIFT ) & \ GRCAN_CANRXSIZE_SIZE_MASK ) ) #define GRCAN_CANRXSIZE_SIZE( _val ) \ - ( ( ( _val ) << GRCAN_CANRXSIZE_SIZE_SHIFT ) & \ - GRCAN_CANRXSIZE_SIZE_MASK ) + ( ( ( _val ) << GRCAN_CANRXSIZE_SIZE_SHIFT ) & GRCAN_CANRXSIZE_SIZE_MASK ) /** @} */ @@ -499,17 +463,15 @@ extern "C" { */ #define GRCAN_CANRXWR_WRITE_SHIFT 4 -#define GRCAN_CANRXWR_WRITE_MASK 0xffff0U +#define GRCAN_CANRXWR_WRITE_MASK 0xffff0U #define GRCAN_CANRXWR_WRITE_GET( _reg ) \ - ( ( ( _reg ) & GRCAN_CANRXWR_WRITE_MASK ) >> \ - GRCAN_CANRXWR_WRITE_SHIFT ) -#define GRCAN_CANRXWR_WRITE_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRCAN_CANRXWR_WRITE_MASK ) | \ + ( ( ( _reg ) & GRCAN_CANRXWR_WRITE_MASK ) >> GRCAN_CANRXWR_WRITE_SHIFT ) +#define GRCAN_CANRXWR_WRITE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRCAN_CANRXWR_WRITE_MASK ) | \ ( ( ( _val ) << GRCAN_CANRXWR_WRITE_SHIFT ) & \ GRCAN_CANRXWR_WRITE_MASK ) ) #define GRCAN_CANRXWR_WRITE( _val ) \ - ( ( ( _val ) << GRCAN_CANRXWR_WRITE_SHIFT ) & \ - GRCAN_CANRXWR_WRITE_MASK ) + ( ( ( _val ) << GRCAN_CANRXWR_WRITE_SHIFT ) & GRCAN_CANRXWR_WRITE_MASK ) /** @} */ @@ -522,17 +484,14 @@ extern "C" { */ #define GRCAN_CANRXRD_READ_SHIFT 4 -#define GRCAN_CANRXRD_READ_MASK 0xffff0U +#define GRCAN_CANRXRD_READ_MASK 0xffff0U #define GRCAN_CANRXRD_READ_GET( _reg ) \ - ( ( ( _reg ) & GRCAN_CANRXRD_READ_MASK ) >> \ - GRCAN_CANRXRD_READ_SHIFT ) -#define GRCAN_CANRXRD_READ_SET( _reg, _val ) \ + ( ( ( _reg ) & GRCAN_CANRXRD_READ_MASK ) >> GRCAN_CANRXRD_READ_SHIFT ) +#define GRCAN_CANRXRD_READ_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRCAN_CANRXRD_READ_MASK ) | \ - ( ( ( _val ) << GRCAN_CANRXRD_READ_SHIFT ) & \ - GRCAN_CANRXRD_READ_MASK ) ) + ( ( ( _val ) << GRCAN_CANRXRD_READ_SHIFT ) & GRCAN_CANRXRD_READ_MASK ) ) #define GRCAN_CANRXRD_READ( _val ) \ - ( ( ( _val ) << GRCAN_CANRXRD_READ_SHIFT ) & \ - GRCAN_CANRXRD_READ_MASK ) + ( ( ( _val ) << GRCAN_CANRXRD_READ_SHIFT ) & GRCAN_CANRXRD_READ_MASK ) /** @} */ @@ -546,17 +505,14 @@ extern "C" { */ #define GRCAN_CANRXIRQ_IRQ_SHIFT 4 -#define GRCAN_CANRXIRQ_IRQ_MASK 0xffff0U +#define GRCAN_CANRXIRQ_IRQ_MASK 0xffff0U #define GRCAN_CANRXIRQ_IRQ_GET( _reg ) \ - ( ( ( _reg ) & GRCAN_CANRXIRQ_IRQ_MASK ) >> \ - GRCAN_CANRXIRQ_IRQ_SHIFT ) -#define GRCAN_CANRXIRQ_IRQ_SET( _reg, _val ) \ + ( ( ( _reg ) & GRCAN_CANRXIRQ_IRQ_MASK ) >> GRCAN_CANRXIRQ_IRQ_SHIFT ) +#define GRCAN_CANRXIRQ_IRQ_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRCAN_CANRXIRQ_IRQ_MASK ) | \ - ( ( ( _val ) << GRCAN_CANRXIRQ_IRQ_SHIFT ) & \ - GRCAN_CANRXIRQ_IRQ_MASK ) ) + ( ( ( _val ) << GRCAN_CANRXIRQ_IRQ_SHIFT ) & GRCAN_CANRXIRQ_IRQ_MASK ) ) #define GRCAN_CANRXIRQ_IRQ( _val ) \ - ( ( ( _val ) << GRCAN_CANRXIRQ_IRQ_SHIFT ) & \ - GRCAN_CANRXIRQ_IRQ_MASK ) + ( ( ( _val ) << GRCAN_CANRXIRQ_IRQ_SHIFT ) & GRCAN_CANRXIRQ_IRQ_MASK ) /** @} */ @@ -570,17 +526,14 @@ extern "C" { */ #define GRCAN_CANRXMASK_AM_SHIFT 0 -#define GRCAN_CANRXMASK_AM_MASK 0x1fffffffU +#define GRCAN_CANRXMASK_AM_MASK 0x1fffffffU #define GRCAN_CANRXMASK_AM_GET( _reg ) \ - ( ( ( _reg ) & GRCAN_CANRXMASK_AM_MASK ) >> \ - GRCAN_CANRXMASK_AM_SHIFT ) -#define GRCAN_CANRXMASK_AM_SET( _reg, _val ) \ + ( ( ( _reg ) & GRCAN_CANRXMASK_AM_MASK ) >> GRCAN_CANRXMASK_AM_SHIFT ) +#define GRCAN_CANRXMASK_AM_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRCAN_CANRXMASK_AM_MASK ) | \ - ( ( ( _val ) << GRCAN_CANRXMASK_AM_SHIFT ) & \ - GRCAN_CANRXMASK_AM_MASK ) ) + ( ( ( _val ) << GRCAN_CANRXMASK_AM_SHIFT ) & GRCAN_CANRXMASK_AM_MASK ) ) #define GRCAN_CANRXMASK_AM( _val ) \ - ( ( ( _val ) << GRCAN_CANRXMASK_AM_SHIFT ) & \ - GRCAN_CANRXMASK_AM_MASK ) + ( ( ( _val ) << GRCAN_CANRXMASK_AM_SHIFT ) & GRCAN_CANRXMASK_AM_MASK ) /** @} */ @@ -594,17 +547,14 @@ extern "C" { */ #define GRCAN_CANRXCODE_AC_SHIFT 0 -#define GRCAN_CANRXCODE_AC_MASK 0x1fffffffU +#define GRCAN_CANRXCODE_AC_MASK 0x1fffffffU #define GRCAN_CANRXCODE_AC_GET( _reg ) \ - ( ( ( _reg ) & GRCAN_CANRXCODE_AC_MASK ) >> \ - GRCAN_CANRXCODE_AC_SHIFT ) -#define GRCAN_CANRXCODE_AC_SET( _reg, _val ) \ + ( ( ( _reg ) & GRCAN_CANRXCODE_AC_MASK ) >> GRCAN_CANRXCODE_AC_SHIFT ) +#define GRCAN_CANRXCODE_AC_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRCAN_CANRXCODE_AC_MASK ) | \ - ( ( ( _val ) << GRCAN_CANRXCODE_AC_SHIFT ) & \ - GRCAN_CANRXCODE_AC_MASK ) ) + ( ( ( _val ) << GRCAN_CANRXCODE_AC_SHIFT ) & GRCAN_CANRXCODE_AC_MASK ) ) #define GRCAN_CANRXCODE_AC( _val ) \ - ( ( ( _val ) << GRCAN_CANRXCODE_AC_SHIFT ) & \ - GRCAN_CANRXCODE_AC_MASK ) + ( ( ( _val ) << GRCAN_CANRXCODE_AC_SHIFT ) & GRCAN_CANRXCODE_AC_MASK ) /** @} */ diff --git a/bsps/include/grlib/grcan.h b/bsps/include/grlib/grcan.h index d67c3f789c..29434e008e 100644 --- a/bsps/include/grlib/grcan.h +++ b/bsps/include/grlib/grcan.h @@ -52,124 +52,125 @@ extern "C" { #endif struct grcan_regs { - volatile uint32_t conf; /* 0x00 */ - volatile uint32_t stat; /* 0x04 */ - volatile uint32_t ctrl; /* 0x08 */ - volatile uint32_t dummy0[3]; /* 0x0C-0x014 */ - volatile uint32_t smask; /* 0x18 */ - volatile uint32_t scode; /* 0x1C */ + volatile uint32_t conf; /* 0x00 */ + volatile uint32_t stat; /* 0x04 */ + volatile uint32_t ctrl; /* 0x08 */ + volatile uint32_t dummy0[ 3 ]; /* 0x0C-0x014 */ + volatile uint32_t smask; /* 0x18 */ + volatile uint32_t scode; /* 0x1C */ - volatile uint32_t dummy1[8]; /* 0x20-0x3C */ + volatile uint32_t dummy1[ 8 ]; /* 0x20-0x3C */ - volatile uint32_t nbtr; /* 0x40 */ - volatile uint32_t fdbtr; /* 0x44 */ - volatile uint32_t tdelay; /* 0x48 */ + volatile uint32_t nbtr; /* 0x40 */ + volatile uint32_t fdbtr; /* 0x44 */ + volatile uint32_t tdelay; /* 0x48 */ - volatile uint32_t dummy1b[45]; /* 0x4C-0xFC */ + volatile uint32_t dummy1b[ 45 ]; /* 0x4C-0xFC */ - volatile uint32_t pimsr; /* 0x100 */ - volatile uint32_t pimr; /* 0x104 */ - volatile uint32_t pisr; /* 0x108 */ - volatile uint32_t pir; /* 0x10C */ - volatile uint32_t imr; /* 0x110 */ - volatile uint32_t picr; /* 0x114 */ + volatile uint32_t pimsr; /* 0x100 */ + volatile uint32_t pimr; /* 0x104 */ + volatile uint32_t pisr; /* 0x108 */ + volatile uint32_t pir; /* 0x10C */ + volatile uint32_t imr; /* 0x110 */ + volatile uint32_t picr; /* 0x114 */ - volatile uint32_t dummy2[58]; /* 0x118-0x1FC */ + volatile uint32_t dummy2[ 58 ]; /* 0x118-0x1FC */ - volatile uint32_t tx0ctrl; /* 0x200 */ - volatile uint32_t tx0addr; /* 0x204 */ - volatile uint32_t tx0size; /* 0x208 */ - volatile uint32_t tx0wr; /* 0x20C */ - volatile uint32_t tx0rd; /* 0x210 */ - volatile uint32_t tx0irq; /* 0x214 */ + volatile uint32_t tx0ctrl; /* 0x200 */ + volatile uint32_t tx0addr; /* 0x204 */ + volatile uint32_t tx0size; /* 0x208 */ + volatile uint32_t tx0wr; /* 0x20C */ + volatile uint32_t tx0rd; /* 0x210 */ + volatile uint32_t tx0irq; /* 0x214 */ - volatile uint32_t dummy3[58]; /* 0x218-0x2FC */ + volatile uint32_t dummy3[ 58 ]; /* 0x218-0x2FC */ - volatile uint32_t rx0ctrl; /* 0x300 */ - volatile uint32_t rx0addr; /* 0x304 */ - volatile uint32_t rx0size; /* 0x308 */ - volatile uint32_t rx0wr; /* 0x30C */ - volatile uint32_t rx0rd; /* 0x310 */ - volatile uint32_t rx0irq; /* 0x314 */ - volatile uint32_t rx0mask; /* 0x318 */ - volatile uint32_t rx0code; /* 0x31C */ + volatile uint32_t rx0ctrl; /* 0x300 */ + volatile uint32_t rx0addr; /* 0x304 */ + volatile uint32_t rx0size; /* 0x308 */ + volatile uint32_t rx0wr; /* 0x30C */ + volatile uint32_t rx0rd; /* 0x310 */ + volatile uint32_t rx0irq; /* 0x314 */ + volatile uint32_t rx0mask; /* 0x318 */ + volatile uint32_t rx0code; /* 0x31C */ }; struct grcan_stats { - unsigned int passive_cnt; - unsigned int overrun_cnt; - unsigned int rxsync_cnt; - unsigned int txsync_cnt; - unsigned int txloss_cnt; - unsigned int ahberr_cnt; - unsigned int ints; - unsigned int busoff_cnt; + unsigned int passive_cnt; + unsigned int overrun_cnt; + unsigned int rxsync_cnt; + unsigned int txsync_cnt; + unsigned int txloss_cnt; + unsigned int ahberr_cnt; + unsigned int ints; + unsigned int busoff_cnt; }; struct grcan_timing { - unsigned char scaler; - unsigned char ps1; - unsigned char ps2; - unsigned char rsj; - unsigned char bpr; + unsigned char scaler; + unsigned char ps1; + unsigned char ps2; + unsigned char rsj; + unsigned char bpr; }; struct grcanfd_timing { - unsigned char scaler; - unsigned char ps1; - unsigned char ps2; - unsigned char sjw; - unsigned char resv_zero; + unsigned char scaler; + unsigned char ps1; + unsigned char ps2; + unsigned char sjw; + unsigned char resv_zero; }; struct grcan_selection { - int selection; - int enable0; - int enable1; + int selection; + int enable0; + int enable1; }; struct grcan_filter { - unsigned long long mask; - unsigned long long code; + unsigned long long mask; + unsigned long long code; }; #define GRCAN_FDOPT_NOM 0 #define GRCAN_FDOPT_FDBTR 0x01 #define GRCAN_FDOPT_FDFRM 0x02 -#define GRCAN_FDMASK (GRCAN_FDOPT_FDBTR | GRCAN_FDOPT_FDFRM) +#define GRCAN_FDMASK ( GRCAN_FDOPT_FDBTR | GRCAN_FDOPT_FDFRM ) /* CAN MESSAGE */ typedef struct { - char extended; /* 1= Extended Frame (29-bit id), 0= STD Frame (11-bit id) */ - char rtr; /* RTR - Remote Transmission Request */ - char unused; /* Must be 0 to select classic CAN frame */ - unsigned char len; - unsigned char data[8]; - unsigned int id; + char extended; /* 1= Extended Frame (29-bit id), 0= STD Frame (11-bit id) */ + char rtr; /* RTR - Remote Transmission Request */ + char unused; /* Must be 0 to select classic CAN frame */ + unsigned char len; + unsigned char data[ 8 ]; + unsigned int id; } CANMsg; /* CAN-FD MESSAGE */ typedef struct { - uint8_t extended; /* 1= Extended Frame (29-bit id), 0= STD Frame (11-bit id) */ - uint8_t rtr; /* RTR - Remote Transmission Request */ - uint8_t fdopts; /* Bit1: 1=Switch bit rate. bit2: 1=FD frame. */ - uint8_t len; /* 0-8, 12, 16, 20, 24, 32, 48 or 64 bytes */ - uint32_t id; - union { - uint64_t dwords[8]; /* up to 64 bytes if FD=1 and len>8 */ - uint8_t bytes[64]; /* up to 64 bytes if FD=1 and len>8 */ - } data; + uint8_t + extended; /* 1= Extended Frame (29-bit id), 0= STD Frame (11-bit id) */ + uint8_t rtr; /* RTR - Remote Transmission Request */ + uint8_t fdopts; /* Bit1: 1=Switch bit rate. bit2: 1=FD frame. */ + uint8_t len; /* 0-8, 12, 16, 20, 24, 32, 48 or 64 bytes */ + uint32_t id; + union { + uint64_t dwords[ 8 ]; /* up to 64 bytes if FD=1 and len>8 */ + uint8_t bytes[ 64 ]; /* up to 64 bytes if FD=1 and len>8 */ + } data; } CANFDMsg; enum { - GRCAN_RET_OK = 0, - GRCAN_RET_INVARG = -1, - GRCAN_RET_NOTSTARTED = -2, - GRCAN_RET_TIMEOUT = -3, - /* Bus-off condition detected (request aborted by driver) */ - GRCAN_RET_BUSOFF = -4, - /* AHB error condition detected (request aborted by driver) */ - GRCAN_RET_AHBERR = -5, + GRCAN_RET_OK = 0, + GRCAN_RET_INVARG = -1, + GRCAN_RET_NOTSTARTED = -2, + GRCAN_RET_TIMEOUT = -3, + /* Bus-off condition detected (request aborted by driver) */ + GRCAN_RET_BUSOFF = -4, + /* AHB error condition detected (request aborted by driver) */ + GRCAN_RET_AHBERR = -5, }; /* @@ -188,22 +189,22 @@ enum { * disables DMA, masks all interrupts and releases semaphores. */ enum grcan_state { - STATE_STOPPED = 0, - STATE_STARTED = 1, - STATE_BUSOFF = 2, - STATE_AHBERR = 3, + STATE_STOPPED = 0, + STATE_STARTED = 1, + STATE_BUSOFF = 2, + STATE_AHBERR = 3, }; -#define GRCAN_CFG_ABORT 0x00000001 -#define GRCAN_CFG_ENABLE0 0x00000002 -#define GRCAN_CFG_ENABLE1 0x00000004 -#define GRCAN_CFG_SELECTION 0x00000008 -#define GRCAN_CFG_SILENT 0x00000010 -#define GRCAN_CFG_BPR 0x00000300 -#define GRCAN_CFG_RSJ 0x00007000 -#define GRCAN_CFG_PS1 0x00f00000 -#define GRCAN_CFG_PS2 0x000f0000 -#define GRCAN_CFG_SCALER 0xff000000 +#define GRCAN_CFG_ABORT 0x00000001 +#define GRCAN_CFG_ENABLE0 0x00000002 +#define GRCAN_CFG_ENABLE1 0x00000004 +#define GRCAN_CFG_SELECTION 0x00000008 +#define GRCAN_CFG_SILENT 0x00000010 +#define GRCAN_CFG_BPR 0x00000300 +#define GRCAN_CFG_RSJ 0x00007000 +#define GRCAN_CFG_PS1 0x00f00000 +#define GRCAN_CFG_PS2 0x000f0000 +#define GRCAN_CFG_SCALER 0xff000000 #define GRCAN_CFG_BPR_BIT 8 #define GRCAN_CFG_RSJ_BIT 12 @@ -214,67 +215,67 @@ enum grcan_state { #define GRCAN_CTRL_RESET 0x2 #define GRCAN_CTRL_ENABLE 0x1 -#define GRCAN_TXCTRL_ENABLE 1 +#define GRCAN_TXCTRL_ENABLE 1 #define GRCAN_TXCTRL_ONGOING 1 -#define GRCAN_RXCTRL_ENABLE 1 +#define GRCAN_RXCTRL_ENABLE 1 #define GRCAN_RXCTRL_ONGOING 1 #define GRCANFD_NBTR_SCALER 0x00ff0000 -#define GRCANFD_NBTR_PS1 0x0000fc00 -#define GRCANFD_NBTR_PS2 0x000003e0 -#define GRCANFD_NBTR_SJW 0x0000001f +#define GRCANFD_NBTR_PS1 0x0000fc00 +#define GRCANFD_NBTR_PS2 0x000003e0 +#define GRCANFD_NBTR_SJW 0x0000001f #define GRCANFD_NBTR_SCALER_BIT 16 -#define GRCANFD_NBTR_PS1_BIT 10 -#define GRCANFD_NBTR_PS2_BIT 5 -#define GRCANFD_NBTR_SJW_BIT 0 +#define GRCANFD_NBTR_PS1_BIT 10 +#define GRCANFD_NBTR_PS2_BIT 5 +#define GRCANFD_NBTR_SJW_BIT 0 #define GRCANFD_FDBTR_SCALER 0x00ff0000 -#define GRCANFD_FDBTR_PS1 0x00003c00 -#define GRCANFD_FDBTR_PS2 0x000001e0 -#define GRCANFD_FDBTR_SJW 0x0000000f +#define GRCANFD_FDBTR_PS1 0x00003c00 +#define GRCANFD_FDBTR_PS2 0x000001e0 +#define GRCANFD_FDBTR_SJW 0x0000000f #define GRCANFD_FDBTR_SCALER_BIT 16 -#define GRCANFD_FDBTR_PS1_BIT 10 -#define GRCANFD_FDBTR_PS2_BIT 5 -#define GRCANFD_FDBTR_SJW_BIT 0 +#define GRCANFD_FDBTR_PS1_BIT 10 +#define GRCANFD_FDBTR_PS2_BIT 5 +#define GRCANFD_FDBTR_SJW_BIT 0 /* Relative offset of IRQ sources to AMBA Plug&Play */ -#define GRCAN_IRQ_IRQ 0 +#define GRCAN_IRQ_IRQ 0 #define GRCAN_IRQ_TXSYNC 1 #define GRCAN_IRQ_RXSYNC 2 -#define GRCAN_ERR_IRQ 0x1 -#define GRCAN_OFF_IRQ 0x2 -#define GRCAN_OR_IRQ 0x4 -#define GRCAN_RXAHBERR_IRQ 0x8 -#define GRCAN_TXAHBERR_IRQ 0x10 -#define GRCAN_RXIRQ_IRQ 0x20 -#define GRCAN_TXIRQ_IRQ 0x40 -#define GRCAN_RXFULL_IRQ 0x80 -#define GRCAN_TXEMPTY_IRQ 0x100 -#define GRCAN_RX_IRQ 0x200 -#define GRCAN_TX_IRQ 0x400 -#define GRCAN_RXSYNC_IRQ 0x800 -#define GRCAN_TXSYNC_IRQ 0x1000 -#define GRCAN_RXERR_IRQ 0x2000 -#define GRCAN_TXERR_IRQ 0x4000 -#define GRCAN_RXMISS_IRQ 0x8000 -#define GRCAN_TXLOSS_IRQ 0x10000 +#define GRCAN_ERR_IRQ 0x1 +#define GRCAN_OFF_IRQ 0x2 +#define GRCAN_OR_IRQ 0x4 +#define GRCAN_RXAHBERR_IRQ 0x8 +#define GRCAN_TXAHBERR_IRQ 0x10 +#define GRCAN_RXIRQ_IRQ 0x20 +#define GRCAN_TXIRQ_IRQ 0x40 +#define GRCAN_RXFULL_IRQ 0x80 +#define GRCAN_TXEMPTY_IRQ 0x100 +#define GRCAN_RX_IRQ 0x200 +#define GRCAN_TX_IRQ 0x400 +#define GRCAN_RXSYNC_IRQ 0x800 +#define GRCAN_TXSYNC_IRQ 0x1000 +#define GRCAN_RXERR_IRQ 0x2000 +#define GRCAN_TXERR_IRQ 0x4000 +#define GRCAN_RXMISS_IRQ 0x8000 +#define GRCAN_TXLOSS_IRQ 0x10000 -#define GRCAN_STAT_PASS 0x1 -#define GRCAN_STAT_OFF 0x2 -#define GRCAN_STAT_OR 0x4 -#define GRCAN_STAT_AHBERR 0x8 -#define GRCAN_STAT_ACTIVE 0x10 -#define GRCAN_STAT_RXERRCNT 0xff00 -#define GRCAN_STAT_TXERRCNT 0xff0000 +#define GRCAN_STAT_PASS 0x1 +#define GRCAN_STAT_OFF 0x2 +#define GRCAN_STAT_OR 0x4 +#define GRCAN_STAT_AHBERR 0x8 +#define GRCAN_STAT_ACTIVE 0x10 +#define GRCAN_STAT_RXERRCNT 0xff00 +#define GRCAN_STAT_TXERRCNT 0xff0000 /* * Return number of GRCAN devices available to driver */ -extern int grcan_dev_count(void); +extern int grcan_dev_count( void ); /* * Open a GRCAN device @@ -283,7 +284,7 @@ extern int grcan_dev_count(void); * return: Device handle to use with all other grcan_ API functions. The * function returns NULL if device can not be opened. */ -extern void *grcan_open(int dev_no); +extern void *grcan_open( int dev_no ); /* * Open a GRCAN device by name. Finds device index then calls @@ -294,14 +295,14 @@ extern void *grcan_open(int dev_no); * return: Device handle to use with all other grcan_ API functions. The * function returns NULL if device can not be opened or not found. */ -extern void *grcan_open_by_name(char *name, int *dev_no); +extern void *grcan_open_by_name( char *name, int *dev_no ); /* * Close a GRCAN device * * return: This function always returns 0 (success) */ -extern int grcan_close(void *d); +extern int grcan_close( void *d ); /* * Returns if CAN hardware device is CANFD capable. @@ -310,7 +311,7 @@ extern int grcan_close(void *d); * return: 0=Not FD capable, 1=FD capable. * function returns NULL if device can not be opened. */ -extern int grcan_canfd_capable(void *d); +extern int grcan_canfd_capable( void *d ); /* * Receive CAN messages @@ -331,11 +332,7 @@ extern int grcan_canfd_capable(void *d); * Device has left started mode. * GRCAN_RET_AHBERR: Similar to BUSOFF, but was caused by AHB Error. */ -extern int grcan_read( - void *d, - CANMsg *msg, - size_t count -); +extern int grcan_read( void *d, CANMsg *msg, size_t count ); /* * Receive CAN messages (only GRCANFD) @@ -356,11 +353,7 @@ extern int grcan_read( * Device has left started mode. * GRCAN_RET_AHBERR: Similar to BUSOFF, but was caused by AHB Error. */ -extern int grcanfd_read( - void *d, - CANFDMsg *msg, - size_t count -); +extern int grcanfd_read( void *d, CANFDMsg *msg, size_t count ); /* * Transmit CAN messages @@ -381,11 +374,7 @@ extern int grcanfd_read( * Device has left started mode * GRCAN_RET_AHBERR: Similar to BUSOFF, but was caused by AHB Error. */ -extern int grcan_write( - void *d, - CANMsg *msg, - size_t count -); +extern int grcan_write( void *d, CANMsg *msg, size_t count ); /* * Transmit CAN-FD complient messages (only GRCANFD) @@ -406,11 +395,7 @@ extern int grcan_write( * Device has left started mode * GRCAN_RET_AHBERR: Similar to BUSOFF, but was caused by AHB Error. */ -extern int grcanfd_write( - void *d, - CANFDMsg *msg, - size_t ucount -); +extern int grcanfd_write( void *d, CANFDMsg *msg, size_t ucount ); /* * Returns current GRCAN software state @@ -425,7 +410,7 @@ extern int grcanfd_write( * STATE_BUSOFF Bus-off has been detected * STATE_AHBERR AHB error has been detected */ -extern int grcan_get_state(void *d); +extern int grcan_get_state( void *d ); /* The remaining functions return 0 on success and non-zero on failure. */ @@ -433,57 +418,61 @@ extern int grcan_get_state(void *d); * mode */ /* Bring the link up after open or bus-off */ -extern int grcan_start(void *d); +extern int grcan_start( void *d ); /* stop to change baud rate/config or closing down */ -extern int grcan_stop(void *d); +extern int grcan_stop( void *d ); /* Wait until all TX messages have been sent */ -extern int grcan_flush(void *d); +extern int grcan_flush( void *d ); /* Functions that require connection * to be stopped */ /* enable silent mode read only state */ -extern int grcan_set_silent(void *d, int silent); +extern int grcan_set_silent( void *d, int silent ); /* enable/disable stopping link on AHB Error */ -extern int grcan_set_abort(void *d, int abort); +extern int grcan_set_abort( void *d, int abort ); /* Set Enable0,Enable1,Selection */ -extern int grcan_set_selection(void *d, const struct grcan_selection *selection); +extern int grcan_set_selection( + void *d, + const struct grcan_selection *selection +); /* Set baudrate by using driver's baud rate timing calculation routines */ -extern int grcan_set_speed(void *d, unsigned int hz); +extern int grcan_set_speed( void *d, unsigned int hz ); /* Set baudrate by specifying the timing registers manually */ -extern int grcan_set_btrs(void *d, const struct grcan_timing *timing); +extern int grcan_set_btrs( void *d, const struct grcan_timing *timing ); /* Set the Nominal and FD baudrate by using driver's baud rate timing * calculation routines */ -extern int grcanfd_set_speed(void *d, unsigned int nomhz, unsigned int fdhz); +extern int grcanfd_set_speed( void *d, unsigned int nomhz, unsigned int fdhz ); /* Set Nominal and FD baudrate by specifying the timing registers manually*/ extern int grcanfd_set_btrs( - void *d, - const struct grcanfd_timing *nominal, - const struct grcanfd_timing *fd); + void *d, + const struct grcanfd_timing *nominal, + const struct grcanfd_timing *fd +); /* Functions can be called whenever */ /* Enable/disable Blocking on reception (until at least one message has been received) */ -int grcan_set_rxblock(void* d, int block); +int grcan_set_rxblock( void *d, int block ); /* Enable/disable Blocking on transmission (until at least one message has been transmitted) */ -int grcan_set_txblock(void* d, int block); +int grcan_set_txblock( void *d, int block ); /* Enable/disable Blocking until all requested messages has been sent */ -int grcan_set_txcomplete(void* d, int complete); +int grcan_set_txcomplete( void *d, int complete ); /* Enable/disable Blocking until all requested has been received */ -int grcan_set_rxcomplete(void* d, int complete); +int grcan_set_rxcomplete( void *d, int complete ); /* Get statistics */ -extern int grcan_get_stats(void *d, struct grcan_stats *stats); +extern int grcan_get_stats( void *d, struct grcan_stats *stats ); /* Clear statistics */ -extern int grcan_clr_stats(void *d); +extern int grcan_clr_stats( void *d ); /* Set Acceptance filters, provide pointer to "struct grcan_filter" or NULL to disable filtering (let all messages pass) */ -extern int grcan_set_afilter(void *d, const struct grcan_filter *filter); +extern int grcan_set_afilter( void *d, const struct grcan_filter *filter ); /* Set Sync Messages RX/TX filters, NULL disables the IRQ completely */ -extern int grcan_set_sfilter(void *d, const struct grcan_filter *filter); +extern int grcan_set_sfilter( void *d, const struct grcan_filter *filter ); /* Get status register of GRCAN core */ -extern int grcan_get_status(void *d, unsigned int *status); +extern int grcan_get_status( void *d, unsigned int *status ); -void grcan_register_drv(void); +void grcan_register_drv( void ); #ifdef __cplusplus } diff --git a/bsps/include/grlib/grclkgate-regs.h b/bsps/include/grlib/grclkgate-regs.h index 22dae51207..74b0621c99 100644 --- a/bsps/include/grlib/grclkgate-regs.h +++ b/bsps/include/grlib/grclkgate-regs.h @@ -82,15 +82,15 @@ extern "C" { */ #define GRCLKGATE_UNLOCK_UNLOCK_SHIFT 0 -#define GRCLKGATE_UNLOCK_UNLOCK_MASK 0xffffffffU -#define GRCLKGATE_UNLOCK_UNLOCK_GET( _reg ) \ +#define GRCLKGATE_UNLOCK_UNLOCK_MASK 0xffffffffU +#define GRCLKGATE_UNLOCK_UNLOCK_GET( _reg ) \ ( ( ( _reg ) & GRCLKGATE_UNLOCK_UNLOCK_MASK ) >> \ GRCLKGATE_UNLOCK_UNLOCK_SHIFT ) -#define GRCLKGATE_UNLOCK_UNLOCK_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRCLKGATE_UNLOCK_UNLOCK_MASK ) | \ +#define GRCLKGATE_UNLOCK_UNLOCK_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRCLKGATE_UNLOCK_UNLOCK_MASK ) | \ ( ( ( _val ) << GRCLKGATE_UNLOCK_UNLOCK_SHIFT ) & \ GRCLKGATE_UNLOCK_UNLOCK_MASK ) ) -#define GRCLKGATE_UNLOCK_UNLOCK( _val ) \ +#define GRCLKGATE_UNLOCK_UNLOCK( _val ) \ ( ( ( _val ) << GRCLKGATE_UNLOCK_UNLOCK_SHIFT ) & \ GRCLKGATE_UNLOCK_UNLOCK_MASK ) @@ -105,15 +105,15 @@ extern "C" { */ #define GRCLKGATE_CLKEN_ENABLE_SHIFT 0 -#define GRCLKGATE_CLKEN_ENABLE_MASK 0xffffffffU -#define GRCLKGATE_CLKEN_ENABLE_GET( _reg ) \ +#define GRCLKGATE_CLKEN_ENABLE_MASK 0xffffffffU +#define GRCLKGATE_CLKEN_ENABLE_GET( _reg ) \ ( ( ( _reg ) & GRCLKGATE_CLKEN_ENABLE_MASK ) >> \ GRCLKGATE_CLKEN_ENABLE_SHIFT ) -#define GRCLKGATE_CLKEN_ENABLE_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRCLKGATE_CLKEN_ENABLE_MASK ) | \ +#define GRCLKGATE_CLKEN_ENABLE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRCLKGATE_CLKEN_ENABLE_MASK ) | \ ( ( ( _val ) << GRCLKGATE_CLKEN_ENABLE_SHIFT ) & \ GRCLKGATE_CLKEN_ENABLE_MASK ) ) -#define GRCLKGATE_CLKEN_ENABLE( _val ) \ +#define GRCLKGATE_CLKEN_ENABLE( _val ) \ ( ( ( _val ) << GRCLKGATE_CLKEN_ENABLE_SHIFT ) & \ GRCLKGATE_CLKEN_ENABLE_MASK ) @@ -128,17 +128,15 @@ extern "C" { */ #define GRCLKGATE_RESET_RESET_SHIFT 0 -#define GRCLKGATE_RESET_RESET_MASK 0xffffffffU +#define GRCLKGATE_RESET_RESET_MASK 0xffffffffU #define GRCLKGATE_RESET_RESET_GET( _reg ) \ - ( ( ( _reg ) & GRCLKGATE_RESET_RESET_MASK ) >> \ - GRCLKGATE_RESET_RESET_SHIFT ) -#define GRCLKGATE_RESET_RESET_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRCLKGATE_RESET_RESET_MASK ) | \ + ( ( ( _reg ) & GRCLKGATE_RESET_RESET_MASK ) >> GRCLKGATE_RESET_RESET_SHIFT ) +#define GRCLKGATE_RESET_RESET_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRCLKGATE_RESET_RESET_MASK ) | \ ( ( ( _val ) << GRCLKGATE_RESET_RESET_SHIFT ) & \ GRCLKGATE_RESET_RESET_MASK ) ) #define GRCLKGATE_RESET_RESET( _val ) \ - ( ( ( _val ) << GRCLKGATE_RESET_RESET_SHIFT ) & \ - GRCLKGATE_RESET_RESET_MASK ) + ( ( ( _val ) << GRCLKGATE_RESET_RESET_SHIFT ) & GRCLKGATE_RESET_RESET_MASK ) /** @} */ @@ -151,28 +149,28 @@ extern "C" { */ #define GRCLKGATE_OVERRIDE_FOVERRIDE_SHIFT 16 -#define GRCLKGATE_OVERRIDE_FOVERRIDE_MASK 0xf0000U -#define GRCLKGATE_OVERRIDE_FOVERRIDE_GET( _reg ) \ +#define GRCLKGATE_OVERRIDE_FOVERRIDE_MASK 0xf0000U +#define GRCLKGATE_OVERRIDE_FOVERRIDE_GET( _reg ) \ ( ( ( _reg ) & GRCLKGATE_OVERRIDE_FOVERRIDE_MASK ) >> \ GRCLKGATE_OVERRIDE_FOVERRIDE_SHIFT ) -#define GRCLKGATE_OVERRIDE_FOVERRIDE_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRCLKGATE_OVERRIDE_FOVERRIDE_MASK ) | \ +#define GRCLKGATE_OVERRIDE_FOVERRIDE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRCLKGATE_OVERRIDE_FOVERRIDE_MASK ) | \ ( ( ( _val ) << GRCLKGATE_OVERRIDE_FOVERRIDE_SHIFT ) & \ GRCLKGATE_OVERRIDE_FOVERRIDE_MASK ) ) -#define GRCLKGATE_OVERRIDE_FOVERRIDE( _val ) \ +#define GRCLKGATE_OVERRIDE_FOVERRIDE( _val ) \ ( ( ( _val ) << GRCLKGATE_OVERRIDE_FOVERRIDE_SHIFT ) & \ GRCLKGATE_OVERRIDE_FOVERRIDE_MASK ) #define GRCLKGATE_OVERRIDE_OVERRIDE_SHIFT 0 -#define GRCLKGATE_OVERRIDE_OVERRIDE_MASK 0xfU -#define GRCLKGATE_OVERRIDE_OVERRIDE_GET( _reg ) \ +#define GRCLKGATE_OVERRIDE_OVERRIDE_MASK 0xfU +#define GRCLKGATE_OVERRIDE_OVERRIDE_GET( _reg ) \ ( ( ( _reg ) & GRCLKGATE_OVERRIDE_OVERRIDE_MASK ) >> \ GRCLKGATE_OVERRIDE_OVERRIDE_SHIFT ) -#define GRCLKGATE_OVERRIDE_OVERRIDE_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRCLKGATE_OVERRIDE_OVERRIDE_MASK ) | \ +#define GRCLKGATE_OVERRIDE_OVERRIDE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRCLKGATE_OVERRIDE_OVERRIDE_MASK ) | \ ( ( ( _val ) << GRCLKGATE_OVERRIDE_OVERRIDE_SHIFT ) & \ GRCLKGATE_OVERRIDE_OVERRIDE_MASK ) ) -#define GRCLKGATE_OVERRIDE_OVERRIDE( _val ) \ +#define GRCLKGATE_OVERRIDE_OVERRIDE( _val ) \ ( ( ( _val ) << GRCLKGATE_OVERRIDE_OVERRIDE_SHIFT ) & \ GRCLKGATE_OVERRIDE_OVERRIDE_MASK ) diff --git a/bsps/include/grlib/grctm.h b/bsps/include/grlib/grctm.h index 816a337188..73ea4bb2de 100644 --- a/bsps/include/grlib/grctm.h +++ b/bsps/include/grlib/grctm.h @@ -30,161 +30,167 @@ #ifndef __GRCTM_H__ #define __GRCTM_H__ -#define DAT0_IRQ 0x1 -#define DAT1_IRQ 0x2 -#define DAT2_IRQ 0x4 -#define PULSE0_IRQ 0x10 -#define PULSE1_IRQ 0x20 -#define PULSE2_IRQ 0x40 -#define PULSE3_IRQ 0x80 -#define PULSE4_IRQ 0x100 -#define PULSE5_IRQ 0x200 -#define PULSE6_IRQ 0x400 -#define PULSE7_IRQ 0x800 +#define DAT0_IRQ 0x1 +#define DAT1_IRQ 0x2 +#define DAT2_IRQ 0x4 +#define PULSE0_IRQ 0x10 +#define PULSE1_IRQ 0x20 +#define PULSE2_IRQ 0x40 +#define PULSE3_IRQ 0x80 +#define PULSE4_IRQ 0x100 +#define PULSE5_IRQ 0x200 +#define PULSE6_IRQ 0x400 +#define PULSE7_IRQ 0x800 struct grctm_regs { - volatile uint32_t grr; - volatile uint32_t gcr; - volatile uint32_t gsr; - volatile uint32_t unused[2]; - volatile uint32_t pfr; - volatile uint32_t etcr; - volatile uint32_t etfr; - volatile uint32_t dcr0; - volatile uint32_t dfr0; - volatile uint32_t dcr1; - volatile uint32_t dfr1; - volatile uint32_t dcr2; - volatile uint32_t dfr2; - volatile uint32_t stcr; - volatile uint32_t stfr; - volatile uint32_t pdr[8]; - volatile uint32_t pimsr; - volatile uint32_t pimr; - volatile uint32_t pisr; - volatile uint32_t pir; - volatile uint32_t imr; - volatile uint32_t picr; - volatile uint32_t unused1[2]; - volatile uint32_t etir; - volatile uint32_t fsir; - volatile uint32_t serconf; - volatile uint32_t unused2; - volatile uint32_t twsc; - volatile uint32_t twadj; - volatile uint32_t twtx; - volatile uint32_t twrx; + volatile uint32_t grr; + volatile uint32_t gcr; + volatile uint32_t gsr; + volatile uint32_t unused[ 2 ]; + volatile uint32_t pfr; + volatile uint32_t etcr; + volatile uint32_t etfr; + volatile uint32_t dcr0; + volatile uint32_t dfr0; + volatile uint32_t dcr1; + volatile uint32_t dfr1; + volatile uint32_t dcr2; + volatile uint32_t dfr2; + volatile uint32_t stcr; + volatile uint32_t stfr; + volatile uint32_t pdr[ 8 ]; + volatile uint32_t pimsr; + volatile uint32_t pimr; + volatile uint32_t pisr; + volatile uint32_t pir; + volatile uint32_t imr; + volatile uint32_t picr; + volatile uint32_t unused1[ 2 ]; + volatile uint32_t etir; + volatile uint32_t fsir; + volatile uint32_t serconf; + volatile uint32_t unused2; + volatile uint32_t twsc; + volatile uint32_t twadj; + volatile uint32_t twtx; + volatile uint32_t twrx; }; struct grctm_stats { - - /* IRQ Stats */ - unsigned int nirqs; - unsigned int pulse; + /* IRQ Stats */ + unsigned int nirqs; + unsigned int pulse; }; /* Function ISR callback prototype */ -typedef void (*grctm_isr_t)(unsigned int pimr, void *data); +typedef void ( *grctm_isr_t )( unsigned int pimr, void *data ); /* Open a GRCTM device by minor number. */ -extern void *grctm_open(int minor); +extern void *grctm_open( int minor ); /* Close a previously opened GRCTM device */ -extern void grctm_close(void *spwcuc); +extern void grctm_close( void *spwcuc ); /* Hardware Reset of GRCTM */ -extern int grctm_reset(void *grctm); +extern int grctm_reset( void *grctm ); /* Enable Interrupts at Interrupt controller */ -extern void grctm_int_enable(void *grctm); +extern void grctm_int_enable( void *grctm ); /* Disable Interrupts at Interrupt controller */ -extern void grctm_int_disable(void *grctm); +extern void grctm_int_disable( void *grctm ); /* Clear Statistics gathered by the driver */ -extern void grctm_clr_stats(void *grctm); +extern void grctm_clr_stats( void *grctm ); /* Get Statistics gathered by the driver */ -extern void grctm_get_stats(void *grctm, struct grctm_stats *stats); +extern void grctm_get_stats( void *grctm, struct grctm_stats *stats ); /* Register an Interrupt handler and custom data, the function call is * removed by setting func to NULL. */ -extern void grctm_int_register(void *grctm, grctm_isr_t func, void *data); +extern void grctm_int_register( void *grctm, grctm_isr_t func, void *data ); /* Enable external synchronisation (from spwcuc) */ -extern void grctm_enable_ext_sync(void *grctm); +extern void grctm_enable_ext_sync( void *grctm ); /* Disable external synchronisation (from spwcuc) */ -extern void grctm_disable_ext_sync(void *grctm); +extern void grctm_disable_ext_sync( void *grctm ); /* Enable TimeWire synchronisation */ -extern void grctm_enable_tw_sync(void *grctm); +extern void grctm_enable_tw_sync( void *grctm ); /* Disable TimeWire synchronisation */ -extern void grctm_disable_tw_sync(void *grctm); +extern void grctm_disable_tw_sync( void *grctm ); /* Disable frequency synthesizer from driving ET */ -extern void grctm_disable_fs(void *grctm); +extern void grctm_disable_fs( void *grctm ); /* Enable frequency synthesizer to drive ET */ -extern void grctm_enable_fs(void *grctm); +extern void grctm_enable_fs( void *grctm ); /* Return elapsed coarse time */ -extern unsigned int grctm_get_et_coarse(void *grctm); +extern unsigned int grctm_get_et_coarse( void *grctm ); /* Return elapsed fine time */ -extern unsigned int grctm_get_et_fine(void *grctm); +extern unsigned int grctm_get_et_fine( void *grctm ); /* Return elapsed time (coarse and fine) */ -extern unsigned long long grctm_get_et(void *grctm); +extern unsigned long long grctm_get_et( void *grctm ); /* Return 1 if specified datation has been latched */ -extern int grctm_is_dat_latched(void *grctm, int dat); +extern int grctm_is_dat_latched( void *grctm, int dat ); /* Set triggering edge of datation input */ -extern void grctm_set_dat_edge(void *grctm, int dat, int edge); +extern void grctm_set_dat_edge( void *grctm, int dat, int edge ); /* Return latched datation coarse time */ -extern unsigned int grctm_get_dat_coarse(void *grctm, int dat); +extern unsigned int grctm_get_dat_coarse( void *grctm, int dat ); /* Return latched datation fine time */ -extern unsigned int grctm_get_dat_fine(void *grctm, int dat); +extern unsigned int grctm_get_dat_fine( void *grctm, int dat ); /* Return latched datation ET */ -extern unsigned long long grctm_get_dat_et(void *grctm, int dat); +extern unsigned long long grctm_get_dat_et( void *grctm, int dat ); /* Return current pulse configuration */ -extern unsigned int grctm_get_pulse_reg(void *grctm, int pulse); +extern unsigned int grctm_get_pulse_reg( void *grctm, int pulse ); /* Set pulse register */ -extern void grctm_set_pulse_reg(void *grctm, int pulse, unsigned int val); +extern void grctm_set_pulse_reg( void *grctm, int pulse, unsigned int val ); /* Configure pulse: pp = period, pw = width, pl = level, en = enable */ -extern void grctm_cfg_pulse(void *grctm, int pulse, int pp, int pw, int pl, int en); +extern void grctm_cfg_pulse( + void *grctm, + int pulse, + int pp, + int pw, + int pl, + int en +); /* Enable pulse output */ -extern void grctm_enable_pulse(void *grctm, int pulse); +extern void grctm_enable_pulse( void *grctm, int pulse ); /* Disable pulse output */ -extern void grctm_disable_pulse(void *grctm, int pulse); +extern void grctm_disable_pulse( void *grctm, int pulse ); /* Clear interrupts */ -extern void grctm_clear_irqs(void *grctm, int irqs); +extern void grctm_clear_irqs( void *grctm, int irqs ); /* Enable interrupts */ -extern void grctm_enable_irqs(void *grctm, int irqs); +extern void grctm_enable_irqs( void *grctm, int irqs ); /* Set Frequency synthesizer increment */ -void grctm_set_fs_incr(void *grctm, int incr); +void grctm_set_fs_incr( void *grctm, int incr ); /* Set ET increment */ -void grctm_set_et_incr(void *grctm, int incr); +void grctm_set_et_incr( void *grctm, int incr ); /* Get register base address */ -struct grctm_regs *grctm_get_regs(void *grctm); +struct grctm_regs *grctm_get_regs( void *grctm ); /* Register the GRCTM driver to Driver Manager */ -extern void grctm_register(void); +extern void grctm_register( void ); #endif diff --git a/bsps/include/grlib/grethgbit-regs.h b/bsps/include/grlib/grethgbit-regs.h index 8d8f4ce8bf..71d936a372 100644 --- a/bsps/include/grlib/grethgbit-regs.h +++ b/bsps/include/grlib/grethgbit-regs.h @@ -84,17 +84,14 @@ extern "C" { #define GRETHGBIT_CR_EA 0x80000000U #define GRETHGBIT_CR_BS_SHIFT 28 -#define GRETHGBIT_CR_BS_MASK 0x70000000U +#define GRETHGBIT_CR_BS_MASK 0x70000000U #define GRETHGBIT_CR_BS_GET( _reg ) \ - ( ( ( _reg ) & GRETHGBIT_CR_BS_MASK ) >> \ - GRETHGBIT_CR_BS_SHIFT ) -#define GRETHGBIT_CR_BS_SET( _reg, _val ) \ + ( ( ( _reg ) & GRETHGBIT_CR_BS_MASK ) >> GRETHGBIT_CR_BS_SHIFT ) +#define GRETHGBIT_CR_BS_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRETHGBIT_CR_BS_MASK ) | \ - ( ( ( _val ) << GRETHGBIT_CR_BS_SHIFT ) & \ - GRETHGBIT_CR_BS_MASK ) ) + ( ( ( _val ) << GRETHGBIT_CR_BS_SHIFT ) & GRETHGBIT_CR_BS_MASK ) ) #define GRETHGBIT_CR_BS( _val ) \ - ( ( ( _val ) << GRETHGBIT_CR_BS_SHIFT ) & \ - GRETHGBIT_CR_BS_MASK ) + ( ( ( _val ) << GRETHGBIT_CR_BS_SHIFT ) & GRETHGBIT_CR_BS_MASK ) #define GRETHGBIT_CR_GA 0x8000000U @@ -171,17 +168,15 @@ extern "C" { */ #define GRETHGBIT_MACMSB_MSB_SHIFT 0 -#define GRETHGBIT_MACMSB_MSB_MASK 0xffffU +#define GRETHGBIT_MACMSB_MSB_MASK 0xffffU #define GRETHGBIT_MACMSB_MSB_GET( _reg ) \ - ( ( ( _reg ) & GRETHGBIT_MACMSB_MSB_MASK ) >> \ - GRETHGBIT_MACMSB_MSB_SHIFT ) -#define GRETHGBIT_MACMSB_MSB_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRETHGBIT_MACMSB_MSB_MASK ) | \ + ( ( ( _reg ) & GRETHGBIT_MACMSB_MSB_MASK ) >> GRETHGBIT_MACMSB_MSB_SHIFT ) +#define GRETHGBIT_MACMSB_MSB_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRETHGBIT_MACMSB_MSB_MASK ) | \ ( ( ( _val ) << GRETHGBIT_MACMSB_MSB_SHIFT ) & \ GRETHGBIT_MACMSB_MSB_MASK ) ) #define GRETHGBIT_MACMSB_MSB( _val ) \ - ( ( ( _val ) << GRETHGBIT_MACMSB_MSB_SHIFT ) & \ - GRETHGBIT_MACMSB_MSB_MASK ) + ( ( ( _val ) << GRETHGBIT_MACMSB_MSB_SHIFT ) & GRETHGBIT_MACMSB_MSB_MASK ) /** @} */ @@ -194,17 +189,15 @@ extern "C" { */ #define GRETHGBIT_MACLSB_LSB_SHIFT 0 -#define GRETHGBIT_MACLSB_LSB_MASK 0xffffffffU +#define GRETHGBIT_MACLSB_LSB_MASK 0xffffffffU #define GRETHGBIT_MACLSB_LSB_GET( _reg ) \ - ( ( ( _reg ) & GRETHGBIT_MACLSB_LSB_MASK ) >> \ - GRETHGBIT_MACLSB_LSB_SHIFT ) -#define GRETHGBIT_MACLSB_LSB_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRETHGBIT_MACLSB_LSB_MASK ) | \ + ( ( ( _reg ) & GRETHGBIT_MACLSB_LSB_MASK ) >> GRETHGBIT_MACLSB_LSB_SHIFT ) +#define GRETHGBIT_MACLSB_LSB_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRETHGBIT_MACLSB_LSB_MASK ) | \ ( ( ( _val ) << GRETHGBIT_MACLSB_LSB_SHIFT ) & \ GRETHGBIT_MACLSB_LSB_MASK ) ) #define GRETHGBIT_MACLSB_LSB( _val ) \ - ( ( ( _val ) << GRETHGBIT_MACLSB_LSB_SHIFT ) & \ - GRETHGBIT_MACLSB_LSB_MASK ) + ( ( ( _val ) << GRETHGBIT_MACLSB_LSB_SHIFT ) & GRETHGBIT_MACLSB_LSB_MASK ) /** @} */ @@ -217,41 +210,39 @@ extern "C" { */ #define GRETHGBIT_MDIO_DATA_SHIFT 16 -#define GRETHGBIT_MDIO_DATA_MASK 0xffff0000U +#define GRETHGBIT_MDIO_DATA_MASK 0xffff0000U #define GRETHGBIT_MDIO_DATA_GET( _reg ) \ - ( ( ( _reg ) & GRETHGBIT_MDIO_DATA_MASK ) >> \ - GRETHGBIT_MDIO_DATA_SHIFT ) -#define GRETHGBIT_MDIO_DATA_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRETHGBIT_MDIO_DATA_MASK ) | \ + ( ( ( _reg ) & GRETHGBIT_MDIO_DATA_MASK ) >> GRETHGBIT_MDIO_DATA_SHIFT ) +#define GRETHGBIT_MDIO_DATA_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRETHGBIT_MDIO_DATA_MASK ) | \ ( ( ( _val ) << GRETHGBIT_MDIO_DATA_SHIFT ) & \ GRETHGBIT_MDIO_DATA_MASK ) ) #define GRETHGBIT_MDIO_DATA( _val ) \ - ( ( ( _val ) << GRETHGBIT_MDIO_DATA_SHIFT ) & \ - GRETHGBIT_MDIO_DATA_MASK ) + ( ( ( _val ) << GRETHGBIT_MDIO_DATA_SHIFT ) & GRETHGBIT_MDIO_DATA_MASK ) #define GRETHGBIT_MDIO_PHYADDR_SHIFT 11 -#define GRETHGBIT_MDIO_PHYADDR_MASK 0xf800U -#define GRETHGBIT_MDIO_PHYADDR_GET( _reg ) \ +#define GRETHGBIT_MDIO_PHYADDR_MASK 0xf800U +#define GRETHGBIT_MDIO_PHYADDR_GET( _reg ) \ ( ( ( _reg ) & GRETHGBIT_MDIO_PHYADDR_MASK ) >> \ GRETHGBIT_MDIO_PHYADDR_SHIFT ) -#define GRETHGBIT_MDIO_PHYADDR_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRETHGBIT_MDIO_PHYADDR_MASK ) | \ +#define GRETHGBIT_MDIO_PHYADDR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRETHGBIT_MDIO_PHYADDR_MASK ) | \ ( ( ( _val ) << GRETHGBIT_MDIO_PHYADDR_SHIFT ) & \ GRETHGBIT_MDIO_PHYADDR_MASK ) ) -#define GRETHGBIT_MDIO_PHYADDR( _val ) \ +#define GRETHGBIT_MDIO_PHYADDR( _val ) \ ( ( ( _val ) << GRETHGBIT_MDIO_PHYADDR_SHIFT ) & \ GRETHGBIT_MDIO_PHYADDR_MASK ) #define GRETHGBIT_MDIO_REGADDR_SHIFT 6 -#define GRETHGBIT_MDIO_REGADDR_MASK 0x7c0U -#define GRETHGBIT_MDIO_REGADDR_GET( _reg ) \ +#define GRETHGBIT_MDIO_REGADDR_MASK 0x7c0U +#define GRETHGBIT_MDIO_REGADDR_GET( _reg ) \ ( ( ( _reg ) & GRETHGBIT_MDIO_REGADDR_MASK ) >> \ GRETHGBIT_MDIO_REGADDR_SHIFT ) -#define GRETHGBIT_MDIO_REGADDR_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRETHGBIT_MDIO_REGADDR_MASK ) | \ +#define GRETHGBIT_MDIO_REGADDR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRETHGBIT_MDIO_REGADDR_MASK ) | \ ( ( ( _val ) << GRETHGBIT_MDIO_REGADDR_SHIFT ) & \ GRETHGBIT_MDIO_REGADDR_MASK ) ) -#define GRETHGBIT_MDIO_REGADDR( _val ) \ +#define GRETHGBIT_MDIO_REGADDR( _val ) \ ( ( ( _val ) << GRETHGBIT_MDIO_REGADDR_SHIFT ) & \ GRETHGBIT_MDIO_REGADDR_MASK ) @@ -275,28 +266,28 @@ extern "C" { */ #define GRETHGBIT_TDTBA_BASEADDR_SHIFT 10 -#define GRETHGBIT_TDTBA_BASEADDR_MASK 0xfffffc00U -#define GRETHGBIT_TDTBA_BASEADDR_GET( _reg ) \ +#define GRETHGBIT_TDTBA_BASEADDR_MASK 0xfffffc00U +#define GRETHGBIT_TDTBA_BASEADDR_GET( _reg ) \ ( ( ( _reg ) & GRETHGBIT_TDTBA_BASEADDR_MASK ) >> \ GRETHGBIT_TDTBA_BASEADDR_SHIFT ) -#define GRETHGBIT_TDTBA_BASEADDR_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRETHGBIT_TDTBA_BASEADDR_MASK ) | \ +#define GRETHGBIT_TDTBA_BASEADDR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRETHGBIT_TDTBA_BASEADDR_MASK ) | \ ( ( ( _val ) << GRETHGBIT_TDTBA_BASEADDR_SHIFT ) & \ GRETHGBIT_TDTBA_BASEADDR_MASK ) ) -#define GRETHGBIT_TDTBA_BASEADDR( _val ) \ +#define GRETHGBIT_TDTBA_BASEADDR( _val ) \ ( ( ( _val ) << GRETHGBIT_TDTBA_BASEADDR_SHIFT ) & \ GRETHGBIT_TDTBA_BASEADDR_MASK ) #define GRETHGBIT_TDTBA_DESCPNT_SHIFT 3 -#define GRETHGBIT_TDTBA_DESCPNT_MASK 0x3f8U -#define GRETHGBIT_TDTBA_DESCPNT_GET( _reg ) \ +#define GRETHGBIT_TDTBA_DESCPNT_MASK 0x3f8U +#define GRETHGBIT_TDTBA_DESCPNT_GET( _reg ) \ ( ( ( _reg ) & GRETHGBIT_TDTBA_DESCPNT_MASK ) >> \ GRETHGBIT_TDTBA_DESCPNT_SHIFT ) -#define GRETHGBIT_TDTBA_DESCPNT_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRETHGBIT_TDTBA_DESCPNT_MASK ) | \ +#define GRETHGBIT_TDTBA_DESCPNT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRETHGBIT_TDTBA_DESCPNT_MASK ) | \ ( ( ( _val ) << GRETHGBIT_TDTBA_DESCPNT_SHIFT ) & \ GRETHGBIT_TDTBA_DESCPNT_MASK ) ) -#define GRETHGBIT_TDTBA_DESCPNT( _val ) \ +#define GRETHGBIT_TDTBA_DESCPNT( _val ) \ ( ( ( _val ) << GRETHGBIT_TDTBA_DESCPNT_SHIFT ) & \ GRETHGBIT_TDTBA_DESCPNT_MASK ) @@ -312,28 +303,28 @@ extern "C" { */ #define GRETHGBIT_RDTBA_BASEADDR_SHIFT 10 -#define GRETHGBIT_RDTBA_BASEADDR_MASK 0xfffffc00U -#define GRETHGBIT_RDTBA_BASEADDR_GET( _reg ) \ +#define GRETHGBIT_RDTBA_BASEADDR_MASK 0xfffffc00U +#define GRETHGBIT_RDTBA_BASEADDR_GET( _reg ) \ ( ( ( _reg ) & GRETHGBIT_RDTBA_BASEADDR_MASK ) >> \ GRETHGBIT_RDTBA_BASEADDR_SHIFT ) -#define GRETHGBIT_RDTBA_BASEADDR_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRETHGBIT_RDTBA_BASEADDR_MASK ) | \ +#define GRETHGBIT_RDTBA_BASEADDR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRETHGBIT_RDTBA_BASEADDR_MASK ) | \ ( ( ( _val ) << GRETHGBIT_RDTBA_BASEADDR_SHIFT ) & \ GRETHGBIT_RDTBA_BASEADDR_MASK ) ) -#define GRETHGBIT_RDTBA_BASEADDR( _val ) \ +#define GRETHGBIT_RDTBA_BASEADDR( _val ) \ ( ( ( _val ) << GRETHGBIT_RDTBA_BASEADDR_SHIFT ) & \ GRETHGBIT_RDTBA_BASEADDR_MASK ) #define GRETHGBIT_RDTBA_DESCPNT_SHIFT 3 -#define GRETHGBIT_RDTBA_DESCPNT_MASK 0x3f8U -#define GRETHGBIT_RDTBA_DESCPNT_GET( _reg ) \ +#define GRETHGBIT_RDTBA_DESCPNT_MASK 0x3f8U +#define GRETHGBIT_RDTBA_DESCPNT_GET( _reg ) \ ( ( ( _reg ) & GRETHGBIT_RDTBA_DESCPNT_MASK ) >> \ GRETHGBIT_RDTBA_DESCPNT_SHIFT ) -#define GRETHGBIT_RDTBA_DESCPNT_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRETHGBIT_RDTBA_DESCPNT_MASK ) | \ +#define GRETHGBIT_RDTBA_DESCPNT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRETHGBIT_RDTBA_DESCPNT_MASK ) | \ ( ( ( _val ) << GRETHGBIT_RDTBA_DESCPNT_SHIFT ) & \ GRETHGBIT_RDTBA_DESCPNT_MASK ) ) -#define GRETHGBIT_RDTBA_DESCPNT( _val ) \ +#define GRETHGBIT_RDTBA_DESCPNT( _val ) \ ( ( ( _val ) << GRETHGBIT_RDTBA_DESCPNT_SHIFT ) & \ GRETHGBIT_RDTBA_DESCPNT_MASK ) @@ -348,15 +339,15 @@ extern "C" { */ #define GRETHGBIT_EDCLMACMSB_MSB_SHIFT 0 -#define GRETHGBIT_EDCLMACMSB_MSB_MASK 0xffffU -#define GRETHGBIT_EDCLMACMSB_MSB_GET( _reg ) \ +#define GRETHGBIT_EDCLMACMSB_MSB_MASK 0xffffU +#define GRETHGBIT_EDCLMACMSB_MSB_GET( _reg ) \ ( ( ( _reg ) & GRETHGBIT_EDCLMACMSB_MSB_MASK ) >> \ GRETHGBIT_EDCLMACMSB_MSB_SHIFT ) -#define GRETHGBIT_EDCLMACMSB_MSB_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRETHGBIT_EDCLMACMSB_MSB_MASK ) | \ +#define GRETHGBIT_EDCLMACMSB_MSB_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRETHGBIT_EDCLMACMSB_MSB_MASK ) | \ ( ( ( _val ) << GRETHGBIT_EDCLMACMSB_MSB_SHIFT ) & \ GRETHGBIT_EDCLMACMSB_MSB_MASK ) ) -#define GRETHGBIT_EDCLMACMSB_MSB( _val ) \ +#define GRETHGBIT_EDCLMACMSB_MSB( _val ) \ ( ( ( _val ) << GRETHGBIT_EDCLMACMSB_MSB_SHIFT ) & \ GRETHGBIT_EDCLMACMSB_MSB_MASK ) @@ -371,15 +362,15 @@ extern "C" { */ #define GRETHGBIT_EDCLMACLSB_LSB_SHIFT 0 -#define GRETHGBIT_EDCLMACLSB_LSB_MASK 0xffffffffU -#define GRETHGBIT_EDCLMACLSB_LSB_GET( _reg ) \ +#define GRETHGBIT_EDCLMACLSB_LSB_MASK 0xffffffffU +#define GRETHGBIT_EDCLMACLSB_LSB_GET( _reg ) \ ( ( ( _reg ) & GRETHGBIT_EDCLMACLSB_LSB_MASK ) >> \ GRETHGBIT_EDCLMACLSB_LSB_SHIFT ) -#define GRETHGBIT_EDCLMACLSB_LSB_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRETHGBIT_EDCLMACLSB_LSB_MASK ) | \ +#define GRETHGBIT_EDCLMACLSB_LSB_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRETHGBIT_EDCLMACLSB_LSB_MASK ) | \ ( ( ( _val ) << GRETHGBIT_EDCLMACLSB_LSB_SHIFT ) & \ GRETHGBIT_EDCLMACLSB_LSB_MASK ) ) -#define GRETHGBIT_EDCLMACLSB_LSB( _val ) \ +#define GRETHGBIT_EDCLMACLSB_LSB( _val ) \ ( ( ( _val ) << GRETHGBIT_EDCLMACLSB_LSB_SHIFT ) & \ GRETHGBIT_EDCLMACLSB_LSB_MASK ) diff --git a/bsps/include/grlib/grgpio-regs.h b/bsps/include/grlib/grgpio-regs.h index 8c3c7ffb16..abe408ed9b 100644 --- a/bsps/include/grlib/grgpio-regs.h +++ b/bsps/include/grlib/grgpio-regs.h @@ -82,17 +82,14 @@ extern "C" { */ #define GRGPIO_DATA_DATA_SHIFT 0 -#define GRGPIO_DATA_DATA_MASK 0xffffffffU +#define GRGPIO_DATA_DATA_MASK 0xffffffffU #define GRGPIO_DATA_DATA_GET( _reg ) \ - ( ( ( _reg ) & GRGPIO_DATA_DATA_MASK ) >> \ - GRGPIO_DATA_DATA_SHIFT ) -#define GRGPIO_DATA_DATA_SET( _reg, _val ) \ + ( ( ( _reg ) & GRGPIO_DATA_DATA_MASK ) >> GRGPIO_DATA_DATA_SHIFT ) +#define GRGPIO_DATA_DATA_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRGPIO_DATA_DATA_MASK ) | \ - ( ( ( _val ) << GRGPIO_DATA_DATA_SHIFT ) & \ - GRGPIO_DATA_DATA_MASK ) ) + ( ( ( _val ) << GRGPIO_DATA_DATA_SHIFT ) & GRGPIO_DATA_DATA_MASK ) ) #define GRGPIO_DATA_DATA( _val ) \ - ( ( ( _val ) << GRGPIO_DATA_DATA_SHIFT ) & \ - GRGPIO_DATA_DATA_MASK ) + ( ( ( _val ) << GRGPIO_DATA_DATA_SHIFT ) & GRGPIO_DATA_DATA_MASK ) /** @} */ @@ -105,17 +102,14 @@ extern "C" { */ #define GRGPIO_OUTPUT_DATA_SHIFT 0 -#define GRGPIO_OUTPUT_DATA_MASK 0xffffffffU +#define GRGPIO_OUTPUT_DATA_MASK 0xffffffffU #define GRGPIO_OUTPUT_DATA_GET( _reg ) \ - ( ( ( _reg ) & GRGPIO_OUTPUT_DATA_MASK ) >> \ - GRGPIO_OUTPUT_DATA_SHIFT ) -#define GRGPIO_OUTPUT_DATA_SET( _reg, _val ) \ + ( ( ( _reg ) & GRGPIO_OUTPUT_DATA_MASK ) >> GRGPIO_OUTPUT_DATA_SHIFT ) +#define GRGPIO_OUTPUT_DATA_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRGPIO_OUTPUT_DATA_MASK ) | \ - ( ( ( _val ) << GRGPIO_OUTPUT_DATA_SHIFT ) & \ - GRGPIO_OUTPUT_DATA_MASK ) ) + ( ( ( _val ) << GRGPIO_OUTPUT_DATA_SHIFT ) & GRGPIO_OUTPUT_DATA_MASK ) ) #define GRGPIO_OUTPUT_DATA( _val ) \ - ( ( ( _val ) << GRGPIO_OUTPUT_DATA_SHIFT ) & \ - GRGPIO_OUTPUT_DATA_MASK ) + ( ( ( _val ) << GRGPIO_OUTPUT_DATA_SHIFT ) & GRGPIO_OUTPUT_DATA_MASK ) /** @} */ @@ -128,17 +122,15 @@ extern "C" { */ #define GRGPIO_DIRECTION_DIR_SHIFT 0 -#define GRGPIO_DIRECTION_DIR_MASK 0xffffffffU +#define GRGPIO_DIRECTION_DIR_MASK 0xffffffffU #define GRGPIO_DIRECTION_DIR_GET( _reg ) \ - ( ( ( _reg ) & GRGPIO_DIRECTION_DIR_MASK ) >> \ - GRGPIO_DIRECTION_DIR_SHIFT ) -#define GRGPIO_DIRECTION_DIR_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRGPIO_DIRECTION_DIR_MASK ) | \ + ( ( ( _reg ) & GRGPIO_DIRECTION_DIR_MASK ) >> GRGPIO_DIRECTION_DIR_SHIFT ) +#define GRGPIO_DIRECTION_DIR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRGPIO_DIRECTION_DIR_MASK ) | \ ( ( ( _val ) << GRGPIO_DIRECTION_DIR_SHIFT ) & \ GRGPIO_DIRECTION_DIR_MASK ) ) #define GRGPIO_DIRECTION_DIR( _val ) \ - ( ( ( _val ) << GRGPIO_DIRECTION_DIR_SHIFT ) & \ - GRGPIO_DIRECTION_DIR_MASK ) + ( ( ( _val ) << GRGPIO_DIRECTION_DIR_SHIFT ) & GRGPIO_DIRECTION_DIR_MASK ) /** @} */ @@ -151,17 +143,14 @@ extern "C" { */ #define GRGPIO_IMASK_MASK_SHIFT 0 -#define GRGPIO_IMASK_MASK_MASK 0xffffffffU +#define GRGPIO_IMASK_MASK_MASK 0xffffffffU #define GRGPIO_IMASK_MASK_GET( _reg ) \ - ( ( ( _reg ) & GRGPIO_IMASK_MASK_MASK ) >> \ - GRGPIO_IMASK_MASK_SHIFT ) -#define GRGPIO_IMASK_MASK_SET( _reg, _val ) \ + ( ( ( _reg ) & GRGPIO_IMASK_MASK_MASK ) >> GRGPIO_IMASK_MASK_SHIFT ) +#define GRGPIO_IMASK_MASK_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRGPIO_IMASK_MASK_MASK ) | \ - ( ( ( _val ) << GRGPIO_IMASK_MASK_SHIFT ) & \ - GRGPIO_IMASK_MASK_MASK ) ) + ( ( ( _val ) << GRGPIO_IMASK_MASK_SHIFT ) & GRGPIO_IMASK_MASK_MASK ) ) #define GRGPIO_IMASK_MASK( _val ) \ - ( ( ( _val ) << GRGPIO_IMASK_MASK_SHIFT ) & \ - GRGPIO_IMASK_MASK_MASK ) + ( ( ( _val ) << GRGPIO_IMASK_MASK_SHIFT ) & GRGPIO_IMASK_MASK_MASK ) /** @} */ @@ -174,17 +163,14 @@ extern "C" { */ #define GRGPIO_IPOL_POL_SHIFT 0 -#define GRGPIO_IPOL_POL_MASK 0xffffffffU +#define GRGPIO_IPOL_POL_MASK 0xffffffffU #define GRGPIO_IPOL_POL_GET( _reg ) \ - ( ( ( _reg ) & GRGPIO_IPOL_POL_MASK ) >> \ - GRGPIO_IPOL_POL_SHIFT ) -#define GRGPIO_IPOL_POL_SET( _reg, _val ) \ + ( ( ( _reg ) & GRGPIO_IPOL_POL_MASK ) >> GRGPIO_IPOL_POL_SHIFT ) +#define GRGPIO_IPOL_POL_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRGPIO_IPOL_POL_MASK ) | \ - ( ( ( _val ) << GRGPIO_IPOL_POL_SHIFT ) & \ - GRGPIO_IPOL_POL_MASK ) ) + ( ( ( _val ) << GRGPIO_IPOL_POL_SHIFT ) & GRGPIO_IPOL_POL_MASK ) ) #define GRGPIO_IPOL_POL( _val ) \ - ( ( ( _val ) << GRGPIO_IPOL_POL_SHIFT ) & \ - GRGPIO_IPOL_POL_MASK ) + ( ( ( _val ) << GRGPIO_IPOL_POL_SHIFT ) & GRGPIO_IPOL_POL_MASK ) /** @} */ @@ -197,17 +183,14 @@ extern "C" { */ #define GRGPIO_IEDGE_EDGE_SHIFT 0 -#define GRGPIO_IEDGE_EDGE_MASK 0xffffffffU +#define GRGPIO_IEDGE_EDGE_MASK 0xffffffffU #define GRGPIO_IEDGE_EDGE_GET( _reg ) \ - ( ( ( _reg ) & GRGPIO_IEDGE_EDGE_MASK ) >> \ - GRGPIO_IEDGE_EDGE_SHIFT ) -#define GRGPIO_IEDGE_EDGE_SET( _reg, _val ) \ + ( ( ( _reg ) & GRGPIO_IEDGE_EDGE_MASK ) >> GRGPIO_IEDGE_EDGE_SHIFT ) +#define GRGPIO_IEDGE_EDGE_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRGPIO_IEDGE_EDGE_MASK ) | \ - ( ( ( _val ) << GRGPIO_IEDGE_EDGE_SHIFT ) & \ - GRGPIO_IEDGE_EDGE_MASK ) ) + ( ( ( _val ) << GRGPIO_IEDGE_EDGE_SHIFT ) & GRGPIO_IEDGE_EDGE_MASK ) ) #define GRGPIO_IEDGE_EDGE( _val ) \ - ( ( ( _val ) << GRGPIO_IEDGE_EDGE_SHIFT ) & \ - GRGPIO_IEDGE_EDGE_MASK ) + ( ( ( _val ) << GRGPIO_IEDGE_EDGE_SHIFT ) & GRGPIO_IEDGE_EDGE_MASK ) /** @} */ @@ -220,17 +203,15 @@ extern "C" { */ #define GRGPIO_BYPASS_BYPASS_SHIFT 0 -#define GRGPIO_BYPASS_BYPASS_MASK 0xffffffffU +#define GRGPIO_BYPASS_BYPASS_MASK 0xffffffffU #define GRGPIO_BYPASS_BYPASS_GET( _reg ) \ - ( ( ( _reg ) & GRGPIO_BYPASS_BYPASS_MASK ) >> \ - GRGPIO_BYPASS_BYPASS_SHIFT ) -#define GRGPIO_BYPASS_BYPASS_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRGPIO_BYPASS_BYPASS_MASK ) | \ + ( ( ( _reg ) & GRGPIO_BYPASS_BYPASS_MASK ) >> GRGPIO_BYPASS_BYPASS_SHIFT ) +#define GRGPIO_BYPASS_BYPASS_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRGPIO_BYPASS_BYPASS_MASK ) | \ ( ( ( _val ) << GRGPIO_BYPASS_BYPASS_SHIFT ) & \ GRGPIO_BYPASS_BYPASS_MASK ) ) #define GRGPIO_BYPASS_BYPASS( _val ) \ - ( ( ( _val ) << GRGPIO_BYPASS_BYPASS_SHIFT ) & \ - GRGPIO_BYPASS_BYPASS_MASK ) + ( ( ( _val ) << GRGPIO_BYPASS_BYPASS_SHIFT ) & GRGPIO_BYPASS_BYPASS_MASK ) /** @} */ @@ -249,30 +230,24 @@ extern "C" { #define GRGPIO_CAP_IFL 0x10000U #define GRGPIO_CAP_IRQGEN_SHIFT 8 -#define GRGPIO_CAP_IRQGEN_MASK 0x1f00U +#define GRGPIO_CAP_IRQGEN_MASK 0x1f00U #define GRGPIO_CAP_IRQGEN_GET( _reg ) \ - ( ( ( _reg ) & GRGPIO_CAP_IRQGEN_MASK ) >> \ - GRGPIO_CAP_IRQGEN_SHIFT ) -#define GRGPIO_CAP_IRQGEN_SET( _reg, _val ) \ + ( ( ( _reg ) & GRGPIO_CAP_IRQGEN_MASK ) >> GRGPIO_CAP_IRQGEN_SHIFT ) +#define GRGPIO_CAP_IRQGEN_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRGPIO_CAP_IRQGEN_MASK ) | \ - ( ( ( _val ) << GRGPIO_CAP_IRQGEN_SHIFT ) & \ - GRGPIO_CAP_IRQGEN_MASK ) ) + ( ( ( _val ) << GRGPIO_CAP_IRQGEN_SHIFT ) & GRGPIO_CAP_IRQGEN_MASK ) ) #define GRGPIO_CAP_IRQGEN( _val ) \ - ( ( ( _val ) << GRGPIO_CAP_IRQGEN_SHIFT ) & \ - GRGPIO_CAP_IRQGEN_MASK ) + ( ( ( _val ) << GRGPIO_CAP_IRQGEN_SHIFT ) & GRGPIO_CAP_IRQGEN_MASK ) #define GRGPIO_CAP_NLINES_SHIFT 0 -#define GRGPIO_CAP_NLINES_MASK 0x1fU +#define GRGPIO_CAP_NLINES_MASK 0x1fU #define GRGPIO_CAP_NLINES_GET( _reg ) \ - ( ( ( _reg ) & GRGPIO_CAP_NLINES_MASK ) >> \ - GRGPIO_CAP_NLINES_SHIFT ) -#define GRGPIO_CAP_NLINES_SET( _reg, _val ) \ + ( ( ( _reg ) & GRGPIO_CAP_NLINES_MASK ) >> GRGPIO_CAP_NLINES_SHIFT ) +#define GRGPIO_CAP_NLINES_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRGPIO_CAP_NLINES_MASK ) | \ - ( ( ( _val ) << GRGPIO_CAP_NLINES_SHIFT ) & \ - GRGPIO_CAP_NLINES_MASK ) ) + ( ( ( _val ) << GRGPIO_CAP_NLINES_SHIFT ) & GRGPIO_CAP_NLINES_MASK ) ) #define GRGPIO_CAP_NLINES( _val ) \ - ( ( ( _val ) << GRGPIO_CAP_NLINES_SHIFT ) & \ - GRGPIO_CAP_NLINES_MASK ) + ( ( ( _val ) << GRGPIO_CAP_NLINES_SHIFT ) & GRGPIO_CAP_NLINES_MASK ) /** @} */ @@ -286,54 +261,54 @@ extern "C" { */ #define GRGPIO_IRQMAPR_IRQMAP_I_0_SHIFT 24 -#define GRGPIO_IRQMAPR_IRQMAP_I_0_MASK 0x1f000000U -#define GRGPIO_IRQMAPR_IRQMAP_I_0_GET( _reg ) \ +#define GRGPIO_IRQMAPR_IRQMAP_I_0_MASK 0x1f000000U +#define GRGPIO_IRQMAPR_IRQMAP_I_0_GET( _reg ) \ ( ( ( _reg ) & GRGPIO_IRQMAPR_IRQMAP_I_0_MASK ) >> \ GRGPIO_IRQMAPR_IRQMAP_I_0_SHIFT ) -#define GRGPIO_IRQMAPR_IRQMAP_I_0_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRGPIO_IRQMAPR_IRQMAP_I_0_MASK ) | \ +#define GRGPIO_IRQMAPR_IRQMAP_I_0_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRGPIO_IRQMAPR_IRQMAP_I_0_MASK ) | \ ( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_0_SHIFT ) & \ GRGPIO_IRQMAPR_IRQMAP_I_0_MASK ) ) -#define GRGPIO_IRQMAPR_IRQMAP_I_0( _val ) \ +#define GRGPIO_IRQMAPR_IRQMAP_I_0( _val ) \ ( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_0_SHIFT ) & \ GRGPIO_IRQMAPR_IRQMAP_I_0_MASK ) #define GRGPIO_IRQMAPR_IRQMAP_I_1_SHIFT 16 -#define GRGPIO_IRQMAPR_IRQMAP_I_1_MASK 0x1f0000U -#define GRGPIO_IRQMAPR_IRQMAP_I_1_GET( _reg ) \ +#define GRGPIO_IRQMAPR_IRQMAP_I_1_MASK 0x1f0000U +#define GRGPIO_IRQMAPR_IRQMAP_I_1_GET( _reg ) \ ( ( ( _reg ) & GRGPIO_IRQMAPR_IRQMAP_I_1_MASK ) >> \ GRGPIO_IRQMAPR_IRQMAP_I_1_SHIFT ) -#define GRGPIO_IRQMAPR_IRQMAP_I_1_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRGPIO_IRQMAPR_IRQMAP_I_1_MASK ) | \ +#define GRGPIO_IRQMAPR_IRQMAP_I_1_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRGPIO_IRQMAPR_IRQMAP_I_1_MASK ) | \ ( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_1_SHIFT ) & \ GRGPIO_IRQMAPR_IRQMAP_I_1_MASK ) ) -#define GRGPIO_IRQMAPR_IRQMAP_I_1( _val ) \ +#define GRGPIO_IRQMAPR_IRQMAP_I_1( _val ) \ ( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_1_SHIFT ) & \ GRGPIO_IRQMAPR_IRQMAP_I_1_MASK ) #define GRGPIO_IRQMAPR_IRQMAP_I_2_SHIFT 8 -#define GRGPIO_IRQMAPR_IRQMAP_I_2_MASK 0x1f00U -#define GRGPIO_IRQMAPR_IRQMAP_I_2_GET( _reg ) \ +#define GRGPIO_IRQMAPR_IRQMAP_I_2_MASK 0x1f00U +#define GRGPIO_IRQMAPR_IRQMAP_I_2_GET( _reg ) \ ( ( ( _reg ) & GRGPIO_IRQMAPR_IRQMAP_I_2_MASK ) >> \ GRGPIO_IRQMAPR_IRQMAP_I_2_SHIFT ) -#define GRGPIO_IRQMAPR_IRQMAP_I_2_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRGPIO_IRQMAPR_IRQMAP_I_2_MASK ) | \ +#define GRGPIO_IRQMAPR_IRQMAP_I_2_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRGPIO_IRQMAPR_IRQMAP_I_2_MASK ) | \ ( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_2_SHIFT ) & \ GRGPIO_IRQMAPR_IRQMAP_I_2_MASK ) ) -#define GRGPIO_IRQMAPR_IRQMAP_I_2( _val ) \ +#define GRGPIO_IRQMAPR_IRQMAP_I_2( _val ) \ ( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_2_SHIFT ) & \ GRGPIO_IRQMAPR_IRQMAP_I_2_MASK ) #define GRGPIO_IRQMAPR_IRQMAP_I_3_SHIFT 0 -#define GRGPIO_IRQMAPR_IRQMAP_I_3_MASK 0x1fU -#define GRGPIO_IRQMAPR_IRQMAP_I_3_GET( _reg ) \ +#define GRGPIO_IRQMAPR_IRQMAP_I_3_MASK 0x1fU +#define GRGPIO_IRQMAPR_IRQMAP_I_3_GET( _reg ) \ ( ( ( _reg ) & GRGPIO_IRQMAPR_IRQMAP_I_3_MASK ) >> \ GRGPIO_IRQMAPR_IRQMAP_I_3_SHIFT ) -#define GRGPIO_IRQMAPR_IRQMAP_I_3_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRGPIO_IRQMAPR_IRQMAP_I_3_MASK ) | \ +#define GRGPIO_IRQMAPR_IRQMAP_I_3_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRGPIO_IRQMAPR_IRQMAP_I_3_MASK ) | \ ( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_3_SHIFT ) & \ GRGPIO_IRQMAPR_IRQMAP_I_3_MASK ) ) -#define GRGPIO_IRQMAPR_IRQMAP_I_3( _val ) \ +#define GRGPIO_IRQMAPR_IRQMAP_I_3( _val ) \ ( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_3_SHIFT ) & \ GRGPIO_IRQMAPR_IRQMAP_I_3_MASK ) @@ -348,17 +323,15 @@ extern "C" { */ #define GRGPIO_IAVAIL_IMASK_SHIFT 0 -#define GRGPIO_IAVAIL_IMASK_MASK 0xffffffffU +#define GRGPIO_IAVAIL_IMASK_MASK 0xffffffffU #define GRGPIO_IAVAIL_IMASK_GET( _reg ) \ - ( ( ( _reg ) & GRGPIO_IAVAIL_IMASK_MASK ) >> \ - GRGPIO_IAVAIL_IMASK_SHIFT ) -#define GRGPIO_IAVAIL_IMASK_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRGPIO_IAVAIL_IMASK_MASK ) | \ + ( ( ( _reg ) & GRGPIO_IAVAIL_IMASK_MASK ) >> GRGPIO_IAVAIL_IMASK_SHIFT ) +#define GRGPIO_IAVAIL_IMASK_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRGPIO_IAVAIL_IMASK_MASK ) | \ ( ( ( _val ) << GRGPIO_IAVAIL_IMASK_SHIFT ) & \ GRGPIO_IAVAIL_IMASK_MASK ) ) #define GRGPIO_IAVAIL_IMASK( _val ) \ - ( ( ( _val ) << GRGPIO_IAVAIL_IMASK_SHIFT ) & \ - GRGPIO_IAVAIL_IMASK_MASK ) + ( ( ( _val ) << GRGPIO_IAVAIL_IMASK_SHIFT ) & GRGPIO_IAVAIL_IMASK_MASK ) /** @} */ @@ -371,17 +344,14 @@ extern "C" { */ #define GRGPIO_IFLAG_IFLAG_SHIFT 0 -#define GRGPIO_IFLAG_IFLAG_MASK 0xffffffffU +#define GRGPIO_IFLAG_IFLAG_MASK 0xffffffffU #define GRGPIO_IFLAG_IFLAG_GET( _reg ) \ - ( ( ( _reg ) & GRGPIO_IFLAG_IFLAG_MASK ) >> \ - GRGPIO_IFLAG_IFLAG_SHIFT ) -#define GRGPIO_IFLAG_IFLAG_SET( _reg, _val ) \ + ( ( ( _reg ) & GRGPIO_IFLAG_IFLAG_MASK ) >> GRGPIO_IFLAG_IFLAG_SHIFT ) +#define GRGPIO_IFLAG_IFLAG_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRGPIO_IFLAG_IFLAG_MASK ) | \ - ( ( ( _val ) << GRGPIO_IFLAG_IFLAG_SHIFT ) & \ - GRGPIO_IFLAG_IFLAG_MASK ) ) + ( ( ( _val ) << GRGPIO_IFLAG_IFLAG_SHIFT ) & GRGPIO_IFLAG_IFLAG_MASK ) ) #define GRGPIO_IFLAG_IFLAG( _val ) \ - ( ( ( _val ) << GRGPIO_IFLAG_IFLAG_SHIFT ) & \ - GRGPIO_IFLAG_IFLAG_MASK ) + ( ( ( _val ) << GRGPIO_IFLAG_IFLAG_SHIFT ) & GRGPIO_IFLAG_IFLAG_MASK ) /** @} */ @@ -394,17 +364,14 @@ extern "C" { */ #define GRGPIO_IPEN_IPEN_SHIFT 0 -#define GRGPIO_IPEN_IPEN_MASK 0xffffffffU +#define GRGPIO_IPEN_IPEN_MASK 0xffffffffU #define GRGPIO_IPEN_IPEN_GET( _reg ) \ - ( ( ( _reg ) & GRGPIO_IPEN_IPEN_MASK ) >> \ - GRGPIO_IPEN_IPEN_SHIFT ) -#define GRGPIO_IPEN_IPEN_SET( _reg, _val ) \ + ( ( ( _reg ) & GRGPIO_IPEN_IPEN_MASK ) >> GRGPIO_IPEN_IPEN_SHIFT ) +#define GRGPIO_IPEN_IPEN_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRGPIO_IPEN_IPEN_MASK ) | \ - ( ( ( _val ) << GRGPIO_IPEN_IPEN_SHIFT ) & \ - GRGPIO_IPEN_IPEN_MASK ) ) + ( ( ( _val ) << GRGPIO_IPEN_IPEN_SHIFT ) & GRGPIO_IPEN_IPEN_MASK ) ) #define GRGPIO_IPEN_IPEN( _val ) \ - ( ( ( _val ) << GRGPIO_IPEN_IPEN_SHIFT ) & \ - GRGPIO_IPEN_IPEN_MASK ) + ( ( ( _val ) << GRGPIO_IPEN_IPEN_SHIFT ) & GRGPIO_IPEN_IPEN_MASK ) /** @} */ @@ -417,17 +384,14 @@ extern "C" { */ #define GRGPIO_PULSE_PULSE_SHIFT 0 -#define GRGPIO_PULSE_PULSE_MASK 0xffffffffU +#define GRGPIO_PULSE_PULSE_MASK 0xffffffffU #define GRGPIO_PULSE_PULSE_GET( _reg ) \ - ( ( ( _reg ) & GRGPIO_PULSE_PULSE_MASK ) >> \ - GRGPIO_PULSE_PULSE_SHIFT ) -#define GRGPIO_PULSE_PULSE_SET( _reg, _val ) \ + ( ( ( _reg ) & GRGPIO_PULSE_PULSE_MASK ) >> GRGPIO_PULSE_PULSE_SHIFT ) +#define GRGPIO_PULSE_PULSE_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRGPIO_PULSE_PULSE_MASK ) | \ - ( ( ( _val ) << GRGPIO_PULSE_PULSE_SHIFT ) & \ - GRGPIO_PULSE_PULSE_MASK ) ) + ( ( ( _val ) << GRGPIO_PULSE_PULSE_SHIFT ) & GRGPIO_PULSE_PULSE_MASK ) ) #define GRGPIO_PULSE_PULSE( _val ) \ - ( ( ( _val ) << GRGPIO_PULSE_PULSE_SHIFT ) & \ - GRGPIO_PULSE_PULSE_MASK ) + ( ( ( _val ) << GRGPIO_PULSE_PULSE_SHIFT ) & GRGPIO_PULSE_PULSE_MASK ) /** @} */ @@ -440,17 +404,14 @@ extern "C" { */ #define GRGPIO_LOR_DATA_SHIFT 0 -#define GRGPIO_LOR_DATA_MASK 0xffffffffU +#define GRGPIO_LOR_DATA_MASK 0xffffffffU #define GRGPIO_LOR_DATA_GET( _reg ) \ - ( ( ( _reg ) & GRGPIO_LOR_DATA_MASK ) >> \ - GRGPIO_LOR_DATA_SHIFT ) -#define GRGPIO_LOR_DATA_SET( _reg, _val ) \ + ( ( ( _reg ) & GRGPIO_LOR_DATA_MASK ) >> GRGPIO_LOR_DATA_SHIFT ) +#define GRGPIO_LOR_DATA_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRGPIO_LOR_DATA_MASK ) | \ - ( ( ( _val ) << GRGPIO_LOR_DATA_SHIFT ) & \ - GRGPIO_LOR_DATA_MASK ) ) + ( ( ( _val ) << GRGPIO_LOR_DATA_SHIFT ) & GRGPIO_LOR_DATA_MASK ) ) #define GRGPIO_LOR_DATA( _val ) \ - ( ( ( _val ) << GRGPIO_LOR_DATA_SHIFT ) & \ - GRGPIO_LOR_DATA_MASK ) + ( ( ( _val ) << GRGPIO_LOR_DATA_SHIFT ) & GRGPIO_LOR_DATA_MASK ) /** @} */ @@ -463,17 +424,14 @@ extern "C" { */ #define GRGPIO_LAND_DATA_SHIFT 0 -#define GRGPIO_LAND_DATA_MASK 0xffffffffU +#define GRGPIO_LAND_DATA_MASK 0xffffffffU #define GRGPIO_LAND_DATA_GET( _reg ) \ - ( ( ( _reg ) & GRGPIO_LAND_DATA_MASK ) >> \ - GRGPIO_LAND_DATA_SHIFT ) -#define GRGPIO_LAND_DATA_SET( _reg, _val ) \ + ( ( ( _reg ) & GRGPIO_LAND_DATA_MASK ) >> GRGPIO_LAND_DATA_SHIFT ) +#define GRGPIO_LAND_DATA_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRGPIO_LAND_DATA_MASK ) | \ - ( ( ( _val ) << GRGPIO_LAND_DATA_SHIFT ) & \ - GRGPIO_LAND_DATA_MASK ) ) + ( ( ( _val ) << GRGPIO_LAND_DATA_SHIFT ) & GRGPIO_LAND_DATA_MASK ) ) #define GRGPIO_LAND_DATA( _val ) \ - ( ( ( _val ) << GRGPIO_LAND_DATA_SHIFT ) & \ - GRGPIO_LAND_DATA_MASK ) + ( ( ( _val ) << GRGPIO_LAND_DATA_SHIFT ) & GRGPIO_LAND_DATA_MASK ) /** @} */ @@ -486,17 +444,14 @@ extern "C" { */ #define GRGPIO_LXOR_DATA_SHIFT 0 -#define GRGPIO_LXOR_DATA_MASK 0xffffffffU +#define GRGPIO_LXOR_DATA_MASK 0xffffffffU #define GRGPIO_LXOR_DATA_GET( _reg ) \ - ( ( ( _reg ) & GRGPIO_LXOR_DATA_MASK ) >> \ - GRGPIO_LXOR_DATA_SHIFT ) -#define GRGPIO_LXOR_DATA_SET( _reg, _val ) \ + ( ( ( _reg ) & GRGPIO_LXOR_DATA_MASK ) >> GRGPIO_LXOR_DATA_SHIFT ) +#define GRGPIO_LXOR_DATA_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRGPIO_LXOR_DATA_MASK ) | \ - ( ( ( _val ) << GRGPIO_LXOR_DATA_SHIFT ) & \ - GRGPIO_LXOR_DATA_MASK ) ) + ( ( ( _val ) << GRGPIO_LXOR_DATA_SHIFT ) & GRGPIO_LXOR_DATA_MASK ) ) #define GRGPIO_LXOR_DATA( _val ) \ - ( ( ( _val ) << GRGPIO_LXOR_DATA_SHIFT ) & \ - GRGPIO_LXOR_DATA_MASK ) + ( ( ( _val ) << GRGPIO_LXOR_DATA_SHIFT ) & GRGPIO_LXOR_DATA_MASK ) /** @} */ diff --git a/bsps/include/grlib/grgpio.h b/bsps/include/grlib/grgpio.h index 6d4a28dc81..26bd83e724 100644 --- a/bsps/include/grlib/grgpio.h +++ b/bsps/include/grlib/grgpio.h @@ -35,7 +35,7 @@ extern "C" { #endif -extern void grgpio_register_drv (void); +extern void grgpio_register_drv( void ); #ifdef __cplusplus } diff --git a/bsps/include/grlib/griommu-regs.h b/bsps/include/grlib/griommu-regs.h index 4140101a14..fc67384c5a 100644 --- a/bsps/include/grlib/griommu-regs.h +++ b/bsps/include/grlib/griommu-regs.h @@ -90,32 +90,26 @@ extern "C" { #define GRIOMMU_CAP0_CP 0x10000000U #define GRIOMMU_CAP0_NARB_SHIFT 20 -#define GRIOMMU_CAP0_NARB_MASK 0xf00000U +#define GRIOMMU_CAP0_NARB_MASK 0xf00000U #define GRIOMMU_CAP0_NARB_GET( _reg ) \ - ( ( ( _reg ) & GRIOMMU_CAP0_NARB_MASK ) >> \ - GRIOMMU_CAP0_NARB_SHIFT ) -#define GRIOMMU_CAP0_NARB_SET( _reg, _val ) \ + ( ( ( _reg ) & GRIOMMU_CAP0_NARB_MASK ) >> GRIOMMU_CAP0_NARB_SHIFT ) +#define GRIOMMU_CAP0_NARB_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRIOMMU_CAP0_NARB_MASK ) | \ - ( ( ( _val ) << GRIOMMU_CAP0_NARB_SHIFT ) & \ - GRIOMMU_CAP0_NARB_MASK ) ) + ( ( ( _val ) << GRIOMMU_CAP0_NARB_SHIFT ) & GRIOMMU_CAP0_NARB_MASK ) ) #define GRIOMMU_CAP0_NARB( _val ) \ - ( ( ( _val ) << GRIOMMU_CAP0_NARB_SHIFT ) & \ - GRIOMMU_CAP0_NARB_MASK ) + ( ( ( _val ) << GRIOMMU_CAP0_NARB_SHIFT ) & GRIOMMU_CAP0_NARB_MASK ) #define GRIOMMU_CAP0_CS 0x80000U #define GRIOMMU_CAP0_FT_SHIFT 17 -#define GRIOMMU_CAP0_FT_MASK 0x60000U +#define GRIOMMU_CAP0_FT_MASK 0x60000U #define GRIOMMU_CAP0_FT_GET( _reg ) \ - ( ( ( _reg ) & GRIOMMU_CAP0_FT_MASK ) >> \ - GRIOMMU_CAP0_FT_SHIFT ) -#define GRIOMMU_CAP0_FT_SET( _reg, _val ) \ + ( ( ( _reg ) & GRIOMMU_CAP0_FT_MASK ) >> GRIOMMU_CAP0_FT_SHIFT ) +#define GRIOMMU_CAP0_FT_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRIOMMU_CAP0_FT_MASK ) | \ - ( ( ( _val ) << GRIOMMU_CAP0_FT_SHIFT ) & \ - GRIOMMU_CAP0_FT_MASK ) ) + ( ( ( _val ) << GRIOMMU_CAP0_FT_SHIFT ) & GRIOMMU_CAP0_FT_MASK ) ) #define GRIOMMU_CAP0_FT( _val ) \ - ( ( ( _val ) << GRIOMMU_CAP0_FT_SHIFT ) & \ - GRIOMMU_CAP0_FT_MASK ) + ( ( ( _val ) << GRIOMMU_CAP0_FT_SHIFT ) & GRIOMMU_CAP0_FT_MASK ) #define GRIOMMU_CAP0_ST 0x10000U @@ -130,30 +124,24 @@ extern "C" { #define GRIOMMU_CAP0_MB 0x100U #define GRIOMMU_CAP0_GRPS_SHIFT 4 -#define GRIOMMU_CAP0_GRPS_MASK 0xf0U +#define GRIOMMU_CAP0_GRPS_MASK 0xf0U #define GRIOMMU_CAP0_GRPS_GET( _reg ) \ - ( ( ( _reg ) & GRIOMMU_CAP0_GRPS_MASK ) >> \ - GRIOMMU_CAP0_GRPS_SHIFT ) -#define GRIOMMU_CAP0_GRPS_SET( _reg, _val ) \ + ( ( ( _reg ) & GRIOMMU_CAP0_GRPS_MASK ) >> GRIOMMU_CAP0_GRPS_SHIFT ) +#define GRIOMMU_CAP0_GRPS_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRIOMMU_CAP0_GRPS_MASK ) | \ - ( ( ( _val ) << GRIOMMU_CAP0_GRPS_SHIFT ) & \ - GRIOMMU_CAP0_GRPS_MASK ) ) + ( ( ( _val ) << GRIOMMU_CAP0_GRPS_SHIFT ) & GRIOMMU_CAP0_GRPS_MASK ) ) #define GRIOMMU_CAP0_GRPS( _val ) \ - ( ( ( _val ) << GRIOMMU_CAP0_GRPS_SHIFT ) & \ - GRIOMMU_CAP0_GRPS_MASK ) + ( ( ( _val ) << GRIOMMU_CAP0_GRPS_SHIFT ) & GRIOMMU_CAP0_GRPS_MASK ) #define GRIOMMU_CAP0_MSTS_SHIFT 0 -#define GRIOMMU_CAP0_MSTS_MASK 0xfU +#define GRIOMMU_CAP0_MSTS_MASK 0xfU #define GRIOMMU_CAP0_MSTS_GET( _reg ) \ - ( ( ( _reg ) & GRIOMMU_CAP0_MSTS_MASK ) >> \ - GRIOMMU_CAP0_MSTS_SHIFT ) -#define GRIOMMU_CAP0_MSTS_SET( _reg, _val ) \ + ( ( ( _reg ) & GRIOMMU_CAP0_MSTS_MASK ) >> GRIOMMU_CAP0_MSTS_SHIFT ) +#define GRIOMMU_CAP0_MSTS_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRIOMMU_CAP0_MSTS_MASK ) | \ - ( ( ( _val ) << GRIOMMU_CAP0_MSTS_SHIFT ) & \ - GRIOMMU_CAP0_MSTS_MASK ) ) + ( ( ( _val ) << GRIOMMU_CAP0_MSTS_SHIFT ) & GRIOMMU_CAP0_MSTS_MASK ) ) #define GRIOMMU_CAP0_MSTS( _val ) \ - ( ( ( _val ) << GRIOMMU_CAP0_MSTS_SHIFT ) & \ - GRIOMMU_CAP0_MSTS_MASK ) + ( ( ( _val ) << GRIOMMU_CAP0_MSTS_SHIFT ) & GRIOMMU_CAP0_MSTS_MASK ) /** @} */ @@ -166,69 +154,57 @@ extern "C" { */ #define GRIOMMU_CAP1_CADDR_SHIFT 20 -#define GRIOMMU_CAP1_CADDR_MASK 0xfff00000U +#define GRIOMMU_CAP1_CADDR_MASK 0xfff00000U #define GRIOMMU_CAP1_CADDR_GET( _reg ) \ - ( ( ( _reg ) & GRIOMMU_CAP1_CADDR_MASK ) >> \ - GRIOMMU_CAP1_CADDR_SHIFT ) -#define GRIOMMU_CAP1_CADDR_SET( _reg, _val ) \ + ( ( ( _reg ) & GRIOMMU_CAP1_CADDR_MASK ) >> GRIOMMU_CAP1_CADDR_SHIFT ) +#define GRIOMMU_CAP1_CADDR_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRIOMMU_CAP1_CADDR_MASK ) | \ - ( ( ( _val ) << GRIOMMU_CAP1_CADDR_SHIFT ) & \ - GRIOMMU_CAP1_CADDR_MASK ) ) + ( ( ( _val ) << GRIOMMU_CAP1_CADDR_SHIFT ) & GRIOMMU_CAP1_CADDR_MASK ) ) #define GRIOMMU_CAP1_CADDR( _val ) \ - ( ( ( _val ) << GRIOMMU_CAP1_CADDR_SHIFT ) & \ - GRIOMMU_CAP1_CADDR_MASK ) + ( ( ( _val ) << GRIOMMU_CAP1_CADDR_SHIFT ) & GRIOMMU_CAP1_CADDR_MASK ) #define GRIOMMU_CAP1_CMASK_SHIFT 16 -#define GRIOMMU_CAP1_CMASK_MASK 0xf0000U +#define GRIOMMU_CAP1_CMASK_MASK 0xf0000U #define GRIOMMU_CAP1_CMASK_GET( _reg ) \ - ( ( ( _reg ) & GRIOMMU_CAP1_CMASK_MASK ) >> \ - GRIOMMU_CAP1_CMASK_SHIFT ) -#define GRIOMMU_CAP1_CMASK_SET( _reg, _val ) \ + ( ( ( _reg ) & GRIOMMU_CAP1_CMASK_MASK ) >> GRIOMMU_CAP1_CMASK_SHIFT ) +#define GRIOMMU_CAP1_CMASK_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRIOMMU_CAP1_CMASK_MASK ) | \ - ( ( ( _val ) << GRIOMMU_CAP1_CMASK_SHIFT ) & \ - GRIOMMU_CAP1_CMASK_MASK ) ) + ( ( ( _val ) << GRIOMMU_CAP1_CMASK_SHIFT ) & GRIOMMU_CAP1_CMASK_MASK ) ) #define GRIOMMU_CAP1_CMASK( _val ) \ - ( ( ( _val ) << GRIOMMU_CAP1_CMASK_SHIFT ) & \ - GRIOMMU_CAP1_CMASK_MASK ) + ( ( ( _val ) << GRIOMMU_CAP1_CMASK_SHIFT ) & GRIOMMU_CAP1_CMASK_MASK ) #define GRIOMMU_CAP1_CTAGBITS_SHIFT 8 -#define GRIOMMU_CAP1_CTAGBITS_MASK 0xff00U +#define GRIOMMU_CAP1_CTAGBITS_MASK 0xff00U #define GRIOMMU_CAP1_CTAGBITS_GET( _reg ) \ - ( ( ( _reg ) & GRIOMMU_CAP1_CTAGBITS_MASK ) >> \ - GRIOMMU_CAP1_CTAGBITS_SHIFT ) -#define GRIOMMU_CAP1_CTAGBITS_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRIOMMU_CAP1_CTAGBITS_MASK ) | \ + ( ( ( _reg ) & GRIOMMU_CAP1_CTAGBITS_MASK ) >> GRIOMMU_CAP1_CTAGBITS_SHIFT ) +#define GRIOMMU_CAP1_CTAGBITS_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRIOMMU_CAP1_CTAGBITS_MASK ) | \ ( ( ( _val ) << GRIOMMU_CAP1_CTAGBITS_SHIFT ) & \ GRIOMMU_CAP1_CTAGBITS_MASK ) ) #define GRIOMMU_CAP1_CTAGBITS( _val ) \ - ( ( ( _val ) << GRIOMMU_CAP1_CTAGBITS_SHIFT ) & \ - GRIOMMU_CAP1_CTAGBITS_MASK ) + ( ( ( _val ) << GRIOMMU_CAP1_CTAGBITS_SHIFT ) & GRIOMMU_CAP1_CTAGBITS_MASK ) #define GRIOMMU_CAP1_CISIZE_SHIFT 5 -#define GRIOMMU_CAP1_CISIZE_MASK 0xe0U +#define GRIOMMU_CAP1_CISIZE_MASK 0xe0U #define GRIOMMU_CAP1_CISIZE_GET( _reg ) \ - ( ( ( _reg ) & GRIOMMU_CAP1_CISIZE_MASK ) >> \ - GRIOMMU_CAP1_CISIZE_SHIFT ) -#define GRIOMMU_CAP1_CISIZE_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRIOMMU_CAP1_CISIZE_MASK ) | \ + ( ( ( _reg ) & GRIOMMU_CAP1_CISIZE_MASK ) >> GRIOMMU_CAP1_CISIZE_SHIFT ) +#define GRIOMMU_CAP1_CISIZE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRIOMMU_CAP1_CISIZE_MASK ) | \ ( ( ( _val ) << GRIOMMU_CAP1_CISIZE_SHIFT ) & \ GRIOMMU_CAP1_CISIZE_MASK ) ) #define GRIOMMU_CAP1_CISIZE( _val ) \ - ( ( ( _val ) << GRIOMMU_CAP1_CISIZE_SHIFT ) & \ - GRIOMMU_CAP1_CISIZE_MASK ) + ( ( ( _val ) << GRIOMMU_CAP1_CISIZE_SHIFT ) & GRIOMMU_CAP1_CISIZE_MASK ) #define GRIOMMU_CAP1_CLINES_SHIFT 0 -#define GRIOMMU_CAP1_CLINES_MASK 0x1fU +#define GRIOMMU_CAP1_CLINES_MASK 0x1fU #define GRIOMMU_CAP1_CLINES_GET( _reg ) \ - ( ( ( _reg ) & GRIOMMU_CAP1_CLINES_MASK ) >> \ - GRIOMMU_CAP1_CLINES_SHIFT ) -#define GRIOMMU_CAP1_CLINES_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRIOMMU_CAP1_CLINES_MASK ) | \ + ( ( ( _reg ) & GRIOMMU_CAP1_CLINES_MASK ) >> GRIOMMU_CAP1_CLINES_SHIFT ) +#define GRIOMMU_CAP1_CLINES_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRIOMMU_CAP1_CLINES_MASK ) | \ ( ( ( _val ) << GRIOMMU_CAP1_CLINES_SHIFT ) & \ GRIOMMU_CAP1_CLINES_MASK ) ) #define GRIOMMU_CAP1_CLINES( _val ) \ - ( ( ( _val ) << GRIOMMU_CAP1_CLINES_SHIFT ) & \ - GRIOMMU_CAP1_CLINES_MASK ) + ( ( ( _val ) << GRIOMMU_CAP1_CLINES_SHIFT ) & GRIOMMU_CAP1_CLINES_MASK ) /** @} */ @@ -241,82 +217,66 @@ extern "C" { */ #define GRIOMMU_CAP2_TMASK_SHIFT 24 -#define GRIOMMU_CAP2_TMASK_MASK 0xff000000U +#define GRIOMMU_CAP2_TMASK_MASK 0xff000000U #define GRIOMMU_CAP2_TMASK_GET( _reg ) \ - ( ( ( _reg ) & GRIOMMU_CAP2_TMASK_MASK ) >> \ - GRIOMMU_CAP2_TMASK_SHIFT ) -#define GRIOMMU_CAP2_TMASK_SET( _reg, _val ) \ + ( ( ( _reg ) & GRIOMMU_CAP2_TMASK_MASK ) >> GRIOMMU_CAP2_TMASK_SHIFT ) +#define GRIOMMU_CAP2_TMASK_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRIOMMU_CAP2_TMASK_MASK ) | \ - ( ( ( _val ) << GRIOMMU_CAP2_TMASK_SHIFT ) & \ - GRIOMMU_CAP2_TMASK_MASK ) ) + ( ( ( _val ) << GRIOMMU_CAP2_TMASK_SHIFT ) & GRIOMMU_CAP2_TMASK_MASK ) ) #define GRIOMMU_CAP2_TMASK( _val ) \ - ( ( ( _val ) << GRIOMMU_CAP2_TMASK_SHIFT ) & \ - GRIOMMU_CAP2_TMASK_MASK ) + ( ( ( _val ) << GRIOMMU_CAP2_TMASK_SHIFT ) & GRIOMMU_CAP2_TMASK_MASK ) #define GRIOMMU_CAP2_MTYPE_SHIFT 18 -#define GRIOMMU_CAP2_MTYPE_MASK 0xc0000U +#define GRIOMMU_CAP2_MTYPE_MASK 0xc0000U #define GRIOMMU_CAP2_MTYPE_GET( _reg ) \ - ( ( ( _reg ) & GRIOMMU_CAP2_MTYPE_MASK ) >> \ - GRIOMMU_CAP2_MTYPE_SHIFT ) -#define GRIOMMU_CAP2_MTYPE_SET( _reg, _val ) \ + ( ( ( _reg ) & GRIOMMU_CAP2_MTYPE_MASK ) >> GRIOMMU_CAP2_MTYPE_SHIFT ) +#define GRIOMMU_CAP2_MTYPE_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRIOMMU_CAP2_MTYPE_MASK ) | \ - ( ( ( _val ) << GRIOMMU_CAP2_MTYPE_SHIFT ) & \ - GRIOMMU_CAP2_MTYPE_MASK ) ) + ( ( ( _val ) << GRIOMMU_CAP2_MTYPE_SHIFT ) & GRIOMMU_CAP2_MTYPE_MASK ) ) #define GRIOMMU_CAP2_MTYPE( _val ) \ - ( ( ( _val ) << GRIOMMU_CAP2_MTYPE_SHIFT ) & \ - GRIOMMU_CAP2_MTYPE_MASK ) + ( ( ( _val ) << GRIOMMU_CAP2_MTYPE_SHIFT ) & GRIOMMU_CAP2_MTYPE_MASK ) #define GRIOMMU_CAP2_TTYPE_SHIFT 16 -#define GRIOMMU_CAP2_TTYPE_MASK 0x30000U +#define GRIOMMU_CAP2_TTYPE_MASK 0x30000U #define GRIOMMU_CAP2_TTYPE_GET( _reg ) \ - ( ( ( _reg ) & GRIOMMU_CAP2_TTYPE_MASK ) >> \ - GRIOMMU_CAP2_TTYPE_SHIFT ) -#define GRIOMMU_CAP2_TTYPE_SET( _reg, _val ) \ + ( ( ( _reg ) & GRIOMMU_CAP2_TTYPE_MASK ) >> GRIOMMU_CAP2_TTYPE_SHIFT ) +#define GRIOMMU_CAP2_TTYPE_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRIOMMU_CAP2_TTYPE_MASK ) | \ - ( ( ( _val ) << GRIOMMU_CAP2_TTYPE_SHIFT ) & \ - GRIOMMU_CAP2_TTYPE_MASK ) ) + ( ( ( _val ) << GRIOMMU_CAP2_TTYPE_SHIFT ) & GRIOMMU_CAP2_TTYPE_MASK ) ) #define GRIOMMU_CAP2_TTYPE( _val ) \ - ( ( ( _val ) << GRIOMMU_CAP2_TTYPE_SHIFT ) & \ - GRIOMMU_CAP2_TTYPE_MASK ) + ( ( ( _val ) << GRIOMMU_CAP2_TTYPE_SHIFT ) & GRIOMMU_CAP2_TTYPE_MASK ) #define GRIOMMU_CAP2_TTAGBITS_SHIFT 8 -#define GRIOMMU_CAP2_TTAGBITS_MASK 0xff00U +#define GRIOMMU_CAP2_TTAGBITS_MASK 0xff00U #define GRIOMMU_CAP2_TTAGBITS_GET( _reg ) \ - ( ( ( _reg ) & GRIOMMU_CAP2_TTAGBITS_MASK ) >> \ - GRIOMMU_CAP2_TTAGBITS_SHIFT ) -#define GRIOMMU_CAP2_TTAGBITS_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRIOMMU_CAP2_TTAGBITS_MASK ) | \ + ( ( ( _reg ) & GRIOMMU_CAP2_TTAGBITS_MASK ) >> GRIOMMU_CAP2_TTAGBITS_SHIFT ) +#define GRIOMMU_CAP2_TTAGBITS_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRIOMMU_CAP2_TTAGBITS_MASK ) | \ ( ( ( _val ) << GRIOMMU_CAP2_TTAGBITS_SHIFT ) & \ GRIOMMU_CAP2_TTAGBITS_MASK ) ) #define GRIOMMU_CAP2_TTAGBITS( _val ) \ - ( ( ( _val ) << GRIOMMU_CAP2_TTAGBITS_SHIFT ) & \ - GRIOMMU_CAP2_TTAGBITS_MASK ) + ( ( ( _val ) << GRIOMMU_CAP2_TTAGBITS_SHIFT ) & GRIOMMU_CAP2_TTAGBITS_MASK ) #define GRIOMMU_CAP2_ISIZE_SHIFT 5 -#define GRIOMMU_CAP2_ISIZE_MASK 0xe0U +#define GRIOMMU_CAP2_ISIZE_MASK 0xe0U #define GRIOMMU_CAP2_ISIZE_GET( _reg ) \ - ( ( ( _reg ) & GRIOMMU_CAP2_ISIZE_MASK ) >> \ - GRIOMMU_CAP2_ISIZE_SHIFT ) -#define GRIOMMU_CAP2_ISIZE_SET( _reg, _val ) \ + ( ( ( _reg ) & GRIOMMU_CAP2_ISIZE_MASK ) >> GRIOMMU_CAP2_ISIZE_SHIFT ) +#define GRIOMMU_CAP2_ISIZE_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRIOMMU_CAP2_ISIZE_MASK ) | \ - ( ( ( _val ) << GRIOMMU_CAP2_ISIZE_SHIFT ) & \ - GRIOMMU_CAP2_ISIZE_MASK ) ) + ( ( ( _val ) << GRIOMMU_CAP2_ISIZE_SHIFT ) & GRIOMMU_CAP2_ISIZE_MASK ) ) #define GRIOMMU_CAP2_ISIZE( _val ) \ - ( ( ( _val ) << GRIOMMU_CAP2_ISIZE_SHIFT ) & \ - GRIOMMU_CAP2_ISIZE_MASK ) + ( ( ( _val ) << GRIOMMU_CAP2_ISIZE_SHIFT ) & GRIOMMU_CAP2_ISIZE_MASK ) #define GRIOMMU_CAP2_TLBENT_SHIFT 0 -#define GRIOMMU_CAP2_TLBENT_MASK 0x1fU +#define GRIOMMU_CAP2_TLBENT_MASK 0x1fU #define GRIOMMU_CAP2_TLBENT_GET( _reg ) \ - ( ( ( _reg ) & GRIOMMU_CAP2_TLBENT_MASK ) >> \ - GRIOMMU_CAP2_TLBENT_SHIFT ) -#define GRIOMMU_CAP2_TLBENT_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRIOMMU_CAP2_TLBENT_MASK ) | \ + ( ( ( _reg ) & GRIOMMU_CAP2_TLBENT_MASK ) >> GRIOMMU_CAP2_TLBENT_SHIFT ) +#define GRIOMMU_CAP2_TLBENT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRIOMMU_CAP2_TLBENT_MASK ) | \ ( ( ( _val ) << GRIOMMU_CAP2_TLBENT_SHIFT ) & \ GRIOMMU_CAP2_TLBENT_MASK ) ) #define GRIOMMU_CAP2_TLBENT( _val ) \ - ( ( ( _val ) << GRIOMMU_CAP2_TLBENT_SHIFT ) & \ - GRIOMMU_CAP2_TLBENT_MASK ) + ( ( ( _val ) << GRIOMMU_CAP2_TLBENT_SHIFT ) & GRIOMMU_CAP2_TLBENT_MASK ) /** @} */ @@ -329,51 +289,42 @@ extern "C" { */ #define GRIOMMU_CTRL_PGSZ_SHIFT 18 -#define GRIOMMU_CTRL_PGSZ_MASK 0x1c0000U +#define GRIOMMU_CTRL_PGSZ_MASK 0x1c0000U #define GRIOMMU_CTRL_PGSZ_GET( _reg ) \ - ( ( ( _reg ) & GRIOMMU_CTRL_PGSZ_MASK ) >> \ - GRIOMMU_CTRL_PGSZ_SHIFT ) -#define GRIOMMU_CTRL_PGSZ_SET( _reg, _val ) \ + ( ( ( _reg ) & GRIOMMU_CTRL_PGSZ_MASK ) >> GRIOMMU_CTRL_PGSZ_SHIFT ) +#define GRIOMMU_CTRL_PGSZ_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRIOMMU_CTRL_PGSZ_MASK ) | \ - ( ( ( _val ) << GRIOMMU_CTRL_PGSZ_SHIFT ) & \ - GRIOMMU_CTRL_PGSZ_MASK ) ) + ( ( ( _val ) << GRIOMMU_CTRL_PGSZ_SHIFT ) & GRIOMMU_CTRL_PGSZ_MASK ) ) #define GRIOMMU_CTRL_PGSZ( _val ) \ - ( ( ( _val ) << GRIOMMU_CTRL_PGSZ_SHIFT ) & \ - GRIOMMU_CTRL_PGSZ_MASK ) + ( ( ( _val ) << GRIOMMU_CTRL_PGSZ_SHIFT ) & GRIOMMU_CTRL_PGSZ_MASK ) #define GRIOMMU_CTRL_LB 0x20000U #define GRIOMMU_CTRL_SP 0x10000U #define GRIOMMU_CTRL_ITR_SHIFT 12 -#define GRIOMMU_CTRL_ITR_MASK 0xf000U +#define GRIOMMU_CTRL_ITR_MASK 0xf000U #define GRIOMMU_CTRL_ITR_GET( _reg ) \ - ( ( ( _reg ) & GRIOMMU_CTRL_ITR_MASK ) >> \ - GRIOMMU_CTRL_ITR_SHIFT ) -#define GRIOMMU_CTRL_ITR_SET( _reg, _val ) \ + ( ( ( _reg ) & GRIOMMU_CTRL_ITR_MASK ) >> GRIOMMU_CTRL_ITR_SHIFT ) +#define GRIOMMU_CTRL_ITR_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRIOMMU_CTRL_ITR_MASK ) | \ - ( ( ( _val ) << GRIOMMU_CTRL_ITR_SHIFT ) & \ - GRIOMMU_CTRL_ITR_MASK ) ) + ( ( ( _val ) << GRIOMMU_CTRL_ITR_SHIFT ) & GRIOMMU_CTRL_ITR_MASK ) ) #define GRIOMMU_CTRL_ITR( _val ) \ - ( ( ( _val ) << GRIOMMU_CTRL_ITR_SHIFT ) & \ - GRIOMMU_CTRL_ITR_MASK ) + ( ( ( _val ) << GRIOMMU_CTRL_ITR_SHIFT ) & GRIOMMU_CTRL_ITR_MASK ) #define GRIOMMU_CTRL_DP 0x800U #define GRIOMMU_CTRL_SIV 0x400U #define GRIOMMU_CTRL_HPROT_SHIFT 8 -#define GRIOMMU_CTRL_HPROT_MASK 0x300U +#define GRIOMMU_CTRL_HPROT_MASK 0x300U #define GRIOMMU_CTRL_HPROT_GET( _reg ) \ - ( ( ( _reg ) & GRIOMMU_CTRL_HPROT_MASK ) >> \ - GRIOMMU_CTRL_HPROT_SHIFT ) -#define GRIOMMU_CTRL_HPROT_SET( _reg, _val ) \ + ( ( ( _reg ) & GRIOMMU_CTRL_HPROT_MASK ) >> GRIOMMU_CTRL_HPROT_SHIFT ) +#define GRIOMMU_CTRL_HPROT_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRIOMMU_CTRL_HPROT_MASK ) | \ - ( ( ( _val ) << GRIOMMU_CTRL_HPROT_SHIFT ) & \ - GRIOMMU_CTRL_HPROT_MASK ) ) + ( ( ( _val ) << GRIOMMU_CTRL_HPROT_SHIFT ) & GRIOMMU_CTRL_HPROT_MASK ) ) #define GRIOMMU_CTRL_HPROT( _val ) \ - ( ( ( _val ) << GRIOMMU_CTRL_HPROT_SHIFT ) & \ - GRIOMMU_CTRL_HPROT_MASK ) + ( ( ( _val ) << GRIOMMU_CTRL_HPROT_SHIFT ) & GRIOMMU_CTRL_HPROT_MASK ) #define GRIOMMU_CTRL_AU 0x80U @@ -386,17 +337,14 @@ extern "C" { #define GRIOMMU_CTRL_CE 0x8U #define GRIOMMU_CTRL_PM_SHIFT 1 -#define GRIOMMU_CTRL_PM_MASK 0x6U +#define GRIOMMU_CTRL_PM_MASK 0x6U #define GRIOMMU_CTRL_PM_GET( _reg ) \ - ( ( ( _reg ) & GRIOMMU_CTRL_PM_MASK ) >> \ - GRIOMMU_CTRL_PM_SHIFT ) -#define GRIOMMU_CTRL_PM_SET( _reg, _val ) \ + ( ( ( _reg ) & GRIOMMU_CTRL_PM_MASK ) >> GRIOMMU_CTRL_PM_SHIFT ) +#define GRIOMMU_CTRL_PM_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRIOMMU_CTRL_PM_MASK ) | \ - ( ( ( _val ) << GRIOMMU_CTRL_PM_SHIFT ) & \ - GRIOMMU_CTRL_PM_MASK ) ) + ( ( ( _val ) << GRIOMMU_CTRL_PM_SHIFT ) & GRIOMMU_CTRL_PM_MASK ) ) #define GRIOMMU_CTRL_PM( _val ) \ - ( ( ( _val ) << GRIOMMU_CTRL_PM_SHIFT ) & \ - GRIOMMU_CTRL_PM_MASK ) + ( ( ( _val ) << GRIOMMU_CTRL_PM_SHIFT ) & GRIOMMU_CTRL_PM_MASK ) #define GRIOMMU_CTRL_EN 0x1U @@ -411,17 +359,14 @@ extern "C" { */ #define GRIOMMU_FLUSH_FGRP_SHIFT 4 -#define GRIOMMU_FLUSH_FGRP_MASK 0xf0U +#define GRIOMMU_FLUSH_FGRP_MASK 0xf0U #define GRIOMMU_FLUSH_FGRP_GET( _reg ) \ - ( ( ( _reg ) & GRIOMMU_FLUSH_FGRP_MASK ) >> \ - GRIOMMU_FLUSH_FGRP_SHIFT ) -#define GRIOMMU_FLUSH_FGRP_SET( _reg, _val ) \ + ( ( ( _reg ) & GRIOMMU_FLUSH_FGRP_MASK ) >> GRIOMMU_FLUSH_FGRP_SHIFT ) +#define GRIOMMU_FLUSH_FGRP_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRIOMMU_FLUSH_FGRP_MASK ) | \ - ( ( ( _val ) << GRIOMMU_FLUSH_FGRP_SHIFT ) & \ - GRIOMMU_FLUSH_FGRP_MASK ) ) + ( ( ( _val ) << GRIOMMU_FLUSH_FGRP_SHIFT ) & GRIOMMU_FLUSH_FGRP_MASK ) ) #define GRIOMMU_FLUSH_FGRP( _val ) \ - ( ( ( _val ) << GRIOMMU_FLUSH_FGRP_SHIFT ) & \ - GRIOMMU_FLUSH_FGRP_MASK ) + ( ( ( _val ) << GRIOMMU_FLUSH_FGRP_SHIFT ) & GRIOMMU_FLUSH_FGRP_MASK ) #define GRIOMMU_FLUSH_GF 0x2U @@ -480,30 +425,30 @@ extern "C" { */ #define GRIOMMU_AHBFAS_FADDR_31_5_SHIFT 5 -#define GRIOMMU_AHBFAS_FADDR_31_5_MASK 0xffffffe0U -#define GRIOMMU_AHBFAS_FADDR_31_5_GET( _reg ) \ +#define GRIOMMU_AHBFAS_FADDR_31_5_MASK 0xffffffe0U +#define GRIOMMU_AHBFAS_FADDR_31_5_GET( _reg ) \ ( ( ( _reg ) & GRIOMMU_AHBFAS_FADDR_31_5_MASK ) >> \ GRIOMMU_AHBFAS_FADDR_31_5_SHIFT ) -#define GRIOMMU_AHBFAS_FADDR_31_5_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRIOMMU_AHBFAS_FADDR_31_5_MASK ) | \ +#define GRIOMMU_AHBFAS_FADDR_31_5_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRIOMMU_AHBFAS_FADDR_31_5_MASK ) | \ ( ( ( _val ) << GRIOMMU_AHBFAS_FADDR_31_5_SHIFT ) & \ GRIOMMU_AHBFAS_FADDR_31_5_MASK ) ) -#define GRIOMMU_AHBFAS_FADDR_31_5( _val ) \ +#define GRIOMMU_AHBFAS_FADDR_31_5( _val ) \ ( ( ( _val ) << GRIOMMU_AHBFAS_FADDR_31_5_SHIFT ) & \ GRIOMMU_AHBFAS_FADDR_31_5_MASK ) #define GRIOMMU_AHBFAS_FW 0x10U #define GRIOMMU_AHBFAS_FMASTER_SHIFT 0 -#define GRIOMMU_AHBFAS_FMASTER_MASK 0xfU -#define GRIOMMU_AHBFAS_FMASTER_GET( _reg ) \ +#define GRIOMMU_AHBFAS_FMASTER_MASK 0xfU +#define GRIOMMU_AHBFAS_FMASTER_GET( _reg ) \ ( ( ( _reg ) & GRIOMMU_AHBFAS_FMASTER_MASK ) >> \ GRIOMMU_AHBFAS_FMASTER_SHIFT ) -#define GRIOMMU_AHBFAS_FMASTER_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRIOMMU_AHBFAS_FMASTER_MASK ) | \ +#define GRIOMMU_AHBFAS_FMASTER_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRIOMMU_AHBFAS_FMASTER_MASK ) | \ ( ( ( _val ) << GRIOMMU_AHBFAS_FMASTER_SHIFT ) & \ GRIOMMU_AHBFAS_FMASTER_MASK ) ) -#define GRIOMMU_AHBFAS_FMASTER( _val ) \ +#define GRIOMMU_AHBFAS_FMASTER( _val ) \ ( ( ( _val ) << GRIOMMU_AHBFAS_FMASTER_SHIFT ) & \ GRIOMMU_AHBFAS_FMASTER_MASK ) @@ -519,45 +464,39 @@ extern "C" { */ #define GRIOMMU_MSTCFG_VENDOR_SHIFT 24 -#define GRIOMMU_MSTCFG_VENDOR_MASK 0xff000000U +#define GRIOMMU_MSTCFG_VENDOR_MASK 0xff000000U #define GRIOMMU_MSTCFG_VENDOR_GET( _reg ) \ - ( ( ( _reg ) & GRIOMMU_MSTCFG_VENDOR_MASK ) >> \ - GRIOMMU_MSTCFG_VENDOR_SHIFT ) -#define GRIOMMU_MSTCFG_VENDOR_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRIOMMU_MSTCFG_VENDOR_MASK ) | \ + ( ( ( _reg ) & GRIOMMU_MSTCFG_VENDOR_MASK ) >> GRIOMMU_MSTCFG_VENDOR_SHIFT ) +#define GRIOMMU_MSTCFG_VENDOR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRIOMMU_MSTCFG_VENDOR_MASK ) | \ ( ( ( _val ) << GRIOMMU_MSTCFG_VENDOR_SHIFT ) & \ GRIOMMU_MSTCFG_VENDOR_MASK ) ) #define GRIOMMU_MSTCFG_VENDOR( _val ) \ - ( ( ( _val ) << GRIOMMU_MSTCFG_VENDOR_SHIFT ) & \ - GRIOMMU_MSTCFG_VENDOR_MASK ) + ( ( ( _val ) << GRIOMMU_MSTCFG_VENDOR_SHIFT ) & GRIOMMU_MSTCFG_VENDOR_MASK ) #define GRIOMMU_MSTCFG_DEVICE_SHIFT 12 -#define GRIOMMU_MSTCFG_DEVICE_MASK 0xfff000U +#define GRIOMMU_MSTCFG_DEVICE_MASK 0xfff000U #define GRIOMMU_MSTCFG_DEVICE_GET( _reg ) \ - ( ( ( _reg ) & GRIOMMU_MSTCFG_DEVICE_MASK ) >> \ - GRIOMMU_MSTCFG_DEVICE_SHIFT ) -#define GRIOMMU_MSTCFG_DEVICE_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRIOMMU_MSTCFG_DEVICE_MASK ) | \ + ( ( ( _reg ) & GRIOMMU_MSTCFG_DEVICE_MASK ) >> GRIOMMU_MSTCFG_DEVICE_SHIFT ) +#define GRIOMMU_MSTCFG_DEVICE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRIOMMU_MSTCFG_DEVICE_MASK ) | \ ( ( ( _val ) << GRIOMMU_MSTCFG_DEVICE_SHIFT ) & \ GRIOMMU_MSTCFG_DEVICE_MASK ) ) #define GRIOMMU_MSTCFG_DEVICE( _val ) \ - ( ( ( _val ) << GRIOMMU_MSTCFG_DEVICE_SHIFT ) & \ - GRIOMMU_MSTCFG_DEVICE_MASK ) + ( ( ( _val ) << GRIOMMU_MSTCFG_DEVICE_SHIFT ) & GRIOMMU_MSTCFG_DEVICE_MASK ) #define GRIOMMU_MSTCFG_BS 0x10U #define GRIOMMU_MSTCFG_GROUP_SHIFT 0 -#define GRIOMMU_MSTCFG_GROUP_MASK 0xfU +#define GRIOMMU_MSTCFG_GROUP_MASK 0xfU #define GRIOMMU_MSTCFG_GROUP_GET( _reg ) \ - ( ( ( _reg ) & GRIOMMU_MSTCFG_GROUP_MASK ) >> \ - GRIOMMU_MSTCFG_GROUP_SHIFT ) -#define GRIOMMU_MSTCFG_GROUP_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRIOMMU_MSTCFG_GROUP_MASK ) | \ + ( ( ( _reg ) & GRIOMMU_MSTCFG_GROUP_MASK ) >> GRIOMMU_MSTCFG_GROUP_SHIFT ) +#define GRIOMMU_MSTCFG_GROUP_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRIOMMU_MSTCFG_GROUP_MASK ) | \ ( ( ( _val ) << GRIOMMU_MSTCFG_GROUP_SHIFT ) & \ GRIOMMU_MSTCFG_GROUP_MASK ) ) #define GRIOMMU_MSTCFG_GROUP( _val ) \ - ( ( ( _val ) << GRIOMMU_MSTCFG_GROUP_SHIFT ) & \ - GRIOMMU_MSTCFG_GROUP_MASK ) + ( ( ( _val ) << GRIOMMU_MSTCFG_GROUP_SHIFT ) & GRIOMMU_MSTCFG_GROUP_MASK ) /** @} */ @@ -570,15 +509,15 @@ extern "C" { */ #define GRIOMMU_GRPCTRL_BASE_31_4_SHIFT 4 -#define GRIOMMU_GRPCTRL_BASE_31_4_MASK 0xfffffff0U -#define GRIOMMU_GRPCTRL_BASE_31_4_GET( _reg ) \ +#define GRIOMMU_GRPCTRL_BASE_31_4_MASK 0xfffffff0U +#define GRIOMMU_GRPCTRL_BASE_31_4_GET( _reg ) \ ( ( ( _reg ) & GRIOMMU_GRPCTRL_BASE_31_4_MASK ) >> \ GRIOMMU_GRPCTRL_BASE_31_4_SHIFT ) -#define GRIOMMU_GRPCTRL_BASE_31_4_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRIOMMU_GRPCTRL_BASE_31_4_MASK ) | \ +#define GRIOMMU_GRPCTRL_BASE_31_4_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRIOMMU_GRPCTRL_BASE_31_4_MASK ) | \ ( ( ( _val ) << GRIOMMU_GRPCTRL_BASE_31_4_SHIFT ) & \ GRIOMMU_GRPCTRL_BASE_31_4_MASK ) ) -#define GRIOMMU_GRPCTRL_BASE_31_4( _val ) \ +#define GRIOMMU_GRPCTRL_BASE_31_4( _val ) \ ( ( ( _val ) << GRIOMMU_GRPCTRL_BASE_31_4_SHIFT ) & \ GRIOMMU_GRPCTRL_BASE_31_4_MASK ) @@ -606,15 +545,15 @@ extern "C" { #define GRIOMMU_DIAGCTRL_TP 0x100000U #define GRIOMMU_DIAGCTRL_SETADDR_SHIFT 0 -#define GRIOMMU_DIAGCTRL_SETADDR_MASK 0x7ffffU -#define GRIOMMU_DIAGCTRL_SETADDR_GET( _reg ) \ +#define GRIOMMU_DIAGCTRL_SETADDR_MASK 0x7ffffU +#define GRIOMMU_DIAGCTRL_SETADDR_GET( _reg ) \ ( ( ( _reg ) & GRIOMMU_DIAGCTRL_SETADDR_MASK ) >> \ GRIOMMU_DIAGCTRL_SETADDR_SHIFT ) -#define GRIOMMU_DIAGCTRL_SETADDR_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRIOMMU_DIAGCTRL_SETADDR_MASK ) | \ +#define GRIOMMU_DIAGCTRL_SETADDR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRIOMMU_DIAGCTRL_SETADDR_MASK ) | \ ( ( ( _val ) << GRIOMMU_DIAGCTRL_SETADDR_SHIFT ) & \ GRIOMMU_DIAGCTRL_SETADDR_MASK ) ) -#define GRIOMMU_DIAGCTRL_SETADDR( _val ) \ +#define GRIOMMU_DIAGCTRL_SETADDR( _val ) \ ( ( ( _val ) << GRIOMMU_DIAGCTRL_SETADDR_SHIFT ) & \ GRIOMMU_DIAGCTRL_SETADDR_MASK ) @@ -630,17 +569,15 @@ extern "C" { */ #define GRIOMMU_DIAGD_CDATAN_SHIFT 0 -#define GRIOMMU_DIAGD_CDATAN_MASK 0xffffffffU +#define GRIOMMU_DIAGD_CDATAN_MASK 0xffffffffU #define GRIOMMU_DIAGD_CDATAN_GET( _reg ) \ - ( ( ( _reg ) & GRIOMMU_DIAGD_CDATAN_MASK ) >> \ - GRIOMMU_DIAGD_CDATAN_SHIFT ) -#define GRIOMMU_DIAGD_CDATAN_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRIOMMU_DIAGD_CDATAN_MASK ) | \ + ( ( ( _reg ) & GRIOMMU_DIAGD_CDATAN_MASK ) >> GRIOMMU_DIAGD_CDATAN_SHIFT ) +#define GRIOMMU_DIAGD_CDATAN_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRIOMMU_DIAGD_CDATAN_MASK ) | \ ( ( ( _val ) << GRIOMMU_DIAGD_CDATAN_SHIFT ) & \ GRIOMMU_DIAGD_CDATAN_MASK ) ) #define GRIOMMU_DIAGD_CDATAN( _val ) \ - ( ( ( _val ) << GRIOMMU_DIAGD_CDATAN_SHIFT ) & \ - GRIOMMU_DIAGD_CDATAN_MASK ) + ( ( ( _val ) << GRIOMMU_DIAGD_CDATAN_SHIFT ) & GRIOMMU_DIAGD_CDATAN_MASK ) /** @} */ @@ -654,17 +591,14 @@ extern "C" { */ #define GRIOMMU_DIAGT_TAG_SHIFT 1 -#define GRIOMMU_DIAGT_TAG_MASK 0xfffffffeU +#define GRIOMMU_DIAGT_TAG_MASK 0xfffffffeU #define GRIOMMU_DIAGT_TAG_GET( _reg ) \ - ( ( ( _reg ) & GRIOMMU_DIAGT_TAG_MASK ) >> \ - GRIOMMU_DIAGT_TAG_SHIFT ) -#define GRIOMMU_DIAGT_TAG_SET( _reg, _val ) \ + ( ( ( _reg ) & GRIOMMU_DIAGT_TAG_MASK ) >> GRIOMMU_DIAGT_TAG_SHIFT ) +#define GRIOMMU_DIAGT_TAG_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRIOMMU_DIAGT_TAG_MASK ) | \ - ( ( ( _val ) << GRIOMMU_DIAGT_TAG_SHIFT ) & \ - GRIOMMU_DIAGT_TAG_MASK ) ) + ( ( ( _val ) << GRIOMMU_DIAGT_TAG_SHIFT ) & GRIOMMU_DIAGT_TAG_MASK ) ) #define GRIOMMU_DIAGT_TAG( _val ) \ - ( ( ( _val ) << GRIOMMU_DIAGT_TAG_SHIFT ) & \ - GRIOMMU_DIAGT_TAG_MASK ) + ( ( ( _val ) << GRIOMMU_DIAGT_TAG_SHIFT ) & GRIOMMU_DIAGT_TAG_MASK ) #define GRIOMMU_DIAGT_V 0x1U @@ -679,15 +613,15 @@ extern "C" { */ #define GRIOMMU_DERRI_DPERRINJ_SHIFT 0 -#define GRIOMMU_DERRI_DPERRINJ_MASK 0xffffffffU -#define GRIOMMU_DERRI_DPERRINJ_GET( _reg ) \ +#define GRIOMMU_DERRI_DPERRINJ_MASK 0xffffffffU +#define GRIOMMU_DERRI_DPERRINJ_GET( _reg ) \ ( ( ( _reg ) & GRIOMMU_DERRI_DPERRINJ_MASK ) >> \ GRIOMMU_DERRI_DPERRINJ_SHIFT ) -#define GRIOMMU_DERRI_DPERRINJ_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRIOMMU_DERRI_DPERRINJ_MASK ) | \ +#define GRIOMMU_DERRI_DPERRINJ_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRIOMMU_DERRI_DPERRINJ_MASK ) | \ ( ( ( _val ) << GRIOMMU_DERRI_DPERRINJ_SHIFT ) & \ GRIOMMU_DERRI_DPERRINJ_MASK ) ) -#define GRIOMMU_DERRI_DPERRINJ( _val ) \ +#define GRIOMMU_DERRI_DPERRINJ( _val ) \ ( ( ( _val ) << GRIOMMU_DERRI_DPERRINJ_SHIFT ) & \ GRIOMMU_DERRI_DPERRINJ_MASK ) @@ -702,15 +636,15 @@ extern "C" { */ #define GRIOMMU_TERRI_TPERRINJ_SHIFT 0 -#define GRIOMMU_TERRI_TPERRINJ_MASK 0xffffffffU -#define GRIOMMU_TERRI_TPERRINJ_GET( _reg ) \ +#define GRIOMMU_TERRI_TPERRINJ_MASK 0xffffffffU +#define GRIOMMU_TERRI_TPERRINJ_GET( _reg ) \ ( ( ( _reg ) & GRIOMMU_TERRI_TPERRINJ_MASK ) >> \ GRIOMMU_TERRI_TPERRINJ_SHIFT ) -#define GRIOMMU_TERRI_TPERRINJ_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRIOMMU_TERRI_TPERRINJ_MASK ) | \ +#define GRIOMMU_TERRI_TPERRINJ_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRIOMMU_TERRI_TPERRINJ_MASK ) | \ ( ( ( _val ) << GRIOMMU_TERRI_TPERRINJ_SHIFT ) & \ GRIOMMU_TERRI_TPERRINJ_MASK ) ) -#define GRIOMMU_TERRI_TPERRINJ( _val ) \ +#define GRIOMMU_TERRI_TPERRINJ( _val ) \ ( ( ( _val ) << GRIOMMU_TERRI_TPERRINJ_SHIFT ) & \ GRIOMMU_TERRI_TPERRINJ_MASK ) @@ -732,15 +666,15 @@ extern "C" { #define GRIOMMU_ASMPCTRL_MC 0x10000U #define GRIOMMU_ASMPCTRL_GRPACCSZCTRL_SHIFT 0 -#define GRIOMMU_ASMPCTRL_GRPACCSZCTRL_MASK 0xffffU -#define GRIOMMU_ASMPCTRL_GRPACCSZCTRL_GET( _reg ) \ +#define GRIOMMU_ASMPCTRL_GRPACCSZCTRL_MASK 0xffffU +#define GRIOMMU_ASMPCTRL_GRPACCSZCTRL_GET( _reg ) \ ( ( ( _reg ) & GRIOMMU_ASMPCTRL_GRPACCSZCTRL_MASK ) >> \ GRIOMMU_ASMPCTRL_GRPACCSZCTRL_SHIFT ) -#define GRIOMMU_ASMPCTRL_GRPACCSZCTRL_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRIOMMU_ASMPCTRL_GRPACCSZCTRL_MASK ) | \ +#define GRIOMMU_ASMPCTRL_GRPACCSZCTRL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRIOMMU_ASMPCTRL_GRPACCSZCTRL_MASK ) | \ ( ( ( _val ) << GRIOMMU_ASMPCTRL_GRPACCSZCTRL_SHIFT ) & \ GRIOMMU_ASMPCTRL_GRPACCSZCTRL_MASK ) ) -#define GRIOMMU_ASMPCTRL_GRPACCSZCTRL( _val ) \ +#define GRIOMMU_ASMPCTRL_GRPACCSZCTRL( _val ) \ ( ( ( _val ) << GRIOMMU_ASMPCTRL_GRPACCSZCTRL_SHIFT ) & \ GRIOMMU_ASMPCTRL_GRPACCSZCTRL_MASK ) diff --git a/bsps/include/grlib/griommu.h b/bsps/include/grlib/griommu.h index c2f077d025..2af78b1752 100644 --- a/bsps/include/grlib/griommu.h +++ b/bsps/include/grlib/griommu.h @@ -43,13 +43,13 @@ extern "C" { #endif -extern void griommu_register_drv(void); +extern void griommu_register_drv( void ); -#define GRIOMMU_ERR_OK 0 -#define GRIOMMU_ERR_NOINIT -1 -#define GRIOMMU_ERR_EINVAL -2 +#define GRIOMMU_ERR_OK 0 +#define GRIOMMU_ERR_NOINIT -1 +#define GRIOMMU_ERR_EINVAL -2 #define GRIOMMU_ERR_IMPLEMENTED -3 -#define GRIOMMU_ERR_NOTFOUND -4 +#define GRIOMMU_ERR_NOTFOUND -4 /* Size of APV (has to be divided by page size in bytes) */ #define GRIOMMU_APV_SIZE 0x20000000 @@ -58,8 +58,8 @@ extern void griommu_register_drv(void); #define GRIOMMU_APV_ALIGN 0x10 /* IOMMU APV allocation helper functions */ -extern void * griommu_apv_new(void); -extern void griommu_apv_delete(void * apv); +extern void *griommu_apv_new( void ); +extern void griommu_apv_delete( void *apv ); /* IOMMU Master Setup */ @@ -67,115 +67,127 @@ extern void griommu_apv_delete(void * apv); /* * GRIOMMU MASTER register fields */ -#define MASTER_VENDOR (0xff << MASTER_VENDOR_BIT) -#define MASTER_DEVICE (0xfff << MASTER_DEVICE_BIT) -#define MASTER_BS (0x1 << MASTER_BS_BIT) -#define MASTER_GROUP (0xf << MASTER_GROUP_BIT) +#define MASTER_VENDOR ( 0xff << MASTER_VENDOR_BIT ) +#define MASTER_DEVICE ( 0xfff << MASTER_DEVICE_BIT ) +#define MASTER_BS ( 0x1 << MASTER_BS_BIT ) +#define MASTER_GROUP ( 0xf << MASTER_GROUP_BIT ) #define MASTER_VENDOR_BIT 24 #define MASTER_DEVICE_BIT 12 -#define MASTER_BS_BIT 4 -#define MASTER_GROUP_BIT 0 +#define MASTER_BS_BIT 4 +#define MASTER_GROUP_BIT 0 #define GRIOMMU_OPTIONS_BUS0 0 #define GRIOMMU_OPTIONS_BUS1 1 -extern int griommu_master_setup(int master, int group, int options); -extern int griommu_master_find(int vendor, int device, int instance); -extern int griommu_master_info(int master, uint32_t * info); -#define griommu_get_master_vendor(info) \ - ((info & MASTER_VENDOR) >> MASTER_VENDOR_BIT) -#define griommu_get_master_device(info) \ - ((info & MASTER_DEVICE) >> MASTER_DEVICE_BIT) -#define griommu_get_master_routing(info) \ - ((info & MASTER_BS) >> MASTER_BS_BIT) -#define griommu_get_master_group(info) \ - ((info & MASTER_GROUP) >> MASTER_GROUP_BIT) +extern int griommu_master_setup( int master, int group, int options ); +extern int griommu_master_find( int vendor, int device, int instance ); +extern int griommu_master_info( int master, uint32_t *info ); +#define griommu_get_master_vendor( info ) \ + ( ( info & MASTER_VENDOR ) >> MASTER_VENDOR_BIT ) +#define griommu_get_master_device( info ) \ + ( ( info & MASTER_DEVICE ) >> MASTER_DEVICE_BIT ) +#define griommu_get_master_routing( info ) \ + ( ( info & MASTER_BS ) >> MASTER_BS_BIT ) +#define griommu_get_master_group( info ) \ + ( ( info & MASTER_GROUP ) >> MASTER_GROUP_BIT ) /* IOMMU Group Setup */ #define GRIOMMU_OPTIONS_GROUP_PASSTHROUGH 2 -#define GRIOMMU_OPTIONS_GROUP_ENABLE 1 -#define GRIOMMU_OPTIONS_GROUP_DISABLE 0 -extern int griommu_group_setup(int group, void * apv, int options); -extern int griommu_group_info(int group, uint32_t * info); -#define GRIOMMU_OPTIONS_APV_ALLOW 0x1 +#define GRIOMMU_OPTIONS_GROUP_ENABLE 1 +#define GRIOMMU_OPTIONS_GROUP_DISABLE 0 +extern int griommu_group_setup( int group, void *apv, int options ); +extern int griommu_group_info( int group, uint32_t *info ); +#define GRIOMMU_OPTIONS_APV_ALLOW 0x1 #define GRIOMMU_OPTIONS_APV_DONTALLOW 0x0 -extern int griommu_group_apv_init(int group, int options); -extern int griommu_group_apv_address_set(int group, uint32_t addr, int size, - int options); -extern int griommu_group_apv_page_set(int group, int index, int size, - int options); -extern int griommu_group_apv_flush(int group); +extern int griommu_group_apv_init( int group, int options ); +extern int griommu_group_apv_address_set( + int group, + uint32_t addr, + int size, + int options +); +extern int griommu_group_apv_page_set( + int group, + int index, + int size, + int options +); +extern int griommu_group_apv_flush( int group ); /* IOMMU Setup */ /* * GRIOMMU CTRL register fields */ -#define CTRL_PGSZ (0x7 << CTRL_PGSZ_BIT) -#define CTRL_LB (0x1 << CTRL_LB_BIT) -#define CTRL_SP (0x1 << CTRL_SP_BIT) -#define CTRL_ITR (0xf << CTRL_ITR_BIT) -#define CTRL_DP (0x1 << CTRL_DP_BIT) -#define CTRL_SIV (0x1 << CTRL_SIV_BIT) -#define CTRL_HPROT (0x3 << CTRL_HPROT_BIT) -#define CTRL_AU (0x1 << CTRL_AU_BIT) -#define CTRL_WP (0x1 << CTRL_WP_BIT) -#define CTRL_DM (0x1 << CTRL_DM_BIT) -#define CTRL_GS (0x1 << CTRL_GS_BIT) -#define CTRL_CE (0x1 << CTRL_CE_BIT) -#define CTRL_PM (0x3 << CTRL_PM_BIT) -#define CTRL_PM_APV (0x0 << CTRL_PM_BIT) -#define CTRL_PM_IOMMU (0x1 << CTRL_PM_BIT) -#define CTRL_EN (0x1 << CTRL_EN_BIT) +#define CTRL_PGSZ ( 0x7 << CTRL_PGSZ_BIT ) +#define CTRL_LB ( 0x1 << CTRL_LB_BIT ) +#define CTRL_SP ( 0x1 << CTRL_SP_BIT ) +#define CTRL_ITR ( 0xf << CTRL_ITR_BIT ) +#define CTRL_DP ( 0x1 << CTRL_DP_BIT ) +#define CTRL_SIV ( 0x1 << CTRL_SIV_BIT ) +#define CTRL_HPROT ( 0x3 << CTRL_HPROT_BIT ) +#define CTRL_AU ( 0x1 << CTRL_AU_BIT ) +#define CTRL_WP ( 0x1 << CTRL_WP_BIT ) +#define CTRL_DM ( 0x1 << CTRL_DM_BIT ) +#define CTRL_GS ( 0x1 << CTRL_GS_BIT ) +#define CTRL_CE ( 0x1 << CTRL_CE_BIT ) +#define CTRL_PM ( 0x3 << CTRL_PM_BIT ) +#define CTRL_PM_APV ( 0x0 << CTRL_PM_BIT ) +#define CTRL_PM_IOMMU ( 0x1 << CTRL_PM_BIT ) +#define CTRL_EN ( 0x1 << CTRL_EN_BIT ) -#define CTRL_PGSZ_BIT 18 -#define CTRL_LB_BIT 17 -#define CTRL_SP_BIT 16 -#define CTRL_ITR_BIT 12 -#define CTRL_DP_BIT 11 -#define CTRL_SIV_BIT 10 +#define CTRL_PGSZ_BIT 18 +#define CTRL_LB_BIT 17 +#define CTRL_SP_BIT 16 +#define CTRL_ITR_BIT 12 +#define CTRL_DP_BIT 11 +#define CTRL_SIV_BIT 10 #define CTRL_HPROT_BIT 8 -#define CTRL_AU_BIT 7 -#define CTRL_WP_BIT 6 -#define CTRL_DM_BIT 5 -#define CTRL_GS_BIT 4 -#define CTRL_CE_BIT 3 -#define CTRL_PM_BIT 1 -#define CTRL_EN_BIT 0 +#define CTRL_AU_BIT 7 +#define CTRL_WP_BIT 6 +#define CTRL_DM_BIT 5 +#define CTRL_GS_BIT 4 +#define CTRL_CE_BIT 3 +#define CTRL_PM_BIT 1 +#define CTRL_EN_BIT 0 -#define GRIOMMU_OPTIONS_LOOKUPBUS_BUS0 0 -#define GRIOMMU_OPTIONS_LOOKUPBUS_BUS1 CTRL_LB -#define GRIOMMU_OPTIONS_CACHE_DISABLE 0 -#define GRIOMMU_OPTIONS_CACHE_ENABLE CTRL_CE +#define GRIOMMU_OPTIONS_LOOKUPBUS_BUS0 0 +#define GRIOMMU_OPTIONS_LOOKUPBUS_BUS1 CTRL_LB +#define GRIOMMU_OPTIONS_CACHE_DISABLE 0 +#define GRIOMMU_OPTIONS_CACHE_ENABLE CTRL_CE #define GRIOMMU_OPTIONS_GROUPADDRESSING_DISABLE 0 -#define GRIOMMU_OPTIONS_GROUPADDRESSING_ENABLE CTRL_GS -#define GRIOMMU_OPTIONS_WPROTONLY_DISABLE 0 -#define GRIOMMU_OPTIONS_WPROTONLY_ENABLE CTRL_WP -#define GRIOMMU_OPTIONS_AHBUPDATE_DISABLE 0 -#define GRIOMMU_OPTIONS_AHBUPDATE_ENABLE CTRL_AU -#define GRIOMMU_OPTIONS_PREFETCH_DISABLE CTRL_DP -#define GRIOMMU_OPTIONS_PREFETCH_ENABLE 0 -#define GRIOMMU_OPTIONS_PAGESIZE_4KIB 0 -#define GRIOMMU_OPTIONS_PAGESIZE_8KIB (0x1 << CTRL_PGSZ_BIT) -#define GRIOMMU_OPTIONS_PAGESIZE_16KIB (0x2 << CTRL_PGSZ_BIT) -#define GRIOMMU_OPTIONS_PAGESIZE_32KIB (0x3 << CTRL_PGSZ_BIT) -#define GRIOMMU_OPTIONS_PAGESIZE_64KIB (0x4 << CTRL_PGSZ_BIT) -#define GRIOMMU_OPTIONS_PAGESIZE_128KIB (0x5 << CTRL_PGSZ_BIT) -#define GRIOMMU_OPTIONS_PAGESIZE_256KIB (0x6 << CTRL_PGSZ_BIT) -#define GRIOMMU_OPTIONS_PAGESIZE_512KIB (0x7 << CTRL_PGSZ_BIT) -extern int griommu_setup(int options); -extern int griommu_status(void); +#define GRIOMMU_OPTIONS_GROUPADDRESSING_ENABLE CTRL_GS +#define GRIOMMU_OPTIONS_WPROTONLY_DISABLE 0 +#define GRIOMMU_OPTIONS_WPROTONLY_ENABLE CTRL_WP +#define GRIOMMU_OPTIONS_AHBUPDATE_DISABLE 0 +#define GRIOMMU_OPTIONS_AHBUPDATE_ENABLE CTRL_AU +#define GRIOMMU_OPTIONS_PREFETCH_DISABLE CTRL_DP +#define GRIOMMU_OPTIONS_PREFETCH_ENABLE 0 +#define GRIOMMU_OPTIONS_PAGESIZE_4KIB 0 +#define GRIOMMU_OPTIONS_PAGESIZE_8KIB ( 0x1 << CTRL_PGSZ_BIT ) +#define GRIOMMU_OPTIONS_PAGESIZE_16KIB ( 0x2 << CTRL_PGSZ_BIT ) +#define GRIOMMU_OPTIONS_PAGESIZE_32KIB ( 0x3 << CTRL_PGSZ_BIT ) +#define GRIOMMU_OPTIONS_PAGESIZE_64KIB ( 0x4 << CTRL_PGSZ_BIT ) +#define GRIOMMU_OPTIONS_PAGESIZE_128KIB ( 0x5 << CTRL_PGSZ_BIT ) +#define GRIOMMU_OPTIONS_PAGESIZE_256KIB ( 0x6 << CTRL_PGSZ_BIT ) +#define GRIOMMU_OPTIONS_PAGESIZE_512KIB ( 0x7 << CTRL_PGSZ_BIT ) +extern int griommu_setup( int options ); +extern int griommu_status( void ); -#define GRIOMMU_MODE_IOMMU 1 +#define GRIOMMU_MODE_IOMMU 1 #define GRIOMMU_MODE_GROUPAPV 0 -extern int griommu_enable(int mode); -extern int griommu_disable(void); +extern int griommu_enable( int mode ); +extern int griommu_disable( void ); /* IOMMU APV setup */ -extern int griommu_apv_flush(void); -extern int griommu_apv_init(void * apv, int options); -extern int griommu_apv_address_set(void * apv, uint32_t addr, int size, - int options); -extern int griommu_apv_page_set(void * apv, int index, int size, int options); +extern int griommu_apv_flush( void ); +extern int griommu_apv_init( void *apv, int options ); +extern int griommu_apv_address_set( + void *apv, + uint32_t addr, + int size, + int options +); +extern int griommu_apv_page_set( void *apv, int index, int size, int options ); /* GRIOMMU Interrupts */ /* Function Interrupt-Code ISR callback prototype. @@ -183,21 +195,21 @@ extern int griommu_apv_page_set(void * apv, int index, int size, int options); * access - AHB Access that failed * status - Error status register of the GRIOMMU core */ -typedef void (*griommu_isr_t)(void *arg, uint32_t access, uint32_t status); -#define GRIOMMU_INTERRUPT_ALL (0x2f << 0) -#define GRIOMMU_INTERRUPT_PARITY_ERROR (0x1 << 5) -#define GRIOMMU_INTERRUPT_FLUSH_COMPLETED (0x1 << 3) -#define GRIOMMU_INTERRUPT_FLUSH_START (0x1 << 2) -#define GRIOMMU_INTERRUPT_ACCESS_DENIED (0x1 << 1) -#define GRIOMMU_INTERRUPT_TRANSLATION_ERROR (0x1 << 0) -extern int griommu_isr_register(griommu_isr_t isr, void * arg, int options); -extern int griommu_isr_unregister(void); -extern int griommu_interrupt_unmask(int options); -extern int griommu_interrupt_mask(int options); +typedef void ( *griommu_isr_t )( void *arg, uint32_t access, uint32_t status ); +#define GRIOMMU_INTERRUPT_ALL ( 0x2f << 0 ) +#define GRIOMMU_INTERRUPT_PARITY_ERROR ( 0x1 << 5 ) +#define GRIOMMU_INTERRUPT_FLUSH_COMPLETED ( 0x1 << 3 ) +#define GRIOMMU_INTERRUPT_FLUSH_START ( 0x1 << 2 ) +#define GRIOMMU_INTERRUPT_ACCESS_DENIED ( 0x1 << 1 ) +#define GRIOMMU_INTERRUPT_TRANSLATION_ERROR ( 0x1 << 0 ) +extern int griommu_isr_register( griommu_isr_t isr, void *arg, int options ); +extern int griommu_isr_unregister( void ); +extern int griommu_interrupt_unmask( int options ); +extern int griommu_interrupt_mask( int options ); -extern int griommu_error_status(uint32_t * access); +extern int griommu_error_status( uint32_t *access ); -extern int griommu_print(void); +extern int griommu_print( void ); #ifdef __cplusplus } diff --git a/bsps/include/grlib/grlib.h b/bsps/include/grlib/grlib.h index 568ce9bdf1..450e6a62cb 100644 --- a/bsps/include/grlib/grlib.h +++ b/bsps/include/grlib/grlib.h @@ -67,47 +67,47 @@ struct apbuart_regs { /* IRQMP and IRQAMP interrupt controller timestamps */ struct irqmp_timestamp_regs { - volatile uint32_t counter; /* 0x00 */ - volatile uint32_t control; /* 0x04 */ - volatile uint32_t assertion; /* 0x08 */ - volatile uint32_t ack; /* 0x0c */ + volatile uint32_t counter; /* 0x00 */ + volatile uint32_t control; /* 0x04 */ + volatile uint32_t assertion; /* 0x08 */ + volatile uint32_t ack; /* 0x0c */ }; static inline bool irqmp_has_timestamp( volatile struct irqmp_timestamp_regs *irqmp_ts ) { - return (irqmp_ts->control >> 27) > 0; + return ( irqmp_ts->control >> 27 ) > 0; } /* IRQMP and IRQAMP interrupt controllers */ struct irqmp_regs { - volatile uint32_t ilevel; /* 0x00 */ - volatile uint32_t ipend; /* 0x04 */ - volatile uint32_t iforce; /* 0x08 */ - volatile uint32_t iclear; /* 0x0c */ - volatile uint32_t mpstat; /* 0x10 */ - volatile uint32_t bcast; /* 0x14 */ - volatile uint32_t notused02; /* 0x18 */ - volatile uint32_t wdgctrl; /* 0x1c */ - volatile uint32_t ampctrl; /* 0x20 */ - volatile uint32_t icsel[2]; /* 0x24,0x28 */ - volatile uint32_t notused13; /* 0x2c */ - volatile uint32_t notused20; /* 0x30 */ - volatile uint32_t notused21; /* 0x34 */ - volatile uint32_t notused22; /* 0x38 */ - volatile uint32_t notused23; /* 0x3c */ - volatile uint32_t mask[16]; /* 0x40 */ - volatile uint32_t force[16]; /* 0x80 */ + volatile uint32_t ilevel; /* 0x00 */ + volatile uint32_t ipend; /* 0x04 */ + volatile uint32_t iforce; /* 0x08 */ + volatile uint32_t iclear; /* 0x0c */ + volatile uint32_t mpstat; /* 0x10 */ + volatile uint32_t bcast; /* 0x14 */ + volatile uint32_t notused02; /* 0x18 */ + volatile uint32_t wdgctrl; /* 0x1c */ + volatile uint32_t ampctrl; /* 0x20 */ + volatile uint32_t icsel[ 2 ]; /* 0x24,0x28 */ + volatile uint32_t notused13; /* 0x2c */ + volatile uint32_t notused20; /* 0x30 */ + volatile uint32_t notused21; /* 0x34 */ + volatile uint32_t notused22; /* 0x38 */ + volatile uint32_t notused23; /* 0x3c */ + volatile uint32_t mask[ 16 ]; /* 0x40 */ + volatile uint32_t force[ 16 ]; /* 0x80 */ /* Extended IRQ registers */ - volatile uint32_t intid[16]; /* 0xc0 */ - volatile struct irqmp_timestamp_regs timestamp[16]; /* 0x100 */ - volatile uint32_t resetaddr[4]; /* 0x200 */ - volatile uint32_t resv0[12]; /* 0x210 - 0x23C */ - volatile uint32_t pboot; /* 0x240 */ - volatile uint32_t resv1[47]; /* 0x244 - 0x2FC */ - volatile uint32_t irqmap[8]; /* 0x300 - 0x31C */ - volatile uint32_t resv2[824]; /* 0x320 - 0x1000 */ + volatile uint32_t intid[ 16 ]; /* 0xc0 */ + volatile struct irqmp_timestamp_regs timestamp[ 16 ]; /* 0x100 */ + volatile uint32_t resetaddr[ 4 ]; /* 0x200 */ + volatile uint32_t resv0[ 12 ]; /* 0x210 - 0x23C */ + volatile uint32_t pboot; /* 0x240 */ + volatile uint32_t resv1[ 47 ]; /* 0x244 - 0x2FC */ + volatile uint32_t irqmap[ 8 ]; /* 0x300 - 0x31C */ + volatile uint32_t resv2[ 824 ]; /* 0x320 - 0x1000 */ }; /* GPTIMER Timer instance */ @@ -128,11 +128,11 @@ struct gptimer_timer_regs { /* GPTIMER common registers */ struct gptimer_regs { - volatile uint32_t scaler_value; /* common timer registers */ - volatile uint32_t scaler_reload; - volatile uint32_t cfg; - volatile uint32_t notused; - struct gptimer_timer_regs timer[7]; + volatile uint32_t scaler_value; /* common timer registers */ + volatile uint32_t scaler_reload; + volatile uint32_t cfg; + volatile uint32_t notused; + struct gptimer_timer_regs timer[ 7 ]; }; /* GRGPIO GPIO */ @@ -145,7 +145,7 @@ struct grgpio_regs { volatile uint32_t iedge; /* 0x14 Interrupt edge register */ volatile uint32_t bypass; /* 0x18 Bypass register */ volatile uint32_t cap; /* 0x1C Capability register */ - volatile uint32_t irqmap[4]; /* 0x20 - 0x2C Interrupt map registers */ + volatile uint32_t irqmap[ 4 ]; /* 0x20 - 0x2C Interrupt map registers */ volatile uint32_t res_30; /* 0x30 Reserved */ volatile uint32_t res_34; /* 0x34 Reserved */ volatile uint32_t res_38; /* 0x38 Reserved */ @@ -155,17 +155,21 @@ struct grgpio_regs { volatile uint32_t res_48; /* 0x48 Reserved */ volatile uint32_t pulse; /* 0x4C Pulse register */ volatile uint32_t res_50; /* 0x50 Reserved */ - volatile uint32_t output_or; /* 0x54 I/O port output register, logical-OR */ - volatile uint32_t dir_or; /* 0x58 I/O port direction register, logical-OR */ - volatile uint32_t imask_or; /* 0x5C Interrupt mask register, logical-OR */ - volatile uint32_t res_60; /* 0x60 Reserved */ - volatile uint32_t output_and; /* 0x64 I/O port output register, logical-AND */ - volatile uint32_t dir_and; /* 0x68 I/O port direction register, logical-AND */ - volatile uint32_t imask_and; /* 0x6C Interrupt mask register, logical-AND */ - volatile uint32_t res_70; /* 0x70 Reserved */ - volatile uint32_t output_xor; /* 0x74 I/O port output register, logical-XOR */ - volatile uint32_t dir_xor; /* 0x78 I/O port direction register, logical-XOR */ - volatile uint32_t imask_xor; /* 0x7C Interrupt mask register, logical-XOR */ + volatile uint32_t output_or; /* 0x54 I/O port output register, logical-OR */ + volatile uint32_t dir_or; /* 0x58 I/O port direction register, logical-OR */ + volatile uint32_t imask_or; /* 0x5C Interrupt mask register, logical-OR */ + volatile uint32_t res_60; /* 0x60 Reserved */ + volatile uint32_t + output_and; /* 0x64 I/O port output register, logical-AND */ + volatile uint32_t + dir_and; /* 0x68 I/O port direction register, logical-AND */ + volatile uint32_t imask_and; /* 0x6C Interrupt mask register, logical-AND */ + volatile uint32_t res_70; /* 0x70 Reserved */ + volatile uint32_t + output_xor; /* 0x74 I/O port output register, logical-XOR */ + volatile uint32_t + dir_xor; /* 0x78 I/O port direction register, logical-XOR */ + volatile uint32_t imask_xor; /* 0x7C Interrupt mask register, logical-XOR */ }; /* L2C - Level 2 Cache Controller registers */ @@ -186,12 +190,14 @@ struct l2c_regs { volatile uint32_t scrub_delay; /* 0x34 Scrub Delay */ volatile uint32_t error_injection; /* 0x38 Error injection */ volatile uint32_t access_control; /* 0x3c Access control */ - volatile uint32_t reserved_40[16]; /* 0x40 Reserved */ - volatile uint32_t mtrr[32]; /* 0x80 - 0xFC MTRR registers */ - volatile uint32_t reserved_100[131008]; /* 0x100 Reserved */ - volatile uint32_t diag_iface_tag[16384]; /* 0x80000 - 0x8FFFC Diagnostic interface (Tag) */ - volatile uint32_t reserved_90000[376832]; /* 0x90000 Reserved */ - volatile uint32_t diag_iface_data[524288];/* 0x200000 - 0x3FFFFC Diagnostic interface (Data) */ + volatile uint32_t reserved_40[ 16 ]; /* 0x40 Reserved */ + volatile uint32_t mtrr[ 32 ]; /* 0x80 - 0xFC MTRR registers */ + volatile uint32_t reserved_100[ 131008 ]; /* 0x100 Reserved */ + volatile uint32_t + diag_iface_tag[ 16384 ]; /* 0x80000 - 0x8FFFC Diagnostic interface (Tag) */ + volatile uint32_t reserved_90000[ 376832 ]; /* 0x90000 Reserved */ + volatile uint32_t diag_iface_data + [ 524288 ]; /* 0x200000 - 0x3FFFFC Diagnostic interface (Data) */ }; #ifdef __cplusplus diff --git a/bsps/include/grlib/grlib_impl.h b/bsps/include/grlib/grlib_impl.h index 3054cfd575..1b36d269f5 100644 --- a/bsps/include/grlib/grlib_impl.h +++ b/bsps/include/grlib/grlib_impl.h @@ -36,25 +36,32 @@ * Use interrupt lock primitives compatible with SMP defined in RTEMS 4.11.99 * and higher. */ -#if (((__RTEMS_MAJOR__ << 16) | (__RTEMS_MINOR__ << 8) | __RTEMS_REVISION__) >= 0x040b63) +#if ( \ + ( ( __RTEMS_MAJOR__ << 16 ) | ( __RTEMS_MINOR__ << 8 ) | \ + __RTEMS_REVISION__ ) >= 0x040b63 \ +) #include /* map via rtems_interrupt_lock_* API: */ -#define SPIN_DECLARE(lock) RTEMS_INTERRUPT_LOCK_MEMBER(lock) -#define SPIN_INIT(lock, name) rtems_interrupt_lock_initialize(lock, name) -#define SPIN_LOCK(lock, level) rtems_interrupt_lock_acquire_isr(lock, &level) -#define SPIN_LOCK_IRQ(lock, level) rtems_interrupt_lock_acquire(lock, &level) -#define SPIN_UNLOCK(lock, level) rtems_interrupt_lock_release_isr(lock, &level) -#define SPIN_UNLOCK_IRQ(lock, level) rtems_interrupt_lock_release(lock, &level) -#define SPIN_IRQFLAGS(k) rtems_interrupt_lock_context k -#define SPIN_ISR_IRQFLAGS(k) SPIN_IRQFLAGS(k) -#define SPIN_FREE(lock) rtems_interrupt_lock_destroy(lock) +#define SPIN_DECLARE( lock ) RTEMS_INTERRUPT_LOCK_MEMBER( lock ) +#define SPIN_INIT( lock, name ) rtems_interrupt_lock_initialize( lock, name ) +#define SPIN_LOCK( lock, level ) \ + rtems_interrupt_lock_acquire_isr( lock, &level ) +#define SPIN_LOCK_IRQ( lock, level ) \ + rtems_interrupt_lock_acquire( lock, &level ) +#define SPIN_UNLOCK( lock, level ) \ + rtems_interrupt_lock_release_isr( lock, &level ) +#define SPIN_UNLOCK_IRQ( lock, level ) \ + rtems_interrupt_lock_release( lock, &level ) +#define SPIN_IRQFLAGS( k ) rtems_interrupt_lock_context k +#define SPIN_ISR_IRQFLAGS( k ) SPIN_IRQFLAGS( k ) +#define SPIN_FREE( lock ) rtems_interrupt_lock_destroy( lock ) /* turn on/off local CPU's interrupt to ensure HW timing - not SMP safe. */ -#define IRQ_LOCAL_DECLARE(_level) rtems_interrupt_level _level -#define IRQ_LOCAL_DISABLE(_level) rtems_interrupt_local_disable(_level) -#define IRQ_LOCAL_ENABLE(_level) rtems_interrupt_local_enable(_level) +#define IRQ_LOCAL_DECLARE( _level ) rtems_interrupt_level _level +#define IRQ_LOCAL_DISABLE( _level ) rtems_interrupt_local_disable( _level ) +#define IRQ_LOCAL_ENABLE( _level ) rtems_interrupt_local_enable( _level ) #else @@ -63,20 +70,20 @@ #endif /* maintain single-core compatibility with older versions of RTEMS: */ -#define SPIN_DECLARE(name) -#define SPIN_INIT(lock, name) -#define SPIN_LOCK(lock, level) -#define SPIN_LOCK_IRQ(lock, level) rtems_interrupt_disable(level) -#define SPIN_UNLOCK(lock, level) -#define SPIN_UNLOCK_IRQ(lock, level) rtems_interrupt_enable(level) -#define SPIN_IRQFLAGS(k) rtems_interrupt_level k -#define SPIN_ISR_IRQFLAGS(k) -#define SPIN_FREE(lock) +#define SPIN_DECLARE( name ) +#define SPIN_INIT( lock, name ) +#define SPIN_LOCK( lock, level ) +#define SPIN_LOCK_IRQ( lock, level ) rtems_interrupt_disable( level ) +#define SPIN_UNLOCK( lock, level ) +#define SPIN_UNLOCK_IRQ( lock, level ) rtems_interrupt_enable( level ) +#define SPIN_IRQFLAGS( k ) rtems_interrupt_level k +#define SPIN_ISR_IRQFLAGS( k ) +#define SPIN_FREE( lock ) /* turn on/off local CPU's interrupt to ensure HW timing - not SMP safe. */ -#define IRQ_LOCAL_DECLARE(_level) rtems_interrupt_level _level -#define IRQ_LOCAL_DISABLE(_level) rtems_interrupt_disable(_level) -#define IRQ_LOCAL_ENABLE(_level) rtems_interrupt_enable(_level) +#define IRQ_LOCAL_DECLARE( _level ) rtems_interrupt_level _level +#define IRQ_LOCAL_DISABLE( _level ) rtems_interrupt_disable( _level ) +#define IRQ_LOCAL_ENABLE( _level ) rtems_interrupt_enable( _level ) #endif @@ -84,99 +91,99 @@ extern "C" { #endif -#if (((__RTEMS_MAJOR__ << 16) | (__RTEMS_MINOR__ << 8) | __RTEMS_REVISION__) >= 0x050000) +#if ( \ + ( ( __RTEMS_MAJOR__ << 16 ) | ( __RTEMS_MINOR__ << 8 ) | \ + __RTEMS_REVISION__ ) >= 0x050000 \ +) -static inline void *grlib_malloc(size_t size) +static inline void *grlib_malloc( size_t size ) { - return rtems_malloc(size); + return rtems_malloc( size ); } -static inline void *grlib_calloc(size_t nelem, size_t elsize) +static inline void *grlib_calloc( size_t nelem, size_t elsize ) { - return rtems_calloc(nelem, elsize); + return rtems_calloc( nelem, elsize ); } #else -static inline void *grlib_malloc(size_t size) +static inline void *grlib_malloc( size_t size ) { - return malloc(size); + return malloc( size ); } -static inline void *grlib_calloc(size_t nelem, size_t elsize) +static inline void *grlib_calloc( size_t nelem, size_t elsize ) { - return calloc(nelem, elsize); + return calloc( nelem, elsize ); } #endif #ifdef __sparc__ -static inline uint8_t grlib_read_uncached8(uintptr_t address) +static inline uint8_t grlib_read_uncached8( uintptr_t address ) { - uint8_t tmp; - __asm__ (" lduba [%1]1, %0 " - : "=r"(tmp) - : "r"(address) - ); - return tmp; + uint8_t tmp; + __asm__( " lduba [%1]1, %0 " + : "=r"( tmp ) + : "r"( address ) ); + return tmp; } -static inline uint16_t grlib_read_uncached16(uintptr_t addr) { - uint16_t tmp; - __asm__ (" lduha [%1]1, %0 " - : "=r"(tmp) - : "r"(addr) - ); - return tmp; +static inline uint16_t grlib_read_uncached16( uintptr_t addr ) +{ + uint16_t tmp; + __asm__( " lduha [%1]1, %0 " + : "=r"( tmp ) + : "r"( addr ) ); + return tmp; } - -static inline uint32_t grlib_read_uncached32(uintptr_t address) +static inline uint32_t grlib_read_uncached32( uintptr_t address ) { - uint32_t tmp; - __asm__ (" lda [%1]1, %0 " - : "=r"(tmp) - : "r"(address) - ); - return tmp; + uint32_t tmp; + __asm__( " lda [%1]1, %0 " + : "=r"( tmp ) + : "r"( address ) ); + return tmp; } -static inline uint64_t grlib_read_uncached64(uint64_t *address) +static inline uint64_t grlib_read_uncached64( uint64_t *address ) { - uint64_t tmp; - __asm__ (" ldda [%1]1, %0 " - : "=r"(tmp) - : "r"(address) - ); - return tmp; + uint64_t tmp; + __asm__( " ldda [%1]1, %0 " + : "=r"( tmp ) + : "r"( address ) ); + return tmp; } #define GRLIB_DMA_IS_CACHE_COHERENT CPU_SPARC_HAS_SNOOPING #else -static inline uint8_t grlib_read_uncached8(uintptr_t address) +static inline uint8_t grlib_read_uncached8( uintptr_t address ) { - uint8_t tmp = (*(volatile uint8_t *)(address)); - return tmp; + uint8_t tmp = ( *(volatile uint8_t *) ( address ) ); + return tmp; } -static inline uint16_t grlib_read_uncached16(uintptr_t address) { - uint16_t tmp = (*(volatile uint16_t *)(address)); - return tmp; +static inline uint16_t grlib_read_uncached16( uintptr_t address ) +{ + uint16_t tmp = ( *(volatile uint16_t *) ( address ) ); + return tmp; } -static inline uint32_t grlib_read_uncached32(uintptr_t address) +static inline uint32_t grlib_read_uncached32( uintptr_t address ) { - uint32_t tmp = (*(volatile uint32_t *)(address)); - return tmp; + uint32_t tmp = ( *(volatile uint32_t *) ( address ) ); + return tmp; } -static inline uint64_t grlib_read_uncached64(uintptr_t address) +static inline uint64_t grlib_read_uncached64( uintptr_t address ) { - uint64_t tmp = (*(volatile uint64_t *)(address)); - return tmp; + uint64_t tmp = ( *(volatile uint64_t *) ( address ) ); + return tmp; } #define GRLIB_DMA_IS_CACHE_COHERENT 1 diff --git a/bsps/include/grlib/grpci.h b/bsps/include/grlib/grpci.h index 5c05d0bdc4..7b4fba272d 100644 --- a/bsps/include/grlib/grpci.h +++ b/bsps/include/grlib/grpci.h @@ -35,23 +35,25 @@ extern "C" { #endif /* Register the GRPCI driver to the Driver Manager */ -extern void grpci_register_drv(void); +extern void grpci_register_drv( void ); /* Transfer data using GRPCI DMA unit from AMBA to PCI space. Blocks until * operation completes. */ int grpci_dma_to_pci( - unsigned int ahb_addr, - unsigned int pci_addr, - unsigned int len); + unsigned int ahb_addr, + unsigned int pci_addr, + unsigned int len +); /* Transfer data using GRPCI DMA unit from PCI to AMBA space. Blocks until * operation completes. */ int grpci_dma_from_pci( - unsigned int ahb_addr, - unsigned int pci_addr, - unsigned int len); + unsigned int ahb_addr, + unsigned int pci_addr, + unsigned int len +); #ifdef __cplusplus } diff --git a/bsps/include/grlib/grpci2-regs.h b/bsps/include/grlib/grpci2-regs.h index 380e24a4cf..e0eca676c2 100644 --- a/bsps/include/grlib/grpci2-regs.h +++ b/bsps/include/grlib/grpci2-regs.h @@ -96,15 +96,15 @@ extern "C" { #define GRPCI2_CTRL_EI 0x1000000U #define GRPCI2_CTRL_BUS_NUMBER_SHIFT 16 -#define GRPCI2_CTRL_BUS_NUMBER_MASK 0xff0000U -#define GRPCI2_CTRL_BUS_NUMBER_GET( _reg ) \ +#define GRPCI2_CTRL_BUS_NUMBER_MASK 0xff0000U +#define GRPCI2_CTRL_BUS_NUMBER_GET( _reg ) \ ( ( ( _reg ) & GRPCI2_CTRL_BUS_NUMBER_MASK ) >> \ GRPCI2_CTRL_BUS_NUMBER_SHIFT ) -#define GRPCI2_CTRL_BUS_NUMBER_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRPCI2_CTRL_BUS_NUMBER_MASK ) | \ +#define GRPCI2_CTRL_BUS_NUMBER_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_CTRL_BUS_NUMBER_MASK ) | \ ( ( ( _val ) << GRPCI2_CTRL_BUS_NUMBER_SHIFT ) & \ GRPCI2_CTRL_BUS_NUMBER_MASK ) ) -#define GRPCI2_CTRL_BUS_NUMBER( _val ) \ +#define GRPCI2_CTRL_BUS_NUMBER( _val ) \ ( ( ( _val ) << GRPCI2_CTRL_BUS_NUMBER_SHIFT ) & \ GRPCI2_CTRL_BUS_NUMBER_MASK ) @@ -117,28 +117,28 @@ extern "C" { #define GRPCI2_CTRL_DIF 0x100U #define GRPCI2_CTRL_DEVICE_INT_MASK_SHIFT 4 -#define GRPCI2_CTRL_DEVICE_INT_MASK_MASK 0xf0U -#define GRPCI2_CTRL_DEVICE_INT_MASK_GET( _reg ) \ +#define GRPCI2_CTRL_DEVICE_INT_MASK_MASK 0xf0U +#define GRPCI2_CTRL_DEVICE_INT_MASK_GET( _reg ) \ ( ( ( _reg ) & GRPCI2_CTRL_DEVICE_INT_MASK_MASK ) >> \ GRPCI2_CTRL_DEVICE_INT_MASK_SHIFT ) -#define GRPCI2_CTRL_DEVICE_INT_MASK_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRPCI2_CTRL_DEVICE_INT_MASK_MASK ) | \ +#define GRPCI2_CTRL_DEVICE_INT_MASK_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_CTRL_DEVICE_INT_MASK_MASK ) | \ ( ( ( _val ) << GRPCI2_CTRL_DEVICE_INT_MASK_SHIFT ) & \ GRPCI2_CTRL_DEVICE_INT_MASK_MASK ) ) -#define GRPCI2_CTRL_DEVICE_INT_MASK( _val ) \ +#define GRPCI2_CTRL_DEVICE_INT_MASK( _val ) \ ( ( ( _val ) << GRPCI2_CTRL_DEVICE_INT_MASK_SHIFT ) & \ GRPCI2_CTRL_DEVICE_INT_MASK_MASK ) #define GRPCI2_CTRL_HOST_INT_MASK_SHIFT 0 -#define GRPCI2_CTRL_HOST_INT_MASK_MASK 0xfU -#define GRPCI2_CTRL_HOST_INT_MASK_GET( _reg ) \ +#define GRPCI2_CTRL_HOST_INT_MASK_MASK 0xfU +#define GRPCI2_CTRL_HOST_INT_MASK_GET( _reg ) \ ( ( ( _reg ) & GRPCI2_CTRL_HOST_INT_MASK_MASK ) >> \ GRPCI2_CTRL_HOST_INT_MASK_SHIFT ) -#define GRPCI2_CTRL_HOST_INT_MASK_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRPCI2_CTRL_HOST_INT_MASK_MASK ) | \ +#define GRPCI2_CTRL_HOST_INT_MASK_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_CTRL_HOST_INT_MASK_MASK ) | \ ( ( ( _val ) << GRPCI2_CTRL_HOST_INT_MASK_SHIFT ) & \ GRPCI2_CTRL_HOST_INT_MASK_MASK ) ) -#define GRPCI2_CTRL_HOST_INT_MASK( _val ) \ +#define GRPCI2_CTRL_HOST_INT_MASK( _val ) \ ( ( ( _val ) << GRPCI2_CTRL_HOST_INT_MASK_SHIFT ) & \ GRPCI2_CTRL_HOST_INT_MASK_MASK ) @@ -165,15 +165,15 @@ extern "C" { #define GRPCI2_STATCAP_HI 0x4000000U #define GRPCI2_STATCAP_IRQ_MODE_SHIFT 24 -#define GRPCI2_STATCAP_IRQ_MODE_MASK 0x3000000U -#define GRPCI2_STATCAP_IRQ_MODE_GET( _reg ) \ +#define GRPCI2_STATCAP_IRQ_MODE_MASK 0x3000000U +#define GRPCI2_STATCAP_IRQ_MODE_GET( _reg ) \ ( ( ( _reg ) & GRPCI2_STATCAP_IRQ_MODE_MASK ) >> \ GRPCI2_STATCAP_IRQ_MODE_SHIFT ) -#define GRPCI2_STATCAP_IRQ_MODE_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRPCI2_STATCAP_IRQ_MODE_MASK ) | \ +#define GRPCI2_STATCAP_IRQ_MODE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_STATCAP_IRQ_MODE_MASK ) | \ ( ( ( _val ) << GRPCI2_STATCAP_IRQ_MODE_SHIFT ) & \ GRPCI2_STATCAP_IRQ_MODE_MASK ) ) -#define GRPCI2_STATCAP_IRQ_MODE( _val ) \ +#define GRPCI2_STATCAP_IRQ_MODE( _val ) \ ( ( ( _val ) << GRPCI2_STATCAP_IRQ_MODE_SHIFT ) & \ GRPCI2_STATCAP_IRQ_MODE_MASK ) @@ -184,56 +184,52 @@ extern "C" { #define GRPCI2_STATCAP_CFGER 0x80000U #define GRPCI2_STATCAP_CORE_INT_STATUS_SHIFT 12 -#define GRPCI2_STATCAP_CORE_INT_STATUS_MASK 0x7f000U -#define GRPCI2_STATCAP_CORE_INT_STATUS_GET( _reg ) \ +#define GRPCI2_STATCAP_CORE_INT_STATUS_MASK 0x7f000U +#define GRPCI2_STATCAP_CORE_INT_STATUS_GET( _reg ) \ ( ( ( _reg ) & GRPCI2_STATCAP_CORE_INT_STATUS_MASK ) >> \ GRPCI2_STATCAP_CORE_INT_STATUS_SHIFT ) -#define GRPCI2_STATCAP_CORE_INT_STATUS_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRPCI2_STATCAP_CORE_INT_STATUS_MASK ) | \ +#define GRPCI2_STATCAP_CORE_INT_STATUS_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_STATCAP_CORE_INT_STATUS_MASK ) | \ ( ( ( _val ) << GRPCI2_STATCAP_CORE_INT_STATUS_SHIFT ) & \ GRPCI2_STATCAP_CORE_INT_STATUS_MASK ) ) -#define GRPCI2_STATCAP_CORE_INT_STATUS( _val ) \ +#define GRPCI2_STATCAP_CORE_INT_STATUS( _val ) \ ( ( ( _val ) << GRPCI2_STATCAP_CORE_INT_STATUS_SHIFT ) & \ GRPCI2_STATCAP_CORE_INT_STATUS_MASK ) #define GRPCI2_STATCAP_HOST_INT_STATUS_SHIFT 8 -#define GRPCI2_STATCAP_HOST_INT_STATUS_MASK 0xf00U -#define GRPCI2_STATCAP_HOST_INT_STATUS_GET( _reg ) \ +#define GRPCI2_STATCAP_HOST_INT_STATUS_MASK 0xf00U +#define GRPCI2_STATCAP_HOST_INT_STATUS_GET( _reg ) \ ( ( ( _reg ) & GRPCI2_STATCAP_HOST_INT_STATUS_MASK ) >> \ GRPCI2_STATCAP_HOST_INT_STATUS_SHIFT ) -#define GRPCI2_STATCAP_HOST_INT_STATUS_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRPCI2_STATCAP_HOST_INT_STATUS_MASK ) | \ +#define GRPCI2_STATCAP_HOST_INT_STATUS_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_STATCAP_HOST_INT_STATUS_MASK ) | \ ( ( ( _val ) << GRPCI2_STATCAP_HOST_INT_STATUS_SHIFT ) & \ GRPCI2_STATCAP_HOST_INT_STATUS_MASK ) ) -#define GRPCI2_STATCAP_HOST_INT_STATUS( _val ) \ +#define GRPCI2_STATCAP_HOST_INT_STATUS( _val ) \ ( ( ( _val ) << GRPCI2_STATCAP_HOST_INT_STATUS_SHIFT ) & \ GRPCI2_STATCAP_HOST_INT_STATUS_MASK ) #define GRPCI2_STATCAP_FDEPTH_SHIFT 2 -#define GRPCI2_STATCAP_FDEPTH_MASK 0x1cU +#define GRPCI2_STATCAP_FDEPTH_MASK 0x1cU #define GRPCI2_STATCAP_FDEPTH_GET( _reg ) \ - ( ( ( _reg ) & GRPCI2_STATCAP_FDEPTH_MASK ) >> \ - GRPCI2_STATCAP_FDEPTH_SHIFT ) -#define GRPCI2_STATCAP_FDEPTH_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRPCI2_STATCAP_FDEPTH_MASK ) | \ + ( ( ( _reg ) & GRPCI2_STATCAP_FDEPTH_MASK ) >> GRPCI2_STATCAP_FDEPTH_SHIFT ) +#define GRPCI2_STATCAP_FDEPTH_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_STATCAP_FDEPTH_MASK ) | \ ( ( ( _val ) << GRPCI2_STATCAP_FDEPTH_SHIFT ) & \ GRPCI2_STATCAP_FDEPTH_MASK ) ) #define GRPCI2_STATCAP_FDEPTH( _val ) \ - ( ( ( _val ) << GRPCI2_STATCAP_FDEPTH_SHIFT ) & \ - GRPCI2_STATCAP_FDEPTH_MASK ) + ( ( ( _val ) << GRPCI2_STATCAP_FDEPTH_SHIFT ) & GRPCI2_STATCAP_FDEPTH_MASK ) #define GRPCI2_STATCAP_FNUM_SHIFT 0 -#define GRPCI2_STATCAP_FNUM_MASK 0x3U +#define GRPCI2_STATCAP_FNUM_MASK 0x3U #define GRPCI2_STATCAP_FNUM_GET( _reg ) \ - ( ( ( _reg ) & GRPCI2_STATCAP_FNUM_MASK ) >> \ - GRPCI2_STATCAP_FNUM_SHIFT ) -#define GRPCI2_STATCAP_FNUM_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRPCI2_STATCAP_FNUM_MASK ) | \ + ( ( ( _reg ) & GRPCI2_STATCAP_FNUM_MASK ) >> GRPCI2_STATCAP_FNUM_SHIFT ) +#define GRPCI2_STATCAP_FNUM_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_STATCAP_FNUM_MASK ) | \ ( ( ( _val ) << GRPCI2_STATCAP_FNUM_SHIFT ) & \ GRPCI2_STATCAP_FNUM_MASK ) ) #define GRPCI2_STATCAP_FNUM( _val ) \ - ( ( ( _val ) << GRPCI2_STATCAP_FNUM_SHIFT ) & \ - GRPCI2_STATCAP_FNUM_MASK ) + ( ( ( _val ) << GRPCI2_STATCAP_FNUM_SHIFT ) & GRPCI2_STATCAP_FNUM_MASK ) /** @} */ @@ -246,28 +242,28 @@ extern "C" { */ #define GRPCI2_BCIM_AHB_MASTER_UNMASK_SHIFT 16 -#define GRPCI2_BCIM_AHB_MASTER_UNMASK_MASK 0xffff0000U -#define GRPCI2_BCIM_AHB_MASTER_UNMASK_GET( _reg ) \ +#define GRPCI2_BCIM_AHB_MASTER_UNMASK_MASK 0xffff0000U +#define GRPCI2_BCIM_AHB_MASTER_UNMASK_GET( _reg ) \ ( ( ( _reg ) & GRPCI2_BCIM_AHB_MASTER_UNMASK_MASK ) >> \ GRPCI2_BCIM_AHB_MASTER_UNMASK_SHIFT ) -#define GRPCI2_BCIM_AHB_MASTER_UNMASK_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRPCI2_BCIM_AHB_MASTER_UNMASK_MASK ) | \ +#define GRPCI2_BCIM_AHB_MASTER_UNMASK_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_BCIM_AHB_MASTER_UNMASK_MASK ) | \ ( ( ( _val ) << GRPCI2_BCIM_AHB_MASTER_UNMASK_SHIFT ) & \ GRPCI2_BCIM_AHB_MASTER_UNMASK_MASK ) ) -#define GRPCI2_BCIM_AHB_MASTER_UNMASK( _val ) \ +#define GRPCI2_BCIM_AHB_MASTER_UNMASK( _val ) \ ( ( ( _val ) << GRPCI2_BCIM_AHB_MASTER_UNMASK_SHIFT ) & \ GRPCI2_BCIM_AHB_MASTER_UNMASK_MASK ) #define GRPCI2_BCIM_BURST_LENGTH_SHIFT 0 -#define GRPCI2_BCIM_BURST_LENGTH_MASK 0xffU -#define GRPCI2_BCIM_BURST_LENGTH_GET( _reg ) \ +#define GRPCI2_BCIM_BURST_LENGTH_MASK 0xffU +#define GRPCI2_BCIM_BURST_LENGTH_GET( _reg ) \ ( ( ( _reg ) & GRPCI2_BCIM_BURST_LENGTH_MASK ) >> \ GRPCI2_BCIM_BURST_LENGTH_SHIFT ) -#define GRPCI2_BCIM_BURST_LENGTH_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRPCI2_BCIM_BURST_LENGTH_MASK ) | \ +#define GRPCI2_BCIM_BURST_LENGTH_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_BCIM_BURST_LENGTH_MASK ) | \ ( ( ( _val ) << GRPCI2_BCIM_BURST_LENGTH_SHIFT ) & \ GRPCI2_BCIM_BURST_LENGTH_MASK ) ) -#define GRPCI2_BCIM_BURST_LENGTH( _val ) \ +#define GRPCI2_BCIM_BURST_LENGTH( _val ) \ ( ( ( _val ) << GRPCI2_BCIM_BURST_LENGTH_SHIFT ) & \ GRPCI2_BCIM_BURST_LENGTH_MASK ) @@ -282,15 +278,15 @@ extern "C" { */ #define GRPCI2_AHB2PCI_AHB_TO_PCI_IO_SHIFT 16 -#define GRPCI2_AHB2PCI_AHB_TO_PCI_IO_MASK 0xffff0000U -#define GRPCI2_AHB2PCI_AHB_TO_PCI_IO_GET( _reg ) \ +#define GRPCI2_AHB2PCI_AHB_TO_PCI_IO_MASK 0xffff0000U +#define GRPCI2_AHB2PCI_AHB_TO_PCI_IO_GET( _reg ) \ ( ( ( _reg ) & GRPCI2_AHB2PCI_AHB_TO_PCI_IO_MASK ) >> \ GRPCI2_AHB2PCI_AHB_TO_PCI_IO_SHIFT ) -#define GRPCI2_AHB2PCI_AHB_TO_PCI_IO_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRPCI2_AHB2PCI_AHB_TO_PCI_IO_MASK ) | \ +#define GRPCI2_AHB2PCI_AHB_TO_PCI_IO_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_AHB2PCI_AHB_TO_PCI_IO_MASK ) | \ ( ( ( _val ) << GRPCI2_AHB2PCI_AHB_TO_PCI_IO_SHIFT ) & \ GRPCI2_AHB2PCI_AHB_TO_PCI_IO_MASK ) ) -#define GRPCI2_AHB2PCI_AHB_TO_PCI_IO( _val ) \ +#define GRPCI2_AHB2PCI_AHB_TO_PCI_IO( _val ) \ ( ( ( _val ) << GRPCI2_AHB2PCI_AHB_TO_PCI_IO_SHIFT ) & \ GRPCI2_AHB2PCI_AHB_TO_PCI_IO_MASK ) @@ -307,17 +303,15 @@ extern "C" { #define GRPCI2_DMACTRL_SAFE 0x80000000U #define GRPCI2_DMACTRL_CHIRQ_SHIFT 12 -#define GRPCI2_DMACTRL_CHIRQ_MASK 0xff000U +#define GRPCI2_DMACTRL_CHIRQ_MASK 0xff000U #define GRPCI2_DMACTRL_CHIRQ_GET( _reg ) \ - ( ( ( _reg ) & GRPCI2_DMACTRL_CHIRQ_MASK ) >> \ - GRPCI2_DMACTRL_CHIRQ_SHIFT ) -#define GRPCI2_DMACTRL_CHIRQ_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRPCI2_DMACTRL_CHIRQ_MASK ) | \ + ( ( ( _reg ) & GRPCI2_DMACTRL_CHIRQ_MASK ) >> GRPCI2_DMACTRL_CHIRQ_SHIFT ) +#define GRPCI2_DMACTRL_CHIRQ_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_DMACTRL_CHIRQ_MASK ) | \ ( ( ( _val ) << GRPCI2_DMACTRL_CHIRQ_SHIFT ) & \ GRPCI2_DMACTRL_CHIRQ_MASK ) ) #define GRPCI2_DMACTRL_CHIRQ( _val ) \ - ( ( ( _val ) << GRPCI2_DMACTRL_CHIRQ_SHIFT ) & \ - GRPCI2_DMACTRL_CHIRQ_MASK ) + ( ( ( _val ) << GRPCI2_DMACTRL_CHIRQ_SHIFT ) & GRPCI2_DMACTRL_CHIRQ_MASK ) #define GRPCI2_DMACTRL_MA 0x800U @@ -330,17 +324,15 @@ extern "C" { #define GRPCI2_DMACTRL_DE 0x80U #define GRPCI2_DMACTRL_NUMCH_SHIFT 4 -#define GRPCI2_DMACTRL_NUMCH_MASK 0x70U +#define GRPCI2_DMACTRL_NUMCH_MASK 0x70U #define GRPCI2_DMACTRL_NUMCH_GET( _reg ) \ - ( ( ( _reg ) & GRPCI2_DMACTRL_NUMCH_MASK ) >> \ - GRPCI2_DMACTRL_NUMCH_SHIFT ) -#define GRPCI2_DMACTRL_NUMCH_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRPCI2_DMACTRL_NUMCH_MASK ) | \ + ( ( ( _reg ) & GRPCI2_DMACTRL_NUMCH_MASK ) >> GRPCI2_DMACTRL_NUMCH_SHIFT ) +#define GRPCI2_DMACTRL_NUMCH_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_DMACTRL_NUMCH_MASK ) | \ ( ( ( _val ) << GRPCI2_DMACTRL_NUMCH_SHIFT ) & \ GRPCI2_DMACTRL_NUMCH_MASK ) ) #define GRPCI2_DMACTRL_NUMCH( _val ) \ - ( ( ( _val ) << GRPCI2_DMACTRL_NUMCH_SHIFT ) & \ - GRPCI2_DMACTRL_NUMCH_MASK ) + ( ( ( _val ) << GRPCI2_DMACTRL_NUMCH_SHIFT ) & GRPCI2_DMACTRL_NUMCH_MASK ) #define GRPCI2_DMACTRL_ACTIVE 0x8U @@ -362,17 +354,15 @@ extern "C" { */ #define GRPCI2_DMABASE_BASE_SHIFT 0 -#define GRPCI2_DMABASE_BASE_MASK 0xffffffffU +#define GRPCI2_DMABASE_BASE_MASK 0xffffffffU #define GRPCI2_DMABASE_BASE_GET( _reg ) \ - ( ( ( _reg ) & GRPCI2_DMABASE_BASE_MASK ) >> \ - GRPCI2_DMABASE_BASE_SHIFT ) -#define GRPCI2_DMABASE_BASE_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRPCI2_DMABASE_BASE_MASK ) | \ + ( ( ( _reg ) & GRPCI2_DMABASE_BASE_MASK ) >> GRPCI2_DMABASE_BASE_SHIFT ) +#define GRPCI2_DMABASE_BASE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_DMABASE_BASE_MASK ) | \ ( ( ( _val ) << GRPCI2_DMABASE_BASE_SHIFT ) & \ GRPCI2_DMABASE_BASE_MASK ) ) #define GRPCI2_DMABASE_BASE( _val ) \ - ( ( ( _val ) << GRPCI2_DMABASE_BASE_SHIFT ) & \ - GRPCI2_DMABASE_BASE_MASK ) + ( ( ( _val ) << GRPCI2_DMABASE_BASE_SHIFT ) & GRPCI2_DMABASE_BASE_MASK ) /** @} */ @@ -385,17 +375,15 @@ extern "C" { */ #define GRPCI2_DMACHAN_CHAN_SHIFT 0 -#define GRPCI2_DMACHAN_CHAN_MASK 0xffffffffU +#define GRPCI2_DMACHAN_CHAN_MASK 0xffffffffU #define GRPCI2_DMACHAN_CHAN_GET( _reg ) \ - ( ( ( _reg ) & GRPCI2_DMACHAN_CHAN_MASK ) >> \ - GRPCI2_DMACHAN_CHAN_SHIFT ) -#define GRPCI2_DMACHAN_CHAN_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRPCI2_DMACHAN_CHAN_MASK ) | \ + ( ( ( _reg ) & GRPCI2_DMACHAN_CHAN_MASK ) >> GRPCI2_DMACHAN_CHAN_SHIFT ) +#define GRPCI2_DMACHAN_CHAN_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_DMACHAN_CHAN_MASK ) | \ ( ( ( _val ) << GRPCI2_DMACHAN_CHAN_SHIFT ) & \ GRPCI2_DMACHAN_CHAN_MASK ) ) #define GRPCI2_DMACHAN_CHAN( _val ) \ - ( ( ( _val ) << GRPCI2_DMACHAN_CHAN_SHIFT ) & \ - GRPCI2_DMACHAN_CHAN_MASK ) + ( ( ( _val ) << GRPCI2_DMACHAN_CHAN_SHIFT ) & GRPCI2_DMACHAN_CHAN_MASK ) /** @} */ @@ -409,17 +397,15 @@ extern "C" { */ #define GRPCI2_PCI2AHB_ADDR_SHIFT 0 -#define GRPCI2_PCI2AHB_ADDR_MASK 0xffffffffU +#define GRPCI2_PCI2AHB_ADDR_MASK 0xffffffffU #define GRPCI2_PCI2AHB_ADDR_GET( _reg ) \ - ( ( ( _reg ) & GRPCI2_PCI2AHB_ADDR_MASK ) >> \ - GRPCI2_PCI2AHB_ADDR_SHIFT ) -#define GRPCI2_PCI2AHB_ADDR_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRPCI2_PCI2AHB_ADDR_MASK ) | \ + ( ( ( _reg ) & GRPCI2_PCI2AHB_ADDR_MASK ) >> GRPCI2_PCI2AHB_ADDR_SHIFT ) +#define GRPCI2_PCI2AHB_ADDR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_PCI2AHB_ADDR_MASK ) | \ ( ( ( _val ) << GRPCI2_PCI2AHB_ADDR_SHIFT ) & \ GRPCI2_PCI2AHB_ADDR_MASK ) ) #define GRPCI2_PCI2AHB_ADDR( _val ) \ - ( ( ( _val ) << GRPCI2_PCI2AHB_ADDR_SHIFT ) & \ - GRPCI2_PCI2AHB_ADDR_MASK ) + ( ( ( _val ) << GRPCI2_PCI2AHB_ADDR_SHIFT ) & GRPCI2_PCI2AHB_ADDR_MASK ) /** @} */ @@ -433,17 +419,15 @@ extern "C" { */ #define GRPCI2_AHBM2PCI_ADDR_SHIFT 0 -#define GRPCI2_AHBM2PCI_ADDR_MASK 0xffffffffU +#define GRPCI2_AHBM2PCI_ADDR_MASK 0xffffffffU #define GRPCI2_AHBM2PCI_ADDR_GET( _reg ) \ - ( ( ( _reg ) & GRPCI2_AHBM2PCI_ADDR_MASK ) >> \ - GRPCI2_AHBM2PCI_ADDR_SHIFT ) -#define GRPCI2_AHBM2PCI_ADDR_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRPCI2_AHBM2PCI_ADDR_MASK ) | \ + ( ( ( _reg ) & GRPCI2_AHBM2PCI_ADDR_MASK ) >> GRPCI2_AHBM2PCI_ADDR_SHIFT ) +#define GRPCI2_AHBM2PCI_ADDR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_AHBM2PCI_ADDR_MASK ) | \ ( ( ( _val ) << GRPCI2_AHBM2PCI_ADDR_SHIFT ) & \ GRPCI2_AHBM2PCI_ADDR_MASK ) ) #define GRPCI2_AHBM2PCI_ADDR( _val ) \ - ( ( ( _val ) << GRPCI2_AHBM2PCI_ADDR_SHIFT ) & \ - GRPCI2_AHBM2PCI_ADDR_MASK ) + ( ( ( _val ) << GRPCI2_AHBM2PCI_ADDR_SHIFT ) & GRPCI2_AHBM2PCI_ADDR_MASK ) /** @} */ @@ -457,15 +441,15 @@ extern "C" { */ #define GRPCI2_TCTRC_TRIG_INDEX_SHIFT 16 -#define GRPCI2_TCTRC_TRIG_INDEX_MASK 0xffff0000U -#define GRPCI2_TCTRC_TRIG_INDEX_GET( _reg ) \ +#define GRPCI2_TCTRC_TRIG_INDEX_MASK 0xffff0000U +#define GRPCI2_TCTRC_TRIG_INDEX_GET( _reg ) \ ( ( ( _reg ) & GRPCI2_TCTRC_TRIG_INDEX_MASK ) >> \ GRPCI2_TCTRC_TRIG_INDEX_SHIFT ) -#define GRPCI2_TCTRC_TRIG_INDEX_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRPCI2_TCTRC_TRIG_INDEX_MASK ) | \ +#define GRPCI2_TCTRC_TRIG_INDEX_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_TCTRC_TRIG_INDEX_MASK ) | \ ( ( ( _val ) << GRPCI2_TCTRC_TRIG_INDEX_SHIFT ) & \ GRPCI2_TCTRC_TRIG_INDEX_MASK ) ) -#define GRPCI2_TCTRC_TRIG_INDEX( _val ) \ +#define GRPCI2_TCTRC_TRIG_INDEX( _val ) \ ( ( ( _val ) << GRPCI2_TCTRC_TRIG_INDEX_SHIFT ) & \ GRPCI2_TCTRC_TRIG_INDEX_MASK ) @@ -474,17 +458,14 @@ extern "C" { #define GRPCI2_TCTRC_EN 0x4000U #define GRPCI2_TCTRC_DEPTH_SHIFT 4 -#define GRPCI2_TCTRC_DEPTH_MASK 0xff0U +#define GRPCI2_TCTRC_DEPTH_MASK 0xff0U #define GRPCI2_TCTRC_DEPTH_GET( _reg ) \ - ( ( ( _reg ) & GRPCI2_TCTRC_DEPTH_MASK ) >> \ - GRPCI2_TCTRC_DEPTH_SHIFT ) -#define GRPCI2_TCTRC_DEPTH_SET( _reg, _val ) \ + ( ( ( _reg ) & GRPCI2_TCTRC_DEPTH_MASK ) >> GRPCI2_TCTRC_DEPTH_SHIFT ) +#define GRPCI2_TCTRC_DEPTH_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRPCI2_TCTRC_DEPTH_MASK ) | \ - ( ( ( _val ) << GRPCI2_TCTRC_DEPTH_SHIFT ) & \ - GRPCI2_TCTRC_DEPTH_MASK ) ) + ( ( ( _val ) << GRPCI2_TCTRC_DEPTH_SHIFT ) & GRPCI2_TCTRC_DEPTH_MASK ) ) #define GRPCI2_TCTRC_DEPTH( _val ) \ - ( ( ( _val ) << GRPCI2_TCTRC_DEPTH_SHIFT ) & \ - GRPCI2_TCTRC_DEPTH_MASK ) + ( ( ( _val ) << GRPCI2_TCTRC_DEPTH_SHIFT ) & GRPCI2_TCTRC_DEPTH_MASK ) #define GRPCI2_TCTRC_SO 0x2U @@ -501,41 +482,41 @@ extern "C" { */ #define GRPCI2_TMODE_TRACING_MODE_SHIFT 24 -#define GRPCI2_TMODE_TRACING_MODE_MASK 0xf000000U -#define GRPCI2_TMODE_TRACING_MODE_GET( _reg ) \ +#define GRPCI2_TMODE_TRACING_MODE_MASK 0xf000000U +#define GRPCI2_TMODE_TRACING_MODE_GET( _reg ) \ ( ( ( _reg ) & GRPCI2_TMODE_TRACING_MODE_MASK ) >> \ GRPCI2_TMODE_TRACING_MODE_SHIFT ) -#define GRPCI2_TMODE_TRACING_MODE_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRPCI2_TMODE_TRACING_MODE_MASK ) | \ +#define GRPCI2_TMODE_TRACING_MODE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_TMODE_TRACING_MODE_MASK ) | \ ( ( ( _val ) << GRPCI2_TMODE_TRACING_MODE_SHIFT ) & \ GRPCI2_TMODE_TRACING_MODE_MASK ) ) -#define GRPCI2_TMODE_TRACING_MODE( _val ) \ +#define GRPCI2_TMODE_TRACING_MODE( _val ) \ ( ( ( _val ) << GRPCI2_TMODE_TRACING_MODE_SHIFT ) & \ GRPCI2_TMODE_TRACING_MODE_MASK ) #define GRPCI2_TMODE_TRIG_COUNT_SHIFT 16 -#define GRPCI2_TMODE_TRIG_COUNT_MASK 0xff0000U -#define GRPCI2_TMODE_TRIG_COUNT_GET( _reg ) \ +#define GRPCI2_TMODE_TRIG_COUNT_MASK 0xff0000U +#define GRPCI2_TMODE_TRIG_COUNT_GET( _reg ) \ ( ( ( _reg ) & GRPCI2_TMODE_TRIG_COUNT_MASK ) >> \ GRPCI2_TMODE_TRIG_COUNT_SHIFT ) -#define GRPCI2_TMODE_TRIG_COUNT_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRPCI2_TMODE_TRIG_COUNT_MASK ) | \ +#define GRPCI2_TMODE_TRIG_COUNT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_TMODE_TRIG_COUNT_MASK ) | \ ( ( ( _val ) << GRPCI2_TMODE_TRIG_COUNT_SHIFT ) & \ GRPCI2_TMODE_TRIG_COUNT_MASK ) ) -#define GRPCI2_TMODE_TRIG_COUNT( _val ) \ +#define GRPCI2_TMODE_TRIG_COUNT( _val ) \ ( ( ( _val ) << GRPCI2_TMODE_TRIG_COUNT_SHIFT ) & \ GRPCI2_TMODE_TRIG_COUNT_MASK ) #define GRPCI2_TMODE_DELAYED_STOP_SHIFT 0 -#define GRPCI2_TMODE_DELAYED_STOP_MASK 0xffffU -#define GRPCI2_TMODE_DELAYED_STOP_GET( _reg ) \ +#define GRPCI2_TMODE_DELAYED_STOP_MASK 0xffffU +#define GRPCI2_TMODE_DELAYED_STOP_GET( _reg ) \ ( ( ( _reg ) & GRPCI2_TMODE_DELAYED_STOP_MASK ) >> \ GRPCI2_TMODE_DELAYED_STOP_SHIFT ) -#define GRPCI2_TMODE_DELAYED_STOP_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRPCI2_TMODE_DELAYED_STOP_MASK ) | \ +#define GRPCI2_TMODE_DELAYED_STOP_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_TMODE_DELAYED_STOP_MASK ) | \ ( ( ( _val ) << GRPCI2_TMODE_DELAYED_STOP_SHIFT ) & \ GRPCI2_TMODE_DELAYED_STOP_MASK ) ) -#define GRPCI2_TMODE_DELAYED_STOP( _val ) \ +#define GRPCI2_TMODE_DELAYED_STOP( _val ) \ ( ( ( _val ) << GRPCI2_TMODE_DELAYED_STOP_SHIFT ) & \ GRPCI2_TMODE_DELAYED_STOP_MASK ) @@ -550,17 +531,15 @@ extern "C" { */ #define GRPCI2_TADP_PATTERN_SHIFT 0 -#define GRPCI2_TADP_PATTERN_MASK 0xffffffffU +#define GRPCI2_TADP_PATTERN_MASK 0xffffffffU #define GRPCI2_TADP_PATTERN_GET( _reg ) \ - ( ( ( _reg ) & GRPCI2_TADP_PATTERN_MASK ) >> \ - GRPCI2_TADP_PATTERN_SHIFT ) -#define GRPCI2_TADP_PATTERN_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRPCI2_TADP_PATTERN_MASK ) | \ + ( ( ( _reg ) & GRPCI2_TADP_PATTERN_MASK ) >> GRPCI2_TADP_PATTERN_SHIFT ) +#define GRPCI2_TADP_PATTERN_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_TADP_PATTERN_MASK ) | \ ( ( ( _val ) << GRPCI2_TADP_PATTERN_SHIFT ) & \ GRPCI2_TADP_PATTERN_MASK ) ) #define GRPCI2_TADP_PATTERN( _val ) \ - ( ( ( _val ) << GRPCI2_TADP_PATTERN_SHIFT ) & \ - GRPCI2_TADP_PATTERN_MASK ) + ( ( ( _val ) << GRPCI2_TADP_PATTERN_SHIFT ) & GRPCI2_TADP_PATTERN_MASK ) /** @} */ @@ -573,17 +552,14 @@ extern "C" { */ #define GRPCI2_TADM_MASK_SHIFT 0 -#define GRPCI2_TADM_MASK_MASK 0xffffffffU +#define GRPCI2_TADM_MASK_MASK 0xffffffffU #define GRPCI2_TADM_MASK_GET( _reg ) \ - ( ( ( _reg ) & GRPCI2_TADM_MASK_MASK ) >> \ - GRPCI2_TADM_MASK_SHIFT ) -#define GRPCI2_TADM_MASK_SET( _reg, _val ) \ + ( ( ( _reg ) & GRPCI2_TADM_MASK_MASK ) >> GRPCI2_TADM_MASK_SHIFT ) +#define GRPCI2_TADM_MASK_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRPCI2_TADM_MASK_MASK ) | \ - ( ( ( _val ) << GRPCI2_TADM_MASK_SHIFT ) & \ - GRPCI2_TADM_MASK_MASK ) ) + ( ( ( _val ) << GRPCI2_TADM_MASK_SHIFT ) & GRPCI2_TADM_MASK_MASK ) ) #define GRPCI2_TADM_MASK( _val ) \ - ( ( ( _val ) << GRPCI2_TADM_MASK_SHIFT ) & \ - GRPCI2_TADM_MASK_MASK ) + ( ( ( _val ) << GRPCI2_TADM_MASK_SHIFT ) & GRPCI2_TADM_MASK_MASK ) /** @} */ @@ -596,17 +572,14 @@ extern "C" { */ #define GRPCI2_TCP_CBE_3_0_SHIFT 16 -#define GRPCI2_TCP_CBE_3_0_MASK 0xf0000U +#define GRPCI2_TCP_CBE_3_0_MASK 0xf0000U #define GRPCI2_TCP_CBE_3_0_GET( _reg ) \ - ( ( ( _reg ) & GRPCI2_TCP_CBE_3_0_MASK ) >> \ - GRPCI2_TCP_CBE_3_0_SHIFT ) -#define GRPCI2_TCP_CBE_3_0_SET( _reg, _val ) \ + ( ( ( _reg ) & GRPCI2_TCP_CBE_3_0_MASK ) >> GRPCI2_TCP_CBE_3_0_SHIFT ) +#define GRPCI2_TCP_CBE_3_0_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRPCI2_TCP_CBE_3_0_MASK ) | \ - ( ( ( _val ) << GRPCI2_TCP_CBE_3_0_SHIFT ) & \ - GRPCI2_TCP_CBE_3_0_MASK ) ) + ( ( ( _val ) << GRPCI2_TCP_CBE_3_0_SHIFT ) & GRPCI2_TCP_CBE_3_0_MASK ) ) #define GRPCI2_TCP_CBE_3_0( _val ) \ - ( ( ( _val ) << GRPCI2_TCP_CBE_3_0_SHIFT ) & \ - GRPCI2_TCP_CBE_3_0_MASK ) + ( ( ( _val ) << GRPCI2_TCP_CBE_3_0_SHIFT ) & GRPCI2_TCP_CBE_3_0_MASK ) #define GRPCI2_TCP_FRAME 0x8000U @@ -645,17 +618,14 @@ extern "C" { */ #define GRPCI2_TCM_CBE_3_0_SHIFT 16 -#define GRPCI2_TCM_CBE_3_0_MASK 0xf0000U +#define GRPCI2_TCM_CBE_3_0_MASK 0xf0000U #define GRPCI2_TCM_CBE_3_0_GET( _reg ) \ - ( ( ( _reg ) & GRPCI2_TCM_CBE_3_0_MASK ) >> \ - GRPCI2_TCM_CBE_3_0_SHIFT ) -#define GRPCI2_TCM_CBE_3_0_SET( _reg, _val ) \ + ( ( ( _reg ) & GRPCI2_TCM_CBE_3_0_MASK ) >> GRPCI2_TCM_CBE_3_0_SHIFT ) +#define GRPCI2_TCM_CBE_3_0_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRPCI2_TCM_CBE_3_0_MASK ) | \ - ( ( ( _val ) << GRPCI2_TCM_CBE_3_0_SHIFT ) & \ - GRPCI2_TCM_CBE_3_0_MASK ) ) + ( ( ( _val ) << GRPCI2_TCM_CBE_3_0_SHIFT ) & GRPCI2_TCM_CBE_3_0_MASK ) ) #define GRPCI2_TCM_CBE_3_0( _val ) \ - ( ( ( _val ) << GRPCI2_TCM_CBE_3_0_SHIFT ) & \ - GRPCI2_TCM_CBE_3_0_MASK ) + ( ( ( _val ) << GRPCI2_TCM_CBE_3_0_SHIFT ) & GRPCI2_TCM_CBE_3_0_MASK ) #define GRPCI2_TCM_FRAME 0x8000U @@ -694,17 +664,14 @@ extern "C" { */ #define GRPCI2_TADS_SIGNAL_SHIFT 0 -#define GRPCI2_TADS_SIGNAL_MASK 0xffffffffU +#define GRPCI2_TADS_SIGNAL_MASK 0xffffffffU #define GRPCI2_TADS_SIGNAL_GET( _reg ) \ - ( ( ( _reg ) & GRPCI2_TADS_SIGNAL_MASK ) >> \ - GRPCI2_TADS_SIGNAL_SHIFT ) -#define GRPCI2_TADS_SIGNAL_SET( _reg, _val ) \ + ( ( ( _reg ) & GRPCI2_TADS_SIGNAL_MASK ) >> GRPCI2_TADS_SIGNAL_SHIFT ) +#define GRPCI2_TADS_SIGNAL_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRPCI2_TADS_SIGNAL_MASK ) | \ - ( ( ( _val ) << GRPCI2_TADS_SIGNAL_SHIFT ) & \ - GRPCI2_TADS_SIGNAL_MASK ) ) + ( ( ( _val ) << GRPCI2_TADS_SIGNAL_SHIFT ) & GRPCI2_TADS_SIGNAL_MASK ) ) #define GRPCI2_TADS_SIGNAL( _val ) \ - ( ( ( _val ) << GRPCI2_TADS_SIGNAL_SHIFT ) & \ - GRPCI2_TADS_SIGNAL_MASK ) + ( ( ( _val ) << GRPCI2_TADS_SIGNAL_SHIFT ) & GRPCI2_TADS_SIGNAL_MASK ) /** @} */ @@ -718,17 +685,14 @@ extern "C" { */ #define GRPCI2_TCS_CBE_3_0_SHIFT 16 -#define GRPCI2_TCS_CBE_3_0_MASK 0xf0000U +#define GRPCI2_TCS_CBE_3_0_MASK 0xf0000U #define GRPCI2_TCS_CBE_3_0_GET( _reg ) \ - ( ( ( _reg ) & GRPCI2_TCS_CBE_3_0_MASK ) >> \ - GRPCI2_TCS_CBE_3_0_SHIFT ) -#define GRPCI2_TCS_CBE_3_0_SET( _reg, _val ) \ + ( ( ( _reg ) & GRPCI2_TCS_CBE_3_0_MASK ) >> GRPCI2_TCS_CBE_3_0_SHIFT ) +#define GRPCI2_TCS_CBE_3_0_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRPCI2_TCS_CBE_3_0_MASK ) | \ - ( ( ( _val ) << GRPCI2_TCS_CBE_3_0_SHIFT ) & \ - GRPCI2_TCS_CBE_3_0_MASK ) ) + ( ( ( _val ) << GRPCI2_TCS_CBE_3_0_SHIFT ) & GRPCI2_TCS_CBE_3_0_MASK ) ) #define GRPCI2_TCS_CBE_3_0( _val ) \ - ( ( ( _val ) << GRPCI2_TCS_CBE_3_0_SHIFT ) & \ - GRPCI2_TCS_CBE_3_0_MASK ) + ( ( ( _val ) << GRPCI2_TCS_CBE_3_0_SHIFT ) & GRPCI2_TCS_CBE_3_0_MASK ) #define GRPCI2_TCS_FRAME 0x8000U diff --git a/bsps/include/grlib/grpci2.h b/bsps/include/grlib/grpci2.h index 871bbae6a9..dc87c68432 100644 --- a/bsps/include/grlib/grpci2.h +++ b/bsps/include/grlib/grpci2.h @@ -34,7 +34,7 @@ extern "C" { #endif -extern void grpci2_register_drv(void); +extern void grpci2_register_drv( void ); /* Driver Resources: * @@ -72,9 +72,9 @@ extern void grpci2_register_drv(void); * at and when accessing a BAR which AMBA address it will be translated to. */ struct grpci2_pcibar_cfg { - unsigned int pciadr; /* PCI address of BAR (BAR content) */ - unsigned int ahbadr; /* 'pciadr' translated to this AHB Address */ - unsigned int barsize; /* PCI BAR Size, must be a power of 2 */ + unsigned int pciadr; /* PCI address of BAR (BAR content) */ + unsigned int ahbadr; /* 'pciadr' translated to this AHB Address */ + unsigned int barsize; /* PCI BAR Size, must be a power of 2 */ }; #ifdef __cplusplus diff --git a/bsps/include/grlib/grpci2dma.h b/bsps/include/grlib/grpci2dma.h index 4e27c61d9b..9d9dda17d7 100644 --- a/bsps/include/grlib/grpci2dma.h +++ b/bsps/include/grlib/grpci2dma.h @@ -44,12 +44,12 @@ extern "C" { #endif /* Error return codes */ -#define GRPCI2DMA_ERR_OK 0 +#define GRPCI2DMA_ERR_OK 0 #define GRPCI2DMA_ERR_WRONGPTR -1 -#define GRPCI2DMA_ERR_NOINIT -2 -#define GRPCI2DMA_ERR_TOOMANY -3 -#define GRPCI2DMA_ERR_ERROR -4 -#define GRPCI2DMA_ERR_STOPDMA -5 +#define GRPCI2DMA_ERR_NOINIT -2 +#define GRPCI2DMA_ERR_TOOMANY -3 +#define GRPCI2DMA_ERR_ERROR -4 +#define GRPCI2DMA_ERR_STOPDMA -5 #define GRPCI2DMA_ERR_NOTFOUND -6 /* Size of a dma descriptors */ @@ -63,10 +63,10 @@ extern "C" { /* User-helper functions to allocate/deallocate * channel and data descriptors */ -extern void * grpci2dma_channel_new(int number); -extern void grpci2dma_channel_delete(void * chanbd); -extern void * grpci2dma_data_new(int number); -extern void grpci2dma_data_delete(void * databd); +extern void *grpci2dma_channel_new( int number ); +extern void grpci2dma_channel_delete( void *chanbd ); +extern void *grpci2dma_data_new( int number ); +extern void grpci2dma_data_delete( void *databd ); /* Function: * -grpci2dma_prepare @@ -91,13 +91,21 @@ extern void grpci2dma_data_delete(void * databd); * -value > 0: A positive return value means the number of data descriptors * prepared/used in the buffer, starting from index. */ -#define GRPCI2DMA_AHBTOPCI 1 -#define GRPCI2DMA_PCITOAHB 0 +#define GRPCI2DMA_AHBTOPCI 1 +#define GRPCI2DMA_PCITOAHB 0 #define GRPCI2DMA_LITTLEENDIAN 1 -#define GRPCI2DMA_BIGENDIAN 0 +#define GRPCI2DMA_BIGENDIAN 0 extern int grpci2dma_prepare( - uint32_t pci_start, uint32_t ahb_start, int dir, int endianness, - int size, void * databd, int bdindex, int bdmax, int block_size); + uint32_t pci_start, + uint32_t ahb_start, + int dir, + int endianness, + int size, + void *databd, + int bdindex, + int bdmax, + int block_size +); /* Function: * -grpci2dma_status @@ -117,16 +125,16 @@ extern int grpci2dma_prepare( * which means that either the transfer finished or it was never prepared. */ #define GRPCI2DMA_BD_STATUS_DISABLED 0 -#define GRPCI2DMA_BD_STATUS_ENABLED 1 -#define GRPCI2DMA_BD_STATUS_ERR 2 -extern int grpci2dma_status(void *databd, int bdindex, int bdsize); +#define GRPCI2DMA_BD_STATUS_ENABLED 1 +#define GRPCI2DMA_BD_STATUS_ERR 2 +extern int grpci2dma_status( void *databd, int bdindex, int bdsize ); /* Function Interrupt-Code ISR callback prototype. * arg - Custom arg provided by user * cid - Channel ID that got the interrupt * status - Error status of the DMA core */ -typedef void (*grpci2dma_isr_t)(void *arg, int cid, unsigned int status); +typedef void ( *grpci2dma_isr_t )( void *arg, int cid, unsigned int status ); /* Function: * -grpci2dma_isr_register @@ -142,7 +150,10 @@ typedef void (*grpci2dma_isr_t)(void *arg, int cid, unsigned int status); * -OK (=0): Done */ extern int grpci2dma_isr_register( - int chan_no, grpci2dma_isr_t dmaisr, void *arg); + int chan_no, + grpci2dma_isr_t dmaisr, + void *arg +); /* Function: * -grpci2dma_isr_unregister @@ -155,7 +166,7 @@ extern int grpci2dma_isr_register( * -WRONGPTR: Wrong input parameters * -OK (=0): Done */ -extern int grpci2dma_isr_unregister(int chan_no); +extern int grpci2dma_isr_unregister( int chan_no ); /* Function: * -grpci2dma_open @@ -171,7 +182,7 @@ extern int grpci2dma_isr_unregister(int chan_no); * -ERROR: Inconsistent state found in driver * -value > 0: A positive return value means the id for the channel. */ -extern int grpci2dma_open(void * chan); +extern int grpci2dma_open( void *chan ); /* Function: * -grpci2dma_close @@ -187,7 +198,7 @@ extern int grpci2dma_open(void * chan); * -WRONGPTR: Wrong input parameters * -OK (=0): Done. */ -extern int grpci2dma_close(int chan_no); +extern int grpci2dma_close( int chan_no ); /* Function: * -grpci2dma_start @@ -203,7 +214,7 @@ extern int grpci2dma_close(int chan_no); * -ERROR: Inconsistent state found in driver * -OK (=0): Done. */ -extern int grpci2dma_start(int chan_no, int options); +extern int grpci2dma_start( int chan_no, int options ); /* Function: * -grpci2dma_stop @@ -217,7 +228,7 @@ extern int grpci2dma_start(int chan_no, int options); * -ERROR: Inconsistent state found in driver * -OK (=0): Done. */ -extern int grpci2dma_stop(int chan_no); +extern int grpci2dma_stop( int chan_no ); /* Function: * -grpci2dma_push @@ -234,7 +245,12 @@ extern int grpci2dma_stop(int chan_no); * -NOTFOUND: Channel not opened. * -OK (=0): Done. */ -extern int grpci2dma_push(int chan_no, void *databd, int bdindex, int bdsize); +extern int grpci2dma_push( + int chan_no, + void *databd, + int bdindex, + int bdsize +); /* Function: * -grpci2dma_active @@ -245,7 +261,7 @@ extern int grpci2dma_push(int chan_no, void *databd, int bdindex, int bdsize); * -(!=0): Active. * -(=0): Not active. */ -extern int grpci2dma_active(void); +extern int grpci2dma_active( void ); /* Function: * -grpci2dma_interrupt_enable @@ -268,12 +284,16 @@ extern int grpci2dma_active(void); #define GRPCI2DMA_OPTIONS_ALL 1 #define GRPCI2DMA_OPTIONS_ONE 0 extern int grpci2dma_interrupt_enable( - void *databd, int bdindex, int bdmax, int options); + void *databd, + int bdindex, + int bdmax, + int options +); /* Debug function: print dma channel and associated data descriptors. * Only prints if driver internal DEBUG flag is defined. */ -extern int grpci2dma_print(int chan_no); -extern int grpci2dma_print_bd(void * data); +extern int grpci2dma_print( int chan_no ); +extern int grpci2dma_print_bd( void *data ); #ifdef __cplusplus } diff --git a/bsps/include/grlib/grpwm.h b/bsps/include/grlib/grpwm.h index ab9d7a91e4..e450b6341f 100644 --- a/bsps/include/grlib/grpwm.h +++ b/bsps/include/grlib/grpwm.h @@ -35,109 +35,119 @@ extern "C" { #endif -extern void grpwm_register_drv (void); +extern void grpwm_register_drv( void ); -#define GRPWM_IOCTL_GET_CAP 1 /* Get Capabilities */ -#define GRPWM_IOCTL_SET_CONFIG 2 /* Configure one PWM Channel */ -#define GRPWM_IOCTL_SET_SCALER 3 /* Set one scaler */ -#define GRPWM_IOCTL_UPDATE 4 /* Set current period and compare value */ -#define GRPWM_IOCTL_IRQ 5 /* Set up IRQ handling */ +#define GRPWM_IOCTL_GET_CAP 1 /* Get Capabilities */ +#define GRPWM_IOCTL_SET_CONFIG 2 /* Configure one PWM Channel */ +#define GRPWM_IOCTL_SET_SCALER 3 /* Set one scaler */ +#define GRPWM_IOCTL_UPDATE 4 /* Set current period and compare value */ +#define GRPWM_IOCTL_IRQ 5 /* Set up IRQ handling */ /*** Argument for GRPWM_IOCTL_GET_CAP ***/ /* The Capability of the PWM core */ struct grpwm_ioctl_cap { - int channel_cnt; /* Number of channels */ - unsigned int pwm; /* Capability1 register */ - unsigned int wave; /* Capability2 register, Wave form capabilities of last PWM channel, otherwise 0 */ + int channel_cnt; /* Number of channels */ + unsigned int pwm; /* Capability1 register */ + unsigned int + wave; /* Capability2 register, Wave form capabilities of last PWM channel, otherwise 0 */ }; /*** Argument for GRPWM_IOCTL_GET_CONFIG and GRPWM_IOCTL_SET_CONFIG ***/ /* Config One PWM */ struct grpwm_ioctl_config { - unsigned int channel; /* Select channel to configure */ + unsigned int channel; /* Select channel to configure */ - /* Specific for one PWM channel */ - unsigned int options; /* PWM options */ - unsigned char dbscaler; /* value greater than 15 disable Dead band */ - unsigned char scaler_index; /* Select scaler used by PWM channel */ + /* Specific for one PWM channel */ + unsigned int options; /* PWM options */ + unsigned char dbscaler; /* value greater than 15 disable Dead band */ + unsigned char scaler_index; /* Select scaler used by PWM channel */ - /* IRQ Setup */ - unsigned char irqscaler; /* IRQ scaler */ - void *isr_arg; /* Argument of IRQ handler */ - void (*isr)(int channel, void *arg); /* Interrupt service routine for this PWM Channel */ + /* IRQ Setup */ + unsigned char irqscaler; /* IRQ scaler */ + void *isr_arg; /* Argument of IRQ handler */ + void ( *isr )( + int channel, + void *arg + ); /* Interrupt service routine for this PWM Channel */ - /* Waveform set up */ - int wave_activate; /* Enables Waveform functionality */ - unsigned int wave_synccfg; /* Bits [29,30,31] is written into Wave-Config register */ - unsigned int wave_sync; /* Sets sync compare register */ - unsigned int *wave_data; /* If not NULL, the Wave RAM is filled with data */ - unsigned int wave_data_length; /* Length of Wave RAM Data, Also used for wstopaddr */ + /* Waveform set up */ + int wave_activate; /* Enables Waveform functionality */ + unsigned int + wave_synccfg; /* Bits [29,30,31] is written into Wave-Config register */ + unsigned int wave_sync; /* Sets sync compare register */ + unsigned int *wave_data; /* If not NULL, the Wave RAM is filled with data */ + unsigned int + wave_data_length; /* Length of Wave RAM Data, Also used for wstopaddr */ }; -#define GRPWM_CONFIG_OPTION_FLIP 0x04000000 /* Set this to Flip PWM output pair */ -#define GRPWM_CONFIG_OPTION_DEAD_BAND 0x00200000 /* Dead Band enable */ -#define GRPWM_CONFIG_OPTION_SYMMETRIC 0x00000040 /* If not defined, asymmetric */ -#define GRPWM_CONFIG_OPTION_ASYMMERTIC 0 -#define GRPWM_CONFIG_OPTION_DUAL 0x00000020 /* Dual Compare Enable */ -#define GRPWM_CONFIG_OPTION_PAIR 0x00000004 /* PWM Pair Enable */ -#define GRPWM_CONFIG_OPTION_SINGLE 0x00000000 /* PWM Pair Disable */ -#define GRPWM_CONFIG_OPTION_POLARITY_HIGH 0x00000002 /* PWM Polarity HIGH */ -#define GRPWM_CONFIG_OPTION_POLARITY_LOW 0x00000000 /* PWM Polarity LOW */ +#define GRPWM_CONFIG_OPTION_FLIP \ + 0x04000000 /* Set this to Flip PWM output pair */ +#define GRPWM_CONFIG_OPTION_DEAD_BAND 0x00200000 /* Dead Band enable */ +#define GRPWM_CONFIG_OPTION_SYMMETRIC \ + 0x00000040 /* If not defined, asymmetric */ +#define GRPWM_CONFIG_OPTION_ASYMMERTIC 0 +#define GRPWM_CONFIG_OPTION_DUAL 0x00000020 /* Dual Compare Enable */ +#define GRPWM_CONFIG_OPTION_PAIR 0x00000004 /* PWM Pair Enable */ +#define GRPWM_CONFIG_OPTION_SINGLE 0x00000000 /* PWM Pair Disable */ +#define GRPWM_CONFIG_OPTION_POLARITY_HIGH 0x00000002 /* PWM Polarity HIGH */ +#define GRPWM_CONFIG_OPTION_POLARITY_LOW 0x00000000 /* PWM Polarity LOW */ -#define GRPWM_CONFIG_OPTION_MASK ( \ - GRPWM_CONFIG_OPTION_DEAD_BAND | GRPWM_CONFIG_OPTION_SYMMETRIC | \ - GRPWM_CONFIG_OPTION_DUAL | GRPWM_CONFIG_OPTION_PAIR | \ - GRPWM_CONFIG_OPTION_POLARITY_HIGH \ - ) +#define GRPWM_CONFIG_OPTION_MASK \ + ( GRPWM_CONFIG_OPTION_DEAD_BAND | GRPWM_CONFIG_OPTION_SYMMETRIC | \ + GRPWM_CONFIG_OPTION_DUAL | GRPWM_CONFIG_OPTION_PAIR | \ + GRPWM_CONFIG_OPTION_POLARITY_HIGH ) /*** Argument for GPPWM_IOCTL_SET_SCALER ***/ struct grpwm_ioctl_scaler { - unsigned int index_mask;/* Scaler update index mask, bit 0 = Scaler 0, bit 1 = Scaler 1 */ - unsigned int values[8]; /* Scaler update values, values[N] is stored into scaler N, if mask & 1<> 16) & 0xF) +#define SLINK_WRD_CHAN( x ) ( ( x >> 16 ) & 0xF ) /* Get IO card # from received SLINK word */ -#define SLINK_WRD_CARDNUM(x) ((x >> 21) & 0x3) +#define SLINK_WRD_CARDNUM( x ) ( ( x >> 21 ) & 0x3 ) /* Get data part from SLINK word */ -#define SLINK_WRD_PAYLOAD(x) (x & 0xFFFF) +#define SLINK_WRD_PAYLOAD( x ) ( x & 0xFFFF ) /* Checks status value to see if transmit queue has free slot */ -#define SLINK_STS_TRANSFREE(x) (x & SLINK_S_TNF) +#define SLINK_STS_TRANSFREE( x ) ( x & SLINK_S_TNF ) /* Get Sequence Index value */ -#define SLINK_STS_SI(x) ((x >> 16) & 0xFF) +#define SLINK_STS_SI( x ) ( ( x >> 16 ) & 0xFF ) /**** Function declarations, driver interface ****/ /* Initializes the SLINK core */ -int SLINK_init(unsigned int nullwrd, int parity, int qsize, - void (*interrupt_trans_handler)(int), - void (*sequence_callback)(int)); +int SLINK_init( + unsigned int nullwrd, + int parity, + int qsize, + void ( *interrupt_trans_handler )( int ), + void ( *sequence_callback )( int ) +); /* Enables the core */ -void SLINK_start(void); +void SLINK_start( void ); /* Disables the core */ -void SLINK_stop(void); +void SLINK_stop( void ); /* Reads one word */ -int SLINK_read(int data, int channel, int *reply); +int SLINK_read( int data, int channel, int *reply ); /* Writes one word */ -int SLINK_write(int data, int channel); +int SLINK_write( int data, int channel ); /* Peforms a SEQUENCE */ -int SLINK_seqstart(int *a, int *b, int n, int channel, int reconly); +int SLINK_seqstart( int *a, int *b, int n, int channel, int reconly ); /* Aborts a SEQUENCE */ -void SLINK_seqabort(void); +void SLINK_seqabort( void ); /* Status of current or last SEQUENCE */ -int SLINK_seqstatus(void); +int SLINK_seqstatus( void ); /* Number of words transferred in last SEQUENCE */ -int SLINK_seqwrds(void); +int SLINK_seqwrds( void ); /* Returns value of core's status register */ -int SLINK_hwstatus(void); +int SLINK_hwstatus( void ); /* Returns number of elements in queue associated with IO card */ -int SLINK_queuestatus(int iocard); +int SLINK_queuestatus( int iocard ); /* Take first element from queue for IO card # 'iocard' */ -int SLINK_dequeue(int iocard, int *elem); +int SLINK_dequeue( int iocard, int *elem ); /* Returns structure containing core driver statistics */ -SLINK_stats *SLINK_statistics(void); +SLINK_stats *SLINK_statistics( void ); #ifdef __cplusplus } diff --git a/bsps/include/grlib/grspw.h b/bsps/include/grlib/grspw.h index 1e7cb29e1c..2a07807e43 100644 --- a/bsps/include/grlib/grspw.h +++ b/bsps/include/grlib/grspw.h @@ -53,74 +53,77 @@ extern "C" { #define SPW_LINKERR_EVENT RTEMS_EVENT_0 typedef struct { - unsigned int rxsize; - unsigned int txdsize; - unsigned int txhsize; + unsigned int rxsize; + unsigned int txdsize; + unsigned int txhsize; } spw_ioctl_packetsize; -#define GRSPW_PKTSEND_OPTION_HDR_CRC 0x1 -#define GRSPW_PKTSEND_OPTION_DATA_CRC 0x2 -#define GRSPW_PKTSEND_OPTION_NOCRCLEN(len) ((len & 0xf) << 8) -#define GRSPW_PKTSEND_OPTION_NOCRCLEN_MASK 0xf00 +#define GRSPW_PKTSEND_OPTION_HDR_CRC 0x1 +#define GRSPW_PKTSEND_OPTION_DATA_CRC 0x2 +#define GRSPW_PKTSEND_OPTION_NOCRCLEN( len ) ( ( len & 0xf ) << 8 ) +#define GRSPW_PKTSEND_OPTION_NOCRCLEN_MASK 0xf00 typedef struct { - unsigned int hlen; - char *hdr; - unsigned int dlen; - char *data; - unsigned int sent; - unsigned int options; + unsigned int hlen; + char *hdr; + unsigned int dlen; + char *data; + unsigned int sent; + unsigned int options; } spw_ioctl_pkt_send; typedef struct { - unsigned int tx_link_err; - unsigned int rx_rmap_header_crc_err; - unsigned int rx_rmap_data_crc_err; - unsigned int rx_eep_err; - unsigned int rx_truncated; - unsigned int parity_err; - unsigned int escape_err; - unsigned int credit_err; - unsigned int write_sync_err; - unsigned int disconnect_err; - unsigned int early_ep; - unsigned int invalid_address; - unsigned int packets_sent; - unsigned int packets_received; + unsigned int tx_link_err; + unsigned int rx_rmap_header_crc_err; + unsigned int rx_rmap_data_crc_err; + unsigned int rx_eep_err; + unsigned int rx_truncated; + unsigned int parity_err; + unsigned int escape_err; + unsigned int credit_err; + unsigned int write_sync_err; + unsigned int disconnect_err; + unsigned int early_ep; + unsigned int invalid_address; + unsigned int packets_sent; + unsigned int packets_received; } spw_stats; typedef struct { - unsigned int nodeaddr; - unsigned int destkey; - unsigned int clkdiv; /* Note: contain both CLKDIVSTART and CLKDIVRUN, but IOCTL_SET_CLKDIV* commands are split into two */ - unsigned int rxmaxlen; - unsigned int timer; - unsigned int disconnect; - unsigned int promiscuous; - unsigned int rmapen; - unsigned int rmapbufdis; - unsigned int linkdisabled; - unsigned int linkstart; + unsigned int nodeaddr; + unsigned int destkey; + unsigned int + clkdiv; /* Note: contain both CLKDIVSTART and CLKDIVRUN, but IOCTL_SET_CLKDIV* commands are split into two */ + unsigned int rxmaxlen; + unsigned int timer; + unsigned int disconnect; + unsigned int promiscuous; + unsigned int rmapen; + unsigned int rmapbufdis; + unsigned int linkdisabled; + unsigned int linkstart; - unsigned int check_rmap_err; /* check incoming packets for rmap errors */ - unsigned int rm_prot_id; /* remove protocol id from incoming packets */ - unsigned int tx_blocking; /* use blocking tx */ - unsigned int tx_block_on_full; /* block when all tx_buffers are used */ - unsigned int rx_blocking; /* block when no data is available */ - unsigned int disable_err; /* disable link automatically when link error is detected */ - unsigned int link_err_irq; /* generate an interrupt when link error occurs */ - rtems_id event_id; /* task id that should receive link err irq event */ + unsigned int check_rmap_err; /* check incoming packets for rmap errors */ + unsigned int rm_prot_id; /* remove protocol id from incoming packets */ + unsigned int tx_blocking; /* use blocking tx */ + unsigned int tx_block_on_full; /* block when all tx_buffers are used */ + unsigned int rx_blocking; /* block when no data is available */ + unsigned int + disable_err; /* disable link automatically when link error is detected */ + unsigned int link_err_irq; /* generate an interrupt when link error occurs */ + rtems_id event_id; /* task id that should receive link err irq event */ - unsigned int is_rmap; - unsigned int is_rxunaligned; - unsigned int is_rmapcrc; + unsigned int is_rmap; + unsigned int is_rxunaligned; + unsigned int is_rmapcrc; - unsigned int nodemask; - unsigned int keep_source; /* copy source address to user-buffer in read() operations + unsigned int nodemask; + unsigned int + keep_source; /* copy source address to user-buffer in read() operations * Note that rm_prot_id has no effect when keep_source is * set. */ - unsigned int rtimeout; /* Read timeout if != 0 */ + unsigned int rtimeout; /* Read timeout if != 0 */ } spw_config; #define SPACEWIRE_IOCTRL_SET_NODEADDR 1 @@ -156,36 +159,39 @@ typedef struct { #define SPACEWIRE_IOCTRL_GET_TCODE 38 #define SPACEWIRE_IOCTRL_SET_READ_TIMEOUT 39 -#define SPACEWIRE_IOCTRL_START 64 -#define SPACEWIRE_IOCTRL_STOP 65 +#define SPACEWIRE_IOCTRL_START 64 +#define SPACEWIRE_IOCTRL_STOP 65 /* Defines what register bits that will be touched * for SPACEWIRE_IOCTRL_SET_TCODE_CTRL */ -#define SPACEWIRE_TCODE_CTRL_IE_MSK 0x001 -#define SPACEWIRE_TCODE_CTRL_TT_MSK 0x004 -#define SPACEWIRE_TCODE_CTRL_TR_MSK 0x008 +#define SPACEWIRE_TCODE_CTRL_IE_MSK 0x001 +#define SPACEWIRE_TCODE_CTRL_TT_MSK 0x004 +#define SPACEWIRE_TCODE_CTRL_TR_MSK 0x008 /* Defines what register bits that should be set * for SPACEWIRE_IOCTRL_SET_TCODE_CTRL */ -#define SPACEWIRE_TCODE_CTRL_IE 0x100 -#define SPACEWIRE_TCODE_CTRL_TT 0x400 -#define SPACEWIRE_TCODE_CTRL_TR 0x800 +#define SPACEWIRE_TCODE_CTRL_IE 0x100 +#define SPACEWIRE_TCODE_CTRL_TT 0x400 +#define SPACEWIRE_TCODE_CTRL_TR 0x800 /* SPACEWIRE_IOCTRL_SET_TCODE argument mask */ -#define SPACEWIRE_TCODE_TCODE 0x0ff -#define SPACEWIRE_TCODE_SET 0x100 /* Set Timecode register */ -#define SPACEWIRE_TCODE_TX 0x400 +#define SPACEWIRE_TCODE_TCODE 0x0ff +#define SPACEWIRE_TCODE_SET 0x100 /* Set Timecode register */ +#define SPACEWIRE_TCODE_TX 0x400 -void grspw_register_drv (void); +void grspw_register_drv( void ); -void grspw_print(int options); +void grspw_print( int options ); /* Global GRSPW Function pointer called upon timecode receive interrupt */ -extern void (*grspw_timecode_callback) - (void *pDev, void *regs, int minor, unsigned int tc); - +extern void ( *grspw_timecode_callback )( + void *pDev, + void *regs, + int minor, + unsigned int tc +); #ifdef __cplusplus } diff --git a/bsps/include/grlib/grspw2-regs.h b/bsps/include/grlib/grspw2-regs.h index 6293230cfe..5f4e930553 100644 --- a/bsps/include/grlib/grspw2-regs.h +++ b/bsps/include/grlib/grspw2-regs.h @@ -82,30 +82,25 @@ extern "C" { */ #define GRSPW2_DMACTRL_INTNUM_SHIFT 26 -#define GRSPW2_DMACTRL_INTNUM_MASK 0xfc000000U +#define GRSPW2_DMACTRL_INTNUM_MASK 0xfc000000U #define GRSPW2_DMACTRL_INTNUM_GET( _reg ) \ - ( ( ( _reg ) & GRSPW2_DMACTRL_INTNUM_MASK ) >> \ - GRSPW2_DMACTRL_INTNUM_SHIFT ) -#define GRSPW2_DMACTRL_INTNUM_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPW2_DMACTRL_INTNUM_MASK ) | \ + ( ( ( _reg ) & GRSPW2_DMACTRL_INTNUM_MASK ) >> GRSPW2_DMACTRL_INTNUM_SHIFT ) +#define GRSPW2_DMACTRL_INTNUM_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_DMACTRL_INTNUM_MASK ) | \ ( ( ( _val ) << GRSPW2_DMACTRL_INTNUM_SHIFT ) & \ GRSPW2_DMACTRL_INTNUM_MASK ) ) #define GRSPW2_DMACTRL_INTNUM( _val ) \ - ( ( ( _val ) << GRSPW2_DMACTRL_INTNUM_SHIFT ) & \ - GRSPW2_DMACTRL_INTNUM_MASK ) + ( ( ( _val ) << GRSPW2_DMACTRL_INTNUM_SHIFT ) & GRSPW2_DMACTRL_INTNUM_MASK ) #define GRSPW2_DMACTRL_RES_SHIFT 24 -#define GRSPW2_DMACTRL_RES_MASK 0x3000000U +#define GRSPW2_DMACTRL_RES_MASK 0x3000000U #define GRSPW2_DMACTRL_RES_GET( _reg ) \ - ( ( ( _reg ) & GRSPW2_DMACTRL_RES_MASK ) >> \ - GRSPW2_DMACTRL_RES_SHIFT ) -#define GRSPW2_DMACTRL_RES_SET( _reg, _val ) \ + ( ( ( _reg ) & GRSPW2_DMACTRL_RES_MASK ) >> GRSPW2_DMACTRL_RES_SHIFT ) +#define GRSPW2_DMACTRL_RES_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRSPW2_DMACTRL_RES_MASK ) | \ - ( ( ( _val ) << GRSPW2_DMACTRL_RES_SHIFT ) & \ - GRSPW2_DMACTRL_RES_MASK ) ) + ( ( ( _val ) << GRSPW2_DMACTRL_RES_SHIFT ) & GRSPW2_DMACTRL_RES_MASK ) ) #define GRSPW2_DMACTRL_RES( _val ) \ - ( ( ( _val ) << GRSPW2_DMACTRL_RES_SHIFT ) & \ - GRSPW2_DMACTRL_RES_MASK ) + ( ( ( _val ) << GRSPW2_DMACTRL_RES_SHIFT ) & GRSPW2_DMACTRL_RES_MASK ) #define GRSPW2_DMACTRL_EP 0x800000U @@ -166,30 +161,28 @@ extern "C" { */ #define GRSPW2_DMAMAXLEN_RXMAXLEN_SHIFT 2 -#define GRSPW2_DMAMAXLEN_RXMAXLEN_MASK 0x1fffffcU -#define GRSPW2_DMAMAXLEN_RXMAXLEN_GET( _reg ) \ +#define GRSPW2_DMAMAXLEN_RXMAXLEN_MASK 0x1fffffcU +#define GRSPW2_DMAMAXLEN_RXMAXLEN_GET( _reg ) \ ( ( ( _reg ) & GRSPW2_DMAMAXLEN_RXMAXLEN_MASK ) >> \ GRSPW2_DMAMAXLEN_RXMAXLEN_SHIFT ) -#define GRSPW2_DMAMAXLEN_RXMAXLEN_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPW2_DMAMAXLEN_RXMAXLEN_MASK ) | \ +#define GRSPW2_DMAMAXLEN_RXMAXLEN_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_DMAMAXLEN_RXMAXLEN_MASK ) | \ ( ( ( _val ) << GRSPW2_DMAMAXLEN_RXMAXLEN_SHIFT ) & \ GRSPW2_DMAMAXLEN_RXMAXLEN_MASK ) ) -#define GRSPW2_DMAMAXLEN_RXMAXLEN( _val ) \ +#define GRSPW2_DMAMAXLEN_RXMAXLEN( _val ) \ ( ( ( _val ) << GRSPW2_DMAMAXLEN_RXMAXLEN_SHIFT ) & \ GRSPW2_DMAMAXLEN_RXMAXLEN_MASK ) #define GRSPW2_DMAMAXLEN_RES_SHIFT 0 -#define GRSPW2_DMAMAXLEN_RES_MASK 0x3U +#define GRSPW2_DMAMAXLEN_RES_MASK 0x3U #define GRSPW2_DMAMAXLEN_RES_GET( _reg ) \ - ( ( ( _reg ) & GRSPW2_DMAMAXLEN_RES_MASK ) >> \ - GRSPW2_DMAMAXLEN_RES_SHIFT ) -#define GRSPW2_DMAMAXLEN_RES_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPW2_DMAMAXLEN_RES_MASK ) | \ + ( ( ( _reg ) & GRSPW2_DMAMAXLEN_RES_MASK ) >> GRSPW2_DMAMAXLEN_RES_SHIFT ) +#define GRSPW2_DMAMAXLEN_RES_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_DMAMAXLEN_RES_MASK ) | \ ( ( ( _val ) << GRSPW2_DMAMAXLEN_RES_SHIFT ) & \ GRSPW2_DMAMAXLEN_RES_MASK ) ) #define GRSPW2_DMAMAXLEN_RES( _val ) \ - ( ( ( _val ) << GRSPW2_DMAMAXLEN_RES_SHIFT ) & \ - GRSPW2_DMAMAXLEN_RES_MASK ) + ( ( ( _val ) << GRSPW2_DMAMAXLEN_RES_SHIFT ) & GRSPW2_DMAMAXLEN_RES_MASK ) /** @} */ @@ -203,28 +196,28 @@ extern "C" { */ #define GRSPW2_DMATXDESC_DESCBASEADDR_SHIFT 0 -#define GRSPW2_DMATXDESC_DESCBASEADDR_MASK 0xffffffffU -#define GRSPW2_DMATXDESC_DESCBASEADDR_GET( _reg ) \ +#define GRSPW2_DMATXDESC_DESCBASEADDR_MASK 0xffffffffU +#define GRSPW2_DMATXDESC_DESCBASEADDR_GET( _reg ) \ ( ( ( _reg ) & GRSPW2_DMATXDESC_DESCBASEADDR_MASK ) >> \ GRSPW2_DMATXDESC_DESCBASEADDR_SHIFT ) -#define GRSPW2_DMATXDESC_DESCBASEADDR_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPW2_DMATXDESC_DESCBASEADDR_MASK ) | \ +#define GRSPW2_DMATXDESC_DESCBASEADDR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_DMATXDESC_DESCBASEADDR_MASK ) | \ ( ( ( _val ) << GRSPW2_DMATXDESC_DESCBASEADDR_SHIFT ) & \ GRSPW2_DMATXDESC_DESCBASEADDR_MASK ) ) -#define GRSPW2_DMATXDESC_DESCBASEADDR( _val ) \ +#define GRSPW2_DMATXDESC_DESCBASEADDR( _val ) \ ( ( ( _val ) << GRSPW2_DMATXDESC_DESCBASEADDR_SHIFT ) & \ GRSPW2_DMATXDESC_DESCBASEADDR_MASK ) #define GRSPW2_DMATXDESC_DESCSEL_SHIFT 4 -#define GRSPW2_DMATXDESC_DESCSEL_MASK 0xfffffff0U -#define GRSPW2_DMATXDESC_DESCSEL_GET( _reg ) \ +#define GRSPW2_DMATXDESC_DESCSEL_MASK 0xfffffff0U +#define GRSPW2_DMATXDESC_DESCSEL_GET( _reg ) \ ( ( ( _reg ) & GRSPW2_DMATXDESC_DESCSEL_MASK ) >> \ GRSPW2_DMATXDESC_DESCSEL_SHIFT ) -#define GRSPW2_DMATXDESC_DESCSEL_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPW2_DMATXDESC_DESCSEL_MASK ) | \ +#define GRSPW2_DMATXDESC_DESCSEL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_DMATXDESC_DESCSEL_MASK ) | \ ( ( ( _val ) << GRSPW2_DMATXDESC_DESCSEL_SHIFT ) & \ GRSPW2_DMATXDESC_DESCSEL_MASK ) ) -#define GRSPW2_DMATXDESC_DESCSEL( _val ) \ +#define GRSPW2_DMATXDESC_DESCSEL( _val ) \ ( ( ( _val ) << GRSPW2_DMATXDESC_DESCSEL_SHIFT ) & \ GRSPW2_DMATXDESC_DESCSEL_MASK ) @@ -240,28 +233,28 @@ extern "C" { */ #define GRSPW2_DMARXDESC_DESCBASEADDR_SHIFT 10 -#define GRSPW2_DMARXDESC_DESCBASEADDR_MASK 0xfffffc00U -#define GRSPW2_DMARXDESC_DESCBASEADDR_GET( _reg ) \ +#define GRSPW2_DMARXDESC_DESCBASEADDR_MASK 0xfffffc00U +#define GRSPW2_DMARXDESC_DESCBASEADDR_GET( _reg ) \ ( ( ( _reg ) & GRSPW2_DMARXDESC_DESCBASEADDR_MASK ) >> \ GRSPW2_DMARXDESC_DESCBASEADDR_SHIFT ) -#define GRSPW2_DMARXDESC_DESCBASEADDR_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPW2_DMARXDESC_DESCBASEADDR_MASK ) | \ +#define GRSPW2_DMARXDESC_DESCBASEADDR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_DMARXDESC_DESCBASEADDR_MASK ) | \ ( ( ( _val ) << GRSPW2_DMARXDESC_DESCBASEADDR_SHIFT ) & \ GRSPW2_DMARXDESC_DESCBASEADDR_MASK ) ) -#define GRSPW2_DMARXDESC_DESCBASEADDR( _val ) \ +#define GRSPW2_DMARXDESC_DESCBASEADDR( _val ) \ ( ( ( _val ) << GRSPW2_DMARXDESC_DESCBASEADDR_SHIFT ) & \ GRSPW2_DMARXDESC_DESCBASEADDR_MASK ) #define GRSPW2_DMARXDESC_DESCSEL_SHIFT 3 -#define GRSPW2_DMARXDESC_DESCSEL_MASK 0x3f8U -#define GRSPW2_DMARXDESC_DESCSEL_GET( _reg ) \ +#define GRSPW2_DMARXDESC_DESCSEL_MASK 0x3f8U +#define GRSPW2_DMARXDESC_DESCSEL_GET( _reg ) \ ( ( ( _reg ) & GRSPW2_DMARXDESC_DESCSEL_MASK ) >> \ GRSPW2_DMARXDESC_DESCSEL_SHIFT ) -#define GRSPW2_DMARXDESC_DESCSEL_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPW2_DMARXDESC_DESCSEL_MASK ) | \ +#define GRSPW2_DMARXDESC_DESCSEL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_DMARXDESC_DESCSEL_MASK ) | \ ( ( ( _val ) << GRSPW2_DMARXDESC_DESCSEL_SHIFT ) & \ GRSPW2_DMARXDESC_DESCSEL_MASK ) ) -#define GRSPW2_DMARXDESC_DESCSEL( _val ) \ +#define GRSPW2_DMARXDESC_DESCSEL( _val ) \ ( ( ( _val ) << GRSPW2_DMARXDESC_DESCSEL_SHIFT ) & \ GRSPW2_DMARXDESC_DESCSEL_MASK ) @@ -276,30 +269,26 @@ extern "C" { */ #define GRSPW2_DMAADDR_MASK_SHIFT 8 -#define GRSPW2_DMAADDR_MASK_MASK 0xff00U +#define GRSPW2_DMAADDR_MASK_MASK 0xff00U #define GRSPW2_DMAADDR_MASK_GET( _reg ) \ - ( ( ( _reg ) & GRSPW2_DMAADDR_MASK_MASK ) >> \ - GRSPW2_DMAADDR_MASK_SHIFT ) -#define GRSPW2_DMAADDR_MASK_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPW2_DMAADDR_MASK_MASK ) | \ + ( ( ( _reg ) & GRSPW2_DMAADDR_MASK_MASK ) >> GRSPW2_DMAADDR_MASK_SHIFT ) +#define GRSPW2_DMAADDR_MASK_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_DMAADDR_MASK_MASK ) | \ ( ( ( _val ) << GRSPW2_DMAADDR_MASK_SHIFT ) & \ GRSPW2_DMAADDR_MASK_MASK ) ) #define GRSPW2_DMAADDR_MASK( _val ) \ - ( ( ( _val ) << GRSPW2_DMAADDR_MASK_SHIFT ) & \ - GRSPW2_DMAADDR_MASK_MASK ) + ( ( ( _val ) << GRSPW2_DMAADDR_MASK_SHIFT ) & GRSPW2_DMAADDR_MASK_MASK ) #define GRSPW2_DMAADDR_ADDR_SHIFT 0 -#define GRSPW2_DMAADDR_ADDR_MASK 0xffU +#define GRSPW2_DMAADDR_ADDR_MASK 0xffU #define GRSPW2_DMAADDR_ADDR_GET( _reg ) \ - ( ( ( _reg ) & GRSPW2_DMAADDR_ADDR_MASK ) >> \ - GRSPW2_DMAADDR_ADDR_SHIFT ) -#define GRSPW2_DMAADDR_ADDR_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPW2_DMAADDR_ADDR_MASK ) | \ + ( ( ( _reg ) & GRSPW2_DMAADDR_ADDR_MASK ) >> GRSPW2_DMAADDR_ADDR_SHIFT ) +#define GRSPW2_DMAADDR_ADDR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_DMAADDR_ADDR_MASK ) | \ ( ( ( _val ) << GRSPW2_DMAADDR_ADDR_SHIFT ) & \ GRSPW2_DMAADDR_ADDR_MASK ) ) #define GRSPW2_DMAADDR_ADDR( _val ) \ - ( ( ( _val ) << GRSPW2_DMAADDR_ADDR_SHIFT ) & \ - GRSPW2_DMAADDR_ADDR_MASK ) + ( ( ( _val ) << GRSPW2_DMAADDR_ADDR_SHIFT ) & GRSPW2_DMAADDR_ADDR_MASK ) /** @} */ @@ -364,17 +353,14 @@ typedef struct grspw2_dma { #define GRSPW2_CTRL_RC 0x20000000U #define GRSPW2_CTRL_NCH_SHIFT 27 -#define GRSPW2_CTRL_NCH_MASK 0x18000000U +#define GRSPW2_CTRL_NCH_MASK 0x18000000U #define GRSPW2_CTRL_NCH_GET( _reg ) \ - ( ( ( _reg ) & GRSPW2_CTRL_NCH_MASK ) >> \ - GRSPW2_CTRL_NCH_SHIFT ) -#define GRSPW2_CTRL_NCH_SET( _reg, _val ) \ + ( ( ( _reg ) & GRSPW2_CTRL_NCH_MASK ) >> GRSPW2_CTRL_NCH_SHIFT ) +#define GRSPW2_CTRL_NCH_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRSPW2_CTRL_NCH_MASK ) | \ - ( ( ( _val ) << GRSPW2_CTRL_NCH_SHIFT ) & \ - GRSPW2_CTRL_NCH_MASK ) ) + ( ( ( _val ) << GRSPW2_CTRL_NCH_SHIFT ) & GRSPW2_CTRL_NCH_MASK ) ) #define GRSPW2_CTRL_NCH( _val ) \ - ( ( ( _val ) << GRSPW2_CTRL_NCH_SHIFT ) & \ - GRSPW2_CTRL_NCH_MASK ) + ( ( ( _val ) << GRSPW2_CTRL_NCH_SHIFT ) & GRSPW2_CTRL_NCH_MASK ) #define GRSPW2_CTRL_PO 0x4000000U @@ -391,17 +377,14 @@ typedef struct grspw2_dma { #define GRSPW2_CTRL_NP 0x100000U #define GRSPW2_CTRL_PNPA_SHIFT 18 -#define GRSPW2_CTRL_PNPA_MASK 0xc0000U +#define GRSPW2_CTRL_PNPA_MASK 0xc0000U #define GRSPW2_CTRL_PNPA_GET( _reg ) \ - ( ( ( _reg ) & GRSPW2_CTRL_PNPA_MASK ) >> \ - GRSPW2_CTRL_PNPA_SHIFT ) -#define GRSPW2_CTRL_PNPA_SET( _reg, _val ) \ + ( ( ( _reg ) & GRSPW2_CTRL_PNPA_MASK ) >> GRSPW2_CTRL_PNPA_SHIFT ) +#define GRSPW2_CTRL_PNPA_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRSPW2_CTRL_PNPA_MASK ) | \ - ( ( ( _val ) << GRSPW2_CTRL_PNPA_SHIFT ) & \ - GRSPW2_CTRL_PNPA_MASK ) ) + ( ( ( _val ) << GRSPW2_CTRL_PNPA_SHIFT ) & GRSPW2_CTRL_PNPA_MASK ) ) #define GRSPW2_CTRL_PNPA( _val ) \ - ( ( ( _val ) << GRSPW2_CTRL_PNPA_SHIFT ) & \ - GRSPW2_CTRL_PNPA_MASK ) + ( ( ( _val ) << GRSPW2_CTRL_PNPA_SHIFT ) & GRSPW2_CTRL_PNPA_MASK ) #define GRSPW2_CTRL_RD 0x20000U @@ -450,32 +433,26 @@ typedef struct grspw2_dma { */ #define GRSPW2_STS_NRXD_SHIFT 26 -#define GRSPW2_STS_NRXD_MASK 0xc000000U +#define GRSPW2_STS_NRXD_MASK 0xc000000U #define GRSPW2_STS_NRXD_GET( _reg ) \ - ( ( ( _reg ) & GRSPW2_STS_NRXD_MASK ) >> \ - GRSPW2_STS_NRXD_SHIFT ) -#define GRSPW2_STS_NRXD_SET( _reg, _val ) \ + ( ( ( _reg ) & GRSPW2_STS_NRXD_MASK ) >> GRSPW2_STS_NRXD_SHIFT ) +#define GRSPW2_STS_NRXD_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRSPW2_STS_NRXD_MASK ) | \ - ( ( ( _val ) << GRSPW2_STS_NRXD_SHIFT ) & \ - GRSPW2_STS_NRXD_MASK ) ) + ( ( ( _val ) << GRSPW2_STS_NRXD_SHIFT ) & GRSPW2_STS_NRXD_MASK ) ) #define GRSPW2_STS_NRXD( _val ) \ - ( ( ( _val ) << GRSPW2_STS_NRXD_SHIFT ) & \ - GRSPW2_STS_NRXD_MASK ) + ( ( ( _val ) << GRSPW2_STS_NRXD_SHIFT ) & GRSPW2_STS_NRXD_MASK ) #define GRSPW2_STS_NTXD 0x2000000U #define GRSPW2_STS_LS_SHIFT 21 -#define GRSPW2_STS_LS_MASK 0xe00000U +#define GRSPW2_STS_LS_MASK 0xe00000U #define GRSPW2_STS_LS_GET( _reg ) \ - ( ( ( _reg ) & GRSPW2_STS_LS_MASK ) >> \ - GRSPW2_STS_LS_SHIFT ) -#define GRSPW2_STS_LS_SET( _reg, _val ) \ + ( ( ( _reg ) & GRSPW2_STS_LS_MASK ) >> GRSPW2_STS_LS_SHIFT ) +#define GRSPW2_STS_LS_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRSPW2_STS_LS_MASK ) | \ - ( ( ( _val ) << GRSPW2_STS_LS_SHIFT ) & \ - GRSPW2_STS_LS_MASK ) ) + ( ( ( _val ) << GRSPW2_STS_LS_SHIFT ) & GRSPW2_STS_LS_MASK ) ) #define GRSPW2_STS_LS( _val ) \ - ( ( ( _val ) << GRSPW2_STS_LS_SHIFT ) & \ - GRSPW2_STS_LS_MASK ) + ( ( ( _val ) << GRSPW2_STS_LS_SHIFT ) & GRSPW2_STS_LS_MASK ) #define GRSPW2_STS_AP 0x200U @@ -484,17 +461,14 @@ typedef struct grspw2_dma { #define GRSPW2_STS_IA 0x80U #define GRSPW2_STS_RES_SHIFT 5 -#define GRSPW2_STS_RES_MASK 0x60U +#define GRSPW2_STS_RES_MASK 0x60U #define GRSPW2_STS_RES_GET( _reg ) \ - ( ( ( _reg ) & GRSPW2_STS_RES_MASK ) >> \ - GRSPW2_STS_RES_SHIFT ) -#define GRSPW2_STS_RES_SET( _reg, _val ) \ + ( ( ( _reg ) & GRSPW2_STS_RES_MASK ) >> GRSPW2_STS_RES_SHIFT ) +#define GRSPW2_STS_RES_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRSPW2_STS_RES_MASK ) | \ - ( ( ( _val ) << GRSPW2_STS_RES_SHIFT ) & \ - GRSPW2_STS_RES_MASK ) ) + ( ( ( _val ) << GRSPW2_STS_RES_SHIFT ) & GRSPW2_STS_RES_MASK ) ) #define GRSPW2_STS_RES( _val ) \ - ( ( ( _val ) << GRSPW2_STS_RES_SHIFT ) & \ - GRSPW2_STS_RES_MASK ) + ( ( ( _val ) << GRSPW2_STS_RES_SHIFT ) & GRSPW2_STS_RES_MASK ) #define GRSPW2_STS_PE 0x10U @@ -517,28 +491,28 @@ typedef struct grspw2_dma { */ #define GRSPW2_DEFADDR_DEFMASK_SHIFT 8 -#define GRSPW2_DEFADDR_DEFMASK_MASK 0xff00U -#define GRSPW2_DEFADDR_DEFMASK_GET( _reg ) \ +#define GRSPW2_DEFADDR_DEFMASK_MASK 0xff00U +#define GRSPW2_DEFADDR_DEFMASK_GET( _reg ) \ ( ( ( _reg ) & GRSPW2_DEFADDR_DEFMASK_MASK ) >> \ GRSPW2_DEFADDR_DEFMASK_SHIFT ) -#define GRSPW2_DEFADDR_DEFMASK_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPW2_DEFADDR_DEFMASK_MASK ) | \ +#define GRSPW2_DEFADDR_DEFMASK_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_DEFADDR_DEFMASK_MASK ) | \ ( ( ( _val ) << GRSPW2_DEFADDR_DEFMASK_SHIFT ) & \ GRSPW2_DEFADDR_DEFMASK_MASK ) ) -#define GRSPW2_DEFADDR_DEFMASK( _val ) \ +#define GRSPW2_DEFADDR_DEFMASK( _val ) \ ( ( ( _val ) << GRSPW2_DEFADDR_DEFMASK_SHIFT ) & \ GRSPW2_DEFADDR_DEFMASK_MASK ) #define GRSPW2_DEFADDR_DEFADDR_SHIFT 0 -#define GRSPW2_DEFADDR_DEFADDR_MASK 0xffU -#define GRSPW2_DEFADDR_DEFADDR_GET( _reg ) \ +#define GRSPW2_DEFADDR_DEFADDR_MASK 0xffU +#define GRSPW2_DEFADDR_DEFADDR_GET( _reg ) \ ( ( ( _reg ) & GRSPW2_DEFADDR_DEFADDR_MASK ) >> \ GRSPW2_DEFADDR_DEFADDR_SHIFT ) -#define GRSPW2_DEFADDR_DEFADDR_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPW2_DEFADDR_DEFADDR_MASK ) | \ +#define GRSPW2_DEFADDR_DEFADDR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_DEFADDR_DEFADDR_MASK ) | \ ( ( ( _val ) << GRSPW2_DEFADDR_DEFADDR_SHIFT ) & \ GRSPW2_DEFADDR_DEFADDR_MASK ) ) -#define GRSPW2_DEFADDR_DEFADDR( _val ) \ +#define GRSPW2_DEFADDR_DEFADDR( _val ) \ ( ( ( _val ) << GRSPW2_DEFADDR_DEFADDR_SHIFT ) & \ GRSPW2_DEFADDR_DEFADDR_MASK ) @@ -553,28 +527,28 @@ typedef struct grspw2_dma { */ #define GRSPW2_CLKDIV_CLKDIVSTART_SHIFT 8 -#define GRSPW2_CLKDIV_CLKDIVSTART_MASK 0xff00U -#define GRSPW2_CLKDIV_CLKDIVSTART_GET( _reg ) \ +#define GRSPW2_CLKDIV_CLKDIVSTART_MASK 0xff00U +#define GRSPW2_CLKDIV_CLKDIVSTART_GET( _reg ) \ ( ( ( _reg ) & GRSPW2_CLKDIV_CLKDIVSTART_MASK ) >> \ GRSPW2_CLKDIV_CLKDIVSTART_SHIFT ) -#define GRSPW2_CLKDIV_CLKDIVSTART_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPW2_CLKDIV_CLKDIVSTART_MASK ) | \ +#define GRSPW2_CLKDIV_CLKDIVSTART_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_CLKDIV_CLKDIVSTART_MASK ) | \ ( ( ( _val ) << GRSPW2_CLKDIV_CLKDIVSTART_SHIFT ) & \ GRSPW2_CLKDIV_CLKDIVSTART_MASK ) ) -#define GRSPW2_CLKDIV_CLKDIVSTART( _val ) \ +#define GRSPW2_CLKDIV_CLKDIVSTART( _val ) \ ( ( ( _val ) << GRSPW2_CLKDIV_CLKDIVSTART_SHIFT ) & \ GRSPW2_CLKDIV_CLKDIVSTART_MASK ) #define GRSPW2_CLKDIV_CLKDIVRUN_SHIFT 0 -#define GRSPW2_CLKDIV_CLKDIVRUN_MASK 0xffU -#define GRSPW2_CLKDIV_CLKDIVRUN_GET( _reg ) \ +#define GRSPW2_CLKDIV_CLKDIVRUN_MASK 0xffU +#define GRSPW2_CLKDIV_CLKDIVRUN_GET( _reg ) \ ( ( ( _reg ) & GRSPW2_CLKDIV_CLKDIVRUN_MASK ) >> \ GRSPW2_CLKDIV_CLKDIVRUN_SHIFT ) -#define GRSPW2_CLKDIV_CLKDIVRUN_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPW2_CLKDIV_CLKDIVRUN_MASK ) | \ +#define GRSPW2_CLKDIV_CLKDIVRUN_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_CLKDIV_CLKDIVRUN_MASK ) | \ ( ( ( _val ) << GRSPW2_CLKDIV_CLKDIVRUN_SHIFT ) & \ GRSPW2_CLKDIV_CLKDIVRUN_MASK ) ) -#define GRSPW2_CLKDIV_CLKDIVRUN( _val ) \ +#define GRSPW2_CLKDIV_CLKDIVRUN( _val ) \ ( ( ( _val ) << GRSPW2_CLKDIV_CLKDIVRUN_SHIFT ) & \ GRSPW2_CLKDIV_CLKDIVRUN_MASK ) @@ -589,17 +563,15 @@ typedef struct grspw2_dma { */ #define GRSPW2_DKEY_DESTKEY_SHIFT 0 -#define GRSPW2_DKEY_DESTKEY_MASK 0xffU +#define GRSPW2_DKEY_DESTKEY_MASK 0xffU #define GRSPW2_DKEY_DESTKEY_GET( _reg ) \ - ( ( ( _reg ) & GRSPW2_DKEY_DESTKEY_MASK ) >> \ - GRSPW2_DKEY_DESTKEY_SHIFT ) -#define GRSPW2_DKEY_DESTKEY_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPW2_DKEY_DESTKEY_MASK ) | \ + ( ( ( _reg ) & GRSPW2_DKEY_DESTKEY_MASK ) >> GRSPW2_DKEY_DESTKEY_SHIFT ) +#define GRSPW2_DKEY_DESTKEY_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_DKEY_DESTKEY_MASK ) | \ ( ( ( _val ) << GRSPW2_DKEY_DESTKEY_SHIFT ) & \ GRSPW2_DKEY_DESTKEY_MASK ) ) #define GRSPW2_DKEY_DESTKEY( _val ) \ - ( ( ( _val ) << GRSPW2_DKEY_DESTKEY_SHIFT ) & \ - GRSPW2_DKEY_DESTKEY_MASK ) + ( ( ( _val ) << GRSPW2_DKEY_DESTKEY_SHIFT ) & GRSPW2_DKEY_DESTKEY_MASK ) /** @} */ @@ -612,30 +584,24 @@ typedef struct grspw2_dma { */ #define GRSPW2_TC_TCTRL_SHIFT 6 -#define GRSPW2_TC_TCTRL_MASK 0xc0U +#define GRSPW2_TC_TCTRL_MASK 0xc0U #define GRSPW2_TC_TCTRL_GET( _reg ) \ - ( ( ( _reg ) & GRSPW2_TC_TCTRL_MASK ) >> \ - GRSPW2_TC_TCTRL_SHIFT ) -#define GRSPW2_TC_TCTRL_SET( _reg, _val ) \ + ( ( ( _reg ) & GRSPW2_TC_TCTRL_MASK ) >> GRSPW2_TC_TCTRL_SHIFT ) +#define GRSPW2_TC_TCTRL_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRSPW2_TC_TCTRL_MASK ) | \ - ( ( ( _val ) << GRSPW2_TC_TCTRL_SHIFT ) & \ - GRSPW2_TC_TCTRL_MASK ) ) + ( ( ( _val ) << GRSPW2_TC_TCTRL_SHIFT ) & GRSPW2_TC_TCTRL_MASK ) ) #define GRSPW2_TC_TCTRL( _val ) \ - ( ( ( _val ) << GRSPW2_TC_TCTRL_SHIFT ) & \ - GRSPW2_TC_TCTRL_MASK ) + ( ( ( _val ) << GRSPW2_TC_TCTRL_SHIFT ) & GRSPW2_TC_TCTRL_MASK ) #define GRSPW2_TC_TIMECNT_SHIFT 0 -#define GRSPW2_TC_TIMECNT_MASK 0x3fU +#define GRSPW2_TC_TIMECNT_MASK 0x3fU #define GRSPW2_TC_TIMECNT_GET( _reg ) \ - ( ( ( _reg ) & GRSPW2_TC_TIMECNT_MASK ) >> \ - GRSPW2_TC_TIMECNT_SHIFT ) -#define GRSPW2_TC_TIMECNT_SET( _reg, _val ) \ + ( ( ( _reg ) & GRSPW2_TC_TIMECNT_MASK ) >> GRSPW2_TC_TIMECNT_SHIFT ) +#define GRSPW2_TC_TIMECNT_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRSPW2_TC_TIMECNT_MASK ) | \ - ( ( ( _val ) << GRSPW2_TC_TIMECNT_SHIFT ) & \ - GRSPW2_TC_TIMECNT_MASK ) ) + ( ( ( _val ) << GRSPW2_TC_TIMECNT_SHIFT ) & GRSPW2_TC_TIMECNT_MASK ) ) #define GRSPW2_TC_TIMECNT( _val ) \ - ( ( ( _val ) << GRSPW2_TC_TIMECNT_SHIFT ) & \ - GRSPW2_TC_TIMECNT_MASK ) + ( ( ( _val ) << GRSPW2_TC_TIMECNT_SHIFT ) & GRSPW2_TC_TIMECNT_MASK ) /** @} */ @@ -648,17 +614,15 @@ typedef struct grspw2_dma { */ #define GRSPW2_INTCTRL_INTNUM_SHIFT 26 -#define GRSPW2_INTCTRL_INTNUM_MASK 0xfc000000U +#define GRSPW2_INTCTRL_INTNUM_MASK 0xfc000000U #define GRSPW2_INTCTRL_INTNUM_GET( _reg ) \ - ( ( ( _reg ) & GRSPW2_INTCTRL_INTNUM_MASK ) >> \ - GRSPW2_INTCTRL_INTNUM_SHIFT ) -#define GRSPW2_INTCTRL_INTNUM_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPW2_INTCTRL_INTNUM_MASK ) | \ + ( ( ( _reg ) & GRSPW2_INTCTRL_INTNUM_MASK ) >> GRSPW2_INTCTRL_INTNUM_SHIFT ) +#define GRSPW2_INTCTRL_INTNUM_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_INTCTRL_INTNUM_MASK ) | \ ( ( ( _val ) << GRSPW2_INTCTRL_INTNUM_SHIFT ) & \ GRSPW2_INTCTRL_INTNUM_MASK ) ) #define GRSPW2_INTCTRL_INTNUM( _val ) \ - ( ( ( _val ) << GRSPW2_INTCTRL_INTNUM_SHIFT ) & \ - GRSPW2_INTCTRL_INTNUM_MASK ) + ( ( ( _val ) << GRSPW2_INTCTRL_INTNUM_SHIFT ) & GRSPW2_INTCTRL_INTNUM_MASK ) #define GRSPW2_INTCTRL_RS 0x2000000U @@ -669,17 +633,14 @@ typedef struct grspw2_dma { #define GRSPW2_INTCTRL_RES 0x2U #define GRSPW2_INTCTRL_TQ_SHIFT 21 -#define GRSPW2_INTCTRL_TQ_MASK 0x600000U +#define GRSPW2_INTCTRL_TQ_MASK 0x600000U #define GRSPW2_INTCTRL_TQ_GET( _reg ) \ - ( ( ( _reg ) & GRSPW2_INTCTRL_TQ_MASK ) >> \ - GRSPW2_INTCTRL_TQ_SHIFT ) -#define GRSPW2_INTCTRL_TQ_SET( _reg, _val ) \ + ( ( ( _reg ) & GRSPW2_INTCTRL_TQ_MASK ) >> GRSPW2_INTCTRL_TQ_SHIFT ) +#define GRSPW2_INTCTRL_TQ_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRSPW2_INTCTRL_TQ_MASK ) | \ - ( ( ( _val ) << GRSPW2_INTCTRL_TQ_SHIFT ) & \ - GRSPW2_INTCTRL_TQ_MASK ) ) + ( ( ( _val ) << GRSPW2_INTCTRL_TQ_SHIFT ) & GRSPW2_INTCTRL_TQ_MASK ) ) #define GRSPW2_INTCTRL_TQ( _val ) \ - ( ( ( _val ) << GRSPW2_INTCTRL_TQ_SHIFT ) & \ - GRSPW2_INTCTRL_TQ_MASK ) + ( ( ( _val ) << GRSPW2_INTCTRL_TQ_SHIFT ) & GRSPW2_INTCTRL_TQ_MASK ) #define GRSPW2_INTCTRL_AQ 0x100000U @@ -688,17 +649,14 @@ typedef struct grspw2_dma { #define GRSPW2_INTCTRL_RES 0x40000U #define GRSPW2_INTCTRL_AA_SHIFT 16 -#define GRSPW2_INTCTRL_AA_MASK 0x30000U +#define GRSPW2_INTCTRL_AA_MASK 0x30000U #define GRSPW2_INTCTRL_AA_GET( _reg ) \ - ( ( ( _reg ) & GRSPW2_INTCTRL_AA_MASK ) >> \ - GRSPW2_INTCTRL_AA_SHIFT ) -#define GRSPW2_INTCTRL_AA_SET( _reg, _val ) \ + ( ( ( _reg ) & GRSPW2_INTCTRL_AA_MASK ) >> GRSPW2_INTCTRL_AA_SHIFT ) +#define GRSPW2_INTCTRL_AA_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRSPW2_INTCTRL_AA_MASK ) | \ - ( ( ( _val ) << GRSPW2_INTCTRL_AA_SHIFT ) & \ - GRSPW2_INTCTRL_AA_MASK ) ) + ( ( ( _val ) << GRSPW2_INTCTRL_AA_SHIFT ) & GRSPW2_INTCTRL_AA_MASK ) ) #define GRSPW2_INTCTRL_AA( _val ) \ - ( ( ( _val ) << GRSPW2_INTCTRL_AA_SHIFT ) & \ - GRSPW2_INTCTRL_AA_MASK ) + ( ( ( _val ) << GRSPW2_INTCTRL_AA_SHIFT ) & GRSPW2_INTCTRL_AA_MASK ) #define GRSPW2_INTCTRL_AT 0x8000U @@ -707,17 +665,14 @@ typedef struct grspw2_dma { #define GRSPW2_INTCTRL_RES 0x2000U #define GRSPW2_INTCTRL_ID_SHIFT 8 -#define GRSPW2_INTCTRL_ID_MASK 0x1f00U +#define GRSPW2_INTCTRL_ID_MASK 0x1f00U #define GRSPW2_INTCTRL_ID_GET( _reg ) \ - ( ( ( _reg ) & GRSPW2_INTCTRL_ID_MASK ) >> \ - GRSPW2_INTCTRL_ID_SHIFT ) -#define GRSPW2_INTCTRL_ID_SET( _reg, _val ) \ + ( ( ( _reg ) & GRSPW2_INTCTRL_ID_MASK ) >> GRSPW2_INTCTRL_ID_SHIFT ) +#define GRSPW2_INTCTRL_ID_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRSPW2_INTCTRL_ID_MASK ) | \ - ( ( ( _val ) << GRSPW2_INTCTRL_ID_SHIFT ) & \ - GRSPW2_INTCTRL_ID_MASK ) ) + ( ( ( _val ) << GRSPW2_INTCTRL_ID_SHIFT ) & GRSPW2_INTCTRL_ID_MASK ) ) #define GRSPW2_INTCTRL_ID( _val ) \ - ( ( ( _val ) << GRSPW2_INTCTRL_ID_SHIFT ) & \ - GRSPW2_INTCTRL_ID_MASK ) + ( ( ( _val ) << GRSPW2_INTCTRL_ID_SHIFT ) & GRSPW2_INTCTRL_ID_MASK ) #define GRSPW2_INTCTRL_II 0x80U @@ -734,17 +689,14 @@ typedef struct grspw2_dma { */ #define GRSPW2_INTRX_RXIRQ_SHIFT 0 -#define GRSPW2_INTRX_RXIRQ_MASK 0xffffffffU +#define GRSPW2_INTRX_RXIRQ_MASK 0xffffffffU #define GRSPW2_INTRX_RXIRQ_GET( _reg ) \ - ( ( ( _reg ) & GRSPW2_INTRX_RXIRQ_MASK ) >> \ - GRSPW2_INTRX_RXIRQ_SHIFT ) -#define GRSPW2_INTRX_RXIRQ_SET( _reg, _val ) \ + ( ( ( _reg ) & GRSPW2_INTRX_RXIRQ_MASK ) >> GRSPW2_INTRX_RXIRQ_SHIFT ) +#define GRSPW2_INTRX_RXIRQ_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRSPW2_INTRX_RXIRQ_MASK ) | \ - ( ( ( _val ) << GRSPW2_INTRX_RXIRQ_SHIFT ) & \ - GRSPW2_INTRX_RXIRQ_MASK ) ) + ( ( ( _val ) << GRSPW2_INTRX_RXIRQ_SHIFT ) & GRSPW2_INTRX_RXIRQ_MASK ) ) #define GRSPW2_INTRX_RXIRQ( _val ) \ - ( ( ( _val ) << GRSPW2_INTRX_RXIRQ_SHIFT ) & \ - GRSPW2_INTRX_RXIRQ_MASK ) + ( ( ( _val ) << GRSPW2_INTRX_RXIRQ_SHIFT ) & GRSPW2_INTRX_RXIRQ_MASK ) /** @} */ @@ -757,17 +709,14 @@ typedef struct grspw2_dma { */ #define GRSPW2_INTTO_INTTO_SHIFT 0 -#define GRSPW2_INTTO_INTTO_MASK 0xffffffffU +#define GRSPW2_INTTO_INTTO_MASK 0xffffffffU #define GRSPW2_INTTO_INTTO_GET( _reg ) \ - ( ( ( _reg ) & GRSPW2_INTTO_INTTO_MASK ) >> \ - GRSPW2_INTTO_INTTO_SHIFT ) -#define GRSPW2_INTTO_INTTO_SET( _reg, _val ) \ + ( ( ( _reg ) & GRSPW2_INTTO_INTTO_MASK ) >> GRSPW2_INTTO_INTTO_SHIFT ) +#define GRSPW2_INTTO_INTTO_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRSPW2_INTTO_INTTO_MASK ) | \ - ( ( ( _val ) << GRSPW2_INTTO_INTTO_SHIFT ) & \ - GRSPW2_INTTO_INTTO_MASK ) ) + ( ( ( _val ) << GRSPW2_INTTO_INTTO_SHIFT ) & GRSPW2_INTTO_INTTO_MASK ) ) #define GRSPW2_INTTO_INTTO( _val ) \ - ( ( ( _val ) << GRSPW2_INTTO_INTTO_SHIFT ) & \ - GRSPW2_INTTO_INTTO_MASK ) + ( ( ( _val ) << GRSPW2_INTTO_INTTO_SHIFT ) & GRSPW2_INTTO_INTTO_MASK ) /** @} */ @@ -780,15 +729,15 @@ typedef struct grspw2_dma { */ #define GRSPW2_INTTOEXT_INTTOEXT_SHIFT 0 -#define GRSPW2_INTTOEXT_INTTOEXT_MASK 0xffffffffU -#define GRSPW2_INTTOEXT_INTTOEXT_GET( _reg ) \ +#define GRSPW2_INTTOEXT_INTTOEXT_MASK 0xffffffffU +#define GRSPW2_INTTOEXT_INTTOEXT_GET( _reg ) \ ( ( ( _reg ) & GRSPW2_INTTOEXT_INTTOEXT_MASK ) >> \ GRSPW2_INTTOEXT_INTTOEXT_SHIFT ) -#define GRSPW2_INTTOEXT_INTTOEXT_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPW2_INTTOEXT_INTTOEXT_MASK ) | \ +#define GRSPW2_INTTOEXT_INTTOEXT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_INTTOEXT_INTTOEXT_MASK ) | \ ( ( ( _val ) << GRSPW2_INTTOEXT_INTTOEXT_SHIFT ) & \ GRSPW2_INTTOEXT_INTTOEXT_MASK ) ) -#define GRSPW2_INTTOEXT_INTTOEXT( _val ) \ +#define GRSPW2_INTTOEXT_INTTOEXT( _val ) \ ( ( ( _val ) << GRSPW2_INTTOEXT_INTTOEXT_SHIFT ) & \ GRSPW2_INTTOEXT_INTTOEXT_MASK ) @@ -803,17 +752,15 @@ typedef struct grspw2_dma { */ #define GRSPW2_TICKMASK_MASK_SHIFT 0 -#define GRSPW2_TICKMASK_MASK_MASK 0xffffffffU +#define GRSPW2_TICKMASK_MASK_MASK 0xffffffffU #define GRSPW2_TICKMASK_MASK_GET( _reg ) \ - ( ( ( _reg ) & GRSPW2_TICKMASK_MASK_MASK ) >> \ - GRSPW2_TICKMASK_MASK_SHIFT ) -#define GRSPW2_TICKMASK_MASK_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPW2_TICKMASK_MASK_MASK ) | \ + ( ( ( _reg ) & GRSPW2_TICKMASK_MASK_MASK ) >> GRSPW2_TICKMASK_MASK_SHIFT ) +#define GRSPW2_TICKMASK_MASK_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_TICKMASK_MASK_MASK ) | \ ( ( ( _val ) << GRSPW2_TICKMASK_MASK_SHIFT ) & \ GRSPW2_TICKMASK_MASK_MASK ) ) #define GRSPW2_TICKMASK_MASK( _val ) \ - ( ( ( _val ) << GRSPW2_TICKMASK_MASK_SHIFT ) & \ - GRSPW2_TICKMASK_MASK_MASK ) + ( ( ( _val ) << GRSPW2_TICKMASK_MASK_SHIFT ) & GRSPW2_TICKMASK_MASK_MASK ) /** @} */ @@ -827,15 +774,15 @@ typedef struct grspw2_dma { */ #define GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_SHIFT 0 -#define GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_MASK 0xffffffffU -#define GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_GET( _reg ) \ +#define GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_MASK 0xffffffffU +#define GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_GET( _reg ) \ ( ( ( _reg ) & GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_MASK ) >> \ GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_SHIFT ) -#define GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_MASK ) | \ +#define GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_MASK ) | \ ( ( ( _val ) << GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_SHIFT ) & \ GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_MASK ) ) -#define GRSPW2_AUTOACK_TICKMASKEXT_AAMASK( _val ) \ +#define GRSPW2_AUTOACK_TICKMASKEXT_AAMASK( _val ) \ ( ( ( _val ) << GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_SHIFT ) & \ GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_MASK ) @@ -851,69 +798,59 @@ typedef struct grspw2_dma { */ #define GRSPW2_INTCFG_INTNUM3_SHIFT 26 -#define GRSPW2_INTCFG_INTNUM3_MASK 0xfc000000U +#define GRSPW2_INTCFG_INTNUM3_MASK 0xfc000000U #define GRSPW2_INTCFG_INTNUM3_GET( _reg ) \ - ( ( ( _reg ) & GRSPW2_INTCFG_INTNUM3_MASK ) >> \ - GRSPW2_INTCFG_INTNUM3_SHIFT ) -#define GRSPW2_INTCFG_INTNUM3_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPW2_INTCFG_INTNUM3_MASK ) | \ + ( ( ( _reg ) & GRSPW2_INTCFG_INTNUM3_MASK ) >> GRSPW2_INTCFG_INTNUM3_SHIFT ) +#define GRSPW2_INTCFG_INTNUM3_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_INTCFG_INTNUM3_MASK ) | \ ( ( ( _val ) << GRSPW2_INTCFG_INTNUM3_SHIFT ) & \ GRSPW2_INTCFG_INTNUM3_MASK ) ) #define GRSPW2_INTCFG_INTNUM3( _val ) \ - ( ( ( _val ) << GRSPW2_INTCFG_INTNUM3_SHIFT ) & \ - GRSPW2_INTCFG_INTNUM3_MASK ) + ( ( ( _val ) << GRSPW2_INTCFG_INTNUM3_SHIFT ) & GRSPW2_INTCFG_INTNUM3_MASK ) #define GRSPW2_INTCFG_INTNUM2_SHIFT 20 -#define GRSPW2_INTCFG_INTNUM2_MASK 0x3f00000U +#define GRSPW2_INTCFG_INTNUM2_MASK 0x3f00000U #define GRSPW2_INTCFG_INTNUM2_GET( _reg ) \ - ( ( ( _reg ) & GRSPW2_INTCFG_INTNUM2_MASK ) >> \ - GRSPW2_INTCFG_INTNUM2_SHIFT ) -#define GRSPW2_INTCFG_INTNUM2_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPW2_INTCFG_INTNUM2_MASK ) | \ + ( ( ( _reg ) & GRSPW2_INTCFG_INTNUM2_MASK ) >> GRSPW2_INTCFG_INTNUM2_SHIFT ) +#define GRSPW2_INTCFG_INTNUM2_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_INTCFG_INTNUM2_MASK ) | \ ( ( ( _val ) << GRSPW2_INTCFG_INTNUM2_SHIFT ) & \ GRSPW2_INTCFG_INTNUM2_MASK ) ) #define GRSPW2_INTCFG_INTNUM2( _val ) \ - ( ( ( _val ) << GRSPW2_INTCFG_INTNUM2_SHIFT ) & \ - GRSPW2_INTCFG_INTNUM2_MASK ) + ( ( ( _val ) << GRSPW2_INTCFG_INTNUM2_SHIFT ) & GRSPW2_INTCFG_INTNUM2_MASK ) #define GRSPW2_INTCFG_INTNUM1_SHIFT 14 -#define GRSPW2_INTCFG_INTNUM1_MASK 0xfc000U +#define GRSPW2_INTCFG_INTNUM1_MASK 0xfc000U #define GRSPW2_INTCFG_INTNUM1_GET( _reg ) \ - ( ( ( _reg ) & GRSPW2_INTCFG_INTNUM1_MASK ) >> \ - GRSPW2_INTCFG_INTNUM1_SHIFT ) -#define GRSPW2_INTCFG_INTNUM1_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPW2_INTCFG_INTNUM1_MASK ) | \ + ( ( ( _reg ) & GRSPW2_INTCFG_INTNUM1_MASK ) >> GRSPW2_INTCFG_INTNUM1_SHIFT ) +#define GRSPW2_INTCFG_INTNUM1_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_INTCFG_INTNUM1_MASK ) | \ ( ( ( _val ) << GRSPW2_INTCFG_INTNUM1_SHIFT ) & \ GRSPW2_INTCFG_INTNUM1_MASK ) ) #define GRSPW2_INTCFG_INTNUM1( _val ) \ - ( ( ( _val ) << GRSPW2_INTCFG_INTNUM1_SHIFT ) & \ - GRSPW2_INTCFG_INTNUM1_MASK ) + ( ( ( _val ) << GRSPW2_INTCFG_INTNUM1_SHIFT ) & GRSPW2_INTCFG_INTNUM1_MASK ) #define GRSPW2_INTCFG_INTNUM0_SHIFT 8 -#define GRSPW2_INTCFG_INTNUM0_MASK 0x3f00U +#define GRSPW2_INTCFG_INTNUM0_MASK 0x3f00U #define GRSPW2_INTCFG_INTNUM0_GET( _reg ) \ - ( ( ( _reg ) & GRSPW2_INTCFG_INTNUM0_MASK ) >> \ - GRSPW2_INTCFG_INTNUM0_SHIFT ) -#define GRSPW2_INTCFG_INTNUM0_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPW2_INTCFG_INTNUM0_MASK ) | \ + ( ( ( _reg ) & GRSPW2_INTCFG_INTNUM0_MASK ) >> GRSPW2_INTCFG_INTNUM0_SHIFT ) +#define GRSPW2_INTCFG_INTNUM0_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_INTCFG_INTNUM0_MASK ) | \ ( ( ( _val ) << GRSPW2_INTCFG_INTNUM0_SHIFT ) & \ GRSPW2_INTCFG_INTNUM0_MASK ) ) #define GRSPW2_INTCFG_INTNUM0( _val ) \ - ( ( ( _val ) << GRSPW2_INTCFG_INTNUM0_SHIFT ) & \ - GRSPW2_INTCFG_INTNUM0_MASK ) + ( ( ( _val ) << GRSPW2_INTCFG_INTNUM0_SHIFT ) & GRSPW2_INTCFG_INTNUM0_MASK ) #define GRSPW2_INTCFG_NUMINT_SHIFT 4 -#define GRSPW2_INTCFG_NUMINT_MASK 0xf0U +#define GRSPW2_INTCFG_NUMINT_MASK 0xf0U #define GRSPW2_INTCFG_NUMINT_GET( _reg ) \ - ( ( ( _reg ) & GRSPW2_INTCFG_NUMINT_MASK ) >> \ - GRSPW2_INTCFG_NUMINT_SHIFT ) -#define GRSPW2_INTCFG_NUMINT_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPW2_INTCFG_NUMINT_MASK ) | \ + ( ( ( _reg ) & GRSPW2_INTCFG_NUMINT_MASK ) >> GRSPW2_INTCFG_NUMINT_SHIFT ) +#define GRSPW2_INTCFG_NUMINT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_INTCFG_NUMINT_MASK ) | \ ( ( ( _val ) << GRSPW2_INTCFG_NUMINT_SHIFT ) & \ GRSPW2_INTCFG_NUMINT_MASK ) ) #define GRSPW2_INTCFG_NUMINT( _val ) \ - ( ( ( _val ) << GRSPW2_INTCFG_NUMINT_SHIFT ) & \ - GRSPW2_INTCFG_NUMINT_MASK ) + ( ( ( _val ) << GRSPW2_INTCFG_NUMINT_SHIFT ) & GRSPW2_INTCFG_NUMINT_MASK ) #define GRSPW2_INTCFG_PR 0x8U @@ -934,17 +871,14 @@ typedef struct grspw2_dma { */ #define GRSPW2_ISR_ISR_SHIFT 0 -#define GRSPW2_ISR_ISR_MASK 0xffffffffU +#define GRSPW2_ISR_ISR_MASK 0xffffffffU #define GRSPW2_ISR_ISR_GET( _reg ) \ - ( ( ( _reg ) & GRSPW2_ISR_ISR_MASK ) >> \ - GRSPW2_ISR_ISR_SHIFT ) -#define GRSPW2_ISR_ISR_SET( _reg, _val ) \ + ( ( ( _reg ) & GRSPW2_ISR_ISR_MASK ) >> GRSPW2_ISR_ISR_SHIFT ) +#define GRSPW2_ISR_ISR_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRSPW2_ISR_ISR_MASK ) | \ - ( ( ( _val ) << GRSPW2_ISR_ISR_SHIFT ) & \ - GRSPW2_ISR_ISR_MASK ) ) + ( ( ( _val ) << GRSPW2_ISR_ISR_SHIFT ) & GRSPW2_ISR_ISR_MASK ) ) #define GRSPW2_ISR_ISR( _val ) \ - ( ( ( _val ) << GRSPW2_ISR_ISR_SHIFT ) & \ - GRSPW2_ISR_ISR_MASK ) + ( ( ( _val ) << GRSPW2_ISR_ISR_SHIFT ) & GRSPW2_ISR_ISR_MASK ) /** @} */ @@ -958,17 +892,14 @@ typedef struct grspw2_dma { */ #define GRSPW2_ISREXT_ISR_SHIFT 0 -#define GRSPW2_ISREXT_ISR_MASK 0xffffffffU +#define GRSPW2_ISREXT_ISR_MASK 0xffffffffU #define GRSPW2_ISREXT_ISR_GET( _reg ) \ - ( ( ( _reg ) & GRSPW2_ISREXT_ISR_MASK ) >> \ - GRSPW2_ISREXT_ISR_SHIFT ) -#define GRSPW2_ISREXT_ISR_SET( _reg, _val ) \ + ( ( ( _reg ) & GRSPW2_ISREXT_ISR_MASK ) >> GRSPW2_ISREXT_ISR_SHIFT ) +#define GRSPW2_ISREXT_ISR_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRSPW2_ISREXT_ISR_MASK ) | \ - ( ( ( _val ) << GRSPW2_ISREXT_ISR_SHIFT ) & \ - GRSPW2_ISREXT_ISR_MASK ) ) + ( ( ( _val ) << GRSPW2_ISREXT_ISR_SHIFT ) & GRSPW2_ISREXT_ISR_MASK ) ) #define GRSPW2_ISREXT_ISR( _val ) \ - ( ( ( _val ) << GRSPW2_ISREXT_ISR_SHIFT ) & \ - GRSPW2_ISREXT_ISR_MASK ) + ( ( ( _val ) << GRSPW2_ISREXT_ISR_SHIFT ) & GRSPW2_ISREXT_ISR_MASK ) /** @} */ @@ -984,17 +915,15 @@ typedef struct grspw2_dma { #define GRSPW2_PRESCALER_R 0x80000000U #define GRSPW2_PRESCALER_RL_SHIFT 0 -#define GRSPW2_PRESCALER_RL_MASK 0x7fffffffU +#define GRSPW2_PRESCALER_RL_MASK 0x7fffffffU #define GRSPW2_PRESCALER_RL_GET( _reg ) \ - ( ( ( _reg ) & GRSPW2_PRESCALER_RL_MASK ) >> \ - GRSPW2_PRESCALER_RL_SHIFT ) -#define GRSPW2_PRESCALER_RL_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPW2_PRESCALER_RL_MASK ) | \ + ( ( ( _reg ) & GRSPW2_PRESCALER_RL_MASK ) >> GRSPW2_PRESCALER_RL_SHIFT ) +#define GRSPW2_PRESCALER_RL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_PRESCALER_RL_MASK ) | \ ( ( ( _val ) << GRSPW2_PRESCALER_RL_SHIFT ) & \ GRSPW2_PRESCALER_RL_MASK ) ) #define GRSPW2_PRESCALER_RL( _val ) \ - ( ( ( _val ) << GRSPW2_PRESCALER_RL_SHIFT ) & \ - GRSPW2_PRESCALER_RL_MASK ) + ( ( ( _val ) << GRSPW2_PRESCALER_RL_SHIFT ) & GRSPW2_PRESCALER_RL_MASK ) /** @} */ @@ -1010,17 +939,14 @@ typedef struct grspw2_dma { #define GRSPW2_ISRTIMER_EN 0x80000000U #define GRSPW2_ISRTIMER_RL_SHIFT 0 -#define GRSPW2_ISRTIMER_RL_MASK 0x7fffffffU +#define GRSPW2_ISRTIMER_RL_MASK 0x7fffffffU #define GRSPW2_ISRTIMER_RL_GET( _reg ) \ - ( ( ( _reg ) & GRSPW2_ISRTIMER_RL_MASK ) >> \ - GRSPW2_ISRTIMER_RL_SHIFT ) -#define GRSPW2_ISRTIMER_RL_SET( _reg, _val ) \ + ( ( ( _reg ) & GRSPW2_ISRTIMER_RL_MASK ) >> GRSPW2_ISRTIMER_RL_SHIFT ) +#define GRSPW2_ISRTIMER_RL_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRSPW2_ISRTIMER_RL_MASK ) | \ - ( ( ( _val ) << GRSPW2_ISRTIMER_RL_SHIFT ) & \ - GRSPW2_ISRTIMER_RL_MASK ) ) + ( ( ( _val ) << GRSPW2_ISRTIMER_RL_SHIFT ) & GRSPW2_ISRTIMER_RL_MASK ) ) #define GRSPW2_ISRTIMER_RL( _val ) \ - ( ( ( _val ) << GRSPW2_ISRTIMER_RL_SHIFT ) & \ - GRSPW2_ISRTIMER_RL_MASK ) + ( ( ( _val ) << GRSPW2_ISRTIMER_RL_SHIFT ) & GRSPW2_ISRTIMER_RL_MASK ) /** @} */ @@ -1036,17 +962,14 @@ typedef struct grspw2_dma { #define GRSPW2_IATIMER_EN 0x80000000U #define GRSPW2_IATIMER_RL_SHIFT 0 -#define GRSPW2_IATIMER_RL_MASK 0x7fffffffU +#define GRSPW2_IATIMER_RL_MASK 0x7fffffffU #define GRSPW2_IATIMER_RL_GET( _reg ) \ - ( ( ( _reg ) & GRSPW2_IATIMER_RL_MASK ) >> \ - GRSPW2_IATIMER_RL_SHIFT ) -#define GRSPW2_IATIMER_RL_SET( _reg, _val ) \ + ( ( ( _reg ) & GRSPW2_IATIMER_RL_MASK ) >> GRSPW2_IATIMER_RL_SHIFT ) +#define GRSPW2_IATIMER_RL_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRSPW2_IATIMER_RL_MASK ) | \ - ( ( ( _val ) << GRSPW2_IATIMER_RL_SHIFT ) & \ - GRSPW2_IATIMER_RL_MASK ) ) + ( ( ( _val ) << GRSPW2_IATIMER_RL_SHIFT ) & GRSPW2_IATIMER_RL_MASK ) ) #define GRSPW2_IATIMER_RL( _val ) \ - ( ( ( _val ) << GRSPW2_IATIMER_RL_SHIFT ) & \ - GRSPW2_IATIMER_RL_MASK ) + ( ( ( _val ) << GRSPW2_IATIMER_RL_SHIFT ) & GRSPW2_IATIMER_RL_MASK ) /** @} */ @@ -1062,17 +985,14 @@ typedef struct grspw2_dma { #define GRSPW2_ICTIMER_EN 0x80000000U #define GRSPW2_ICTIMER_RL_SHIFT 0 -#define GRSPW2_ICTIMER_RL_MASK 0x7fffffffU +#define GRSPW2_ICTIMER_RL_MASK 0x7fffffffU #define GRSPW2_ICTIMER_RL_GET( _reg ) \ - ( ( ( _reg ) & GRSPW2_ICTIMER_RL_MASK ) >> \ - GRSPW2_ICTIMER_RL_SHIFT ) -#define GRSPW2_ICTIMER_RL_SET( _reg, _val ) \ + ( ( ( _reg ) & GRSPW2_ICTIMER_RL_MASK ) >> GRSPW2_ICTIMER_RL_SHIFT ) +#define GRSPW2_ICTIMER_RL_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRSPW2_ICTIMER_RL_MASK ) | \ - ( ( ( _val ) << GRSPW2_ICTIMER_RL_SHIFT ) & \ - GRSPW2_ICTIMER_RL_MASK ) ) + ( ( ( _val ) << GRSPW2_ICTIMER_RL_SHIFT ) & GRSPW2_ICTIMER_RL_MASK ) ) #define GRSPW2_ICTIMER_RL( _val ) \ - ( ( ( _val ) << GRSPW2_ICTIMER_RL_SHIFT ) & \ - GRSPW2_ICTIMER_RL_MASK ) + ( ( ( _val ) << GRSPW2_ICTIMER_RL_SHIFT ) & GRSPW2_ICTIMER_RL_MASK ) /** @} */ @@ -1086,30 +1006,26 @@ typedef struct grspw2_dma { */ #define GRSPW2_PNPVEND_VEND_SHIFT 16 -#define GRSPW2_PNPVEND_VEND_MASK 0xffff0000U +#define GRSPW2_PNPVEND_VEND_MASK 0xffff0000U #define GRSPW2_PNPVEND_VEND_GET( _reg ) \ - ( ( ( _reg ) & GRSPW2_PNPVEND_VEND_MASK ) >> \ - GRSPW2_PNPVEND_VEND_SHIFT ) -#define GRSPW2_PNPVEND_VEND_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPW2_PNPVEND_VEND_MASK ) | \ + ( ( ( _reg ) & GRSPW2_PNPVEND_VEND_MASK ) >> GRSPW2_PNPVEND_VEND_SHIFT ) +#define GRSPW2_PNPVEND_VEND_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_PNPVEND_VEND_MASK ) | \ ( ( ( _val ) << GRSPW2_PNPVEND_VEND_SHIFT ) & \ GRSPW2_PNPVEND_VEND_MASK ) ) #define GRSPW2_PNPVEND_VEND( _val ) \ - ( ( ( _val ) << GRSPW2_PNPVEND_VEND_SHIFT ) & \ - GRSPW2_PNPVEND_VEND_MASK ) + ( ( ( _val ) << GRSPW2_PNPVEND_VEND_SHIFT ) & GRSPW2_PNPVEND_VEND_MASK ) #define GRSPW2_PNPVEND_PROD_SHIFT 0 -#define GRSPW2_PNPVEND_PROD_MASK 0xffffU +#define GRSPW2_PNPVEND_PROD_MASK 0xffffU #define GRSPW2_PNPVEND_PROD_GET( _reg ) \ - ( ( ( _reg ) & GRSPW2_PNPVEND_PROD_MASK ) >> \ - GRSPW2_PNPVEND_PROD_SHIFT ) -#define GRSPW2_PNPVEND_PROD_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPW2_PNPVEND_PROD_MASK ) | \ + ( ( ( _reg ) & GRSPW2_PNPVEND_PROD_MASK ) >> GRSPW2_PNPVEND_PROD_SHIFT ) +#define GRSPW2_PNPVEND_PROD_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_PNPVEND_PROD_MASK ) | \ ( ( ( _val ) << GRSPW2_PNPVEND_PROD_SHIFT ) & \ GRSPW2_PNPVEND_PROD_MASK ) ) #define GRSPW2_PNPVEND_PROD( _val ) \ - ( ( ( _val ) << GRSPW2_PNPVEND_PROD_SHIFT ) & \ - GRSPW2_PNPVEND_PROD_MASK ) + ( ( ( _val ) << GRSPW2_PNPVEND_PROD_SHIFT ) & GRSPW2_PNPVEND_PROD_MASK ) /** @} */ @@ -1123,17 +1039,14 @@ typedef struct grspw2_dma { */ #define GRSPW2_PNPOA0_RA_SHIFT 0 -#define GRSPW2_PNPOA0_RA_MASK 0xffffffffU +#define GRSPW2_PNPOA0_RA_MASK 0xffffffffU #define GRSPW2_PNPOA0_RA_GET( _reg ) \ - ( ( ( _reg ) & GRSPW2_PNPOA0_RA_MASK ) >> \ - GRSPW2_PNPOA0_RA_SHIFT ) -#define GRSPW2_PNPOA0_RA_SET( _reg, _val ) \ + ( ( ( _reg ) & GRSPW2_PNPOA0_RA_MASK ) >> GRSPW2_PNPOA0_RA_SHIFT ) +#define GRSPW2_PNPOA0_RA_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRSPW2_PNPOA0_RA_MASK ) | \ - ( ( ( _val ) << GRSPW2_PNPOA0_RA_SHIFT ) & \ - GRSPW2_PNPOA0_RA_MASK ) ) + ( ( ( _val ) << GRSPW2_PNPOA0_RA_SHIFT ) & GRSPW2_PNPOA0_RA_MASK ) ) #define GRSPW2_PNPOA0_RA( _val ) \ - ( ( ( _val ) << GRSPW2_PNPOA0_RA_SHIFT ) & \ - GRSPW2_PNPOA0_RA_MASK ) + ( ( ( _val ) << GRSPW2_PNPOA0_RA_SHIFT ) & GRSPW2_PNPOA0_RA_MASK ) /** @} */ @@ -1147,17 +1060,14 @@ typedef struct grspw2_dma { */ #define GRSPW2_PNPOA1_RA_SHIFT 0 -#define GRSPW2_PNPOA1_RA_MASK 0xffffffffU +#define GRSPW2_PNPOA1_RA_MASK 0xffffffffU #define GRSPW2_PNPOA1_RA_GET( _reg ) \ - ( ( ( _reg ) & GRSPW2_PNPOA1_RA_MASK ) >> \ - GRSPW2_PNPOA1_RA_SHIFT ) -#define GRSPW2_PNPOA1_RA_SET( _reg, _val ) \ + ( ( ( _reg ) & GRSPW2_PNPOA1_RA_MASK ) >> GRSPW2_PNPOA1_RA_SHIFT ) +#define GRSPW2_PNPOA1_RA_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRSPW2_PNPOA1_RA_MASK ) | \ - ( ( ( _val ) << GRSPW2_PNPOA1_RA_SHIFT ) & \ - GRSPW2_PNPOA1_RA_MASK ) ) + ( ( ( _val ) << GRSPW2_PNPOA1_RA_SHIFT ) & GRSPW2_PNPOA1_RA_MASK ) ) #define GRSPW2_PNPOA1_RA( _val ) \ - ( ( ( _val ) << GRSPW2_PNPOA1_RA_SHIFT ) & \ - GRSPW2_PNPOA1_RA_MASK ) + ( ( ( _val ) << GRSPW2_PNPOA1_RA_SHIFT ) & GRSPW2_PNPOA1_RA_MASK ) /** @} */ @@ -1171,17 +1081,14 @@ typedef struct grspw2_dma { */ #define GRSPW2_PNPOA2_RA_SHIFT 0 -#define GRSPW2_PNPOA2_RA_MASK 0xffffffffU +#define GRSPW2_PNPOA2_RA_MASK 0xffffffffU #define GRSPW2_PNPOA2_RA_GET( _reg ) \ - ( ( ( _reg ) & GRSPW2_PNPOA2_RA_MASK ) >> \ - GRSPW2_PNPOA2_RA_SHIFT ) -#define GRSPW2_PNPOA2_RA_SET( _reg, _val ) \ + ( ( ( _reg ) & GRSPW2_PNPOA2_RA_MASK ) >> GRSPW2_PNPOA2_RA_SHIFT ) +#define GRSPW2_PNPOA2_RA_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRSPW2_PNPOA2_RA_MASK ) | \ - ( ( ( _val ) << GRSPW2_PNPOA2_RA_SHIFT ) & \ - GRSPW2_PNPOA2_RA_MASK ) ) + ( ( ( _val ) << GRSPW2_PNPOA2_RA_SHIFT ) & GRSPW2_PNPOA2_RA_MASK ) ) #define GRSPW2_PNPOA2_RA( _val ) \ - ( ( ( _val ) << GRSPW2_PNPOA2_RA_SHIFT ) & \ - GRSPW2_PNPOA2_RA_MASK ) + ( ( ( _val ) << GRSPW2_PNPOA2_RA_SHIFT ) & GRSPW2_PNPOA2_RA_MASK ) /** @} */ @@ -1195,17 +1102,15 @@ typedef struct grspw2_dma { */ #define GRSPW2_PNPDEVID_DID_SHIFT 0 -#define GRSPW2_PNPDEVID_DID_MASK 0xffffffffU +#define GRSPW2_PNPDEVID_DID_MASK 0xffffffffU #define GRSPW2_PNPDEVID_DID_GET( _reg ) \ - ( ( ( _reg ) & GRSPW2_PNPDEVID_DID_MASK ) >> \ - GRSPW2_PNPDEVID_DID_SHIFT ) -#define GRSPW2_PNPDEVID_DID_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPW2_PNPDEVID_DID_MASK ) | \ + ( ( ( _reg ) & GRSPW2_PNPDEVID_DID_MASK ) >> GRSPW2_PNPDEVID_DID_SHIFT ) +#define GRSPW2_PNPDEVID_DID_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_PNPDEVID_DID_MASK ) | \ ( ( ( _val ) << GRSPW2_PNPDEVID_DID_SHIFT ) & \ GRSPW2_PNPDEVID_DID_MASK ) ) #define GRSPW2_PNPDEVID_DID( _val ) \ - ( ( ( _val ) << GRSPW2_PNPDEVID_DID_SHIFT ) & \ - GRSPW2_PNPDEVID_DID_MASK ) + ( ( ( _val ) << GRSPW2_PNPDEVID_DID_SHIFT ) & GRSPW2_PNPDEVID_DID_MASK ) /** @} */ @@ -1219,30 +1124,26 @@ typedef struct grspw2_dma { */ #define GRSPW2_PNPUVEND_VEND_SHIFT 16 -#define GRSPW2_PNPUVEND_VEND_MASK 0xffff0000U +#define GRSPW2_PNPUVEND_VEND_MASK 0xffff0000U #define GRSPW2_PNPUVEND_VEND_GET( _reg ) \ - ( ( ( _reg ) & GRSPW2_PNPUVEND_VEND_MASK ) >> \ - GRSPW2_PNPUVEND_VEND_SHIFT ) -#define GRSPW2_PNPUVEND_VEND_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPW2_PNPUVEND_VEND_MASK ) | \ + ( ( ( _reg ) & GRSPW2_PNPUVEND_VEND_MASK ) >> GRSPW2_PNPUVEND_VEND_SHIFT ) +#define GRSPW2_PNPUVEND_VEND_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_PNPUVEND_VEND_MASK ) | \ ( ( ( _val ) << GRSPW2_PNPUVEND_VEND_SHIFT ) & \ GRSPW2_PNPUVEND_VEND_MASK ) ) #define GRSPW2_PNPUVEND_VEND( _val ) \ - ( ( ( _val ) << GRSPW2_PNPUVEND_VEND_SHIFT ) & \ - GRSPW2_PNPUVEND_VEND_MASK ) + ( ( ( _val ) << GRSPW2_PNPUVEND_VEND_SHIFT ) & GRSPW2_PNPUVEND_VEND_MASK ) #define GRSPW2_PNPUVEND_PROD_SHIFT 0 -#define GRSPW2_PNPUVEND_PROD_MASK 0xffffU +#define GRSPW2_PNPUVEND_PROD_MASK 0xffffU #define GRSPW2_PNPUVEND_PROD_GET( _reg ) \ - ( ( ( _reg ) & GRSPW2_PNPUVEND_PROD_MASK ) >> \ - GRSPW2_PNPUVEND_PROD_SHIFT ) -#define GRSPW2_PNPUVEND_PROD_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPW2_PNPUVEND_PROD_MASK ) | \ + ( ( ( _reg ) & GRSPW2_PNPUVEND_PROD_MASK ) >> GRSPW2_PNPUVEND_PROD_SHIFT ) +#define GRSPW2_PNPUVEND_PROD_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_PNPUVEND_PROD_MASK ) | \ ( ( ( _val ) << GRSPW2_PNPUVEND_PROD_SHIFT ) & \ GRSPW2_PNPUVEND_PROD_MASK ) ) #define GRSPW2_PNPUVEND_PROD( _val ) \ - ( ( ( _val ) << GRSPW2_PNPUVEND_PROD_SHIFT ) & \ - GRSPW2_PNPUVEND_PROD_MASK ) + ( ( ( _val ) << GRSPW2_PNPUVEND_PROD_SHIFT ) & GRSPW2_PNPUVEND_PROD_MASK ) /** @} */ @@ -1256,17 +1157,14 @@ typedef struct grspw2_dma { */ #define GRSPW2_PNPUSN_USN_SHIFT 0 -#define GRSPW2_PNPUSN_USN_MASK 0xffffffffU +#define GRSPW2_PNPUSN_USN_MASK 0xffffffffU #define GRSPW2_PNPUSN_USN_GET( _reg ) \ - ( ( ( _reg ) & GRSPW2_PNPUSN_USN_MASK ) >> \ - GRSPW2_PNPUSN_USN_SHIFT ) -#define GRSPW2_PNPUSN_USN_SET( _reg, _val ) \ + ( ( ( _reg ) & GRSPW2_PNPUSN_USN_MASK ) >> GRSPW2_PNPUSN_USN_SHIFT ) +#define GRSPW2_PNPUSN_USN_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRSPW2_PNPUSN_USN_MASK ) | \ - ( ( ( _val ) << GRSPW2_PNPUSN_USN_SHIFT ) & \ - GRSPW2_PNPUSN_USN_MASK ) ) + ( ( ( _val ) << GRSPW2_PNPUSN_USN_SHIFT ) & GRSPW2_PNPUSN_USN_MASK ) ) #define GRSPW2_PNPUSN_USN( _val ) \ - ( ( ( _val ) << GRSPW2_PNPUSN_USN_SHIFT ) & \ - GRSPW2_PNPUSN_USN_MASK ) + ( ( ( _val ) << GRSPW2_PNPUSN_USN_SHIFT ) & GRSPW2_PNPUSN_USN_MASK ) /** @} */ diff --git a/bsps/include/grlib/grspw_pkt.h b/bsps/include/grlib/grspw_pkt.h index e035c81660..929a08dd5e 100644 --- a/bsps/include/grlib/grspw_pkt.h +++ b/bsps/include/grlib/grspw_pkt.h @@ -60,13 +60,13 @@ extern int grspw_work_task_priority; #define TXPKT_FLAG_DCRC 0x0200 /* Data CRC type */ -#define TXPKT_FLAG_DCRCT_MASK 0x0c00 +#define TXPKT_FLAG_DCRCT_MASK 0x0c00 /* RMAP CRC. 1 byte */ -#define TXPKT_FLAG_DCRCT_RMAP 0x0000 +#define TXPKT_FLAG_DCRCT_RMAP 0x0000 /* CCSDS/CCITT CRC-16. 2 byte */ -#define TXPKT_FLAG_DCRCT_CCSDS 0x0400 +#define TXPKT_FLAG_DCRCT_CCSDS 0x0400 /* 16-bit ISO-checksum (J.G. Fletcher, ISO 8473-1:1998). 2 byte */ -#define TXPKT_FLAG_DCRCT_ISO16 0x0800 +#define TXPKT_FLAG_DCRCT_ISO16 0x0800 /* Control how many bytes the beginning of the Header * the CRC should not be calculated for */ @@ -88,9 +88,9 @@ extern int grspw_work_task_priority; #define TXPKT_FLAG_NOCRC_LENe 0x0000000e #define TXPKT_FLAG_NOCRC_LENf 0x0000000f -#define TXPKT_FLAG_INPUT_MASK (TXPKT_FLAG_NOCRC_MASK | TXPKT_FLAG_IE | \ - TXPKT_FLAG_HCRC | TXPKT_FLAG_DCRC | \ - TXPKT_FLAG_DCRCT_MASK) +#define TXPKT_FLAG_INPUT_MASK \ + ( TXPKT_FLAG_NOCRC_MASK | TXPKT_FLAG_IE | TXPKT_FLAG_HCRC | \ + TXPKT_FLAG_DCRC | TXPKT_FLAG_DCRCT_MASK ) /* Marks if packet was transmitted or not */ #define TXPKT_FLAG_TX 0x4000 @@ -98,14 +98,14 @@ extern int grspw_work_task_priority; /* Link Error */ #define TXPKT_FLAG_LINKERR 0x8000 -#define TXPKT_FLAG_OUTPUT_MASK (TXPKT_FLAG_TX | TXPKT_FLAG_LINKERR) +#define TXPKT_FLAG_OUTPUT_MASK ( TXPKT_FLAG_TX | TXPKT_FLAG_LINKERR ) /*** RX Packet Flags ***/ /* Enable IRQ generation */ #define RXPKT_FLAG_IE 0x0010 -#define RXPKT_FLAG_INPUT_MASK (RXPKT_FLAG_IE) +#define RXPKT_FLAG_INPUT_MASK ( RXPKT_FLAG_IE ) /* Packet was truncated */ #define RXPKT_FLAG_TRUNK 0x0800 @@ -118,14 +118,14 @@ extern int grspw_work_task_priority; /* Marks if packet was recevied or not */ #define RXPKT_FLAG_RX 0x8000 -#define RXPKT_FLAG_OUTPUT_MASK (RXPKT_FLAG_TRUNK | RXPKT_FLAG_DCRC | \ - RXPKT_FLAG_HCRC | RXPKT_FLAG_EEOP) +#define RXPKT_FLAG_OUTPUT_MASK \ + ( RXPKT_FLAG_TRUNK | RXPKT_FLAG_DCRC | RXPKT_FLAG_HCRC | RXPKT_FLAG_EEOP ) /*** General packet flag options ***/ /* Translate Hdr and/or Payload address */ #define PKT_FLAG_TR_DATA 0x1000 -#define PKT_FLAG_TR_HDR 0x2000 +#define PKT_FLAG_TR_HDR 0x2000 /* All General options */ #define PKT_FLAG_MASK 0x3000 @@ -148,156 +148,162 @@ extern int grspw_work_task_priority; * type (RX/TX). See XXPKT_FLAG_* options above. */ struct grspw_pkt { - struct grspw_pkt *next; /* Next packet in list. NULL if last packet */ - unsigned int pkt_id; /* User assigned ID (not touched by driver) */ - unsigned short flags; /* RX/TX Options and status */ - unsigned char reserved; /* Reserved, must be zero */ - unsigned char hlen; /* Length of Header Buffer (only TX) */ - unsigned int dlen; /* Length of Data Buffer */ - void *data; /* 4-byte or byte aligned depends on HW */ - void *hdr; /* 4-byte or byte aligned depends on HW (only TX) */ + struct grspw_pkt *next; /* Next packet in list. NULL if last packet */ + unsigned int pkt_id; /* User assigned ID (not touched by driver) */ + unsigned short flags; /* RX/TX Options and status */ + unsigned char reserved; /* Reserved, must be zero */ + unsigned char hlen; /* Length of Header Buffer (only TX) */ + unsigned int dlen; /* Length of Data Buffer */ + void *data; /* 4-byte or byte aligned depends on HW */ + void *hdr; /* 4-byte or byte aligned depends on HW (only TX) */ }; /* GRSPW SpaceWire Packet List */ struct grspw_list { - struct grspw_pkt *head; - struct grspw_pkt *tail; + struct grspw_pkt *head; + struct grspw_pkt *tail; }; /* SpaceWire Link State */ typedef enum { - SPW_LS_ERRRST = 0, - SPW_LS_ERRWAIT = 1, - SPW_LS_READY = 2, - SPW_LS_STARTED = 3, - SPW_LS_CONNECTING = 4, - SPW_LS_RUN = 5 + SPW_LS_ERRRST = 0, + SPW_LS_ERRWAIT = 1, + SPW_LS_READY = 2, + SPW_LS_STARTED = 3, + SPW_LS_CONNECTING = 4, + SPW_LS_RUN = 5 } spw_link_state_t; /* Address Configuration */ struct grspw_addr_config { - /* Ignore address field and put all received packets to first + /* Ignore address field and put all received packets to first * DMA channel. */ - int promiscuous; + int promiscuous; - /* Default Node Address and Mask */ - unsigned char def_addr; - unsigned char def_mask; - /* DMA Channel custom Node Address and Mask */ - struct { - char node_en; /* Enable Separate Addr */ - unsigned char node_addr; /* Node address */ - unsigned char node_mask; /* Node address mask */ - } dma_nacfg[4]; + /* Default Node Address and Mask */ + unsigned char def_addr; + unsigned char def_mask; + /* DMA Channel custom Node Address and Mask */ + struct { + char node_en; /* Enable Separate Addr */ + unsigned char node_addr; /* Node address */ + unsigned char node_mask; /* Node address mask */ + } dma_nacfg[ 4 ]; }; /* Hardware Support in GRSPW Core */ struct grspw_hw_sup { - char rmap; /* If RMAP in HW is available */ - char rmap_crc; /* If RMAP CRC is available */ - char rx_unalign; /* RX unaligned (byte boundary) access allowed*/ - char nports; /* Number of Ports (1 or 2) */ - char ndma_chans; /* Number of DMA Channels (1..4) */ - char strip_adr; /* Hardware can strip ADR from packet data */ - char strip_pid; /* Hardware can strip PID from packet data */ - int hw_version; /* GRSPW Hardware Version */ - char reserved[2]; - char irq; /* SpW Distributed Interrupt available if 1 */ - char irq_num; /* Number of interrupts that can be generated */ - char itmr_width; /* SpW Intr. ISR timers bit width. 0=no timer */ - char ccsds_crc; /* CCSDS CRC-16 and 16-bit ISO is available */ + char rmap; /* If RMAP in HW is available */ + char rmap_crc; /* If RMAP CRC is available */ + char rx_unalign; /* RX unaligned (byte boundary) access allowed*/ + char nports; /* Number of Ports (1 or 2) */ + char ndma_chans; /* Number of DMA Channels (1..4) */ + char strip_adr; /* Hardware can strip ADR from packet data */ + char strip_pid; /* Hardware can strip PID from packet data */ + int hw_version; /* GRSPW Hardware Version */ + char reserved[ 2 ]; + char irq; /* SpW Distributed Interrupt available if 1 */ + char irq_num; /* Number of interrupts that can be generated */ + char itmr_width; /* SpW Intr. ISR timers bit width. 0=no timer */ + char ccsds_crc; /* CCSDS CRC-16 and 16-bit ISO is available */ }; struct grspw_core_stats { - int irq_cnt; - int err_credit; - int err_eeop; - int err_addr; - int err_parity; - int err_disconnect; - int err_escape; - int err_wsync; /* only in GRSPW1 */ + int irq_cnt; + int err_credit; + int err_eeop; + int err_addr; + int err_parity; + int err_disconnect; + int err_escape; + int err_wsync; /* only in GRSPW1 */ }; /* grspw_link_ctrl() options */ -#define LINKOPTS_ENABLE 0x0000 -#define LINKOPTS_DISABLE 0x0001 -#define LINKOPTS_START 0x0002 -#define LINKOPTS_AUTOSTART 0x0004 -#define LINKOPTS_DIS_ONERR 0x0008 /* Disable DMA transmitter on link error +#define LINKOPTS_ENABLE 0x0000 +#define LINKOPTS_DISABLE 0x0001 +#define LINKOPTS_START 0x0002 +#define LINKOPTS_AUTOSTART 0x0004 +#define LINKOPTS_DIS_ONERR \ + 0x0008 /* Disable DMA transmitter on link error * Controls LE bit in DMACTRL register. */ -#define LINKOPTS_DIS_ON_CE 0x0020000/* Disable Link on Credit error */ -#define LINKOPTS_DIS_ON_ER 0x0040000/* Disable Link on Escape error */ -#define LINKOPTS_DIS_ON_DE 0x0080000/* Disable Link on Disconnect error */ -#define LINKOPTS_DIS_ON_PE 0x0100000/* Disable Link on Parity error */ -#define LINKOPTS_DIS_ON_WE 0x0400000/* Disable Link on write synchonization +#define LINKOPTS_DIS_ON_CE 0x0020000 /* Disable Link on Credit error */ +#define LINKOPTS_DIS_ON_ER 0x0040000 /* Disable Link on Escape error */ +#define LINKOPTS_DIS_ON_DE 0x0080000 /* Disable Link on Disconnect error */ +#define LINKOPTS_DIS_ON_PE 0x0100000 /* Disable Link on Parity error */ +#define LINKOPTS_DIS_ON_WE \ + 0x0400000 /* Disable Link on write synchonization * error (GRSPW1 only) */ -#define LINKOPTS_DIS_ON_EE 0x1000000/* Disable Link on Early EOP/EEP error*/ +#define LINKOPTS_DIS_ON_EE 0x1000000 /* Disable Link on Early EOP/EEP error*/ -/*#define LINKOPTS_TICK_OUT_IRQ 0x0100*//* Enable Tick-out IRQ */ -#define LINKOPTS_EIRQ 0x0200 /* Enable Error Link IRQ */ +/*#define LINKOPTS_TICK_OUT_IRQ 0x0100*/ /* Enable Tick-out IRQ */ +#define LINKOPTS_EIRQ 0x0200 /* Enable Error Link IRQ */ -#define LINKOPTS_MASK 0x15e020f/* All above options */ -#define LINKOPTS_MASK_DIS_ON 0x15e0000/* All disable link on error options +#define LINKOPTS_MASK 0x15e020f /* All above options */ +#define LINKOPTS_MASK_DIS_ON \ + 0x15e0000 /* All disable link on error options * On a certain error the link disable * bit will be written and the work * task will call dma_stop() for all * channels. */ -#define LINKSTS_CE 0x002 /* Credit error */ -#define LINKSTS_ER 0x004 /* Escape error */ -#define LINKSTS_DE 0x008 /* Disconnect error */ -#define LINKSTS_PE 0x010 /* Parity error */ -#define LINKSTS_WE 0x040 /* Write synchonization error (GRSPW1 only) */ -#define LINKSTS_IA 0x080 /* Invalid address */ -#define LINKSTS_EE 0x100 /* Early EOP/EEP */ -#define LINKSTS_MASK 0x1de +#define LINKSTS_CE 0x002 /* Credit error */ +#define LINKSTS_ER 0x004 /* Escape error */ +#define LINKSTS_DE 0x008 /* Disconnect error */ +#define LINKSTS_PE 0x010 /* Parity error */ +#define LINKSTS_WE 0x040 /* Write synchonization error (GRSPW1 only) */ +#define LINKSTS_IA 0x080 /* Invalid address */ +#define LINKSTS_EE 0x100 /* Early EOP/EEP */ +#define LINKSTS_MASK 0x1de /* grspw_tc_ctrl() options */ -#define TCOPTS_EN_RXIRQ 0x0001 /* Tick-Out IRQ */ -#define TCOPTS_EN_TX 0x0004 -#define TCOPTS_EN_RX 0x0008 +#define TCOPTS_EN_RXIRQ 0x0001 /* Tick-Out IRQ */ +#define TCOPTS_EN_TX 0x0004 +#define TCOPTS_EN_RX 0x0008 /* grspw_ic_ctrl() options: * Corresponds code duplicatingly to GRSPW_CTRL_XX_BIT defines */ -#define ICOPTS_INTNUM (0x1f << 27) -#define ICOPTS_EN_SPWIRQ_ON_EE (1 << 24) -#define ICOPTS_EN_SPWIRQ_ON_IA (1 << 23) -#define ICOPTS_EN_PRIO (1 << 22) -#define ICOPTS_EN_TIMEOUTIRQ (1 << 20) -#define ICOPTS_EN_ACKIRQ (1 << 19) -#define ICOPTS_EN_TICKOUTIRQ (1 << 18) -#define ICOPTS_EN_RX (1 << 17) -#define ICOPTS_EN_TX (1 << 16) -#define ICOPTS_BASEIRQ (0x1f << 8) -#define ICOPTS_EN_FLAGFILTER (1 << 0) /* NOTE: Not in icctrl. CTRL.bit12 */ +#define ICOPTS_INTNUM ( 0x1f << 27 ) +#define ICOPTS_EN_SPWIRQ_ON_EE ( 1 << 24 ) +#define ICOPTS_EN_SPWIRQ_ON_IA ( 1 << 23 ) +#define ICOPTS_EN_PRIO ( 1 << 22 ) +#define ICOPTS_EN_TIMEOUTIRQ ( 1 << 20 ) +#define ICOPTS_EN_ACKIRQ ( 1 << 19 ) +#define ICOPTS_EN_TICKOUTIRQ ( 1 << 18 ) +#define ICOPTS_EN_RX ( 1 << 17 ) +#define ICOPTS_EN_TX ( 1 << 16 ) +#define ICOPTS_BASEIRQ ( 0x1f << 8 ) +#define ICOPTS_EN_FLAGFILTER ( 1 << 0 ) /* NOTE: Not in icctrl. CTRL.bit12 */ /* grspw_ic_rlisr() and grspw_ic_rlintack() */ -#define ICRELOAD_EN (1 << 31) -#define ICRELOAD_MASK 0x7fffffff +#define ICRELOAD_EN ( 1 << 31 ) +#define ICRELOAD_MASK 0x7fffffff /* grspw_rmap_ctrl() options */ -#define RMAPOPTS_EN_RMAP 0x0001 -#define RMAPOPTS_EN_BUF 0x0002 +#define RMAPOPTS_EN_RMAP 0x0001 +#define RMAPOPTS_EN_BUF 0x0002 /* grspw_dma_config.flags options */ -#define DMAFLAG_NO_SPILL 0x0001 /* See HW doc DMA-CTRL NS bit */ -#define DMAFLAG_RESV1 0x0002 /* HAS NO EFFECT */ -#define DMAFLAG_STRIP_ADR 0x0004 /* See HW doc DMA-CTRL SA bit */ -#define DMAFLAG_STRIP_PID 0x0008 /* See HW doc DMA-CTRL SP bit */ -#define DMAFLAG_RESV2 0x0010 /* HAS NO EFFECT */ -#define DMAFLAG_MASK (DMAFLAG_NO_SPILL|DMAFLAG_STRIP_ADR|DMAFLAG_STRIP_PID) +#define DMAFLAG_NO_SPILL 0x0001 /* See HW doc DMA-CTRL NS bit */ +#define DMAFLAG_RESV1 0x0002 /* HAS NO EFFECT */ +#define DMAFLAG_STRIP_ADR 0x0004 /* See HW doc DMA-CTRL SA bit */ +#define DMAFLAG_STRIP_PID 0x0008 /* See HW doc DMA-CTRL SP bit */ +#define DMAFLAG_RESV2 0x0010 /* HAS NO EFFECT */ +#define DMAFLAG_MASK \ + ( DMAFLAG_NO_SPILL | DMAFLAG_STRIP_ADR | DMAFLAG_STRIP_PID ) /* grspw_dma_config.flags misc options (not shifted internally) */ -#define DMAFLAG2_TXIE 0x00100000 /* See HW doc DMA-CTRL TI bit. +#define DMAFLAG2_TXIE \ + 0x00100000 /* See HW doc DMA-CTRL TI bit. * Used to enable TX DMA interrupt * when tx_irq_en_cnt=0. */ -#define DMAFLAG2_RXIE 0x00200000 /* See HW doc DMA-CTRL RI bit. +#define DMAFLAG2_RXIE \ + 0x00200000 /* See HW doc DMA-CTRL RI bit. * Used to enable RX DMA interrupt * when rx_irq_en_cnt=0. */ @@ -308,51 +314,51 @@ struct grspw_core_stats { * application handler or custom ISR handler is responsible to re-enable * DMA interrupts. */ -#define DMAFLAG2_IRQD_SRC 0x01000000 /* Disable triggering RX/TX source */ -#define DMAFLAG2_IRQD_NONE 0x00c00000 /* Never disable RX/TX IRQ in ISR */ -#define DMAFLAG2_IRQD_BOTH 0x00000000 /* Always disable both RX/TX sources */ -#define DMAFLAG2_IRQD_MASK 0x01c00000 /* Mask of options */ +#define DMAFLAG2_IRQD_SRC 0x01000000 /* Disable triggering RX/TX source */ +#define DMAFLAG2_IRQD_NONE 0x00c00000 /* Never disable RX/TX IRQ in ISR */ +#define DMAFLAG2_IRQD_BOTH 0x00000000 /* Always disable both RX/TX sources */ +#define DMAFLAG2_IRQD_MASK 0x01c00000 /* Mask of options */ #define DMAFLAG2_IRQD_BIT 22 -#define DMAFLAG2_MASK (DMAFLAG2_TXIE | DMAFLAG2_RXIE | DMAFLAG2_IRQD_MASK) +#define DMAFLAG2_MASK ( DMAFLAG2_TXIE | DMAFLAG2_RXIE | DMAFLAG2_IRQD_MASK ) struct grspw_dma_config { - int flags; /* DMA config flags, see DMAFLAG1&2_* options */ - int rxmaxlen; /* RX Max Packet Length */ - int rx_irq_en_cnt; /* Enable RX IRQ every cnt descriptors */ - int tx_irq_en_cnt; /* Enable TX IRQ every cnt descriptors */ + int flags; /* DMA config flags, see DMAFLAG1&2_* options */ + int rxmaxlen; /* RX Max Packet Length */ + int rx_irq_en_cnt; /* Enable RX IRQ every cnt descriptors */ + int tx_irq_en_cnt; /* Enable TX IRQ every cnt descriptors */ }; /* Statistics per DMA channel */ struct grspw_dma_stats { - /* IRQ Statistics */ - int irq_cnt; /* Number of DMA IRQs generated by channel */ + /* IRQ Statistics */ + int irq_cnt; /* Number of DMA IRQs generated by channel */ - /* Descriptor Statistics */ - int tx_pkts; /* Number of Transmitted packets */ - int tx_err_link; /* Number of Transmitted packets with Link Error*/ - int rx_pkts; /* Number of Received packets */ - int rx_err_trunk; /* Number of Received Truncated packets */ - int rx_err_endpkt; /* Number of Received packets with bad ending */ + /* Descriptor Statistics */ + int tx_pkts; /* Number of Transmitted packets */ + int tx_err_link; /* Number of Transmitted packets with Link Error*/ + int rx_pkts; /* Number of Received packets */ + int rx_err_trunk; /* Number of Received Truncated packets */ + int rx_err_endpkt; /* Number of Received packets with bad ending */ - /* Diagnostics to help developers sizing their number buffers to avoid + /* Diagnostics to help developers sizing their number buffers to avoid * out-of-buffers or other phenomenons. */ - int send_cnt_min; /* Minimum number of packets in TX SEND Q */ - int send_cnt_max; /* Maximum number of packets in TX SEND Q */ - int tx_sched_cnt_min; /* Minimum number of packets in TX SCHED Q */ - int tx_sched_cnt_max; /* Maximum number of packets in TX SCHED Q */ - int sent_cnt_max; /* Maximum number of packets in TX SENT Q */ - int tx_work_cnt; /* Times the work thread processed TX BDs */ - int tx_work_enabled; /* No. RX BDs enabled by work thread */ + int send_cnt_min; /* Minimum number of packets in TX SEND Q */ + int send_cnt_max; /* Maximum number of packets in TX SEND Q */ + int tx_sched_cnt_min; /* Minimum number of packets in TX SCHED Q */ + int tx_sched_cnt_max; /* Maximum number of packets in TX SCHED Q */ + int sent_cnt_max; /* Maximum number of packets in TX SENT Q */ + int tx_work_cnt; /* Times the work thread processed TX BDs */ + int tx_work_enabled; /* No. RX BDs enabled by work thread */ - int ready_cnt_min; /* Minimum number of packets in RX READY Q */ - int ready_cnt_max; /* Maximum number of packets in RX READY Q */ - int rx_sched_cnt_min; /* Minimum number of packets in RX SCHED Q */ - int rx_sched_cnt_max; /* Maximum number of packets in RX SCHED Q */ - int recv_cnt_max; /* Maximum number of packets in RX RECV Q */ - int rx_work_cnt; /* Times the work thread processed RX BDs */ - int rx_work_enabled; /* No. RX BDs enabled by work thread */ + int ready_cnt_min; /* Minimum number of packets in RX READY Q */ + int ready_cnt_max; /* Maximum number of packets in RX READY Q */ + int rx_sched_cnt_min; /* Minimum number of packets in RX SCHED Q */ + int rx_sched_cnt_max; /* Maximum number of packets in RX SCHED Q */ + int recv_cnt_max; /* Maximum number of packets in RX RECV Q */ + int rx_work_cnt; /* Times the work thread processed RX BDs */ + int rx_work_enabled; /* No. RX BDs enabled by work thread */ }; /* ISR message sending call back. Compatible with rtems_message_queue_send(). @@ -364,7 +370,11 @@ struct grspw_dma_stats { * \param buf Pointer to a 32-bit message word * \param n Always 4 (byte size of buf). */ -typedef int (*grspw_msgqisr_t)(void *data, unsigned int *buf, unsigned int n); +typedef int ( *grspw_msgqisr_t )( + void *data, + unsigned int *buf, + unsigned int n +); /* Work message definitions, the int sent to *buf * Bits 31..24: reserved. @@ -376,38 +386,39 @@ typedef int (*grspw_msgqisr_t)(void *data, unsigned int *buf, unsigned int n); * Bit 11..8: Indicats DMA error on DMA channel 3..0. * Bit 7..0: Indicats RX and/or TX packets completed on channel 3..0. */ -#define WORK_NONE 0 -#define WORK_SHUTDOWN 0x1000 /* Signal shut down */ -#define WORK_QUIT_TASK 0x2000 /* Work task shall exit (delete itself) */ -#define WORK_FREE_MSGQ 0x4000 /* Delete MsgQ (valid when WORK_QUIT_TASK) */ -#define WORK_DMA(chan, rxtx) (((rxtx) & 0x3) << ((chan) * 2)) -#define WORK_DMA_TX(chan) WORK_DMA(chan, 1) -#define WORK_DMA_RX(chan) WORK_DMA(chan, 2) -#define WORK_DMA_ER(chan) (0x1 << ((chan) + 8)) -#define WORK_DMA_MASK 0xfff /* max 4 channels all work */ -#define WORK_DMA_TX_MASK 0x055 /* max 4 channels TX work */ -#define WORK_DMA_RX_MASK 0x0aa /* max 4 channels RX work */ -#define WORK_DMA_ER_MASK 0xf00 /* max 4 channels Error work */ -#define WORK_DMA_CHAN_MASK(chan) (WORK_DMA_ER(chan) | WORK_DMA(chan, 0x3)) -#define WORK_CORE_BIT 16 -#define WORK_CORE_MASK 0x00ff0000 -#define WORK_CORE(device) ((device) << WORK_CORE_BIT) +#define WORK_NONE 0 +#define WORK_SHUTDOWN 0x1000 /* Signal shut down */ +#define WORK_QUIT_TASK 0x2000 /* Work task shall exit (delete itself) */ +#define WORK_FREE_MSGQ 0x4000 /* Delete MsgQ (valid when WORK_QUIT_TASK) */ +#define WORK_DMA( chan, rxtx ) ( ( ( rxtx ) & 0x3 ) << ( ( chan ) * 2 ) ) +#define WORK_DMA_TX( chan ) WORK_DMA( chan, 1 ) +#define WORK_DMA_RX( chan ) WORK_DMA( chan, 2 ) +#define WORK_DMA_ER( chan ) ( 0x1 << ( ( chan ) + 8 ) ) +#define WORK_DMA_MASK 0xfff /* max 4 channels all work */ +#define WORK_DMA_TX_MASK 0x055 /* max 4 channels TX work */ +#define WORK_DMA_RX_MASK 0x0aa /* max 4 channels RX work */ +#define WORK_DMA_ER_MASK 0xf00 /* max 4 channels Error work */ +#define WORK_DMA_CHAN_MASK( chan ) \ + ( WORK_DMA_ER( chan ) | WORK_DMA( chan, 0x3 ) ) +#define WORK_CORE_BIT 16 +#define WORK_CORE_MASK 0x00ff0000 +#define WORK_CORE( device ) ( ( device ) << WORK_CORE_BIT ) /* Message Q used to send messages to work task */ struct grspw_work_config { - grspw_msgqisr_t msgisr; - void *msgisr_arg; /* example: rtems_id to Msg Q */ + grspw_msgqisr_t msgisr; + void *msgisr_arg; /* example: rtems_id to Msg Q */ }; extern void grspw_initialize_user( - /* Callback every time a GRSPW device is found. Args: DeviceIndex */ - void *(*devfound)(int), - /* Callback every time a GRSPW device is removed. Args: + /* Callback every time a GRSPW device is found. Args: DeviceIndex */ + void *( *devfound )(int), + /* Callback every time a GRSPW device is removed. Args: * int = DeviceIndex * void* = Return Value from devfound() */ - void (*devremove)(int,void*) - ); + void ( *devremove )( int, void * ) +); /* Creates a MsgQ (optional) and spawns a worker task associated with the * message Q. The task can also be associated with a custom msgQ if *msgQ. @@ -421,13 +432,18 @@ extern void grspw_initialize_user( * \param msgMax Maximum number of messages, set to 0 for default. * \return 0 on failure, task id on success. */ -extern rtems_id grspw_work_spawn(int prio, int stack, rtems_id *pMsgQ, int msgMax); +extern rtems_id grspw_work_spawn( + int prio, + int stack, + rtems_id *pMsgQ, + int msgMax +); /* Free task associated with message queue and optionally also the message * queue itself. The message queue is deleted by the work task and is therefore * delayed until it the work task resumes its execution. */ -extern rtems_status_code grspw_work_free(rtems_id msgQ, int freeMsgQ); +extern rtems_status_code grspw_work_free( rtems_id msgQ, int freeMsgQ ); /* Configure a GRSPW device Work task and Message Q set up. * This affects messages to: @@ -435,7 +451,7 @@ extern rtems_status_code grspw_work_free(rtems_id msgQ, int freeMsgQ); * - Link status interrupt handling (optional) * - RX DMA, defaults to common msgQ (configured per DMA channel) */ -extern void grspw_work_cfg(void *d, struct grspw_work_config *wc); +extern void grspw_work_cfg( void *d, struct grspw_work_config *wc ); /* Work-task function, called only from the work task. The function is provided * as a way for the user to create its own work tasks. @@ -445,13 +461,13 @@ extern void grspw_work_cfg(void *d, struct grspw_work_config *wc); * The messages are always 32-bit words and follows the format defined by the * WORK_* macros above. */ -extern void grspw_work_func(rtems_task_argument arg); +extern void grspw_work_func( rtems_task_argument arg ); enum grspw_worktask_ev { - WORKTASK_EV_NONE = 0, - WORKTASK_EV_QUIT = 1, - WORKTASK_EV_SHUTDOWN = 2, - WORKTASK_EV_DMA_STOP = 3, + WORKTASK_EV_NONE = 0, + WORKTASK_EV_QUIT = 1, + WORKTASK_EV_SHUTDOWN = 2, + WORKTASK_EV_DMA_STOP = 3, }; /* Weak function to let user override. Function called every time one of the @@ -460,64 +476,68 @@ enum grspw_worktask_ev { * The user can for example add custom code to invoke on a DMA error, link * error or monitor when the work-task exits after a call to grspw_work_free(). */ -extern void grspw_work_event(enum grspw_worktask_ev ev, unsigned int msg); +extern void grspw_work_event( enum grspw_worktask_ev ev, unsigned int msg ); #ifdef RTEMS_SMP /* Set ISR interrupt affinity. The LEON IRQCtrl requires that the cpumask shall * always have one bit set. */ -extern int grspw_isr_affinity(void *d, const cpu_set_t *cpus); +extern int grspw_isr_affinity( void *d, const cpu_set_t *cpus ); #endif -extern int grspw_dev_count(void); -extern void *grspw_open(int dev_no); -extern int grspw_close(void *d); -extern void grspw_hw_support(void *d, struct grspw_hw_sup *hw); -extern void grspw_stats_read(void *d, struct grspw_core_stats *sts); -extern void grspw_stats_clr(void *d); +extern int grspw_dev_count( void ); +extern void *grspw_open( int dev_no ); +extern int grspw_close( void *d ); +extern void grspw_hw_support( void *d, struct grspw_hw_sup *hw ); +extern void grspw_stats_read( void *d, struct grspw_core_stats *sts ); +extern void grspw_stats_clr( void *d ); /* Set and Read current node address configuration. The dma_nacfg[N] field * represents the configuration for DMA Channel N. * * Set cfg->promiscous to -1 in order to only read current configuration. */ -extern void grspw_addr_ctrl(void *d, struct grspw_addr_config *cfg); +extern void grspw_addr_ctrl( void *d, struct grspw_addr_config *cfg ); /*** Link Control interface ***/ /* Read Link State */ -extern spw_link_state_t grspw_link_state(void *d); +extern spw_link_state_t grspw_link_state( void *d ); /* options [in/out]: set to -1 to only read current config * * CLKDIV register contain: * bits 7..0 : Clock Div RUN (only run-state) * bits 15..8 : Clock Div During Startup (all link states except run-state) */ -extern void grspw_link_ctrl(void *d, int *options, int *stscfg, int *clkdiv); +extern void grspw_link_ctrl( void *d, int *options, int *stscfg, int *clkdiv ); /* Read the current value of the status register */ -extern unsigned int grspw_link_status(void *d); +extern unsigned int grspw_link_status( void *d ); /* Clear bits in the status register */ -extern void grspw_link_status_clr(void *d, unsigned int clearmask); +extern void grspw_link_status_clr( void *d, unsigned int clearmask ); /*** Time Code Interface ***/ /* Generate Tick-In (increment Time Counter, Send Time Code) */ -extern void grspw_tc_tx(void *d); +extern void grspw_tc_tx( void *d ); /* Control Timcode settings of core */ -extern void grspw_tc_ctrl(void *d, int *options); +extern void grspw_tc_ctrl( void *d, int *options ); /* Assign ISR Function to TimeCode RX IRQ */ -extern void grspw_tc_isr(void *d, void (*tcisr)(void *data, int tc), void *data); +extern void grspw_tc_isr( + void *d, + void ( *tcisr )( void *data, int tc ), + void *data +); /* Read/Write TCTRL and TIMECNT. Write if not -1, always read current value * TCTRL = bits 7 and 6 * TIMECNT = bits 5 to 0 */ -extern void grspw_tc_time(void *d, int *time); +extern void grspw_tc_time( void *d, int *time ); /*** Interrupt-code Interface ***/ struct spwpkt_ic_config { - unsigned int tomask; - unsigned int aamask; - unsigned int scaler; - unsigned int isr_reload; - unsigned int ack_reload; + unsigned int tomask; + unsigned int aamask; + unsigned int scaler; + unsigned int isr_reload; + unsigned int ack_reload; }; /* Function Interrupt-Code ISR callback prototype. Called when respective * interrupt handling option has been enabled by grspw_ic_ctrl(), the @@ -533,22 +553,30 @@ struct spwpkt_ic_config { * intto - Interrupt Tick-out Recevie register of the GRSPW core read by ISR * (only defined if TQ bit enabled through grspw_ic_ctrl()) */ -typedef void (*spwpkt_ic_isr_t)(void *data, unsigned int rxirq, - unsigned int rxack, unsigned int intto); +typedef void ( *spwpkt_ic_isr_t )( + void *data, + unsigned int rxirq, + unsigned int rxack, + unsigned int intto +); /* Control Interrupt-code settings of core * Write if 'options' not pointing to -1, always read current value */ -extern void grspw_ic_ctrl(void *d, unsigned int *options); +extern void grspw_ic_ctrl( void *d, unsigned int *options ); /* Write (rw&1 == 1) configuration parameters to registers and/or, * Read (rw&2 == 1) configuration parameters from registers, in that sequence. */ -extern void grspw_ic_config(void *d, int rw, struct spwpkt_ic_config *cfg); +extern void grspw_ic_config( void *d, int rw, struct spwpkt_ic_config *cfg ); /* Read or Write Interrupt-code status registers. * If pointer argument *ptr == 0 then only read, if *ptr != 0 then only write. * If *ptr is NULL no operation. */ -extern void grspw_ic_sts(void *d, unsigned int *rxirq, unsigned int *rxack, - unsigned int *intto); +extern void grspw_ic_sts( + void *d, + unsigned int *rxirq, + unsigned int *rxack, + unsigned int *intto +); /* Generate Tick-In for the given Interrupt-code * Returns zero on success and non-zero on failure * @@ -556,14 +584,14 @@ extern void grspw_ic_sts(void *d, unsigned int *rxirq, unsigned int *rxack, * Bit 5 - ACK if 1 * Bits 4-0 Interrupt-code number */ -extern int grspw_ic_tickin(void *d, int ic); +extern int grspw_ic_tickin( void *d, int ic ); /* Assign handler function to Interrupt-code timeout IRQ */ -extern void grspw_ic_isr(void *d, spwpkt_ic_isr_t handler, void *data); +extern void grspw_ic_isr( void *d, spwpkt_ic_isr_t handler, void *data ); /*** RMAP Control Interface ***/ /* Set (not -1) and/or read RMAP options. */ -extern int grspw_rmap_ctrl(void *d, int *options, int *dstkey); -extern void grspw_rmap_support(void *d, char *rmap, char *rmap_crc); +extern int grspw_rmap_ctrl( void *d, int *options, int *dstkey ); +extern void grspw_rmap_support( void *d, char *rmap, char *rmap_crc ); /*** SpW Port Control Interface ***/ @@ -573,24 +601,24 @@ extern void grspw_rmap_support(void *d, char *rmap, char *rmap_crc); * 1=Port 1 * Other positive values=Both Port0 and Port1 */ -extern int grspw_port_ctrl(void *d, int *port); +extern int grspw_port_ctrl( void *d, int *port ); /* Returns Number ports available in hardware */ -extern int grspw_port_count(void *d); +extern int grspw_port_count( void *d ); /* Returns the current active port */ -extern int grspw_port_active(void *d); +extern int grspw_port_active( void *d ); /*** DMA Interface ***/ -extern void *grspw_dma_open(void *d, int chan_no); -extern int grspw_dma_close(void *c); +extern void *grspw_dma_open( void *d, int chan_no ); +extern int grspw_dma_close( void *c ); -extern int grspw_dma_start(void *c); -extern void grspw_dma_stop(void *c); +extern int grspw_dma_start( void *c ); +extern void grspw_dma_stop( void *c ); /* Enable interrupt manually */ -extern unsigned int grspw_dma_enable_int(void *c, int rxtx, int force); +extern unsigned int grspw_dma_enable_int( void *c, int rxtx, int force ); /* Return Current DMA Control & Status Register */ -extern unsigned int grspw_dma_ctrlsts(void *c); +extern unsigned int grspw_dma_ctrlsts( void *c ); /* Schedule List of packets for transmission at some point in * future. @@ -620,7 +648,12 @@ extern unsigned int grspw_dma_ctrlsts(void *c); * 0 Successfully added pkts to send/sched list * 1 DMA stopped. No operation. */ -extern int grspw_dma_tx_send(void *c, int opts, struct grspw_list *pkts, int count); +extern int grspw_dma_tx_send( + void *c, + int opts, + struct grspw_list *pkts, + int count +); /* Reclaim TX packet buffers that has previously been scheduled for transmission * with grspw_dma_tx_send(). @@ -643,13 +676,24 @@ extern int grspw_dma_tx_send(void *c, int opts, struct grspw_list *pkts, int cou * 0 Successful. pkts list filled with all packets from sent list * 1 Same as 0, but indicates that DMA stopped */ -extern int grspw_dma_tx_reclaim(void *c, int opts, struct grspw_list *pkts, int *count); +extern int grspw_dma_tx_reclaim( + void *c, + int opts, + struct grspw_list *pkts, + int *count +); /* Get current number of Packets in respective TX Queue. */ -extern void grspw_dma_tx_count(void *c, int *send, int *sched, int *sent, int *hw); +extern void grspw_dma_tx_count( + void *c, + int *send, + int *sched, + int *sent, + int *hw +); #define GRSPW_OP_AND 0 -#define GRSPW_OP_OR 1 +#define GRSPW_OP_OR 1 /* Block until send_cnt or fewer packets are Queued in "Send and Scheduled" Q, * op (AND or OR), sent_cnt or more packet "have been sent" (Sent Q) condition * is met. @@ -669,7 +713,13 @@ extern void grspw_dma_tx_count(void *c, int *send, int *sched, int *sent, int *h * 2 Timeout, conditions are not met * 3 Another task is already waiting. Service is Busy. */ -extern int grspw_dma_tx_wait(void *c, int send_cnt, int op, int sent_cnt, int timeout); +extern int grspw_dma_tx_wait( + void *c, + int send_cnt, + int op, + int sent_cnt, + int timeout +); /* Get received RX packet buffers that has previously been scheduled for * reception with grspw_dma_rx_prepare(). @@ -692,7 +742,12 @@ extern int grspw_dma_tx_wait(void *c, int send_cnt, int op, int sent_cnt, int ti * 0 Successfully filled pkts list with packets from recv list. * 1 DMA stopped */ -extern int grspw_dma_rx_recv(void *c, int opts, struct grspw_list *pkts, int *count); +extern int grspw_dma_rx_recv( + void *c, + int opts, + struct grspw_list *pkts, + int *count +); /* Add more RX packet buffers for future for reception. The received packets * can later be read out with grspw_dma_rx_recv(). @@ -715,10 +770,21 @@ extern int grspw_dma_rx_recv(void *c, int opts, struct grspw_list *pkts, int *co * 0 Successfully added packet buffers from pkt list into the ready queue * 1 DMA stopped */ -extern int grspw_dma_rx_prepare(void *c, int opts, struct grspw_list *pkts, int count); +extern int grspw_dma_rx_prepare( + void *c, + int opts, + struct grspw_list *pkts, + int count +); /* Get current number of Packets in respective RX Queue. */ -extern void grspw_dma_rx_count(void *c, int *ready, int *sched, int *recv, int *hw); +extern void grspw_dma_rx_count( + void *c, + int *ready, + int *sched, + int *recv, + int *hw +); /* Block until recv_cnt or more packets are Queued in RECV Q, op (AND or OR), * ready_cnt or fewer packet buffers are available in the "READY and Scheduled" Q, @@ -739,138 +805,158 @@ extern void grspw_dma_rx_count(void *c, int *ready, int *sched, int *recv, int * * 2 Timeout, conditions are not met * 3 Another task is already waiting. Service is Busy. */ -extern int grspw_dma_rx_wait(void *c, int recv_cnt, int op, int ready_cnt, int timeout); +extern int grspw_dma_rx_wait( + void *c, + int recv_cnt, + int op, + int ready_cnt, + int timeout +); -extern int grspw_dma_config(void *c, struct grspw_dma_config *cfg); -extern void grspw_dma_config_read(void *c, struct grspw_dma_config *cfg); +extern int grspw_dma_config( void *c, struct grspw_dma_config *cfg ); +extern void grspw_dma_config_read( void *c, struct grspw_dma_config *cfg ); -extern void grspw_dma_stats_read(void *c, struct grspw_dma_stats *sts); -extern void grspw_dma_stats_clr(void *c); +extern void grspw_dma_stats_read( void *c, struct grspw_dma_stats *sts ); +extern void grspw_dma_stats_clr( void *c ); /* Register GRSPW packet driver to Driver Manager */ -void grspw2_register_drv (void); +void grspw2_register_drv( void ); /*** GRSPW SpaceWire Packet List Handling Routines ***/ -static inline void grspw_list_clr(struct grspw_list *list) +static inline void grspw_list_clr( struct grspw_list *list ) { - list->head = NULL; - list->tail = NULL; + list->head = NULL; + list->tail = NULL; } -static inline int grspw_list_is_empty(struct grspw_list *list) +static inline int grspw_list_is_empty( struct grspw_list *list ) { - return (list->head == NULL); + return ( list->head == NULL ); } /* Return Number of entries in list */ -static inline int grspw_list_cnt(struct grspw_list *list) +static inline int grspw_list_cnt( struct grspw_list *list ) { - struct grspw_pkt *lastpkt = NULL, *pkt = list->head; - int cnt = 0; - while ( pkt ) { - cnt++; - lastpkt = pkt; - pkt = pkt->next; - } - if ( lastpkt && (list->tail != lastpkt) ) - return -1; - return cnt; + struct grspw_pkt *lastpkt = NULL, *pkt = list->head; + int cnt = 0; + while ( pkt ) { + cnt++; + lastpkt = pkt; + pkt = pkt->next; + } + if ( lastpkt && ( list->tail != lastpkt ) ) { + return -1; + } + return cnt; } -static inline void -grspw_list_append(struct grspw_list *list, struct grspw_pkt *pkt) +static inline void grspw_list_append( + struct grspw_list *list, + struct grspw_pkt *pkt +) { - pkt->next = NULL; - if ( list->tail == NULL ) { - list->head = pkt; - } else { - list->tail->next = pkt; - } - list->tail = pkt; + pkt->next = NULL; + if ( list->tail == NULL ) { + list->head = pkt; + } else { + list->tail->next = pkt; + } + list->tail = pkt; } -static inline void -grspw_list_prepend(struct grspw_list *list, struct grspw_pkt *pkt) +static inline void grspw_list_prepend( + struct grspw_list *list, + struct grspw_pkt *pkt +) { - pkt->next = list->head; - if ( list->head == NULL ) { - list->tail = pkt; - } - list->head = pkt; + pkt->next = list->head; + if ( list->head == NULL ) { + list->tail = pkt; + } + list->head = pkt; } -static inline void -grspw_list_append_list(struct grspw_list *list, struct grspw_list *alist) +static inline void grspw_list_append_list( + struct grspw_list *list, + struct grspw_list *alist +) { - if (grspw_list_is_empty(alist)) { - return; - } - alist->tail->next = NULL; - if ( list->tail == NULL ) { - list->head = alist->head; - } else { - list->tail->next = alist->head; - } - list->tail = alist->tail; + if ( grspw_list_is_empty( alist ) ) { + return; + } + alist->tail->next = NULL; + if ( list->tail == NULL ) { + list->head = alist->head; + } else { + list->tail->next = alist->head; + } + list->tail = alist->tail; } -static inline void -grspw_list_prepend_list(struct grspw_list *list, struct grspw_list *alist) +static inline void grspw_list_prepend_list( + struct grspw_list *list, + struct grspw_list *alist +) { - if (grspw_list_is_empty(alist)) { - return; - } - if ( list->head == NULL ) { - list->tail = alist->tail; - alist->tail->next = NULL; - } else { - alist->tail->next = list->head; - } - list->head = alist->head; + if ( grspw_list_is_empty( alist ) ) { + return; + } + if ( list->head == NULL ) { + list->tail = alist->tail; + alist->tail->next = NULL; + } else { + alist->tail->next = list->head; + } + list->head = alist->head; } /* Remove dlist (delete-list) from head of list */ -static inline void -grspw_list_remove_head_list(struct grspw_list *list, struct grspw_list *dlist) +static inline void grspw_list_remove_head_list( + struct grspw_list *list, + struct grspw_list *dlist +) { - if (grspw_list_is_empty(dlist)) { - return; - } - list->head = dlist->tail->next; - if ( list->head == NULL ) { - list->tail = NULL; - } - dlist->tail->next = NULL; + if ( grspw_list_is_empty( dlist ) ) { + return; + } + list->head = dlist->tail->next; + if ( list->head == NULL ) { + list->tail = NULL; + } + dlist->tail->next = NULL; } /* Take A number of entries from head of list 'list' and put the entires * to rlist (result list). */ -static inline int -grspw_list_take_head_list(struct grspw_list *list, struct grspw_list *rlist, int max) +static inline int grspw_list_take_head_list( + struct grspw_list *list, + struct grspw_list *rlist, + int max +) { - int cnt; - struct grspw_pkt *pkt, *last; + int cnt; + struct grspw_pkt *pkt, *last; - pkt = list->head; + pkt = list->head; - if ( (max < 1) || (pkt == NULL) ) { - grspw_list_clr(rlist); - return 0; - } + if ( ( max < 1 ) || ( pkt == NULL ) ) { + grspw_list_clr( rlist ); + return 0; + } - cnt = 0; - rlist->head = pkt; - last = pkt; - while ((cnt < max) && pkt) { - last = pkt; - pkt = pkt->next; - cnt++; - } - rlist->tail = last; - grspw_list_remove_head_list(list, rlist); - return cnt; + cnt = 0; + rlist->head = pkt; + last = pkt; + while ( ( cnt < max ) && pkt ) { + last = pkt; + pkt = pkt->next; + cnt++; + } + rlist->tail = last; + grspw_list_remove_head_list( list, rlist ); + return cnt; } #endif diff --git a/bsps/include/grlib/grspw_router.h b/bsps/include/grlib/grspw_router.h index 55c67b599c..a1122cd48f 100644 --- a/bsps/include/grlib/grspw_router.h +++ b/bsps/include/grlib/grspw_router.h @@ -38,153 +38,157 @@ extern "C" { /* Maximum number of ROUTER devices supported by driver */ #define ROUTER_MAX 2 -#define ROUTER_ERR_OK 0 -#define ROUTER_ERR_EINVAL -1 -#define ROUTER_ERR_ERROR -2 -#define ROUTER_ERR_TOOMANY -3 +#define ROUTER_ERR_OK 0 +#define ROUTER_ERR_EINVAL -1 +#define ROUTER_ERR_ERROR -2 +#define ROUTER_ERR_TOOMANY -3 #define ROUTER_ERR_IMPLEMENTED -4 /* Hardware Information */ struct router_hw_info { - uint8_t nports_spw; - uint8_t nports_amba; - uint8_t nports_fifo; - int8_t srouting; - int8_t pnp_enable; - int8_t timers_avail; - int8_t pnp_avail; - uint8_t ver_major; - uint8_t ver_minor; - uint8_t ver_patch; - uint8_t iid; + uint8_t nports_spw; + uint8_t nports_amba; + uint8_t nports_fifo; + int8_t srouting; + int8_t pnp_enable; + int8_t timers_avail; + int8_t pnp_avail; + uint8_t ver_major; + uint8_t ver_minor; + uint8_t ver_patch; + uint8_t iid; - /* Router capabilities */ - uint8_t amba_port_fifo_size; - uint8_t spw_port_fifo_size; - uint8_t rmap_maxdlen; - int8_t aux_async; - int8_t aux_dist_int_support; - int8_t dual_port_support; - int8_t dist_int_support; - int8_t spwd_support; - uint8_t pktcnt_support; - uint8_t charcnt_support; + /* Router capabilities */ + uint8_t amba_port_fifo_size; + uint8_t spw_port_fifo_size; + uint8_t rmap_maxdlen; + int8_t aux_async; + int8_t aux_dist_int_support; + int8_t dual_port_support; + int8_t dist_int_support; + int8_t spwd_support; + uint8_t pktcnt_support; + uint8_t charcnt_support; }; -#define ROUTER_FLG_CFG 0x01 -#define ROUTER_FLG_IID 0x02 -#define ROUTER_FLG_IDIV 0x04 -#define ROUTER_FLG_TPRES 0x08 -#define ROUTER_FLG_TRLD 0x10 -#define ROUTER_FLG_ALL 0x1f /* All Above Flags */ +#define ROUTER_FLG_CFG 0x01 +#define ROUTER_FLG_IID 0x02 +#define ROUTER_FLG_IDIV 0x04 +#define ROUTER_FLG_TPRES 0x08 +#define ROUTER_FLG_TRLD 0x10 +#define ROUTER_FLG_ALL 0x1f /* All Above Flags */ struct router_config { - uint32_t flags; /* Determine what configuration should be updated */ + uint32_t flags; /* Determine what configuration should be updated */ - /* Router Configuration Register */ - uint32_t config; + /* Router Configuration Register */ + uint32_t config; - /* Set Instance ID */ - uint8_t iid; + /* Set Instance ID */ + uint8_t iid; - /* SpaceWire Link Initialization Clock Divisor */ - uint8_t idiv; + /* SpaceWire Link Initialization Clock Divisor */ + uint8_t idiv; - /* Timer Prescaler */ - uint32_t timer_prescaler; + /* Timer Prescaler */ + uint32_t timer_prescaler; }; /* Routing table address control */ struct router_route_acontrol { - uint32_t control[31]; - uint32_t control_logical[224]; + uint32_t control[ 31 ]; + uint32_t control_logical[ 224 ]; }; /* Routing table port mapping */ struct router_route_portmap { - uint32_t pmap[31]; /* Port Setup for ports 1-31 */ - uint32_t pmap_logical[224]; /* Port setup for locgical addresses 32-255 */ + uint32_t pmap[ 31 ]; /* Port Setup for ports 1-31 */ + uint32_t pmap_logical[ 224 ]; /* Port setup for locgical addresses 32-255 */ }; /* Routing table */ -#define ROUTER_ROUTE_FLG_MAP 0x01 +#define ROUTER_ROUTE_FLG_MAP 0x01 #define ROUTER_ROUTE_FLG_CTRL 0x02 -#define ROUTER_ROUTE_FLG_ALL 0x3 /* All Above Flags */ +#define ROUTER_ROUTE_FLG_ALL 0x3 /* All Above Flags */ struct router_routing_table { - uint32_t flags; /* Determine what configuration should be updated */ + uint32_t flags; /* Determine what configuration should be updated */ - struct router_route_acontrol acontrol; - struct router_route_portmap portmap; + struct router_route_acontrol acontrol; + struct router_route_portmap portmap; }; /* Set/Get Port Control/Status */ -#define ROUTER_PORT_FLG_SET_CTRL 0x01 -#define ROUTER_PORT_FLG_GET_CTRL 0x02 -#define ROUTER_PORT_FLG_SET_STS 0x04 -#define ROUTER_PORT_FLG_GET_STS 0x08 -#define ROUTER_PORT_FLG_SET_CTRL2 0x10 -#define ROUTER_PORT_FLG_GET_CTRL2 0x20 -#define ROUTER_PORT_FLG_SET_TIMER 0x40 -#define ROUTER_PORT_FLG_GET_TIMER 0x80 -#define ROUTER_PORT_FLG_SET_PKTLEN 0x100 -#define ROUTER_PORT_FLG_GET_PKTLEN 0x200 +#define ROUTER_PORT_FLG_SET_CTRL 0x01 +#define ROUTER_PORT_FLG_GET_CTRL 0x02 +#define ROUTER_PORT_FLG_SET_STS 0x04 +#define ROUTER_PORT_FLG_GET_STS 0x08 +#define ROUTER_PORT_FLG_SET_CTRL2 0x10 +#define ROUTER_PORT_FLG_GET_CTRL2 0x20 +#define ROUTER_PORT_FLG_SET_TIMER 0x40 +#define ROUTER_PORT_FLG_GET_TIMER 0x80 +#define ROUTER_PORT_FLG_SET_PKTLEN 0x100 +#define ROUTER_PORT_FLG_GET_PKTLEN 0x200 struct router_port { - uint32_t flag; - /* Port control */ - uint32_t ctrl; - /* Port status */ - uint32_t sts; - /* Port control 2 */ - uint32_t ctrl2; - /* Timer Reload */ - uint32_t timer_reload; - /* Maximum packet length */ - uint32_t packet_length; + uint32_t flag; + /* Port control */ + uint32_t ctrl; + /* Port status */ + uint32_t sts; + /* Port control 2 */ + uint32_t ctrl2; + /* Timer Reload */ + uint32_t timer_reload; + /* Maximum packet length */ + uint32_t packet_length; }; /* Register GRSPW Router driver to Driver Manager */ -void router_register_drv(void); +void router_register_drv( void ); -extern void *router_open(unsigned int dev_no); -extern int router_close(void *d); -extern int router_print(void *d); -extern int router_hwinfo_get(void *d, struct router_hw_info *hwinfo); +extern void *router_open( unsigned int dev_no ); +extern int router_close( void *d ); +extern int router_print( void *d ); +extern int router_hwinfo_get( void *d, struct router_hw_info *hwinfo ); /* Router general config */ -extern int router_config_set(void *d, struct router_config *cfg); -extern int router_config_get(void *d, struct router_config *cfg); +extern int router_config_set( void *d, struct router_config *cfg ); +extern int router_config_get( void *d, struct router_config *cfg ); /* Routing table config */ -extern int router_routing_table_set(void *d, - struct router_routing_table *cfg); -extern int router_routing_table_get(void *d, - struct router_routing_table *cfg); +extern int router_routing_table_set( + void *d, + struct router_routing_table *cfg +); +extern int router_routing_table_get( + void *d, + struct router_routing_table *cfg +); /* * ROUTER PCTRL register fields */ -#define PCTRL_RD (0xff << PCTRL_RD_BIT) -#define PCTRL_ST (0x1 << PCTRL_ST_BIT) -#define PCTRL_SR (0x1 << PCTRL_SR_BIT) -#define PCTRL_AD (0x1 << PCTRL_AD_BIT) -#define PCTRL_LR (0x1 << PCTRL_LR_BIT) -#define PCTRL_PL (0x1 << PCTRL_PL_BIT) -#define PCTRL_TS (0x1 << PCTRL_TS_BIT) -#define PCTRL_IC (0x1 << PCTRL_IC_BIT) -#define PCTRL_ET (0x1 << PCTRL_ET_BIT) -#define PCTRL_NP (0x1 << PCTRL_NP_BIT) -#define PCTRL_PS (0x1 << PCTRL_PS_BIT) -#define PCTRL_BE (0x1 << PCTRL_BE_BIT) -#define PCTRL_DI (0x1 << PCTRL_DI_BIT) -#define PCTRL_TR (0x1 << PCTRL_TR_BIT) -#define PCTRL_PR (0x1 << PCTRL_PR_BIT) -#define PCTRL_TF (0x1 << PCTRL_TF_BIT) -#define PCTRL_RS (0x1 << PCTRL_RS_BIT) -#define PCTRL_TE (0x1 << PCTRL_TE_BIT) -#define PCTRL_CE (0x1 << PCTRL_CE_BIT) -#define PCTRL_AS (0x1 << PCTRL_AS_BIT) -#define PCTRL_LS (0x1 << PCTRL_LS_BIT) -#define PCTRL_LD (0x1 << PCTRL_LD_BIT) +#define PCTRL_RD ( 0xff << PCTRL_RD_BIT ) +#define PCTRL_ST ( 0x1 << PCTRL_ST_BIT ) +#define PCTRL_SR ( 0x1 << PCTRL_SR_BIT ) +#define PCTRL_AD ( 0x1 << PCTRL_AD_BIT ) +#define PCTRL_LR ( 0x1 << PCTRL_LR_BIT ) +#define PCTRL_PL ( 0x1 << PCTRL_PL_BIT ) +#define PCTRL_TS ( 0x1 << PCTRL_TS_BIT ) +#define PCTRL_IC ( 0x1 << PCTRL_IC_BIT ) +#define PCTRL_ET ( 0x1 << PCTRL_ET_BIT ) +#define PCTRL_NP ( 0x1 << PCTRL_NP_BIT ) +#define PCTRL_PS ( 0x1 << PCTRL_PS_BIT ) +#define PCTRL_BE ( 0x1 << PCTRL_BE_BIT ) +#define PCTRL_DI ( 0x1 << PCTRL_DI_BIT ) +#define PCTRL_TR ( 0x1 << PCTRL_TR_BIT ) +#define PCTRL_PR ( 0x1 << PCTRL_PR_BIT ) +#define PCTRL_TF ( 0x1 << PCTRL_TF_BIT ) +#define PCTRL_RS ( 0x1 << PCTRL_RS_BIT ) +#define PCTRL_TE ( 0x1 << PCTRL_TE_BIT ) +#define PCTRL_CE ( 0x1 << PCTRL_CE_BIT ) +#define PCTRL_AS ( 0x1 << PCTRL_AS_BIT ) +#define PCTRL_LS ( 0x1 << PCTRL_LS_BIT ) +#define PCTRL_LD ( 0x1 << PCTRL_LD_BIT ) #define PCTRL_RD_BIT 24 #define PCTRL_ST_BIT 21 @@ -212,16 +216,16 @@ extern int router_routing_table_get(void *d, /* * ROUTER PCTRL2 register fields */ -#define PCTRL2_SM (0xff << PCTRL2_SM_BIT) -#define PCTRL2_SV (0xff << PCTRL2_SV_BIT) -#define PCTRL2_OR (0x1 << PCTRL2_OR_BIT) -#define PCTRL2_UR (0x1 << PCTRL2_UR_BIT) -#define PCTRL2_AT (0x1 << PCTRL2_AT_BIT) -#define PCTRL2_AR (0x1 << PCTRL2_AR_BIT) -#define PCTRL2_IT (0x1 << PCTRL2_IT_BIT) -#define PCTRL2_IR (0x1 << PCTRL2_IR_BIT) -#define PCTRL2_SD (0x1f << PCTRL2_SD_BIT) -#define PCTRL2_SC (0x1f << PCTRL2_SC_BIT) +#define PCTRL2_SM ( 0xff << PCTRL2_SM_BIT ) +#define PCTRL2_SV ( 0xff << PCTRL2_SV_BIT ) +#define PCTRL2_OR ( 0x1 << PCTRL2_OR_BIT ) +#define PCTRL2_UR ( 0x1 << PCTRL2_UR_BIT ) +#define PCTRL2_AT ( 0x1 << PCTRL2_AT_BIT ) +#define PCTRL2_AR ( 0x1 << PCTRL2_AR_BIT ) +#define PCTRL2_IT ( 0x1 << PCTRL2_IT_BIT ) +#define PCTRL2_IR ( 0x1 << PCTRL2_IR_BIT ) +#define PCTRL2_SD ( 0x1f << PCTRL2_SD_BIT ) +#define PCTRL2_SC ( 0x1f << PCTRL2_SC_BIT ) #define PCTRL2_SM_BIT 24 #define PCTRL2_SV_BIT 16 @@ -235,51 +239,73 @@ extern int router_routing_table_get(void *d, #define PCTRL2_SC_BIT 0 /* Router Set/Get Port configuration */ -extern int router_port_ioc(void *d, int port, struct router_port *cfg); +extern int router_port_ioc( void *d, int port, struct router_port *cfg ); /* Read-modify-write Port Control register */ -extern int router_port_ctrl_rmw(void *d, int port, uint32_t *oldvalue, uint32_t bitmask, uint32_t value); +extern int router_port_ctrl_rmw( + void *d, + int port, + uint32_t *oldvalue, + uint32_t bitmask, + uint32_t value +); /* Read-modify-write Port Control2 register */ -extern int router_port_ctrl2_rmw(void *d, int port, uint32_t *oldvalue, uint32_t bitmask, uint32_t value); +extern int router_port_ctrl2_rmw( + void *d, + int port, + uint32_t *oldvalue, + uint32_t bitmask, + uint32_t value +); /* Read Port Control register */ -extern int router_port_ctrl_get(void *d, int port, uint32_t *ctrl); +extern int router_port_ctrl_get( void *d, int port, uint32_t *ctrl ); /* Read Port Control2 register */ -extern int router_port_ctrl2_get(void *d, int port, uint32_t *ctrl2); +extern int router_port_ctrl2_get( void *d, int port, uint32_t *ctrl2 ); /* Write Port Control Register */ -extern int router_port_ctrl_set(void *d, int port, uint32_t mask, uint32_t ctrl); +extern int router_port_ctrl_set( + void *d, + int port, + uint32_t mask, + uint32_t ctrl +); /* Write Port Control2 Register */ -extern int router_port_ctrl2_set(void *d, int port, uint32_t mask, uint32_t ctrl2); +extern int router_port_ctrl2_set( + void *d, + int port, + uint32_t mask, + uint32_t ctrl2 +); /* Set Timer Reload Value for a specific port */ -extern int router_port_treload_set(void *d, int port, uint32_t reload); +extern int router_port_treload_set( void *d, int port, uint32_t reload ); /* Get Timer Reload Value for a specific port */ -extern int router_port_treload_get(void *d, int port, uint32_t *reload); +extern int router_port_treload_get( void *d, int port, uint32_t *reload ); /* Get Maximum packet length for a specific port */ -extern int router_port_maxplen_get(void *d, int port, uint32_t *length); +extern int router_port_maxplen_get( void *d, int port, uint32_t *length ); /* Set Maximum packet length for a specific port */ -extern int router_port_maxplen_set(void *d, int port, uint32_t length); +extern int router_port_maxplen_set( void *d, int port, uint32_t length ); /* * ROUTER PSTSCFG register fields */ -#define PSTSCFG_EO (0x1 << PSTSCFG_EO_BIT) -#define PSTSCFG_EE (0x1 << PSTSCFG_EE_BIT) -#define PSTSCFG_PL (0x1 << PSTSCFG_PL_BIT) -#define PSTSCFG_TT (0x1 << PSTSCFG_TT_BIT) -#define PSTSCFG_PT (0x1 << PSTSCFG_PT_BIT) -#define PSTSCFG_HC (0x1 << PSTSCFG_HC_BIT) -#define PSTSCFG_PI (0x1 << PSTSCFG_PI_BIT) -#define PSTSCFG_CE (0x1 << PSTSCFG_CE_BIT) -#define PSTSCFG_EC (0xf << PSTSCFG_EC_BIT) -#define PSTSCFG_TS (0x1 << PSTSCFG_TS_BIT) -#define PSTSCFG_ME (0x1 << PSTSCFG_ME_BIT) -#define PSTSCFG_IP (0x1f << PSTSCFG_IP_BIT) -#define PSTSCFG_CP (0x1 << PSTSCFG_CP_BIT) -#define PSTSCFG_PC (0xf << PSTSCFG_PC_BIT) -#define PSTSCFG_WCLEAR (PSTSCFG_EO | PSTSCFG_EE | PSTSCFG_PL | \ - PSTSCFG_TT | PSTSCFG_PT | PSTSCFG_HC | \ - PSTSCFG_PI | PSTSCFG_CE | PSTSCFG_TS | \ - PSTSCFG_ME | PSTSCFG_CP) -#define PSTSCFG_WCLEAR2 (PSTSCFG_CE | PSTSCFG_CP) +#define PSTSCFG_EO ( 0x1 << PSTSCFG_EO_BIT ) +#define PSTSCFG_EE ( 0x1 << PSTSCFG_EE_BIT ) +#define PSTSCFG_PL ( 0x1 << PSTSCFG_PL_BIT ) +#define PSTSCFG_TT ( 0x1 << PSTSCFG_TT_BIT ) +#define PSTSCFG_PT ( 0x1 << PSTSCFG_PT_BIT ) +#define PSTSCFG_HC ( 0x1 << PSTSCFG_HC_BIT ) +#define PSTSCFG_PI ( 0x1 << PSTSCFG_PI_BIT ) +#define PSTSCFG_CE ( 0x1 << PSTSCFG_CE_BIT ) +#define PSTSCFG_EC ( 0xf << PSTSCFG_EC_BIT ) +#define PSTSCFG_TS ( 0x1 << PSTSCFG_TS_BIT ) +#define PSTSCFG_ME ( 0x1 << PSTSCFG_ME_BIT ) +#define PSTSCFG_IP ( 0x1f << PSTSCFG_IP_BIT ) +#define PSTSCFG_CP ( 0x1 << PSTSCFG_CP_BIT ) +#define PSTSCFG_PC ( 0xf << PSTSCFG_PC_BIT ) +#define PSTSCFG_WCLEAR \ + ( PSTSCFG_EO | PSTSCFG_EE | PSTSCFG_PL | PSTSCFG_TT | PSTSCFG_PT | \ + PSTSCFG_HC | PSTSCFG_PI | PSTSCFG_CE | PSTSCFG_TS | PSTSCFG_ME | \ + PSTSCFG_CP ) +#define PSTSCFG_WCLEAR2 ( PSTSCFG_CE | PSTSCFG_CP ) #define PSTSCFG_EO_BIT 31 #define PSTSCFG_EE_BIT 30 @@ -299,30 +325,30 @@ extern int router_port_maxplen_set(void *d, int port, uint32_t length); /* * ROUTER PSTS register fields */ -#define PSTS_PT (0x3 << PSTS_PT_BIT) -#define PSTS_PL (0x1 << PSTS_PL_BIT) -#define PSTS_TT (0x1 << PSTS_TT_BIT) -#define PSTS_RS (0x1 << PSTS_RS_BIT) -#define PSTS_SR (0x1 << PSTS_SR_BIT) -#define PSTS_LR (0x1 << PSTS_LR_BIT) -#define PSTS_SP (0x1 << PSTS_SP_BIT) -#define PSTS_AC (0x1 << PSTS_AC_BIT) -#define PSTS_TS (0x1 << PSTS_TS_BIT) -#define PSTS_ME (0x1 << PSTS_ME_BIT) -#define PSTS_TF (0x1 << PSTS_TF_BIT) -#define PSTS_RE (0x1 << PSTS_RE_BIT) -#define PSTS_LS (0x7 << PSTS_LS_BIT) -#define PSTS_IP (0x1f << PSTS_IP_BIT) -#define PSTS_PR (0x1 << PSTS_PR_BIT) -#define PSTS_PB (0x1 << PSTS_PB_BIT) -#define PSTS_IA (0x1 << PSTS_IA_BIT) -#define PSTS_CE (0x1 << PSTS_CE_BIT) -#define PSTS_ER (0x1 << PSTS_ER_BIT) -#define PSTS_DE (0x1 << PSTS_DE_BIT) -#define PSTS_PE (0x1 << PSTS_PE_BIT) -#define PSTS_WCLEAR (PSTS_PL | PSTS_TT | PSTS_RS | PSTS_SR | \ - PSTS_TS | PSTS_ME | PSTS_IA | PSTS_CE | \ - PSTS_ER | PSTS_DE | PSTS_PE) +#define PSTS_PT ( 0x3 << PSTS_PT_BIT ) +#define PSTS_PL ( 0x1 << PSTS_PL_BIT ) +#define PSTS_TT ( 0x1 << PSTS_TT_BIT ) +#define PSTS_RS ( 0x1 << PSTS_RS_BIT ) +#define PSTS_SR ( 0x1 << PSTS_SR_BIT ) +#define PSTS_LR ( 0x1 << PSTS_LR_BIT ) +#define PSTS_SP ( 0x1 << PSTS_SP_BIT ) +#define PSTS_AC ( 0x1 << PSTS_AC_BIT ) +#define PSTS_TS ( 0x1 << PSTS_TS_BIT ) +#define PSTS_ME ( 0x1 << PSTS_ME_BIT ) +#define PSTS_TF ( 0x1 << PSTS_TF_BIT ) +#define PSTS_RE ( 0x1 << PSTS_RE_BIT ) +#define PSTS_LS ( 0x7 << PSTS_LS_BIT ) +#define PSTS_IP ( 0x1f << PSTS_IP_BIT ) +#define PSTS_PR ( 0x1 << PSTS_PR_BIT ) +#define PSTS_PB ( 0x1 << PSTS_PB_BIT ) +#define PSTS_IA ( 0x1 << PSTS_IA_BIT ) +#define PSTS_CE ( 0x1 << PSTS_CE_BIT ) +#define PSTS_ER ( 0x1 << PSTS_ER_BIT ) +#define PSTS_DE ( 0x1 << PSTS_DE_BIT ) +#define PSTS_PE ( 0x1 << PSTS_PE_BIT ) +#define PSTS_WCLEAR \ + ( PSTS_PL | PSTS_TT | PSTS_RS | PSTS_SR | PSTS_TS | PSTS_ME | PSTS_IA | \ + PSTS_CE | PSTS_ER | PSTS_DE | PSTS_PE ) #define PSTS_PT_BIT 30 #define PSTS_PL_BIT 29 @@ -347,35 +373,40 @@ extern int router_port_maxplen_set(void *d, int port, uint32_t length); #define PSTS_PE_BIT 0 /* Check Port Status register and clear errors if there are */ -extern int router_port_status(void *d, int port, uint32_t *sts, uint32_t clrmsk); +extern int router_port_status( + void *d, + int port, + uint32_t *sts, + uint32_t clrmsk +); #define ROUTER_LINK_STATUS_ERROR_RESET 0 -#define ROUTER_LINK_STATUS_ERROR_WAIT 1 -#define ROUTER_LINK_STATUS_READY 2 -#define ROUTER_LINK_STATUS_STARTED 3 -#define ROUTER_LINK_STATUS_CONNECTING 4 -#define ROUTER_LINK_STATUS_RUN_STATE 5 +#define ROUTER_LINK_STATUS_ERROR_WAIT 1 +#define ROUTER_LINK_STATUS_READY 2 +#define ROUTER_LINK_STATUS_STARTED 3 +#define ROUTER_LINK_STATUS_CONNECTING 4 +#define ROUTER_LINK_STATUS_RUN_STATE 5 /* Get Link status */ -extern int router_port_link_status(void *d, int port); +extern int router_port_link_status( void *d, int port ); /* Operate a Link */ -extern int router_port_enable(void *d, int port); -extern int router_port_disable(void *d, int port); -extern int router_port_link_stop(void *d, int port); -extern int router_port_link_start(void *d, int port); -extern int router_port_link_div(void *d, int port, int rundiv); -extern int router_port_link_receive_spill(void *d, int port); -extern int router_port_link_transmit_reset(void *d, int port); +extern int router_port_enable( void *d, int port ); +extern int router_port_disable( void *d, int port ); +extern int router_port_link_stop( void *d, int port ); +extern int router_port_link_start( void *d, int port ); +extern int router_port_link_div( void *d, int port, int rundiv ); +extern int router_port_link_receive_spill( void *d, int port ); +extern int router_port_link_transmit_reset( void *d, int port ); /* Get port credit counter register */ -extern int router_port_cred_get(void *d, int port, uint32_t *cred); +extern int router_port_cred_get( void *d, int port, uint32_t *cred ); /* * ROUTER RTACTRL register fields */ -#define RTACTRL_SR (0x1 << RTACTRL_SR_BIT) -#define RTACTRL_EN (0x1 << RTACTRL_EN_BIT) -#define RTACTRL_PR (0x1 << RTACTRL_PR_BIT) -#define RTACTRL_HD (0x1 << RTACTRL_HD_BIT) +#define RTACTRL_SR ( 0x1 << RTACTRL_SR_BIT ) +#define RTACTRL_EN ( 0x1 << RTACTRL_EN_BIT ) +#define RTACTRL_PR ( 0x1 << RTACTRL_PR_BIT ) +#define RTACTRL_HD ( 0x1 << RTACTRL_HD_BIT ) #define RTACTRL_SR_BIT 3 #define RTACTRL_EN_BIT 2 @@ -383,75 +414,75 @@ extern int router_port_cred_get(void *d, int port, uint32_t *cred); #define RTACTRL_HD_BIT 0 /* Individual route modification */ -#define ROUTER_ROUTE_PACKETDISTRIBUTION_ENABLE (0x1 << 16) -#define ROUTER_ROUTE_PACKETDISTRIBUTION_DISABLE (0x0 << 16) -#define ROUTER_ROUTE_SPILLIFNOTREADY_ENABLE RTACTRL_SR -#define ROUTER_ROUTE_SPILLIFNOTREADY_DISABLE 0 -#define ROUTER_ROUTE_ENABLE RTACTRL_EN -#define ROUTER_ROUTE_DISABLE 0 -#define ROUTER_ROUTE_PRIORITY_HIGH RTACTRL_PR -#define ROUTER_ROUTE_PRIORITY_LOW 0 -#define ROUTER_ROUTE_HEADERDELETION_ENABLE RTACTRL_HD -#define ROUTER_ROUTE_HEADERDELETION_DISABLE 0 +#define ROUTER_ROUTE_PACKETDISTRIBUTION_ENABLE ( 0x1 << 16 ) +#define ROUTER_ROUTE_PACKETDISTRIBUTION_DISABLE ( 0x0 << 16 ) +#define ROUTER_ROUTE_SPILLIFNOTREADY_ENABLE RTACTRL_SR +#define ROUTER_ROUTE_SPILLIFNOTREADY_DISABLE 0 +#define ROUTER_ROUTE_ENABLE RTACTRL_EN +#define ROUTER_ROUTE_DISABLE 0 +#define ROUTER_ROUTE_PRIORITY_HIGH RTACTRL_PR +#define ROUTER_ROUTE_PRIORITY_LOW 0 +#define ROUTER_ROUTE_HEADERDELETION_ENABLE RTACTRL_HD +#define ROUTER_ROUTE_HEADERDELETION_DISABLE 0 struct router_route { - uint8_t from_address; - uint8_t to_port[32]; - int count; - int options; + uint8_t from_address; + uint8_t to_port[ 32 ]; + int count; + int options; }; -extern int router_route_set(void *d, struct router_route *route); -extern int router_route_get(void *d, struct router_route *route); +extern int router_route_set( void *d, struct router_route *route ); +extern int router_route_get( void *d, struct router_route *route ); /* Router configuration port write enable */ -extern int router_write_enable(void *d); -extern int router_write_disable(void *d); +extern int router_write_enable( void *d ); +extern int router_write_disable( void *d ); /* Router reset */ -extern int router_reset(void *d); +extern int router_reset( void *d ); /* Set Instance ID */ -extern int router_instance_set(void *d, uint8_t iid); +extern int router_instance_set( void *d, uint8_t iid ); /* Get Instance ID */ -extern int router_instance_get(void *d, uint8_t *iid); +extern int router_instance_get( void *d, uint8_t *iid ); /* Set SpaceWire Link Initialization Clock Divisor */ -extern int router_idiv_set(void *d, uint8_t idiv); +extern int router_idiv_set( void *d, uint8_t idiv ); /* Get SpaceWire Link Initialization Clock Divisor */ -extern int router_idiv_get(void *d, uint8_t *idiv); +extern int router_idiv_get( void *d, uint8_t *idiv ); /* Set Timer Prescaler */ -extern int router_tpresc_set(void *d, uint32_t prescaler); +extern int router_tpresc_set( void *d, uint32_t prescaler ); /* Get Timer Prescaler */ -extern int router_tpresc_get(void *d, uint32_t *prescaler); +extern int router_tpresc_get( void *d, uint32_t *prescaler ); /* Set/get Router configuration */ -extern int router_cfgsts_set(void *d, uint32_t cfgsts); -extern int router_cfgsts_get(void *d, uint32_t *cfgsts); +extern int router_cfgsts_set( void *d, uint32_t cfgsts ); +extern int router_cfgsts_get( void *d, uint32_t *cfgsts ); /* Router timecode */ -extern int router_tc_enable(void *d); -extern int router_tc_disable(void *d); -extern int router_tc_reset(void *d); -extern int router_tc_get(void *d); +extern int router_tc_enable( void *d ); +extern int router_tc_disable( void *d ); +extern int router_tc_reset( void *d ); +extern int router_tc_get( void *d ); /* Router Interrupts */ /* * ROUTER IMASK register fields */ -#define IMASK_PE (0x1 << IMASK_PE_BIT) -#define IMASK_SR (0x1 << IMASK_SR_BIT) -#define IMASK_RS (0x1 << IMASK_RS_BIT) -#define IMASK_TT (0x1 << IMASK_TT_BIT) -#define IMASK_PL (0x1 << IMASK_PL_BIT) -#define IMASK_TS (0x1 << IMASK_TS_BIT) -#define IMASK_AC (0x1 << IMASK_AC_BIT) -#define IMASK_RE (0x1 << IMASK_RE_BIT) -#define IMASK_IA (0x1 << IMASK_IA_BIT) -#define IMASK_LE (0x1 << IMASK_LE_BIT) -#define IMASK_ME (0x1 << IMASK_ME_BIT) -#define IMASK_ALL ( IMASK_PE | IMASK_SR | IMASK_RS | IMASK_TT \ - IMASK_PL | IMASK_TS | IMASK_AC | IMASK_RE | IMASK_IA \ - IMASK_LE | IMASK_ME) +#define IMASK_PE ( 0x1 << IMASK_PE_BIT ) +#define IMASK_SR ( 0x1 << IMASK_SR_BIT ) +#define IMASK_RS ( 0x1 << IMASK_RS_BIT ) +#define IMASK_TT ( 0x1 << IMASK_TT_BIT ) +#define IMASK_PL ( 0x1 << IMASK_PL_BIT ) +#define IMASK_TS ( 0x1 << IMASK_TS_BIT ) +#define IMASK_AC ( 0x1 << IMASK_AC_BIT ) +#define IMASK_RE ( 0x1 << IMASK_RE_BIT ) +#define IMASK_IA ( 0x1 << IMASK_IA_BIT ) +#define IMASK_LE ( 0x1 << IMASK_LE_BIT ) +#define IMASK_ME ( 0x1 << IMASK_ME_BIT ) +#define IMASK_ALL \ + ( IMASK_PE | IMASK_SR | IMASK_RS | IMASK_TT IMASK_PL | IMASK_TS | \ + IMASK_AC | IMASK_RE | IMASK_IA IMASK_LE | IMASK_ME ) #define IMASK_PE_BIT 10 #define IMASK_SR_BIT 9 @@ -465,33 +496,33 @@ extern int router_tc_get(void *d); #define IMASK_LE_BIT 1 #define IMASK_ME_BIT 0 -#define ROUTER_INTERRUPT_ALL IMASK_ALL -#define ROUTER_INTERRUPT_SPWPNP_ERROR IMASK_PE -#define ROUTER_INTERRUPT_SPILLED IMASK_SR -#define ROUTER_INTERRUPT_RUNSTATE IMASK_RS -#define ROUTER_INTERRUPT_TC_TRUNCATION IMASK_TT +#define ROUTER_INTERRUPT_ALL IMASK_ALL +#define ROUTER_INTERRUPT_SPWPNP_ERROR IMASK_PE +#define ROUTER_INTERRUPT_SPILLED IMASK_SR +#define ROUTER_INTERRUPT_RUNSTATE IMASK_RS +#define ROUTER_INTERRUPT_TC_TRUNCATION IMASK_TT #define ROUTER_INTERRUPT_PACKET_TRUNCATION IMASK_PL -#define ROUTER_INTERRUPT_TIMEOUT IMASK_TS -#define ROUTER_INTERRUPT_CFGPORT IMASK_AC -#define ROUTER_INTERRUPT_RMAP_ERROR IMASK_RE -#define ROUTER_INTERRUPT_INVALID_ADDRESS IMASK_IA -#define ROUTER_INTERRUPT_LINK_ERROR IMASK_LE -#define ROUTER_INTERRUPT_MEMORY_ERROR IMASK_ME -extern int router_port_interrupt_unmask(void *d, int port); -extern int router_port_interrupt_mask(void *d, int port); -extern int router_interrupt_unmask(void *d, int options); -extern int router_interrupt_mask(void *d, int options); +#define ROUTER_INTERRUPT_TIMEOUT IMASK_TS +#define ROUTER_INTERRUPT_CFGPORT IMASK_AC +#define ROUTER_INTERRUPT_RMAP_ERROR IMASK_RE +#define ROUTER_INTERRUPT_INVALID_ADDRESS IMASK_IA +#define ROUTER_INTERRUPT_LINK_ERROR IMASK_LE +#define ROUTER_INTERRUPT_MEMORY_ERROR IMASK_ME +extern int router_port_interrupt_unmask( void *d, int port ); +extern int router_port_interrupt_mask( void *d, int port ); +extern int router_interrupt_unmask( void *d, int options ); +extern int router_interrupt_mask( void *d, int options ); /* Router Interrupt code generation */ /* * ROUTER ICODEGEN register fields */ -#define ICODEGEN_UA (0x1 << ICODEGEN_UA_BIT) -#define ICODEGEN_AH (0x1 << ICODEGEN_AH_BIT) -#define ICODEGEN_IT (0x1 << ICODEGEN_IT_BIT) -#define ICODEGEN_TE (0x1 << ICODEGEN_TE_BIT) -#define ICODEGEN_EN (0x1 << ICODEGEN_EN_BIT) -#define ICODEGEN_IN (0x1f << ICODEGEN_IN_BIT) +#define ICODEGEN_UA ( 0x1 << ICODEGEN_UA_BIT ) +#define ICODEGEN_AH ( 0x1 << ICODEGEN_AH_BIT ) +#define ICODEGEN_IT ( 0x1 << ICODEGEN_IT_BIT ) +#define ICODEGEN_TE ( 0x1 << ICODEGEN_TE_BIT ) +#define ICODEGEN_EN ( 0x1 << ICODEGEN_EN_BIT ) +#define ICODEGEN_IN ( 0x1f << ICODEGEN_IN_BIT ) #define ICODEGEN_UA_BIT 20 #define ICODEGEN_AH_BIT 19 @@ -500,23 +531,27 @@ extern int router_interrupt_mask(void *d, int options); #define ICODEGEN_EN_BIT 16 #define ICODEGEN_IN_BIT 0 -#define ROUTER_ICODEGEN_ITYPE_EDGE ICODEGEN_IT -#define ROUTER_ICODEGEN_ITYPE_LEVEL 0 -#define ROUTER_ICODEGEN_AUTOUNACK_ENABLE ICODEGEN_UA +#define ROUTER_ICODEGEN_ITYPE_EDGE ICODEGEN_IT +#define ROUTER_ICODEGEN_ITYPE_LEVEL 0 +#define ROUTER_ICODEGEN_AUTOUNACK_ENABLE ICODEGEN_UA #define ROUTER_ICODEGEN_AUTOUNACK_DISABLE 0 -#define ROUTER_ICODEGEN_AUTOACK_ENABLE ICODEGEN_AH -#define ROUTER_ICODEGEN_AUTOACK_DISABLE 0 -extern int router_icodegen_enable(void *d, uint8_t intn, uint32_t aitimer, - int options); -extern int router_icodegen_disable(void *d); +#define ROUTER_ICODEGEN_AUTOACK_ENABLE ICODEGEN_AH +#define ROUTER_ICODEGEN_AUTOACK_DISABLE 0 +extern int router_icodegen_enable( + void *d, + uint8_t intn, + uint32_t aitimer, + int options +); +extern int router_icodegen_disable( void *d ); /* Router interrupt change timers */ -extern int router_isrctimer_set(void *d, uint32_t reloadvalue); -extern int router_isrctimer_get(void *d, uint32_t *reloadvalue); +extern int router_isrctimer_set( void *d, uint32_t reloadvalue ); +extern int router_isrctimer_get( void *d, uint32_t *reloadvalue ); /* Router interrupt timers */ -extern int router_isrtimer_set(void *d, uint32_t reloadvalue); -extern int router_isrtimer_get(void *d, uint32_t *reloadvalue); +extern int router_isrtimer_set( void *d, uint32_t reloadvalue ); +extern int router_isrtimer_get( void *d, uint32_t *reloadvalue ); #ifdef __cplusplus } diff --git a/bsps/include/grlib/grspwrouter-regs.h b/bsps/include/grlib/grspwrouter-regs.h index 5b18ea8cad..f074d59110 100644 --- a/bsps/include/grlib/grspwrouter-regs.h +++ b/bsps/include/grlib/grspwrouter-regs.h @@ -85,15 +85,15 @@ extern "C" { #define GRSPWROUTER_OCHARCNT_OR 0x80000000U #define GRSPWROUTER_OCHARCNT_CC_SHIFT 0 -#define GRSPWROUTER_OCHARCNT_CC_MASK 0x7fffffffU -#define GRSPWROUTER_OCHARCNT_CC_GET( _reg ) \ +#define GRSPWROUTER_OCHARCNT_CC_MASK 0x7fffffffU +#define GRSPWROUTER_OCHARCNT_CC_GET( _reg ) \ ( ( ( _reg ) & GRSPWROUTER_OCHARCNT_CC_MASK ) >> \ GRSPWROUTER_OCHARCNT_CC_SHIFT ) -#define GRSPWROUTER_OCHARCNT_CC_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPWROUTER_OCHARCNT_CC_MASK ) | \ +#define GRSPWROUTER_OCHARCNT_CC_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_OCHARCNT_CC_MASK ) | \ ( ( ( _val ) << GRSPWROUTER_OCHARCNT_CC_SHIFT ) & \ GRSPWROUTER_OCHARCNT_CC_MASK ) ) -#define GRSPWROUTER_OCHARCNT_CC( _val ) \ +#define GRSPWROUTER_OCHARCNT_CC( _val ) \ ( ( ( _val ) << GRSPWROUTER_OCHARCNT_CC_SHIFT ) & \ GRSPWROUTER_OCHARCNT_CC_MASK ) @@ -111,15 +111,15 @@ extern "C" { #define GRSPWROUTER_ICHARCNT_OR 0x80000000U #define GRSPWROUTER_ICHARCNT_CC_SHIFT 0 -#define GRSPWROUTER_ICHARCNT_CC_MASK 0x7fffffffU -#define GRSPWROUTER_ICHARCNT_CC_GET( _reg ) \ +#define GRSPWROUTER_ICHARCNT_CC_MASK 0x7fffffffU +#define GRSPWROUTER_ICHARCNT_CC_GET( _reg ) \ ( ( ( _reg ) & GRSPWROUTER_ICHARCNT_CC_MASK ) >> \ GRSPWROUTER_ICHARCNT_CC_SHIFT ) -#define GRSPWROUTER_ICHARCNT_CC_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPWROUTER_ICHARCNT_CC_MASK ) | \ +#define GRSPWROUTER_ICHARCNT_CC_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_ICHARCNT_CC_MASK ) | \ ( ( ( _val ) << GRSPWROUTER_ICHARCNT_CC_SHIFT ) & \ GRSPWROUTER_ICHARCNT_CC_MASK ) ) -#define GRSPWROUTER_ICHARCNT_CC( _val ) \ +#define GRSPWROUTER_ICHARCNT_CC( _val ) \ ( ( ( _val ) << GRSPWROUTER_ICHARCNT_CC_SHIFT ) & \ GRSPWROUTER_ICHARCNT_CC_MASK ) @@ -137,15 +137,15 @@ extern "C" { #define GRSPWROUTER_OPKTCNT_OR 0x80000000U #define GRSPWROUTER_OPKTCNT_PC_SHIFT 0 -#define GRSPWROUTER_OPKTCNT_PC_MASK 0x7fffffffU -#define GRSPWROUTER_OPKTCNT_PC_GET( _reg ) \ +#define GRSPWROUTER_OPKTCNT_PC_MASK 0x7fffffffU +#define GRSPWROUTER_OPKTCNT_PC_GET( _reg ) \ ( ( ( _reg ) & GRSPWROUTER_OPKTCNT_PC_MASK ) >> \ GRSPWROUTER_OPKTCNT_PC_SHIFT ) -#define GRSPWROUTER_OPKTCNT_PC_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPWROUTER_OPKTCNT_PC_MASK ) | \ +#define GRSPWROUTER_OPKTCNT_PC_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_OPKTCNT_PC_MASK ) | \ ( ( ( _val ) << GRSPWROUTER_OPKTCNT_PC_SHIFT ) & \ GRSPWROUTER_OPKTCNT_PC_MASK ) ) -#define GRSPWROUTER_OPKTCNT_PC( _val ) \ +#define GRSPWROUTER_OPKTCNT_PC( _val ) \ ( ( ( _val ) << GRSPWROUTER_OPKTCNT_PC_SHIFT ) & \ GRSPWROUTER_OPKTCNT_PC_MASK ) @@ -163,15 +163,15 @@ extern "C" { #define GRSPWROUTER_IPKTCNT_OR 0x80000000U #define GRSPWROUTER_IPKTCNT_PC_SHIFT 0 -#define GRSPWROUTER_IPKTCNT_PC_MASK 0x7fffffffU -#define GRSPWROUTER_IPKTCNT_PC_GET( _reg ) \ +#define GRSPWROUTER_IPKTCNT_PC_MASK 0x7fffffffU +#define GRSPWROUTER_IPKTCNT_PC_GET( _reg ) \ ( ( ( _reg ) & GRSPWROUTER_IPKTCNT_PC_MASK ) >> \ GRSPWROUTER_IPKTCNT_PC_SHIFT ) -#define GRSPWROUTER_IPKTCNT_PC_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPWROUTER_IPKTCNT_PC_MASK ) | \ +#define GRSPWROUTER_IPKTCNT_PC_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_IPKTCNT_PC_MASK ) | \ ( ( ( _val ) << GRSPWROUTER_IPKTCNT_PC_SHIFT ) & \ GRSPWROUTER_IPKTCNT_PC_MASK ) ) -#define GRSPWROUTER_IPKTCNT_PC( _val ) \ +#define GRSPWROUTER_IPKTCNT_PC( _val ) \ ( ( ( _val ) << GRSPWROUTER_IPKTCNT_PC_SHIFT ) & \ GRSPWROUTER_IPKTCNT_PC_MASK ) @@ -227,17 +227,15 @@ typedef struct grspwrouter_portstats { */ #define GRSPWROUTER_RTPMAP_PE_SHIFT 1 -#define GRSPWROUTER_RTPMAP_PE_MASK 0xfffffffeU +#define GRSPWROUTER_RTPMAP_PE_MASK 0xfffffffeU #define GRSPWROUTER_RTPMAP_PE_GET( _reg ) \ - ( ( ( _reg ) & GRSPWROUTER_RTPMAP_PE_MASK ) >> \ - GRSPWROUTER_RTPMAP_PE_SHIFT ) -#define GRSPWROUTER_RTPMAP_PE_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPWROUTER_RTPMAP_PE_MASK ) | \ + ( ( ( _reg ) & GRSPWROUTER_RTPMAP_PE_MASK ) >> GRSPWROUTER_RTPMAP_PE_SHIFT ) +#define GRSPWROUTER_RTPMAP_PE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_RTPMAP_PE_MASK ) | \ ( ( ( _val ) << GRSPWROUTER_RTPMAP_PE_SHIFT ) & \ GRSPWROUTER_RTPMAP_PE_MASK ) ) #define GRSPWROUTER_RTPMAP_PE( _val ) \ - ( ( ( _val ) << GRSPWROUTER_RTPMAP_PE_SHIFT ) & \ - GRSPWROUTER_RTPMAP_PE_MASK ) + ( ( ( _val ) << GRSPWROUTER_RTPMAP_PE_SHIFT ) & GRSPWROUTER_RTPMAP_PE_MASK ) #define GRSPWROUTER_RTPMAP_PD 0x1U @@ -288,30 +286,26 @@ typedef struct grspwrouter_portstats { */ #define GRSPWROUTER_PCTRL_RD_SHIFT 24 -#define GRSPWROUTER_PCTRL_RD_MASK 0xff000000U +#define GRSPWROUTER_PCTRL_RD_MASK 0xff000000U #define GRSPWROUTER_PCTRL_RD_GET( _reg ) \ - ( ( ( _reg ) & GRSPWROUTER_PCTRL_RD_MASK ) >> \ - GRSPWROUTER_PCTRL_RD_SHIFT ) -#define GRSPWROUTER_PCTRL_RD_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPWROUTER_PCTRL_RD_MASK ) | \ + ( ( ( _reg ) & GRSPWROUTER_PCTRL_RD_MASK ) >> GRSPWROUTER_PCTRL_RD_SHIFT ) +#define GRSPWROUTER_PCTRL_RD_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_PCTRL_RD_MASK ) | \ ( ( ( _val ) << GRSPWROUTER_PCTRL_RD_SHIFT ) & \ GRSPWROUTER_PCTRL_RD_MASK ) ) #define GRSPWROUTER_PCTRL_RD( _val ) \ - ( ( ( _val ) << GRSPWROUTER_PCTRL_RD_SHIFT ) & \ - GRSPWROUTER_PCTRL_RD_MASK ) + ( ( ( _val ) << GRSPWROUTER_PCTRL_RD_SHIFT ) & GRSPWROUTER_PCTRL_RD_MASK ) #define GRSPWROUTER_PCTRL_RES_SHIFT 22 -#define GRSPWROUTER_PCTRL_RES_MASK 0xc00000U +#define GRSPWROUTER_PCTRL_RES_MASK 0xc00000U #define GRSPWROUTER_PCTRL_RES_GET( _reg ) \ - ( ( ( _reg ) & GRSPWROUTER_PCTRL_RES_MASK ) >> \ - GRSPWROUTER_PCTRL_RES_SHIFT ) -#define GRSPWROUTER_PCTRL_RES_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPWROUTER_PCTRL_RES_MASK ) | \ + ( ( ( _reg ) & GRSPWROUTER_PCTRL_RES_MASK ) >> GRSPWROUTER_PCTRL_RES_SHIFT ) +#define GRSPWROUTER_PCTRL_RES_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_PCTRL_RES_MASK ) | \ ( ( ( _val ) << GRSPWROUTER_PCTRL_RES_SHIFT ) & \ GRSPWROUTER_PCTRL_RES_MASK ) ) #define GRSPWROUTER_PCTRL_RES( _val ) \ - ( ( ( _val ) << GRSPWROUTER_PCTRL_RES_SHIFT ) & \ - GRSPWROUTER_PCTRL_RES_MASK ) + ( ( ( _val ) << GRSPWROUTER_PCTRL_RES_SHIFT ) & GRSPWROUTER_PCTRL_RES_MASK ) #define GRSPWROUTER_PCTRL_ST 0x200000U @@ -385,15 +379,15 @@ typedef struct grspwrouter_portstats { #define GRSPWROUTER_PSTSCFG_CE 0x1000000U #define GRSPWROUTER_PSTSCFG_EC_SHIFT 20 -#define GRSPWROUTER_PSTSCFG_EC_MASK 0xf00000U -#define GRSPWROUTER_PSTSCFG_EC_GET( _reg ) \ +#define GRSPWROUTER_PSTSCFG_EC_MASK 0xf00000U +#define GRSPWROUTER_PSTSCFG_EC_GET( _reg ) \ ( ( ( _reg ) & GRSPWROUTER_PSTSCFG_EC_MASK ) >> \ GRSPWROUTER_PSTSCFG_EC_SHIFT ) -#define GRSPWROUTER_PSTSCFG_EC_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPWROUTER_PSTSCFG_EC_MASK ) | \ +#define GRSPWROUTER_PSTSCFG_EC_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_PSTSCFG_EC_MASK ) | \ ( ( ( _val ) << GRSPWROUTER_PSTSCFG_EC_SHIFT ) & \ GRSPWROUTER_PSTSCFG_EC_MASK ) ) -#define GRSPWROUTER_PSTSCFG_EC( _val ) \ +#define GRSPWROUTER_PSTSCFG_EC( _val ) \ ( ( ( _val ) << GRSPWROUTER_PSTSCFG_EC_SHIFT ) & \ GRSPWROUTER_PSTSCFG_EC_MASK ) @@ -404,43 +398,43 @@ typedef struct grspwrouter_portstats { #define GRSPWROUTER_PSTSCFG_ME 0x20000U #define GRSPWROUTER_PSTSCFG_IP_SHIFT 7 -#define GRSPWROUTER_PSTSCFG_IP_MASK 0xf80U -#define GRSPWROUTER_PSTSCFG_IP_GET( _reg ) \ +#define GRSPWROUTER_PSTSCFG_IP_MASK 0xf80U +#define GRSPWROUTER_PSTSCFG_IP_GET( _reg ) \ ( ( ( _reg ) & GRSPWROUTER_PSTSCFG_IP_MASK ) >> \ GRSPWROUTER_PSTSCFG_IP_SHIFT ) -#define GRSPWROUTER_PSTSCFG_IP_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPWROUTER_PSTSCFG_IP_MASK ) | \ +#define GRSPWROUTER_PSTSCFG_IP_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_PSTSCFG_IP_MASK ) | \ ( ( ( _val ) << GRSPWROUTER_PSTSCFG_IP_SHIFT ) & \ GRSPWROUTER_PSTSCFG_IP_MASK ) ) -#define GRSPWROUTER_PSTSCFG_IP( _val ) \ +#define GRSPWROUTER_PSTSCFG_IP( _val ) \ ( ( ( _val ) << GRSPWROUTER_PSTSCFG_IP_SHIFT ) & \ GRSPWROUTER_PSTSCFG_IP_MASK ) #define GRSPWROUTER_PSTSCFG_RES_SHIFT 5 -#define GRSPWROUTER_PSTSCFG_RES_MASK 0x60U -#define GRSPWROUTER_PSTSCFG_RES_GET( _reg ) \ +#define GRSPWROUTER_PSTSCFG_RES_MASK 0x60U +#define GRSPWROUTER_PSTSCFG_RES_GET( _reg ) \ ( ( ( _reg ) & GRSPWROUTER_PSTSCFG_RES_MASK ) >> \ GRSPWROUTER_PSTSCFG_RES_SHIFT ) -#define GRSPWROUTER_PSTSCFG_RES_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPWROUTER_PSTSCFG_RES_MASK ) | \ +#define GRSPWROUTER_PSTSCFG_RES_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_PSTSCFG_RES_MASK ) | \ ( ( ( _val ) << GRSPWROUTER_PSTSCFG_RES_SHIFT ) & \ GRSPWROUTER_PSTSCFG_RES_MASK ) ) -#define GRSPWROUTER_PSTSCFG_RES( _val ) \ +#define GRSPWROUTER_PSTSCFG_RES( _val ) \ ( ( ( _val ) << GRSPWROUTER_PSTSCFG_RES_SHIFT ) & \ GRSPWROUTER_PSTSCFG_RES_MASK ) #define GRSPWROUTER_PSTSCFG_CP 0x10U #define GRSPWROUTER_PSTSCFG_PC_SHIFT 0 -#define GRSPWROUTER_PSTSCFG_PC_MASK 0xfU -#define GRSPWROUTER_PSTSCFG_PC_GET( _reg ) \ +#define GRSPWROUTER_PSTSCFG_PC_MASK 0xfU +#define GRSPWROUTER_PSTSCFG_PC_GET( _reg ) \ ( ( ( _reg ) & GRSPWROUTER_PSTSCFG_PC_MASK ) >> \ GRSPWROUTER_PSTSCFG_PC_SHIFT ) -#define GRSPWROUTER_PSTSCFG_PC_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPWROUTER_PSTSCFG_PC_MASK ) | \ +#define GRSPWROUTER_PSTSCFG_PC_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_PSTSCFG_PC_MASK ) | \ ( ( ( _val ) << GRSPWROUTER_PSTSCFG_PC_SHIFT ) & \ GRSPWROUTER_PSTSCFG_PC_MASK ) ) -#define GRSPWROUTER_PSTSCFG_PC( _val ) \ +#define GRSPWROUTER_PSTSCFG_PC( _val ) \ ( ( ( _val ) << GRSPWROUTER_PSTSCFG_PC_SHIFT ) & \ GRSPWROUTER_PSTSCFG_PC_MASK ) @@ -455,17 +449,15 @@ typedef struct grspwrouter_portstats { */ #define GRSPWROUTER_PSTS_PT_SHIFT 30 -#define GRSPWROUTER_PSTS_PT_MASK 0xc0000000U +#define GRSPWROUTER_PSTS_PT_MASK 0xc0000000U #define GRSPWROUTER_PSTS_PT_GET( _reg ) \ - ( ( ( _reg ) & GRSPWROUTER_PSTS_PT_MASK ) >> \ - GRSPWROUTER_PSTS_PT_SHIFT ) -#define GRSPWROUTER_PSTS_PT_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPWROUTER_PSTS_PT_MASK ) | \ + ( ( ( _reg ) & GRSPWROUTER_PSTS_PT_MASK ) >> GRSPWROUTER_PSTS_PT_SHIFT ) +#define GRSPWROUTER_PSTS_PT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_PSTS_PT_MASK ) | \ ( ( ( _val ) << GRSPWROUTER_PSTS_PT_SHIFT ) & \ GRSPWROUTER_PSTS_PT_MASK ) ) #define GRSPWROUTER_PSTS_PT( _val ) \ - ( ( ( _val ) << GRSPWROUTER_PSTS_PT_SHIFT ) & \ - GRSPWROUTER_PSTS_PT_MASK ) + ( ( ( _val ) << GRSPWROUTER_PSTS_PT_SHIFT ) & GRSPWROUTER_PSTS_PT_MASK ) #define GRSPWROUTER_PSTS_PL 0x20000000U @@ -492,30 +484,26 @@ typedef struct grspwrouter_portstats { #define GRSPWROUTER_PSTS_RE 0x8000U #define GRSPWROUTER_PSTS_LS_SHIFT 12 -#define GRSPWROUTER_PSTS_LS_MASK 0x7000U +#define GRSPWROUTER_PSTS_LS_MASK 0x7000U #define GRSPWROUTER_PSTS_LS_GET( _reg ) \ - ( ( ( _reg ) & GRSPWROUTER_PSTS_LS_MASK ) >> \ - GRSPWROUTER_PSTS_LS_SHIFT ) -#define GRSPWROUTER_PSTS_LS_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPWROUTER_PSTS_LS_MASK ) | \ + ( ( ( _reg ) & GRSPWROUTER_PSTS_LS_MASK ) >> GRSPWROUTER_PSTS_LS_SHIFT ) +#define GRSPWROUTER_PSTS_LS_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_PSTS_LS_MASK ) | \ ( ( ( _val ) << GRSPWROUTER_PSTS_LS_SHIFT ) & \ GRSPWROUTER_PSTS_LS_MASK ) ) #define GRSPWROUTER_PSTS_LS( _val ) \ - ( ( ( _val ) << GRSPWROUTER_PSTS_LS_SHIFT ) & \ - GRSPWROUTER_PSTS_LS_MASK ) + ( ( ( _val ) << GRSPWROUTER_PSTS_LS_SHIFT ) & GRSPWROUTER_PSTS_LS_MASK ) #define GRSPWROUTER_PSTS_IP_SHIFT 7 -#define GRSPWROUTER_PSTS_IP_MASK 0xf80U +#define GRSPWROUTER_PSTS_IP_MASK 0xf80U #define GRSPWROUTER_PSTS_IP_GET( _reg ) \ - ( ( ( _reg ) & GRSPWROUTER_PSTS_IP_MASK ) >> \ - GRSPWROUTER_PSTS_IP_SHIFT ) -#define GRSPWROUTER_PSTS_IP_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPWROUTER_PSTS_IP_MASK ) | \ + ( ( ( _reg ) & GRSPWROUTER_PSTS_IP_MASK ) >> GRSPWROUTER_PSTS_IP_SHIFT ) +#define GRSPWROUTER_PSTS_IP_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_PSTS_IP_MASK ) | \ ( ( ( _val ) << GRSPWROUTER_PSTS_IP_SHIFT ) & \ GRSPWROUTER_PSTS_IP_MASK ) ) #define GRSPWROUTER_PSTS_IP( _val ) \ - ( ( ( _val ) << GRSPWROUTER_PSTS_IP_SHIFT ) & \ - GRSPWROUTER_PSTS_IP_MASK ) + ( ( ( _val ) << GRSPWROUTER_PSTS_IP_SHIFT ) & GRSPWROUTER_PSTS_IP_MASK ) #define GRSPWROUTER_PSTS_PR 0x40U @@ -542,17 +530,15 @@ typedef struct grspwrouter_portstats { */ #define GRSPWROUTER_PTIMER_RL_SHIFT 0 -#define GRSPWROUTER_PTIMER_RL_MASK 0x3ffU +#define GRSPWROUTER_PTIMER_RL_MASK 0x3ffU #define GRSPWROUTER_PTIMER_RL_GET( _reg ) \ - ( ( ( _reg ) & GRSPWROUTER_PTIMER_RL_MASK ) >> \ - GRSPWROUTER_PTIMER_RL_SHIFT ) -#define GRSPWROUTER_PTIMER_RL_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPWROUTER_PTIMER_RL_MASK ) | \ + ( ( ( _reg ) & GRSPWROUTER_PTIMER_RL_MASK ) >> GRSPWROUTER_PTIMER_RL_SHIFT ) +#define GRSPWROUTER_PTIMER_RL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_PTIMER_RL_MASK ) | \ ( ( ( _val ) << GRSPWROUTER_PTIMER_RL_SHIFT ) & \ GRSPWROUTER_PTIMER_RL_MASK ) ) #define GRSPWROUTER_PTIMER_RL( _val ) \ - ( ( ( _val ) << GRSPWROUTER_PTIMER_RL_SHIFT ) & \ - GRSPWROUTER_PTIMER_RL_MASK ) + ( ( ( _val ) << GRSPWROUTER_PTIMER_RL_SHIFT ) & GRSPWROUTER_PTIMER_RL_MASK ) /** @} */ @@ -566,28 +552,28 @@ typedef struct grspwrouter_portstats { */ #define GRSPWROUTER_PCTRL2CFG_SM_SHIFT 24 -#define GRSPWROUTER_PCTRL2CFG_SM_MASK 0xff000000U -#define GRSPWROUTER_PCTRL2CFG_SM_GET( _reg ) \ +#define GRSPWROUTER_PCTRL2CFG_SM_MASK 0xff000000U +#define GRSPWROUTER_PCTRL2CFG_SM_GET( _reg ) \ ( ( ( _reg ) & GRSPWROUTER_PCTRL2CFG_SM_MASK ) >> \ GRSPWROUTER_PCTRL2CFG_SM_SHIFT ) -#define GRSPWROUTER_PCTRL2CFG_SM_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPWROUTER_PCTRL2CFG_SM_MASK ) | \ +#define GRSPWROUTER_PCTRL2CFG_SM_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_PCTRL2CFG_SM_MASK ) | \ ( ( ( _val ) << GRSPWROUTER_PCTRL2CFG_SM_SHIFT ) & \ GRSPWROUTER_PCTRL2CFG_SM_MASK ) ) -#define GRSPWROUTER_PCTRL2CFG_SM( _val ) \ +#define GRSPWROUTER_PCTRL2CFG_SM( _val ) \ ( ( ( _val ) << GRSPWROUTER_PCTRL2CFG_SM_SHIFT ) & \ GRSPWROUTER_PCTRL2CFG_SM_MASK ) #define GRSPWROUTER_PCTRL2CFG_SV_SHIFT 16 -#define GRSPWROUTER_PCTRL2CFG_SV_MASK 0xff0000U -#define GRSPWROUTER_PCTRL2CFG_SV_GET( _reg ) \ +#define GRSPWROUTER_PCTRL2CFG_SV_MASK 0xff0000U +#define GRSPWROUTER_PCTRL2CFG_SV_GET( _reg ) \ ( ( ( _reg ) & GRSPWROUTER_PCTRL2CFG_SV_MASK ) >> \ GRSPWROUTER_PCTRL2CFG_SV_SHIFT ) -#define GRSPWROUTER_PCTRL2CFG_SV_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPWROUTER_PCTRL2CFG_SV_MASK ) | \ +#define GRSPWROUTER_PCTRL2CFG_SV_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_PCTRL2CFG_SV_MASK ) | \ ( ( ( _val ) << GRSPWROUTER_PCTRL2CFG_SV_SHIFT ) & \ GRSPWROUTER_PCTRL2CFG_SV_MASK ) ) -#define GRSPWROUTER_PCTRL2CFG_SV( _val ) \ +#define GRSPWROUTER_PCTRL2CFG_SV( _val ) \ ( ( ( _val ) << GRSPWROUTER_PCTRL2CFG_SV_SHIFT ) & \ GRSPWROUTER_PCTRL2CFG_SV_MASK ) @@ -604,30 +590,26 @@ typedef struct grspwrouter_portstats { */ #define GRSPWROUTER_PCTRL2_SM_SHIFT 24 -#define GRSPWROUTER_PCTRL2_SM_MASK 0xff000000U +#define GRSPWROUTER_PCTRL2_SM_MASK 0xff000000U #define GRSPWROUTER_PCTRL2_SM_GET( _reg ) \ - ( ( ( _reg ) & GRSPWROUTER_PCTRL2_SM_MASK ) >> \ - GRSPWROUTER_PCTRL2_SM_SHIFT ) -#define GRSPWROUTER_PCTRL2_SM_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPWROUTER_PCTRL2_SM_MASK ) | \ + ( ( ( _reg ) & GRSPWROUTER_PCTRL2_SM_MASK ) >> GRSPWROUTER_PCTRL2_SM_SHIFT ) +#define GRSPWROUTER_PCTRL2_SM_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_PCTRL2_SM_MASK ) | \ ( ( ( _val ) << GRSPWROUTER_PCTRL2_SM_SHIFT ) & \ GRSPWROUTER_PCTRL2_SM_MASK ) ) #define GRSPWROUTER_PCTRL2_SM( _val ) \ - ( ( ( _val ) << GRSPWROUTER_PCTRL2_SM_SHIFT ) & \ - GRSPWROUTER_PCTRL2_SM_MASK ) + ( ( ( _val ) << GRSPWROUTER_PCTRL2_SM_SHIFT ) & GRSPWROUTER_PCTRL2_SM_MASK ) #define GRSPWROUTER_PCTRL2_SV_SHIFT 16 -#define GRSPWROUTER_PCTRL2_SV_MASK 0xff0000U +#define GRSPWROUTER_PCTRL2_SV_MASK 0xff0000U #define GRSPWROUTER_PCTRL2_SV_GET( _reg ) \ - ( ( ( _reg ) & GRSPWROUTER_PCTRL2_SV_MASK ) >> \ - GRSPWROUTER_PCTRL2_SV_SHIFT ) -#define GRSPWROUTER_PCTRL2_SV_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPWROUTER_PCTRL2_SV_MASK ) | \ + ( ( ( _reg ) & GRSPWROUTER_PCTRL2_SV_MASK ) >> GRSPWROUTER_PCTRL2_SV_SHIFT ) +#define GRSPWROUTER_PCTRL2_SV_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_PCTRL2_SV_MASK ) | \ ( ( ( _val ) << GRSPWROUTER_PCTRL2_SV_SHIFT ) & \ GRSPWROUTER_PCTRL2_SV_MASK ) ) #define GRSPWROUTER_PCTRL2_SV( _val ) \ - ( ( ( _val ) << GRSPWROUTER_PCTRL2_SV_SHIFT ) & \ - GRSPWROUTER_PCTRL2_SV_MASK ) + ( ( ( _val ) << GRSPWROUTER_PCTRL2_SV_SHIFT ) & GRSPWROUTER_PCTRL2_SV_MASK ) #define GRSPWROUTER_PCTRL2_OR 0x8000U @@ -644,17 +626,15 @@ typedef struct grspwrouter_portstats { #define GRSPWROUTER_PCTRL2_IR 0x200U #define GRSPWROUTER_PCTRL2_SD_SHIFT 1 -#define GRSPWROUTER_PCTRL2_SD_MASK 0x3eU +#define GRSPWROUTER_PCTRL2_SD_MASK 0x3eU #define GRSPWROUTER_PCTRL2_SD_GET( _reg ) \ - ( ( ( _reg ) & GRSPWROUTER_PCTRL2_SD_MASK ) >> \ - GRSPWROUTER_PCTRL2_SD_SHIFT ) -#define GRSPWROUTER_PCTRL2_SD_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPWROUTER_PCTRL2_SD_MASK ) | \ + ( ( ( _reg ) & GRSPWROUTER_PCTRL2_SD_MASK ) >> GRSPWROUTER_PCTRL2_SD_SHIFT ) +#define GRSPWROUTER_PCTRL2_SD_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_PCTRL2_SD_MASK ) | \ ( ( ( _val ) << GRSPWROUTER_PCTRL2_SD_SHIFT ) & \ GRSPWROUTER_PCTRL2_SD_MASK ) ) #define GRSPWROUTER_PCTRL2_SD( _val ) \ - ( ( ( _val ) << GRSPWROUTER_PCTRL2_SD_SHIFT ) & \ - GRSPWROUTER_PCTRL2_SD_MASK ) + ( ( ( _val ) << GRSPWROUTER_PCTRL2_SD_SHIFT ) & GRSPWROUTER_PCTRL2_SD_MASK ) #define GRSPWROUTER_PCTRL2_SC 0x1U @@ -670,43 +650,37 @@ typedef struct grspwrouter_portstats { */ #define GRSPWROUTER_RTRCFG_SP_SHIFT 27 -#define GRSPWROUTER_RTRCFG_SP_MASK 0xf8000000U +#define GRSPWROUTER_RTRCFG_SP_MASK 0xf8000000U #define GRSPWROUTER_RTRCFG_SP_GET( _reg ) \ - ( ( ( _reg ) & GRSPWROUTER_RTRCFG_SP_MASK ) >> \ - GRSPWROUTER_RTRCFG_SP_SHIFT ) -#define GRSPWROUTER_RTRCFG_SP_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPWROUTER_RTRCFG_SP_MASK ) | \ + ( ( ( _reg ) & GRSPWROUTER_RTRCFG_SP_MASK ) >> GRSPWROUTER_RTRCFG_SP_SHIFT ) +#define GRSPWROUTER_RTRCFG_SP_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_RTRCFG_SP_MASK ) | \ ( ( ( _val ) << GRSPWROUTER_RTRCFG_SP_SHIFT ) & \ GRSPWROUTER_RTRCFG_SP_MASK ) ) #define GRSPWROUTER_RTRCFG_SP( _val ) \ - ( ( ( _val ) << GRSPWROUTER_RTRCFG_SP_SHIFT ) & \ - GRSPWROUTER_RTRCFG_SP_MASK ) + ( ( ( _val ) << GRSPWROUTER_RTRCFG_SP_SHIFT ) & GRSPWROUTER_RTRCFG_SP_MASK ) #define GRSPWROUTER_RTRCFG_AP_SHIFT 22 -#define GRSPWROUTER_RTRCFG_AP_MASK 0x7c00000U +#define GRSPWROUTER_RTRCFG_AP_MASK 0x7c00000U #define GRSPWROUTER_RTRCFG_AP_GET( _reg ) \ - ( ( ( _reg ) & GRSPWROUTER_RTRCFG_AP_MASK ) >> \ - GRSPWROUTER_RTRCFG_AP_SHIFT ) -#define GRSPWROUTER_RTRCFG_AP_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPWROUTER_RTRCFG_AP_MASK ) | \ + ( ( ( _reg ) & GRSPWROUTER_RTRCFG_AP_MASK ) >> GRSPWROUTER_RTRCFG_AP_SHIFT ) +#define GRSPWROUTER_RTRCFG_AP_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_RTRCFG_AP_MASK ) | \ ( ( ( _val ) << GRSPWROUTER_RTRCFG_AP_SHIFT ) & \ GRSPWROUTER_RTRCFG_AP_MASK ) ) #define GRSPWROUTER_RTRCFG_AP( _val ) \ - ( ( ( _val ) << GRSPWROUTER_RTRCFG_AP_SHIFT ) & \ - GRSPWROUTER_RTRCFG_AP_MASK ) + ( ( ( _val ) << GRSPWROUTER_RTRCFG_AP_SHIFT ) & GRSPWROUTER_RTRCFG_AP_MASK ) #define GRSPWROUTER_RTRCFG_FP_SHIFT 17 -#define GRSPWROUTER_RTRCFG_FP_MASK 0x3e0000U +#define GRSPWROUTER_RTRCFG_FP_MASK 0x3e0000U #define GRSPWROUTER_RTRCFG_FP_GET( _reg ) \ - ( ( ( _reg ) & GRSPWROUTER_RTRCFG_FP_MASK ) >> \ - GRSPWROUTER_RTRCFG_FP_SHIFT ) -#define GRSPWROUTER_RTRCFG_FP_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPWROUTER_RTRCFG_FP_MASK ) | \ + ( ( ( _reg ) & GRSPWROUTER_RTRCFG_FP_MASK ) >> GRSPWROUTER_RTRCFG_FP_SHIFT ) +#define GRSPWROUTER_RTRCFG_FP_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_RTRCFG_FP_MASK ) | \ ( ( ( _val ) << GRSPWROUTER_RTRCFG_FP_SHIFT ) & \ GRSPWROUTER_RTRCFG_FP_MASK ) ) #define GRSPWROUTER_RTRCFG_FP( _val ) \ - ( ( ( _val ) << GRSPWROUTER_RTRCFG_FP_SHIFT ) & \ - GRSPWROUTER_RTRCFG_FP_MASK ) + ( ( ( _val ) << GRSPWROUTER_RTRCFG_FP_SHIFT ) & GRSPWROUTER_RTRCFG_FP_MASK ) #define GRSPWROUTER_RTRCFG_R 0x10000U @@ -757,30 +731,24 @@ typedef struct grspwrouter_portstats { #define GRSPWROUTER_TC_EN 0x100U #define GRSPWROUTER_TC_CF_SHIFT 6 -#define GRSPWROUTER_TC_CF_MASK 0xc0U +#define GRSPWROUTER_TC_CF_MASK 0xc0U #define GRSPWROUTER_TC_CF_GET( _reg ) \ - ( ( ( _reg ) & GRSPWROUTER_TC_CF_MASK ) >> \ - GRSPWROUTER_TC_CF_SHIFT ) -#define GRSPWROUTER_TC_CF_SET( _reg, _val ) \ + ( ( ( _reg ) & GRSPWROUTER_TC_CF_MASK ) >> GRSPWROUTER_TC_CF_SHIFT ) +#define GRSPWROUTER_TC_CF_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRSPWROUTER_TC_CF_MASK ) | \ - ( ( ( _val ) << GRSPWROUTER_TC_CF_SHIFT ) & \ - GRSPWROUTER_TC_CF_MASK ) ) + ( ( ( _val ) << GRSPWROUTER_TC_CF_SHIFT ) & GRSPWROUTER_TC_CF_MASK ) ) #define GRSPWROUTER_TC_CF( _val ) \ - ( ( ( _val ) << GRSPWROUTER_TC_CF_SHIFT ) & \ - GRSPWROUTER_TC_CF_MASK ) + ( ( ( _val ) << GRSPWROUTER_TC_CF_SHIFT ) & GRSPWROUTER_TC_CF_MASK ) #define GRSPWROUTER_TC_TC_SHIFT 0 -#define GRSPWROUTER_TC_TC_MASK 0x3fU +#define GRSPWROUTER_TC_TC_MASK 0x3fU #define GRSPWROUTER_TC_TC_GET( _reg ) \ - ( ( ( _reg ) & GRSPWROUTER_TC_TC_MASK ) >> \ - GRSPWROUTER_TC_TC_SHIFT ) -#define GRSPWROUTER_TC_TC_SET( _reg, _val ) \ + ( ( ( _reg ) & GRSPWROUTER_TC_TC_MASK ) >> GRSPWROUTER_TC_TC_SHIFT ) +#define GRSPWROUTER_TC_TC_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRSPWROUTER_TC_TC_MASK ) | \ - ( ( ( _val ) << GRSPWROUTER_TC_TC_SHIFT ) & \ - GRSPWROUTER_TC_TC_MASK ) ) + ( ( ( _val ) << GRSPWROUTER_TC_TC_SHIFT ) & GRSPWROUTER_TC_TC_MASK ) ) #define GRSPWROUTER_TC_TC( _val ) \ - ( ( ( _val ) << GRSPWROUTER_TC_TC_SHIFT ) & \ - GRSPWROUTER_TC_TC_MASK ) + ( ( ( _val ) << GRSPWROUTER_TC_TC_SHIFT ) & GRSPWROUTER_TC_TC_MASK ) /** @} */ @@ -793,56 +761,44 @@ typedef struct grspwrouter_portstats { */ #define GRSPWROUTER_VER_MA_SHIFT 24 -#define GRSPWROUTER_VER_MA_MASK 0xff000000U +#define GRSPWROUTER_VER_MA_MASK 0xff000000U #define GRSPWROUTER_VER_MA_GET( _reg ) \ - ( ( ( _reg ) & GRSPWROUTER_VER_MA_MASK ) >> \ - GRSPWROUTER_VER_MA_SHIFT ) -#define GRSPWROUTER_VER_MA_SET( _reg, _val ) \ + ( ( ( _reg ) & GRSPWROUTER_VER_MA_MASK ) >> GRSPWROUTER_VER_MA_SHIFT ) +#define GRSPWROUTER_VER_MA_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRSPWROUTER_VER_MA_MASK ) | \ - ( ( ( _val ) << GRSPWROUTER_VER_MA_SHIFT ) & \ - GRSPWROUTER_VER_MA_MASK ) ) + ( ( ( _val ) << GRSPWROUTER_VER_MA_SHIFT ) & GRSPWROUTER_VER_MA_MASK ) ) #define GRSPWROUTER_VER_MA( _val ) \ - ( ( ( _val ) << GRSPWROUTER_VER_MA_SHIFT ) & \ - GRSPWROUTER_VER_MA_MASK ) + ( ( ( _val ) << GRSPWROUTER_VER_MA_SHIFT ) & GRSPWROUTER_VER_MA_MASK ) #define GRSPWROUTER_VER_MI_SHIFT 16 -#define GRSPWROUTER_VER_MI_MASK 0xff0000U +#define GRSPWROUTER_VER_MI_MASK 0xff0000U #define GRSPWROUTER_VER_MI_GET( _reg ) \ - ( ( ( _reg ) & GRSPWROUTER_VER_MI_MASK ) >> \ - GRSPWROUTER_VER_MI_SHIFT ) -#define GRSPWROUTER_VER_MI_SET( _reg, _val ) \ + ( ( ( _reg ) & GRSPWROUTER_VER_MI_MASK ) >> GRSPWROUTER_VER_MI_SHIFT ) +#define GRSPWROUTER_VER_MI_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRSPWROUTER_VER_MI_MASK ) | \ - ( ( ( _val ) << GRSPWROUTER_VER_MI_SHIFT ) & \ - GRSPWROUTER_VER_MI_MASK ) ) + ( ( ( _val ) << GRSPWROUTER_VER_MI_SHIFT ) & GRSPWROUTER_VER_MI_MASK ) ) #define GRSPWROUTER_VER_MI( _val ) \ - ( ( ( _val ) << GRSPWROUTER_VER_MI_SHIFT ) & \ - GRSPWROUTER_VER_MI_MASK ) + ( ( ( _val ) << GRSPWROUTER_VER_MI_SHIFT ) & GRSPWROUTER_VER_MI_MASK ) #define GRSPWROUTER_VER_PA_SHIFT 8 -#define GRSPWROUTER_VER_PA_MASK 0xff00U +#define GRSPWROUTER_VER_PA_MASK 0xff00U #define GRSPWROUTER_VER_PA_GET( _reg ) \ - ( ( ( _reg ) & GRSPWROUTER_VER_PA_MASK ) >> \ - GRSPWROUTER_VER_PA_SHIFT ) -#define GRSPWROUTER_VER_PA_SET( _reg, _val ) \ + ( ( ( _reg ) & GRSPWROUTER_VER_PA_MASK ) >> GRSPWROUTER_VER_PA_SHIFT ) +#define GRSPWROUTER_VER_PA_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRSPWROUTER_VER_PA_MASK ) | \ - ( ( ( _val ) << GRSPWROUTER_VER_PA_SHIFT ) & \ - GRSPWROUTER_VER_PA_MASK ) ) + ( ( ( _val ) << GRSPWROUTER_VER_PA_SHIFT ) & GRSPWROUTER_VER_PA_MASK ) ) #define GRSPWROUTER_VER_PA( _val ) \ - ( ( ( _val ) << GRSPWROUTER_VER_PA_SHIFT ) & \ - GRSPWROUTER_VER_PA_MASK ) + ( ( ( _val ) << GRSPWROUTER_VER_PA_SHIFT ) & GRSPWROUTER_VER_PA_MASK ) #define GRSPWROUTER_VER_ID_SHIFT 0 -#define GRSPWROUTER_VER_ID_MASK 0xffU +#define GRSPWROUTER_VER_ID_MASK 0xffU #define GRSPWROUTER_VER_ID_GET( _reg ) \ - ( ( ( _reg ) & GRSPWROUTER_VER_ID_MASK ) >> \ - GRSPWROUTER_VER_ID_SHIFT ) -#define GRSPWROUTER_VER_ID_SET( _reg, _val ) \ + ( ( ( _reg ) & GRSPWROUTER_VER_ID_MASK ) >> GRSPWROUTER_VER_ID_SHIFT ) +#define GRSPWROUTER_VER_ID_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRSPWROUTER_VER_ID_MASK ) | \ - ( ( ( _val ) << GRSPWROUTER_VER_ID_SHIFT ) & \ - GRSPWROUTER_VER_ID_MASK ) ) + ( ( ( _val ) << GRSPWROUTER_VER_ID_SHIFT ) & GRSPWROUTER_VER_ID_MASK ) ) #define GRSPWROUTER_VER_ID( _val ) \ - ( ( ( _val ) << GRSPWROUTER_VER_ID_SHIFT ) & \ - GRSPWROUTER_VER_ID_MASK ) + ( ( ( _val ) << GRSPWROUTER_VER_ID_SHIFT ) & GRSPWROUTER_VER_ID_MASK ) /** @} */ @@ -855,17 +811,15 @@ typedef struct grspwrouter_portstats { */ #define GRSPWROUTER_IDIV_ID_SHIFT 0 -#define GRSPWROUTER_IDIV_ID_MASK 0xffU +#define GRSPWROUTER_IDIV_ID_MASK 0xffU #define GRSPWROUTER_IDIV_ID_GET( _reg ) \ - ( ( ( _reg ) & GRSPWROUTER_IDIV_ID_MASK ) >> \ - GRSPWROUTER_IDIV_ID_SHIFT ) -#define GRSPWROUTER_IDIV_ID_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPWROUTER_IDIV_ID_MASK ) | \ + ( ( ( _reg ) & GRSPWROUTER_IDIV_ID_MASK ) >> GRSPWROUTER_IDIV_ID_SHIFT ) +#define GRSPWROUTER_IDIV_ID_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_IDIV_ID_MASK ) | \ ( ( ( _val ) << GRSPWROUTER_IDIV_ID_SHIFT ) & \ GRSPWROUTER_IDIV_ID_MASK ) ) #define GRSPWROUTER_IDIV_ID( _val ) \ - ( ( ( _val ) << GRSPWROUTER_IDIV_ID_SHIFT ) & \ - GRSPWROUTER_IDIV_ID_MASK ) + ( ( ( _val ) << GRSPWROUTER_IDIV_ID_SHIFT ) & GRSPWROUTER_IDIV_ID_MASK ) /** @} */ @@ -891,15 +845,15 @@ typedef struct grspwrouter_portstats { */ #define GRSPWROUTER_PRESCALER_RL_SHIFT 0 -#define GRSPWROUTER_PRESCALER_RL_MASK 0xffffffffU -#define GRSPWROUTER_PRESCALER_RL_GET( _reg ) \ +#define GRSPWROUTER_PRESCALER_RL_MASK 0xffffffffU +#define GRSPWROUTER_PRESCALER_RL_GET( _reg ) \ ( ( ( _reg ) & GRSPWROUTER_PRESCALER_RL_MASK ) >> \ GRSPWROUTER_PRESCALER_RL_SHIFT ) -#define GRSPWROUTER_PRESCALER_RL_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPWROUTER_PRESCALER_RL_MASK ) | \ +#define GRSPWROUTER_PRESCALER_RL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_PRESCALER_RL_MASK ) | \ ( ( ( _val ) << GRSPWROUTER_PRESCALER_RL_SHIFT ) & \ GRSPWROUTER_PRESCALER_RL_MASK ) ) -#define GRSPWROUTER_PRESCALER_RL( _val ) \ +#define GRSPWROUTER_PRESCALER_RL( _val ) \ ( ( ( _val ) << GRSPWROUTER_PRESCALER_RL_SHIFT ) & \ GRSPWROUTER_PRESCALER_RL_MASK ) @@ -946,17 +900,15 @@ typedef struct grspwrouter_portstats { */ #define GRSPWROUTER_IPMASK_IE_SHIFT 0 -#define GRSPWROUTER_IPMASK_IE_MASK 0xffffffffU +#define GRSPWROUTER_IPMASK_IE_MASK 0xffffffffU #define GRSPWROUTER_IPMASK_IE_GET( _reg ) \ - ( ( ( _reg ) & GRSPWROUTER_IPMASK_IE_MASK ) >> \ - GRSPWROUTER_IPMASK_IE_SHIFT ) -#define GRSPWROUTER_IPMASK_IE_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPWROUTER_IPMASK_IE_MASK ) | \ + ( ( ( _reg ) & GRSPWROUTER_IPMASK_IE_MASK ) >> GRSPWROUTER_IPMASK_IE_SHIFT ) +#define GRSPWROUTER_IPMASK_IE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_IPMASK_IE_MASK ) | \ ( ( ( _val ) << GRSPWROUTER_IPMASK_IE_SHIFT ) & \ GRSPWROUTER_IPMASK_IE_MASK ) ) #define GRSPWROUTER_IPMASK_IE( _val ) \ - ( ( ( _val ) << GRSPWROUTER_IPMASK_IE_SHIFT ) & \ - GRSPWROUTER_IPMASK_IE_MASK ) + ( ( ( _val ) << GRSPWROUTER_IPMASK_IE_SHIFT ) & GRSPWROUTER_IPMASK_IE_MASK ) /** @} */ @@ -969,17 +921,14 @@ typedef struct grspwrouter_portstats { */ #define GRSPWROUTER_PIP_IP_SHIFT 0 -#define GRSPWROUTER_PIP_IP_MASK 0xffffffffU +#define GRSPWROUTER_PIP_IP_MASK 0xffffffffU #define GRSPWROUTER_PIP_IP_GET( _reg ) \ - ( ( ( _reg ) & GRSPWROUTER_PIP_IP_MASK ) >> \ - GRSPWROUTER_PIP_IP_SHIFT ) -#define GRSPWROUTER_PIP_IP_SET( _reg, _val ) \ + ( ( ( _reg ) & GRSPWROUTER_PIP_IP_MASK ) >> GRSPWROUTER_PIP_IP_SHIFT ) +#define GRSPWROUTER_PIP_IP_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRSPWROUTER_PIP_IP_MASK ) | \ - ( ( ( _val ) << GRSPWROUTER_PIP_IP_SHIFT ) & \ - GRSPWROUTER_PIP_IP_MASK ) ) + ( ( ( _val ) << GRSPWROUTER_PIP_IP_SHIFT ) & GRSPWROUTER_PIP_IP_MASK ) ) #define GRSPWROUTER_PIP_IP( _val ) \ - ( ( ( _val ) << GRSPWROUTER_PIP_IP_SHIFT ) & \ - GRSPWROUTER_PIP_IP_MASK ) + ( ( ( _val ) << GRSPWROUTER_PIP_IP_SHIFT ) & GRSPWROUTER_PIP_IP_MASK ) /** @} */ @@ -1005,15 +954,15 @@ typedef struct grspwrouter_portstats { #define GRSPWROUTER_ICODEGEN_EN 0x20000U #define GRSPWROUTER_ICODEGEN_IN_SHIFT 6 -#define GRSPWROUTER_ICODEGEN_IN_MASK 0xffc0U -#define GRSPWROUTER_ICODEGEN_IN_GET( _reg ) \ +#define GRSPWROUTER_ICODEGEN_IN_MASK 0xffc0U +#define GRSPWROUTER_ICODEGEN_IN_GET( _reg ) \ ( ( ( _reg ) & GRSPWROUTER_ICODEGEN_IN_MASK ) >> \ GRSPWROUTER_ICODEGEN_IN_SHIFT ) -#define GRSPWROUTER_ICODEGEN_IN_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPWROUTER_ICODEGEN_IN_MASK ) | \ +#define GRSPWROUTER_ICODEGEN_IN_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_ICODEGEN_IN_MASK ) | \ ( ( ( _val ) << GRSPWROUTER_ICODEGEN_IN_SHIFT ) & \ GRSPWROUTER_ICODEGEN_IN_MASK ) ) -#define GRSPWROUTER_ICODEGEN_IN( _val ) \ +#define GRSPWROUTER_ICODEGEN_IN( _val ) \ ( ( ( _val ) << GRSPWROUTER_ICODEGEN_IN_SHIFT ) & \ GRSPWROUTER_ICODEGEN_IN_MASK ) @@ -1029,17 +978,15 @@ typedef struct grspwrouter_portstats { */ #define GRSPWROUTER_ISR0_IB_SHIFT 0 -#define GRSPWROUTER_ISR0_IB_MASK 0xffffffffU +#define GRSPWROUTER_ISR0_IB_MASK 0xffffffffU #define GRSPWROUTER_ISR0_IB_GET( _reg ) \ - ( ( ( _reg ) & GRSPWROUTER_ISR0_IB_MASK ) >> \ - GRSPWROUTER_ISR0_IB_SHIFT ) -#define GRSPWROUTER_ISR0_IB_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPWROUTER_ISR0_IB_MASK ) | \ + ( ( ( _reg ) & GRSPWROUTER_ISR0_IB_MASK ) >> GRSPWROUTER_ISR0_IB_SHIFT ) +#define GRSPWROUTER_ISR0_IB_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_ISR0_IB_MASK ) | \ ( ( ( _val ) << GRSPWROUTER_ISR0_IB_SHIFT ) & \ GRSPWROUTER_ISR0_IB_MASK ) ) #define GRSPWROUTER_ISR0_IB( _val ) \ - ( ( ( _val ) << GRSPWROUTER_ISR0_IB_SHIFT ) & \ - GRSPWROUTER_ISR0_IB_MASK ) + ( ( ( _val ) << GRSPWROUTER_ISR0_IB_SHIFT ) & GRSPWROUTER_ISR0_IB_MASK ) /** @} */ @@ -1053,17 +1000,15 @@ typedef struct grspwrouter_portstats { */ #define GRSPWROUTER_ISR1_IB_SHIFT 0 -#define GRSPWROUTER_ISR1_IB_MASK 0xffffffffU +#define GRSPWROUTER_ISR1_IB_MASK 0xffffffffU #define GRSPWROUTER_ISR1_IB_GET( _reg ) \ - ( ( ( _reg ) & GRSPWROUTER_ISR1_IB_MASK ) >> \ - GRSPWROUTER_ISR1_IB_SHIFT ) -#define GRSPWROUTER_ISR1_IB_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPWROUTER_ISR1_IB_MASK ) | \ + ( ( ( _reg ) & GRSPWROUTER_ISR1_IB_MASK ) >> GRSPWROUTER_ISR1_IB_SHIFT ) +#define GRSPWROUTER_ISR1_IB_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_ISR1_IB_MASK ) | \ ( ( ( _val ) << GRSPWROUTER_ISR1_IB_SHIFT ) & \ GRSPWROUTER_ISR1_IB_MASK ) ) #define GRSPWROUTER_ISR1_IB( _val ) \ - ( ( ( _val ) << GRSPWROUTER_ISR1_IB_SHIFT ) & \ - GRSPWROUTER_ISR1_IB_MASK ) + ( ( ( _val ) << GRSPWROUTER_ISR1_IB_SHIFT ) & GRSPWROUTER_ISR1_IB_MASK ) /** @} */ @@ -1077,15 +1022,15 @@ typedef struct grspwrouter_portstats { */ #define GRSPWROUTER_ISRTIMER_RL_SHIFT 0 -#define GRSPWROUTER_ISRTIMER_RL_MASK 0xffffffffU -#define GRSPWROUTER_ISRTIMER_RL_GET( _reg ) \ +#define GRSPWROUTER_ISRTIMER_RL_MASK 0xffffffffU +#define GRSPWROUTER_ISRTIMER_RL_GET( _reg ) \ ( ( ( _reg ) & GRSPWROUTER_ISRTIMER_RL_MASK ) >> \ GRSPWROUTER_ISRTIMER_RL_SHIFT ) -#define GRSPWROUTER_ISRTIMER_RL_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPWROUTER_ISRTIMER_RL_MASK ) | \ +#define GRSPWROUTER_ISRTIMER_RL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_ISRTIMER_RL_MASK ) | \ ( ( ( _val ) << GRSPWROUTER_ISRTIMER_RL_SHIFT ) & \ GRSPWROUTER_ISRTIMER_RL_MASK ) ) -#define GRSPWROUTER_ISRTIMER_RL( _val ) \ +#define GRSPWROUTER_ISRTIMER_RL( _val ) \ ( ( ( _val ) << GRSPWROUTER_ISRTIMER_RL_SHIFT ) & \ GRSPWROUTER_ISRTIMER_RL_MASK ) @@ -1101,15 +1046,15 @@ typedef struct grspwrouter_portstats { */ #define GRSPWROUTER_AITIMER_RL_SHIFT 0 -#define GRSPWROUTER_AITIMER_RL_MASK 0xffffffffU -#define GRSPWROUTER_AITIMER_RL_GET( _reg ) \ +#define GRSPWROUTER_AITIMER_RL_MASK 0xffffffffU +#define GRSPWROUTER_AITIMER_RL_GET( _reg ) \ ( ( ( _reg ) & GRSPWROUTER_AITIMER_RL_MASK ) >> \ GRSPWROUTER_AITIMER_RL_SHIFT ) -#define GRSPWROUTER_AITIMER_RL_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPWROUTER_AITIMER_RL_MASK ) | \ +#define GRSPWROUTER_AITIMER_RL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_AITIMER_RL_MASK ) | \ ( ( ( _val ) << GRSPWROUTER_AITIMER_RL_SHIFT ) & \ GRSPWROUTER_AITIMER_RL_MASK ) ) -#define GRSPWROUTER_AITIMER_RL( _val ) \ +#define GRSPWROUTER_AITIMER_RL( _val ) \ ( ( ( _val ) << GRSPWROUTER_AITIMER_RL_SHIFT ) & \ GRSPWROUTER_AITIMER_RL_MASK ) @@ -1125,15 +1070,15 @@ typedef struct grspwrouter_portstats { */ #define GRSPWROUTER_ISRCTIMER_RL_SHIFT 0 -#define GRSPWROUTER_ISRCTIMER_RL_MASK 0x1fU -#define GRSPWROUTER_ISRCTIMER_RL_GET( _reg ) \ +#define GRSPWROUTER_ISRCTIMER_RL_MASK 0x1fU +#define GRSPWROUTER_ISRCTIMER_RL_GET( _reg ) \ ( ( ( _reg ) & GRSPWROUTER_ISRCTIMER_RL_MASK ) >> \ GRSPWROUTER_ISRCTIMER_RL_SHIFT ) -#define GRSPWROUTER_ISRCTIMER_RL_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPWROUTER_ISRCTIMER_RL_MASK ) | \ +#define GRSPWROUTER_ISRCTIMER_RL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_ISRCTIMER_RL_MASK ) | \ ( ( ( _val ) << GRSPWROUTER_ISRCTIMER_RL_SHIFT ) & \ GRSPWROUTER_ISRCTIMER_RL_MASK ) ) -#define GRSPWROUTER_ISRCTIMER_RL( _val ) \ +#define GRSPWROUTER_ISRCTIMER_RL( _val ) \ ( ( ( _val ) << GRSPWROUTER_ISRCTIMER_RL_SHIFT ) & \ GRSPWROUTER_ISRCTIMER_RL_MASK ) @@ -1148,15 +1093,15 @@ typedef struct grspwrouter_portstats { */ #define GRSPWROUTER_LRUNSTAT_LR_SHIFT 1 -#define GRSPWROUTER_LRUNSTAT_LR_MASK 0xfffffffeU -#define GRSPWROUTER_LRUNSTAT_LR_GET( _reg ) \ +#define GRSPWROUTER_LRUNSTAT_LR_MASK 0xfffffffeU +#define GRSPWROUTER_LRUNSTAT_LR_GET( _reg ) \ ( ( ( _reg ) & GRSPWROUTER_LRUNSTAT_LR_MASK ) >> \ GRSPWROUTER_LRUNSTAT_LR_SHIFT ) -#define GRSPWROUTER_LRUNSTAT_LR_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPWROUTER_LRUNSTAT_LR_MASK ) | \ +#define GRSPWROUTER_LRUNSTAT_LR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_LRUNSTAT_LR_MASK ) | \ ( ( ( _val ) << GRSPWROUTER_LRUNSTAT_LR_SHIFT ) & \ GRSPWROUTER_LRUNSTAT_LR_MASK ) ) -#define GRSPWROUTER_LRUNSTAT_LR( _val ) \ +#define GRSPWROUTER_LRUNSTAT_LR( _val ) \ ( ( ( _val ) << GRSPWROUTER_LRUNSTAT_LR_SHIFT ) & \ GRSPWROUTER_LRUNSTAT_LR_MASK ) @@ -1173,47 +1118,38 @@ typedef struct grspwrouter_portstats { */ #define GRSPWROUTER_CAP_AF_SHIFT 24 -#define GRSPWROUTER_CAP_AF_MASK 0x3000000U +#define GRSPWROUTER_CAP_AF_MASK 0x3000000U #define GRSPWROUTER_CAP_AF_GET( _reg ) \ - ( ( ( _reg ) & GRSPWROUTER_CAP_AF_MASK ) >> \ - GRSPWROUTER_CAP_AF_SHIFT ) -#define GRSPWROUTER_CAP_AF_SET( _reg, _val ) \ + ( ( ( _reg ) & GRSPWROUTER_CAP_AF_MASK ) >> GRSPWROUTER_CAP_AF_SHIFT ) +#define GRSPWROUTER_CAP_AF_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRSPWROUTER_CAP_AF_MASK ) | \ - ( ( ( _val ) << GRSPWROUTER_CAP_AF_SHIFT ) & \ - GRSPWROUTER_CAP_AF_MASK ) ) + ( ( ( _val ) << GRSPWROUTER_CAP_AF_SHIFT ) & GRSPWROUTER_CAP_AF_MASK ) ) #define GRSPWROUTER_CAP_AF( _val ) \ - ( ( ( _val ) << GRSPWROUTER_CAP_AF_SHIFT ) & \ - GRSPWROUTER_CAP_AF_MASK ) + ( ( ( _val ) << GRSPWROUTER_CAP_AF_SHIFT ) & GRSPWROUTER_CAP_AF_MASK ) #define GRSPWROUTER_CAP_R 0x800000U #define GRSPWROUTER_CAP_PF_SHIFT 20 -#define GRSPWROUTER_CAP_PF_MASK 0x700000U +#define GRSPWROUTER_CAP_PF_MASK 0x700000U #define GRSPWROUTER_CAP_PF_GET( _reg ) \ - ( ( ( _reg ) & GRSPWROUTER_CAP_PF_MASK ) >> \ - GRSPWROUTER_CAP_PF_SHIFT ) -#define GRSPWROUTER_CAP_PF_SET( _reg, _val ) \ + ( ( ( _reg ) & GRSPWROUTER_CAP_PF_MASK ) >> GRSPWROUTER_CAP_PF_SHIFT ) +#define GRSPWROUTER_CAP_PF_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRSPWROUTER_CAP_PF_MASK ) | \ - ( ( ( _val ) << GRSPWROUTER_CAP_PF_SHIFT ) & \ - GRSPWROUTER_CAP_PF_MASK ) ) + ( ( ( _val ) << GRSPWROUTER_CAP_PF_SHIFT ) & GRSPWROUTER_CAP_PF_MASK ) ) #define GRSPWROUTER_CAP_PF( _val ) \ - ( ( ( _val ) << GRSPWROUTER_CAP_PF_SHIFT ) & \ - GRSPWROUTER_CAP_PF_MASK ) + ( ( ( _val ) << GRSPWROUTER_CAP_PF_SHIFT ) & GRSPWROUTER_CAP_PF_MASK ) #define GRSPWROUTER_CAP_R 0x80000U #define GRSPWROUTER_CAP_RM_SHIFT 16 -#define GRSPWROUTER_CAP_RM_MASK 0x70000U +#define GRSPWROUTER_CAP_RM_MASK 0x70000U #define GRSPWROUTER_CAP_RM_GET( _reg ) \ - ( ( ( _reg ) & GRSPWROUTER_CAP_RM_MASK ) >> \ - GRSPWROUTER_CAP_RM_SHIFT ) -#define GRSPWROUTER_CAP_RM_SET( _reg, _val ) \ + ( ( ( _reg ) & GRSPWROUTER_CAP_RM_MASK ) >> GRSPWROUTER_CAP_RM_SHIFT ) +#define GRSPWROUTER_CAP_RM_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRSPWROUTER_CAP_RM_MASK ) | \ - ( ( ( _val ) << GRSPWROUTER_CAP_RM_SHIFT ) & \ - GRSPWROUTER_CAP_RM_MASK ) ) + ( ( ( _val ) << GRSPWROUTER_CAP_RM_SHIFT ) & GRSPWROUTER_CAP_RM_MASK ) ) #define GRSPWROUTER_CAP_RM( _val ) \ - ( ( ( _val ) << GRSPWROUTER_CAP_RM_SHIFT ) & \ - GRSPWROUTER_CAP_RM_MASK ) + ( ( ( _val ) << GRSPWROUTER_CAP_RM_SHIFT ) & GRSPWROUTER_CAP_RM_MASK ) #define GRSPWROUTER_CAP_R 0x8000U @@ -1228,30 +1164,24 @@ typedef struct grspwrouter_portstats { #define GRSPWROUTER_CAP_SD 0x400U #define GRSPWROUTER_CAP_PC_SHIFT 5 -#define GRSPWROUTER_CAP_PC_MASK 0x3e0U +#define GRSPWROUTER_CAP_PC_MASK 0x3e0U #define GRSPWROUTER_CAP_PC_GET( _reg ) \ - ( ( ( _reg ) & GRSPWROUTER_CAP_PC_MASK ) >> \ - GRSPWROUTER_CAP_PC_SHIFT ) -#define GRSPWROUTER_CAP_PC_SET( _reg, _val ) \ + ( ( ( _reg ) & GRSPWROUTER_CAP_PC_MASK ) >> GRSPWROUTER_CAP_PC_SHIFT ) +#define GRSPWROUTER_CAP_PC_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRSPWROUTER_CAP_PC_MASK ) | \ - ( ( ( _val ) << GRSPWROUTER_CAP_PC_SHIFT ) & \ - GRSPWROUTER_CAP_PC_MASK ) ) + ( ( ( _val ) << GRSPWROUTER_CAP_PC_SHIFT ) & GRSPWROUTER_CAP_PC_MASK ) ) #define GRSPWROUTER_CAP_PC( _val ) \ - ( ( ( _val ) << GRSPWROUTER_CAP_PC_SHIFT ) & \ - GRSPWROUTER_CAP_PC_MASK ) + ( ( ( _val ) << GRSPWROUTER_CAP_PC_SHIFT ) & GRSPWROUTER_CAP_PC_MASK ) #define GRSPWROUTER_CAP_CC_SHIFT 0 -#define GRSPWROUTER_CAP_CC_MASK 0x1fU +#define GRSPWROUTER_CAP_CC_MASK 0x1fU #define GRSPWROUTER_CAP_CC_GET( _reg ) \ - ( ( ( _reg ) & GRSPWROUTER_CAP_CC_MASK ) >> \ - GRSPWROUTER_CAP_CC_SHIFT ) -#define GRSPWROUTER_CAP_CC_SET( _reg, _val ) \ + ( ( ( _reg ) & GRSPWROUTER_CAP_CC_MASK ) >> GRSPWROUTER_CAP_CC_SHIFT ) +#define GRSPWROUTER_CAP_CC_SET( _reg, _val ) \ ( ( ( _reg ) & ~GRSPWROUTER_CAP_CC_MASK ) | \ - ( ( ( _val ) << GRSPWROUTER_CAP_CC_SHIFT ) & \ - GRSPWROUTER_CAP_CC_MASK ) ) + ( ( ( _val ) << GRSPWROUTER_CAP_CC_SHIFT ) & GRSPWROUTER_CAP_CC_MASK ) ) #define GRSPWROUTER_CAP_CC( _val ) \ - ( ( ( _val ) << GRSPWROUTER_CAP_CC_SHIFT ) & \ - GRSPWROUTER_CAP_CC_MASK ) + ( ( ( _val ) << GRSPWROUTER_CAP_CC_SHIFT ) & GRSPWROUTER_CAP_CC_MASK ) /** @} */ @@ -1265,28 +1195,28 @@ typedef struct grspwrouter_portstats { */ #define GRSPWROUTER_PNPVEND_VI_SHIFT 16 -#define GRSPWROUTER_PNPVEND_VI_MASK 0xffff0000U -#define GRSPWROUTER_PNPVEND_VI_GET( _reg ) \ +#define GRSPWROUTER_PNPVEND_VI_MASK 0xffff0000U +#define GRSPWROUTER_PNPVEND_VI_GET( _reg ) \ ( ( ( _reg ) & GRSPWROUTER_PNPVEND_VI_MASK ) >> \ GRSPWROUTER_PNPVEND_VI_SHIFT ) -#define GRSPWROUTER_PNPVEND_VI_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPWROUTER_PNPVEND_VI_MASK ) | \ +#define GRSPWROUTER_PNPVEND_VI_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_PNPVEND_VI_MASK ) | \ ( ( ( _val ) << GRSPWROUTER_PNPVEND_VI_SHIFT ) & \ GRSPWROUTER_PNPVEND_VI_MASK ) ) -#define GRSPWROUTER_PNPVEND_VI( _val ) \ +#define GRSPWROUTER_PNPVEND_VI( _val ) \ ( ( ( _val ) << GRSPWROUTER_PNPVEND_VI_SHIFT ) & \ GRSPWROUTER_PNPVEND_VI_MASK ) #define GRSPWROUTER_PNPVEND_PI_SHIFT 0 -#define GRSPWROUTER_PNPVEND_PI_MASK 0x3ffffffU -#define GRSPWROUTER_PNPVEND_PI_GET( _reg ) \ +#define GRSPWROUTER_PNPVEND_PI_MASK 0x3ffffffU +#define GRSPWROUTER_PNPVEND_PI_GET( _reg ) \ ( ( ( _reg ) & GRSPWROUTER_PNPVEND_PI_MASK ) >> \ GRSPWROUTER_PNPVEND_PI_SHIFT ) -#define GRSPWROUTER_PNPVEND_PI_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPWROUTER_PNPVEND_PI_MASK ) | \ +#define GRSPWROUTER_PNPVEND_PI_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_PNPVEND_PI_MASK ) | \ ( ( ( _val ) << GRSPWROUTER_PNPVEND_PI_SHIFT ) & \ GRSPWROUTER_PNPVEND_PI_MASK ) ) -#define GRSPWROUTER_PNPVEND_PI( _val ) \ +#define GRSPWROUTER_PNPVEND_PI( _val ) \ ( ( ( _val ) << GRSPWROUTER_PNPVEND_PI_SHIFT ) & \ GRSPWROUTER_PNPVEND_PI_MASK ) @@ -1302,28 +1232,28 @@ typedef struct grspwrouter_portstats { */ #define GRSPWROUTER_PNPUVEND_VI_SHIFT 16 -#define GRSPWROUTER_PNPUVEND_VI_MASK 0xffff0000U -#define GRSPWROUTER_PNPUVEND_VI_GET( _reg ) \ +#define GRSPWROUTER_PNPUVEND_VI_MASK 0xffff0000U +#define GRSPWROUTER_PNPUVEND_VI_GET( _reg ) \ ( ( ( _reg ) & GRSPWROUTER_PNPUVEND_VI_MASK ) >> \ GRSPWROUTER_PNPUVEND_VI_SHIFT ) -#define GRSPWROUTER_PNPUVEND_VI_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPWROUTER_PNPUVEND_VI_MASK ) | \ +#define GRSPWROUTER_PNPUVEND_VI_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_PNPUVEND_VI_MASK ) | \ ( ( ( _val ) << GRSPWROUTER_PNPUVEND_VI_SHIFT ) & \ GRSPWROUTER_PNPUVEND_VI_MASK ) ) -#define GRSPWROUTER_PNPUVEND_VI( _val ) \ +#define GRSPWROUTER_PNPUVEND_VI( _val ) \ ( ( ( _val ) << GRSPWROUTER_PNPUVEND_VI_SHIFT ) & \ GRSPWROUTER_PNPUVEND_VI_MASK ) #define GRSPWROUTER_PNPUVEND_PI_SHIFT 0 -#define GRSPWROUTER_PNPUVEND_PI_MASK 0x3ffffffU -#define GRSPWROUTER_PNPUVEND_PI_GET( _reg ) \ +#define GRSPWROUTER_PNPUVEND_PI_MASK 0x3ffffffU +#define GRSPWROUTER_PNPUVEND_PI_GET( _reg ) \ ( ( ( _reg ) & GRSPWROUTER_PNPUVEND_PI_MASK ) >> \ GRSPWROUTER_PNPUVEND_PI_SHIFT ) -#define GRSPWROUTER_PNPUVEND_PI_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPWROUTER_PNPUVEND_PI_MASK ) | \ +#define GRSPWROUTER_PNPUVEND_PI_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_PNPUVEND_PI_MASK ) | \ ( ( ( _val ) << GRSPWROUTER_PNPUVEND_PI_SHIFT ) & \ GRSPWROUTER_PNPUVEND_PI_MASK ) ) -#define GRSPWROUTER_PNPUVEND_PI( _val ) \ +#define GRSPWROUTER_PNPUVEND_PI( _val ) \ ( ( ( _val ) << GRSPWROUTER_PNPUVEND_PI_SHIFT ) & \ GRSPWROUTER_PNPUVEND_PI_MASK ) @@ -1339,17 +1269,15 @@ typedef struct grspwrouter_portstats { */ #define GRSPWROUTER_PNPUSN_SN_SHIFT 0 -#define GRSPWROUTER_PNPUSN_SN_MASK 0xffffffffU +#define GRSPWROUTER_PNPUSN_SN_MASK 0xffffffffU #define GRSPWROUTER_PNPUSN_SN_GET( _reg ) \ - ( ( ( _reg ) & GRSPWROUTER_PNPUSN_SN_MASK ) >> \ - GRSPWROUTER_PNPUSN_SN_SHIFT ) -#define GRSPWROUTER_PNPUSN_SN_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPWROUTER_PNPUSN_SN_MASK ) | \ + ( ( ( _reg ) & GRSPWROUTER_PNPUSN_SN_MASK ) >> GRSPWROUTER_PNPUSN_SN_SHIFT ) +#define GRSPWROUTER_PNPUSN_SN_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_PNPUSN_SN_MASK ) | \ ( ( ( _val ) << GRSPWROUTER_PNPUSN_SN_SHIFT ) & \ GRSPWROUTER_PNPUSN_SN_MASK ) ) #define GRSPWROUTER_PNPUSN_SN( _val ) \ - ( ( ( _val ) << GRSPWROUTER_PNPUSN_SN_SHIFT ) & \ - GRSPWROUTER_PNPUSN_SN_MASK ) + ( ( ( _val ) << GRSPWROUTER_PNPUSN_SN_SHIFT ) & GRSPWROUTER_PNPUSN_SN_MASK ) /** @} */ @@ -1363,15 +1291,15 @@ typedef struct grspwrouter_portstats { */ #define GRSPWROUTER_PNPNETDISC_ND_SHIFT 0 -#define GRSPWROUTER_PNPNETDISC_ND_MASK 0xffffffffU -#define GRSPWROUTER_PNPNETDISC_ND_GET( _reg ) \ +#define GRSPWROUTER_PNPNETDISC_ND_MASK 0xffffffffU +#define GRSPWROUTER_PNPNETDISC_ND_GET( _reg ) \ ( ( ( _reg ) & GRSPWROUTER_PNPNETDISC_ND_MASK ) >> \ GRSPWROUTER_PNPNETDISC_ND_SHIFT ) -#define GRSPWROUTER_PNPNETDISC_ND_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPWROUTER_PNPNETDISC_ND_MASK ) | \ +#define GRSPWROUTER_PNPNETDISC_ND_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_PNPNETDISC_ND_MASK ) | \ ( ( ( _val ) << GRSPWROUTER_PNPNETDISC_ND_SHIFT ) & \ GRSPWROUTER_PNPNETDISC_ND_MASK ) ) -#define GRSPWROUTER_PNPNETDISC_ND( _val ) \ +#define GRSPWROUTER_PNPNETDISC_ND( _val ) \ ( ( ( _val ) << GRSPWROUTER_PNPNETDISC_ND_SHIFT ) & \ GRSPWROUTER_PNPNETDISC_ND_MASK ) @@ -1387,15 +1315,15 @@ typedef struct grspwrouter_portstats { */ #define GRSPWROUTER_MAXPLEN_ML_SHIFT 0 -#define GRSPWROUTER_MAXPLEN_ML_MASK 0x1ffffffU -#define GRSPWROUTER_MAXPLEN_ML_GET( _reg ) \ +#define GRSPWROUTER_MAXPLEN_ML_MASK 0x1ffffffU +#define GRSPWROUTER_MAXPLEN_ML_GET( _reg ) \ ( ( ( _reg ) & GRSPWROUTER_MAXPLEN_ML_MASK ) >> \ GRSPWROUTER_MAXPLEN_ML_SHIFT ) -#define GRSPWROUTER_MAXPLEN_ML_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPWROUTER_MAXPLEN_ML_MASK ) | \ +#define GRSPWROUTER_MAXPLEN_ML_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_MAXPLEN_ML_MASK ) | \ ( ( ( _val ) << GRSPWROUTER_MAXPLEN_ML_SHIFT ) & \ GRSPWROUTER_MAXPLEN_ML_MASK ) ) -#define GRSPWROUTER_MAXPLEN_ML( _val ) \ +#define GRSPWROUTER_MAXPLEN_ML( _val ) \ ( ( ( _val ) << GRSPWROUTER_MAXPLEN_ML_SHIFT ) & \ GRSPWROUTER_MAXPLEN_ML_MASK ) @@ -1411,28 +1339,28 @@ typedef struct grspwrouter_portstats { */ #define GRSPWROUTER_CREDCNT_OC_SHIFT 6 -#define GRSPWROUTER_CREDCNT_OC_MASK 0xfc0U -#define GRSPWROUTER_CREDCNT_OC_GET( _reg ) \ +#define GRSPWROUTER_CREDCNT_OC_MASK 0xfc0U +#define GRSPWROUTER_CREDCNT_OC_GET( _reg ) \ ( ( ( _reg ) & GRSPWROUTER_CREDCNT_OC_MASK ) >> \ GRSPWROUTER_CREDCNT_OC_SHIFT ) -#define GRSPWROUTER_CREDCNT_OC_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPWROUTER_CREDCNT_OC_MASK ) | \ +#define GRSPWROUTER_CREDCNT_OC_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_CREDCNT_OC_MASK ) | \ ( ( ( _val ) << GRSPWROUTER_CREDCNT_OC_SHIFT ) & \ GRSPWROUTER_CREDCNT_OC_MASK ) ) -#define GRSPWROUTER_CREDCNT_OC( _val ) \ +#define GRSPWROUTER_CREDCNT_OC( _val ) \ ( ( ( _val ) << GRSPWROUTER_CREDCNT_OC_SHIFT ) & \ GRSPWROUTER_CREDCNT_OC_MASK ) #define GRSPWROUTER_CREDCNT_IC_SHIFT 0 -#define GRSPWROUTER_CREDCNT_IC_MASK 0x3fU -#define GRSPWROUTER_CREDCNT_IC_GET( _reg ) \ +#define GRSPWROUTER_CREDCNT_IC_MASK 0x3fU +#define GRSPWROUTER_CREDCNT_IC_GET( _reg ) \ ( ( ( _reg ) & GRSPWROUTER_CREDCNT_IC_MASK ) >> \ GRSPWROUTER_CREDCNT_IC_SHIFT ) -#define GRSPWROUTER_CREDCNT_IC_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPWROUTER_CREDCNT_IC_MASK ) | \ +#define GRSPWROUTER_CREDCNT_IC_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_CREDCNT_IC_MASK ) | \ ( ( ( _val ) << GRSPWROUTER_CREDCNT_IC_SHIFT ) & \ GRSPWROUTER_CREDCNT_IC_MASK ) ) -#define GRSPWROUTER_CREDCNT_IC( _val ) \ +#define GRSPWROUTER_CREDCNT_IC( _val ) \ ( ( ( _val ) << GRSPWROUTER_CREDCNT_IC_SHIFT ) & \ GRSPWROUTER_CREDCNT_IC_MASK ) @@ -1448,17 +1376,15 @@ typedef struct grspwrouter_portstats { */ #define GRSPWROUTER_GPO_GPO_SHIFT 0 -#define GRSPWROUTER_GPO_GPO_MASK 0xffffffffU +#define GRSPWROUTER_GPO_GPO_MASK 0xffffffffU #define GRSPWROUTER_GPO_GPO_GET( _reg ) \ - ( ( ( _reg ) & GRSPWROUTER_GPO_GPO_MASK ) >> \ - GRSPWROUTER_GPO_GPO_SHIFT ) -#define GRSPWROUTER_GPO_GPO_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPWROUTER_GPO_GPO_MASK ) | \ + ( ( ( _reg ) & GRSPWROUTER_GPO_GPO_MASK ) >> GRSPWROUTER_GPO_GPO_SHIFT ) +#define GRSPWROUTER_GPO_GPO_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_GPO_GPO_MASK ) | \ ( ( ( _val ) << GRSPWROUTER_GPO_GPO_SHIFT ) & \ GRSPWROUTER_GPO_GPO_MASK ) ) #define GRSPWROUTER_GPO_GPO( _val ) \ - ( ( ( _val ) << GRSPWROUTER_GPO_GPO_SHIFT ) & \ - GRSPWROUTER_GPO_GPO_MASK ) + ( ( ( _val ) << GRSPWROUTER_GPO_GPO_SHIFT ) & GRSPWROUTER_GPO_GPO_MASK ) /** @} */ @@ -1472,17 +1398,15 @@ typedef struct grspwrouter_portstats { */ #define GRSPWROUTER_GPI_GPI_SHIFT 0 -#define GRSPWROUTER_GPI_GPI_MASK 0xffffffffU +#define GRSPWROUTER_GPI_GPI_MASK 0xffffffffU #define GRSPWROUTER_GPI_GPI_GET( _reg ) \ - ( ( ( _reg ) & GRSPWROUTER_GPI_GPI_MASK ) >> \ - GRSPWROUTER_GPI_GPI_SHIFT ) -#define GRSPWROUTER_GPI_GPI_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPWROUTER_GPI_GPI_MASK ) | \ + ( ( ( _reg ) & GRSPWROUTER_GPI_GPI_MASK ) >> GRSPWROUTER_GPI_GPI_SHIFT ) +#define GRSPWROUTER_GPI_GPI_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_GPI_GPI_MASK ) | \ ( ( ( _val ) << GRSPWROUTER_GPI_GPI_SHIFT ) & \ GRSPWROUTER_GPI_GPI_MASK ) ) #define GRSPWROUTER_GPI_GPI( _val ) \ - ( ( ( _val ) << GRSPWROUTER_GPI_GPI_SHIFT ) & \ - GRSPWROUTER_GPI_GPI_MASK ) + ( ( ( _val ) << GRSPWROUTER_GPI_GPI_SHIFT ) & GRSPWROUTER_GPI_GPI_MASK ) /** @} */ @@ -1504,17 +1428,15 @@ typedef struct grspwrouter_portstats { #define GRSPWROUTER_RTCOMB_HD 0x10000000U #define GRSPWROUTER_RTCOMB_PE_SHIFT 1 -#define GRSPWROUTER_RTCOMB_PE_MASK 0xffffffeU +#define GRSPWROUTER_RTCOMB_PE_MASK 0xffffffeU #define GRSPWROUTER_RTCOMB_PE_GET( _reg ) \ - ( ( ( _reg ) & GRSPWROUTER_RTCOMB_PE_MASK ) >> \ - GRSPWROUTER_RTCOMB_PE_SHIFT ) -#define GRSPWROUTER_RTCOMB_PE_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPWROUTER_RTCOMB_PE_MASK ) | \ + ( ( ( _reg ) & GRSPWROUTER_RTCOMB_PE_MASK ) >> GRSPWROUTER_RTCOMB_PE_SHIFT ) +#define GRSPWROUTER_RTCOMB_PE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_RTCOMB_PE_MASK ) | \ ( ( ( _val ) << GRSPWROUTER_RTCOMB_PE_SHIFT ) & \ GRSPWROUTER_RTCOMB_PE_MASK ) ) #define GRSPWROUTER_RTCOMB_PE( _val ) \ - ( ( ( _val ) << GRSPWROUTER_RTCOMB_PE_SHIFT ) & \ - GRSPWROUTER_RTCOMB_PE_MASK ) + ( ( ( _val ) << GRSPWROUTER_RTCOMB_PE_SHIFT ) & GRSPWROUTER_RTCOMB_PE_MASK ) #define GRSPWROUTER_RTCOMB_PD 0x1U @@ -1529,15 +1451,15 @@ typedef struct grspwrouter_portstats { */ #define GRSPWROUTER_APBAREA_APB_SHIFT 0 -#define GRSPWROUTER_APBAREA_APB_MASK 0xffffffffU -#define GRSPWROUTER_APBAREA_APB_GET( _reg ) \ +#define GRSPWROUTER_APBAREA_APB_MASK 0xffffffffU +#define GRSPWROUTER_APBAREA_APB_GET( _reg ) \ ( ( ( _reg ) & GRSPWROUTER_APBAREA_APB_MASK ) >> \ GRSPWROUTER_APBAREA_APB_SHIFT ) -#define GRSPWROUTER_APBAREA_APB_SET( _reg, _val ) \ - ( ( ( _reg ) & ~GRSPWROUTER_APBAREA_APB_MASK ) | \ +#define GRSPWROUTER_APBAREA_APB_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_APBAREA_APB_MASK ) | \ ( ( ( _val ) << GRSPWROUTER_APBAREA_APB_SHIFT ) & \ GRSPWROUTER_APBAREA_APB_MASK ) ) -#define GRSPWROUTER_APBAREA_APB( _val ) \ +#define GRSPWROUTER_APBAREA_APB( _val ) \ ( ( ( _val ) << GRSPWROUTER_APBAREA_APB_SHIFT ) & \ GRSPWROUTER_APBAREA_APB_MASK ) diff --git a/bsps/include/grlib/grtc.h b/bsps/include/grlib/grtc.h index 17ad165e9b..011115e6e8 100644 --- a/bsps/include/grlib/grtc.h +++ b/bsps/include/grlib/grtc.h @@ -34,58 +34,60 @@ extern "C" { #endif -#define GRTC_IOC_UNUSED 0 +#define GRTC_IOC_UNUSED 0 /* Driver operation controlling commands */ -#define GRTC_IOC_START 1 -#define GRTC_IOC_STOP 2 -#define GRTC_IOC_ISSTARTED 3 -#define GRTC_IOC_SET_BLOCKING_MODE 4 /* Raw mode only */ -#define GRTC_IOC_SET_TIMEOUT 5 /* Raw mode only */ +#define GRTC_IOC_START 1 +#define GRTC_IOC_STOP 2 +#define GRTC_IOC_ISSTARTED 3 +#define GRTC_IOC_SET_BLOCKING_MODE 4 /* Raw mode only */ +#define GRTC_IOC_SET_TIMEOUT 5 /* Raw mode only */ -#define GRTC_IOC_ADD_BUFF 16 /* Frame mode only */ -#define GRTC_IOC_RECV 17 /* Frame mode only */ +#define GRTC_IOC_ADD_BUFF 16 /* Frame mode only */ +#define GRTC_IOC_RECV 17 /* Frame mode only */ /* Available only in STOPPED mode */ -#define GRTC_IOC_SET_MODE 32 /* Set frame mode (ioctl) or raw mode (read) */ -#define GRTC_IOC_SET_BUF_PARAM 33 -#define GRTC_IOC_SET_CONFIG 34 -#define GRTC_IOC_POOLS_SETUP 35 /* Frame mode only */ +#define GRTC_IOC_SET_MODE 32 /* Set frame mode (ioctl) or raw mode (read) */ +#define GRTC_IOC_SET_BUF_PARAM 33 +#define GRTC_IOC_SET_CONFIG 34 +#define GRTC_IOC_POOLS_SETUP 35 /* Frame mode only */ /* Available in both running and stopped mode */ -#define GRTC_IOC_GET_CONFIG 64 -#define GRTC_IOC_GET_BUF_PARAM 65 -#define GRTC_IOC_GET_HW_STATUS 66 -#define GRTC_IOC_ASSIGN_FRM_POOL 67 -#define GRTC_IOC_GET_CLCW_ADR 68 /* Get address of CLCWRx1 */ -#define GRTC_IOC_GET_STATS 69 /* Get statistics, note that most of the stats are only avilable in FRAME mode */ -#define GRTC_IOC_CLR_STATS 70 /* Clear statistics */ +#define GRTC_IOC_GET_CONFIG 64 +#define GRTC_IOC_GET_BUF_PARAM 65 +#define GRTC_IOC_GET_HW_STATUS 66 +#define GRTC_IOC_ASSIGN_FRM_POOL 67 +#define GRTC_IOC_GET_CLCW_ADR 68 /* Get address of CLCWRx1 */ +#define GRTC_IOC_GET_STATS \ + 69 /* Get statistics, note that most of the stats are only avilable in FRAME mode */ +#define GRTC_IOC_CLR_STATS 70 /* Clear statistics */ /* Available only in RUNNING mode */ /* Args to GRTC_IOC_GET_BUF_PARAMS */ -#define GRTC_BUF_MAXLEN (0x100*1024) -#define GRTC_BUF_MASK 0xfffffc00 +#define GRTC_BUF_MAXLEN ( 0x100 * 1024 ) +#define GRTC_BUF_MASK 0xfffffc00 struct grtc_ioc_buf_params { - unsigned int length; /* Length of new buffer in multiples of 1kbyte blocks */ - void *custom_buffer; /* If set zero driver will allocate with malloc, set LSB to 1 to indicate remote address */ + unsigned int length; /* Length of new buffer in multiples of 1kbyte blocks */ + void * + custom_buffer; /* If set zero driver will allocate with malloc, set LSB to 1 to indicate remote address */ }; /* Args to GRTC_IOC_SET_BLOCKING_MODE */ enum { - GRTC_BLKMODE_POLL = 0, /* Never block (polling mode) */ - GRTC_BLKMODE_BLK = 1, /* Block until at least 1 byte can be read */ - GRTC_BLKMODE_COMPLETE = 2 /* Block until all data requested has be read */ + GRTC_BLKMODE_POLL = 0, /* Never block (polling mode) */ + GRTC_BLKMODE_BLK = 1, /* Block until at least 1 byte can be read */ + GRTC_BLKMODE_COMPLETE = 2 /* Block until all data requested has be read */ }; /* Argument of GRTC_IOC_SET_CONFIG and GRTC_IOC_GET_CONFIG * Pointer to: */ struct grtc_ioc_config { - int psr_enable; - int nrzm_enable; - int pss_enable; - int crc_calc; /* Enable Software CRC calculation (only Frame mode) */ + int psr_enable; + int nrzm_enable; + int pss_enable; + int crc_calc; /* Enable Software CRC calculation (only Frame mode) */ }; /* Argument of GRTC_IOC_GET_HW_STATUS: @@ -93,79 +95,80 @@ struct grtc_ioc_config { * in by driver. */ struct grtc_ioc_hw_status { - unsigned int sir; - unsigned int far; - unsigned int clcw1; - unsigned int clcw2; - unsigned int phir; - unsigned int str; + unsigned int sir; + unsigned int far; + unsigned int clcw1; + unsigned int clcw2; + unsigned int phir; + unsigned int str; }; struct grtc_hdr { - unsigned short flags_scid; - unsigned short vc_len; - unsigned char seqnum; -} __attribute__((packed)); + unsigned short flags_scid; + unsigned short vc_len; + unsigned char seqnum; +} __attribute__(( packed )); /* Frame pool, all frames in pool have the same buffer length (frame mode only) */ struct grtc_frame { - struct grtc_frame *next; /* Next frame in list */ - unsigned short len; /* Length of frame extracted */ - unsigned short reserved; /* Reserved */ - struct grtc_frame_pool *pool; /* The frame pool this frame belongs to */ - - /* The Frame content */ - struct grtc_hdr hdr; /* Primary Header */ - unsigned char data[3]; /* Frame payload */ -} __attribute__((packed)); + struct grtc_frame *next; /* Next frame in list */ + unsigned short len; /* Length of frame extracted */ + unsigned short reserved; /* Reserved */ + struct grtc_frame_pool *pool; /* The frame pool this frame belongs to */ + + /* The Frame content */ + struct grtc_hdr hdr; /* Primary Header */ + unsigned char data[ 3 ]; /* Frame payload */ +} __attribute__(( packed )); /* GRTC_IOC_RECV argument, single linked list of received frames */ struct grtc_list { - struct grtc_frame *head; /* First frame in list */ - struct grtc_frame *tail; /* Last frame in list */ - int cnt; /* Number of frames in list */ + struct grtc_frame *head; /* First frame in list */ + struct grtc_frame *tail; /* Last frame in list */ + int cnt; /* Number of frames in list */ }; struct grtc_ioc_pools_setup { - unsigned int pool_cnt; /* Number of pools */ - unsigned int pool_frame_len[1]; /* Array of 'pool_cnt' length: Frame length of frames in a pool + unsigned int pool_cnt; /* Number of pools */ + unsigned int pool_frame_len + [ 1 ]; /* Array of 'pool_cnt' length: Frame length of frames in a pool * Lengths must be sorted, starting with the smallest frame pool. */ }; struct grtc_ioc_assign_frm_pool { - unsigned int frame_len; /* The length of the pool to insert the frame into */ - struct grtc_frame *frames; /* Frames to assign to a pool */ + unsigned int frame_len; /* The length of the pool to insert the frame into */ + struct grtc_frame *frames; /* Frames to assign to a pool */ }; -enum { - GRTC_MODE_RAW = 0, - GRTC_MODE_FRAME = 1 -}; +enum { GRTC_MODE_RAW = 0, GRTC_MODE_FRAME = 1 }; /* TC driver stats collected during receiving. The statistics is only available * in FRAME mode. In RAW mode the user interprets the incoming frames and is * therefore responsible for generating the staticstics. */ struct grtc_ioc_stats { - unsigned long long frames_recv; /* Total number of non-erroneous frames received */ - /* Errors related to incoming data */ - unsigned int err; /* total number of errors */ - unsigned int err_hdr; /* number of errors in Header */ - unsigned int err_payload; /* Number of errors in payload */ - unsigned int err_ending; /* Number of errors in end (Filler, end marker) */ - unsigned int err_abandoned; /* Number of abandoned frames, NOT IMPLEMENTED */ - /* Errors related to the handling of incoming frames */ - unsigned int dropped; /* Number of dropped frames TC driver */ - unsigned int dropped_no_buf; /* Number of dropped frame caused by no buffers were available */ - unsigned int dropped_too_long; /* Number of dropped frames that was larger than any buffer available for driver */ + unsigned long long + frames_recv; /* Total number of non-erroneous frames received */ + /* Errors related to incoming data */ + unsigned int err; /* total number of errors */ + unsigned int err_hdr; /* number of errors in Header */ + unsigned int err_payload; /* Number of errors in payload */ + unsigned int err_ending; /* Number of errors in end (Filler, end marker) */ + unsigned int err_abandoned; /* Number of abandoned frames, NOT IMPLEMENTED */ + /* Errors related to the handling of incoming frames */ + unsigned int dropped; /* Number of dropped frames TC driver */ + unsigned int + dropped_no_buf; /* Number of dropped frame caused by no buffers were available */ + unsigned int + dropped_too_long; /* Number of dropped frames that was larger than any buffer available for driver */ }; /* Register GRTC driver at driver manager */ -void grtc_register_drv(void); +void grtc_register_drv( void ); /* Register GRTC RMAP driver at driver manager */ -void grtc_rmap_register_drv (void); +void grtc_rmap_register_drv( void ); #ifdef __cplusplus } diff --git a/bsps/include/grlib/grtm.h b/bsps/include/grlib/grtm.h index 8e667faa97..b04c7411e5 100644 --- a/bsps/include/grlib/grtm.h +++ b/bsps/include/grlib/grtm.h @@ -36,126 +36,139 @@ extern "C" { #endif -#define GRTM_IOC_UNUSED 0 +#define GRTM_IOC_UNUSED 0 /* Driver operation controlling commands */ -#define GRTM_IOC_START 1 -#define GRTM_IOC_STOP 2 -#define GRTM_IOC_ISSTARTED 3 -#define GRTM_IOC_SET_BLOCKING_MODE 4 -#define GRTM_IOC_SET_TIMEOUT 5 +#define GRTM_IOC_START 1 +#define GRTM_IOC_STOP 2 +#define GRTM_IOC_ISSTARTED 3 +#define GRTM_IOC_SET_BLOCKING_MODE 4 +#define GRTM_IOC_SET_TIMEOUT 5 /* Available only in STOPPED mode */ -#define GRTM_IOC_SET_CONFIG 32 +#define GRTM_IOC_SET_CONFIG 32 /* Available in both running and stopped mode */ -#define GRTM_IOC_RECLAIM 64 -#define GRTM_IOC_GET_CONFIG 65 -#define GRTM_IOC_GET_HW_IMPL 66 -#define GRTM_IOC_GET_HW_STATUS 67 /* Not implemented */ -#define GRTM_IOC_GET_OCFREG 68 -#define GRTM_IOC_GET_STATS 69 -#define GRTM_IOC_CLR_STATS 70 +#define GRTM_IOC_RECLAIM 64 +#define GRTM_IOC_GET_CONFIG 65 +#define GRTM_IOC_GET_HW_IMPL 66 +#define GRTM_IOC_GET_HW_STATUS 67 /* Not implemented */ +#define GRTM_IOC_GET_OCFREG 68 +#define GRTM_IOC_GET_STATS 69 +#define GRTM_IOC_CLR_STATS 70 /* Available only in RUNNING mode */ -#define GRTM_IOC_SEND 96 +#define GRTM_IOC_SEND 96 /* Args to GRTC_IOC_SET_BLOCKING_MODE */ enum { - GRTM_BLKMODE_POLL = 0, /* Never block (polling mode) */ - GRTM_BLKMODE_BLK = 1, /* Block until at least 1 byte can be read */ + GRTM_BLKMODE_POLL = 0, /* Never block (polling mode) */ + GRTM_BLKMODE_BLK = 1, /* Block until at least 1 byte can be read */ }; /* Reed Solomon Encoder implemented */ enum { - GRTM_RS_IMPL_NONE = 0, - GRTM_RS_IMPL_E16 = 1, /* E16 */ - GRTM_RS_IMPL_E8 = 2, /* E8 */ - GRTM_RS_IMPL_BOTH = 3 /* Both E8 and E16 */ + GRTM_RS_IMPL_NONE = 0, + GRTM_RS_IMPL_E16 = 1, /* E16 */ + GRTM_RS_IMPL_E8 = 2, /* E8 */ + GRTM_RS_IMPL_BOTH = 3 /* Both E8 and E16 */ }; struct grtm_ioc_hw { - char cs; /* Sub Carrier */ - char sp; /* Split-Phase Level */ - char ce; - char nrz; - char psr; - char te; - unsigned char rsdep; - unsigned char rs; - char aasm; - char fecf; - char ocf; - char evc; - char idle; - char fsh; - char mcg; - char iz; - char fhec; - char aos; - char cif; - char ocfb; - - unsigned short blk_size; /* Block Size */ - unsigned short fifo_size; /* FIFO Size */ - + char cs; /* Sub Carrier */ + char sp; /* Split-Phase Level */ + char ce; + char nrz; + char psr; + char te; + unsigned char rsdep; + unsigned char rs; + char aasm; + char fecf; + char ocf; + char evc; + char idle; + char fsh; + char mcg; + char iz; + char fhec; + char aos; + char cif; + char ocfb; + + unsigned short blk_size; /* Block Size */ + unsigned short fifo_size; /* FIFO Size */ }; /* Driver Mode */ enum { - GRTM_MODE_TM = 0, /* TM */ - GRTM_MODE_AOS = 1 /* AOS */ + GRTM_MODE_TM = 0, /* TM */ + GRTM_MODE_AOS = 1 /* AOS */ }; /* Physical layer Options */ -#define GRTM_IOC_PHY_SCF (1<<15) /* Sub Carrier Fall */ -#define GRTM_IOC_PHY_SF (1<<31) /* Symbol Fall */ +#define GRTM_IOC_PHY_SCF ( 1 << 15 ) /* Sub Carrier Fall */ +#define GRTM_IOC_PHY_SF ( 1 << 31 ) /* Symbol Fall */ /* Coding Sub-layer Options */ -#define GRTM_IOC_CODE_SC (1<<0) /* Enable Sub Carrier modulation */ -#define GRTM_IOC_CODE_SP (1<<1) /* Enable Split-Phase (SP) level modulation */ -#define GRTM_IOC_CODE_CE (1<<5) /* Enable Convolutional Encoding */ -#define GRTM_IOC_CODE_NRZ (1<<6) /* Enable Non-Return-to-Zero mark encoding */ -#define GRTM_IOC_CODE_PSR (1<<7) /* Enable Pseudo-Randomizer */ -#define GRTM_IOC_CODE_RS8 (1<<11) /* Reed-solomon Encoder to use: 0=E16, 1=E8 */ -#define GRTM_IOC_CODE_RS (1<<15) /* Enable Reed-Solomon Encoder */ -#define GRTM_IOC_CODE_AASM (1<<16) /* Enable Alternative attached synchronization marker */ -#define GRTM_IOC_CODE_ALL (GRTM_IOC_CODE_SC|GRTM_IOC_CODE_SP|GRTM_IOC_CODE_CE| \ - GRTM_IOC_CODE_NRZ|GRTM_IOC_CODE_PSR|GRTM_IOC_CODE_RS8|\ - GRTM_IOC_CODE_RS|GRTM_IOC_CODE_AASM) +#define GRTM_IOC_CODE_SC ( 1 << 0 ) /* Enable Sub Carrier modulation */ +#define GRTM_IOC_CODE_SP \ + ( 1 << 1 ) /* Enable Split-Phase (SP) level modulation */ +#define GRTM_IOC_CODE_CE ( 1 << 5 ) /* Enable Convolutional Encoding */ +#define GRTM_IOC_CODE_NRZ \ + ( 1 << 6 ) /* Enable Non-Return-to-Zero mark encoding */ +#define GRTM_IOC_CODE_PSR ( 1 << 7 ) /* Enable Pseudo-Randomizer */ +#define GRTM_IOC_CODE_RS8 \ + ( 1 << 11 ) /* Reed-solomon Encoder to use: 0=E16, 1=E8 */ +#define GRTM_IOC_CODE_RS ( 1 << 15 ) /* Enable Reed-Solomon Encoder */ +#define GRTM_IOC_CODE_AASM \ + ( 1 << 16 ) /* Enable Alternative attached synchronization marker */ +#define GRTM_IOC_CODE_ALL \ + ( GRTM_IOC_CODE_SC | GRTM_IOC_CODE_SP | GRTM_IOC_CODE_CE | \ + GRTM_IOC_CODE_NRZ | GRTM_IOC_CODE_PSR | GRTM_IOC_CODE_RS8 | \ + GRTM_IOC_CODE_RS | GRTM_IOC_CODE_AASM ) enum { - GRTM_CERATE_00 = 0, /* Rate 1/2, no puncturing */ - GRTM_CERATE_02 = 2, /* Rate 1/2, punctured */ - GRTM_CERATE_04 = 4, /* Rate 2/3, punctured */ - GRTM_CERATE_05 = 5, /* Rate 3/4, punctured */ - GRTM_CERATE_06 = 6, /* Rate 5/6, punctured */ - GRTM_CERATE_07 = 7, /* Rate 7/8, punctured */ + GRTM_CERATE_00 = 0, /* Rate 1/2, no puncturing */ + GRTM_CERATE_02 = 2, /* Rate 1/2, punctured */ + GRTM_CERATE_04 = 4, /* Rate 2/3, punctured */ + GRTM_CERATE_05 = 5, /* Rate 3/4, punctured */ + GRTM_CERATE_06 = 6, /* Rate 5/6, punctured */ + GRTM_CERATE_07 = 7, /* Rate 7/8, punctured */ }; /* Options for Generating all frames */ -#define GRTM_IOC_ALL_FHEC 0x01 /* Enable Frame Header Error Control (Only AOS) */ -#define GRTM_IOC_ALL_FECF 0x02 /* Enable Transfer Frame CRC */ -#define GRTM_IOC_ALL_IZ 0x04 /* Enable Insert Zone */ -#define GRTM_IOC_ALL_ALL (GRTM_IOC_ALL_FHEC|GRTM_IOC_ALL_FECF|GRTM_IOC_ALL_IZ) +#define GRTM_IOC_ALL_FHEC \ + 0x01 /* Enable Frame Header Error Control (Only AOS) */ +#define GRTM_IOC_ALL_FECF 0x02 /* Enable Transfer Frame CRC */ +#define GRTM_IOC_ALL_IZ 0x04 /* Enable Insert Zone */ +#define GRTM_IOC_ALL_ALL \ + ( GRTM_IOC_ALL_FHEC | GRTM_IOC_ALL_FECF | GRTM_IOC_ALL_IZ ) /* Master Frame Generation Options */ -#define GRTM_IOC_MF_OW 0x01 /* Over Write OCF bits 16 and 17 */ -#define GRTM_IOC_MF_OCF 0x02 /* Enable Operation Control Field (OCF) for master channel */ -#define GRTM_IOC_MF_FSH 0x04 /* Enable MC_FSH for master channel */ -#define GRTM_IOC_MF_MC 0x08 /* Enable Master channel counter generation */ -#define GRTM_IOC_MF_ALL (GRTM_IOC_MF_OW|GRTM_IOC_MF_OCF|GRTM_IOC_MF_FSH|GRTM_IOC_MF_MC) +#define GRTM_IOC_MF_OW 0x01 /* Over Write OCF bits 16 and 17 */ +#define GRTM_IOC_MF_OCF \ + 0x02 /* Enable Operation Control Field (OCF) for master channel */ +#define GRTM_IOC_MF_FSH 0x04 /* Enable MC_FSH for master channel */ +#define GRTM_IOC_MF_MC 0x08 /* Enable Master channel counter generation */ +#define GRTM_IOC_MF_ALL \ + ( GRTM_IOC_MF_OW | GRTM_IOC_MF_OCF | GRTM_IOC_MF_FSH | GRTM_IOC_MF_MC ) /* Idle Frames Generation Options */ -#define GRTM_IOC_IDLE_MC 0x01 /* Enable Master Channel (MC) counter generation (TM Only) */ -#define GRTM_IOC_IDLE_VCC 0x02 /* Enable Virtual Channel counter cycle generation (AOS Only)*/ -#define GRTM_IOC_IDLE_FSH 0x04 /* Enable Frame Secondary Header (FSH) for idle frames (TM Only) */ -#define GRTM_IOC_IDLE_EVC 0x08 /* Enable Extended Virtual Channel Counter Generation */ -#define GRTM_IOC_IDLE_OCF 0x10 /* Enable OCF/CLCW in idle frame */ -#define GRTM_IOC_IDLE_EN 0x20 /* Enable Idle frame generation */ -#define GRTM_IOC_IDLE_ALL (GRTM_IOC_IDLE_MC|GRTM_IOC_IDLE_VCC|GRTM_IOC_IDLE_FSH| \ - GRTM_IOC_IDLE_EVC|GRTM_IOC_IDLE_OCF|GRTM_IOC_IDLE_EN) +#define GRTM_IOC_IDLE_MC \ + 0x01 /* Enable Master Channel (MC) counter generation (TM Only) */ +#define GRTM_IOC_IDLE_VCC \ + 0x02 /* Enable Virtual Channel counter cycle generation (AOS Only)*/ +#define GRTM_IOC_IDLE_FSH \ + 0x04 /* Enable Frame Secondary Header (FSH) for idle frames (TM Only) */ +#define GRTM_IOC_IDLE_EVC \ + 0x08 /* Enable Extended Virtual Channel Counter Generation */ +#define GRTM_IOC_IDLE_OCF 0x10 /* Enable OCF/CLCW in idle frame */ +#define GRTM_IOC_IDLE_EN 0x20 /* Enable Idle frame generation */ +#define GRTM_IOC_IDLE_ALL \ + ( GRTM_IOC_IDLE_MC | GRTM_IOC_IDLE_VCC | GRTM_IOC_IDLE_FSH | \ + GRTM_IOC_IDLE_EVC | GRTM_IOC_IDLE_OCF | GRTM_IOC_IDLE_EN ) /* Argument of GRTM_IOC_SET_CONFIG and GRTM_IOC_GET_CONFIG. * Driver and Hardware configuration. @@ -163,99 +176,110 @@ enum { * Pointer to: */ struct grtm_ioc_config { + /* Mode AOS or TM */ + unsigned char mode; /* 0=TM, 1=AOS */ - /* Mode AOS or TM */ - unsigned char mode; /* 0=TM, 1=AOS */ + unsigned short frame_length; /* Length of every frame transmitted */ + unsigned short + limit; /* Number of data bytes fetched by DMA before transmission starts */ + unsigned int as_marker; /* Attached Synchronization Marker */ - unsigned short frame_length; /* Length of every frame transmitted */ - unsigned short limit; /* Number of data bytes fetched by DMA before transmission starts */ - unsigned int as_marker; /* Attached Synchronization Marker */ - - /* Physical layer options */ - unsigned short phy_subrate; /* Sub Carrier rate - sub carrier devision factor - 1 */ - unsigned short phy_symbolrate; /* Symbol Rate division factor - 1 */ - unsigned char phy_opts; /* Mask of GRTM_IOC_PHY_XXXX */ + /* Physical layer options */ + unsigned short + phy_subrate; /* Sub Carrier rate - sub carrier devision factor - 1 */ + unsigned short phy_symbolrate; /* Symbol Rate division factor - 1 */ + unsigned char phy_opts; /* Mask of GRTM_IOC_PHY_XXXX */ - /* Coding sub-layer Options */ - unsigned char code_rsdep; /* Coding sub-layer Reed-Solomon interleave depth (3-bit) */ - unsigned char code_ce_rate; /* Convolutional encoding rate, select one of GRTM_CERATE_00 ... GRTM_CERATE_07 */ - unsigned char code_csel; /* */ - unsigned int code_opts; /* Mask of GRTM_IOC_CODE_XXXX */ + /* Coding sub-layer Options */ + unsigned char + code_rsdep; /* Coding sub-layer Reed-Solomon interleave depth (3-bit) */ + unsigned char + code_ce_rate; /* Convolutional encoding rate, select one of GRTM_CERATE_00 ... GRTM_CERATE_07 */ + unsigned char code_csel; /* */ + unsigned int code_opts; /* Mask of GRTM_IOC_CODE_XXXX */ - /* All Frames Generation */ - unsigned char all_izlen; /* FSH/IZ Length (5-bit) */ - unsigned char all_opts; /* Mask of GRTM_IOC_ALL_XXXX */ + /* All Frames Generation */ + unsigned char all_izlen; /* FSH/IZ Length (5-bit) */ + unsigned char all_opts; /* Mask of GRTM_IOC_ALL_XXXX */ - /* Master Frame Generation */ - unsigned char mf_opts; /* Mask of GRTM_IOC_MF_XXXX */ + /* Master Frame Generation */ + unsigned char mf_opts; /* Mask of GRTM_IOC_MF_XXXX */ - /* Idle frame Generation */ - unsigned short idle_scid; - unsigned char idle_vcid; - unsigned char idle_opts; /* Mask of GRTM_IOC_IDLE_XXXX */ + /* Idle frame Generation */ + unsigned short idle_scid; + unsigned char idle_vcid; + unsigned char idle_opts; /* Mask of GRTM_IOC_IDLE_XXXX */ - /* Interrupt options */ - unsigned int enable_cnt; /* Number of frames in between Interrupt is generated, Zero disables interrupt */ - int isr_desc_proc; /* Enable ISR to process descriptors */ - int blocking; /* Blocking mode select (POLL,BLK..) */ - rtems_interval timeout; /* Blocking mode timeout */ + /* Interrupt options */ + unsigned int + enable_cnt; /* Number of frames in between Interrupt is generated, Zero disables interrupt */ + int isr_desc_proc; /* Enable ISR to process descriptors */ + int blocking; /* Blocking mode select (POLL,BLK..) */ + rtems_interval timeout; /* Blocking mode timeout */ }; struct grtm_frame; struct grtm_list { - struct grtm_frame *head; /* First Frame in list */ - struct grtm_frame *tail; /* Last Frame in list */ + struct grtm_frame *head; /* First Frame in list */ + struct grtm_frame *tail; /* Last Frame in list */ }; -#define GRTM_FLAGS_SENT 0x01 -#define GRRM_FLAGS_ERR 0x02 +#define GRTM_FLAGS_SENT 0x01 +#define GRRM_FLAGS_ERR 0x02 -#define GRTM_FLAGS_TRANSLATE (1<<31) /* Translate frame payload address from CPU address to remote bus (the bus GRTM is resident on) */ -#define GRTM_FLAGS_TRANSLATE_AND_REMEMBER (1<<30) /* As GRTM_FLAGS_TRANSLATE, however if the translated payload address equals the payload address +#define GRTM_FLAGS_TRANSLATE \ + ( 1 \ + << 31 ) /* Translate frame payload address from CPU address to remote bus (the bus GRTM is resident on) */ +#define GRTM_FLAGS_TRANSLATE_AND_REMEMBER \ + ( 1 \ + << 30 ) /* As GRTM_FLAGS_TRANSLATE, however if the translated payload address equals the payload address * the GRTM_FLAGS_TRANSLATE_AND_REMEMBER bit is cleared and the GRTM_FLAGS_TRANSLATE bit is set */ -#define GRTM_FLAGS_COPY_DATA (1<<29) /* Where available: Transfer Frame payload to target, may be used for SpaceWire, where the GRTM driver transfer +#define GRTM_FLAGS_COPY_DATA \ + ( 1 \ + << 29 ) /* Where available: Transfer Frame payload to target, may be used for SpaceWire, where the GRTM driver transfer * the payload to a buffer on the SpaceWire target. */ -#define GRTM_FLAGS_TS (1<<14) -#define GRTM_FLAGS_VCE (1<<9) -#define GRTM_FLAGS_MCB (1<<8) -#define GRTM_FLAGS_FSHB (1<<7) -#define GRTM_FLAGS_OCFB (1<<6) -#define GRTM_FLAGS_FHECB (1<<5) -#define GRTM_FLAGS_IZB (1<<4) -#define GRTM_FLAGS_FECFB (1<<3) +#define GRTM_FLAGS_TS ( 1 << 14 ) +#define GRTM_FLAGS_VCE ( 1 << 9 ) +#define GRTM_FLAGS_MCB ( 1 << 8 ) +#define GRTM_FLAGS_FSHB ( 1 << 7 ) +#define GRTM_FLAGS_OCFB ( 1 << 6 ) +#define GRTM_FLAGS_FHECB ( 1 << 5 ) +#define GRTM_FLAGS_IZB ( 1 << 4 ) +#define GRTM_FLAGS_FECFB ( 1 << 3 ) -#define GRTM_FLAGS_MASK (GRTM_FLAGS_TS|GRTM_FLAGS_VCE|GRTM_FLAGS_MCB|\ - GRTM_FLAGS_FSHB|GRTM_FLAGS_OCFB|GRTM_FLAGS_FHECB|\ - GRTM_FLAGS_IZB|GRTM_FLAGS_FECFB) +#define GRTM_FLAGS_MASK \ + ( GRTM_FLAGS_TS | GRTM_FLAGS_VCE | GRTM_FLAGS_MCB | GRTM_FLAGS_FSHB | \ + GRTM_FLAGS_OCFB | GRTM_FLAGS_FHECB | GRTM_FLAGS_IZB | GRTM_FLAGS_FECFB ) /* The GRTM software representation of a Frame */ struct grtm_frame { - /* Options and status */ - unsigned int flags; /* bypass options, and sent/error status */ - - struct grtm_frame *next; /* Next packet in chain */ + /* Options and status */ + unsigned int flags; /* bypass options, and sent/error status */ - unsigned int *payload; /* The Headers and Payload, Frame data and header must be word aligned */ + struct grtm_frame *next; /* Next packet in chain */ + + unsigned int * + payload; /* The Headers and Payload, Frame data and header must be word aligned */ }; -#define FRAME_SIZE(payloadlen) (sizeof(struct grtm_frame)+payloadlen) +#define FRAME_SIZE( payloadlen ) ( sizeof( struct grtm_frame ) + payloadlen ) struct grtm_ioc_stats { - unsigned long long frames_sent; - unsigned int err_underrun; - unsigned int err_tx; - unsigned int err_ahb; - unsigned int err_transfer_frame; + unsigned long long frames_sent; + unsigned int err_underrun; + unsigned int err_tx; + unsigned int err_ahb; + unsigned int err_transfer_frame; }; /* Register GRTM driver at driver manager */ -void grtm_register_drv(void); +void grtm_register_drv( void ); /* Register GRTM RMAP driver at driver manager */ -void grtm_rmap_register_drv (void); +void grtm_rmap_register_drv( void ); #ifdef __cplusplus } diff --git a/bsps/include/grlib/i2cmst.h b/bsps/include/grlib/i2cmst.h index 65cc41d6f8..0365d65f3d 100644 --- a/bsps/include/grlib/i2cmst.h +++ b/bsps/include/grlib/i2cmst.h @@ -61,28 +61,28 @@ typedef struct gr_i2cmst_regs { } gr_i2cmst_regs_t; /* Control (CTRL) register */ -#define GRI2C_CTRL_EN 0x00000080 /* Enable core */ -#define GRI2C_CTRL_IEN 0x00000040 /* Interrupt enable */ +#define GRI2C_CTRL_EN 0x00000080 /* Enable core */ +#define GRI2C_CTRL_IEN 0x00000040 /* Interrupt enable */ /* Command (CMD) register */ -#define GRI2C_CMD_STA 0x00000080 /* Generate START condition */ -#define GRI2C_CMD_STO 0x00000040 /* Generate STOP condition */ -#define GRI2C_CMD_RD 0x00000020 /* Read from slave */ -#define GRI2C_CMD_WR 0x00000010 /* Write to slave */ -#define GRI2C_CMD_ACK 0x00000008 /* Acknowledge */ -#define GRI2C_CMD_IACK 0x00000001 /* Interrupt acknowledge */ +#define GRI2C_CMD_STA 0x00000080 /* Generate START condition */ +#define GRI2C_CMD_STO 0x00000040 /* Generate STOP condition */ +#define GRI2C_CMD_RD 0x00000020 /* Read from slave */ +#define GRI2C_CMD_WR 0x00000010 /* Write to slave */ +#define GRI2C_CMD_ACK 0x00000008 /* Acknowledge */ +#define GRI2C_CMD_IACK 0x00000001 /* Interrupt acknowledge */ /* Status (STS) register */ -#define GRI2C_STS_RXACK 0x00000080 /* Receive acknowledge */ -#define GRI2C_STS_BUSY 0x00000040 /* I2C-bus busy */ -#define GRI2C_STS_AL 0x00000020 /* Arbitration lost */ -#define GRI2C_STS_TIP 0x00000002 /* Transfer in progress */ -#define GRI2C_STS_IF 0x00000001 /* Interrupt flag */ +#define GRI2C_STS_RXACK 0x00000080 /* Receive acknowledge */ +#define GRI2C_STS_BUSY 0x00000040 /* I2C-bus busy */ +#define GRI2C_STS_AL 0x00000020 /* Arbitration lost */ +#define GRI2C_STS_TIP 0x00000002 /* Transfer in progress */ +#define GRI2C_STS_IF 0x00000001 /* Interrupt flag */ -#define GRI2C_STATUS_IDLE 0x00000000 +#define GRI2C_STATUS_IDLE 0x00000000 /* Register I2CMST driver to Driver Manager */ -void i2cmst_register_drv (void); +void i2cmst_register_drv( void ); #ifdef __cplusplus } diff --git a/bsps/include/grlib/irqamp-regs.h b/bsps/include/grlib/irqamp-regs.h index 97b56c9c86..6befc2ceec 100644 --- a/bsps/include/grlib/irqamp-regs.h +++ b/bsps/include/grlib/irqamp-regs.h @@ -83,17 +83,14 @@ extern "C" { */ #define IRQAMP_ITCNT_TCNT_SHIFT 0 -#define IRQAMP_ITCNT_TCNT_MASK 0xffffffffU +#define IRQAMP_ITCNT_TCNT_MASK 0xffffffffU #define IRQAMP_ITCNT_TCNT_GET( _reg ) \ - ( ( ( _reg ) & IRQAMP_ITCNT_TCNT_MASK ) >> \ - IRQAMP_ITCNT_TCNT_SHIFT ) -#define IRQAMP_ITCNT_TCNT_SET( _reg, _val ) \ + ( ( ( _reg ) & IRQAMP_ITCNT_TCNT_MASK ) >> IRQAMP_ITCNT_TCNT_SHIFT ) +#define IRQAMP_ITCNT_TCNT_SET( _reg, _val ) \ ( ( ( _reg ) & ~IRQAMP_ITCNT_TCNT_MASK ) | \ - ( ( ( _val ) << IRQAMP_ITCNT_TCNT_SHIFT ) & \ - IRQAMP_ITCNT_TCNT_MASK ) ) + ( ( ( _val ) << IRQAMP_ITCNT_TCNT_SHIFT ) & IRQAMP_ITCNT_TCNT_MASK ) ) #define IRQAMP_ITCNT_TCNT( _val ) \ - ( ( ( _val ) << IRQAMP_ITCNT_TCNT_SHIFT ) & \ - IRQAMP_ITCNT_TCNT_MASK ) + ( ( ( _val ) << IRQAMP_ITCNT_TCNT_SHIFT ) & IRQAMP_ITCNT_TCNT_MASK ) /** @} */ @@ -107,17 +104,15 @@ extern "C" { */ #define IRQAMP_ITSTMPC_TSTAMP_SHIFT 27 -#define IRQAMP_ITSTMPC_TSTAMP_MASK 0xf8000000U +#define IRQAMP_ITSTMPC_TSTAMP_MASK 0xf8000000U #define IRQAMP_ITSTMPC_TSTAMP_GET( _reg ) \ - ( ( ( _reg ) & IRQAMP_ITSTMPC_TSTAMP_MASK ) >> \ - IRQAMP_ITSTMPC_TSTAMP_SHIFT ) -#define IRQAMP_ITSTMPC_TSTAMP_SET( _reg, _val ) \ - ( ( ( _reg ) & ~IRQAMP_ITSTMPC_TSTAMP_MASK ) | \ + ( ( ( _reg ) & IRQAMP_ITSTMPC_TSTAMP_MASK ) >> IRQAMP_ITSTMPC_TSTAMP_SHIFT ) +#define IRQAMP_ITSTMPC_TSTAMP_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_ITSTMPC_TSTAMP_MASK ) | \ ( ( ( _val ) << IRQAMP_ITSTMPC_TSTAMP_SHIFT ) & \ IRQAMP_ITSTMPC_TSTAMP_MASK ) ) #define IRQAMP_ITSTMPC_TSTAMP( _val ) \ - ( ( ( _val ) << IRQAMP_ITSTMPC_TSTAMP_SHIFT ) & \ - IRQAMP_ITSTMPC_TSTAMP_MASK ) + ( ( ( _val ) << IRQAMP_ITSTMPC_TSTAMP_SHIFT ) & IRQAMP_ITSTMPC_TSTAMP_MASK ) #define IRQAMP_ITSTMPC_S1 0x4000000U @@ -126,17 +121,15 @@ extern "C" { #define IRQAMP_ITSTMPC_KS 0x20U #define IRQAMP_ITSTMPC_TSISEL_SHIFT 0 -#define IRQAMP_ITSTMPC_TSISEL_MASK 0x1fU +#define IRQAMP_ITSTMPC_TSISEL_MASK 0x1fU #define IRQAMP_ITSTMPC_TSISEL_GET( _reg ) \ - ( ( ( _reg ) & IRQAMP_ITSTMPC_TSISEL_MASK ) >> \ - IRQAMP_ITSTMPC_TSISEL_SHIFT ) -#define IRQAMP_ITSTMPC_TSISEL_SET( _reg, _val ) \ - ( ( ( _reg ) & ~IRQAMP_ITSTMPC_TSISEL_MASK ) | \ + ( ( ( _reg ) & IRQAMP_ITSTMPC_TSISEL_MASK ) >> IRQAMP_ITSTMPC_TSISEL_SHIFT ) +#define IRQAMP_ITSTMPC_TSISEL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_ITSTMPC_TSISEL_MASK ) | \ ( ( ( _val ) << IRQAMP_ITSTMPC_TSISEL_SHIFT ) & \ IRQAMP_ITSTMPC_TSISEL_MASK ) ) #define IRQAMP_ITSTMPC_TSISEL( _val ) \ - ( ( ( _val ) << IRQAMP_ITSTMPC_TSISEL_SHIFT ) & \ - IRQAMP_ITSTMPC_TSISEL_MASK ) + ( ( ( _val ) << IRQAMP_ITSTMPC_TSISEL_SHIFT ) & IRQAMP_ITSTMPC_TSISEL_MASK ) /** @} */ @@ -150,15 +143,15 @@ extern "C" { */ #define IRQAMP_ITSTMPAS_TASSERTION_SHIFT 0 -#define IRQAMP_ITSTMPAS_TASSERTION_MASK 0xffffffffU -#define IRQAMP_ITSTMPAS_TASSERTION_GET( _reg ) \ +#define IRQAMP_ITSTMPAS_TASSERTION_MASK 0xffffffffU +#define IRQAMP_ITSTMPAS_TASSERTION_GET( _reg ) \ ( ( ( _reg ) & IRQAMP_ITSTMPAS_TASSERTION_MASK ) >> \ IRQAMP_ITSTMPAS_TASSERTION_SHIFT ) -#define IRQAMP_ITSTMPAS_TASSERTION_SET( _reg, _val ) \ - ( ( ( _reg ) & ~IRQAMP_ITSTMPAS_TASSERTION_MASK ) | \ +#define IRQAMP_ITSTMPAS_TASSERTION_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_ITSTMPAS_TASSERTION_MASK ) | \ ( ( ( _val ) << IRQAMP_ITSTMPAS_TASSERTION_SHIFT ) & \ IRQAMP_ITSTMPAS_TASSERTION_MASK ) ) -#define IRQAMP_ITSTMPAS_TASSERTION( _val ) \ +#define IRQAMP_ITSTMPAS_TASSERTION( _val ) \ ( ( ( _val ) << IRQAMP_ITSTMPAS_TASSERTION_SHIFT ) & \ IRQAMP_ITSTMPAS_TASSERTION_MASK ) @@ -174,15 +167,15 @@ extern "C" { */ #define IRQAMP_ITSTMPAC_TACKNOWLEDGE_SHIFT 0 -#define IRQAMP_ITSTMPAC_TACKNOWLEDGE_MASK 0xffffffffU -#define IRQAMP_ITSTMPAC_TACKNOWLEDGE_GET( _reg ) \ +#define IRQAMP_ITSTMPAC_TACKNOWLEDGE_MASK 0xffffffffU +#define IRQAMP_ITSTMPAC_TACKNOWLEDGE_GET( _reg ) \ ( ( ( _reg ) & IRQAMP_ITSTMPAC_TACKNOWLEDGE_MASK ) >> \ IRQAMP_ITSTMPAC_TACKNOWLEDGE_SHIFT ) -#define IRQAMP_ITSTMPAC_TACKNOWLEDGE_SET( _reg, _val ) \ - ( ( ( _reg ) & ~IRQAMP_ITSTMPAC_TACKNOWLEDGE_MASK ) | \ +#define IRQAMP_ITSTMPAC_TACKNOWLEDGE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_ITSTMPAC_TACKNOWLEDGE_MASK ) | \ ( ( ( _val ) << IRQAMP_ITSTMPAC_TACKNOWLEDGE_SHIFT ) & \ IRQAMP_ITSTMPAC_TACKNOWLEDGE_MASK ) ) -#define IRQAMP_ITSTMPAC_TACKNOWLEDGE( _val ) \ +#define IRQAMP_ITSTMPAC_TACKNOWLEDGE( _val ) \ ( ( ( _val ) << IRQAMP_ITSTMPAC_TACKNOWLEDGE_SHIFT ) & \ IRQAMP_ITSTMPAC_TACKNOWLEDGE_MASK ) @@ -237,17 +230,15 @@ typedef struct irqamp_timestamp { */ #define IRQAMP_ILEVEL_IL_15_1_SHIFT 1 -#define IRQAMP_ILEVEL_IL_15_1_MASK 0xfffeU +#define IRQAMP_ILEVEL_IL_15_1_MASK 0xfffeU #define IRQAMP_ILEVEL_IL_15_1_GET( _reg ) \ - ( ( ( _reg ) & IRQAMP_ILEVEL_IL_15_1_MASK ) >> \ - IRQAMP_ILEVEL_IL_15_1_SHIFT ) -#define IRQAMP_ILEVEL_IL_15_1_SET( _reg, _val ) \ - ( ( ( _reg ) & ~IRQAMP_ILEVEL_IL_15_1_MASK ) | \ + ( ( ( _reg ) & IRQAMP_ILEVEL_IL_15_1_MASK ) >> IRQAMP_ILEVEL_IL_15_1_SHIFT ) +#define IRQAMP_ILEVEL_IL_15_1_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_ILEVEL_IL_15_1_MASK ) | \ ( ( ( _val ) << IRQAMP_ILEVEL_IL_15_1_SHIFT ) & \ IRQAMP_ILEVEL_IL_15_1_MASK ) ) #define IRQAMP_ILEVEL_IL_15_1( _val ) \ - ( ( ( _val ) << IRQAMP_ILEVEL_IL_15_1_SHIFT ) & \ - IRQAMP_ILEVEL_IL_15_1_MASK ) + ( ( ( _val ) << IRQAMP_ILEVEL_IL_15_1_SHIFT ) & IRQAMP_ILEVEL_IL_15_1_MASK ) /** @} */ @@ -260,30 +251,28 @@ typedef struct irqamp_timestamp { */ #define IRQAMP_IPEND_EIP_31_16_SHIFT 16 -#define IRQAMP_IPEND_EIP_31_16_MASK 0xffff0000U -#define IRQAMP_IPEND_EIP_31_16_GET( _reg ) \ +#define IRQAMP_IPEND_EIP_31_16_MASK 0xffff0000U +#define IRQAMP_IPEND_EIP_31_16_GET( _reg ) \ ( ( ( _reg ) & IRQAMP_IPEND_EIP_31_16_MASK ) >> \ IRQAMP_IPEND_EIP_31_16_SHIFT ) -#define IRQAMP_IPEND_EIP_31_16_SET( _reg, _val ) \ - ( ( ( _reg ) & ~IRQAMP_IPEND_EIP_31_16_MASK ) | \ +#define IRQAMP_IPEND_EIP_31_16_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_IPEND_EIP_31_16_MASK ) | \ ( ( ( _val ) << IRQAMP_IPEND_EIP_31_16_SHIFT ) & \ IRQAMP_IPEND_EIP_31_16_MASK ) ) -#define IRQAMP_IPEND_EIP_31_16( _val ) \ +#define IRQAMP_IPEND_EIP_31_16( _val ) \ ( ( ( _val ) << IRQAMP_IPEND_EIP_31_16_SHIFT ) & \ IRQAMP_IPEND_EIP_31_16_MASK ) #define IRQAMP_IPEND_IP_15_1_SHIFT 1 -#define IRQAMP_IPEND_IP_15_1_MASK 0xfffeU +#define IRQAMP_IPEND_IP_15_1_MASK 0xfffeU #define IRQAMP_IPEND_IP_15_1_GET( _reg ) \ - ( ( ( _reg ) & IRQAMP_IPEND_IP_15_1_MASK ) >> \ - IRQAMP_IPEND_IP_15_1_SHIFT ) -#define IRQAMP_IPEND_IP_15_1_SET( _reg, _val ) \ - ( ( ( _reg ) & ~IRQAMP_IPEND_IP_15_1_MASK ) | \ + ( ( ( _reg ) & IRQAMP_IPEND_IP_15_1_MASK ) >> IRQAMP_IPEND_IP_15_1_SHIFT ) +#define IRQAMP_IPEND_IP_15_1_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_IPEND_IP_15_1_MASK ) | \ ( ( ( _val ) << IRQAMP_IPEND_IP_15_1_SHIFT ) & \ IRQAMP_IPEND_IP_15_1_MASK ) ) #define IRQAMP_IPEND_IP_15_1( _val ) \ - ( ( ( _val ) << IRQAMP_IPEND_IP_15_1_SHIFT ) & \ - IRQAMP_IPEND_IP_15_1_MASK ) + ( ( ( _val ) << IRQAMP_IPEND_IP_15_1_SHIFT ) & IRQAMP_IPEND_IP_15_1_MASK ) /** @} */ @@ -297,15 +286,15 @@ typedef struct irqamp_timestamp { */ #define IRQAMP_IFORCE0_IF_15_1_SHIFT 1 -#define IRQAMP_IFORCE0_IF_15_1_MASK 0xfffeU -#define IRQAMP_IFORCE0_IF_15_1_GET( _reg ) \ +#define IRQAMP_IFORCE0_IF_15_1_MASK 0xfffeU +#define IRQAMP_IFORCE0_IF_15_1_GET( _reg ) \ ( ( ( _reg ) & IRQAMP_IFORCE0_IF_15_1_MASK ) >> \ IRQAMP_IFORCE0_IF_15_1_SHIFT ) -#define IRQAMP_IFORCE0_IF_15_1_SET( _reg, _val ) \ - ( ( ( _reg ) & ~IRQAMP_IFORCE0_IF_15_1_MASK ) | \ +#define IRQAMP_IFORCE0_IF_15_1_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_IFORCE0_IF_15_1_MASK ) | \ ( ( ( _val ) << IRQAMP_IFORCE0_IF_15_1_SHIFT ) & \ IRQAMP_IFORCE0_IF_15_1_MASK ) ) -#define IRQAMP_IFORCE0_IF_15_1( _val ) \ +#define IRQAMP_IFORCE0_IF_15_1( _val ) \ ( ( ( _val ) << IRQAMP_IFORCE0_IF_15_1_SHIFT ) & \ IRQAMP_IFORCE0_IF_15_1_MASK ) @@ -320,30 +309,28 @@ typedef struct irqamp_timestamp { */ #define IRQAMP_ICLEAR_EIC_31_16_SHIFT 16 -#define IRQAMP_ICLEAR_EIC_31_16_MASK 0xffff0000U -#define IRQAMP_ICLEAR_EIC_31_16_GET( _reg ) \ +#define IRQAMP_ICLEAR_EIC_31_16_MASK 0xffff0000U +#define IRQAMP_ICLEAR_EIC_31_16_GET( _reg ) \ ( ( ( _reg ) & IRQAMP_ICLEAR_EIC_31_16_MASK ) >> \ IRQAMP_ICLEAR_EIC_31_16_SHIFT ) -#define IRQAMP_ICLEAR_EIC_31_16_SET( _reg, _val ) \ - ( ( ( _reg ) & ~IRQAMP_ICLEAR_EIC_31_16_MASK ) | \ +#define IRQAMP_ICLEAR_EIC_31_16_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_ICLEAR_EIC_31_16_MASK ) | \ ( ( ( _val ) << IRQAMP_ICLEAR_EIC_31_16_SHIFT ) & \ IRQAMP_ICLEAR_EIC_31_16_MASK ) ) -#define IRQAMP_ICLEAR_EIC_31_16( _val ) \ +#define IRQAMP_ICLEAR_EIC_31_16( _val ) \ ( ( ( _val ) << IRQAMP_ICLEAR_EIC_31_16_SHIFT ) & \ IRQAMP_ICLEAR_EIC_31_16_MASK ) #define IRQAMP_ICLEAR_IC_15_1_SHIFT 1 -#define IRQAMP_ICLEAR_IC_15_1_MASK 0xfffeU +#define IRQAMP_ICLEAR_IC_15_1_MASK 0xfffeU #define IRQAMP_ICLEAR_IC_15_1_GET( _reg ) \ - ( ( ( _reg ) & IRQAMP_ICLEAR_IC_15_1_MASK ) >> \ - IRQAMP_ICLEAR_IC_15_1_SHIFT ) -#define IRQAMP_ICLEAR_IC_15_1_SET( _reg, _val ) \ - ( ( ( _reg ) & ~IRQAMP_ICLEAR_IC_15_1_MASK ) | \ + ( ( ( _reg ) & IRQAMP_ICLEAR_IC_15_1_MASK ) >> IRQAMP_ICLEAR_IC_15_1_SHIFT ) +#define IRQAMP_ICLEAR_IC_15_1_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_ICLEAR_IC_15_1_MASK ) | \ ( ( ( _val ) << IRQAMP_ICLEAR_IC_15_1_SHIFT ) & \ IRQAMP_ICLEAR_IC_15_1_MASK ) ) #define IRQAMP_ICLEAR_IC_15_1( _val ) \ - ( ( ( _val ) << IRQAMP_ICLEAR_IC_15_1_SHIFT ) & \ - IRQAMP_ICLEAR_IC_15_1_MASK ) + ( ( ( _val ) << IRQAMP_ICLEAR_IC_15_1_SHIFT ) & IRQAMP_ICLEAR_IC_15_1_MASK ) /** @} */ @@ -357,47 +344,39 @@ typedef struct irqamp_timestamp { */ #define IRQAMP_MPSTAT_NCPU_SHIFT 28 -#define IRQAMP_MPSTAT_NCPU_MASK 0xf0000000U +#define IRQAMP_MPSTAT_NCPU_MASK 0xf0000000U #define IRQAMP_MPSTAT_NCPU_GET( _reg ) \ - ( ( ( _reg ) & IRQAMP_MPSTAT_NCPU_MASK ) >> \ - IRQAMP_MPSTAT_NCPU_SHIFT ) -#define IRQAMP_MPSTAT_NCPU_SET( _reg, _val ) \ + ( ( ( _reg ) & IRQAMP_MPSTAT_NCPU_MASK ) >> IRQAMP_MPSTAT_NCPU_SHIFT ) +#define IRQAMP_MPSTAT_NCPU_SET( _reg, _val ) \ ( ( ( _reg ) & ~IRQAMP_MPSTAT_NCPU_MASK ) | \ - ( ( ( _val ) << IRQAMP_MPSTAT_NCPU_SHIFT ) & \ - IRQAMP_MPSTAT_NCPU_MASK ) ) + ( ( ( _val ) << IRQAMP_MPSTAT_NCPU_SHIFT ) & IRQAMP_MPSTAT_NCPU_MASK ) ) #define IRQAMP_MPSTAT_NCPU( _val ) \ - ( ( ( _val ) << IRQAMP_MPSTAT_NCPU_SHIFT ) & \ - IRQAMP_MPSTAT_NCPU_MASK ) + ( ( ( _val ) << IRQAMP_MPSTAT_NCPU_SHIFT ) & IRQAMP_MPSTAT_NCPU_MASK ) #define IRQAMP_MPSTAT_BA 0x8000000U #define IRQAMP_MPSTAT_ER 0x4000000U #define IRQAMP_MPSTAT_EIRQ_SHIFT 16 -#define IRQAMP_MPSTAT_EIRQ_MASK 0xf0000U +#define IRQAMP_MPSTAT_EIRQ_MASK 0xf0000U #define IRQAMP_MPSTAT_EIRQ_GET( _reg ) \ - ( ( ( _reg ) & IRQAMP_MPSTAT_EIRQ_MASK ) >> \ - IRQAMP_MPSTAT_EIRQ_SHIFT ) -#define IRQAMP_MPSTAT_EIRQ_SET( _reg, _val ) \ + ( ( ( _reg ) & IRQAMP_MPSTAT_EIRQ_MASK ) >> IRQAMP_MPSTAT_EIRQ_SHIFT ) +#define IRQAMP_MPSTAT_EIRQ_SET( _reg, _val ) \ ( ( ( _reg ) & ~IRQAMP_MPSTAT_EIRQ_MASK ) | \ - ( ( ( _val ) << IRQAMP_MPSTAT_EIRQ_SHIFT ) & \ - IRQAMP_MPSTAT_EIRQ_MASK ) ) + ( ( ( _val ) << IRQAMP_MPSTAT_EIRQ_SHIFT ) & IRQAMP_MPSTAT_EIRQ_MASK ) ) #define IRQAMP_MPSTAT_EIRQ( _val ) \ - ( ( ( _val ) << IRQAMP_MPSTAT_EIRQ_SHIFT ) & \ - IRQAMP_MPSTAT_EIRQ_MASK ) + ( ( ( _val ) << IRQAMP_MPSTAT_EIRQ_SHIFT ) & IRQAMP_MPSTAT_EIRQ_MASK ) #define IRQAMP_MPSTAT_STATUS_SHIFT 0 -#define IRQAMP_MPSTAT_STATUS_MASK 0xffffU +#define IRQAMP_MPSTAT_STATUS_MASK 0xffffU #define IRQAMP_MPSTAT_STATUS_GET( _reg ) \ - ( ( ( _reg ) & IRQAMP_MPSTAT_STATUS_MASK ) >> \ - IRQAMP_MPSTAT_STATUS_SHIFT ) -#define IRQAMP_MPSTAT_STATUS_SET( _reg, _val ) \ - ( ( ( _reg ) & ~IRQAMP_MPSTAT_STATUS_MASK ) | \ + ( ( ( _reg ) & IRQAMP_MPSTAT_STATUS_MASK ) >> IRQAMP_MPSTAT_STATUS_SHIFT ) +#define IRQAMP_MPSTAT_STATUS_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_MPSTAT_STATUS_MASK ) | \ ( ( ( _val ) << IRQAMP_MPSTAT_STATUS_SHIFT ) & \ IRQAMP_MPSTAT_STATUS_MASK ) ) #define IRQAMP_MPSTAT_STATUS( _val ) \ - ( ( ( _val ) << IRQAMP_MPSTAT_STATUS_SHIFT ) & \ - IRQAMP_MPSTAT_STATUS_MASK ) + ( ( ( _val ) << IRQAMP_MPSTAT_STATUS_SHIFT ) & IRQAMP_MPSTAT_STATUS_MASK ) /** @} */ @@ -410,17 +389,15 @@ typedef struct irqamp_timestamp { */ #define IRQAMP_BRDCST_BM15_1_SHIFT 1 -#define IRQAMP_BRDCST_BM15_1_MASK 0xfffeU +#define IRQAMP_BRDCST_BM15_1_MASK 0xfffeU #define IRQAMP_BRDCST_BM15_1_GET( _reg ) \ - ( ( ( _reg ) & IRQAMP_BRDCST_BM15_1_MASK ) >> \ - IRQAMP_BRDCST_BM15_1_SHIFT ) -#define IRQAMP_BRDCST_BM15_1_SET( _reg, _val ) \ - ( ( ( _reg ) & ~IRQAMP_BRDCST_BM15_1_MASK ) | \ + ( ( ( _reg ) & IRQAMP_BRDCST_BM15_1_MASK ) >> IRQAMP_BRDCST_BM15_1_SHIFT ) +#define IRQAMP_BRDCST_BM15_1_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_BRDCST_BM15_1_MASK ) | \ ( ( ( _val ) << IRQAMP_BRDCST_BM15_1_SHIFT ) & \ IRQAMP_BRDCST_BM15_1_MASK ) ) #define IRQAMP_BRDCST_BM15_1( _val ) \ - ( ( ( _val ) << IRQAMP_BRDCST_BM15_1_SHIFT ) & \ - IRQAMP_BRDCST_BM15_1_MASK ) + ( ( ( _val ) << IRQAMP_BRDCST_BM15_1_SHIFT ) & IRQAMP_BRDCST_BM15_1_MASK ) /** @} */ @@ -433,15 +410,15 @@ typedef struct irqamp_timestamp { */ #define IRQAMP_ERRSTAT_ERRMODE_3_0_SHIFT 0 -#define IRQAMP_ERRSTAT_ERRMODE_3_0_MASK 0xfU -#define IRQAMP_ERRSTAT_ERRMODE_3_0_GET( _reg ) \ +#define IRQAMP_ERRSTAT_ERRMODE_3_0_MASK 0xfU +#define IRQAMP_ERRSTAT_ERRMODE_3_0_GET( _reg ) \ ( ( ( _reg ) & IRQAMP_ERRSTAT_ERRMODE_3_0_MASK ) >> \ IRQAMP_ERRSTAT_ERRMODE_3_0_SHIFT ) -#define IRQAMP_ERRSTAT_ERRMODE_3_0_SET( _reg, _val ) \ - ( ( ( _reg ) & ~IRQAMP_ERRSTAT_ERRMODE_3_0_MASK ) | \ +#define IRQAMP_ERRSTAT_ERRMODE_3_0_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_ERRSTAT_ERRMODE_3_0_MASK ) | \ ( ( ( _val ) << IRQAMP_ERRSTAT_ERRMODE_3_0_SHIFT ) & \ IRQAMP_ERRSTAT_ERRMODE_3_0_MASK ) ) -#define IRQAMP_ERRSTAT_ERRMODE_3_0( _val ) \ +#define IRQAMP_ERRSTAT_ERRMODE_3_0( _val ) \ ( ( ( _val ) << IRQAMP_ERRSTAT_ERRMODE_3_0_SHIFT ) & \ IRQAMP_ERRSTAT_ERRMODE_3_0_MASK ) @@ -457,41 +434,39 @@ typedef struct irqamp_timestamp { */ #define IRQAMP_WDOGCTRL_NWDOG_SHIFT 27 -#define IRQAMP_WDOGCTRL_NWDOG_MASK 0xf8000000U +#define IRQAMP_WDOGCTRL_NWDOG_MASK 0xf8000000U #define IRQAMP_WDOGCTRL_NWDOG_GET( _reg ) \ - ( ( ( _reg ) & IRQAMP_WDOGCTRL_NWDOG_MASK ) >> \ - IRQAMP_WDOGCTRL_NWDOG_SHIFT ) -#define IRQAMP_WDOGCTRL_NWDOG_SET( _reg, _val ) \ - ( ( ( _reg ) & ~IRQAMP_WDOGCTRL_NWDOG_MASK ) | \ + ( ( ( _reg ) & IRQAMP_WDOGCTRL_NWDOG_MASK ) >> IRQAMP_WDOGCTRL_NWDOG_SHIFT ) +#define IRQAMP_WDOGCTRL_NWDOG_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_WDOGCTRL_NWDOG_MASK ) | \ ( ( ( _val ) << IRQAMP_WDOGCTRL_NWDOG_SHIFT ) & \ IRQAMP_WDOGCTRL_NWDOG_MASK ) ) #define IRQAMP_WDOGCTRL_NWDOG( _val ) \ - ( ( ( _val ) << IRQAMP_WDOGCTRL_NWDOG_SHIFT ) & \ - IRQAMP_WDOGCTRL_NWDOG_MASK ) + ( ( ( _val ) << IRQAMP_WDOGCTRL_NWDOG_SHIFT ) & IRQAMP_WDOGCTRL_NWDOG_MASK ) #define IRQAMP_WDOGCTRL_WDOGIRQ_SHIFT 16 -#define IRQAMP_WDOGCTRL_WDOGIRQ_MASK 0xf0000U -#define IRQAMP_WDOGCTRL_WDOGIRQ_GET( _reg ) \ +#define IRQAMP_WDOGCTRL_WDOGIRQ_MASK 0xf0000U +#define IRQAMP_WDOGCTRL_WDOGIRQ_GET( _reg ) \ ( ( ( _reg ) & IRQAMP_WDOGCTRL_WDOGIRQ_MASK ) >> \ IRQAMP_WDOGCTRL_WDOGIRQ_SHIFT ) -#define IRQAMP_WDOGCTRL_WDOGIRQ_SET( _reg, _val ) \ - ( ( ( _reg ) & ~IRQAMP_WDOGCTRL_WDOGIRQ_MASK ) | \ +#define IRQAMP_WDOGCTRL_WDOGIRQ_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_WDOGCTRL_WDOGIRQ_MASK ) | \ ( ( ( _val ) << IRQAMP_WDOGCTRL_WDOGIRQ_SHIFT ) & \ IRQAMP_WDOGCTRL_WDOGIRQ_MASK ) ) -#define IRQAMP_WDOGCTRL_WDOGIRQ( _val ) \ +#define IRQAMP_WDOGCTRL_WDOGIRQ( _val ) \ ( ( ( _val ) << IRQAMP_WDOGCTRL_WDOGIRQ_SHIFT ) & \ IRQAMP_WDOGCTRL_WDOGIRQ_MASK ) #define IRQAMP_WDOGCTRL_WDOGMSK_SHIFT 0 -#define IRQAMP_WDOGCTRL_WDOGMSK_MASK 0xfU -#define IRQAMP_WDOGCTRL_WDOGMSK_GET( _reg ) \ +#define IRQAMP_WDOGCTRL_WDOGMSK_MASK 0xfU +#define IRQAMP_WDOGCTRL_WDOGMSK_GET( _reg ) \ ( ( ( _reg ) & IRQAMP_WDOGCTRL_WDOGMSK_MASK ) >> \ IRQAMP_WDOGCTRL_WDOGMSK_SHIFT ) -#define IRQAMP_WDOGCTRL_WDOGMSK_SET( _reg, _val ) \ - ( ( ( _reg ) & ~IRQAMP_WDOGCTRL_WDOGMSK_MASK ) | \ +#define IRQAMP_WDOGCTRL_WDOGMSK_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_WDOGCTRL_WDOGMSK_MASK ) | \ ( ( ( _val ) << IRQAMP_WDOGCTRL_WDOGMSK_SHIFT ) & \ IRQAMP_WDOGCTRL_WDOGMSK_MASK ) ) -#define IRQAMP_WDOGCTRL_WDOGMSK( _val ) \ +#define IRQAMP_WDOGCTRL_WDOGMSK( _val ) \ ( ( ( _val ) << IRQAMP_WDOGCTRL_WDOGMSK_SHIFT ) & \ IRQAMP_WDOGCTRL_WDOGMSK_MASK ) @@ -507,17 +482,15 @@ typedef struct irqamp_timestamp { */ #define IRQAMP_ASMPCTRL_NCTRL_SHIFT 28 -#define IRQAMP_ASMPCTRL_NCTRL_MASK 0xf0000000U +#define IRQAMP_ASMPCTRL_NCTRL_MASK 0xf0000000U #define IRQAMP_ASMPCTRL_NCTRL_GET( _reg ) \ - ( ( ( _reg ) & IRQAMP_ASMPCTRL_NCTRL_MASK ) >> \ - IRQAMP_ASMPCTRL_NCTRL_SHIFT ) -#define IRQAMP_ASMPCTRL_NCTRL_SET( _reg, _val ) \ - ( ( ( _reg ) & ~IRQAMP_ASMPCTRL_NCTRL_MASK ) | \ + ( ( ( _reg ) & IRQAMP_ASMPCTRL_NCTRL_MASK ) >> IRQAMP_ASMPCTRL_NCTRL_SHIFT ) +#define IRQAMP_ASMPCTRL_NCTRL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_ASMPCTRL_NCTRL_MASK ) | \ ( ( ( _val ) << IRQAMP_ASMPCTRL_NCTRL_SHIFT ) & \ IRQAMP_ASMPCTRL_NCTRL_MASK ) ) #define IRQAMP_ASMPCTRL_NCTRL( _val ) \ - ( ( ( _val ) << IRQAMP_ASMPCTRL_NCTRL_SHIFT ) & \ - IRQAMP_ASMPCTRL_NCTRL_MASK ) + ( ( ( _val ) << IRQAMP_ASMPCTRL_NCTRL_SHIFT ) & IRQAMP_ASMPCTRL_NCTRL_MASK ) #define IRQAMP_ASMPCTRL_ICF 0x2U @@ -535,56 +508,48 @@ typedef struct irqamp_timestamp { */ #define IRQAMP_ICSELR_ICSEL0_SHIFT 28 -#define IRQAMP_ICSELR_ICSEL0_MASK 0xf0000000U +#define IRQAMP_ICSELR_ICSEL0_MASK 0xf0000000U #define IRQAMP_ICSELR_ICSEL0_GET( _reg ) \ - ( ( ( _reg ) & IRQAMP_ICSELR_ICSEL0_MASK ) >> \ - IRQAMP_ICSELR_ICSEL0_SHIFT ) -#define IRQAMP_ICSELR_ICSEL0_SET( _reg, _val ) \ - ( ( ( _reg ) & ~IRQAMP_ICSELR_ICSEL0_MASK ) | \ + ( ( ( _reg ) & IRQAMP_ICSELR_ICSEL0_MASK ) >> IRQAMP_ICSELR_ICSEL0_SHIFT ) +#define IRQAMP_ICSELR_ICSEL0_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_ICSELR_ICSEL0_MASK ) | \ ( ( ( _val ) << IRQAMP_ICSELR_ICSEL0_SHIFT ) & \ IRQAMP_ICSELR_ICSEL0_MASK ) ) #define IRQAMP_ICSELR_ICSEL0( _val ) \ - ( ( ( _val ) << IRQAMP_ICSELR_ICSEL0_SHIFT ) & \ - IRQAMP_ICSELR_ICSEL0_MASK ) + ( ( ( _val ) << IRQAMP_ICSELR_ICSEL0_SHIFT ) & IRQAMP_ICSELR_ICSEL0_MASK ) #define IRQAMP_ICSELR_ICSEL1_SHIFT 24 -#define IRQAMP_ICSELR_ICSEL1_MASK 0xf000000U +#define IRQAMP_ICSELR_ICSEL1_MASK 0xf000000U #define IRQAMP_ICSELR_ICSEL1_GET( _reg ) \ - ( ( ( _reg ) & IRQAMP_ICSELR_ICSEL1_MASK ) >> \ - IRQAMP_ICSELR_ICSEL1_SHIFT ) -#define IRQAMP_ICSELR_ICSEL1_SET( _reg, _val ) \ - ( ( ( _reg ) & ~IRQAMP_ICSELR_ICSEL1_MASK ) | \ + ( ( ( _reg ) & IRQAMP_ICSELR_ICSEL1_MASK ) >> IRQAMP_ICSELR_ICSEL1_SHIFT ) +#define IRQAMP_ICSELR_ICSEL1_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_ICSELR_ICSEL1_MASK ) | \ ( ( ( _val ) << IRQAMP_ICSELR_ICSEL1_SHIFT ) & \ IRQAMP_ICSELR_ICSEL1_MASK ) ) #define IRQAMP_ICSELR_ICSEL1( _val ) \ - ( ( ( _val ) << IRQAMP_ICSELR_ICSEL1_SHIFT ) & \ - IRQAMP_ICSELR_ICSEL1_MASK ) + ( ( ( _val ) << IRQAMP_ICSELR_ICSEL1_SHIFT ) & IRQAMP_ICSELR_ICSEL1_MASK ) #define IRQAMP_ICSELR_ICSEL2_SHIFT 20 -#define IRQAMP_ICSELR_ICSEL2_MASK 0xf00000U +#define IRQAMP_ICSELR_ICSEL2_MASK 0xf00000U #define IRQAMP_ICSELR_ICSEL2_GET( _reg ) \ - ( ( ( _reg ) & IRQAMP_ICSELR_ICSEL2_MASK ) >> \ - IRQAMP_ICSELR_ICSEL2_SHIFT ) -#define IRQAMP_ICSELR_ICSEL2_SET( _reg, _val ) \ - ( ( ( _reg ) & ~IRQAMP_ICSELR_ICSEL2_MASK ) | \ + ( ( ( _reg ) & IRQAMP_ICSELR_ICSEL2_MASK ) >> IRQAMP_ICSELR_ICSEL2_SHIFT ) +#define IRQAMP_ICSELR_ICSEL2_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_ICSELR_ICSEL2_MASK ) | \ ( ( ( _val ) << IRQAMP_ICSELR_ICSEL2_SHIFT ) & \ IRQAMP_ICSELR_ICSEL2_MASK ) ) #define IRQAMP_ICSELR_ICSEL2( _val ) \ - ( ( ( _val ) << IRQAMP_ICSELR_ICSEL2_SHIFT ) & \ - IRQAMP_ICSELR_ICSEL2_MASK ) + ( ( ( _val ) << IRQAMP_ICSELR_ICSEL2_SHIFT ) & IRQAMP_ICSELR_ICSEL2_MASK ) #define IRQAMP_ICSELR_ICSEL3_SHIFT 16 -#define IRQAMP_ICSELR_ICSEL3_MASK 0xf0000U +#define IRQAMP_ICSELR_ICSEL3_MASK 0xf0000U #define IRQAMP_ICSELR_ICSEL3_GET( _reg ) \ - ( ( ( _reg ) & IRQAMP_ICSELR_ICSEL3_MASK ) >> \ - IRQAMP_ICSELR_ICSEL3_SHIFT ) -#define IRQAMP_ICSELR_ICSEL3_SET( _reg, _val ) \ - ( ( ( _reg ) & ~IRQAMP_ICSELR_ICSEL3_MASK ) | \ + ( ( ( _reg ) & IRQAMP_ICSELR_ICSEL3_MASK ) >> IRQAMP_ICSELR_ICSEL3_SHIFT ) +#define IRQAMP_ICSELR_ICSEL3_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_ICSELR_ICSEL3_MASK ) | \ ( ( ( _val ) << IRQAMP_ICSELR_ICSEL3_SHIFT ) & \ IRQAMP_ICSELR_ICSEL3_MASK ) ) #define IRQAMP_ICSELR_ICSEL3( _val ) \ - ( ( ( _val ) << IRQAMP_ICSELR_ICSEL3_SHIFT ) & \ - IRQAMP_ICSELR_ICSEL3_MASK ) + ( ( ( _val ) << IRQAMP_ICSELR_ICSEL3_SHIFT ) & IRQAMP_ICSELR_ICSEL3_MASK ) /** @} */ @@ -598,30 +563,28 @@ typedef struct irqamp_timestamp { */ #define IRQAMP_PIMASK_EIM_31_16_SHIFT 16 -#define IRQAMP_PIMASK_EIM_31_16_MASK 0xffff0000U -#define IRQAMP_PIMASK_EIM_31_16_GET( _reg ) \ +#define IRQAMP_PIMASK_EIM_31_16_MASK 0xffff0000U +#define IRQAMP_PIMASK_EIM_31_16_GET( _reg ) \ ( ( ( _reg ) & IRQAMP_PIMASK_EIM_31_16_MASK ) >> \ IRQAMP_PIMASK_EIM_31_16_SHIFT ) -#define IRQAMP_PIMASK_EIM_31_16_SET( _reg, _val ) \ - ( ( ( _reg ) & ~IRQAMP_PIMASK_EIM_31_16_MASK ) | \ +#define IRQAMP_PIMASK_EIM_31_16_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_PIMASK_EIM_31_16_MASK ) | \ ( ( ( _val ) << IRQAMP_PIMASK_EIM_31_16_SHIFT ) & \ IRQAMP_PIMASK_EIM_31_16_MASK ) ) -#define IRQAMP_PIMASK_EIM_31_16( _val ) \ +#define IRQAMP_PIMASK_EIM_31_16( _val ) \ ( ( ( _val ) << IRQAMP_PIMASK_EIM_31_16_SHIFT ) & \ IRQAMP_PIMASK_EIM_31_16_MASK ) #define IRQAMP_PIMASK_IM15_1_SHIFT 1 -#define IRQAMP_PIMASK_IM15_1_MASK 0xfffeU +#define IRQAMP_PIMASK_IM15_1_MASK 0xfffeU #define IRQAMP_PIMASK_IM15_1_GET( _reg ) \ - ( ( ( _reg ) & IRQAMP_PIMASK_IM15_1_MASK ) >> \ - IRQAMP_PIMASK_IM15_1_SHIFT ) -#define IRQAMP_PIMASK_IM15_1_SET( _reg, _val ) \ - ( ( ( _reg ) & ~IRQAMP_PIMASK_IM15_1_MASK ) | \ + ( ( ( _reg ) & IRQAMP_PIMASK_IM15_1_MASK ) >> IRQAMP_PIMASK_IM15_1_SHIFT ) +#define IRQAMP_PIMASK_IM15_1_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_PIMASK_IM15_1_MASK ) | \ ( ( ( _val ) << IRQAMP_PIMASK_IM15_1_SHIFT ) & \ IRQAMP_PIMASK_IM15_1_MASK ) ) #define IRQAMP_PIMASK_IM15_1( _val ) \ - ( ( ( _val ) << IRQAMP_PIMASK_IM15_1_SHIFT ) & \ - IRQAMP_PIMASK_IM15_1_MASK ) + ( ( ( _val ) << IRQAMP_PIMASK_IM15_1_SHIFT ) & IRQAMP_PIMASK_IM15_1_MASK ) /** @} */ @@ -635,30 +598,28 @@ typedef struct irqamp_timestamp { */ #define IRQAMP_PIFORCE_FC_15_1_SHIFT 17 -#define IRQAMP_PIFORCE_FC_15_1_MASK 0xfffe0000U -#define IRQAMP_PIFORCE_FC_15_1_GET( _reg ) \ +#define IRQAMP_PIFORCE_FC_15_1_MASK 0xfffe0000U +#define IRQAMP_PIFORCE_FC_15_1_GET( _reg ) \ ( ( ( _reg ) & IRQAMP_PIFORCE_FC_15_1_MASK ) >> \ IRQAMP_PIFORCE_FC_15_1_SHIFT ) -#define IRQAMP_PIFORCE_FC_15_1_SET( _reg, _val ) \ - ( ( ( _reg ) & ~IRQAMP_PIFORCE_FC_15_1_MASK ) | \ +#define IRQAMP_PIFORCE_FC_15_1_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_PIFORCE_FC_15_1_MASK ) | \ ( ( ( _val ) << IRQAMP_PIFORCE_FC_15_1_SHIFT ) & \ IRQAMP_PIFORCE_FC_15_1_MASK ) ) -#define IRQAMP_PIFORCE_FC_15_1( _val ) \ +#define IRQAMP_PIFORCE_FC_15_1( _val ) \ ( ( ( _val ) << IRQAMP_PIFORCE_FC_15_1_SHIFT ) & \ IRQAMP_PIFORCE_FC_15_1_MASK ) #define IRQAMP_PIFORCE_IF15_1_SHIFT 1 -#define IRQAMP_PIFORCE_IF15_1_MASK 0xfffeU +#define IRQAMP_PIFORCE_IF15_1_MASK 0xfffeU #define IRQAMP_PIFORCE_IF15_1_GET( _reg ) \ - ( ( ( _reg ) & IRQAMP_PIFORCE_IF15_1_MASK ) >> \ - IRQAMP_PIFORCE_IF15_1_SHIFT ) -#define IRQAMP_PIFORCE_IF15_1_SET( _reg, _val ) \ - ( ( ( _reg ) & ~IRQAMP_PIFORCE_IF15_1_MASK ) | \ + ( ( ( _reg ) & IRQAMP_PIFORCE_IF15_1_MASK ) >> IRQAMP_PIFORCE_IF15_1_SHIFT ) +#define IRQAMP_PIFORCE_IF15_1_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_PIFORCE_IF15_1_MASK ) | \ ( ( ( _val ) << IRQAMP_PIFORCE_IF15_1_SHIFT ) & \ IRQAMP_PIFORCE_IF15_1_MASK ) ) #define IRQAMP_PIFORCE_IF15_1( _val ) \ - ( ( ( _val ) << IRQAMP_PIFORCE_IF15_1_SHIFT ) & \ - IRQAMP_PIFORCE_IF15_1_MASK ) + ( ( ( _val ) << IRQAMP_PIFORCE_IF15_1_SHIFT ) & IRQAMP_PIFORCE_IF15_1_MASK ) /** @} */ @@ -672,15 +633,15 @@ typedef struct irqamp_timestamp { */ #define IRQAMP_PEXTACK_EID_4_0_SHIFT 0 -#define IRQAMP_PEXTACK_EID_4_0_MASK 0x1fU -#define IRQAMP_PEXTACK_EID_4_0_GET( _reg ) \ +#define IRQAMP_PEXTACK_EID_4_0_MASK 0x1fU +#define IRQAMP_PEXTACK_EID_4_0_GET( _reg ) \ ( ( ( _reg ) & IRQAMP_PEXTACK_EID_4_0_MASK ) >> \ IRQAMP_PEXTACK_EID_4_0_SHIFT ) -#define IRQAMP_PEXTACK_EID_4_0_SET( _reg, _val ) \ - ( ( ( _reg ) & ~IRQAMP_PEXTACK_EID_4_0_MASK ) | \ +#define IRQAMP_PEXTACK_EID_4_0_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_PEXTACK_EID_4_0_MASK ) | \ ( ( ( _val ) << IRQAMP_PEXTACK_EID_4_0_SHIFT ) & \ IRQAMP_PEXTACK_EID_4_0_MASK ) ) -#define IRQAMP_PEXTACK_EID_4_0( _val ) \ +#define IRQAMP_PEXTACK_EID_4_0( _val ) \ ( ( ( _val ) << IRQAMP_PEXTACK_EID_4_0_SHIFT ) & \ IRQAMP_PEXTACK_EID_4_0_MASK ) @@ -696,15 +657,15 @@ typedef struct irqamp_timestamp { */ #define IRQAMP_BADDR_BOOTADDR_31_3_SHIFT 3 -#define IRQAMP_BADDR_BOOTADDR_31_3_MASK 0xfffffff8U -#define IRQAMP_BADDR_BOOTADDR_31_3_GET( _reg ) \ +#define IRQAMP_BADDR_BOOTADDR_31_3_MASK 0xfffffff8U +#define IRQAMP_BADDR_BOOTADDR_31_3_GET( _reg ) \ ( ( ( _reg ) & IRQAMP_BADDR_BOOTADDR_31_3_MASK ) >> \ IRQAMP_BADDR_BOOTADDR_31_3_SHIFT ) -#define IRQAMP_BADDR_BOOTADDR_31_3_SET( _reg, _val ) \ - ( ( ( _reg ) & ~IRQAMP_BADDR_BOOTADDR_31_3_MASK ) | \ +#define IRQAMP_BADDR_BOOTADDR_31_3_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_BADDR_BOOTADDR_31_3_MASK ) | \ ( ( ( _val ) << IRQAMP_BADDR_BOOTADDR_31_3_SHIFT ) & \ IRQAMP_BADDR_BOOTADDR_31_3_MASK ) ) -#define IRQAMP_BADDR_BOOTADDR_31_3( _val ) \ +#define IRQAMP_BADDR_BOOTADDR_31_3( _val ) \ ( ( ( _val ) << IRQAMP_BADDR_BOOTADDR_31_3_SHIFT ) & \ IRQAMP_BADDR_BOOTADDR_31_3_MASK ) @@ -721,54 +682,54 @@ typedef struct irqamp_timestamp { */ #define IRQAMP_IRQMAP_IRQMAP_4_N_0_SHIFT 24 -#define IRQAMP_IRQMAP_IRQMAP_4_N_0_MASK 0xff000000U -#define IRQAMP_IRQMAP_IRQMAP_4_N_0_GET( _reg ) \ +#define IRQAMP_IRQMAP_IRQMAP_4_N_0_MASK 0xff000000U +#define IRQAMP_IRQMAP_IRQMAP_4_N_0_GET( _reg ) \ ( ( ( _reg ) & IRQAMP_IRQMAP_IRQMAP_4_N_0_MASK ) >> \ IRQAMP_IRQMAP_IRQMAP_4_N_0_SHIFT ) -#define IRQAMP_IRQMAP_IRQMAP_4_N_0_SET( _reg, _val ) \ - ( ( ( _reg ) & ~IRQAMP_IRQMAP_IRQMAP_4_N_0_MASK ) | \ +#define IRQAMP_IRQMAP_IRQMAP_4_N_0_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_IRQMAP_IRQMAP_4_N_0_MASK ) | \ ( ( ( _val ) << IRQAMP_IRQMAP_IRQMAP_4_N_0_SHIFT ) & \ IRQAMP_IRQMAP_IRQMAP_4_N_0_MASK ) ) -#define IRQAMP_IRQMAP_IRQMAP_4_N_0( _val ) \ +#define IRQAMP_IRQMAP_IRQMAP_4_N_0( _val ) \ ( ( ( _val ) << IRQAMP_IRQMAP_IRQMAP_4_N_0_SHIFT ) & \ IRQAMP_IRQMAP_IRQMAP_4_N_0_MASK ) #define IRQAMP_IRQMAP_IRQMAP_4_N_1_SHIFT 16 -#define IRQAMP_IRQMAP_IRQMAP_4_N_1_MASK 0xff0000U -#define IRQAMP_IRQMAP_IRQMAP_4_N_1_GET( _reg ) \ +#define IRQAMP_IRQMAP_IRQMAP_4_N_1_MASK 0xff0000U +#define IRQAMP_IRQMAP_IRQMAP_4_N_1_GET( _reg ) \ ( ( ( _reg ) & IRQAMP_IRQMAP_IRQMAP_4_N_1_MASK ) >> \ IRQAMP_IRQMAP_IRQMAP_4_N_1_SHIFT ) -#define IRQAMP_IRQMAP_IRQMAP_4_N_1_SET( _reg, _val ) \ - ( ( ( _reg ) & ~IRQAMP_IRQMAP_IRQMAP_4_N_1_MASK ) | \ +#define IRQAMP_IRQMAP_IRQMAP_4_N_1_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_IRQMAP_IRQMAP_4_N_1_MASK ) | \ ( ( ( _val ) << IRQAMP_IRQMAP_IRQMAP_4_N_1_SHIFT ) & \ IRQAMP_IRQMAP_IRQMAP_4_N_1_MASK ) ) -#define IRQAMP_IRQMAP_IRQMAP_4_N_1( _val ) \ +#define IRQAMP_IRQMAP_IRQMAP_4_N_1( _val ) \ ( ( ( _val ) << IRQAMP_IRQMAP_IRQMAP_4_N_1_SHIFT ) & \ IRQAMP_IRQMAP_IRQMAP_4_N_1_MASK ) #define IRQAMP_IRQMAP_IRQMAP_4_N_2_SHIFT 8 -#define IRQAMP_IRQMAP_IRQMAP_4_N_2_MASK 0xff00U -#define IRQAMP_IRQMAP_IRQMAP_4_N_2_GET( _reg ) \ +#define IRQAMP_IRQMAP_IRQMAP_4_N_2_MASK 0xff00U +#define IRQAMP_IRQMAP_IRQMAP_4_N_2_GET( _reg ) \ ( ( ( _reg ) & IRQAMP_IRQMAP_IRQMAP_4_N_2_MASK ) >> \ IRQAMP_IRQMAP_IRQMAP_4_N_2_SHIFT ) -#define IRQAMP_IRQMAP_IRQMAP_4_N_2_SET( _reg, _val ) \ - ( ( ( _reg ) & ~IRQAMP_IRQMAP_IRQMAP_4_N_2_MASK ) | \ +#define IRQAMP_IRQMAP_IRQMAP_4_N_2_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_IRQMAP_IRQMAP_4_N_2_MASK ) | \ ( ( ( _val ) << IRQAMP_IRQMAP_IRQMAP_4_N_2_SHIFT ) & \ IRQAMP_IRQMAP_IRQMAP_4_N_2_MASK ) ) -#define IRQAMP_IRQMAP_IRQMAP_4_N_2( _val ) \ +#define IRQAMP_IRQMAP_IRQMAP_4_N_2( _val ) \ ( ( ( _val ) << IRQAMP_IRQMAP_IRQMAP_4_N_2_SHIFT ) & \ IRQAMP_IRQMAP_IRQMAP_4_N_2_MASK ) #define IRQAMP_IRQMAP_IRQMAP_4_N_3_SHIFT 0 -#define IRQAMP_IRQMAP_IRQMAP_4_N_3_MASK 0xffU -#define IRQAMP_IRQMAP_IRQMAP_4_N_3_GET( _reg ) \ +#define IRQAMP_IRQMAP_IRQMAP_4_N_3_MASK 0xffU +#define IRQAMP_IRQMAP_IRQMAP_4_N_3_GET( _reg ) \ ( ( ( _reg ) & IRQAMP_IRQMAP_IRQMAP_4_N_3_MASK ) >> \ IRQAMP_IRQMAP_IRQMAP_4_N_3_SHIFT ) -#define IRQAMP_IRQMAP_IRQMAP_4_N_3_SET( _reg, _val ) \ - ( ( ( _reg ) & ~IRQAMP_IRQMAP_IRQMAP_4_N_3_MASK ) | \ +#define IRQAMP_IRQMAP_IRQMAP_4_N_3_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_IRQMAP_IRQMAP_4_N_3_MASK ) | \ ( ( ( _val ) << IRQAMP_IRQMAP_IRQMAP_4_N_3_SHIFT ) & \ IRQAMP_IRQMAP_IRQMAP_4_N_3_MASK ) ) -#define IRQAMP_IRQMAP_IRQMAP_4_N_3( _val ) \ +#define IRQAMP_IRQMAP_IRQMAP_4_N_3( _val ) \ ( ( ( _val ) << IRQAMP_IRQMAP_IRQMAP_4_N_3_SHIFT ) & \ IRQAMP_IRQMAP_IRQMAP_4_N_3_MASK ) diff --git a/bsps/include/grlib/irqamp.h b/bsps/include/grlib/irqamp.h index dd7c5235f0..ade1691275 100644 --- a/bsps/include/grlib/irqamp.h +++ b/bsps/include/grlib/irqamp.h @@ -82,7 +82,7 @@ static inline irqamp_timestamp *irqamp_get_timestamp_registers( ) { irqamp_timestamp *timestamp_regs; - uint32_t itstmpc; + uint32_t itstmpc; timestamp_regs = &irqamp_regs->itstmp[ 0 ]; itstmpc = grlib_load_32( ×tamp_regs->itstmpc ); diff --git a/bsps/include/grlib/l2c.h b/bsps/include/grlib/l2c.h index 2867d5bca5..9176aa26a2 100644 --- a/bsps/include/grlib/l2c.h +++ b/bsps/include/grlib/l2c.h @@ -43,118 +43,132 @@ extern "C" { #endif -extern void l2cache_register_drv(void); +extern void l2cache_register_drv( void ); -#define L2CACHE_ERR_OK 0 -#define L2CACHE_ERR_NOINIT -1 -#define L2CACHE_ERR_EINVAL -2 +#define L2CACHE_ERR_OK 0 +#define L2CACHE_ERR_NOINIT -1 +#define L2CACHE_ERR_EINVAL -2 #define L2CACHE_ERR_TOOMANY -3 -#define L2CACHE_ERR_ERROR -4 +#define L2CACHE_ERR_ERROR -4 /* L2C Flush options */ -#define L2CACHE_OPTIONS_FLUSH_WAIT (0x1 << 2) -#define L2CACHE_OPTIONS_FLUSH_INVALIDATE (0x3 << 0) -#define L2CACHE_OPTIONS_FLUSH_WRITEBACK (0x2 << 0) -#define L2CACHE_OPTIONS_FLUSH_INV_WBACK (0x1 << 0) -#define L2CACHE_OPTIONS_FLUSH_NONE (0 << 0) +#define L2CACHE_OPTIONS_FLUSH_WAIT ( 0x1 << 2 ) +#define L2CACHE_OPTIONS_FLUSH_INVALIDATE ( 0x3 << 0 ) +#define L2CACHE_OPTIONS_FLUSH_WRITEBACK ( 0x2 << 0 ) +#define L2CACHE_OPTIONS_FLUSH_INV_WBACK ( 0x1 << 0 ) +#define L2CACHE_OPTIONS_FLUSH_NONE ( 0 << 0 ) /* L2C Status */ -#define L2CACHE_STATUS_ENABLED 1 -#define L2CACHE_STATUS_SPLIT_ENABLED (0x1 << 1) -#define L2CACHE_STATUS_EDAC_ENABLED (0x1 << 2) -#define L2CACHE_STATUS_REPL (0x3 << L2CACHE_STATUS_REPL_BIT) -#define L2CACHE_STATUS_REPL_BIT 3 -#define L2CACHE_STATUS_WRITETHROUGH (0x1 << 5) -#define L2CACHE_STATUS_LOCK (0xf << L2CACHE_STATUS_LOCK_BIT) -#define L2CACHE_STATUS_LOCK_BIT 6 -#define L2CACHE_STATUS_SCRUB_ENABLED (0x1 << 10) -#define L2CACHE_STATUS_INT (0xf << L2CACHE_STATUS_INT_BIT) -#define L2CACHE_STATUS_INT_BIT 11 -#define L2CACHE_STATUS_INT_BCKEND (0x1 << 11) -#define L2CACHE_STATUS_INT_WPHIT (0x1 << 12) -#define L2CACHE_STATUS_INT_UEE (0x1 << 13) -#define L2CACHE_STATUS_INT_CEE (0x1 << 14) -#define L2CACHE_STATUS_SCRUB_DELAY (0xffff << L2CACHE_STATUS_SCRUB_DELAY_BIT) +#define L2CACHE_STATUS_ENABLED 1 +#define L2CACHE_STATUS_SPLIT_ENABLED ( 0x1 << 1 ) +#define L2CACHE_STATUS_EDAC_ENABLED ( 0x1 << 2 ) +#define L2CACHE_STATUS_REPL ( 0x3 << L2CACHE_STATUS_REPL_BIT ) +#define L2CACHE_STATUS_REPL_BIT 3 +#define L2CACHE_STATUS_WRITETHROUGH ( 0x1 << 5 ) +#define L2CACHE_STATUS_LOCK ( 0xf << L2CACHE_STATUS_LOCK_BIT ) +#define L2CACHE_STATUS_LOCK_BIT 6 +#define L2CACHE_STATUS_SCRUB_ENABLED ( 0x1 << 10 ) +#define L2CACHE_STATUS_INT ( 0xf << L2CACHE_STATUS_INT_BIT ) +#define L2CACHE_STATUS_INT_BIT 11 +#define L2CACHE_STATUS_INT_BCKEND ( 0x1 << 11 ) +#define L2CACHE_STATUS_INT_WPHIT ( 0x1 << 12 ) +#define L2CACHE_STATUS_INT_UEE ( 0x1 << 13 ) +#define L2CACHE_STATUS_INT_CEE ( 0x1 << 14 ) +#define L2CACHE_STATUS_SCRUB_DELAY ( 0xffff << L2CACHE_STATUS_SCRUB_DELAY_BIT ) #define L2CACHE_STATUS_SCRUB_DELAY_BIT 15 -#define L2CACHE_STATUS_SIGN_BIT 31 +#define L2CACHE_STATUS_SIGN_BIT 31 /* status helper macros */ -#define L2CACHE_ENABLED(status) (status & L2CACHE_STATUS_ENABLED) -#define L2CACHE_DISABLED(status) (!(status & L2CACHE_STATUS_ENABLED)) -#define L2CACHE_SPLIT_ENABLED(status) (status & L2CACHE_STATUS_SPLIT_ENABLED) -#define L2CACHE_SPLIT_DISABLED(status) \ - (!(status & L2CACHE_STATUS_SPLIT_ENABLED)) -#define L2CACHE_EDAC_ENABLED(status) (status & L2CACHE_STATUS_EDAC_ENABLED) -#define L2CACHE_EDAC_DISABLED(status) (!(status & L2CACHE_STATUS_EDAC_ENABLED)) -#define L2CACHE_REPL(status) \ - ((status & L2CACHE_STATUS_REPL) >> L2CACHE_STATUS_REPL_BIT) -#define L2CACHE_WRITETHROUGH(status) (status & L2CACHE_STATUS_WRITETHROUGH) -#define L2CACHE_WRITEBACK(status) (!(status & L2CACHE_STATUS_WRITETHROUGH)) -#define L2CACHE_LOCKED_WAYS(status) \ - ((status & L2CACHE_STATUS_LOCK) >> L2CACHE_STATUS_LOCK_BIT) -#define L2CACHE_SCRUB_ENABLED(status) (status & L2CACHE_STATUS_SCRUB_ENABLED) -#define L2CACHE_SCRUB_DISABLED(status) \ - (!(status & L2CACHE_STATUS_SCRUB_ENABLED)) -#define L2CACHE_SCRUB_DELAY(status) \ - ((status & L2CACHE_STATUS_SCRUB_DELAY) >> L2CACHE_STATUS_SCRUB_DELAY_BIT) -#define L2CACHE_INT_ENABLED(status) (status & L2CACHE_STATUS_INT) -#define L2CACHE_INT_DISABLED(status) (!(status & L2CACHE_STATUS_INT)) -extern int l2cache_status(void); +#define L2CACHE_ENABLED( status ) ( status & L2CACHE_STATUS_ENABLED ) +#define L2CACHE_DISABLED( status ) ( !( status & L2CACHE_STATUS_ENABLED ) ) +#define L2CACHE_SPLIT_ENABLED( status ) \ + ( status & L2CACHE_STATUS_SPLIT_ENABLED ) +#define L2CACHE_SPLIT_DISABLED( status ) \ + ( !( status & L2CACHE_STATUS_SPLIT_ENABLED ) ) +#define L2CACHE_EDAC_ENABLED( status ) ( status & L2CACHE_STATUS_EDAC_ENABLED ) +#define L2CACHE_EDAC_DISABLED( status ) \ + ( !( status & L2CACHE_STATUS_EDAC_ENABLED ) ) +#define L2CACHE_REPL( status ) \ + ( ( status & L2CACHE_STATUS_REPL ) >> L2CACHE_STATUS_REPL_BIT ) +#define L2CACHE_WRITETHROUGH( status ) ( status & L2CACHE_STATUS_WRITETHROUGH ) +#define L2CACHE_WRITEBACK( status ) \ + ( !( status & L2CACHE_STATUS_WRITETHROUGH ) ) +#define L2CACHE_LOCKED_WAYS( status ) \ + ( ( status & L2CACHE_STATUS_LOCK ) >> L2CACHE_STATUS_LOCK_BIT ) +#define L2CACHE_SCRUB_ENABLED( status ) \ + ( status & L2CACHE_STATUS_SCRUB_ENABLED ) +#define L2CACHE_SCRUB_DISABLED( status ) \ + ( !( status & L2CACHE_STATUS_SCRUB_ENABLED ) ) +#define L2CACHE_SCRUB_DELAY( status ) \ + ( ( status & L2CACHE_STATUS_SCRUB_DELAY ) >> L2CACHE_STATUS_SCRUB_DELAY_BIT ) +#define L2CACHE_INT_ENABLED( status ) ( status & L2CACHE_STATUS_INT ) +#define L2CACHE_INT_DISABLED( status ) ( !( status & L2CACHE_STATUS_INT ) ) +extern int l2cache_status( void ); /* L2C Setup */ -extern int l2cache_enable(int flush); -extern int l2cache_disable(int flush); +extern int l2cache_enable( int flush ); +extern int l2cache_disable( int flush ); -extern int l2cache_split_enable(void); -extern int l2cache_split_disable(void); +extern int l2cache_split_enable( void ); +extern int l2cache_split_disable( void ); -extern int l2cache_edac_enable(int flush); -extern int l2cache_edac_disable(int flush); +extern int l2cache_edac_enable( int flush ); +extern int l2cache_edac_disable( int flush ); -extern int l2cache_scrub_enable(int delay); -extern int l2cache_scrub_disable(void); -extern int l2cache_scrub_line(int way, int index); +extern int l2cache_scrub_enable( int delay ); +extern int l2cache_scrub_disable( void ); +extern int l2cache_scrub_line( int way, int index ); -extern int l2cache_writethrough(int flush); -extern int l2cache_writeback(int flush); +extern int l2cache_writethrough( int flush ); +extern int l2cache_writeback( int flush ); -#define L2CACHE_OPTIONS_REPL_INDEX_WAY_BIT (2) -#define L2CACHE_OPTIONS_REPL_MASTERIDX_MOD (3 << 0) -#define L2CACHE_OPTIONS_REPL_MASTERIDX_IDX (2 << 0) -#define L2CACHE_OPTIONS_REPL_RANDOM (1 << 0) -#define L2CACHE_OPTIONS_REPL_LRU (0 << 0) -extern int l2cache_replacement(int options, int flush); +#define L2CACHE_OPTIONS_REPL_INDEX_WAY_BIT ( 2 ) +#define L2CACHE_OPTIONS_REPL_MASTERIDX_MOD ( 3 << 0 ) +#define L2CACHE_OPTIONS_REPL_MASTERIDX_IDX ( 2 << 0 ) +#define L2CACHE_OPTIONS_REPL_RANDOM ( 1 << 0 ) +#define L2CACHE_OPTIONS_REPL_LRU ( 0 << 0 ) +extern int l2cache_replacement( int options, int flush ); /* L2C Flush */ -extern int l2cache_flush(int flush); -extern int l2cache_flush_address(uint32_t addr, int size, int flush); -extern int l2cache_flush_line(int way, int index, int flush); -extern int l2cache_flush_way(int way, int flush); +extern int l2cache_flush( int flush ); +extern int l2cache_flush_address( uint32_t addr, int size, int flush ); +extern int l2cache_flush_line( int way, int index, int flush ); +extern int l2cache_flush_way( int way, int flush ); /* L2C Lock way */ -#define L2CACHE_OPTIONS_DIRTY (0x1 << 2) -#define L2CACHE_OPTIONS_VALID (0x1 << 1) -#define L2CACHE_OPTIONS_FETCH (0x1 << 0) +#define L2CACHE_OPTIONS_DIRTY ( 0x1 << 2 ) +#define L2CACHE_OPTIONS_VALID ( 0x1 << 1 ) +#define L2CACHE_OPTIONS_FETCH ( 0x1 << 0 ) #define L2CACHE_OPTIONS_DISABLE 2 -#define L2CACHE_OPTIONS_ENABLE 1 -#define L2CACHE_OPTIONS_NONE 0 -extern int l2cache_lock_way(uint32_t tag, int options, int flush, int enable); -extern int l2cache_unlock(void); +#define L2CACHE_OPTIONS_ENABLE 1 +#define L2CACHE_OPTIONS_NONE 0 +extern int l2cache_lock_way( + uint32_t tag, + int options, + int flush, + int enable +); +extern int l2cache_unlock( void ); /* L2C Fill a way */ -extern int l2cache_fill_way(int way, uint32_t tag, int options, int flush); +extern int l2cache_fill_way( int way, uint32_t tag, int options, int flush ); /* L2C MTRR */ -#define L2CACHE_OPTIONS_MTRR_ACCESS_WRITETHROUGH (0x1 << 2) -#define L2CACHE_OPTIONS_MTRR_ACCESS_UNCACHED (0x0 << 2) -#define L2CACHE_OPTIONS_MTRR_WRITEPROT_ENABLE (0x1 << 1) -#define L2CACHE_OPTIONS_MTRR_WRITEPROT_DISABLE (0x0 << 1) -extern int l2cache_mtrr_enable(int id, uint32_t addr, uint32_t mask, - int options, int flush); -extern int l2cache_mtrr_disable(int id); +#define L2CACHE_OPTIONS_MTRR_ACCESS_WRITETHROUGH ( 0x1 << 2 ) +#define L2CACHE_OPTIONS_MTRR_ACCESS_UNCACHED ( 0x0 << 2 ) +#define L2CACHE_OPTIONS_MTRR_WRITEPROT_ENABLE ( 0x1 << 1 ) +#define L2CACHE_OPTIONS_MTRR_WRITEPROT_DISABLE ( 0x0 << 1 ) +extern int l2cache_mtrr_enable( + int id, + uint32_t addr, + uint32_t mask, + int options, + int flush +); +extern int l2cache_mtrr_disable( int id ); /* L2C Debug print */ -extern int l2cache_print(void); +extern int l2cache_print( void ); /* L2C Interrupts */ /* Function Interrupt-Code ISR callback prototype. @@ -162,22 +176,22 @@ extern int l2cache_print(void); * addr - Cacheline addr that generated the error * status - Error status register of the L2CACHE core */ -typedef void (*l2cache_isr_t)(void *arg, uint32_t addr, uint32_t status); -#define L2CACHE_INTERRUPT_ALL (0xf << 0) -#define L2CACHE_INTERRUPT_BACKENDERROR (0x1 << 3) -#define L2CACHE_INTERRUPT_WPROTHIT (0x1 << 2) -#define L2CACHE_INTERRUPT_UNCORRERROR (0x1 << 1) -#define L2CACHE_INTERRUPT_CORRERROR (0x1 << 0) -extern int l2cache_isr_register( l2cache_isr_t isr, void * arg, int options); -extern int l2cache_isr_unregister(void); -extern int l2cache_interrupt_mask(int options); -extern int l2cache_interrupt_unmask(int options); +typedef void ( *l2cache_isr_t )( void *arg, uint32_t addr, uint32_t status ); +#define L2CACHE_INTERRUPT_ALL ( 0xf << 0 ) +#define L2CACHE_INTERRUPT_BACKENDERROR ( 0x1 << 3 ) +#define L2CACHE_INTERRUPT_WPROTHIT ( 0x1 << 2 ) +#define L2CACHE_INTERRUPT_UNCORRERROR ( 0x1 << 1 ) +#define L2CACHE_INTERRUPT_CORRERROR ( 0x1 << 0 ) +extern int l2cache_isr_register( l2cache_isr_t isr, void *arg, int options ); +extern int l2cache_isr_unregister( void ); +extern int l2cache_interrupt_mask( int options ); +extern int l2cache_interrupt_unmask( int options ); /* L2C error interface */ #define L2CACHE_STATUS_MULTIPLEERRORS 2 -#define L2CACHE_STATUS_NEWERROR 1 -#define L2CACHE_STATUS_NOERROR 0 -extern int l2cache_error_status(uint32_t * addr, uint32_t * status); +#define L2CACHE_STATUS_NEWERROR 1 +#define L2CACHE_STATUS_NOERROR 0 +extern int l2cache_error_status( uint32_t *addr, uint32_t *status ); /*#define TEST_L2CACHE*/ #ifdef TEST_L2CACHE @@ -186,31 +200,34 @@ extern int l2cache_error_status(uint32_t * addr, uint32_t * status); * L2CACHE Tag private data struture */ struct l2cache_tag { - uint32_t tag; - int valid; - int dirty; - int lru; + uint32_t tag; + int valid; + int dirty; + int lru; }; /* * L2CACHE Line private data struture */ struct l2cache_dataline { - uint32_t data[16]; - int words; + uint32_t data[ 16 ]; + int words; }; -extern int l2cache_get_index( uint32_t addr); -extern uint32_t l2cache_get_tag( uint32_t addr); +extern int l2cache_get_index( uint32_t addr ); +extern uint32_t l2cache_get_tag( uint32_t addr ); -extern int l2cache_diag_tag( int way, int index, struct l2cache_tag * tag); -extern int l2cache_diag_line( int way, int index, - struct l2cache_dataline * dataline); +extern int l2cache_diag_tag( int way, int index, struct l2cache_tag *tag ); +extern int l2cache_diag_line( + int way, + int index, + struct l2cache_dataline *dataline +); -#define L2CACHE_HIT 1 +#define L2CACHE_HIT 1 #define L2CACHE_MISS 0 -extern int l2cache_lookup(uint32_t addr, int * way); +extern int l2cache_lookup( uint32_t addr, int *way ); -extern int l2cache_error_inject_address( uint32_t addr, uint32_t mask); +extern int l2cache_error_inject_address( uint32_t addr, uint32_t mask ); #endif /* TEST_L2CACHE */ #ifdef __cplusplus diff --git a/bsps/include/grlib/l2cache-regs.h b/bsps/include/grlib/l2cache-regs.h index 24d2e561b1..51926b1b15 100644 --- a/bsps/include/grlib/l2cache-regs.h +++ b/bsps/include/grlib/l2cache-regs.h @@ -86,56 +86,47 @@ extern "C" { #define L2CACHE_L2CC_EDAC 0x40000000U #define L2CACHE_L2CC_REPL_SHIFT 28 -#define L2CACHE_L2CC_REPL_MASK 0x30000000U +#define L2CACHE_L2CC_REPL_MASK 0x30000000U #define L2CACHE_L2CC_REPL_GET( _reg ) \ - ( ( ( _reg ) & L2CACHE_L2CC_REPL_MASK ) >> \ - L2CACHE_L2CC_REPL_SHIFT ) -#define L2CACHE_L2CC_REPL_SET( _reg, _val ) \ + ( ( ( _reg ) & L2CACHE_L2CC_REPL_MASK ) >> L2CACHE_L2CC_REPL_SHIFT ) +#define L2CACHE_L2CC_REPL_SET( _reg, _val ) \ ( ( ( _reg ) & ~L2CACHE_L2CC_REPL_MASK ) | \ - ( ( ( _val ) << L2CACHE_L2CC_REPL_SHIFT ) & \ - L2CACHE_L2CC_REPL_MASK ) ) + ( ( ( _val ) << L2CACHE_L2CC_REPL_SHIFT ) & L2CACHE_L2CC_REPL_MASK ) ) #define L2CACHE_L2CC_REPL( _val ) \ - ( ( ( _val ) << L2CACHE_L2CC_REPL_SHIFT ) & \ - L2CACHE_L2CC_REPL_MASK ) + ( ( ( _val ) << L2CACHE_L2CC_REPL_SHIFT ) & L2CACHE_L2CC_REPL_MASK ) #define L2CACHE_L2CC_BBS_SHIFT 16 -#define L2CACHE_L2CC_BBS_MASK 0x70000U +#define L2CACHE_L2CC_BBS_MASK 0x70000U #define L2CACHE_L2CC_BBS_GET( _reg ) \ - ( ( ( _reg ) & L2CACHE_L2CC_BBS_MASK ) >> \ - L2CACHE_L2CC_BBS_SHIFT ) -#define L2CACHE_L2CC_BBS_SET( _reg, _val ) \ + ( ( ( _reg ) & L2CACHE_L2CC_BBS_MASK ) >> L2CACHE_L2CC_BBS_SHIFT ) +#define L2CACHE_L2CC_BBS_SET( _reg, _val ) \ ( ( ( _reg ) & ~L2CACHE_L2CC_BBS_MASK ) | \ - ( ( ( _val ) << L2CACHE_L2CC_BBS_SHIFT ) & \ - L2CACHE_L2CC_BBS_MASK ) ) + ( ( ( _val ) << L2CACHE_L2CC_BBS_SHIFT ) & L2CACHE_L2CC_BBS_MASK ) ) #define L2CACHE_L2CC_BBS( _val ) \ - ( ( ( _val ) << L2CACHE_L2CC_BBS_SHIFT ) & \ - L2CACHE_L2CC_BBS_MASK ) + ( ( ( _val ) << L2CACHE_L2CC_BBS_SHIFT ) & L2CACHE_L2CC_BBS_MASK ) #define L2CACHE_L2CC_INDEX_WAY_SHIFT 12 -#define L2CACHE_L2CC_INDEX_WAY_MASK 0xf000U -#define L2CACHE_L2CC_INDEX_WAY_GET( _reg ) \ +#define L2CACHE_L2CC_INDEX_WAY_MASK 0xf000U +#define L2CACHE_L2CC_INDEX_WAY_GET( _reg ) \ ( ( ( _reg ) & L2CACHE_L2CC_INDEX_WAY_MASK ) >> \ L2CACHE_L2CC_INDEX_WAY_SHIFT ) -#define L2CACHE_L2CC_INDEX_WAY_SET( _reg, _val ) \ - ( ( ( _reg ) & ~L2CACHE_L2CC_INDEX_WAY_MASK ) | \ +#define L2CACHE_L2CC_INDEX_WAY_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CC_INDEX_WAY_MASK ) | \ ( ( ( _val ) << L2CACHE_L2CC_INDEX_WAY_SHIFT ) & \ L2CACHE_L2CC_INDEX_WAY_MASK ) ) -#define L2CACHE_L2CC_INDEX_WAY( _val ) \ +#define L2CACHE_L2CC_INDEX_WAY( _val ) \ ( ( ( _val ) << L2CACHE_L2CC_INDEX_WAY_SHIFT ) & \ L2CACHE_L2CC_INDEX_WAY_MASK ) #define L2CACHE_L2CC_LOCK_SHIFT 8 -#define L2CACHE_L2CC_LOCK_MASK 0xf00U +#define L2CACHE_L2CC_LOCK_MASK 0xf00U #define L2CACHE_L2CC_LOCK_GET( _reg ) \ - ( ( ( _reg ) & L2CACHE_L2CC_LOCK_MASK ) >> \ - L2CACHE_L2CC_LOCK_SHIFT ) -#define L2CACHE_L2CC_LOCK_SET( _reg, _val ) \ + ( ( ( _reg ) & L2CACHE_L2CC_LOCK_MASK ) >> L2CACHE_L2CC_LOCK_SHIFT ) +#define L2CACHE_L2CC_LOCK_SET( _reg, _val ) \ ( ( ( _reg ) & ~L2CACHE_L2CC_LOCK_MASK ) | \ - ( ( ( _val ) << L2CACHE_L2CC_LOCK_SHIFT ) & \ - L2CACHE_L2CC_LOCK_MASK ) ) + ( ( ( _val ) << L2CACHE_L2CC_LOCK_SHIFT ) & L2CACHE_L2CC_LOCK_MASK ) ) #define L2CACHE_L2CC_LOCK( _val ) \ - ( ( ( _val ) << L2CACHE_L2CC_LOCK_SHIFT ) & \ - L2CACHE_L2CC_LOCK_MASK ) + ( ( ( _val ) << L2CACHE_L2CC_LOCK_SHIFT ) & L2CACHE_L2CC_LOCK_MASK ) #define L2CACHE_L2CC_HPRHB 0x20U @@ -166,56 +157,46 @@ extern "C" { #define L2CACHE_L2CS_MP 0x400000U #define L2CACHE_L2CS_MTRR_SHIFT 16 -#define L2CACHE_L2CS_MTRR_MASK 0x3f0000U +#define L2CACHE_L2CS_MTRR_MASK 0x3f0000U #define L2CACHE_L2CS_MTRR_GET( _reg ) \ - ( ( ( _reg ) & L2CACHE_L2CS_MTRR_MASK ) >> \ - L2CACHE_L2CS_MTRR_SHIFT ) -#define L2CACHE_L2CS_MTRR_SET( _reg, _val ) \ + ( ( ( _reg ) & L2CACHE_L2CS_MTRR_MASK ) >> L2CACHE_L2CS_MTRR_SHIFT ) +#define L2CACHE_L2CS_MTRR_SET( _reg, _val ) \ ( ( ( _reg ) & ~L2CACHE_L2CS_MTRR_MASK ) | \ - ( ( ( _val ) << L2CACHE_L2CS_MTRR_SHIFT ) & \ - L2CACHE_L2CS_MTRR_MASK ) ) + ( ( ( _val ) << L2CACHE_L2CS_MTRR_SHIFT ) & L2CACHE_L2CS_MTRR_MASK ) ) #define L2CACHE_L2CS_MTRR( _val ) \ - ( ( ( _val ) << L2CACHE_L2CS_MTRR_SHIFT ) & \ - L2CACHE_L2CS_MTRR_MASK ) + ( ( ( _val ) << L2CACHE_L2CS_MTRR_SHIFT ) & L2CACHE_L2CS_MTRR_MASK ) #define L2CACHE_L2CS_BBUS_W_SHIFT 13 -#define L2CACHE_L2CS_BBUS_W_MASK 0xe000U +#define L2CACHE_L2CS_BBUS_W_MASK 0xe000U #define L2CACHE_L2CS_BBUS_W_GET( _reg ) \ - ( ( ( _reg ) & L2CACHE_L2CS_BBUS_W_MASK ) >> \ - L2CACHE_L2CS_BBUS_W_SHIFT ) -#define L2CACHE_L2CS_BBUS_W_SET( _reg, _val ) \ - ( ( ( _reg ) & ~L2CACHE_L2CS_BBUS_W_MASK ) | \ + ( ( ( _reg ) & L2CACHE_L2CS_BBUS_W_MASK ) >> L2CACHE_L2CS_BBUS_W_SHIFT ) +#define L2CACHE_L2CS_BBUS_W_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CS_BBUS_W_MASK ) | \ ( ( ( _val ) << L2CACHE_L2CS_BBUS_W_SHIFT ) & \ L2CACHE_L2CS_BBUS_W_MASK ) ) #define L2CACHE_L2CS_BBUS_W( _val ) \ - ( ( ( _val ) << L2CACHE_L2CS_BBUS_W_SHIFT ) & \ - L2CACHE_L2CS_BBUS_W_MASK ) + ( ( ( _val ) << L2CACHE_L2CS_BBUS_W_SHIFT ) & L2CACHE_L2CS_BBUS_W_MASK ) #define L2CACHE_L2CS_WAY_SIZE_SHIFT 2 -#define L2CACHE_L2CS_WAY_SIZE_MASK 0x1ffcU +#define L2CACHE_L2CS_WAY_SIZE_MASK 0x1ffcU #define L2CACHE_L2CS_WAY_SIZE_GET( _reg ) \ - ( ( ( _reg ) & L2CACHE_L2CS_WAY_SIZE_MASK ) >> \ - L2CACHE_L2CS_WAY_SIZE_SHIFT ) -#define L2CACHE_L2CS_WAY_SIZE_SET( _reg, _val ) \ - ( ( ( _reg ) & ~L2CACHE_L2CS_WAY_SIZE_MASK ) | \ + ( ( ( _reg ) & L2CACHE_L2CS_WAY_SIZE_MASK ) >> L2CACHE_L2CS_WAY_SIZE_SHIFT ) +#define L2CACHE_L2CS_WAY_SIZE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CS_WAY_SIZE_MASK ) | \ ( ( ( _val ) << L2CACHE_L2CS_WAY_SIZE_SHIFT ) & \ L2CACHE_L2CS_WAY_SIZE_MASK ) ) #define L2CACHE_L2CS_WAY_SIZE( _val ) \ - ( ( ( _val ) << L2CACHE_L2CS_WAY_SIZE_SHIFT ) & \ - L2CACHE_L2CS_WAY_SIZE_MASK ) + ( ( ( _val ) << L2CACHE_L2CS_WAY_SIZE_SHIFT ) & L2CACHE_L2CS_WAY_SIZE_MASK ) #define L2CACHE_L2CS_WAY_SHIFT 0 -#define L2CACHE_L2CS_WAY_MASK 0x3U +#define L2CACHE_L2CS_WAY_MASK 0x3U #define L2CACHE_L2CS_WAY_GET( _reg ) \ - ( ( ( _reg ) & L2CACHE_L2CS_WAY_MASK ) >> \ - L2CACHE_L2CS_WAY_SHIFT ) -#define L2CACHE_L2CS_WAY_SET( _reg, _val ) \ + ( ( ( _reg ) & L2CACHE_L2CS_WAY_MASK ) >> L2CACHE_L2CS_WAY_SHIFT ) +#define L2CACHE_L2CS_WAY_SET( _reg, _val ) \ ( ( ( _reg ) & ~L2CACHE_L2CS_WAY_MASK ) | \ - ( ( ( _val ) << L2CACHE_L2CS_WAY_SHIFT ) & \ - L2CACHE_L2CS_WAY_MASK ) ) + ( ( ( _val ) << L2CACHE_L2CS_WAY_SHIFT ) & L2CACHE_L2CS_WAY_MASK ) ) #define L2CACHE_L2CS_WAY( _val ) \ - ( ( ( _val ) << L2CACHE_L2CS_WAY_SHIFT ) & \ - L2CACHE_L2CS_WAY_MASK ) + ( ( ( _val ) << L2CACHE_L2CS_WAY_SHIFT ) & L2CACHE_L2CS_WAY_MASK ) /** @} */ @@ -229,32 +210,28 @@ extern "C" { */ #define L2CACHE_L2CFMA_ADDR_SHIFT 5 -#define L2CACHE_L2CFMA_ADDR_MASK 0xffffffe0U +#define L2CACHE_L2CFMA_ADDR_MASK 0xffffffe0U #define L2CACHE_L2CFMA_ADDR_GET( _reg ) \ - ( ( ( _reg ) & L2CACHE_L2CFMA_ADDR_MASK ) >> \ - L2CACHE_L2CFMA_ADDR_SHIFT ) -#define L2CACHE_L2CFMA_ADDR_SET( _reg, _val ) \ - ( ( ( _reg ) & ~L2CACHE_L2CFMA_ADDR_MASK ) | \ + ( ( ( _reg ) & L2CACHE_L2CFMA_ADDR_MASK ) >> L2CACHE_L2CFMA_ADDR_SHIFT ) +#define L2CACHE_L2CFMA_ADDR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CFMA_ADDR_MASK ) | \ ( ( ( _val ) << L2CACHE_L2CFMA_ADDR_SHIFT ) & \ L2CACHE_L2CFMA_ADDR_MASK ) ) #define L2CACHE_L2CFMA_ADDR( _val ) \ - ( ( ( _val ) << L2CACHE_L2CFMA_ADDR_SHIFT ) & \ - L2CACHE_L2CFMA_ADDR_MASK ) + ( ( ( _val ) << L2CACHE_L2CFMA_ADDR_SHIFT ) & L2CACHE_L2CFMA_ADDR_MASK ) #define L2CACHE_L2CFMA_DI 0x8U #define L2CACHE_L2CFMA_FMODE_SHIFT 0 -#define L2CACHE_L2CFMA_FMODE_MASK 0x7U +#define L2CACHE_L2CFMA_FMODE_MASK 0x7U #define L2CACHE_L2CFMA_FMODE_GET( _reg ) \ - ( ( ( _reg ) & L2CACHE_L2CFMA_FMODE_MASK ) >> \ - L2CACHE_L2CFMA_FMODE_SHIFT ) -#define L2CACHE_L2CFMA_FMODE_SET( _reg, _val ) \ - ( ( ( _reg ) & ~L2CACHE_L2CFMA_FMODE_MASK ) | \ + ( ( ( _reg ) & L2CACHE_L2CFMA_FMODE_MASK ) >> L2CACHE_L2CFMA_FMODE_SHIFT ) +#define L2CACHE_L2CFMA_FMODE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CFMA_FMODE_MASK ) | \ ( ( ( _val ) << L2CACHE_L2CFMA_FMODE_SHIFT ) & \ L2CACHE_L2CFMA_FMODE_MASK ) ) #define L2CACHE_L2CFMA_FMODE( _val ) \ - ( ( ( _val ) << L2CACHE_L2CFMA_FMODE_SHIFT ) & \ - L2CACHE_L2CFMA_FMODE_MASK ) + ( ( ( _val ) << L2CACHE_L2CFMA_FMODE_SHIFT ) & L2CACHE_L2CFMA_FMODE_MASK ) /** @} */ @@ -268,30 +245,25 @@ extern "C" { */ #define L2CACHE_L2CFSI_INDEX_SHIFT 16 -#define L2CACHE_L2CFSI_INDEX_MASK 0xffff0000U +#define L2CACHE_L2CFSI_INDEX_MASK 0xffff0000U #define L2CACHE_L2CFSI_INDEX_GET( _reg ) \ - ( ( ( _reg ) & L2CACHE_L2CFSI_INDEX_MASK ) >> \ - L2CACHE_L2CFSI_INDEX_SHIFT ) -#define L2CACHE_L2CFSI_INDEX_SET( _reg, _val ) \ - ( ( ( _reg ) & ~L2CACHE_L2CFSI_INDEX_MASK ) | \ + ( ( ( _reg ) & L2CACHE_L2CFSI_INDEX_MASK ) >> L2CACHE_L2CFSI_INDEX_SHIFT ) +#define L2CACHE_L2CFSI_INDEX_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CFSI_INDEX_MASK ) | \ ( ( ( _val ) << L2CACHE_L2CFSI_INDEX_SHIFT ) & \ L2CACHE_L2CFSI_INDEX_MASK ) ) #define L2CACHE_L2CFSI_INDEX( _val ) \ - ( ( ( _val ) << L2CACHE_L2CFSI_INDEX_SHIFT ) & \ - L2CACHE_L2CFSI_INDEX_MASK ) + ( ( ( _val ) << L2CACHE_L2CFSI_INDEX_SHIFT ) & L2CACHE_L2CFSI_INDEX_MASK ) #define L2CACHE_L2CFSI_TAG_SHIFT 10 -#define L2CACHE_L2CFSI_TAG_MASK 0xfffffc00U +#define L2CACHE_L2CFSI_TAG_MASK 0xfffffc00U #define L2CACHE_L2CFSI_TAG_GET( _reg ) \ - ( ( ( _reg ) & L2CACHE_L2CFSI_TAG_MASK ) >> \ - L2CACHE_L2CFSI_TAG_SHIFT ) -#define L2CACHE_L2CFSI_TAG_SET( _reg, _val ) \ + ( ( ( _reg ) & L2CACHE_L2CFSI_TAG_MASK ) >> L2CACHE_L2CFSI_TAG_SHIFT ) +#define L2CACHE_L2CFSI_TAG_SET( _reg, _val ) \ ( ( ( _reg ) & ~L2CACHE_L2CFSI_TAG_MASK ) | \ - ( ( ( _val ) << L2CACHE_L2CFSI_TAG_SHIFT ) & \ - L2CACHE_L2CFSI_TAG_MASK ) ) + ( ( ( _val ) << L2CACHE_L2CFSI_TAG_SHIFT ) & L2CACHE_L2CFSI_TAG_MASK ) ) #define L2CACHE_L2CFSI_TAG( _val ) \ - ( ( ( _val ) << L2CACHE_L2CFSI_TAG_SHIFT ) & \ - L2CACHE_L2CFSI_TAG_MASK ) + ( ( ( _val ) << L2CACHE_L2CFSI_TAG_SHIFT ) & L2CACHE_L2CFSI_TAG_MASK ) #define L2CACHE_L2CFSI_FL 0x200U @@ -300,34 +272,29 @@ extern "C" { #define L2CACHE_L2CFSI_DB 0x80U #define L2CACHE_L2CFSI_WAY_SHIFT 4 -#define L2CACHE_L2CFSI_WAY_MASK 0x30U +#define L2CACHE_L2CFSI_WAY_MASK 0x30U #define L2CACHE_L2CFSI_WAY_GET( _reg ) \ - ( ( ( _reg ) & L2CACHE_L2CFSI_WAY_MASK ) >> \ - L2CACHE_L2CFSI_WAY_SHIFT ) -#define L2CACHE_L2CFSI_WAY_SET( _reg, _val ) \ + ( ( ( _reg ) & L2CACHE_L2CFSI_WAY_MASK ) >> L2CACHE_L2CFSI_WAY_SHIFT ) +#define L2CACHE_L2CFSI_WAY_SET( _reg, _val ) \ ( ( ( _reg ) & ~L2CACHE_L2CFSI_WAY_MASK ) | \ - ( ( ( _val ) << L2CACHE_L2CFSI_WAY_SHIFT ) & \ - L2CACHE_L2CFSI_WAY_MASK ) ) + ( ( ( _val ) << L2CACHE_L2CFSI_WAY_SHIFT ) & L2CACHE_L2CFSI_WAY_MASK ) ) #define L2CACHE_L2CFSI_WAY( _val ) \ - ( ( ( _val ) << L2CACHE_L2CFSI_WAY_SHIFT ) & \ - L2CACHE_L2CFSI_WAY_MASK ) + ( ( ( _val ) << L2CACHE_L2CFSI_WAY_SHIFT ) & L2CACHE_L2CFSI_WAY_MASK ) #define L2CACHE_L2CFSI_DI 0x8U #define L2CACHE_L2CFSI_WF 0x4U #define L2CACHE_L2CFSI_FMODE_SHIFT 0 -#define L2CACHE_L2CFSI_FMODE_MASK 0x3U +#define L2CACHE_L2CFSI_FMODE_MASK 0x3U #define L2CACHE_L2CFSI_FMODE_GET( _reg ) \ - ( ( ( _reg ) & L2CACHE_L2CFSI_FMODE_MASK ) >> \ - L2CACHE_L2CFSI_FMODE_SHIFT ) -#define L2CACHE_L2CFSI_FMODE_SET( _reg, _val ) \ - ( ( ( _reg ) & ~L2CACHE_L2CFSI_FMODE_MASK ) | \ + ( ( ( _reg ) & L2CACHE_L2CFSI_FMODE_MASK ) >> L2CACHE_L2CFSI_FMODE_SHIFT ) +#define L2CACHE_L2CFSI_FMODE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CFSI_FMODE_MASK ) | \ ( ( ( _val ) << L2CACHE_L2CFSI_FMODE_SHIFT ) & \ L2CACHE_L2CFSI_FMODE_MASK ) ) #define L2CACHE_L2CFSI_FMODE( _val ) \ - ( ( ( _val ) << L2CACHE_L2CFSI_FMODE_SHIFT ) & \ - L2CACHE_L2CFSI_FMODE_MASK ) + ( ( ( _val ) << L2CACHE_L2CFSI_FMODE_SHIFT ) & L2CACHE_L2CFSI_FMODE_MASK ) /** @} */ @@ -341,32 +308,30 @@ extern "C" { */ #define L2CACHE_L2CERR_AHB_MASTER_INDEX_SHIFT 28 -#define L2CACHE_L2CERR_AHB_MASTER_INDEX_MASK 0xf0000000U -#define L2CACHE_L2CERR_AHB_MASTER_INDEX_GET( _reg ) \ +#define L2CACHE_L2CERR_AHB_MASTER_INDEX_MASK 0xf0000000U +#define L2CACHE_L2CERR_AHB_MASTER_INDEX_GET( _reg ) \ ( ( ( _reg ) & L2CACHE_L2CERR_AHB_MASTER_INDEX_MASK ) >> \ L2CACHE_L2CERR_AHB_MASTER_INDEX_SHIFT ) -#define L2CACHE_L2CERR_AHB_MASTER_INDEX_SET( _reg, _val ) \ - ( ( ( _reg ) & ~L2CACHE_L2CERR_AHB_MASTER_INDEX_MASK ) | \ +#define L2CACHE_L2CERR_AHB_MASTER_INDEX_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CERR_AHB_MASTER_INDEX_MASK ) | \ ( ( ( _val ) << L2CACHE_L2CERR_AHB_MASTER_INDEX_SHIFT ) & \ L2CACHE_L2CERR_AHB_MASTER_INDEX_MASK ) ) -#define L2CACHE_L2CERR_AHB_MASTER_INDEX( _val ) \ +#define L2CACHE_L2CERR_AHB_MASTER_INDEX( _val ) \ ( ( ( _val ) << L2CACHE_L2CERR_AHB_MASTER_INDEX_SHIFT ) & \ L2CACHE_L2CERR_AHB_MASTER_INDEX_MASK ) #define L2CACHE_L2CERR_SCRUB 0x8000000U #define L2CACHE_L2CERR_TYPE_SHIFT 24 -#define L2CACHE_L2CERR_TYPE_MASK 0x7000000U +#define L2CACHE_L2CERR_TYPE_MASK 0x7000000U #define L2CACHE_L2CERR_TYPE_GET( _reg ) \ - ( ( ( _reg ) & L2CACHE_L2CERR_TYPE_MASK ) >> \ - L2CACHE_L2CERR_TYPE_SHIFT ) -#define L2CACHE_L2CERR_TYPE_SET( _reg, _val ) \ - ( ( ( _reg ) & ~L2CACHE_L2CERR_TYPE_MASK ) | \ + ( ( ( _reg ) & L2CACHE_L2CERR_TYPE_MASK ) >> L2CACHE_L2CERR_TYPE_SHIFT ) +#define L2CACHE_L2CERR_TYPE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CERR_TYPE_MASK ) | \ ( ( ( _val ) << L2CACHE_L2CERR_TYPE_SHIFT ) & \ L2CACHE_L2CERR_TYPE_MASK ) ) #define L2CACHE_L2CERR_TYPE( _val ) \ - ( ( ( _val ) << L2CACHE_L2CERR_TYPE_SHIFT ) & \ - L2CACHE_L2CERR_TYPE_MASK ) + ( ( ( _val ) << L2CACHE_L2CERR_TYPE_SHIFT ) & L2CACHE_L2CERR_TYPE_MASK ) #define L2CACHE_L2CERR_TAG_DATA 0x800000U @@ -379,67 +344,67 @@ extern "C" { #define L2CACHE_L2CERR_DISERESP 0x80000U #define L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_SHIFT 16 -#define L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_MASK 0x70000U -#define L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_GET( _reg ) \ +#define L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_MASK 0x70000U +#define L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_GET( _reg ) \ ( ( ( _reg ) & L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_MASK ) >> \ L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_SHIFT ) -#define L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_SET( _reg, _val ) \ - ( ( ( _reg ) & ~L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_MASK ) | \ +#define L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_MASK ) | \ ( ( ( _val ) << L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_SHIFT ) & \ L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_MASK ) ) -#define L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER( _val ) \ +#define L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER( _val ) \ ( ( ( _val ) << L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_SHIFT ) & \ L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_MASK ) #define L2CACHE_L2CERR_IRQ_PENDING_SHIFT 12 -#define L2CACHE_L2CERR_IRQ_PENDING_MASK 0xf000U -#define L2CACHE_L2CERR_IRQ_PENDING_GET( _reg ) \ +#define L2CACHE_L2CERR_IRQ_PENDING_MASK 0xf000U +#define L2CACHE_L2CERR_IRQ_PENDING_GET( _reg ) \ ( ( ( _reg ) & L2CACHE_L2CERR_IRQ_PENDING_MASK ) >> \ L2CACHE_L2CERR_IRQ_PENDING_SHIFT ) -#define L2CACHE_L2CERR_IRQ_PENDING_SET( _reg, _val ) \ - ( ( ( _reg ) & ~L2CACHE_L2CERR_IRQ_PENDING_MASK ) | \ +#define L2CACHE_L2CERR_IRQ_PENDING_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CERR_IRQ_PENDING_MASK ) | \ ( ( ( _val ) << L2CACHE_L2CERR_IRQ_PENDING_SHIFT ) & \ L2CACHE_L2CERR_IRQ_PENDING_MASK ) ) -#define L2CACHE_L2CERR_IRQ_PENDING( _val ) \ +#define L2CACHE_L2CERR_IRQ_PENDING( _val ) \ ( ( ( _val ) << L2CACHE_L2CERR_IRQ_PENDING_SHIFT ) & \ L2CACHE_L2CERR_IRQ_PENDING_MASK ) #define L2CACHE_L2CERR_IRQ_MASK_SHIFT 8 -#define L2CACHE_L2CERR_IRQ_MASK_MASK 0xf00U -#define L2CACHE_L2CERR_IRQ_MASK_GET( _reg ) \ +#define L2CACHE_L2CERR_IRQ_MASK_MASK 0xf00U +#define L2CACHE_L2CERR_IRQ_MASK_GET( _reg ) \ ( ( ( _reg ) & L2CACHE_L2CERR_IRQ_MASK_MASK ) >> \ L2CACHE_L2CERR_IRQ_MASK_SHIFT ) -#define L2CACHE_L2CERR_IRQ_MASK_SET( _reg, _val ) \ - ( ( ( _reg ) & ~L2CACHE_L2CERR_IRQ_MASK_MASK ) | \ +#define L2CACHE_L2CERR_IRQ_MASK_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CERR_IRQ_MASK_MASK ) | \ ( ( ( _val ) << L2CACHE_L2CERR_IRQ_MASK_SHIFT ) & \ L2CACHE_L2CERR_IRQ_MASK_MASK ) ) -#define L2CACHE_L2CERR_IRQ_MASK( _val ) \ +#define L2CACHE_L2CERR_IRQ_MASK( _val ) \ ( ( ( _val ) << L2CACHE_L2CERR_IRQ_MASK_SHIFT ) & \ L2CACHE_L2CERR_IRQ_MASK_MASK ) #define L2CACHE_L2CERR_SELECT_CB_SHIFT 6 -#define L2CACHE_L2CERR_SELECT_CB_MASK 0xc0U -#define L2CACHE_L2CERR_SELECT_CB_GET( _reg ) \ +#define L2CACHE_L2CERR_SELECT_CB_MASK 0xc0U +#define L2CACHE_L2CERR_SELECT_CB_GET( _reg ) \ ( ( ( _reg ) & L2CACHE_L2CERR_SELECT_CB_MASK ) >> \ L2CACHE_L2CERR_SELECT_CB_SHIFT ) -#define L2CACHE_L2CERR_SELECT_CB_SET( _reg, _val ) \ - ( ( ( _reg ) & ~L2CACHE_L2CERR_SELECT_CB_MASK ) | \ +#define L2CACHE_L2CERR_SELECT_CB_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CERR_SELECT_CB_MASK ) | \ ( ( ( _val ) << L2CACHE_L2CERR_SELECT_CB_SHIFT ) & \ L2CACHE_L2CERR_SELECT_CB_MASK ) ) -#define L2CACHE_L2CERR_SELECT_CB( _val ) \ +#define L2CACHE_L2CERR_SELECT_CB( _val ) \ ( ( ( _val ) << L2CACHE_L2CERR_SELECT_CB_SHIFT ) & \ L2CACHE_L2CERR_SELECT_CB_MASK ) #define L2CACHE_L2CERR_SELECT_TCB_SHIFT 4 -#define L2CACHE_L2CERR_SELECT_TCB_MASK 0x30U -#define L2CACHE_L2CERR_SELECT_TCB_GET( _reg ) \ +#define L2CACHE_L2CERR_SELECT_TCB_MASK 0x30U +#define L2CACHE_L2CERR_SELECT_TCB_GET( _reg ) \ ( ( ( _reg ) & L2CACHE_L2CERR_SELECT_TCB_MASK ) >> \ L2CACHE_L2CERR_SELECT_TCB_SHIFT ) -#define L2CACHE_L2CERR_SELECT_TCB_SET( _reg, _val ) \ - ( ( ( _reg ) & ~L2CACHE_L2CERR_SELECT_TCB_MASK ) | \ +#define L2CACHE_L2CERR_SELECT_TCB_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CERR_SELECT_TCB_MASK ) | \ ( ( ( _val ) << L2CACHE_L2CERR_SELECT_TCB_SHIFT ) & \ L2CACHE_L2CERR_SELECT_TCB_MASK ) ) -#define L2CACHE_L2CERR_SELECT_TCB( _val ) \ +#define L2CACHE_L2CERR_SELECT_TCB( _val ) \ ( ( ( _val ) << L2CACHE_L2CERR_SELECT_TCB_SHIFT ) & \ L2CACHE_L2CERR_SELECT_TCB_MASK ) @@ -463,17 +428,15 @@ extern "C" { */ #define L2CACHE_L2CERRA_EADDR_SHIFT 0 -#define L2CACHE_L2CERRA_EADDR_MASK 0xffffffffU +#define L2CACHE_L2CERRA_EADDR_MASK 0xffffffffU #define L2CACHE_L2CERRA_EADDR_GET( _reg ) \ - ( ( ( _reg ) & L2CACHE_L2CERRA_EADDR_MASK ) >> \ - L2CACHE_L2CERRA_EADDR_SHIFT ) -#define L2CACHE_L2CERRA_EADDR_SET( _reg, _val ) \ - ( ( ( _reg ) & ~L2CACHE_L2CERRA_EADDR_MASK ) | \ + ( ( ( _reg ) & L2CACHE_L2CERRA_EADDR_MASK ) >> L2CACHE_L2CERRA_EADDR_SHIFT ) +#define L2CACHE_L2CERRA_EADDR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CERRA_EADDR_MASK ) | \ ( ( ( _val ) << L2CACHE_L2CERRA_EADDR_SHIFT ) & \ L2CACHE_L2CERRA_EADDR_MASK ) ) #define L2CACHE_L2CERRA_EADDR( _val ) \ - ( ( ( _val ) << L2CACHE_L2CERRA_EADDR_SHIFT ) & \ - L2CACHE_L2CERRA_EADDR_MASK ) + ( ( ( _val ) << L2CACHE_L2CERRA_EADDR_SHIFT ) & L2CACHE_L2CERRA_EADDR_MASK ) /** @} */ @@ -486,17 +449,14 @@ extern "C" { */ #define L2CACHE_L2CTCB_TCB_SHIFT 0 -#define L2CACHE_L2CTCB_TCB_MASK 0x7fU +#define L2CACHE_L2CTCB_TCB_MASK 0x7fU #define L2CACHE_L2CTCB_TCB_GET( _reg ) \ - ( ( ( _reg ) & L2CACHE_L2CTCB_TCB_MASK ) >> \ - L2CACHE_L2CTCB_TCB_SHIFT ) -#define L2CACHE_L2CTCB_TCB_SET( _reg, _val ) \ + ( ( ( _reg ) & L2CACHE_L2CTCB_TCB_MASK ) >> L2CACHE_L2CTCB_TCB_SHIFT ) +#define L2CACHE_L2CTCB_TCB_SET( _reg, _val ) \ ( ( ( _reg ) & ~L2CACHE_L2CTCB_TCB_MASK ) | \ - ( ( ( _val ) << L2CACHE_L2CTCB_TCB_SHIFT ) & \ - L2CACHE_L2CTCB_TCB_MASK ) ) + ( ( ( _val ) << L2CACHE_L2CTCB_TCB_SHIFT ) & L2CACHE_L2CTCB_TCB_MASK ) ) #define L2CACHE_L2CTCB_TCB( _val ) \ - ( ( ( _val ) << L2CACHE_L2CTCB_TCB_SHIFT ) & \ - L2CACHE_L2CTCB_TCB_MASK ) + ( ( ( _val ) << L2CACHE_L2CTCB_TCB_SHIFT ) & L2CACHE_L2CTCB_TCB_MASK ) /** @} */ @@ -509,17 +469,14 @@ extern "C" { */ #define L2CACHE_L2CCB_CB_SHIFT 0 -#define L2CACHE_L2CCB_CB_MASK 0xfffffffU +#define L2CACHE_L2CCB_CB_MASK 0xfffffffU #define L2CACHE_L2CCB_CB_GET( _reg ) \ - ( ( ( _reg ) & L2CACHE_L2CCB_CB_MASK ) >> \ - L2CACHE_L2CCB_CB_SHIFT ) -#define L2CACHE_L2CCB_CB_SET( _reg, _val ) \ + ( ( ( _reg ) & L2CACHE_L2CCB_CB_MASK ) >> L2CACHE_L2CCB_CB_SHIFT ) +#define L2CACHE_L2CCB_CB_SET( _reg, _val ) \ ( ( ( _reg ) & ~L2CACHE_L2CCB_CB_MASK ) | \ - ( ( ( _val ) << L2CACHE_L2CCB_CB_SHIFT ) & \ - L2CACHE_L2CCB_CB_MASK ) ) + ( ( ( _val ) << L2CACHE_L2CCB_CB_SHIFT ) & L2CACHE_L2CCB_CB_MASK ) ) #define L2CACHE_L2CCB_CB( _val ) \ - ( ( ( _val ) << L2CACHE_L2CCB_CB_SHIFT ) & \ - L2CACHE_L2CCB_CB_MASK ) + ( ( ( _val ) << L2CACHE_L2CCB_CB_SHIFT ) & L2CACHE_L2CCB_CB_MASK ) /** @} */ @@ -533,30 +490,28 @@ extern "C" { */ #define L2CACHE_L2CSCRUB_INDEX_SHIFT 16 -#define L2CACHE_L2CSCRUB_INDEX_MASK 0xffff0000U -#define L2CACHE_L2CSCRUB_INDEX_GET( _reg ) \ +#define L2CACHE_L2CSCRUB_INDEX_MASK 0xffff0000U +#define L2CACHE_L2CSCRUB_INDEX_GET( _reg ) \ ( ( ( _reg ) & L2CACHE_L2CSCRUB_INDEX_MASK ) >> \ L2CACHE_L2CSCRUB_INDEX_SHIFT ) -#define L2CACHE_L2CSCRUB_INDEX_SET( _reg, _val ) \ - ( ( ( _reg ) & ~L2CACHE_L2CSCRUB_INDEX_MASK ) | \ +#define L2CACHE_L2CSCRUB_INDEX_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CSCRUB_INDEX_MASK ) | \ ( ( ( _val ) << L2CACHE_L2CSCRUB_INDEX_SHIFT ) & \ L2CACHE_L2CSCRUB_INDEX_MASK ) ) -#define L2CACHE_L2CSCRUB_INDEX( _val ) \ +#define L2CACHE_L2CSCRUB_INDEX( _val ) \ ( ( ( _val ) << L2CACHE_L2CSCRUB_INDEX_SHIFT ) & \ L2CACHE_L2CSCRUB_INDEX_MASK ) #define L2CACHE_L2CSCRUB_WAY_SHIFT 2 -#define L2CACHE_L2CSCRUB_WAY_MASK 0xcU +#define L2CACHE_L2CSCRUB_WAY_MASK 0xcU #define L2CACHE_L2CSCRUB_WAY_GET( _reg ) \ - ( ( ( _reg ) & L2CACHE_L2CSCRUB_WAY_MASK ) >> \ - L2CACHE_L2CSCRUB_WAY_SHIFT ) -#define L2CACHE_L2CSCRUB_WAY_SET( _reg, _val ) \ - ( ( ( _reg ) & ~L2CACHE_L2CSCRUB_WAY_MASK ) | \ + ( ( ( _reg ) & L2CACHE_L2CSCRUB_WAY_MASK ) >> L2CACHE_L2CSCRUB_WAY_SHIFT ) +#define L2CACHE_L2CSCRUB_WAY_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CSCRUB_WAY_MASK ) | \ ( ( ( _val ) << L2CACHE_L2CSCRUB_WAY_SHIFT ) & \ L2CACHE_L2CSCRUB_WAY_MASK ) ) #define L2CACHE_L2CSCRUB_WAY( _val ) \ - ( ( ( _val ) << L2CACHE_L2CSCRUB_WAY_SHIFT ) & \ - L2CACHE_L2CSCRUB_WAY_MASK ) + ( ( ( _val ) << L2CACHE_L2CSCRUB_WAY_SHIFT ) & L2CACHE_L2CSCRUB_WAY_MASK ) #define L2CACHE_L2CSCRUB_PEN 0x2U @@ -573,17 +528,15 @@ extern "C" { */ #define L2CACHE_L2CSDEL_DEL_SHIFT 0 -#define L2CACHE_L2CSDEL_DEL_MASK 0xffffU +#define L2CACHE_L2CSDEL_DEL_MASK 0xffffU #define L2CACHE_L2CSDEL_DEL_GET( _reg ) \ - ( ( ( _reg ) & L2CACHE_L2CSDEL_DEL_MASK ) >> \ - L2CACHE_L2CSDEL_DEL_SHIFT ) -#define L2CACHE_L2CSDEL_DEL_SET( _reg, _val ) \ - ( ( ( _reg ) & ~L2CACHE_L2CSDEL_DEL_MASK ) | \ + ( ( ( _reg ) & L2CACHE_L2CSDEL_DEL_MASK ) >> L2CACHE_L2CSDEL_DEL_SHIFT ) +#define L2CACHE_L2CSDEL_DEL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CSDEL_DEL_MASK ) | \ ( ( ( _val ) << L2CACHE_L2CSDEL_DEL_SHIFT ) & \ L2CACHE_L2CSDEL_DEL_MASK ) ) #define L2CACHE_L2CSDEL_DEL( _val ) \ - ( ( ( _val ) << L2CACHE_L2CSDEL_DEL_SHIFT ) & \ - L2CACHE_L2CSDEL_DEL_MASK ) + ( ( ( _val ) << L2CACHE_L2CSDEL_DEL_SHIFT ) & L2CACHE_L2CSDEL_DEL_MASK ) /** @} */ @@ -597,17 +550,15 @@ extern "C" { */ #define L2CACHE_L2CEINJ_ADDR_SHIFT 2 -#define L2CACHE_L2CEINJ_ADDR_MASK 0xfffffffcU +#define L2CACHE_L2CEINJ_ADDR_MASK 0xfffffffcU #define L2CACHE_L2CEINJ_ADDR_GET( _reg ) \ - ( ( ( _reg ) & L2CACHE_L2CEINJ_ADDR_MASK ) >> \ - L2CACHE_L2CEINJ_ADDR_SHIFT ) -#define L2CACHE_L2CEINJ_ADDR_SET( _reg, _val ) \ - ( ( ( _reg ) & ~L2CACHE_L2CEINJ_ADDR_MASK ) | \ + ( ( ( _reg ) & L2CACHE_L2CEINJ_ADDR_MASK ) >> L2CACHE_L2CEINJ_ADDR_SHIFT ) +#define L2CACHE_L2CEINJ_ADDR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CEINJ_ADDR_MASK ) | \ ( ( ( _val ) << L2CACHE_L2CEINJ_ADDR_SHIFT ) & \ L2CACHE_L2CEINJ_ADDR_MASK ) ) #define L2CACHE_L2CEINJ_ADDR( _val ) \ - ( ( ( _val ) << L2CACHE_L2CEINJ_ADDR_SHIFT ) & \ - L2CACHE_L2CEINJ_ADDR_MASK ) + ( ( ( _val ) << L2CACHE_L2CEINJ_ADDR_SHIFT ) & L2CACHE_L2CEINJ_ADDR_MASK ) #define L2CACHE_L2CEINJ_INJ 0x1U @@ -673,43 +624,37 @@ extern "C" { */ #define L2CACHE_L2CMTRR_ADDR_SHIFT 18 -#define L2CACHE_L2CMTRR_ADDR_MASK 0xfffc0000U +#define L2CACHE_L2CMTRR_ADDR_MASK 0xfffc0000U #define L2CACHE_L2CMTRR_ADDR_GET( _reg ) \ - ( ( ( _reg ) & L2CACHE_L2CMTRR_ADDR_MASK ) >> \ - L2CACHE_L2CMTRR_ADDR_SHIFT ) -#define L2CACHE_L2CMTRR_ADDR_SET( _reg, _val ) \ - ( ( ( _reg ) & ~L2CACHE_L2CMTRR_ADDR_MASK ) | \ + ( ( ( _reg ) & L2CACHE_L2CMTRR_ADDR_MASK ) >> L2CACHE_L2CMTRR_ADDR_SHIFT ) +#define L2CACHE_L2CMTRR_ADDR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CMTRR_ADDR_MASK ) | \ ( ( ( _val ) << L2CACHE_L2CMTRR_ADDR_SHIFT ) & \ L2CACHE_L2CMTRR_ADDR_MASK ) ) #define L2CACHE_L2CMTRR_ADDR( _val ) \ - ( ( ( _val ) << L2CACHE_L2CMTRR_ADDR_SHIFT ) & \ - L2CACHE_L2CMTRR_ADDR_MASK ) + ( ( ( _val ) << L2CACHE_L2CMTRR_ADDR_SHIFT ) & L2CACHE_L2CMTRR_ADDR_MASK ) #define L2CACHE_L2CMTRR_ACC_SHIFT 16 -#define L2CACHE_L2CMTRR_ACC_MASK 0x30000U +#define L2CACHE_L2CMTRR_ACC_MASK 0x30000U #define L2CACHE_L2CMTRR_ACC_GET( _reg ) \ - ( ( ( _reg ) & L2CACHE_L2CMTRR_ACC_MASK ) >> \ - L2CACHE_L2CMTRR_ACC_SHIFT ) -#define L2CACHE_L2CMTRR_ACC_SET( _reg, _val ) \ - ( ( ( _reg ) & ~L2CACHE_L2CMTRR_ACC_MASK ) | \ + ( ( ( _reg ) & L2CACHE_L2CMTRR_ACC_MASK ) >> L2CACHE_L2CMTRR_ACC_SHIFT ) +#define L2CACHE_L2CMTRR_ACC_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CMTRR_ACC_MASK ) | \ ( ( ( _val ) << L2CACHE_L2CMTRR_ACC_SHIFT ) & \ L2CACHE_L2CMTRR_ACC_MASK ) ) #define L2CACHE_L2CMTRR_ACC( _val ) \ - ( ( ( _val ) << L2CACHE_L2CMTRR_ACC_SHIFT ) & \ - L2CACHE_L2CMTRR_ACC_MASK ) + ( ( ( _val ) << L2CACHE_L2CMTRR_ACC_SHIFT ) & L2CACHE_L2CMTRR_ACC_MASK ) #define L2CACHE_L2CMTRR_MASK_SHIFT 2 -#define L2CACHE_L2CMTRR_MASK_MASK 0xfffcU +#define L2CACHE_L2CMTRR_MASK_MASK 0xfffcU #define L2CACHE_L2CMTRR_MASK_GET( _reg ) \ - ( ( ( _reg ) & L2CACHE_L2CMTRR_MASK_MASK ) >> \ - L2CACHE_L2CMTRR_MASK_SHIFT ) -#define L2CACHE_L2CMTRR_MASK_SET( _reg, _val ) \ - ( ( ( _reg ) & ~L2CACHE_L2CMTRR_MASK_MASK ) | \ + ( ( ( _reg ) & L2CACHE_L2CMTRR_MASK_MASK ) >> L2CACHE_L2CMTRR_MASK_SHIFT ) +#define L2CACHE_L2CMTRR_MASK_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CMTRR_MASK_MASK ) | \ ( ( ( _val ) << L2CACHE_L2CMTRR_MASK_SHIFT ) & \ L2CACHE_L2CMTRR_MASK_MASK ) ) #define L2CACHE_L2CMTRR_MASK( _val ) \ - ( ( ( _val ) << L2CACHE_L2CMTRR_MASK_SHIFT ) & \ - L2CACHE_L2CMTRR_MASK_MASK ) + ( ( ( _val ) << L2CACHE_L2CMTRR_MASK_SHIFT ) & L2CACHE_L2CMTRR_MASK_MASK ) #define L2CACHE_L2CMTRR_WP 0x2U diff --git a/bsps/include/grlib/l4stat-regs.h b/bsps/include/grlib/l4stat-regs.h index 971898f476..2835f44fa9 100644 --- a/bsps/include/grlib/l4stat-regs.h +++ b/bsps/include/grlib/l4stat-regs.h @@ -82,17 +82,14 @@ extern "C" { */ #define L4STAT_CVAL_CVAL_SHIFT 0 -#define L4STAT_CVAL_CVAL_MASK 0xffffffffU +#define L4STAT_CVAL_CVAL_MASK 0xffffffffU #define L4STAT_CVAL_CVAL_GET( _reg ) \ - ( ( ( _reg ) & L4STAT_CVAL_CVAL_MASK ) >> \ - L4STAT_CVAL_CVAL_SHIFT ) -#define L4STAT_CVAL_CVAL_SET( _reg, _val ) \ + ( ( ( _reg ) & L4STAT_CVAL_CVAL_MASK ) >> L4STAT_CVAL_CVAL_SHIFT ) +#define L4STAT_CVAL_CVAL_SET( _reg, _val ) \ ( ( ( _reg ) & ~L4STAT_CVAL_CVAL_MASK ) | \ - ( ( ( _val ) << L4STAT_CVAL_CVAL_SHIFT ) & \ - L4STAT_CVAL_CVAL_MASK ) ) + ( ( ( _val ) << L4STAT_CVAL_CVAL_SHIFT ) & L4STAT_CVAL_CVAL_MASK ) ) #define L4STAT_CVAL_CVAL( _val ) \ - ( ( ( _val ) << L4STAT_CVAL_CVAL_SHIFT ) & \ - L4STAT_CVAL_CVAL_MASK ) + ( ( ( _val ) << L4STAT_CVAL_CVAL_SHIFT ) & L4STAT_CVAL_CVAL_MASK ) /** @} */ @@ -105,30 +102,24 @@ extern "C" { */ #define L4STAT_CCTRL_NCPU_SHIFT 28 -#define L4STAT_CCTRL_NCPU_MASK 0xf0000000U +#define L4STAT_CCTRL_NCPU_MASK 0xf0000000U #define L4STAT_CCTRL_NCPU_GET( _reg ) \ - ( ( ( _reg ) & L4STAT_CCTRL_NCPU_MASK ) >> \ - L4STAT_CCTRL_NCPU_SHIFT ) -#define L4STAT_CCTRL_NCPU_SET( _reg, _val ) \ + ( ( ( _reg ) & L4STAT_CCTRL_NCPU_MASK ) >> L4STAT_CCTRL_NCPU_SHIFT ) +#define L4STAT_CCTRL_NCPU_SET( _reg, _val ) \ ( ( ( _reg ) & ~L4STAT_CCTRL_NCPU_MASK ) | \ - ( ( ( _val ) << L4STAT_CCTRL_NCPU_SHIFT ) & \ - L4STAT_CCTRL_NCPU_MASK ) ) + ( ( ( _val ) << L4STAT_CCTRL_NCPU_SHIFT ) & L4STAT_CCTRL_NCPU_MASK ) ) #define L4STAT_CCTRL_NCPU( _val ) \ - ( ( ( _val ) << L4STAT_CCTRL_NCPU_SHIFT ) & \ - L4STAT_CCTRL_NCPU_MASK ) + ( ( ( _val ) << L4STAT_CCTRL_NCPU_SHIFT ) & L4STAT_CCTRL_NCPU_MASK ) #define L4STAT_CCTRL_NCNT_SHIFT 23 -#define L4STAT_CCTRL_NCNT_MASK 0xf800000U +#define L4STAT_CCTRL_NCNT_MASK 0xf800000U #define L4STAT_CCTRL_NCNT_GET( _reg ) \ - ( ( ( _reg ) & L4STAT_CCTRL_NCNT_MASK ) >> \ - L4STAT_CCTRL_NCNT_SHIFT ) -#define L4STAT_CCTRL_NCNT_SET( _reg, _val ) \ + ( ( ( _reg ) & L4STAT_CCTRL_NCNT_MASK ) >> L4STAT_CCTRL_NCNT_SHIFT ) +#define L4STAT_CCTRL_NCNT_SET( _reg, _val ) \ ( ( ( _reg ) & ~L4STAT_CCTRL_NCNT_MASK ) | \ - ( ( ( _val ) << L4STAT_CCTRL_NCNT_SHIFT ) & \ - L4STAT_CCTRL_NCNT_MASK ) ) + ( ( ( _val ) << L4STAT_CCTRL_NCNT_SHIFT ) & L4STAT_CCTRL_NCNT_MASK ) ) #define L4STAT_CCTRL_NCNT( _val ) \ - ( ( ( _val ) << L4STAT_CCTRL_NCNT_SHIFT ) & \ - L4STAT_CCTRL_NCNT_MASK ) + ( ( ( _val ) << L4STAT_CCTRL_NCNT_SHIFT ) & L4STAT_CCTRL_NCNT_MASK ) #define L4STAT_CCTRL_MC 0x400000U @@ -145,47 +136,40 @@ extern "C" { #define L4STAT_CCTRL_CD 0x10000U #define L4STAT_CCTRL_SU_SHIFT 14 -#define L4STAT_CCTRL_SU_MASK 0xc000U +#define L4STAT_CCTRL_SU_MASK 0xc000U #define L4STAT_CCTRL_SU_GET( _reg ) \ - ( ( ( _reg ) & L4STAT_CCTRL_SU_MASK ) >> \ - L4STAT_CCTRL_SU_SHIFT ) -#define L4STAT_CCTRL_SU_SET( _reg, _val ) \ + ( ( ( _reg ) & L4STAT_CCTRL_SU_MASK ) >> L4STAT_CCTRL_SU_SHIFT ) +#define L4STAT_CCTRL_SU_SET( _reg, _val ) \ ( ( ( _reg ) & ~L4STAT_CCTRL_SU_MASK ) | \ - ( ( ( _val ) << L4STAT_CCTRL_SU_SHIFT ) & \ - L4STAT_CCTRL_SU_MASK ) ) + ( ( ( _val ) << L4STAT_CCTRL_SU_SHIFT ) & L4STAT_CCTRL_SU_MASK ) ) #define L4STAT_CCTRL_SU( _val ) \ - ( ( ( _val ) << L4STAT_CCTRL_SU_SHIFT ) & \ - L4STAT_CCTRL_SU_MASK ) + ( ( ( _val ) << L4STAT_CCTRL_SU_SHIFT ) & L4STAT_CCTRL_SU_MASK ) #define L4STAT_CCTRL_CL 0x2000U #define L4STAT_CCTRL_EN 0x1000U #define L4STAT_CCTRL_EVENT_ID_SHIFT 4 -#define L4STAT_CCTRL_EVENT_ID_MASK 0xff0U +#define L4STAT_CCTRL_EVENT_ID_MASK 0xff0U #define L4STAT_CCTRL_EVENT_ID_GET( _reg ) \ - ( ( ( _reg ) & L4STAT_CCTRL_EVENT_ID_MASK ) >> \ - L4STAT_CCTRL_EVENT_ID_SHIFT ) -#define L4STAT_CCTRL_EVENT_ID_SET( _reg, _val ) \ - ( ( ( _reg ) & ~L4STAT_CCTRL_EVENT_ID_MASK ) | \ + ( ( ( _reg ) & L4STAT_CCTRL_EVENT_ID_MASK ) >> L4STAT_CCTRL_EVENT_ID_SHIFT ) +#define L4STAT_CCTRL_EVENT_ID_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L4STAT_CCTRL_EVENT_ID_MASK ) | \ ( ( ( _val ) << L4STAT_CCTRL_EVENT_ID_SHIFT ) & \ L4STAT_CCTRL_EVENT_ID_MASK ) ) #define L4STAT_CCTRL_EVENT_ID( _val ) \ - ( ( ( _val ) << L4STAT_CCTRL_EVENT_ID_SHIFT ) & \ - L4STAT_CCTRL_EVENT_ID_MASK ) + ( ( ( _val ) << L4STAT_CCTRL_EVENT_ID_SHIFT ) & L4STAT_CCTRL_EVENT_ID_MASK ) #define L4STAT_CCTRL_CPU_AHBM_SHIFT 0 -#define L4STAT_CCTRL_CPU_AHBM_MASK 0xfU +#define L4STAT_CCTRL_CPU_AHBM_MASK 0xfU #define L4STAT_CCTRL_CPU_AHBM_GET( _reg ) \ - ( ( ( _reg ) & L4STAT_CCTRL_CPU_AHBM_MASK ) >> \ - L4STAT_CCTRL_CPU_AHBM_SHIFT ) -#define L4STAT_CCTRL_CPU_AHBM_SET( _reg, _val ) \ - ( ( ( _reg ) & ~L4STAT_CCTRL_CPU_AHBM_MASK ) | \ + ( ( ( _reg ) & L4STAT_CCTRL_CPU_AHBM_MASK ) >> L4STAT_CCTRL_CPU_AHBM_SHIFT ) +#define L4STAT_CCTRL_CPU_AHBM_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L4STAT_CCTRL_CPU_AHBM_MASK ) | \ ( ( ( _val ) << L4STAT_CCTRL_CPU_AHBM_SHIFT ) & \ L4STAT_CCTRL_CPU_AHBM_MASK ) ) #define L4STAT_CCTRL_CPU_AHBM( _val ) \ - ( ( ( _val ) << L4STAT_CCTRL_CPU_AHBM_SHIFT ) & \ - L4STAT_CCTRL_CPU_AHBM_MASK ) + ( ( ( _val ) << L4STAT_CCTRL_CPU_AHBM_SHIFT ) & L4STAT_CCTRL_CPU_AHBM_MASK ) /** @} */ @@ -199,17 +183,14 @@ extern "C" { */ #define L4STAT_CSVAL_CSVAL_SHIFT 0 -#define L4STAT_CSVAL_CSVAL_MASK 0xffffffffU +#define L4STAT_CSVAL_CSVAL_MASK 0xffffffffU #define L4STAT_CSVAL_CSVAL_GET( _reg ) \ - ( ( ( _reg ) & L4STAT_CSVAL_CSVAL_MASK ) >> \ - L4STAT_CSVAL_CSVAL_SHIFT ) -#define L4STAT_CSVAL_CSVAL_SET( _reg, _val ) \ + ( ( ( _reg ) & L4STAT_CSVAL_CSVAL_MASK ) >> L4STAT_CSVAL_CSVAL_SHIFT ) +#define L4STAT_CSVAL_CSVAL_SET( _reg, _val ) \ ( ( ( _reg ) & ~L4STAT_CSVAL_CSVAL_MASK ) | \ - ( ( ( _val ) << L4STAT_CSVAL_CSVAL_SHIFT ) & \ - L4STAT_CSVAL_CSVAL_MASK ) ) + ( ( ( _val ) << L4STAT_CSVAL_CSVAL_SHIFT ) & L4STAT_CSVAL_CSVAL_MASK ) ) #define L4STAT_CSVAL_CSVAL( _val ) \ - ( ( ( _val ) << L4STAT_CSVAL_CSVAL_SHIFT ) & \ - L4STAT_CSVAL_CSVAL_MASK ) + ( ( ( _val ) << L4STAT_CSVAL_CSVAL_SHIFT ) & L4STAT_CSVAL_CSVAL_MASK ) /** @} */ @@ -222,17 +203,15 @@ extern "C" { */ #define L4STAT_TSTAMP_TSTAMP_SHIFT 0 -#define L4STAT_TSTAMP_TSTAMP_MASK 0xffffffffU +#define L4STAT_TSTAMP_TSTAMP_MASK 0xffffffffU #define L4STAT_TSTAMP_TSTAMP_GET( _reg ) \ - ( ( ( _reg ) & L4STAT_TSTAMP_TSTAMP_MASK ) >> \ - L4STAT_TSTAMP_TSTAMP_SHIFT ) -#define L4STAT_TSTAMP_TSTAMP_SET( _reg, _val ) \ - ( ( ( _reg ) & ~L4STAT_TSTAMP_TSTAMP_MASK ) | \ + ( ( ( _reg ) & L4STAT_TSTAMP_TSTAMP_MASK ) >> L4STAT_TSTAMP_TSTAMP_SHIFT ) +#define L4STAT_TSTAMP_TSTAMP_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L4STAT_TSTAMP_TSTAMP_MASK ) | \ ( ( ( _val ) << L4STAT_TSTAMP_TSTAMP_SHIFT ) & \ L4STAT_TSTAMP_TSTAMP_MASK ) ) #define L4STAT_TSTAMP_TSTAMP( _val ) \ - ( ( ( _val ) << L4STAT_TSTAMP_TSTAMP_SHIFT ) & \ - L4STAT_TSTAMP_TSTAMP_MASK ) + ( ( ( _val ) << L4STAT_TSTAMP_TSTAMP_SHIFT ) & L4STAT_TSTAMP_TSTAMP_MASK ) /** @} */ diff --git a/bsps/include/grlib/l4stat.h b/bsps/include/grlib/l4stat.h index ddbde084ce..75c0f272f7 100644 --- a/bsps/include/grlib/l4stat.h +++ b/bsps/include/grlib/l4stat.h @@ -35,73 +35,78 @@ extern "C" { #endif -#define L4STAT_ERR_OK 0 -#define L4STAT_ERR_EINVAL -1 -#define L4STAT_ERR_ERROR -2 -#define L4STAT_ERR_TOOMANY -3 +#define L4STAT_ERR_OK 0 +#define L4STAT_ERR_EINVAL -1 +#define L4STAT_ERR_ERROR -2 +#define L4STAT_ERR_TOOMANY -3 #define L4STAT_ERR_IMPLEMENTED -4 /* Register L4STAT driver to Driver Manager */ -void l4stat_register_drv (void); +void l4stat_register_drv( void ); -extern int l4stat_counter_print(unsigned int counter); +extern int l4stat_counter_print( unsigned int counter ); /* * L4STAT CCTRL register fields */ -#define CCTRL_NCPU (0xf << CCTRL_NCPU_BIT) -#define CCTRL_NCNT_L3STAT (0x1ff << CCTRL_NCNT_BIT) -#define CCTRL_NCNT (0x1f << CCTRL_NCNT_BIT) -#define CCTRL_MC (0x1 << CCTRL_MC_BIT) -#define CCTRL_IA (0x1 << CCTRL_IA_BIT) -#define CCTRL_DS (0x1 << CCTRL_DS_BIT) -#define CCTRL_EE (0x1 << CCTRL_EE_BIT) -#define CCTRL_AE (0x1 << CCTRL_AE_BIT) -#define CCTRL_EL (0x1 << CCTRL_EL_BIT) -#define CCTRL_CD (0x1 << CCTRL_CD_BIT) -#define CCTRL_SU (0x3 << CCTRL_SU_BIT) -#define CCTRL_CL (0x1 << CCTRL_CL_BIT) -#define CCTRL_EN (0x1 << CCTRL_EN_BIT) -#define CCTRL_EVENTID (0xff << CCTRL_EVENTID_BIT) -#define CCTRL_CPUAHBM (0xf << CCTRL_CPUAHBM_BIT) +#define CCTRL_NCPU ( 0xf << CCTRL_NCPU_BIT ) +#define CCTRL_NCNT_L3STAT ( 0x1ff << CCTRL_NCNT_BIT ) +#define CCTRL_NCNT ( 0x1f << CCTRL_NCNT_BIT ) +#define CCTRL_MC ( 0x1 << CCTRL_MC_BIT ) +#define CCTRL_IA ( 0x1 << CCTRL_IA_BIT ) +#define CCTRL_DS ( 0x1 << CCTRL_DS_BIT ) +#define CCTRL_EE ( 0x1 << CCTRL_EE_BIT ) +#define CCTRL_AE ( 0x1 << CCTRL_AE_BIT ) +#define CCTRL_EL ( 0x1 << CCTRL_EL_BIT ) +#define CCTRL_CD ( 0x1 << CCTRL_CD_BIT ) +#define CCTRL_SU ( 0x3 << CCTRL_SU_BIT ) +#define CCTRL_CL ( 0x1 << CCTRL_CL_BIT ) +#define CCTRL_EN ( 0x1 << CCTRL_EN_BIT ) +#define CCTRL_EVENTID ( 0xff << CCTRL_EVENTID_BIT ) +#define CCTRL_CPUAHBM ( 0xf << CCTRL_CPUAHBM_BIT ) -#define CCTRL_NCPU_BIT 28 -#define CCTRL_NCNT_BIT 23 -#define CCTRL_MC_BIT 22 -#define CCTRL_IA_BIT 21 -#define CCTRL_DS_BIT 20 -#define CCTRL_EE_BIT 19 -#define CCTRL_AE_BIT 18 -#define CCTRL_EL_BIT 17 -#define CCTRL_CD_BIT 16 -#define CCTRL_SU_BIT 14 -#define CCTRL_CL_BIT 13 -#define CCTRL_EN_BIT 12 +#define CCTRL_NCPU_BIT 28 +#define CCTRL_NCNT_BIT 23 +#define CCTRL_MC_BIT 22 +#define CCTRL_IA_BIT 21 +#define CCTRL_DS_BIT 20 +#define CCTRL_EE_BIT 19 +#define CCTRL_AE_BIT 18 +#define CCTRL_EL_BIT 17 +#define CCTRL_CD_BIT 16 +#define CCTRL_SU_BIT 14 +#define CCTRL_CL_BIT 13 +#define CCTRL_EN_BIT 12 #define CCTRL_EVENTID_BIT 4 #define CCTRL_CPUAHBM_BIT 0 -#define L4STAT_OPTIONS_EVENT_LEVEL_ENABLE CCTRL_EL -#define L4STAT_OPTIONS_EVENT_LEVEL_DISABLE 0 -#define L4STAT_OPTIONS_MAXIMUM_DURATION CCTRL_CD -#define L4STAT_OPTIONS_SUPERVISOR_MODE_FILTER (0x1 << CCTRL_SU_BIT) -#define L4STAT_OPTIONS_USER_MODE_FILTER (0x2 << CCTRL_SU_BIT) -#define L4STAT_OPTIONS_NO_FILTER 0 -#define L4STAT_OPTIONS_CLEAR_ON_READ CCTRL_CL +#define L4STAT_OPTIONS_EVENT_LEVEL_ENABLE CCTRL_EL +#define L4STAT_OPTIONS_EVENT_LEVEL_DISABLE 0 +#define L4STAT_OPTIONS_MAXIMUM_DURATION CCTRL_CD +#define L4STAT_OPTIONS_SUPERVISOR_MODE_FILTER ( 0x1 << CCTRL_SU_BIT ) +#define L4STAT_OPTIONS_USER_MODE_FILTER ( 0x2 << CCTRL_SU_BIT ) +#define L4STAT_OPTIONS_NO_FILTER 0 +#define L4STAT_OPTIONS_CLEAR_ON_READ CCTRL_CL -extern int l4stat_counter_enable(unsigned int counter, int event, int cpu, int options); -extern int l4stat_counter_disable(unsigned int counter); -extern int l4stat_counter_set(unsigned int counter, uint32_t val); -extern int l4stat_counter_get(unsigned int counter, uint32_t *val); +extern int l4stat_counter_enable( + unsigned int counter, + int event, + int cpu, + int options +); +extern int l4stat_counter_disable( unsigned int counter ); +extern int l4stat_counter_set( unsigned int counter, uint32_t val ); +extern int l4stat_counter_get( unsigned int counter, uint32_t *val ); -static inline int l4stat_counter_clear(unsigned int counter) +static inline int l4stat_counter_clear( unsigned int counter ) { - return l4stat_counter_set(counter, 0); + return l4stat_counter_set( counter, 0 ); } -extern int l4stat_counter_max_set(unsigned int counter, uint32_t val); -extern int l4stat_counter_max_get(unsigned int counter, uint32_t *val); -extern int l4stat_tstamp_set(uint32_t val); -extern int l4stat_tstamp_get(uint32_t *val); +extern int l4stat_counter_max_set( unsigned int counter, uint32_t val ); +extern int l4stat_counter_max_get( unsigned int counter, uint32_t *val ); +extern int l4stat_tstamp_set( uint32_t val ); +extern int l4stat_tstamp_get( uint32_t *val ); #ifdef __cplusplus } diff --git a/bsps/include/grlib/mctrl.h b/bsps/include/grlib/mctrl.h index e2d7eadb43..aeb4c8477c 100644 --- a/bsps/include/grlib/mctrl.h +++ b/bsps/include/grlib/mctrl.h @@ -36,7 +36,7 @@ extern "C" { #endif /* Register MEMCTRL driver to Driver manager */ -void mctrl_register_drv (void); +void mctrl_register_drv( void ); #ifdef __cplusplus } diff --git a/bsps/include/grlib/memscrub-regs.h b/bsps/include/grlib/memscrub-regs.h index bfeacc7d20..d28e923855 100644 --- a/bsps/include/grlib/memscrub-regs.h +++ b/bsps/include/grlib/memscrub-regs.h @@ -82,30 +82,26 @@ extern "C" { */ #define MEMSCRUB_AHBS_CECNT_SHIFT 22 -#define MEMSCRUB_AHBS_CECNT_MASK 0xffc00000U +#define MEMSCRUB_AHBS_CECNT_MASK 0xffc00000U #define MEMSCRUB_AHBS_CECNT_GET( _reg ) \ - ( ( ( _reg ) & MEMSCRUB_AHBS_CECNT_MASK ) >> \ - MEMSCRUB_AHBS_CECNT_SHIFT ) -#define MEMSCRUB_AHBS_CECNT_SET( _reg, _val ) \ - ( ( ( _reg ) & ~MEMSCRUB_AHBS_CECNT_MASK ) | \ + ( ( ( _reg ) & MEMSCRUB_AHBS_CECNT_MASK ) >> MEMSCRUB_AHBS_CECNT_SHIFT ) +#define MEMSCRUB_AHBS_CECNT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MEMSCRUB_AHBS_CECNT_MASK ) | \ ( ( ( _val ) << MEMSCRUB_AHBS_CECNT_SHIFT ) & \ MEMSCRUB_AHBS_CECNT_MASK ) ) #define MEMSCRUB_AHBS_CECNT( _val ) \ - ( ( ( _val ) << MEMSCRUB_AHBS_CECNT_SHIFT ) & \ - MEMSCRUB_AHBS_CECNT_MASK ) + ( ( ( _val ) << MEMSCRUB_AHBS_CECNT_SHIFT ) & MEMSCRUB_AHBS_CECNT_MASK ) #define MEMSCRUB_AHBS_UECNT_SHIFT 14 -#define MEMSCRUB_AHBS_UECNT_MASK 0x3fc000U +#define MEMSCRUB_AHBS_UECNT_MASK 0x3fc000U #define MEMSCRUB_AHBS_UECNT_GET( _reg ) \ - ( ( ( _reg ) & MEMSCRUB_AHBS_UECNT_MASK ) >> \ - MEMSCRUB_AHBS_UECNT_SHIFT ) -#define MEMSCRUB_AHBS_UECNT_SET( _reg, _val ) \ - ( ( ( _reg ) & ~MEMSCRUB_AHBS_UECNT_MASK ) | \ + ( ( ( _reg ) & MEMSCRUB_AHBS_UECNT_MASK ) >> MEMSCRUB_AHBS_UECNT_SHIFT ) +#define MEMSCRUB_AHBS_UECNT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MEMSCRUB_AHBS_UECNT_MASK ) | \ ( ( ( _val ) << MEMSCRUB_AHBS_UECNT_SHIFT ) & \ MEMSCRUB_AHBS_UECNT_MASK ) ) #define MEMSCRUB_AHBS_UECNT( _val ) \ - ( ( ( _val ) << MEMSCRUB_AHBS_UECNT_SHIFT ) & \ - MEMSCRUB_AHBS_UECNT_MASK ) + ( ( ( _val ) << MEMSCRUB_AHBS_UECNT_SHIFT ) & MEMSCRUB_AHBS_UECNT_MASK ) #define MEMSCRUB_AHBS_DONE 0x2000U @@ -120,30 +116,26 @@ extern "C" { #define MEMSCRUB_AHBS_HWRITE 0x80U #define MEMSCRUB_AHBS_HMASTER_SHIFT 3 -#define MEMSCRUB_AHBS_HMASTER_MASK 0x78U +#define MEMSCRUB_AHBS_HMASTER_MASK 0x78U #define MEMSCRUB_AHBS_HMASTER_GET( _reg ) \ - ( ( ( _reg ) & MEMSCRUB_AHBS_HMASTER_MASK ) >> \ - MEMSCRUB_AHBS_HMASTER_SHIFT ) -#define MEMSCRUB_AHBS_HMASTER_SET( _reg, _val ) \ - ( ( ( _reg ) & ~MEMSCRUB_AHBS_HMASTER_MASK ) | \ + ( ( ( _reg ) & MEMSCRUB_AHBS_HMASTER_MASK ) >> MEMSCRUB_AHBS_HMASTER_SHIFT ) +#define MEMSCRUB_AHBS_HMASTER_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MEMSCRUB_AHBS_HMASTER_MASK ) | \ ( ( ( _val ) << MEMSCRUB_AHBS_HMASTER_SHIFT ) & \ MEMSCRUB_AHBS_HMASTER_MASK ) ) #define MEMSCRUB_AHBS_HMASTER( _val ) \ - ( ( ( _val ) << MEMSCRUB_AHBS_HMASTER_SHIFT ) & \ - MEMSCRUB_AHBS_HMASTER_MASK ) + ( ( ( _val ) << MEMSCRUB_AHBS_HMASTER_SHIFT ) & MEMSCRUB_AHBS_HMASTER_MASK ) #define MEMSCRUB_AHBS_HSIZE_SHIFT 0 -#define MEMSCRUB_AHBS_HSIZE_MASK 0x7U +#define MEMSCRUB_AHBS_HSIZE_MASK 0x7U #define MEMSCRUB_AHBS_HSIZE_GET( _reg ) \ - ( ( ( _reg ) & MEMSCRUB_AHBS_HSIZE_MASK ) >> \ - MEMSCRUB_AHBS_HSIZE_SHIFT ) -#define MEMSCRUB_AHBS_HSIZE_SET( _reg, _val ) \ - ( ( ( _reg ) & ~MEMSCRUB_AHBS_HSIZE_MASK ) | \ + ( ( ( _reg ) & MEMSCRUB_AHBS_HSIZE_MASK ) >> MEMSCRUB_AHBS_HSIZE_SHIFT ) +#define MEMSCRUB_AHBS_HSIZE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MEMSCRUB_AHBS_HSIZE_MASK ) | \ ( ( ( _val ) << MEMSCRUB_AHBS_HSIZE_SHIFT ) & \ MEMSCRUB_AHBS_HSIZE_MASK ) ) #define MEMSCRUB_AHBS_HSIZE( _val ) \ - ( ( ( _val ) << MEMSCRUB_AHBS_HSIZE_SHIFT ) & \ - MEMSCRUB_AHBS_HSIZE_MASK ) + ( ( ( _val ) << MEMSCRUB_AHBS_HSIZE_SHIFT ) & MEMSCRUB_AHBS_HSIZE_MASK ) /** @} */ @@ -157,15 +149,15 @@ extern "C" { */ #define MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_SHIFT 0 -#define MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_MASK 0xffffffffU -#define MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_GET( _reg ) \ +#define MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_MASK 0xffffffffU +#define MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_GET( _reg ) \ ( ( ( _reg ) & MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_MASK ) >> \ MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_SHIFT ) -#define MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_SET( _reg, _val ) \ - ( ( ( _reg ) & ~MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_MASK ) | \ +#define MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_MASK ) | \ ( ( ( _val ) << MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_SHIFT ) & \ MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_MASK ) ) -#define MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS( _val ) \ +#define MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS( _val ) \ ( ( ( _val ) << MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_SHIFT ) & \ MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_MASK ) @@ -181,28 +173,28 @@ extern "C" { */ #define MEMSCRUB_AHBERC_CECNTT_SHIFT 22 -#define MEMSCRUB_AHBERC_CECNTT_MASK 0xffc00000U -#define MEMSCRUB_AHBERC_CECNTT_GET( _reg ) \ +#define MEMSCRUB_AHBERC_CECNTT_MASK 0xffc00000U +#define MEMSCRUB_AHBERC_CECNTT_GET( _reg ) \ ( ( ( _reg ) & MEMSCRUB_AHBERC_CECNTT_MASK ) >> \ MEMSCRUB_AHBERC_CECNTT_SHIFT ) -#define MEMSCRUB_AHBERC_CECNTT_SET( _reg, _val ) \ - ( ( ( _reg ) & ~MEMSCRUB_AHBERC_CECNTT_MASK ) | \ +#define MEMSCRUB_AHBERC_CECNTT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MEMSCRUB_AHBERC_CECNTT_MASK ) | \ ( ( ( _val ) << MEMSCRUB_AHBERC_CECNTT_SHIFT ) & \ MEMSCRUB_AHBERC_CECNTT_MASK ) ) -#define MEMSCRUB_AHBERC_CECNTT( _val ) \ +#define MEMSCRUB_AHBERC_CECNTT( _val ) \ ( ( ( _val ) << MEMSCRUB_AHBERC_CECNTT_SHIFT ) & \ MEMSCRUB_AHBERC_CECNTT_MASK ) #define MEMSCRUB_AHBERC_UECNTT_SHIFT 14 -#define MEMSCRUB_AHBERC_UECNTT_MASK 0x3fc000U -#define MEMSCRUB_AHBERC_UECNTT_GET( _reg ) \ +#define MEMSCRUB_AHBERC_UECNTT_MASK 0x3fc000U +#define MEMSCRUB_AHBERC_UECNTT_GET( _reg ) \ ( ( ( _reg ) & MEMSCRUB_AHBERC_UECNTT_MASK ) >> \ MEMSCRUB_AHBERC_UECNTT_SHIFT ) -#define MEMSCRUB_AHBERC_UECNTT_SET( _reg, _val ) \ - ( ( ( _reg ) & ~MEMSCRUB_AHBERC_UECNTT_MASK ) | \ +#define MEMSCRUB_AHBERC_UECNTT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MEMSCRUB_AHBERC_UECNTT_MASK ) | \ ( ( ( _val ) << MEMSCRUB_AHBERC_UECNTT_SHIFT ) & \ MEMSCRUB_AHBERC_UECNTT_MASK ) ) -#define MEMSCRUB_AHBERC_UECNTT( _val ) \ +#define MEMSCRUB_AHBERC_UECNTT( _val ) \ ( ( ( _val ) << MEMSCRUB_AHBERC_UECNTT_SHIFT ) & \ MEMSCRUB_AHBERC_UECNTT_MASK ) @@ -221,43 +213,43 @@ extern "C" { */ #define MEMSCRUB_STAT_RUNCOUNT_SHIFT 22 -#define MEMSCRUB_STAT_RUNCOUNT_MASK 0xffc00000U -#define MEMSCRUB_STAT_RUNCOUNT_GET( _reg ) \ +#define MEMSCRUB_STAT_RUNCOUNT_MASK 0xffc00000U +#define MEMSCRUB_STAT_RUNCOUNT_GET( _reg ) \ ( ( ( _reg ) & MEMSCRUB_STAT_RUNCOUNT_MASK ) >> \ MEMSCRUB_STAT_RUNCOUNT_SHIFT ) -#define MEMSCRUB_STAT_RUNCOUNT_SET( _reg, _val ) \ - ( ( ( _reg ) & ~MEMSCRUB_STAT_RUNCOUNT_MASK ) | \ +#define MEMSCRUB_STAT_RUNCOUNT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MEMSCRUB_STAT_RUNCOUNT_MASK ) | \ ( ( ( _val ) << MEMSCRUB_STAT_RUNCOUNT_SHIFT ) & \ MEMSCRUB_STAT_RUNCOUNT_MASK ) ) -#define MEMSCRUB_STAT_RUNCOUNT( _val ) \ +#define MEMSCRUB_STAT_RUNCOUNT( _val ) \ ( ( ( _val ) << MEMSCRUB_STAT_RUNCOUNT_SHIFT ) & \ MEMSCRUB_STAT_RUNCOUNT_MASK ) #define MEMSCRUB_STAT_BLKCOUNT_SHIFT 14 -#define MEMSCRUB_STAT_BLKCOUNT_MASK 0x3fc000U -#define MEMSCRUB_STAT_BLKCOUNT_GET( _reg ) \ +#define MEMSCRUB_STAT_BLKCOUNT_MASK 0x3fc000U +#define MEMSCRUB_STAT_BLKCOUNT_GET( _reg ) \ ( ( ( _reg ) & MEMSCRUB_STAT_BLKCOUNT_MASK ) >> \ MEMSCRUB_STAT_BLKCOUNT_SHIFT ) -#define MEMSCRUB_STAT_BLKCOUNT_SET( _reg, _val ) \ - ( ( ( _reg ) & ~MEMSCRUB_STAT_BLKCOUNT_MASK ) | \ +#define MEMSCRUB_STAT_BLKCOUNT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MEMSCRUB_STAT_BLKCOUNT_MASK ) | \ ( ( ( _val ) << MEMSCRUB_STAT_BLKCOUNT_SHIFT ) & \ MEMSCRUB_STAT_BLKCOUNT_MASK ) ) -#define MEMSCRUB_STAT_BLKCOUNT( _val ) \ +#define MEMSCRUB_STAT_BLKCOUNT( _val ) \ ( ( ( _val ) << MEMSCRUB_STAT_BLKCOUNT_SHIFT ) & \ MEMSCRUB_STAT_BLKCOUNT_MASK ) #define MEMSCRUB_STAT_DONE 0x2000U #define MEMSCRUB_STAT_BURSTLEN_SHIFT 1 -#define MEMSCRUB_STAT_BURSTLEN_MASK 0x1eU -#define MEMSCRUB_STAT_BURSTLEN_GET( _reg ) \ +#define MEMSCRUB_STAT_BURSTLEN_MASK 0x1eU +#define MEMSCRUB_STAT_BURSTLEN_GET( _reg ) \ ( ( ( _reg ) & MEMSCRUB_STAT_BURSTLEN_MASK ) >> \ MEMSCRUB_STAT_BURSTLEN_SHIFT ) -#define MEMSCRUB_STAT_BURSTLEN_SET( _reg, _val ) \ - ( ( ( _reg ) & ~MEMSCRUB_STAT_BURSTLEN_MASK ) | \ +#define MEMSCRUB_STAT_BURSTLEN_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MEMSCRUB_STAT_BURSTLEN_MASK ) | \ ( ( ( _val ) << MEMSCRUB_STAT_BURSTLEN_SHIFT ) & \ MEMSCRUB_STAT_BURSTLEN_MASK ) ) -#define MEMSCRUB_STAT_BURSTLEN( _val ) \ +#define MEMSCRUB_STAT_BURSTLEN( _val ) \ ( ( ( _val ) << MEMSCRUB_STAT_BURSTLEN_SHIFT ) & \ MEMSCRUB_STAT_BURSTLEN_MASK ) @@ -274,17 +266,15 @@ extern "C" { */ #define MEMSCRUB_CONFIG_DELAY_SHIFT 8 -#define MEMSCRUB_CONFIG_DELAY_MASK 0xff00U +#define MEMSCRUB_CONFIG_DELAY_MASK 0xff00U #define MEMSCRUB_CONFIG_DELAY_GET( _reg ) \ - ( ( ( _reg ) & MEMSCRUB_CONFIG_DELAY_MASK ) >> \ - MEMSCRUB_CONFIG_DELAY_SHIFT ) -#define MEMSCRUB_CONFIG_DELAY_SET( _reg, _val ) \ - ( ( ( _reg ) & ~MEMSCRUB_CONFIG_DELAY_MASK ) | \ + ( ( ( _reg ) & MEMSCRUB_CONFIG_DELAY_MASK ) >> MEMSCRUB_CONFIG_DELAY_SHIFT ) +#define MEMSCRUB_CONFIG_DELAY_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MEMSCRUB_CONFIG_DELAY_MASK ) | \ ( ( ( _val ) << MEMSCRUB_CONFIG_DELAY_SHIFT ) & \ MEMSCRUB_CONFIG_DELAY_MASK ) ) #define MEMSCRUB_CONFIG_DELAY( _val ) \ - ( ( ( _val ) << MEMSCRUB_CONFIG_DELAY_SHIFT ) & \ - MEMSCRUB_CONFIG_DELAY_MASK ) + ( ( ( _val ) << MEMSCRUB_CONFIG_DELAY_SHIFT ) & MEMSCRUB_CONFIG_DELAY_MASK ) #define MEMSCRUB_CONFIG_IRQD 0x80U @@ -293,17 +283,15 @@ extern "C" { #define MEMSCRUB_CONFIG_LOOP 0x10U #define MEMSCRUB_CONFIG_MODE_SHIFT 2 -#define MEMSCRUB_CONFIG_MODE_MASK 0xcU +#define MEMSCRUB_CONFIG_MODE_MASK 0xcU #define MEMSCRUB_CONFIG_MODE_GET( _reg ) \ - ( ( ( _reg ) & MEMSCRUB_CONFIG_MODE_MASK ) >> \ - MEMSCRUB_CONFIG_MODE_SHIFT ) -#define MEMSCRUB_CONFIG_MODE_SET( _reg, _val ) \ - ( ( ( _reg ) & ~MEMSCRUB_CONFIG_MODE_MASK ) | \ + ( ( ( _reg ) & MEMSCRUB_CONFIG_MODE_MASK ) >> MEMSCRUB_CONFIG_MODE_SHIFT ) +#define MEMSCRUB_CONFIG_MODE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MEMSCRUB_CONFIG_MODE_MASK ) | \ ( ( ( _val ) << MEMSCRUB_CONFIG_MODE_SHIFT ) & \ MEMSCRUB_CONFIG_MODE_MASK ) ) #define MEMSCRUB_CONFIG_MODE( _val ) \ - ( ( ( _val ) << MEMSCRUB_CONFIG_MODE_SHIFT ) & \ - MEMSCRUB_CONFIG_MODE_MASK ) + ( ( ( _val ) << MEMSCRUB_CONFIG_MODE_SHIFT ) & MEMSCRUB_CONFIG_MODE_MASK ) #define MEMSCRUB_CONFIG_ES 0x2U @@ -320,15 +308,15 @@ extern "C" { */ #define MEMSCRUB_RANGEL_RLADDR_SHIFT 0 -#define MEMSCRUB_RANGEL_RLADDR_MASK 0xffffffffU -#define MEMSCRUB_RANGEL_RLADDR_GET( _reg ) \ +#define MEMSCRUB_RANGEL_RLADDR_MASK 0xffffffffU +#define MEMSCRUB_RANGEL_RLADDR_GET( _reg ) \ ( ( ( _reg ) & MEMSCRUB_RANGEL_RLADDR_MASK ) >> \ MEMSCRUB_RANGEL_RLADDR_SHIFT ) -#define MEMSCRUB_RANGEL_RLADDR_SET( _reg, _val ) \ - ( ( ( _reg ) & ~MEMSCRUB_RANGEL_RLADDR_MASK ) | \ +#define MEMSCRUB_RANGEL_RLADDR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MEMSCRUB_RANGEL_RLADDR_MASK ) | \ ( ( ( _val ) << MEMSCRUB_RANGEL_RLADDR_SHIFT ) & \ MEMSCRUB_RANGEL_RLADDR_MASK ) ) -#define MEMSCRUB_RANGEL_RLADDR( _val ) \ +#define MEMSCRUB_RANGEL_RLADDR( _val ) \ ( ( ( _val ) << MEMSCRUB_RANGEL_RLADDR_SHIFT ) & \ MEMSCRUB_RANGEL_RLADDR_MASK ) @@ -344,15 +332,15 @@ extern "C" { */ #define MEMSCRUB_RANGEH_RHADDR_SHIFT 0 -#define MEMSCRUB_RANGEH_RHADDR_MASK 0xffffffffU -#define MEMSCRUB_RANGEH_RHADDR_GET( _reg ) \ +#define MEMSCRUB_RANGEH_RHADDR_MASK 0xffffffffU +#define MEMSCRUB_RANGEH_RHADDR_GET( _reg ) \ ( ( ( _reg ) & MEMSCRUB_RANGEH_RHADDR_MASK ) >> \ MEMSCRUB_RANGEH_RHADDR_SHIFT ) -#define MEMSCRUB_RANGEH_RHADDR_SET( _reg, _val ) \ - ( ( ( _reg ) & ~MEMSCRUB_RANGEH_RHADDR_MASK ) | \ +#define MEMSCRUB_RANGEH_RHADDR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MEMSCRUB_RANGEH_RHADDR_MASK ) | \ ( ( ( _val ) << MEMSCRUB_RANGEH_RHADDR_SHIFT ) & \ MEMSCRUB_RANGEH_RHADDR_MASK ) ) -#define MEMSCRUB_RANGEH_RHADDR( _val ) \ +#define MEMSCRUB_RANGEH_RHADDR( _val ) \ ( ( ( _val ) << MEMSCRUB_RANGEH_RHADDR_SHIFT ) & \ MEMSCRUB_RANGEH_RHADDR_MASK ) @@ -367,17 +355,15 @@ extern "C" { */ #define MEMSCRUB_POS_POSITION_SHIFT 0 -#define MEMSCRUB_POS_POSITION_MASK 0xffffffffU +#define MEMSCRUB_POS_POSITION_MASK 0xffffffffU #define MEMSCRUB_POS_POSITION_GET( _reg ) \ - ( ( ( _reg ) & MEMSCRUB_POS_POSITION_MASK ) >> \ - MEMSCRUB_POS_POSITION_SHIFT ) -#define MEMSCRUB_POS_POSITION_SET( _reg, _val ) \ - ( ( ( _reg ) & ~MEMSCRUB_POS_POSITION_MASK ) | \ + ( ( ( _reg ) & MEMSCRUB_POS_POSITION_MASK ) >> MEMSCRUB_POS_POSITION_SHIFT ) +#define MEMSCRUB_POS_POSITION_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MEMSCRUB_POS_POSITION_MASK ) | \ ( ( ( _val ) << MEMSCRUB_POS_POSITION_SHIFT ) & \ MEMSCRUB_POS_POSITION_MASK ) ) #define MEMSCRUB_POS_POSITION( _val ) \ - ( ( ( _val ) << MEMSCRUB_POS_POSITION_SHIFT ) & \ - MEMSCRUB_POS_POSITION_MASK ) + ( ( ( _val ) << MEMSCRUB_POS_POSITION_SHIFT ) & MEMSCRUB_POS_POSITION_MASK ) /** @} */ @@ -390,30 +376,26 @@ extern "C" { */ #define MEMSCRUB_ETHRES_RECT_SHIFT 22 -#define MEMSCRUB_ETHRES_RECT_MASK 0xffc00000U +#define MEMSCRUB_ETHRES_RECT_MASK 0xffc00000U #define MEMSCRUB_ETHRES_RECT_GET( _reg ) \ - ( ( ( _reg ) & MEMSCRUB_ETHRES_RECT_MASK ) >> \ - MEMSCRUB_ETHRES_RECT_SHIFT ) -#define MEMSCRUB_ETHRES_RECT_SET( _reg, _val ) \ - ( ( ( _reg ) & ~MEMSCRUB_ETHRES_RECT_MASK ) | \ + ( ( ( _reg ) & MEMSCRUB_ETHRES_RECT_MASK ) >> MEMSCRUB_ETHRES_RECT_SHIFT ) +#define MEMSCRUB_ETHRES_RECT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MEMSCRUB_ETHRES_RECT_MASK ) | \ ( ( ( _val ) << MEMSCRUB_ETHRES_RECT_SHIFT ) & \ MEMSCRUB_ETHRES_RECT_MASK ) ) #define MEMSCRUB_ETHRES_RECT( _val ) \ - ( ( ( _val ) << MEMSCRUB_ETHRES_RECT_SHIFT ) & \ - MEMSCRUB_ETHRES_RECT_MASK ) + ( ( ( _val ) << MEMSCRUB_ETHRES_RECT_SHIFT ) & MEMSCRUB_ETHRES_RECT_MASK ) #define MEMSCRUB_ETHRES_BECT_SHIFT 14 -#define MEMSCRUB_ETHRES_BECT_MASK 0x3fc000U +#define MEMSCRUB_ETHRES_BECT_MASK 0x3fc000U #define MEMSCRUB_ETHRES_BECT_GET( _reg ) \ - ( ( ( _reg ) & MEMSCRUB_ETHRES_BECT_MASK ) >> \ - MEMSCRUB_ETHRES_BECT_SHIFT ) -#define MEMSCRUB_ETHRES_BECT_SET( _reg, _val ) \ - ( ( ( _reg ) & ~MEMSCRUB_ETHRES_BECT_MASK ) | \ + ( ( ( _reg ) & MEMSCRUB_ETHRES_BECT_MASK ) >> MEMSCRUB_ETHRES_BECT_SHIFT ) +#define MEMSCRUB_ETHRES_BECT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MEMSCRUB_ETHRES_BECT_MASK ) | \ ( ( ( _val ) << MEMSCRUB_ETHRES_BECT_SHIFT ) & \ MEMSCRUB_ETHRES_BECT_MASK ) ) #define MEMSCRUB_ETHRES_BECT( _val ) \ - ( ( ( _val ) << MEMSCRUB_ETHRES_BECT_SHIFT ) & \ - MEMSCRUB_ETHRES_BECT_MASK ) + ( ( ( _val ) << MEMSCRUB_ETHRES_BECT_SHIFT ) & MEMSCRUB_ETHRES_BECT_MASK ) #define MEMSCRUB_ETHRES_RECTE 0x2U @@ -430,17 +412,14 @@ extern "C" { */ #define MEMSCRUB_INIT_DATA_SHIFT 0 -#define MEMSCRUB_INIT_DATA_MASK 0xffffffffU +#define MEMSCRUB_INIT_DATA_MASK 0xffffffffU #define MEMSCRUB_INIT_DATA_GET( _reg ) \ - ( ( ( _reg ) & MEMSCRUB_INIT_DATA_MASK ) >> \ - MEMSCRUB_INIT_DATA_SHIFT ) -#define MEMSCRUB_INIT_DATA_SET( _reg, _val ) \ + ( ( ( _reg ) & MEMSCRUB_INIT_DATA_MASK ) >> MEMSCRUB_INIT_DATA_SHIFT ) +#define MEMSCRUB_INIT_DATA_SET( _reg, _val ) \ ( ( ( _reg ) & ~MEMSCRUB_INIT_DATA_MASK ) | \ - ( ( ( _val ) << MEMSCRUB_INIT_DATA_SHIFT ) & \ - MEMSCRUB_INIT_DATA_MASK ) ) + ( ( ( _val ) << MEMSCRUB_INIT_DATA_SHIFT ) & MEMSCRUB_INIT_DATA_MASK ) ) #define MEMSCRUB_INIT_DATA( _val ) \ - ( ( ( _val ) << MEMSCRUB_INIT_DATA_SHIFT ) & \ - MEMSCRUB_INIT_DATA_MASK ) + ( ( ( _val ) << MEMSCRUB_INIT_DATA_SHIFT ) & MEMSCRUB_INIT_DATA_MASK ) /** @} */ @@ -454,15 +433,15 @@ extern "C" { */ #define MEMSCRUB_RANGEL2_RLADDR_SHIFT 0 -#define MEMSCRUB_RANGEL2_RLADDR_MASK 0xffffffffU -#define MEMSCRUB_RANGEL2_RLADDR_GET( _reg ) \ +#define MEMSCRUB_RANGEL2_RLADDR_MASK 0xffffffffU +#define MEMSCRUB_RANGEL2_RLADDR_GET( _reg ) \ ( ( ( _reg ) & MEMSCRUB_RANGEL2_RLADDR_MASK ) >> \ MEMSCRUB_RANGEL2_RLADDR_SHIFT ) -#define MEMSCRUB_RANGEL2_RLADDR_SET( _reg, _val ) \ - ( ( ( _reg ) & ~MEMSCRUB_RANGEL2_RLADDR_MASK ) | \ +#define MEMSCRUB_RANGEL2_RLADDR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MEMSCRUB_RANGEL2_RLADDR_MASK ) | \ ( ( ( _val ) << MEMSCRUB_RANGEL2_RLADDR_SHIFT ) & \ MEMSCRUB_RANGEL2_RLADDR_MASK ) ) -#define MEMSCRUB_RANGEL2_RLADDR( _val ) \ +#define MEMSCRUB_RANGEL2_RLADDR( _val ) \ ( ( ( _val ) << MEMSCRUB_RANGEL2_RLADDR_SHIFT ) & \ MEMSCRUB_RANGEL2_RLADDR_MASK ) @@ -478,15 +457,15 @@ extern "C" { */ #define MEMSCRUB_RANGEH2_RHADDR_SHIFT 0 -#define MEMSCRUB_RANGEH2_RHADDR_MASK 0xffffffffU -#define MEMSCRUB_RANGEH2_RHADDR_GET( _reg ) \ +#define MEMSCRUB_RANGEH2_RHADDR_MASK 0xffffffffU +#define MEMSCRUB_RANGEH2_RHADDR_GET( _reg ) \ ( ( ( _reg ) & MEMSCRUB_RANGEH2_RHADDR_MASK ) >> \ MEMSCRUB_RANGEH2_RHADDR_SHIFT ) -#define MEMSCRUB_RANGEH2_RHADDR_SET( _reg, _val ) \ - ( ( ( _reg ) & ~MEMSCRUB_RANGEH2_RHADDR_MASK ) | \ +#define MEMSCRUB_RANGEH2_RHADDR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MEMSCRUB_RANGEH2_RHADDR_MASK ) | \ ( ( ( _val ) << MEMSCRUB_RANGEH2_RHADDR_SHIFT ) & \ MEMSCRUB_RANGEH2_RHADDR_MASK ) ) -#define MEMSCRUB_RANGEH2_RHADDR( _val ) \ +#define MEMSCRUB_RANGEH2_RHADDR( _val ) \ ( ( ( _val ) << MEMSCRUB_RANGEH2_RHADDR_SHIFT ) & \ MEMSCRUB_RANGEH2_RHADDR_MASK ) diff --git a/bsps/include/grlib/memscrub.h b/bsps/include/grlib/memscrub.h index 84919927c3..321b14c318 100644 --- a/bsps/include/grlib/memscrub.h +++ b/bsps/include/grlib/memscrub.h @@ -36,55 +36,55 @@ extern "C" { #endif -#define MEMSCRUB_ERR_OK 0 +#define MEMSCRUB_ERR_OK 0 #define MEMSCRUB_ERR_EINVAL -1 -#define MEMSCRUB_ERR_ERROR -2 +#define MEMSCRUB_ERR_ERROR -2 -extern void memscrub_register_drv(void); +extern void memscrub_register_drv( void ); /* * MEMORYSCRUBBER CONFIG register fields */ #define CONFIG_DELAY_BIT 8 -#define CONFIG_IRQD_BIT 7 -#define CONFIG_SERA_BIT 5 -#define CONFIG_LOOP_BIT 4 -#define CONFIG_MODE_BIT 2 -#define CONFIG_ES_BIT 1 -#define CONFIG_SCEN_BIT 0 +#define CONFIG_IRQD_BIT 7 +#define CONFIG_SERA_BIT 5 +#define CONFIG_LOOP_BIT 4 +#define CONFIG_MODE_BIT 2 +#define CONFIG_ES_BIT 1 +#define CONFIG_SCEN_BIT 0 -#define CONFIG_DELAY (0xff << CONFIG_DELAY_BIT) -#define CONFIG_IRQD (0x1 << CONFIG_IRQD_BIT) -#define CONFIG_SERA (0x1 << CONFIG_SERA_BIT) -#define CONFIG_LOOP (0x1 << CONFIG_LOOP_BIT) -#define CONFIG_MODE (0x3 << CONFIG_MODE_BIT) -#define CONFIG_ES (0x1 << CONFIG_ES_BIT) -#define CONFIG_SCEN (0x1 << CONFIG_SCEN_BIT) -#define CONFIG_MODE_SCRUB (0x0 << CONFIG_MODE_BIT) -#define CONFIG_MODE_REGEN (0x1 << CONFIG_MODE_BIT) -#define CONFIG_MODE_INIT (0x2 << CONFIG_MODE_BIT) +#define CONFIG_DELAY ( 0xff << CONFIG_DELAY_BIT ) +#define CONFIG_IRQD ( 0x1 << CONFIG_IRQD_BIT ) +#define CONFIG_SERA ( 0x1 << CONFIG_SERA_BIT ) +#define CONFIG_LOOP ( 0x1 << CONFIG_LOOP_BIT ) +#define CONFIG_MODE ( 0x3 << CONFIG_MODE_BIT ) +#define CONFIG_ES ( 0x1 << CONFIG_ES_BIT ) +#define CONFIG_SCEN ( 0x1 << CONFIG_SCEN_BIT ) +#define CONFIG_MODE_SCRUB ( 0x0 << CONFIG_MODE_BIT ) +#define CONFIG_MODE_REGEN ( 0x1 << CONFIG_MODE_BIT ) +#define CONFIG_MODE_INIT ( 0x2 << CONFIG_MODE_BIT ) -#define MEMSCRUB_OPTIONS_INTERRUPTDONE_ENABLE CONFIG_IRQD -#define MEMSCRUB_OPTIONS_INTERRUPTDONE_DISABLE 0 -#define MEMSCRUB_OPTIONS_EXTERNALSTART_ENABLE CONFIG_ES -#define MEMSCRUB_OPTIONS_EXTERNALSTART_DISABLE 0 -#define MEMSCRUB_OPTIONS_LOOPMODE_ENABLE CONFIG_LOOP -#define MEMSCRUB_OPTIONS_LOOPMODE_DISABLE 0 -#define MEMSCRUB_OPTIONS_SECONDARY_MEMRANGE_ENABLE CONFIG_SERA +#define MEMSCRUB_OPTIONS_INTERRUPTDONE_ENABLE CONFIG_IRQD +#define MEMSCRUB_OPTIONS_INTERRUPTDONE_DISABLE 0 +#define MEMSCRUB_OPTIONS_EXTERNALSTART_ENABLE CONFIG_ES +#define MEMSCRUB_OPTIONS_EXTERNALSTART_DISABLE 0 +#define MEMSCRUB_OPTIONS_LOOPMODE_ENABLE CONFIG_LOOP +#define MEMSCRUB_OPTIONS_LOOPMODE_DISABLE 0 +#define MEMSCRUB_OPTIONS_SECONDARY_MEMRANGE_ENABLE CONFIG_SERA #define MEMSCRUB_OPTIONS_SECONDARY_MEMRANGE_DISABLE 0 /* Scrubbing modes */ -extern int memscrub_init_start(uint32_t value, uint8_t delay, int options); -extern int memscrub_scrub_start(uint8_t delay, int options); -extern int memscrub_regen_start(uint8_t delay, int options); -extern int memscrub_stop(void); -extern int memscrub_active(void); +extern int memscrub_init_start( uint32_t value, uint8_t delay, int options ); +extern int memscrub_scrub_start( uint8_t delay, int options ); +extern int memscrub_regen_start( uint8_t delay, int options ); +extern int memscrub_stop( void ); +extern int memscrub_active( void ); /* Set/get memory ranges */ -extern int memscrub_range_set(uint32_t start, uint32_t end); -extern int memscrub_range_get(uint32_t * start, uint32_t * end); -extern int memscrub_secondary_range_set(uint32_t start, uint32_t end); -extern int memscrub_secondary_range_get(uint32_t * start, uint32_t * end); +extern int memscrub_range_set( uint32_t start, uint32_t end ); +extern int memscrub_range_get( uint32_t *start, uint32_t *end ); +extern int memscrub_secondary_range_set( uint32_t start, uint32_t end ); +extern int memscrub_secondary_range_get( uint32_t *start, uint32_t *end ); /* Interrupts */ /* MEMSCRUB Interrupts */ @@ -94,13 +94,20 @@ extern int memscrub_secondary_range_get(uint32_t * start, uint32_t * end); * ahbstatus - AHB status register of the MEMSCRUB core * status - status register of the MEMSCRUB core */ -typedef void (*memscrub_isr_t)(void *arg, uint32_t ahbaccess, - uint32_t ahbstatus, uint32_t scrubstatus); -extern int memscrub_isr_register(memscrub_isr_t isr, void * data); -extern int memscrub_isr_unregister(void); +typedef void ( *memscrub_isr_t )( + void *arg, + uint32_t ahbaccess, + uint32_t ahbstatus, + uint32_t scrubstatus +); +extern int memscrub_isr_register( memscrub_isr_t isr, void *data ); +extern int memscrub_isr_unregister( void ); -extern int memscrub_error_status(uint32_t *ahbaccess, uint32_t *ahbstatus, - uint32_t *scrubstatus); +extern int memscrub_error_status( + uint32_t *ahbaccess, + uint32_t *ahbstatus, + uint32_t *scrubstatus +); /* Set the different error thresholds. */ @@ -109,80 +116,83 @@ extern int memscrub_error_status(uint32_t *ahbaccess, uint32_t *ahbstatus, */ #define AHBS_CECNT_BIT 22 #define AHBS_UECNT_BIT 14 -#define AHBS_DONE_BIT 13 -#define AHBS_SEC_BIT 11 -#define AHBS_SBC_BIT 10 -#define AHBS_CE_BIT 9 -#define AHBS_NE_BIT 8 -#define AHBS_HW_BIT 7 -#define AHBS_HM_BIT 3 -#define AHBS_HS_BIT 0 +#define AHBS_DONE_BIT 13 +#define AHBS_SEC_BIT 11 +#define AHBS_SBC_BIT 10 +#define AHBS_CE_BIT 9 +#define AHBS_NE_BIT 8 +#define AHBS_HW_BIT 7 +#define AHBS_HM_BIT 3 +#define AHBS_HS_BIT 0 -#define AHBS_CECNT (0x3ff << AHBS_CECNT_BIT) -#define AHBS_UECNT (0xff << AHBS_UECNT_BIT) -#define AHBS_DONE (1 << AHBS_DONE_BIT) -#define AHBS_SEC (1 << AHBS_SEC_BIT) -#define AHBS_SBC (1 << AHBS_SBC_BIT) -#define AHBS_CE (1 << AHBS_CE_BIT) -#define AHBS_NE (1 << AHBS_NE_BIT) -#define AHBS_HW (1 << AHBS_HW_BIT) -#define AHBS_HM (0xf << AHBS_HM_BIT) -#define AHBS_HS (0x7 << AHBS_HS_BIT) +#define AHBS_CECNT ( 0x3ff << AHBS_CECNT_BIT ) +#define AHBS_UECNT ( 0xff << AHBS_UECNT_BIT ) +#define AHBS_DONE ( 1 << AHBS_DONE_BIT ) +#define AHBS_SEC ( 1 << AHBS_SEC_BIT ) +#define AHBS_SBC ( 1 << AHBS_SBC_BIT ) +#define AHBS_CE ( 1 << AHBS_CE_BIT ) +#define AHBS_NE ( 1 << AHBS_NE_BIT ) +#define AHBS_HW ( 1 << AHBS_HW_BIT ) +#define AHBS_HM ( 0xf << AHBS_HM_BIT ) +#define AHBS_HS ( 0x7 << AHBS_HS_BIT ) /* * MEMORYSCRUBBER STAT register fields */ #define STAT_RUNCOUNT_BIT 22 #define STAT_BLKCOUNT_BIT 14 -#define STAT_DONE_BIT 13 +#define STAT_DONE_BIT 13 #define STAT_BURSTLEN_BIT 1 -#define STAT_ACTIVE_BIT 0 +#define STAT_ACTIVE_BIT 0 -#define STAT_RUNCOUNT (0x3ff << STAT_RUNCOUNT_BIT) -#define STAT_BLKCOUNT (0xff << STAT_BLKCOUNT_BIT) -#define STAT_DONE (0x1 << STAT_DONE_BIT) -#define STAT_BURSTLEN (0xf << STAT_BURSTLEN_BIT) -#define STAT_ACTIVE (0x1 << STAT_ACTIVE_BIT) +#define STAT_RUNCOUNT ( 0x3ff << STAT_RUNCOUNT_BIT ) +#define STAT_BLKCOUNT ( 0xff << STAT_BLKCOUNT_BIT ) +#define STAT_DONE ( 0x1 << STAT_DONE_BIT ) +#define STAT_BURSTLEN ( 0xf << STAT_BURSTLEN_BIT ) +#define STAT_ACTIVE ( 0x1 << STAT_ACTIVE_BIT ) /* * MEMORYSCRUBBER AHBERC register fields */ #define AHBERC_CECNTT_BIT 22 #define AHBERC_UECNTT_BIT 14 -#define AHBERC_CECTE_BIT 1 -#define AHBERC_UECTE_BIT 0 +#define AHBERC_CECTE_BIT 1 +#define AHBERC_UECTE_BIT 0 -#define AHBERC_CECNTT (0x3ff << AHBERC_CECNTT_BIT) -#define AHBERC_UECNTT (0xff << AHBERC_UECNTT_BIT) -#define AHBERC_CECTE (0x1 << AHBERC_CECTE_BIT) -#define AHBERC_UECTE (0x1 << AHBERC_UECTE_BIT) +#define AHBERC_CECNTT ( 0x3ff << AHBERC_CECNTT_BIT ) +#define AHBERC_UECNTT ( 0xff << AHBERC_UECNTT_BIT ) +#define AHBERC_CECTE ( 0x1 << AHBERC_CECTE_BIT ) +#define AHBERC_UECTE ( 0x1 << AHBERC_UECTE_BIT ) /* * MEMORYSCRUBBER ETHRES register fields */ -#define ETHRES_RECT_BIT 22 -#define ETHRES_BECT_BIT 14 +#define ETHRES_RECT_BIT 22 +#define ETHRES_BECT_BIT 14 #define ETHRES_RECTE_BIT 1 #define ETHRES_BECTE_BIT 0 -#define ETHRES_RECT (0x3ff << ETHRES_RECT_BIT) -#define ETHRES_BECT (0xff << ETHRES_BECT_BIT) -#define ETHRES_RECTE (0x1 << ETHRES_RECTE_BIT) -#define ETHRES_BECTE (0x1 << ETHRES_BECTE_BIT) +#define ETHRES_RECT ( 0x3ff << ETHRES_RECT_BIT ) +#define ETHRES_BECT ( 0xff << ETHRES_BECT_BIT ) +#define ETHRES_RECTE ( 0x1 << ETHRES_RECTE_BIT ) +#define ETHRES_BECTE ( 0x1 << ETHRES_BECTE_BIT ) -#define MEMSCRUB_OPTIONS_AHBERROR_CORTHRES_ENABLE AHBERC_CECTE -#define MEMSCRUB_OPTIONS_AHBERROR_CORTHRES_DISABLE 0 -#define MEMSCRUB_OPTIONS_AHBERROR_UNCORTHRES_ENABLE AHBERC_UECTE -#define MEMSCRUB_OPTIONS_AHBERROR_UNCORTHRES_DISABLE 0 -#define MEMSCRUB_OPTIONS_SCRUBERROR_RUNTHRES_ENABLE ETHRES_RECTE -#define MEMSCRUB_OPTIONS_SCRUBERROR_RUNTHRES_DISABLE 0 -#define MEMSCRUB_OPTIONS_SCRUBERROR_BLOCKTHRES_ENABLE ETHRES_BECTE +#define MEMSCRUB_OPTIONS_AHBERROR_CORTHRES_ENABLE AHBERC_CECTE +#define MEMSCRUB_OPTIONS_AHBERROR_CORTHRES_DISABLE 0 +#define MEMSCRUB_OPTIONS_AHBERROR_UNCORTHRES_ENABLE AHBERC_UECTE +#define MEMSCRUB_OPTIONS_AHBERROR_UNCORTHRES_DISABLE 0 +#define MEMSCRUB_OPTIONS_SCRUBERROR_RUNTHRES_ENABLE ETHRES_RECTE +#define MEMSCRUB_OPTIONS_SCRUBERROR_RUNTHRES_DISABLE 0 +#define MEMSCRUB_OPTIONS_SCRUBERROR_BLOCKTHRES_ENABLE ETHRES_BECTE #define MEMSCRUB_OPTIONS_SCRUBERROR_BLOCKTHRES_DISABLE 0 -extern int memscrub_ahberror_setup(int uethres, int cethres, int options); -extern int memscrub_scruberror_setup(int blkthres, int runthres, - int options); +extern int memscrub_ahberror_setup( int uethres, int cethres, int options ); +extern int memscrub_scruberror_setup( + int blkthres, + int runthres, + int options +); -extern int memscrub_scrub_position(uint32_t * position); +extern int memscrub_scrub_position( uint32_t *position ); #ifdef __cplusplus } diff --git a/bsps/include/grlib/mmctrl-regs.h b/bsps/include/grlib/mmctrl-regs.h index 3e860ef96a..f35c729b22 100644 --- a/bsps/include/grlib/mmctrl-regs.h +++ b/bsps/include/grlib/mmctrl-regs.h @@ -87,75 +87,64 @@ extern "C" { #define MMCTRL_SDCFG1_TRP 0x40000000U #define MMCTRL_SDCFG1_TRFC_SHIFT 27 -#define MMCTRL_SDCFG1_TRFC_MASK 0x38000000U +#define MMCTRL_SDCFG1_TRFC_MASK 0x38000000U #define MMCTRL_SDCFG1_TRFC_GET( _reg ) \ - ( ( ( _reg ) & MMCTRL_SDCFG1_TRFC_MASK ) >> \ - MMCTRL_SDCFG1_TRFC_SHIFT ) -#define MMCTRL_SDCFG1_TRFC_SET( _reg, _val ) \ + ( ( ( _reg ) & MMCTRL_SDCFG1_TRFC_MASK ) >> MMCTRL_SDCFG1_TRFC_SHIFT ) +#define MMCTRL_SDCFG1_TRFC_SET( _reg, _val ) \ ( ( ( _reg ) & ~MMCTRL_SDCFG1_TRFC_MASK ) | \ - ( ( ( _val ) << MMCTRL_SDCFG1_TRFC_SHIFT ) & \ - MMCTRL_SDCFG1_TRFC_MASK ) ) + ( ( ( _val ) << MMCTRL_SDCFG1_TRFC_SHIFT ) & MMCTRL_SDCFG1_TRFC_MASK ) ) #define MMCTRL_SDCFG1_TRFC( _val ) \ - ( ( ( _val ) << MMCTRL_SDCFG1_TRFC_SHIFT ) & \ - MMCTRL_SDCFG1_TRFC_MASK ) + ( ( ( _val ) << MMCTRL_SDCFG1_TRFC_SHIFT ) & MMCTRL_SDCFG1_TRFC_MASK ) #define MMCTRL_SDCFG1_TC 0x4000000U #define MMCTRL_SDCFG1_BANKSZ_SHIFT 23 -#define MMCTRL_SDCFG1_BANKSZ_MASK 0x3800000U +#define MMCTRL_SDCFG1_BANKSZ_MASK 0x3800000U #define MMCTRL_SDCFG1_BANKSZ_GET( _reg ) \ - ( ( ( _reg ) & MMCTRL_SDCFG1_BANKSZ_MASK ) >> \ - MMCTRL_SDCFG1_BANKSZ_SHIFT ) -#define MMCTRL_SDCFG1_BANKSZ_SET( _reg, _val ) \ - ( ( ( _reg ) & ~MMCTRL_SDCFG1_BANKSZ_MASK ) | \ + ( ( ( _reg ) & MMCTRL_SDCFG1_BANKSZ_MASK ) >> MMCTRL_SDCFG1_BANKSZ_SHIFT ) +#define MMCTRL_SDCFG1_BANKSZ_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MMCTRL_SDCFG1_BANKSZ_MASK ) | \ ( ( ( _val ) << MMCTRL_SDCFG1_BANKSZ_SHIFT ) & \ MMCTRL_SDCFG1_BANKSZ_MASK ) ) #define MMCTRL_SDCFG1_BANKSZ( _val ) \ - ( ( ( _val ) << MMCTRL_SDCFG1_BANKSZ_SHIFT ) & \ - MMCTRL_SDCFG1_BANKSZ_MASK ) + ( ( ( _val ) << MMCTRL_SDCFG1_BANKSZ_SHIFT ) & MMCTRL_SDCFG1_BANKSZ_MASK ) #define MMCTRL_SDCFG1_COLSZ_SHIFT 21 -#define MMCTRL_SDCFG1_COLSZ_MASK 0x600000U +#define MMCTRL_SDCFG1_COLSZ_MASK 0x600000U #define MMCTRL_SDCFG1_COLSZ_GET( _reg ) \ - ( ( ( _reg ) & MMCTRL_SDCFG1_COLSZ_MASK ) >> \ - MMCTRL_SDCFG1_COLSZ_SHIFT ) -#define MMCTRL_SDCFG1_COLSZ_SET( _reg, _val ) \ - ( ( ( _reg ) & ~MMCTRL_SDCFG1_COLSZ_MASK ) | \ + ( ( ( _reg ) & MMCTRL_SDCFG1_COLSZ_MASK ) >> MMCTRL_SDCFG1_COLSZ_SHIFT ) +#define MMCTRL_SDCFG1_COLSZ_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MMCTRL_SDCFG1_COLSZ_MASK ) | \ ( ( ( _val ) << MMCTRL_SDCFG1_COLSZ_SHIFT ) & \ MMCTRL_SDCFG1_COLSZ_MASK ) ) #define MMCTRL_SDCFG1_COLSZ( _val ) \ - ( ( ( _val ) << MMCTRL_SDCFG1_COLSZ_SHIFT ) & \ - MMCTRL_SDCFG1_COLSZ_MASK ) + ( ( ( _val ) << MMCTRL_SDCFG1_COLSZ_SHIFT ) & MMCTRL_SDCFG1_COLSZ_MASK ) #define MMCTRL_SDCFG1_COMMAND_SHIFT 18 -#define MMCTRL_SDCFG1_COMMAND_MASK 0x1c0000U +#define MMCTRL_SDCFG1_COMMAND_MASK 0x1c0000U #define MMCTRL_SDCFG1_COMMAND_GET( _reg ) \ - ( ( ( _reg ) & MMCTRL_SDCFG1_COMMAND_MASK ) >> \ - MMCTRL_SDCFG1_COMMAND_SHIFT ) -#define MMCTRL_SDCFG1_COMMAND_SET( _reg, _val ) \ - ( ( ( _reg ) & ~MMCTRL_SDCFG1_COMMAND_MASK ) | \ + ( ( ( _reg ) & MMCTRL_SDCFG1_COMMAND_MASK ) >> MMCTRL_SDCFG1_COMMAND_SHIFT ) +#define MMCTRL_SDCFG1_COMMAND_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MMCTRL_SDCFG1_COMMAND_MASK ) | \ ( ( ( _val ) << MMCTRL_SDCFG1_COMMAND_SHIFT ) & \ MMCTRL_SDCFG1_COMMAND_MASK ) ) #define MMCTRL_SDCFG1_COMMAND( _val ) \ - ( ( ( _val ) << MMCTRL_SDCFG1_COMMAND_SHIFT ) & \ - MMCTRL_SDCFG1_COMMAND_MASK ) + ( ( ( _val ) << MMCTRL_SDCFG1_COMMAND_SHIFT ) & MMCTRL_SDCFG1_COMMAND_MASK ) #define MMCTRL_SDCFG1_MS 0x10000U #define MMCTRL_SDCFG1_64 0x8000U #define MMCTRL_SDCFG1_RFLOAD_SHIFT 0 -#define MMCTRL_SDCFG1_RFLOAD_MASK 0x7fffU +#define MMCTRL_SDCFG1_RFLOAD_MASK 0x7fffU #define MMCTRL_SDCFG1_RFLOAD_GET( _reg ) \ - ( ( ( _reg ) & MMCTRL_SDCFG1_RFLOAD_MASK ) >> \ - MMCTRL_SDCFG1_RFLOAD_SHIFT ) -#define MMCTRL_SDCFG1_RFLOAD_SET( _reg, _val ) \ - ( ( ( _reg ) & ~MMCTRL_SDCFG1_RFLOAD_MASK ) | \ + ( ( ( _reg ) & MMCTRL_SDCFG1_RFLOAD_MASK ) >> MMCTRL_SDCFG1_RFLOAD_SHIFT ) +#define MMCTRL_SDCFG1_RFLOAD_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MMCTRL_SDCFG1_RFLOAD_MASK ) | \ ( ( ( _val ) << MMCTRL_SDCFG1_RFLOAD_SHIFT ) & \ MMCTRL_SDCFG1_RFLOAD_MASK ) ) #define MMCTRL_SDCFG1_RFLOAD( _val ) \ - ( ( ( _val ) << MMCTRL_SDCFG1_RFLOAD_SHIFT ) & \ - MMCTRL_SDCFG1_RFLOAD_MASK ) + ( ( ( _val ) << MMCTRL_SDCFG1_RFLOAD_SHIFT ) & MMCTRL_SDCFG1_RFLOAD_MASK ) /** @} */ @@ -187,58 +176,49 @@ extern "C" { */ #define MMCTRL_MUXCFG_ERRLOC_SHIFT 20 -#define MMCTRL_MUXCFG_ERRLOC_MASK 0xfff00000U +#define MMCTRL_MUXCFG_ERRLOC_MASK 0xfff00000U #define MMCTRL_MUXCFG_ERRLOC_GET( _reg ) \ - ( ( ( _reg ) & MMCTRL_MUXCFG_ERRLOC_MASK ) >> \ - MMCTRL_MUXCFG_ERRLOC_SHIFT ) -#define MMCTRL_MUXCFG_ERRLOC_SET( _reg, _val ) \ - ( ( ( _reg ) & ~MMCTRL_MUXCFG_ERRLOC_MASK ) | \ + ( ( ( _reg ) & MMCTRL_MUXCFG_ERRLOC_MASK ) >> MMCTRL_MUXCFG_ERRLOC_SHIFT ) +#define MMCTRL_MUXCFG_ERRLOC_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MMCTRL_MUXCFG_ERRLOC_MASK ) | \ ( ( ( _val ) << MMCTRL_MUXCFG_ERRLOC_SHIFT ) & \ MMCTRL_MUXCFG_ERRLOC_MASK ) ) #define MMCTRL_MUXCFG_ERRLOC( _val ) \ - ( ( ( _val ) << MMCTRL_MUXCFG_ERRLOC_SHIFT ) & \ - MMCTRL_MUXCFG_ERRLOC_MASK ) + ( ( ( _val ) << MMCTRL_MUXCFG_ERRLOC_SHIFT ) & MMCTRL_MUXCFG_ERRLOC_MASK ) #define MMCTRL_MUXCFG_DDERR 0x80000U #define MMCTRL_MUXCFG_DWIDTH_SHIFT 16 -#define MMCTRL_MUXCFG_DWIDTH_MASK 0x70000U +#define MMCTRL_MUXCFG_DWIDTH_MASK 0x70000U #define MMCTRL_MUXCFG_DWIDTH_GET( _reg ) \ - ( ( ( _reg ) & MMCTRL_MUXCFG_DWIDTH_MASK ) >> \ - MMCTRL_MUXCFG_DWIDTH_SHIFT ) -#define MMCTRL_MUXCFG_DWIDTH_SET( _reg, _val ) \ - ( ( ( _reg ) & ~MMCTRL_MUXCFG_DWIDTH_MASK ) | \ + ( ( ( _reg ) & MMCTRL_MUXCFG_DWIDTH_MASK ) >> MMCTRL_MUXCFG_DWIDTH_SHIFT ) +#define MMCTRL_MUXCFG_DWIDTH_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MMCTRL_MUXCFG_DWIDTH_MASK ) | \ ( ( ( _val ) << MMCTRL_MUXCFG_DWIDTH_SHIFT ) & \ MMCTRL_MUXCFG_DWIDTH_MASK ) ) #define MMCTRL_MUXCFG_DWIDTH( _val ) \ - ( ( ( _val ) << MMCTRL_MUXCFG_DWIDTH_SHIFT ) & \ - MMCTRL_MUXCFG_DWIDTH_MASK ) + ( ( ( _val ) << MMCTRL_MUXCFG_DWIDTH_SHIFT ) & MMCTRL_MUXCFG_DWIDTH_MASK ) #define MMCTRL_MUXCFG_BEID_SHIFT 12 -#define MMCTRL_MUXCFG_BEID_MASK 0xf000U +#define MMCTRL_MUXCFG_BEID_MASK 0xf000U #define MMCTRL_MUXCFG_BEID_GET( _reg ) \ - ( ( ( _reg ) & MMCTRL_MUXCFG_BEID_MASK ) >> \ - MMCTRL_MUXCFG_BEID_SHIFT ) -#define MMCTRL_MUXCFG_BEID_SET( _reg, _val ) \ + ( ( ( _reg ) & MMCTRL_MUXCFG_BEID_MASK ) >> MMCTRL_MUXCFG_BEID_SHIFT ) +#define MMCTRL_MUXCFG_BEID_SET( _reg, _val ) \ ( ( ( _reg ) & ~MMCTRL_MUXCFG_BEID_MASK ) | \ - ( ( ( _val ) << MMCTRL_MUXCFG_BEID_SHIFT ) & \ - MMCTRL_MUXCFG_BEID_MASK ) ) + ( ( ( _val ) << MMCTRL_MUXCFG_BEID_SHIFT ) & MMCTRL_MUXCFG_BEID_MASK ) ) #define MMCTRL_MUXCFG_BEID( _val ) \ - ( ( ( _val ) << MMCTRL_MUXCFG_BEID_SHIFT ) & \ - MMCTRL_MUXCFG_BEID_MASK ) + ( ( ( _val ) << MMCTRL_MUXCFG_BEID_SHIFT ) & MMCTRL_MUXCFG_BEID_MASK ) #define MMCTRL_MUXCFG_DATAMUX_SHIFT 5 -#define MMCTRL_MUXCFG_DATAMUX_MASK 0xe0U +#define MMCTRL_MUXCFG_DATAMUX_MASK 0xe0U #define MMCTRL_MUXCFG_DATAMUX_GET( _reg ) \ - ( ( ( _reg ) & MMCTRL_MUXCFG_DATAMUX_MASK ) >> \ - MMCTRL_MUXCFG_DATAMUX_SHIFT ) -#define MMCTRL_MUXCFG_DATAMUX_SET( _reg, _val ) \ - ( ( ( _reg ) & ~MMCTRL_MUXCFG_DATAMUX_MASK ) | \ + ( ( ( _reg ) & MMCTRL_MUXCFG_DATAMUX_MASK ) >> MMCTRL_MUXCFG_DATAMUX_SHIFT ) +#define MMCTRL_MUXCFG_DATAMUX_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MMCTRL_MUXCFG_DATAMUX_MASK ) | \ ( ( ( _val ) << MMCTRL_MUXCFG_DATAMUX_SHIFT ) & \ MMCTRL_MUXCFG_DATAMUX_MASK ) ) #define MMCTRL_MUXCFG_DATAMUX( _val ) \ - ( ( ( _val ) << MMCTRL_MUXCFG_DATAMUX_SHIFT ) & \ - MMCTRL_MUXCFG_DATAMUX_MASK ) + ( ( ( _val ) << MMCTRL_MUXCFG_DATAMUX_SHIFT ) & MMCTRL_MUXCFG_DATAMUX_MASK ) #define MMCTRL_MUXCFG_CEN 0x10U @@ -261,17 +241,14 @@ extern "C" { */ #define MMCTRL_FTDA_FTDA_SHIFT 2 -#define MMCTRL_FTDA_FTDA_MASK 0xfffffffcU +#define MMCTRL_FTDA_FTDA_MASK 0xfffffffcU #define MMCTRL_FTDA_FTDA_GET( _reg ) \ - ( ( ( _reg ) & MMCTRL_FTDA_FTDA_MASK ) >> \ - MMCTRL_FTDA_FTDA_SHIFT ) -#define MMCTRL_FTDA_FTDA_SET( _reg, _val ) \ + ( ( ( _reg ) & MMCTRL_FTDA_FTDA_MASK ) >> MMCTRL_FTDA_FTDA_SHIFT ) +#define MMCTRL_FTDA_FTDA_SET( _reg, _val ) \ ( ( ( _reg ) & ~MMCTRL_FTDA_FTDA_MASK ) | \ - ( ( ( _val ) << MMCTRL_FTDA_FTDA_SHIFT ) & \ - MMCTRL_FTDA_FTDA_MASK ) ) + ( ( ( _val ) << MMCTRL_FTDA_FTDA_SHIFT ) & MMCTRL_FTDA_FTDA_MASK ) ) #define MMCTRL_FTDA_FTDA( _val ) \ - ( ( ( _val ) << MMCTRL_FTDA_FTDA_SHIFT ) & \ - MMCTRL_FTDA_FTDA_MASK ) + ( ( ( _val ) << MMCTRL_FTDA_FTDA_SHIFT ) & MMCTRL_FTDA_FTDA_MASK ) /** @} */ @@ -284,56 +261,44 @@ extern "C" { */ #define MMCTRL_FTDC_CBD_SHIFT 24 -#define MMCTRL_FTDC_CBD_MASK 0xff000000U +#define MMCTRL_FTDC_CBD_MASK 0xff000000U #define MMCTRL_FTDC_CBD_GET( _reg ) \ - ( ( ( _reg ) & MMCTRL_FTDC_CBD_MASK ) >> \ - MMCTRL_FTDC_CBD_SHIFT ) -#define MMCTRL_FTDC_CBD_SET( _reg, _val ) \ + ( ( ( _reg ) & MMCTRL_FTDC_CBD_MASK ) >> MMCTRL_FTDC_CBD_SHIFT ) +#define MMCTRL_FTDC_CBD_SET( _reg, _val ) \ ( ( ( _reg ) & ~MMCTRL_FTDC_CBD_MASK ) | \ - ( ( ( _val ) << MMCTRL_FTDC_CBD_SHIFT ) & \ - MMCTRL_FTDC_CBD_MASK ) ) + ( ( ( _val ) << MMCTRL_FTDC_CBD_SHIFT ) & MMCTRL_FTDC_CBD_MASK ) ) #define MMCTRL_FTDC_CBD( _val ) \ - ( ( ( _val ) << MMCTRL_FTDC_CBD_SHIFT ) & \ - MMCTRL_FTDC_CBD_MASK ) + ( ( ( _val ) << MMCTRL_FTDC_CBD_SHIFT ) & MMCTRL_FTDC_CBD_MASK ) #define MMCTRL_FTDC_CBC_SHIFT 16 -#define MMCTRL_FTDC_CBC_MASK 0xff0000U +#define MMCTRL_FTDC_CBC_MASK 0xff0000U #define MMCTRL_FTDC_CBC_GET( _reg ) \ - ( ( ( _reg ) & MMCTRL_FTDC_CBC_MASK ) >> \ - MMCTRL_FTDC_CBC_SHIFT ) -#define MMCTRL_FTDC_CBC_SET( _reg, _val ) \ + ( ( ( _reg ) & MMCTRL_FTDC_CBC_MASK ) >> MMCTRL_FTDC_CBC_SHIFT ) +#define MMCTRL_FTDC_CBC_SET( _reg, _val ) \ ( ( ( _reg ) & ~MMCTRL_FTDC_CBC_MASK ) | \ - ( ( ( _val ) << MMCTRL_FTDC_CBC_SHIFT ) & \ - MMCTRL_FTDC_CBC_MASK ) ) + ( ( ( _val ) << MMCTRL_FTDC_CBC_SHIFT ) & MMCTRL_FTDC_CBC_MASK ) ) #define MMCTRL_FTDC_CBC( _val ) \ - ( ( ( _val ) << MMCTRL_FTDC_CBC_SHIFT ) & \ - MMCTRL_FTDC_CBC_MASK ) + ( ( ( _val ) << MMCTRL_FTDC_CBC_SHIFT ) & MMCTRL_FTDC_CBC_MASK ) #define MMCTRL_FTDC_CBB_SHIFT 8 -#define MMCTRL_FTDC_CBB_MASK 0xff00U +#define MMCTRL_FTDC_CBB_MASK 0xff00U #define MMCTRL_FTDC_CBB_GET( _reg ) \ - ( ( ( _reg ) & MMCTRL_FTDC_CBB_MASK ) >> \ - MMCTRL_FTDC_CBB_SHIFT ) -#define MMCTRL_FTDC_CBB_SET( _reg, _val ) \ + ( ( ( _reg ) & MMCTRL_FTDC_CBB_MASK ) >> MMCTRL_FTDC_CBB_SHIFT ) +#define MMCTRL_FTDC_CBB_SET( _reg, _val ) \ ( ( ( _reg ) & ~MMCTRL_FTDC_CBB_MASK ) | \ - ( ( ( _val ) << MMCTRL_FTDC_CBB_SHIFT ) & \ - MMCTRL_FTDC_CBB_MASK ) ) + ( ( ( _val ) << MMCTRL_FTDC_CBB_SHIFT ) & MMCTRL_FTDC_CBB_MASK ) ) #define MMCTRL_FTDC_CBB( _val ) \ - ( ( ( _val ) << MMCTRL_FTDC_CBB_SHIFT ) & \ - MMCTRL_FTDC_CBB_MASK ) + ( ( ( _val ) << MMCTRL_FTDC_CBB_SHIFT ) & MMCTRL_FTDC_CBB_MASK ) #define MMCTRL_FTDC_CBA_SHIFT 0 -#define MMCTRL_FTDC_CBA_MASK 0xffU +#define MMCTRL_FTDC_CBA_MASK 0xffU #define MMCTRL_FTDC_CBA_GET( _reg ) \ - ( ( ( _reg ) & MMCTRL_FTDC_CBA_MASK ) >> \ - MMCTRL_FTDC_CBA_SHIFT ) -#define MMCTRL_FTDC_CBA_SET( _reg, _val ) \ + ( ( ( _reg ) & MMCTRL_FTDC_CBA_MASK ) >> MMCTRL_FTDC_CBA_SHIFT ) +#define MMCTRL_FTDC_CBA_SET( _reg, _val ) \ ( ( ( _reg ) & ~MMCTRL_FTDC_CBA_MASK ) | \ - ( ( ( _val ) << MMCTRL_FTDC_CBA_SHIFT ) & \ - MMCTRL_FTDC_CBA_MASK ) ) + ( ( ( _val ) << MMCTRL_FTDC_CBA_SHIFT ) & MMCTRL_FTDC_CBA_MASK ) ) #define MMCTRL_FTDC_CBA( _val ) \ - ( ( ( _val ) << MMCTRL_FTDC_CBA_SHIFT ) & \ - MMCTRL_FTDC_CBA_MASK ) + ( ( ( _val ) << MMCTRL_FTDC_CBA_SHIFT ) & MMCTRL_FTDC_CBA_MASK ) /** @} */ @@ -346,17 +311,14 @@ extern "C" { */ #define MMCTRL_FTDD_DATA_SHIFT 0 -#define MMCTRL_FTDD_DATA_MASK 0xffffffffU +#define MMCTRL_FTDD_DATA_MASK 0xffffffffU #define MMCTRL_FTDD_DATA_GET( _reg ) \ - ( ( ( _reg ) & MMCTRL_FTDD_DATA_MASK ) >> \ - MMCTRL_FTDD_DATA_SHIFT ) -#define MMCTRL_FTDD_DATA_SET( _reg, _val ) \ + ( ( ( _reg ) & MMCTRL_FTDD_DATA_MASK ) >> MMCTRL_FTDD_DATA_SHIFT ) +#define MMCTRL_FTDD_DATA_SET( _reg, _val ) \ ( ( ( _reg ) & ~MMCTRL_FTDD_DATA_MASK ) | \ - ( ( ( _val ) << MMCTRL_FTDD_DATA_SHIFT ) & \ - MMCTRL_FTDD_DATA_MASK ) ) + ( ( ( _val ) << MMCTRL_FTDD_DATA_SHIFT ) & MMCTRL_FTDD_DATA_MASK ) ) #define MMCTRL_FTDD_DATA( _val ) \ - ( ( ( _val ) << MMCTRL_FTDD_DATA_SHIFT ) & \ - MMCTRL_FTDD_DATA_MASK ) + ( ( ( _val ) << MMCTRL_FTDD_DATA_SHIFT ) & MMCTRL_FTDD_DATA_MASK ) /** @} */ @@ -369,15 +331,15 @@ extern "C" { */ #define MMCTRL_FTBND_FTBND_31_3_SHIFT 3 -#define MMCTRL_FTBND_FTBND_31_3_MASK 0xfffffff8U -#define MMCTRL_FTBND_FTBND_31_3_GET( _reg ) \ +#define MMCTRL_FTBND_FTBND_31_3_MASK 0xfffffff8U +#define MMCTRL_FTBND_FTBND_31_3_GET( _reg ) \ ( ( ( _reg ) & MMCTRL_FTBND_FTBND_31_3_MASK ) >> \ MMCTRL_FTBND_FTBND_31_3_SHIFT ) -#define MMCTRL_FTBND_FTBND_31_3_SET( _reg, _val ) \ - ( ( ( _reg ) & ~MMCTRL_FTBND_FTBND_31_3_MASK ) | \ +#define MMCTRL_FTBND_FTBND_31_3_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MMCTRL_FTBND_FTBND_31_3_MASK ) | \ ( ( ( _val ) << MMCTRL_FTBND_FTBND_31_3_SHIFT ) & \ MMCTRL_FTBND_FTBND_31_3_MASK ) ) -#define MMCTRL_FTBND_FTBND_31_3( _val ) \ +#define MMCTRL_FTBND_FTBND_31_3( _val ) \ ( ( ( _val ) << MMCTRL_FTBND_FTBND_31_3_SHIFT ) & \ MMCTRL_FTBND_FTBND_31_3_MASK ) diff --git a/bsps/include/grlib/occan.h b/bsps/include/grlib/occan.h index ea851b3fad..ba8aa1061d 100644 --- a/bsps/include/grlib/occan.h +++ b/bsps/include/grlib/occan.h @@ -41,58 +41,57 @@ extern "C" { /* CAN MESSAGE */ typedef struct { - char extended; /* 1= Extended Frame (29-bit id), 0= STD Frame (11-bit id) */ - char rtr; /* RTR - Remote Transmission Request */ - char sshot; /* single shot */ - unsigned char len; - unsigned char data[8]; - unsigned int id; + char extended; /* 1= Extended Frame (29-bit id), 0= STD Frame (11-bit id) */ + char rtr; /* RTR - Remote Transmission Request */ + char sshot; /* single shot */ + unsigned char len; + unsigned char data[ 8 ]; + unsigned int id; } CANMsg; typedef struct { - /* tx/rx stats */ - unsigned int rx_msgs; - unsigned int tx_msgs; + /* tx/rx stats */ + unsigned int rx_msgs; + unsigned int tx_msgs; - /* Error Interrupt counters */ - unsigned int err_warn; - unsigned int err_dovr; - unsigned int err_errp; - unsigned int err_arb; - unsigned int err_bus; + /* Error Interrupt counters */ + unsigned int err_warn; + unsigned int err_dovr; + unsigned int err_errp; + unsigned int err_arb; + unsigned int err_bus; - /**** BUS ERRORS (err_arb) ****/ + /**** BUS ERRORS (err_arb) ****/ - /* ALC 4-0 */ - unsigned int err_arb_bitnum[32]; /* At what bit arbitration is lost */ + /* ALC 4-0 */ + unsigned int err_arb_bitnum[ 32 ]; /* At what bit arbitration is lost */ - /******************************/ + /******************************/ - /**** BUS ERRORS (err_bus) ****/ + /**** BUS ERRORS (err_bus) ****/ - /* ECC 7-6 */ - unsigned int err_bus_bit; /* Bit error */ - unsigned int err_bus_form; /* Form Error */ - unsigned int err_bus_stuff; /* Stuff Error */ - unsigned int err_bus_other; /* Other Error */ + /* ECC 7-6 */ + unsigned int err_bus_bit; /* Bit error */ + unsigned int err_bus_form; /* Form Error */ + unsigned int err_bus_stuff; /* Stuff Error */ + unsigned int err_bus_other; /* Other Error */ - /* ECC 5 */ - unsigned int err_bus_rx; /* Errors during Reception */ - unsigned int err_bus_tx; /* Errors during Transmission */ + /* ECC 5 */ + unsigned int err_bus_rx; /* Errors during Reception */ + unsigned int err_bus_tx; /* Errors during Transmission */ - /* ECC 4:0 */ - unsigned int err_bus_segs[32]; /* Segment (Where in frame error occured) + /* ECC 4:0 */ + unsigned int err_bus_segs[ 32 ]; /* Segment (Where in frame error occured) * See OCCAN_SEG_* defines for indexes */ - /******************************/ + /******************************/ + /* total number of interrupts */ + unsigned int ints; - /* total number of interrupts */ - unsigned int ints; - - /* software monitoring hw errors */ - unsigned int tx_buf_error; + /* software monitoring hw errors */ + unsigned int tx_buf_error; /* Software fifo overrun */ unsigned int rx_sw_dovr; @@ -104,70 +103,67 @@ typedef struct { #define OCCAN_SEG_ID20 0x06 /* ID field bit 20:18 */ #define OCCAN_SEG_ID17 0x07 /* ID field bit 17:13 */ #define OCCAN_SEG_ID12 0x0f /* ID field bit 12:5 */ -#define OCCAN_SEG_ID4 0x0e /* ID field bit 4:0 */ +#define OCCAN_SEG_ID4 0x0e /* ID field bit 4:0 */ #define OCCAN_SEG_START 0x03 /* Start of Frame */ -#define OCCAN_SEG_SRTR 0x04 /* Bit SRTR */ -#define OCCAN_SEG_IDE 0x05 /* Bit IDE */ -#define OCCAN_SEG_RTR 0x0c /* Bit RTR */ -#define OCCAN_SEG_RSV0 0x09 /* Reserved bit 0 */ -#define OCCAN_SEG_RSV1 0x0d /* Reserved bit 1 */ +#define OCCAN_SEG_SRTR 0x04 /* Bit SRTR */ +#define OCCAN_SEG_IDE 0x05 /* Bit IDE */ +#define OCCAN_SEG_RTR 0x0c /* Bit RTR */ +#define OCCAN_SEG_RSV0 0x09 /* Reserved bit 0 */ +#define OCCAN_SEG_RSV1 0x0d /* Reserved bit 1 */ -#define OCCAN_SEG_DLEN 0x0b /* Data Length code */ -#define OCCAN_SEG_DFIELD 0x0a /* Data Field */ +#define OCCAN_SEG_DLEN 0x0b /* Data Length code */ +#define OCCAN_SEG_DFIELD 0x0a /* Data Field */ -#define OCCAN_SEG_CRC_SEQ 0x08 /* CRC Sequence */ -#define OCCAN_SEG_CRC_DELIM 0x18 /* CRC Delimiter */ +#define OCCAN_SEG_CRC_SEQ 0x08 /* CRC Sequence */ +#define OCCAN_SEG_CRC_DELIM 0x18 /* CRC Delimiter */ -#define OCCAN_SEG_ACK_SLOT 0x19 /* Acknowledge slot */ -#define OCCAN_SEG_ACK_DELIM 0x1b /* Acknowledge delimiter */ -#define OCCAN_SEG_EOF 0x1a /* End Of Frame */ +#define OCCAN_SEG_ACK_SLOT 0x19 /* Acknowledge slot */ +#define OCCAN_SEG_ACK_DELIM 0x1b /* Acknowledge delimiter */ +#define OCCAN_SEG_EOF 0x1a /* End Of Frame */ #define OCCAN_SEG_INTERMISSION 0x12 /* Intermission */ -#define OCCAN_SEG_ACT_ERR 0x11 /* Active error flag */ -#define OCCAN_SEG_PASS_ERR 0x16 /* Passive error flag */ -#define OCCAN_SEG_DOMINANT 0x13 /* Tolerate dominant bits */ -#define OCCAN_SEG_EDELIM 0x17 /* Error delimiter */ -#define OCCAN_SEG_OVERLOAD 0x1c /* overload flag */ +#define OCCAN_SEG_ACT_ERR 0x11 /* Active error flag */ +#define OCCAN_SEG_PASS_ERR 0x16 /* Passive error flag */ +#define OCCAN_SEG_DOMINANT 0x13 /* Tolerate dominant bits */ +#define OCCAN_SEG_EDELIM 0x17 /* Error delimiter */ +#define OCCAN_SEG_OVERLOAD 0x1c /* overload flag */ - -#define CANMSG_OPT_RTR 0x40 /* RTR Frame */ -#define CANMSG_OPT_EXTENDED 0x80 /* Exteneded frame */ -#define CANMSG_OPT_SSHOT 0x01 /* Single Shot, no retry */ +#define CANMSG_OPT_RTR 0x40 /* RTR Frame */ +#define CANMSG_OPT_EXTENDED 0x80 /* Exteneded frame */ +#define CANMSG_OPT_SSHOT 0x01 /* Single Shot, no retry */ #define OCCAN_IOC_START 1 #define OCCAN_IOC_STOP 2 -#define OCCAN_IOC_GET_CONF 3 -#define OCCAN_IOC_GET_STATS 4 +#define OCCAN_IOC_GET_CONF 3 +#define OCCAN_IOC_GET_STATS 4 #define OCCAN_IOC_GET_STATUS 5 -#define OCCAN_IOC_SET_SPEED 6 -#define OCCAN_IOC_SPEED_AUTO 7 -#define OCCAN_IOC_SET_LINK 8 -#define OCCAN_IOC_SET_FILTER 9 +#define OCCAN_IOC_SET_SPEED 6 +#define OCCAN_IOC_SPEED_AUTO 7 +#define OCCAN_IOC_SET_LINK 8 +#define OCCAN_IOC_SET_FILTER 9 #define OCCAN_IOC_SET_BLK_MODE 10 -#define OCCAN_IOC_SET_BUFLEN 11 -#define OCCAN_IOC_SET_BTRS 12 - +#define OCCAN_IOC_SET_BUFLEN 11 +#define OCCAN_IOC_SET_BTRS 12 struct occan_afilter { - unsigned char code[4]; - unsigned char mask[4]; - int single_mode; + unsigned char code[ 4 ]; + unsigned char mask[ 4 ]; + int single_mode; }; -#define OCCAN_STATUS_RESET 0x01 -#define OCCAN_STATUS_OVERRUN 0x02 -#define OCCAN_STATUS_WARN 0x04 +#define OCCAN_STATUS_RESET 0x01 +#define OCCAN_STATUS_OVERRUN 0x02 +#define OCCAN_STATUS_WARN 0x04 #define OCCAN_STATUS_ERR_PASSIVE 0x08 -#define OCCAN_STATUS_ERR_BUSOFF 0x10 +#define OCCAN_STATUS_ERR_BUSOFF 0x10 #define OCCAN_STATUS_QUEUE_ERROR 0x80 #define OCCAN_BLK_MODE_RX 0x1 #define OCCAN_BLK_MODE_TX 0x2 -void occan_register_drv (void); - +void occan_register_drv( void ); #define OCCAN_SPEED_500K 500000 #define OCCAN_SPEED_250K 250000 diff --git a/bsps/include/grlib/pcif.h b/bsps/include/grlib/pcif.h index 0875db86e7..3fd643d7e1 100644 --- a/bsps/include/grlib/pcif.h +++ b/bsps/include/grlib/pcif.h @@ -35,7 +35,7 @@ extern "C" { #endif /* Register the PCIF PCI host driver to the Driver Manager */ -extern void pcif_register_drv(void); +extern void pcif_register_drv( void ); #ifdef __cplusplus } diff --git a/bsps/include/grlib/satcan.h b/bsps/include/grlib/satcan.h index 229b1fd099..dda5972fbe 100644 --- a/bsps/include/grlib/satcan.h +++ b/bsps/include/grlib/satcan.h @@ -37,19 +37,19 @@ extern "C" { /* Config structure passed to SatCAN_init(..) */ typedef struct { - /* Configuration */ - int nodeno; - int dps; - /* Callback functions */ - void (*ahb_irq_callback)(void); - void (*pps_irq_callback)(void); - void (*m5_irq_callback)(void); - void (*m4_irq_callback)(void); - void (*m3_irq_callback)(void); - void (*m2_irq_callback)(void); - void (*m1_irq_callback)(void); - void (*sync_irq_callback)(void); - void (*can_irq_callback)(unsigned int fifo); + /* Configuration */ + int nodeno; + int dps; + /* Callback functions */ + void ( *ahb_irq_callback )( void ); + void ( *pps_irq_callback )( void ); + void ( *m5_irq_callback )( void ); + void ( *m4_irq_callback )( void ); + void ( *m3_irq_callback )( void ); + void ( *m2_irq_callback )( void ); + void ( *m1_irq_callback )( void ); + void ( *sync_irq_callback )( void ); + void ( *can_irq_callback )( unsigned int fifo ); } satcan_config; #define SATCAN_HEADER_SIZE 4 @@ -58,18 +58,18 @@ typedef struct { /* SatCAN message */ typedef struct { - unsigned char header[SATCAN_HEADER_SIZE]; /* Header of SatCAN message */ - unsigned char payload[SATCAN_PAYLOAD_SIZE]; /* Payload of SatCAN message */ + unsigned char header[ SATCAN_HEADER_SIZE ]; /* Header of SatCAN message */ + unsigned char payload[ SATCAN_PAYLOAD_SIZE ]; /* Payload of SatCAN message */ } satcan_msg; /* SatCAN modify register structure */ typedef struct { - unsigned int reg; - unsigned int val; + unsigned int reg; + unsigned int val; } satcan_regmod; /* Driver interface */ -int satcan_register(satcan_config *conf); +int satcan_register( satcan_config *conf ); /* SatCAN interrupt IDs */ #define SATCAN_IRQ_NONACT_TO_ACT 0 @@ -96,42 +96,47 @@ int satcan_register(satcan_config *conf); #define SATCAN_IRQ_CRITICAL 25 /* IOC */ -#define SATCAN_IOC_DMA_2K 1 /* Use DMA area for 2K messages */ -#define SATCAN_IOC_DMA_8K 2 /* Use DMA area for 8K messages */ -#define SATCAN_IOC_GET_REG 3 /* Provides direct read access to all core registers */ -#define SATCAN_IOC_SET_REG 4 /* Provides direct write access to all core registers */ -#define SATCAN_IOC_OR_REG 5 /* Provides direct read access to all core registers */ -#define SATCAN_IOC_AND_REG 6 /* Provides direct write access to all core registers */ -#define SATCAN_IOC_EN_TX1_DIS_TX2 7 /* Enable DMA TX channel 1, Disable DMA TX channel 2 */ -#define SATCAN_IOC_EN_TX2_DIS_TX1 8 /* Enable DMA TX channel 2, Disable DMA TX channel 1 */ -#define SATCAN_IOC_GET_DMA_MODE 9 /* Returns the current DMA mode */ -#define SATCAN_IOC_SET_DMA_MODE 10 /* Sets the DMA mode */ -#define SATCAN_IOC_ACTIVATE_DMA 11 /* Directly activate DMA channel */ -#define SATCAN_IOC_DEACTIVATE_DMA 12 /* Directly deactivate DMA channel */ -#define SATCAN_IOC_DMA_STATUS 13 /* Returns status of directly activated DMA */ -#define SATCAN_IOC_GET_DOFFSET 14 /* Get TX DMA offset */ -#define SATCAN_IOC_SET_DOFFSET 15 /* Set TX DMA offset */ -#define SATCAN_IOC_GET_TIMEOUT 16 /* Set TX DMA timeout */ -#define SATCAN_IOC_SET_TIMEOUT 17 /* Get TX DMA timeout */ +#define SATCAN_IOC_DMA_2K 1 /* Use DMA area for 2K messages */ +#define SATCAN_IOC_DMA_8K 2 /* Use DMA area for 8K messages */ +#define SATCAN_IOC_GET_REG \ + 3 /* Provides direct read access to all core registers */ +#define SATCAN_IOC_SET_REG \ + 4 /* Provides direct write access to all core registers */ +#define SATCAN_IOC_OR_REG \ + 5 /* Provides direct read access to all core registers */ +#define SATCAN_IOC_AND_REG \ + 6 /* Provides direct write access to all core registers */ +#define SATCAN_IOC_EN_TX1_DIS_TX2 \ + 7 /* Enable DMA TX channel 1, Disable DMA TX channel 2 */ +#define SATCAN_IOC_EN_TX2_DIS_TX1 \ + 8 /* Enable DMA TX channel 2, Disable DMA TX channel 1 */ +#define SATCAN_IOC_GET_DMA_MODE 9 /* Returns the current DMA mode */ +#define SATCAN_IOC_SET_DMA_MODE 10 /* Sets the DMA mode */ +#define SATCAN_IOC_ACTIVATE_DMA 11 /* Directly activate DMA channel */ +#define SATCAN_IOC_DEACTIVATE_DMA 12 /* Directly deactivate DMA channel */ +#define SATCAN_IOC_DMA_STATUS 13 /* Returns status of directly activated DMA */ +#define SATCAN_IOC_GET_DOFFSET 14 /* Get TX DMA offset */ +#define SATCAN_IOC_SET_DOFFSET 15 /* Set TX DMA offset */ +#define SATCAN_IOC_GET_TIMEOUT 16 /* Set TX DMA timeout */ +#define SATCAN_IOC_SET_TIMEOUT 17 /* Get TX DMA timeout */ - -/* Values used to select core register with IOC_SET_REG/IOC_GET_REG */ -#define SATCAN_SWRES 0 /* Software reset */ -#define SATCAN_INT_EN 1 /* Interrupt enable */ -#define SATCAN_FIFO 3 /* FIFO read */ -#define SATCAN_FIFO_RES 4 /* FIFO reset */ -#define SATCAN_TSTAMP 5 /* Current time stamp */ -#define SATCAN_CMD0 6 /* Command register 0 */ -#define SATCAN_CMD1 7 /* Command register 1 */ -#define SATCAN_START_CTC 8 /* Start cycle time counter */ -#define SATCAN_RAM_BASE 9 /* RAM offset address */ -#define SATCAN_STOP_CTC 10 /* Stop cycle time counter / DPS active status */ -#define SATCAN_DPS_ACT 10 /* Stop cycle time counter / DPS active status */ -#define SATCAN_PLL_RST 11 /* DPLL reset */ -#define SATCAN_PLL_CMD 12 /* DPLL command */ -#define SATCAN_PLL_STAT 13 /* DPLL status */ -#define SATCAN_PLL_OFF 14 /* DPLL offset */ -#define SATCAN_DMA 15 /* DMA channel enable */ +/* Values used to select core register with IOC_SET_REG/IOC_GET_REG */ +#define SATCAN_SWRES 0 /* Software reset */ +#define SATCAN_INT_EN 1 /* Interrupt enable */ +#define SATCAN_FIFO 3 /* FIFO read */ +#define SATCAN_FIFO_RES 4 /* FIFO reset */ +#define SATCAN_TSTAMP 5 /* Current time stamp */ +#define SATCAN_CMD0 6 /* Command register 0 */ +#define SATCAN_CMD1 7 /* Command register 1 */ +#define SATCAN_START_CTC 8 /* Start cycle time counter */ +#define SATCAN_RAM_BASE 9 /* RAM offset address */ +#define SATCAN_STOP_CTC 10 /* Stop cycle time counter / DPS active status */ +#define SATCAN_DPS_ACT 10 /* Stop cycle time counter / DPS active status */ +#define SATCAN_PLL_RST 11 /* DPLL reset */ +#define SATCAN_PLL_CMD 12 /* DPLL command */ +#define SATCAN_PLL_STAT 13 /* DPLL status */ +#define SATCAN_PLL_OFF 14 /* DPLL offset */ +#define SATCAN_DMA 15 /* DMA channel enable */ #define SATCAN_DMA_TX_1_CUR 16 /* DMA channel 1 TX current address */ #define SATCAN_DMA_TX_1_END 17 /* DMA channel 1 TX end address */ #define SATCAN_DMA_TX_2_CUR 18 /* DMA channel 2 TX current address */ @@ -145,14 +150,13 @@ int satcan_register(satcan_config *conf); #define SATCAN_WIMASK 34 /* Wrapper interrupt mask register */ #define SATCAN_WAHBADDR 35 /* Wrapper AHB address register */ - /* Values used to communicate DMA mode */ #define SATCAN_DMA_MODE_USER 0 #define SATCAN_DMA_MODE_SYSTEM 1 /* Values used to directly activate DMA channel */ -#define SATCAN_DMA_ENABLE_TX1 1 -#define SATCAN_DMA_ENABLE_TX2 2 +#define SATCAN_DMA_ENABLE_TX1 1 +#define SATCAN_DMA_ENABLE_TX2 2 #ifdef __cplusplus } diff --git a/bsps/include/grlib/spictrl-regs.h b/bsps/include/grlib/spictrl-regs.h index c70f7545b1..ef0f7da269 100644 --- a/bsps/include/grlib/spictrl-regs.h +++ b/bsps/include/grlib/spictrl-regs.h @@ -82,30 +82,25 @@ extern "C" { */ #define SPICTRL_CAP_SSSZ_SHIFT 24 -#define SPICTRL_CAP_SSSZ_MASK 0xff000000U +#define SPICTRL_CAP_SSSZ_MASK 0xff000000U #define SPICTRL_CAP_SSSZ_GET( _reg ) \ - ( ( ( _reg ) & SPICTRL_CAP_SSSZ_MASK ) >> \ - SPICTRL_CAP_SSSZ_SHIFT ) -#define SPICTRL_CAP_SSSZ_SET( _reg, _val ) \ + ( ( ( _reg ) & SPICTRL_CAP_SSSZ_MASK ) >> SPICTRL_CAP_SSSZ_SHIFT ) +#define SPICTRL_CAP_SSSZ_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPICTRL_CAP_SSSZ_MASK ) | \ - ( ( ( _val ) << SPICTRL_CAP_SSSZ_SHIFT ) & \ - SPICTRL_CAP_SSSZ_MASK ) ) + ( ( ( _val ) << SPICTRL_CAP_SSSZ_SHIFT ) & SPICTRL_CAP_SSSZ_MASK ) ) #define SPICTRL_CAP_SSSZ( _val ) \ - ( ( ( _val ) << SPICTRL_CAP_SSSZ_SHIFT ) & \ - SPICTRL_CAP_SSSZ_MASK ) + ( ( ( _val ) << SPICTRL_CAP_SSSZ_SHIFT ) & SPICTRL_CAP_SSSZ_MASK ) #define SPICTRL_CAP_MAXWLEN_SHIFT 20 -#define SPICTRL_CAP_MAXWLEN_MASK 0xf00000U +#define SPICTRL_CAP_MAXWLEN_MASK 0xf00000U #define SPICTRL_CAP_MAXWLEN_GET( _reg ) \ - ( ( ( _reg ) & SPICTRL_CAP_MAXWLEN_MASK ) >> \ - SPICTRL_CAP_MAXWLEN_SHIFT ) -#define SPICTRL_CAP_MAXWLEN_SET( _reg, _val ) \ - ( ( ( _reg ) & ~SPICTRL_CAP_MAXWLEN_MASK ) | \ + ( ( ( _reg ) & SPICTRL_CAP_MAXWLEN_MASK ) >> SPICTRL_CAP_MAXWLEN_SHIFT ) +#define SPICTRL_CAP_MAXWLEN_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPICTRL_CAP_MAXWLEN_MASK ) | \ ( ( ( _val ) << SPICTRL_CAP_MAXWLEN_SHIFT ) & \ SPICTRL_CAP_MAXWLEN_MASK ) ) #define SPICTRL_CAP_MAXWLEN( _val ) \ - ( ( ( _val ) << SPICTRL_CAP_MAXWLEN_SHIFT ) & \ - SPICTRL_CAP_MAXWLEN_MASK ) + ( ( ( _val ) << SPICTRL_CAP_MAXWLEN_SHIFT ) & SPICTRL_CAP_MAXWLEN_MASK ) #define SPICTRL_CAP_TWEN 0x80000U @@ -116,45 +111,36 @@ extern "C" { #define SPICTRL_CAP_SSEN 0x10000U #define SPICTRL_CAP_FDEPTH_SHIFT 8 -#define SPICTRL_CAP_FDEPTH_MASK 0xff00U +#define SPICTRL_CAP_FDEPTH_MASK 0xff00U #define SPICTRL_CAP_FDEPTH_GET( _reg ) \ - ( ( ( _reg ) & SPICTRL_CAP_FDEPTH_MASK ) >> \ - SPICTRL_CAP_FDEPTH_SHIFT ) -#define SPICTRL_CAP_FDEPTH_SET( _reg, _val ) \ + ( ( ( _reg ) & SPICTRL_CAP_FDEPTH_MASK ) >> SPICTRL_CAP_FDEPTH_SHIFT ) +#define SPICTRL_CAP_FDEPTH_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPICTRL_CAP_FDEPTH_MASK ) | \ - ( ( ( _val ) << SPICTRL_CAP_FDEPTH_SHIFT ) & \ - SPICTRL_CAP_FDEPTH_MASK ) ) + ( ( ( _val ) << SPICTRL_CAP_FDEPTH_SHIFT ) & SPICTRL_CAP_FDEPTH_MASK ) ) #define SPICTRL_CAP_FDEPTH( _val ) \ - ( ( ( _val ) << SPICTRL_CAP_FDEPTH_SHIFT ) & \ - SPICTRL_CAP_FDEPTH_MASK ) + ( ( ( _val ) << SPICTRL_CAP_FDEPTH_SHIFT ) & SPICTRL_CAP_FDEPTH_MASK ) #define SPICTRL_CAP_SR 0x80U #define SPICTRL_CAP_FT_SHIFT 5 -#define SPICTRL_CAP_FT_MASK 0x60U +#define SPICTRL_CAP_FT_MASK 0x60U #define SPICTRL_CAP_FT_GET( _reg ) \ - ( ( ( _reg ) & SPICTRL_CAP_FT_MASK ) >> \ - SPICTRL_CAP_FT_SHIFT ) -#define SPICTRL_CAP_FT_SET( _reg, _val ) \ + ( ( ( _reg ) & SPICTRL_CAP_FT_MASK ) >> SPICTRL_CAP_FT_SHIFT ) +#define SPICTRL_CAP_FT_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPICTRL_CAP_FT_MASK ) | \ - ( ( ( _val ) << SPICTRL_CAP_FT_SHIFT ) & \ - SPICTRL_CAP_FT_MASK ) ) + ( ( ( _val ) << SPICTRL_CAP_FT_SHIFT ) & SPICTRL_CAP_FT_MASK ) ) #define SPICTRL_CAP_FT( _val ) \ - ( ( ( _val ) << SPICTRL_CAP_FT_SHIFT ) & \ - SPICTRL_CAP_FT_MASK ) + ( ( ( _val ) << SPICTRL_CAP_FT_SHIFT ) & SPICTRL_CAP_FT_MASK ) #define SPICTRL_CAP_REV_SHIFT 0 -#define SPICTRL_CAP_REV_MASK 0x1fU +#define SPICTRL_CAP_REV_MASK 0x1fU #define SPICTRL_CAP_REV_GET( _reg ) \ - ( ( ( _reg ) & SPICTRL_CAP_REV_MASK ) >> \ - SPICTRL_CAP_REV_SHIFT ) -#define SPICTRL_CAP_REV_SET( _reg, _val ) \ + ( ( ( _reg ) & SPICTRL_CAP_REV_MASK ) >> SPICTRL_CAP_REV_SHIFT ) +#define SPICTRL_CAP_REV_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPICTRL_CAP_REV_MASK ) | \ - ( ( ( _val ) << SPICTRL_CAP_REV_SHIFT ) & \ - SPICTRL_CAP_REV_MASK ) ) + ( ( ( _val ) << SPICTRL_CAP_REV_SHIFT ) & SPICTRL_CAP_REV_MASK ) ) #define SPICTRL_CAP_REV( _val ) \ - ( ( ( _val ) << SPICTRL_CAP_REV_SHIFT ) & \ - SPICTRL_CAP_REV_MASK ) + ( ( ( _val ) << SPICTRL_CAP_REV_SHIFT ) & SPICTRL_CAP_REV_MASK ) /** @} */ @@ -181,30 +167,24 @@ extern "C" { #define SPICTRL_MODE_EN 0x1000000U #define SPICTRL_MODE_LEN_SHIFT 20 -#define SPICTRL_MODE_LEN_MASK 0xf00000U +#define SPICTRL_MODE_LEN_MASK 0xf00000U #define SPICTRL_MODE_LEN_GET( _reg ) \ - ( ( ( _reg ) & SPICTRL_MODE_LEN_MASK ) >> \ - SPICTRL_MODE_LEN_SHIFT ) -#define SPICTRL_MODE_LEN_SET( _reg, _val ) \ + ( ( ( _reg ) & SPICTRL_MODE_LEN_MASK ) >> SPICTRL_MODE_LEN_SHIFT ) +#define SPICTRL_MODE_LEN_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPICTRL_MODE_LEN_MASK ) | \ - ( ( ( _val ) << SPICTRL_MODE_LEN_SHIFT ) & \ - SPICTRL_MODE_LEN_MASK ) ) + ( ( ( _val ) << SPICTRL_MODE_LEN_SHIFT ) & SPICTRL_MODE_LEN_MASK ) ) #define SPICTRL_MODE_LEN( _val ) \ - ( ( ( _val ) << SPICTRL_MODE_LEN_SHIFT ) & \ - SPICTRL_MODE_LEN_MASK ) + ( ( ( _val ) << SPICTRL_MODE_LEN_SHIFT ) & SPICTRL_MODE_LEN_MASK ) #define SPICTRL_MODE_PM_SHIFT 16 -#define SPICTRL_MODE_PM_MASK 0xf0000U +#define SPICTRL_MODE_PM_MASK 0xf0000U #define SPICTRL_MODE_PM_GET( _reg ) \ - ( ( ( _reg ) & SPICTRL_MODE_PM_MASK ) >> \ - SPICTRL_MODE_PM_SHIFT ) -#define SPICTRL_MODE_PM_SET( _reg, _val ) \ + ( ( ( _reg ) & SPICTRL_MODE_PM_MASK ) >> SPICTRL_MODE_PM_SHIFT ) +#define SPICTRL_MODE_PM_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPICTRL_MODE_PM_MASK ) | \ - ( ( ( _val ) << SPICTRL_MODE_PM_SHIFT ) & \ - SPICTRL_MODE_PM_MASK ) ) + ( ( ( _val ) << SPICTRL_MODE_PM_SHIFT ) & SPICTRL_MODE_PM_MASK ) ) #define SPICTRL_MODE_PM( _val ) \ - ( ( ( _val ) << SPICTRL_MODE_PM_SHIFT ) & \ - SPICTRL_MODE_PM_MASK ) + ( ( ( _val ) << SPICTRL_MODE_PM_SHIFT ) & SPICTRL_MODE_PM_MASK ) #define SPICTRL_MODE_TWEN 0x8000U @@ -215,30 +195,25 @@ extern "C" { #define SPICTRL_MODE_OD 0x1000U #define SPICTRL_MODE_CG_SHIFT 7 -#define SPICTRL_MODE_CG_MASK 0xf80U +#define SPICTRL_MODE_CG_MASK 0xf80U #define SPICTRL_MODE_CG_GET( _reg ) \ - ( ( ( _reg ) & SPICTRL_MODE_CG_MASK ) >> \ - SPICTRL_MODE_CG_SHIFT ) -#define SPICTRL_MODE_CG_SET( _reg, _val ) \ + ( ( ( _reg ) & SPICTRL_MODE_CG_MASK ) >> SPICTRL_MODE_CG_SHIFT ) +#define SPICTRL_MODE_CG_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPICTRL_MODE_CG_MASK ) | \ - ( ( ( _val ) << SPICTRL_MODE_CG_SHIFT ) & \ - SPICTRL_MODE_CG_MASK ) ) + ( ( ( _val ) << SPICTRL_MODE_CG_SHIFT ) & SPICTRL_MODE_CG_MASK ) ) #define SPICTRL_MODE_CG( _val ) \ - ( ( ( _val ) << SPICTRL_MODE_CG_SHIFT ) & \ - SPICTRL_MODE_CG_MASK ) + ( ( ( _val ) << SPICTRL_MODE_CG_SHIFT ) & SPICTRL_MODE_CG_MASK ) #define SPICTRL_MODE_ASELDEL_SHIFT 5 -#define SPICTRL_MODE_ASELDEL_MASK 0x60U +#define SPICTRL_MODE_ASELDEL_MASK 0x60U #define SPICTRL_MODE_ASELDEL_GET( _reg ) \ - ( ( ( _reg ) & SPICTRL_MODE_ASELDEL_MASK ) >> \ - SPICTRL_MODE_ASELDEL_SHIFT ) -#define SPICTRL_MODE_ASELDEL_SET( _reg, _val ) \ - ( ( ( _reg ) & ~SPICTRL_MODE_ASELDEL_MASK ) | \ + ( ( ( _reg ) & SPICTRL_MODE_ASELDEL_MASK ) >> SPICTRL_MODE_ASELDEL_SHIFT ) +#define SPICTRL_MODE_ASELDEL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPICTRL_MODE_ASELDEL_MASK ) | \ ( ( ( _val ) << SPICTRL_MODE_ASELDEL_SHIFT ) & \ SPICTRL_MODE_ASELDEL_MASK ) ) #define SPICTRL_MODE_ASELDEL( _val ) \ - ( ( ( _val ) << SPICTRL_MODE_ASELDEL_SHIFT ) & \ - SPICTRL_MODE_ASELDEL_MASK ) + ( ( ( _val ) << SPICTRL_MODE_ASELDEL_SHIFT ) & SPICTRL_MODE_ASELDEL_MASK ) #define SPICTRL_MODE_TAC 0x10U @@ -319,17 +294,14 @@ extern "C" { */ #define SPICTRL_TX_TDATA_SHIFT 0 -#define SPICTRL_TX_TDATA_MASK 0xffffffffU +#define SPICTRL_TX_TDATA_MASK 0xffffffffU #define SPICTRL_TX_TDATA_GET( _reg ) \ - ( ( ( _reg ) & SPICTRL_TX_TDATA_MASK ) >> \ - SPICTRL_TX_TDATA_SHIFT ) -#define SPICTRL_TX_TDATA_SET( _reg, _val ) \ + ( ( ( _reg ) & SPICTRL_TX_TDATA_MASK ) >> SPICTRL_TX_TDATA_SHIFT ) +#define SPICTRL_TX_TDATA_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPICTRL_TX_TDATA_MASK ) | \ - ( ( ( _val ) << SPICTRL_TX_TDATA_SHIFT ) & \ - SPICTRL_TX_TDATA_MASK ) ) + ( ( ( _val ) << SPICTRL_TX_TDATA_SHIFT ) & SPICTRL_TX_TDATA_MASK ) ) #define SPICTRL_TX_TDATA( _val ) \ - ( ( ( _val ) << SPICTRL_TX_TDATA_SHIFT ) & \ - SPICTRL_TX_TDATA_MASK ) + ( ( ( _val ) << SPICTRL_TX_TDATA_SHIFT ) & SPICTRL_TX_TDATA_MASK ) /** @} */ @@ -342,17 +314,14 @@ extern "C" { */ #define SPICTRL_RX_RDATA_SHIFT 0 -#define SPICTRL_RX_RDATA_MASK 0xffffffffU +#define SPICTRL_RX_RDATA_MASK 0xffffffffU #define SPICTRL_RX_RDATA_GET( _reg ) \ - ( ( ( _reg ) & SPICTRL_RX_RDATA_MASK ) >> \ - SPICTRL_RX_RDATA_SHIFT ) -#define SPICTRL_RX_RDATA_SET( _reg, _val ) \ + ( ( ( _reg ) & SPICTRL_RX_RDATA_MASK ) >> SPICTRL_RX_RDATA_SHIFT ) +#define SPICTRL_RX_RDATA_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPICTRL_RX_RDATA_MASK ) | \ - ( ( ( _val ) << SPICTRL_RX_RDATA_SHIFT ) & \ - SPICTRL_RX_RDATA_MASK ) ) + ( ( ( _val ) << SPICTRL_RX_RDATA_SHIFT ) & SPICTRL_RX_RDATA_MASK ) ) #define SPICTRL_RX_RDATA( _val ) \ - ( ( ( _val ) << SPICTRL_RX_RDATA_SHIFT ) & \ - SPICTRL_RX_RDATA_MASK ) + ( ( ( _val ) << SPICTRL_RX_RDATA_SHIFT ) & SPICTRL_RX_RDATA_MASK ) /** @} */ @@ -365,17 +334,15 @@ extern "C" { */ #define SPICTRL_SLVSEL_SLVSEL_SHIFT 0 -#define SPICTRL_SLVSEL_SLVSEL_MASK 0x3U +#define SPICTRL_SLVSEL_SLVSEL_MASK 0x3U #define SPICTRL_SLVSEL_SLVSEL_GET( _reg ) \ - ( ( ( _reg ) & SPICTRL_SLVSEL_SLVSEL_MASK ) >> \ - SPICTRL_SLVSEL_SLVSEL_SHIFT ) -#define SPICTRL_SLVSEL_SLVSEL_SET( _reg, _val ) \ - ( ( ( _reg ) & ~SPICTRL_SLVSEL_SLVSEL_MASK ) | \ + ( ( ( _reg ) & SPICTRL_SLVSEL_SLVSEL_MASK ) >> SPICTRL_SLVSEL_SLVSEL_SHIFT ) +#define SPICTRL_SLVSEL_SLVSEL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPICTRL_SLVSEL_SLVSEL_MASK ) | \ ( ( ( _val ) << SPICTRL_SLVSEL_SLVSEL_SHIFT ) & \ SPICTRL_SLVSEL_SLVSEL_MASK ) ) #define SPICTRL_SLVSEL_SLVSEL( _val ) \ - ( ( ( _val ) << SPICTRL_SLVSEL_SLVSEL_SHIFT ) & \ - SPICTRL_SLVSEL_SLVSEL_MASK ) + ( ( ( _val ) << SPICTRL_SLVSEL_SLVSEL_SHIFT ) & SPICTRL_SLVSEL_SLVSEL_MASK ) /** @} */ @@ -389,15 +356,15 @@ extern "C" { */ #define SPICTRL_ASLVSEL_ASLVSEL_SHIFT 0 -#define SPICTRL_ASLVSEL_ASLVSEL_MASK 0x3U -#define SPICTRL_ASLVSEL_ASLVSEL_GET( _reg ) \ +#define SPICTRL_ASLVSEL_ASLVSEL_MASK 0x3U +#define SPICTRL_ASLVSEL_ASLVSEL_GET( _reg ) \ ( ( ( _reg ) & SPICTRL_ASLVSEL_ASLVSEL_MASK ) >> \ SPICTRL_ASLVSEL_ASLVSEL_SHIFT ) -#define SPICTRL_ASLVSEL_ASLVSEL_SET( _reg, _val ) \ - ( ( ( _reg ) & ~SPICTRL_ASLVSEL_ASLVSEL_MASK ) | \ +#define SPICTRL_ASLVSEL_ASLVSEL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPICTRL_ASLVSEL_ASLVSEL_MASK ) | \ ( ( ( _val ) << SPICTRL_ASLVSEL_ASLVSEL_SHIFT ) & \ SPICTRL_ASLVSEL_ASLVSEL_MASK ) ) -#define SPICTRL_ASLVSEL_ASLVSEL( _val ) \ +#define SPICTRL_ASLVSEL_ASLVSEL( _val ) \ ( ( ( _val ) << SPICTRL_ASLVSEL_ASLVSEL_SHIFT ) & \ SPICTRL_ASLVSEL_ASLVSEL_MASK ) diff --git a/bsps/include/grlib/spictrl.h b/bsps/include/grlib/spictrl.h index 9bed479a37..3a167e7875 100644 --- a/bsps/include/grlib/spictrl.h +++ b/bsps/include/grlib/spictrl.h @@ -35,27 +35,27 @@ extern "C" { #endif -extern void spictrl_register_drv (void); +extern void spictrl_register_drv( void ); /*** REGISTER LAYOUT ***/ struct spictrl_regs { - volatile uint32_t capability; /* 0x00 */ - volatile uint32_t resv[7]; /* 0x04 */ - volatile uint32_t mode; /* 0x20 */ - volatile uint32_t event; /* 0x24 */ - volatile uint32_t mask; /* 0x28 */ - volatile uint32_t command; /* 0x2c */ - volatile uint32_t tx; /* 0x30 */ - volatile uint32_t rx; /* 0x34 */ - volatile uint32_t slvsel; /* 0x38 */ - volatile uint32_t am_slvsel; /* 0x3c */ - volatile uint32_t am_cfg; /* 0x40 */ - volatile uint32_t am_period; /* 0x44 */ - uint32_t reserved0[2]; - volatile uint32_t am_mask[4]; /* 0x50-0x5C */ - uint32_t reserved1[(0x200-0x60)/4]; - volatile uint32_t am_tx[128]; /* 0x200-0x3FC */ - volatile uint32_t am_rx[128]; /* 0x400-0x5FC */ + volatile uint32_t capability; /* 0x00 */ + volatile uint32_t resv[ 7 ]; /* 0x04 */ + volatile uint32_t mode; /* 0x20 */ + volatile uint32_t event; /* 0x24 */ + volatile uint32_t mask; /* 0x28 */ + volatile uint32_t command; /* 0x2c */ + volatile uint32_t tx; /* 0x30 */ + volatile uint32_t rx; /* 0x34 */ + volatile uint32_t slvsel; /* 0x38 */ + volatile uint32_t am_slvsel; /* 0x3c */ + volatile uint32_t am_cfg; /* 0x40 */ + volatile uint32_t am_period; /* 0x44 */ + uint32_t reserved0[ 2 ]; + volatile uint32_t am_mask[ 4 ]; /* 0x50-0x5C */ + uint32_t reserved1[ ( 0x200 - 0x60 ) / 4 ]; + volatile uint32_t am_tx[ 128 ]; /* 0x200-0x3FC */ + volatile uint32_t am_rx[ 128 ]; /* 0x400-0x5FC */ }; /* -- About automated periodic transfer mode -- @@ -85,39 +85,48 @@ struct spictrl_regs { */ /* Custom SPICTRL driver ioctl commands */ -#define SPICTRL_IOCTL_PERIOD_START 5000 /* Start automated periodic transfer mode */ -#define SPICTRL_IOCTL_PERIOD_STOP 5001 /* Stop to SPI core from doing periodic transfers */ -#define SPICTRL_IOCTL_CONFIG 5002 /* Configure Periodic transfer mode (before calling write() and START) */ -#define SPICTRL_IOCTL_STATUS 5003 /* Get status */ +#define SPICTRL_IOCTL_PERIOD_START \ + 5000 /* Start automated periodic transfer mode */ +#define SPICTRL_IOCTL_PERIOD_STOP \ + 5001 /* Stop to SPI core from doing periodic transfers */ +#define SPICTRL_IOCTL_CONFIG \ + 5002 /* Configure Periodic transfer mode (before calling write() and START) */ +#define SPICTRL_IOCTL_STATUS 5003 /* Get status */ -#define SPICTRL_IOCTL_PERIOD_READ 5005 /* Write transmit registers and mask register +#define SPICTRL_IOCTL_PERIOD_READ \ + 5005 /* Write transmit registers and mask register * (only in automatic periodic mode) * Note that it is probably prefferred to read * the received words using the read() using * operations instead. */ -#define SPICTRL_IOCTL_PERIOD_WRITE 5006 /* Read receive registers and mask register +#define SPICTRL_IOCTL_PERIOD_WRITE \ + 5006 /* Read receive registers and mask register * (only in automatic periodic mode) */ -#define SPICTRL_IOCTL_REGS 5007 /* Get SPICTRL Register */ +#define SPICTRL_IOCTL_REGS 5007 /* Get SPICTRL Register */ /* SPICTRL_IOCTL_CONFIG argument */ struct spictrl_ioctl_config { - int clock_gap; /* Clock GAP between */ - unsigned int flags; /* Normal mode flags */ - int periodic_mode; /* 1=Enables Automated periodic transfers if supported by hardware */ - unsigned int period; /* Number of clocks between automated transfers are started */ - unsigned int period_flags; /* Options */ - unsigned int period_slvsel; /* Slave Select when transfer is not active, default is 0xffffffff */ + int clock_gap; /* Clock GAP between */ + unsigned int flags; /* Normal mode flags */ + int + periodic_mode; /* 1=Enables Automated periodic transfers if supported by hardware */ + unsigned int + period; /* Number of clocks between automated transfers are started */ + unsigned int period_flags; /* Options */ + unsigned int + period_slvsel; /* Slave Select when transfer is not active, default is 0xffffffff */ }; -#define SPICTRL_FLAGS_TAC 0x10 +#define SPICTRL_FLAGS_TAC 0x10 -#define SPICTRL_PERIOD_FLAGS_ERPT 0x80 /* Trigger start-period from external signal */ -#define SPICTRL_PERIOD_FLAGS_SEQ 0x40 -#define SPICTRL_PERIOD_FLAGS_STRICT 0x20 -#define SPICTRL_PERIOD_FLAGS_OVTB 0x10 -#define SPICTRL_PERIOD_FLAGS_OVDB 0x08 -#define SPICTRL_PERIOD_FLAGS_ASEL 0x04 -#define SPICTRL_PERIOD_FLAGS_EACT 0x01 +#define SPICTRL_PERIOD_FLAGS_ERPT \ + 0x80 /* Trigger start-period from external signal */ +#define SPICTRL_PERIOD_FLAGS_SEQ 0x40 +#define SPICTRL_PERIOD_FLAGS_STRICT 0x20 +#define SPICTRL_PERIOD_FLAGS_OVTB 0x10 +#define SPICTRL_PERIOD_FLAGS_OVDB 0x08 +#define SPICTRL_PERIOD_FLAGS_ASEL 0x04 +#define SPICTRL_PERIOD_FLAGS_EACT 0x01 /* SPICTRL_IOCTL_PERIOD_READ and SPICTRL_IOCTL_PERIOD_WRITE Argument data structure * @@ -125,7 +134,7 @@ struct spictrl_ioctl_config { * operation. See options notes. */ struct spictrl_period_io { - int options; /* READ: bit0=Read Mask Registers into masks[]. + int options; /* READ: bit0=Read Mask Registers into masks[]. * bit1=Read Receive registers according to masks[] * (after reading masks). * @@ -133,9 +142,9 @@ struct spictrl_period_io { * bit1=Update Transmit registers according to masks[]. * (before reading masks) */ - unsigned int masks[4]; + unsigned int masks[ 4 ]; - void *data; /* Data read sequentially according to masks[] bit. */ + void *data; /* Data read sequentially according to masks[] bit. */ }; #ifdef __cplusplus diff --git a/bsps/include/grlib/spwcuc.h b/bsps/include/grlib/spwcuc.h index c36212b4cc..260de5e44a 100644 --- a/bsps/include/grlib/spwcuc.h +++ b/bsps/include/grlib/spwcuc.h @@ -31,87 +31,90 @@ #ifndef __SPWCUC_H__ #define __SPWCUC_H__ -#define PKT_INIT_IRQ 0x1 -#define PKT_ERR_IRQ 0x2 -#define PKT_RX_IRQ 0x4 -#define WRAP_ERR_IRQ 0x8 -#define WRAP_IRQ 0x10 -#define SYNC_ERR_IRQ 0x20 -#define SYNC_IRQ 0x40 -#define TOL_ERR_IRQ 0x80 -#define TICK_RX_ERR_IRQ 0x100 -#define TICK_RX_WRAP_IRQ 0x200 -#define TICK_RX_IRQ 0x400 -#define TICK_TX_WRAP_IRQ 0x800 -#define TICK_TX_IRQ 0x1000 +#define PKT_INIT_IRQ 0x1 +#define PKT_ERR_IRQ 0x2 +#define PKT_RX_IRQ 0x4 +#define WRAP_ERR_IRQ 0x8 +#define WRAP_IRQ 0x10 +#define SYNC_ERR_IRQ 0x20 +#define SYNC_IRQ 0x40 +#define TOL_ERR_IRQ 0x80 +#define TICK_RX_ERR_IRQ 0x100 +#define TICK_RX_WRAP_IRQ 0x200 +#define TICK_RX_IRQ 0x400 +#define TICK_TX_WRAP_IRQ 0x800 +#define TICK_TX_IRQ 0x1000 /* SPWCUC Register layout */ struct spwcuc_regs { - volatile uint32_t config; /* 00 */ - volatile uint32_t status; /* 04 */ - volatile uint32_t control; /* 08 */ - volatile uint32_t unused0; /* 0c */ - volatile uint32_t dla; /* 10 */ - volatile uint32_t pid; /* 14 */ - volatile uint32_t offset; /* 18 */ - volatile uint32_t unused1; /* 1c */ - volatile uint32_t pkt_ct; /* 20 */ - volatile uint32_t pkt_ft; /* 24 */ - volatile uint32_t pkt_pf_crc; /* 28 */ - volatile uint32_t unused2; /* 2c */ - volatile uint32_t etct; /* 30 */ - volatile uint32_t etft; /* 34 */ - volatile uint32_t etct_next; /* 38 */ - volatile uint32_t etft_next; /* 3c */ - volatile uint32_t unused3[8]; /* 40-5c */ - volatile uint32_t pimsr; /* 60 */ - volatile uint32_t pimr; /* 64 */ - volatile uint32_t pisr; /* 68 */ - volatile uint32_t pir; /* 6c */ - volatile uint32_t imr; /* 70 */ - volatile uint32_t picr; /* 74 */ + volatile uint32_t config; /* 00 */ + volatile uint32_t status; /* 04 */ + volatile uint32_t control; /* 08 */ + volatile uint32_t unused0; /* 0c */ + volatile uint32_t dla; /* 10 */ + volatile uint32_t pid; /* 14 */ + volatile uint32_t offset; /* 18 */ + volatile uint32_t unused1; /* 1c */ + volatile uint32_t pkt_ct; /* 20 */ + volatile uint32_t pkt_ft; /* 24 */ + volatile uint32_t pkt_pf_crc; /* 28 */ + volatile uint32_t unused2; /* 2c */ + volatile uint32_t etct; /* 30 */ + volatile uint32_t etft; /* 34 */ + volatile uint32_t etct_next; /* 38 */ + volatile uint32_t etft_next; /* 3c */ + volatile uint32_t unused3[ 8 ]; /* 40-5c */ + volatile uint32_t pimsr; /* 60 */ + volatile uint32_t pimr; /* 64 */ + volatile uint32_t pisr; /* 68 */ + volatile uint32_t pir; /* 6c */ + volatile uint32_t imr; /* 70 */ + volatile uint32_t picr; /* 74 */ }; struct spwcuc_cfg { - unsigned char sel_out; /* Bits 3-0 enable time code transmission on respective output */ - unsigned char sel_in; /* Select SpW to receive time codes on, 0-3 */ - unsigned char mapping; /* Define mapping of time code time info into T-field, 0-31 */ - unsigned char tolerance; /* Define SpaceWire time code reception tolerance, 0-31 */ - unsigned char tid; /* Define CUC P-Field time code identification, 1 = Level 1, 2 = Level 2 */ - unsigned char ctf; /* If 1 check time code flags to be all zero */ - unsigned char cp; /* If 1 check P-Field time code id against tid */ + unsigned char + sel_out; /* Bits 3-0 enable time code transmission on respective output */ + unsigned char sel_in; /* Select SpW to receive time codes on, 0-3 */ + unsigned char + mapping; /* Define mapping of time code time info into T-field, 0-31 */ + unsigned char + tolerance; /* Define SpaceWire time code reception tolerance, 0-31 */ + unsigned char + tid; /* Define CUC P-Field time code identification, 1 = Level 1, 2 = Level 2 */ + unsigned char ctf; /* If 1 check time code flags to be all zero */ + unsigned char cp; /* If 1 check P-Field time code id against tid */ - unsigned char txen; /* Enable SpaceWire time code transmission */ - unsigned char rxen; /* Enable SpaceWire time code reception */ - unsigned char pktsyncen; /* Enable SpaceWire time CUC packet sync */ - unsigned char pktiniten; /* Enable SpaceWire time CUC packet init */ - unsigned char pktrxen; /* Enable SpaceWire time CUC packet reception */ + unsigned char txen; /* Enable SpaceWire time code transmission */ + unsigned char rxen; /* Enable SpaceWire time code reception */ + unsigned char pktsyncen; /* Enable SpaceWire time CUC packet sync */ + unsigned char pktiniten; /* Enable SpaceWire time CUC packet init */ + unsigned char pktrxen; /* Enable SpaceWire time CUC packet reception */ - unsigned char dla; /* SpaceWire destination logical address */ - unsigned char dla_mask; /* SpaceWire destination logical address mask */ - unsigned char pid; /* SpaceWire protocol ID */ - - unsigned int offset; /* Packet reception offset */ + unsigned char dla; /* SpaceWire destination logical address */ + unsigned char dla_mask; /* SpaceWire destination logical address mask */ + unsigned char pid; /* SpaceWire protocol ID */ + + unsigned int offset; /* Packet reception offset */ }; /* SPWCUC Statistics gathered by driver */ struct spwcuc_stats { - - /* IRQ Stats */ - unsigned int nirqs; - unsigned int tick_tx; - unsigned int tick_tx_wrap; - unsigned int tick_rx; - unsigned int tick_rx_wrap; - unsigned int tick_rx_error; - unsigned int tolerr; - unsigned int sync; - unsigned int syncerr; - unsigned int wrap; - unsigned int wraperr; - unsigned int pkt_rx; - unsigned int pkt_err; - unsigned int pkt_init; + /* IRQ Stats */ + unsigned int nirqs; + unsigned int tick_tx; + unsigned int tick_tx_wrap; + unsigned int tick_rx; + unsigned int tick_rx_wrap; + unsigned int tick_rx_error; + unsigned int tolerr; + unsigned int sync; + unsigned int syncerr; + unsigned int wrap; + unsigned int wraperr; + unsigned int pkt_rx; + unsigned int pkt_err; + unsigned int pkt_init; }; /* Function ISR callback prototype @@ -119,33 +122,33 @@ struct spwcuc_stats { * pimr - PIMR/PIR register of the SPWCUC core read by ISR * data - Custom data provided by user */ -typedef void (*spwcuc_isr_t)(unsigned int pimr, void *data); +typedef void ( *spwcuc_isr_t )( unsigned int pimr, void *data ); /* Open a SPWCUC device by minor number. A SPWCUC device can only by opened * once. The handle returned must be used as the input parameter 'spwcuc' in * the rest of the calls in the function interface. */ -extern void *spwcuc_open(int minor); +extern void *spwcuc_open( int minor ); /* Close a previously opened SPWCUC device */ -extern void spwcuc_close(void *spwcuc); +extern void spwcuc_close( void *spwcuc ); /* Reset SPWCUC Core */ -extern int spwcuc_reset(void *spwcuc); +extern int spwcuc_reset( void *spwcuc ); /* Enable Interrupts at Interrupt controller */ -extern void spwcuc_int_enable(void *spwcuc); +extern void spwcuc_int_enable( void *spwcuc ); /* Disable Interrupts at Interrupt controller */ -extern void spwcuc_int_disable(void *spwcuc); +extern void spwcuc_int_disable( void *spwcuc ); /* Clear Statistics gathered by the driver */ -extern void spwcuc_clr_stats(void *spwcuc); +extern void spwcuc_clr_stats( void *spwcuc ); /* Get Statistics gathered by the driver. The statistics are stored into * the location pointed to by 'stats'. */ -extern void spwcuc_get_stats(void *spwcuc, struct spwcuc_stats *stats); +extern void spwcuc_get_stats( void *spwcuc, struct spwcuc_stats *stats ); /* Register an Interrupt handler and custom data, the function call is * removed by setting func to NULL. @@ -153,55 +156,55 @@ extern void spwcuc_get_stats(void *spwcuc, struct spwcuc_stats *stats); * The driver's interrupt handler is installed on open(), however the user * callback called from the driver's ISR is installed using this function. */ -extern void spwcuc_int_register(void *spwcuc, spwcuc_isr_t func, void *data); +extern void spwcuc_int_register( void *spwcuc, spwcuc_isr_t func, void *data ); /* Configure the spwcuc core. The configuration is taken from the data * structure pointed to by 'cfg'. See data structure spwcuc_cfg fields. */ -extern void spwcuc_config(void *spwcuc, struct spwcuc_cfg *cfg); +extern void spwcuc_config( void *spwcuc, struct spwcuc_cfg *cfg ); /* Return elapsed coarse time */ -extern unsigned int spwcuc_get_et_coarse(void *spwcuc); +extern unsigned int spwcuc_get_et_coarse( void *spwcuc ); /* Return elapsed fine time */ -extern unsigned int spwcuc_get_et_fine(void *spwcuc); +extern unsigned int spwcuc_get_et_fine( void *spwcuc ); /* Return elapsed time (coarse and fine) 64-bit value */ -extern unsigned long long spwcuc_get_et(void *spwcuc); +extern unsigned long long spwcuc_get_et( void *spwcuc ); /* Return next elapsed coarse time (for use when sending SpW time packet) */ -extern unsigned int spwcuc_get_next_et_coarse(void *spwcuc); +extern unsigned int spwcuc_get_next_et_coarse( void *spwcuc ); /* Return next elapsed fine time (for use when sending SpW time packet) */ -extern unsigned int spwcuc_get_next_et_fine(void *spwcuc); +extern unsigned int spwcuc_get_next_et_fine( void *spwcuc ); /* Return next elapsed time (for use when sending SpW time packet) */ -extern unsigned long long spwcuc_get_next_et(void *spwcuc); +extern unsigned long long spwcuc_get_next_et( void *spwcuc ); /* Force/Set the elapsed time (coarse 32-bit and fine 24-bit) by writing the * T-Field Time Packet Registers then the FORCE bit. */ -extern void spwcuc_force_et(void *spwcuc, unsigned long long time); +extern void spwcuc_force_et( void *spwcuc, unsigned long long time ); /* Return received (from time packet) elapsed coarse time */ -extern unsigned int spwcuc_get_tp_et_coarse(void *spwcuc); +extern unsigned int spwcuc_get_tp_et_coarse( void *spwcuc ); /* Return received (from time packet) elapsed fine time */ -extern unsigned int spwcuc_get_tp_et_fine(void *spwcuc); +extern unsigned int spwcuc_get_tp_et_fine( void *spwcuc ); /* Return received (from time packet) elapsed time (coarse and fine) */ -extern unsigned long long spwcuc_get_tp_et(void *spwcuc); +extern unsigned long long spwcuc_get_tp_et( void *spwcuc ); /* Clear interrupts */ -extern void spwcuc_clear_irqs(void *spwcuc, int irqs); +extern void spwcuc_clear_irqs( void *spwcuc, int irqs ); /* Enable interrupts */ -extern void spwcuc_enable_irqs(void *spwcuc, int irqs); +extern void spwcuc_enable_irqs( void *spwcuc, int irqs ); /* Get Register */ -extern struct spwcuc_regs *spwcuc_get_regs(void *spwcuc); +extern struct spwcuc_regs *spwcuc_get_regs( void *spwcuc ); /* Register the SPWCUC Driver to the Driver Manager */ -extern void spwcuc_register(void); +extern void spwcuc_register( void ); #endif diff --git a/bsps/include/grlib/spwpnp-regs.h b/bsps/include/grlib/spwpnp-regs.h index 00c688bc55..24a3837318 100644 --- a/bsps/include/grlib/spwpnp-regs.h +++ b/bsps/include/grlib/spwpnp-regs.h @@ -83,30 +83,26 @@ extern "C" { */ #define SPWPNP_PNPVEND_VEND_SHIFT 16 -#define SPWPNP_PNPVEND_VEND_MASK 0xffff0000U +#define SPWPNP_PNPVEND_VEND_MASK 0xffff0000U #define SPWPNP_PNPVEND_VEND_GET( _reg ) \ - ( ( ( _reg ) & SPWPNP_PNPVEND_VEND_MASK ) >> \ - SPWPNP_PNPVEND_VEND_SHIFT ) -#define SPWPNP_PNPVEND_VEND_SET( _reg, _val ) \ - ( ( ( _reg ) & ~SPWPNP_PNPVEND_VEND_MASK ) | \ + ( ( ( _reg ) & SPWPNP_PNPVEND_VEND_MASK ) >> SPWPNP_PNPVEND_VEND_SHIFT ) +#define SPWPNP_PNPVEND_VEND_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWPNP_PNPVEND_VEND_MASK ) | \ ( ( ( _val ) << SPWPNP_PNPVEND_VEND_SHIFT ) & \ SPWPNP_PNPVEND_VEND_MASK ) ) #define SPWPNP_PNPVEND_VEND( _val ) \ - ( ( ( _val ) << SPWPNP_PNPVEND_VEND_SHIFT ) & \ - SPWPNP_PNPVEND_VEND_MASK ) + ( ( ( _val ) << SPWPNP_PNPVEND_VEND_SHIFT ) & SPWPNP_PNPVEND_VEND_MASK ) #define SPWPNP_PNPVEND_PROD_SHIFT 0 -#define SPWPNP_PNPVEND_PROD_MASK 0xffffU +#define SPWPNP_PNPVEND_PROD_MASK 0xffffU #define SPWPNP_PNPVEND_PROD_GET( _reg ) \ - ( ( ( _reg ) & SPWPNP_PNPVEND_PROD_MASK ) >> \ - SPWPNP_PNPVEND_PROD_SHIFT ) -#define SPWPNP_PNPVEND_PROD_SET( _reg, _val ) \ - ( ( ( _reg ) & ~SPWPNP_PNPVEND_PROD_MASK ) | \ + ( ( ( _reg ) & SPWPNP_PNPVEND_PROD_MASK ) >> SPWPNP_PNPVEND_PROD_SHIFT ) +#define SPWPNP_PNPVEND_PROD_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWPNP_PNPVEND_PROD_MASK ) | \ ( ( ( _val ) << SPWPNP_PNPVEND_PROD_SHIFT ) & \ SPWPNP_PNPVEND_PROD_MASK ) ) #define SPWPNP_PNPVEND_PROD( _val ) \ - ( ( ( _val ) << SPWPNP_PNPVEND_PROD_SHIFT ) & \ - SPWPNP_PNPVEND_PROD_MASK ) + ( ( ( _val ) << SPWPNP_PNPVEND_PROD_SHIFT ) & SPWPNP_PNPVEND_PROD_MASK ) /** @} */ @@ -120,43 +116,37 @@ extern "C" { */ #define SPWPNP_PNPVER_MAJOR_SHIFT 24 -#define SPWPNP_PNPVER_MAJOR_MASK 0xff000000U +#define SPWPNP_PNPVER_MAJOR_MASK 0xff000000U #define SPWPNP_PNPVER_MAJOR_GET( _reg ) \ - ( ( ( _reg ) & SPWPNP_PNPVER_MAJOR_MASK ) >> \ - SPWPNP_PNPVER_MAJOR_SHIFT ) -#define SPWPNP_PNPVER_MAJOR_SET( _reg, _val ) \ - ( ( ( _reg ) & ~SPWPNP_PNPVER_MAJOR_MASK ) | \ + ( ( ( _reg ) & SPWPNP_PNPVER_MAJOR_MASK ) >> SPWPNP_PNPVER_MAJOR_SHIFT ) +#define SPWPNP_PNPVER_MAJOR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWPNP_PNPVER_MAJOR_MASK ) | \ ( ( ( _val ) << SPWPNP_PNPVER_MAJOR_SHIFT ) & \ SPWPNP_PNPVER_MAJOR_MASK ) ) #define SPWPNP_PNPVER_MAJOR( _val ) \ - ( ( ( _val ) << SPWPNP_PNPVER_MAJOR_SHIFT ) & \ - SPWPNP_PNPVER_MAJOR_MASK ) + ( ( ( _val ) << SPWPNP_PNPVER_MAJOR_SHIFT ) & SPWPNP_PNPVER_MAJOR_MASK ) #define SPWPNP_PNPVER_MINOR_SHIFT 16 -#define SPWPNP_PNPVER_MINOR_MASK 0xff0000U +#define SPWPNP_PNPVER_MINOR_MASK 0xff0000U #define SPWPNP_PNPVER_MINOR_GET( _reg ) \ - ( ( ( _reg ) & SPWPNP_PNPVER_MINOR_MASK ) >> \ - SPWPNP_PNPVER_MINOR_SHIFT ) -#define SPWPNP_PNPVER_MINOR_SET( _reg, _val ) \ - ( ( ( _reg ) & ~SPWPNP_PNPVER_MINOR_MASK ) | \ + ( ( ( _reg ) & SPWPNP_PNPVER_MINOR_MASK ) >> SPWPNP_PNPVER_MINOR_SHIFT ) +#define SPWPNP_PNPVER_MINOR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWPNP_PNPVER_MINOR_MASK ) | \ ( ( ( _val ) << SPWPNP_PNPVER_MINOR_SHIFT ) & \ SPWPNP_PNPVER_MINOR_MASK ) ) #define SPWPNP_PNPVER_MINOR( _val ) \ - ( ( ( _val ) << SPWPNP_PNPVER_MINOR_SHIFT ) & \ - SPWPNP_PNPVER_MINOR_MASK ) + ( ( ( _val ) << SPWPNP_PNPVER_MINOR_SHIFT ) & SPWPNP_PNPVER_MINOR_MASK ) #define SPWPNP_PNPVER_PATCH_SHIFT 8 -#define SPWPNP_PNPVER_PATCH_MASK 0xff00U +#define SPWPNP_PNPVER_PATCH_MASK 0xff00U #define SPWPNP_PNPVER_PATCH_GET( _reg ) \ - ( ( ( _reg ) & SPWPNP_PNPVER_PATCH_MASK ) >> \ - SPWPNP_PNPVER_PATCH_SHIFT ) -#define SPWPNP_PNPVER_PATCH_SET( _reg, _val ) \ - ( ( ( _reg ) & ~SPWPNP_PNPVER_PATCH_MASK ) | \ + ( ( ( _reg ) & SPWPNP_PNPVER_PATCH_MASK ) >> SPWPNP_PNPVER_PATCH_SHIFT ) +#define SPWPNP_PNPVER_PATCH_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWPNP_PNPVER_PATCH_MASK ) | \ ( ( ( _val ) << SPWPNP_PNPVER_PATCH_SHIFT ) & \ SPWPNP_PNPVER_PATCH_MASK ) ) #define SPWPNP_PNPVER_PATCH( _val ) \ - ( ( ( _val ) << SPWPNP_PNPVER_PATCH_SHIFT ) & \ - SPWPNP_PNPVER_PATCH_MASK ) + ( ( ( _val ) << SPWPNP_PNPVER_PATCH_SHIFT ) & SPWPNP_PNPVER_PATCH_MASK ) /** @} */ @@ -170,15 +160,15 @@ extern "C" { */ #define SPWPNP_PNPDEVSTS_STATUS_SHIFT 0 -#define SPWPNP_PNPDEVSTS_STATUS_MASK 0xffU -#define SPWPNP_PNPDEVSTS_STATUS_GET( _reg ) \ +#define SPWPNP_PNPDEVSTS_STATUS_MASK 0xffU +#define SPWPNP_PNPDEVSTS_STATUS_GET( _reg ) \ ( ( ( _reg ) & SPWPNP_PNPDEVSTS_STATUS_MASK ) >> \ SPWPNP_PNPDEVSTS_STATUS_SHIFT ) -#define SPWPNP_PNPDEVSTS_STATUS_SET( _reg, _val ) \ - ( ( ( _reg ) & ~SPWPNP_PNPDEVSTS_STATUS_MASK ) | \ +#define SPWPNP_PNPDEVSTS_STATUS_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWPNP_PNPDEVSTS_STATUS_MASK ) | \ ( ( ( _val ) << SPWPNP_PNPDEVSTS_STATUS_SHIFT ) & \ SPWPNP_PNPDEVSTS_STATUS_MASK ) ) -#define SPWPNP_PNPDEVSTS_STATUS( _val ) \ +#define SPWPNP_PNPDEVSTS_STATUS( _val ) \ ( ( ( _val ) << SPWPNP_PNPDEVSTS_STATUS_SHIFT ) & \ SPWPNP_PNPDEVSTS_STATUS_MASK ) @@ -194,15 +184,15 @@ extern "C" { */ #define SPWPNP_PNPACTLNK_ACTIVE_SHIFT 1 -#define SPWPNP_PNPACTLNK_ACTIVE_MASK 0xfffffffeU -#define SPWPNP_PNPACTLNK_ACTIVE_GET( _reg ) \ +#define SPWPNP_PNPACTLNK_ACTIVE_MASK 0xfffffffeU +#define SPWPNP_PNPACTLNK_ACTIVE_GET( _reg ) \ ( ( ( _reg ) & SPWPNP_PNPACTLNK_ACTIVE_MASK ) >> \ SPWPNP_PNPACTLNK_ACTIVE_SHIFT ) -#define SPWPNP_PNPACTLNK_ACTIVE_SET( _reg, _val ) \ - ( ( ( _reg ) & ~SPWPNP_PNPACTLNK_ACTIVE_MASK ) | \ +#define SPWPNP_PNPACTLNK_ACTIVE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWPNP_PNPACTLNK_ACTIVE_MASK ) | \ ( ( ( _val ) << SPWPNP_PNPACTLNK_ACTIVE_SHIFT ) & \ SPWPNP_PNPACTLNK_ACTIVE_MASK ) ) -#define SPWPNP_PNPACTLNK_ACTIVE( _val ) \ +#define SPWPNP_PNPACTLNK_ACTIVE( _val ) \ ( ( ( _val ) << SPWPNP_PNPACTLNK_ACTIVE_SHIFT ) & \ SPWPNP_PNPACTLNK_ACTIVE_MASK ) @@ -218,17 +208,14 @@ extern "C" { */ #define SPWPNP_PNPOA0_RA_SHIFT 0 -#define SPWPNP_PNPOA0_RA_MASK 0xffffffffU +#define SPWPNP_PNPOA0_RA_MASK 0xffffffffU #define SPWPNP_PNPOA0_RA_GET( _reg ) \ - ( ( ( _reg ) & SPWPNP_PNPOA0_RA_MASK ) >> \ - SPWPNP_PNPOA0_RA_SHIFT ) -#define SPWPNP_PNPOA0_RA_SET( _reg, _val ) \ + ( ( ( _reg ) & SPWPNP_PNPOA0_RA_MASK ) >> SPWPNP_PNPOA0_RA_SHIFT ) +#define SPWPNP_PNPOA0_RA_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPWPNP_PNPOA0_RA_MASK ) | \ - ( ( ( _val ) << SPWPNP_PNPOA0_RA_SHIFT ) & \ - SPWPNP_PNPOA0_RA_MASK ) ) + ( ( ( _val ) << SPWPNP_PNPOA0_RA_SHIFT ) & SPWPNP_PNPOA0_RA_MASK ) ) #define SPWPNP_PNPOA0_RA( _val ) \ - ( ( ( _val ) << SPWPNP_PNPOA0_RA_SHIFT ) & \ - SPWPNP_PNPOA0_RA_MASK ) + ( ( ( _val ) << SPWPNP_PNPOA0_RA_SHIFT ) & SPWPNP_PNPOA0_RA_MASK ) /** @} */ @@ -242,17 +229,14 @@ extern "C" { */ #define SPWPNP_PNPOA1_RA_SHIFT 0 -#define SPWPNP_PNPOA1_RA_MASK 0xffffffffU +#define SPWPNP_PNPOA1_RA_MASK 0xffffffffU #define SPWPNP_PNPOA1_RA_GET( _reg ) \ - ( ( ( _reg ) & SPWPNP_PNPOA1_RA_MASK ) >> \ - SPWPNP_PNPOA1_RA_SHIFT ) -#define SPWPNP_PNPOA1_RA_SET( _reg, _val ) \ + ( ( ( _reg ) & SPWPNP_PNPOA1_RA_MASK ) >> SPWPNP_PNPOA1_RA_SHIFT ) +#define SPWPNP_PNPOA1_RA_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPWPNP_PNPOA1_RA_MASK ) | \ - ( ( ( _val ) << SPWPNP_PNPOA1_RA_SHIFT ) & \ - SPWPNP_PNPOA1_RA_MASK ) ) + ( ( ( _val ) << SPWPNP_PNPOA1_RA_SHIFT ) & SPWPNP_PNPOA1_RA_MASK ) ) #define SPWPNP_PNPOA1_RA( _val ) \ - ( ( ( _val ) << SPWPNP_PNPOA1_RA_SHIFT ) & \ - SPWPNP_PNPOA1_RA_MASK ) + ( ( ( _val ) << SPWPNP_PNPOA1_RA_SHIFT ) & SPWPNP_PNPOA1_RA_MASK ) /** @} */ @@ -266,17 +250,14 @@ extern "C" { */ #define SPWPNP_PNPOA2_RA_SHIFT 0 -#define SPWPNP_PNPOA2_RA_MASK 0xffffffffU +#define SPWPNP_PNPOA2_RA_MASK 0xffffffffU #define SPWPNP_PNPOA2_RA_GET( _reg ) \ - ( ( ( _reg ) & SPWPNP_PNPOA2_RA_MASK ) >> \ - SPWPNP_PNPOA2_RA_SHIFT ) -#define SPWPNP_PNPOA2_RA_SET( _reg, _val ) \ + ( ( ( _reg ) & SPWPNP_PNPOA2_RA_MASK ) >> SPWPNP_PNPOA2_RA_SHIFT ) +#define SPWPNP_PNPOA2_RA_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPWPNP_PNPOA2_RA_MASK ) | \ - ( ( ( _val ) << SPWPNP_PNPOA2_RA_SHIFT ) & \ - SPWPNP_PNPOA2_RA_MASK ) ) + ( ( ( _val ) << SPWPNP_PNPOA2_RA_SHIFT ) & SPWPNP_PNPOA2_RA_MASK ) ) #define SPWPNP_PNPOA2_RA( _val ) \ - ( ( ( _val ) << SPWPNP_PNPOA2_RA_SHIFT ) & \ - SPWPNP_PNPOA2_RA_MASK ) + ( ( ( _val ) << SPWPNP_PNPOA2_RA_SHIFT ) & SPWPNP_PNPOA2_RA_MASK ) /** @} */ @@ -290,17 +271,15 @@ extern "C" { */ #define SPWPNP_PNPDEVID_DID_SHIFT 0 -#define SPWPNP_PNPDEVID_DID_MASK 0xffffffffU +#define SPWPNP_PNPDEVID_DID_MASK 0xffffffffU #define SPWPNP_PNPDEVID_DID_GET( _reg ) \ - ( ( ( _reg ) & SPWPNP_PNPDEVID_DID_MASK ) >> \ - SPWPNP_PNPDEVID_DID_SHIFT ) -#define SPWPNP_PNPDEVID_DID_SET( _reg, _val ) \ - ( ( ( _reg ) & ~SPWPNP_PNPDEVID_DID_MASK ) | \ + ( ( ( _reg ) & SPWPNP_PNPDEVID_DID_MASK ) >> SPWPNP_PNPDEVID_DID_SHIFT ) +#define SPWPNP_PNPDEVID_DID_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWPNP_PNPDEVID_DID_MASK ) | \ ( ( ( _val ) << SPWPNP_PNPDEVID_DID_SHIFT ) & \ SPWPNP_PNPDEVID_DID_MASK ) ) #define SPWPNP_PNPDEVID_DID( _val ) \ - ( ( ( _val ) << SPWPNP_PNPDEVID_DID_SHIFT ) & \ - SPWPNP_PNPDEVID_DID_MASK ) + ( ( ( _val ) << SPWPNP_PNPDEVID_DID_SHIFT ) & SPWPNP_PNPDEVID_DID_MASK ) /** @} */ @@ -314,30 +293,26 @@ extern "C" { */ #define SPWPNP_PNPUVEND_VEND_SHIFT 16 -#define SPWPNP_PNPUVEND_VEND_MASK 0xffff0000U +#define SPWPNP_PNPUVEND_VEND_MASK 0xffff0000U #define SPWPNP_PNPUVEND_VEND_GET( _reg ) \ - ( ( ( _reg ) & SPWPNP_PNPUVEND_VEND_MASK ) >> \ - SPWPNP_PNPUVEND_VEND_SHIFT ) -#define SPWPNP_PNPUVEND_VEND_SET( _reg, _val ) \ - ( ( ( _reg ) & ~SPWPNP_PNPUVEND_VEND_MASK ) | \ + ( ( ( _reg ) & SPWPNP_PNPUVEND_VEND_MASK ) >> SPWPNP_PNPUVEND_VEND_SHIFT ) +#define SPWPNP_PNPUVEND_VEND_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWPNP_PNPUVEND_VEND_MASK ) | \ ( ( ( _val ) << SPWPNP_PNPUVEND_VEND_SHIFT ) & \ SPWPNP_PNPUVEND_VEND_MASK ) ) #define SPWPNP_PNPUVEND_VEND( _val ) \ - ( ( ( _val ) << SPWPNP_PNPUVEND_VEND_SHIFT ) & \ - SPWPNP_PNPUVEND_VEND_MASK ) + ( ( ( _val ) << SPWPNP_PNPUVEND_VEND_SHIFT ) & SPWPNP_PNPUVEND_VEND_MASK ) #define SPWPNP_PNPUVEND_PROD_SHIFT 0 -#define SPWPNP_PNPUVEND_PROD_MASK 0xffffU +#define SPWPNP_PNPUVEND_PROD_MASK 0xffffU #define SPWPNP_PNPUVEND_PROD_GET( _reg ) \ - ( ( ( _reg ) & SPWPNP_PNPUVEND_PROD_MASK ) >> \ - SPWPNP_PNPUVEND_PROD_SHIFT ) -#define SPWPNP_PNPUVEND_PROD_SET( _reg, _val ) \ - ( ( ( _reg ) & ~SPWPNP_PNPUVEND_PROD_MASK ) | \ + ( ( ( _reg ) & SPWPNP_PNPUVEND_PROD_MASK ) >> SPWPNP_PNPUVEND_PROD_SHIFT ) +#define SPWPNP_PNPUVEND_PROD_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWPNP_PNPUVEND_PROD_MASK ) | \ ( ( ( _val ) << SPWPNP_PNPUVEND_PROD_SHIFT ) & \ SPWPNP_PNPUVEND_PROD_MASK ) ) #define SPWPNP_PNPUVEND_PROD( _val ) \ - ( ( ( _val ) << SPWPNP_PNPUVEND_PROD_SHIFT ) & \ - SPWPNP_PNPUVEND_PROD_MASK ) + ( ( ( _val ) << SPWPNP_PNPUVEND_PROD_SHIFT ) & SPWPNP_PNPUVEND_PROD_MASK ) /** @} */ @@ -351,17 +326,14 @@ extern "C" { */ #define SPWPNP_PNPUSN_USN_SHIFT 0 -#define SPWPNP_PNPUSN_USN_MASK 0xffffffffU +#define SPWPNP_PNPUSN_USN_MASK 0xffffffffU #define SPWPNP_PNPUSN_USN_GET( _reg ) \ - ( ( ( _reg ) & SPWPNP_PNPUSN_USN_MASK ) >> \ - SPWPNP_PNPUSN_USN_SHIFT ) -#define SPWPNP_PNPUSN_USN_SET( _reg, _val ) \ + ( ( ( _reg ) & SPWPNP_PNPUSN_USN_MASK ) >> SPWPNP_PNPUSN_USN_SHIFT ) +#define SPWPNP_PNPUSN_USN_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPWPNP_PNPUSN_USN_MASK ) | \ - ( ( ( _val ) << SPWPNP_PNPUSN_USN_SHIFT ) & \ - SPWPNP_PNPUSN_USN_MASK ) ) + ( ( ( _val ) << SPWPNP_PNPUSN_USN_SHIFT ) & SPWPNP_PNPUSN_USN_MASK ) ) #define SPWPNP_PNPUSN_USN( _val ) \ - ( ( ( _val ) << SPWPNP_PNPUSN_USN_SHIFT ) & \ - SPWPNP_PNPUSN_USN_MASK ) + ( ( ( _val ) << SPWPNP_PNPUSN_USN_SHIFT ) & SPWPNP_PNPUSN_USN_MASK ) /** @} */ @@ -375,17 +347,15 @@ extern "C" { */ #define SPWPNP_PNPVSTRL_LEN_SHIFT 0 -#define SPWPNP_PNPVSTRL_LEN_MASK 0x7fffU +#define SPWPNP_PNPVSTRL_LEN_MASK 0x7fffU #define SPWPNP_PNPVSTRL_LEN_GET( _reg ) \ - ( ( ( _reg ) & SPWPNP_PNPVSTRL_LEN_MASK ) >> \ - SPWPNP_PNPVSTRL_LEN_SHIFT ) -#define SPWPNP_PNPVSTRL_LEN_SET( _reg, _val ) \ - ( ( ( _reg ) & ~SPWPNP_PNPVSTRL_LEN_MASK ) | \ + ( ( ( _reg ) & SPWPNP_PNPVSTRL_LEN_MASK ) >> SPWPNP_PNPVSTRL_LEN_SHIFT ) +#define SPWPNP_PNPVSTRL_LEN_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWPNP_PNPVSTRL_LEN_MASK ) | \ ( ( ( _val ) << SPWPNP_PNPVSTRL_LEN_SHIFT ) & \ SPWPNP_PNPVSTRL_LEN_MASK ) ) #define SPWPNP_PNPVSTRL_LEN( _val ) \ - ( ( ( _val ) << SPWPNP_PNPVSTRL_LEN_SHIFT ) & \ - SPWPNP_PNPVSTRL_LEN_MASK ) + ( ( ( _val ) << SPWPNP_PNPVSTRL_LEN_SHIFT ) & SPWPNP_PNPVSTRL_LEN_MASK ) /** @} */ @@ -399,17 +369,15 @@ extern "C" { */ #define SPWPNP_PNPPSTRL_LEN_SHIFT 0 -#define SPWPNP_PNPPSTRL_LEN_MASK 0x7fffU +#define SPWPNP_PNPPSTRL_LEN_MASK 0x7fffU #define SPWPNP_PNPPSTRL_LEN_GET( _reg ) \ - ( ( ( _reg ) & SPWPNP_PNPPSTRL_LEN_MASK ) >> \ - SPWPNP_PNPPSTRL_LEN_SHIFT ) -#define SPWPNP_PNPPSTRL_LEN_SET( _reg, _val ) \ - ( ( ( _reg ) & ~SPWPNP_PNPPSTRL_LEN_MASK ) | \ + ( ( ( _reg ) & SPWPNP_PNPPSTRL_LEN_MASK ) >> SPWPNP_PNPPSTRL_LEN_SHIFT ) +#define SPWPNP_PNPPSTRL_LEN_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWPNP_PNPPSTRL_LEN_MASK ) | \ ( ( ( _val ) << SPWPNP_PNPPSTRL_LEN_SHIFT ) & \ SPWPNP_PNPPSTRL_LEN_MASK ) ) #define SPWPNP_PNPPSTRL_LEN( _val ) \ - ( ( ( _val ) << SPWPNP_PNPPSTRL_LEN_SHIFT ) & \ - SPWPNP_PNPPSTRL_LEN_MASK ) + ( ( ( _val ) << SPWPNP_PNPPSTRL_LEN_SHIFT ) & SPWPNP_PNPPSTRL_LEN_MASK ) /** @} */ @@ -423,17 +391,14 @@ extern "C" { */ #define SPWPNP_PNPPCNT_PC_SHIFT 0 -#define SPWPNP_PNPPCNT_PC_MASK 0x1fU +#define SPWPNP_PNPPCNT_PC_MASK 0x1fU #define SPWPNP_PNPPCNT_PC_GET( _reg ) \ - ( ( ( _reg ) & SPWPNP_PNPPCNT_PC_MASK ) >> \ - SPWPNP_PNPPCNT_PC_SHIFT ) -#define SPWPNP_PNPPCNT_PC_SET( _reg, _val ) \ + ( ( ( _reg ) & SPWPNP_PNPPCNT_PC_MASK ) >> SPWPNP_PNPPCNT_PC_SHIFT ) +#define SPWPNP_PNPPCNT_PC_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPWPNP_PNPPCNT_PC_MASK ) | \ - ( ( ( _val ) << SPWPNP_PNPPCNT_PC_SHIFT ) & \ - SPWPNP_PNPPCNT_PC_MASK ) ) + ( ( ( _val ) << SPWPNP_PNPPCNT_PC_SHIFT ) & SPWPNP_PNPPCNT_PC_MASK ) ) #define SPWPNP_PNPPCNT_PC( _val ) \ - ( ( ( _val ) << SPWPNP_PNPPCNT_PC_SHIFT ) & \ - SPWPNP_PNPPCNT_PC_MASK ) + ( ( ( _val ) << SPWPNP_PNPPCNT_PC_SHIFT ) & SPWPNP_PNPPCNT_PC_MASK ) /** @} */ @@ -447,17 +412,14 @@ extern "C" { */ #define SPWPNP_PNPACNT_AC_SHIFT 0 -#define SPWPNP_PNPACNT_AC_MASK 0xffU +#define SPWPNP_PNPACNT_AC_MASK 0xffU #define SPWPNP_PNPACNT_AC_GET( _reg ) \ - ( ( ( _reg ) & SPWPNP_PNPACNT_AC_MASK ) >> \ - SPWPNP_PNPACNT_AC_SHIFT ) -#define SPWPNP_PNPACNT_AC_SET( _reg, _val ) \ + ( ( ( _reg ) & SPWPNP_PNPACNT_AC_MASK ) >> SPWPNP_PNPACNT_AC_SHIFT ) +#define SPWPNP_PNPACNT_AC_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPWPNP_PNPACNT_AC_MASK ) | \ - ( ( ( _val ) << SPWPNP_PNPACNT_AC_SHIFT ) & \ - SPWPNP_PNPACNT_AC_MASK ) ) + ( ( ( _val ) << SPWPNP_PNPACNT_AC_SHIFT ) & SPWPNP_PNPACNT_AC_MASK ) ) #define SPWPNP_PNPACNT_AC( _val ) \ - ( ( ( _val ) << SPWPNP_PNPACNT_AC_SHIFT ) & \ - SPWPNP_PNPACNT_AC_MASK ) + ( ( ( _val ) << SPWPNP_PNPACNT_AC_SHIFT ) & SPWPNP_PNPACNT_AC_MASK ) /** @} */ diff --git a/bsps/include/grlib/spwtdp-regs.h b/bsps/include/grlib/spwtdp-regs.h index 2e951e4544..21abb9cf04 100644 --- a/bsps/include/grlib/spwtdp-regs.h +++ b/bsps/include/grlib/spwtdp-regs.h @@ -98,34 +98,29 @@ extern "C" { #define SPWTDP_CONF0_AE 0x8000U #define SPWTDP_CONF0_MAPPING_SHIFT 8 -#define SPWTDP_CONF0_MAPPING_MASK 0x1f00U +#define SPWTDP_CONF0_MAPPING_MASK 0x1f00U #define SPWTDP_CONF0_MAPPING_GET( _reg ) \ - ( ( ( _reg ) & SPWTDP_CONF0_MAPPING_MASK ) >> \ - SPWTDP_CONF0_MAPPING_SHIFT ) -#define SPWTDP_CONF0_MAPPING_SET( _reg, _val ) \ - ( ( ( _reg ) & ~SPWTDP_CONF0_MAPPING_MASK ) | \ + ( ( ( _reg ) & SPWTDP_CONF0_MAPPING_MASK ) >> SPWTDP_CONF0_MAPPING_SHIFT ) +#define SPWTDP_CONF0_MAPPING_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWTDP_CONF0_MAPPING_MASK ) | \ ( ( ( _val ) << SPWTDP_CONF0_MAPPING_SHIFT ) & \ SPWTDP_CONF0_MAPPING_MASK ) ) #define SPWTDP_CONF0_MAPPING( _val ) \ - ( ( ( _val ) << SPWTDP_CONF0_MAPPING_SHIFT ) & \ - SPWTDP_CONF0_MAPPING_MASK ) + ( ( ( _val ) << SPWTDP_CONF0_MAPPING_SHIFT ) & SPWTDP_CONF0_MAPPING_MASK ) #define SPWTDP_CONF0_TD 0x80U #define SPWTDP_CONF0_MU 0x40U #define SPWTDP_CONF0_SEL_SHIFT 4 -#define SPWTDP_CONF0_SEL_MASK 0x30U +#define SPWTDP_CONF0_SEL_MASK 0x30U #define SPWTDP_CONF0_SEL_GET( _reg ) \ - ( ( ( _reg ) & SPWTDP_CONF0_SEL_MASK ) >> \ - SPWTDP_CONF0_SEL_SHIFT ) -#define SPWTDP_CONF0_SEL_SET( _reg, _val ) \ + ( ( ( _reg ) & SPWTDP_CONF0_SEL_MASK ) >> SPWTDP_CONF0_SEL_SHIFT ) +#define SPWTDP_CONF0_SEL_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPWTDP_CONF0_SEL_MASK ) | \ - ( ( ( _val ) << SPWTDP_CONF0_SEL_SHIFT ) & \ - SPWTDP_CONF0_SEL_MASK ) ) + ( ( ( _val ) << SPWTDP_CONF0_SEL_SHIFT ) & SPWTDP_CONF0_SEL_MASK ) ) #define SPWTDP_CONF0_SEL( _val ) \ - ( ( ( _val ) << SPWTDP_CONF0_SEL_SHIFT ) & \ - SPWTDP_CONF0_SEL_MASK ) + ( ( ( _val ) << SPWTDP_CONF0_SEL_SHIFT ) & SPWTDP_CONF0_SEL_MASK ) #define SPWTDP_CONF0_ME 0x8U @@ -146,17 +141,14 @@ extern "C" { */ #define SPWTDP_CONF3_STM_SHIFT 16 -#define SPWTDP_CONF3_STM_MASK 0x3f0000U +#define SPWTDP_CONF3_STM_MASK 0x3f0000U #define SPWTDP_CONF3_STM_GET( _reg ) \ - ( ( ( _reg ) & SPWTDP_CONF3_STM_MASK ) >> \ - SPWTDP_CONF3_STM_SHIFT ) -#define SPWTDP_CONF3_STM_SET( _reg, _val ) \ + ( ( ( _reg ) & SPWTDP_CONF3_STM_MASK ) >> SPWTDP_CONF3_STM_SHIFT ) +#define SPWTDP_CONF3_STM_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPWTDP_CONF3_STM_MASK ) | \ - ( ( ( _val ) << SPWTDP_CONF3_STM_SHIFT ) & \ - SPWTDP_CONF3_STM_MASK ) ) + ( ( ( _val ) << SPWTDP_CONF3_STM_SHIFT ) & SPWTDP_CONF3_STM_MASK ) ) #define SPWTDP_CONF3_STM( _val ) \ - ( ( ( _val ) << SPWTDP_CONF3_STM_SHIFT ) & \ - SPWTDP_CONF3_STM_MASK ) + ( ( ( _val ) << SPWTDP_CONF3_STM_SHIFT ) & SPWTDP_CONF3_STM_MASK ) #define SPWTDP_CONF3_DI64R 0x2000U @@ -167,30 +159,24 @@ extern "C" { #define SPWTDP_CONF3_DI 0x400U #define SPWTDP_CONF3_INRX_SHIFT 5 -#define SPWTDP_CONF3_INRX_MASK 0x3e0U +#define SPWTDP_CONF3_INRX_MASK 0x3e0U #define SPWTDP_CONF3_INRX_GET( _reg ) \ - ( ( ( _reg ) & SPWTDP_CONF3_INRX_MASK ) >> \ - SPWTDP_CONF3_INRX_SHIFT ) -#define SPWTDP_CONF3_INRX_SET( _reg, _val ) \ + ( ( ( _reg ) & SPWTDP_CONF3_INRX_MASK ) >> SPWTDP_CONF3_INRX_SHIFT ) +#define SPWTDP_CONF3_INRX_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPWTDP_CONF3_INRX_MASK ) | \ - ( ( ( _val ) << SPWTDP_CONF3_INRX_SHIFT ) & \ - SPWTDP_CONF3_INRX_MASK ) ) + ( ( ( _val ) << SPWTDP_CONF3_INRX_SHIFT ) & SPWTDP_CONF3_INRX_MASK ) ) #define SPWTDP_CONF3_INRX( _val ) \ - ( ( ( _val ) << SPWTDP_CONF3_INRX_SHIFT ) & \ - SPWTDP_CONF3_INRX_MASK ) + ( ( ( _val ) << SPWTDP_CONF3_INRX_SHIFT ) & SPWTDP_CONF3_INRX_MASK ) #define SPWTDP_CONF3_INTX_SHIFT 0 -#define SPWTDP_CONF3_INTX_MASK 0x1fU +#define SPWTDP_CONF3_INTX_MASK 0x1fU #define SPWTDP_CONF3_INTX_GET( _reg ) \ - ( ( ( _reg ) & SPWTDP_CONF3_INTX_MASK ) >> \ - SPWTDP_CONF3_INTX_SHIFT ) -#define SPWTDP_CONF3_INTX_SET( _reg, _val ) \ + ( ( ( _reg ) & SPWTDP_CONF3_INTX_MASK ) >> SPWTDP_CONF3_INTX_SHIFT ) +#define SPWTDP_CONF3_INTX_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPWTDP_CONF3_INTX_MASK ) | \ - ( ( ( _val ) << SPWTDP_CONF3_INTX_SHIFT ) & \ - SPWTDP_CONF3_INTX_MASK ) ) + ( ( ( _val ) << SPWTDP_CONF3_INTX_SHIFT ) & SPWTDP_CONF3_INTX_MASK ) ) #define SPWTDP_CONF3_INTX( _val ) \ - ( ( ( _val ) << SPWTDP_CONF3_INTX_SHIFT ) & \ - SPWTDP_CONF3_INTX_MASK ) + ( ( ( _val ) << SPWTDP_CONF3_INTX_SHIFT ) & SPWTDP_CONF3_INTX_MASK ) /** @} */ @@ -207,30 +193,24 @@ extern "C" { #define SPWTDP_CTRL_IS 0x40000000U #define SPWTDP_CTRL_SPWTC_SHIFT 16 -#define SPWTDP_CTRL_SPWTC_MASK 0xff0000U +#define SPWTDP_CTRL_SPWTC_MASK 0xff0000U #define SPWTDP_CTRL_SPWTC_GET( _reg ) \ - ( ( ( _reg ) & SPWTDP_CTRL_SPWTC_MASK ) >> \ - SPWTDP_CTRL_SPWTC_SHIFT ) -#define SPWTDP_CTRL_SPWTC_SET( _reg, _val ) \ + ( ( ( _reg ) & SPWTDP_CTRL_SPWTC_MASK ) >> SPWTDP_CTRL_SPWTC_SHIFT ) +#define SPWTDP_CTRL_SPWTC_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPWTDP_CTRL_SPWTC_MASK ) | \ - ( ( ( _val ) << SPWTDP_CTRL_SPWTC_SHIFT ) & \ - SPWTDP_CTRL_SPWTC_MASK ) ) + ( ( ( _val ) << SPWTDP_CTRL_SPWTC_SHIFT ) & SPWTDP_CTRL_SPWTC_MASK ) ) #define SPWTDP_CTRL_SPWTC( _val ) \ - ( ( ( _val ) << SPWTDP_CTRL_SPWTC_SHIFT ) & \ - SPWTDP_CTRL_SPWTC_MASK ) + ( ( ( _val ) << SPWTDP_CTRL_SPWTC_SHIFT ) & SPWTDP_CTRL_SPWTC_MASK ) #define SPWTDP_CTRL_CPF_SHIFT 0 -#define SPWTDP_CTRL_CPF_MASK 0xffffU +#define SPWTDP_CTRL_CPF_MASK 0xffffU #define SPWTDP_CTRL_CPF_GET( _reg ) \ - ( ( ( _reg ) & SPWTDP_CTRL_CPF_MASK ) >> \ - SPWTDP_CTRL_CPF_SHIFT ) -#define SPWTDP_CTRL_CPF_SET( _reg, _val ) \ + ( ( ( _reg ) & SPWTDP_CTRL_CPF_MASK ) >> SPWTDP_CTRL_CPF_SHIFT ) +#define SPWTDP_CTRL_CPF_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPWTDP_CTRL_CPF_MASK ) | \ - ( ( ( _val ) << SPWTDP_CTRL_CPF_SHIFT ) & \ - SPWTDP_CTRL_CPF_MASK ) ) + ( ( ( _val ) << SPWTDP_CTRL_CPF_SHIFT ) & SPWTDP_CTRL_CPF_MASK ) ) #define SPWTDP_CTRL_CPF( _val ) \ - ( ( ( _val ) << SPWTDP_CTRL_CPF_SHIFT ) & \ - SPWTDP_CTRL_CPF_MASK ) + ( ( ( _val ) << SPWTDP_CTRL_CPF_SHIFT ) & SPWTDP_CTRL_CPF_MASK ) /** @} */ @@ -243,17 +223,14 @@ extern "C" { */ #define SPWTDP_CET0_CET0_SHIFT 0 -#define SPWTDP_CET0_CET0_MASK 0xffffffffU +#define SPWTDP_CET0_CET0_MASK 0xffffffffU #define SPWTDP_CET0_CET0_GET( _reg ) \ - ( ( ( _reg ) & SPWTDP_CET0_CET0_MASK ) >> \ - SPWTDP_CET0_CET0_SHIFT ) -#define SPWTDP_CET0_CET0_SET( _reg, _val ) \ + ( ( ( _reg ) & SPWTDP_CET0_CET0_MASK ) >> SPWTDP_CET0_CET0_SHIFT ) +#define SPWTDP_CET0_CET0_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPWTDP_CET0_CET0_MASK ) | \ - ( ( ( _val ) << SPWTDP_CET0_CET0_SHIFT ) & \ - SPWTDP_CET0_CET0_MASK ) ) + ( ( ( _val ) << SPWTDP_CET0_CET0_SHIFT ) & SPWTDP_CET0_CET0_MASK ) ) #define SPWTDP_CET0_CET0( _val ) \ - ( ( ( _val ) << SPWTDP_CET0_CET0_SHIFT ) & \ - SPWTDP_CET0_CET0_MASK ) + ( ( ( _val ) << SPWTDP_CET0_CET0_SHIFT ) & SPWTDP_CET0_CET0_MASK ) /** @} */ @@ -266,17 +243,14 @@ extern "C" { */ #define SPWTDP_CET1_CET1_SHIFT 0 -#define SPWTDP_CET1_CET1_MASK 0xffffffffU +#define SPWTDP_CET1_CET1_MASK 0xffffffffU #define SPWTDP_CET1_CET1_GET( _reg ) \ - ( ( ( _reg ) & SPWTDP_CET1_CET1_MASK ) >> \ - SPWTDP_CET1_CET1_SHIFT ) -#define SPWTDP_CET1_CET1_SET( _reg, _val ) \ + ( ( ( _reg ) & SPWTDP_CET1_CET1_MASK ) >> SPWTDP_CET1_CET1_SHIFT ) +#define SPWTDP_CET1_CET1_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPWTDP_CET1_CET1_MASK ) | \ - ( ( ( _val ) << SPWTDP_CET1_CET1_SHIFT ) & \ - SPWTDP_CET1_CET1_MASK ) ) + ( ( ( _val ) << SPWTDP_CET1_CET1_SHIFT ) & SPWTDP_CET1_CET1_MASK ) ) #define SPWTDP_CET1_CET1( _val ) \ - ( ( ( _val ) << SPWTDP_CET1_CET1_SHIFT ) & \ - SPWTDP_CET1_CET1_MASK ) + ( ( ( _val ) << SPWTDP_CET1_CET1_SHIFT ) & SPWTDP_CET1_CET1_MASK ) /** @} */ @@ -289,17 +263,14 @@ extern "C" { */ #define SPWTDP_CET2_CET2_SHIFT 0 -#define SPWTDP_CET2_CET2_MASK 0xffffffffU +#define SPWTDP_CET2_CET2_MASK 0xffffffffU #define SPWTDP_CET2_CET2_GET( _reg ) \ - ( ( ( _reg ) & SPWTDP_CET2_CET2_MASK ) >> \ - SPWTDP_CET2_CET2_SHIFT ) -#define SPWTDP_CET2_CET2_SET( _reg, _val ) \ + ( ( ( _reg ) & SPWTDP_CET2_CET2_MASK ) >> SPWTDP_CET2_CET2_SHIFT ) +#define SPWTDP_CET2_CET2_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPWTDP_CET2_CET2_MASK ) | \ - ( ( ( _val ) << SPWTDP_CET2_CET2_SHIFT ) & \ - SPWTDP_CET2_CET2_MASK ) ) + ( ( ( _val ) << SPWTDP_CET2_CET2_SHIFT ) & SPWTDP_CET2_CET2_MASK ) ) #define SPWTDP_CET2_CET2( _val ) \ - ( ( ( _val ) << SPWTDP_CET2_CET2_SHIFT ) & \ - SPWTDP_CET2_CET2_MASK ) + ( ( ( _val ) << SPWTDP_CET2_CET2_SHIFT ) & SPWTDP_CET2_CET2_MASK ) /** @} */ @@ -312,17 +283,14 @@ extern "C" { */ #define SPWTDP_CET3_CET3_SHIFT 0 -#define SPWTDP_CET3_CET3_MASK 0xffffffffU +#define SPWTDP_CET3_CET3_MASK 0xffffffffU #define SPWTDP_CET3_CET3_GET( _reg ) \ - ( ( ( _reg ) & SPWTDP_CET3_CET3_MASK ) >> \ - SPWTDP_CET3_CET3_SHIFT ) -#define SPWTDP_CET3_CET3_SET( _reg, _val ) \ + ( ( ( _reg ) & SPWTDP_CET3_CET3_MASK ) >> SPWTDP_CET3_CET3_SHIFT ) +#define SPWTDP_CET3_CET3_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPWTDP_CET3_CET3_MASK ) | \ - ( ( ( _val ) << SPWTDP_CET3_CET3_SHIFT ) & \ - SPWTDP_CET3_CET3_MASK ) ) + ( ( ( _val ) << SPWTDP_CET3_CET3_SHIFT ) & SPWTDP_CET3_CET3_MASK ) ) #define SPWTDP_CET3_CET3( _val ) \ - ( ( ( _val ) << SPWTDP_CET3_CET3_SHIFT ) & \ - SPWTDP_CET3_CET3_MASK ) + ( ( ( _val ) << SPWTDP_CET3_CET3_SHIFT ) & SPWTDP_CET3_CET3_MASK ) /** @} */ @@ -335,17 +303,14 @@ extern "C" { */ #define SPWTDP_CET4_CET4_SHIFT 24 -#define SPWTDP_CET4_CET4_MASK 0xff000000U +#define SPWTDP_CET4_CET4_MASK 0xff000000U #define SPWTDP_CET4_CET4_GET( _reg ) \ - ( ( ( _reg ) & SPWTDP_CET4_CET4_MASK ) >> \ - SPWTDP_CET4_CET4_SHIFT ) -#define SPWTDP_CET4_CET4_SET( _reg, _val ) \ + ( ( ( _reg ) & SPWTDP_CET4_CET4_MASK ) >> SPWTDP_CET4_CET4_SHIFT ) +#define SPWTDP_CET4_CET4_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPWTDP_CET4_CET4_MASK ) | \ - ( ( ( _val ) << SPWTDP_CET4_CET4_SHIFT ) & \ - SPWTDP_CET4_CET4_MASK ) ) + ( ( ( _val ) << SPWTDP_CET4_CET4_SHIFT ) & SPWTDP_CET4_CET4_MASK ) ) #define SPWTDP_CET4_CET4( _val ) \ - ( ( ( _val ) << SPWTDP_CET4_CET4_SHIFT ) & \ - SPWTDP_CET4_CET4_MASK ) + ( ( ( _val ) << SPWTDP_CET4_CET4_SHIFT ) & SPWTDP_CET4_CET4_MASK ) /** @} */ @@ -358,17 +323,14 @@ extern "C" { */ #define SPWTDP_DPF_DPF_SHIFT 0 -#define SPWTDP_DPF_DPF_MASK 0xffffU +#define SPWTDP_DPF_DPF_MASK 0xffffU #define SPWTDP_DPF_DPF_GET( _reg ) \ - ( ( ( _reg ) & SPWTDP_DPF_DPF_MASK ) >> \ - SPWTDP_DPF_DPF_SHIFT ) -#define SPWTDP_DPF_DPF_SET( _reg, _val ) \ + ( ( ( _reg ) & SPWTDP_DPF_DPF_MASK ) >> SPWTDP_DPF_DPF_SHIFT ) +#define SPWTDP_DPF_DPF_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPWTDP_DPF_DPF_MASK ) | \ - ( ( ( _val ) << SPWTDP_DPF_DPF_SHIFT ) & \ - SPWTDP_DPF_DPF_MASK ) ) + ( ( ( _val ) << SPWTDP_DPF_DPF_SHIFT ) & SPWTDP_DPF_DPF_MASK ) ) #define SPWTDP_DPF_DPF( _val ) \ - ( ( ( _val ) << SPWTDP_DPF_DPF_SHIFT ) & \ - SPWTDP_DPF_DPF_MASK ) + ( ( ( _val ) << SPWTDP_DPF_DPF_SHIFT ) & SPWTDP_DPF_DPF_MASK ) /** @} */ @@ -381,17 +343,14 @@ extern "C" { */ #define SPWTDP_DET0_DET0_SHIFT 0 -#define SPWTDP_DET0_DET0_MASK 0xffffffffU +#define SPWTDP_DET0_DET0_MASK 0xffffffffU #define SPWTDP_DET0_DET0_GET( _reg ) \ - ( ( ( _reg ) & SPWTDP_DET0_DET0_MASK ) >> \ - SPWTDP_DET0_DET0_SHIFT ) -#define SPWTDP_DET0_DET0_SET( _reg, _val ) \ + ( ( ( _reg ) & SPWTDP_DET0_DET0_MASK ) >> SPWTDP_DET0_DET0_SHIFT ) +#define SPWTDP_DET0_DET0_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPWTDP_DET0_DET0_MASK ) | \ - ( ( ( _val ) << SPWTDP_DET0_DET0_SHIFT ) & \ - SPWTDP_DET0_DET0_MASK ) ) + ( ( ( _val ) << SPWTDP_DET0_DET0_SHIFT ) & SPWTDP_DET0_DET0_MASK ) ) #define SPWTDP_DET0_DET0( _val ) \ - ( ( ( _val ) << SPWTDP_DET0_DET0_SHIFT ) & \ - SPWTDP_DET0_DET0_MASK ) + ( ( ( _val ) << SPWTDP_DET0_DET0_SHIFT ) & SPWTDP_DET0_DET0_MASK ) /** @} */ @@ -404,17 +363,14 @@ extern "C" { */ #define SPWTDP_DET1_DET1_SHIFT 0 -#define SPWTDP_DET1_DET1_MASK 0xffffffffU +#define SPWTDP_DET1_DET1_MASK 0xffffffffU #define SPWTDP_DET1_DET1_GET( _reg ) \ - ( ( ( _reg ) & SPWTDP_DET1_DET1_MASK ) >> \ - SPWTDP_DET1_DET1_SHIFT ) -#define SPWTDP_DET1_DET1_SET( _reg, _val ) \ + ( ( ( _reg ) & SPWTDP_DET1_DET1_MASK ) >> SPWTDP_DET1_DET1_SHIFT ) +#define SPWTDP_DET1_DET1_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPWTDP_DET1_DET1_MASK ) | \ - ( ( ( _val ) << SPWTDP_DET1_DET1_SHIFT ) & \ - SPWTDP_DET1_DET1_MASK ) ) + ( ( ( _val ) << SPWTDP_DET1_DET1_SHIFT ) & SPWTDP_DET1_DET1_MASK ) ) #define SPWTDP_DET1_DET1( _val ) \ - ( ( ( _val ) << SPWTDP_DET1_DET1_SHIFT ) & \ - SPWTDP_DET1_DET1_MASK ) + ( ( ( _val ) << SPWTDP_DET1_DET1_SHIFT ) & SPWTDP_DET1_DET1_MASK ) /** @} */ @@ -427,17 +383,14 @@ extern "C" { */ #define SPWTDP_DET2_DET2_SHIFT 0 -#define SPWTDP_DET2_DET2_MASK 0xffffffffU +#define SPWTDP_DET2_DET2_MASK 0xffffffffU #define SPWTDP_DET2_DET2_GET( _reg ) \ - ( ( ( _reg ) & SPWTDP_DET2_DET2_MASK ) >> \ - SPWTDP_DET2_DET2_SHIFT ) -#define SPWTDP_DET2_DET2_SET( _reg, _val ) \ + ( ( ( _reg ) & SPWTDP_DET2_DET2_MASK ) >> SPWTDP_DET2_DET2_SHIFT ) +#define SPWTDP_DET2_DET2_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPWTDP_DET2_DET2_MASK ) | \ - ( ( ( _val ) << SPWTDP_DET2_DET2_SHIFT ) & \ - SPWTDP_DET2_DET2_MASK ) ) + ( ( ( _val ) << SPWTDP_DET2_DET2_SHIFT ) & SPWTDP_DET2_DET2_MASK ) ) #define SPWTDP_DET2_DET2( _val ) \ - ( ( ( _val ) << SPWTDP_DET2_DET2_SHIFT ) & \ - SPWTDP_DET2_DET2_MASK ) + ( ( ( _val ) << SPWTDP_DET2_DET2_SHIFT ) & SPWTDP_DET2_DET2_MASK ) /** @} */ @@ -450,17 +403,14 @@ extern "C" { */ #define SPWTDP_DET3_DET3_SHIFT 0 -#define SPWTDP_DET3_DET3_MASK 0xffffffffU +#define SPWTDP_DET3_DET3_MASK 0xffffffffU #define SPWTDP_DET3_DET3_GET( _reg ) \ - ( ( ( _reg ) & SPWTDP_DET3_DET3_MASK ) >> \ - SPWTDP_DET3_DET3_SHIFT ) -#define SPWTDP_DET3_DET3_SET( _reg, _val ) \ + ( ( ( _reg ) & SPWTDP_DET3_DET3_MASK ) >> SPWTDP_DET3_DET3_SHIFT ) +#define SPWTDP_DET3_DET3_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPWTDP_DET3_DET3_MASK ) | \ - ( ( ( _val ) << SPWTDP_DET3_DET3_SHIFT ) & \ - SPWTDP_DET3_DET3_MASK ) ) + ( ( ( _val ) << SPWTDP_DET3_DET3_SHIFT ) & SPWTDP_DET3_DET3_MASK ) ) #define SPWTDP_DET3_DET3( _val ) \ - ( ( ( _val ) << SPWTDP_DET3_DET3_SHIFT ) & \ - SPWTDP_DET3_DET3_MASK ) + ( ( ( _val ) << SPWTDP_DET3_DET3_SHIFT ) & SPWTDP_DET3_DET3_MASK ) /** @} */ @@ -473,17 +423,14 @@ extern "C" { */ #define SPWTDP_DET4_DET4_SHIFT 24 -#define SPWTDP_DET4_DET4_MASK 0xff000000U +#define SPWTDP_DET4_DET4_MASK 0xff000000U #define SPWTDP_DET4_DET4_GET( _reg ) \ - ( ( ( _reg ) & SPWTDP_DET4_DET4_MASK ) >> \ - SPWTDP_DET4_DET4_SHIFT ) -#define SPWTDP_DET4_DET4_SET( _reg, _val ) \ + ( ( ( _reg ) & SPWTDP_DET4_DET4_MASK ) >> SPWTDP_DET4_DET4_SHIFT ) +#define SPWTDP_DET4_DET4_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPWTDP_DET4_DET4_MASK ) | \ - ( ( ( _val ) << SPWTDP_DET4_DET4_SHIFT ) & \ - SPWTDP_DET4_DET4_MASK ) ) + ( ( ( _val ) << SPWTDP_DET4_DET4_SHIFT ) & SPWTDP_DET4_DET4_MASK ) ) #define SPWTDP_DET4_DET4( _val ) \ - ( ( ( _val ) << SPWTDP_DET4_DET4_SHIFT ) & \ - SPWTDP_DET4_DET4_MASK ) + ( ( ( _val ) << SPWTDP_DET4_DET4_SHIFT ) & SPWTDP_DET4_DET4_MASK ) /** @} */ @@ -496,17 +443,14 @@ extern "C" { */ #define SPWTDP_TRPFRX_TRPF_SHIFT 0 -#define SPWTDP_TRPFRX_TRPF_MASK 0xffffU +#define SPWTDP_TRPFRX_TRPF_MASK 0xffffU #define SPWTDP_TRPFRX_TRPF_GET( _reg ) \ - ( ( ( _reg ) & SPWTDP_TRPFRX_TRPF_MASK ) >> \ - SPWTDP_TRPFRX_TRPF_SHIFT ) -#define SPWTDP_TRPFRX_TRPF_SET( _reg, _val ) \ + ( ( ( _reg ) & SPWTDP_TRPFRX_TRPF_MASK ) >> SPWTDP_TRPFRX_TRPF_SHIFT ) +#define SPWTDP_TRPFRX_TRPF_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPWTDP_TRPFRX_TRPF_MASK ) | \ - ( ( ( _val ) << SPWTDP_TRPFRX_TRPF_SHIFT ) & \ - SPWTDP_TRPFRX_TRPF_MASK ) ) + ( ( ( _val ) << SPWTDP_TRPFRX_TRPF_SHIFT ) & SPWTDP_TRPFRX_TRPF_MASK ) ) #define SPWTDP_TRPFRX_TRPF( _val ) \ - ( ( ( _val ) << SPWTDP_TRPFRX_TRPF_SHIFT ) & \ - SPWTDP_TRPFRX_TRPF_MASK ) + ( ( ( _val ) << SPWTDP_TRPFRX_TRPF_SHIFT ) & SPWTDP_TRPFRX_TRPF_MASK ) /** @} */ @@ -519,17 +463,14 @@ extern "C" { */ #define SPWTDP_TR0_TR0_SHIFT 0 -#define SPWTDP_TR0_TR0_MASK 0xffffffffU +#define SPWTDP_TR0_TR0_MASK 0xffffffffU #define SPWTDP_TR0_TR0_GET( _reg ) \ - ( ( ( _reg ) & SPWTDP_TR0_TR0_MASK ) >> \ - SPWTDP_TR0_TR0_SHIFT ) -#define SPWTDP_TR0_TR0_SET( _reg, _val ) \ + ( ( ( _reg ) & SPWTDP_TR0_TR0_MASK ) >> SPWTDP_TR0_TR0_SHIFT ) +#define SPWTDP_TR0_TR0_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPWTDP_TR0_TR0_MASK ) | \ - ( ( ( _val ) << SPWTDP_TR0_TR0_SHIFT ) & \ - SPWTDP_TR0_TR0_MASK ) ) + ( ( ( _val ) << SPWTDP_TR0_TR0_SHIFT ) & SPWTDP_TR0_TR0_MASK ) ) #define SPWTDP_TR0_TR0( _val ) \ - ( ( ( _val ) << SPWTDP_TR0_TR0_SHIFT ) & \ - SPWTDP_TR0_TR0_MASK ) + ( ( ( _val ) << SPWTDP_TR0_TR0_SHIFT ) & SPWTDP_TR0_TR0_MASK ) /** @} */ @@ -542,17 +483,14 @@ extern "C" { */ #define SPWTDP_TR1_TR1_SHIFT 0 -#define SPWTDP_TR1_TR1_MASK 0xffffffffU +#define SPWTDP_TR1_TR1_MASK 0xffffffffU #define SPWTDP_TR1_TR1_GET( _reg ) \ - ( ( ( _reg ) & SPWTDP_TR1_TR1_MASK ) >> \ - SPWTDP_TR1_TR1_SHIFT ) -#define SPWTDP_TR1_TR1_SET( _reg, _val ) \ + ( ( ( _reg ) & SPWTDP_TR1_TR1_MASK ) >> SPWTDP_TR1_TR1_SHIFT ) +#define SPWTDP_TR1_TR1_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPWTDP_TR1_TR1_MASK ) | \ - ( ( ( _val ) << SPWTDP_TR1_TR1_SHIFT ) & \ - SPWTDP_TR1_TR1_MASK ) ) + ( ( ( _val ) << SPWTDP_TR1_TR1_SHIFT ) & SPWTDP_TR1_TR1_MASK ) ) #define SPWTDP_TR1_TR1( _val ) \ - ( ( ( _val ) << SPWTDP_TR1_TR1_SHIFT ) & \ - SPWTDP_TR1_TR1_MASK ) + ( ( ( _val ) << SPWTDP_TR1_TR1_SHIFT ) & SPWTDP_TR1_TR1_MASK ) /** @} */ @@ -565,17 +503,14 @@ extern "C" { */ #define SPWTDP_TR2_TR2_SHIFT 0 -#define SPWTDP_TR2_TR2_MASK 0xffffffffU +#define SPWTDP_TR2_TR2_MASK 0xffffffffU #define SPWTDP_TR2_TR2_GET( _reg ) \ - ( ( ( _reg ) & SPWTDP_TR2_TR2_MASK ) >> \ - SPWTDP_TR2_TR2_SHIFT ) -#define SPWTDP_TR2_TR2_SET( _reg, _val ) \ + ( ( ( _reg ) & SPWTDP_TR2_TR2_MASK ) >> SPWTDP_TR2_TR2_SHIFT ) +#define SPWTDP_TR2_TR2_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPWTDP_TR2_TR2_MASK ) | \ - ( ( ( _val ) << SPWTDP_TR2_TR2_SHIFT ) & \ - SPWTDP_TR2_TR2_MASK ) ) + ( ( ( _val ) << SPWTDP_TR2_TR2_SHIFT ) & SPWTDP_TR2_TR2_MASK ) ) #define SPWTDP_TR2_TR2( _val ) \ - ( ( ( _val ) << SPWTDP_TR2_TR2_SHIFT ) & \ - SPWTDP_TR2_TR2_MASK ) + ( ( ( _val ) << SPWTDP_TR2_TR2_SHIFT ) & SPWTDP_TR2_TR2_MASK ) /** @} */ @@ -588,17 +523,14 @@ extern "C" { */ #define SPWTDP_TR3_TR3_SHIFT 0 -#define SPWTDP_TR3_TR3_MASK 0xffffffffU +#define SPWTDP_TR3_TR3_MASK 0xffffffffU #define SPWTDP_TR3_TR3_GET( _reg ) \ - ( ( ( _reg ) & SPWTDP_TR3_TR3_MASK ) >> \ - SPWTDP_TR3_TR3_SHIFT ) -#define SPWTDP_TR3_TR3_SET( _reg, _val ) \ + ( ( ( _reg ) & SPWTDP_TR3_TR3_MASK ) >> SPWTDP_TR3_TR3_SHIFT ) +#define SPWTDP_TR3_TR3_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPWTDP_TR3_TR3_MASK ) | \ - ( ( ( _val ) << SPWTDP_TR3_TR3_SHIFT ) & \ - SPWTDP_TR3_TR3_MASK ) ) + ( ( ( _val ) << SPWTDP_TR3_TR3_SHIFT ) & SPWTDP_TR3_TR3_MASK ) ) #define SPWTDP_TR3_TR3( _val ) \ - ( ( ( _val ) << SPWTDP_TR3_TR3_SHIFT ) & \ - SPWTDP_TR3_TR3_MASK ) + ( ( ( _val ) << SPWTDP_TR3_TR3_SHIFT ) & SPWTDP_TR3_TR3_MASK ) /** @} */ @@ -611,17 +543,14 @@ extern "C" { */ #define SPWTDP_TR4_TR4_SHIFT 24 -#define SPWTDP_TR4_TR4_MASK 0xff000000U +#define SPWTDP_TR4_TR4_MASK 0xff000000U #define SPWTDP_TR4_TR4_GET( _reg ) \ - ( ( ( _reg ) & SPWTDP_TR4_TR4_MASK ) >> \ - SPWTDP_TR4_TR4_SHIFT ) -#define SPWTDP_TR4_TR4_SET( _reg, _val ) \ + ( ( ( _reg ) & SPWTDP_TR4_TR4_MASK ) >> SPWTDP_TR4_TR4_SHIFT ) +#define SPWTDP_TR4_TR4_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPWTDP_TR4_TR4_MASK ) | \ - ( ( ( _val ) << SPWTDP_TR4_TR4_SHIFT ) & \ - SPWTDP_TR4_TR4_MASK ) ) + ( ( ( _val ) << SPWTDP_TR4_TR4_SHIFT ) & SPWTDP_TR4_TR4_MASK ) ) #define SPWTDP_TR4_TR4( _val ) \ - ( ( ( _val ) << SPWTDP_TR4_TR4_SHIFT ) & \ - SPWTDP_TR4_TR4_MASK ) + ( ( ( _val ) << SPWTDP_TR4_TR4_SHIFT ) & SPWTDP_TR4_TR4_MASK ) /** @} */ @@ -635,30 +564,24 @@ extern "C" { */ #define SPWTDP_TTPFTX_TSTC_SHIFT 24 -#define SPWTDP_TTPFTX_TSTC_MASK 0xff000000U +#define SPWTDP_TTPFTX_TSTC_MASK 0xff000000U #define SPWTDP_TTPFTX_TSTC_GET( _reg ) \ - ( ( ( _reg ) & SPWTDP_TTPFTX_TSTC_MASK ) >> \ - SPWTDP_TTPFTX_TSTC_SHIFT ) -#define SPWTDP_TTPFTX_TSTC_SET( _reg, _val ) \ + ( ( ( _reg ) & SPWTDP_TTPFTX_TSTC_MASK ) >> SPWTDP_TTPFTX_TSTC_SHIFT ) +#define SPWTDP_TTPFTX_TSTC_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPWTDP_TTPFTX_TSTC_MASK ) | \ - ( ( ( _val ) << SPWTDP_TTPFTX_TSTC_SHIFT ) & \ - SPWTDP_TTPFTX_TSTC_MASK ) ) + ( ( ( _val ) << SPWTDP_TTPFTX_TSTC_SHIFT ) & SPWTDP_TTPFTX_TSTC_MASK ) ) #define SPWTDP_TTPFTX_TSTC( _val ) \ - ( ( ( _val ) << SPWTDP_TTPFTX_TSTC_SHIFT ) & \ - SPWTDP_TTPFTX_TSTC_MASK ) + ( ( ( _val ) << SPWTDP_TTPFTX_TSTC_SHIFT ) & SPWTDP_TTPFTX_TSTC_MASK ) #define SPWTDP_TTPFTX_TTPF_SHIFT 0 -#define SPWTDP_TTPFTX_TTPF_MASK 0xffffU +#define SPWTDP_TTPFTX_TTPF_MASK 0xffffU #define SPWTDP_TTPFTX_TTPF_GET( _reg ) \ - ( ( ( _reg ) & SPWTDP_TTPFTX_TTPF_MASK ) >> \ - SPWTDP_TTPFTX_TTPF_SHIFT ) -#define SPWTDP_TTPFTX_TTPF_SET( _reg, _val ) \ + ( ( ( _reg ) & SPWTDP_TTPFTX_TTPF_MASK ) >> SPWTDP_TTPFTX_TTPF_SHIFT ) +#define SPWTDP_TTPFTX_TTPF_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPWTDP_TTPFTX_TTPF_MASK ) | \ - ( ( ( _val ) << SPWTDP_TTPFTX_TTPF_SHIFT ) & \ - SPWTDP_TTPFTX_TTPF_MASK ) ) + ( ( ( _val ) << SPWTDP_TTPFTX_TTPF_SHIFT ) & SPWTDP_TTPFTX_TTPF_MASK ) ) #define SPWTDP_TTPFTX_TTPF( _val ) \ - ( ( ( _val ) << SPWTDP_TTPFTX_TTPF_SHIFT ) & \ - SPWTDP_TTPFTX_TTPF_MASK ) + ( ( ( _val ) << SPWTDP_TTPFTX_TTPF_SHIFT ) & SPWTDP_TTPFTX_TTPF_MASK ) /** @} */ @@ -671,17 +594,14 @@ extern "C" { */ #define SPWTDP_TT0_TT0_SHIFT 0 -#define SPWTDP_TT0_TT0_MASK 0xffffffffU +#define SPWTDP_TT0_TT0_MASK 0xffffffffU #define SPWTDP_TT0_TT0_GET( _reg ) \ - ( ( ( _reg ) & SPWTDP_TT0_TT0_MASK ) >> \ - SPWTDP_TT0_TT0_SHIFT ) -#define SPWTDP_TT0_TT0_SET( _reg, _val ) \ + ( ( ( _reg ) & SPWTDP_TT0_TT0_MASK ) >> SPWTDP_TT0_TT0_SHIFT ) +#define SPWTDP_TT0_TT0_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPWTDP_TT0_TT0_MASK ) | \ - ( ( ( _val ) << SPWTDP_TT0_TT0_SHIFT ) & \ - SPWTDP_TT0_TT0_MASK ) ) + ( ( ( _val ) << SPWTDP_TT0_TT0_SHIFT ) & SPWTDP_TT0_TT0_MASK ) ) #define SPWTDP_TT0_TT0( _val ) \ - ( ( ( _val ) << SPWTDP_TT0_TT0_SHIFT ) & \ - SPWTDP_TT0_TT0_MASK ) + ( ( ( _val ) << SPWTDP_TT0_TT0_SHIFT ) & SPWTDP_TT0_TT0_MASK ) /** @} */ @@ -694,17 +614,14 @@ extern "C" { */ #define SPWTDP_TT1_TT1_SHIFT 0 -#define SPWTDP_TT1_TT1_MASK 0xffffffffU +#define SPWTDP_TT1_TT1_MASK 0xffffffffU #define SPWTDP_TT1_TT1_GET( _reg ) \ - ( ( ( _reg ) & SPWTDP_TT1_TT1_MASK ) >> \ - SPWTDP_TT1_TT1_SHIFT ) -#define SPWTDP_TT1_TT1_SET( _reg, _val ) \ + ( ( ( _reg ) & SPWTDP_TT1_TT1_MASK ) >> SPWTDP_TT1_TT1_SHIFT ) +#define SPWTDP_TT1_TT1_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPWTDP_TT1_TT1_MASK ) | \ - ( ( ( _val ) << SPWTDP_TT1_TT1_SHIFT ) & \ - SPWTDP_TT1_TT1_MASK ) ) + ( ( ( _val ) << SPWTDP_TT1_TT1_SHIFT ) & SPWTDP_TT1_TT1_MASK ) ) #define SPWTDP_TT1_TT1( _val ) \ - ( ( ( _val ) << SPWTDP_TT1_TT1_SHIFT ) & \ - SPWTDP_TT1_TT1_MASK ) + ( ( ( _val ) << SPWTDP_TT1_TT1_SHIFT ) & SPWTDP_TT1_TT1_MASK ) /** @} */ @@ -717,17 +634,14 @@ extern "C" { */ #define SPWTDP_TT2_TT2_SHIFT 0 -#define SPWTDP_TT2_TT2_MASK 0xffffffffU +#define SPWTDP_TT2_TT2_MASK 0xffffffffU #define SPWTDP_TT2_TT2_GET( _reg ) \ - ( ( ( _reg ) & SPWTDP_TT2_TT2_MASK ) >> \ - SPWTDP_TT2_TT2_SHIFT ) -#define SPWTDP_TT2_TT2_SET( _reg, _val ) \ + ( ( ( _reg ) & SPWTDP_TT2_TT2_MASK ) >> SPWTDP_TT2_TT2_SHIFT ) +#define SPWTDP_TT2_TT2_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPWTDP_TT2_TT2_MASK ) | \ - ( ( ( _val ) << SPWTDP_TT2_TT2_SHIFT ) & \ - SPWTDP_TT2_TT2_MASK ) ) + ( ( ( _val ) << SPWTDP_TT2_TT2_SHIFT ) & SPWTDP_TT2_TT2_MASK ) ) #define SPWTDP_TT2_TT2( _val ) \ - ( ( ( _val ) << SPWTDP_TT2_TT2_SHIFT ) & \ - SPWTDP_TT2_TT2_MASK ) + ( ( ( _val ) << SPWTDP_TT2_TT2_SHIFT ) & SPWTDP_TT2_TT2_MASK ) /** @} */ @@ -740,17 +654,14 @@ extern "C" { */ #define SPWTDP_TT3_TT3_SHIFT 0 -#define SPWTDP_TT3_TT3_MASK 0xffffffffU +#define SPWTDP_TT3_TT3_MASK 0xffffffffU #define SPWTDP_TT3_TT3_GET( _reg ) \ - ( ( ( _reg ) & SPWTDP_TT3_TT3_MASK ) >> \ - SPWTDP_TT3_TT3_SHIFT ) -#define SPWTDP_TT3_TT3_SET( _reg, _val ) \ + ( ( ( _reg ) & SPWTDP_TT3_TT3_MASK ) >> SPWTDP_TT3_TT3_SHIFT ) +#define SPWTDP_TT3_TT3_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPWTDP_TT3_TT3_MASK ) | \ - ( ( ( _val ) << SPWTDP_TT3_TT3_SHIFT ) & \ - SPWTDP_TT3_TT3_MASK ) ) + ( ( ( _val ) << SPWTDP_TT3_TT3_SHIFT ) & SPWTDP_TT3_TT3_MASK ) ) #define SPWTDP_TT3_TT3( _val ) \ - ( ( ( _val ) << SPWTDP_TT3_TT3_SHIFT ) & \ - SPWTDP_TT3_TT3_MASK ) + ( ( ( _val ) << SPWTDP_TT3_TT3_SHIFT ) & SPWTDP_TT3_TT3_MASK ) /** @} */ @@ -763,17 +674,14 @@ extern "C" { */ #define SPWTDP_TT4_TT4_SHIFT 24 -#define SPWTDP_TT4_TT4_MASK 0xff000000U +#define SPWTDP_TT4_TT4_MASK 0xff000000U #define SPWTDP_TT4_TT4_GET( _reg ) \ - ( ( ( _reg ) & SPWTDP_TT4_TT4_MASK ) >> \ - SPWTDP_TT4_TT4_SHIFT ) -#define SPWTDP_TT4_TT4_SET( _reg, _val ) \ + ( ( ( _reg ) & SPWTDP_TT4_TT4_MASK ) >> SPWTDP_TT4_TT4_SHIFT ) +#define SPWTDP_TT4_TT4_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPWTDP_TT4_TT4_MASK ) | \ - ( ( ( _val ) << SPWTDP_TT4_TT4_SHIFT ) & \ - SPWTDP_TT4_TT4_MASK ) ) + ( ( ( _val ) << SPWTDP_TT4_TT4_SHIFT ) & SPWTDP_TT4_TT4_MASK ) ) #define SPWTDP_TT4_TT4( _val ) \ - ( ( ( _val ) << SPWTDP_TT4_TT4_SHIFT ) & \ - SPWTDP_TT4_TT4_MASK ) + ( ( ( _val ) << SPWTDP_TT4_TT4_SHIFT ) & SPWTDP_TT4_TT4_MASK ) /** @} */ @@ -786,17 +694,14 @@ extern "C" { */ #define SPWTDP_LPF_LPF_SHIFT 0 -#define SPWTDP_LPF_LPF_MASK 0xffffU +#define SPWTDP_LPF_LPF_MASK 0xffffU #define SPWTDP_LPF_LPF_GET( _reg ) \ - ( ( ( _reg ) & SPWTDP_LPF_LPF_MASK ) >> \ - SPWTDP_LPF_LPF_SHIFT ) -#define SPWTDP_LPF_LPF_SET( _reg, _val ) \ + ( ( ( _reg ) & SPWTDP_LPF_LPF_MASK ) >> SPWTDP_LPF_LPF_SHIFT ) +#define SPWTDP_LPF_LPF_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPWTDP_LPF_LPF_MASK ) | \ - ( ( ( _val ) << SPWTDP_LPF_LPF_SHIFT ) & \ - SPWTDP_LPF_LPF_MASK ) ) + ( ( ( _val ) << SPWTDP_LPF_LPF_SHIFT ) & SPWTDP_LPF_LPF_MASK ) ) #define SPWTDP_LPF_LPF( _val ) \ - ( ( ( _val ) << SPWTDP_LPF_LPF_SHIFT ) & \ - SPWTDP_LPF_LPF_MASK ) + ( ( ( _val ) << SPWTDP_LPF_LPF_SHIFT ) & SPWTDP_LPF_LPF_MASK ) /** @} */ @@ -843,17 +748,14 @@ extern "C" { */ #define SPWTDP_DC_DC_SHIFT 0 -#define SPWTDP_DC_DC_MASK 0x7fffU +#define SPWTDP_DC_DC_MASK 0x7fffU #define SPWTDP_DC_DC_GET( _reg ) \ - ( ( ( _reg ) & SPWTDP_DC_DC_MASK ) >> \ - SPWTDP_DC_DC_SHIFT ) -#define SPWTDP_DC_DC_SET( _reg, _val ) \ + ( ( ( _reg ) & SPWTDP_DC_DC_MASK ) >> SPWTDP_DC_DC_SHIFT ) +#define SPWTDP_DC_DC_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPWTDP_DC_DC_MASK ) | \ - ( ( ( _val ) << SPWTDP_DC_DC_SHIFT ) & \ - SPWTDP_DC_DC_MASK ) ) + ( ( ( _val ) << SPWTDP_DC_DC_SHIFT ) & SPWTDP_DC_DC_MASK ) ) #define SPWTDP_DC_DC( _val ) \ - ( ( ( _val ) << SPWTDP_DC_DC_SHIFT ) & \ - SPWTDP_DC_DC_MASK ) + ( ( ( _val ) << SPWTDP_DC_DC_SHIFT ) & SPWTDP_DC_DC_MASK ) /** @} */ @@ -868,17 +770,14 @@ extern "C" { #define SPWTDP_DS_EN 0x80000000U #define SPWTDP_DS_CD_SHIFT 0 -#define SPWTDP_DS_CD_MASK 0xffffffU +#define SPWTDP_DS_CD_MASK 0xffffffU #define SPWTDP_DS_CD_GET( _reg ) \ - ( ( ( _reg ) & SPWTDP_DS_CD_MASK ) >> \ - SPWTDP_DS_CD_SHIFT ) -#define SPWTDP_DS_CD_SET( _reg, _val ) \ + ( ( ( _reg ) & SPWTDP_DS_CD_MASK ) >> SPWTDP_DS_CD_SHIFT ) +#define SPWTDP_DS_CD_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPWTDP_DS_CD_MASK ) | \ - ( ( ( _val ) << SPWTDP_DS_CD_SHIFT ) & \ - SPWTDP_DS_CD_MASK ) ) + ( ( ( _val ) << SPWTDP_DS_CD_SHIFT ) & SPWTDP_DS_CD_MASK ) ) #define SPWTDP_DS_CD( _val ) \ - ( ( ( _val ) << SPWTDP_DS_CD_SHIFT ) & \ - SPWTDP_DS_CD_MASK ) + ( ( ( _val ) << SPWTDP_DS_CD_SHIFT ) & SPWTDP_DS_CD_MASK ) /** @} */ @@ -891,17 +790,14 @@ extern "C" { */ #define SPWTDP_EDM0_EDM0_SHIFT 0 -#define SPWTDP_EDM0_EDM0_MASK 0xffffffffU +#define SPWTDP_EDM0_EDM0_MASK 0xffffffffU #define SPWTDP_EDM0_EDM0_GET( _reg ) \ - ( ( ( _reg ) & SPWTDP_EDM0_EDM0_MASK ) >> \ - SPWTDP_EDM0_EDM0_SHIFT ) -#define SPWTDP_EDM0_EDM0_SET( _reg, _val ) \ + ( ( ( _reg ) & SPWTDP_EDM0_EDM0_MASK ) >> SPWTDP_EDM0_EDM0_SHIFT ) +#define SPWTDP_EDM0_EDM0_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPWTDP_EDM0_EDM0_MASK ) | \ - ( ( ( _val ) << SPWTDP_EDM0_EDM0_SHIFT ) & \ - SPWTDP_EDM0_EDM0_MASK ) ) + ( ( ( _val ) << SPWTDP_EDM0_EDM0_SHIFT ) & SPWTDP_EDM0_EDM0_MASK ) ) #define SPWTDP_EDM0_EDM0( _val ) \ - ( ( ( _val ) << SPWTDP_EDM0_EDM0_SHIFT ) & \ - SPWTDP_EDM0_EDM0_MASK ) + ( ( ( _val ) << SPWTDP_EDM0_EDM0_SHIFT ) & SPWTDP_EDM0_EDM0_MASK ) /** @} */ @@ -915,17 +811,14 @@ extern "C" { */ #define SPWTDP_EDPF0_EDPF0_SHIFT 0 -#define SPWTDP_EDPF0_EDPF0_MASK 0xffffU +#define SPWTDP_EDPF0_EDPF0_MASK 0xffffU #define SPWTDP_EDPF0_EDPF0_GET( _reg ) \ - ( ( ( _reg ) & SPWTDP_EDPF0_EDPF0_MASK ) >> \ - SPWTDP_EDPF0_EDPF0_SHIFT ) -#define SPWTDP_EDPF0_EDPF0_SET( _reg, _val ) \ + ( ( ( _reg ) & SPWTDP_EDPF0_EDPF0_MASK ) >> SPWTDP_EDPF0_EDPF0_SHIFT ) +#define SPWTDP_EDPF0_EDPF0_SET( _reg, _val ) \ ( ( ( _reg ) & ~SPWTDP_EDPF0_EDPF0_MASK ) | \ - ( ( ( _val ) << SPWTDP_EDPF0_EDPF0_SHIFT ) & \ - SPWTDP_EDPF0_EDPF0_MASK ) ) + ( ( ( _val ) << SPWTDP_EDPF0_EDPF0_SHIFT ) & SPWTDP_EDPF0_EDPF0_MASK ) ) #define SPWTDP_EDPF0_EDPF0( _val ) \ - ( ( ( _val ) << SPWTDP_EDPF0_EDPF0_SHIFT ) & \ - SPWTDP_EDPF0_EDPF0_MASK ) + ( ( ( _val ) << SPWTDP_EDPF0_EDPF0_SHIFT ) & SPWTDP_EDPF0_EDPF0_MASK ) /** @} */ @@ -939,17 +832,15 @@ extern "C" { */ #define SPWTDP_ED0ET0_ED0ET0_SHIFT 0 -#define SPWTDP_ED0ET0_ED0ET0_MASK 0xffffffffU +#define SPWTDP_ED0ET0_ED0ET0_MASK 0xffffffffU #define SPWTDP_ED0ET0_ED0ET0_GET( _reg ) \ - ( ( ( _reg ) & SPWTDP_ED0ET0_ED0ET0_MASK ) >> \ - SPWTDP_ED0ET0_ED0ET0_SHIFT ) -#define SPWTDP_ED0ET0_ED0ET0_SET( _reg, _val ) \ - ( ( ( _reg ) & ~SPWTDP_ED0ET0_ED0ET0_MASK ) | \ + ( ( ( _reg ) & SPWTDP_ED0ET0_ED0ET0_MASK ) >> SPWTDP_ED0ET0_ED0ET0_SHIFT ) +#define SPWTDP_ED0ET0_ED0ET0_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWTDP_ED0ET0_ED0ET0_MASK ) | \ ( ( ( _val ) << SPWTDP_ED0ET0_ED0ET0_SHIFT ) & \ SPWTDP_ED0ET0_ED0ET0_MASK ) ) #define SPWTDP_ED0ET0_ED0ET0( _val ) \ - ( ( ( _val ) << SPWTDP_ED0ET0_ED0ET0_SHIFT ) & \ - SPWTDP_ED0ET0_ED0ET0_MASK ) + ( ( ( _val ) << SPWTDP_ED0ET0_ED0ET0_SHIFT ) & SPWTDP_ED0ET0_ED0ET0_MASK ) /** @} */ @@ -963,17 +854,15 @@ extern "C" { */ #define SPWTDP_ED0ET1_ED0ET1_SHIFT 0 -#define SPWTDP_ED0ET1_ED0ET1_MASK 0xffffffffU +#define SPWTDP_ED0ET1_ED0ET1_MASK 0xffffffffU #define SPWTDP_ED0ET1_ED0ET1_GET( _reg ) \ - ( ( ( _reg ) & SPWTDP_ED0ET1_ED0ET1_MASK ) >> \ - SPWTDP_ED0ET1_ED0ET1_SHIFT ) -#define SPWTDP_ED0ET1_ED0ET1_SET( _reg, _val ) \ - ( ( ( _reg ) & ~SPWTDP_ED0ET1_ED0ET1_MASK ) | \ + ( ( ( _reg ) & SPWTDP_ED0ET1_ED0ET1_MASK ) >> SPWTDP_ED0ET1_ED0ET1_SHIFT ) +#define SPWTDP_ED0ET1_ED0ET1_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWTDP_ED0ET1_ED0ET1_MASK ) | \ ( ( ( _val ) << SPWTDP_ED0ET1_ED0ET1_SHIFT ) & \ SPWTDP_ED0ET1_ED0ET1_MASK ) ) #define SPWTDP_ED0ET1_ED0ET1( _val ) \ - ( ( ( _val ) << SPWTDP_ED0ET1_ED0ET1_SHIFT ) & \ - SPWTDP_ED0ET1_ED0ET1_MASK ) + ( ( ( _val ) << SPWTDP_ED0ET1_ED0ET1_SHIFT ) & SPWTDP_ED0ET1_ED0ET1_MASK ) /** @} */ @@ -987,17 +876,15 @@ extern "C" { */ #define SPWTDP_ED0ET2_ED0ET2_SHIFT 0 -#define SPWTDP_ED0ET2_ED0ET2_MASK 0xffffffffU +#define SPWTDP_ED0ET2_ED0ET2_MASK 0xffffffffU #define SPWTDP_ED0ET2_ED0ET2_GET( _reg ) \ - ( ( ( _reg ) & SPWTDP_ED0ET2_ED0ET2_MASK ) >> \ - SPWTDP_ED0ET2_ED0ET2_SHIFT ) -#define SPWTDP_ED0ET2_ED0ET2_SET( _reg, _val ) \ - ( ( ( _reg ) & ~SPWTDP_ED0ET2_ED0ET2_MASK ) | \ + ( ( ( _reg ) & SPWTDP_ED0ET2_ED0ET2_MASK ) >> SPWTDP_ED0ET2_ED0ET2_SHIFT ) +#define SPWTDP_ED0ET2_ED0ET2_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWTDP_ED0ET2_ED0ET2_MASK ) | \ ( ( ( _val ) << SPWTDP_ED0ET2_ED0ET2_SHIFT ) & \ SPWTDP_ED0ET2_ED0ET2_MASK ) ) #define SPWTDP_ED0ET2_ED0ET2( _val ) \ - ( ( ( _val ) << SPWTDP_ED0ET2_ED0ET2_SHIFT ) & \ - SPWTDP_ED0ET2_ED0ET2_MASK ) + ( ( ( _val ) << SPWTDP_ED0ET2_ED0ET2_SHIFT ) & SPWTDP_ED0ET2_ED0ET2_MASK ) /** @} */ @@ -1011,17 +898,15 @@ extern "C" { */ #define SPWTDP_ED0ET3_ED0ET3_SHIFT 0 -#define SPWTDP_ED0ET3_ED0ET3_MASK 0xffffffffU +#define SPWTDP_ED0ET3_ED0ET3_MASK 0xffffffffU #define SPWTDP_ED0ET3_ED0ET3_GET( _reg ) \ - ( ( ( _reg ) & SPWTDP_ED0ET3_ED0ET3_MASK ) >> \ - SPWTDP_ED0ET3_ED0ET3_SHIFT ) -#define SPWTDP_ED0ET3_ED0ET3_SET( _reg, _val ) \ - ( ( ( _reg ) & ~SPWTDP_ED0ET3_ED0ET3_MASK ) | \ + ( ( ( _reg ) & SPWTDP_ED0ET3_ED0ET3_MASK ) >> SPWTDP_ED0ET3_ED0ET3_SHIFT ) +#define SPWTDP_ED0ET3_ED0ET3_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWTDP_ED0ET3_ED0ET3_MASK ) | \ ( ( ( _val ) << SPWTDP_ED0ET3_ED0ET3_SHIFT ) & \ SPWTDP_ED0ET3_ED0ET3_MASK ) ) #define SPWTDP_ED0ET3_ED0ET3( _val ) \ - ( ( ( _val ) << SPWTDP_ED0ET3_ED0ET3_SHIFT ) & \ - SPWTDP_ED0ET3_ED0ET3_MASK ) + ( ( ( _val ) << SPWTDP_ED0ET3_ED0ET3_SHIFT ) & SPWTDP_ED0ET3_ED0ET3_MASK ) /** @} */ @@ -1035,17 +920,15 @@ extern "C" { */ #define SPWTDP_ED0ET4_ED0ET4_SHIFT 24 -#define SPWTDP_ED0ET4_ED0ET4_MASK 0xff000000U +#define SPWTDP_ED0ET4_ED0ET4_MASK 0xff000000U #define SPWTDP_ED0ET4_ED0ET4_GET( _reg ) \ - ( ( ( _reg ) & SPWTDP_ED0ET4_ED0ET4_MASK ) >> \ - SPWTDP_ED0ET4_ED0ET4_SHIFT ) -#define SPWTDP_ED0ET4_ED0ET4_SET( _reg, _val ) \ - ( ( ( _reg ) & ~SPWTDP_ED0ET4_ED0ET4_MASK ) | \ + ( ( ( _reg ) & SPWTDP_ED0ET4_ED0ET4_MASK ) >> SPWTDP_ED0ET4_ED0ET4_SHIFT ) +#define SPWTDP_ED0ET4_ED0ET4_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWTDP_ED0ET4_ED0ET4_MASK ) | \ ( ( ( _val ) << SPWTDP_ED0ET4_ED0ET4_SHIFT ) & \ SPWTDP_ED0ET4_ED0ET4_MASK ) ) #define SPWTDP_ED0ET4_ED0ET4( _val ) \ - ( ( ( _val ) << SPWTDP_ED0ET4_ED0ET4_SHIFT ) & \ - SPWTDP_ED0ET4_ED0ET4_MASK ) + ( ( ( _val ) << SPWTDP_ED0ET4_ED0ET4_SHIFT ) & SPWTDP_ED0ET4_ED0ET4_MASK ) /** @} */ diff --git a/bsps/include/grlib/spwtdp.h b/bsps/include/grlib/spwtdp.h index eb2e662e72..010f9e1278 100644 --- a/bsps/include/grlib/spwtdp.h +++ b/bsps/include/grlib/spwtdp.h @@ -36,267 +36,290 @@ extern "C" { #endif -#define SPWTDP_ERR_OK 0 -#define SPWTDP_ERR_EINVAL -1 -#define SPWTDP_ERR_ERROR -2 -#define SPWTDP_ERR_NOINIT -3 +#define SPWTDP_ERR_OK 0 +#define SPWTDP_ERR_EINVAL -1 +#define SPWTDP_ERR_ERROR -2 +#define SPWTDP_ERR_NOINIT -3 /* Maximum number of SPWTDP devices supported by driver */ #define SPWTDP_MAX 2 /* SPWTDP Register layout */ struct spwtdp_regs { - volatile uint32_t conf[4]; /* 0x000-0x00C */ - volatile uint32_t stat[4]; /* 0x010-0x01C */ - volatile uint32_t cmd_ctrl; /* 0x020 */ - volatile uint32_t cmd_et[5]; /* 0x024-0x034 */ - volatile uint32_t resv1[2]; /* 0x038-0x03C */ - volatile uint32_t dat_ctrl; /* 0x040 */ - volatile uint32_t dat_et[5]; /* 0x044-0x054 */ - volatile uint32_t resv2[2]; /* 0x058-0x05C */ - volatile uint32_t ts_rx_ctrl; /* 0x060 */ - volatile uint32_t ts_rx_et[5]; /* 0x064-0x074 */ - volatile uint32_t resv3[2]; /* 0x078-0x07C */ - volatile uint32_t ts_tx_ctrl; /* 0x080 */ - volatile uint32_t ts_tx_et[5]; /* 0x084-0x094 */ - volatile uint32_t resv4[2]; /* 0x098 */ - volatile uint32_t lat_ctrl; /* 0x0A0 */ - volatile uint32_t lat_et[5]; /* 0x0A4-0x0B4 */ - volatile uint32_t resv5[2]; /* 0x0B8-0x0BC */ - volatile uint32_t ien; /* 0x0C0 */ - volatile uint32_t ists; /* 0x0C4 */ - volatile uint32_t dlycnt; /* 0x0C8 */ - volatile uint32_t dissync; /* 0x0CC */ - volatile uint32_t resv6[12]; /* 0x0D0-0x0FC */ - volatile uint32_t edmask[4]; /* 0x100-0x10C */ - struct { - volatile uint32_t ctrl; /* 0x110, 0x130, 0x150, 0x170 */ - volatile uint32_t et[5]; /* 0x114-0x124, 0x134-0x144, 0x154-0x164, 0x174-0x184, */ - volatile uint32_t resv0[2]; /* 0x128-0x12C, 0x148-0x14C, 0x168-0x16C, 0x188-0x18C, */ - } edat[4]; /* 0x110-0x18C */ - volatile uint32_t resv7[4]; /* 0x190-0x19C */ - volatile uint32_t pulse[8]; /* 0x1A0-0x1BC */ - volatile uint32_t resv8[16]; /* 0x1C0-0x1FC */ + volatile uint32_t conf[ 4 ]; /* 0x000-0x00C */ + volatile uint32_t stat[ 4 ]; /* 0x010-0x01C */ + volatile uint32_t cmd_ctrl; /* 0x020 */ + volatile uint32_t cmd_et[ 5 ]; /* 0x024-0x034 */ + volatile uint32_t resv1[ 2 ]; /* 0x038-0x03C */ + volatile uint32_t dat_ctrl; /* 0x040 */ + volatile uint32_t dat_et[ 5 ]; /* 0x044-0x054 */ + volatile uint32_t resv2[ 2 ]; /* 0x058-0x05C */ + volatile uint32_t ts_rx_ctrl; /* 0x060 */ + volatile uint32_t ts_rx_et[ 5 ]; /* 0x064-0x074 */ + volatile uint32_t resv3[ 2 ]; /* 0x078-0x07C */ + volatile uint32_t ts_tx_ctrl; /* 0x080 */ + volatile uint32_t ts_tx_et[ 5 ]; /* 0x084-0x094 */ + volatile uint32_t resv4[ 2 ]; /* 0x098 */ + volatile uint32_t lat_ctrl; /* 0x0A0 */ + volatile uint32_t lat_et[ 5 ]; /* 0x0A4-0x0B4 */ + volatile uint32_t resv5[ 2 ]; /* 0x0B8-0x0BC */ + volatile uint32_t ien; /* 0x0C0 */ + volatile uint32_t ists; /* 0x0C4 */ + volatile uint32_t dlycnt; /* 0x0C8 */ + volatile uint32_t dissync; /* 0x0CC */ + volatile uint32_t resv6[ 12 ]; /* 0x0D0-0x0FC */ + volatile uint32_t edmask[ 4 ]; /* 0x100-0x10C */ + struct { + volatile uint32_t ctrl; /* 0x110, 0x130, 0x150, 0x170 */ + volatile uint32_t + et[ 5 ]; /* 0x114-0x124, 0x134-0x144, 0x154-0x164, 0x174-0x184, */ + volatile uint32_t + resv0[ 2 ]; /* 0x128-0x12C, 0x148-0x14C, 0x168-0x16C, 0x188-0x18C, */ + } edat[ 4 ]; /* 0x110-0x18C */ + volatile uint32_t resv7[ 4 ]; /* 0x190-0x19C */ + volatile uint32_t pulse[ 8 ]; /* 0x1A0-0x1BC */ + volatile uint32_t resv8[ 16 ]; /* 0x1C0-0x1FC */ }; /* * Configuration register definitions */ -#define CONF0_JE (0x1 << CONF0_JE_BIT) -#define CONF0_ST (0x1 << CONF0_ST_BIT) -#define CONF0_EP (0x1 << CONF0_EP_BIT) -#define CONF0_ET (0x1 << CONF0_ET_BIT) -#define CONF0_SP (0x1 << CONF0_SP_BIT) -#define CONF0_SE (0x1 << CONF0_SE_BIT) -#define CONF0_LE (0x1 << CONF0_LE_BIT) -#define CONF0_AE (0x1 << CONF0_AE_BIT) -#define CONF0_MAP (0x1f << CONF0_MAP_BIT) -#define CONF0_TD (0x1 << CONF0_TD_BIT) -#define CONF0_MU (0x1 << CONF0_MU_BIT) -#define CONF0_SEL (0x3 << CONF0_SEL_BIT) -#define CONF0_ME (0x1 << CONF0_ME_BIT) -#define CONF0_RE (0x1 << CONF0_RE_BIT) -#define CONF0_TE (0x1 << CONF0_TE_BIT) -#define CONF0_RS (0x1 << CONF0_RS_BIT) +#define CONF0_JE ( 0x1 << CONF0_JE_BIT ) +#define CONF0_ST ( 0x1 << CONF0_ST_BIT ) +#define CONF0_EP ( 0x1 << CONF0_EP_BIT ) +#define CONF0_ET ( 0x1 << CONF0_ET_BIT ) +#define CONF0_SP ( 0x1 << CONF0_SP_BIT ) +#define CONF0_SE ( 0x1 << CONF0_SE_BIT ) +#define CONF0_LE ( 0x1 << CONF0_LE_BIT ) +#define CONF0_AE ( 0x1 << CONF0_AE_BIT ) +#define CONF0_MAP ( 0x1f << CONF0_MAP_BIT ) +#define CONF0_TD ( 0x1 << CONF0_TD_BIT ) +#define CONF0_MU ( 0x1 << CONF0_MU_BIT ) +#define CONF0_SEL ( 0x3 << CONF0_SEL_BIT ) +#define CONF0_ME ( 0x1 << CONF0_ME_BIT ) +#define CONF0_RE ( 0x1 << CONF0_RE_BIT ) +#define CONF0_TE ( 0x1 << CONF0_TE_BIT ) +#define CONF0_RS ( 0x1 << CONF0_RS_BIT ) -#define CONF0_JE_BIT 24 -#define CONF0_ST_BIT 21 -#define CONF0_EP_BIT 20 -#define CONF0_ET_BIT 19 -#define CONF0_SP_BIT 18 -#define CONF0_SE_BIT 17 -#define CONF0_LE_BIT 16 -#define CONF0_AE_BIT 15 -#define CONF0_MAP_BIT 8 -#define CONF0_TD_BIT 7 -#define CONF0_MU_BIT 6 -#define CONF0_SEL_BIT 4 -#define CONF0_ME_BIT 3 -#define CONF0_RE_BIT 2 -#define CONF0_TE_BIT 1 -#define CONF0_RS_BIT 0 +#define CONF0_JE_BIT 24 +#define CONF0_ST_BIT 21 +#define CONF0_EP_BIT 20 +#define CONF0_ET_BIT 19 +#define CONF0_SP_BIT 18 +#define CONF0_SE_BIT 17 +#define CONF0_LE_BIT 16 +#define CONF0_AE_BIT 15 +#define CONF0_MAP_BIT 8 +#define CONF0_TD_BIT 7 +#define CONF0_MU_BIT 6 +#define CONF0_SEL_BIT 4 +#define CONF0_ME_BIT 3 +#define CONF0_RE_BIT 2 +#define CONF0_TE_BIT 1 +#define CONF0_RS_BIT 0 -#define CONF1_FSINC (0x3fffffff << CONF1_FSINC_BIT) +#define CONF1_FSINC ( 0x3fffffff << CONF1_FSINC_BIT ) -#define CONF1_FSINC_BIT 0 +#define CONF1_FSINC_BIT 0 -#define CONF2_CV (0xffffff << CONF2_CV_BIT) -#define CONF2_ETINC (0xff << CONF2_ETINC_BIT) +#define CONF2_CV ( 0xffffff << CONF2_CV_BIT ) +#define CONF2_ETINC ( 0xff << CONF2_ETINC_BIT ) -#define CONF2_CV_BIT 8 -#define CONF2_ETINC_BIT 0 +#define CONF2_CV_BIT 8 +#define CONF2_ETINC_BIT 0 -#define CONF3_OUTPORT (0xf << CONF3_OUTPORT_BIT) -#define CONF3_INPORT (0xf << CONF3_INPORT_BIT) -#define CONF3_STM (0x3f << CONF3_STM_BIT) -#define CONF3_DI64R (0x1 << CONF3_DI64R_BIT) -#define CONF3_DI64T (0x1 << CONF3_DI64T_BIT) -#define CONF3_DI64 (0x1 << CONF3_DI64_BIT) -#define CONF3_DI (0x1 << CONF3_DI_BIT) -#define CONF3_INRX (0x1f << CONF3_INRX_BIT) -#define CONF3_INTX (0x1f << CONF3_INTX_BIT) +#define CONF3_OUTPORT ( 0xf << CONF3_OUTPORT_BIT ) +#define CONF3_INPORT ( 0xf << CONF3_INPORT_BIT ) +#define CONF3_STM ( 0x3f << CONF3_STM_BIT ) +#define CONF3_DI64R ( 0x1 << CONF3_DI64R_BIT ) +#define CONF3_DI64T ( 0x1 << CONF3_DI64T_BIT ) +#define CONF3_DI64 ( 0x1 << CONF3_DI64_BIT ) +#define CONF3_DI ( 0x1 << CONF3_DI_BIT ) +#define CONF3_INRX ( 0x1f << CONF3_INRX_BIT ) +#define CONF3_INTX ( 0x1f << CONF3_INTX_BIT ) #define CONF3_OUTPORT_BIT 28 -#define CONF3_INPORT_BIT 24 -#define CONF3_STM_BIT 16 -#define CONF3_DI64R_BIT 13 -#define CONF3_DI64T_BIT 12 -#define CONF3_DI64_BIT 11 -#define CONF3_DI_BIT 10 -#define CONF3_INRX_BIT 5 -#define CONF3_INTX_BIT 0 +#define CONF3_INPORT_BIT 24 +#define CONF3_STM_BIT 16 +#define CONF3_DI64R_BIT 13 +#define CONF3_DI64T_BIT 12 +#define CONF3_DI64_BIT 11 +#define CONF3_DI_BIT 10 +#define CONF3_INRX_BIT 5 +#define CONF3_INTX_BIT 0 /* * Control register definitions */ -#define CTRL_NC (0x1 << CTRL_NC_BIT) -#define CTRL_IS (0x1 << CTRL_IS_BIT) -#define CTRL_SPWTC (0xff << CTRL_SPWTC_BIT) -#define CTRL_CPF (0xffff << CTRL_CPF_BIT) +#define CTRL_NC ( 0x1 << CTRL_NC_BIT ) +#define CTRL_IS ( 0x1 << CTRL_IS_BIT ) +#define CTRL_SPWTC ( 0xff << CTRL_SPWTC_BIT ) +#define CTRL_CPF ( 0xffff << CTRL_CPF_BIT ) -#define CTRL_NC_BIT 31 -#define CTRL_IS_BIT 30 -#define CTRL_SPWTC_BIT 16 -#define CTRL_CPF_BIT 0 +#define CTRL_NC_BIT 31 +#define CTRL_IS_BIT 30 +#define CTRL_SPWTC_BIT 16 +#define CTRL_CPF_BIT 0 /* * Interrupt register definition */ -#define SPWTDP_IRQ_S (0x1 << SPWTDP_IRQ_S_BIT) -#define SPWTDP_IRQ_TR (0x1 << SPWTDP_IRQ_TR_BIT) -#define SPWTDP_IRQ_TM (0x1 << SPWTDP_IRQ_TM_BIT) -#define SPWTDP_IRQ_TT (0x1 << SPWTDP_IRQ_TT_BIT) -#define SPWTDP_IRQ_DIR (0x1 << SPWTDP_IRQ_DIR_BIT) -#define SPWTDP_IRQ_DIT (0x1 << SPWTDP_IRQ_DIT_BIT) -#define SPWTDP_IRQ_EDI0 (0x1 << SPWTDP_IRQ_EDI0_BIT) -#define SPWTDP_IRQ_EDI1 (0x1 << SPWTDP_IRQ_EDI1_BIT) -#define SPWTDP_IRQ_EDI2 (0x1 << SPWTDP_IRQ_EDI2_BIT) -#define SPWTDP_IRQ_EDI3 (0x1 << SPWTDP_IRQ_EDI3_BIT) -#define SPWTDP_IRQ_SET (0x1 << SPWTDP_IRQ_SET_BIT) -#define SPWTDP_IRQ_P0 (0x1 << SPWTDP_IRQ_P0_BIT) -#define SPWTDP_IRQ_P1 (0x1 << SPWTDP_IRQ_P1_BIT) -#define SPWTDP_IRQ_P2 (0x1 << SPWTDP_IRQ_P2_BIT) -#define SPWTDP_IRQ_P3 (0x1 << SPWTDP_IRQ_P3_BIT) -#define SPWTDP_IRQ_P4 (0x1 << SPWTDP_IRQ_P4_BIT) -#define SPWTDP_IRQ_P5 (0x1 << SPWTDP_IRQ_P5_BIT) -#define SPWTDP_IRQ_P6 (0x1 << SPWTDP_IRQ_P6_BIT) -#define SPWTDP_IRQ_P7 (0x1 << SPWTDP_IRQ_P7_BIT) -#define SPWTDP_IRQ_NCTC (0x1 << SPWTDP_IRQ_NCTC_BIT) -#define SPWTDP_IRQ_WCLEAR \ - (SPWTDP_IRQ_S | SPWTDP_IRQ_TR | SPWTDP_IRQ_TM | \ - SPWTDP_IRQ_TT | SPWTDP_IRQ_DIR | SPWTDP_IRQ_DIT | SPWTDP_IRQ_EDI0 | \ - SPWTDP_IRQ_EDI1 | SPWTDP_IRQ_EDI2 | SPWTDP_IRQ_EDI3 | SPWTDP_IRQ_SET |\ - SPWTDP_IRQ_P0 | SPWTDP_IRQ_P1 | SPWTDP_IRQ_P2 | SPWTDP_IRQ_P3 | \ - SPWTDP_IRQ_P4 | SPWTDP_IRQ_P5 | SPWTDP_IRQ_P6 | SPWTDP_IRQ_P7 | \ - SPWTDP_IRQ_NCTC) -#define SPWTDP_IRQ_ALL (SPWTDP_IRQ_WCLEAR) +#define SPWTDP_IRQ_S ( 0x1 << SPWTDP_IRQ_S_BIT ) +#define SPWTDP_IRQ_TR ( 0x1 << SPWTDP_IRQ_TR_BIT ) +#define SPWTDP_IRQ_TM ( 0x1 << SPWTDP_IRQ_TM_BIT ) +#define SPWTDP_IRQ_TT ( 0x1 << SPWTDP_IRQ_TT_BIT ) +#define SPWTDP_IRQ_DIR ( 0x1 << SPWTDP_IRQ_DIR_BIT ) +#define SPWTDP_IRQ_DIT ( 0x1 << SPWTDP_IRQ_DIT_BIT ) +#define SPWTDP_IRQ_EDI0 ( 0x1 << SPWTDP_IRQ_EDI0_BIT ) +#define SPWTDP_IRQ_EDI1 ( 0x1 << SPWTDP_IRQ_EDI1_BIT ) +#define SPWTDP_IRQ_EDI2 ( 0x1 << SPWTDP_IRQ_EDI2_BIT ) +#define SPWTDP_IRQ_EDI3 ( 0x1 << SPWTDP_IRQ_EDI3_BIT ) +#define SPWTDP_IRQ_SET ( 0x1 << SPWTDP_IRQ_SET_BIT ) +#define SPWTDP_IRQ_P0 ( 0x1 << SPWTDP_IRQ_P0_BIT ) +#define SPWTDP_IRQ_P1 ( 0x1 << SPWTDP_IRQ_P1_BIT ) +#define SPWTDP_IRQ_P2 ( 0x1 << SPWTDP_IRQ_P2_BIT ) +#define SPWTDP_IRQ_P3 ( 0x1 << SPWTDP_IRQ_P3_BIT ) +#define SPWTDP_IRQ_P4 ( 0x1 << SPWTDP_IRQ_P4_BIT ) +#define SPWTDP_IRQ_P5 ( 0x1 << SPWTDP_IRQ_P5_BIT ) +#define SPWTDP_IRQ_P6 ( 0x1 << SPWTDP_IRQ_P6_BIT ) +#define SPWTDP_IRQ_P7 ( 0x1 << SPWTDP_IRQ_P7_BIT ) +#define SPWTDP_IRQ_NCTC ( 0x1 << SPWTDP_IRQ_NCTC_BIT ) +#define SPWTDP_IRQ_WCLEAR \ + ( SPWTDP_IRQ_S | SPWTDP_IRQ_TR | SPWTDP_IRQ_TM | SPWTDP_IRQ_TT | \ + SPWTDP_IRQ_DIR | SPWTDP_IRQ_DIT | SPWTDP_IRQ_EDI0 | SPWTDP_IRQ_EDI1 | \ + SPWTDP_IRQ_EDI2 | SPWTDP_IRQ_EDI3 | SPWTDP_IRQ_SET | SPWTDP_IRQ_P0 | \ + SPWTDP_IRQ_P1 | SPWTDP_IRQ_P2 | SPWTDP_IRQ_P3 | SPWTDP_IRQ_P4 | \ + SPWTDP_IRQ_P5 | SPWTDP_IRQ_P6 | SPWTDP_IRQ_P7 | SPWTDP_IRQ_NCTC ) +#define SPWTDP_IRQ_ALL ( SPWTDP_IRQ_WCLEAR ) -#define SPWTDP_IRQ_S_BIT 0 -#define SPWTDP_IRQ_TR_BIT 1 -#define SPWTDP_IRQ_TM_BIT 2 -#define SPWTDP_IRQ_TT_BIT 3 -#define SPWTDP_IRQ_DIR_BIT 4 -#define SPWTDP_IRQ_DIT_BIT 5 +#define SPWTDP_IRQ_S_BIT 0 +#define SPWTDP_IRQ_TR_BIT 1 +#define SPWTDP_IRQ_TM_BIT 2 +#define SPWTDP_IRQ_TT_BIT 3 +#define SPWTDP_IRQ_DIR_BIT 4 +#define SPWTDP_IRQ_DIT_BIT 5 #define SPWTDP_IRQ_EDI0_BIT 6 #define SPWTDP_IRQ_EDI1_BIT 7 #define SPWTDP_IRQ_EDI2_BIT 8 #define SPWTDP_IRQ_EDI3_BIT 9 -#define SPWTDP_IRQ_SET_BIT 10 -#define SPWTDP_IRQ_P0_BIT 11 -#define SPWTDP_IRQ_P1_BIT 12 -#define SPWTDP_IRQ_P2_BIT 13 -#define SPWTDP_IRQ_P3_BIT 14 -#define SPWTDP_IRQ_P4_BIT 15 -#define SPWTDP_IRQ_P5_BIT 16 -#define SPWTDP_IRQ_P6_BIT 17 -#define SPWTDP_IRQ_P7_BIT 18 +#define SPWTDP_IRQ_SET_BIT 10 +#define SPWTDP_IRQ_P0_BIT 11 +#define SPWTDP_IRQ_P1_BIT 12 +#define SPWTDP_IRQ_P2_BIT 13 +#define SPWTDP_IRQ_P3_BIT 14 +#define SPWTDP_IRQ_P4_BIT 15 +#define SPWTDP_IRQ_P5_BIT 16 +#define SPWTDP_IRQ_P6_BIT 17 +#define SPWTDP_IRQ_P7_BIT 18 #define SPWTDP_IRQ_NCTC_BIT 19 /* Register the SPWTDP Driver to the Driver Manager */ -void spwtdp_register_drv(void); +void spwtdp_register_drv( void ); /* Open a SPWTDP device by registration order index. A SPWTDP device can only by * opened once. The handle returned must be used as the input parameter 'spwtdp' * in the rest of the calls in the function interface. */ -extern void *spwtdp_open(int dev_no); +extern void *spwtdp_open( int dev_no ); /* Close a previously opened SPWTDP device */ -extern int spwtdp_close(void *spwtdp); +extern int spwtdp_close( void *spwtdp ); /* Reset SPWTDP Core */ -extern int spwtdp_reset(void *spwtdp); +extern int spwtdp_reset( void *spwtdp ); /* Setup the frequency configuration registers */ -extern int spwtdp_freq_setup(void *spwtdp, uint32_t fsinc, uint32_t cv, - uint8_t etinc); +extern int spwtdp_freq_setup( + void *spwtdp, + uint32_t fsinc, + uint32_t cv, + uint8_t etinc +); /* Unmask Interrupts at Interrupt controller */ -extern int spwtdp_interrupt_unmask(void *spwtdp, uint32_t irqmask); +extern int spwtdp_interrupt_unmask( void *spwtdp, uint32_t irqmask ); /* Mask Interrupts at Interrupt controller */ -extern int spwtdp_interrupt_mask(void *spwtdp, uint32_t irqmask); +extern int spwtdp_interrupt_mask( void *spwtdp, uint32_t irqmask ); /* Function ISR callback prototype * * ists - Interrupt STatus register of the SPWTDP core read by ISR * data - Custom data provided by user */ -typedef void (*spwtdp_isr_t)(unsigned int ists, void *data); +typedef void ( *spwtdp_isr_t )( unsigned int ists, void *data ); /* Register an Interrupt handler and custom data, the function call is * removed by calling unregister function. */ -extern int spwtdp_isr_register(void *spwtdp, spwtdp_isr_t isr, void *data); +extern int spwtdp_isr_register( void *spwtdp, spwtdp_isr_t isr, void *data ); /* Unregister an Interrupt handler */ -extern int spwtdp_isr_unregister(void *spwtdp); +extern int spwtdp_isr_unregister( void *spwtdp ); /* Get and clear interrupt status */ -extern int spwtdp_interrupt_status(void *spwtdp, uint32_t *sts, - uint32_t clrmask); +extern int spwtdp_interrupt_status( + void *spwtdp, + uint32_t *sts, + uint32_t clrmask +); /* Setup Initiator and target */ -#define SPWTDP_TDP_ENABLE CONF0_TD -#define SPWTDP_TDP_DISABLE 0 -#define SPWTDP_LATENCY_ENABLE CONF0_LE -#define SPWTDP_LATENCY_DISABLE 0 -#define SPWTDP_EXTET_INC_POLARITY_RISING CONF0_EP +#define SPWTDP_TDP_ENABLE CONF0_TD +#define SPWTDP_TDP_DISABLE 0 +#define SPWTDP_LATENCY_ENABLE CONF0_LE +#define SPWTDP_LATENCY_DISABLE 0 +#define SPWTDP_EXTET_INC_POLARITY_RISING CONF0_EP #define SPWTDP_EXTET_INC_POLARITY_FALLING 0 -#define SPWTDP_EXTET_INC_ENABLE CONF0_ET -#define SPWTDP_EXTET_INC_DISABLE 0 -#define SPWTDP_EXTET_POLARITY_RISING CONF0_SP -#define SPWTDP_EXTET_POLARITY_FALLING 0 -#define SPWTDP_EXTET_ENABLE CONF0_SE -#define SPWTDP_EXTET_DISABLE 0 -#define SPWTDP_TARGET_SPWSYNC_ENABLE CONF0_ST -#define SPWTDP_TARGET_SPWSYNC_DISABLE 0 -#define SPWTDP_TARGET_JITTERC_ENABLE CONF0_JE -#define SPWTDP_TARGET_JITTERC_DISABLE 0 -#define SPWTDP_TARGET_MITIGATION_ENABLE CONF0_ME -#define SPWTDP_TARGET_MITIGATION_DISABLE 0 -extern int spwtdp_initiator_conf(void *spwtdp, uint8_t mapping, - uint32_t options); -extern int spwtdp_target_conf(void *spwtdp, uint8_t mapping, uint32_t options); +#define SPWTDP_EXTET_INC_ENABLE CONF0_ET +#define SPWTDP_EXTET_INC_DISABLE 0 +#define SPWTDP_EXTET_POLARITY_RISING CONF0_SP +#define SPWTDP_EXTET_POLARITY_FALLING 0 +#define SPWTDP_EXTET_ENABLE CONF0_SE +#define SPWTDP_EXTET_DISABLE 0 +#define SPWTDP_TARGET_SPWSYNC_ENABLE CONF0_ST +#define SPWTDP_TARGET_SPWSYNC_DISABLE 0 +#define SPWTDP_TARGET_JITTERC_ENABLE CONF0_JE +#define SPWTDP_TARGET_JITTERC_DISABLE 0 +#define SPWTDP_TARGET_MITIGATION_ENABLE CONF0_ME +#define SPWTDP_TARGET_MITIGATION_DISABLE 0 +extern int spwtdp_initiator_conf( + void *spwtdp, + uint8_t mapping, + uint32_t options +); +extern int spwtdp_target_conf( + void *spwtdp, + uint8_t mapping, + uint32_t options +); /* Setup Initiator and target dist interrupts */ -extern int spwtdp_initiator_int_conf(void *spwtdp, uint8_t stm, uint8_t inrx, - uint8_t intx); +extern int spwtdp_initiator_int_conf( + void *spwtdp, + uint8_t stm, + uint8_t inrx, + uint8_t intx +); #define SPWTDP_TARGET_DISTINT_INTACK CONF3_DI -#define SPWTDP_TARGET_DISTINT_INT 0 -extern int spwtdp_target_int_conf(void *spwtdp, uint8_t inrx, uint8_t intx, - uint32_t options); +#define SPWTDP_TARGET_DISTINT_INT 0 +extern int spwtdp_target_int_conf( + void *spwtdp, + uint8_t inrx, + uint8_t intx, + uint32_t options +); /* Enable Initiator and target */ -extern int spwtdp_initiator_enable(void *spwtdp); -extern int spwtdp_target_enable(void *spwtdp); +extern int spwtdp_initiator_enable( void *spwtdp ); +extern int spwtdp_target_enable( void *spwtdp ); /* Disable Initiator and target */ -extern int spwtdp_initiator_disable(void *spwtdp); -extern int spwtdp_target_disable(void *spwtdp); +extern int spwtdp_initiator_disable( void *spwtdp ); +extern int spwtdp_target_disable( void *spwtdp ); /* Get and clear status */ -extern int spwtdp_status(void *spwtdp, uint32_t *sts, uint32_t clrmask); +extern int spwtdp_status( void *spwtdp, uint32_t *sts, uint32_t clrmask ); /* Define time struct */ /* Length of the max data sample (136 bits), aligned to the next 32-bit word @@ -304,33 +327,41 @@ extern int spwtdp_status(void *spwtdp, uint32_t *sts, uint32_t clrmask); */ #define SPWTDP_TIME_DATA_LENGTH 20 struct spwtdp_time_t { - uint8_t data[SPWTDP_TIME_DATA_LENGTH]; - uint32_t preamble; + uint8_t data[ SPWTDP_TIME_DATA_LENGTH ]; + uint32_t preamble; }; typedef struct spwtdp_time_t spwtdp_time_t; /* Get datation elapsed time */ -extern int spwtdp_dat_et_get(void *spwtdp, spwtdp_time_t * val); -extern int spwtdp_tsrx_et_get(void *spwtdp, spwtdp_time_t * val); -extern int spwtdp_tstx_et_get(void *spwtdp, spwtdp_time_t * val); -extern int spwtdp_lat_et_get(void *spwtdp, spwtdp_time_t * val); -extern int spwtdp_cmd_et_get(void *spwtdp, spwtdp_time_t * val); +extern int spwtdp_dat_et_get( void *spwtdp, spwtdp_time_t *val ); +extern int spwtdp_tsrx_et_get( void *spwtdp, spwtdp_time_t *val ); +extern int spwtdp_tstx_et_get( void *spwtdp, spwtdp_time_t *val ); +extern int spwtdp_lat_et_get( void *spwtdp, spwtdp_time_t *val ); +extern int spwtdp_cmd_et_get( void *spwtdp, spwtdp_time_t *val ); /* Configure TSTX */ -extern int spwtdp_initiator_tstx_conf(void *spwtdp, uint8_t tstc); +extern int spwtdp_initiator_tstx_conf( void *spwtdp, uint8_t tstc ); /* Manage control register */ -extern int spwtdp_initiator_cmd_et_set(void *spwtdp, spwtdp_time_t val); -extern int spwtdp_initiator_cmd_spwtc_set(void *spwtdp, uint8_t spwtc); -#define SPWTDP_TARGET_CTRL_NEWCOMMAND_ENABLE CTRL_NC +extern int spwtdp_initiator_cmd_et_set( void *spwtdp, spwtdp_time_t val ); +extern int spwtdp_initiator_cmd_spwtc_set( void *spwtdp, uint8_t spwtc ); +#define SPWTDP_TARGET_CTRL_NEWCOMMAND_ENABLE CTRL_NC #define SPWTDP_TARGET_CTRL_NEWCOMMAND_DISABLE 0 -#define SPWTDP_TARGET_CTRL_INIT CTRL_IS -#define SPWTDP_TARGET_CTRL_SYNC 0 -extern int spwtdp_target_cmd_conf(void *spwtdp, uint8_t spwtc, uint16_t cpf, - uint32_t options); +#define SPWTDP_TARGET_CTRL_INIT CTRL_IS +#define SPWTDP_TARGET_CTRL_SYNC 0 +extern int spwtdp_target_cmd_conf( + void *spwtdp, + uint8_t spwtc, + uint16_t cpf, + uint32_t options +); /* Get precision */ -extern int spwtdp_precision_get(void *spwtdp, uint8_t *fine, uint8_t *coarse); +extern int spwtdp_precision_get( + void *spwtdp, + uint8_t *fine, + uint8_t *coarse +); #ifdef __cplusplus } diff --git a/bsps/include/grlib/tlib.h b/bsps/include/grlib/tlib.h index b2e8984489..8f97a22b91 100644 --- a/bsps/include/grlib/tlib.h +++ b/bsps/include/grlib/tlib.h @@ -44,38 +44,42 @@ extern "C" { struct tlib_dev; -typedef void (*tlib_isr_t)(void *data); +typedef void ( *tlib_isr_t )( void *data ); -enum { - TLIB_FLAGS_BROADCAST = 0x01 -}; +enum { TLIB_FLAGS_BROADCAST = 0x01 }; struct tlib_drv { - /*** Functions ***/ - void (*reset)(struct tlib_dev *hand); - void (*get_freq)( - struct tlib_dev *hand, - unsigned int *basefreq, - unsigned int *tickrate); - int (*set_freq)(struct tlib_dev *hand, unsigned int tickrate); - void (*irq_reg)(struct tlib_dev *hand, tlib_isr_t func, void *data, int flags); - void (*irq_unreg)(struct tlib_dev *hand, tlib_isr_t func,void *data); - void (*start)(struct tlib_dev *hand, int once); - void (*stop)(struct tlib_dev *hand); - void (*restart)(struct tlib_dev *hand); - void (*get_counter)(struct tlib_dev *hand, unsigned int *counter); - int (*custom)(struct tlib_dev *hand, int cmd, void *arg); - int (*int_pend)(struct tlib_dev *hand, int ack); - void (*get_widthmask)(struct tlib_dev *hand, unsigned int *widthmask); + /*** Functions ***/ + void ( *reset )( struct tlib_dev *hand ); + void ( *get_freq )( + struct tlib_dev *hand, + unsigned int *basefreq, + unsigned int *tickrate + ); + int ( *set_freq )( struct tlib_dev *hand, unsigned int tickrate ); + void ( *irq_reg )( + struct tlib_dev *hand, + tlib_isr_t func, + void *data, + int flags + ); + void ( *irq_unreg )( struct tlib_dev *hand, tlib_isr_t func, void *data ); + void ( *start )( struct tlib_dev *hand, int once ); + void ( *stop )( struct tlib_dev *hand ); + void ( *restart )( struct tlib_dev *hand ); + void ( *get_counter )( struct tlib_dev *hand, unsigned int *counter ); + int ( *custom )( struct tlib_dev *hand, int cmd, void *arg ); + int ( *int_pend )( struct tlib_dev *hand, int ack ); + void ( *get_widthmask )( struct tlib_dev *hand, unsigned int *widthmask ); }; struct tlib_dev { - struct tlib_dev *next; - char status; /* 0=closed, 1=open, 2=timer started */ - char index; /* Timer Index */ - tlib_isr_t isr_func; - void *isr_data; - struct tlib_drv *drv; + struct tlib_dev *next; + char status; /* 0=closed, 1=open, 2=timer started */ + char index; /* Timer Index */ + tlib_isr_t isr_func; + void *isr_data; + struct tlib_drv *drv; }; #ifdef RTEMS_DRVMGR_STARTUP @@ -83,7 +87,7 @@ struct tlib_dev { * driver is used. A specific Timer is registered as the System Clock * timer. */ -extern void Clock_timer_register(int timer_number); +extern void Clock_timer_register( int timer_number ); #endif /* Register Timer. Called by Timer Drivers in order to register @@ -91,69 +95,75 @@ extern void Clock_timer_register(int timer_number); * the Timer Number used in tlib_open() to identify a specific * Timer. */ -extern int tlib_dev_reg(struct tlib_dev *newdev); +extern int tlib_dev_reg( struct tlib_dev *newdev ); /* Allocate a Timer. * * A Timer handle is returned identifying the timer in later calls. */ -extern void *tlib_open(int timer_no); +extern void *tlib_open( int timer_no ); /* Close Timer */ -extern void tlib_close(void *hand); +extern void tlib_close( void *hand ); /* Returns Number of Timers currently registered to Timer Library */ -extern int tlib_ntimer(void); +extern int tlib_ntimer( void ); -static inline void tlib_reset(void *hand) +static inline void tlib_reset( void *hand ) { - struct tlib_dev *dev = hand; + struct tlib_dev *dev = hand; - dev->drv->reset(dev); + dev->drv->reset( dev ); } /* Get Frequencies: * - Base Frequency (unchangable base freq rate of timer, prescaler, clkinput) * - Current Tick Rate [in multiples of Base Frequency] */ static inline void tlib_get_freq( - void *hand, - unsigned int *basefreq, - unsigned int *tickrate) + void *hand, + unsigned int *basefreq, + unsigned int *tickrate +) { - struct tlib_dev *dev = hand; + struct tlib_dev *dev = hand; - dev->drv->get_freq(dev, basefreq, tickrate); + dev->drv->get_freq( dev, basefreq, tickrate ); } /* Set current Tick Rate in number of "Base-Frequency ticks" */ -static inline int tlib_set_freq(void *hand, unsigned int tickrate) +static inline int tlib_set_freq( void *hand, unsigned int tickrate ) { - struct tlib_dev *dev = hand; + struct tlib_dev *dev = hand; - return dev->drv->set_freq(dev, tickrate); + return dev->drv->set_freq( dev, tickrate ); } /* Register ISR at Timer ISR */ -static inline void tlib_irq_unregister(void *hand) +static inline void tlib_irq_unregister( void *hand ) { - struct tlib_dev *dev = hand; + struct tlib_dev *dev = hand; - if ( dev->isr_func ) { - dev->drv->irq_unreg(dev, dev->isr_func, dev->isr_data); - dev->isr_func = NULL; - } + if ( dev->isr_func ) { + dev->drv->irq_unreg( dev, dev->isr_func, dev->isr_data ); + dev->isr_func = NULL; + } } /* Register ISR at Timer ISR */ -static inline void tlib_irq_register(void *hand, tlib_isr_t func, void *data, int flags) +static inline void tlib_irq_register( + void *hand, + tlib_isr_t func, + void *data, + int flags +) { - struct tlib_dev *dev = hand; + struct tlib_dev *dev = hand; - /* Unregister previous ISR if installed */ - tlib_irq_unregister(hand); - dev->isr_func = func; - dev->isr_data = data; - dev->drv->irq_reg(dev, func, data, flags); + /* Unregister previous ISR if installed */ + tlib_irq_unregister( hand ); + dev->isr_func = func; + dev->isr_data = data; + dev->drv->irq_reg( dev, func, data, flags ); } /* Start Timer, ISRs will be generated if enabled. @@ -161,57 +171,57 @@ static inline void tlib_irq_register(void *hand, tlib_isr_t func, void *data, in * once determines if timer should restart (=0) on underflow automatically, * or stop when underflow is reached (=1). */ -static inline void tlib_start(void *hand, int once) +static inline void tlib_start( void *hand, int once ) { - struct tlib_dev *dev = hand; + struct tlib_dev *dev = hand; - dev->drv->start(dev, once); + dev->drv->start( dev, once ); } /* Stop Timer, no more ISRs will be generated */ -static inline void tlib_stop(void *hand) +static inline void tlib_stop( void *hand ) { - struct tlib_dev *dev = hand; + struct tlib_dev *dev = hand; - dev->drv->stop(dev); + dev->drv->stop( dev ); } /* Restart/Reload Timer, may be usefull if a Watchdog Timer */ -static inline void tlib_restart(void *hand) +static inline void tlib_restart( void *hand ) { - struct tlib_dev *dev = hand; + struct tlib_dev *dev = hand; - dev->drv->restart(dev); + dev->drv->restart( dev ); } /* Get current counter value (since last tick) */ -static inline void tlib_get_counter(void *hand, unsigned int *counter) +static inline void tlib_get_counter( void *hand, unsigned int *counter ) { - struct tlib_dev *dev = hand; + struct tlib_dev *dev = hand; - dev->drv->get_counter(dev, counter); + dev->drv->get_counter( dev, counter ); } /* Do a custom operation */ -static inline void tlib_custom(void *hand, int cmd, void *arg) +static inline void tlib_custom( void *hand, int cmd, void *arg ) { - struct tlib_dev *dev = hand; + struct tlib_dev *dev = hand; - dev->drv->custom(dev, cmd, arg); + dev->drv->custom( dev, cmd, arg ); } -static inline int tlib_interrupt_pending(void *hand, int ack) +static inline int tlib_interrupt_pending( void *hand, int ack ) { - struct tlib_dev *dev = hand; + struct tlib_dev *dev = hand; - return dev->drv->int_pend(dev, ack); + return dev->drv->int_pend( dev, ack ); } -static inline void tlib_get_widthmask(void *hand, unsigned int *widthmask) +static inline void tlib_get_widthmask( void *hand, unsigned int *widthmask ) { - struct tlib_dev *dev = hand; + struct tlib_dev *dev = hand; - dev->drv->get_widthmask(dev, widthmask); + dev->drv->get_widthmask( dev, widthmask ); } #ifdef __cplusplus