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bsps/aarch64: Add missing ISB after SCTLR write

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A write to the sctlr_el1 register is a 'context-changing operation'
and thus requires a pipeline flush for the change to actually take
effect on subsequent instructions.

The isb instruction gurantees this, and ensures mmu is enabled
immediately.
This commit is contained in:
Preetam Das
2026-01-16 16:02:01 -06:00
committed by Joel Sherrill
parent 88c4f7fa59
commit 57d18ec2f1
1 changed files with 3 additions and 0 deletions
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bsps/aarch64/include/bsp/aarch64-mmu.h
+3
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@@ -223,6 +223,9 @@ aarch64_mmu_enable( const aarch64_mmu_control *control )
sctlr = _AArch64_Read_sctlr_el1();
sctlr |= AARCH64_SCTLR_EL1_I | AARCH64_SCTLR_EL1_C | AARCH64_SCTLR_EL1_M;
_AArch64_Write_sctlr_el1( sctlr );
/* Ensure write to sctlr_el1 is complete before returning */
_AARCH64_Instruction_synchronization_barrier();
}
BSP_START_TEXT_SECTION static inline void