From 57d18ec2f1546af20c14327030797e5a025e8203 Mon Sep 17 00:00:00 2001 From: Preetam Das Date: Thu, 15 Jan 2026 01:11:42 +0530 Subject: [PATCH] bsps/aarch64: Add missing ISB after SCTLR write A write to the sctlr_el1 register is a 'context-changing operation' and thus requires a pipeline flush for the change to actually take effect on subsequent instructions. The isb instruction gurantees this, and ensures mmu is enabled immediately. --- bsps/aarch64/include/bsp/aarch64-mmu.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/bsps/aarch64/include/bsp/aarch64-mmu.h b/bsps/aarch64/include/bsp/aarch64-mmu.h index 6f24de761a..2a241fccb0 100644 --- a/bsps/aarch64/include/bsp/aarch64-mmu.h +++ b/bsps/aarch64/include/bsp/aarch64-mmu.h @@ -223,6 +223,9 @@ aarch64_mmu_enable( const aarch64_mmu_control *control ) sctlr = _AArch64_Read_sctlr_el1(); sctlr |= AARCH64_SCTLR_EL1_I | AARCH64_SCTLR_EL1_C | AARCH64_SCTLR_EL1_M; _AArch64_Write_sctlr_el1( sctlr ); + + /* Ensure write to sctlr_el1 is complete before returning */ + _AARCH64_Instruction_synchronization_barrier(); } BSP_START_TEXT_SECTION static inline void