mirror of
https://gitlab.rtems.org/rtems/rtos/rtems.git
synced 2026-09-22 19:11:44 +08:00
committed by
Joel Sherrill
parent
e81a5db70e
commit
3332e54772
@@ -50,16 +50,6 @@ void bsp_fatal_extension(
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rtems_fatal_code code
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)
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{
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rtems_interrupt_level level;
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/*
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* Make sure that interrupts don't interfere with the fatal error handling on
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* this processor. This reduces the likelihood to end up in a recursive
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* fatal error handling sequence.
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*/
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rtems_interrupt_local_disable( level );
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(void) level;
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#if defined(RTEMS_SMP)
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if (
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source == RTEMS_FATAL_SOURCE_SMP &&
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@@ -133,7 +133,8 @@ rtems_status_code rtems_extension_delete( rtems_id id );
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*
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* @par Notes
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* @parblock
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* The fatal extensions are invoked in extension forward order.
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* The fatal extensions are invoked in extension forward order and with
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* maskable interrupts disabled.
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*
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* The fatal extension should be extremely careful with respect to the RTEMS
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* directives it calls. Depending on the system termination source, the system
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@@ -55,6 +55,14 @@ void _Terminate(
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{
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ISR_Level level;
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/*
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* Make sure that interrupts don't interfere with the fatal error handling on
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* this processor. This reduces the likelihood to end up in a recursive
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* fatal error handling sequence.
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*/
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_ISR_Local_disable( level );
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(void) level;
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_User_extensions_Fatal( the_source, the_error );
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/*
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@@ -65,8 +73,6 @@ void _Terminate(
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*
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* The following code is only executed in badly configured applications.
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*/
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_ISR_Local_disable( level );
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(void) level;
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_CPU_Thread_Idle_body( 0 );
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}
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@@ -146,6 +146,7 @@ static void Fatal(
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ctx->source = source;
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ctx->code = code;
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_Atomic_Fetch_add_uint( &ctx->counter, 1, ATOMIC_ORDER_RELAXED );
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_ISR_Set_level( 0 );
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}
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static void FatalTaskExit(
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@@ -163,6 +163,7 @@ static void BadEnqueueFatal(
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SetFatalHandler( NULL, NULL );
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_ISR_Set_level( 0 );
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cpu_self = _Per_CPU_Get();
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_Thread_Dispatch_unnest( cpu_self );
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_Thread_Dispatch_unnest( cpu_self );
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@@ -654,6 +654,7 @@ static void Fatal(
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ctx = arg;
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++ctx->calls.fatal;
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T_assert_eq_int( ctx->calls.fatal, 1 );
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_ISR_Set_level( 0 );
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longjmp( ctx->thread_dispatch_context, 1 );
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}
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@@ -670,6 +671,7 @@ static void ResumeThreadDispatch(
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ctx = arg;
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SetFatalHandler( Fatal, ctx );
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_ISR_Set_level( 0 );
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longjmp( ctx->thread_dispatch_context, 1 );
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}
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@@ -390,6 +390,7 @@ static void Fatal(
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UnlockAllocator( ctx );
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SuspendSelf();
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_ISR_Set_level( 0 );
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cpu_self = _Per_CPU_Get();
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_Thread_Dispatch_unnest( cpu_self );
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_Thread_Dispatch_direct_no_return( cpu_self );
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@@ -720,6 +720,7 @@ static void Fatal(
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CaptureWorkerState( ctx );
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_ISR_Set_level( 0 );
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cpu_self = _Per_CPU_Get();
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_Thread_Dispatch_unnest( cpu_self );
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_Thread_Dispatch_direct_no_return( cpu_self );
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@@ -738,6 +739,7 @@ static void ResumeThreadDispatch(
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ctx = arg;
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SetFatalHandler( Fatal, ctx );
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_ISR_Set_level( 0 );
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longjmp( ctx->thread_dispatch_context, 1 );
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}
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@@ -191,12 +191,16 @@ static void FatalExtension2(
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rtems_fatal_code code
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)
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{
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rtems_status_code sc;
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rtems_status_code sc;
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rtems_interrupt_level level;
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FatalExtension( source, always_set_to_false, code, 2 );
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_ISR_Set_level( 0 );
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sc = rtems_extension_delete( extension_ids[ 3 ] );
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T_quiet_rsc_success( sc );
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rtems_interrupt_local_disable( level );
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(void) level;
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}
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static void FatalExtension3(
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@@ -223,12 +227,16 @@ static void FatalExtension5(
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rtems_fatal_code code
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)
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{
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rtems_status_code sc;
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rtems_status_code sc;
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rtems_interrupt_level level;
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FatalExtension( source, always_set_to_false, code, 5 );
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_ISR_Set_level( 0 );
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sc = rtems_extension_delete( extension_ids[ 5 ] );
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T_quiet_rsc_success( sc );
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rtems_interrupt_local_disable( level );
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(void) level;
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}
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static void FatalExtension6(
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@@ -237,12 +245,16 @@ static void FatalExtension6(
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rtems_fatal_code code
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)
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{
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rtems_status_code sc;
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rtems_status_code sc;
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rtems_interrupt_level level;
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FatalExtension( source, always_set_to_false, code, 6 );
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_ISR_Set_level( 0 );
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sc = rtems_extension_delete( extension_ids[ 4 ] );
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T_quiet_rsc_success( sc );
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rtems_interrupt_local_disable( level );
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(void) level;
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}
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/**
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@@ -254,6 +266,7 @@ static void ScoreInterrValTerminate_Action_0( void )
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{
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rtems_status_code sc;
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rtems_extensions_table table;
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uint32_t test_case_isr_level;
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memset( &table, 0, sizeof( table ) );
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@@ -297,6 +310,7 @@ static void ScoreInterrValTerminate_Action_0( void )
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);
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T_step_rsc_success( 4, sc );
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test_case_isr_level = _ISR_Get_level();
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test_case_active = true;
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if ( setjmp( before_terminate ) == 0 ) {
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@@ -392,15 +406,16 @@ static void ScoreInterrValTerminate_Action_0( void )
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* Check that maskable interrupts were enabled for the user extensions. Check
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* that the idle loop executes with maskable interrupts disabled.
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*/
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T_step_eq_u32( 35, extension_isr_level, 0 );
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T_step_ne_u32( 36, idle_isr_level, 0 );
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T_step_eq_u32( 35, test_case_isr_level, 0 );
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T_step_ne_u32( 36, extension_isr_level, 0 );
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T_step_ne_u32( 37, idle_isr_level, 0 );
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/*
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* Check that an idle loop executed after invocation of the user extensions.
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*/
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T_step_eq_uint( 37, idle_counter, 7 );
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T_step_eq_uint( 38, idle_counter, 7 );
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T_step_eq_uint(
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38,
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39,
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_Atomic_Load_uint( &counter, ATOMIC_ORDER_RELAXED ),
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7
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);
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@@ -411,7 +426,7 @@ static void ScoreInterrValTerminate_Action_0( void )
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*/
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T_TEST_CASE( ScoreInterrValTerminate )
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{
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T_plan( 39 );
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T_plan( 40 );
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ScoreInterrValTerminate_Action_0();
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}
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@@ -275,6 +275,7 @@ static void ThreadQueueDeadlock(
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T_eq_int( source, INTERNAL_ERROR_CORE );
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T_eq_int( code, INTERNAL_ERROR_THREAD_QUEUE_DEADLOCK );
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SetFatalHandler( NULL, NULL );
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_ISR_Set_level( 0 );
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longjmp( ctx->before_enqueue, 1 );
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}
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