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score: Remove unused _CPU_Fatal_halt()

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Update #5067.
This commit is contained in:
Sebastian Huber
2024-07-17 18:38:08 +02:00
committed by Joel Sherrill
parent e80883b406
commit e81a5db70e
42 changed files with 1 additions and 383 deletions
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41
bsps/i386/pc386/start/bsp_fatal_halt.c
View File

@@ -1,41 +0,0 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/**
* COPYRIGHT (c) 2016.
* On-Line Applications Research Corporation (OAR).
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <rtems/score/cpuimpl.h>
void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error )
{
__asm__ volatile (
"cli\n\t"
"movl %0,%%eax\n\t"
"hlt\n\t"
: "=r" ((error))
: "0" ((error))
);
RTEMS_UNREACHABLE();
}

6
bsps/riscv/griscv/start/bsp_fatal_halt.c
View File

@@ -27,7 +27,6 @@
*/
#include <bsp/bootcard.h>
#include <rtems/score/cpuimpl.h>
void bsp_reset( rtems_fatal_source source, rtems_fatal_code code )
{
@@ -35,8 +34,3 @@ void bsp_reset( rtems_fatal_source source, rtems_fatal_code code )
asm ("ecall");
RTEMS_UNREACHABLE();
}
void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr code )
{
bsp_reset( source, code );
}

5
bsps/riscv/noel/start/bsp_fatal_halt.c
View File

@@ -43,8 +43,3 @@ void bsp_reset( rtems_fatal_source source, rtems_fatal_code code )
__asm__ volatile ("srai zero, zero, 0x7");
RTEMS_UNREACHABLE();
}
void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr code )
{
bsp_reset( source, code );
}

6
bsps/riscv/riscv/start/bsp_fatal_halt.c
View File

@@ -30,7 +30,6 @@
#include <bsp/riscv.h>
#include <bsp/fdt.h>
#include <rtems/score/cpuimpl.h>
#include <libfdt.h>
@@ -65,8 +64,3 @@ void bsp_reset( rtems_fatal_source source, rtems_fatal_code code )
}
}
}
void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr code )
{
bsp_reset( source, code );
}

54
cpukit/libtest/testgcovcpufatalhalt.c
View File

@@ -1,54 +0,0 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/**
* @file
*
* @ingroup RTEMSTestFrameworkImpl
*
* @brief This source file contains the implementation of a wrapper for
* _CPU_Fatal_halt() which dumps the gcov information using
* rtems_test_gcov_dump_info() before the real _CPU_Fatal_halt() is called.
*/
/*
* Copyright (C) 2021, 2022 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include <rtems/test-info.h>
#include <rtems/score/cpu.h>
void __real__CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error );
void __wrap__CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error );
void __wrap__CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error )
{
rtems_test_gcov_dump_info();
__real__CPU_Fatal_halt( source, error );
}

13
cpukit/score/cpu/aarch64/cpu.c
View File

@@ -178,16 +178,3 @@ void _CPU_Initialize( void )
{
/* Do nothing */
}
void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error )
{
ISR_Level level;
_CPU_ISR_Disable( level );
(void) level;
__asm__ volatile ("mov x0, %0\n"
: "=r" (error)
: "0" (error)
: "x0" );
while (1);
}

2
cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h
View File

@@ -61,8 +61,6 @@
extern "C" {
#endif
RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error );
typedef struct {
uint64_t x0;
uint64_t register_lr_original;

19
cpukit/score/cpu/arm/cpu.c
View File

@@ -8,7 +8,7 @@
* @brief This source file contains static assertions to ensure the consistency
* of interfaces used in C and assembler and it contains the ARM-specific
* implementation of _CPU_Initialize(), _CPU_ISR_Get_level(),
* _CPU_ISR_Set_level(), _CPU_Context_Initialize(), and _CPU_Fatal_halt().
* _CPU_ISR_Set_level(), and _CPU_Context_Initialize().
*/
/*
@@ -165,20 +165,3 @@ void _CPU_Initialize( void )
}
#endif /* ARM_MULTILIB_ARCH_V4 */
void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error )
{
ISR_Level level;
_CPU_ISR_Disable( level );
(void) level;
__asm__ volatile ("mov r0, %0\n"
: "=r" (error)
: "0" (error)
: "r0" );
while ( true ) {
/* Do nothing */
}
}

2
cpukit/score/cpu/arm/include/rtems/score/cpuimpl.h
View File

@@ -149,8 +149,6 @@ static inline struct Per_CPU_Control *_ARM_Get_current_per_CPU_control( void )
#endif /* ARM_MULTILIB_ARCH_V4 */
RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error );
void _CPU_Context_volatile_clobber( uintptr_t pattern );
void _CPU_Context_validate( uintptr_t pattern );

11
cpukit/score/cpu/bfin/cpu.c
View File

@@ -74,17 +74,6 @@ void _CPU_Initialize(void)
__asm__ __volatile__ ("syscfg = %0" : : "d" (0x00000004));
}
void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error )
{
__asm__ volatile ( "cli R1; R1 = %0; _halt: idle; jump _halt;"
: : "r" (error) );
}
/* end of Fatal Error manager macros */
/*
* _CPU_ISR_Get_level
*

2
cpukit/score/cpu/bfin/include/rtems/score/cpuimpl.h
View File

@@ -37,8 +37,6 @@
extern "C" {
#endif
RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error );
static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
{
(void) pattern;

2
cpukit/score/cpu/i386/include/rtems/score/cpuimpl.h
View File

@@ -58,8 +58,6 @@
extern "C" {
#endif
RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error );
static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
{
(void) pattern;

12
cpukit/score/cpu/lm32/cpu.c
View File

@@ -46,18 +46,6 @@ void _CPU_Initialize(void)
/* FP context initialization support goes here */
}
void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error )
{
ISR_Level level;
_CPU_ISR_Disable( level );
(void) level;
while ( true ) {
/* Do nothing */
}
}
uint32_t _CPU_ISR_Get_level( void )
{
/*

2
cpukit/score/cpu/lm32/include/rtems/score/cpuimpl.h
View File

@@ -36,8 +36,6 @@
extern "C" {
#endif
RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error );
static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
{
(void) pattern;

23
cpukit/score/cpu/m68k/cpu.c
View File

@@ -108,29 +108,6 @@ void _CPU_Initialize(void)
m68k_install_interrupt_stack();
}
void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error )
{
#if ( defined(__mcoldfire__) )
__asm__ volatile( "move.w %%sr,%%d0\n\t"
"or.l %2,%%d0\n\t"
"move.w %%d0,%%sr\n\t"
"move.l %1,%%d0\n\t"
"move.l #0xDEADBEEF,%%d1\n\t"
"halt"
: "=g" (error)
: "0" (error), "d"(0x0700)
: "d0", "d1" );
#else
__asm__ volatile( "movl %0,%%d0; "
"orw #0x0700,%%sr; "
"stop #0x2700" : "=d" ((error)) : "0" ((error)) );
#endif
/* end of Fatal Error manager macros */
}
uint32_t _CPU_ISR_Get_level( void )
{
uint32_t level;

2
cpukit/score/cpu/m68k/include/rtems/score/cpuimpl.h
View File

@@ -56,8 +56,6 @@
extern "C" {
#endif
RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error );
static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
{
(void) pattern;

11
cpukit/score/cpu/microblaze/include/rtems/score/cpu.h
View File

@@ -290,17 +290,6 @@ void _CPU_Context_Initialize(
/* end of Context handler macros */
/* Fatal Error manager macros */
/* TODO */
#define _CPU_Fatal_halt(_source, _error ) \
do { \
__asm__ volatile ( "sleep" ); \
for(;;) {} \
} while (0)
/* end of Fatal Error manager macros */
/* Bitfield handler macros */
#define CPU_USE_GENERIC_BITFIELD_CODE TRUE

12
cpukit/score/cpu/mips/cpu.c
View File

@@ -113,18 +113,6 @@ void _CPU_Initialize(void)
#endif
}
void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error )
{
ISR_Level level;
_CPU_ISR_Disable( level );
(void) level;
while ( true ) {
/* Do nothing */
}
}
uint32_t _CPU_ISR_Get_level( void )
{
unsigned int sr;

2
cpukit/score/cpu/mips/include/rtems/score/cpuimpl.h
View File

@@ -56,8 +56,6 @@
extern "C" {
#endif
RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error );
static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
{
(void) pattern;

12
cpukit/score/cpu/moxie/cpu.c
View File

@@ -58,18 +58,6 @@ void _CPU_Initialize(void)
/* FP context initialization support goes here */
}
void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error )
{
ISR_Level level;
_CPU_ISR_Disable( level );
(void) level;
while ( true ) {
/* Do nothing */
}
}
/*
* _CPU_ISR_Get_level
*

2
cpukit/score/cpu/moxie/include/rtems/score/cpuimpl.h
View File

@@ -56,8 +56,6 @@
extern "C" {
#endif
RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error );
static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
{
(void) pattern;

2
cpukit/score/cpu/nios2/include/rtems/score/cpuimpl.h
View File

@@ -56,8 +56,6 @@
extern "C" {
#endif
RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error );
void _CPU_Context_volatile_clobber( uintptr_t pattern );
void _CPU_Context_validate( uintptr_t pattern );

45
cpukit/score/cpu/nios2/nios2-fatal-halt.c
View File

@@ -1,45 +0,0 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
* Copyright (c) 2011 embedded brains GmbH & Co. KG
*
* Copyright (c) 2006 Kolja Waschk (rtemsdev/ixo.de)
*
* COPYRIGHT (c) 1989-2004.
* On-Line Applications Research Corporation (OAR).
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <rtems/score/cpuimpl.h>
#include <rtems/score/nios2-utility.h>
void _CPU_Fatal_halt( uint32_t _source, CPU_Uint32ptr _error )
{
/* write 0 to status register (disable interrupts) */
__builtin_wrctl( NIOS2_CTLREG_INDEX_STATUS, 0 );
/* write error code to ET register */
__asm__ volatile ("mov et, %z0" : : "rM" (_error));
while (1);
}

11
cpukit/score/cpu/no_cpu/include/rtems/score/cpuimpl.h
View File

@@ -120,17 +120,6 @@ register struct Per_CPU_Control *_CPU_Per_CPU_current asm( "rX" );
*/
#define _CPU_Get_thread_executing() ( _CPU_Per_CPU_current->executing )
/**
* This routine copies _error into a known place -- typically a stack
* location or a register, optionally disables interrupts, and
* halts/stops the CPU.
*
* Port Specific Information:
*
* XXX document implementation including references if appropriate
*/
RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error );
/* end of Fatal Error manager macros */
/**

14
cpukit/score/cpu/or1k/cpu.c
View File

@@ -47,20 +47,6 @@ void _CPU_Initialize(void)
/* Do nothing */
}
void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error )
{
ISR_Level level;
_CPU_ISR_Disable( level );
(void) level;
_OR1KSIM_CPU_Halt();
while ( true ) {
/* Do nothing */
}
}
/* end of Fatal Error manager macros */
/**

2
cpukit/score/cpu/or1k/include/rtems/score/cpuimpl.h
View File

@@ -56,8 +56,6 @@
extern "C" {
#endif
RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error );
void _CPU_Context_volatile_clobber( uintptr_t pattern );
void _CPU_Context_validate( uintptr_t pattern );

15
cpukit/score/cpu/powerpc/cpu.c
View File

@@ -345,18 +345,3 @@ RTEMS_STATIC_ASSERT(
sizeof(CPU_Exception_frame) + FRAME_LINK_SPACE <= PPC_EXC_FRAME_SIZE,
CPU_Exception_frame
);
void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error )
{
ppc_interrupt_disable();
__asm__ volatile (
"mr 3, %0\n"
"mr 4, %1\n"
"1:\n"
"b 1b\n"
: \
: "r" (source), "r" (error)
: "memory"
);
RTEMS_UNREACHABLE();
}

2
cpukit/score/cpu/powerpc/include/rtems/score/cpuimpl.h
View File

@@ -269,8 +269,6 @@ static inline struct Per_CPU_Control *_PPC_Get_current_per_CPU_control( void )
#endif /* RTEMS_SMP */
RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error );
void _CPU_Context_volatile_clobber( uintptr_t pattern );
void _CPU_Context_validate( uintptr_t pattern );

2
cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h
View File

@@ -426,8 +426,6 @@ static inline struct Per_CPU_Control *_RISCV_Get_current_per_CPU_control( void )
#endif /* RTEMS_SMP */
RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error );
void _CPU_Context_volatile_clobber( uintptr_t pattern );
void _CPU_Context_validate( uintptr_t pattern );

7
cpukit/score/cpu/sh/cpu.c
View File

@@ -76,13 +76,6 @@ void _CPU_Initialize(void)
_CPU_ISR_Set_level( level ) ;
}
void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error )
{
__asm__ volatile("mov.l %0,r0"::"m" (error));
__asm__ volatile("mov #1, r4");
__asm__ volatile("trapa #34");
}
/*
* _CPU_ISR_Get_level
*/

2
cpukit/score/cpu/sh/include/rtems/score/cpuimpl.h
View File

@@ -37,8 +37,6 @@
extern "C" {
#endif
RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error );
static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
{
(void) pattern;

2
cpukit/score/cpu/sparc/include/rtems/score/cpuimpl.h
View File

@@ -223,8 +223,6 @@ register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__( "g6" );
#define _CPU_Get_thread_executing() ( _SPARC_Per_CPU_current->executing )
RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error );
void _CPU_Context_volatile_clobber( uintptr_t pattern );
void _CPU_Context_validate( uintptr_t pattern );

2
cpukit/score/cpu/sparc/syscall.S
View File

@@ -45,11 +45,9 @@ SYM(syscall):
PUBLIC(bsp_reset)
PUBLIC(sparc_syscall_exit)
PUBLIC(_CPU_Fatal_halt)
SYM(bsp_reset):
SYM(sparc_syscall_exit):
SYM(_CPU_Fatal_halt):
mov SYS_exit, %g1
mov %o0, %g2 ! Additional exit code 1

9
cpukit/score/cpu/sparc64/cpu.c
View File

@@ -83,15 +83,6 @@ void _CPU_Initialize(void)
_CPU_ISR_Dispatch_disable = 0;
}
void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error )
{
uint32_t level;
level = sparc_disable_interrupts();
__asm__ volatile ( "mov %0, %%g1 " : "=r" (level) : "0" (level) );
while (1); /* loop forever */
}
void _CPU_Context_Initialize(
Context_Control *the_context,
void *stack_base,

2
cpukit/score/cpu/sparc64/include/rtems/score/cpuimpl.h
View File

@@ -56,8 +56,6 @@
extern "C" {
#endif
RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error );
static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
{
(void) pattern;

7
cpukit/score/cpu/v850/cpu.c
View File

@@ -50,13 +50,6 @@ void _CPU_Initialize(void)
{
}
void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error )
{
__asm__ __volatile__ ( "di" );
__asm__ __volatile__ ( "mov %0, r10; " : "=r" ((error)) );
__asm__ __volatile__ ( "halt" );
}
/*
* v850 Specific Information:
*

2
cpukit/score/cpu/v850/include/rtems/score/cpuimpl.h
View File

@@ -56,8 +56,6 @@
extern "C" {
#endif
RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error );
static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
{
(void) pattern;

12
cpukit/score/cpu/x86_64/cpu.c
View File

@@ -60,15 +60,3 @@ void _CPU_Initialize(void)
asm volatile( "stmxcsr %0" : "=m"(_CPU_Null_fp_context.mxcsr) );
asm volatile( "fstcw %0" : "=m"(_CPU_Null_fp_context.fpucw) );
}
void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error )
{
ISR_Level level;
_CPU_ISR_Disable( level );
(void) level;
while ( true ) {
/* Do nothing */
}
}

2
cpukit/score/cpu/x86_64/include/rtems/score/cpuimpl.h
View File

@@ -57,8 +57,6 @@
extern "C" {
#endif
RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error );
static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
{
(void) pattern;

1
spec/build/bsps/i386/pc386/obj.yml
View File

@@ -51,7 +51,6 @@ source:
- bsps/i386/pc386/console/tty_drv.c
- bsps/i386/pc386/console/uart.c
- bsps/i386/pc386/console/uart_bus_pci.c
- bsps/i386/pc386/start/bsp_fatal_halt.c
- bsps/i386/pc386/start/bspcmdline.c
- bsps/i386/pc386/start/bspgetworkarea.c
- bsps/i386/pc386/start/bspidle.S

1
spec/build/cpukit/cpunios2.yml
View File

@@ -31,7 +31,6 @@ source:
- cpukit/score/cpu/nios2/nios2-context-volatile-clobber.S
- cpukit/score/cpu/nios2/nios2-eic-il-low-level.S
- cpukit/score/cpu/nios2/nios2-exception-frame-print.c
- cpukit/score/cpu/nios2/nios2-fatal-halt.c
- cpukit/score/cpu/nios2/nios2-iic-irq.c
- cpukit/score/cpu/nios2/nios2-iic-low-level.S
- cpukit/score/cpu/nios2/nios2-initialize.c

1
spec/build/cpukit/librtemstest.yml
View File

@@ -44,7 +44,6 @@ source:
- cpukit/libtest/testbusy.c
- cpukit/libtest/testexit.c
- cpukit/libtest/testextension.c
- cpukit/libtest/testgcovcpufatalhalt.c
- cpukit/libtest/testgcovbspreset.c
- cpukit/libtest/testgcovdumpinfo.c
- cpukit/libtest/testparallel.c