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2002-03-20 Greg Menke <gregory.menke@gsfc.nasa.gov>

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* cpu_asm.S: Now compiles on 4600 and 4650.
This commit is contained in:
Joel Sherrill
2002-03-20 18:16:07 +00:00
parent eaeb467139
commit 25d3d4d16c
4 changed files with 22 additions and 0 deletions
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c/src/exec/score/cpu/mips/ChangeLog
+4
View File
@@ -1,3 +1,7 @@
2002-03-20 Greg Menke <gregory.menke@gsfc.nasa.gov>
* cpu_asm.S: Now compiles on 4600 and 4650.
2002-03-13 Greg Menke <gregory.menke@gsfc.nasa.gov>
* cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug.
c/src/exec/score/cpu/mips/cpu_asm.S
+7
View File
@@ -674,9 +674,16 @@ _ISR_Handler_Exception:
/* CP0 special registers */
#if __mips == 1
MFC0 t0,C0_TAR
#endif
MFC0 t1,C0_BADVADDR
#if __mips == 1
STREG t0,R_TAR*R_SZ(sp)
#else
NOP
#endif
STREG t1,R_BADVADDR*R_SZ(sp)
#if ( CPU_HARDWARE_FP == TRUE )
cpukit/score/cpu/mips/ChangeLog
+4
View File
@@ -1,3 +1,7 @@
2002-03-20 Greg Menke <gregory.menke@gsfc.nasa.gov>
* cpu_asm.S: Now compiles on 4600 and 4650.
2002-03-13 Greg Menke <gregory.menke@gsfc.nasa.gov>
* cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug.
cpukit/score/cpu/mips/cpu_asm.S
+7
View File
@@ -674,9 +674,16 @@ _ISR_Handler_Exception:
/* CP0 special registers */
#if __mips == 1
MFC0 t0,C0_TAR
#endif
MFC0 t1,C0_BADVADDR
#if __mips == 1
STREG t0,R_TAR*R_SZ(sp)
#else
NOP
#endif
STREG t1,R_BADVADDR*R_SZ(sp)
#if ( CPU_HARDWARE_FP == TRUE )