diff --git a/c/src/exec/score/cpu/mips/ChangeLog b/c/src/exec/score/cpu/mips/ChangeLog
index ddb8d5f32a..f37bcc2d9e 100644
--- a/c/src/exec/score/cpu/mips/ChangeLog
+++ b/c/src/exec/score/cpu/mips/ChangeLog
@@ -1,3 +1,7 @@
+2002-03-20	Greg Menke <gregory.menke@gsfc.nasa.gov>
+
+	* cpu_asm.S: Now compiles on 4600 and 4650.
+
 2002-03-13	Greg Menke <gregory.menke@gsfc.nasa.gov>
 
 	* cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug.
diff --git a/c/src/exec/score/cpu/mips/cpu_asm.S b/c/src/exec/score/cpu/mips/cpu_asm.S
index 63796714c1..657c490d96 100644
--- a/c/src/exec/score/cpu/mips/cpu_asm.S
+++ b/c/src/exec/score/cpu/mips/cpu_asm.S
@@ -674,9 +674,16 @@ _ISR_Handler_Exception:
 
         /* CP0 special registers */
 
+#if __mips == 1
 	MFC0	 t0,C0_TAR
+#endif
         MFC0     t1,C0_BADVADDR
+	
+#if __mips == 1
         STREG	 t0,R_TAR*R_SZ(sp)
+#else
+	NOP
+#endif
         STREG    t1,R_BADVADDR*R_SZ(sp)
 	
 #if ( CPU_HARDWARE_FP == TRUE )
diff --git a/cpukit/score/cpu/mips/ChangeLog b/cpukit/score/cpu/mips/ChangeLog
index ddb8d5f32a..f37bcc2d9e 100644
--- a/cpukit/score/cpu/mips/ChangeLog
+++ b/cpukit/score/cpu/mips/ChangeLog
@@ -1,3 +1,7 @@
+2002-03-20	Greg Menke <gregory.menke@gsfc.nasa.gov>
+
+	* cpu_asm.S: Now compiles on 4600 and 4650.
+
 2002-03-13	Greg Menke <gregory.menke@gsfc.nasa.gov>
 
 	* cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug.
diff --git a/cpukit/score/cpu/mips/cpu_asm.S b/cpukit/score/cpu/mips/cpu_asm.S
index 63796714c1..657c490d96 100644
--- a/cpukit/score/cpu/mips/cpu_asm.S
+++ b/cpukit/score/cpu/mips/cpu_asm.S
@@ -674,9 +674,16 @@ _ISR_Handler_Exception:
 
         /* CP0 special registers */
 
+#if __mips == 1
 	MFC0	 t0,C0_TAR
+#endif
         MFC0     t1,C0_BADVADDR
+	
+#if __mips == 1
         STREG	 t0,R_TAR*R_SZ(sp)
+#else
+	NOP
+#endif
         STREG    t1,R_BADVADDR*R_SZ(sp)
 	
 #if ( CPU_HARDWARE_FP == TRUE )