743b614875
* [components][clock_time] Refactor time subsystem around clock_time Introduce the clock_time core with clock source/event separation, high-resolution scheduling, and boot-time helpers, plus clock_timer adapters for timer peripherals. Remove legacy ktime/cputime/hwtimer implementations and migrate arch and BSP time paths to the new subsystem while keeping POSIX time integration functional. Update drivers, Kconfig/SConscript wiring, documentation, and tests; add clock_time overview docs and align naming to clock_boottime/clock_hrtimer/clock_timer. * [components][clock_time] Use BSP-provided clock timer frequency on riscv64 * [risc-v] Use runtime clock timer frequency for tick and delays * [bsp] Add clock timer frequency hooks for riscv64 boards * [bsp] Update Renesas RA driver doc clock_timer link * [bsp] Sync zynqmp-r5-axu4ev rtconfig after config refresh * [bsp][rk3500] Update rk3500 clock configuration * [bsp][hpmicro] Add rt_hw_us_delay hook and update board delays * [bsp][stm32l496-st-nucleo] enable clock_time for hwtimer sample in ci * [bsp][hpmicro] Fix rtconfig include scope for hpm6750evk Move rtconfig.h include outside the ENET_MULTIPLE_PORT guard for hpm6750evk and hpm6750evk2 so configuration macros are available regardless of ENET settings. * [bsp][raspi3] select clock time for systimer * [bsp][hpm5300evk] Trim trailing blank line * [bsp][hpm5301evklite] Trim trailing blank line * [bsp][hpm5e00evk] Trim trailing blank line * [bsp][hpm6200evk] Trim trailing blank line * [bsp][hpm6300evk] Trim trailing blank line * [bsp][hpm6750evk] Trim trailing blank line * [bsp][hpm6750evk2] Trim trailing blank line * [bsp][hpm6750evkmini] Trim trailing blank line * [bsp][hpm6800evk] Trim trailing blank line * [bsp][hpm6e00evk] Trim trailing blank line * [bsp][nxp] switch lpc178x to gcc and remove mcx timer source * [bsp][stm32] fix the CONFIG_RT_USING_CLOCK_TIME issue. * [docs][clock_time] add clock time documentation * [docs][clock_time] Update clock time subsystem documentation - Update device driver index to use correct page reference - Clarify upper layer responsibilities in architecture overview - Update README to describe POSIX/libc, Soft RTC, and device driver usage - Refine architecture diagram with improved layout and color scheme - Remove obsolete clock_timer.md file * [kernel][utest] Trim trailing space * [clock_time] Fix hrtimer wrap handling * [clock_time] fix the static rt_inline issue * [clock_time] fix the rt_clock_hrtimer_control result issue
STM32G071-Nucleo BSP Introduction
MCU: STM32G071RB @64MHz, 128KB FLASH, 36KB RAM
The STM32G071x8/xB mainstream microcontrollers are based on high-performance Arm® Cortex®-M0+ 32-bit RISC core operating at up to 64 MHz frequency. Offering a high level of integration, they are suitable for a wide range of applications in consumer, industrial and appliance domains and ready for the Internet of Things (IoT) solutions.
The devices incorporate a memory protection unit (MPU), high-speed embedded memories (up to 128 Kbytes of Flash program memory with read protection, write protection, proprietary code protection, and securable area, and 36 Kbytes of SRAM), DMA and an extensive range of system functions, enhanced I/Os and peripherals. The devices offer standard communication interfaces (two I2Cs, two SPIs / one I2S, one HDMI CEC, and four USARTs), one 12-bit ADC (2.5 MSps) with up to 19 channels, one 12-bit DAC with two channels, two fast comparators, an internal voltage reference buffer, a low-power RTC, an advanced control PWM timer running at up to double the CPU frequency, five general-purpose 16-bit timers with one running at up to double the CPU frequency, a 32-bit general-purpose timer, two basic timers, two low-power 16-bit timers, two watchdog timers, and a SysTick timer. The STM32G071x8/xB devices provide a fully integrated USB Type-C Power Delivery controller. The devices operate within ambient temperatures from -40 to 125°C. They can operate with supply voltages from 1.7 V to 3.6 V. Optimized dynamic consumption combined with a comprehensive set of power-saving modes, low-power timers and low-power UART, allows the design of low-power applications. VBAT direct battery input allows keeping RTC and backup registers powered. The devices come in packages with 28 to 64 pins.
KEY FEATURES
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Core: Arm® 32-bit Cortex®-M0+ CPU, frequency up to 64 MHz
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-40°C to 85°C/105°C/125°C operating temperature
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Memories
- Up to 128 Kbytes of Flash memory with protection and securable area
- 36 Kbytes of SRAM (32 Kbytes with HW parity check)
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CRC calculation unit
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Reset and power management
- Voltage range: 1.7 V to 3.6 V
- Power-on/Power-down reset (POR/PDR)
- Programmable Brownout reset (BOR)
- Programmable voltage detector (PVD)
- Low-power modes:Sleep, Stop, Standby, Shutdown
- VBAT supply for RTC and backup registers
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Clock management
- 4 to 48 MHz crystal oscillator
- 32 kHz crystal oscillator with calibration
- Internal 16 MHz RC with PLL option (±1 %)
- Internal 32 kHz RC oscillator (±5 %)
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Up to 60 fast I/Os
- All mappable on external interrupt vectors
- Multiple 5 V-tolerant I/Os
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7-channel DMA controller with flexible mapping
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12-bit, 0.4 µs ADC (up to 16 ext. channels)
- Up to 16-bit with hardware oversampling
- Conversion range: 0 to 3.6V
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Two 12-bit DACs, low-power sample-and-hold
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Two fast low-power analog comparators, with programmable input and output, rail-to-rail
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14 timers (two 128 MHz capable): 16-bit for advanced motor control, one 32-bit and five 16-bit general-purpose, two basic 16-bit, two low-power 16-bit, two watchdogs, SysTick timer
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Calendar RTC with alarm and periodic wakeup from Stop/Standby/Shutdown
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Communication interfaces
- Two I2C-bus interfaces supporting Fast-mode Plus (1 Mbit/s) with extra current sink, one supporting SMBus/PMBus and wakeup from Stop mode
- Four USARTs with master/slave synchronous SPI; two supporting ISO7816 interface, LIN, IrDA capability, auto baud rate detection and wakeup feature
- One low-power UART
- Two SPIs (32 Mbit/s) with 4- to 16-bit programmable bitframe, one multiplexed with I2S interface
- HDMI CEC interface, wakeup on header
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USB Type-C™ Power Delivery controller
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Development support: serial wire debug (SWD)
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96-bit unique ID
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All packages ECOPACK®2 compliant
Read more
| Documents | Description |
|---|---|
| STM32_Nucleo-64_BSP_Introduction | How to run RT-Thread on STM32 Nucleo-64 boards (Must-Read) |
| STM32G071RB ST Official Website | STM32G071RB datasheet and other resources |
Maintained By
Translated By
Meco Man @ RT-Thread Community