68 Commits
Author SHA1 Message Date
CYFS 2aeebc5cbe [bsp][cvitek]:fix i2c err and clock_time#11324
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2026-04-15 11:52:39 +08:00
Bernard Xiong 743b614875 [components][clock_time] Refactor time subsystem around clock_time (#11111)
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* [components][clock_time] Refactor time subsystem around clock_time

Introduce the clock_time core with clock source/event separation, high-resolution scheduling, and boot-time helpers, plus clock_timer adapters for timer peripherals.

Remove legacy ktime/cputime/hwtimer implementations and migrate arch and BSP time paths to the new subsystem while keeping POSIX time integration functional.

Update drivers, Kconfig/SConscript wiring, documentation, and tests; add clock_time overview docs and align naming to clock_boottime/clock_hrtimer/clock_timer.

* [components][clock_time] Use BSP-provided clock timer frequency on riscv64

* [risc-v] Use runtime clock timer frequency for tick and delays

* [bsp] Add clock timer frequency hooks for riscv64 boards

* [bsp] Update Renesas RA driver doc clock_timer link

* [bsp] Sync zynqmp-r5-axu4ev rtconfig after config refresh

* [bsp][rk3500] Update rk3500 clock configuration

* [bsp][hpmicro] Add rt_hw_us_delay hook and update board delays

* [bsp][stm32l496-st-nucleo] enable clock_time for hwtimer sample in ci

* [bsp][hpmicro] Fix rtconfig include scope for hpm6750evk

Move rtconfig.h include outside the ENET_MULTIPLE_PORT guard for hpm6750evk and hpm6750evk2 so configuration macros are available regardless of ENET settings.

* [bsp][raspi3] select clock time for systimer

* [bsp][hpm5300evk] Trim trailing blank line

* [bsp][hpm5301evklite] Trim trailing blank line

* [bsp][hpm5e00evk] Trim trailing blank line

* [bsp][hpm6200evk] Trim trailing blank line

* [bsp][hpm6300evk] Trim trailing blank line

* [bsp][hpm6750evk] Trim trailing blank line

* [bsp][hpm6750evk2] Trim trailing blank line

* [bsp][hpm6750evkmini] Trim trailing blank line

* [bsp][hpm6800evk] Trim trailing blank line

* [bsp][hpm6e00evk] Trim trailing blank line

* [bsp][nxp] switch lpc178x to gcc and remove mcx timer source

* [bsp][stm32] fix the CONFIG_RT_USING_CLOCK_TIME issue.

* [docs][clock_time] add clock time documentation

* [docs][clock_time] Update clock time subsystem documentation

- Update device driver index to use correct page reference
- Clarify upper layer responsibilities in architecture overview
- Update README to describe POSIX/libc, Soft RTC, and device driver usage
- Refine architecture diagram with improved layout and color scheme
- Remove obsolete clock_timer.md file

* [kernel][utest] Trim trailing space

* [clock_time] Fix hrtimer wrap handling

* [clock_time] fix the static rt_inline issue

* [clock_time] fix the rt_clock_hrtimer_control result issue
2026-01-31 17:44:27 +08:00
ache 36bf8f656b feat:clang format ignore migration 2025-10-28 14:13:56 +08:00
flyingcys f4168669a7 Fix the crash of the SPI driver under the smart mode
Signed-off-by: flyingcys flyingcys@163.com
2025-07-04 20:51:04 +08:00
Chen Wang 5b88c8c207 bsp: cvitek: fix build warnings for spi
See https://github.com/RT-Thread/rt-thread/issues/10138.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2025-03-24 20:38:08 +08:00
imcu 6073200d2e [bsp][cvitek] fix spi driver build error
Build error: 'struct _device_spi' has no member named 'base_addr'

Analyze: the name should be dws.regs

Solution: change base_addr to dws.regs

Signed-off-by: zdtyuiop4444 <ign7798540@gmail.com>
2025-03-24 09:24:11 +08:00
Chen Wang 2322f0154e bsp: cvitek: remove support for spinor/spinand
Confirmed with milkv, only the sd card version is sold
by default for duo in the market. The spi pins are
provided through stamp holes, so that users can solder
the corresponding components on their baseboard during
secondary development.

In order to simplify maintenance work, the mainline
will only support the sd-card version and no longer
support spinor/spinand.

Updated config files the same in this patch.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2025-01-08 17:54:14 -05:00
Chen Wang b774c9b938 bsp: cvitek: use ioremap for arm64 core
For ARM, RT-smart and RT-standard both enable mmc (see
rt_hw_board_init() in bsp/cvitek/cv18xx_aarch64/board/board.c,
rt_hw_mmu_setup is called both for smart or standard).

So ioremap is must to do for ARM.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-12-30 11:32:10 +08:00
Chen Wang 6a7e797712 bsp: cvitek: remove GPL license declaration
GPL is conflict with Apache, which is used by RTT.

See <https://www.apache.org/licenses/GPL-compatibility.html>

Also clean up and remove some words such "LINUX".

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-12-19 22:39:47 +08:00
Chen Wang 16475b3c92 bsp: cvitek: fix warning on rtc driver
When RTC is enabled, a warning appear during compiling:
warning: implicit declaration of function 'rtc_alarm_enable' [-Wimplicit-function-declaration]
  366 |     rtc_alarm_enable(alarm->enable);
      |     ^~~~~~~~~~~~~~~~

It's due to _rtc_set_alarm is not covered by RT_USING_ALARM. It's wrong.

Solution: cover all functions including _rtc_get_alarm & _rtc_set_alarm
under RT_USING_ALARM macro conditional defintion.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-11-26 21:45:00 -05:00
Chen Wang 032fe9c3a3 bsp: cvitek: support mount fat/ext rootfs for rt-smart
Support mount rootfs automaticly during booting up.
First try ext, then fat.

Plus some code cleanup, such as remove BSP_USING_ON_CHIP_FLASH_FS,
which is not defined and unused.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-11-26 21:45:00 -05:00
Chen Wang 1052f99537 bsp: cvitek: 906b: romfs -> diskfs
ROMFS is Read-Only Memory Filesystem. But ext4/fat are not read-only.

So renamed:
- mnt_romfs.c -> mnt_diskfs.c
- BSP_ROOTFS_TYPE_ROMFS -> BSP_ROOTFS_TYPE_DISKFS

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-11-26 21:45:00 -05:00
flyingcys 8ed4ae144f support milkv-duo rt-smart
1. switches memory management to SLA

2. use ioremap modification driver

Signed-off-by: flyingcys flyingcys@163.com
2024-11-25 10:48:36 +08:00
Alex Imcu d141d148cf [bsp][cvitek] fix pinmux array order error (#9593) 2024-11-08 15:36:37 +08:00
imcu 633d203fa6 bsp:cvitek:add all function type of pinmux 2024-09-25 21:04:40 -04:00
CXSforHPU bb91502465 [drivers] Specifies the name of the drivers driver file
https://github.com/RT-Thread/rt-thread/pull/9420
2024-09-13 17:40:40 -04:00
Z8MAN8 cea7670e7f bsp: cvitek: fix cvitek uart driver can not repeat configure
After first called from uart open, the dw8250_uart_configure
API cannot be called again. Otherwise, this will mess up the
device, and uart will not act properly to interrupt again.

Analysis: Configure uart device will close recive interrupte,
causing uart device to malfunction.

Solution: After configure uart device, enable the device's
recive interrupte.

Signed-off-by: Shicheng Chu <1468559561@qq.com>
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
2024-09-03 20:50:50 -04:00
flyingcys 2e224b30ad [bsp/cvitek] eth driver support phy link detect
Signed-off-by: flyingcys <flyingcys@163.com>
2024-09-03 18:17:30 -04:00
heyuanjie87 b3fbddda80 [bsp/cvitek]修正sdhci发送命令超时后触发两次信号量的问题
修正命令超时后触发两次信号量的问题

详解:
中断状态寄存器的BIT0仅表示sdhci处理命令完成,完成结果由其它位指示,当出错时
BIT0也会值1产生中断

Signed-off-by: heyuanjie87 <943313837@qq.com>
2024-08-28 18:33:50 -04:00
Shicheng Chu 66738d71da bsp: cvitek: Add support for duos_sd
Supports both big and little cores of RISC-V C906,
but does not support ARM cores. Currently, only UART
drivers are supported on the peripherals.

Signed-off-by: Shicheng Chu <1468559561@qq.com>
2024-08-27 00:53:15 -04:00
Z8MAN8 742dae7220 bsp: cvitek: Add timer driver
Signed-off-by: Shicheng Chu <1468559561@qq.com>
2024-08-25 12:11:57 -04:00
Z8MAN8 f5156774b2 bsp: cvitek: Canonically rename some macro definitions
Analysis: Some macro definition names are not standardized
and lack prefixes.

Solution: Add BSP_ prefix to GPIO_IRQ_BASE SYS_GPIO_IRQ_BASE
PLIC_PHY_ADDR TIMER_CLK_FREQ UART_IRQ_BASE I2C_IRQ_BASE.

Signed-off-by: Shicheng Chu <1468559561@qq.com>
2024-08-20 09:52:18 +08:00
Z8MAN8 dc95efe17c bsp: cvitek: add support for RTCSYS_SARADC
Cvitek adc dirver only supports one adc controller now,
but the other adc controller RTCSYS_SARADC is missing.

Signed-off-by: Shicheng Chu <1468559561@qq.com>
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
2024-08-07 11:15:37 +08:00
Shell cfa3ecfa9e bsp: cvitek/c906B: feat: add config of bootfs
To support more choice on bootfs. romfs, cromfs are now supported on
risc_v_big platform.

Changes:
- added mount operations under port
- added prototypes for cromfs init APIs

Signed-off-by: Shell <smokewood@qq.com>
Reviewed-on: https://github.com/RT-Thread/rt-thread/pull/9229
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
2024-07-29 20:16:54 +08:00
heyuanjie87 5b82841748 [feat]添加ioremap兼容定义以适应smart运行 2024-07-24 12:28:50 +08:00
Z8MAN8 2a3bb2bf95 [bsp][cvitek]: 将adc wdt驱动的局部函数移至源文件 2024-07-21 17:37:09 +08:00
Chen Wang 7c1d205a4e bsp: cvitek: switch to device init function for some drivers
Some drivers use INIT_BOARD_EXPORT, it is not necessary,
it is enough to use INIT_DEVICE_EXPORT for genearl drivers.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-07-18 21:35:35 +08:00
Bernard Xiong a974cde8f9 Merge pull request #9201 from unicornx/dev-wdt-bugfix
bsp: cvitek:  accuulated bugfixes for wdt driver
2024-07-17 22:26:05 +08:00
Bernard Xiong a2f4e120c3 Merge pull request #9200 from unicornx/dev-spi-new
bsp: cvitek: re-wrote spi driver
2024-07-17 22:25:26 +08:00
Chen Wang 1bcf232d12 bsp: cvitek: fix the wdt timeout unit problem
See `components/drivers/include/drivers/watchdog.h`

maco definition of
RT_DEVICE_CTRL_WDT_GET_TIMEOUT
RT_DEVICE_CTRL_WDT_SET_TIMEOUT
RT_DEVICE_CTRL_WDT_GET_TIMELEFT

The wdt timeout time unit is defined as seconds in the API, but
the code incorrectly uses ms.

Correct this and comply with the API definition.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Reviewed-by: Yuanjie He <943313837@qq.com>
Reviewed-by: Shell <smokewood@qq.com>
2024-07-17 16:56:07 +08:00
flyingcys 1ef2afbc93 bsp: cvitek: re-wrote spi driver
Rewrote the spi driver.

Reuse the driver code from https://github.com/sophgo/cvi_alios_open,
which is Apache 2.0 licenced.

Signed-off-by: flyingcys <flyingcys@163.com>
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
2024-07-17 11:52:27 +08:00
Chen Wang 2d5eb2669f bsp: cvitek: remove warning when building wdt driver
```
./bsp/cvitek/drivers/drv_wdt.c: In function '_wdt_control':
warning: assignment to 'void *' from 'unsigned int' makes pointer
from integer without a cast [-Wint-conversion]
  119 |         wdt_device->parent.user_data = (rt_uint32_t)(*(rt_uint32_t *)arg);
      |                                      ^
warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
  122 |         *(rt_uint32_t *)arg = (rt_uint32_t)wdt_device->parent.user_data;
      |                               ^
```

Rootcasue: It's not portable to store integar in a pointer.

Solution: use global _wdt_dev to store the timeout value.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-07-17 09:05:26 +08:00
flyingcys dda79ad6bc bsp: cvitek: re-wrote i2c driver
Optimize the original i2c driver code.

Signed-off-by: flyingcys <flyingcys@163.com>
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
2024-07-17 08:19:03 +08:00
Chen Wang d8294de640 bsp:cvitek: add pinmux for adc
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-07-16 18:29:17 +08:00
Chen Wang 2c85bcb463 bsp:cvitek: add pinmux for spi
Board level pin available info:

duo & duo256:

NAME    SPI         CV1800B/GPIO    <PINNAME>__<FUNCNAME>
----    ---         ------------    ---------------------
GP6     SPI2_SCK    PWR_GPIO[23]    SD1_CLK__SPI2_SCK
GP7     SPI2_SDO    PWR_GPIO[22]    SD1_CMD__SPI2_SDO
GP8     SPI2_SDI    PWR_GPIO[21]    SD1_D0__SPI2_SDI
GP9     SPI2_CS_X   PWR_GPIO[18]    SD1_D3__SPI2_CS_X

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-07-16 18:29:17 +08:00
Chen Wang 51825a5b5c bsp:cvitek: add pinmux for pwm
Board level pin available info is summarized and list here for memo:

Duo:

NAME    PWM         CV1800B/GPIO    <PINNAME>__<FUNCNAME>
----    ---         ------------    ---------------------
PWM-1
GP9     PWM4        PWR_GPIO[18]    SD1_D3__PWM_4
GP12    PWM4        XGPIOA[16]      UART0_TX__PWM_4

GP4     PWM5        PWR_GPIO[19]    SD1_D2__PWM_5
GP13    PWM5        XGPIOA[17]      UART0_RX__PWM_5

GP5     PWM6        PWR_GPIO[20]    SD1_D1__PWM_6

GP8     PMW7        PWR_GPIO[21]    SD1_D0__PWM_7

PWM-2
GP7     PWM8        PWR_GPIO[22]    SD1_CMD__PWM_8
GP6     PWM9        PWR_GPIO[23]    SD1_CLK__PWM_9
GP2     PWM10       PWR_GPIO[26]    SD1_GPIO1__PWM_10
GP3     PWM11       PWR_GPIO[25]    SD1_GPIO0__PWM_11

Duo256:

NAME    PWM         CV1800B/GPIO    <PINNAME>__<FUNCNAME>
----    ---         ------------    ---------------------
PWM-1
GP9     PWM4        PWR_GPIO[18]    SD1_D3__PWM_4
GP12    PWM4        XGPIOA[16]      UART0_TX__PWM_4

GP4     PWM5        PWR_GPIO[19]    SD1_D2__PWM_5
GP13    PWM5        XGPIOA[17]      UART0_RX__PWM_5

GP3     PWM6        XGPIOA[18]      JTAG_CPU_TCK__PWM_6
GP5     PWM6        PWR_GPIO[20]    SD1_D1__PWM_6

GP2     PWM7        XGPIOA[19]      JTAG_CPU_TMS__PWM_7
GP8     PMW7        PWR_GPIO[21]    SD1_D0__PWM_7

PWM-2
GP7     PWM8        PWR_GPIO[22]    SD1_CMD__PWM_8
GP6     PWM9        PWR_GPIO[23]    SD1_CLK__PWM_9
GP10    PWM10       XGPIOC[14]      PAD_MIPI_TXM1__PWM_10
GP11    PWM11       XGPIOC[15]      PAD_MIPI_TXP1__PWM_11

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-07-16 18:29:17 +08:00
Chen Wang 114e143d56 bsp:cvitek: add pinmux for uart
Board level UART pinmux summary, following capability
should be controlled by pinname whitelist.

Duo:

NAME    UART        CV1800B/GPIO    <PINNAME>__<FUNCNAME>
----    ---         ------------    ---------------------
GP13    UART0_RX    XGPIOA[17]      UART0_RX__UART0_RX
GP12    UART0_TX    XGPIOA[16]      UART0_TX__UART0_TX

GP1     UART1_RX    XGPIOA[29]      IIC0_SDA__UART1_RX
GP13    UART1_RX    XGPIOA[17]      UART0_RX__UART1_RX
GP0     UART1_TX    XGPIOA[28]      IIC0_SCL__UART1_TX
GP12    UART1_TX    XGPIOA[16]      UART0_TX__UART1_TX

GP1     UART2_RX    XGPIOA[29]      IIC0_SDA__UART2_RX
GP5     UART2_RX    PWR_GPIO[20]    SD1_D1__UART2_RX
GP0     UART2_TX    XGPIOA[28]      IIC0_SCL__UART2_TX
GP4     UART2_TX    PWR_GPIO[19]    SD1_D2__UART2_TX

GP5     UART3_RX    PWR_GPIO[20]    SD1_D1__UART3_RX
GP4     UART3_TX    PWR_GPIO[19]    SD1_D2__UART3_TX

GP3     UART4_RX    PWR_GPIO[25]    SD1_GPIO0__UART4_RX
GP2     UART4_TX    PWR_GPIO[26]    SD1_GPIO1__UART4_TX

Duo 256m:

NAME    UART        CV1800B/GPIO    <PINNAME>__<FUNCNAME>
----    ---         ------------    ---------------------
GP13    UART0_RX    XGPIOA[17]      UART0_RX__UART0_RX
GP12    UART0_TX    XGPIOA[16]      UART0_TX__UART0_TX

GP1     UART1_RX    XGPIOA[29]      IIC0_SDA__UART1_RX
GP3     UART1_RX    XGPIOA[18]      JTAG_CPU_TCK__UART1_RX
GP13    UART1_RX    XGPIOA[17]      UART0_RX__UART1_RX
GP0     UART1_TX    XGPIOA[28]      IIC0_SCL__UART1_TX
GP2     UART1_TX    XGPIOA[19]      JTAG_CPU_TMS__UART1_TX
GP12    UART1_TX    XGPIOA[16]      UART0_TX__UART1_TX

GP1     UART2_RX    XGPIOA[29]      IIC0_SDA__UART2_RX
GP5     UART2_RX    PWR_GPIO[20]    SD1_D1__UART2_RX
GP0     UART2_TX    XGPIOA[28]      IIC0_SCL__UART2_TX
GP4     UART2_TX    PWR_GPIO[19]    SD1_D2__UART2_TX

GP5     UART3_RX    PWR_GPIO[20]    SD1_D1__UART3_RX
GP4     UART3_TX    PWR_GPIO[19]    SD1_D2__UART3_TX

Note: this patch also update the .config and rtconfig.h
because this patch modify some configuration items's name,
for example: RT_USIMG_UART0 -> BSP_USING_UART0.

FIXME: only handle RISC-V related, no ARM.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-07-16 18:29:17 +08:00
Chen Wang e1eb3d3217 bsp:cvitek: add pinmux for i2c
Based on new pinmux framework, add configuration for uart.

Board level pin available info is summarized and should be
controlled by pin whitelist.

Duo

NAME    I2C         CV1800B/GPIO    <PINNAME>__<FUNCNAME>
----    ---         ------------    ---------------------
GP0     I2C0_SCL    XGPIOA[28]      IIC0_SCL__IIC0_SCL
GP1     I2C0_SDA    XGPIOA[29]      IIC0_SDA__IIC0_SDA

GP4     I2C1_SCL    PWR_GPIO[19]    SD1_D2__IIC1_SCL
GP9     I2C1_SCL    PWR_GPIO[18]    SD1_D3__IIC1_SCL
GP11    I2C1_SCL    XGPIOC[10]      PAD_MIPIRX0N__IIC1_SCL
GP5     I2C1_SDA    PWR_GPIO[20]    SD1_D1__IIC1_SDA
GP8     I2C1_SDA    PWR_GPIO[21]    SD1_D0__IIC1_SDA
GP10    I2C1_SDA    XGPIOC[9]       PAD_MIPIRX1P__IIC1_SDA

GP7     I2C3_SCL    PWR_GPIO[22]    SD1_CMD__IIC3_SCL
GP6     I2C3_SDA    PWR_GPIO[23]    SD1_CLK__IIC3_SDA

Duo256m

NAME    I2C         CV1800B/GPIO    <PINNAME>__<FUNCNAME>
----    ---         ------------    ---------------------
GP4     I2C1_SCL    PWR_GPIO[19]    SD1_D2__IIC1_SCL
GP9     I2C1_SCL    PWR_GPIO[18]    SD1_D3__IIC1_SCL
GP5     I2C1_SDA    PWR_GPIO[20]    SD1_D1__IIC1_SDA
GP8     I2C1_SDA    PWR_GPIO[21]    SD1_D0__IIC1_SDA

GP11    I2C2_SCL    XGPIOC[15]      PAD_MIPI_TXP1__IIC2_SCL
GP10    I2C2_SDA    XGPIOC[14]      PAD_MIPI_TXM1__IIC2_SDA

GP7     I2C3_SCL    PWR_GPIO[22]    SD1_CMD__IIC3_SCL
GP6     I2C3_SDA    PWR_GPIO[23]    SD1_CLK__IIC3_SDA

Duo S(Note, we have not supported duo S, just list for memo)

NAME    I2C         CV1800B/GPIO    <PINNAME>__<FUNCNAME>
----    ---         ------------    ---------------------

J3-B18  I2C1_SCL    XGPIOB[18]      VIVO_D3__IIC1_SCL
J3-B12  I2C1_SCL    XGPIOB[12]      VIVO_D9__IIC1_SCL
J3-B11  I2C1_SDA    XGPIOB[11]      VIVO_D10__IIC1_SDA

J3-B13  I2C2_SCL    XGPIOB[13]      VIVO_D8__IIC2_SCL
J4-E1   I2C2_SCL    PWR_GPIO[1]     PWR_GPIO1__IIC2_SCL
J3-B14  I2C2_SDA    XGPIOB[14]      VIVO_D7__IIC2_SDA
J4-E2   I2C2_SDA    PWR_GPIO[2]     PWR_GPIO2__IIC2_SDA

J3-B20  I2C4_SCL    XGPIOB[20]      VIVO_D1__IIC4_SCL
J4-B1   I2C4_SCL    XGPIOB[1]       ADC3__IIC4_SCL
J3-B21  I2C4_SDA    XGPIOB[21]      VIVO_D0__IIC4_SDA
J4-B2   I2C4_SDA    XGPIOB[2]       ADC2__IIC4_SDA

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-07-16 18:29:17 +08:00
Chen Wang d8d0af9143 bsp:cvitek: add calibration for adc
The ADC controller needs to be calibrated during the initialization
phase, otherwise the measured voltage value will be inaccurate.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-07-16 11:47:22 +08:00
Chen Wang a63c07fd75 bsp: cvitek: new design for pinmux
In the new design, we require the user to manually enter the
PinName (as a string) in menuconfig instead of being given
menu items to select.

The original method will lead to too many menu item-related
macros being defined in the code, causing ifdef and other
codes scatter everywhere in the driver code, which is
inconvenient to maintain.

The new design adds a pinmux driver module to manage the
multiplexing of pins. This patch provides this driver module.

P.S., the reason why users are allowed to specify pinname
in a string instead of the pin number is mainly because
the technical manual provided by the SOC manufacturer
does not have numbers for some pins, only names.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Reviewed-by: Yuanjie He <943313837@qq.com>
Reviewed-by: Shell <smokewood@qq.com>
2024-07-16 11:37:23 +08:00
Chen Wang 80668e0ba2 bsp:cvitek: revert add i2c pinmux config for c906
The contents of the SOC type part in the Kconfig configuration
are retained, and other parts related to I2C pin multiplexing
selection have been rolled back.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Reviewed-by: Yuanjie He <943313837@qq.com>
Reviewed-by: Shell <smokewood@qq.com>
2024-07-16 11:37:23 +08:00
heyuanjie87 6180dabab3 [bsp/cvitek]将eth驱动中地址类型改为指针以适应ioremap (#9137)
ioremap后地址可能超32位
2024-07-11 10:28:02 +08:00
heyuanjie87 776764c4d6 [bsp/cvitek/eth]解决编译警告 2024-07-04 00:33:32 +08:00
heyuanjie87 017c31a062 [bsp/cvitek]解决eth编译报错 2024-07-02 22:54:58 +08:00
Z8MAN8 071b3d9244 [bsp]: fix bugs of cvitek and pico drivers 2024-06-26 20:28:29 +08:00
flyingcys 09a0e4c5f8 update gpio driver 2024-05-27 11:26:09 +08:00
Chen Wangandflyingcys 5dd3b7427a Accumulated patchsets for bsp/cvitek (#8968)
* bsp: cvitek: kconfig: add wdt for cv18xx_riscv

Add Watchdog timer in Kconfig.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>

* drv: cvitek: remove using macro from source file

Building of source file should be controlled by SConscript,
but not in source file itself.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>

* bsp: cvitek: kconfig: add i2c for cv18xx_riscv

Add I2C in Kconfig for c906B.

Note, the IRQ# is different from that of c906L.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>

* bsp: cvitek: kconfig: add rtc for cv18xx_riscv

Add RTC in Kconfig for c906B.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>

* bsp: cvitek: fix channel issue for pwm driver

The original code confuses the concepts of controllers and channels.
Fixed it and do some code cleanup.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>

* bsp:cvitek: add i2c pinmux config for cv18xx_riscv

Pinmux in driver code is controlled by SOC type, bcos driver
code should be general and support all pins defined by SoC.

Pinmux configuration in Kconfig is controlled by BOARD type,
bcos when we operate on board, it does not expose all chip-level
pin signals and we can only use part of them.

Following is I2C signals exported by duo family. Details see
https://milkv.io/docs/duo/overview.

Note: we have not added support for duo-S.

Duo
===

NAME    I2C         CV1800B/GPIO    <PINNAME>__<FUNCNAME>
----    ---         ------------    ---------------------
GP0     I2C0_SCL    XGPIOA[28]      IIC0_SCL__IIC0_SCL
GP1     I2C0_SDA    XGPIOA[29]      IIC0_SDA__IIC0_SDA

GP4     I2C1_SCL    PWR_GPIO[19]    SD1_D2__IIC1_SCL
GP9     I2C1_SCL    PWR_GPIO[18]    SD1_D3__IIC1_SCL
GP11    I2C1_SCL    XGPIOC[10]      PAD_MIPIRX0N__IIC1_SCL
GP5     I2C1_SDA    PWR_GPIO[20]    SD1_D1__IIC1_SDA
GP8     I2C1_SDA    PWR_GPIO[21]    SD1_D0__IIC1_SDA
GP10    I2C1_SDA    XGPIOC[9]       PAD_MIPIRX1P__IIC1_SDA

GP7     I2C3_SCL    PWR_GPIO[22]    SD1_CMD__IIC3_SCL
GP6     I2C3_SDA    PWR_GPIO[23]    SD1_CLK__IIC3_SDA

Duo 256m
========

NAME    I2C         CV1800B/GPIO    <PINNAME>__<FUNCNAME>
----    ---         ------------    ---------------------
GP4     I2C1_SCL    PWR_GPIO[19]    SD1_D2__IIC1_SCL
GP9     I2C1_SCL    PWR_GPIO[18]    SD1_D3__IIC1_SCL
GP5     I2C1_SDA    PWR_GPIO[20]    SD1_D1__IIC1_SDA
GP8     I2C1_SDA    PWR_GPIO[21]    SD1_D0__IIC1_SDA

GP11    I2C2_SCL    XGPIOC[15]      PAD_MIPI_TXP1__IIC2_SCL
GP10    I2C2_SDA    XGPIOC[14]      PAD_MIPI_TXM1__IIC2_SDA

GP7     I2C3_SCL    PWR_GPIO[22]    SD1_CMD__IIC3_SCL
GP6     I2C3_SDA    PWR_GPIO[23]    SD1_CLK__IIC3_SDA

Duo S
=====

NAME    I2C         CV1800B/GPIO    <PINNAME>__<FUNCNAME>
----    ---         ------------    ---------------------

J3-B18  I2C1_SCL    XGPIOB[18]      VIVO_D3__IIC1_SCL
J3-B12  I2C1_SCL    XGPIOB[12]      VIVO_D9__IIC1_SCL
J3-B11  I2C1_SDA    XGPIOB[11]      VIVO_D10__IIC1_SDA

J3-B13  I2C2_SCL    XGPIOB[13]      VIVO_D8__IIC2_SCL
J4-E1   I2C2_SCL    PWR_GPIO[1]     PWR_GPIO1__IIC2_SCL
J3-B14  I2C2_SDA    XGPIOB[14]      VIVO_D7__IIC2_SDA
J4-E2   I2C2_SDA    PWR_GPIO[2]     PWR_GPIO2__IIC2_SDA

J3-B20  I2C4_SCL    XGPIOB[20]      VIVO_D1__IIC4_SCL
J4-B1   I2C4_SCL    XGPIOB[1]       ADC3__IIC4_SCL
J3-B21  I2C4_SDA    XGPIOB[21]      VIVO_D0__IIC4_SDA
J4-B2   I2C4_SDA    XGPIOB[2]       ADC2__IIC4_SDA

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: flyingcys <flyingcys@163.com>

* bsp:cvitek: remove using macro from source file for i2c

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>

* bsp:cvitek: unify menu message text for i2c as other drivers

Other dirvers has no extra word "HW".

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>

* bsp:cvitek: add i2c pinmux config for c906_little

Porting what we have done in commit "bsp:cvitek: add i2c pinmux config
for cv18xx_riscv" to c906_little.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>

---------

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: flyingcys <flyingcys@163.com>
Co-authored-by: flyingcys <flyingcys@163.com>
2024-05-22 08:19:07 +08:00
flyingcys ec8ff90a4a [bsp/cvitek]update gpio driver (#8946)
update gpio driver
2024-05-13 18:20:57 -04:00
flyingcys 7890e2cb14 [bsp/cvitek]add eth driver 2024-04-29 17:47:50 -04:00
flyingcys aee6048a53 [bsp/cvitek]update cvitek sdhci drvier (#8874)
update cvitek sdhci drvier
2024-04-28 23:07:42 +08:00