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Merge remote-tracking branch 'upstream/master'

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XYX12306
2020-05-15 19:52:14 +08:00
parent 572df0f5bf 4ef35a9dee
commit fe2122d076
151 changed files with 16415 additions and 1319 deletions
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.travis.yml
+1
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@@ -109,6 +109,7 @@ env:
- RTT_BSP='stm32/stm32l4r9-st-eval' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32l010-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32l053-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32l412-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32l432-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32l475-atk-pandora' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32l475-st-discovery' RTT_TOOL_CHAIN='sourcery-arm'
bsp/lpc54608-LPCXpresso/project.ewp
+4 -4
View File
@@ -2148,16 +2148,16 @@
<group>
<name>CPlusPlus</name>
<file>
<name>$PROJ_DIR$\../../components/cplusplus/Mutex.cpp</name>
<name>$PROJ_DIR$\../../components/cplusplus/cxx_Mutex.cpp</name>
</file>
<file>
<name>$PROJ_DIR$\../../components/cplusplus/Semaphore.cpp</name>
<name>$PROJ_DIR$\../../components/cplusplus/cxx_Semaphore.cpp</name>
</file>
<file>
<name>$PROJ_DIR$\../../components/cplusplus/Thread.cpp</name>
<name>$PROJ_DIR$\../../components/cplusplus/cxx_Thread.cpp</name>
</file>
<file>
<name>$PROJ_DIR$\../../components/cplusplus/crt.cpp</name>
<name>$PROJ_DIR$\../../components/cplusplus/cxx_crt.cpp</name>
</file>
<file>
<name>$PROJ_DIR$\../../components/cplusplus/crt_init.c</name>
bsp/lpc54608-LPCXpresso/project.ewt
+4 -4
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@@ -2355,19 +2355,19 @@
<group>
<name>CPlusPlus</name>
<file>
<name>$PROJ_DIR$\..\..\components\cplusplus\crt.cpp</name>
<name>$PROJ_DIR$\..\..\components\cplusplus\cxx_crt.cpp</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\components\cplusplus\crt_init.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\components\cplusplus\Mutex.cpp</name>
<name>$PROJ_DIR$\..\..\components\cplusplus\cxx_Mutex.cpp</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\components\cplusplus\Semaphore.cpp</name>
<name>$PROJ_DIR$\..\..\components\cplusplus\cxx_Semaphore.cpp</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\components\cplusplus\Thread.cpp</name>
<name>$PROJ_DIR$\..\..\components\cplusplus\cxx_Thread.cpp</name>
</file>
</group>
<group>
bsp/lpc54608-LPCXpresso/project.uvprojx
+868 -875
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File diff suppressed because it is too large Load Diff
bsp/lpc55sxx/tools/sdk_dist.py
+1 -1
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@@ -8,7 +8,7 @@ sys.path.append(os.path.join(os.path.dirname(cwd_path), 'rt-thread', 'tools'))
def dist_do_building(BSP_ROOT):
from mkdist import bsp_copy_files
import rtconfig
dist_dir = os.path.join(BSP_ROOT, 'dist', os.path.basename(BSP_ROOT))
library_path = os.path.join(os.path.dirname(BSP_ROOT), 'Libraries')
library_dir = os.path.join(dist_dir, 'Libraries')
bsp/nrf5x/libraries/drivers/SConscript
+5 -1
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@@ -10,8 +10,12 @@ src = Split("""
if GetDepend(['BSP_USING_UART']):
src += ['drv_uart.c']
if GetDepend(['BSP_USING_ON_CHIP_FLASH']):
src += ['drv_flash.c']
# src += ['drv_common.c']
if GetDepend(['BSP_USING_QSPI_FLASH']):
src += ['drv_qspi_flash.c']
path = [cwd]
bsp/nrf5x/libraries/drivers/drv_flash.c
+188
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@@ -0,0 +1,188 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-04-29 supperthomas first version
*/
#include "board.h"
#include <nrfx.h>
#include "nrfx_nvmc.h"
#ifdef BSP_USING_ON_CHIP_FLASH
#if defined(PKG_USING_FAL)
#include "fal.h"
#endif
#include <rtdbg.h>
#define LOG_TAG "drv.flash"
/**
* @brief Gets the page of a given address
* @param Addr: Address of the FLASH Memory
* @retval The page of a given address
*/
static uint32_t GetPage(uint32_t Addr)
{
uint32_t page = 0;
if (Addr < (MCU_FLASH_START_ADDRESS + MCU_FLASH_SIZE))
{
page = (Addr - MCU_FLASH_START_ADDRESS) / MCU_FLASH_PAGE_SIZE;
}
else
{
return 0xffffffff;
}
return page;
}
/**
* Read data from flash.
* @note This operation's units is word.
*
* @param addr flash address
* @param buf buffer to store read data
* @param size read bytes size
*
* @return result
*/
int mcu_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size)
{
size_t i;
if ((addr + size) > MCU_FLASH_END_ADDRESS)
{
LOG_E("read outrange flash size! addr is (0x%p)", (void *)(addr + size));
return -RT_EINVAL;
}
for (i = 0; i < size; i++, buf++, addr++)
{
*buf = *(rt_uint8_t *) addr;
}
return size;
}
/**
* Write data to flash.
* @note This operation's units is word.
* @note This operation must after erase. @see flash_erase.
*
* @param addr flash address
* @param buf the write data buffer
* @param size write bytes size
*
* @return result
*/
int mcu_flash_write(rt_uint32_t addr, const uint8_t *buf, size_t size)
{
if ((addr + size) > MCU_FLASH_END_ADDRESS)
{
LOG_E("ERROR: write outrange flash size! addr is (0x%p)\n", (void *)(addr + size));
return -RT_EINVAL;
}
if (addr % 4 != 0)
{
LOG_E("write addr should be 4-byte alignment");
//4byte write
//else byts
return -RT_EINVAL;
}
if (size < 1)
{
return -RT_ERROR;
}
if (size % 4 != 0)
{
nrfx_nvmc_bytes_write(addr, buf, size);
return size;
}
else
{
nrfx_nvmc_words_write(addr, buf, size / 4);
return size;
}
}
/**
* Erase data on flash.
* @note This operation is irreversible.
* @note This operation's units is different which on many chips.
*
* @param addr flash address
* @param size erase bytes size
*
* @return result
*/
int mcu_flash_erase(rt_uint32_t addr, size_t size)
{
nrfx_err_t result = RT_EOK;
uint32_t FirstPage = 0, NbOfPages = 0;
if ((addr + size) > MCU_FLASH_END_ADDRESS)
{
LOG_E("ERROR: erase outrange flash size! addr is (0x%p)\n", (void *)(addr + size));
return -RT_EINVAL;
}
FirstPage = GetPage(addr);
NbOfPages = GetPage(addr + size - 1) - FirstPage + 1;
for (int i = 0; i < NbOfPages ; i++)
{
result = nrfx_nvmc_page_erase((FirstPage + i) * MCU_FLASH_PAGE_SIZE);
if (NRFX_SUCCESS != result)
{
LOG_E("ERROR: erase flash page %d ! error code is (%x)\n", FirstPage + i, result);
return -RT_EINVAL;
}
}
LOG_D("erase done: addr (0x%p), size %d", (void *)addr, NbOfPages * MCU_FLASH_PAGE_SIZE);
return size;
}
#if defined(PKG_USING_FAL)
static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size);
static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size);
static int fal_flash_erase(long offset, size_t size);
static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size)
{
return mcu_flash_read(mcu_onchip_flash.addr + offset, buf, size);
}
static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size)
{
return mcu_flash_write(mcu_onchip_flash.addr + offset, buf, size);
}
static int fal_flash_erase(long offset, size_t size)
{
return mcu_flash_erase(mcu_onchip_flash.addr + offset, size);
}
const struct fal_flash_dev mcu_onchip_flash =
{
.name = ON_CHIP_FLASH_DEV_NAME,
.addr = MCU_FLASH_START_ADDRESS,
.len = MCU_FLASH_SIZE,
.blk_size = MCU_FLASH_PAGE_SIZE,
.ops = {NULL, fal_flash_read, fal_flash_write, fal_flash_erase},
.write_gran = 8
};
#endif
#endif /* BSP_USING_ON_CHIP_FLASH */
bsp/nrf5x/libraries/drivers/drv_qspi_flash.c
+153
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@@ -0,0 +1,153 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-04-29 supperthomas first version
*
*/
#include <stdint.h>
#include "board.h"
#include "nrfx_qspi.h"
#if defined(PKG_USING_FAL)
#include <fal.h>
//log
#include <rtdbg.h>
#define LOG_TAG "drv.qspiflash"
#define WAIT_FOR_PERIPH() do { \
while (!m_finished) {} \
m_finished = false; \
} while (0)
static volatile bool m_finished = false;
static void qspi_handler(nrfx_qspi_evt_t event, void *p_context)
{
m_finished = true;
}
static void configure_memory()
{
#define QSPI_STD_CMD_WRSR 0x01
#define QSPI_STD_CMD_RSTEN 0x66
#define QSPI_STD_CMD_RST 0x99
uint8_t temporary = 0x40;
uint32_t err_code;
nrf_qspi_cinstr_conf_t cinstr_cfg =
{
.opcode = QSPI_STD_CMD_RSTEN,
.length = NRF_QSPI_CINSTR_LEN_1B,
.io2_level = true,
.io3_level = true,
.wipwait = true,
.wren = true
};
// Send reset enable
err_code = nrfx_qspi_cinstr_xfer(&cinstr_cfg, NULL, NULL);
if (NRFX_SUCCESS != err_code)
{
LOG_E("\r\n ERROR: QSPI_STD_CMD_RSTEN:0x%x\n", err_code);
return ;
}
// Send reset command
cinstr_cfg.opcode = QSPI_STD_CMD_RST;
err_code = nrfx_qspi_cinstr_xfer(&cinstr_cfg, NULL, NULL);
if (NRFX_SUCCESS != err_code)
{
LOG_E("\r\n ERROR: QSPI_STD_CMD_RST:0x%x\n", err_code);
return ;
}
// Switch to qspi mode
cinstr_cfg.opcode = QSPI_STD_CMD_WRSR;
cinstr_cfg.length = NRF_QSPI_CINSTR_LEN_2B;
err_code = nrfx_qspi_cinstr_xfer(&cinstr_cfg, &temporary, NULL);
if (NRFX_SUCCESS != err_code)
{
LOG_E("\r\n ERROR: QSPI_STD_CMD_WRSR:0x%x\n", err_code);
return;
}
}
static int init(void)
{
uint32_t err_code;
nrfx_qspi_config_t config = NRFX_QSPI_DEFAULT_CONFIG(BSP_QSPI_SCK_PIN, BSP_QSPI_CSN_PIN,
BSP_QSPI_IO0_PIN, BSP_QSPI_IO1_PIN, BSP_QSPI_IO2_PIN, BSP_QSPI_IO3_PIN);
err_code = nrfx_qspi_init(&config, qspi_handler, NULL);
if (NRFX_SUCCESS != err_code)
{
LOG_E("\r\n ERROR: QSPI_init:0x%x\n", err_code);
return -1;
}
configure_memory();
return 0;
}
static int read(long offset, uint8_t *buf, size_t size)
{
uint32_t err_code;
m_finished = false;
err_code = nrfx_qspi_read(buf, size, offset);
WAIT_FOR_PERIPH();
if (NRFX_SUCCESS == err_code)
{
return size;
}
else
{
LOG_E("\r\n ERROR: read:0x%x\n", err_code);
return -1;
}
}
static int write(long offset, const uint8_t *buf, size_t size)
{
uint32_t err_code;
m_finished = false;
err_code = nrfx_qspi_write(buf, size, offset);
WAIT_FOR_PERIPH();
if (NRFX_SUCCESS == err_code)
{
return size;
}
else
{
LOG_E("\r\n ERROR: write:0x%x\n", err_code);
return -1;
}
}
static int erase(long offset, size_t size)
{
uint32_t err_code;
m_finished = false;
err_code = nrfx_qspi_erase(NRF_QSPI_ERASE_LEN_64KB, offset);
WAIT_FOR_PERIPH();
if (NRFX_SUCCESS == err_code)
{
return size;
}
else
{
LOG_E("\r\n ERROR: erase:0x%x\n", err_code);
return -1;
}
}
struct fal_flash_dev nor_flash0 =
{
.name = NOR_FLASH_DEV_NAME,
.addr = 0,
.len = QSPI_FLASH_SIZE_KB * 1024,
.blk_size = 4096,
.ops = {init, read, write, erase},
.write_gran = 1
};
#endif
bsp/nrf5x/libraries/drivers/drv_uart.c
+73 -56
View File
@@ -1,59 +1,83 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-04-28 xckhmf Modify for <nrfx>
*
*/
#include <rtdevice.h>
#include <nrfx_uart.h>
#include "drv_uart.h"
static struct rt_serial_device _serial0_0;
static void uart_event_hander(nrfx_uart_event_t const *p_event,void *p_context);
#ifdef BSP_USING_UART
typedef struct
{
struct rt_serial_device *serial;
nrfx_uart_t uart;
uint8_t rx_byte;
uint16_t rx_length;
uint32_t rx_pin;
uint32_t tx_pin;
nrfx_uart_event_handler_t event_handler;
} UART_CFG_T;
} drv_uart_cfg_t;
UART_CFG_T uart0 = {
#ifdef BSP_USING_UART0
static struct rt_serial_device _serial_0;
static void uart0_event_hander(nrfx_uart_event_t const *p_event,void *p_context);
drv_uart_cfg_t m_uart0_cfg = {
.uart = NRFX_UART_INSTANCE(0),
#ifdef RT_USING_CONSOLE
.rx_pin = 8,
.tx_pin = 6,
.event_handler = uart_event_hander,
#else
.rx_pin = 19,
.tx_pin = 20
#endif
.rx_byte = 0,
.rx_length = 0,
.rx_pin = BSP_UART0_RX_PIN,
.tx_pin = BSP_UART0_TX_PIN,
.event_handler = uart0_event_hander
};
UART_CFG_T *working_cfg = RT_NULL;
#endif /* BSP_USING_UART0 */
static void uart_event_hander(nrfx_uart_event_t const *p_event,void *p_context)
{
#ifdef BSP_USING_UART1
#error <nrfx_uart> not support UART1. Use UART0 instead.
#endif /* BSP_USING_UART1 */
#ifdef BSP_USING_UART0
static void uart0_event_hander(nrfx_uart_event_t const *p_event,void *p_context)
{
if (p_event->type == NRFX_UART_EVT_RX_DONE)
{
rt_hw_serial_isr(working_cfg->serial, RT_SERIAL_EVENT_RX_IND);
if(p_event->data.rxtx.bytes == 1)
{
m_uart0_cfg.rx_length = p_event->data.rxtx.bytes;
/* rx_byte equal p_data */
//m_uart0_cfg.rx_byte = *(p_event->data.rxtx.p_data);
rt_hw_serial_isr(m_uart0_cfg.serial, RT_SERIAL_EVENT_RX_IND);
}
nrfx_uart_rx(&(m_uart0_cfg.uart),&m_uart0_cfg.rx_byte,1);
}
if (p_event->type == NRFX_UART_EVT_TX_DONE)
{
/* @TODO:[RT_DEVICE_FLAG_INT_TX]*/
}
}
#endif /* BSP_USING_UART0 */
static rt_err_t _uart_cfg(struct rt_serial_device *serial, struct serial_configure *cfg)
{
nrfx_uart_config_t config = NRFX_UART_DEFAULT_CONFIG(uart0.tx_pin,uart0.rx_pin);
UART_CFG_T *instance = &uart0;
nrfx_uart_config_t config = NRFX_UART_DEFAULT_CONFIG(BSP_UART0_TX_PIN,BSP_UART0_RX_PIN);
drv_uart_cfg_t *instance = RT_NULL;
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(cfg != RT_NULL);
if (serial->parent.user_data != RT_NULL)
if (serial->parent.user_data == RT_NULL)
{
instance = (UART_CFG_T*)serial->parent.user_data;
return -RT_ERROR;
}
instance = (drv_uart_cfg_t*)serial->parent.user_data;
nrfx_uart_uninit(&(instance->uart));
switch (cfg->baud_rate)
@@ -83,28 +107,23 @@ static rt_err_t _uart_cfg(struct rt_serial_device *serial, struct serial_configu
config.hal_cfg.hwfc = NRF_UART_HWFC_DISABLED;
config.pselrxd = instance->rx_pin;
config.pseltxd = instance->tx_pin;
nrfx_uart_init(&(instance->uart), &config, instance->event_handler);
nrf_uart_int_enable(instance->uart.p_reg, NRF_UART_INT_MASK_RXDRDY | NRF_UART_INT_MASK_RXTO | NRF_UART_INT_MASK_ERROR);
nrfx_uart_rx(&(instance->uart),&(instance->rx_byte),1);
nrf_uart_int_disable(instance->uart.p_reg, NRF_UART_INT_MASK_TXDRDY);
nrfx_uart_rx_enable(&(instance->uart));
working_cfg = instance;
return RT_EOK;
}
static rt_err_t _uart_ctrl(struct rt_serial_device *serial, int cmd, void *arg)
{
UART_CFG_T *instance = working_cfg;
drv_uart_cfg_t *instance = NULL;
RT_ASSERT(serial != RT_NULL);
if (serial->parent.user_data != RT_NULL)
if (serial->parent.user_data == RT_NULL)
{
instance = (UART_CFG_T*)serial->parent.user_data;
return -RT_ERROR;
}
instance = (drv_uart_cfg_t*)serial->parent.user_data;
switch (cmd)
{
@@ -129,10 +148,7 @@ static rt_err_t _uart_ctrl(struct rt_serial_device *serial, int cmd, void *arg)
break;
case RT_DEVICE_CTRL_PIN:
if (working_cfg != instance)
{
_uart_cfg(instance->serial, &(instance->serial->config));
}
_uart_cfg(instance->serial, &(instance->serial->config));
break;
case RT_DEVICE_POWERSAVE:
@@ -152,13 +168,13 @@ static rt_err_t _uart_ctrl(struct rt_serial_device *serial, int cmd, void *arg)
static int _uart_putc(struct rt_serial_device *serial, char c)
{
UART_CFG_T *instance = working_cfg;
drv_uart_cfg_t *instance = NULL;
int rtn = 1;
RT_ASSERT(serial != RT_NULL);
if (serial->parent.user_data != RT_NULL)
{
instance = (UART_CFG_T*)serial->parent.user_data;
instance = (drv_uart_cfg_t*)serial->parent.user_data;
}
nrf_uart_event_clear(instance->uart.p_reg, NRF_UART_EVENT_TXDRDY);
@@ -171,23 +187,21 @@ static int _uart_putc(struct rt_serial_device *serial, char c)
return rtn;
}
/*
@note: this function is invaild ,the cause of the problem is [nrfx_uart.c - line 340]
*/
static int _uart_getc(struct rt_serial_device *serial)
{
int ch = -1;
UART_CFG_T *instance = working_cfg;
drv_uart_cfg_t *instance = NULL;
RT_ASSERT(serial != RT_NULL);
if (serial->parent.user_data != RT_NULL)
{
instance = (UART_CFG_T*)serial->parent.user_data;
instance = (drv_uart_cfg_t*)serial->parent.user_data;
}
if(instance->rx_length)
{
ch = instance->rx_byte;
instance->rx_length--;
}
ch = (int)(nrf_uart_rxd_get(instance->uart.p_reg));
return ch;
}
@@ -202,11 +216,14 @@ void rt_hw_uart_init(void)
{
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
config.bufsz = RT_SERIAL_RB_BUFSZ;
_serial0_0.config = config;
_serial0_0.ops = &_uart_ops;
uart0.serial = &_serial0_0;
#ifdef BSP_USING_UART0
_serial_0.config = config;
_serial_0.ops = &_uart_ops;
m_uart0_cfg.serial = &_serial_0;
rt_hw_serial_register(&_serial_0, "uart0", \
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, &m_uart0_cfg);
#endif /* BSP_USING_UART0 */
rt_hw_serial_register(&_serial0_0, "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, &uart0);
}
#endif /* BSP_USING_UART */
bsp/nrf5x/nrf52840/.config
+15 -5
View File
@@ -200,6 +200,7 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_MYMQTT is not set
# CONFIG_PKG_USING_KAWAII_MQTT is not set
# CONFIG_PKG_USING_BC28_MQTT is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_JSMN is not set
@@ -226,6 +227,7 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_CMUX is not set
# CONFIG_PKG_USING_PPP_DEVICE is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
# CONFIG_PKG_USING_ATSRV_SOCKET is not set
@@ -302,6 +304,7 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
# CONFIG_PKG_USING_BS8116A is not set
# CONFIG_PKG_USING_URLENCODE is not set
#
# system packages
@@ -312,6 +315,12 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_FAL is not set
# CONFIG_PKG_USING_FAL_V00500 is not set
# CONFIG_PKG_USING_FAL_V00400 is not set
# CONFIG_PKG_USING_FAL_V00300 is not set
# CONFIG_PKG_USING_FAL_V00200 is not set
# CONFIG_PKG_USING_FAL_V00100 is not set
# CONFIG_PKG_USING_FAL_LATEST_VERSION is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
@@ -343,6 +352,11 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_LITTLED is not set
# CONFIG_PKG_USING_LKDGUI is not set
# CONFIG_PKG_USING_NRF5X_SDK is not set
CONFIG_PKG_USING_NRFX=y
CONFIG_PKG_NRFX_PATH="/packages/peripherals/nrfx"
CONFIG_PKG_USING_NRFX_V210=y
# CONFIG_PKG_USING_NRFX_LATEST_VERSION is not set
CONFIG_PKG_NRFX_VER="v2.1.0"
# CONFIG_PKG_USING_WM_LIBRARIES is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_INFRARED is not set
@@ -367,11 +381,6 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_BEEP is not set
# CONFIG_PKG_USING_EASYBLINK is not set
# CONFIG_PKG_USING_PMS_SERIES is not set
CONFIG_PKG_USING_NRFX=y
CONFIG_PKG_NRFX_PATH="/packages/peripherals/nrfx"
CONFIG_PKG_USING_NRFX_V210=y
# CONFIG_PKG_USING_NRFX_LATEST_VERSION is not set
CONFIG_PKG_NRFX_VER="v2.1.0"
#
# miscellaneous packages
@@ -423,6 +432,7 @@ CONFIG_SOC_NRF52840=y
# On-chip Peripheral Drivers
#
# CONFIG_BSP_USING_GPIO is not set
# CONFIG_BSP_USING_ON_CHIP_FLASH is not set
CONFIG_BSP_USING_UART=y
CONFIG_BSP_USING_UART0=y
# CONFIG_BSP_USING_UART1 is not set
bsp/nrf5x/nrf52840/board/Kconfig
+80 -4
View File
@@ -2,17 +2,52 @@ menu "Hardware Drivers Config"
config SOC_NRF52840
bool
config SOC_NRF52840
config SOC_NRF52840
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
default y
menu "Onboard Peripheral Drivers"
config BSP_USING_JLINK_TO_USART
bool "Enable JLINK TO USART (uart0)"
bool "Enable JLINK TO USART (uart0|RX_PIN:8|TX_PIN:6)"
select BSP_USING_UART
select BSP_USING_UART0
default y
menuconfig BSP_USING_QSPI_FLASH
select PKG_USING_FAL
bool "Enable QSPI FLASH(MX25R64 8MB)"
default n
if BSP_USING_QSPI_FLASH
config BSP_QSPI_SCK_PIN
int "QSPI SCK pin number"
range 0 31
default 19
config BSP_QSPI_CSN_PIN
int "QSPI CSN pin number"
range 0 31
default 17
config BSP_QSPI_IO0_PIN
int "QSPI IO0 pin number"
range 0 31
default 20
config BSP_QSPI_IO1_PIN
int "QSPI IO1 pin number"
range 0 31
default 21
config BSP_QSPI_IO2_PIN
int "QSPI IO2 pin number"
range 0 31
default 22
config BSP_QSPI_IO3_PIN
int "QSPI IO3 pin number"
range 0 31
default 23
config QSPI_FLASH_SIZE_KB
int "QSPI FLASH SIZE, DEFAULT size 8192 KB"
default 8192
endif
endmenu
menu "On-chip Peripheral Drivers"
@@ -30,11 +65,52 @@ menu "On-chip Peripheral Drivers"
config BSP_USING_UART0
bool "Enable UART0"
default y
if BSP_USING_UART0
config BSP_UART0_RX_PIN
int "uart0 rx pin number"
range 0 31
default 8
config BSP_UART0_TX_PIN
int "uart0 tx pin number"
range 0 31
default 6
endif
config BSP_USING_UART1
bool "Enable UART1"
default n
endif
endif
config BSP_USING_ON_CHIP_FLASH
select PKG_USING_FAL
bool "Enable on-chip FLASH"
default n
menu "On-chip flash config"
config MCU_FLASH_START_ADDRESS
hex "MCU FLASH START ADDRESS"
default 0x00000000
config MCU_FLASH_SIZE_KB
int "MCU FLASH SIZE, MAX size 1024 KB"
range 1 1024
default 1024
config MCU_SRAM_START_ADDRESS
hex "MCU RAM START ADDRESS"
default 0x20000000
config MCU_SRAM_SIZE_KB
int "MCU RAM SIZE, MAX size 256 KB"
range 1 256
default 256
config MCU_FLASH_PAGE_SIZE
hex "MCU FLASH PAGE SIZE, please not change,nrfx default is 0x1000"
range 0x1000 0x1000
default 0x1000
endmenu
endmenu
endmenu
bsp/nrf5x/nrf52840/board/board.h
+5
View File
@@ -5,6 +5,11 @@
#include "nrf.h"
#define MCU_FLASH_SIZE MCU_FLASH_SIZE_KB*1024
#define MCU_FLASH_END_ADDRESS ((uint32_t)(MCU_FLASH_START_ADDRESS + MCU_FLASH_SIZE))
#define MCU_SRAM_SIZE MCU_SRAM_SIZE_KB*1024
#define MCU_SRAM_END_ADDRESS (MCU_SRAM_START_ADDRESS + MCU_SRAM_SIZE)
#if defined(__CC_ARM) || defined(__CLANG_ARM)
extern int Image$$RW_IRAM1$$ZI$$Limit;
#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
bsp/nrf5x/nrf52840/board/fal_cfg.h
+82
View File
@@ -0,0 +1,82 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-05-05 supperthomas this is sample you can change by yourself
*
*/
#ifndef _FAL_CFG_H_
#define _FAL_CFG_H_
#include <rtconfig.h>
#include <board.h>
#if (defined(BSP_USING_QSPI_FLASH)&&defined(BSP_USING_ON_CHIP_FLASH))
#define ON_CHIP_FLASH_DEV_NAME "mcu_onchip"
#define NOR_FLASH_DEV_NAME "norflash0"
extern const struct fal_flash_dev mcu_onchip_flash;
extern struct fal_flash_dev nor_flash0;
/* flash device table */
#define FAL_FLASH_DEV_TABLE \
{ \
&mcu_onchip_flash, \
&nor_flash0, \
}
/* ====================== Partition Configuration ========================== */
#ifdef FAL_PART_HAS_TABLE_CFG
/* partition table */
#define FAL_PART_TABLE \
{ \
{FAL_PART_MAGIC_WORD, "bl", ON_CHIP_FLASH_DEV_NAME, 0, 64*1024, 0}, \
{FAL_PART_MAGIC_WORD, "app_flash", ON_CHIP_FLASH_DEV_NAME, 64*1024, 960*1024, 0}, \
{FAL_PART_MAGIC_WORD, "nor_flash_part_0", NOR_FLASH_DEV_NAME, 0, 1024*1024, 0}, \
{FAL_PART_MAGIC_WORD, "nor_flash_part_1", NOR_FLASH_DEV_NAME, 1024*1024, 7*1024*1024, 0}, \
}
#endif /* FAL_PART_HAS_TABLE_CFG */
#elif defined(BSP_USING_QSPI_FLASH)
#define NOR_FLASH_DEV_NAME "norflash0"
extern struct fal_flash_dev nor_flash0;
/* flash device table */
#define FAL_FLASH_DEV_TABLE \
{ \
&nor_flash0, \
}
/* ====================== Partition Configuration ========================== */
#ifdef FAL_PART_HAS_TABLE_CFG
/* partition table */
#define FAL_PART_TABLE \
{ \
{FAL_PART_MAGIC_WORD, "nor_flash_part_0", NOR_FLASH_DEV_NAME, 0, 1024*1024, 0}, \
{FAL_PART_MAGIC_WORD, "nor_flash_part_1", NOR_FLASH_DEV_NAME, 1024*1024, 7*1024*1024, 0}, \
}
#endif
#elif defined(BSP_USING_ON_CHIP_FLASH)
extern const struct fal_flash_dev mcu_onchip_flash;
#define ON_CHIP_FLASH_DEV_NAME "mcu_onchip"
/* flash device table */
#define FAL_FLASH_DEV_TABLE \
{ \
&mcu_onchip_flash, \
}
/* ====================== Partition Configuration ========================== */
#ifdef FAL_PART_HAS_TABLE_CFG
/* partition table */
#define FAL_PART_TABLE \
{ \
{FAL_PART_MAGIC_WORD, "bl", ON_CHIP_FLASH_DEV_NAME, 0, 64*1024, 0}, \
{FAL_PART_MAGIC_WORD, "app_flash", ON_CHIP_FLASH_DEV_NAME, 64*1024, 960*1024, 0}, \
}
#endif
#endif
#endif /* _FAL_CFG_H_ */
bsp/nrf5x/nrf52840/board/linker_scripts/link.sct
+3 -3
View File
@@ -2,13 +2,13 @@
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x0001F000 0x00061000 { ; load region size_region
ER_IROM1 0x0001F000 0x00061000 { ; load address = execution address
LR_IROM1 0x00000000 0x100000 { ; load region size_region
ER_IROM1 0x00000000 0x100000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 0x200025F8 0x0000DA08 { ; RW data
RW_IRAM1 0x20000000 0x40000 { ; RW data
.ANY (+RW +ZI)
}
}
bsp/nrf5x/nrf52840/board/sdk_config.h
+9 -5
View File
@@ -2902,7 +2902,7 @@
// <e> NRFX_QSPI_ENABLED - nrfx_qspi - QSPI peripheral driver
//==========================================================
#ifndef NRFX_QSPI_ENABLED
#define NRFX_QSPI_ENABLED 0
#define NRFX_QSPI_ENABLED 1
#endif
// <o> NRFX_QSPI_CONFIG_SCK_DELAY - tSHSL, tWHSL and tSHWL in number of 16 MHz periods (62.5 ns). <0-255>
@@ -3010,7 +3010,7 @@
#define NRFX_QSPI_PIN_IO3 NRF_QSPI_PIN_NOT_CONNECTED
#endif
// <o> NRFX_QSPI_CONFIG_IRQ_PRIORITY - Interrupt priority
// <o> NRFX_QSPI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
// <0=> 0 (highest)
// <1=> 1
@@ -3021,8 +3021,8 @@
// <6=> 6
// <7=> 7
#ifndef NRFX_QSPI_CONFIG_IRQ_PRIORITY
#define NRFX_QSPI_CONFIG_IRQ_PRIORITY 6
#ifndef NRFX_QSPI_DEFAULT_CONFIG_IRQ_PRIORITY
#define NRFX_QSPI_DEFAULT_CONFIG_IRQ_PRIORITY 6
#endif
// </e>
@@ -11687,7 +11687,11 @@
// </h>
//==========================================================
// <e> NRFX_NVMC_ENABLED - nrfx_nvmc - NVMC peripheral driver
//==========================================================
#ifndef NRFX_NVMC_ENABLED
#define NRFX_NVMC_ENABLED 1
#endif
// </e>
// </h>
bsp/nrf5x/nrf52840/project.uvoptx
+7 -7
View File
@@ -119,13 +119,13 @@
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
<Name>UL2CM3(-S0 -C0 -P0 ) -FN2 -FC4000 -FD20000000 -FF0nrf52xxx -FF1nrf52xxx_uicr -FL0200000 -FL11000 -FS00 -FS110001000 -FP0($$Device:nRF52840_xxAA$Flash\nrf52xxx.flm) -FP1($$Device:nRF52840_xxAA$Flash\nrf52xxx_uicr.flm)</Name>
<Key>JL2CM3</Key>
<Name>-U683349164 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC4000 -FN2 -FF0nrf52xxx.flm -FS00 -FL0200000 -FP0($$Device:nRF52840_xxAA$Flash\nrf52xxx.flm) -FF1nrf52xxx_uicr.flm -FS110001000 -FL11000 -FP1($$Device:nRF52840_xxAA$Flash\nrf52xxx_uicr.flm)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>JL2CM3</Key>
<Name>-U683349164 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC2000 -FN2 -FF0nrf52xxx.flm -FS00 -FL0200000 -FP0($$Device:nRF52840_xxAA$Flash\nrf52xxx.flm) -FF1nrf52xxx_uicr.flm -FS110001000 -FL11000 -FP1($$Device:nRF52840_xxAA$Flash\nrf52xxx_uicr.flm)</Name>
<Key>UL2CM3</Key>
<Name>UL2CM3(-S0 -C0 -P0 ) -FN2 -FC4000 -FD20000000 -FF0nrf52xxx -FF1nrf52xxx_uicr -FL0200000 -FL11000 -FS00 -FS110001000 -FP0($$Device:nRF52840_xxAA$Flash\nrf52xxx.flm) -FP1($$Device:nRF52840_xxAA$Flash\nrf52xxx_uicr.flm)</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
@@ -359,7 +359,7 @@
<Group>
<GroupName>Applications</GroupName>
<tvExp>1</tvExp>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
@@ -379,7 +379,7 @@
<Group>
<GroupName>Drivers</GroupName>
<tvExp>1</tvExp>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
@@ -411,7 +411,7 @@
<Group>
<GroupName>nrfx</GroupName>
<tvExp>1</tvExp>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
bsp/nrf5x/nrf52840/project.uvprojx
+4 -4
View File
@@ -18,7 +18,7 @@
<Vendor>Nordic Semiconductor</Vendor>
<PackID>NordicSemiconductor.nRF_DeviceFamilyPack.8.32.1</PackID>
<PackURL>http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/</PackURL>
<Cpu>IRAM(0x20000000,0x00040000) IROM(0x00000000,0x00100000) CPUTYPE("Cortex-M4") FPU2 DSP CLOCK(12000000) ELITTLE</Cpu>
<Cpu>IRAM(0x20000000,0x40000) IROM(0x00000000,0x100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC4000 -FN2 -FF0nrf52xxx -FS00 -FL0200000 -FF1nrf52xxx_uicr -FS110001000 -FL11000 -FP0($$Device:nRF52840_xxAA$Flash\nrf52xxx.flm) -FP1($$Device:nRF52840_xxAA$Flash\nrf52xxx_uicr.flm))</FlashDriverDll>
@@ -275,7 +275,7 @@
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0xde000</Size>
<Size>0x100000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
@@ -299,8 +299,8 @@
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x200026c0</StartAddress>
<Size>0x3d940</Size>
<StartAddress>0x20000000</StartAddress>
<Size>0x40000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
bsp/nrf5x/nrf52840/rtconfig.h
+3
View File
@@ -155,10 +155,13 @@
/* Onboard Peripheral Drivers */
#define BSP_USING_JLINK_TO_USART
/* On-chip Peripheral Drivers */
#define BSP_USING_UART
#define BSP_USING_UART0
#define BSP_UART0_RX_PIN 8
#define BSP_UART0_TX_PIN 6
#endif
bsp/nrf5x/nrf52840/template.uvoptx
+4 -4
View File
@@ -119,13 +119,13 @@
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
<Name>UL2CM3(-S0 -C0 -P0 ) -FN2 -FC4000 -FD20000000 -FF0nrf52xxx -FF1nrf52xxx_uicr -FL0200000 -FL11000 -FS00 -FS110001000 -FP0($$Device:nRF52840_xxAA$Flash\nrf52xxx.flm) -FP1($$Device:nRF52840_xxAA$Flash\nrf52xxx_uicr.flm)</Name>
<Key>JL2CM3</Key>
<Name>-U683349164 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC4000 -FN2 -FF0nrf52xxx.flm -FS00 -FL0200000 -FP0($$Device:nRF52840_xxAA$Flash\nrf52xxx.flm) -FF1nrf52xxx_uicr.flm -FS110001000 -FL11000 -FP1($$Device:nRF52840_xxAA$Flash\nrf52xxx_uicr.flm)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>JL2CM3</Key>
<Name>-U683349164 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC2000 -FN2 -FF0nrf52xxx.flm -FS00 -FL0200000 -FP0($$Device:nRF52840_xxAA$Flash\nrf52xxx.flm) -FF1nrf52xxx_uicr.flm -FS110001000 -FL11000 -FP1($$Device:nRF52840_xxAA$Flash\nrf52xxx_uicr.flm)</Name>
<Key>UL2CM3</Key>
<Name>UL2CM3(-S0 -C0 -P0 ) -FN2 -FC4000 -FD20000000 -FF0nrf52xxx -FF1nrf52xxx_uicr -FL0200000 -FL11000 -FS00 -FS110001000 -FP0($$Device:nRF52840_xxAA$Flash\nrf52xxx.flm) -FP1($$Device:nRF52840_xxAA$Flash\nrf52xxx_uicr.flm)</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
bsp/nrf5x/nrf52840/template.uvprojx
+4 -4
View File
@@ -18,7 +18,7 @@
<Vendor>Nordic Semiconductor</Vendor>
<PackID>NordicSemiconductor.nRF_DeviceFamilyPack.8.32.1</PackID>
<PackURL>http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/</PackURL>
<Cpu>IRAM(0x20000000,0x00040000) IROM(0x00000000,0x00100000) CPUTYPE("Cortex-M4") FPU2 DSP CLOCK(12000000) ELITTLE</Cpu>
<Cpu>IRAM(0x20000000,0x40000) IROM(0x00000000,0x100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC4000 -FN2 -FF0nrf52xxx -FS00 -FL0200000 -FF1nrf52xxx_uicr -FS110001000 -FL11000 -FP0($$Device:nRF52840_xxAA$Flash\nrf52xxx.flm) -FP1($$Device:nRF52840_xxAA$Flash\nrf52xxx_uicr.flm))</FlashDriverDll>
@@ -275,7 +275,7 @@
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0xde000</Size>
<Size>0x100000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
@@ -299,8 +299,8 @@
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x200026c0</StartAddress>
<Size>0x3d940</Size>
<StartAddress>0x20000000</StartAddress>
<Size>0x40000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
bsp/nuclei/gd32vf103_rvstar/rtconfig.py
+12
View File
@@ -5,6 +5,9 @@ ARCH='risc-v'
CPU='nuclei'
CROSS_TOOL='gcc'
# bsp lib config
BSP_LIBRARY_TYPE = None
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
@@ -18,7 +21,9 @@ else:
# EXEC_PATH = os.getenv('RTT_EXEC_PATH')
BUILD = 'debug'
# Fixed configurations below
NUCLEI_SDK_OPENOCD_CFG = "type in your config"
NUCLEI_SDK_SOC = "gd32vf103"
NUCLEI_SDK_BOARD = "gd32vf103v_rvstar"
NUCLEI_SDK_DOWNLOAD = "flashxip"
@@ -56,3 +61,10 @@ if PLATFORM == 'gcc':
DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
def dist_handle(BSP_ROOT):
import sys
cwd_path = os.getcwd()
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
from sdk_dist import dist_do_building
dist_do_building(BSP_ROOT)
bsp/nuclei/tools/sdk_dist.py
+18
View File
@@ -0,0 +1,18 @@
import os
import sys
import shutil
cwd_path = os.getcwd()
sys.path.append(os.path.join(os.path.dirname(cwd_path), 'rt-thread', 'tools'))
# BSP dist function
def dist_do_building(BSP_ROOT):
from mkdist import bsp_copy_files
import rtconfig
dist_dir = os.path.join(BSP_ROOT, 'dist', os.path.basename(BSP_ROOT))
library_dir = os.path.join(dist_dir, 'libraries')
print("=> copy nuclei bsp library")
library_path = os.path.join(os.path.dirname(BSP_ROOT), 'libraries')
library_dir = os.path.join(dist_dir, 'libraries')
bsp_copy_files(os.path.join(library_path, rtconfig.BSP_LIBRARY_TYPE), os.path.join(library_dir, rtconfig.BSP_LIBRARY_TYPE))
bsp/stm32/libraries/HAL_Drivers/config/f1/pwm_config.h
+11
View File
@@ -17,6 +17,17 @@
extern "C" {
#endif
#ifdef BSP_USING_PWM1
#ifndef PWM1_CONFIG
#define PWM1_CONFIG \
{ \
.tim_handle.Instance = TIM1, \
.name = "pwm1", \
.channel = 0 \
}
#endif /* PWM1_CONFIG */
#endif /* BSP_USING_PWM1 */
#ifdef BSP_USING_PWM2
#ifndef PWM2_CONFIG
#define PWM2_CONFIG \
bsp/stm32/libraries/HAL_Drivers/config/h7/dma_config.h
+13 -78
View File
@@ -7,6 +7,7 @@
* Date Author Notes
* 2019-01-02 zylx first version
* 2019-01-08 SummerGift clean up the code
* 2020-05-02 whj4674672 support stm32h7 dma1 and dma2
*/
#ifndef __DMA_CONFIG_H__
@@ -19,27 +20,21 @@ extern "C" {
#endif
/* DMA1 stream0 */
#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
#define SPI3_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler
#define SPI3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define SPI3_RX_DMA_INSTANCE DMA1_Stream0
#define SPI3_RX_DMA_CHANNEL DMA_CHANNEL_0
#define SPI3_RX_DMA_IRQ DMA1_Stream0_IRQn
#elif defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE)
#define UART5_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler
#define UART5_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define UART5_RX_DMA_INSTANCE DMA1_Stream0
#define UART5_RX_DMA_CHANNEL DMA_CHANNEL_4
#define UART5_RX_DMA_IRQ DMA1_Stream0_IRQn
#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
#define UART2_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler
#define UART2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define UART2_RX_DMA_INSTANCE DMA1_Stream0
#define UART2_RX_DMA_REQUEST DMA_REQUEST_USART2_RX
#define UART2_RX_DMA_IRQ DMA1_Stream0_IRQn
#endif
/* DMA1 stream1 */
#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
#define UART3_DMA_RX_IRQHandler DMA1_Stream1_IRQHandler
#define UART3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define UART3_RX_DMA_INSTANCE DMA1_Stream1
#define UART3_RX_DMA_CHANNEL DMA_CHANNEL_4
#define UART3_RX_DMA_IRQ DMA1_Stream1_IRQn
#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
#define UART2_DMA_TX_IRQHandler DMA1_Stream1_IRQHandler
#define UART2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define UART2_TX_DMA_INSTANCE DMA1_Stream1
#define UART2_TX_DMA_REQUEST DMA_REQUEST_USART2_TX
#define UART2_TX_DMA_IRQ DMA1_Stream1_IRQn
#endif
/* DMA1 stream2 */
@@ -49,12 +44,6 @@ extern "C" {
#define SPI3_RX_DMA_INSTANCE DMA1_Stream2
#define SPI3_RX_DMA_CHANNEL DMA_CHANNEL_0
#define SPI3_RX_DMA_IRQ DMA1_Stream2_IRQn
#elif defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
#define UART4_DMA_RX_IRQHandler DMA1_Stream2_IRQHandler
#define UART4_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define UART4_RX_DMA_INSTANCE DMA1_Stream2
#define UART4_RX_DMA_CHANNEL DMA_CHANNEL_4
#define UART4_RX_DMA_IRQ DMA1_Stream2_IRQn
#endif
/* DMA1 stream3 */
@@ -83,12 +72,6 @@ extern "C" {
#define SPI3_TX_DMA_INSTANCE DMA1_Stream5
#define SPI3_TX_DMA_CHANNEL DMA_CHANNEL_0
#define SPI3_TX_DMA_IRQ DMA1_Stream5_IRQn
#elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
#define UART2_DMA_RX_IRQHandler DMA1_Stream5_IRQHandler
#define UART2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define UART2_RX_DMA_INSTANCE DMA1_Stream5
#define UART2_RX_DMA_CHANNEL DMA_CHANNEL_4
#define UART2_RX_DMA_IRQ DMA1_Stream5_IRQn
#endif
/* DMA1 stream6 */
@@ -109,12 +92,6 @@ extern "C" {
#define SPI1_RX_DMA_INSTANCE DMA2_Stream0
#define SPI1_RX_DMA_CHANNEL DMA_CHANNEL_3
#define SPI1_RX_DMA_IRQ DMA2_Stream0_IRQn
#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
#define SPI4_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler
#define SPI4_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI4_RX_DMA_INSTANCE DMA2_Stream0
#define SPI4_RX_DMA_CHANNEL DMA_CHANNEL_4
#define SPI4_RX_DMA_IRQ DMA2_Stream0_IRQn
#endif
/* DMA2 stream1 */
@@ -133,18 +110,6 @@ extern "C" {
#define SPI1_RX_DMA_INSTANCE DMA2_Stream2
#define SPI1_RX_DMA_CHANNEL DMA_CHANNEL_3
#define SPI1_RX_DMA_IRQ DMA2_Stream2_IRQn
#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
#define UART1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler
#define UART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define UART1_RX_DMA_INSTANCE DMA2_Stream2
#define UART1_RX_DMA_CHANNEL DMA_CHANNEL_4
#define UART1_RX_DMA_IRQ DMA2_Stream2_IRQn
#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
#define QSPI_DMA_IRQHandler DMA2_Stream2_IRQHandler
#define QSPI_DMA_RCC RCC_AHB1ENR_DMA2EN
#define QSPI_DMA_INSTANCE DMA2_Stream2
#define QSPI_DMA_CHANNEL DMA_CHANNEL_11
#define QSPI_DMA_IRQ DMA2_Stream2_IRQn
#endif
/* DMA2 stream3 */
@@ -154,18 +119,6 @@ extern "C" {
#define SPI5_RX_DMA_INSTANCE DMA2_Stream3
#define SPI5_RX_DMA_CHANNEL DMA_CHANNEL_2
#define SPI5_RX_DMA_IRQ DMA2_Stream3_IRQn
#elif defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
#define SPI1_DMA_TX_IRQHandler DMA2_Stream3_IRQHandler
#define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI1_TX_DMA_INSTANCE DMA2_Stream3
#define SPI1_TX_DMA_CHANNEL DMA_CHANNEL_3
#define SPI1_TX_DMA_IRQ DMA2_Stream3_IRQn
#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
#define SPI4_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler
#define SPI4_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI4_RX_DMA_INSTANCE DMA2_Stream3
#define SPI4_RX_DMA_CHANNEL DMA_CHANNEL_5
#define SPI4_RX_DMA_IRQ DMA2_Stream3_IRQn
#endif
/* DMA2 stream4 */
@@ -175,12 +128,6 @@ extern "C" {
#define SPI5_TX_DMA_INSTANCE DMA2_Stream4
#define SPI5_TX_DMA_CHANNEL DMA_CHANNEL_2
#define SPI5_TX_DMA_IRQ DMA2_Stream4_IRQn
#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
#define SPI4_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler
#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI4_TX_DMA_INSTANCE DMA2_Stream4
#define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_5
#define SPI4_TX_DMA_IRQ DMA2_Stream4_IRQn
#endif
/* DMA2 stream5 */
@@ -190,18 +137,6 @@ extern "C" {
#define SPI1_TX_DMA_INSTANCE DMA2_Stream5
#define SPI1_TX_DMA_CHANNEL DMA_CHANNEL_3
#define SPI1_TX_DMA_IRQ DMA2_Stream5_IRQn
#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
#define UART1_DMA_RX_IRQHandler DMA2_Stream5_IRQHandler
#define UART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define UART1_RX_DMA_INSTANCE DMA2_Stream5
#define UART1_RX_DMA_CHANNEL DMA_CHANNEL_4
#define UART1_RX_DMA_IRQ DMA2_Stream5_IRQn
#elif defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
#define SPI5_DMA_RX_IRQHandler DMA2_Stream5_IRQHandler
#define SPI5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI5_RX_DMA_INSTANCE DMA2_Stream5
#define SPI5_RX_DMA_CHANNEL DMA_CHANNEL_7
#define SPI5_RX_DMA_IRQ DMA2_Stream5_IRQn
#endif
/* DMA2 stream6 */
bsp/stm32/libraries/HAL_Drivers/config/h7/uart_config.h
+38 -26
View File
@@ -7,6 +7,7 @@
* Date Author Notes
* 2018-10-30 SummerGift first version
* 2019-01-05 zylx modify dma support
* 2020-05-02 whj4674672 support stm32h7 uart dma
*/
#ifndef __UART_CONFIG_H__
@@ -31,12 +32,12 @@ extern "C" {
#if defined(BSP_UART1_RX_USING_DMA)
#ifndef UART1_DMA_RX_CONFIG
#define UART1_DMA_RX_CONFIG \
#define UART1_DMA_RX_CONFIG \
{ \
.Instance = UART1_RX_DMA_INSTANCE, \
.channel = UART1_RX_DMA_CHANNEL, \
.dma_rcc = UART1_RX_DMA_RCC, \
.dma_irq = UART1_RX_DMA_IRQ, \
.Instance = UART1_RX_DMA_INSTANCE, \
.request = UART1_RX_DMA_REQUEST, \
.dma_rcc = UART1_RX_DMA_RCC, \
.dma_irq = UART1_RX_DMA_IRQ, \
}
#endif /* UART1_DMA_RX_CONFIG */
#endif /* BSP_UART1_RX_USING_DMA */
@@ -54,16 +55,27 @@ extern "C" {
#if defined(BSP_UART2_RX_USING_DMA)
#ifndef UART2_DMA_RX_CONFIG
#define UART2_DMA_RX_CONFIG \
#define UART2_DMA_RX_CONFIG \
{ \
.Instance = UART2_RX_DMA_INSTANCE, \
.channel = UART2_RX_DMA_CHANNEL, \
.dma_rcc = UART2_RX_DMA_RCC, \
.dma_irq = UART2_RX_DMA_IRQ, \
.Instance = UART2_RX_DMA_INSTANCE, \
.request = UART2_RX_DMA_REQUEST, \
.dma_rcc = UART2_RX_DMA_RCC, \
.dma_irq = UART2_RX_DMA_IRQ, \
}
#endif /* UART2_DMA_RX_CONFIG */
#endif /* BSP_UART2_RX_USING_DMA */
#if defined(BSP_UART2_TX_USING_DMA)
#ifndef UART2_DMA_TX_CONFIG
#define UART2_DMA_TX_CONFIG \
{ \
.Instance = UART2_TX_DMA_INSTANCE, \
.request = UART2_TX_DMA_REQUEST, \
.dma_rcc = UART2_TX_DMA_RCC, \
.dma_irq = UART2_TX_DMA_IRQ, \
}
#endif /* UART2_DMA_TX_CONFIG */
#endif /* BSP_UART2_TX_USING_DMA */
#if defined(BSP_USING_UART3)
#ifndef UART3_CONFIG
#define UART3_CONFIG \
@@ -77,12 +89,12 @@ extern "C" {
#if defined(BSP_UART3_RX_USING_DMA)
#ifndef UART3_DMA_RX_CONFIG
#define UART3_DMA_RX_CONFIG \
#define UART3_DMA_RX_CONFIG \
{ \
.Instance = UART3_RX_DMA_INSTANCE, \
.channel = UART3_RX_DMA_CHANNEL, \
.dma_rcc = UART3_RX_DMA_RCC, \
.dma_irq = UART3_RX_DMA_IRQ, \
.Instance = UART3_RX_DMA_INSTANCE, \
.request = UART3_RX_DMA_REQUEST, \
.dma_rcc = UART3_RX_DMA_RCC, \
.dma_irq = UART3_RX_DMA_IRQ, \
}
#endif /* UART3_DMA_RX_CONFIG */
#endif /* BSP_UART3_RX_USING_DMA */
@@ -100,12 +112,12 @@ extern "C" {
#if defined(BSP_UART4_RX_USING_DMA)
#ifndef UART4_DMA_RX_CONFIG
#define UART4_DMA_RX_CONFIG \
#define UART4_DMA_RX_CONFIG \
{ \
.Instance = UART4_RX_DMA_INSTANCE, \
.channel = UART4_RX_DMA_CHANNEL, \
.dma_rcc = UART4_RX_DMA_RCC, \
.dma_irq = UART4_RX_DMA_IRQ, \
.Instance = UART4_RX_DMA_INSTANCE, \
.request = UART4_RX_DMA_REQUEST, \
.dma_rcc = UART4_RX_DMA_RCC, \
.dma_irq = UART4_RX_DMA_IRQ, \
}
#endif /* UART4_DMA_RX_CONFIG */
#endif /* BSP_UART4_RX_USING_DMA */
@@ -123,12 +135,12 @@ extern "C" {
#if defined(BSP_UART5_RX_USING_DMA)
#ifndef UART5_DMA_RX_CONFIG
#define UART5_DMA_RX_CONFIG \
#define UART5_DMA_RX_CONFIG \
{ \
.Instance = UART5_RX_DMA_INSTANCE, \
.channel = UART5_RX_DMA_CHANNEL, \
.dma_rcc = UART5_RX_DMA_RCC, \
.dma_irq = UART5_RX_DMA_IRQ, \
.Instance = UART5_RX_DMA_INSTANCE, \
.request = UART5_RX_DMA_REQUEST, \
.dma_rcc = UART5_RX_DMA_RCC, \
.dma_irq = UART5_RX_DMA_IRQ, \
}
#endif /* UART5_DMA_RX_CONFIG */
#endif /* BSP_UART5_RX_USING_DMA */
bsp/stm32/libraries/HAL_Drivers/drv_can.c
+5 -5
View File
@@ -688,9 +688,9 @@ void CAN1_SCE_IRQHandler(void)
drv_can1.device.status.ackerrcnt++;
if (!READ_BIT(drv_can1.CanHandle.Instance->TSR, CAN_FLAG_TXOK0))
rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_TX_FAIL | 0 << 8);
else if (!READ_BIT(drv_can1.CanHandle.Instance->TSR, CAN_FLAG_TXOK0))
else if (!READ_BIT(drv_can1.CanHandle.Instance->TSR, CAN_FLAG_TXOK1))
rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_TX_FAIL | 1 << 8);
else if (!READ_BIT(drv_can1.CanHandle.Instance->TSR, CAN_FLAG_TXOK0))
else if (!READ_BIT(drv_can1.CanHandle.Instance->TSR, CAN_FLAG_TXOK2))
rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_TX_FAIL | 2 << 8);
break;
case RT_CAN_BUS_IMPLICIT_BIT_ERR:
@@ -806,11 +806,11 @@ void CAN2_SCE_IRQHandler(void)
break;
case RT_CAN_BUS_ACK_ERR:
drv_can2.device.status.ackerrcnt++;
if (!READ_BIT(drv_can1.CanHandle.Instance->TSR, CAN_FLAG_TXOK0))
if (!READ_BIT(drv_can2.CanHandle.Instance->TSR, CAN_FLAG_TXOK0))
rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_TX_FAIL | 0 << 8);
else if (!READ_BIT(drv_can2.CanHandle.Instance->TSR, CAN_FLAG_TXOK0))
else if (!READ_BIT(drv_can2.CanHandle.Instance->TSR, CAN_FLAG_TXOK1))
rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_TX_FAIL | 1 << 8);
else if (!READ_BIT(drv_can2.CanHandle.Instance->TSR, CAN_FLAG_TXOK0))
else if (!READ_BIT(drv_can2.CanHandle.Instance->TSR, CAN_FLAG_TXOK2))
rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_TX_FAIL | 2 << 8);
break;
case RT_CAN_BUS_IMPLICIT_BIT_ERR:
bsp/stm32/libraries/HAL_Drivers/drv_dma.h
+2 -1
View File
@@ -35,7 +35,8 @@ struct dma_config {
rt_uint32_t channel;
#endif
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4)
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4)\
|| defined(SOC_SERIES_STM32H7)
rt_uint32_t request;
#endif
};
bsp/stm32/libraries/HAL_Drivers/drv_spi.c
-2
View File
@@ -257,8 +257,6 @@ static rt_err_t stm32_spi_init(struct stm32_spi *spi_drv, struct rt_spi_configur
HAL_NVIC_EnableIRQ(spi_drv->config->dma_tx->dma_irq);
}
__HAL_SPI_ENABLE(spi_handle);
LOG_D("%s init done", spi_drv->config->bus_name);
return RT_EOK;
}
bsp/stm32/libraries/HAL_Drivers/drv_usart.c
+5 -3
View File
@@ -8,6 +8,7 @@
* 2018-10-30 SummerGift first version
* 2020-03-16 SummerGift add device close feature
* 2020-03-20 SummerGift fix bug caused by ORE
* 2020-05-02 whj4674672 support stm32h7 uart dma
*/
#include "board.h"
@@ -864,7 +865,7 @@ static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
SET_BIT(RCC->AHBENR, dma_config->dma_rcc);
tmpreg = READ_BIT(RCC->AHBENR, dma_config->dma_rcc);
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) \
|| defined(SOC_SERIES_STM32G4)
|| defined(SOC_SERIES_STM32G4)|| defined(SOC_SERIES_STM32H7)
/* enable DMA clock && Delay after an RCC peripheral clock enabling*/
SET_BIT(RCC->AHB1ENR, dma_config->dma_rcc);
tmpreg = READ_BIT(RCC->AHB1ENR, dma_config->dma_rcc);
@@ -892,7 +893,8 @@ static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
DMA_Handle->Instance = dma_config->Instance;
DMA_Handle->Init.Channel = dma_config->channel;
#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4)
#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4)\
|| defined(SOC_SERIES_STM32H7)
DMA_Handle->Instance = dma_config->Instance;
DMA_Handle->Init.Request = dma_config->request;
#endif
@@ -913,7 +915,7 @@ static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
}
DMA_Handle->Init.Priority = DMA_PRIORITY_MEDIUM;
#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32H7)
DMA_Handle->Init.FIFOMode = DMA_FIFOMODE_DISABLE;
#endif
if (HAL_DMA_DeInit(DMA_Handle) != HAL_OK)
bsp/stm32/libraries/templates/stm32f0xx/rtconfig.py
+7
View File
@@ -141,3 +141,10 @@ elif PLATFORM == 'iar':
EXEC_PATH = EXEC_PATH + '/arm/bin/'
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
def dist_handle(BSP_ROOT):
import sys
cwd_path = os.getcwd()
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
from sdk_dist import dist_do_building
dist_do_building(BSP_ROOT)
bsp/stm32/libraries/templates/stm32f10x/rtconfig.py
+7
View File
@@ -141,3 +141,10 @@ elif PLATFORM == 'iar':
EXEC_PATH = EXEC_PATH + '/arm/bin/'
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
def dist_handle(BSP_ROOT):
import sys
cwd_path = os.getcwd()
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
from sdk_dist import dist_do_building
dist_do_building(BSP_ROOT)
bsp/stm32/libraries/templates/stm32f2xx/rtconfig.py
+7
View File
@@ -141,3 +141,10 @@ elif PLATFORM == 'iar':
EXEC_PATH = EXEC_PATH + '/arm/bin/'
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
def dist_handle(BSP_ROOT):
import sys
cwd_path = os.getcwd()
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
from sdk_dist import dist_do_building
dist_do_building(BSP_ROOT)
bsp/stm32/libraries/templates/stm32f4xx/rtconfig.py
+7
View File
@@ -141,3 +141,10 @@ elif PLATFORM == 'iar':
EXEC_PATH = EXEC_PATH + '/arm/bin/'
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
def dist_handle(BSP_ROOT):
import sys
cwd_path = os.getcwd()
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
from sdk_dist import dist_do_building
dist_do_building(BSP_ROOT)
bsp/stm32/libraries/templates/stm32f7xx/rtconfig.py
+7
View File
@@ -140,3 +140,10 @@ elif PLATFORM == 'iar':
EXEC_PATH = EXEC_PATH + '/arm/bin/'
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
def dist_handle(BSP_ROOT):
import sys
cwd_path = os.getcwd()
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
from sdk_dist import dist_do_building
dist_do_building(BSP_ROOT)
bsp/stm32/libraries/templates/stm32h7xx/rtconfig.py
+7
View File
@@ -142,3 +142,10 @@ elif PLATFORM == 'iar':
EXEC_PATH = EXEC_PATH + '/arm/bin/'
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
def dist_handle(BSP_ROOT):
import sys
cwd_path = os.getcwd()
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
from sdk_dist import dist_do_building
dist_do_building(BSP_ROOT)
bsp/stm32/libraries/templates/stm32l1xx/rtconfig.py
+7
View File
@@ -141,3 +141,10 @@ elif PLATFORM == 'iar':
EXEC_PATH = EXEC_PATH + '/arm/bin/'
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
def dist_handle(BSP_ROOT):
import sys
cwd_path = os.getcwd()
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
from sdk_dist import dist_do_building
dist_do_building(BSP_ROOT)
bsp/stm32/libraries/templates/stm32l4xx/rtconfig.py
+7
View File
@@ -141,3 +141,10 @@ elif PLATFORM == 'iar':
EXEC_PATH = EXEC_PATH + '/arm/bin/'
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
def dist_handle(BSP_ROOT):
import sys
cwd_path = os.getcwd()
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
from sdk_dist import dist_do_building
dist_do_building(BSP_ROOT)
bsp/stm32/stm32f072-st-nucleo/rtconfig.py
+8
View File
@@ -141,3 +141,11 @@ elif PLATFORM == 'iar':
EXEC_PATH = EXEC_PATH + '/arm/bin/'
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
def dist_handle(BSP_ROOT):
import sys
cwd_path = os.getcwd()
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
from sdk_dist import dist_do_building
dist_do_building(BSP_ROOT)
bsp/stm32/stm32f091-st-nucleo/rtconfig.py
+7
View File
@@ -141,3 +141,10 @@ elif PLATFORM == 'iar':
EXEC_PATH = EXEC_PATH + '/arm/bin/'
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
def dist_handle(BSP_ROOT):
import sys
cwd_path = os.getcwd()
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
from sdk_dist import dist_do_building
dist_do_building(BSP_ROOT)
bsp/stm32/stm32f103-atk-nano/rtconfig.py
+7
View File
@@ -141,3 +141,10 @@ elif PLATFORM == 'iar':
EXEC_PATH = EXEC_PATH + '/arm/bin/'
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
def dist_handle(BSP_ROOT):
import sys
cwd_path = os.getcwd()
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
from sdk_dist import dist_do_building
dist_do_building(BSP_ROOT)
bsp/stm32/stm32f103-atk-warshipv3/applications/main.c
+1 -1
View File
@@ -14,7 +14,7 @@
/* defined the LED0 pin: PB5 */
#define LED0_PIN GET_PIN(B, 5)
/* defined the LED0 pin: PE5 */
/* defined the LED1 pin: PE5 */
#define LED1_PIN GET_PIN(E, 5)
int main(void)
bsp/stm32/stm32f103-atk-warshipv3/rtconfig.py
+7
View File
@@ -141,3 +141,10 @@ elif PLATFORM == 'iar':
EXEC_PATH = EXEC_PATH + '/arm/bin/'
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
def dist_handle(BSP_ROOT):
import sys
cwd_path = os.getcwd()
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
from sdk_dist import dist_do_building
dist_do_building(BSP_ROOT)
bsp/stm32/stm32f103-dofly-M3S/rtconfig.py
+7
View File
@@ -141,3 +141,10 @@ elif PLATFORM == 'iar':
EXEC_PATH = EXEC_PATH + '/arm/bin/'
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
def dist_handle(BSP_ROOT):
import sys
cwd_path = os.getcwd()
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
from sdk_dist import dist_do_building
dist_do_building(BSP_ROOT)
bsp/stm32/stm32f103-dofly-lyc8/rtconfig.py
+7
View File
@@ -141,3 +141,10 @@ elif PLATFORM == 'iar':
EXEC_PATH = EXEC_PATH + '/arm/bin/'
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
def dist_handle(BSP_ROOT):
import sys
cwd_path = os.getcwd()
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
from sdk_dist import dist_do_building
dist_do_building(BSP_ROOT)
bsp/stm32/stm32f103-fire-arbitrary/rtconfig.py
+7
View File
@@ -141,3 +141,10 @@ elif PLATFORM == 'iar':
EXEC_PATH = EXEC_PATH + '/arm/bin/'
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
def dist_handle(BSP_ROOT):
import sys
cwd_path = os.getcwd()
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
from sdk_dist import dist_do_building
dist_do_building(BSP_ROOT)
bsp/stm32/stm32f103-gizwits-gokitv21/.config
+69 -15
View File
@@ -64,7 +64,7 @@ CONFIG_RT_USING_DEVICE=y
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
CONFIG_RT_VER_NUM=0x40002
CONFIG_RT_VER_NUM=0x40003
CONFIG_ARCH_ARM=y
CONFIG_RT_USING_CPU_FFS=y
CONFIG_ARCH_ARM_CORTEX_M=y
@@ -126,7 +126,6 @@ CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_MTD is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
@@ -134,15 +133,10 @@ CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
#
# Using Hardware Crypto drivers
#
# CONFIG_RT_USING_TOUCH is not set
# CONFIG_RT_USING_HWCRYPTO is not set
#
# Using WiFi
#
# CONFIG_RT_USING_PULSE_ENCODER is not set
# CONFIG_RT_USING_INPUT_CAPTURE is not set
# CONFIG_RT_USING_WIFI is not set
#
@@ -156,6 +150,7 @@ CONFIG_RT_USING_PIN=y
#
# CONFIG_RT_USING_LIBC is not set
# CONFIG_RT_USING_PTHREADS is not set
# CONFIG_RT_LIBC_USING_TIME is not set
#
# Network
@@ -176,11 +171,6 @@ CONFIG_RT_USING_PIN=y
#
# CONFIG_RT_USING_LWIP is not set
#
# Modbus master and slave stack
#
# CONFIG_RT_USING_MODBUS is not set
#
# AT commands
#
@@ -210,10 +200,13 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_WEBNET is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_MYMQTT is not set
# CONFIG_PKG_USING_KAWAII_MQTT is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_LIBMODBUS is not set
# CONFIG_PKG_USING_FREEMODBUS is not set
# CONFIG_PKG_USING_LJSON is not set
# CONFIG_PKG_USING_EZXML is not set
# CONFIG_PKG_USING_NANOPB is not set
@@ -235,6 +228,7 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_PPP_DEVICE is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
# CONFIG_PKG_USING_ATSRV_SOCKET is not set
# CONFIG_PKG_USING_WIZNET is not set
@@ -247,12 +241,28 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
# CONFIG_PKG_USING_JOYLINK is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
# CONFIG_PKG_USING_IPMSG is not set
# CONFIG_PKG_USING_LSSDP is not set
# CONFIG_PKG_USING_AIRKISS_OPEN is not set
# CONFIG_PKG_USING_LIBRWS is not set
# CONFIG_PKG_USING_TCPSERVER is not set
# CONFIG_PKG_USING_PROTOBUF_C is not set
# CONFIG_PKG_USING_ONNX_PARSER is not set
# CONFIG_PKG_USING_ONNX_BACKEND is not set
# CONFIG_PKG_USING_DLT645 is not set
# CONFIG_PKG_USING_QXWZ is not set
# CONFIG_PKG_USING_SMTP_CLIENT is not set
# CONFIG_PKG_USING_ABUP_FOTA is not set
# CONFIG_PKG_USING_LIBCURL2RTT is not set
# CONFIG_PKG_USING_CAPNP is not set
# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
# CONFIG_PKG_USING_AGILE_TELNET is not set
# CONFIG_PKG_USING_CMUX is not set
#
# security packages
@@ -260,6 +270,7 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_MBEDTLS is not set
# CONFIG_PKG_USING_libsodium is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
# CONFIG_PKG_USING_TFM is not set
#
# language packages
@@ -274,6 +285,8 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_OPENMV is not set
# CONFIG_PKG_USING_MUPDF is not set
# CONFIG_PKG_USING_STEMWIN is not set
# CONFIG_PKG_USING_WAVPLAYER is not set
# CONFIG_PKG_USING_TJPGD is not set
#
# tools packages
@@ -286,6 +299,12 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ADBD is not set
# CONFIG_PKG_USING_COREMARK is not set
# CONFIG_PKG_USING_DHRYSTONE is not set
# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
# CONFIG_PKG_USING_BS8116A is not set
#
# system packages
@@ -303,6 +322,11 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
# CONFIG_PKG_USING_THREAD_POOL is not set
# CONFIG_PKG_USING_ROBOTS is not set
# CONFIG_PKG_USING_EV is not set
# CONFIG_PKG_USING_SYSWATCH is not set
# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
# CONFIG_PKG_USING_PLCCORE is not set
#
# peripheral libraries and drivers
@@ -310,6 +334,7 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_SHT3X is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_U8G2 is not set
@@ -318,15 +343,33 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_SX12XX is not set
# CONFIG_PKG_USING_SIGNAL_LED is not set
# CONFIG_PKG_USING_LEDBLINK is not set
# CONFIG_PKG_USING_LITTLED is not set
# CONFIG_PKG_USING_LKDGUI is not set
# CONFIG_PKG_USING_NRF5X_SDK is not set
# CONFIG_PKG_USING_WM_LIBRARIES is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_INFRARED is not set
# CONFIG_PKG_USING_ROSSERIAL is not set
# CONFIG_PKG_USING_AGILE_BUTTON is not set
# CONFIG_PKG_USING_AGILE_LED is not set
# CONFIG_PKG_USING_AT24CXX is not set
# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_PCA9685 is not set
# CONFIG_PKG_USING_I2C_TOOLS is not set
# CONFIG_PKG_USING_NRF24L01 is not set
# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
# CONFIG_PKG_USING_MAX17048 is not set
# CONFIG_PKG_USING_RPLIDAR is not set
# CONFIG_PKG_USING_AS608 is not set
# CONFIG_PKG_USING_RC522 is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
# CONFIG_PKG_USING_MULTI_RTIMER is not set
# CONFIG_PKG_USING_MAX7219 is not set
# CONFIG_PKG_USING_BEEP is not set
# CONFIG_PKG_USING_EASYBLINK is not set
# CONFIG_PKG_USING_PMS_SERIES is not set
#
# miscellaneous packages
@@ -337,12 +380,15 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_DSTR is not set
# CONFIG_PKG_USING_TINYFRAME is not set
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
# CONFIG_PKG_USING_DIGITALCTRL is not set
# CONFIG_PKG_USING_UPACKER is not set
# CONFIG_PKG_USING_UPARAM is not set
#
# samples: kernel and components samples
@@ -354,6 +400,12 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_VI is not set
# CONFIG_PKG_USING_NNOM is not set
# CONFIG_PKG_USING_LIBANN is not set
# CONFIG_PKG_USING_ELAPACK is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_UKAL is not set
CONFIG_SOC_FAMILY_STM32=y
CONFIG_SOC_SERIES_STM32F1=y
@@ -372,8 +424,10 @@ CONFIG_SOC_STM32F103C8=y
CONFIG_BSP_USING_GPIO=y
CONFIG_BSP_USING_UART=y
CONFIG_BSP_USING_UART1=y
CONFIG_BSP_USING_UART2=y
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_I2C1 is not set
# CONFIG_BSP_USING_UDID is not set
#
# Board extended module Drivers
bsp/stm32/stm32f103-gizwits-gokitv21/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c
+46
View File
@@ -117,6 +117,34 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart)
/* USER CODE END USART1_MspInit 1 */
}
if(huart->Instance==USART2)
{
/* USER CODE BEGIN USART2_MspInit 0 */
/* USER CODE END USART2_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_USART2_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
/**USART2 GPIO Configuration
PA2 ------> USART2_TX
PA3 ------> USART2_RX
*/
GPIO_InitStruct.Pin = GPIO_PIN_2;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_3;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_PULLUP;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/* USER CODE BEGIN USART2_MspInit 1 */
/* USER CODE END USART2_MspInit 1 */
}
}
@@ -146,6 +174,24 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
/* USER CODE END USART1_MspDeInit 1 */
}
if(huart->Instance==USART2)
{
/* USER CODE BEGIN USART2_MspDeInit 0 */
/* USER CODE END USART2_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_USART2_CLK_DISABLE();
/**USART2 GPIO Configuration
PA2 ------> USART2_TX
PA3 ------> USART2_RX
*/
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3);
/* USER CODE BEGIN USART2_MspDeInit 1 */
/* USER CODE END USART2_MspDeInit 1 */
}
}
bsp/stm32/stm32f103-gizwits-gokitv21/board/Kconfig
+8
View File
@@ -31,6 +31,14 @@ menu "On-chip Peripheral Drivers"
bool "Enable UART1 RX DMA"
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
default n
config BSP_USING_UART2
bool "Enable UART2"
default n
config BSP_UART1_RX_USING_DMA
bool "Enable UART2 RX DMA"
depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
default n
endif
menuconfig BSP_USING_SPI
bsp/stm32/stm32f103-gizwits-gokitv21/project.uvprojx
-14
View File
@@ -392,13 +392,6 @@
<FilePath>..\..\..\src\components.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>cpu.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\cpu.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>device.c</FileName>
@@ -732,13 +725,6 @@
<FilePath>..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_cec.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>stm32f1xx_hal_sram.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_sram.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>stm32f1xx_hal_gpio.c</FileName>
bsp/stm32/stm32f103-gizwits-gokitv21/rtconfig.h
+2 -10
View File
@@ -39,7 +39,7 @@
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x40002
#define RT_VER_NUM 0x40003
#define ARCH_ARM
#define RT_USING_CPU_FFS
#define ARCH_ARM_CORTEX_M
@@ -82,12 +82,6 @@
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_PIN
/* Using Hardware Crypto drivers */
/* Using WiFi */
/* Using USB */
@@ -105,9 +99,6 @@
/* light weight TCP/IP stack */
/* Modbus master and slave stack */
/* AT commands */
@@ -170,6 +161,7 @@
#define BSP_USING_GPIO
#define BSP_USING_UART
#define BSP_USING_UART1
#define BSP_USING_UART2
/* Board extended module Drivers */

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