diff --git a/.travis.yml b/.travis.yml index 8b4f03006a..cd1f6f8886 100644 --- a/.travis.yml +++ b/.travis.yml @@ -109,6 +109,7 @@ env: - RTT_BSP='stm32/stm32l4r9-st-eval' RTT_TOOL_CHAIN='sourcery-arm' - RTT_BSP='stm32/stm32l010-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm' - RTT_BSP='stm32/stm32l053-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm' + - RTT_BSP='stm32/stm32l412-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm' - RTT_BSP='stm32/stm32l432-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm' - RTT_BSP='stm32/stm32l475-atk-pandora' RTT_TOOL_CHAIN='sourcery-arm' - RTT_BSP='stm32/stm32l475-st-discovery' RTT_TOOL_CHAIN='sourcery-arm' diff --git a/bsp/lpc54608-LPCXpresso/project.ewp b/bsp/lpc54608-LPCXpresso/project.ewp index 22154af07d..d16ead5d2c 100644 --- a/bsp/lpc54608-LPCXpresso/project.ewp +++ b/bsp/lpc54608-LPCXpresso/project.ewp @@ -2148,16 +2148,16 @@ CPlusPlus - $PROJ_DIR$\../../components/cplusplus/Mutex.cpp + $PROJ_DIR$\../../components/cplusplus/cxx_Mutex.cpp - $PROJ_DIR$\../../components/cplusplus/Semaphore.cpp + $PROJ_DIR$\../../components/cplusplus/cxx_Semaphore.cpp - $PROJ_DIR$\../../components/cplusplus/Thread.cpp + $PROJ_DIR$\../../components/cplusplus/cxx_Thread.cpp - $PROJ_DIR$\../../components/cplusplus/crt.cpp + $PROJ_DIR$\../../components/cplusplus/cxx_crt.cpp $PROJ_DIR$\../../components/cplusplus/crt_init.c diff --git a/bsp/lpc54608-LPCXpresso/project.ewt b/bsp/lpc54608-LPCXpresso/project.ewt index de78292e60..a1d63d5e4b 100644 --- a/bsp/lpc54608-LPCXpresso/project.ewt +++ b/bsp/lpc54608-LPCXpresso/project.ewt @@ -2355,19 +2355,19 @@ CPlusPlus - $PROJ_DIR$\..\..\components\cplusplus\crt.cpp + $PROJ_DIR$\..\..\components\cplusplus\cxx_crt.cpp $PROJ_DIR$\..\..\components\cplusplus\crt_init.c - $PROJ_DIR$\..\..\components\cplusplus\Mutex.cpp + $PROJ_DIR$\..\..\components\cplusplus\cxx_Mutex.cpp - $PROJ_DIR$\..\..\components\cplusplus\Semaphore.cpp + $PROJ_DIR$\..\..\components\cplusplus\cxx_Semaphore.cpp - $PROJ_DIR$\..\..\components\cplusplus\Thread.cpp + $PROJ_DIR$\..\..\components\cplusplus\cxx_Thread.cpp diff --git a/bsp/lpc54608-LPCXpresso/project.uvprojx b/bsp/lpc54608-LPCXpresso/project.uvprojx index ad2e225b2e..e7978224d2 100644 --- a/bsp/lpc54608-LPCXpresso/project.uvprojx +++ b/bsp/lpc54608-LPCXpresso/project.uvprojx @@ -330,9 +330,9 @@ 0 --library_interface=armcc --library_type=standardlib --diag_suppress=66,1296,186 - CPU_LPC54608J512ET180=1, CPU_LPC54608, CORE_M4, SDK_DEBUGCONSOLE=0, RT_USING_ARM_LIBC + SDK_DEBUGCONSOLE=0, CPU_LPC54608, CORE_M4, CPU_LPC54608J512ET180=1, RT_USING_ARM_LIBC - .;..\..\include;applications;.;drivers;SDK_2.2_LPCXpresso54608\CMSIS\Include;SDK_2.2_LPCXpresso54608\devices\LPC54608;SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers;SDK_2.2_LPCXpresso54608\devices\LPC54608\utilities;SDK_2.2_LPCXpresso54608\sdmmc_2.1.2\inc;SDK_2.2_LPCXpresso54608\sdmmc_2.1.2\src;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m4;..\..\components\cplusplus;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\dfs\filesystems\elmfat;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\spi;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\armlibc;..\..\components\libc\compilers\common;..\..\components\libc\pthreads;..\..\components\libc\time;..\..\components\net\lwip-2.0.2\src;..\..\components\net\lwip-2.0.2\src\include;..\..\components\net\lwip-2.0.2\src\include\ipv4;..\..\components\net\lwip-2.0.2\src\arch\include;..\..\components\net\lwip-2.0.2\src\include\netif;..\..\components\net\netdev\include;..\..\components\net\sal_socket\include;..\..\components\net\sal_socket\include\socket;..\..\components\net\sal_socket\impl;..\..\components\net\sal_socket\include\dfs_net;..\..\components\net\sal_socket\include\dfs_net\sys_select;..\..\components\net\sal_socket\include\socket\sys_socket + .;../../include;applications;.;drivers;SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/inc;SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/src;SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers;SDK_2.2_LPCXpresso54608/devices/LPC54608/utilities;SDK_2.2_LPCXpresso54608/CMSIS/Include;SDK_2.2_LPCXpresso54608/devices/LPC54608;../../libcpu/arm/common;../../libcpu/arm/cortex-m4;../../components/finsh;../../components/dfs/include;../../components/dfs/filesystems/elmfat;../../components/dfs/filesystems/devfs;../../components/net/lwip-2.0.2/src;../../components/net/lwip-2.0.2/src/include;../../components/net/lwip-2.0.2/src/include/ipv4;../../components/net/lwip-2.0.2/src/arch/include;../../components/net/lwip-2.0.2/src/include/netif;../../components/net/netdev/include;../../components/net/sal_socket/include;../../components/net/sal_socket/include/socket;../../components/net/sal_socket/impl;../../components/net/sal_socket/include/dfs_net;../../components/net/sal_socket/include/dfs_net/sys_select;../../components/net/sal_socket/include/socket/sys_socket;../../components/drivers/include;../../components/drivers/include;../../components/drivers/spi;../../components/drivers/include;../../components/drivers/include;../../components/drivers/include;../../components/drivers/include;../../components/drivers/include;../../components/drivers/include;../../components/cplusplus;../../components/libc/compilers/armlibc;../../components/libc/compilers/common;../../components/libc/pthreads;../../components/libc/time @@ -379,112 +379,105 @@ clock.c 1 - ..\..\src\clock.c + ../../src/clock.c components.c 1 - ..\..\src\components.c - - - - - cpu.c - 1 - ..\..\src\cpu.c + ../../src/components.c device.c 1 - ..\..\src\device.c + ../../src/device.c idle.c 1 - ..\..\src\idle.c + ../../src/idle.c ipc.c 1 - ..\..\src\ipc.c + ../../src/ipc.c irq.c 1 - ..\..\src\irq.c + ../../src/irq.c kservice.c 1 - ..\..\src\kservice.c + ../../src/kservice.c mem.c 1 - ..\..\src\mem.c + ../../src/mem.c memheap.c 1 - ..\..\src\memheap.c + ../../src/memheap.c mempool.c 1 - ..\..\src\mempool.c + ../../src/mempool.c object.c 1 - ..\..\src\object.c + ../../src/object.c scheduler.c 1 - ..\..\src\scheduler.c + ../../src/scheduler.c signal.c 1 - ..\..\src\signal.c + ../../src/signal.c thread.c 1 - ..\..\src\thread.c + ../../src/thread.c timer.c 1 - ..\..\src\timer.c + ../../src/timer.c @@ -494,21 +487,21 @@ application.c 1 - applications\application.c + applications/application.c mnt.c 1 - applications\mnt.c + applications/mnt.c startup.c 1 - applications\startup.c + applications/startup.c @@ -518,84 +511,395 @@ board.c 1 - drivers\board.c + drivers/board.c clock_config.c 1 - drivers\clock_config.c + drivers/clock_config.c drt_mpu.c 1 - drivers\drt_mpu.c + drivers/drt_mpu.c drv_emac.c 1 - drivers\drv_emac.c + drivers/drv_emac.c drv_ft5406.c 1 - drivers\drv_ft5406.c + drivers/drv_ft5406.c drv_i2c.c 1 - drivers\drv_i2c.c + drivers/drv_i2c.c drv_lcd.c 1 - drivers\drv_lcd.c + drivers/drv_lcd.c drv_sd.c 1 - drivers\drv_sd.c + drivers/drv_sd.c drv_sdram.c 1 - drivers\drv_sdram.c + drivers/drv_sdram.c drv_sram.c 1 - drivers\drv_sram.c + drivers/drv_sram.c drv_uart.c 1 - drivers\drv_uart.c + drivers/drv_uart.c fsl_phy.c 1 - drivers\fsl_phy.c + drivers/fsl_phy.c + + + + + Libraries + + + fsl_sd.c + 1 + SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/src/fsl_sd.c + + + + + fsl_sdmmc.c + 1 + SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/src/fsl_sdmmc.c + + + + + fsl_host.c + 1 + SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/src/fsl_host.c + + + + + fsl_sd_event.c + 1 + SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/src/fsl_sd_event.c + + + + + fsl_adc.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_adc.c + + + + + fsl_clock.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_clock.c + + + + + fsl_common.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_common.c + + + + + fsl_crc.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_crc.c + + + + + fsl_ctimer.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_ctimer.c + + + + + fsl_dma.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_dma.c + + + + + fsl_dmic.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_dmic.c + + + + + fsl_dmic_dma.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_dmic_dma.c + + + + + fsl_eeprom.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_eeprom.c + + + + + fsl_emc.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_emc.c + + + + + fsl_enet.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_enet.c + + + + + fsl_flashiap.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_flashiap.c + + + + + fsl_flexcomm.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_flexcomm.c + + + + + fsl_fmc.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_fmc.c + + + + + fsl_fmeas.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_fmeas.c + + + + + fsl_gint.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_gint.c + + + + + fsl_gpio.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_gpio.c + + + + + fsl_i2c.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_i2c.c + + + + + fsl_i2c_dma.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_i2c_dma.c + + + + + fsl_i2s.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_i2s.c + + + + + fsl_i2s_dma.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_i2s_dma.c + + + + + fsl_inputmux.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_inputmux.c + + + + + fsl_lcdc.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_lcdc.c + + + + + fsl_mcan.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_mcan.c + + + + + fsl_mrt.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_mrt.c + + + + + fsl_pint.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_pint.c + + + + + fsl_power.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_power.c + + + + + fsl_reset.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_reset.c + + + + + fsl_rit.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_rit.c + + + + + fsl_rtc.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_rtc.c + + + + + fsl_sctimer.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_sctimer.c + + + + + fsl_sdif.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_sdif.c + + + + + fsl_spi.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_spi.c + + + + + fsl_spi_dma.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_spi_dma.c + + + + + fsl_spifi.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_spifi.c + + + + + fsl_spifi_dma.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_spifi_dma.c + + + + + fsl_usart.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_usart.c + + + + + fsl_usart_dma.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_usart_dma.c + + + + + fsl_utick.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_utick.c + + + + + fsl_wwdt.c + 1 + SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_wwdt.c @@ -605,332 +909,21 @@ startup_LPC54608.s 2 - SDK_2.2_LPCXpresso54608\devices\LPC54608\arm\startup_LPC54608.s + SDK_2.2_LPCXpresso54608/devices/LPC54608/arm/startup_LPC54608.s system_LPC54608.c 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\system_LPC54608.c + SDK_2.2_LPCXpresso54608/devices/LPC54608/system_LPC54608.c keil_lib_power.lib 4 - SDK_2.2_LPCXpresso54608\devices\LPC54608\arm\keil_lib_power.lib - - - - - Libraries - - - fsl_adc.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_adc.c - - - - - fsl_clock.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_clock.c - - - - - fsl_common.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_common.c - - - - - fsl_crc.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_crc.c - - - - - fsl_ctimer.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_ctimer.c - - - - - fsl_dma.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_dma.c - - - - - fsl_dmic.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_dmic.c - - - - - fsl_dmic_dma.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_dmic_dma.c - - - - - fsl_eeprom.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_eeprom.c - - - - - fsl_emc.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_emc.c - - - - - fsl_enet.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_enet.c - - - - - fsl_flashiap.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_flashiap.c - - - - - fsl_flexcomm.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_flexcomm.c - - - - - fsl_fmc.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_fmc.c - - - - - fsl_fmeas.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_fmeas.c - - - - - fsl_gint.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_gint.c - - - - - fsl_gpio.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_gpio.c - - - - - fsl_i2c.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_i2c.c - - - - - fsl_i2c_dma.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_i2c_dma.c - - - - - fsl_i2s.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_i2s.c - - - - - fsl_i2s_dma.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_i2s_dma.c - - - - - fsl_inputmux.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_inputmux.c - - - - - fsl_lcdc.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_lcdc.c - - - - - fsl_mcan.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_mcan.c - - - - - fsl_mrt.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_mrt.c - - - - - fsl_pint.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_pint.c - - - - - fsl_power.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_power.c - - - - - fsl_reset.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_reset.c - - - - - fsl_rit.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_rit.c - - - - - fsl_rtc.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_rtc.c - - - - - fsl_sctimer.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_sctimer.c - - - - - fsl_sdif.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_sdif.c - - - - - fsl_spi.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_spi.c - - - - - fsl_spi_dma.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_spi_dma.c - - - - - fsl_spifi.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_spifi.c - - - - - fsl_spifi_dma.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_spifi_dma.c - - - - - fsl_usart.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_usart.c - - - - - fsl_usart_dma.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_usart_dma.c - - - - - fsl_utick.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_utick.c - - - - - fsl_wwdt.c - 1 - SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_wwdt.c - - - - - fsl_sd.c - 1 - SDK_2.2_LPCXpresso54608\sdmmc_2.1.2\src\fsl_sd.c - - - - - fsl_sdmmc.c - 1 - SDK_2.2_LPCXpresso54608\sdmmc_2.1.2\src\fsl_sdmmc.c - - - - - fsl_host.c - 1 - SDK_2.2_LPCXpresso54608\sdmmc_2.1.2\src\fsl_host.c - - - - - fsl_sd_event.c - 1 - SDK_2.2_LPCXpresso54608\sdmmc_2.1.2\src\fsl_sd_event.c + SDK_2.2_LPCXpresso54608/devices/LPC54608/arm/keil_lib_power.lib @@ -940,73 +933,136 @@ backtrace.c 1 - ..\..\libcpu\arm\common\backtrace.c + ../../libcpu/arm/common/backtrace.c div0.c 1 - ..\..\libcpu\arm\common\div0.c + ../../libcpu/arm/common/div0.c showmem.c 1 - ..\..\libcpu\arm\common\showmem.c + ../../libcpu/arm/common/showmem.c cpuport.c 1 - ..\..\libcpu\arm\cortex-m4\cpuport.c + ../../libcpu/arm/cortex-m4/cpuport.c context_rvds.S 2 - ..\..\libcpu\arm\cortex-m4\context_rvds.S + ../../libcpu/arm/cortex-m4/context_rvds.S - CPlusPlus + finsh - Mutex.cpp - 8 - ..\..\components\cplusplus\Mutex.cpp - - - - - Semaphore.cpp - 8 - ..\..\components\cplusplus\Semaphore.cpp - - - - - Thread.cpp - 8 - ..\..\components\cplusplus\Thread.cpp - - - - - crt.cpp - 8 - ..\..\components\cplusplus\crt.cpp - - - - - crt_init.c + shell.c 1 - ..\..\components\cplusplus\crt_init.c + ../../components/finsh/shell.c + + + + + cmd.c + 1 + ../../components/finsh/cmd.c + + + + + msh.c + 1 + ../../components/finsh/msh.c + + + + + msh_file.c + 1 + ../../components/finsh/msh_file.c + + + + + finsh_compiler.c + 1 + ../../components/finsh/finsh_compiler.c + + + + + finsh_error.c + 1 + ../../components/finsh/finsh_error.c + + + + + finsh_heap.c + 1 + ../../components/finsh/finsh_heap.c + + + + + finsh_init.c + 1 + ../../components/finsh/finsh_init.c + + + + + finsh_node.c + 1 + ../../components/finsh/finsh_node.c + + + + + finsh_ops.c + 1 + ../../components/finsh/finsh_ops.c + + + + + finsh_parser.c + 1 + ../../components/finsh/finsh_parser.c + + + + + finsh_var.c + 1 + ../../components/finsh/finsh_var.c + + + + + finsh_vm.c + 1 + ../../components/finsh/finsh_vm.c + + + + + finsh_token.c + 1 + ../../components/finsh/finsh_token.c @@ -1016,213 +1072,530 @@ dfs.c 1 - ..\..\components\dfs\src\dfs.c + ../../components/dfs/src/dfs.c dfs_file.c 1 - ..\..\components\dfs\src\dfs_file.c + ../../components/dfs/src/dfs_file.c dfs_fs.c 1 - ..\..\components\dfs\src\dfs_fs.c + ../../components/dfs/src/dfs_fs.c dfs_posix.c 1 - ..\..\components\dfs\src\dfs_posix.c + ../../components/dfs/src/dfs_posix.c poll.c 1 - ..\..\components\dfs\src\poll.c + ../../components/dfs/src/poll.c select.c 1 - ..\..\components\dfs\src\select.c - - - - - devfs.c - 1 - ..\..\components\dfs\filesystems\devfs\devfs.c + ../../components/dfs/src/select.c dfs_elm.c 1 - ..\..\components\dfs\filesystems\elmfat\dfs_elm.c + ../../components/dfs/filesystems/elmfat/dfs_elm.c ff.c 1 - ..\..\components\dfs\filesystems\elmfat\ff.c + ../../components/dfs/filesystems/elmfat/ff.c + + + + + devfs.c + 1 + ../../components/dfs/filesystems/devfs/devfs.c + + + + + lwIP + + + sys_arch.c + 1 + ../../components/net/lwip-2.0.2/src/arch/sys_arch.c + + + + + api_lib.c + 1 + ../../components/net/lwip-2.0.2/src/api/api_lib.c + + + + + api_msg.c + 1 + ../../components/net/lwip-2.0.2/src/api/api_msg.c + + + + + err.c + 1 + ../../components/net/lwip-2.0.2/src/api/err.c + + + + + netbuf.c + 1 + ../../components/net/lwip-2.0.2/src/api/netbuf.c + + + + + netdb.c + 1 + ../../components/net/lwip-2.0.2/src/api/netdb.c + + + + + netifapi.c + 1 + ../../components/net/lwip-2.0.2/src/api/netifapi.c + + + + + sockets.c + 1 + ../../components/net/lwip-2.0.2/src/api/sockets.c + + + + + tcpip.c + 1 + ../../components/net/lwip-2.0.2/src/api/tcpip.c + + + + + def.c + 1 + ../../components/net/lwip-2.0.2/src/core/def.c + + + + + dns.c + 1 + ../../components/net/lwip-2.0.2/src/core/dns.c + + + + + inet_chksum.c + 1 + ../../components/net/lwip-2.0.2/src/core/inet_chksum.c + + + + + init.c + 1 + ../../components/net/lwip-2.0.2/src/core/init.c + + + + + ip.c + 1 + ../../components/net/lwip-2.0.2/src/core/ip.c + + + + + memp.c + 1 + ../../components/net/lwip-2.0.2/src/core/memp.c + + + + + netif.c + 1 + ../../components/net/lwip-2.0.2/src/core/netif.c + + + + + pbuf.c + 1 + ../../components/net/lwip-2.0.2/src/core/pbuf.c + + + + + raw.c + 1 + ../../components/net/lwip-2.0.2/src/core/raw.c + + + + + stats.c + 1 + ../../components/net/lwip-2.0.2/src/core/stats.c + + + + + sys.c + 1 + ../../components/net/lwip-2.0.2/src/core/sys.c + + + + + tcp.c + 1 + ../../components/net/lwip-2.0.2/src/core/tcp.c + + + + + tcp_in.c + 1 + ../../components/net/lwip-2.0.2/src/core/tcp_in.c + + + + + tcp_out.c + 1 + ../../components/net/lwip-2.0.2/src/core/tcp_out.c + + + + + timeouts.c + 1 + ../../components/net/lwip-2.0.2/src/core/timeouts.c + + + + + udp.c + 1 + ../../components/net/lwip-2.0.2/src/core/udp.c + + + + + ethernet.c + 1 + ../../components/net/lwip-2.0.2/src/netif/ethernet.c + + + + + ethernetif.c + 1 + ../../components/net/lwip-2.0.2/src/netif/ethernetif.c + + + + + lowpan6.c + 1 + ../../components/net/lwip-2.0.2/src/netif/lowpan6.c + + + + + autoip.c + 1 + ../../components/net/lwip-2.0.2/src/core/ipv4/autoip.c + + + + + dhcp.c + 1 + ../../components/net/lwip-2.0.2/src/core/ipv4/dhcp.c + + + + + etharp.c + 1 + ../../components/net/lwip-2.0.2/src/core/ipv4/etharp.c + + + + + icmp.c + 1 + ../../components/net/lwip-2.0.2/src/core/ipv4/icmp.c + + + + + igmp.c + 1 + ../../components/net/lwip-2.0.2/src/core/ipv4/igmp.c + + + + + ip4.c + 1 + ../../components/net/lwip-2.0.2/src/core/ipv4/ip4.c + + + + + ip4_addr.c + 1 + ../../components/net/lwip-2.0.2/src/core/ipv4/ip4_addr.c + + + + + ip4_frag.c + 1 + ../../components/net/lwip-2.0.2/src/core/ipv4/ip4_frag.c + + + + + ping.c + 1 + ../../components/net/lwip-2.0.2/src/apps/ping/ping.c + + + + + netdev + + + netdev.c + 1 + ../../components/net/netdev/src/netdev.c + + + + + netdev_ipaddr.c + 1 + ../../components/net/netdev/src/netdev_ipaddr.c + + + + + SAL + + + sal_socket.c + 1 + ../../components/net/sal_socket/src/sal_socket.c + + + + + net_netdb.c + 1 + ../../components/net/sal_socket/socket/net_netdb.c + + + + + af_inet_lwip.c + 1 + ../../components/net/sal_socket/impl/af_inet_lwip.c + + + + + net_sockets.c + 1 + ../../components/net/sal_socket/socket/net_sockets.c + + + + + dfs_net.c + 1 + ../../components/net/sal_socket/dfs_net/dfs_net.c DeviceDrivers - - - i2c_core.c - 1 - ..\..\components\drivers\i2c\i2c_core.c - - - - - i2c_dev.c - 1 - ..\..\components\drivers\i2c\i2c_dev.c - - - - - i2c-bit-ops.c - 1 - ..\..\components\drivers\i2c\i2c-bit-ops.c - - - - - pin.c - 1 - ..\..\components\drivers\misc\pin.c - - - - - mtd_nand.c - 1 - ..\..\components\drivers\mtd\mtd_nand.c - - - - - rtc.c - 1 - ..\..\components\drivers\rtc\rtc.c - - block_dev.c 1 - ..\..\components\drivers\sdio\block_dev.c + ../../components/drivers/sdio/block_dev.c mmcsd_core.c 1 - ..\..\components\drivers\sdio\mmcsd_core.c + ../../components/drivers/sdio/mmcsd_core.c sd.c 1 - ..\..\components\drivers\sdio\sd.c + ../../components/drivers/sdio/sd.c sdio.c 1 - ..\..\components\drivers\sdio\sdio.c + ../../components/drivers/sdio/sdio.c mmc.c 1 - ..\..\components\drivers\sdio\mmc.c + ../../components/drivers/sdio/mmc.c - serial.c + rtc.c 1 - ..\..\components\drivers\serial\serial.c + ../../components/drivers/rtc/rtc.c spi_core.c 1 - ..\..\components\drivers\spi\spi_core.c + ../../components/drivers/spi/spi_core.c spi_dev.c 1 - ..\..\components\drivers\spi\spi_dev.c + ../../components/drivers/spi/spi_dev.c + + + + + i2c_core.c + 1 + ../../components/drivers/i2c/i2c_core.c + + + + + i2c_dev.c + 1 + ../../components/drivers/i2c/i2c_dev.c + + + + + i2c-bit-ops.c + 1 + ../../components/drivers/i2c/i2c-bit-ops.c + + + + + serial.c + 1 + ../../components/drivers/serial/serial.c completion.c 1 - ..\..\components\drivers\src\completion.c + ../../components/drivers/src/completion.c dataqueue.c 1 - ..\..\components\drivers\src\dataqueue.c + ../../components/drivers/src/dataqueue.c pipe.c 1 - ..\..\components\drivers\src\pipe.c + ../../components/drivers/src/pipe.c ringblk_buf.c 1 - ..\..\components\drivers\src\ringblk_buf.c + ../../components/drivers/src/ringblk_buf.c ringbuffer.c 1 - ..\..\components\drivers\src\ringbuffer.c + ../../components/drivers/src/ringbuffer.c waitqueue.c 1 - ..\..\components\drivers\src\waitqueue.c + ../../components/drivers/src/waitqueue.c workqueue.c 1 - ..\..\components\drivers\src\workqueue.c + ../../components/drivers/src/workqueue.c + + + + + mtd_nand.c + 1 + ../../components/drivers/mtd/mtd_nand.c + + + + + pin.c + 1 + ../../components/drivers/misc/pin.c @@ -1239,103 +1612,40 @@ - finsh + CPlusPlus - shell.c - 1 - ..\..\components\finsh\shell.c + cxx_Mutex.cpp + 8 + ../../components/cplusplus/cxx_Mutex.cpp - cmd.c - 1 - ..\..\components\finsh\cmd.c + cxx_Semaphore.cpp + 8 + ../../components/cplusplus/cxx_Semaphore.cpp - msh.c - 1 - ..\..\components\finsh\msh.c + cxx_Thread.cpp + 8 + ../../components/cplusplus/cxx_Thread.cpp - msh_file.c - 1 - ..\..\components\finsh\msh_file.c + cxx_crt.cpp + 8 + ../../components/cplusplus/cxx_crt.cpp - finsh_compiler.c + crt_init.c 1 - ..\..\components\finsh\finsh_compiler.c - - - - - finsh_error.c - 1 - ..\..\components\finsh\finsh_error.c - - - - - finsh_heap.c - 1 - ..\..\components\finsh\finsh_heap.c - - - - - finsh_init.c - 1 - ..\..\components\finsh\finsh_init.c - - - - - finsh_node.c - 1 - ..\..\components\finsh\finsh_node.c - - - - - finsh_ops.c - 1 - ..\..\components\finsh\finsh_ops.c - - - - - finsh_parser.c - 1 - ..\..\components\finsh\finsh_parser.c - - - - - finsh_var.c - 1 - ..\..\components\finsh\finsh_var.c - - - - - finsh_vm.c - 1 - ..\..\components\finsh\finsh_vm.c - - - - - finsh_token.c - 1 - ..\..\components\finsh\finsh_token.c + ../../components/cplusplus/crt_init.c @@ -1345,35 +1655,35 @@ libc.c 1 - ..\..\components\libc\compilers\armlibc\libc.c + ../../components/libc/compilers/armlibc/libc.c mem_std.c 1 - ..\..\components\libc\compilers\armlibc\mem_std.c + ../../components/libc/compilers/armlibc/mem_std.c stdio.c 1 - ..\..\components\libc\compilers\armlibc\stdio.c + ../../components/libc/compilers/armlibc/stdio.c stubs.c 1 - ..\..\components\libc\compilers\armlibc\stubs.c + ../../components/libc/compilers/armlibc/stubs.c time.c 1 - ..\..\components\libc\compilers\common\time.c + ../../components/libc/compilers/common/time.c @@ -1383,408 +1693,91 @@ mqueue.c 1 - ..\..\components\libc\pthreads\mqueue.c + ../../components/libc/pthreads/mqueue.c pthread.c 1 - ..\..\components\libc\pthreads\pthread.c + ../../components/libc/pthreads/pthread.c pthread_attr.c 1 - ..\..\components\libc\pthreads\pthread_attr.c + ../../components/libc/pthreads/pthread_attr.c pthread_barrier.c 1 - ..\..\components\libc\pthreads\pthread_barrier.c + ../../components/libc/pthreads/pthread_barrier.c pthread_cond.c 1 - ..\..\components\libc\pthreads\pthread_cond.c + ../../components/libc/pthreads/pthread_cond.c pthread_mutex.c 1 - ..\..\components\libc\pthreads\pthread_mutex.c + ../../components/libc/pthreads/pthread_mutex.c pthread_rwlock.c 1 - ..\..\components\libc\pthreads\pthread_rwlock.c + ../../components/libc/pthreads/pthread_rwlock.c pthread_spin.c 1 - ..\..\components\libc\pthreads\pthread_spin.c + ../../components/libc/pthreads/pthread_spin.c pthread_tls.c 1 - ..\..\components\libc\pthreads\pthread_tls.c + ../../components/libc/pthreads/pthread_tls.c sched.c 1 - ..\..\components\libc\pthreads\sched.c + ../../components/libc/pthreads/sched.c semaphore.c 1 - ..\..\components\libc\pthreads\semaphore.c + ../../components/libc/pthreads/semaphore.c clock_time.c 1 - ..\..\components\libc\time\clock_time.c + ../../components/libc/time/clock_time.c posix_sleep.c 1 - ..\..\components\libc\time\posix_sleep.c - - - - - lwIP - - - sys_arch.c - 1 - ..\..\components\net\lwip-2.0.2\src\arch\sys_arch.c - - - - - api_lib.c - 1 - ..\..\components\net\lwip-2.0.2\src\api\api_lib.c - - - - - api_msg.c - 1 - ..\..\components\net\lwip-2.0.2\src\api\api_msg.c - - - - - err.c - 1 - ..\..\components\net\lwip-2.0.2\src\api\err.c - - - - - netbuf.c - 1 - ..\..\components\net\lwip-2.0.2\src\api\netbuf.c - - - - - netdb.c - 1 - ..\..\components\net\lwip-2.0.2\src\api\netdb.c - - - - - netifapi.c - 1 - ..\..\components\net\lwip-2.0.2\src\api\netifapi.c - - - - - sockets.c - 1 - ..\..\components\net\lwip-2.0.2\src\api\sockets.c - - - - - tcpip.c - 1 - ..\..\components\net\lwip-2.0.2\src\api\tcpip.c - - - - - def.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\def.c - - - - - dns.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\dns.c - - - - - inet_chksum.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\inet_chksum.c - - - - - init.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\init.c - - - - - ip.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ip.c - - - - - memp.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\memp.c - - - - - netif.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\netif.c - - - - - pbuf.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\pbuf.c - - - - - raw.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\raw.c - - - - - stats.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\stats.c - - - - - sys.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\sys.c - - - - - tcp.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\tcp.c - - - - - tcp_in.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\tcp_in.c - - - - - tcp_out.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\tcp_out.c - - - - - timeouts.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\timeouts.c - - - - - udp.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\udp.c - - - - - ethernet.c - 1 - ..\..\components\net\lwip-2.0.2\src\netif\ethernet.c - - - - - ethernetif.c - 1 - ..\..\components\net\lwip-2.0.2\src\netif\ethernetif.c - - - - - lowpan6.c - 1 - ..\..\components\net\lwip-2.0.2\src\netif\lowpan6.c - - - - - autoip.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\autoip.c - - - - - dhcp.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\dhcp.c - - - - - etharp.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\etharp.c - - - - - icmp.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\icmp.c - - - - - igmp.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\igmp.c - - - - - ip4.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4.c - - - - - ip4_addr.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4_addr.c - - - - - ip4_frag.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4_frag.c - - - - - ping.c - 1 - ..\..\components\net\lwip-2.0.2\src\apps\ping\ping.c - - - - - netdev - - - netdev.c - 1 - ..\..\components\net\netdev\src\netdev.c - - - - - netdev_ipaddr.c - 1 - ..\..\components\net\netdev\src\netdev_ipaddr.c - - - - - SAL - - - sal_socket.c - 1 - ..\..\components\net\sal_socket\src\sal_socket.c - - - - - net_netdb.c - 1 - ..\..\components\net\sal_socket\socket\net_netdb.c - - - - - af_inet_lwip.c - 1 - ..\..\components\net\sal_socket\impl\af_inet_lwip.c - - - - - net_sockets.c - 1 - ..\..\components\net\sal_socket\socket\net_sockets.c - - - - - dfs_net.c - 1 - ..\..\components\net\sal_socket\dfs_net\dfs_net.c + ../../components/libc/time/posix_sleep.c diff --git a/bsp/lpc55sxx/tools/sdk_dist.py b/bsp/lpc55sxx/tools/sdk_dist.py index 9254b1b589..a69c8f2db1 100644 --- a/bsp/lpc55sxx/tools/sdk_dist.py +++ b/bsp/lpc55sxx/tools/sdk_dist.py @@ -8,7 +8,7 @@ sys.path.append(os.path.join(os.path.dirname(cwd_path), 'rt-thread', 'tools')) def dist_do_building(BSP_ROOT): from mkdist import bsp_copy_files import rtconfig - + dist_dir = os.path.join(BSP_ROOT, 'dist', os.path.basename(BSP_ROOT)) library_path = os.path.join(os.path.dirname(BSP_ROOT), 'Libraries') library_dir = os.path.join(dist_dir, 'Libraries') diff --git a/bsp/nrf5x/libraries/drivers/SConscript b/bsp/nrf5x/libraries/drivers/SConscript index 1bd5bdb0a9..8e04139a8c 100644 --- a/bsp/nrf5x/libraries/drivers/SConscript +++ b/bsp/nrf5x/libraries/drivers/SConscript @@ -10,8 +10,12 @@ src = Split(""" if GetDepend(['BSP_USING_UART']): src += ['drv_uart.c'] + +if GetDepend(['BSP_USING_ON_CHIP_FLASH']): + src += ['drv_flash.c'] -# src += ['drv_common.c'] +if GetDepend(['BSP_USING_QSPI_FLASH']): + src += ['drv_qspi_flash.c'] path = [cwd] diff --git a/bsp/nrf5x/libraries/drivers/drv_flash.c b/bsp/nrf5x/libraries/drivers/drv_flash.c new file mode 100644 index 0000000000..727bbeda78 --- /dev/null +++ b/bsp/nrf5x/libraries/drivers/drv_flash.c @@ -0,0 +1,188 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-04-29 supperthomas first version + */ + +#include "board.h" +#include +#include "nrfx_nvmc.h" + +#ifdef BSP_USING_ON_CHIP_FLASH + +#if defined(PKG_USING_FAL) +#include "fal.h" +#endif + +#include +#define LOG_TAG "drv.flash" + + + +/** + * @brief Gets the page of a given address + * @param Addr: Address of the FLASH Memory + * @retval The page of a given address + */ +static uint32_t GetPage(uint32_t Addr) +{ + uint32_t page = 0; + if (Addr < (MCU_FLASH_START_ADDRESS + MCU_FLASH_SIZE)) + { + page = (Addr - MCU_FLASH_START_ADDRESS) / MCU_FLASH_PAGE_SIZE; + } + else + { + return 0xffffffff; + } + return page; +} + + +/** + * Read data from flash. + * @note This operation's units is word. + * + * @param addr flash address + * @param buf buffer to store read data + * @param size read bytes size + * + * @return result + */ +int mcu_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size) +{ + + size_t i; + + if ((addr + size) > MCU_FLASH_END_ADDRESS) + { + LOG_E("read outrange flash size! addr is (0x%p)", (void *)(addr + size)); + return -RT_EINVAL; + } + + for (i = 0; i < size; i++, buf++, addr++) + { + *buf = *(rt_uint8_t *) addr; + } + + return size; +} + +/** + * Write data to flash. + * @note This operation's units is word. + * @note This operation must after erase. @see flash_erase. + * + * @param addr flash address + * @param buf the write data buffer + * @param size write bytes size + * + * @return result + */ +int mcu_flash_write(rt_uint32_t addr, const uint8_t *buf, size_t size) +{ + if ((addr + size) > MCU_FLASH_END_ADDRESS) + { + LOG_E("ERROR: write outrange flash size! addr is (0x%p)\n", (void *)(addr + size)); + return -RT_EINVAL; + } + + + if (addr % 4 != 0) + { + LOG_E("write addr should be 4-byte alignment"); + //4byte write + //else byts + return -RT_EINVAL; + } + + if (size < 1) + { + return -RT_ERROR; + } + if (size % 4 != 0) + { + nrfx_nvmc_bytes_write(addr, buf, size); + return size; + } + else + { + nrfx_nvmc_words_write(addr, buf, size / 4); + return size; + } + +} + +/** + * Erase data on flash. + * @note This operation is irreversible. + * @note This operation's units is different which on many chips. + * + * @param addr flash address + * @param size erase bytes size + * + * @return result + */ +int mcu_flash_erase(rt_uint32_t addr, size_t size) +{ + nrfx_err_t result = RT_EOK; + + uint32_t FirstPage = 0, NbOfPages = 0; + + if ((addr + size) > MCU_FLASH_END_ADDRESS) + { + LOG_E("ERROR: erase outrange flash size! addr is (0x%p)\n", (void *)(addr + size)); + return -RT_EINVAL; + } + + FirstPage = GetPage(addr); + NbOfPages = GetPage(addr + size - 1) - FirstPage + 1; + + for (int i = 0; i < NbOfPages ; i++) + { + result = nrfx_nvmc_page_erase((FirstPage + i) * MCU_FLASH_PAGE_SIZE); + if (NRFX_SUCCESS != result) + { + LOG_E("ERROR: erase flash page %d ! error code is (%x)\n", FirstPage + i, result); + return -RT_EINVAL; + } + } + LOG_D("erase done: addr (0x%p), size %d", (void *)addr, NbOfPages * MCU_FLASH_PAGE_SIZE); + return size; +} + +#if defined(PKG_USING_FAL) + +static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size); +static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size); +static int fal_flash_erase(long offset, size_t size); + +static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size) +{ + return mcu_flash_read(mcu_onchip_flash.addr + offset, buf, size); +} + +static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size) +{ + return mcu_flash_write(mcu_onchip_flash.addr + offset, buf, size); +} + +static int fal_flash_erase(long offset, size_t size) +{ + return mcu_flash_erase(mcu_onchip_flash.addr + offset, size); +} +const struct fal_flash_dev mcu_onchip_flash = +{ + .name = ON_CHIP_FLASH_DEV_NAME, + .addr = MCU_FLASH_START_ADDRESS, + .len = MCU_FLASH_SIZE, + .blk_size = MCU_FLASH_PAGE_SIZE, + .ops = {NULL, fal_flash_read, fal_flash_write, fal_flash_erase}, + .write_gran = 8 +}; +#endif +#endif /* BSP_USING_ON_CHIP_FLASH */ diff --git a/bsp/nrf5x/libraries/drivers/drv_qspi_flash.c b/bsp/nrf5x/libraries/drivers/drv_qspi_flash.c new file mode 100644 index 0000000000..18e6671a96 --- /dev/null +++ b/bsp/nrf5x/libraries/drivers/drv_qspi_flash.c @@ -0,0 +1,153 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-04-29 supperthomas first version + * + */ +#include +#include "board.h" +#include "nrfx_qspi.h" +#if defined(PKG_USING_FAL) +#include + +//log +#include +#define LOG_TAG "drv.qspiflash" + +#define WAIT_FOR_PERIPH() do { \ + while (!m_finished) {} \ + m_finished = false; \ + } while (0) + +static volatile bool m_finished = false; +static void qspi_handler(nrfx_qspi_evt_t event, void *p_context) +{ + m_finished = true; +} + +static void configure_memory() +{ +#define QSPI_STD_CMD_WRSR 0x01 +#define QSPI_STD_CMD_RSTEN 0x66 +#define QSPI_STD_CMD_RST 0x99 + + uint8_t temporary = 0x40; + uint32_t err_code; + nrf_qspi_cinstr_conf_t cinstr_cfg = + { + .opcode = QSPI_STD_CMD_RSTEN, + .length = NRF_QSPI_CINSTR_LEN_1B, + .io2_level = true, + .io3_level = true, + .wipwait = true, + .wren = true + }; + + // Send reset enable + err_code = nrfx_qspi_cinstr_xfer(&cinstr_cfg, NULL, NULL); + if (NRFX_SUCCESS != err_code) + { + LOG_E("\r\n ERROR: QSPI_STD_CMD_RSTEN:0x%x\n", err_code); + return ; + } + // Send reset command + cinstr_cfg.opcode = QSPI_STD_CMD_RST; + err_code = nrfx_qspi_cinstr_xfer(&cinstr_cfg, NULL, NULL); + if (NRFX_SUCCESS != err_code) + { + LOG_E("\r\n ERROR: QSPI_STD_CMD_RST:0x%x\n", err_code); + return ; + } + + // Switch to qspi mode + cinstr_cfg.opcode = QSPI_STD_CMD_WRSR; + cinstr_cfg.length = NRF_QSPI_CINSTR_LEN_2B; + err_code = nrfx_qspi_cinstr_xfer(&cinstr_cfg, &temporary, NULL); + if (NRFX_SUCCESS != err_code) + { + LOG_E("\r\n ERROR: QSPI_STD_CMD_WRSR:0x%x\n", err_code); + return; + } +} +static int init(void) +{ + uint32_t err_code; + nrfx_qspi_config_t config = NRFX_QSPI_DEFAULT_CONFIG(BSP_QSPI_SCK_PIN, BSP_QSPI_CSN_PIN, + BSP_QSPI_IO0_PIN, BSP_QSPI_IO1_PIN, BSP_QSPI_IO2_PIN, BSP_QSPI_IO3_PIN); + + err_code = nrfx_qspi_init(&config, qspi_handler, NULL); + if (NRFX_SUCCESS != err_code) + { + LOG_E("\r\n ERROR: QSPI_init:0x%x\n", err_code); + return -1; + } + configure_memory(); + return 0; +} + +static int read(long offset, uint8_t *buf, size_t size) +{ + uint32_t err_code; + m_finished = false; + err_code = nrfx_qspi_read(buf, size, offset); + WAIT_FOR_PERIPH(); + if (NRFX_SUCCESS == err_code) + { + return size; + } + else + { + LOG_E("\r\n ERROR: read:0x%x\n", err_code); + return -1; + } +} + +static int write(long offset, const uint8_t *buf, size_t size) +{ + uint32_t err_code; + m_finished = false; + err_code = nrfx_qspi_write(buf, size, offset); + WAIT_FOR_PERIPH(); + if (NRFX_SUCCESS == err_code) + { + return size; + } + else + { + LOG_E("\r\n ERROR: write:0x%x\n", err_code); + return -1; + } +} + +static int erase(long offset, size_t size) +{ + uint32_t err_code; + m_finished = false; + err_code = nrfx_qspi_erase(NRF_QSPI_ERASE_LEN_64KB, offset); + WAIT_FOR_PERIPH(); + if (NRFX_SUCCESS == err_code) + { + return size; + } + else + { + LOG_E("\r\n ERROR: erase:0x%x\n", err_code); + return -1; + } +} + +struct fal_flash_dev nor_flash0 = +{ + .name = NOR_FLASH_DEV_NAME, + .addr = 0, + .len = QSPI_FLASH_SIZE_KB * 1024, + .blk_size = 4096, + .ops = {init, read, write, erase}, + .write_gran = 1 +}; + +#endif diff --git a/bsp/nrf5x/libraries/drivers/drv_uart.c b/bsp/nrf5x/libraries/drivers/drv_uart.c index b310fa57a4..08c7148353 100644 --- a/bsp/nrf5x/libraries/drivers/drv_uart.c +++ b/bsp/nrf5x/libraries/drivers/drv_uart.c @@ -1,59 +1,83 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-04-28 xckhmf Modify for + * + */ #include #include #include "drv_uart.h" -static struct rt_serial_device _serial0_0; -static void uart_event_hander(nrfx_uart_event_t const *p_event,void *p_context); +#ifdef BSP_USING_UART typedef struct { struct rt_serial_device *serial; nrfx_uart_t uart; + uint8_t rx_byte; + uint16_t rx_length; uint32_t rx_pin; uint32_t tx_pin; nrfx_uart_event_handler_t event_handler; -} UART_CFG_T; +} drv_uart_cfg_t; - -UART_CFG_T uart0 = { +#ifdef BSP_USING_UART0 +static struct rt_serial_device _serial_0; +static void uart0_event_hander(nrfx_uart_event_t const *p_event,void *p_context); +drv_uart_cfg_t m_uart0_cfg = { .uart = NRFX_UART_INSTANCE(0), -#ifdef RT_USING_CONSOLE - .rx_pin = 8, - .tx_pin = 6, - .event_handler = uart_event_hander, -#else - .rx_pin = 19, - .tx_pin = 20 -#endif + .rx_byte = 0, + .rx_length = 0, + .rx_pin = BSP_UART0_RX_PIN, + .tx_pin = BSP_UART0_TX_PIN, + .event_handler = uart0_event_hander }; -UART_CFG_T *working_cfg = RT_NULL; +#endif /* BSP_USING_UART0 */ -static void uart_event_hander(nrfx_uart_event_t const *p_event,void *p_context) -{ - +#ifdef BSP_USING_UART1 + #error not support UART1. Use UART0 instead. +#endif /* BSP_USING_UART1 */ + +#ifdef BSP_USING_UART0 +static void uart0_event_hander(nrfx_uart_event_t const *p_event,void *p_context) +{ if (p_event->type == NRFX_UART_EVT_RX_DONE) { - rt_hw_serial_isr(working_cfg->serial, RT_SERIAL_EVENT_RX_IND); + if(p_event->data.rxtx.bytes == 1) + { + m_uart0_cfg.rx_length = p_event->data.rxtx.bytes; + + /* rx_byte equal p_data */ + //m_uart0_cfg.rx_byte = *(p_event->data.rxtx.p_data); + + rt_hw_serial_isr(m_uart0_cfg.serial, RT_SERIAL_EVENT_RX_IND); + } + nrfx_uart_rx(&(m_uart0_cfg.uart),&m_uart0_cfg.rx_byte,1); } if (p_event->type == NRFX_UART_EVT_TX_DONE) { - + /* @TODO:[RT_DEVICE_FLAG_INT_TX]*/ } } +#endif /* BSP_USING_UART0 */ static rt_err_t _uart_cfg(struct rt_serial_device *serial, struct serial_configure *cfg) { - nrfx_uart_config_t config = NRFX_UART_DEFAULT_CONFIG(uart0.tx_pin,uart0.rx_pin); - UART_CFG_T *instance = &uart0; + nrfx_uart_config_t config = NRFX_UART_DEFAULT_CONFIG(BSP_UART0_TX_PIN,BSP_UART0_RX_PIN); + drv_uart_cfg_t *instance = RT_NULL; RT_ASSERT(serial != RT_NULL); RT_ASSERT(cfg != RT_NULL); - - if (serial->parent.user_data != RT_NULL) + + if (serial->parent.user_data == RT_NULL) { - instance = (UART_CFG_T*)serial->parent.user_data; + return -RT_ERROR; } - + instance = (drv_uart_cfg_t*)serial->parent.user_data; nrfx_uart_uninit(&(instance->uart)); switch (cfg->baud_rate) @@ -83,28 +107,23 @@ static rt_err_t _uart_cfg(struct rt_serial_device *serial, struct serial_configu config.hal_cfg.hwfc = NRF_UART_HWFC_DISABLED; config.pselrxd = instance->rx_pin; config.pseltxd = instance->tx_pin; - + nrfx_uart_init(&(instance->uart), &config, instance->event_handler); - - nrf_uart_int_enable(instance->uart.p_reg, NRF_UART_INT_MASK_RXDRDY | NRF_UART_INT_MASK_RXTO | NRF_UART_INT_MASK_ERROR); + nrfx_uart_rx(&(instance->uart),&(instance->rx_byte),1); nrf_uart_int_disable(instance->uart.p_reg, NRF_UART_INT_MASK_TXDRDY); - - nrfx_uart_rx_enable(&(instance->uart)); - - working_cfg = instance; return RT_EOK; } static rt_err_t _uart_ctrl(struct rt_serial_device *serial, int cmd, void *arg) { - UART_CFG_T *instance = working_cfg; - + drv_uart_cfg_t *instance = NULL; RT_ASSERT(serial != RT_NULL); - if (serial->parent.user_data != RT_NULL) + if (serial->parent.user_data == RT_NULL) { - instance = (UART_CFG_T*)serial->parent.user_data; + return -RT_ERROR; } + instance = (drv_uart_cfg_t*)serial->parent.user_data; switch (cmd) { @@ -129,10 +148,7 @@ static rt_err_t _uart_ctrl(struct rt_serial_device *serial, int cmd, void *arg) break; case RT_DEVICE_CTRL_PIN: - if (working_cfg != instance) - { - _uart_cfg(instance->serial, &(instance->serial->config)); - } + _uart_cfg(instance->serial, &(instance->serial->config)); break; case RT_DEVICE_POWERSAVE: @@ -152,13 +168,13 @@ static rt_err_t _uart_ctrl(struct rt_serial_device *serial, int cmd, void *arg) static int _uart_putc(struct rt_serial_device *serial, char c) { - UART_CFG_T *instance = working_cfg; + drv_uart_cfg_t *instance = NULL; int rtn = 1; RT_ASSERT(serial != RT_NULL); if (serial->parent.user_data != RT_NULL) { - instance = (UART_CFG_T*)serial->parent.user_data; + instance = (drv_uart_cfg_t*)serial->parent.user_data; } nrf_uart_event_clear(instance->uart.p_reg, NRF_UART_EVENT_TXDRDY); @@ -171,23 +187,21 @@ static int _uart_putc(struct rt_serial_device *serial, char c) return rtn; } -/* - @note: this function is invaild ,the cause of the problem is [nrfx_uart.c - line 340] -*/ static int _uart_getc(struct rt_serial_device *serial) { int ch = -1; - UART_CFG_T *instance = working_cfg; - + drv_uart_cfg_t *instance = NULL; RT_ASSERT(serial != RT_NULL); if (serial->parent.user_data != RT_NULL) { - instance = (UART_CFG_T*)serial->parent.user_data; + instance = (drv_uart_cfg_t*)serial->parent.user_data; + } + if(instance->rx_length) + { + ch = instance->rx_byte; + instance->rx_length--; } - - ch = (int)(nrf_uart_rxd_get(instance->uart.p_reg)); - return ch; } @@ -202,11 +216,14 @@ void rt_hw_uart_init(void) { struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; - config.bufsz = RT_SERIAL_RB_BUFSZ; - _serial0_0.config = config; - _serial0_0.ops = &_uart_ops; - uart0.serial = &_serial0_0; +#ifdef BSP_USING_UART0 + _serial_0.config = config; + _serial_0.ops = &_uart_ops; + m_uart0_cfg.serial = &_serial_0; + rt_hw_serial_register(&_serial_0, "uart0", \ + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, &m_uart0_cfg); +#endif /* BSP_USING_UART0 */ - rt_hw_serial_register(&_serial0_0, "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, &uart0); } +#endif /* BSP_USING_UART */ diff --git a/bsp/nrf5x/nrf52840/.config b/bsp/nrf5x/nrf52840/.config index 36e39de794..7565108653 100644 --- a/bsp/nrf5x/nrf52840/.config +++ b/bsp/nrf5x/nrf52840/.config @@ -200,6 +200,7 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_MONGOOSE is not set # CONFIG_PKG_USING_MYMQTT is not set # CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set # CONFIG_PKG_USING_JSMN is not set @@ -226,6 +227,7 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set # CONFIG_PKG_USING_PPP_DEVICE is not set # CONFIG_PKG_USING_AT_DEVICE is not set # CONFIG_PKG_USING_ATSRV_SOCKET is not set @@ -302,6 +304,7 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set # CONFIG_PKG_USING_LUNAR_CALENDAR is not set # CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_URLENCODE is not set # # system packages @@ -312,6 +315,12 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_PARTITION is not set # CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FAL_V00500 is not set +# CONFIG_PKG_USING_FAL_V00400 is not set +# CONFIG_PKG_USING_FAL_V00300 is not set +# CONFIG_PKG_USING_FAL_V00200 is not set +# CONFIG_PKG_USING_FAL_V00100 is not set +# CONFIG_PKG_USING_FAL_LATEST_VERSION is not set # CONFIG_PKG_USING_SQLITE is not set # CONFIG_PKG_USING_RTI is not set # CONFIG_PKG_USING_LITTLEVGL2RTT is not set @@ -343,6 +352,11 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_LITTLED is not set # CONFIG_PKG_USING_LKDGUI is not set # CONFIG_PKG_USING_NRF5X_SDK is not set +CONFIG_PKG_USING_NRFX=y +CONFIG_PKG_NRFX_PATH="/packages/peripherals/nrfx" +CONFIG_PKG_USING_NRFX_V210=y +# CONFIG_PKG_USING_NRFX_LATEST_VERSION is not set +CONFIG_PKG_NRFX_VER="v2.1.0" # CONFIG_PKG_USING_WM_LIBRARIES is not set # CONFIG_PKG_USING_KENDRYTE_SDK is not set # CONFIG_PKG_USING_INFRARED is not set @@ -367,11 +381,6 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_BEEP is not set # CONFIG_PKG_USING_EASYBLINK is not set # CONFIG_PKG_USING_PMS_SERIES is not set -CONFIG_PKG_USING_NRFX=y -CONFIG_PKG_NRFX_PATH="/packages/peripherals/nrfx" -CONFIG_PKG_USING_NRFX_V210=y -# CONFIG_PKG_USING_NRFX_LATEST_VERSION is not set -CONFIG_PKG_NRFX_VER="v2.1.0" # # miscellaneous packages @@ -423,6 +432,7 @@ CONFIG_SOC_NRF52840=y # On-chip Peripheral Drivers # # CONFIG_BSP_USING_GPIO is not set +# CONFIG_BSP_USING_ON_CHIP_FLASH is not set CONFIG_BSP_USING_UART=y CONFIG_BSP_USING_UART0=y # CONFIG_BSP_USING_UART1 is not set diff --git a/bsp/nrf5x/nrf52840/board/Kconfig b/bsp/nrf5x/nrf52840/board/Kconfig index b7edace9e8..8e6f6043f8 100644 --- a/bsp/nrf5x/nrf52840/board/Kconfig +++ b/bsp/nrf5x/nrf52840/board/Kconfig @@ -2,17 +2,52 @@ menu "Hardware Drivers Config" config SOC_NRF52840 bool - config SOC_NRF52840 + config SOC_NRF52840 select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN default y menu "Onboard Peripheral Drivers" config BSP_USING_JLINK_TO_USART - bool "Enable JLINK TO USART (uart0)" + bool "Enable JLINK TO USART (uart0|RX_PIN:8|TX_PIN:6)" select BSP_USING_UART select BSP_USING_UART0 default y + + menuconfig BSP_USING_QSPI_FLASH + select PKG_USING_FAL + bool "Enable QSPI FLASH(MX25R64 8MB)" + default n + + if BSP_USING_QSPI_FLASH + config BSP_QSPI_SCK_PIN + int "QSPI SCK pin number" + range 0 31 + default 19 + config BSP_QSPI_CSN_PIN + int "QSPI CSN pin number" + range 0 31 + default 17 + config BSP_QSPI_IO0_PIN + int "QSPI IO0 pin number" + range 0 31 + default 20 + config BSP_QSPI_IO1_PIN + int "QSPI IO1 pin number" + range 0 31 + default 21 + config BSP_QSPI_IO2_PIN + int "QSPI IO2 pin number" + range 0 31 + default 22 + config BSP_QSPI_IO3_PIN + int "QSPI IO3 pin number" + range 0 31 + default 23 + config QSPI_FLASH_SIZE_KB + int "QSPI FLASH SIZE, DEFAULT size 8192 KB" + default 8192 + endif endmenu menu "On-chip Peripheral Drivers" @@ -30,11 +65,52 @@ menu "On-chip Peripheral Drivers" config BSP_USING_UART0 bool "Enable UART0" default y - + if BSP_USING_UART0 + config BSP_UART0_RX_PIN + int "uart0 rx pin number" + range 0 31 + default 8 + config BSP_UART0_TX_PIN + int "uart0 tx pin number" + range 0 31 + default 6 + endif config BSP_USING_UART1 bool "Enable UART1" default n - endif + endif + + config BSP_USING_ON_CHIP_FLASH + select PKG_USING_FAL + bool "Enable on-chip FLASH" + default n + + menu "On-chip flash config" + + + config MCU_FLASH_START_ADDRESS + hex "MCU FLASH START ADDRESS" + default 0x00000000 + + config MCU_FLASH_SIZE_KB + int "MCU FLASH SIZE, MAX size 1024 KB" + range 1 1024 + default 1024 + + config MCU_SRAM_START_ADDRESS + hex "MCU RAM START ADDRESS" + default 0x20000000 + + config MCU_SRAM_SIZE_KB + int "MCU RAM SIZE, MAX size 256 KB" + range 1 256 + default 256 + + config MCU_FLASH_PAGE_SIZE + hex "MCU FLASH PAGE SIZE, please not change,nrfx default is 0x1000" + range 0x1000 0x1000 + default 0x1000 + endmenu endmenu endmenu diff --git a/bsp/nrf5x/nrf52840/board/board.h b/bsp/nrf5x/nrf52840/board/board.h index 021abe9f95..669f903e55 100644 --- a/bsp/nrf5x/nrf52840/board/board.h +++ b/bsp/nrf5x/nrf52840/board/board.h @@ -5,6 +5,11 @@ #include "nrf.h" +#define MCU_FLASH_SIZE MCU_FLASH_SIZE_KB*1024 +#define MCU_FLASH_END_ADDRESS ((uint32_t)(MCU_FLASH_START_ADDRESS + MCU_FLASH_SIZE)) +#define MCU_SRAM_SIZE MCU_SRAM_SIZE_KB*1024 +#define MCU_SRAM_END_ADDRESS (MCU_SRAM_START_ADDRESS + MCU_SRAM_SIZE) + #if defined(__CC_ARM) || defined(__CLANG_ARM) extern int Image$$RW_IRAM1$$ZI$$Limit; #define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) diff --git a/bsp/nrf5x/nrf52840/board/fal_cfg.h b/bsp/nrf5x/nrf52840/board/fal_cfg.h new file mode 100644 index 0000000000..42611e0c13 --- /dev/null +++ b/bsp/nrf5x/nrf52840/board/fal_cfg.h @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-05-05 supperthomas this is sample you can change by yourself + * + */ + +#ifndef _FAL_CFG_H_ +#define _FAL_CFG_H_ + +#include +#include + +#if (defined(BSP_USING_QSPI_FLASH)&&defined(BSP_USING_ON_CHIP_FLASH)) + +#define ON_CHIP_FLASH_DEV_NAME "mcu_onchip" +#define NOR_FLASH_DEV_NAME "norflash0" + +extern const struct fal_flash_dev mcu_onchip_flash; +extern struct fal_flash_dev nor_flash0; + +/* flash device table */ +#define FAL_FLASH_DEV_TABLE \ + { \ + &mcu_onchip_flash, \ + &nor_flash0, \ + } +/* ====================== Partition Configuration ========================== */ +#ifdef FAL_PART_HAS_TABLE_CFG +/* partition table */ +#define FAL_PART_TABLE \ + { \ + {FAL_PART_MAGIC_WORD, "bl", ON_CHIP_FLASH_DEV_NAME, 0, 64*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "app_flash", ON_CHIP_FLASH_DEV_NAME, 64*1024, 960*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "nor_flash_part_0", NOR_FLASH_DEV_NAME, 0, 1024*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "nor_flash_part_1", NOR_FLASH_DEV_NAME, 1024*1024, 7*1024*1024, 0}, \ + } +#endif /* FAL_PART_HAS_TABLE_CFG */ + +#elif defined(BSP_USING_QSPI_FLASH) + +#define NOR_FLASH_DEV_NAME "norflash0" +extern struct fal_flash_dev nor_flash0; + +/* flash device table */ +#define FAL_FLASH_DEV_TABLE \ + { \ + &nor_flash0, \ + } +/* ====================== Partition Configuration ========================== */ +#ifdef FAL_PART_HAS_TABLE_CFG +/* partition table */ +#define FAL_PART_TABLE \ + { \ + {FAL_PART_MAGIC_WORD, "nor_flash_part_0", NOR_FLASH_DEV_NAME, 0, 1024*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "nor_flash_part_1", NOR_FLASH_DEV_NAME, 1024*1024, 7*1024*1024, 0}, \ + } +#endif +#elif defined(BSP_USING_ON_CHIP_FLASH) +extern const struct fal_flash_dev mcu_onchip_flash; +#define ON_CHIP_FLASH_DEV_NAME "mcu_onchip" +/* flash device table */ +#define FAL_FLASH_DEV_TABLE \ + { \ + &mcu_onchip_flash, \ + } +/* ====================== Partition Configuration ========================== */ +#ifdef FAL_PART_HAS_TABLE_CFG +/* partition table */ +#define FAL_PART_TABLE \ + { \ + {FAL_PART_MAGIC_WORD, "bl", ON_CHIP_FLASH_DEV_NAME, 0, 64*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "app_flash", ON_CHIP_FLASH_DEV_NAME, 64*1024, 960*1024, 0}, \ + } +#endif +#endif + +#endif /* _FAL_CFG_H_ */ diff --git a/bsp/nrf5x/nrf52840/board/linker_scripts/link.sct b/bsp/nrf5x/nrf52840/board/linker_scripts/link.sct index 0200e96087..a2f8ebd922 100644 --- a/bsp/nrf5x/nrf52840/board/linker_scripts/link.sct +++ b/bsp/nrf5x/nrf52840/board/linker_scripts/link.sct @@ -2,13 +2,13 @@ ; *** Scatter-Loading Description File generated by uVision *** ; ************************************************************* -LR_IROM1 0x0001F000 0x00061000 { ; load region size_region - ER_IROM1 0x0001F000 0x00061000 { ; load address = execution address +LR_IROM1 0x00000000 0x100000 { ; load region size_region + ER_IROM1 0x00000000 0x100000 { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) } - RW_IRAM1 0x200025F8 0x0000DA08 { ; RW data + RW_IRAM1 0x20000000 0x40000 { ; RW data .ANY (+RW +ZI) } } diff --git a/bsp/nrf5x/nrf52840/board/sdk_config.h b/bsp/nrf5x/nrf52840/board/sdk_config.h index aeffd2905c..75efba927a 100644 --- a/bsp/nrf5x/nrf52840/board/sdk_config.h +++ b/bsp/nrf5x/nrf52840/board/sdk_config.h @@ -2902,7 +2902,7 @@ // NRFX_QSPI_ENABLED - nrfx_qspi - QSPI peripheral driver //========================================================== #ifndef NRFX_QSPI_ENABLED -#define NRFX_QSPI_ENABLED 0 +#define NRFX_QSPI_ENABLED 1 #endif // NRFX_QSPI_CONFIG_SCK_DELAY - tSHSL, tWHSL and tSHWL in number of 16 MHz periods (62.5 ns). <0-255> @@ -3010,7 +3010,7 @@ #define NRFX_QSPI_PIN_IO3 NRF_QSPI_PIN_NOT_CONNECTED #endif -// NRFX_QSPI_CONFIG_IRQ_PRIORITY - Interrupt priority +// NRFX_QSPI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority // <0=> 0 (highest) // <1=> 1 @@ -3021,8 +3021,8 @@ // <6=> 6 // <7=> 7 -#ifndef NRFX_QSPI_CONFIG_IRQ_PRIORITY -#define NRFX_QSPI_CONFIG_IRQ_PRIORITY 6 +#ifndef NRFX_QSPI_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_QSPI_DEFAULT_CONFIG_IRQ_PRIORITY 6 #endif // @@ -11687,7 +11687,11 @@ // //========================================================== - +// NRFX_NVMC_ENABLED - nrfx_nvmc - NVMC peripheral driver +//========================================================== +#ifndef NRFX_NVMC_ENABLED +#define NRFX_NVMC_ENABLED 1 +#endif // // diff --git a/bsp/nrf5x/nrf52840/project.uvoptx b/bsp/nrf5x/nrf52840/project.uvoptx index 7d8a5a4f97..ff162faafb 100644 --- a/bsp/nrf5x/nrf52840/project.uvoptx +++ b/bsp/nrf5x/nrf52840/project.uvoptx @@ -119,13 +119,13 @@ 0 - UL2CM3 - UL2CM3(-S0 -C0 -P0 ) -FN2 -FC4000 -FD20000000 -FF0nrf52xxx -FF1nrf52xxx_uicr -FL0200000 -FL11000 -FS00 -FS110001000 -FP0($$Device:nRF52840_xxAA$Flash\nrf52xxx.flm) -FP1($$Device:nRF52840_xxAA$Flash\nrf52xxx_uicr.flm) + JL2CM3 + -U683349164 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC4000 -FN2 -FF0nrf52xxx.flm -FS00 -FL0200000 -FP0($$Device:nRF52840_xxAA$Flash\nrf52xxx.flm) -FF1nrf52xxx_uicr.flm -FS110001000 -FL11000 -FP1($$Device:nRF52840_xxAA$Flash\nrf52xxx_uicr.flm) 0 - JL2CM3 - -U683349164 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC2000 -FN2 -FF0nrf52xxx.flm -FS00 -FL0200000 -FP0($$Device:nRF52840_xxAA$Flash\nrf52xxx.flm) -FF1nrf52xxx_uicr.flm -FS110001000 -FL11000 -FP1($$Device:nRF52840_xxAA$Flash\nrf52xxx_uicr.flm) + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN2 -FC4000 -FD20000000 -FF0nrf52xxx -FF1nrf52xxx_uicr -FL0200000 -FL11000 -FS00 -FS110001000 -FP0($$Device:nRF52840_xxAA$Flash\nrf52xxx.flm) -FP1($$Device:nRF52840_xxAA$Flash\nrf52xxx_uicr.flm) @@ -359,7 +359,7 @@ Applications - 1 + 0 0 0 0 @@ -379,7 +379,7 @@ Drivers - 1 + 0 0 0 0 @@ -411,7 +411,7 @@ nrfx - 1 + 0 0 0 0 diff --git a/bsp/nrf5x/nrf52840/project.uvprojx b/bsp/nrf5x/nrf52840/project.uvprojx index babb19e132..b1bf5b73cf 100644 --- a/bsp/nrf5x/nrf52840/project.uvprojx +++ b/bsp/nrf5x/nrf52840/project.uvprojx @@ -18,7 +18,7 @@ Nordic Semiconductor NordicSemiconductor.nRF_DeviceFamilyPack.8.32.1 http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/ - IRAM(0x20000000,0x00040000) IROM(0x00000000,0x00100000) CPUTYPE("Cortex-M4") FPU2 DSP CLOCK(12000000) ELITTLE + IRAM(0x20000000,0x40000) IROM(0x00000000,0x100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE UL2CM3(-S0 -C0 -P0 -FD20000000 -FC4000 -FN2 -FF0nrf52xxx -FS00 -FL0200000 -FF1nrf52xxx_uicr -FS110001000 -FL11000 -FP0($$Device:nRF52840_xxAA$Flash\nrf52xxx.flm) -FP1($$Device:nRF52840_xxAA$Flash\nrf52xxx_uicr.flm)) @@ -275,7 +275,7 @@ 1 0x0 - 0xde000 + 0x100000 1 @@ -299,8 +299,8 @@ 0 - 0x200026c0 - 0x3d940 + 0x20000000 + 0x40000 0 diff --git a/bsp/nrf5x/nrf52840/rtconfig.h b/bsp/nrf5x/nrf52840/rtconfig.h index 1741c7dd7b..c63c401e68 100644 --- a/bsp/nrf5x/nrf52840/rtconfig.h +++ b/bsp/nrf5x/nrf52840/rtconfig.h @@ -155,10 +155,13 @@ /* Onboard Peripheral Drivers */ +#define BSP_USING_JLINK_TO_USART /* On-chip Peripheral Drivers */ #define BSP_USING_UART #define BSP_USING_UART0 +#define BSP_UART0_RX_PIN 8 +#define BSP_UART0_TX_PIN 6 #endif diff --git a/bsp/nrf5x/nrf52840/template.uvoptx b/bsp/nrf5x/nrf52840/template.uvoptx index 2e5f9fc2ac..f567bf47e8 100644 --- a/bsp/nrf5x/nrf52840/template.uvoptx +++ b/bsp/nrf5x/nrf52840/template.uvoptx @@ -119,13 +119,13 @@ 0 - UL2CM3 - UL2CM3(-S0 -C0 -P0 ) -FN2 -FC4000 -FD20000000 -FF0nrf52xxx -FF1nrf52xxx_uicr -FL0200000 -FL11000 -FS00 -FS110001000 -FP0($$Device:nRF52840_xxAA$Flash\nrf52xxx.flm) -FP1($$Device:nRF52840_xxAA$Flash\nrf52xxx_uicr.flm) + JL2CM3 + -U683349164 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC4000 -FN2 -FF0nrf52xxx.flm -FS00 -FL0200000 -FP0($$Device:nRF52840_xxAA$Flash\nrf52xxx.flm) -FF1nrf52xxx_uicr.flm -FS110001000 -FL11000 -FP1($$Device:nRF52840_xxAA$Flash\nrf52xxx_uicr.flm) 0 - JL2CM3 - -U683349164 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC2000 -FN2 -FF0nrf52xxx.flm -FS00 -FL0200000 -FP0($$Device:nRF52840_xxAA$Flash\nrf52xxx.flm) -FF1nrf52xxx_uicr.flm -FS110001000 -FL11000 -FP1($$Device:nRF52840_xxAA$Flash\nrf52xxx_uicr.flm) + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN2 -FC4000 -FD20000000 -FF0nrf52xxx -FF1nrf52xxx_uicr -FL0200000 -FL11000 -FS00 -FS110001000 -FP0($$Device:nRF52840_xxAA$Flash\nrf52xxx.flm) -FP1($$Device:nRF52840_xxAA$Flash\nrf52xxx_uicr.flm) diff --git a/bsp/nrf5x/nrf52840/template.uvprojx b/bsp/nrf5x/nrf52840/template.uvprojx index 9a8aa49622..62c5997a13 100644 --- a/bsp/nrf5x/nrf52840/template.uvprojx +++ b/bsp/nrf5x/nrf52840/template.uvprojx @@ -18,7 +18,7 @@ Nordic Semiconductor NordicSemiconductor.nRF_DeviceFamilyPack.8.32.1 http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/ - IRAM(0x20000000,0x00040000) IROM(0x00000000,0x00100000) CPUTYPE("Cortex-M4") FPU2 DSP CLOCK(12000000) ELITTLE + IRAM(0x20000000,0x40000) IROM(0x00000000,0x100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE UL2CM3(-S0 -C0 -P0 -FD20000000 -FC4000 -FN2 -FF0nrf52xxx -FS00 -FL0200000 -FF1nrf52xxx_uicr -FS110001000 -FL11000 -FP0($$Device:nRF52840_xxAA$Flash\nrf52xxx.flm) -FP1($$Device:nRF52840_xxAA$Flash\nrf52xxx_uicr.flm)) @@ -275,7 +275,7 @@ 1 0x0 - 0xde000 + 0x100000 1 @@ -299,8 +299,8 @@ 0 - 0x200026c0 - 0x3d940 + 0x20000000 + 0x40000 0 diff --git a/bsp/nuclei/gd32vf103_rvstar/rtconfig.py b/bsp/nuclei/gd32vf103_rvstar/rtconfig.py index 8136b392f8..bf74338e8a 100644 --- a/bsp/nuclei/gd32vf103_rvstar/rtconfig.py +++ b/bsp/nuclei/gd32vf103_rvstar/rtconfig.py @@ -5,6 +5,9 @@ ARCH='risc-v' CPU='nuclei' CROSS_TOOL='gcc' +# bsp lib config +BSP_LIBRARY_TYPE = None + if os.getenv('RTT_CC'): CROSS_TOOL = os.getenv('RTT_CC') @@ -18,7 +21,9 @@ else: # EXEC_PATH = os.getenv('RTT_EXEC_PATH') BUILD = 'debug' + # Fixed configurations below +NUCLEI_SDK_OPENOCD_CFG = "type in your config" NUCLEI_SDK_SOC = "gd32vf103" NUCLEI_SDK_BOARD = "gd32vf103v_rvstar" NUCLEI_SDK_DOWNLOAD = "flashxip" @@ -56,3 +61,10 @@ if PLATFORM == 'gcc': DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n' POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/nuclei/tools/sdk_dist.py b/bsp/nuclei/tools/sdk_dist.py new file mode 100644 index 0000000000..f802e92730 --- /dev/null +++ b/bsp/nuclei/tools/sdk_dist.py @@ -0,0 +1,18 @@ +import os +import sys +import shutil +cwd_path = os.getcwd() +sys.path.append(os.path.join(os.path.dirname(cwd_path), 'rt-thread', 'tools')) + +# BSP dist function +def dist_do_building(BSP_ROOT): + from mkdist import bsp_copy_files + import rtconfig + + dist_dir = os.path.join(BSP_ROOT, 'dist', os.path.basename(BSP_ROOT)) + library_dir = os.path.join(dist_dir, 'libraries') + + print("=> copy nuclei bsp library") + library_path = os.path.join(os.path.dirname(BSP_ROOT), 'libraries') + library_dir = os.path.join(dist_dir, 'libraries') + bsp_copy_files(os.path.join(library_path, rtconfig.BSP_LIBRARY_TYPE), os.path.join(library_dir, rtconfig.BSP_LIBRARY_TYPE)) diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f1/pwm_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f1/pwm_config.h index 1a5575de0c..50ea3791b6 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f1/pwm_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f1/pwm_config.h @@ -17,6 +17,17 @@ extern "C" { #endif +#ifdef BSP_USING_PWM1 +#ifndef PWM1_CONFIG +#define PWM1_CONFIG \ + { \ + .tim_handle.Instance = TIM1, \ + .name = "pwm1", \ + .channel = 0 \ + } +#endif /* PWM1_CONFIG */ +#endif /* BSP_USING_PWM1 */ + #ifdef BSP_USING_PWM2 #ifndef PWM2_CONFIG #define PWM2_CONFIG \ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/h7/dma_config.h b/bsp/stm32/libraries/HAL_Drivers/config/h7/dma_config.h index f716e23765..23b3a231c3 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/h7/dma_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/h7/dma_config.h @@ -7,6 +7,7 @@ * Date Author Notes * 2019-01-02 zylx first version * 2019-01-08 SummerGift clean up the code + * 2020-05-02 whj4674672 support stm32h7 dma1 and dma2 */ #ifndef __DMA_CONFIG_H__ @@ -19,27 +20,21 @@ extern "C" { #endif /* DMA1 stream0 */ -#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE) -#define SPI3_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler -#define SPI3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN -#define SPI3_RX_DMA_INSTANCE DMA1_Stream0 -#define SPI3_RX_DMA_CHANNEL DMA_CHANNEL_0 -#define SPI3_RX_DMA_IRQ DMA1_Stream0_IRQn -#elif defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE) -#define UART5_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler -#define UART5_RX_DMA_RCC RCC_AHB1ENR_DMA1EN -#define UART5_RX_DMA_INSTANCE DMA1_Stream0 -#define UART5_RX_DMA_CHANNEL DMA_CHANNEL_4 -#define UART5_RX_DMA_IRQ DMA1_Stream0_IRQn +#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE) +#define UART2_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler +#define UART2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define UART2_RX_DMA_INSTANCE DMA1_Stream0 +#define UART2_RX_DMA_REQUEST DMA_REQUEST_USART2_RX +#define UART2_RX_DMA_IRQ DMA1_Stream0_IRQn #endif /* DMA1 stream1 */ -#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE) -#define UART3_DMA_RX_IRQHandler DMA1_Stream1_IRQHandler -#define UART3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN -#define UART3_RX_DMA_INSTANCE DMA1_Stream1 -#define UART3_RX_DMA_CHANNEL DMA_CHANNEL_4 -#define UART3_RX_DMA_IRQ DMA1_Stream1_IRQn +#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE) +#define UART2_DMA_TX_IRQHandler DMA1_Stream1_IRQHandler +#define UART2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define UART2_TX_DMA_INSTANCE DMA1_Stream1 +#define UART2_TX_DMA_REQUEST DMA_REQUEST_USART2_TX +#define UART2_TX_DMA_IRQ DMA1_Stream1_IRQn #endif /* DMA1 stream2 */ @@ -49,12 +44,6 @@ extern "C" { #define SPI3_RX_DMA_INSTANCE DMA1_Stream2 #define SPI3_RX_DMA_CHANNEL DMA_CHANNEL_0 #define SPI3_RX_DMA_IRQ DMA1_Stream2_IRQn -#elif defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE) -#define UART4_DMA_RX_IRQHandler DMA1_Stream2_IRQHandler -#define UART4_RX_DMA_RCC RCC_AHB1ENR_DMA1EN -#define UART4_RX_DMA_INSTANCE DMA1_Stream2 -#define UART4_RX_DMA_CHANNEL DMA_CHANNEL_4 -#define UART4_RX_DMA_IRQ DMA1_Stream2_IRQn #endif /* DMA1 stream3 */ @@ -83,12 +72,6 @@ extern "C" { #define SPI3_TX_DMA_INSTANCE DMA1_Stream5 #define SPI3_TX_DMA_CHANNEL DMA_CHANNEL_0 #define SPI3_TX_DMA_IRQ DMA1_Stream5_IRQn -#elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE) -#define UART2_DMA_RX_IRQHandler DMA1_Stream5_IRQHandler -#define UART2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN -#define UART2_RX_DMA_INSTANCE DMA1_Stream5 -#define UART2_RX_DMA_CHANNEL DMA_CHANNEL_4 -#define UART2_RX_DMA_IRQ DMA1_Stream5_IRQn #endif /* DMA1 stream6 */ @@ -109,12 +92,6 @@ extern "C" { #define SPI1_RX_DMA_INSTANCE DMA2_Stream0 #define SPI1_RX_DMA_CHANNEL DMA_CHANNEL_3 #define SPI1_RX_DMA_IRQ DMA2_Stream0_IRQn -#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE) -#define SPI4_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler -#define SPI4_RX_DMA_RCC RCC_AHB1ENR_DMA2EN -#define SPI4_RX_DMA_INSTANCE DMA2_Stream0 -#define SPI4_RX_DMA_CHANNEL DMA_CHANNEL_4 -#define SPI4_RX_DMA_IRQ DMA2_Stream0_IRQn #endif /* DMA2 stream1 */ @@ -133,18 +110,6 @@ extern "C" { #define SPI1_RX_DMA_INSTANCE DMA2_Stream2 #define SPI1_RX_DMA_CHANNEL DMA_CHANNEL_3 #define SPI1_RX_DMA_IRQ DMA2_Stream2_IRQn -#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE) -#define UART1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler -#define UART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN -#define UART1_RX_DMA_INSTANCE DMA2_Stream2 -#define UART1_RX_DMA_CHANNEL DMA_CHANNEL_4 -#define UART1_RX_DMA_IRQ DMA2_Stream2_IRQn -#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE) -#define QSPI_DMA_IRQHandler DMA2_Stream2_IRQHandler -#define QSPI_DMA_RCC RCC_AHB1ENR_DMA2EN -#define QSPI_DMA_INSTANCE DMA2_Stream2 -#define QSPI_DMA_CHANNEL DMA_CHANNEL_11 -#define QSPI_DMA_IRQ DMA2_Stream2_IRQn #endif /* DMA2 stream3 */ @@ -154,18 +119,6 @@ extern "C" { #define SPI5_RX_DMA_INSTANCE DMA2_Stream3 #define SPI5_RX_DMA_CHANNEL DMA_CHANNEL_2 #define SPI5_RX_DMA_IRQ DMA2_Stream3_IRQn -#elif defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) -#define SPI1_DMA_TX_IRQHandler DMA2_Stream3_IRQHandler -#define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN -#define SPI1_TX_DMA_INSTANCE DMA2_Stream3 -#define SPI1_TX_DMA_CHANNEL DMA_CHANNEL_3 -#define SPI1_TX_DMA_IRQ DMA2_Stream3_IRQn -#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE) -#define SPI4_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler -#define SPI4_RX_DMA_RCC RCC_AHB1ENR_DMA2EN -#define SPI4_RX_DMA_INSTANCE DMA2_Stream3 -#define SPI4_RX_DMA_CHANNEL DMA_CHANNEL_5 -#define SPI4_RX_DMA_IRQ DMA2_Stream3_IRQn #endif /* DMA2 stream4 */ @@ -175,12 +128,6 @@ extern "C" { #define SPI5_TX_DMA_INSTANCE DMA2_Stream4 #define SPI5_TX_DMA_CHANNEL DMA_CHANNEL_2 #define SPI5_TX_DMA_IRQ DMA2_Stream4_IRQn -#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE) -#define SPI4_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler -#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN -#define SPI4_TX_DMA_INSTANCE DMA2_Stream4 -#define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_5 -#define SPI4_TX_DMA_IRQ DMA2_Stream4_IRQn #endif /* DMA2 stream5 */ @@ -190,18 +137,6 @@ extern "C" { #define SPI1_TX_DMA_INSTANCE DMA2_Stream5 #define SPI1_TX_DMA_CHANNEL DMA_CHANNEL_3 #define SPI1_TX_DMA_IRQ DMA2_Stream5_IRQn -#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE) -#define UART1_DMA_RX_IRQHandler DMA2_Stream5_IRQHandler -#define UART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN -#define UART1_RX_DMA_INSTANCE DMA2_Stream5 -#define UART1_RX_DMA_CHANNEL DMA_CHANNEL_4 -#define UART1_RX_DMA_IRQ DMA2_Stream5_IRQn -#elif defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE) -#define SPI5_DMA_RX_IRQHandler DMA2_Stream5_IRQHandler -#define SPI5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN -#define SPI5_RX_DMA_INSTANCE DMA2_Stream5 -#define SPI5_RX_DMA_CHANNEL DMA_CHANNEL_7 -#define SPI5_RX_DMA_IRQ DMA2_Stream5_IRQn #endif /* DMA2 stream6 */ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/h7/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/config/h7/uart_config.h index 2fefa1344c..6ae67d4a2f 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/h7/uart_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/h7/uart_config.h @@ -7,6 +7,7 @@ * Date Author Notes * 2018-10-30 SummerGift first version * 2019-01-05 zylx modify dma support + * 2020-05-02 whj4674672 support stm32h7 uart dma */ #ifndef __UART_CONFIG_H__ @@ -31,12 +32,12 @@ extern "C" { #if defined(BSP_UART1_RX_USING_DMA) #ifndef UART1_DMA_RX_CONFIG -#define UART1_DMA_RX_CONFIG \ +#define UART1_DMA_RX_CONFIG \ { \ - .Instance = UART1_RX_DMA_INSTANCE, \ - .channel = UART1_RX_DMA_CHANNEL, \ - .dma_rcc = UART1_RX_DMA_RCC, \ - .dma_irq = UART1_RX_DMA_IRQ, \ + .Instance = UART1_RX_DMA_INSTANCE, \ + .request = UART1_RX_DMA_REQUEST, \ + .dma_rcc = UART1_RX_DMA_RCC, \ + .dma_irq = UART1_RX_DMA_IRQ, \ } #endif /* UART1_DMA_RX_CONFIG */ #endif /* BSP_UART1_RX_USING_DMA */ @@ -54,16 +55,27 @@ extern "C" { #if defined(BSP_UART2_RX_USING_DMA) #ifndef UART2_DMA_RX_CONFIG -#define UART2_DMA_RX_CONFIG \ +#define UART2_DMA_RX_CONFIG \ { \ - .Instance = UART2_RX_DMA_INSTANCE, \ - .channel = UART2_RX_DMA_CHANNEL, \ - .dma_rcc = UART2_RX_DMA_RCC, \ - .dma_irq = UART2_RX_DMA_IRQ, \ + .Instance = UART2_RX_DMA_INSTANCE, \ + .request = UART2_RX_DMA_REQUEST, \ + .dma_rcc = UART2_RX_DMA_RCC, \ + .dma_irq = UART2_RX_DMA_IRQ, \ } #endif /* UART2_DMA_RX_CONFIG */ #endif /* BSP_UART2_RX_USING_DMA */ - +#if defined(BSP_UART2_TX_USING_DMA) +#ifndef UART2_DMA_TX_CONFIG +#define UART2_DMA_TX_CONFIG \ + { \ + .Instance = UART2_TX_DMA_INSTANCE, \ + .request = UART2_TX_DMA_REQUEST, \ + .dma_rcc = UART2_TX_DMA_RCC, \ + .dma_irq = UART2_TX_DMA_IRQ, \ + } +#endif /* UART2_DMA_TX_CONFIG */ +#endif /* BSP_UART2_TX_USING_DMA */ + #if defined(BSP_USING_UART3) #ifndef UART3_CONFIG #define UART3_CONFIG \ @@ -77,12 +89,12 @@ extern "C" { #if defined(BSP_UART3_RX_USING_DMA) #ifndef UART3_DMA_RX_CONFIG -#define UART3_DMA_RX_CONFIG \ +#define UART3_DMA_RX_CONFIG \ { \ - .Instance = UART3_RX_DMA_INSTANCE, \ - .channel = UART3_RX_DMA_CHANNEL, \ - .dma_rcc = UART3_RX_DMA_RCC, \ - .dma_irq = UART3_RX_DMA_IRQ, \ + .Instance = UART3_RX_DMA_INSTANCE, \ + .request = UART3_RX_DMA_REQUEST, \ + .dma_rcc = UART3_RX_DMA_RCC, \ + .dma_irq = UART3_RX_DMA_IRQ, \ } #endif /* UART3_DMA_RX_CONFIG */ #endif /* BSP_UART3_RX_USING_DMA */ @@ -100,12 +112,12 @@ extern "C" { #if defined(BSP_UART4_RX_USING_DMA) #ifndef UART4_DMA_RX_CONFIG -#define UART4_DMA_RX_CONFIG \ +#define UART4_DMA_RX_CONFIG \ { \ - .Instance = UART4_RX_DMA_INSTANCE, \ - .channel = UART4_RX_DMA_CHANNEL, \ - .dma_rcc = UART4_RX_DMA_RCC, \ - .dma_irq = UART4_RX_DMA_IRQ, \ + .Instance = UART4_RX_DMA_INSTANCE, \ + .request = UART4_RX_DMA_REQUEST, \ + .dma_rcc = UART4_RX_DMA_RCC, \ + .dma_irq = UART4_RX_DMA_IRQ, \ } #endif /* UART4_DMA_RX_CONFIG */ #endif /* BSP_UART4_RX_USING_DMA */ @@ -123,12 +135,12 @@ extern "C" { #if defined(BSP_UART5_RX_USING_DMA) #ifndef UART5_DMA_RX_CONFIG -#define UART5_DMA_RX_CONFIG \ +#define UART5_DMA_RX_CONFIG \ { \ - .Instance = UART5_RX_DMA_INSTANCE, \ - .channel = UART5_RX_DMA_CHANNEL, \ - .dma_rcc = UART5_RX_DMA_RCC, \ - .dma_irq = UART5_RX_DMA_IRQ, \ + .Instance = UART5_RX_DMA_INSTANCE, \ + .request = UART5_RX_DMA_REQUEST, \ + .dma_rcc = UART5_RX_DMA_RCC, \ + .dma_irq = UART5_RX_DMA_IRQ, \ } #endif /* UART5_DMA_RX_CONFIG */ #endif /* BSP_UART5_RX_USING_DMA */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_can.c b/bsp/stm32/libraries/HAL_Drivers/drv_can.c index 4490094470..b423d79c95 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_can.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_can.c @@ -688,9 +688,9 @@ void CAN1_SCE_IRQHandler(void) drv_can1.device.status.ackerrcnt++; if (!READ_BIT(drv_can1.CanHandle.Instance->TSR, CAN_FLAG_TXOK0)) rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_TX_FAIL | 0 << 8); - else if (!READ_BIT(drv_can1.CanHandle.Instance->TSR, CAN_FLAG_TXOK0)) + else if (!READ_BIT(drv_can1.CanHandle.Instance->TSR, CAN_FLAG_TXOK1)) rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_TX_FAIL | 1 << 8); - else if (!READ_BIT(drv_can1.CanHandle.Instance->TSR, CAN_FLAG_TXOK0)) + else if (!READ_BIT(drv_can1.CanHandle.Instance->TSR, CAN_FLAG_TXOK2)) rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_TX_FAIL | 2 << 8); break; case RT_CAN_BUS_IMPLICIT_BIT_ERR: @@ -806,11 +806,11 @@ void CAN2_SCE_IRQHandler(void) break; case RT_CAN_BUS_ACK_ERR: drv_can2.device.status.ackerrcnt++; - if (!READ_BIT(drv_can1.CanHandle.Instance->TSR, CAN_FLAG_TXOK0)) + if (!READ_BIT(drv_can2.CanHandle.Instance->TSR, CAN_FLAG_TXOK0)) rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_TX_FAIL | 0 << 8); - else if (!READ_BIT(drv_can2.CanHandle.Instance->TSR, CAN_FLAG_TXOK0)) + else if (!READ_BIT(drv_can2.CanHandle.Instance->TSR, CAN_FLAG_TXOK1)) rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_TX_FAIL | 1 << 8); - else if (!READ_BIT(drv_can2.CanHandle.Instance->TSR, CAN_FLAG_TXOK0)) + else if (!READ_BIT(drv_can2.CanHandle.Instance->TSR, CAN_FLAG_TXOK2)) rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_TX_FAIL | 2 << 8); break; case RT_CAN_BUS_IMPLICIT_BIT_ERR: diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_dma.h b/bsp/stm32/libraries/HAL_Drivers/drv_dma.h index 934579349a..256068d5e1 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_dma.h +++ b/bsp/stm32/libraries/HAL_Drivers/drv_dma.h @@ -35,7 +35,8 @@ struct dma_config { rt_uint32_t channel; #endif -#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) +#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4)\ + || defined(SOC_SERIES_STM32H7) rt_uint32_t request; #endif }; diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_spi.c b/bsp/stm32/libraries/HAL_Drivers/drv_spi.c index 914691d2be..3267ffe749 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_spi.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_spi.c @@ -257,8 +257,6 @@ static rt_err_t stm32_spi_init(struct stm32_spi *spi_drv, struct rt_spi_configur HAL_NVIC_EnableIRQ(spi_drv->config->dma_tx->dma_irq); } - __HAL_SPI_ENABLE(spi_handle); - LOG_D("%s init done", spi_drv->config->bus_name); return RT_EOK; } diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_usart.c b/bsp/stm32/libraries/HAL_Drivers/drv_usart.c index faf010c138..428efbe539 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_usart.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_usart.c @@ -8,6 +8,7 @@ * 2018-10-30 SummerGift first version * 2020-03-16 SummerGift add device close feature * 2020-03-20 SummerGift fix bug caused by ORE + * 2020-05-02 whj4674672 support stm32h7 uart dma */ #include "board.h" @@ -864,7 +865,7 @@ static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag) SET_BIT(RCC->AHBENR, dma_config->dma_rcc); tmpreg = READ_BIT(RCC->AHBENR, dma_config->dma_rcc); #elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) \ - || defined(SOC_SERIES_STM32G4) + || defined(SOC_SERIES_STM32G4)|| defined(SOC_SERIES_STM32H7) /* enable DMA clock && Delay after an RCC peripheral clock enabling*/ SET_BIT(RCC->AHB1ENR, dma_config->dma_rcc); tmpreg = READ_BIT(RCC->AHB1ENR, dma_config->dma_rcc); @@ -892,7 +893,8 @@ static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag) #elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) DMA_Handle->Instance = dma_config->Instance; DMA_Handle->Init.Channel = dma_config->channel; -#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4)\ + || defined(SOC_SERIES_STM32H7) DMA_Handle->Instance = dma_config->Instance; DMA_Handle->Init.Request = dma_config->request; #endif @@ -913,7 +915,7 @@ static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag) } DMA_Handle->Init.Priority = DMA_PRIORITY_MEDIUM; -#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32H7) DMA_Handle->Init.FIFOMode = DMA_FIFOMODE_DISABLE; #endif if (HAL_DMA_DeInit(DMA_Handle) != HAL_OK) diff --git a/bsp/stm32/libraries/templates/stm32f0xx/rtconfig.py b/bsp/stm32/libraries/templates/stm32f0xx/rtconfig.py index bbc6a35774..395d83ca99 100644 --- a/bsp/stm32/libraries/templates/stm32f0xx/rtconfig.py +++ b/bsp/stm32/libraries/templates/stm32f0xx/rtconfig.py @@ -141,3 +141,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/libraries/templates/stm32f10x/rtconfig.py b/bsp/stm32/libraries/templates/stm32f10x/rtconfig.py index fa46b74340..46b00c62cd 100644 --- a/bsp/stm32/libraries/templates/stm32f10x/rtconfig.py +++ b/bsp/stm32/libraries/templates/stm32f10x/rtconfig.py @@ -141,3 +141,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/libraries/templates/stm32f2xx/rtconfig.py b/bsp/stm32/libraries/templates/stm32f2xx/rtconfig.py index 72f931202c..5b3a3f31f0 100644 --- a/bsp/stm32/libraries/templates/stm32f2xx/rtconfig.py +++ b/bsp/stm32/libraries/templates/stm32f2xx/rtconfig.py @@ -141,3 +141,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/libraries/templates/stm32f4xx/rtconfig.py b/bsp/stm32/libraries/templates/stm32f4xx/rtconfig.py index 638f59502a..0faea85775 100644 --- a/bsp/stm32/libraries/templates/stm32f4xx/rtconfig.py +++ b/bsp/stm32/libraries/templates/stm32f4xx/rtconfig.py @@ -141,3 +141,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/libraries/templates/stm32f7xx/rtconfig.py b/bsp/stm32/libraries/templates/stm32f7xx/rtconfig.py index 21d8e13bb3..cf4cf47fe0 100644 --- a/bsp/stm32/libraries/templates/stm32f7xx/rtconfig.py +++ b/bsp/stm32/libraries/templates/stm32f7xx/rtconfig.py @@ -140,3 +140,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/libraries/templates/stm32h7xx/rtconfig.py b/bsp/stm32/libraries/templates/stm32h7xx/rtconfig.py index ef6708f653..780275b28c 100644 --- a/bsp/stm32/libraries/templates/stm32h7xx/rtconfig.py +++ b/bsp/stm32/libraries/templates/stm32h7xx/rtconfig.py @@ -142,3 +142,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/libraries/templates/stm32l1xx/rtconfig.py b/bsp/stm32/libraries/templates/stm32l1xx/rtconfig.py index 8b60665034..0450b21fcd 100644 --- a/bsp/stm32/libraries/templates/stm32l1xx/rtconfig.py +++ b/bsp/stm32/libraries/templates/stm32l1xx/rtconfig.py @@ -141,3 +141,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/libraries/templates/stm32l4xx/rtconfig.py b/bsp/stm32/libraries/templates/stm32l4xx/rtconfig.py index 2e022a964b..deb2083359 100644 --- a/bsp/stm32/libraries/templates/stm32l4xx/rtconfig.py +++ b/bsp/stm32/libraries/templates/stm32l4xx/rtconfig.py @@ -141,3 +141,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/stm32f072-st-nucleo/rtconfig.py b/bsp/stm32/stm32f072-st-nucleo/rtconfig.py index bbc6a35774..8d8cd61658 100644 --- a/bsp/stm32/stm32f072-st-nucleo/rtconfig.py +++ b/bsp/stm32/stm32f072-st-nucleo/rtconfig.py @@ -141,3 +141,11 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) + diff --git a/bsp/stm32/stm32f091-st-nucleo/rtconfig.py b/bsp/stm32/stm32f091-st-nucleo/rtconfig.py index bbc6a35774..395d83ca99 100644 --- a/bsp/stm32/stm32f091-st-nucleo/rtconfig.py +++ b/bsp/stm32/stm32f091-st-nucleo/rtconfig.py @@ -141,3 +141,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/stm32f103-atk-nano/rtconfig.py b/bsp/stm32/stm32f103-atk-nano/rtconfig.py index 9ace3b0a3c..b8509ee7a0 100644 --- a/bsp/stm32/stm32f103-atk-nano/rtconfig.py +++ b/bsp/stm32/stm32f103-atk-nano/rtconfig.py @@ -141,3 +141,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/stm32f103-atk-warshipv3/applications/main.c b/bsp/stm32/stm32f103-atk-warshipv3/applications/main.c index ab323bcb8c..140fb13c73 100644 --- a/bsp/stm32/stm32f103-atk-warshipv3/applications/main.c +++ b/bsp/stm32/stm32f103-atk-warshipv3/applications/main.c @@ -14,7 +14,7 @@ /* defined the LED0 pin: PB5 */ #define LED0_PIN GET_PIN(B, 5) -/* defined the LED0 pin: PE5 */ +/* defined the LED1 pin: PE5 */ #define LED1_PIN GET_PIN(E, 5) int main(void) diff --git a/bsp/stm32/stm32f103-atk-warshipv3/rtconfig.py b/bsp/stm32/stm32f103-atk-warshipv3/rtconfig.py index fa46b74340..46b00c62cd 100644 --- a/bsp/stm32/stm32f103-atk-warshipv3/rtconfig.py +++ b/bsp/stm32/stm32f103-atk-warshipv3/rtconfig.py @@ -141,3 +141,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/stm32f103-dofly-M3S/rtconfig.py b/bsp/stm32/stm32f103-dofly-M3S/rtconfig.py index 233b0e6440..8c30e41437 100644 --- a/bsp/stm32/stm32f103-dofly-M3S/rtconfig.py +++ b/bsp/stm32/stm32f103-dofly-M3S/rtconfig.py @@ -141,3 +141,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/stm32f103-dofly-lyc8/rtconfig.py b/bsp/stm32/stm32f103-dofly-lyc8/rtconfig.py index 9ace3b0a3c..b8509ee7a0 100644 --- a/bsp/stm32/stm32f103-dofly-lyc8/rtconfig.py +++ b/bsp/stm32/stm32f103-dofly-lyc8/rtconfig.py @@ -141,3 +141,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/stm32f103-fire-arbitrary/rtconfig.py b/bsp/stm32/stm32f103-fire-arbitrary/rtconfig.py index 9ace3b0a3c..b8509ee7a0 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/rtconfig.py +++ b/bsp/stm32/stm32f103-fire-arbitrary/rtconfig.py @@ -141,3 +141,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/stm32f103-gizwits-gokitv21/.config b/bsp/stm32/stm32f103-gizwits-gokitv21/.config index aef45f1590..50885e3d05 100644 --- a/bsp/stm32/stm32f103-gizwits-gokitv21/.config +++ b/bsp/stm32/stm32f103-gizwits-gokitv21/.config @@ -64,7 +64,7 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" -CONFIG_RT_VER_NUM=0x40002 +CONFIG_RT_VER_NUM=0x40003 CONFIG_ARCH_ARM=y CONFIG_RT_USING_CPU_FFS=y CONFIG_ARCH_ARM_CORTEX_M=y @@ -126,7 +126,6 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set -# CONFIG_RT_USING_MTD is not set # CONFIG_RT_USING_PM is not set # CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set @@ -134,15 +133,10 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_WDT is not set # CONFIG_RT_USING_AUDIO is not set # CONFIG_RT_USING_SENSOR is not set - -# -# Using Hardware Crypto drivers -# +# CONFIG_RT_USING_TOUCH is not set # CONFIG_RT_USING_HWCRYPTO is not set - -# -# Using WiFi -# +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_WIFI is not set # @@ -156,6 +150,7 @@ CONFIG_RT_USING_PIN=y # # CONFIG_RT_USING_LIBC is not set # CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_LIBC_USING_TIME is not set # # Network @@ -176,11 +171,6 @@ CONFIG_RT_USING_PIN=y # # CONFIG_RT_USING_LWIP is not set -# -# Modbus master and slave stack -# -# CONFIG_RT_USING_MODBUS is not set - # # AT commands # @@ -210,10 +200,13 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_WEBCLIENT is not set # CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set # CONFIG_PKG_USING_JSMN is not set # CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_LJSON is not set # CONFIG_PKG_USING_EZXML is not set # CONFIG_PKG_USING_NANOPB is not set @@ -235,6 +228,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set # CONFIG_PKG_USING_AT_DEVICE is not set # CONFIG_PKG_USING_ATSRV_SOCKET is not set # CONFIG_PKG_USING_WIZNET is not set @@ -247,12 +241,28 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_ALI_IOTKIT is not set # CONFIG_PKG_USING_AZURE is not set # CONFIG_PKG_USING_TENCENT_IOTHUB is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set # CONFIG_PKG_USING_NIMBLE is not set # CONFIG_PKG_USING_OTA_DOWNLOADER is not set # CONFIG_PKG_USING_IPMSG is not set # CONFIG_PKG_USING_LSSDP is not set # CONFIG_PKG_USING_AIRKISS_OPEN is not set # CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_CMUX is not set # # security packages @@ -260,6 +270,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_MBEDTLS is not set # CONFIG_PKG_USING_libsodium is not set # CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set # # language packages @@ -274,6 +285,8 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set # CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set # # tools packages @@ -286,6 +299,12 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_ULOG_EASYFLASH is not set # CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set # # system packages @@ -303,6 +322,11 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_DFS_YAFFS is not set # CONFIG_PKG_USING_LITTLEFS is not set # CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set # # peripheral libraries and drivers @@ -310,6 +334,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_SENSORS_DRIVERS is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_U8G2 is not set @@ -318,15 +343,33 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_SX12XX is not set # CONFIG_PKG_USING_SIGNAL_LED is not set # CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set # CONFIG_PKG_USING_WM_LIBRARIES is not set # CONFIG_PKG_USING_KENDRYTE_SDK is not set # CONFIG_PKG_USING_INFRARED is not set # CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set # CONFIG_PKG_USING_AT24CXX is not set # CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set # CONFIG_PKG_USING_AD7746 is not set # CONFIG_PKG_USING_PCA9685 is not set # CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set # # miscellaneous packages @@ -337,12 +380,15 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_MINILZO is not set # CONFIG_PKG_USING_QUICKLZ is not set # CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set # CONFIG_PKG_USING_KENDRYTE_DEMO is not set # CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set # # samples: kernel and components samples @@ -354,6 +400,12 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_HELLO is not set # CONFIG_PKG_USING_VI is not set # CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set CONFIG_SOC_FAMILY_STM32=y CONFIG_SOC_SERIES_STM32F1=y @@ -372,8 +424,10 @@ CONFIG_SOC_STM32F103C8=y CONFIG_BSP_USING_GPIO=y CONFIG_BSP_USING_UART=y CONFIG_BSP_USING_UART1=y +CONFIG_BSP_USING_UART2=y # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_I2C1 is not set +# CONFIG_BSP_USING_UDID is not set # # Board extended module Drivers diff --git a/bsp/stm32/stm32f103-gizwits-gokitv21/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c b/bsp/stm32/stm32f103-gizwits-gokitv21/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c index 99fed4303e..12171ceb42 100644 --- a/bsp/stm32/stm32f103-gizwits-gokitv21/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c +++ b/bsp/stm32/stm32f103-gizwits-gokitv21/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c @@ -117,6 +117,34 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspInit 1 */ } + + if(huart->Instance==USART2) + { + /* USER CODE BEGIN USART2_MspInit 0 */ + + /* USER CODE END USART2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_USART2_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**USART2 GPIO Configuration + PA2 ------> USART2_TX + PA3 ------> USART2_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_2; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_3; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_PULLUP; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN USART2_MspInit 1 */ + + /* USER CODE END USART2_MspInit 1 */ + } } @@ -146,6 +174,24 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspDeInit 1 */ } + if(huart->Instance==USART2) + { + /* USER CODE BEGIN USART2_MspDeInit 0 */ + + /* USER CODE END USART2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART2_CLK_DISABLE(); + + /**USART2 GPIO Configuration + PA2 ------> USART2_TX + PA3 ------> USART2_RX + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3); + + /* USER CODE BEGIN USART2_MspDeInit 1 */ + + /* USER CODE END USART2_MspDeInit 1 */ + } } diff --git a/bsp/stm32/stm32f103-gizwits-gokitv21/board/Kconfig b/bsp/stm32/stm32f103-gizwits-gokitv21/board/Kconfig index 63948e6b26..63afb79a2f 100644 --- a/bsp/stm32/stm32f103-gizwits-gokitv21/board/Kconfig +++ b/bsp/stm32/stm32f103-gizwits-gokitv21/board/Kconfig @@ -31,6 +31,14 @@ menu "On-chip Peripheral Drivers" bool "Enable UART1 RX DMA" depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA default n + config BSP_USING_UART2 + bool "Enable UART2" + default n + + config BSP_UART1_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n endif menuconfig BSP_USING_SPI diff --git a/bsp/stm32/stm32f103-gizwits-gokitv21/project.uvprojx b/bsp/stm32/stm32f103-gizwits-gokitv21/project.uvprojx index abce08c317..45218d9445 100644 --- a/bsp/stm32/stm32f103-gizwits-gokitv21/project.uvprojx +++ b/bsp/stm32/stm32f103-gizwits-gokitv21/project.uvprojx @@ -392,13 +392,6 @@ ..\..\..\src\components.c - - - cpu.c - 1 - ..\..\..\src\cpu.c - - device.c @@ -732,13 +725,6 @@ ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_cec.c - - - stm32f1xx_hal_sram.c - 1 - ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_sram.c - - stm32f1xx_hal_gpio.c diff --git a/bsp/stm32/stm32f103-gizwits-gokitv21/rtconfig.h b/bsp/stm32/stm32f103-gizwits-gokitv21/rtconfig.h index 27752e4b61..4c0dc473f8 100644 --- a/bsp/stm32/stm32f103-gizwits-gokitv21/rtconfig.h +++ b/bsp/stm32/stm32f103-gizwits-gokitv21/rtconfig.h @@ -39,7 +39,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" -#define RT_VER_NUM 0x40002 +#define RT_VER_NUM 0x40003 #define ARCH_ARM #define RT_USING_CPU_FFS #define ARCH_ARM_CORTEX_M @@ -82,12 +82,6 @@ #define RT_SERIAL_RB_BUFSZ 64 #define RT_USING_PIN -/* Using Hardware Crypto drivers */ - - -/* Using WiFi */ - - /* Using USB */ @@ -105,9 +99,6 @@ /* light weight TCP/IP stack */ -/* Modbus master and slave stack */ - - /* AT commands */ @@ -170,6 +161,7 @@ #define BSP_USING_GPIO #define BSP_USING_UART #define BSP_USING_UART1 +#define BSP_USING_UART2 /* Board extended module Drivers */ diff --git a/bsp/stm32/stm32f103-gizwits-gokitv21/rtconfig.py b/bsp/stm32/stm32f103-gizwits-gokitv21/rtconfig.py index fa46b74340..46b00c62cd 100644 --- a/bsp/stm32/stm32f103-gizwits-gokitv21/rtconfig.py +++ b/bsp/stm32/stm32f103-gizwits-gokitv21/rtconfig.py @@ -141,3 +141,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/stm32f103-hw100k-ibox/rtconfig.py b/bsp/stm32/stm32f103-hw100k-ibox/rtconfig.py index fa46b74340..46b00c62cd 100644 --- a/bsp/stm32/stm32f103-hw100k-ibox/rtconfig.py +++ b/bsp/stm32/stm32f103-hw100k-ibox/rtconfig.py @@ -141,3 +141,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/stm32f103-mini-system/rtconfig.py b/bsp/stm32/stm32f103-mini-system/rtconfig.py index c16c2fdda7..7912203103 100644 --- a/bsp/stm32/stm32f103-mini-system/rtconfig.py +++ b/bsp/stm32/stm32f103-mini-system/rtconfig.py @@ -142,3 +142,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/stm32f103-yf-ufun/rtconfig.py b/bsp/stm32/stm32f103-yf-ufun/rtconfig.py index fa46b74340..46b00c62cd 100644 --- a/bsp/stm32/stm32f103-yf-ufun/rtconfig.py +++ b/bsp/stm32/stm32f103-yf-ufun/rtconfig.py @@ -141,3 +141,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/stm32f107-uc-eval/rtconfig.py b/bsp/stm32/stm32f107-uc-eval/rtconfig.py index 9ace3b0a3c..b8509ee7a0 100644 --- a/bsp/stm32/stm32f107-uc-eval/rtconfig.py +++ b/bsp/stm32/stm32f107-uc-eval/rtconfig.py @@ -141,3 +141,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/stm32f401-st-nucleo/rtconfig.py b/bsp/stm32/stm32f401-st-nucleo/rtconfig.py index 3b4b3a5208..90240ee5f8 100644 --- a/bsp/stm32/stm32f401-st-nucleo/rtconfig.py +++ b/bsp/stm32/stm32f401-st-nucleo/rtconfig.py @@ -142,3 +142,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/stm32f405-smdz-breadfruit/rtconfig.py b/bsp/stm32/stm32f405-smdz-breadfruit/rtconfig.py index 81e39f9513..e54b11c079 100644 --- a/bsp/stm32/stm32f405-smdz-breadfruit/rtconfig.py +++ b/bsp/stm32/stm32f405-smdz-breadfruit/rtconfig.py @@ -141,3 +141,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/stm32f407-atk-explorer/rtconfig.py b/bsp/stm32/stm32f407-atk-explorer/rtconfig.py index 638f59502a..0faea85775 100644 --- a/bsp/stm32/stm32f407-atk-explorer/rtconfig.py +++ b/bsp/stm32/stm32f407-atk-explorer/rtconfig.py @@ -141,3 +141,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/stm32f407-st-discovery/rtconfig.py b/bsp/stm32/stm32f407-st-discovery/rtconfig.py index 32024fa83a..50393c3125 100644 --- a/bsp/stm32/stm32f407-st-discovery/rtconfig.py +++ b/bsp/stm32/stm32f407-st-discovery/rtconfig.py @@ -141,3 +141,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/stm32f410-st-nucleo/rtconfig.py b/bsp/stm32/stm32f410-st-nucleo/rtconfig.py index 8c0a3e1281..2ac9f2b706 100644 --- a/bsp/stm32/stm32f410-st-nucleo/rtconfig.py +++ b/bsp/stm32/stm32f410-st-nucleo/rtconfig.py @@ -141,3 +141,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/stm32f411-st-nucleo/rtconfig.py b/bsp/stm32/stm32f411-st-nucleo/rtconfig.py index 8c0a3e1281..2ac9f2b706 100644 --- a/bsp/stm32/stm32f411-st-nucleo/rtconfig.py +++ b/bsp/stm32/stm32f411-st-nucleo/rtconfig.py @@ -141,3 +141,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/stm32f411-weact-MiniF4/rtconfig.py b/bsp/stm32/stm32f411-weact-MiniF4/rtconfig.py index 8c0a3e1281..2ac9f2b706 100644 --- a/bsp/stm32/stm32f411-weact-MiniF4/rtconfig.py +++ b/bsp/stm32/stm32f411-weact-MiniF4/rtconfig.py @@ -141,3 +141,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/stm32f412-st-nucleo/rtconfig.py b/bsp/stm32/stm32f412-st-nucleo/rtconfig.py index 40b84ad846..dddfc31180 100644 --- a/bsp/stm32/stm32f412-st-nucleo/rtconfig.py +++ b/bsp/stm32/stm32f412-st-nucleo/rtconfig.py @@ -142,3 +142,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/stm32f427-robomaster-a/rtconfig.py b/bsp/stm32/stm32f427-robomaster-a/rtconfig.py index 638f59502a..0faea85775 100644 --- a/bsp/stm32/stm32f427-robomaster-a/rtconfig.py +++ b/bsp/stm32/stm32f427-robomaster-a/rtconfig.py @@ -141,3 +141,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/stm32f429-armfly-v6/rtconfig.py b/bsp/stm32/stm32f429-armfly-v6/rtconfig.py index 79419c6c06..ed19e36763 100644 --- a/bsp/stm32/stm32f429-armfly-v6/rtconfig.py +++ b/bsp/stm32/stm32f429-armfly-v6/rtconfig.py @@ -142,3 +142,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/stm32f429-atk-apollo/rtconfig.py b/bsp/stm32/stm32f429-atk-apollo/rtconfig.py index 638f59502a..0faea85775 100644 --- a/bsp/stm32/stm32f429-atk-apollo/rtconfig.py +++ b/bsp/stm32/stm32f429-atk-apollo/rtconfig.py @@ -141,3 +141,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/stm32f429-fire-challenger/rtconfig.py b/bsp/stm32/stm32f429-fire-challenger/rtconfig.py index 638f59502a..0faea85775 100644 --- a/bsp/stm32/stm32f429-fire-challenger/rtconfig.py +++ b/bsp/stm32/stm32f429-fire-challenger/rtconfig.py @@ -141,3 +141,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/stm32f429-st-disco/rtconfig.py b/bsp/stm32/stm32f429-st-disco/rtconfig.py index 32024fa83a..50393c3125 100644 --- a/bsp/stm32/stm32f429-st-disco/rtconfig.py +++ b/bsp/stm32/stm32f429-st-disco/rtconfig.py @@ -141,3 +141,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/stm32f446-st-nucleo/rtconfig.py b/bsp/stm32/stm32f446-st-nucleo/rtconfig.py index 638f59502a..0faea85775 100644 --- a/bsp/stm32/stm32f446-st-nucleo/rtconfig.py +++ b/bsp/stm32/stm32f446-st-nucleo/rtconfig.py @@ -141,3 +141,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/stm32f469-st-disco/rtconfig.py b/bsp/stm32/stm32f469-st-disco/rtconfig.py index 32024fa83a..50393c3125 100644 --- a/bsp/stm32/stm32f469-st-disco/rtconfig.py +++ b/bsp/stm32/stm32f469-st-disco/rtconfig.py @@ -141,3 +141,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/stm32f767-atk-apollo/rtconfig.py b/bsp/stm32/stm32f767-atk-apollo/rtconfig.py index dedc1b9580..bc4112597c 100644 --- a/bsp/stm32/stm32f767-atk-apollo/rtconfig.py +++ b/bsp/stm32/stm32f767-atk-apollo/rtconfig.py @@ -140,4 +140,11 @@ elif PLATFORM == 'iar': CXXFLAGS = CFLAGS EXEC_PATH = EXEC_PATH + '/arm/bin/' - POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' \ No newline at end of file + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/stm32f767-fire-challenger/rtconfig.py b/bsp/stm32/stm32f767-fire-challenger/rtconfig.py index 7a46cc624d..c83a51a09d 100644 --- a/bsp/stm32/stm32f767-fire-challenger/rtconfig.py +++ b/bsp/stm32/stm32f767-fire-challenger/rtconfig.py @@ -140,4 +140,11 @@ elif PLATFORM == 'iar': CXXFLAGS = CFLAGS EXEC_PATH = EXEC_PATH + '/arm/bin/' - POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' \ No newline at end of file + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/stm32f769-st-disco/rtconfig.py b/bsp/stm32/stm32f769-st-disco/rtconfig.py index 21d8e13bb3..cf4cf47fe0 100644 --- a/bsp/stm32/stm32f769-st-disco/rtconfig.py +++ b/bsp/stm32/stm32f769-st-disco/rtconfig.py @@ -140,3 +140,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/stm32g071-st-nucleo/rtconfig.py b/bsp/stm32/stm32g071-st-nucleo/rtconfig.py index d86774675d..7452398326 100644 --- a/bsp/stm32/stm32g071-st-nucleo/rtconfig.py +++ b/bsp/stm32/stm32g071-st-nucleo/rtconfig.py @@ -141,3 +141,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/stm32g431-st-nucleo/rtconfig.py b/bsp/stm32/stm32g431-st-nucleo/rtconfig.py index 638f59502a..0faea85775 100644 --- a/bsp/stm32/stm32g431-st-nucleo/rtconfig.py +++ b/bsp/stm32/stm32g431-st-nucleo/rtconfig.py @@ -141,3 +141,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/stm32h743-atk-apollo/README.md b/bsp/stm32/stm32h743-atk-apollo/README.md index 55d34341ec..b2606a7774 100644 --- a/bsp/stm32/stm32h743-atk-apollo/README.md +++ b/bsp/stm32/stm32h743-atk-apollo/README.md @@ -117,7 +117,7 @@ msh > ## 注意事项 -暂无 +1. 使用UART2 DMA模式时，HEAP的CACHE策略设置了WT模式，所以在使用rt_device_read读取数据之前必须调用用SCB_InvalidateDCache_by_Addr或者SCB_InvalidateDCache，已确保读取到数据的正确性。 ## 联系人信息 diff --git a/bsp/stm32/stm32h743-atk-apollo/board/Kconfig b/bsp/stm32/stm32h743-atk-apollo/board/Kconfig index 1e0e391ee6..8fc1fb5789 100644 --- a/bsp/stm32/stm32h743-atk-apollo/board/Kconfig +++ b/bsp/stm32/stm32h743-atk-apollo/board/Kconfig @@ -56,6 +56,16 @@ menu "On-chip Peripheral Drivers" config BSP_USING_UART2 bool "Enable UART2" default n + + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + + config BSP_UART2_TX_USING_DMA + bool "Enable UART2 TX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n endif config BSP_USING_FMC diff --git a/bsp/stm32/stm32h743-atk-apollo/board/drv_mpu.c b/bsp/stm32/stm32h743-atk-apollo/board/drv_mpu.c index 088d7a0bb7..5f4d8b1b80 100644 --- a/bsp/stm32/stm32h743-atk-apollo/board/drv_mpu.c +++ b/bsp/stm32/stm32h743-atk-apollo/board/drv_mpu.c @@ -52,6 +52,10 @@ int mpu_init(void) /* Enable the MPU */ HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT); + /* Enable CACHE */ + SCB_EnableICache(); + SCB_EnableDCache(); + return 0; } diff --git a/bsp/stm32/stm32h743-atk-apollo/rtconfig.py b/bsp/stm32/stm32h743-atk-apollo/rtconfig.py index ef6708f653..780275b28c 100644 --- a/bsp/stm32/stm32h743-atk-apollo/rtconfig.py +++ b/bsp/stm32/stm32h743-atk-apollo/rtconfig.py @@ -142,3 +142,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/stm32h743-st-nucleo/rtconfig.py b/bsp/stm32/stm32h743-st-nucleo/rtconfig.py index ef6708f653..780275b28c 100644 --- a/bsp/stm32/stm32h743-st-nucleo/rtconfig.py +++ b/bsp/stm32/stm32h743-st-nucleo/rtconfig.py @@ -142,3 +142,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/stm32h747-st-discovery/rtconfig.py b/bsp/stm32/stm32h747-st-discovery/rtconfig.py index ef6708f653..780275b28c 100644 --- a/bsp/stm32/stm32h747-st-discovery/rtconfig.py +++ b/bsp/stm32/stm32h747-st-discovery/rtconfig.py @@ -142,3 +142,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/stm32h750-armfly-h7-tool/rtconfig.py b/bsp/stm32/stm32h750-armfly-h7-tool/rtconfig.py index ef6708f653..780275b28c 100644 --- a/bsp/stm32/stm32h750-armfly-h7-tool/rtconfig.py +++ b/bsp/stm32/stm32h750-armfly-h7-tool/rtconfig.py @@ -142,3 +142,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/stm32l010-st-nucleo/rtconfig.py b/bsp/stm32/stm32l010-st-nucleo/rtconfig.py index 39d6af6879..dd13683b26 100644 --- a/bsp/stm32/stm32l010-st-nucleo/rtconfig.py +++ b/bsp/stm32/stm32l010-st-nucleo/rtconfig.py @@ -141,3 +141,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/stm32l053-st-nucleo/rtconfig.py b/bsp/stm32/stm32l053-st-nucleo/rtconfig.py index 39d6af6879..dd13683b26 100644 --- a/bsp/stm32/stm32l053-st-nucleo/rtconfig.py +++ b/bsp/stm32/stm32l053-st-nucleo/rtconfig.py @@ -141,3 +141,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/stm32l412-st-nucleo/.config b/bsp/stm32/stm32l412-st-nucleo/.config new file mode 100644 index 0000000000..288363f85b --- /dev/null +++ b/bsp/stm32/stm32l412-st-nucleo/.config @@ -0,0 +1,443 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set +CONFIG_RT_DEBUG=y +CONFIG_RT_DEBUG_COLOR=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=256 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart2" +CONFIG_RT_VER_NUM=0x40003 +CONFIG_ARCH_ARM=y +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M4=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +CONFIG_FINSH_USING_MSH_ONLY=y +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +# CONFIG_RT_USING_DFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +CONFIG_RT_USING_RTC=y +# CONFIG_RT_USING_ALARM is not set +# CONFIG_RT_USING_SOFT_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +CONFIG_RT_USING_WDT=y +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_LWP is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOTHUB is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_URLENCODE is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set +CONFIG_SOC_FAMILY_STM32=y +CONFIG_SOC_SERIES_STM32L4=y + +# +# Hardware Drivers Config +# +CONFIG_SOC_STM32L412RB=y + +# +# Onboard Peripheral Drivers +# +CONFIG_BSP_USING_STLINK_TO_USART=y + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART2=y +# CONFIG_BSP_UART2_RX_USING_DMA is not set +# CONFIG_BSP_USING_ON_CHIP_FLASH is not set +# CONFIG_BSP_USING_ONCHIP_RTC is not set +# CONFIG_BSP_USING_WDT is not set +# CONFIG_BSP_USING_CRC is not set +# CONFIG_BSP_USING_RNG is not set +# CONFIG_BSP_USING_UDID is not set + +# +# Board extended module Drivers +# diff --git a/bsp/stm32/stm32l412-st-nucleo/.gitignore b/bsp/stm32/stm32l412-st-nucleo/.gitignore new file mode 100644 index 0000000000..7221bde019 --- /dev/null +++ b/bsp/stm32/stm32l412-st-nucleo/.gitignore @@ -0,0 +1,42 @@ +*.pyc +*.map +*.dblite +*.elf +*.bin +*.hex +*.axf +*.exe +*.pdb +*.idb +*.ilk +*.old +build +Debug +documentation/html +packages/ +*~ +*.o +*.obj +*.out +*.bak +*.dep +*.lib +*.i +*.d +.DS_Stor* +.config 3 +.config 4 +.config 5 +Midea-X1 +*.uimg +GPATH +GRTAGS +GTAGS +.vscode +JLinkLog.txt +JLinkSettings.ini +DebugConfig/ +RTE/ +settings/ +*.uvguix* +cconfig.h diff --git a/bsp/stm32/stm32l412-st-nucleo/Kconfig b/bsp/stm32/stm32l412-st-nucleo/Kconfig new file mode 100644 index 0000000000..8cbc7b71a8 --- /dev/null +++ b/bsp/stm32/stm32l412-st-nucleo/Kconfig @@ -0,0 +1,21 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "../libraries/Kconfig" +source "board/Kconfig" diff --git a/bsp/stm32/stm32l412-st-nucleo/README.md b/bsp/stm32/stm32l412-st-nucleo/README.md new file mode 100644 index 0000000000..ce4af7d1f8 --- /dev/null +++ b/bsp/stm32/stm32l412-st-nucleo/README.md @@ -0,0 +1,116 @@ +# NUCLEO32-L412 开发板 BSP 说明 + +## 简介 + +本文档为ST官方 NUCLEO32-L412 开发板的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +对于 NUCLEO32-L412，内核是 Cortex-M4，绿色的 Nucleo 标志显示了这款芯片是低功耗系列，板载 ST-LINK/V2-1 调试器/编程器，迷你尺寸，mirco USB 接口，可数的外设，Arduino™ nano 兼容的接口。 + +开发板外观如下图所示： + +![board](figures/board.jpg) + +该开发板常用 **板载资源** 如下： + +- MCU：STM32L412RBT6P，主频 80MHz，128KB FLASH ，40KB RAM。 +- 常用外设 + - LED：4个，LD1（COM 双色），LD2（5V_USB 红色），LD3（5V_PWR 绿色），LD4（USER 绿色） + - 按键：2个，用户按键（B1），复位按键（B2） +- 常用接口：USB 支持 3 种不同接口：虚拟 COM 端口、大容量存储和调试端口。 +- 调试接口：板载 ST-LINK/V2-1 调试器。 + +开发板更多详细信息请参考【STMicroelectronics】 [NUCLEO-L412RB-P](https://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-mpu-eval-tools/stm32-mcu-mpu-eval-tools/stm32-nucleo-boards/nucleo-l412rb-p.html)。 + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :----------------- | :----------: | :------------------------------------- | +| 板载 ST-LINK 转串口 | 支持 | UART2 | +| **片上外设** | **支持情况** | **备注** | +| GPIO | 支持 | PA0, PA1... PC15 ---> PIN: 0, 1...47 | +| UART | 支持 | UART2 | +| SPI | 暂不支持 | SPI1 即将支持 | +| I2C | 暂不支持 | 软件 I2C 即将支持 | +| RTC | 支持 | 支持外部晶振和内部低速时钟 | +| PWM | 暂不支持 | 即将支持 | +| USB Device | 暂不支持 | 即将支持 | +| IWG | 支持 | 独立看门狗，未开启窗口模式 | +| **扩展模块** | **支持情况** | **备注** | + + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + + +### 快速上手 + +本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用数据线连接开发板到 PC，打开电源开关。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用 ST-LINK 仿真器下载程序，在通过 microUSB 连接开发板的基础上，点击下载按钮即可下载程序到开发板 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，观察开发板上 LED 的运行效果，红色 LD1 和 LD2 常亮、黄色色 LD3 会周期性闪烁。 + +USB 虚拟 COM 端口默认连接串口 2，在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: + +```bash + \ | / +- RT - Thread Operating System + / | \ 4.0.3 build Apr 24 2020 + 2006 - 2020 Copyright by rt-thread team +msh > +``` +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 串口2 的功能，如果需使用更多高级功能，需要利用 ENV 工具对 BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。 + +本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。 + +## 注意事项 + +- 开机时如果不能打印 RT-Thread 版本信息，请将BSP中串口 GPIO 速率调低 +- 开机时如果不能打印 RT-Thread 版本信息，请重新选择 PC 端串口调试软件的串口号 + +## 联系人信息 + +维护人: + +- [luhuadong](https://github.com/luhuadong), 邮箱： \ No newline at end of file diff --git a/bsp/stm32/stm32l412-st-nucleo/SConscript b/bsp/stm32/stm32l412-st-nucleo/SConscript new file mode 100644 index 0000000000..20f7689c53 --- /dev/null +++ b/bsp/stm32/stm32l412-st-nucleo/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/stm32/stm32l412-st-nucleo/SConstruct b/bsp/stm32/stm32l412-st-nucleo/SConstruct new file mode 100644 index 0000000000..c4b3facad7 --- /dev/null +++ b/bsp/stm32/stm32l412-st-nucleo/SConstruct @@ -0,0 +1,60 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rt-thread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +stm32_library = 'STM32L4xx_HAL' +rtconfig.BSP_LIBRARY_TYPE = stm32_library + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, stm32_library, 'SConscript'))) + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/stm32/stm32l412-st-nucleo/applications/SConscript b/bsp/stm32/stm32l412-st-nucleo/applications/SConscript new file mode 100644 index 0000000000..4939638d41 --- /dev/null +++ b/bsp/stm32/stm32l412-st-nucleo/applications/SConscript @@ -0,0 +1,9 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [str(Dir('#')), cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/stm32/stm32l412-st-nucleo/applications/main.c b/bsp/stm32/stm32l412-st-nucleo/applications/main.c new file mode 100644 index 0000000000..2511e7a3bc --- /dev/null +++ b/bsp/stm32/stm32l412-st-nucleo/applications/main.c @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-04-24 luhuadong first version + */ + +#include +#include +#include + +/* defined the LD4 pin: PB13 */ +#define LD4_PIN GET_PIN(B, 13) + +int main(void) +{ + int count = 1; + /* set LD4 pin mode to output */ + rt_pin_mode(LD4_PIN, PIN_MODE_OUTPUT); + + while (count++) + { + rt_pin_write(LD4_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LD4_PIN, PIN_LOW); + rt_thread_mdelay(500); + } + + return RT_EOK; +} diff --git a/bsp/stm32/stm32l412-st-nucleo/board/CubeMX_Config/.mxproject b/bsp/stm32/stm32l412-st-nucleo/board/CubeMX_Config/.mxproject new file mode 100644 index 0000000000..2bfa20ea63 --- /dev/null +++ b/bsp/stm32/stm32l412-st-nucleo/board/CubeMX_Config/.mxproject @@ -0,0 +1,14 @@ +[PreviousGenFiles] +HeaderPath=/home/rudy/workspace_hd/Projects/rt-thread/bsp/stm32/stm32l412-st-nucleo/board/CubeMX_Config/Inc +HeaderFiles=stm32l4xx_it.h;stm32l4xx_hal_conf.h;main.h; +SourcePath=/home/rudy/workspace_hd/Projects/rt-thread/bsp/stm32/stm32l412-st-nucleo/board/CubeMX_Config/Src +SourceFiles=stm32l4xx_it.c;stm32l4xx_hal_msp.c;main.c; + +[PreviousLibFiles] +LibFiles=Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h;Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h;Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l412xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/tz_context.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/mpu_armv8.h; + +[PreviousUsedIarFiles] +SourceFiles=../Src/main.c;../Src/stm32l4xx_it.c;../Src/stm32l4xx_hal_msp.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;..//Src/system_stm32l4xx.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;..//Src/system_stm32l4xx.c;../Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;; +HeaderPath=../Drivers/STM32L4xx_HAL_Driver/Inc;../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy;../Drivers/CMSIS/Device/ST/STM32L4xx/Include;../Drivers/CMSIS/Include;../Inc; +CDefines=USE_HAL_DRIVER;STM32L412xx;USE_HAL_DRIVER;USE_HAL_DRIVER; + diff --git a/bsp/stm32/stm32l412-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32l412-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc new file mode 100644 index 0000000000..4727ba50c3 --- /dev/null +++ b/bsp/stm32/stm32l412-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc @@ -0,0 +1,201 @@ +#MicroXplorer Configuration settings - do not modify +File.Version=6 +KeepUserPlacement=false +Mcu.Family=STM32L4 +Mcu.IP0=NVIC +Mcu.IP1=RCC +Mcu.IP2=SYS +Mcu.IP3=USART2 +Mcu.IPNb=4 +Mcu.Name=STM32L412RBTxP +Mcu.Package=LQFP64 +Mcu.Pin0=PC13 +Mcu.Pin1=PC14-OSC32_IN (PC14) +Mcu.Pin10=PA7 +Mcu.Pin11=PB13 +Mcu.Pin12=PA13 (JTMS/SWDIO) +Mcu.Pin13=PA14 (JTCK/SWCLK) +Mcu.Pin14=PB3 (JTDO/TRACESWO) +Mcu.Pin15=VP_SYS_VS_Systick +Mcu.Pin2=PC15-OSC32_OUT (PC15) +Mcu.Pin3=PH0-OSC_IN (PH0) +Mcu.Pin4=PH1-OSC_OUT (PH1) +Mcu.Pin5=PA2 +Mcu.Pin6=PA3 +Mcu.Pin7=PA4 +Mcu.Pin8=PA5 +Mcu.Pin9=PA6 +Mcu.PinsNb=16 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants= +Mcu.UserName=STM32L412RBTxP +MxCube.Version=5.5.0 +MxDb.Version=DB.5.0.50 +NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false +NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:true\:false +NVIC.ForceEnableDMAVector=true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:true\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:true\:false +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false +NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 +NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false +NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true +NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false +PA13\ (JTMS/SWDIO).GPIOParameters=GPIO_Label +PA13\ (JTMS/SWDIO).GPIO_Label=TMS +PA13\ (JTMS/SWDIO).Locked=true +PA13\ (JTMS/SWDIO).Mode=Serial_Wire +PA13\ (JTMS/SWDIO).Signal=SYS_JTMS-SWDIO +PA14\ (JTCK/SWCLK).GPIOParameters=GPIO_Label +PA14\ (JTCK/SWCLK).GPIO_Label=TCK +PA14\ (JTCK/SWCLK).Locked=true +PA14\ (JTCK/SWCLK).Mode=Serial_Wire +PA14\ (JTCK/SWCLK).Signal=SYS_JTCK-SWCLK +PA2.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label +PA2.GPIO_Label=USART_TX +PA2.GPIO_PuPd=GPIO_NOPULL +PA2.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH +PA2.Locked=true +PA2.Mode=Asynchronous +PA2.Signal=USART2_TX +PA3.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label +PA3.GPIO_Label=USART_RX +PA3.GPIO_PuPd=GPIO_NOPULL +PA3.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH +PA3.Locked=true +PA3.Mode=Asynchronous +PA3.Signal=USART2_RX +PA4.GPIOParameters=GPIO_Label +PA4.GPIO_Label=SMPS_EN [ADP5301ACBZ_VEN] +PA4.Locked=true +PA4.Signal=GPIO_Output +PA5.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultOutputPP +PA5.GPIO_Label=SMPS_V1 +PA5.GPIO_ModeDefaultOutputPP=GPIO_MODE_OUTPUT_PP +PA5.GPIO_PuPd=GPIO_NOPULL +PA5.GPIO_Speed=GPIO_SPEED_FREQ_LOW +PA5.Locked=true +PA5.Signal=GPIO_Output +PA6.GPIOParameters=GPIO_PuPd,GPIO_Label +PA6.GPIO_Label=SMPS_PG [ADP5301ACBZ_OUTOK] +PA6.GPIO_PuPd=GPIO_PULLUP +PA6.Locked=true +PA6.Signal=GPIO_Input +PA7.GPIOParameters=GPIO_Label +PA7.GPIO_Label=SMPS_SW [TS3A44159PWR_IN1_2] +PA7.Locked=true +PA7.Signal=GPIO_Output +PB13.GPIOParameters=GPIO_Label +PB13.GPIO_Label=LD4 [green Led] +PB13.Locked=true +PB13.Signal=GPIO_Output +PB3\ (JTDO/TRACESWO).GPIOParameters=GPIO_Label +PB3\ (JTDO/TRACESWO).GPIO_Label=SWO +PB3\ (JTDO/TRACESWO).Locked=true +PB3\ (JTDO/TRACESWO).Signal=SYS_JTDO-SWO +PC13.GPIOParameters=GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultEXTI +PC13.GPIO_Label=B1 [Blue PushButton] +PC13.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_FALLING +PC13.GPIO_PuPd=GPIO_NOPULL +PC13.Locked=true +PC13.Signal=GPXTI13 +PC14-OSC32_IN\ (PC14).Locked=true +PC14-OSC32_IN\ (PC14).Mode=LSE-External-Oscillator +PC14-OSC32_IN\ (PC14).Signal=RCC_OSC32_IN +PC15-OSC32_OUT\ (PC15).Locked=true +PC15-OSC32_OUT\ (PC15).Mode=LSE-External-Oscillator +PC15-OSC32_OUT\ (PC15).Signal=RCC_OSC32_OUT +PCC.Checker=false +PCC.Line=STM32L4x2 +PCC.MCU=STM32L412RBTxP +PCC.PartNumber=STM32L412RBTxP +PCC.Seq0=0 +PCC.Series=STM32L4 +PCC.Temperature=25 +PCC.Vdd=3.0 +PH0-OSC_IN\ (PH0).GPIOParameters=GPIO_Label +PH0-OSC_IN\ (PH0).GPIO_Label=MCO +PH0-OSC_IN\ (PH0).Locked=true +PH0-OSC_IN\ (PH0).Mode=HSE-External-Clock-Source +PH0-OSC_IN\ (PH0).Signal=RCC_OSC_IN +PH1-OSC_OUT\ (PH1).Locked=true +PH1-OSC_OUT\ (PH1).Signal=RCC_OSC_OUT +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=false +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32L412RBTxP +ProjectManager.FirmwarePackage=STM32Cube FW_L4 V1.15.1 +ProjectManager.FreePins=false +ProjectManager.HalAssertFull=false +ProjectManager.HeapSize=0x200 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=0 +ProjectManager.MainLocation=Src +ProjectManager.NoMain=false +ProjectManager.PreviousToolchain= +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=CubeMX_Config.ioc +ProjectManager.ProjectName=CubeMX_Config +ProjectManager.StackSize=0x400 +ProjectManager.TargetToolchain=EWARM V8.32 +ProjectManager.ToolChainLocation= +ProjectManager.UnderRoot=false +ProjectManager.functionlistsort= +RCC.ADCFreq_Value=80000000 +RCC.AHBFreq_Value=80000000 +RCC.APB1Freq_Value=80000000 +RCC.APB1TimFreq_Value=80000000 +RCC.APB2Freq_Value=80000000 +RCC.APB2TimFreq_Value=80000000 +RCC.CRSFreq_Value=48000000 +RCC.CortexFreq_Value=80000000 +RCC.FCLKCortexFreq_Value=80000000 +RCC.FLatency=FLASH_LATENCY_4 +RCC.FamilyName=M +RCC.HCLKFreq_Value=80000000 +RCC.HSE_VALUE=8000000 +RCC.HSI48_VALUE=48000000 +RCC.HSICalibrationValue=16 +RCC.HSI_VALUE=16000000 +RCC.I2C1Freq_Value=80000000 +RCC.I2C2Freq_Value=80000000 +RCC.I2C3Freq_Value=80000000 +RCC.IPParameters=ADCFreq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CRSFreq_Value,CortexFreq_Value,FCLKCortexFreq_Value,FLatency,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI48_VALUE,HSICalibrationValue,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSI_VALUE,MCO1PinFreq_Value,MSIAutoCalibration,MSI_VALUE,PLLN,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PREFETCH_ENABLE,PWRFreq_Value,RNGFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value +RCC.LPTIM1Freq_Value=80000000 +RCC.LPTIM2Freq_Value=80000000 +RCC.LPUART1Freq_Value=80000000 +RCC.LSCOPinFreq_Value=32000 +RCC.LSI_VALUE=32000 +RCC.MCO1PinFreq_Value=80000000 +RCC.MSIAutoCalibration=DISABLED +RCC.MSI_VALUE=4000000 +RCC.PLLN=40 +RCC.PLLQoutputFreq_Value=80000000 +RCC.PLLRCLKFreq_Value=80000000 +RCC.PREFETCH_ENABLE=1 +RCC.PWRFreq_Value=80000000 +RCC.RNGFreq_Value=4000000 +RCC.SYSCLKFreq_VALUE=80000000 +RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK +RCC.USART1Freq_Value=80000000 +RCC.USART2Freq_Value=80000000 +RCC.USART3Freq_Value=80000000 +RCC.USBFreq_Value=4000000 +RCC.VCOInputFreq_Value=4000000 +RCC.VCOOutputFreq_Value=160000000 +SH.GPXTI13.0=GPIO_EXTI13 +SH.GPXTI13.ConfNb=1 +USART2.IPParameters=VirtualMode-Asynchronous +USART2.VirtualMode-Asynchronous=VM_ASYNC +VP_SYS_VS_Systick.Mode=SysTick +VP_SYS_VS_Systick.Signal=SYS_VS_Systick +board=NUCLEO-L412RB-P +boardIOC=true diff --git a/bsp/stm32/stm32l412-st-nucleo/board/CubeMX_Config/Inc/main.h b/bsp/stm32/stm32l412-st-nucleo/board/CubeMX_Config/Inc/main.h new file mode 100644 index 0000000000..b6a62ec316 --- /dev/null +++ b/bsp/stm32/stm32l412-st-nucleo/board/CubeMX_Config/Inc/main.h @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +#define B1_Pin GPIO_PIN_13 +#define B1_GPIO_Port GPIOC +#define MCO_Pin GPIO_PIN_0 +#define MCO_GPIO_Port GPIOH +#define USART_TX_Pin GPIO_PIN_2 +#define USART_TX_GPIO_Port GPIOA +#define USART_RX_Pin GPIO_PIN_3 +#define USART_RX_GPIO_Port GPIOA +#define SMPS_EN_Pin GPIO_PIN_4 +#define SMPS_EN_GPIO_Port GPIOA +#define SMPS_V1_Pin GPIO_PIN_5 +#define SMPS_V1_GPIO_Port GPIOA +#define SMPS_PG_Pin GPIO_PIN_6 +#define SMPS_PG_GPIO_Port GPIOA +#define SMPS_SW_Pin GPIO_PIN_7 +#define SMPS_SW_GPIO_Port GPIOA +#define LD4_Pin GPIO_PIN_13 +#define LD4_GPIO_Port GPIOB +#define TMS_Pin GPIO_PIN_13 +#define TMS_GPIO_Port GPIOA +#define TCK_Pin GPIO_PIN_14 +#define TCK_GPIO_Port GPIOA +#define SWO_Pin GPIO_PIN_3 +#define SWO_GPIO_Port GPIOB +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32l412-st-nucleo/board/CubeMX_Config/Inc/stm32l4xx_hal_conf.h b/bsp/stm32/stm32l412-st-nucleo/board/CubeMX_Config/Inc/stm32l4xx_hal_conf.h new file mode 100644 index 0000000000..b944963fc2 --- /dev/null +++ b/bsp/stm32/stm32l412-st-nucleo/board/CubeMX_Config/Inc/stm32l4xx_hal_conf.h @@ -0,0 +1,450 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_conf.h + * @brief HAL configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L4xx_HAL_CONF_H +#define __STM32L4xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ + +#define HAL_MODULE_ENABLED +/*#define HAL_ADC_MODULE_ENABLED */ +/*#define HAL_CRYP_MODULE_ENABLED */ +/*#define HAL_CAN_MODULE_ENABLED */ +/*#define HAL_COMP_MODULE_ENABLED */ +/*#define HAL_CRC_MODULE_ENABLED */ +/*#define HAL_CRYP_MODULE_ENABLED */ +/*#define HAL_DAC_MODULE_ENABLED */ +/*#define HAL_DCMI_MODULE_ENABLED */ +/*#define HAL_DMA2D_MODULE_ENABLED */ +/*#define HAL_DFSDM_MODULE_ENABLED */ +/*#define HAL_DSI_MODULE_ENABLED */ +/*#define HAL_FIREWALL_MODULE_ENABLED */ +/*#define HAL_GFXMMU_MODULE_ENABLED */ +/*#define HAL_HCD_MODULE_ENABLED */ +/*#define HAL_HASH_MODULE_ENABLED */ +/*#define HAL_I2S_MODULE_ENABLED */ +/*#define HAL_IRDA_MODULE_ENABLED */ +/*#define HAL_IWDG_MODULE_ENABLED */ +/*#define HAL_LTDC_MODULE_ENABLED */ +/*#define HAL_LCD_MODULE_ENABLED */ +/*#define HAL_LPTIM_MODULE_ENABLED */ +/*#define HAL_MMC_MODULE_ENABLED */ +/*#define HAL_NAND_MODULE_ENABLED */ +/*#define HAL_NOR_MODULE_ENABLED */ +/*#define HAL_OPAMP_MODULE_ENABLED */ +/*#define HAL_OSPI_MODULE_ENABLED */ +/*#define HAL_OSPI_MODULE_ENABLED */ +/*#define HAL_PCD_MODULE_ENABLED */ +/*#define HAL_PKA_MODULE_ENABLED */ +/*#define HAL_QSPI_MODULE_ENABLED */ +/*#define HAL_QSPI_MODULE_ENABLED */ +/*#define HAL_RNG_MODULE_ENABLED */ +/*#define HAL_RTC_MODULE_ENABLED */ +/*#define HAL_SAI_MODULE_ENABLED */ +/*#define HAL_SD_MODULE_ENABLED */ +/*#define HAL_SMBUS_MODULE_ENABLED */ +/*#define HAL_SMARTCARD_MODULE_ENABLED */ +/*#define HAL_SPI_MODULE_ENABLED */ +/*#define HAL_SRAM_MODULE_ENABLED */ +/*#define HAL_SWPMI_MODULE_ENABLED */ +/*#define HAL_TIM_MODULE_ENABLED */ +/*#define HAL_TSC_MODULE_ENABLED */ +#define HAL_UART_MODULE_ENABLED +/*#define HAL_USART_MODULE_ENABLED */ +/*#define HAL_WWDG_MODULE_ENABLED */ +/*#define HAL_EXTI_MODULE_ENABLED */ +/*#define HAL_PSSI_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal Multiple Speed oscillator (MSI) default value. + * This value is the default MSI range value after Reset. + */ +#if !defined (MSI_VALUE) + #define MSI_VALUE ((uint32_t)4000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* MSI_VALUE */ +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG. + * This internal oscillator is mainly dedicated to provide a high precision clock to + * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. + * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency + * which is subject to manufacturing process variations. + */ +#if !defined (HSI48_VALUE) + #define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz. + The real value my vary depending on manufacturing process variations.*/ +#endif /* HSI48_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature.*/ + +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for SAI1 peripheral + * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source + * frequency. + */ +#if !defined (EXTERNAL_SAI1_CLOCK_VALUE) + #define EXTERNAL_SAI1_CLOCK_VALUE ((uint32_t)48000U) /*!< Value of the SAI1 External clock source in Hz*/ +#endif /* EXTERNAL_SAI1_CLOCK_VALUE */ + +/** + * @brief External clock source for SAI2 peripheral + * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source + * frequency. + */ +#if !defined (EXTERNAL_SAI2_CLOCK_VALUE) + #define EXTERNAL_SAI2_CLOCK_VALUE ((uint32_t)48000U) /*!< Value of the SAI2 External clock source in Hz*/ +#endif /* EXTERNAL_SAI2_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ + +#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 1U +#define INSTRUCTION_CACHE_ENABLE 1U +#define DATA_CACHE_ENABLE 1U + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver + * Activated: CRC code is present inside driver + * Deactivated: CRC code cleaned from driver + */ + +#define USE_SPI_CRC 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32l4xx_hal_rcc.h" + #include "stm32l4xx_hal_rcc_ex.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32l4xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32l4xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32l4xx_hal_dma.h" + #include "stm32l4xx_hal_dma_ex.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_DFSDM_MODULE_ENABLED + #include "stm32l4xx_hal_dfsdm.h" +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32l4xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32l4xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32l4xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_COMP_MODULE_ENABLED + #include "stm32l4xx_hal_comp.h" +#endif /* HAL_COMP_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32l4xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32l4xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32l4xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32l4xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32l4xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32l4xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + +#ifdef HAL_FIREWALL_MODULE_ENABLED + #include "stm32l4xx_hal_firewall.h" +#endif /* HAL_FIREWALL_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32l4xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32l4xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32l4xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32l4xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32l4xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32l4xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32l4xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32l4xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LCD_MODULE_ENABLED + #include "stm32l4xx_hal_lcd.h" +#endif /* HAL_LCD_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32l4xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32l4xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_OPAMP_MODULE_ENABLED + #include "stm32l4xx_hal_opamp.h" +#endif /* HAL_OPAMP_MODULE_ENABLED */ + +#ifdef HAL_OSPI_MODULE_ENABLED + #include "stm32l4xx_hal_ospi.h" +#endif /* HAL_OSPI_MODULE_ENABLED */ + +#ifdef HAL_PKA_MODULE_ENABLED + #include "stm32l4xx_hal_pka.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32l4xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32l4xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32l4xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32l4xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32l4xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32l4xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32l4xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32l4xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_SWPMI_MODULE_ENABLED + #include "stm32l4xx_hal_swpmi.h" +#endif /* HAL_SWPMI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32l4xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_TSC_MODULE_ENABLED + #include "stm32l4xx_hal_tsc.h" +#endif /* HAL_TSC_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32l4xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32l4xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32l4xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32l4xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32l4xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32l4xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32l4xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_GFXMMU_MODULE_ENABLED + #include "stm32l4xx_hal_gfxmmu.h" +#endif /* HAL_GFXMMU_MODULE_ENABLED */ + +#ifdef HAL_PSSI_MODULE_ENABLED + #include "stm32l4xx_hal_pssi.h" +#endif /* HAL_PSSI_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(char *file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L4xx_HAL_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32l412-st-nucleo/board/CubeMX_Config/Inc/stm32l4xx_it.h b/bsp/stm32/stm32l412-st-nucleo/board/CubeMX_Config/Inc/stm32l4xx_it.h new file mode 100644 index 0000000000..1bedbf684d --- /dev/null +++ b/bsp/stm32/stm32l412-st-nucleo/board/CubeMX_Config/Inc/stm32l4xx_it.h @@ -0,0 +1,69 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32l4xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L4xx_IT_H +#define __STM32L4xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L4xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32l412-st-nucleo/board/CubeMX_Config/Src/main.c b/bsp/stm32/stm32l412-st-nucleo/board/CubeMX_Config/Src/main.c new file mode 100644 index 0000000000..ce0385a5af --- /dev/null +++ b/bsp/stm32/stm32l412-st-nucleo/board/CubeMX_Config/Src/main.c @@ -0,0 +1,280 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +UART_HandleTypeDef huart2; + +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +static void MX_GPIO_Init(void); +static void MX_USART2_UART_Init(void); +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + /* USER CODE BEGIN 1 */ + + /* USER CODE END 1 */ + + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_USART2_UART_Init(); + /* USER CODE BEGIN 2 */ + + /* USER CODE END 2 */ + + + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + } + /* USER CODE END 3 */ +} + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + + /** Configure the main internal regulator output voltage + */ + if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) + { + Error_Handler(); + } + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.MSIState = RCC_MSI_ON; + RCC_OscInitStruct.MSICalibrationValue = 0; + RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; + RCC_OscInitStruct.PLL.PLLM = 1; + RCC_OscInitStruct.PLL.PLLN = 40; + RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; + RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) + { + Error_Handler(); + } + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART2; + PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } +} + +/** + * @brief USART2 Initialization Function + * @param None + * @retval None + */ +static void MX_USART2_UART_Init(void) +{ + + /* USER CODE BEGIN USART2_Init 0 */ + + /* USER CODE END USART2_Init 0 */ + + /* USER CODE BEGIN USART2_Init 1 */ + + /* USER CODE END USART2_Init 1 */ + huart2.Instance = USART2; + huart2.Init.BaudRate = 115200; + huart2.Init.WordLength = UART_WORDLENGTH_8B; + huart2.Init.StopBits = UART_STOPBITS_1; + huart2.Init.Parity = UART_PARITY_NONE; + huart2.Init.Mode = UART_MODE_TX_RX; + huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart2.Init.OverSampling = UART_OVERSAMPLING_16; + huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&huart2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART2_Init 2 */ + + /* USER CODE END USART2_Init 2 */ + +} + +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOA, SMPS_EN_Pin|SMPS_V1_Pin|SMPS_SW_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(LD4_GPIO_Port, LD4_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pin : B1_Pin */ + GPIO_InitStruct.Pin = B1_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pins : SMPS_EN_Pin SMPS_V1_Pin SMPS_SW_Pin */ + GPIO_InitStruct.Pin = SMPS_EN_Pin|SMPS_V1_Pin|SMPS_SW_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /*Configure GPIO pin : SMPS_PG_Pin */ + GPIO_InitStruct.Pin = SMPS_PG_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_PULLUP; + HAL_GPIO_Init(SMPS_PG_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pin : LD4_Pin */ + GPIO_InitStruct.Pin = LD4_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(LD4_GPIO_Port, &GPIO_InitStruct); + +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + + /* USER CODE END Error_Handler_Debug */ +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(char *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32l412-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c b/bsp/stm32/stm32l412-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c new file mode 100644 index 0000000000..4e7628b29c --- /dev/null +++ b/bsp/stm32/stm32l412-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c @@ -0,0 +1,149 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * File Name : stm32l4xx_hal_msp.c + * Description : This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); + + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/** +* @brief UART MSP Initialization +* This function configures the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspInit(UART_HandleTypeDef* huart) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(huart->Instance==USART2) + { + /* USER CODE BEGIN USART2_MspInit 0 */ + + /* USER CODE END USART2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_USART2_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**USART2 GPIO Configuration + PA2 ------> USART2_TX + PA3 ------> USART2_RX + */ + GPIO_InitStruct.Pin = USART_TX_Pin|USART_RX_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF7_USART2; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN USART2_MspInit 1 */ + + /* USER CODE END USART2_MspInit 1 */ + } + +} + +/** +* @brief UART MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) +{ + if(huart->Instance==USART2) + { + /* USER CODE BEGIN USART2_MspDeInit 0 */ + + /* USER CODE END USART2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART2_CLK_DISABLE(); + + /**USART2 GPIO Configuration + PA2 ------> USART2_TX + PA3 ------> USART2_RX + */ + HAL_GPIO_DeInit(GPIOA, USART_TX_Pin|USART_RX_Pin); + + /* USER CODE BEGIN USART2_MspDeInit 1 */ + + /* USER CODE END USART2_MspDeInit 1 */ + } + +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32l412-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_it.c b/bsp/stm32/stm32l412-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_it.c new file mode 100644 index 0000000000..8f827e4821 --- /dev/null +++ b/bsp/stm32/stm32l412-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_it.c @@ -0,0 +1,203 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32l4xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32l4xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ + +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M4 Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } +} + +/** + * @brief This function handles Prefetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn 0 */ + + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ + + /* USER CODE END SVCall_IRQn 1 */ +} + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn 0 */ + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32L4xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32l4xx.s). */ +/******************************************************************************/ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32l412-st-nucleo/board/CubeMX_Config/Src/system_stm32l4xx.c b/bsp/stm32/stm32l412-st-nucleo/board/CubeMX_Config/Src/system_stm32l4xx.c new file mode 100644 index 0000000000..26bd517974 --- /dev/null +++ b/bsp/stm32/stm32l412-st-nucleo/board/CubeMX_Config/Src/system_stm32l4xx.c @@ -0,0 +1,337 @@ +/** + ****************************************************************************** + * @file system_stm32l4xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32l4xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * After each device reset the MSI (4 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to + * configure the system clock before to branch to main program. + * + * This file configures the system clock as follows: + *============================================================================= + *----------------------------------------------------------------------------- + * System Clock source | MSI + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 4000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 4000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 1 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 1 + *----------------------------------------------------------------------------- + * PLL_M | 1 + *----------------------------------------------------------------------------- + * PLL_N | 8 + *----------------------------------------------------------------------------- + * PLL_P | 7 + *----------------------------------------------------------------------------- + * PLL_Q | 2 + *----------------------------------------------------------------------------- + * PLL_R | 2 + *----------------------------------------------------------------------------- + * PLLSAI1_P | NA + *----------------------------------------------------------------------------- + * PLLSAI1_Q | NA + *----------------------------------------------------------------------------- + * PLLSAI1_R | NA + *----------------------------------------------------------------------------- + * PLLSAI2_P | NA + *----------------------------------------------------------------------------- + * PLLSAI2_Q | NA + *----------------------------------------------------------------------------- + * PLLSAI2_R | NA + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Disabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32l4xx_system + * @{ + */ + +/** @addtogroup STM32L4xx_System_Private_Includes + * @{ + */ + +#include "stm32l4xx.h" + +#if !defined (HSE_VALUE) + #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (MSI_VALUE) + #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/ +#endif /* MSI_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32L4xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L4xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/******************************************************************************/ +/** + * @} + */ + +/** @addtogroup STM32L4xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L4xx_System_Private_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 4000000U; + + const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; + const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; + const uint32_t MSIRangeTable[12] = {100000U, 200000U, 400000U, 800000U, 1000000U, 2000000U, \ + 4000000U, 8000000U, 16000000U, 24000000U, 32000000U, 48000000U}; +/** + * @} + */ + +/** @addtogroup STM32L4xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L4xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ + +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + #endif + + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set MSION bit */ + RCC->CR |= RCC_CR_MSION; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000U; + + /* Reset HSEON, CSSON , HSION, and PLLON bits */ + RCC->CR &= 0xEAF6FFFFU; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x00001000U; + + /* Reset HSEBYP bit */ + RCC->CR &= 0xFFFBFFFFU; + + /* Disable all interrupts */ + RCC->CIER = 0x00000000U; + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*) + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***) + * or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) MSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value + * 4 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***) HSE_VALUE is a constant defined in stm32l4xx_hal.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0U, msirange = 0U, pllvco = 0U, pllr = 2U, pllsource = 0U, pllm = 2U; + + /* Get MSI Range frequency--------------------------------------------------*/ + if((RCC->CR & RCC_CR_MSIRGSEL) == RESET) + { /* MSISRANGE from RCC_CSR applies */ + msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U; + } + else + { /* MSIRANGE from RCC_CR applies */ + msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U; + } + /*MSI frequency range in HZ*/ + msirange = MSIRangeTable[msirange]; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case 0x00: /* MSI used as system clock source */ + SystemCoreClock = msirange; + break; + + case 0x04: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + + case 0x08: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + + case 0x0C: /* PLL used as system clock source */ + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); + pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4U) + 1U ; + + switch (pllsource) + { + case 0x02: /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm); + break; + + case 0x03: /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm); + break; + + default: /* MSI used as PLL clock source */ + pllvco = (msirange / pllm); + break; + } + pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8U); + pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25U) + 1U) * 2U; + SystemCoreClock = pllvco/pllr; + break; + + default: + SystemCoreClock = msirange; + break; + } + /* Compute HCLK clock frequency --------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32l412-st-nucleo/board/Kconfig b/bsp/stm32/stm32l412-st-nucleo/board/Kconfig new file mode 100644 index 0000000000..10d3a3ad30 --- /dev/null +++ b/bsp/stm32/stm32l412-st-nucleo/board/Kconfig @@ -0,0 +1,74 @@ +menu "Hardware Drivers Config" + +config SOC_STM32L412RB + bool + select SOC_SERIES_STM32L4 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "Onboard Peripheral Drivers" + config BSP_USING_STLINK_TO_USART + bool "Enable STLINK TO USART (uart2)" + select BSP_USING_UART + select BSP_USING_UART2 + default y +endmenu + +menu "On-chip Peripheral Drivers" + + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART2 + bool "Enable UART2" + default n + + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + endif + + config BSP_USING_ON_CHIP_FLASH + bool "Enable on-chip FLASH" + default n + + menuconfig BSP_USING_ONCHIP_RTC + bool "Enable RTC" + select RT_USING_RTC + select RT_USING_LIBC + default n + if BSP_USING_ONCHIP_RTC + choice + prompt "Select clock source" + default BSP_RTC_USING_LSE + + config BSP_RTC_USING_LSE + bool "RTC USING LSE" + + config BSP_RTC_USING_LSI + bool "RTC USING LSI" + endchoice + endif + + config BSP_USING_WDT + bool "Enable Watchdog Timer" + select RT_USING_WDT + default n + source "../libraries/HAL_Drivers/Kconfig" + +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/stm32/stm32l412-st-nucleo/board/SConscript b/bsp/stm32/stm32l412-st-nucleo/board/SConscript new file mode 100644 index 0000000000..6c39045b35 --- /dev/null +++ b/bsp/stm32/stm32l412-st-nucleo/board/SConscript @@ -0,0 +1,39 @@ +import os +import rtconfig +from building import * + +Import('SDK_LIB') + +cwd = GetCurrentDir() + +# add general drivers +src = Split(''' +board.c +CubeMX_Config/Src/stm32l4xx_hal_msp.c +''') + +path = [cwd] +path += [cwd + '/CubeMX_Config/Inc'] + +startup_path_prefix = SDK_LIB + +if rtconfig.CROSS_TOOL == 'gcc': + src += [startup_path_prefix + '/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/startup_stm32l412xx.s'] +elif rtconfig.CROSS_TOOL == 'keil': + src += [startup_path_prefix + '/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/arm/startup_stm32l412xx.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src += [startup_path_prefix + '/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/startup_stm32l412xx.s'] + +# STM32L412xx || STM32L422xx || STM32L431xx +# STM32L432xx || STM32L433xx || STM32L442xx +# STM32L443xx || STM32L451xx || STM32L452xx +# STM32L462xx || STM32L471xx || STM32L475xx +# STM32L476xx || STM32L485xx || STM32L486xx +# STM32L496xx || STM32L4A6xx || STM32L4R5xx +# STM32L4R7xx || STM32L4R9xx || STM32L4S5xx +# STM32L4S7xx || STM32L4S9xx +# You can select chips from the list above +CPPDEFINES = ['STM32L412xx'] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/stm32/stm32l412-st-nucleo/board/board.c b/bsp/stm32/stm32l412-st-nucleo/board/board.c new file mode 100644 index 0000000000..70a17da702 --- /dev/null +++ b/bsp/stm32/stm32l412-st-nucleo/board/board.c @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-04-24 luhuadong first version + */ + +#include "board.h" + +void SystemClock_Config(void) +{ + + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_PeriphCLKInitTypeDef PeriphClkInit; + + /**Configure LSE Drive Capability + */ + HAL_PWR_EnableBkUpAccess(); + + __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); + + /**Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE|RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct.MSIState = RCC_MSI_ON; + RCC_OscInitStruct.MSICalibrationValue = 0; + RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; + RCC_OscInitStruct.PLL.PLLM = 1; + RCC_OscInitStruct.PLL.PLLN = 40; + RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; + RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + _Error_Handler(__FILE__, __LINE__); + } + + /**Initializes the CPU, AHB and APB busses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) + { + _Error_Handler(__FILE__, __LINE__); + } + + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART2; + PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + _Error_Handler(__FILE__, __LINE__); + } + + /**Configure the main internal regulator output voltage + */ + if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) + { + _Error_Handler(__FILE__, __LINE__); + } + + /**Configure the Systick interrupt time + */ + HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000); + + /**Configure the Systick + */ + HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); + + /**Enable MSI Auto calibration + */ + HAL_RCCEx_EnableMSIPLLMode(); + + /* SysTick_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0); +} diff --git a/bsp/stm32/stm32l412-st-nucleo/board/board.h b/bsp/stm32/stm32l412-st-nucleo/board/board.h new file mode 100644 index 0000000000..e88c9168b4 --- /dev/null +++ b/bsp/stm32/stm32l412-st-nucleo/board/board.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-04-24 luhuadong first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include +#include "drv_common.h" +#include "drv_gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define STM32_FLASH_START_ADRESS ((uint32_t)0x08000000) +#define STM32_FLASH_SIZE (128 * 1024) +#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE)) + +#define STM32_SRAM1_SIZE (32) +#define STM32_SRAM1_START (0x20000000) +#define STM32_SRAM1_END (STM32_SRAM1_START + STM32_SRAM1_SIZE * 1024) + +#define HEAP_BEGIN STM32_SRAM1_START +#define HEAP_END STM32_SRAM1_END + +void SystemClock_Config(void); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/bsp/stm32/stm32l412-st-nucleo/board/linker_scripts/link.icf b/bsp/stm32/stm32l412-st-nucleo/board/linker_scripts/link.icf new file mode 100644 index 0000000000..1d95e70851 --- /dev/null +++ b/bsp/stm32/stm32l412-st-nucleo/board/linker_scripts/link.icf @@ -0,0 +1,33 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF; +define symbol __ICFEDIT_region_RAM1_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM1_end__ = 0x2000BFFF; +define symbol __ICFEDIT_region_RAM2_start__ = 0x10000000; +define symbol __ICFEDIT_region_RAM2_end__ = 0x10003FFF; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x0400; +define symbol __ICFEDIT_size_heap__ = 0x0000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM1_region = mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__]; +define region RAM2_region = mem:[from __ICFEDIT_region_RAM2_start__ to __ICFEDIT_region_RAM2_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM1_region { section .sram }; +place in RAM2_region { readwrite, last block CSTACK}; diff --git a/bsp/stm32/stm32l412-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32l412-st-nucleo/board/linker_scripts/link.lds new file mode 100644 index 0000000000..77624514bf --- /dev/null +++ b/bsp/stm32/stm32l412-st-nucleo/board/linker_scripts/link.lds @@ -0,0 +1,158 @@ +/* + * linker script for STM32L4XX with GNU ld + */ + +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + ROM (rx) : ORIGIN = 0x08000000, LENGTH = 128k /* 128KB flash */ + RAM1 (rw) : ORIGIN = 0x20000000, LENGTH = 32k /* 32K sram */ + RAM2 (rw) : ORIGIN = 0x10000000, LENGTH = 8k /* 8K sram */ +} +ENTRY(Reset_Handler) +_system_stack_size = 0x200; + +SECTIONS +{ + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + . = ALIGN(4); + + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(4); + + _etext = .; + } > ROM = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > ROM + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >RAM1 + + .stack : + { + . = ALIGN(4); + _sstack = .; + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } >RAM1 + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > RAM1 + __bss_end = .; + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/stm32/stm32l412-st-nucleo/board/linker_scripts/link.sct b/bsp/stm32/stm32l412-st-nucleo/board/linker_scripts/link.sct new file mode 100644 index 0000000000..ed86f920e0 --- /dev/null +++ b/bsp/stm32/stm32l412-st-nucleo/board/linker_scripts/link.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x08000000 0x00040000 { ; load region size_region + ER_IROM1 0x08000000 0x00040000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM2 0x10000000 0x00004000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/stm32/stm32l412-st-nucleo/figures/board.jpg b/bsp/stm32/stm32l412-st-nucleo/figures/board.jpg new file mode 100644 index 0000000000..e2029fd020 Binary files /dev/null and b/bsp/stm32/stm32l412-st-nucleo/figures/board.jpg differ diff --git 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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + STM32L412CBTx + STMicroelectronics + Keil.STM32L4xx_DFP.2.3.0 + https://www.keil.com/pack/ + IRAM(0x20000000,0x00008000) IRAM2(0x10000000,0x00002000) IROM(0x08000000,0x00020000) CPUTYPE("Cortex-M4") FPU2 DSP CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32L4xx_128 -FS08000000 -FL020000 -FP0($$Device:STM32L412CBTx$CMSIS\Flash\STM32L4xx_128.FLM)) + 0 + $$Device:STM32L412CBTx$Drivers\CMSIS\Device\ST\STM32L4xx\Include\stm32l4xx.h + + + + + + + + + + $$Device:STM32L412CBTx$CMSIS\SVD\STM32L412.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 1 + 1 + 1 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 1 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 1 + 0x8000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 0 + 0x10000000 + 0x2000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + USE_HAL_DRIVER, STM32L412xx, RT_USING_ARM_LIBC + + .;..\..\..\include;.;applications;board;board\CubeMX_Config\Inc;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\compilers\armlibc;..\..\..\components\libc\compilers\common;..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Inc;..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Include;..\libraries\STM32L4xx_HAL\CMSIS\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + Kernel + + + clock.c + 1 + ..\..\..\src\clock.c + + + components.c + 1 + ..\..\..\src\components.c + + + device.c + 1 + ..\..\..\src\device.c + + + idle.c + 1 + ..\..\..\src\idle.c + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + irq.c + 1 + ..\..\..\src\irq.c + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + mem.c + 1 + ..\..\..\src\mem.c + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + object.c + 1 + ..\..\..\src\object.c + + + scheduler.c + 1 + ..\..\..\src\scheduler.c + + + signal.c + 1 + ..\..\..\src\signal.c + + + thread.c + 1 + ..\..\..\src\thread.c + + + timer.c + 1 + ..\..\..\src\timer.c + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + Drivers + + + board.c + 1 + board\board.c + + + stm32l4xx_hal_msp.c + 1 + board\CubeMX_Config\Src\stm32l4xx_hal_msp.c + + + startup_stm32l412xx.s + 2 + ..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Source\Templates\arm\startup_stm32l412xx.s + + + drv_gpio.c + 1 + ..\libraries\HAL_Drivers\drv_gpio.c + + + drv_usart.c + 1 + ..\libraries\HAL_Drivers\drv_usart.c + + + drv_common.c + 1 + ..\libraries\HAL_Drivers\drv_common.c + + + + + cpu + + + backtrace.c + 1 + ..\..\..\libcpu\arm\common\backtrace.c + + + div0.c + 1 + ..\..\..\libcpu\arm\common\div0.c + + + showmem.c + 1 + ..\..\..\libcpu\arm\common\showmem.c + + + cpuport.c + 1 + ..\..\..\libcpu\arm\cortex-m4\cpuport.c + + + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m4\context_rvds.S + + + + + DeviceDrivers + + + pin.c + 1 + ..\..\..\components\drivers\misc\pin.c + + + rtc.c + 1 + ..\..\..\components\drivers\rtc\rtc.c + + + serial.c + 1 + ..\..\..\components\drivers\serial\serial.c + + + completion.c + 1 + ..\..\..\components\drivers\src\completion.c + + + dataqueue.c + 1 + ..\..\..\components\drivers\src\dataqueue.c + + + pipe.c + 1 + ..\..\..\components\drivers\src\pipe.c + + + ringblk_buf.c + 1 + ..\..\..\components\drivers\src\ringblk_buf.c + + + ringbuffer.c + 1 + ..\..\..\components\drivers\src\ringbuffer.c + + + waitqueue.c + 1 + ..\..\..\components\drivers\src\waitqueue.c + + + workqueue.c + 1 + ..\..\..\components\drivers\src\workqueue.c + + + watchdog.c + 1 + ..\..\..\components\drivers\watchdog\watchdog.c + + + + + finsh + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + + msh.c + 1 + ..\..\..\components\finsh\msh.c + + + + + libc + + + libc.c + 1 + ..\..\..\components\libc\compilers\armlibc\libc.c + + + mem_std.c + 1 + ..\..\..\components\libc\compilers\armlibc\mem_std.c + + + stubs.c + 1 + ..\..\..\components\libc\compilers\armlibc\stubs.c + + + time.c + 1 + ..\..\..\components\libc\compilers\common\time.c + + + + + STM32_HAL + + + system_stm32l4xx.c + 1 + ..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Source\Templates\system_stm32l4xx.c + + + stm32l4xx_hal.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal.c + + + stm32l4xx_hal_comp.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_comp.c + + + stm32l4xx_hal_cortex.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cortex.c + + + stm32l4xx_hal_crc.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc.c + + + stm32l4xx_hal_crc_ex.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc_ex.c + + + stm32l4xx_hal_cryp.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cryp.c + + + stm32l4xx_hal_cryp_ex.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cryp_ex.c + + + stm32l4xx_hal_dma.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma.c + + + stm32l4xx_hal_dma_ex.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma_ex.c + + + stm32l4xx_hal_exti.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_exti.c + + + stm32l4xx_hal_pwr.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr.c + + + stm32l4xx_hal_pwr_ex.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr_ex.c + + + stm32l4xx_hal_rcc.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc.c + + + stm32l4xx_hal_rcc_ex.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc_ex.c + + + stm32l4xx_hal_rng.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rng.c + + + stm32l4xx_hal_gpio.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_gpio.c + + + stm32l4xx_hal_uart.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart.c + + + stm32l4xx_hal_uart_ex.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart_ex.c + + + stm32l4xx_hal_usart.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_usart.c + + + stm32l4xx_hal_usart_ex.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_usart_ex.c + + + stm32l4xx_hal_rtc.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rtc.c + + + stm32l4xx_hal_rtc_ex.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rtc_ex.c + + + stm32l4xx_hal_iwdg.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_iwdg.c + + + stm32l4xx_hal_wwdg.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_wwdg.c + + + + + + + + + + + + + + diff --git a/bsp/stm32/stm32l412-st-nucleo/rtconfig.h b/bsp/stm32/stm32l412-st-nucleo/rtconfig.h new file mode 100644 index 0000000000..4c3726610c --- /dev/null +++ b/bsp/stm32/stm32l412-st-nucleo/rtconfig.h @@ -0,0 +1,174 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_DEBUG +#define RT_DEBUG_COLOR + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 256 +#define RT_CONSOLE_DEVICE_NAME "uart2" +#define RT_VER_NUM 0x40003 +#define ARCH_ARM +#define RT_USING_CPU_FFS +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M4 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_USING_MSH_ONLY +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN +#define RT_USING_RTC +#define RT_USING_WDT + +/* Using USB */ + + +/* POSIX layer and C standard library */ + +#define RT_USING_LIBC + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + + +/* peripheral libraries and drivers */ + + +/* miscellaneous packages */ + + +/* samples: kernel and components samples */ + +#define SOC_FAMILY_STM32 +#define SOC_SERIES_STM32L4 + +/* Hardware Drivers Config */ + +#define SOC_STM32L412RB + +/* Onboard Peripheral Drivers */ + +#define BSP_USING_STLINK_TO_USART + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART2 + +/* Board extended module Drivers */ + + +#endif diff --git a/bsp/stm32/stm32l412-st-nucleo/rtconfig.py b/bsp/stm32/stm32l412-st-nucleo/rtconfig.py new file mode 100644 index 0000000000..ad5c811ba7 --- /dev/null +++ b/bsp/stm32/stm32l412-st-nucleo/rtconfig.py @@ -0,0 +1,150 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4.fp ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict --scatter "board\linker_scripts\link.sct"' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=VFPv4_sp' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' --fpu VFPv4_sp' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/stm32l412-st-nucleo/template.ewp b/bsp/stm32/stm32l412-st-nucleo/template.ewp new file mode 100644 index 0000000000..f390ad7bc1 --- /dev/null +++ b/bsp/stm32/stm32l412-st-nucleo/template.ewp @@ -0,0 +1,2031 @@ + + + 3 + + rt-thread + + ARM + + 1 + + General + 3 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 34 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 20 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 20 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + diff --git a/bsp/stm32/stm32l412-st-nucleo/template.eww b/bsp/stm32/stm32l412-st-nucleo/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/stm32/stm32l412-st-nucleo/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/stm32/stm32l412-st-nucleo/template.uvoptx b/bsp/stm32/stm32l412-st-nucleo/template.uvoptx new file mode 100644 index 0000000000..d18ee55260 --- /dev/null +++ b/bsp/stm32/stm32l412-st-nucleo/template.uvoptx @@ -0,0 +1,186 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 5 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + ST-LINKIII-KEIL_SWO + -U066AFF534854845187093307 -O206 -S0 -C0 -A0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32L4xx_256 -FS08000000 -FL040000 -FP0($$Device:STM32L432KCUx$CMSIS\Flash\STM32L4xx_256.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0STM32L4xx_256 -FL040000 -FS08000000 -FP0($$Device:STM32L432KCUx$CMSIS\Flash\STM32L4xx_256.FLM) + + + 0 + JL2CM3 + -U -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32L4xx_512.FLM -FS08000000 -FL080000 -FP0($$Device:STM32L475VETx$CMSIS\Flash\STM32L4xx_512.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + 0 + + 1 + 0 + 2 + 10000000 + + + + + + Source Group 1 + 0 + 0 + 0 + 0 + + + diff --git a/bsp/stm32/stm32l412-st-nucleo/template.uvprojx b/bsp/stm32/stm32l412-st-nucleo/template.uvprojx new file mode 100644 index 0000000000..01e792faf7 --- /dev/null +++ b/bsp/stm32/stm32l412-st-nucleo/template.uvprojx @@ -0,0 +1,386 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060300::V5.06 update 3 (build 300)::ARMCC + + + STM32L432KCUx + STMicroelectronics + Keil.STM32L4xx_DFP.2.0.0 + http://www.keil.com/pack + IRAM(0x20000000,0x0000C000) IRAM2(0x10000000,0x00004000) IROM(0x08000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32L4xx_256 -FS08000000 -FL040000 -FP0($$Device:STM32L432KCUx$CMSIS\Flash\STM32L4xx_256.FLM)) + 0 + $$Device:STM32L432KCUx$Drivers\CMSIS\Device\ST\STM32L4xx\Include\stm32l4xx.h + + + + + + + + + + $$Device:STM32L432KCUx$CMSIS\SVD\STM32L4x2.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 1 + 1 + 1 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 1 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0xc000 + + + 1 + 0x8000000 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x40000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + Source Group 1 + + + + + + diff --git a/bsp/stm32/stm32l432-st-nucleo/rtconfig.py b/bsp/stm32/stm32l432-st-nucleo/rtconfig.py index 2e022a964b..deb2083359 100644 --- a/bsp/stm32/stm32l432-st-nucleo/rtconfig.py +++ b/bsp/stm32/stm32l432-st-nucleo/rtconfig.py @@ -141,3 +141,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/stm32l452-st-nucleo/rtconfig.py b/bsp/stm32/stm32l452-st-nucleo/rtconfig.py index 2e022a964b..deb2083359 100644 --- a/bsp/stm32/stm32l452-st-nucleo/rtconfig.py +++ b/bsp/stm32/stm32l452-st-nucleo/rtconfig.py @@ -141,3 +141,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/stm32l475-atk-pandora/rtconfig.py b/bsp/stm32/stm32l475-atk-pandora/rtconfig.py index 40b84ad846..dddfc31180 100644 --- a/bsp/stm32/stm32l475-atk-pandora/rtconfig.py +++ b/bsp/stm32/stm32l475-atk-pandora/rtconfig.py @@ -142,3 +142,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/stm32l475-st-discovery/rtconfig.py b/bsp/stm32/stm32l475-st-discovery/rtconfig.py index 3e4718a482..c02cbb090a 100644 --- a/bsp/stm32/stm32l475-st-discovery/rtconfig.py +++ b/bsp/stm32/stm32l475-st-discovery/rtconfig.py @@ -141,3 +141,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/stm32l476-st-nucleo/README.md b/bsp/stm32/stm32l476-st-nucleo/README.md index cd8ad13f9c..e1784c3855 100644 --- a/bsp/stm32/stm32l476-st-nucleo/README.md +++ b/bsp/stm32/stm32l476-st-nucleo/README.md @@ -43,6 +43,9 @@ | UART | 支持 | UART2 | | IIC | 支持 | 软件模拟 | | RTC | 支持 | 支持外部晶振和内部低速时钟 | +| SPI | 支持 | SPI1/2/3 | +| ADC | 支持 | ADC1_IN1/ADC2_IN2/ADC3_IN3 | +| TIME | 支持 | TIME15/16/17 | | **扩展模块** | **支持情况** | **备注** | ## 使用说明 diff --git a/bsp/stm32/stm32l476-st-nucleo/board/CubeMX_Config/.mxproject b/bsp/stm32/stm32l476-st-nucleo/board/CubeMX_Config/.mxproject index ef81df8fbd..838bcf2aa4 100644 --- a/bsp/stm32/stm32l476-st-nucleo/board/CubeMX_Config/.mxproject +++ b/bsp/stm32/stm32l476-st-nucleo/board/CubeMX_Config/.mxproject @@ -1,13 +1,14 @@ [PreviousGenFiles] -HeaderPath=D:/VariousProject/rt-thread/bsp/stm32/stm32l476-st-nucleo/board/CubeMX_Config/Inc +HeaderPath=G:/1 Code/rt-thread/bsp/stm32/stm32l476-st-nucleo/board/CubeMX_Config/Inc HeaderFiles=stm32l4xx_it.h;stm32l4xx_hal_conf.h;main.h; -SourcePath=D:/VariousProject/rt-thread/bsp/stm32/stm32l476-st-nucleo/board/CubeMX_Config/Src +SourcePath=G:/1 Code/rt-thread/bsp/stm32/stm32l476-st-nucleo/board/CubeMX_Config/Src SourceFiles=stm32l4xx_it.c;stm32l4xx_hal_msp.c;main.c; [PreviousLibFiles] -LibFiles=Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h;Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h;Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l476xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;Drivers/CMSIS/Include/arm_common_tables.h;Drivers/CMSIS/Include/arm_const_structs.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cmFunc.h;Drivers/CMSIS/Include/core_cmInstr.h;Drivers/CMSIS/Include/core_cmSimd.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h; +LibFiles=Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h;Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_lptim.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_lptim.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h;Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_lptim.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l476xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/tz_context.h; [PreviousUsedKeilFiles] -SourceFiles=..\Src\main.c;..\Src\stm32l4xx_it.c;..\Src\stm32l4xx_hal_msp.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;../\Src/system_stm32l4xx.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;../\Src/system_stm32l4xx.c;../Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;D:/VariousProject/rt-thread/bsp/stm32/stm32l476-st-nucleo/board/CubeMX_Config//MDK-ARM/startup_stm32l476xx.s; -HeaderPath=..\Drivers\STM32L4xx_HAL_Driver\Inc;..\Drivers\STM32L4xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32L4xx\Include;..\Drivers\CMSIS\Include;..\Inc; +SourceFiles=..\Src\main.c;..\Src\stm32l4xx_it.c;..\Src\stm32l4xx_hal_msp.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_lptim.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;..\\Src/system_stm32l4xx.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_lptim.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;..\\Src/system_stm32l4xx.c;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;; +HeaderPath=F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers\STM32L4xx_HAL_Driver\Inc;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers\STM32L4xx_HAL_Driver\Inc\Legacy;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers\CMSIS\Device\ST\STM32L4xx\Include;F:\STM32Cube\Repository\STM32Cube_FW_L4_V1.15.1\Drivers\CMSIS\Include;..\Inc; +CDefines=USE_HAL_DRIVER;STM32L476xx;USE_HAL_DRIVER;USE_HAL_DRIVER; diff --git a/bsp/stm32/stm32l476-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32l476-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc index 243a1fafd1..7d78ad4047 100644 --- a/bsp/stm32/stm32l476-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32l476-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc @@ -1,146 +1,234 @@ #MicroXplorer Configuration settings - do not modify -File.Version=6 -KeepUserPlacement=false Mcu.Family=STM32L4 -Mcu.IP0=NVIC -Mcu.IP1=RCC -Mcu.IP2=RTC -Mcu.IP3=SYS -Mcu.IP4=USART2 -Mcu.IPNb=5 -Mcu.Name=STM32L476R(C-E-G)Tx -Mcu.Package=LQFP64 +PC3.Mode=Full_Duplex_Master +ProjectManager.MainLocation=Src +PA6.Mode=Full_Duplex_Master +RCC.USART1Freq_Value=80000000 +RCC.SAI1Freq_Value=18285714.285714287 +USART2.IPParameters=VirtualMode-Asynchronous +RCC.CortexFreq_Value=80000000 +SPI3.Direction=SPI_DIRECTION_2LINES +VP_TIM17_VS_ClockSourceINT.Mode=Enable_Timer +SPI3.VirtualType=VM_MASTER +ProjectManager.KeepUserCode=true +Mcu.UserName=STM32L476RGTx +SPI1.VirtualType=VM_MASTER +SPI2.VirtualType=VM_MASTER +PB10.Mode=Full_Duplex_Master +ADC2.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_2 +SH.ADCx_IN2.0=ADC2_IN2,IN2-Single-Ended +PC10.Signal=SPI3_SCK +PC12.Signal=SPI3_MOSI +RCC.PLLSAI1RoutputFreq_Value=64000000 +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART2_UART_Init-USART2-false-HAL-true,4-MX_RTC_Init-RTC-false-HAL-true,5-MX_SPI1_Init-SPI1-false-HAL-true,6-MX_SPI2_Init-SPI2-false-HAL-true,7-MX_SPI3_Init-SPI3-false-HAL-true,8-MX_TIM15_Init-TIM15-false-HAL-true,9-MX_TIM16_Init-TIM16-false-HAL-true,10-MX_TIM17_Init-TIM17-false-HAL-true,11-MX_ADC1_Init-ADC1-false-HAL-true,12-MX_ADC2_Init-ADC2-false-HAL-true,13-MX_ADC3_Init-ADC3-false-HAL-true,14-MX_LPTIM1_Init-LPTIM1-false-HAL-true +VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled +RCC.RTCFreq_Value=32768 +RCC.USART2Freq_Value=80000000 +PC15-OSC32_OUT\ (PC15).Mode=LSE-External-Oscillator +ADC3.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_3 +PinOutPanel.RotationAngle=0 +RCC.MCO1PinFreq_Value=80000000 +RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK +ProjectManager.StackSize=0x400 +PC14-OSC32_IN\ (PC14).Mode=LSE-External-Oscillator +PA14\ (JTCK-SWCLK).Signal=SYS_JTCK-SWCLK +RCC.I2C3Freq_Value=80000000 +RCC.LPTIM1Freq_Value=80000000 +Mcu.IP4=NVIC +Mcu.IP5=RCC +RCC.FCLKCortexFreq_Value=80000000 +Mcu.IP2=ADC3 +NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false +Mcu.IP3=LPTIM1 +Mcu.IP0=ADC1 +Mcu.IP1=ADC2 +Mcu.UserConstants= +RCC.VCOSAI1OutputFreq_Value=128000000 +RCC.SDMMCFreq_Value=64000000 +Mcu.ThirdPartyNb=0 +SPI1.Direction=SPI_DIRECTION_2LINES +RCC.HCLKFreq_Value=80000000 +SH.ADCx_IN3.0=ADC3_IN3,IN3-Single-Ended +Mcu.IPNb=15 +ProjectManager.PreviousToolchain= +RCC.APB2TimFreq_Value=80000000 +SPI1.CalculateBaudRate=40.0 MBits/s +SH.ADCx_IN3.ConfNb=1 +PC3.Signal=SPI2_MOSI +Mcu.Pin6=PA2 +RCC.SAI2Freq_Value=18285714.285714287 +Mcu.Pin7=PA3 +Mcu.Pin8=PA5 +Mcu.Pin9=PA6 +RCC.AHBFreq_Value=80000000 Mcu.Pin0=PC14-OSC32_IN (PC14) Mcu.Pin1=PC15-OSC32_OUT (PC15) -Mcu.Pin2=PA2 -Mcu.Pin3=PA3 -Mcu.Pin4=PA13 (JTMS-SWDIO) -Mcu.Pin5=PA14 (JTCK-SWCLK) -Mcu.Pin6=VP_RTC_VS_RTC_Activate -Mcu.Pin7=VP_SYS_VS_Systick -Mcu.PinsNb=8 -Mcu.ThirdPartyNb=0 -Mcu.UserConstants= -Mcu.UserName=STM32L476RGTx -MxCube.Version=5.0.1 -MxDb.Version=DB.5.0.1 -NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false -NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false -NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false -NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false -NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false -NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false -NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 -NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false -NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false -NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false -PA13\ (JTMS-SWDIO).Mode=Serial_Wire -PA13\ (JTMS-SWDIO).Signal=SYS_JTMS-SWDIO -PA14\ (JTCK-SWCLK).Mode=Serial_Wire -PA14\ (JTCK-SWCLK).Signal=SYS_JTCK-SWCLK -PA2.Mode=Asynchronous -PA2.Signal=USART2_TX -PA3.Mode=Asynchronous -PA3.Signal=USART2_RX -PC14-OSC32_IN\ (PC14).Mode=LSE-External-Oscillator -PC14-OSC32_IN\ (PC14).Signal=RCC_OSC32_IN -PC15-OSC32_OUT\ (PC15).Mode=LSE-External-Oscillator -PC15-OSC32_OUT\ (PC15).Signal=RCC_OSC32_OUT -PCC.Checker=true -PCC.Line=STM32L4x6 -PCC.MCU=STM32L476R(C-E-G)Tx -PCC.PartNumber=STM32L476RGTx -PCC.Seq0=0 -PCC.Series=STM32L4 -PCC.Temperature=25 -PCC.Vdd=null -PinOutPanel.RotationAngle=0 -ProjectManager.AskForMigrate=true -ProjectManager.BackupPrevious=false -ProjectManager.CompilerOptimize=6 -ProjectManager.ComputerToolchain=false -ProjectManager.CoupleFile=false -ProjectManager.CustomerFirmwarePackage= -ProjectManager.DefaultFWLocation=true -ProjectManager.DeletePrevious=true -ProjectManager.DeviceId=STM32L476RGTx -ProjectManager.FirmwarePackage=STM32Cube FW_L4 V1.13.0 -ProjectManager.FreePins=false -ProjectManager.HalAssertFull=false -ProjectManager.HeapSize=0x200 -ProjectManager.KeepUserCode=true -ProjectManager.LastFirmware=true -ProjectManager.LibraryCopy=0 -ProjectManager.MainLocation=Src -ProjectManager.NoMain=false -ProjectManager.PreviousToolchain= -ProjectManager.ProjectBuild=false -ProjectManager.ProjectFileName=CubeMX_Config.ioc -ProjectManager.ProjectName=CubeMX_Config -ProjectManager.StackSize=0x400 -ProjectManager.TargetToolchain=MDK-ARM V5 -ProjectManager.ToolChainLocation= -ProjectManager.UnderRoot=false -ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART2_UART_Init-USART2-false-HAL-true,4-MX_RTC_Init-RTC-false-HAL-true -RCC.ADCFreq_Value=64000000 -RCC.AHBFreq_Value=80000000 -RCC.APB1Freq_Value=80000000 -RCC.APB1TimFreq_Value=80000000 -RCC.APB2Freq_Value=80000000 -RCC.APB2TimFreq_Value=80000000 -RCC.CortexFreq_Value=80000000 -RCC.DFSDMFreq_Value=80000000 -RCC.FCLKCortexFreq_Value=80000000 -RCC.FamilyName=M -RCC.HCLKFreq_Value=80000000 -RCC.HSE_VALUE=8000000 -RCC.HSI_VALUE=16000000 -RCC.I2C1Freq_Value=80000000 -RCC.I2C2Freq_Value=80000000 -RCC.I2C3Freq_Value=80000000 -RCC.IPParameters=ADCFreq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,DFSDMFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,LCDFreq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSI_VALUE,MCO1PinFreq_Value,MSI_VALUE,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PLLSAI1PoutputFreq_Value,PLLSAI1QoutputFreq_Value,PLLSAI1RoutputFreq_Value,PLLSAI2PoutputFreq_Value,PLLSAI2RoutputFreq_Value,PLLSourceVirtual,PWRFreq_Value,RNGFreq_Value,RTCClockSelection,RTCFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMCFreq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAI1OutputFreq_Value,VCOSAI2OutputFreq_Value -RCC.LCDFreq_Value=32768 -RCC.LPTIM1Freq_Value=80000000 -RCC.LPTIM2Freq_Value=80000000 -RCC.LPUART1Freq_Value=80000000 -RCC.LSCOPinFreq_Value=32000 -RCC.LSI_VALUE=32000 -RCC.MCO1PinFreq_Value=80000000 -RCC.MSI_VALUE=4000000 -RCC.PLLN=10 -RCC.PLLPoutputFreq_Value=22857142.85714286 -RCC.PLLQoutputFreq_Value=80000000 -RCC.PLLRCLKFreq_Value=80000000 -RCC.PLLSAI1PoutputFreq_Value=18285714.285714287 -RCC.PLLSAI1QoutputFreq_Value=64000000 -RCC.PLLSAI1RoutputFreq_Value=64000000 -RCC.PLLSAI2PoutputFreq_Value=18285714.285714287 -RCC.PLLSAI2RoutputFreq_Value=64000000 -RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSI -RCC.PWRFreq_Value=80000000 -RCC.RNGFreq_Value=64000000 -RCC.RTCClockSelection=RCC_RTCCLKSOURCE_LSE -RCC.RTCFreq_Value=32768 -RCC.SAI1Freq_Value=18285714.285714287 -RCC.SAI2Freq_Value=18285714.285714287 -RCC.SDMMCFreq_Value=64000000 -RCC.SWPMI1Freq_Value=80000000 -RCC.SYSCLKFreq_VALUE=80000000 -RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK -RCC.UART4Freq_Value=80000000 -RCC.UART5Freq_Value=80000000 -RCC.USART1Freq_Value=80000000 -RCC.USART2Freq_Value=80000000 +Mcu.Pin2=PC0 +Mcu.Pin3=PC1 RCC.USART3Freq_Value=80000000 -RCC.USBFreq_Value=64000000 -RCC.VCOInputFreq_Value=16000000 -RCC.VCOOutputFreq_Value=160000000 -RCC.VCOSAI1OutputFreq_Value=128000000 -RCC.VCOSAI2OutputFreq_Value=128000000 -USART2.IPParameters=VirtualMode-Asynchronous +Mcu.Pin4=PC2 +Mcu.Pin5=PC3 +ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_1 +ProjectManager.ProjectBuild=false +RCC.HSE_VALUE=8000000 +NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false +Mcu.IP10=SYS USART2.VirtualMode-Asynchronous=VM_ASYNC -VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled -VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate -VP_SYS_VS_Systick.Mode=SysTick +NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true +RCC.RTCClockSelection=RCC_RTCCLKSOURCE_LSE +Mcu.IP12=TIM16 +Mcu.IP11=TIM15 +ProjectManager.FirmwarePackage=STM32Cube FW_L4 V1.15.1 +MxDb.Version=DB.5.0.60 +Mcu.IP14=USART2 +Mcu.IP13=TIM17 +ProjectManager.BackupPrevious=false +RCC.VCOInputFreq_Value=16000000 +SH.ADCx_IN1.ConfNb=1 +PB14.Mode=Full_Duplex_Master +File.Version=6 +SPI2.CalculateBaudRate=40.0 MBits/s +ADC3.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,OffsetNumber-0\#ChannelRegularConversion,NbrOfConversionFlag +RCC.PLLRCLKFreq_Value=80000000 +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false +VP_TIM15_VS_ClockSourceINT.Signal=TIM15_VS_ClockSourceINT +ProjectManager.HalAssertFull=false +ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_2CYCLES_5 +ProjectManager.ProjectName=CubeMX_Config +Mcu.Package=LQFP64 +PA6.Signal=SPI1_MISO +SPI2.Mode=SPI_MODE_MASTER +SPI3.Mode=SPI_MODE_MASTER +ProjectManager.ToolChainLocation= +RCC.LSI_VALUE=32000 VP_SYS_VS_Systick.Signal=SYS_VS_Systick +VP_LPTIM1_VS_LPTIM_counterModeInternalClock.Mode=Counts__internal_clock_event_00 +ADC3.Rank-0\#ChannelRegularConversion=1 +RCC.LSCOPinFreq_Value=32000 +ADC2.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_2CYCLES_5 +RCC.DFSDMFreq_Value=80000000 +PC11.Mode=Full_Duplex_Master +ADC3.OffsetNumber-0\#ChannelRegularConversion=ADC_OFFSET_NONE +SH.ADCx_IN1.0=ADC1_IN1,IN1-Single-Ended +RCC.PLLPoutputFreq_Value=22857142.85714286 +RCC.APB1TimFreq_Value=80000000 +NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +RCC.LPUART1Freq_Value=80000000 +SPI3.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate +SPI2.Direction=SPI_DIRECTION_2LINES +ADC2.Rank-0\#ChannelRegularConversion=1 +PA13\ (JTMS-SWDIO).Signal=SYS_JTMS-SWDIO +ProjectManager.CustomerFirmwarePackage= +PA3.Signal=USART2_RX +PA5.Mode=Full_Duplex_Master +VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate +RCC.MSI_VALUE=4000000 +RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSI +PA14\ (JTCK-SWCLK).Mode=Serial_Wire +RCC.PLLQoutputFreq_Value=80000000 +ProjectManager.ProjectFileName=CubeMX_Config.ioc +ADC1.Rank-0\#ChannelRegularConversion=1 +PA7.Mode=Full_Duplex_Master +Mcu.PinsNb=24 +ProjectManager.NoMain=false +SPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate +ADC1.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,OffsetNumber-0\#ChannelRegularConversion,NbrOfConversionFlag,master +ADC1.OffsetNumber-0\#ChannelRegularConversion=ADC_OFFSET_NONE +PC11.Signal=SPI3_MISO +RCC.SWPMI1Freq_Value=80000000 +PC2.Signal=ADCx_IN3 +PC10.Mode=Full_Duplex_Master +ProjectManager.DefaultFWLocation=true +PC15-OSC32_OUT\ (PC15).Signal=RCC_OSC32_OUT +VP_TIM16_VS_ClockSourceINT.Mode=Enable_Timer +ProjectManager.DeletePrevious=true +PC0.Signal=ADCx_IN1 +RCC.VCOSAI2OutputFreq_Value=128000000 +VP_TIM17_VS_ClockSourceINT.Signal=TIM17_VS_ClockSourceINT +RCC.FamilyName=M +PA3.Mode=Asynchronous +ADC3.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_2CYCLES_5 +ProjectManager.TargetToolchain=MDK-ARM V5 +ADC2.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,OffsetNumber-0\#ChannelRegularConversion,NbrOfConversionFlag +SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate +RCC.USBFreq_Value=64000000 +RCC.PLLSAI1PoutputFreq_Value=18285714.285714287 +PB10.Signal=SPI2_SCK +PB14.Signal=SPI2_MISO +RCC.PLLSAI2RoutputFreq_Value=64000000 +PA5.Signal=SPI1_SCK +ADC2.OffsetNumber-0\#ChannelRegularConversion=ADC_OFFSET_NONE +PC12.Mode=Full_Duplex_Master board=custom +RCC.VCOOutputFreq_Value=160000000 +ProjectManager.LastFirmware=true +RCC.APB2Freq_Value=80000000 +RCC.UART4Freq_Value=80000000 +SPI3.CalculateBaudRate=40.0 MBits/s +MxCube.Version=5.6.1 +RCC.I2C1Freq_Value=80000000 +SPI1.Mode=SPI_MODE_MASTER +RCC.LCDFreq_Value=32768 +RCC.RNGFreq_Value=64000000 +SH.ADCx_IN2.ConfNb=1 +RCC.PLLSAI1QoutputFreq_Value=64000000 +RCC.ADCFreq_Value=64000000 +VP_SYS_VS_Systick.Mode=SysTick +VP_TIM16_VS_ClockSourceINT.Signal=TIM16_VS_ClockSourceINT +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false +RCC.UART5Freq_Value=80000000 +ProjectManager.FreePins=false +RCC.IPParameters=ADCFreq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,DFSDMFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,LCDFreq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSI_VALUE,MCO1PinFreq_Value,MSI_VALUE,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PLLSAI1PoutputFreq_Value,PLLSAI1QoutputFreq_Value,PLLSAI1RoutputFreq_Value,PLLSAI2PoutputFreq_Value,PLLSAI2RoutputFreq_Value,PLLSourceVirtual,PWRFreq_Value,RNGFreq_Value,RTCClockSelection,RTCFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMCFreq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAI1OutputFreq_Value,VCOSAI2OutputFreq_Value +ProjectManager.AskForMigrate=true +Mcu.Name=STM32L476R(C-E-G)Tx +RCC.LPTIM2Freq_Value=80000000 +PA2.Signal=USART2_TX +ProjectManager.UnderRoot=false +Mcu.IP8=SPI2 +Mcu.IP9=SPI3 +Mcu.IP6=RTC +Mcu.IP7=SPI1 +ProjectManager.CoupleFile=false +PA13\ (JTMS-SWDIO).Mode=Serial_Wire +RCC.SYSCLKFreq_VALUE=80000000 +Mcu.Pin22=VP_TIM16_VS_ClockSourceINT +Mcu.Pin23=VP_TIM17_VS_ClockSourceINT +Mcu.Pin20=VP_SYS_VS_Systick +ADC1.master=1 +Mcu.Pin21=VP_TIM15_VS_ClockSourceINT +ADC2.NbrOfConversionFlag=1 +RCC.PLLSAI2PoutputFreq_Value=18285714.285714287 +NVIC.ForceEnableDMAVector=true +KeepUserPlacement=false +PC14-OSC32_IN\ (PC14).Signal=RCC_OSC32_IN +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false +ProjectManager.CompilerOptimize=6 +VP_TIM15_VS_ClockSourceINT.Mode=Internal +ProjectManager.HeapSize=0x200 +Mcu.Pin15=PC10 +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +Mcu.Pin16=PC11 +Mcu.Pin13=PA13 (JTMS-SWDIO) +Mcu.Pin14=PA14 (JTCK-SWCLK) +Mcu.Pin19=VP_RTC_VS_RTC_Activate +ProjectManager.ComputerToolchain=false +Mcu.Pin17=PC12 +RCC.HSI_VALUE=16000000 +Mcu.Pin18=VP_LPTIM1_VS_LPTIM_counterModeInternalClock +NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 +ADC1.NbrOfConversionFlag=1 +Mcu.Pin11=PB10 +Mcu.Pin12=PB14 +RCC.PLLN=10 +Mcu.Pin10=PA7 +PA2.Mode=Asynchronous +VP_LPTIM1_VS_LPTIM_counterModeInternalClock.Signal=LPTIM1_VS_LPTIM_counterModeInternalClock +RCC.PWRFreq_Value=80000000 +RCC.I2C2Freq_Value=80000000 +RCC.APB1Freq_Value=80000000 +ADC3.NbrOfConversionFlag=1 +ProjectManager.DeviceId=STM32L476RGTx +PC1.Signal=ADCx_IN2 +ProjectManager.LibraryCopy=2 +PA7.Signal=SPI1_MOSI diff --git a/bsp/stm32/stm32l476-st-nucleo/board/CubeMX_Config/Inc/stm32l4xx_hal_conf.h b/bsp/stm32/stm32l476-st-nucleo/board/CubeMX_Config/Inc/stm32l4xx_hal_conf.h index 9cf0bbaca2..04047367e9 100644 --- a/bsp/stm32/stm32l476-st-nucleo/board/CubeMX_Config/Inc/stm32l4xx_hal_conf.h +++ b/bsp/stm32/stm32l476-st-nucleo/board/CubeMX_Config/Inc/stm32l4xx_hal_conf.h @@ -5,7 +5,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2019 STMicroelectronics

+ *

© COPYRIGHT(c) 2020 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -49,7 +49,7 @@ */ #define HAL_MODULE_ENABLED -/*#define HAL_ADC_MODULE_ENABLED */ +#define HAL_ADC_MODULE_ENABLED /*#define HAL_CRYP_MODULE_ENABLED */ /*#define HAL_CAN_MODULE_ENABLED */ /*#define HAL_COMP_MODULE_ENABLED */ @@ -70,12 +70,14 @@ /*#define HAL_LTDC_MODULE_ENABLED */ /*#define HAL_LCD_MODULE_ENABLED */ #define HAL_LPTIM_MODULE_ENABLED +/*#define HAL_MMC_MODULE_ENABLED */ /*#define HAL_NAND_MODULE_ENABLED */ /*#define HAL_NOR_MODULE_ENABLED */ /*#define HAL_OPAMP_MODULE_ENABLED */ /*#define HAL_OSPI_MODULE_ENABLED */ /*#define HAL_OSPI_MODULE_ENABLED */ /*#define HAL_PCD_MODULE_ENABLED */ +/*#define HAL_PKA_MODULE_ENABLED */ /*#define HAL_QSPI_MODULE_ENABLED */ /*#define HAL_QSPI_MODULE_ENABLED */ /*#define HAL_RNG_MODULE_ENABLED */ @@ -84,16 +86,18 @@ /*#define HAL_SD_MODULE_ENABLED */ /*#define HAL_SMBUS_MODULE_ENABLED */ /*#define HAL_SMARTCARD_MODULE_ENABLED */ -/*#define HAL_SPI_MODULE_ENABLED */ +#define HAL_SPI_MODULE_ENABLED /*#define HAL_SRAM_MODULE_ENABLED */ /*#define HAL_SWPMI_MODULE_ENABLED */ -/*#define HAL_TIM_MODULE_ENABLED */ +#define HAL_TIM_MODULE_ENABLED /*#define HAL_TSC_MODULE_ENABLED */ #define HAL_UART_MODULE_ENABLED /*#define HAL_USART_MODULE_ENABLED */ /*#define HAL_WWDG_MODULE_ENABLED */ /*#define HAL_EXTI_MODULE_ENABLED */ +/*#define HAL_PSSI_MODULE_ENABLED */ #define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED #define HAL_I2C_MODULE_ENABLED #define HAL_DMA_MODULE_ENABLED #define HAL_RCC_MODULE_ENABLED @@ -296,6 +300,10 @@ #include "stm32l4xx_hal_sram.h" #endif /* HAL_SRAM_MODULE_ENABLED */ +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32l4xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + #ifdef HAL_NOR_MODULE_ENABLED #include "stm32l4xx_hal_nor.h" #endif /* HAL_NOR_MODULE_ENABLED */ @@ -332,6 +340,10 @@ #include "stm32l4xx_hal_ospi.h" #endif /* HAL_OSPI_MODULE_ENABLED */ +#ifdef HAL_PKA_MODULE_ENABLED + #include "stm32l4xx_hal_pka.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + #ifdef HAL_PWR_MODULE_ENABLED #include "stm32l4xx_hal_pwr.h" #endif /* HAL_PWR_MODULE_ENABLED */ @@ -408,6 +420,10 @@ #include "stm32l4xx_hal_gfxmmu.h" #endif /* HAL_GFXMMU_MODULE_ENABLED */ +#ifdef HAL_PSSI_MODULE_ENABLED + #include "stm32l4xx_hal_pssi.h" +#endif /* HAL_PSSI_MODULE_ENABLED */ + /* Exported macro ------------------------------------------------------------*/ #ifdef USE_FULL_ASSERT /** @@ -418,7 +434,7 @@ * If expr is true, it returns no value. * @retval None */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((char *)__FILE__, __LINE__)) + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) /* Exported functions ------------------------------------------------------- */ void assert_failed(char *file, uint32_t line); #else diff --git a/bsp/stm32/stm32l476-st-nucleo/board/CubeMX_Config/Src/main.c b/bsp/stm32/stm32l476-st-nucleo/board/CubeMX_Config/Src/main.c index e6b32d1921..73f4b3f008 100644 --- a/bsp/stm32/stm32l476-st-nucleo/board/CubeMX_Config/Src/main.c +++ b/bsp/stm32/stm32l476-st-nucleo/board/CubeMX_Config/Src/main.c @@ -62,8 +62,22 @@ /* USER CODE END PM */ /* Private variables ---------------------------------------------------------*/ +ADC_HandleTypeDef hadc1; +ADC_HandleTypeDef hadc2; +ADC_HandleTypeDef hadc3; + +LPTIM_HandleTypeDef hlptim1; + RTC_HandleTypeDef hrtc; +SPI_HandleTypeDef hspi1; +SPI_HandleTypeDef hspi2; +SPI_HandleTypeDef hspi3; + +TIM_HandleTypeDef htim15; +TIM_HandleTypeDef htim16; +TIM_HandleTypeDef htim17; + UART_HandleTypeDef huart2; /* USER CODE BEGIN PV */ @@ -76,6 +90,16 @@ void SystemClock_Config(void); static void MX_GPIO_Init(void); static void MX_USART2_UART_Init(void); static void MX_RTC_Init(void); +static void MX_SPI1_Init(void); +static void MX_SPI2_Init(void); +static void MX_SPI3_Init(void); +static void MX_TIM15_Init(void); +static void MX_TIM16_Init(void); +static void MX_TIM17_Init(void); +static void MX_ADC1_Init(void); +static void MX_ADC2_Init(void); +static void MX_ADC3_Init(void); +static void MX_LPTIM1_Init(void); /* USER CODE BEGIN PFP */ /* Private function prototypes -----------------------------------------------*/ @@ -116,6 +140,16 @@ int main(void) MX_GPIO_Init(); MX_USART2_UART_Init(); MX_RTC_Init(); + MX_SPI1_Init(); + MX_SPI2_Init(); + MX_SPI3_Init(); + MX_TIM15_Init(); + MX_TIM16_Init(); + MX_TIM17_Init(); + MX_ADC1_Init(); + MX_ADC2_Init(); + MX_ADC3_Init(); + MX_LPTIM1_Init(); /* USER CODE BEGIN 2 */ /* USER CODE END 2 */ @@ -143,11 +177,11 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - /**Configure LSE Drive Capability + /** Configure LSE Drive Capability */ HAL_PWR_EnableBkUpAccess(); __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); - /**Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_LSE; RCC_OscInitStruct.LSEState = RCC_LSE_ON; @@ -164,7 +198,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; @@ -177,14 +211,24 @@ void SystemClock_Config(void) { Error_Handler(); } - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_USART2; + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_USART2 + |RCC_PERIPHCLK_LPTIM1|RCC_PERIPHCLK_ADC; PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1; + PeriphClkInit.Lptim1ClockSelection = RCC_LPTIM1CLKSOURCE_PCLK; + PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_PLLSAI1; PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; + PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI; + PeriphClkInit.PLLSAI1.PLLSAI1M = 1; + PeriphClkInit.PLLSAI1.PLLSAI1N = 8; + PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7; + PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2; + PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2; + PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_ADC1CLK; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) { Error_Handler(); } - /**Configure the main internal regulator output voltage + /** Configure the main internal regulator output voltage */ if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) { @@ -192,6 +236,219 @@ void SystemClock_Config(void) } } +/** + * @brief ADC1 Initialization Function + * @param None + * @retval None + */ +static void MX_ADC1_Init(void) +{ + + /* USER CODE BEGIN ADC1_Init 0 */ + + /* USER CODE END ADC1_Init 0 */ + + ADC_MultiModeTypeDef multimode = {0}; + ADC_ChannelConfTypeDef sConfig = {0}; + + /* USER CODE BEGIN ADC1_Init 1 */ + + /* USER CODE END ADC1_Init 1 */ + /** Common config + */ + hadc1.Instance = ADC1; + hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; + hadc1.Init.Resolution = ADC_RESOLUTION_12B; + hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; + hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE; + hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; + hadc1.Init.LowPowerAutoWait = DISABLE; + hadc1.Init.ContinuousConvMode = DISABLE; + hadc1.Init.NbrOfConversion = 1; + hadc1.Init.DiscontinuousConvMode = DISABLE; + hadc1.Init.NbrOfDiscConversion = 1; + hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; + hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; + hadc1.Init.DMAContinuousRequests = DISABLE; + hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED; + hadc1.Init.OversamplingMode = DISABLE; + if (HAL_ADC_Init(&hadc1) != HAL_OK) + { + Error_Handler(); + } + /** Configure the ADC multi-mode + */ + multimode.Mode = ADC_MODE_INDEPENDENT; + if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK) + { + Error_Handler(); + } + /** Configure Regular Channel + */ + sConfig.Channel = ADC_CHANNEL_1; + sConfig.Rank = ADC_REGULAR_RANK_1; + sConfig.SamplingTime = ADC_SAMPLETIME_2CYCLES_5; + sConfig.SingleDiff = ADC_SINGLE_ENDED; + sConfig.OffsetNumber = ADC_OFFSET_NONE; + sConfig.Offset = 0; + if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN ADC1_Init 2 */ + + /* USER CODE END ADC1_Init 2 */ + +} + +/** + * @brief ADC2 Initialization Function + * @param None + * @retval None + */ +static void MX_ADC2_Init(void) +{ + + /* USER CODE BEGIN ADC2_Init 0 */ + + /* USER CODE END ADC2_Init 0 */ + + ADC_ChannelConfTypeDef sConfig = {0}; + + /* USER CODE BEGIN ADC2_Init 1 */ + + /* USER CODE END ADC2_Init 1 */ + /** Common config + */ + hadc2.Instance = ADC2; + hadc2.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; + hadc2.Init.Resolution = ADC_RESOLUTION_12B; + hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT; + hadc2.Init.ScanConvMode = ADC_SCAN_DISABLE; + hadc2.Init.EOCSelection = ADC_EOC_SINGLE_CONV; + hadc2.Init.LowPowerAutoWait = DISABLE; + hadc2.Init.ContinuousConvMode = DISABLE; + hadc2.Init.NbrOfConversion = 1; + hadc2.Init.DiscontinuousConvMode = DISABLE; + hadc2.Init.NbrOfDiscConversion = 1; + hadc2.Init.ExternalTrigConv = ADC_SOFTWARE_START; + hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; + hadc2.Init.DMAContinuousRequests = DISABLE; + hadc2.Init.Overrun = ADC_OVR_DATA_PRESERVED; + hadc2.Init.OversamplingMode = DISABLE; + if (HAL_ADC_Init(&hadc2) != HAL_OK) + { + Error_Handler(); + } + /** Configure Regular Channel + */ + sConfig.Channel = ADC_CHANNEL_2; + sConfig.Rank = ADC_REGULAR_RANK_1; + sConfig.SamplingTime = ADC_SAMPLETIME_2CYCLES_5; + sConfig.SingleDiff = ADC_SINGLE_ENDED; + sConfig.OffsetNumber = ADC_OFFSET_NONE; + sConfig.Offset = 0; + if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN ADC2_Init 2 */ + + /* USER CODE END ADC2_Init 2 */ + +} + +/** + * @brief ADC3 Initialization Function + * @param None + * @retval None + */ +static void MX_ADC3_Init(void) +{ + + /* USER CODE BEGIN ADC3_Init 0 */ + + /* USER CODE END ADC3_Init 0 */ + + ADC_ChannelConfTypeDef sConfig = {0}; + + /* USER CODE BEGIN ADC3_Init 1 */ + + /* USER CODE END ADC3_Init 1 */ + /** Common config + */ + hadc3.Instance = ADC3; + hadc3.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; + hadc3.Init.Resolution = ADC_RESOLUTION_12B; + hadc3.Init.DataAlign = ADC_DATAALIGN_RIGHT; + hadc3.Init.ScanConvMode = ADC_SCAN_DISABLE; + hadc3.Init.EOCSelection = ADC_EOC_SINGLE_CONV; + hadc3.Init.LowPowerAutoWait = DISABLE; + hadc3.Init.ContinuousConvMode = DISABLE; + hadc3.Init.NbrOfConversion = 1; + hadc3.Init.DiscontinuousConvMode = DISABLE; + hadc3.Init.NbrOfDiscConversion = 1; + hadc3.Init.ExternalTrigConv = ADC_SOFTWARE_START; + hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; + hadc3.Init.DMAContinuousRequests = DISABLE; + hadc3.Init.Overrun = ADC_OVR_DATA_PRESERVED; + hadc3.Init.OversamplingMode = DISABLE; + if (HAL_ADC_Init(&hadc3) != HAL_OK) + { + Error_Handler(); + } + /** Configure Regular Channel + */ + sConfig.Channel = ADC_CHANNEL_3; + sConfig.Rank = ADC_REGULAR_RANK_1; + sConfig.SamplingTime = ADC_SAMPLETIME_2CYCLES_5; + sConfig.SingleDiff = ADC_SINGLE_ENDED; + sConfig.OffsetNumber = ADC_OFFSET_NONE; + sConfig.Offset = 0; + if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN ADC3_Init 2 */ + + /* USER CODE END ADC3_Init 2 */ + +} + +/** + * @brief LPTIM1 Initialization Function + * @param None + * @retval None + */ +static void MX_LPTIM1_Init(void) +{ + + /* USER CODE BEGIN LPTIM1_Init 0 */ + + /* USER CODE END LPTIM1_Init 0 */ + + /* USER CODE BEGIN LPTIM1_Init 1 */ + + /* USER CODE END LPTIM1_Init 1 */ + hlptim1.Instance = LPTIM1; + hlptim1.Init.Clock.Source = LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC; + hlptim1.Init.Clock.Prescaler = LPTIM_PRESCALER_DIV1; + hlptim1.Init.Trigger.Source = LPTIM_TRIGSOURCE_SOFTWARE; + hlptim1.Init.OutputPolarity = LPTIM_OUTPUTPOLARITY_HIGH; + hlptim1.Init.UpdateMode = LPTIM_UPDATE_IMMEDIATE; + hlptim1.Init.CounterSource = LPTIM_COUNTERSOURCE_INTERNAL; + hlptim1.Init.Input1Source = LPTIM_INPUT1SOURCE_GPIO; + hlptim1.Init.Input2Source = LPTIM_INPUT2SOURCE_GPIO; + if (HAL_LPTIM_Init(&hlptim1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN LPTIM1_Init 2 */ + + /* USER CODE END LPTIM1_Init 2 */ + +} + /** * @brief RTC Initialization Function * @param None @@ -207,7 +464,7 @@ static void MX_RTC_Init(void) /* USER CODE BEGIN RTC_Init 1 */ /* USER CODE END RTC_Init 1 */ - /**Initialize RTC Only + /** Initialize RTC Only */ hrtc.Instance = RTC; hrtc.Init.HourFormat = RTC_HOURFORMAT_24; @@ -227,6 +484,236 @@ static void MX_RTC_Init(void) } +/** + * @brief SPI1 Initialization Function + * @param None + * @retval None + */ +static void MX_SPI1_Init(void) +{ + + /* USER CODE BEGIN SPI1_Init 0 */ + + /* USER CODE END SPI1_Init 0 */ + + /* USER CODE BEGIN SPI1_Init 1 */ + + /* USER CODE END SPI1_Init 1 */ + /* SPI1 parameter configuration*/ + hspi1.Instance = SPI1; + hspi1.Init.Mode = SPI_MODE_MASTER; + hspi1.Init.Direction = SPI_DIRECTION_2LINES; + hspi1.Init.DataSize = SPI_DATASIZE_4BIT; + hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; + hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; + hspi1.Init.NSS = SPI_NSS_SOFT; + hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; + hspi1.Init.TIMode = SPI_TIMODE_DISABLE; + hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + hspi1.Init.CRCPolynomial = 7; + hspi1.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE; + hspi1.Init.NSSPMode = SPI_NSS_PULSE_ENABLE; + if (HAL_SPI_Init(&hspi1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SPI1_Init 2 */ + + /* USER CODE END SPI1_Init 2 */ + +} + +/** + * @brief SPI2 Initialization Function + * @param None + * @retval None + */ +static void MX_SPI2_Init(void) +{ + + /* USER CODE BEGIN SPI2_Init 0 */ + + /* USER CODE END SPI2_Init 0 */ + + /* USER CODE BEGIN SPI2_Init 1 */ + + /* USER CODE END SPI2_Init 1 */ + /* SPI2 parameter configuration*/ + hspi2.Instance = SPI2; + hspi2.Init.Mode = SPI_MODE_MASTER; + hspi2.Init.Direction = SPI_DIRECTION_2LINES; + hspi2.Init.DataSize = SPI_DATASIZE_4BIT; + hspi2.Init.CLKPolarity = SPI_POLARITY_LOW; + hspi2.Init.CLKPhase = SPI_PHASE_1EDGE; + hspi2.Init.NSS = SPI_NSS_SOFT; + hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB; + hspi2.Init.TIMode = SPI_TIMODE_DISABLE; + hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + hspi2.Init.CRCPolynomial = 7; + hspi2.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE; + hspi2.Init.NSSPMode = SPI_NSS_PULSE_ENABLE; + if (HAL_SPI_Init(&hspi2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SPI2_Init 2 */ + + /* USER CODE END SPI2_Init 2 */ + +} + +/** + * @brief SPI3 Initialization Function + * @param None + * @retval None + */ +static void MX_SPI3_Init(void) +{ + + /* USER CODE BEGIN SPI3_Init 0 */ + + /* USER CODE END SPI3_Init 0 */ + + /* USER CODE BEGIN SPI3_Init 1 */ + + /* USER CODE END SPI3_Init 1 */ + /* SPI3 parameter configuration*/ + hspi3.Instance = SPI3; + hspi3.Init.Mode = SPI_MODE_MASTER; + hspi3.Init.Direction = SPI_DIRECTION_2LINES; + hspi3.Init.DataSize = SPI_DATASIZE_4BIT; + hspi3.Init.CLKPolarity = SPI_POLARITY_LOW; + hspi3.Init.CLKPhase = SPI_PHASE_1EDGE; + hspi3.Init.NSS = SPI_NSS_SOFT; + hspi3.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + hspi3.Init.FirstBit = SPI_FIRSTBIT_MSB; + hspi3.Init.TIMode = SPI_TIMODE_DISABLE; + hspi3.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + hspi3.Init.CRCPolynomial = 7; + hspi3.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE; + hspi3.Init.NSSPMode = SPI_NSS_PULSE_ENABLE; + if (HAL_SPI_Init(&hspi3) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SPI3_Init 2 */ + + /* USER CODE END SPI3_Init 2 */ + +} + +/** + * @brief TIM15 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM15_Init(void) +{ + + /* USER CODE BEGIN TIM15_Init 0 */ + + /* USER CODE END TIM15_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + TIM_MasterConfigTypeDef sMasterConfig = {0}; + + /* USER CODE BEGIN TIM15_Init 1 */ + + /* USER CODE END TIM15_Init 1 */ + htim15.Instance = TIM15; + htim15.Init.Prescaler = 0; + htim15.Init.CounterMode = TIM_COUNTERMODE_UP; + htim15.Init.Period = 0; + htim15.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim15.Init.RepetitionCounter = 0; + htim15.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim15) != HAL_OK) + { + Error_Handler(); + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + if (HAL_TIM_ConfigClockSource(&htim15, &sClockSourceConfig) != HAL_OK) + { + Error_Handler(); + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim15, &sMasterConfig) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM15_Init 2 */ + + /* USER CODE END TIM15_Init 2 */ + +} + +/** + * @brief TIM16 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM16_Init(void) +{ + + /* USER CODE BEGIN TIM16_Init 0 */ + + /* USER CODE END TIM16_Init 0 */ + + /* USER CODE BEGIN TIM16_Init 1 */ + + /* USER CODE END TIM16_Init 1 */ + htim16.Instance = TIM16; + htim16.Init.Prescaler = 0; + htim16.Init.CounterMode = TIM_COUNTERMODE_UP; + htim16.Init.Period = 0; + htim16.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim16.Init.RepetitionCounter = 0; + htim16.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim16) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM16_Init 2 */ + + /* USER CODE END TIM16_Init 2 */ + +} + +/** + * @brief TIM17 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM17_Init(void) +{ + + /* USER CODE BEGIN TIM17_Init 0 */ + + /* USER CODE END TIM17_Init 0 */ + + /* USER CODE BEGIN TIM17_Init 1 */ + + /* USER CODE END TIM17_Init 1 */ + htim17.Instance = TIM17; + htim17.Init.Prescaler = 0; + htim17.Init.CounterMode = TIM_COUNTERMODE_UP; + htim17.Init.Period = 0; + htim17.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim17.Init.RepetitionCounter = 0; + htim17.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim17) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM17_Init 2 */ + + /* USER CODE END TIM17_Init 2 */ + +} + /** * @brief USART2 Initialization Function * @param None @@ -273,6 +760,7 @@ static void MX_GPIO_Init(void) /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); } @@ -302,7 +790,7 @@ void Error_Handler(void) * @param line: assert_param error line source number * @retval None */ -void assert_failed(char *file, uint32_t line) +void assert_failed(uint8_t *file, uint32_t line) { /* USER CODE BEGIN 6 */ /* User can add his own implementation to report the file name and line number, diff --git a/bsp/stm32/stm32l476-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c b/bsp/stm32/stm32l476-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c index b693d8d190..dda464c29e 100644 --- a/bsp/stm32/stm32l476-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c +++ b/bsp/stm32/stm32l476-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c @@ -97,6 +97,207 @@ void HAL_MspInit(void) /* USER CODE END MspInit 1 */ } +static uint32_t HAL_RCC_ADC_CLK_ENABLED=0; + +/** +* @brief ADC MSP Initialization +* This function configures the hardware resources used in this example +* @param hadc: ADC handle pointer +* @retval None +*/ +void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hadc->Instance==ADC1) + { + /* USER CODE BEGIN ADC1_MspInit 0 */ + + /* USER CODE END ADC1_MspInit 0 */ + /* Peripheral clock enable */ + HAL_RCC_ADC_CLK_ENABLED++; + if(HAL_RCC_ADC_CLK_ENABLED==1){ + __HAL_RCC_ADC_CLK_ENABLE(); + } + + __HAL_RCC_GPIOC_CLK_ENABLE(); + /**ADC1 GPIO Configuration + PC0 ------> ADC1_IN1 + */ + GPIO_InitStruct.Pin = GPIO_PIN_0; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG_ADC_CONTROL; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /* USER CODE BEGIN ADC1_MspInit 1 */ + + /* USER CODE END ADC1_MspInit 1 */ + } + else if(hadc->Instance==ADC2) + { + /* USER CODE BEGIN ADC2_MspInit 0 */ + + /* USER CODE END ADC2_MspInit 0 */ + /* Peripheral clock enable */ + HAL_RCC_ADC_CLK_ENABLED++; + if(HAL_RCC_ADC_CLK_ENABLED==1){ + __HAL_RCC_ADC_CLK_ENABLE(); + } + + __HAL_RCC_GPIOC_CLK_ENABLE(); + /**ADC2 GPIO Configuration + PC1 ------> ADC2_IN2 + */ + GPIO_InitStruct.Pin = GPIO_PIN_1; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG_ADC_CONTROL; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /* USER CODE BEGIN ADC2_MspInit 1 */ + + /* USER CODE END ADC2_MspInit 1 */ + } + else if(hadc->Instance==ADC3) + { + /* USER CODE BEGIN ADC3_MspInit 0 */ + + /* USER CODE END ADC3_MspInit 0 */ + /* Peripheral clock enable */ + HAL_RCC_ADC_CLK_ENABLED++; + if(HAL_RCC_ADC_CLK_ENABLED==1){ + __HAL_RCC_ADC_CLK_ENABLE(); + } + + __HAL_RCC_GPIOC_CLK_ENABLE(); + /**ADC3 GPIO Configuration + PC2 ------> ADC3_IN3 + */ + GPIO_InitStruct.Pin = GPIO_PIN_2; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG_ADC_CONTROL; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /* USER CODE BEGIN ADC3_MspInit 1 */ + + /* USER CODE END ADC3_MspInit 1 */ + } + +} + +/** +* @brief ADC MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hadc: ADC handle pointer +* @retval None +*/ +void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) +{ + if(hadc->Instance==ADC1) + { + /* USER CODE BEGIN ADC1_MspDeInit 0 */ + + /* USER CODE END ADC1_MspDeInit 0 */ + /* Peripheral clock disable */ + HAL_RCC_ADC_CLK_ENABLED--; + if(HAL_RCC_ADC_CLK_ENABLED==0){ + __HAL_RCC_ADC_CLK_DISABLE(); + } + + /**ADC1 GPIO Configuration + PC0 ------> ADC1_IN1 + */ + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_0); + + /* USER CODE BEGIN ADC1_MspDeInit 1 */ + + /* USER CODE END ADC1_MspDeInit 1 */ + } + else if(hadc->Instance==ADC2) + { + /* USER CODE BEGIN ADC2_MspDeInit 0 */ + + /* USER CODE END ADC2_MspDeInit 0 */ + /* Peripheral clock disable */ + HAL_RCC_ADC_CLK_ENABLED--; + if(HAL_RCC_ADC_CLK_ENABLED==0){ + __HAL_RCC_ADC_CLK_DISABLE(); + } + + /**ADC2 GPIO Configuration + PC1 ------> ADC2_IN2 + */ + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1); + + /* USER CODE BEGIN ADC2_MspDeInit 1 */ + + /* USER CODE END ADC2_MspDeInit 1 */ + } + else if(hadc->Instance==ADC3) + { + /* USER CODE BEGIN ADC3_MspDeInit 0 */ + + /* USER CODE END ADC3_MspDeInit 0 */ + /* Peripheral clock disable */ + HAL_RCC_ADC_CLK_ENABLED--; + if(HAL_RCC_ADC_CLK_ENABLED==0){ + __HAL_RCC_ADC_CLK_DISABLE(); + } + + /**ADC3 GPIO Configuration + PC2 ------> ADC3_IN3 + */ + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_2); + + /* USER CODE BEGIN ADC3_MspDeInit 1 */ + + /* USER CODE END ADC3_MspDeInit 1 */ + } + +} + +/** +* @brief LPTIM MSP Initialization +* This function configures the hardware resources used in this example +* @param hlptim: LPTIM handle pointer +* @retval None +*/ +void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef* hlptim) +{ + if(hlptim->Instance==LPTIM1) + { + /* USER CODE BEGIN LPTIM1_MspInit 0 */ + + /* USER CODE END LPTIM1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_LPTIM1_CLK_ENABLE(); + /* USER CODE BEGIN LPTIM1_MspInit 1 */ + + /* USER CODE END LPTIM1_MspInit 1 */ + } + +} + +/** +* @brief LPTIM MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hlptim: LPTIM handle pointer +* @retval None +*/ +void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef* hlptim) +{ + if(hlptim->Instance==LPTIM1) + { + /* USER CODE BEGIN LPTIM1_MspDeInit 0 */ + + /* USER CODE END LPTIM1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_LPTIM1_CLK_DISABLE(); + /* USER CODE BEGIN LPTIM1_MspDeInit 1 */ + + /* USER CODE END LPTIM1_MspDeInit 1 */ + } + +} + /** * @brief RTC MSP Initialization * This function configures the hardware resources used in this example @@ -105,7 +306,6 @@ void HAL_MspInit(void) */ void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) { - if(hrtc->Instance==RTC) { /* USER CODE BEGIN RTC_MspInit 0 */ @@ -126,10 +326,8 @@ void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) * @param hrtc: RTC handle pointer * @retval None */ - void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) { - if(hrtc->Instance==RTC) { /* USER CODE BEGIN RTC_MspDeInit 0 */ @@ -144,6 +342,259 @@ void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) } +/** +* @brief SPI MSP Initialization +* This function configures the hardware resources used in this example +* @param hspi: SPI handle pointer +* @retval None +*/ +void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hspi->Instance==SPI1) + { + /* USER CODE BEGIN SPI1_MspInit 0 */ + + /* USER CODE END SPI1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI1_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**SPI1 GPIO Configuration + PA5 ------> SPI1_SCK + PA6 ------> SPI1_MISO + PA7 ------> SPI1_MOSI + */ + GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN SPI1_MspInit 1 */ + + /* USER CODE END SPI1_MspInit 1 */ + } + else if(hspi->Instance==SPI2) + { + /* USER CODE BEGIN SPI2_MspInit 0 */ + + /* USER CODE END SPI2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI2_CLK_ENABLE(); + + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**SPI2 GPIO Configuration + PC3 ------> SPI2_MOSI + PB10 ------> SPI2_SCK + PB14 ------> SPI2_MISO + */ + GPIO_InitStruct.Pin = GPIO_PIN_3; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_14; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USER CODE BEGIN SPI2_MspInit 1 */ + + /* USER CODE END SPI2_MspInit 1 */ + } + else if(hspi->Instance==SPI3) + { + /* USER CODE BEGIN SPI3_MspInit 0 */ + + /* USER CODE END SPI3_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI3_CLK_ENABLE(); + + __HAL_RCC_GPIOC_CLK_ENABLE(); + /**SPI3 GPIO Configuration + PC10 ------> SPI3_SCK + PC11 ------> SPI3_MISO + PC12 ------> SPI3_MOSI + */ + GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF6_SPI3; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /* USER CODE BEGIN SPI3_MspInit 1 */ + + /* USER CODE END SPI3_MspInit 1 */ + } + +} + +/** +* @brief SPI MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hspi: SPI handle pointer +* @retval None +*/ +void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) +{ + if(hspi->Instance==SPI1) + { + /* USER CODE BEGIN SPI1_MspDeInit 0 */ + + /* USER CODE END SPI1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SPI1_CLK_DISABLE(); + + /**SPI1 GPIO Configuration + PA5 ------> SPI1_SCK + PA6 ------> SPI1_MISO + PA7 ------> SPI1_MOSI + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7); + + /* USER CODE BEGIN SPI1_MspDeInit 1 */ + + /* USER CODE END SPI1_MspDeInit 1 */ + } + else if(hspi->Instance==SPI2) + { + /* USER CODE BEGIN SPI2_MspDeInit 0 */ + + /* USER CODE END SPI2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SPI2_CLK_DISABLE(); + + /**SPI2 GPIO Configuration + PC3 ------> SPI2_MOSI + PB10 ------> SPI2_SCK + PB14 ------> SPI2_MISO + */ + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_3); + + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_10|GPIO_PIN_14); + + /* USER CODE BEGIN SPI2_MspDeInit 1 */ + + /* USER CODE END SPI2_MspDeInit 1 */ + } + else if(hspi->Instance==SPI3) + { + /* USER CODE BEGIN SPI3_MspDeInit 0 */ + + /* USER CODE END SPI3_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SPI3_CLK_DISABLE(); + + /**SPI3 GPIO Configuration + PC10 ------> SPI3_SCK + PC11 ------> SPI3_MISO + PC12 ------> SPI3_MOSI + */ + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12); + + /* USER CODE BEGIN SPI3_MspDeInit 1 */ + + /* USER CODE END SPI3_MspDeInit 1 */ + } + +} + +/** +* @brief TIM_Base MSP Initialization +* This function configures the hardware resources used in this example +* @param htim_base: TIM_Base handle pointer +* @retval None +*/ +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) +{ + if(htim_base->Instance==TIM15) + { + /* USER CODE BEGIN TIM15_MspInit 0 */ + + /* USER CODE END TIM15_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM15_CLK_ENABLE(); + /* USER CODE BEGIN TIM15_MspInit 1 */ + + /* USER CODE END TIM15_MspInit 1 */ + } + else if(htim_base->Instance==TIM16) + { + /* USER CODE BEGIN TIM16_MspInit 0 */ + + /* USER CODE END TIM16_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM16_CLK_ENABLE(); + /* USER CODE BEGIN TIM16_MspInit 1 */ + + /* USER CODE END TIM16_MspInit 1 */ + } + else if(htim_base->Instance==TIM17) + { + /* USER CODE BEGIN TIM17_MspInit 0 */ + + /* USER CODE END TIM17_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM17_CLK_ENABLE(); + /* USER CODE BEGIN TIM17_MspInit 1 */ + + /* USER CODE END TIM17_MspInit 1 */ + } + +} + +/** +* @brief TIM_Base MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param htim_base: TIM_Base handle pointer +* @retval None +*/ +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base) +{ + if(htim_base->Instance==TIM15) + { + /* USER CODE BEGIN TIM15_MspDeInit 0 */ + + /* USER CODE END TIM15_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM15_CLK_DISABLE(); + /* USER CODE BEGIN TIM15_MspDeInit 1 */ + + /* USER CODE END TIM15_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM16) + { + /* USER CODE BEGIN TIM16_MspDeInit 0 */ + + /* USER CODE END TIM16_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM16_CLK_DISABLE(); + /* USER CODE BEGIN TIM16_MspDeInit 1 */ + + /* USER CODE END TIM16_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM17) + { + /* USER CODE BEGIN TIM17_MspDeInit 0 */ + + /* USER CODE END TIM17_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM17_CLK_DISABLE(); + /* USER CODE BEGIN TIM17_MspDeInit 1 */ + + /* USER CODE END TIM17_MspDeInit 1 */ + } + +} + /** * @brief UART MSP Initialization * This function configures the hardware resources used in this example @@ -152,7 +603,6 @@ void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { - GPIO_InitTypeDef GPIO_InitStruct = {0}; if(huart->Instance==USART2) { @@ -187,10 +637,8 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) * @param huart: UART handle pointer * @retval None */ - void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) { - if(huart->Instance==USART2) { /* USER CODE BEGIN USART2_MspDeInit 0 */ diff --git a/bsp/stm32/stm32l476-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_it.c b/bsp/stm32/stm32l476-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_it.c index ab5c0b7d8e..e13a77a0e6 100644 --- a/bsp/stm32/stm32l476-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_it.c +++ b/bsp/stm32/stm32l476-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_it.c @@ -71,6 +71,7 @@ /* USER CODE END 0 */ /* External variables --------------------------------------------------------*/ + /* USER CODE BEGIN EV */ /* USER CODE END EV */ diff --git a/bsp/stm32/stm32l476-st-nucleo/board/Kconfig b/bsp/stm32/stm32l476-st-nucleo/board/Kconfig index 5089c9f623..687ad3a85e 100644 --- a/bsp/stm32/stm32l476-st-nucleo/board/Kconfig +++ b/bsp/stm32/stm32l476-st-nucleo/board/Kconfig @@ -89,6 +89,93 @@ menu "On-chip Peripheral Drivers" endif endif + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" + default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable SPI1 BUS" + default n + + config BSP_SPI1_TX_USING_DMA + bool "Enable SPI1 TX DMA" + depends on BSP_USING_SPI1 + default n + + config BSP_SPI1_RX_USING_DMA + bool "Enable SPI1 RX DMA" + depends on BSP_USING_SPI1 + select BSP_SPI1_TX_USING_DMA + default n + + config BSP_USING_SPI2 + bool "Enable SPI2 BUS" + default n + + config BSP_SPI2_TX_USING_DMA + bool "Enable SPI2 TX DMA" + depends on BSP_USING_SPI2 + default n + + config BSP_SPI2_RX_USING_DMA + bool "Enable SPI2 RX DMA" + depends on BSP_USING_SPI2 + select BSP_SPI2_TX_USING_DMA + default n + + config BSP_USING_SPI3 + bool "Enable SPI3 BUS" + default n + + config BSP_SPI3_TX_USING_DMA + bool "Enable SPI3 TX DMA" + depends on BSP_USING_SPI3 + default n + + config BSP_SPI3_RX_USING_DMA + bool "Enable SPI3 RX DMA" + depends on BSP_USING_SPI3 + select BSP_SPI3_TX_USING_DMA + default n + endif + + menuconfig BSP_USING_TIM + bool "Enable timer" + default n + select RT_USING_HWTIMER + if BSP_USING_TIM + config BSP_USING_TIM15 + bool "Enable TIM15" + default n + + config BSP_USING_TIM16 + bool "Enable TIM16" + default n + + config BSP_USING_TIM17 + bool "Enable TIM17" + default n + endif + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC + if BSP_USING_ADC + config BSP_USING_ADC1 + bool "Enable ADC1" + default n + + config BSP_USING_ADC2 + bool "Enable ADC2" + default n + + config BSP_USING_ADC3 + bool "Enable ADC3" + default n + endif + menuconfig BSP_USING_ONCHIP_RTC bool "Enable RTC" select RT_USING_RTC diff --git a/bsp/stm32/stm32l476-st-nucleo/rtconfig.py b/bsp/stm32/stm32l476-st-nucleo/rtconfig.py index 7fc0f14860..826d5425f5 100644 --- a/bsp/stm32/stm32l476-st-nucleo/rtconfig.py +++ b/bsp/stm32/stm32l476-st-nucleo/rtconfig.py @@ -141,3 +141,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/stm32l496-ali-developer/rtconfig.py b/bsp/stm32/stm32l496-ali-developer/rtconfig.py index 2e022a964b..deb2083359 100644 --- a/bsp/stm32/stm32l496-ali-developer/rtconfig.py +++ b/bsp/stm32/stm32l496-ali-developer/rtconfig.py @@ -141,3 +141,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/stm32l496-st-nucleo/rtconfig.py b/bsp/stm32/stm32l496-st-nucleo/rtconfig.py index 40b84ad846..dddfc31180 100644 --- a/bsp/stm32/stm32l496-st-nucleo/rtconfig.py +++ b/bsp/stm32/stm32l496-st-nucleo/rtconfig.py @@ -142,3 +142,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/stm32l4r5-st-nucleo/rtconfig.py b/bsp/stm32/stm32l4r5-st-nucleo/rtconfig.py index 33e1a6bc4a..e9a00ad628 100644 --- a/bsp/stm32/stm32l4r5-st-nucleo/rtconfig.py +++ b/bsp/stm32/stm32l4r5-st-nucleo/rtconfig.py @@ -141,3 +141,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/stm32l4r9-st-eval/rtconfig.py b/bsp/stm32/stm32l4r9-st-eval/rtconfig.py index 75b5d9925e..f1d97ac603 100644 --- a/bsp/stm32/stm32l4r9-st-eval/rtconfig.py +++ b/bsp/stm32/stm32l4r9-st-eval/rtconfig.py @@ -141,3 +141,10 @@ elif PLATFORM == 'iar': EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) diff --git a/bsp/stm32/tools/sdk_dist.py b/bsp/stm32/tools/sdk_dist.py new file mode 100644 index 0000000000..cd04eb6900 --- /dev/null +++ b/bsp/stm32/tools/sdk_dist.py @@ -0,0 +1,20 @@ +import os +import sys +import shutil +cwd_path = os.getcwd() +sys.path.append(os.path.join(os.path.dirname(cwd_path), 'rt-thread', 'tools')) + +# BSP dist function +def dist_do_building(BSP_ROOT): + from mkdist import bsp_copy_files + import rtconfig + + dist_dir = os.path.join(BSP_ROOT, 'dist', os.path.basename(BSP_ROOT)) + library_dir = os.path.join(dist_dir, 'libraries') + + print("=> copy stm32 bsp library") + library_path = os.path.join(os.path.dirname(BSP_ROOT), 'libraries') + bsp_copy_files(os.path.join(library_path, rtconfig.BSP_LIBRARY_TYPE), os.path.join(library_dir, rtconfig.BSP_LIBRARY_TYPE)) + print("=> copy bsp drivers") + bsp_copy_files(os.path.join(library_path, 'HAL_Drivers'), os.path.join(library_dir, 'HAL_Drivers')) + shutil.copyfile(os.path.join(library_path, 'Kconfig'), os.path.join(library_dir, 'Kconfig')) \ No newline at end of file diff --git a/components/cplusplus/crt_init.c b/components/cplusplus/crt_init.c old mode 100755 new mode 100644 diff --git a/components/cplusplus/Mutex.cpp b/components/cplusplus/cxx_Mutex.cpp similarity index 100% rename from components/cplusplus/Mutex.cpp rename to components/cplusplus/cxx_Mutex.cpp diff --git a/components/cplusplus/Semaphore.cpp b/components/cplusplus/cxx_Semaphore.cpp similarity index 100% rename from components/cplusplus/Semaphore.cpp rename to components/cplusplus/cxx_Semaphore.cpp diff --git a/components/cplusplus/Thread.cpp b/components/cplusplus/cxx_Thread.cpp similarity index 100% rename from components/cplusplus/Thread.cpp rename to components/cplusplus/cxx_Thread.cpp diff --git a/components/cplusplus/crt.cpp b/components/cplusplus/cxx_crt.cpp similarity index 100% rename from components/cplusplus/crt.cpp rename to components/cplusplus/cxx_crt.cpp diff --git a/components/drivers/can/can.c b/components/drivers/can/can.c index 3d60dbaa55..9f4612355b 100644 --- a/components/drivers/can/can.c +++ b/components/drivers/can/can.c @@ -422,6 +422,7 @@ static rt_err_t rt_can_close(struct rt_device *dev) tx_fifo = (struct rt_can_tx_fifo *)can->can_tx; RT_ASSERT(tx_fifo != RT_NULL); + rt_sem_detach(&(tx_fifo->sem)); rt_free(tx_fifo); dev->open_flag &= ~RT_DEVICE_FLAG_INT_TX; can->can_tx = RT_NULL; diff --git a/components/drivers/sensors/sensor.h b/components/drivers/sensors/sensor.h index a0eaaae9ea..3821ec36ca 100755 --- a/components/drivers/sensors/sensor.h +++ b/components/drivers/sensors/sensor.h @@ -61,6 +61,8 @@ extern "C" { #define RT_SENSOR_VENDOR_ASAIR (8) /* Aosong */ #define RT_SENSOR_VENDOR_SHARP (9) /* Sharp */ #define RT_SENSOR_VENDOR_SENSIRION (10) /* Sensirion */ +#define RT_SENSOR_VENDOR_TI (11) /* Texas Instruments*/ + /* Sensor unit types */ diff --git a/components/drivers/usb/usbdevice/class/mstorage.c b/components/drivers/usb/usbdevice/class/mstorage.c index 43fb25afe4..a681b8212f 100644 --- a/components/drivers/usb/usbdevice/class/mstorage.c +++ b/components/drivers/usb/usbdevice/class/mstorage.c @@ -426,7 +426,7 @@ static rt_size_t _read_capacity(ufunction_t func, ustorage_cbw_t cbw) data = (struct mstorage*)func->user_data; buf = data->ep_in->buffer; - sector_count = data->geometry.sector_count; + sector_count = data->geometry.sector_count - 1; /* Last Logical Block Address */ sector_size = data->geometry.bytes_per_sector; buf[0] = sector_count >> 24; diff --git a/components/net/at/at_socket/at_socket.c b/components/net/at/at_socket/at_socket.c index 11be4e23c0..220bf9d620 100644 --- a/components/net/at/at_socket/at_socket.c +++ b/components/net/at/at_socket/at_socket.c @@ -744,7 +744,7 @@ int at_recvfrom(int socket, void *mem, size_t len, int flags, struct sockaddr *f goto __exit; } - /* if the socket type is UDP, nead to connect socket first */ + /* if the socket type is UDP, need to connect socket first */ if (from && sock->type == AT_SOCKET_UDP && sock->state == AT_SOCKET_OPEN) { ip_addr_t remote_addr; diff --git a/components/net/netdev/src/netdev.c b/components/net/netdev/src/netdev.c index 68e5364a9e..aa43d8d3db 100644 --- a/components/net/netdev/src/netdev.c +++ b/components/net/netdev/src/netdev.c @@ -1087,7 +1087,7 @@ int netdev_cmd_ping(char* target_name, rt_uint32_t times, rt_size_t size) } } - /* if the response time is more than NETDEV_PING_DELAY, no nead to delay */ + /* if the response time is more than NETDEV_PING_DELAY, no need to delay */ delay_tick = ((rt_tick_get() - start_tick) > NETDEV_PING_DELAY) || (index == times) ? 0 : NETDEV_PING_DELAY; rt_thread_delay(delay_tick); } diff --git a/components/net/sal_socket/src/sal_socket.c b/components/net/sal_socket/src/sal_socket.c index bd51c829c6..e3bea5a28e 100644 --- a/components/net/sal_socket/src/sal_socket.c +++ b/components/net/sal_socket/src/sal_socket.c @@ -679,7 +679,7 @@ int sal_shutdown(int socket, int how) /* get the socket object by socket descriptor */ SAL_SOCKET_OBJ_GET(sock, socket); - /* shutdown operation not nead to check network interface status */ + /* shutdown operation not need to check network interface status */ /* check the network interface socket opreation */ SAL_NETDEV_SOCKETOPS_VALID(sock->netdev, pf, shutdown); @@ -970,7 +970,7 @@ int sal_closesocket(int socket) /* get the socket object by socket descriptor */ SAL_SOCKET_OBJ_GET(sock, socket); - /* clsoesocket operation not nead to vaild network interface status */ + /* clsoesocket operation not need to vaild network interface status */ /* valid the network interface socket opreation */ SAL_NETDEV_SOCKETOPS_VALID(sock->netdev, pf, socket); diff --git a/tools/eclipse.py b/tools/eclipse.py index 699ecef4d1..48b38c8f0a 100644 --- a/tools/eclipse.py +++ b/tools/eclipse.py @@ -109,12 +109,12 @@ def ExcludeFiles(infiles, files): def ExcludePaths(rootpath, paths): ret = [] - files = os.listdir(rootpath) + files = os.listdir(OSPath(rootpath)) for file in files: if file.startswith('.'): continue - fullname = os.path.join(rootpath, file) + fullname = os.path.join(OSPath(rootpath), file) if os.path.isdir(fullname): # print(fullname) diff --git a/tools/mkdist.py b/tools/mkdist.py index d83020f755..a6c744b470 100644 --- a/tools/mkdist.py +++ b/tools/mkdist.py @@ -336,22 +336,6 @@ def MkDist(program, BSP_ROOT, RTT_ROOT, Env, rttide = None): print('=> %s' % os.path.basename(BSP_ROOT)) bsp_copy_files(BSP_ROOT, dist_dir) - # copy stm32 bsp libiary files - if os.path.basename(os.path.dirname(BSP_ROOT)) == 'stm32': - print("=> copy stm32 bsp library") - library_path = os.path.join(os.path.dirname(BSP_ROOT), 'libraries') - library_dir = os.path.join(dist_dir, 'libraries') - bsp_copy_files(os.path.join(library_path, 'HAL_Drivers'), os.path.join(library_dir, 'HAL_Drivers')) - bsp_copy_files(os.path.join(library_path, Env['bsp_lib_type']), os.path.join(library_dir, Env['bsp_lib_type'])) - shutil.copyfile(os.path.join(library_path, 'Kconfig'), os.path.join(library_dir, 'Kconfig')) - - # copy nuclei bsp libiary files - if os.path.basename(os.path.dirname(BSP_ROOT)) == 'nuclei': - print("=> copy nuclei bsp library") - library_path = os.path.join(os.path.dirname(BSP_ROOT), 'libraries') - library_dir = os.path.join(dist_dir, 'libraries') - bsp_copy_files(os.path.join(library_path, Env['bsp_lib_type']), os.path.join(library_dir, Env['bsp_lib_type'])) - # do bsp special dist handle if 'dist_handle' in Env: print("=> start dist handle")