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本次PR涉及①BSP驱动新增②F103库更新③GCC、IAR适配及MDK更新④README文件及由更新驱动引起的脚本改动。 (#5638)
* 本次提交包括①BSP驱动新增②F103库更新③GCC、IAR适配及MDK更新④README文件及由更新驱动引起的脚本改动。 详情如下： 一、BSP驱动新增 这是本次PR的主要目的，现新增了如下BSP驱动： ADC、DAC、RTC、PWM、HWTIMER、I2C、SPI和WDT等八个驱动文件。 二、F103库更新： 本次提交使用2022年3月初极海官网发布的最新F103库，主要增加了版权声明、USB驱动及其他代码调整。 三、编译器适配： 1、新增GCC编译支持，在ENV工具下编译能成功且输出的bin文件能够使开发板闪灯。 2、新增IAR工程支持。 3、由F103的SDK更新，MDK的工程也进行了相应更新。 四、其他 1、README文件做了修改，加入了scons编译后的jlink下载说明和官网链接。 2、Kconfig、SConscript脚本根据驱动更新做了修改。 * 格式化代码（AStyle + Formatting） * 增加BSP APM版权声明 * 在ci添加当前bsp的路径，以能够验证gcc能否正常编译 * 路径的“\”改为“/”
This commit is contained in:
stevetong459
GitHub
1
.github/workflows/action.yml
vendored
1
.github/workflows/action.yml
vendored
@@ -31,6 +31,7 @@ jobs:
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legs:
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- {RTT_BSP: "acm32f0x0-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
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- {RTT_BSP: "CME_M7", RTT_TOOL_CHAIN: "sourcery-arm"}
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- {RTT_BSP: "apm32/apm32f103xe-minibroard", RTT_TOOL_CHAIN: "sourcery-arm"}
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- {RTT_BSP: "apollo2", RTT_TOOL_CHAIN: "sourcery-arm"}
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- {RTT_BSP: "asm9260t", RTT_TOOL_CHAIN: "sourcery-arm"}
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- {RTT_BSP: "at91sam9260", RTT_TOOL_CHAIN: "sourcery-arm"}
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@@ -20,6 +20,33 @@ Path:
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- bsp/acm32f0x0-nucleo/libraries
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### apm32
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bsp 列表：
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- apm32f103xe-minibroard
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------
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License: GEEHY SOFTWARE PACKAGE LICENSE
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Copyright: Copyright (C) 2020-2022 Geehy Semiconductor
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Path:
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- bsp\apm32\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver
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- bsp\apm32\libraries\APM32F10x_Library\Device
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- bsp\apm32\libraries\APM32F10x_Library\USB_Device_Lib
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------
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License: bsd-new
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Copyright (c) 2009-2018 Arm Limited
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Path:
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- bsp\apm32\libraries\APM32F10x_Library\CMSIS\Include
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### apollo2
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License: bsd-new
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@@ -17,17 +17,18 @@ APM32F103ZE MINI BOARD，采用标准JTAG/SWD调试接口，引出了全部的IO
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- 有关开发板和芯片的详情可至极海官网查阅。[官网开发板链接 ](https://www.geehy.com/support/apm32?id=192)
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该开发板常用 **板载资源** 如下：
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- MCU：APM32F103C8T6，主频 96MHz，512KB FLASH ，128KB RAM
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- MCU：APM32F103ZET6，主频 96MHz，512KB FLASH ，128KB RAM
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- 外部 RAM：无
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- 外部 FLASH：无
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- 常用外设
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- LED：2个，（黄色，PE5/PE6）
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- 按键：2个，K1（兼具唤醒功能，PA0），K2（PC13）
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- 常用接口：RS232转串口、、USB SLAVE
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- 常用接口：RS232转串口、USB SLAVE
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- 调试接口：标准 JTAG/SWD
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@@ -42,6 +43,14 @@ APM32F103ZE MINI BOARD，采用标准JTAG/SWD调试接口，引出了全部的IO
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| **片上外设** | **支持情况** | **备注** |
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| GPIO | 支持 | PA0, PA1... PG15 ---> PIN: 0, 1...143 |
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| UART | 支持 | UART1/2 |
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| ADC | 支持 | ADC1/2/3 |
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| DAC | 支持 | DAC1 |
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| RTC | 支持 | |
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| TMR | 支持 | TMR1/2/3/4/5/6/7/8 |
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| PWM | 支持 | TMR3 ->CH1/2 |
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| I2C | 支持 | 软件I2C |
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| SPI | 支持 | SPI1/2/3 |
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| WDT | 支持 | IWDT |
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## 使用说明
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@@ -57,11 +66,28 @@ APM32F103ZE MINI BOARD，采用标准JTAG/SWD调试接口，引出了全部的IO
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使用数据线连接开发板到 PC，打开电源开关。
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#### 编译下载
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- 方式一：MDK
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双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
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双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
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> 工程默认配置使用 J-Link 仿真器下载程序，在通过 J-Link 连接开发板的基础上，点击下载按钮即可下载程序到开发板
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- 方式二：J-Flash下载
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通过ENV工具的scons指令或MDK编译出bin文件后，再使用J-Flash工具将bin文件下载至开发板即可，大致步骤如下：
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##### 1、建立J-Flash工程
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##### 2、连接开发板
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##### 3、将bin文件拖至工程，起始地址设为0x8000000
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##### 4、点击下载
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#### 运行结果
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下载程序成功之后，系统会自动运行，LED 闪烁
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@@ -71,7 +97,7 @@ APM32F103ZE MINI BOARD，采用标准JTAG/SWD调试接口，引出了全部的IO
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```bash
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\ | /
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- RT - Thread Operating System
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/ | \ 4.0.4 build Aug 20 2021
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/ | \ 4.1.0 build Aug 20 2021
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2006 - 2021 Copyright by rt-thread team
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msh >
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```
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@@ -81,4 +107,6 @@ msh >
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## 联系人信息
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-[abbbcc ](https://gitee.com/abbbcc)
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-[abbbcc ](https://gitee.com/abbbcc)
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-[stevetong459 ](https://github.com/stevetong459)
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@@ -24,6 +24,155 @@ menu "On-chip Peripheral Drivers"
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default y
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endif
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menuconfig BSP_USING_ADC
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bool "Enable ADC"
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default n
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select RT_USING_ADC
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if BSP_USING_ADC
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config BSP_USING_ADC1
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bool "Enable ADC1"
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default n
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config BSP_USING_ADC2
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bool "Enable ADC2"
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default n
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config BSP_USING_ADC3
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bool "Enable ADC3"
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default n
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endif
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menuconfig BSP_USING_DAC
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bool "Enable DAC"
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default n
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select RT_USING_DAC
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if BSP_USING_DAC
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config BSP_USING_DAC1
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bool "Enable DAC1"
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default n
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endif
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menuconfig BSP_USING_ONCHIP_RTC
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bool "Enable RTC"
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select RT_USING_RTC
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default n
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if BSP_USING_ONCHIP_RTC
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choice
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prompt "Select clock source"
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default BSP_RTC_USING_LSE
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config BSP_RTC_USING_LSE
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bool "RTC USING LSE"
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config BSP_RTC_USING_LSI
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bool "RTC USING LSI"
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endchoice
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endif
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menuconfig BSP_USING_I2C1
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bool "Enable I2C1 BUS (software simulation)"
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default n
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select RT_USING_I2C
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select RT_USING_I2C_BITOPS
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select RT_USING_PIN
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if BSP_USING_I2C1
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config BSP_I2C1_SCL_PIN
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int "i2c1 scl pin number"
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range 0 63
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default 22
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config BSP_I2C1_SDA_PIN
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int "I2C1 sda pin number"
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range 0 63
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default 23
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endif
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menuconfig BSP_USING_SPI
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bool "Enable SPI"
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default n
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select RT_USING_SPI
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if BSP_USING_SPI
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config BSP_USING_SPI1
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bool "Enable SPI1"
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default n
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config BSP_USING_SPI2
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bool "Enable SPI2"
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default n
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config BSP_USING_SPI3
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bool "Enable SPI3"
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default n
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endif
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menuconfig BSP_USING_TMR
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bool "Enable Timer"
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default n
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select RT_USING_HWTIMER
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if BSP_USING_TMR
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config BSP_USING_TMR1
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bool "Enable TMR1"
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default n
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config BSP_USING_TMR2
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bool "Enable TMR2"
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default n
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config BSP_USING_TMR3
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bool "Enable TMR3"
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default n
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config BSP_USING_TMR4
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bool "Enable TMR4"
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default n
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config BSP_USING_TMR5
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bool "Enable TMR5"
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default n
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config BSP_USING_TMR6
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bool "Enable TMR6"
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default n
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config BSP_USING_TMR7
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bool "Enable TMR7"
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default n
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config BSP_USING_TMR8
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bool "Enable TMR8"
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default n
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endif
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menuconfig BSP_USING_PWM
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bool "Enable PWM"
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default n
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select RT_USING_PWM
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if BSP_USING_PWM
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menuconfig BSP_USING_PWM3
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bool "Enable timer3 output pwm"
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default n
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if BSP_USING_PWM3
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config BSP_USING_PWM3_CH1
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bool "Enable PWM3 channel1"
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default n
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config BSP_USING_PWM3_CH2
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bool "Enable PWM3 channel2"
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default n
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config BSP_USING_PWM3_CH3
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bool "Enable PWM3 channel3"
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default n
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config BSP_USING_PWM3_CH4
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bool "Enable PWM3 channel4"
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default n
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endif
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endif
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config BSP_USING_WDT
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bool "Enable Watchdog Timer"
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select RT_USING_WDT
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default n
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endmenu
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endmenu
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@@ -16,9 +16,15 @@ path = [cwd]
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startup_path_prefix = SDK_LIB
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if rtconfig.CROSS_TOOL == 'keil':
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src += [startup_path_prefix + '/APM32F10x_Library/Device/Geehy/APM32F10x/Source/ARM/startup_apm32f10x_hd.s']
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src += [startup_path_prefix + '/APM32F10x_Library/Device/Geehy/APM32F10x/Source/arm/startup_apm32f10x_hd.s']
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if rtconfig.CROSS_TOOL == 'iar':
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src += [startup_path_prefix + '/APM32F10x_Library/Device/Geehy/APM32F10x/Source/iar/startup_apm32f10x_hd.s']
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if rtconfig.CROSS_TOOL == 'gcc':
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src += [startup_path_prefix + '/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/startup_apm32f10x_hd.s']
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# You can select chips from the list above
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CPPDEFINES = ['APM32F103xE']
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CPPDEFINES = ['APM32F10X_HD']
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group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
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Return('group')
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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* Copyright (c) 2006-2022, RT-Thread Development Team
|
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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@@ -13,15 +13,15 @@
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void apm32_usart_init(void)
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{
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GPIO_Config_T GPIO_ConfigStruct;
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#ifdef BSP_USING_UART1
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RCM_EnableAPB2PeriphClock((RCM_APB2_PERIPH_T)(RCM_APB2_PERIPH_GPIOA | RCM_APB2_PERIPH_USART1));
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GPIO_ConfigStruct.mode = GPIO_MODE_AF_PP;
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GPIO_ConfigStruct.pin = GPIO_PIN_9;
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GPIO_ConfigStruct.speed = GPIO_SPEED_50MHz;
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GPIO_Config(GPIOA, &GPIO_ConfigStruct);
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GPIO_ConfigStruct.mode = GPIO_MODE_IN_PU;
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GPIO_ConfigStruct.pin = GPIO_PIN_10;
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GPIO_ConfigStruct.speed = GPIO_SPEED_50MHz;
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@@ -31,12 +31,12 @@ void apm32_usart_init(void)
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#ifdef BSP_USING_UART2
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RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIOA);
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RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_USART2);
|
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|
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|
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GPIO_ConfigStruct.mode = GPIO_MODE_AF_PP;
|
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GPIO_ConfigStruct.pin = GPIO_PIN_2;
|
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GPIO_ConfigStruct.speed = GPIO_SPEED_50MHz;
|
||||
GPIO_Config(GPIOA, &GPIO_ConfigStruct);
|
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|
||||
|
||||
GPIO_ConfigStruct.mode = GPIO_MODE_IN_PU;
|
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GPIO_ConfigStruct.pin = GPIO_PIN_3;
|
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GPIO_ConfigStruct.speed = GPIO_SPEED_50MHz;
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|
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@@ -1,11 +1,12 @@
|
||||
/*
|
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* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-08-20 Abbcc first version
|
||||
* Date Author Notes
|
||||
* 2020-08-20 Abbcc first version
|
||||
* 2022-03-04 stevetong459 Add head file of new driver
|
||||
*/
|
||||
|
||||
#ifndef __BOARD_H__
|
||||
@@ -21,6 +22,27 @@
|
||||
#include "apm32f10x_eint.h"
|
||||
#include "apm32f10x_usart.h"
|
||||
|
||||
#if defined(RT_USING_ADC)
|
||||
#include "apm32f10x_adc.h"
|
||||
#endif
|
||||
#if defined(RT_USING_DAC)
|
||||
#include "apm32f10x_dac.h"
|
||||
#endif
|
||||
#if defined(RT_USING_RTC)
|
||||
#include "apm32f10x_rtc.h"
|
||||
#include "apm32f10x_pmu.h"
|
||||
#endif
|
||||
#if defined(RT_USING_SPI)
|
||||
#include "apm32f10x_spi.h"
|
||||
#endif
|
||||
#if defined(RT_USING_HWTIMER) || defined(RT_USING_PWM)
|
||||
#include "apm32f10x_tmr.h"
|
||||
#endif
|
||||
#if defined(RT_USING_WDT)
|
||||
#include "apm32f10x_iwdt.h"
|
||||
#include "apm32f10x_wwdt.h"
|
||||
#endif
|
||||
|
||||
#include "drv_common.h"
|
||||
#include "drv_gpio.h"
|
||||
|
||||
|
||||
@@ -0,0 +1,28 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x0400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x0000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite, last block CSTACK};
|
||||
141
bsp/apm32/apm32f103xe-minibroard/board/linker_scripts/link.lds
Normal file
141
bsp/apm32/apm32f103xe-minibroard/board/linker_scripts/link.lds
Normal file
@@ -0,0 +1,141 @@
|
||||
/*
|
||||
* linker script for APM32F10x with GNU ld
|
||||
*/
|
||||
|
||||
/* Program Entry, set to mark it as "used" and avoid gc */
|
||||
MEMORY
|
||||
{
|
||||
CODE (rx) : ORIGIN = 0x08000000, LENGTH = 512k /* 512KB flash */
|
||||
DATA (rw) : ORIGIN = 0x20000000, LENGTH = 128k /* 128KB sram */
|
||||
}
|
||||
ENTRY(Reset_Handler)
|
||||
_system_stack_size = 0x200;
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_stext = .;
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
*(.text) /* remaining code */
|
||||
*(.text.*) /* remaining code */
|
||||
*(.rodata) /* read-only data (constants) */
|
||||
*(.rodata*)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.gnu.linkonce.t*)
|
||||
|
||||
/* section information for finsh shell */
|
||||
. = ALIGN(4);
|
||||
__fsymtab_start = .;
|
||||
KEEP(*(FSymTab))
|
||||
__fsymtab_end = .;
|
||||
. = ALIGN(4);
|
||||
__vsymtab_start = .;
|
||||
KEEP(*(VSymTab))
|
||||
__vsymtab_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
/* section information for initial. */
|
||||
. = ALIGN(4);
|
||||
__rt_init_start = .;
|
||||
KEEP(*(SORT(.rti_fn*)))
|
||||
__rt_init_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
} > CODE = 0
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
|
||||
/* This is used by the startup in order to initialize the .data secion */
|
||||
_sidata = .;
|
||||
} > CODE
|
||||
__exidx_end = .;
|
||||
|
||||
/* .data section which is used for initialized data */
|
||||
|
||||
.data : AT (_sidata)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .data secion */
|
||||
_sdata = . ;
|
||||
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d*)
|
||||
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .data secion */
|
||||
_edata = . ;
|
||||
} >DATA
|
||||
|
||||
.stack :
|
||||
{
|
||||
. = . + _system_stack_size;
|
||||
. = ALIGN(4);
|
||||
_estack = .;
|
||||
} >DATA
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
_sbss = .;
|
||||
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
_ebss = . ;
|
||||
|
||||
*(.bss.init)
|
||||
} > DATA
|
||||
__bss_end = .;
|
||||
|
||||
_end = .;
|
||||
|
||||
/* Stabs debugging sections. */
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
/* DWARF debug sections.
|
||||
* Symbols in the DWARF debugging sections are relative to the beginning
|
||||
* of the section so we begin them at 0. */
|
||||
/* DWARF 1 */
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
/* GNU DWARF 1 extensions */
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
/* DWARF 1.1 and DWARF 2 */
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
/* DWARF 2 */
|
||||
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
/* SGI/MIPS DWARF 2 extensions */
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
}
|
||||
BIN
bsp/apm32/apm32f103xe-minibroard/figures/JFlash_Leader_01.png
Normal file
BIN
bsp/apm32/apm32f103xe-minibroard/figures/JFlash_Leader_01.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 46 KiB |
BIN
bsp/apm32/apm32f103xe-minibroard/figures/JFlash_Leader_02.png
Normal file
BIN
bsp/apm32/apm32f103xe-minibroard/figures/JFlash_Leader_02.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 9.7 KiB |
BIN
bsp/apm32/apm32f103xe-minibroard/figures/JFlash_Leader_03.png
Normal file
BIN
bsp/apm32/apm32f103xe-minibroard/figures/JFlash_Leader_03.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 3.5 KiB |
BIN
bsp/apm32/apm32f103xe-minibroard/figures/JFlash_Leader_04.png
Normal file
BIN
bsp/apm32/apm32f103xe-minibroard/figures/JFlash_Leader_04.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 12 KiB |
2346
bsp/apm32/apm32f103xe-minibroard/project.ewp
Normal file
2346
bsp/apm32/apm32f103xe-minibroard/project.ewp
Normal file
File diff suppressed because it is too large
Load Diff
10
bsp/apm32/apm32f103xe-minibroard/project.eww
Normal file
10
bsp/apm32/apm32f103xe-minibroard/project.eww
Normal file
@@ -0,0 +1,10 @@
|
||||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<workspace>
|
||||
<project>
|
||||
<path>$WS_DIR$\project.ewp</path>
|
||||
</project>
|
||||
<batchBuild/>
|
||||
</workspace>
|
||||
|
||||
|
||||
805
bsp/apm32/apm32f103xe-minibroard/project.uvoptx
Normal file
805
bsp/apm32/apm32f103xe-minibroard/project.uvoptx
Normal file
File diff suppressed because it is too large
Load Diff
@@ -13,7 +13,7 @@
|
||||
<TargetCommonOption>
|
||||
<Device>APM32F103ZE</Device>
|
||||
<Vendor>Geehy</Vendor>
|
||||
<PackID>Geehy.APM32F1xx_DFP.1.0.7</PackID>
|
||||
<PackID>Geehy.APM32F1xx_DFP.1.0.8</PackID>
|
||||
<PackURL>https://www.geehy.com/uploads/tool/</PackURL>
|
||||
<Cpu>IRAM(0x20000000,0x00020000) IROM(0x08000000,0x00080000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE</Cpu>
|
||||
<FlashUtilSpec />
|
||||
@@ -182,7 +182,6 @@
|
||||
<uocXRam>0</uocXRam>
|
||||
<RvdsVP>0</RvdsVP>
|
||||
<RvdsMve>0</RvdsMve>
|
||||
<RvdsCdeCp>0</RvdsCdeCp>
|
||||
<hadIRAM2>0</hadIRAM2>
|
||||
<hadIROM2>0</hadIROM2>
|
||||
<StupSel>8</StupSel>
|
||||
@@ -334,9 +333,9 @@
|
||||
<v6Rtti>0</v6Rtti>
|
||||
<VariousControls>
|
||||
<MiscControls />
|
||||
<Define>USE_STDPERIPH_DRIVER, __RTTHREAD__, APM32F103xE, RT_USING_ARM_LIBC, __CLK_TCK=RT_TICK_PER_SECOND</Define>
|
||||
<Define>USE_STDPERIPH_DRIVER, APM32F10X_HD, __RTTHREAD__, RT_USING_ARM_LIBC, __CLK_TCK=RT_TICK_PER_SECOND</Define>
|
||||
<Undefine />
|
||||
<IncludePath>applications;..\..\..\components\libc\compilers\common;..\..\..\components\libc\compilers\common\extension;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m3;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;..\libraries\Drivers;..\libraries\Drivers\config;..\..\..\components\finsh;.;..\..\..\include;..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Include;..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\inc;..\libraries\APM32F10x_Library\CMSIS\Include;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\posix\io\stdio;..\..\..\components\libc\posix\ipc;..\..\..\examples\utest\testcases\kernel</IncludePath>
|
||||
<IncludePath>applications;..\..\..\components\libc\compilers\common;..\..\..\components\libc\compilers\common\nogcc;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m3;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;..\libraries\Drivers;..\libraries\Drivers\config;..\..\..\components\finsh;.;..\..\..\include;..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Include;..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\inc;..\libraries\APM32F10x_Library\CMSIS\Include;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\posix\ipc;..\..\..\examples\utest\testcases\kernel</IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
<Aads>
|
||||
@@ -349,7 +348,7 @@
|
||||
<NoWarn>0</NoWarn>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<useXO>0</useXO>
|
||||
<ClangAsOpt>4</ClangAsOpt>
|
||||
<uClangAs>0</uClangAs>
|
||||
<VariousControls>
|
||||
<MiscControls />
|
||||
<Define />
|
||||
@@ -391,9 +390,9 @@
|
||||
<GroupName>Compiler</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>syscalls.c</FileName>
|
||||
<FileName>libc_syms.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\components\libc\compilers\armlibc\syscalls.c</FilePath>
|
||||
<FilePath>..\..\..\components\libc\compilers\armlibc\libc_syms.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
@@ -405,9 +404,9 @@
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>stdlib.c</FileName>
|
||||
<FileName>syscalls.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\components\libc\compilers\common\stdlib.c</FilePath>
|
||||
<FilePath>..\..\..\components\libc\compilers\armlibc\syscalls.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
@@ -417,6 +416,13 @@
|
||||
<FilePath>..\..\..\components\libc\compilers\common\time.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>stdlib.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\components\libc\compilers\common\stdlib.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>CPU</GroupName>
|
||||
@@ -429,16 +435,16 @@
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>div0.c</FileName>
|
||||
<FileName>backtrace.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\libcpu\arm\common\div0.c</FilePath>
|
||||
<FilePath>..\..\..\libcpu\arm\common\backtrace.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>backtrace.c</FileName>
|
||||
<FileName>div0.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\libcpu\arm\common\backtrace.c</FilePath>
|
||||
<FilePath>..\..\..\libcpu\arm\common\div0.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
@@ -458,55 +464,6 @@
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>DeviceDrivers</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>completion.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\components\drivers\ipc\completion.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>ringbuffer.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\components\drivers\ipc\ringbuffer.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>waitqueue.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\components\drivers\ipc\waitqueue.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>dataqueue.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\components\drivers\ipc\dataqueue.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>pipe.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\components\drivers\ipc\pipe.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>workqueue.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\components\drivers\ipc\workqueue.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>ringblk_buf.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\components\drivers\ipc\ringblk_buf.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>pin.c</FileName>
|
||||
@@ -521,21 +478,70 @@
|
||||
<FilePath>..\..\..\components\drivers\serial\serial.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>ringbuffer.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\components\drivers\src\ringbuffer.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>pipe.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\components\drivers\src\pipe.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>ringblk_buf.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\components\drivers\src\ringblk_buf.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>workqueue.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\components\drivers\src\workqueue.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>dataqueue.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\components\drivers\src\dataqueue.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>waitqueue.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\components\drivers\src\waitqueue.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>completion.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\components\drivers\src\completion.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>Drivers</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>startup_apm32f10x_hd.s</FileName>
|
||||
<FileType>2</FileType>
|
||||
<FilePath>..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Source\ARM\startup_apm32f10x_hd.s</FilePath>
|
||||
<FileName>board.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>board\board.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>board.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>board\board.c</FilePath>
|
||||
<FileName>startup_apm32f10x_hd.s</FileName>
|
||||
<FileType>2</FileType>
|
||||
<FilePath>..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Source\arm\startup_apm32f10x_hd.s</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
@@ -588,16 +594,37 @@
|
||||
<GroupName>Kernel</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>clock.c</FileName>
|
||||
<FileName>thread.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\src\clock.c</FilePath>
|
||||
<FilePath>..\..\..\src\thread.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>kservice.c</FileName>
|
||||
<FileName>mempool.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\src\kservice.c</FilePath>
|
||||
<FilePath>..\..\..\src\mempool.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>timer.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\src\timer.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>object.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\src\object.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>clock.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\src\clock.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
@@ -630,9 +657,16 @@
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>mempool.c</FileName>
|
||||
<FileName>kservice.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\src\mempool.c</FilePath>
|
||||
<FilePath>..\..\..\src\kservice.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>irq.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\src\irq.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
@@ -642,20 +676,6 @@
|
||||
<FilePath>..\..\..\src\components.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>thread.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\src\thread.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>object.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\src\object.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>idle.c</FileName>
|
||||
@@ -663,20 +683,6 @@
|
||||
<FilePath>..\..\..\src\idle.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>timer.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\src\timer.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>irq.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\src\irq.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>Libraries</GroupName>
|
||||
|
||||
2114
bsp/apm32/apm32f103xe-minibroard/template.ewp
Normal file
2114
bsp/apm32/apm32f103xe-minibroard/template.ewp
Normal file
File diff suppressed because it is too large
Load Diff
10
bsp/apm32/apm32f103xe-minibroard/template.eww
Normal file
10
bsp/apm32/apm32f103xe-minibroard/template.eww
Normal file
@@ -0,0 +1,10 @@
|
||||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<workspace>
|
||||
<project>
|
||||
<path>$WS_DIR$\template.ewp</path>
|
||||
</project>
|
||||
<batchBuild/>
|
||||
</workspace>
|
||||
|
||||
|
||||
185
bsp/apm32/apm32f103xe-minibroard/template.uvoptx
Normal file
185
bsp/apm32/apm32f103xe-minibroard/template.uvoptx
Normal file
@@ -0,0 +1,185 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
|
||||
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Extensions>
|
||||
<cExt>*.c</cExt>
|
||||
<aExt>*.s*; *.src; *.a*</aExt>
|
||||
<oExt>*.obj; *.o</oExt>
|
||||
<lExt>*.lib</lExt>
|
||||
<tExt>*.txt; *.h; *.inc</tExt>
|
||||
<pExt>*.plm</pExt>
|
||||
<CppX>*.cpp</CppX>
|
||||
<nMigrate>0</nMigrate>
|
||||
</Extensions>
|
||||
|
||||
<DaveTm>
|
||||
<dwLowDateTime>0</dwLowDateTime>
|
||||
<dwHighDateTime>0</dwHighDateTime>
|
||||
</DaveTm>
|
||||
|
||||
<Target>
|
||||
<TargetName>rt-thread</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>12000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
||||
<BeepAtEnd>1</BeepAtEnd>
|
||||
<RunSim>0</RunSim>
|
||||
<RunTarget>1</RunTarget>
|
||||
<RunAbUc>0</RunAbUc>
|
||||
</OPTTT>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<FlashByte>65535</FlashByte>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
</OPTHX>
|
||||
<OPTLEX>
|
||||
<PageWidth>79</PageWidth>
|
||||
<PageLength>66</PageLength>
|
||||
<TabStop>8</TabStop>
|
||||
<ListingPath>.\build\keil\List\</ListingPath>
|
||||
</OPTLEX>
|
||||
<ListingPage>
|
||||
<CreateCListing>1</CreateCListing>
|
||||
<CreateAListing>1</CreateAListing>
|
||||
<CreateLListing>1</CreateLListing>
|
||||
<CreateIListing>0</CreateIListing>
|
||||
<AsmCond>1</AsmCond>
|
||||
<AsmSymb>1</AsmSymb>
|
||||
<AsmXref>0</AsmXref>
|
||||
<CCond>1</CCond>
|
||||
<CCode>0</CCode>
|
||||
<CListInc>0</CListInc>
|
||||
<CSymb>0</CSymb>
|
||||
<LinkerCodeListing>0</LinkerCodeListing>
|
||||
</ListingPage>
|
||||
<OPTXL>
|
||||
<LMap>1</LMap>
|
||||
<LComments>1</LComments>
|
||||
<LGenerateSymbols>1</LGenerateSymbols>
|
||||
<LLibSym>1</LLibSym>
|
||||
<LLines>1</LLines>
|
||||
<LLocSym>1</LLocSym>
|
||||
<LPubSym>1</LPubSym>
|
||||
<LXref>0</LXref>
|
||||
<LExpSel>0</LExpSel>
|
||||
</OPTXL>
|
||||
<OPTFL>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<IsCurrentTarget>1</IsCurrentTarget>
|
||||
</OPTFL>
|
||||
<CpuCode>0</CpuCode>
|
||||
<DebugOpt>
|
||||
<uSim>0</uSim>
|
||||
<uTrg>1</uTrg>
|
||||
<sLdApp>1</sLdApp>
|
||||
<sGomain>1</sGomain>
|
||||
<sRbreak>1</sRbreak>
|
||||
<sRwatch>1</sRwatch>
|
||||
<sRmem>1</sRmem>
|
||||
<sRfunc>1</sRfunc>
|
||||
<sRbox>1</sRbox>
|
||||
<tLdApp>1</tLdApp>
|
||||
<tGomain>1</tGomain>
|
||||
<tRbreak>1</tRbreak>
|
||||
<tRwatch>1</tRwatch>
|
||||
<tRmem>1</tRmem>
|
||||
<tRfunc>0</tRfunc>
|
||||
<tRbox>1</tRbox>
|
||||
<tRtrace>1</tRtrace>
|
||||
<sRSysVw>1</sRSysVw>
|
||||
<tRSysVw>1</tRSysVw>
|
||||
<sRunDeb>0</sRunDeb>
|
||||
<sLrtime>0</sLrtime>
|
||||
<bEvRecOn>1</bEvRecOn>
|
||||
<bSchkAxf>0</bSchkAxf>
|
||||
<bTchkAxf>0</bTchkAxf>
|
||||
<nTsel>4</nTsel>
|
||||
<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
<sDlgPa></sDlgPa>
|
||||
<sIfile></sIfile>
|
||||
<tDll></tDll>
|
||||
<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
||||
<tIfile></tIfile>
|
||||
<pMon>Segger\JL2CM3.dll</pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>JL2CM3</Key>
|
||||
<Name>-U59701291 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC1000 -FN1 -FF0APM32F10x_512.FLM -FS08000000 -FL080000 -FP0($$Device:APM32F103ZE$Flash\APM32F10x_512.FLM)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>UL2CM3</Key>
|
||||
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0APM32F10x_512 -FS08000000 -FL080000 -FP0($$Device:APM32F103ZE$Flash\APM32F10x_512.FLM))</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<Breakpoint/>
|
||||
<Tracepoint>
|
||||
<THDelay>0</THDelay>
|
||||
</Tracepoint>
|
||||
<DebugFlag>
|
||||
<trace>0</trace>
|
||||
<periodic>0</periodic>
|
||||
<aLwin>0</aLwin>
|
||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
<aPa>0</aPa>
|
||||
<viewmode>0</viewmode>
|
||||
<vrSel>0</vrSel>
|
||||
<aSym>0</aSym>
|
||||
<aTbox>0</aTbox>
|
||||
<AscS1>0</AscS1>
|
||||
<AscS2>0</AscS2>
|
||||
<AscS3>0</AscS3>
|
||||
<aSer3>0</aSer3>
|
||||
<eProf>0</eProf>
|
||||
<aLa>0</aLa>
|
||||
<aPa1>0</aPa1>
|
||||
<AscS4>0</AscS4>
|
||||
<aSer4>0</aSer4>
|
||||
<StkLoc>0</StkLoc>
|
||||
<TrcWin>0</TrcWin>
|
||||
<newCpu>0</newCpu>
|
||||
<uProt>0</uProt>
|
||||
</DebugFlag>
|
||||
<LintExecutable></LintExecutable>
|
||||
<LintConfigFile></LintConfigFile>
|
||||
<bLintAuto>0</bLintAuto>
|
||||
<bAutoGenD>0</bAutoGenD>
|
||||
<LntExFlags>0</LntExFlags>
|
||||
<pMisraName></pMisraName>
|
||||
<pszMrule></pszMrule>
|
||||
<pSingCmds></pSingCmds>
|
||||
<pMultCmds></pMultCmds>
|
||||
<pMisraNamep></pMisraNamep>
|
||||
<pszMrulep></pszMrulep>
|
||||
<pSingCmdsp></pSingCmdsp>
|
||||
<pMultCmdsp></pMultCmdsp>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
|
||||
<Group>
|
||||
<GroupName>Source Group 1</GroupName>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
</Group>
|
||||
|
||||
</ProjectOpt>
|
||||
@@ -16,7 +16,7 @@
|
||||
<TargetCommonOption>
|
||||
<Device>APM32F103ZE</Device>
|
||||
<Vendor>Geehy</Vendor>
|
||||
<PackID>Geehy.APM32F1xx_DFP.1.0.7</PackID>
|
||||
<PackID>Geehy.APM32F1xx_DFP.1.0.8</PackID>
|
||||
<PackURL>https://www.geehy.com/uploads/tool/</PackURL>
|
||||
<Cpu>IRAM(0x20000000,0x00020000) IROM(0x08000000,0x00080000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE</Cpu>
|
||||
<FlashUtilSpec></FlashUtilSpec>
|
||||
@@ -185,7 +185,6 @@
|
||||
<uocXRam>0</uocXRam>
|
||||
<RvdsVP>0</RvdsVP>
|
||||
<RvdsMve>0</RvdsMve>
|
||||
<RvdsCdeCp>0</RvdsCdeCp>
|
||||
<hadIRAM2>0</hadIRAM2>
|
||||
<hadIROM2>0</hadIROM2>
|
||||
<StupSel>8</StupSel>
|
||||
@@ -352,7 +351,7 @@
|
||||
<NoWarn>0</NoWarn>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<useXO>0</useXO>
|
||||
<ClangAsOpt>4</ClangAsOpt>
|
||||
<uClangAs>0</uClangAs>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
|
||||
@@ -3,21 +3,35 @@
|
||||
*
|
||||
* @brief This file contains all the functions prototypes for the ADC firmware library
|
||||
*
|
||||
* @version V1.0.1
|
||||
* @version V1.0.2
|
||||
*
|
||||
* @date 2021-03-23
|
||||
* @date 2022-01-05
|
||||
*
|
||||
* @attention
|
||||
*
|
||||
* Copyright (C) 2020-2022 Geehy Semiconductor
|
||||
*
|
||||
* You may not use this file except in compliance with the
|
||||
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
|
||||
*
|
||||
* The program is only for reference, which is distributed in the hope
|
||||
* that it will be usefull and instructional for customers to develop
|
||||
* their software. Unless required by applicable law or agreed to in
|
||||
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
|
||||
* and limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __APM32F10X_ADC_H
|
||||
#define __APM32F10X_ADC_H
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
/** @addtogroup Peripherals_Library Standard Peripheral Library
|
||||
@{
|
||||
*/
|
||||
@@ -62,7 +76,7 @@ typedef enum
|
||||
ADC_EXT_TRIG_CONV_None = ((uint32_t)0x000E0000),
|
||||
|
||||
ADC_EXT_TRIG_CONV_TMR3_CC1 = ((uint32_t)0x00000000),
|
||||
ADC_EXT_TRIG_CONV_TMR2_CC3 = ((uint32_t)0x00030000),
|
||||
ADC_EXT_TRIG_CONV_TMR2_CC3 = ((uint32_t)0x00020000),
|
||||
ADC_EXT_TRIG_CONV_TMR8_CC1 = ((uint32_t)0x00060000),
|
||||
ADC_EXT_TRIG_CONV_TMR8_TRGO = ((uint32_t)0x00080000),
|
||||
ADC_EXT_TRIG_CONV_TMR5_CC1 = ((uint32_t)0x000A0000),
|
||||
@@ -110,15 +124,15 @@ typedef enum
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_SAMPLE_TIME_1_5 = ((uint8_t)0x00),
|
||||
ADC_SAMPLE_TIME_7_5 = ((uint8_t)0x01),
|
||||
ADC_SAMPLE_TIME_13_5 = ((uint8_t)0x02),
|
||||
ADC_SAMPLE_TIME_28_5 = ((uint8_t)0x03),
|
||||
ADC_SAMPLE_TIME_41_5 = ((uint8_t)0x04),
|
||||
ADC_SAMPLE_TIME_55_5 = ((uint8_t)0x05),
|
||||
ADC_SAMPLE_TIME_71_5 = ((uint8_t)0x06),
|
||||
ADC_SAMPLE_TIME_239_5 = ((uint8_t)0x07)
|
||||
} ADC_SAMPLE_TIME_T;
|
||||
ADC_SAMPLETIME_1CYCLES5 = ((uint8_t)0x00),
|
||||
ADC_SAMPLETIME_7CYCLES5 = ((uint8_t)0x01),
|
||||
ADC_SAMPLETIME_13CYCLES5 = ((uint8_t)0x02),
|
||||
ADC_SAMPLETIME_28CYCLES5 = ((uint8_t)0x03),
|
||||
ADC_SAMPLETIME_41CYCLES5 = ((uint8_t)0x04),
|
||||
ADC_SAMPLETIME_55CYCLES5 = ((uint8_t)0x05),
|
||||
ADC_SAMPLETIME_71CYCLES5 = ((uint8_t)0x06),
|
||||
ADC_SAMPLETIME_239CYCLES5 = ((uint8_t)0x07)
|
||||
} ADC_SAMPLETIME_T;
|
||||
|
||||
/**
|
||||
* @brief ADC external trigger sources for injected channels conversion
|
||||
@@ -246,80 +260,80 @@ typedef struct
|
||||
*/
|
||||
|
||||
/** ADC reset and common configuration */
|
||||
void ADC_Reset(ADC_T* adc);
|
||||
void ADC_Config(ADC_T* adc, ADC_Config_T* adcConfig);
|
||||
void ADC_ConfigStructInit(ADC_Config_T* adcConfig);
|
||||
void ADC_ConfigRegularChannel(ADC_T* adc, uint8_t channel,uint8_t rank, uint8_t sampleTime);
|
||||
void ADC_Enable(ADC_T* adc);
|
||||
void ADC_Disable(ADC_T* adc);
|
||||
void ADC_Reset(ADC_T *adc);
|
||||
void ADC_Config(ADC_T *adc, ADC_Config_T *adcConfig);
|
||||
void ADC_ConfigStructInit(ADC_Config_T *adcConfig);
|
||||
void ADC_ConfigRegularChannel(ADC_T *adc, uint8_t channel, uint8_t rank, uint8_t sampleTime);
|
||||
void ADC_Enable(ADC_T *adc);
|
||||
void ADC_Disable(ADC_T *adc);
|
||||
|
||||
/** ADC for DMA */
|
||||
void ADC_EnableDMA(ADC_T* adc);
|
||||
void ADC_DisableDMA(ADC_T* adc);
|
||||
void ADC_EnableDMA(ADC_T *adc);
|
||||
void ADC_DisableDMA(ADC_T *adc);
|
||||
|
||||
/** ADC Calibration */
|
||||
void ADC_ResetCalibration(ADC_T* adc);
|
||||
uint8_t ADC_ReadResetCalibrationStatus(ADC_T* adc);
|
||||
void ADC_StartCalibration(ADC_T* adc);
|
||||
uint8_t ADC_ReadCalibrationStartFlag(ADC_T* adc);
|
||||
void ADC_ResetCalibration(ADC_T *adc);
|
||||
uint8_t ADC_ReadResetCalibrationStatus(ADC_T *adc);
|
||||
void ADC_StartCalibration(ADC_T *adc);
|
||||
uint8_t ADC_ReadCalibrationStartFlag(ADC_T *adc);
|
||||
|
||||
/** ADC software start conversion */
|
||||
void ADC_EnableSoftwareStartConv(ADC_T* adc);
|
||||
void ADC_DisableSoftwareStartConv(ADC_T* adc);
|
||||
uint8_t ADC_ReadSoftwareStartConvStatus(ADC_T* adc);
|
||||
void ADC_EnableSoftwareStartConv(ADC_T *adc);
|
||||
void ADC_DisableSoftwareStartConv(ADC_T *adc);
|
||||
uint8_t ADC_ReadSoftwareStartConvStatus(ADC_T *adc);
|
||||
|
||||
/** ADC Discontinuous mode */
|
||||
void ADC_ConfigDiscModeChannel(ADC_T* adc, uint8_t number);
|
||||
void ADC_EnableDiscMode(ADC_T* adc);
|
||||
void ADC_DisableDiscMode(ADC_T* adc);
|
||||
void ADC_ConfigDiscMode(ADC_T *adc, uint8_t number);
|
||||
void ADC_EnableDiscMode(ADC_T *adc);
|
||||
void ADC_DisableDiscMode(ADC_T *adc);
|
||||
|
||||
/** ADC External trigger conversion */
|
||||
void ADC_EnableExternalTrigConv(ADC_T* adc);
|
||||
void ADC_DisableExternalTrigConv(ADC_T* adc);
|
||||
void ADC_EnableExternalTrigConv(ADC_T *adc);
|
||||
void ADC_DisableExternalTrigConv(ADC_T *adc);
|
||||
|
||||
/** ADC Conversion result */
|
||||
uint16_t ADC_ReadConversionValue(ADC_T* adc);
|
||||
uint32_t ADC_ReadDualModeConversionValue(ADC_T* adc);
|
||||
uint16_t ADC_ReadConversionValue(ADC_T *adc);
|
||||
uint32_t ADC_ReadDualModeConversionValue(ADC_T *adc);
|
||||
|
||||
/** ADC Automatic injected group */
|
||||
void ADC_EnableInjectedConv(ADC_T* adc);
|
||||
void ADC_DisableInjectedConv(ADC_T* adc);
|
||||
void ADC_EnableInjectedDiscMode(ADC_T* adc);
|
||||
void ADC_DisableInjectedDiscMode(ADC_T* adc);
|
||||
void ADC_EnableAutoInjectedConv(ADC_T *adc);
|
||||
void ADC_DisableAutoInjectedConv(ADC_T *adc);
|
||||
void ADC_EnableInjectedDiscMode(ADC_T *adc);
|
||||
void ADC_DisableInjectedDiscMode(ADC_T *adc);
|
||||
|
||||
/** ADC External trigger for injected channels conversion */
|
||||
void ADC_ConfigExternalTrigInjectedConv(ADC_T* adc, ADC_EXT_TRIG_INJEC_CONV_T extTrigInjecConv);
|
||||
void ADC_EnableExternalTrigInjectedConv(ADC_T* adc);
|
||||
void ADC_DisableExternalTrigInjectedConv(ADC_T* adc);
|
||||
void ADC_ConfigExternalTrigInjectedConv(ADC_T *adc, ADC_EXT_TRIG_INJEC_CONV_T extTrigInjecConv);
|
||||
void ADC_EnableExternalTrigInjectedConv(ADC_T *adc);
|
||||
void ADC_DisableExternalTrigInjectedConv(ADC_T *adc);
|
||||
|
||||
/** ADC Start of the injected channels conversion */
|
||||
void ADC_EnableSoftwareStartInjectedConv(ADC_T* adc);
|
||||
void ADC_DisableSoftwareStartInjectedConv(ADC_T* adc);
|
||||
uint8_t ADC_ReadSoftwareStartInjectedConvStatus(ADC_T* adc);
|
||||
void ADC_EnableSoftwareStartInjectedConv(ADC_T *adc);
|
||||
void ADC_DisableSoftwareStartInjectedConv(ADC_T *adc);
|
||||
uint8_t ADC_ReadSoftwareStartInjectedConvStatus(ADC_T *adc);
|
||||
|
||||
/** ADC injected channel */
|
||||
void ADC_ConfigInjectedChannel(ADC_T* adc, uint8_t channel, uint8_t rank, uint8_t sampleTime);
|
||||
void ADC_ConfigInjectedSequencerLength(ADC_T* adc, uint8_t length);
|
||||
void ADC_ConfigInjectedOffset(ADC_T* adc, ADC_INJEC_CHANNEL_T channel, uint16_t offSet);
|
||||
uint16_t ADC_ReadInjectedConversionValue(ADC_T* adc, ADC_INJEC_CHANNEL_T channel);
|
||||
void ADC_ConfigInjectedChannel(ADC_T *adc, uint8_t channel, uint8_t rank, uint8_t sampleTime);
|
||||
void ADC_ConfigInjectedSequencerLength(ADC_T *adc, uint8_t length);
|
||||
void ADC_ConfigInjectedOffset(ADC_T *adc, ADC_INJEC_CHANNEL_T channel, uint16_t offSet);
|
||||
uint16_t ADC_ReadInjectedConversionValue(ADC_T *adc, ADC_INJEC_CHANNEL_T channel);
|
||||
|
||||
/** ADC analog watchdog */
|
||||
void ADC_EnableAnalogWatchdog(ADC_T* adc, uint32_t analogWatchdog);
|
||||
void ADC_DisableAnalogWatchdog(ADC_T* adc);
|
||||
void ADC_ConfigAnalogWatchdogThresholds(ADC_T* adc, uint16_t highThreshold, uint16_t lowThreshold);
|
||||
void ADC_ConfigAnalogWatchdogSingleChannel(ADC_T* adc, uint8_t channel);
|
||||
void ADC_EnableAnalogWatchdog(ADC_T *adc, uint32_t analogWatchdog);
|
||||
void ADC_DisableAnalogWatchdog(ADC_T *adc);
|
||||
void ADC_ConfigAnalogWatchdogThresholds(ADC_T *adc, uint16_t highThreshold, uint16_t lowThreshold);
|
||||
void ADC_ConfigAnalogWatchdogSingleChannel(ADC_T *adc, uint8_t channel);
|
||||
|
||||
/** ADC temperature sensor */
|
||||
void ADC_EnableTempSensorVrefint(ADC_T* adc);
|
||||
void ADC_DisableTempSensorVrefint(ADC_T* adc);
|
||||
void ADC_EnableTempSensorVrefint(ADC_T *adc);
|
||||
void ADC_DisableTempSensorVrefint(ADC_T *adc);
|
||||
|
||||
/** Interrupt and flag */
|
||||
void ADC_EnableInterrupt(ADC_T* adc, uint16_t interrupt);
|
||||
void ADC_DisableInterrupt(ADC_T* adc, uint16_t interrupt);
|
||||
uint8_t ADC_ReadStatusFlag(ADC_T* adc, ADC_FLAG_T flag);
|
||||
void ADC_ClearStatusFlag(ADC_T* adc, uint8_t flag);
|
||||
uint8_t ADC_ReadIntFlag(ADC_T* adc, ADC_INT_T interrupt);
|
||||
void ADC_ClearIntFlag(ADC_T* adc, uint16_t interrupt);
|
||||
void ADC_EnableInterrupt(ADC_T *adc, uint16_t interrupt);
|
||||
void ADC_DisableInterrupt(ADC_T *adc, uint16_t interrupt);
|
||||
uint8_t ADC_ReadStatusFlag(ADC_T *adc, ADC_FLAG_T flag);
|
||||
void ADC_ClearStatusFlag(ADC_T *adc, uint8_t flag);
|
||||
uint8_t ADC_ReadIntFlag(ADC_T *adc, ADC_INT_T flag);
|
||||
void ADC_ClearIntFlag(ADC_T *adc, uint16_t flag);
|
||||
|
||||
/**@} end of group ADC_Fuctions*/
|
||||
/**@} end of group ADC_Driver*/
|
||||
|
||||
@@ -3,21 +3,35 @@
|
||||
*
|
||||
* @brief This file contains all the functions prototypes for the BAKPR firmware library.
|
||||
*
|
||||
* @version V1.0.1
|
||||
* @version V1.0.2
|
||||
*
|
||||
* @date 2021-03-23
|
||||
* @date 2022-01-05
|
||||
*
|
||||
* @attention
|
||||
*
|
||||
* Copyright (C) 2020-2022 Geehy Semiconductor
|
||||
*
|
||||
* You may not use this file except in compliance with the
|
||||
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
|
||||
*
|
||||
* The program is only for reference, which is distributed in the hope
|
||||
* that it will be usefull and instructional for customers to develop
|
||||
* their software. Unless required by applicable law or agreed to in
|
||||
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
|
||||
* and limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __APM32F10X_BAKPR_H
|
||||
#define __APM32F10X_BAKPR_H
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
/** @addtogroup Peripherals_Library Standard Peripheral Library
|
||||
@{
|
||||
*/
|
||||
@@ -125,7 +139,7 @@ uint8_t BAKPR_ReadIntFlag(void);
|
||||
void BAKPR_ClearIntFlag(void);
|
||||
|
||||
/**@} end of group BAKPR_Fuctions*/
|
||||
/**@} end of group BAKPR_Driver */
|
||||
/**@} end of group BAKPR_Driver*/
|
||||
/**@} end of group Peripherals_Library*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
@@ -1,23 +1,37 @@
|
||||
/*!
|
||||
* @file apm32f10x_can.h
|
||||
* @file apm32f10x_can.h
|
||||
*
|
||||
* @brief This file contains all the functions prototypes for the CAN firmware library
|
||||
* @brief This file contains all the functions prototypes for the CAN firmware library
|
||||
*
|
||||
* @version V1.0.1
|
||||
* @version V1.0.2
|
||||
*
|
||||
* @date 2021-03-23
|
||||
* @date 2022-01-05
|
||||
*
|
||||
* @attention
|
||||
*
|
||||
* Copyright (C) 2020-2022 Geehy Semiconductor
|
||||
*
|
||||
* You may not use this file except in compliance with the
|
||||
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
|
||||
*
|
||||
* The program is only for reference, which is distributed in the hope
|
||||
* that it will be usefull and instructional for customers to develop
|
||||
* their software. Unless required by applicable law or agreed to in
|
||||
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
|
||||
* and limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __APM32F10X_CAN_H
|
||||
#define __APM32F10X_CAN_H
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
/** @addtogroup Peripherals_Library Standard Peripheral Library
|
||||
@{
|
||||
*/
|
||||
@@ -35,10 +49,10 @@ extern "C" {
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CAN_MODE_NORMAL = ((uint8_t)00), //!< normal mode
|
||||
CAN_MODE_LOOPBACK = ((uint8_t)01), //!< loopback mode
|
||||
CAN_MODE_SILENT = ((uint8_t)02), //!< silent mode
|
||||
CAN_MODE_SILENT_LOOPBACK = ((uint8_t)03), //!< loopback combined with silent mode
|
||||
CAN_MODE_NORMAL = ((uint8_t)0x00), //!< normal mode
|
||||
CAN_MODE_LOOPBACK = ((uint8_t)0x01), //!< loopback mode
|
||||
CAN_MODE_SILENT = ((uint8_t)0x02), //!< silent mode
|
||||
CAN_MODE_SILENT_LOOPBACK = ((uint8_t)0x03) //!< loopback combined with silent mode
|
||||
} CAN_MODE_T;
|
||||
|
||||
/**
|
||||
@@ -46,10 +60,10 @@ typedef enum
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CAN_SJW_1 = ((uint8_t)00), //!< 1 time quantum
|
||||
CAN_SJW_2 = ((uint8_t)01), //!< 2 time quantum
|
||||
CAN_SJW_3 = ((uint8_t)02), //!< 3 time quantum
|
||||
CAN_SJW_4 = ((uint8_t)03) //!< 4 time quantum
|
||||
CAN_SJW_1 = ((uint8_t)0x00), //!< 1 time quantum
|
||||
CAN_SJW_2 = ((uint8_t)0x01), //!< 2 time quantum
|
||||
CAN_SJW_3 = ((uint8_t)0x02), //!< 3 time quantum
|
||||
CAN_SJW_4 = ((uint8_t)0x03) //!< 4 time quantum
|
||||
} CAN_SJW_T;
|
||||
|
||||
/**
|
||||
@@ -87,7 +101,7 @@ typedef enum
|
||||
CAN_TIME_SEGMENT2_5 = (uint8_t)0x04, //!< 5 time quanta
|
||||
CAN_TIME_SEGMENT2_6 = (uint8_t)0x05, //!< 6 time quanta
|
||||
CAN_TIME_SEGMENT2_7 = (uint8_t)0x06, //!< 7 time quanta
|
||||
CAN_TIME_SEGMENT2_8 = (uint8_t)0x07, //!< 8 time quanta
|
||||
CAN_TIME_SEGMENT2_8 = (uint8_t)0x07 //!< 8 time quanta
|
||||
} CAN_TIME_SEGMENT2_T;
|
||||
|
||||
/**
|
||||
@@ -96,7 +110,7 @@ typedef enum
|
||||
typedef enum
|
||||
{
|
||||
CAN_FILTER_FIFO_0 = ((uint8_t)0x00), //!< filter FIFO 0
|
||||
CAN_FILTER_FIFO_1 = ((uint8_t)0x01), //!< filter FIFO 1
|
||||
CAN_FILTER_FIFO_1 = ((uint8_t)0x01) //!< filter FIFO 1
|
||||
} CAN_FILTER_FIFO_T;
|
||||
|
||||
/**
|
||||
@@ -104,8 +118,8 @@ typedef enum
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CAN_FILTER_MODE_IDMASK = ((uint8_t)00), //!< identifier/mask mode
|
||||
CAN_FILTER_MODE_IDLIST = ((uint8_t)01) //!< identifier list mode
|
||||
CAN_FILTER_MODE_IDMASK = ((uint8_t)0x00),//!< identifier/mask mode
|
||||
CAN_FILTER_MODE_IDLIST = ((uint8_t)0x01) //!< identifier list mode
|
||||
} CAN_FILTER_MODE_T;
|
||||
|
||||
/**
|
||||
@@ -114,7 +128,7 @@ typedef enum
|
||||
typedef enum
|
||||
{
|
||||
CAN_FILTER_SCALE_16BIT = ((uint8_t)0x00), //!< Two 16-bit filters
|
||||
CAN_FILTER_SCALE_32BIT = ((uint8_t)0x01), //!< One 32-bit filter
|
||||
CAN_FILTER_SCALE_32BIT = ((uint8_t)0x01) //!< One 32-bit filter
|
||||
} CAN_FILTER_SCALE_T;
|
||||
|
||||
/**
|
||||
@@ -142,7 +156,7 @@ typedef enum
|
||||
{
|
||||
CAN_TX_MAILBIX_0 = ((uint8_t)0x00), //!< Tx mailbox0
|
||||
CAN_TX_MAILBIX_1 = ((uint8_t)0x01), //!< Tx mailbox1
|
||||
CAN_TX_MAILBIX_2 = ((uint8_t)0x02), //!< Tx mailbox2
|
||||
CAN_TX_MAILBIX_2 = ((uint8_t)0x02) //!< Tx mailbox2
|
||||
} CAN_TX_MAILBIX_T;
|
||||
|
||||
/**
|
||||
@@ -151,7 +165,7 @@ typedef enum
|
||||
typedef enum
|
||||
{
|
||||
CAN_RX_FIFO_0 = ((uint8_t)0x00), //!< receive FIFO 0
|
||||
CAN_RX_FIFO_1 = ((uint8_t)0x01), //!< receive FIFO 1
|
||||
CAN_RX_FIFO_1 = ((uint8_t)0x01) //!< receive FIFO 1
|
||||
} CAN_RX_FIFO_T;
|
||||
|
||||
/**
|
||||
@@ -159,9 +173,9 @@ typedef enum
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CAN_OPERATING_MODE_INIT = ((uint8_t)00), //!< Initialization mode
|
||||
CAN_OPERATING_MODE_NORMAL = ((uint8_t)01), //!< Normal mode
|
||||
CAN_OPERATING_MODE_SLEEP = ((uint8_t)02), //!< sleep mode
|
||||
CAN_OPERATING_MODE_INIT = ((uint8_t)0x00), //!< Initialization mode
|
||||
CAN_OPERATING_MODE_NORMAL = ((uint8_t)0x01), //!< Normal mode
|
||||
CAN_OPERATING_MODE_SLEEP = ((uint8_t)0x02) //!< sleep mode
|
||||
} CAN_OPERATING_MODE_T;
|
||||
|
||||
/**
|
||||
@@ -223,7 +237,6 @@ typedef enum
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t timeTrigComMode; //!< Enable or disable the time triggered communication mode.
|
||||
uint8_t autoBusOffManage; //!< Enable or disable the automatic bus-off management.
|
||||
uint8_t autoWakeUpMode; //!< Enable or disable the automatic wake-up mode.
|
||||
uint8_t nonAutoRetran; //!< Enable or disable the non-automatic retransmission mode.
|
||||
@@ -249,7 +262,7 @@ typedef struct
|
||||
CAN_RTXR_T remoteTxReq;
|
||||
uint8_t dataLengthCode;//!< Specifies the data length code. It can be 0 to 8.
|
||||
uint8_t data[8]; //!< Specifies the data to be transmitted. It can be 0 to 0xFF.
|
||||
} CAN_TX_MESSAGE_T;
|
||||
} CAN_TxMessage_T;
|
||||
|
||||
/**
|
||||
* @brief CAN Rx message structure definition
|
||||
@@ -263,7 +276,7 @@ typedef struct
|
||||
uint8_t dataLengthCode; //!< Specifies the data length code. It can be 0 to 8.
|
||||
uint8_t data[8]; //!< Specifies the data to be transmitted. It can be 0 to 0xFF.
|
||||
uint8_t filterMatchIndex;//!< Specifies the filter match index. It can be 0 to 0xFF.
|
||||
} CAN_RX_MESSAGE_T;
|
||||
} CAN_RxMessage_T;
|
||||
|
||||
/**
|
||||
* @brief CAN filter config structure definition
|
||||
@@ -279,7 +292,7 @@ typedef struct
|
||||
CAN_FILTER_FIFO_T filterFIFO;
|
||||
CAN_FILTER_MODE_T filterMode;
|
||||
CAN_FILTER_SCALE_T filterScale;
|
||||
} CAN_FILTER_CONFIG_T;
|
||||
} CAN_FilterConfig_T;
|
||||
|
||||
/**@} end of group CAN_Structure*/
|
||||
|
||||
@@ -289,45 +302,44 @@ typedef struct
|
||||
*/
|
||||
|
||||
/** CAN reset and configuration */
|
||||
void CAN_Reset(CAN_T* can);
|
||||
uint8_t CAN_Config(CAN_T* can, CAN_Config_T* canConfig);
|
||||
void CAN_ConfigFilter(CAN_T* can, CAN_FILTER_CONFIG_T* filterConfig);
|
||||
void CAN_ConfigStructInit(CAN_Config_T* canConfig);
|
||||
void CAN_EnableDBGFreeze(CAN_T* can);
|
||||
void CAN_DisableDBGFreeze(CAN_T* can);
|
||||
void CAN_EnableTTCComMode(CAN_T* can);
|
||||
void CAN_DisableTTCComMode(CAN_T* can);
|
||||
void CAN_Reset(CAN_T *can);
|
||||
uint8_t CAN_Config(CAN_T *can, CAN_Config_T *canConfig);
|
||||
void CAN_ConfigFilter(CAN_T *can, CAN_FilterConfig_T *filterConfig);
|
||||
void CAN_ConfigStructInit(CAN_Config_T *canConfig);
|
||||
void CAN_EnableDBGFreeze(CAN_T *can);
|
||||
void CAN_DisableDBGFreeze(CAN_T *can);
|
||||
void CAN_SlaveStartBank(CAN_T *can, uint8_t bankNum);
|
||||
|
||||
/** CAN frames transmit */
|
||||
uint8_t CAN_TxMessage(CAN_T* can, CAN_TX_MESSAGE_T* TxMessage);
|
||||
uint8_t CAN_TxMessageStatus(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox);
|
||||
void CAN_CancelTxMailbox(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox);
|
||||
uint8_t CAN_TxMessage(CAN_T *can, CAN_TxMessage_T *TxMessage);
|
||||
uint8_t CAN_TxMessageStatus(CAN_T *can, CAN_TX_MAILBIX_T TxMailbox);
|
||||
void CAN_CancelTxMailbox(CAN_T *can, CAN_TX_MAILBIX_T TxMailbox);
|
||||
|
||||
/** CAN frames receive */
|
||||
void CAN_RxMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber, CAN_RX_MESSAGE_T* RxMessage);
|
||||
void CAN_ReleaseFIFO(CAN_T* can, CAN_RX_FIFO_T FIFONumber);
|
||||
uint8_t CAN_PendingMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber);
|
||||
void CAN_RxMessage(CAN_T *can, CAN_RX_FIFO_T FIFONumber, CAN_RxMessage_T *RxMessage);
|
||||
void CAN_ReleaseFIFO(CAN_T *can, CAN_RX_FIFO_T FIFONumber);
|
||||
uint8_t CAN_PendingMessage(CAN_T *can, CAN_RX_FIFO_T FIFONumber);
|
||||
|
||||
/** CAN operation modes */
|
||||
uint8_t CAN_OperatingMode(CAN_T* can, CAN_OPERATING_MODE_T operatingMode);
|
||||
uint8_t CAN_SleepMode(CAN_T* can);
|
||||
uint8_t CAN_WakeUpMode(CAN_T* can);
|
||||
uint8_t CAN_OperatingMode(CAN_T *can, CAN_OPERATING_MODE_T operatingMode);
|
||||
uint8_t CAN_SleepMode(CAN_T *can);
|
||||
uint8_t CAN_WakeUpMode(CAN_T *can);
|
||||
|
||||
/** CAN bus error management */
|
||||
uint8_t CAN_ReadLastErrorCode(CAN_T* can);
|
||||
uint8_t CAN_ReadRxErrorCounter(CAN_T* can);
|
||||
uint8_t CAN_ReadLSBTxErrorCounter(CAN_T* can);
|
||||
uint8_t CAN_ReadLastErrorCode(CAN_T *can);
|
||||
uint8_t CAN_ReadRxErrorCounter(CAN_T *can);
|
||||
uint8_t CAN_ReadLSBTxErrorCounter(CAN_T *can);
|
||||
|
||||
/** CAN interrupt and flag */
|
||||
void CAN_EnableInterrupt(CAN_T* can, uint32_t interrupt);
|
||||
void CAN_DisableInterrupt(CAN_T* can, uint32_t interrupt);
|
||||
uint8_t CAN_ReadStatusFlag(CAN_T* can, CAN_FLAG_T flag);
|
||||
void CAN_ClearStatusFlag(CAN_T* can, CAN_FLAG_T flag);
|
||||
uint8_t CAN_ReadIntFlag(CAN_T* can, CAN_INT_T flag);
|
||||
void CAN_ClearIntFlag(CAN_T* can, CAN_INT_T flag);
|
||||
void CAN_EnableInterrupt(CAN_T *can, uint32_t interrupt);
|
||||
void CAN_DisableInterrupt(CAN_T *can, uint32_t interrupt);
|
||||
uint8_t CAN_ReadStatusFlag(CAN_T *can, CAN_FLAG_T flag);
|
||||
void CAN_ClearStatusFlag(CAN_T *can, CAN_FLAG_T flag);
|
||||
uint8_t CAN_ReadIntFlag(CAN_T *can, CAN_INT_T flag);
|
||||
void CAN_ClearIntFlag(CAN_T *can, CAN_INT_T flag);
|
||||
|
||||
/**@} end of group CAN_Fuctions*/
|
||||
/**@} end of group CAN_Driver */
|
||||
/**@} end of group CAN_Driver*/
|
||||
/**@} end of group Peripherals_Library*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
@@ -1,23 +1,37 @@
|
||||
/*!
|
||||
* @file apm32f10x_crc.h
|
||||
* @file apm32f10x_crc.h
|
||||
*
|
||||
* @brief This file contains all the functions prototypes for the CRC firmware library
|
||||
* @brief This file contains all the functions prototypes for the CRC firmware library
|
||||
*
|
||||
* @version V1.0.1
|
||||
* @version V1.0.2
|
||||
*
|
||||
* @date 2021-03-23
|
||||
* @date 2022-01-05
|
||||
*
|
||||
* @attention
|
||||
*
|
||||
* Copyright (C) 2020-2022 Geehy Semiconductor
|
||||
*
|
||||
* You may not use this file except in compliance with the
|
||||
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
|
||||
*
|
||||
* The program is only for reference, which is distributed in the hope
|
||||
* that it will be usefull and instructional for customers to develop
|
||||
* their software. Unless required by applicable law or agreed to in
|
||||
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
|
||||
* and limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __APM32F10X_CRC_H
|
||||
#define __APM32F10X_CRC_H
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
/** @addtogroup Peripherals_Library Standard Peripheral Library
|
||||
@{
|
||||
*/
|
||||
@@ -41,7 +55,7 @@ void CRC_WriteIDRegister(uint8_t inData);
|
||||
uint8_t CRC_ReadIDRegister(void);
|
||||
|
||||
/**@} end of group CRC_Fuctions*/
|
||||
/**@} end of group CRC_Driver */
|
||||
/**@} end of group CRC_Driver*/
|
||||
/**@} end of group Peripherals_Library*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
@@ -3,21 +3,35 @@
|
||||
*
|
||||
* @brief This file contains all the functions prototypes for the DAC firmware library
|
||||
*
|
||||
* @version V1.0.1
|
||||
* @version V1.0.2
|
||||
*
|
||||
* @date 2021-03-23
|
||||
* @date 2022-01-05
|
||||
*
|
||||
* @attention
|
||||
*
|
||||
* Copyright (C) 2020-2022 Geehy Semiconductor
|
||||
*
|
||||
* You may not use this file except in compliance with the
|
||||
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
|
||||
*
|
||||
* The program is only for reference, which is distributed in the hope
|
||||
* that it will be usefull and instructional for customers to develop
|
||||
* their software. Unless required by applicable law or agreed to in
|
||||
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
|
||||
* and limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __APM32F10X_DAC_H
|
||||
#define __APM32F10X_DAC_H
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
/** @addtogroup Peripherals_Library Standard Peripheral Library
|
||||
@{
|
||||
*/
|
||||
@@ -37,7 +51,7 @@ typedef enum
|
||||
{
|
||||
DAC_CHANNEL_1 = 0x00000000,
|
||||
DAC_CHANNEL_2 = 0x00000010
|
||||
}DAC_CHANNEL_T;
|
||||
} DAC_CHANNEL_T;
|
||||
|
||||
/**
|
||||
* @brief DAC trigger selection
|
||||
@@ -53,7 +67,7 @@ typedef enum
|
||||
DAC_TRIGGER_TMR4_TRGO = 0x0000002C,
|
||||
DAC_TRIGGER_EINT9 = 0x00000034,
|
||||
DAC_TRIGGER_SOFT = 0x0000003C
|
||||
}DAC_TRIGGER_T;
|
||||
} DAC_TRIGGER_T;
|
||||
|
||||
/**
|
||||
* @brief DAC wave generation
|
||||
@@ -63,7 +77,7 @@ typedef enum
|
||||
DAC_WAVE_GENERATION_NONE = 0x00000000,
|
||||
DAC_WAVE_GENERATION_NOISE = 0x00000040,
|
||||
DAC_WAVE_GENERATION_TRIANGLE = 0x00000080
|
||||
}DAC_WAVE_GENERATION_T;
|
||||
} DAC_WAVE_GENERATION_T;
|
||||
|
||||
/**
|
||||
* @brief DAC channelx mask/amplitude selector
|
||||
@@ -71,31 +85,31 @@ typedef enum
|
||||
typedef enum
|
||||
{
|
||||
DAC_LFSR_MASK_BIT11_1 = 0x00000000, //!< Mask bit[11:1] of LFSR for noise wave generation
|
||||
DAC_LFSR_MASK_BIT11_2 = 0x00001000, //!< Mask bit[11:2] of LFSR for noise wave generation
|
||||
DAC_LFSR_MASK_BIT11_3 = 0x00002000, //!< Mask bit[11:3] of LFSR for noise wave generation
|
||||
DAC_LFSR_MASK_BIT11_4 = 0x00003000, //!< Mask bit[11:4] of LFSR for noise wave generation
|
||||
DAC_LFSR_MASK_BIT11_5 = 0x00004000, //!< Mask bit[11:5] of LFSR for noise wave generation
|
||||
DAC_LFSR_MASK_BIT11_6 = 0x00005000, //!< Mask bit[11:6] of LFSR for noise wave generation
|
||||
DAC_LFSR_MASK_BIT11_7 = 0x00006000, //!< Mask bit[11:7] of LFSR for noise wave generation
|
||||
DAC_LFSR_MASK_BIT11_8 = 0x00007000, //!< Mask bit[11:8] of LFSR for noise wave generation
|
||||
DAC_LFSR_MASK_BIT11_9 = 0x00008000, //!< Mask bit[11:9] of LFSR for noise wave generation
|
||||
DAC_LFSR_MASK_BIT11_10 = 0x00009000, //!< Mask bit[11:10] of LFSR for noise wave generation
|
||||
DAC_LFSR_MASK_BIT11 = 0x0000A000, //!< Mask bit11 of LFSR for noise wave generation
|
||||
DAC_LFSR_MASK_NONE = 0x0000B000, //!< Mask none bit of LFSR for noise wave generation
|
||||
DAC_LFSR_MASK_BIT11_2 = 0x00000100, //!< Mask bit[11:2] of LFSR for noise wave generation
|
||||
DAC_LFSR_MASK_BIT11_3 = 0x00000200, //!< Mask bit[11:3] of LFSR for noise wave generation
|
||||
DAC_LFSR_MASK_BIT11_4 = 0x00000300, //!< Mask bit[11:4] of LFSR for noise wave generation
|
||||
DAC_LFSR_MASK_BIT11_5 = 0x00000400, //!< Mask bit[11:5] of LFSR for noise wave generation
|
||||
DAC_LFSR_MASK_BIT11_6 = 0x00000500, //!< Mask bit[11:6] of LFSR for noise wave generation
|
||||
DAC_LFSR_MASK_BIT11_7 = 0x00000600, //!< Mask bit[11:7] of LFSR for noise wave generation
|
||||
DAC_LFSR_MASK_BIT11_8 = 0x00000700, //!< Mask bit[11:8] of LFSR for noise wave generation
|
||||
DAC_LFSR_MASK_BIT11_9 = 0x00000800, //!< Mask bit[11:9] of LFSR for noise wave generation
|
||||
DAC_LFSR_MASK_BIT11_10 = 0x00000900, //!< Mask bit[11:10] of LFSR for noise wave generation
|
||||
DAC_LFSR_MASK_BIT11 = 0x00000A00, //!< Mask bit11 of LFSR for noise wave generation
|
||||
DAC_LFSR_MASK_NONE = 0x00000B00, //!< Mask none bit of LFSR for noise wave generation
|
||||
|
||||
DAC_TRIANGLE_AMPLITUDE_1 = 0x00000000, //!< Triangle amplitude equal to 1
|
||||
DAC_TRIANGLE_AMPLITUDE_3 = 0x00001000, //!< Triangle amplitude equal to 3
|
||||
DAC_TRIANGLE_AMPLITUDE_7 = 0x00002000, //!< Triangle amplitude equal to 7
|
||||
DAC_TRIANGLE_AMPLITUDE_15 = 0x00003000, //!< Triangle amplitude equal to 15
|
||||
DAC_TRIANGLE_AMPLITUDE_31 = 0x00004000, //!< Triangle amplitude equal to 31
|
||||
DAC_TRIANGLE_AMPLITUDE_63 = 0x00005000, //!< Triangle amplitude equal to 63
|
||||
DAC_TRIANGLE_AMPLITUDE_127 = 0x00006000, //!< Triangle amplitude equal to 127
|
||||
DAC_TRIANGLE_AMPLITUDE_255 = 0x00007000, //!< Triangle amplitude equal to 255
|
||||
DAC_TRIANGLE_AMPLITUDE_511 = 0x00008000, //!< Triangle amplitude equal to 511
|
||||
DAC_TRIANGLE_AMPLITUDE_1023 = 0x00009000, //!< Triangle amplitude equal to 1023
|
||||
DAC_TRIANGLE_AMPLITUDE_2047 = 0x0000A000, //!< Triangle amplitude equal to 2047
|
||||
DAC_TRIANGLE_AMPLITUDE_4095 = 0x0000B000 //!< Triangle amplitude equal to 4095
|
||||
}DAC_MASK_AMPLITUDE_SEL_T;
|
||||
DAC_TRIANGLE_AMPLITUDE_3 = 0x00000100, //!< Triangle amplitude equal to 3
|
||||
DAC_TRIANGLE_AMPLITUDE_7 = 0x00000200, //!< Triangle amplitude equal to 7
|
||||
DAC_TRIANGLE_AMPLITUDE_15 = 0x00000300, //!< Triangle amplitude equal to 15
|
||||
DAC_TRIANGLE_AMPLITUDE_31 = 0x00000400, //!< Triangle amplitude equal to 31
|
||||
DAC_TRIANGLE_AMPLITUDE_63 = 0x00000500, //!< Triangle amplitude equal to 63
|
||||
DAC_TRIANGLE_AMPLITUDE_127 = 0x00000600, //!< Triangle amplitude equal to 127
|
||||
DAC_TRIANGLE_AMPLITUDE_255 = 0x00000700, //!< Triangle amplitude equal to 255
|
||||
DAC_TRIANGLE_AMPLITUDE_511 = 0x00000800, //!< Triangle amplitude equal to 511
|
||||
DAC_TRIANGLE_AMPLITUDE_1023 = 0x00000900, //!< Triangle amplitude equal to 1023
|
||||
DAC_TRIANGLE_AMPLITUDE_2047 = 0x00000A00, //!< Triangle amplitude equal to 2047
|
||||
DAC_TRIANGLE_AMPLITUDE_4095 = 0x00000B00 //!< Triangle amplitude equal to 4095
|
||||
} DAC_MASK_AMPLITUDE_SEL_T;
|
||||
|
||||
/**
|
||||
* @brief DAC output buffer
|
||||
@@ -104,7 +118,7 @@ typedef enum
|
||||
{
|
||||
DAC_OUTPUT_BUFFER_ENBALE = 0x00000000,
|
||||
DAC_OUTPUT_BUFFER_DISABLE = 0x00000002
|
||||
}DAC_OUTPUT_BUFFER_T;
|
||||
} DAC_OUTPUT_BUFFER_T;
|
||||
|
||||
/**
|
||||
* @brief DAC data align
|
||||
@@ -114,7 +128,7 @@ typedef enum
|
||||
DAC_ALIGN_12BIT_R = 0x00000000,
|
||||
DAC_ALIGN_12BIT_L = 0x00000004,
|
||||
DAC_ALIGN_8BIT_R = 0x00000008
|
||||
}DAC_ALIGN_T;
|
||||
} DAC_ALIGN_T;
|
||||
|
||||
/**@} end of group DAC_Enumerations*/
|
||||
|
||||
@@ -132,7 +146,7 @@ typedef struct
|
||||
DAC_OUTPUT_BUFFER_T outputBuffer;
|
||||
DAC_WAVE_GENERATION_T waveGeneration;
|
||||
DAC_MASK_AMPLITUDE_SEL_T maskAmplitudeSelect;
|
||||
}DAC_ConfigStruct_T;
|
||||
} DAC_Config_T;
|
||||
|
||||
/**@} end of group DAC_Structure*/
|
||||
|
||||
@@ -143,8 +157,8 @@ typedef struct
|
||||
|
||||
/** DAC Reset and Configuration */
|
||||
void DAC_Reset(void);
|
||||
void DAC_Config(uint32_t channel, DAC_ConfigStruct_T* configStruct);
|
||||
void DAC_ConfigStructInit(DAC_ConfigStruct_T* configStruct);
|
||||
void DAC_Config(uint32_t channel, DAC_Config_T *dacConfig);
|
||||
void DAC_ConfigStructInit(DAC_Config_T *dacConfig);
|
||||
void DAC_Enable(DAC_CHANNEL_T channel);
|
||||
void DAC_Disable(DAC_CHANNEL_T channel);
|
||||
|
||||
@@ -171,7 +185,7 @@ void DAC_ConfigDualChannelData(DAC_ALIGN_T align, uint16_t data2, uint16_t data1
|
||||
uint16_t DAC_ReadDataOutputValue(DAC_CHANNEL_T channel);
|
||||
|
||||
/**@} end of group DAC_Fuctions*/
|
||||
/**@} end of group DAC_Driver */
|
||||
/**@} end of group DAC_Driver*/
|
||||
/**@} end of group Peripherals_Library*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
@@ -3,21 +3,35 @@
|
||||
*
|
||||
* @brief This file contains all the functions prototypes for the DBUGMCU firmware library
|
||||
*
|
||||
* @version V1.0.1
|
||||
* @version V1.0.2
|
||||
*
|
||||
* @date 2021-03-23
|
||||
* @date 2022-01-05
|
||||
*
|
||||
* @attention
|
||||
*
|
||||
* Copyright (C) 2020-2022 Geehy Semiconductor
|
||||
*
|
||||
* You may not use this file except in compliance with the
|
||||
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
|
||||
*
|
||||
* The program is only for reference, which is distributed in the hope
|
||||
* that it will be usefull and instructional for customers to develop
|
||||
* their software. Unless required by applicable law or agreed to in
|
||||
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
|
||||
* and limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __APM32F10X_DBGMCU_H
|
||||
#define __APM32F10X_DBGMCU_H
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
/** @addtogroup Peripherals_Library Standard Peripheral Library
|
||||
@{
|
||||
*/
|
||||
@@ -73,7 +87,7 @@ void DBGMCU_Enable(uint32_t periph);
|
||||
void DBGMCU_Disable(uint32_t periph);
|
||||
|
||||
/**@} end of group DBGMCU_Fuctions*/
|
||||
/**@} end of group DBGMCU_Driver */
|
||||
/**@} end of group DBGMCU_Driver*/
|
||||
/**@} end of group Peripherals_Library*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
@@ -1,23 +1,37 @@
|
||||
/*!
|
||||
* @file apm32f10x_dma.h
|
||||
* @file apm32f10x_dma.h
|
||||
*
|
||||
* @brief This file contains all the functions prototypes for the DMA firmware library
|
||||
* @brief This file contains all the functions prototypes for the DMA firmware library
|
||||
*
|
||||
* @version V1.0.1
|
||||
* @version V1.0.2
|
||||
*
|
||||
* @date 2021-03-23
|
||||
* @date 2022-01-05
|
||||
*
|
||||
* @attention
|
||||
*
|
||||
* Copyright (C) 2020-2022 Geehy Semiconductor
|
||||
*
|
||||
* You may not use this file except in compliance with the
|
||||
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
|
||||
*
|
||||
* The program is only for reference, which is distributed in the hope
|
||||
* that it will be usefull and instructional for customers to develop
|
||||
* their software. Unless required by applicable law or agreed to in
|
||||
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
|
||||
* and limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __APM32F10X_DMA_H
|
||||
#define __APM32F10X_DMA_H
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
/** @addtogroup Peripherals_Library Standard Peripheral Library
|
||||
@{
|
||||
*/
|
||||
@@ -173,7 +187,7 @@ typedef enum
|
||||
} DMA_FLAG_T;
|
||||
|
||||
/**
|
||||
* @brief DMA Flag
|
||||
* @brief DMA Interrupt Flag
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
@@ -262,8 +276,8 @@ typedef struct
|
||||
|
||||
/** Reset and configuration */
|
||||
void DMA_Reset(DMA_Channel_T *channel);
|
||||
void DMA_Config(DMA_Channel_T* channel, DMA_Config_T* dmaConfig);
|
||||
void DMA_ConfigStructInit( DMA_Config_T* dmaConfig);
|
||||
void DMA_Config(DMA_Channel_T *channel, DMA_Config_T *dmaConfig);
|
||||
void DMA_ConfigStructInit(DMA_Config_T *dmaConfig);
|
||||
void DMA_Enable(DMA_Channel_T *channel);
|
||||
void DMA_Disable(DMA_Channel_T *channel);
|
||||
|
||||
@@ -280,7 +294,7 @@ uint8_t DMA_ReadIntFlag(DMA_INT_FLAG_T flag);
|
||||
void DMA_ClearIntFlag(uint32_t flag);
|
||||
|
||||
/**@} end of group DMA_Fuctions*/
|
||||
/**@} end of group DMA_Driver */
|
||||
/**@} end of group DMA_Driver*/
|
||||
/**@} end of group Peripherals_Library*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
@@ -3,20 +3,35 @@
|
||||
*
|
||||
* @brief This file contains all the prototypes,enumeration and macros for the DMC peripheral
|
||||
*
|
||||
* @version V1.0.1
|
||||
* @version V1.0.2
|
||||
*
|
||||
* @date 2021-03-23
|
||||
* @date 2022-01-05
|
||||
*
|
||||
* @attention
|
||||
*
|
||||
* Copyright (C) 2020-2022 Geehy Semiconductor
|
||||
*
|
||||
* You may not use this file except in compliance with the
|
||||
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
|
||||
*
|
||||
* The program is only for reference, which is distributed in the hope
|
||||
* that it will be usefull and instructional for customers to develop
|
||||
* their software. Unless required by applicable law or agreed to in
|
||||
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
|
||||
* and limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __APM32F10X_DMC_H
|
||||
#define __APM32F10X_DMC_H
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
/** @addtogroup Peripherals_Library Standard Peripheral Library
|
||||
@{
|
||||
*/
|
||||
@@ -37,7 +52,7 @@ typedef enum
|
||||
{
|
||||
DMC_BANK_WIDTH_1,
|
||||
DMC_BANK_WIDTH_2
|
||||
}DMC_BANK_WIDTH_T;
|
||||
} DMC_BANK_WIDTH_T;
|
||||
|
||||
/**
|
||||
* @brief Row Address Width
|
||||
@@ -50,7 +65,7 @@ typedef enum
|
||||
DMC_ROW_WIDTH_14,
|
||||
DMC_ROW_WIDTH_15,
|
||||
DMC_ROW_WIDTH_16
|
||||
}DMC_ROW_WIDTH_T;
|
||||
} DMC_ROW_WIDTH_T;
|
||||
|
||||
/**
|
||||
* @brief Column Address Width
|
||||
@@ -65,7 +80,7 @@ typedef enum
|
||||
DMC_COL_WIDTH_13,
|
||||
DMC_COL_WIDTH_14,
|
||||
DMC_COL_WIDTH_15
|
||||
}DMC_COL_WIDTH_T;
|
||||
} DMC_COL_WIDTH_T;
|
||||
|
||||
/**
|
||||
* @brief CAS Latency Select
|
||||
@@ -76,7 +91,7 @@ typedef enum
|
||||
DMC_CAS_LATENCY_2,
|
||||
DMC_CAS_LATENCY_3,
|
||||
DMC_CAS_LATENCY_4
|
||||
}DMC_CAS_LATENCY_T;
|
||||
} DMC_CAS_LATENCY_T;
|
||||
|
||||
/**
|
||||
* @brief RAS Minimun Time Select
|
||||
@@ -99,7 +114,7 @@ typedef enum
|
||||
DMC_RAS_MINIMUM_14,
|
||||
DMC_RAS_MINIMUM_15,
|
||||
DMC_RAS_MINIMUM_16
|
||||
}DMC_RAS_MINIMUM_T;
|
||||
} DMC_RAS_MINIMUM_T;
|
||||
|
||||
/**
|
||||
* @brief RAS To CAS Delay Time Select
|
||||
@@ -114,7 +129,7 @@ typedef enum
|
||||
DMC_DELAY_TIME_6,
|
||||
DMC_DELAY_TIME_7,
|
||||
DMC_DELAY_TIME_8
|
||||
}DMC_DELAY_TIME_T;
|
||||
} DMC_DELAY_TIME_T;
|
||||
|
||||
/**
|
||||
* @brief Precharge Period Select
|
||||
@@ -129,10 +144,10 @@ typedef enum
|
||||
DMC_PRECHARGE_6,
|
||||
DMC_PRECHARGE_7,
|
||||
DMC_PRECHARGE_8
|
||||
}DMC_PRECHARGE_T;
|
||||
} DMC_PRECHARGE_T;
|
||||
|
||||
/**
|
||||
* @brief Last Data Next Precharge For Write Time Select
|
||||
* @brief Last Data Next Precharge For Write Time Select
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
@@ -140,7 +155,7 @@ typedef enum
|
||||
DMC_NEXT_PRECHARGE_2,
|
||||
DMC_NEXT_PRECHARGE_3,
|
||||
DMC_NEXT_PRECHARGE_4
|
||||
}DMC_NEXT_PRECHARGE_T;
|
||||
} DMC_NEXT_PRECHARGE_T;
|
||||
|
||||
/**
|
||||
* @brief Auto-Refresh Period Select
|
||||
@@ -163,7 +178,7 @@ typedef enum
|
||||
DMC_AUTO_REFRESH_14,
|
||||
DMC_AUTO_REFRESH_15,
|
||||
DMC_AUTO_REFRESH_16,
|
||||
}DMC_AUTO_REFRESH_T;
|
||||
} DMC_AUTO_REFRESH_T;
|
||||
|
||||
/**
|
||||
* @brief Active-to-active Command Period Select
|
||||
@@ -186,7 +201,7 @@ typedef enum
|
||||
DMC_ATA_CMD_14,
|
||||
DMC_ATA_CMD_15,
|
||||
DMC_ATA_CMD_16,
|
||||
}DMC_ATA_CMD_T;
|
||||
} DMC_ATA_CMD_T;
|
||||
|
||||
/**
|
||||
* @brief Clock PHASE
|
||||
@@ -195,7 +210,7 @@ typedef enum
|
||||
{
|
||||
DMC_CLK_PHASE_NORMAL,
|
||||
DMC_CLK_PHASE_REVERSE
|
||||
}DMC_CLK_PHASE_T;
|
||||
} DMC_CLK_PHASE_T;
|
||||
|
||||
/**
|
||||
* @brief DMC Memory Size
|
||||
@@ -216,10 +231,10 @@ typedef enum
|
||||
DMC_MEMORY_SIZE_64MB,
|
||||
DMC_MEMORY_SIZE_128MB,
|
||||
DMC_MEMORY_SIZE_256MB,
|
||||
}DMC_MEMORY_SIZE_T;
|
||||
} DMC_MEMORY_SIZE_T;
|
||||
|
||||
/**
|
||||
* @brief Open Banks Of Number
|
||||
* @brief Open Banks Of Number
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
@@ -239,7 +254,7 @@ typedef enum
|
||||
DMC_BANK_NUMBER_14,
|
||||
DMC_BANK_NUMBER_15,
|
||||
DMC_BANK_NUMBER_16,
|
||||
}DMC_BANK_NUMBER_T;
|
||||
} DMC_BANK_NUMBER_T;
|
||||
|
||||
/**
|
||||
* @brief Full refresh type
|
||||
@@ -248,7 +263,7 @@ typedef enum
|
||||
{
|
||||
DMC_REFRESH_ROW_ONE, //!< Refresh one row
|
||||
DMC_REFRESH_ROW_ALL, //!< Refresh all row
|
||||
}DMC_REFRESH_T;
|
||||
} DMC_REFRESH_T;
|
||||
|
||||
/**
|
||||
* @brief Precharge type
|
||||
@@ -257,8 +272,16 @@ typedef enum
|
||||
{
|
||||
DMC_PRECHARGE_IM, //!< Immediate precharge
|
||||
DMC_PRECHARGE_DELAY, //!< Delayed precharge
|
||||
}DMC_PRECHARE_T;
|
||||
} DMC_PRECHARE_T;
|
||||
|
||||
/**
|
||||
* @brief WRAP Burst Type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DMC_WRAPB_4,
|
||||
DMC_WRAPB_8,
|
||||
} DMC_WRPB_T;
|
||||
|
||||
/**@} end of group DMC_Enumerations*/
|
||||
|
||||
@@ -281,7 +304,7 @@ typedef struct
|
||||
uint32_t tCMD : 4; //!< DMC_ATA_CMD_T
|
||||
uint32_t tXSR : 9; //!< auto-refresh commands, can be 0x000 to 0x1FF
|
||||
uint16_t tRFP : 16; //!< Refresh period, can be 0x0000 to 0xFFFF
|
||||
}DMC_TimingConfig_T;
|
||||
} DMC_TimingConfig_T;
|
||||
|
||||
/**
|
||||
* @brief Config struct definition
|
||||
@@ -294,7 +317,7 @@ typedef struct
|
||||
DMC_COL_WIDTH_T colWidth; //!< Number of col address bits
|
||||
DMC_CLK_PHASE_T clkPhase; //!< Clock phase
|
||||
DMC_TimingConfig_T timing; //!< Timing
|
||||
}DMC_Config_T;
|
||||
} DMC_Config_T;
|
||||
|
||||
/**@} end of group DMC_Structure*/
|
||||
|
||||
@@ -303,7 +326,7 @@ typedef struct
|
||||
@{
|
||||
*/
|
||||
|
||||
/** Enable / Disable */
|
||||
/** Enable / Disable */
|
||||
void DMC_Enable(void);
|
||||
void DMC_Disable(void);
|
||||
void DMC_EnableInit(void);
|
||||
@@ -327,6 +350,10 @@ void DMC_ConfigRefreshPeriod(uint16_t period);
|
||||
void DMC_EixtSlefRefreshMode(void);
|
||||
void DMC_EnterSlefRefreshMode(void);
|
||||
|
||||
/** Accelerate Module */
|
||||
void DMC_EnableAccelerateModule(void);
|
||||
void DMC_DisableAccelerateModule(void);
|
||||
|
||||
/** Config */
|
||||
void DMC_ConfigOpenBank(DMC_BANK_NUMBER_T num);
|
||||
void DMC_EnableUpdateMode(void);
|
||||
@@ -336,6 +363,7 @@ void DMC_ConfigFullRefreshAfterSR(DMC_REFRESH_T refresh);
|
||||
void DMC_ConfigPrechargeType(DMC_PRECHARE_T precharge);
|
||||
void DMC_ConfigMemorySize(DMC_MEMORY_SIZE_T memorySize);
|
||||
void DMC_ConfigClockPhase(DMC_CLK_PHASE_T clkPhase);
|
||||
void DMC_ConfigWRAPB(DMC_WRPB_T burst);
|
||||
|
||||
/** read flag */
|
||||
uint8_t DMC_ReadSelfRefreshStatus(void);
|
||||
|
||||
@@ -1,23 +1,37 @@
|
||||
/*!
|
||||
* @file apm32f10x_eint.h
|
||||
* @file apm32f10x_eint.h
|
||||
*
|
||||
* @brief This file contains all the functions prototypes for the EINT firmware library
|
||||
* @brief This file contains all the functions prototypes for the EINT firmware library
|
||||
*
|
||||
* @version V1.0.1
|
||||
* @version V1.0.2
|
||||
*
|
||||
* @date 2021-03-23
|
||||
* @date 2022-01-05
|
||||
*
|
||||
* @attention
|
||||
*
|
||||
* Copyright (C) 2020-2022 Geehy Semiconductor
|
||||
*
|
||||
* You may not use this file except in compliance with the
|
||||
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
|
||||
*
|
||||
* The program is only for reference, which is distributed in the hope
|
||||
* that it will be usefull and instructional for customers to develop
|
||||
* their software. Unless required by applicable law or agreed to in
|
||||
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
|
||||
* and limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __APM32F10X_EINT_H
|
||||
#define __APM32F10X_EINT_H
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
/** @addtogroup Peripherals_Library Standard Peripheral Library
|
||||
@{
|
||||
*/
|
||||
@@ -51,6 +65,7 @@ typedef enum
|
||||
|
||||
typedef enum
|
||||
{
|
||||
EINT_LINENONE = 0x00000, //!<No interrupt selected >
|
||||
EINT_LINE_0 = 0x00001, //!< External interrupt line 0
|
||||
EINT_LINE_1 = 0x00002, //!< External interrupt line 1
|
||||
EINT_LINE_2 = 0x00004, //!< External interrupt line 2
|
||||
@@ -99,7 +114,8 @@ typedef struct
|
||||
|
||||
/** Reset and configuration */
|
||||
void EINT_Reset(void);
|
||||
void EINT_Config( EINT_Config_T* eintConfig);
|
||||
void EINT_Config(EINT_Config_T *eintConfig);
|
||||
void EINT_ConfigStructInit(EINT_Config_T *eintConfig);
|
||||
|
||||
/** Interrupt and flag */
|
||||
void EINT_SelectSWInterrupt(uint32_t line);
|
||||
@@ -109,11 +125,11 @@ uint8_t EINT_ReadIntFlag(EINT_LINE_T line);
|
||||
void EINT_ClearIntFlag(uint32_t line);
|
||||
|
||||
/**@} end of group EINT_Fuctions*/
|
||||
/**@} end of group EINT_Driver */
|
||||
/**@} end of group EINT_Driver*/
|
||||
/**@} end of group Peripherals_Library*/
|
||||
|
||||
#ifdef __APM32F10X_cplusplus
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __EINT_H */
|
||||
#endif /* __APM32F10XEINT_H */
|
||||
|
||||
@@ -1,23 +1,37 @@
|
||||
/*!
|
||||
* @file apm32f10x_emmc.h
|
||||
* @file apm32f10x_emmc.h
|
||||
*
|
||||
* @brief This file contains all the functions prototypes for the EMMC firmware library
|
||||
* @brief This file contains all the functions prototypes for the EMMC firmware library
|
||||
*
|
||||
* @version V1.0.1
|
||||
* @version V1.0.2
|
||||
*
|
||||
* @date 2021-03-23
|
||||
* @date 2022-01-05
|
||||
*
|
||||
* @attention
|
||||
*
|
||||
* Copyright (C) 2020-2022 Geehy Semiconductor
|
||||
*
|
||||
* You may not use this file except in compliance with the
|
||||
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
|
||||
*
|
||||
* The program is only for reference, which is distributed in the hope
|
||||
* that it will be usefull and instructional for customers to develop
|
||||
* their software. Unless required by applicable law or agreed to in
|
||||
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
|
||||
* and limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __APM32F10X_EMMC_H
|
||||
#define __APM32F10X_EMMC_H
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
/** @addtogroup Peripherals_Library Standard Peripheral Library
|
||||
@{
|
||||
*/
|
||||
@@ -66,7 +80,7 @@ typedef enum
|
||||
typedef enum
|
||||
{
|
||||
EMMC_MEMORY_TYPE_SRAM = 0x00000000,
|
||||
EMMC_MEMORY_TYPE_PARAM = 0x00000004,
|
||||
EMMC_MEMORY_TYPE_PSRAM = 0x00000004,
|
||||
EMMC_MEMORY_TYPE_NOR = 0x00000008
|
||||
} EMMC_MEMORY_TYPE_T;
|
||||
|
||||
@@ -262,8 +276,8 @@ typedef struct
|
||||
EMMC_WAITE_SIGNAL_T waiteSignal;
|
||||
EMMC_EXTENDEN_MODE_T extendedMode;
|
||||
EMMC_WRITE_BURST_T writeBurst;
|
||||
EMMC_NORSRAMTimingConfig_T* readWriteTimingStruct;
|
||||
EMMC_NORSRAMTimingConfig_T* writeTimingStruct;
|
||||
EMMC_NORSRAMTimingConfig_T *readWriteTimingStruct;
|
||||
EMMC_NORSRAMTimingConfig_T *writeTimingStruct;
|
||||
} EMMC_NORSRAMConfig_T;
|
||||
|
||||
/**
|
||||
@@ -289,8 +303,8 @@ typedef struct
|
||||
EMMC_ECC_PAGE_SIZE_BYTE_T ECCPageSize;
|
||||
uint32_t TCLRSetupTime;
|
||||
uint32_t TARSetupTime;
|
||||
EMMC_NAND_PCCARDTimingConfig_T* commonSpaceTimingStruct;
|
||||
EMMC_NAND_PCCARDTimingConfig_T* attributeSpaceTimingStruct;
|
||||
EMMC_NAND_PCCARDTimingConfig_T *commonSpaceTimingStruct;
|
||||
EMMC_NAND_PCCARDTimingConfig_T *attributeSpaceTimingStruct;
|
||||
} EMMC_NANDConfig_T;
|
||||
|
||||
/**
|
||||
@@ -301,9 +315,9 @@ typedef struct
|
||||
EMMC_WAIT_FEATURE_T waitFeature;
|
||||
uint32_t TCLRSetupTime;
|
||||
uint32_t TARSetupTime;
|
||||
EMMC_NAND_PCCARDTimingConfig_T* commonSpaceTimingStruct;
|
||||
EMMC_NAND_PCCARDTimingConfig_T* attributeSpaceTimingStruct;
|
||||
EMMC_NAND_PCCARDTimingConfig_T* IOSpaceTimingStruct;
|
||||
EMMC_NAND_PCCARDTimingConfig_T *commonSpaceTimingStruct;
|
||||
EMMC_NAND_PCCARDTimingConfig_T *attributeSpaceTimingStruct;
|
||||
EMMC_NAND_PCCARDTimingConfig_T *IOSpaceTimingStruct;
|
||||
} EMMC_PCCARDConfig_T;
|
||||
|
||||
/**@} end of group EMMC_Structure*/
|
||||
@@ -318,12 +332,12 @@ void EMMC_ResetNAND(EMMC_BANK_NAND_T bank);
|
||||
void EMMC_ResetPCCard(void);
|
||||
|
||||
/** EMMC Configuration */
|
||||
void EMMC_ConfigNORSRAM(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig);
|
||||
void EMMC_ConfigNAND(EMMC_NANDConfig_T* emmcNANDConfig);
|
||||
void EMMC_ConfigPCCard(EMMC_PCCARDConfig_T* emmcPCCardConfig);
|
||||
void EMMC_ConfigNORSRAMStructInit(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig);
|
||||
void EMMC_ConfigNANDStructInit(EMMC_NANDConfig_T* emmcNANDConfig);
|
||||
void EMMC_ConfigPCCardStructInit(EMMC_PCCARDConfig_T* emmcPCCardConfig);
|
||||
void EMMC_ConfigNORSRAM(EMMC_NORSRAMConfig_T *emmcNORSRAMConfig);
|
||||
void EMMC_ConfigNAND(EMMC_NANDConfig_T *emmcNANDConfig);
|
||||
void EMMC_ConfigPCCard(EMMC_PCCARDConfig_T *emmcPCCardConfig);
|
||||
void EMMC_ConfigNORSRAMStructInit(EMMC_NORSRAMConfig_T *emmcNORSRAMConfig);
|
||||
void EMMC_ConfigNANDStructInit(EMMC_NANDConfig_T *emmcNANDConfig);
|
||||
void EMMC_ConfigPCCardStructInit(EMMC_PCCARDConfig_T *emmcPCCardConfig);
|
||||
|
||||
/** EMMC bank control */
|
||||
void EMMC_EnableNORSRAM(EMMC_BANK1_NORSRAM_T bank);
|
||||
@@ -345,7 +359,7 @@ uint8_t EMMC_ReadIntFlag(EMMC_BANK_NAND_T bank, EMMC_INT_T flag);
|
||||
void EMMC_ClearIntFlag(EMMC_BANK_NAND_T bank, uint32_t flag);
|
||||
|
||||
/**@} end of group EMMC_Fuctions*/
|
||||
/**@} end of group EMMC_Driver */
|
||||
/**@} end of group EMMC_Driver*/
|
||||
/**@} end of group Peripherals_Library*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
@@ -1,23 +1,37 @@
|
||||
/*!
|
||||
* @file apm32f10x_fmc.h
|
||||
* @file apm32f10x_fmc.h
|
||||
*
|
||||
* @brief This file contains all the functions prototypes for the FMC firmware library
|
||||
* @brief This file contains all the functions prototypes for the FMC firmware library
|
||||
*
|
||||
* @version V1.0.1
|
||||
* @version V1.0.2
|
||||
*
|
||||
* @date 2021-03-23
|
||||
* @date 2022-01-05
|
||||
*
|
||||
* @attention
|
||||
*
|
||||
* Copyright (C) 2020-2022 Geehy Semiconductor
|
||||
*
|
||||
* You may not use this file except in compliance with the
|
||||
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
|
||||
*
|
||||
* The program is only for reference, which is distributed in the hope
|
||||
* that it will be usefull and instructional for customers to develop
|
||||
* their software. Unless required by applicable law or agreed to in
|
||||
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
|
||||
* and limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __APM32F10X_FMC_H
|
||||
#define __APM32F10X_FMC_H
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
/** @addtogroup Peripherals_Library Standard Peripheral Library
|
||||
@{
|
||||
*/
|
||||
@@ -224,7 +238,7 @@ FMC_STATUS_T FMC_ProgramOptionByteData(uint32_t address, uint8_t data);
|
||||
FMC_STATUS_T FMC_EnableWriteProtection(uint32_t page);
|
||||
FMC_STATUS_T FMC_EnableReadOutProtection(void);
|
||||
FMC_STATUS_T FMC_DisableReadOutProtection(void);
|
||||
FMC_STATUS_T FMC_ConfigUserOptionByte(FMC_UserConfig_T* userConfig);
|
||||
FMC_STATUS_T FMC_ConfigUserOptionByte(FMC_UserConfig_T *userConfig);
|
||||
uint32_t FMC_ReadUserOptionByte(void);
|
||||
uint32_t FMC_ReadOptionByteWriteProtection(void);
|
||||
uint8_t FMC_GetReadProtectionStatus(void);
|
||||
@@ -234,7 +248,7 @@ uint8_t FMC_ReadPrefetchBufferStatus(void);
|
||||
void FMC_EnableInterrupt(FMC_INT_T interrupt);
|
||||
void FMC_DisableInterrupt(FMC_INT_T interrupt);
|
||||
uint8_t FMC_ReadStatusFlag(FMC_FLAG_T flag);
|
||||
void FMC_ClearStatusFlag(FMC_FLAG_T flag);
|
||||
void FMC_ClearStatusFlag(uint32_t flag);
|
||||
|
||||
/** Status management */
|
||||
FMC_STATUS_T FMC_ReadStatus(void);
|
||||
|
||||
@@ -1,23 +1,37 @@
|
||||
/*!
|
||||
* @file apm32f10x_gpio.h
|
||||
* @file apm32f10x_gpio.h
|
||||
*
|
||||
* @brief This file contains all the functions prototypes for the GPIO firmware library
|
||||
* @brief This file contains all the functions prototypes for the GPIO firmware library
|
||||
*
|
||||
* @version V1.0.1
|
||||
* @version V1.0.2
|
||||
*
|
||||
* @date 2021-03-23
|
||||
* @date 2022-01-05
|
||||
*
|
||||
* @attention
|
||||
*
|
||||
* Copyright (C) 2020-2022 Geehy Semiconductor
|
||||
*
|
||||
* You may not use this file except in compliance with the
|
||||
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
|
||||
*
|
||||
* The program is only for reference, which is distributed in the hope
|
||||
* that it will be usefull and instructional for customers to develop
|
||||
* their software. Unless required by applicable law or agreed to in
|
||||
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
|
||||
* and limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __APM32F10X_GPIO_H
|
||||
#define __APM32F10X_GPIO_H
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
/** @addtogroup Peripherals_Library Standard Peripheral Library
|
||||
@{
|
||||
*/
|
||||
@@ -35,10 +49,10 @@
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_SPEED_10MHz = 1,
|
||||
GPIO_SPEED_2MHz,
|
||||
GPIO_SPEED_50MHz
|
||||
}GPIO_SPEED_T;
|
||||
GPIO_SPEED_10MHz = 1,
|
||||
GPIO_SPEED_20MHz,
|
||||
GPIO_SPEED_50MHz
|
||||
} GPIO_SPEED_T;
|
||||
|
||||
/**
|
||||
* @brief Configuration Mode enumeration
|
||||
@@ -53,7 +67,7 @@ typedef enum
|
||||
GPIO_MODE_OUT_OD = 0x84, //!< General purpose output Open-drain
|
||||
GPIO_MODE_AF_PP = 0x88, //!< Alternate function output Push-pull
|
||||
GPIO_MODE_AF_OD = 0x8C, //!< Alternate function output Open-drain
|
||||
}GPIO_MODE_T;
|
||||
} GPIO_MODE_T;
|
||||
|
||||
/**
|
||||
* @brief Definition of the GPIO pins
|
||||
@@ -84,108 +98,108 @@ typedef enum
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_NO_REMAP_SPI1 = 0x00000010,
|
||||
GPIO_REMAP_SPI1 = 0x00000011,
|
||||
GPIO_NO_REMAP_SPI1 = 0x00000010,
|
||||
GPIO_REMAP_SPI1 = 0x00000011,
|
||||
|
||||
GPIO_NO_REMAP_I2C1 = 0x00000110,
|
||||
GPIO_REMAP_I2C1 = 0x00000111,
|
||||
GPIO_NO_REMAP_I2C1 = 0x00000110,
|
||||
GPIO_REMAP_I2C1 = 0x00000111,
|
||||
|
||||
GPIO_NO_REMAP_USART1 = 0x00000210,
|
||||
GPIO_REMAP_USART1 = 0x00000211,
|
||||
GPIO_NO_REMAP_USART1 = 0x00000210,
|
||||
GPIO_REMAP_USART1 = 0x00000211,
|
||||
|
||||
GPIO_NO_REMAP_USART2 = 0x00000310,
|
||||
GPIO_REMAP_USART2 = 0x00000311,
|
||||
GPIO_NO_REMAP_USART2 = 0x00000310,
|
||||
GPIO_REMAP_USART2 = 0x00000311,
|
||||
|
||||
GPIO_NO_REMAP_USART3 = 0x00000430,
|
||||
GPIO_PARTIAL_REMAP_USART3 = 0x00000431,
|
||||
GPIO_FULL_REMAP_USART3 = 0x00000433,
|
||||
GPIO_NO_REMAP_USART3 = 0x00000430,
|
||||
GPIO_PARTIAL_REMAP_USART3 = 0x00000431,
|
||||
GPIO_FULL_REMAP_USART3 = 0x00000433,
|
||||
|
||||
GPIO_NO_REMAP_TMR1 = 0x00000630,
|
||||
GPIO_PARTIAL_REMAP_TMR1 = 0x00000631,
|
||||
GPIO_FULL_REMAP_TMR1 = 0x00000633,
|
||||
GPIO_NO_REMAP_TMR1 = 0x00000630,
|
||||
GPIO_PARTIAL_REMAP_TMR1 = 0x00000631,
|
||||
GPIO_FULL_REMAP_TMR1 = 0x00000633,
|
||||
|
||||
GPIO_NO_REMAP_TMR2 = 0x00000830,
|
||||
GPIO_PARTIAL_REMAP1_TMR2 = 0x00000831,
|
||||
GPIO_PARTIAL_REMAP2_TMR2 = 0x00000832,
|
||||
GPIO_FULL_REMAP_TMR2 = 0x00000833,
|
||||
GPIO_NO_REMAP_TMR2 = 0x00000830,
|
||||
GPIO_PARTIAL_REMAP1_TMR2 = 0x00000831,
|
||||
GPIO_PARTIAL_REMAP2_TMR2 = 0x00000832,
|
||||
GPIO_FULL_REMAP_TMR2 = 0x00000833,
|
||||
|
||||
GPIO_NO_REMAP_TMR3 = 0x00000A30,
|
||||
GPIO_PARTIAL_REMAP_TMR3 = 0x00000A32,
|
||||
GPIO_FULL_REMAP_TMR3 = 0x00000A33,
|
||||
GPIO_NO_REMAP_TMR3 = 0x00000A30,
|
||||
GPIO_PARTIAL_REMAP_TMR3 = 0x00000A32,
|
||||
GPIO_FULL_REMAP_TMR3 = 0x00000A33,
|
||||
|
||||
GPIO_NO_REMAP_TMR4 = 0x00000C10,
|
||||
GPIO_REMAP_TMR4 = 0x00000C11,
|
||||
GPIO_NO_REMAP_TMR4 = 0x00000C10,
|
||||
GPIO_REMAP_TMR4 = 0x00000C11,
|
||||
|
||||
GPIO_NO_REMAP_CAN1 = 0x00000D30,
|
||||
GPIO_REMAP1_CAN1 = 0x00000D32,
|
||||
GPIO_REMAP2_CAN1 = 0x00000D33,
|
||||
GPIO_NO_REMAP_CAN1 = 0x00000D30,
|
||||
GPIO_REMAP1_CAN1 = 0x00000D32,
|
||||
GPIO_REMAP2_CAN1 = 0x00000D33,
|
||||
|
||||
GPIO_NO_REMAP_PD01 = 0x00000F10,
|
||||
GPIO_REMAP_PD01 = 0x00000F11,
|
||||
GPIO_NO_REMAP_PD01 = 0x00000F10,
|
||||
GPIO_REMAP_PD01 = 0x00000F11,
|
||||
|
||||
GPIO_NO_REMAP_TMR5CH4_LSI = 0x00001010,
|
||||
GPIO_REMAP_TMR5CH4_LSI = 0x00001011,
|
||||
GPIO_NO_REMAP_TMR5CH4_LSI = 0x00001010,
|
||||
GPIO_REMAP_TMR5CH4_LSI = 0x00001011,
|
||||
|
||||
GPIO_NO_REMAP_ADC1_ETRGINJ = 0x00001110,
|
||||
GPIO_REMAP_ADC1_ETRGINJ = 0x00001111,
|
||||
GPIO_NO_REMAP_ADC1_ETRGINJ = 0x00001110,
|
||||
GPIO_REMAP_ADC1_ETRGINJ = 0x00001111,
|
||||
|
||||
GPIO_NO_REMAP_ADC1_ETRGREG = 0x00001210,
|
||||
GPIO_REMAP_ADC1_ETRGREG = 0x00001211,
|
||||
GPIO_NO_REMAP_ADC1_ETRGREG = 0x00001210,
|
||||
GPIO_REMAP_ADC1_ETRGREG = 0x00001211,
|
||||
|
||||
GPIO_NO_REMAP_ADC2_ETRGINJ = 0x00001310,
|
||||
GPIO_REMAP_ADC2_ETRGINJ = 0x00001311,
|
||||
GPIO_NO_REMAP_ADC2_ETRGINJ = 0x00001310,
|
||||
GPIO_REMAP_ADC2_ETRGINJ = 0x00001311,
|
||||
|
||||
GPIO_NO_REMAP_ADC2_ETRGREG = 0x00001410,
|
||||
GPIO_REMAP_ADC2_ETRGREG = 0x00001411,
|
||||
GPIO_NO_REMAP_ADC2_ETRGREG = 0x00001410,
|
||||
GPIO_REMAP_ADC2_ETRGREG = 0x00001411,
|
||||
|
||||
GPIO_NO_REMAP_CAN2 = 0x00001610,
|
||||
GPIO_REMAP_CAN2 = 0x00001611,
|
||||
GPIO_NO_REMAP_CAN2 = 0x00001610,
|
||||
GPIO_REMAP_CAN2 = 0x00001611,
|
||||
|
||||
GPIO_NO_REMAP_SWJ = 0x00001870,
|
||||
GPIO_REMAP_SWJ_NOJTRST = 0x00001871,
|
||||
GPIO_REMAP_SWJ_JTAGDISABLE = 0x00001872,
|
||||
GPIO_REMAP_SWJ_DISABLE = 0x00001874,
|
||||
GPIO_NO_REMAP_SWJ = 0x00001870,
|
||||
GPIO_REMAP_SWJ_NOJTRST = 0x00001871,
|
||||
GPIO_REMAP_SWJ_JTAGDISABLE = 0x00001872,
|
||||
GPIO_REMAP_SWJ_DISABLE = 0x00001874,
|
||||
|
||||
GPIO_NO_REMAP_EMMC_NADV = 0x00010A10,
|
||||
GPIO_REMAP_EMMC_NADV = 0x00010A11,
|
||||
}GPIO_REMAP_T;
|
||||
GPIO_NO_REMAP_EMMC_NADV = 0x00010A10,
|
||||
GPIO_REMAP_EMMC_NADV = 0x00010A11,
|
||||
} GPIO_REMAP_T;
|
||||
|
||||
/**
|
||||
* @brief gpio port source define
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_PORT_SOURCE_A,
|
||||
GPIO_PORT_SOURCE_B,
|
||||
GPIO_PORT_SOURCE_C,
|
||||
GPIO_PORT_SOURCE_D,
|
||||
GPIO_PORT_SOURCE_E,
|
||||
GPIO_PORT_SOURCE_F,
|
||||
GPIO_PORT_SOURCE_G,
|
||||
}GPIO_PORT_SOURCE_T;
|
||||
GPIO_PORT_SOURCE_A,
|
||||
GPIO_PORT_SOURCE_B,
|
||||
GPIO_PORT_SOURCE_C,
|
||||
GPIO_PORT_SOURCE_D,
|
||||
GPIO_PORT_SOURCE_E,
|
||||
GPIO_PORT_SOURCE_F,
|
||||
GPIO_PORT_SOURCE_G,
|
||||
} GPIO_PORT_SOURCE_T;
|
||||
|
||||
/**
|
||||
* @brief gpio pin source define
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_PIN_SOURCE_0,
|
||||
GPIO_PIN_SOURCE_1,
|
||||
GPIO_PIN_SOURCE_2,
|
||||
GPIO_PIN_SOURCE_3,
|
||||
GPIO_PIN_SOURCE_4,
|
||||
GPIO_PIN_SOURCE_5,
|
||||
GPIO_PIN_SOURCE_6,
|
||||
GPIO_PIN_SOURCE_7,
|
||||
GPIO_PIN_SOURCE_8,
|
||||
GPIO_PIN_SOURCE_9,
|
||||
GPIO_PIN_SOURCE_10,
|
||||
GPIO_PIN_SOURCE_11,
|
||||
GPIO_PIN_SOURCE_12,
|
||||
GPIO_PIN_SOURCE_13,
|
||||
GPIO_PIN_SOURCE_14,
|
||||
GPIO_PIN_SOURCE_15,
|
||||
}GPIO_PIN_SOURCE_T;
|
||||
GPIO_PIN_SOURCE_0,
|
||||
GPIO_PIN_SOURCE_1,
|
||||
GPIO_PIN_SOURCE_2,
|
||||
GPIO_PIN_SOURCE_3,
|
||||
GPIO_PIN_SOURCE_4,
|
||||
GPIO_PIN_SOURCE_5,
|
||||
GPIO_PIN_SOURCE_6,
|
||||
GPIO_PIN_SOURCE_7,
|
||||
GPIO_PIN_SOURCE_8,
|
||||
GPIO_PIN_SOURCE_9,
|
||||
GPIO_PIN_SOURCE_10,
|
||||
GPIO_PIN_SOURCE_11,
|
||||
GPIO_PIN_SOURCE_12,
|
||||
GPIO_PIN_SOURCE_13,
|
||||
GPIO_PIN_SOURCE_14,
|
||||
GPIO_PIN_SOURCE_15,
|
||||
} GPIO_PIN_SOURCE_T;
|
||||
|
||||
/**@} end of group GPIO_Enumerations*/
|
||||
|
||||
@@ -199,10 +213,10 @@ typedef enum
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t pin;
|
||||
GPIO_SPEED_T speed;
|
||||
GPIO_MODE_T mode;
|
||||
}GPIO_Config_T;
|
||||
uint16_t pin;
|
||||
GPIO_SPEED_T speed;
|
||||
GPIO_MODE_T mode;
|
||||
} GPIO_Config_T;
|
||||
|
||||
/**@} end of group GPIO_Structure*/
|
||||
|
||||
@@ -211,25 +225,25 @@ typedef struct
|
||||
*/
|
||||
|
||||
/** Reset and common Configuration */
|
||||
void GPIO_Reset(GPIO_T* port);
|
||||
void GPIO_Reset(GPIO_T *port);
|
||||
void GPIO_AFIOReset(void);
|
||||
void GPIO_Config(GPIO_T* port, GPIO_Config_T* gpioConfig);
|
||||
void GPIO_StructInit(GPIO_Config_T* gpioConfig);
|
||||
void GPIO_Config(GPIO_T *port, GPIO_Config_T *gpioConfig);
|
||||
void GPIO_ConfigStructInit(GPIO_Config_T *gpioConfig);
|
||||
|
||||
/** Read */
|
||||
uint8_t GPIO_ReadInputBit(GPIO_T* port, uint16_t pin);
|
||||
uint16_t GPIO_ReadInputPort(GPIO_T* port);
|
||||
uint8_t GPIO_ReadOutputBit(GPIO_T* port, uint16_t pin);
|
||||
uint16_t GPIO_ReadOutputPort(GPIO_T* port);
|
||||
uint8_t GPIO_ReadInputBit(GPIO_T *port, uint16_t pin);
|
||||
uint16_t GPIO_ReadInputPort(GPIO_T *port);
|
||||
uint8_t GPIO_ReadOutputBit(GPIO_T *port, uint16_t pin);
|
||||
uint16_t GPIO_ReadOutputPort(GPIO_T *port);
|
||||
|
||||
/** Write */
|
||||
void GPIO_SetBits(GPIO_T* port, uint16_t pin);
|
||||
void GPIO_ResetBits(GPIO_T* port, uint16_t pin);
|
||||
void GPIO_WriteOutputPort(GPIO_T* port, uint16_t portValue);
|
||||
void GPIO_WriteBitValue(GPIO_T* port, uint16_t pin, uint8_t bitVal);
|
||||
void GPIO_SetBit(GPIO_T *port, uint16_t pin);
|
||||
void GPIO_ResetBit(GPIO_T *port, uint16_t pin);
|
||||
void GPIO_WriteOutputPort(GPIO_T *port, uint16_t portValue);
|
||||
void GPIO_WriteBitValue(GPIO_T *port, uint16_t pin, uint8_t bitVal);
|
||||
|
||||
/** GPIO Configuration */
|
||||
void GPIO_ConfigPinLock(GPIO_T* port, uint16_t pin);
|
||||
void GPIO_ConfigPinLock(GPIO_T *port, uint16_t pin);
|
||||
void GPIO_ConfigEventOutput(GPIO_PORT_SOURCE_T portSource, GPIO_PIN_SOURCE_T pinSource);
|
||||
void GPIO_EnableEventOutput(void);
|
||||
void GPIO_DisableEventOutput(void);
|
||||
@@ -237,7 +251,7 @@ void GPIO_ConfigPinRemap(GPIO_REMAP_T remap);
|
||||
void GPIO_ConfigEINTLine(GPIO_PORT_SOURCE_T portSource, GPIO_PIN_SOURCE_T pinSource);
|
||||
|
||||
/**@} end of group GPIO_Fuctions*/
|
||||
/**@} end of group GPIO_Driver */
|
||||
/**@} end of group GPIO_Driver*/
|
||||
/**@} end of group Peripherals_Library*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
@@ -1,23 +1,37 @@
|
||||
/*!
|
||||
* @file apm32f10x_i2c.h
|
||||
* @file apm32f10x_i2c.h
|
||||
*
|
||||
* @brief This file contains all the functions prototypes for the I2C firmware library
|
||||
* @brief This file contains all the functions prototypes for the I2C firmware library
|
||||
*
|
||||
* @version V1.0.1
|
||||
* @version V1.0.2
|
||||
*
|
||||
* @date 2021-03-23
|
||||
* @date 2022-01-05
|
||||
*
|
||||
* @attention
|
||||
*
|
||||
* Copyright (C) 2020-2022 Geehy Semiconductor
|
||||
*
|
||||
* You may not use this file except in compliance with the
|
||||
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
|
||||
*
|
||||
* The program is only for reference, which is distributed in the hope
|
||||
* that it will be usefull and instructional for customers to develop
|
||||
* their software. Unless required by applicable law or agreed to in
|
||||
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
|
||||
* and limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __APM32F10X_I2C_H
|
||||
#define __APM32F10X_I2C_H
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
/** @addtogroup Peripherals_Library Standard Peripheral Library
|
||||
@{
|
||||
*/
|
||||
@@ -269,59 +283,59 @@ typedef struct
|
||||
*/
|
||||
|
||||
/** I2C reset and configuration */
|
||||
void I2C_Reset(I2C_T* i2c);
|
||||
void I2C_Config(I2C_T* i2c, I2C_Config_T* i2cConfig);
|
||||
void I2C_ConfigStructInit(I2C_Config_T* i2cConfig);
|
||||
void I2C_Enable(I2C_T* i2c);
|
||||
void I2C_Disable(I2C_T* i2c);
|
||||
void I2C_EnableGenerateStart(I2C_T* i2c);
|
||||
void I2C_DisableGenerateStart(I2C_T* i2c);
|
||||
void I2C_EnableGenerateStop(I2C_T* i2c);
|
||||
void I2C_DisableGenerateStop(I2C_T* i2c);
|
||||
void I2C_EnableAcknowledge(I2C_T* i2c);
|
||||
void I2C_DisableAcknowledge(I2C_T* i2c);
|
||||
void I2C_ConfigOwnAddress2(I2C_T* i2c, uint8_t address);
|
||||
void I2C_EnableDualAddress(I2C_T* i2c);
|
||||
void I2C_DisableDualAddress(I2C_T* i2c);
|
||||
void I2C_EnableGeneralCall(I2C_T* i2c);
|
||||
void I2C_DisableGeneralCall(I2C_T* i2c);
|
||||
void I2C_Reset(I2C_T *i2c);
|
||||
void I2C_Config(I2C_T *i2c, I2C_Config_T *i2cConfig);
|
||||
void I2C_ConfigStructInit(I2C_Config_T *i2cConfig);
|
||||
void I2C_Enable(I2C_T *i2c);
|
||||
void I2C_Disable(I2C_T *i2c);
|
||||
void I2C_EnableGenerateStart(I2C_T *i2c);
|
||||
void I2C_DisableGenerateStart(I2C_T *i2c);
|
||||
void I2C_EnableGenerateStop(I2C_T *i2c);
|
||||
void I2C_DisableGenerateStop(I2C_T *i2c);
|
||||
void I2C_EnableAcknowledge(I2C_T *i2c);
|
||||
void I2C_DisableAcknowledge(I2C_T *i2c);
|
||||
void I2C_ConfigOwnAddress2(I2C_T *i2c, uint8_t address);
|
||||
void I2C_EnableDualAddress(I2C_T *i2c);
|
||||
void I2C_DisableDualAddress(I2C_T *i2c);
|
||||
void I2C_EnableGeneralCall(I2C_T *i2c);
|
||||
void I2C_DisableGeneralCall(I2C_T *i2c);
|
||||
|
||||
/** Transmit Configuration */
|
||||
void I2C_TxData(I2C_T* i2c, uint8_t data);
|
||||
uint8_t I2C_RxData(I2C_T* i2c);
|
||||
void I2C_Tx7BitAddress(I2C_T* i2c, uint8_t address, I2C_DIRECTION_T direction);
|
||||
uint16_t I2C_ReadRegister(I2C_T* i2c, I2C_REGISTER_T i2cRegister);
|
||||
void I2C_EnableSoftwareReset(I2C_T* i2c);
|
||||
void I2C_DisableSoftwareReset(I2C_T* i2c);
|
||||
void I2C_ConfigNACKPosition(I2C_T* i2c, I2C_NACK_POSITION_T NACKPosition);
|
||||
void I2C_ConfigSMBusAlert(I2C_T* i2c, I2C_SMBUSALER_T SMBusState);
|
||||
void I2C_EnablePECTransmit(I2C_T* i2c);
|
||||
void I2C_DisablePECTransmit(I2C_T* i2c);
|
||||
void I2C_ConfigPECPosition(I2C_T* i2c, I2C_PEC_POSITION_T PECPosition);
|
||||
void I2C_EnablePEC(I2C_T* i2c);
|
||||
void I2C_DisablePEC(I2C_T* i2c);
|
||||
uint8_t I2C_ReadPEC(I2C_T* i2c);
|
||||
void I2C_EnableARP(I2C_T* i2c);
|
||||
void I2C_DisableARP(I2C_T* i2c);
|
||||
void I2C_EnableStretchClock(I2C_T* i2c);
|
||||
void I2C_DisableStretchClock(I2C_T* i2c);
|
||||
void I2C_ConfigFastModeDutyCycle(I2C_T* i2c, I2C_DUTYCYCLE_T dutyCycle);
|
||||
void I2C_TxData(I2C_T *i2c, uint8_t data);
|
||||
uint8_t I2C_RxData(I2C_T *i2c);
|
||||
void I2C_Tx7BitAddress(I2C_T *i2c, uint8_t address, I2C_DIRECTION_T direction);
|
||||
uint16_t I2C_ReadRegister(I2C_T *i2c, I2C_REGISTER_T i2cRegister);
|
||||
void I2C_EnableSoftwareReset(I2C_T *i2c);
|
||||
void I2C_DisableSoftwareReset(I2C_T *i2c);
|
||||
void I2C_ConfigNACKPosition(I2C_T *i2c, I2C_NACK_POSITION_T NACKPosition);
|
||||
void I2C_ConfigSMBusAlert(I2C_T *i2c, I2C_SMBUSALER_T SMBusState);
|
||||
void I2C_EnablePECTransmit(I2C_T *i2c);
|
||||
void I2C_DisablePECTransmit(I2C_T *i2c);
|
||||
void I2C_ConfigPECPosition(I2C_T *i2c, I2C_PEC_POSITION_T PECPosition);
|
||||
void I2C_EnablePEC(I2C_T *i2c);
|
||||
void I2C_DisablePEC(I2C_T *i2c);
|
||||
uint8_t I2C_ReadPEC(I2C_T *i2c);
|
||||
void I2C_EnableARP(I2C_T *i2c);
|
||||
void I2C_DisableARP(I2C_T *i2c);
|
||||
void I2C_EnableStretchClock(I2C_T *i2c);
|
||||
void I2C_DisableStretchClock(I2C_T *i2c);
|
||||
void I2C_ConfigFastModeDutyCycle(I2C_T *i2c, I2C_DUTYCYCLE_T dutyCycle);
|
||||
|
||||
/** DMA */
|
||||
void I2C_EnableDMA(I2C_T* i2c);
|
||||
void I2C_DisableDMA(I2C_T* i2c);
|
||||
void I2C_EnableDMALastTransfer(I2C_T* i2c);
|
||||
void I2C_DisableDMALastTransfer(I2C_T* i2c);
|
||||
void I2C_EnableDMA(I2C_T *i2c);
|
||||
void I2C_DisableDMA(I2C_T *i2c);
|
||||
void I2C_EnableDMALastTransfer(I2C_T *i2c);
|
||||
void I2C_DisableDMALastTransfer(I2C_T *i2c);
|
||||
|
||||
/** Interrupts and flags */
|
||||
void I2C_EnableInterrupt(I2C_T* i2c, uint16_t interrupt);
|
||||
void I2C_DisableInterrupt(I2C_T* i2c, uint16_t interrupt);
|
||||
uint8_t I2C_ReadEventStatus(I2C_T* i2c, I2C_EVENT_T i2cEvent);
|
||||
uint32_t I2C_ReadLastEvent(I2C_T* i2c);
|
||||
uint8_t I2C_ReadStatusFlag(I2C_T* i2c, I2C_FLAG_T flag);
|
||||
void I2C_ClearStatusFlag(I2C_T* i2c, I2C_FLAG_T flag);
|
||||
uint8_t I2C_ReadIntFlag(I2C_T* i2c, I2C_INT_FLAG_T flag);
|
||||
void I2C_ClearIntFlag(I2C_T* i2c, I2C_INT_FLAG_T flag);
|
||||
void I2C_EnableInterrupt(I2C_T *i2c, uint16_t interrupt);
|
||||
void I2C_DisableInterrupt(I2C_T *i2c, uint16_t interrupt);
|
||||
uint8_t I2C_ReadEventStatus(I2C_T *i2c, I2C_EVENT_T i2cEvent);
|
||||
uint32_t I2C_ReadLastEvent(I2C_T *i2c);
|
||||
uint8_t I2C_ReadStatusFlag(I2C_T *i2c, I2C_FLAG_T flag);
|
||||
void I2C_ClearStatusFlag(I2C_T *i2c, I2C_FLAG_T flag);
|
||||
uint8_t I2C_ReadIntFlag(I2C_T *i2c, I2C_INT_FLAG_T flag);
|
||||
void I2C_ClearIntFlag(I2C_T *i2c, uint32_t flag);
|
||||
|
||||
/**@} end of group I2C_Fuctions*/
|
||||
/**@} end of group I2C_Driver*/
|
||||
|
||||
@@ -3,21 +3,35 @@
|
||||
*
|
||||
* @brief This file contains all the functions prototypes for the IWDT firmware library
|
||||
*
|
||||
* @version V1.0.1
|
||||
* @version V1.0.2
|
||||
*
|
||||
* @date 2021-03-23
|
||||
* @date 2022-01-05
|
||||
*
|
||||
* @attention
|
||||
*
|
||||
* Copyright (C) 2020-2022 Geehy Semiconductor
|
||||
*
|
||||
* You may not use this file except in compliance with the
|
||||
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
|
||||
*
|
||||
* The program is only for reference, which is distributed in the hope
|
||||
* that it will be usefull and instructional for customers to develop
|
||||
* their software. Unless required by applicable law or agreed to in
|
||||
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
|
||||
* and limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __APM32F10X_IWDT_H
|
||||
#define __APM32F10X_IWDT_H
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
/** @addtogroup Peripherals_Library Standard Peripheral Library
|
||||
@{
|
||||
*/
|
||||
@@ -37,7 +51,7 @@ typedef enum
|
||||
{
|
||||
IWDT_KEYWORD_RELOAD = 0xAAAA,
|
||||
IWDT_KEYWORD_ENABLE = 0xCCCC
|
||||
}IWDT_KEYWORD_T;
|
||||
} IWDT_KEYWORD_T;
|
||||
|
||||
/**
|
||||
* @brief IWDT Write Access define
|
||||
@@ -46,7 +60,7 @@ typedef enum
|
||||
{
|
||||
IWDT_WRITEACCESS_ENABLE = 0x5555,
|
||||
IWDT_WRITEACCESS_DISABLE = 0x0000
|
||||
}IWDT_WRITEACCESS_T;
|
||||
} IWDT_WRITEACCESS_T;
|
||||
|
||||
/**
|
||||
* @brief IWDT Divider
|
||||
@@ -60,7 +74,7 @@ typedef enum
|
||||
IWDT_DIVIDER_64 = 0x04,
|
||||
IWDT_DIVIDER_128 = 0x05,
|
||||
IWDT_DIVIDER_256 = 0x06
|
||||
}IWDT_DIVIDER_T;
|
||||
} IWDT_DIVIDER_T;
|
||||
|
||||
/**
|
||||
* @brief IWDT Flag
|
||||
@@ -69,7 +83,7 @@ typedef enum
|
||||
{
|
||||
IWDT_FLAG_PSCU = BIT0,
|
||||
IWDT_FLAG_CNTU = BIT1
|
||||
}IWDT_FLAG_T;
|
||||
} IWDT_FLAG_T;
|
||||
|
||||
/**@} end of group IWDT_Enumerations*/
|
||||
|
||||
@@ -98,7 +112,7 @@ void IWDT_DisableWriteAccess(void);
|
||||
uint8_t IWDT_ReadStatusFlag(uint16_t flag);
|
||||
|
||||
/**@} end of group IWDT_Fuctions*/
|
||||
/**@} end of group IWDT_Driver */
|
||||
/**@} end of group IWDT_Driver*/
|
||||
/**@} end of group Peripherals_Library*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
@@ -1,24 +1,38 @@
|
||||
/*!
|
||||
* @file apm32f10x_misc.h
|
||||
* @file apm32f10x_misc.h
|
||||
*
|
||||
* @brief This file provides all the miscellaneous firmware functions.
|
||||
* @brief This file provides all the miscellaneous firmware functions.
|
||||
* Include NVIC,SystemTick and Power management.
|
||||
*
|
||||
* @version V1.0.1
|
||||
* @version V1.0.2
|
||||
*
|
||||
* @date 2021-03-23
|
||||
* @date 2022-01-05
|
||||
*
|
||||
* @attention
|
||||
*
|
||||
* Copyright (C) 2020-2022 Geehy Semiconductor
|
||||
*
|
||||
* You may not use this file except in compliance with the
|
||||
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
|
||||
*
|
||||
* The program is only for reference, which is distributed in the hope
|
||||
* that it will be usefull and instructional for customers to develop
|
||||
* their software. Unless required by applicable law or agreed to in
|
||||
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
|
||||
* and limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __APM32F10X_MISC_H
|
||||
#define __APM32F10X_MISC_H
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
/** @addtogroup Peripherals_Library Standard Peripheral Library
|
||||
@{
|
||||
*/
|
||||
@@ -36,19 +50,19 @@
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NVIC_VECT_TAB_RAM = 0x20000000,
|
||||
NVIC_VECT_TAB_FLASH = 0x08000000,
|
||||
}NVIC_VECT_TAB_T;
|
||||
NVIC_VECT_TAB_RAM = 0x20000000,
|
||||
NVIC_VECT_TAB_FLASH = 0x08000000,
|
||||
} NVIC_VECT_TAB_T;
|
||||
|
||||
/**
|
||||
* @brief system low power mode
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NVIC_LOWPOWER_SEVONPEND = 0x10,
|
||||
NVIC_LOWPOWER_SLEEPDEEP = 0x04,
|
||||
NVIC_LOWPOWER_SLEEPONEXIT = 0x02
|
||||
}NVIC_LOWPOWER_T;
|
||||
NVIC_LOWPOWER_SEVONPEND = 0x10,
|
||||
NVIC_LOWPOWER_SLEEPDEEP = 0x04,
|
||||
NVIC_LOWPOWER_SLEEPONEXIT = 0x02
|
||||
} NVIC_LOWPOWER_T;
|
||||
|
||||
/**
|
||||
* @brief nvic priority group
|
||||
@@ -60,16 +74,16 @@ typedef enum
|
||||
NVIC_PRIORITY_GROUP_2 = 0x500, //!< 2 bits for pre-emption priority,2 bits for subpriority
|
||||
NVIC_PRIORITY_GROUP_3 = 0x400, //!< 3 bits for pre-emption priority,1 bits for subpriority
|
||||
NVIC_PRIORITY_GROUP_4 = 0x300 //!< 4 bits for pre-emption priority,0 bits for subpriority
|
||||
}NVIC_PRIORITY_GROUP_T;
|
||||
} NVIC_PRIORITY_GROUP_T;
|
||||
|
||||
/**
|
||||
* @brief SysTick Clock source
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SYSTICK_CLK_SOURCE_HCLK_DIV8 = 0x00,
|
||||
SYSTICK_CLK_SOURCE_HCLK = 0x01
|
||||
}SYSTICK_CLK_SOURCE_T;
|
||||
SYSTICK_CLK_SOURCE_HCLK_DIV8 = 0x00,
|
||||
SYSTICK_CLK_SOURCE_HCLK = 0x01
|
||||
} SYSTICK_CLK_SOURCE_T;
|
||||
|
||||
/**@} end of group MISC_Enumerations*/
|
||||
|
||||
@@ -93,6 +107,10 @@ void NVIC_ResetystemLowPower(NVIC_LOWPOWER_T lowPowerMode);
|
||||
/** Systick */
|
||||
void SysTick_ConfigCLKSource(SYSTICK_CLK_SOURCE_T clkSource);
|
||||
|
||||
/**@} end of group MISC_Fuctions*/
|
||||
/**@} end of group MISC_Driver*/
|
||||
/**@} end of group Peripherals_Library*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -1,23 +1,37 @@
|
||||
/*!
|
||||
* @file apm32f10x_pmu.h
|
||||
* @file apm32f10x_pmu.h
|
||||
*
|
||||
* @brief This file contains all the functions prototypes for the PMU firmware library.
|
||||
* @brief This file contains all the functions prototypes for the PMU firmware library.
|
||||
*
|
||||
* @version V1.0.1
|
||||
* @version V1.0.2
|
||||
*
|
||||
* @date 2021-03-23
|
||||
* @date 2022-01-05
|
||||
*
|
||||
* @attention
|
||||
*
|
||||
* Copyright (C) 2020-2022 Geehy Semiconductor
|
||||
*
|
||||
* You may not use this file except in compliance with the
|
||||
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
|
||||
*
|
||||
* The program is only for reference, which is distributed in the hope
|
||||
* that it will be usefull and instructional for customers to develop
|
||||
* their software. Unless required by applicable law or agreed to in
|
||||
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
|
||||
* and limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __APM32F10X_PMU_H
|
||||
#define __APM32F10X_PMU_H
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
/** @addtogroup Peripherals_Library Standard Peripheral Library
|
||||
@{
|
||||
*/
|
||||
@@ -30,6 +44,9 @@ extern "C" {
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief PMU PVD detection level
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
PMU_PVD_LEVEL_2V2 = 0x00, //!< PVD detection level set to 2.2V
|
||||
@@ -42,18 +59,27 @@ typedef enum
|
||||
PMU_PVD_LEVEL_2V9 = 0x07, //!< PVD detection level set to 2.9V
|
||||
} PMU_PVD_LEVEL_T;
|
||||
|
||||
/**
|
||||
* @brief PMU Regulator state in STOP mode
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
PMU_REGULATOR_ON = 0x00,
|
||||
PMU_REGULATOR_LOWPOWER = 0x01
|
||||
} PMU_REGULATOR_T;
|
||||
|
||||
/**
|
||||
* @brief PMU STOP mode entry
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
PMU_STOP_ENTRY_WFI = 0x01,
|
||||
PMU_STOP_ENTRY_WFE = 0x02
|
||||
} PMU_STOP_ENTRY_T;
|
||||
|
||||
/**
|
||||
* @brief PMU Flag
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
PMU_FLAG_WUE,
|
||||
@@ -87,7 +113,7 @@ uint8_t PMU_ReadStatusFlag(PMU_FLAG_T flag);
|
||||
void PMU_ClearStatusFlag(PMU_FLAG_T flag);
|
||||
|
||||
/**@} end of group PMU_Fuctions*/
|
||||
/**@} end of group PMU_Driver */
|
||||
/**@} end of group PMU_Driver*/
|
||||
/**@} end of group Peripherals_Library*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
@@ -3,21 +3,35 @@
|
||||
*
|
||||
* @brief This file contains all the prototypes,enumeration and macros for the QSPI peripheral
|
||||
*
|
||||
* @version V1.0.1
|
||||
* @version V1.0.2
|
||||
*
|
||||
* @date 2021-03-23
|
||||
* @date 2022-01-05
|
||||
*
|
||||
* @attention
|
||||
*
|
||||
* Copyright (C) 2020-2022 Geehy Semiconductor
|
||||
*
|
||||
* You may not use this file except in compliance with the
|
||||
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
|
||||
*
|
||||
* The program is only for reference, which is distributed in the hope
|
||||
* that it will be usefull and instructional for customers to develop
|
||||
* their software. Unless required by applicable law or agreed to in
|
||||
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
|
||||
* and limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef __APM32F10X_QSPI_H
|
||||
#define __APM32F10X_QSPI_H
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
/** @addtogroup Peripherals_Library Standard Peripheral Library
|
||||
@{
|
||||
*/
|
||||
@@ -38,7 +52,7 @@ typedef enum
|
||||
QSPI_FRF_STANDARD, //!< Standard mode
|
||||
QSPI_FRF_DUAL, //!< Dual SPI
|
||||
QSPI_FRF_QUAD //!< QUAD SPI
|
||||
}QSPI_FRF_T;
|
||||
} QSPI_FRF_T;
|
||||
|
||||
/**
|
||||
* @brief Transmission mode
|
||||
@@ -48,8 +62,8 @@ typedef enum
|
||||
QSPI_TRANS_MODE_TX_RX, //!< TX and RX mode
|
||||
QSPI_TRANS_MODE_TX, //!< TX mode only
|
||||
QSPI_TRANS_MODE_RX, //!< RX mode only
|
||||
QSPI_TRANS_MODE_EEPROM_READ, //!< EEPROM read mode
|
||||
}QSPI_TRANS_MODE_T;
|
||||
QSPI_TRANS_MODE_EEPROM_READ //!< EEPROM read mode
|
||||
} QSPI_TRANS_MODE_T;
|
||||
|
||||
/**
|
||||
* @brief Clock polarity
|
||||
@@ -57,8 +71,8 @@ typedef enum
|
||||
typedef enum
|
||||
{
|
||||
QSPI_CLKPOL_LOW,
|
||||
QSPI_CLKPOL_HIGH,
|
||||
}QSPI_CLKPOL_T;
|
||||
QSPI_CLKPOL_HIGH
|
||||
} QSPI_CLKPOL_T;
|
||||
|
||||
/**
|
||||
* @brief Clock phase
|
||||
@@ -67,7 +81,7 @@ typedef enum
|
||||
{
|
||||
QSPI_CLKPHA_1EDGE,
|
||||
QSPI_CLKPHA_2EDGE
|
||||
}QSPI_CLKPHA_T;
|
||||
} QSPI_CLKPHA_T;
|
||||
|
||||
/**
|
||||
* @brief Data format size
|
||||
@@ -102,8 +116,8 @@ typedef enum
|
||||
QSPI_DFS_29BIT,
|
||||
QSPI_DFS_30BIT,
|
||||
QSPI_DFS_31BIT,
|
||||
QSPI_DFS_32BIT,
|
||||
}QSPI_DFS_T;
|
||||
QSPI_DFS_32BIT
|
||||
} QSPI_DFS_T;
|
||||
|
||||
/**
|
||||
* @brief QSPI flag
|
||||
@@ -116,7 +130,7 @@ typedef enum
|
||||
QSPI_FLAG_RFNE = BIT3, //!< RX FIFO not empty flag
|
||||
QSPI_FLAG_RFF = BIT4, //!< RX FIFO full flag
|
||||
QSPI_FLAG_DCE = BIT6 //!< Data collision error
|
||||
}QSPI_FLAG_T;
|
||||
} QSPI_FLAG_T;
|
||||
|
||||
/**
|
||||
* @brief QSPI interrupt source
|
||||
@@ -128,8 +142,8 @@ typedef enum
|
||||
QSPI_INT_RFU = BIT2, //!< RX FIFO underflow interrupt
|
||||
QSPI_INT_RFO = BIT3, //!< RX FIFO overflow interrupt
|
||||
QSPI_INT_RFF = BIT4, //!< RX FIFO full interrupt
|
||||
QSPI_INT_MST = BIT5, //!< Master interrupt
|
||||
}QSPI_INT_T;
|
||||
QSPI_INT_MST = BIT5 //!< Master interrupt
|
||||
} QSPI_INT_T;
|
||||
|
||||
/**
|
||||
* @brief QSPI interrupt flag
|
||||
@@ -141,8 +155,8 @@ typedef enum
|
||||
QSPI_INT_FLAG_RFU = BIT2, //!< RX FIFO underflow interrupt flag
|
||||
QSPI_INT_FLAG_RFO = BIT3, //!< RX FIFO overflow interrupt flag
|
||||
QSPI_INT_FLAG_RFF = BIT4, //!< RX FIFO full interrupt flag
|
||||
QSPI_INT_FLAG_MST = BIT5, //!< Master interrupt flag
|
||||
}QSPI_INT_FLAG_T;
|
||||
QSPI_INT_FLAG_MST = BIT5 //!< Master interrupt flag
|
||||
} QSPI_INT_FLAG_T;
|
||||
|
||||
/**
|
||||
* @brief Reception sample edge
|
||||
@@ -151,7 +165,7 @@ typedef enum
|
||||
{
|
||||
QSPI_RSE_RISING,
|
||||
QSPI_RSE_FALLING
|
||||
}QSPI_RSE_T;
|
||||
} QSPI_RSE_T;
|
||||
|
||||
/**
|
||||
* @brief Instruction length
|
||||
@@ -161,8 +175,8 @@ typedef enum
|
||||
QSPI_INST_LEN_0,
|
||||
QSPI_INST_LEN_4BIT,
|
||||
QSPI_INST_LEN_8BIT,
|
||||
QSPI_INST_LEN_16BIT,
|
||||
}QSPI_INST_LEN_T;
|
||||
QSPI_INST_LEN_16BIT
|
||||
} QSPI_INST_LEN_T;
|
||||
|
||||
/**
|
||||
* @brief QSPI address length
|
||||
@@ -184,8 +198,8 @@ typedef enum
|
||||
QSPI_ADDR_LEN_48BIT,
|
||||
QSPI_ADDR_LEN_52BIT,
|
||||
QSPI_ADDR_LEN_56BIT,
|
||||
QSPI_ADDR_LEN_60BIT,
|
||||
}QSPI_ADDR_LEN_T;
|
||||
QSPI_ADDR_LEN_60BIT
|
||||
} QSPI_ADDR_LEN_T;
|
||||
|
||||
/**
|
||||
* @brief Instruction and address transmission mode
|
||||
@@ -194,8 +208,8 @@ typedef enum
|
||||
{
|
||||
QSPI_INST_ADDR_TYPE_STANDARD,
|
||||
QSPI_INST_TYPE_STANDARD,
|
||||
QSPI_INST_ADDR_TYPE_FRF,
|
||||
}QSPI_INST_ADDR_TYPE_T;
|
||||
QSPI_INST_ADDR_TYPE_FRF
|
||||
} QSPI_INST_ADDR_TYPE_T;
|
||||
|
||||
/**
|
||||
* @brief Slave Select Toggle
|
||||
@@ -203,8 +217,8 @@ typedef enum
|
||||
typedef enum
|
||||
{
|
||||
QSPI_SST_DISABLE,
|
||||
QSPI_SST_ENABLE,
|
||||
}QSPI_SST_T;
|
||||
QSPI_SST_ENABLE
|
||||
} QSPI_SST_T;
|
||||
|
||||
/**@} end of group QSPI_Enumerations*/
|
||||
|
||||
@@ -255,7 +269,7 @@ typedef struct
|
||||
QSPI_CLKPOL_T clockPolarity; //!< Clock polarity
|
||||
QSPI_CLKPHA_T clockPhase; //!< Clock phase
|
||||
QSPI_DFS_T dataFrameSize; //!< Data frame size
|
||||
}QSPI_Config_T;
|
||||
} QSPI_Config_T;
|
||||
|
||||
/**@} end of group QSPI_Structure*/
|
||||
|
||||
|
||||
@@ -1,23 +1,37 @@
|
||||
/*!
|
||||
* @file apm32f10x_rcm.h
|
||||
* @file apm32f10x_rcm.h
|
||||
*
|
||||
* @brief This file contains all the functions prototypes for the RCM firmware library
|
||||
* @brief This file contains all the functions prototypes for the RCM firmware library
|
||||
*
|
||||
* @version V1.0.1
|
||||
* @version V1.0.2
|
||||
*
|
||||
* @date 2021-03-23
|
||||
* @date 2022-01-05
|
||||
*
|
||||
* @attention
|
||||
*
|
||||
* Copyright (C) 2020-2022 Geehy Semiconductor
|
||||
*
|
||||
* You may not use this file except in compliance with the
|
||||
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
|
||||
*
|
||||
* The program is only for reference, which is distributed in the hope
|
||||
* that it will be usefull and instructional for customers to develop
|
||||
* their software. Unless required by applicable law or agreed to in
|
||||
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
|
||||
* and limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __APM32F10X_RCM_H
|
||||
#define __APM32F10X_RCM_H
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
/** @addtogroup Peripherals_Library Standard Peripheral Library
|
||||
@{
|
||||
*/
|
||||
@@ -35,9 +49,9 @@ extern "C" {
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
RCM_HSE_CLOSE, //!< CLOSE HSE
|
||||
RCM_HSE_OPEN, //!< OPEN HSE
|
||||
RCM_HSE_BYPASS, //!< HSE BYPASS
|
||||
RCM_HSE_CLOSE,
|
||||
RCM_HSE_OPEN,
|
||||
RCM_HSE_BYPASS
|
||||
} RCM_HSE_T;
|
||||
|
||||
/**
|
||||
@@ -59,7 +73,7 @@ typedef enum
|
||||
RCM_PLLMF_13,
|
||||
RCM_PLLMF_14,
|
||||
RCM_PLLMF_15,
|
||||
RCM_PLLMF_16,
|
||||
RCM_PLLMF_16
|
||||
} RCM_PLLMF_T;
|
||||
|
||||
/**
|
||||
@@ -85,7 +99,7 @@ typedef enum
|
||||
RCM_AHB_DIV_64,
|
||||
RCM_AHB_DIV_128,
|
||||
RCM_AHB_DIV_256,
|
||||
RCM_AHB_DIV_512,
|
||||
RCM_AHB_DIV_512
|
||||
} RCM_AHB_DIV_T;
|
||||
|
||||
/**
|
||||
@@ -117,7 +131,7 @@ typedef enum
|
||||
typedef enum
|
||||
{
|
||||
RCM_FPU_DIV_1,
|
||||
RCM_FPU_DIV_2,
|
||||
RCM_FPU_DIV_2
|
||||
} RCM_FPU_DIV_T;
|
||||
|
||||
/**
|
||||
@@ -128,7 +142,7 @@ typedef enum
|
||||
RCM_PCLK2_DIV_2,
|
||||
RCM_PCLK2_DIV_4,
|
||||
RCM_PCLK2_DIV_6,
|
||||
RCM_PCLK2_DIV_8,
|
||||
RCM_PCLK2_DIV_8
|
||||
} RCM_PCLK2_DIV_T;
|
||||
|
||||
/**
|
||||
@@ -160,7 +174,7 @@ typedef enum
|
||||
RCM_MCOCLK_SYSCLK,
|
||||
RCM_MCOCLK_HSI,
|
||||
RCM_MCOCLK_HSE,
|
||||
RCM_MCOCLK_PLLCLK_DIV_2,
|
||||
RCM_MCOCLK_PLLCLK_DIV_2
|
||||
} RCM_MCOCLK_T;
|
||||
|
||||
/**
|
||||
@@ -199,7 +213,7 @@ typedef enum
|
||||
RCM_AHB_PERIPH_QSPI = BIT5,
|
||||
RCM_AHB_PERIPH_CRC = BIT6,
|
||||
RCM_AHB_PERIPH_EMMC = BIT8,
|
||||
RCM_AHB_PERIPH_SDIO = BIT10,
|
||||
RCM_AHB_PERIPH_SDIO = BIT10
|
||||
} RCM_AHB_PERIPH_T;
|
||||
|
||||
/**
|
||||
@@ -221,7 +235,7 @@ typedef enum
|
||||
RCM_APB2_PERIPH_SPI1 = BIT12,
|
||||
RCM_APB2_PERIPH_TMR8 = BIT13,
|
||||
RCM_APB2_PERIPH_USART1 = BIT14,
|
||||
RCM_APB2_PERIPH_ADC3 = BIT15,
|
||||
RCM_APB2_PERIPH_ADC3 = BIT15
|
||||
} RCM_APB2_PERIPH_T;
|
||||
|
||||
/**
|
||||
@@ -249,7 +263,7 @@ typedef enum
|
||||
RCM_APB1_PERIPH_CAN2 = BIT26,
|
||||
RCM_APB1_PERIPH_BAKR = BIT27,
|
||||
RCM_APB1_PERIPH_PMU = BIT28,
|
||||
RCM_APB1_PERIPH_DAC = BIT29,
|
||||
RCM_APB1_PERIPH_DAC = BIT29
|
||||
} RCM_APB1_PERIPH_T;
|
||||
|
||||
/**
|
||||
@@ -267,7 +281,7 @@ typedef enum
|
||||
RCM_FLAG_SWRST = 0x21C, //!< Software reset flag
|
||||
RCM_FLAG_IWDTRST = 0x21D, //!< Independent watchdog reset flag
|
||||
RCM_FLAG_WWDTRST = 0x21E, //!< Window watchdog reset flag
|
||||
RCM_FLAG_LPRRST = 0x21F, //!< Low-power reset flag
|
||||
RCM_FLAG_LPRRST = 0x21F //!< Low-power reset flag
|
||||
} RCM_FLAG_T;
|
||||
|
||||
/**@} end of group RCM_Enumerations*/
|
||||
@@ -287,7 +301,7 @@ void RCM_ConfigHSE(RCM_HSE_T state);
|
||||
uint8_t RCM_WaitHSEReady(void);
|
||||
|
||||
/** HSI clock */
|
||||
void RCM_SetHSITrim(uint8_t HSITrim);
|
||||
void RCM_ConfigHSITrim(uint8_t HSITrim);
|
||||
void RCM_EnableHSI(void);
|
||||
void RCM_DisableHSI(void);
|
||||
|
||||
@@ -325,7 +339,7 @@ void RCM_DisableRTCCLK(void);
|
||||
/** Reads the clock frequency */
|
||||
uint32_t RCM_ReadSYSCLKFreq(void);
|
||||
uint32_t RCM_ReadHCLKFreq(void);
|
||||
void RCM_ReadPCLKFreq(uint32_t* PCLK1, uint32_t* PCLK2);
|
||||
void RCM_ReadPCLKFreq(uint32_t *PCLK1, uint32_t *PCLK2);
|
||||
uint32_t RCM_ReadADCCLKFreq(void);
|
||||
|
||||
/** Enable or disable Periph Clock */
|
||||
|
||||
@@ -1,23 +1,37 @@
|
||||
/*!
|
||||
* @file apm32f10x_rtc.h
|
||||
* @file apm32f10x_rtc.h
|
||||
*
|
||||
* @brief This file contains all the functions prototypes for the RTC firmware library
|
||||
* @brief This file contains all the functions prototypes for the RTC firmware library
|
||||
*
|
||||
* @version V1.0.1
|
||||
* @version V1.0.2
|
||||
*
|
||||
* @date 2021-03-23
|
||||
* @date 2022-01-05
|
||||
*
|
||||
* @attention
|
||||
*
|
||||
* Copyright (C) 2020-2022 Geehy Semiconductor
|
||||
*
|
||||
* You may not use this file except in compliance with the
|
||||
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
|
||||
*
|
||||
* The program is only for reference, which is distributed in the hope
|
||||
* that it will be usefull and instructional for customers to develop
|
||||
* their software. Unless required by applicable law or agreed to in
|
||||
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
|
||||
* and limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __APM32F10X_RTC_H
|
||||
#define __APM32F10X_RTC_H
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
/** @addtogroup Peripherals_Library Standard Peripheral Library
|
||||
@{
|
||||
*/
|
||||
|
||||
@@ -3,21 +3,35 @@
|
||||
*
|
||||
* @brief This file contains all the prototypes,enumeration and macros for the SCI2C(I2C3, I2C4) peripheral
|
||||
*
|
||||
* @version V1.0.1
|
||||
* @version V1.0.2
|
||||
*
|
||||
* @date 2021-03-23
|
||||
* @date 2022-01-05
|
||||
*
|
||||
* @attention
|
||||
*
|
||||
* Copyright (C) 2020-2022 Geehy Semiconductor
|
||||
*
|
||||
* You may not use this file except in compliance with the
|
||||
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
|
||||
*
|
||||
* The program is only for reference, which is distributed in the hope
|
||||
* that it will be usefull and instructional for customers to develop
|
||||
* their software. Unless required by applicable law or agreed to in
|
||||
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
|
||||
* and limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __APM32F10X_SCI2C_H
|
||||
#define __APM32F10X_SCI2C_H
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
/** @addtogroup Peripherals_Library Standard Peripheral Library
|
||||
@{
|
||||
*/
|
||||
@@ -38,7 +52,7 @@ typedef enum
|
||||
SCI2C_SPEED_STANDARD = 1,
|
||||
SCI2C_SPEED_FAST,
|
||||
SCI2C_SPEED_HIGH
|
||||
}SCI2C_SPEED_T;
|
||||
} SCI2C_SPEED_T;
|
||||
|
||||
/**
|
||||
* @brief Address mode
|
||||
@@ -47,7 +61,7 @@ typedef enum
|
||||
{
|
||||
SCI2C_ADDR_MODE_7BIT,
|
||||
SCI2C_ADDR_MODE_10BIT
|
||||
}SCI2C_ADDR_MODE_T;
|
||||
} SCI2C_ADDR_MODE_T;
|
||||
|
||||
/**
|
||||
* @brief SCI2C mode enumeration
|
||||
@@ -56,7 +70,7 @@ typedef enum
|
||||
{
|
||||
SCI2C_MODE_MASTER,
|
||||
SCI2C_MODE_SLAVE
|
||||
}SCI2C_MODE_T;
|
||||
} SCI2C_MODE_T;
|
||||
|
||||
/**
|
||||
* @brief Restart enable or disable
|
||||
@@ -65,7 +79,7 @@ typedef enum
|
||||
{
|
||||
SCI2C_RESTART_DISABLE,
|
||||
SCI2C_RESTART_ENABLE
|
||||
}SCI2C_RESTART_T;
|
||||
} SCI2C_RESTART_T;
|
||||
|
||||
/**
|
||||
* @brief Enable or disable generate stop condition
|
||||
@@ -74,7 +88,7 @@ typedef enum
|
||||
{
|
||||
SCI2C_STOP_DISABLE,
|
||||
SCI2C_STOP_ENABLE
|
||||
}SCI2C_STOP_T;
|
||||
} SCI2C_STOP_T;
|
||||
/**
|
||||
* @brief Data direction
|
||||
*/
|
||||
@@ -82,7 +96,7 @@ typedef enum
|
||||
{
|
||||
SCI2C_DATA_DIR_WRITE,
|
||||
SCI2C_DATA_DIR_READ,
|
||||
}SCI2C_DATA_DIR_T;
|
||||
} SCI2C_DATA_DIR_T;
|
||||
|
||||
/**
|
||||
* @brief SCI2C interrupt
|
||||
@@ -104,7 +118,7 @@ typedef enum
|
||||
SCI2C_INT_RSTAD = BIT12, //!< Restart detect interrupt
|
||||
SCI2C_INT_MOH = BIT13, //!< Master on hold interrupt
|
||||
SCI2C_INT_ALL = BIT15 //!< All interrupt
|
||||
}SCI2C_INT_T;
|
||||
} SCI2C_INT_T;
|
||||
|
||||
/**
|
||||
* @brief Flag enumeration
|
||||
@@ -121,7 +135,7 @@ typedef enum
|
||||
SCI2C_FLAG_I2CEN = BIT8 | BIT0, //!< I2C enable flag
|
||||
SCI2C_FLAG_SDWB = BIT8 | BIT1, //!< Slave disable while busy flag
|
||||
SCI2C_FLAG_SRDL = BIT8 | BIT2 //!< Slave receive data lost flag
|
||||
}SCI2C_FLAG_T;
|
||||
} SCI2C_FLAG_T;
|
||||
|
||||
/**
|
||||
* @brief Tx abort source
|
||||
@@ -144,7 +158,7 @@ typedef enum
|
||||
SCI2C_TAS_SRI = BIT13, //!< Slave read done
|
||||
SCI2C_TAS_USRARB = BIT14, //!< User abort
|
||||
SCI2C_TAS_FLUCNT = BIT15 //!< Tx flush counter
|
||||
}SCI2C_TAS_T;
|
||||
} SCI2C_TAS_T;
|
||||
|
||||
/**
|
||||
* @brief DMA Enable
|
||||
@@ -153,7 +167,7 @@ typedef enum
|
||||
{
|
||||
SCI2C_DMA_RX = BIT0,
|
||||
SCI2C_DMA_TX = BIT1,
|
||||
}SCI2C_DMA_T;
|
||||
} SCI2C_DMA_T;
|
||||
|
||||
/**@} end of group SCI2C_Enumerations*/
|
||||
|
||||
@@ -213,7 +227,7 @@ typedef struct
|
||||
uint8_t txFifoThreshold; //!< Tx FIFO threshold
|
||||
SCI2C_RESTART_T restart; //!< Enable or disable restart
|
||||
SCI2C_ADDR_MODE_T addrMode; //!< Address mode. 7-bit or 10-bit mode.
|
||||
}SCI2C_Config_T;
|
||||
} SCI2C_Config_T;
|
||||
|
||||
/**@} end of group SCI2C_Structure*/
|
||||
|
||||
|
||||
@@ -3,21 +3,35 @@
|
||||
*
|
||||
* @brief This file contains all the functions prototypes for the SDIO firmware library
|
||||
*
|
||||
* @version V1.0.1
|
||||
* @version V1.0.2
|
||||
*
|
||||
* @date 2021-03-23
|
||||
* @date 2022-01-05
|
||||
*
|
||||
* @attention
|
||||
*
|
||||
* Copyright (C) 2020-2022 Geehy Semiconductor
|
||||
*
|
||||
* You may not use this file except in compliance with the
|
||||
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
|
||||
*
|
||||
* The program is only for reference, which is distributed in the hope
|
||||
* that it will be usefull and instructional for customers to develop
|
||||
* their software. Unless required by applicable law or agreed to in
|
||||
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
|
||||
* and limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __APM32F10X_SDIO_H
|
||||
#define __APM32F10X_SDIO_H
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
/** @addtogroup Peripherals_Library Standard Peripheral Library
|
||||
@{
|
||||
*/
|
||||
@@ -37,7 +51,7 @@ typedef enum
|
||||
{
|
||||
SDIO_CLOCK_EDGE_RISING = 0x00000000,
|
||||
SDIO_CLOCK_EDGE_FALLING = 0x00002000
|
||||
}SDIO_CLOCK_EDGE_T;
|
||||
} SDIO_CLOCK_EDGE_T;
|
||||
|
||||
/**
|
||||
* @brief SDIO clock bypass
|
||||
@@ -46,7 +60,7 @@ typedef enum
|
||||
{
|
||||
SDIO_CLOCK_BYPASS_DISABLE = 0x00000000,
|
||||
SDIO_CLOCK_BYPASS_ENABLE = 0x00000400
|
||||
}SDIO_CLOCK_BYPASS_T;
|
||||
} SDIO_CLOCK_BYPASS_T;
|
||||
|
||||
/**
|
||||
* @brief SDIO clock power save
|
||||
@@ -55,17 +69,17 @@ typedef enum
|
||||
{
|
||||
SDIO_CLOCK_POWER_SAVE_DISABLE = 0x00000000,
|
||||
SDIO_CLOCK_POWER_SAVE_ENABLE = 0x00000200
|
||||
}SDIO_CLOCK_POWER_SAVE_T;
|
||||
} SDIO_CLOCK_POWER_SAVE_T;
|
||||
|
||||
/**
|
||||
* @brief SDIO bus wide
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SDIO_BUSWIDE_1B = 0x00000000,
|
||||
SDIO_BUSWIDE_4B = 0x00000800,
|
||||
SDIO_BUSWIDE_8B = 0x00001000
|
||||
}SDIO_BUSWIDE_T;
|
||||
SDIO_BUS_WIDE_1B = 0x00000000,
|
||||
SDIO_BUS_WIDE_4B = 0x00000800,
|
||||
SDIO_BUS_WIDE_8B = 0x00001000
|
||||
} SDIO_BUS_WIDE_T;
|
||||
|
||||
/**
|
||||
* @brief SDIO hardware flow control
|
||||
@@ -74,7 +88,7 @@ typedef enum
|
||||
{
|
||||
SDIO_HARDWARE_FLOW_CONTROL_DISABLE = 0x00000000,
|
||||
SDIO_HARDWARE_FLOW_CONTROL_ENABLE = 0x00004000
|
||||
}SDIO_HARDWARE_FLOW_CONTROL_T;
|
||||
} SDIO_HARDWARE_FLOW_CONTROL_T;
|
||||
|
||||
/**
|
||||
* @brief SDIO power state
|
||||
@@ -83,7 +97,7 @@ typedef enum
|
||||
{
|
||||
SDIO_POWER_STATE_OFF = 0x00000000,
|
||||
SDIO_POWER_STATE_ON = 0x00000003
|
||||
}SDIO_POWER_STATE_T;
|
||||
} SDIO_POWER_STATE_T;
|
||||
|
||||
/**
|
||||
* @brief SDIO interrupt sources
|
||||
@@ -114,7 +128,7 @@ typedef enum
|
||||
SDIO_INT_RXDA = 0x00200000,
|
||||
SDIO_INT_SDIOINT = 0x00400000,
|
||||
SDIO_INT_ATAEND = 0x00800000
|
||||
}SDIO_INT_T;
|
||||
} SDIO_INT_T;
|
||||
|
||||
/**
|
||||
* @brief SDIO response
|
||||
@@ -124,7 +138,7 @@ typedef enum
|
||||
SDIO_RESPONSE_NO = 0x00000000,
|
||||
SDIO_RESPONSE_SHORT = 0x00000040,
|
||||
SDIO_RESPONSE_LONG = 0x000000C0
|
||||
}SDIO_RESPONSE_T;
|
||||
} SDIO_RESPONSE_T;
|
||||
|
||||
/**
|
||||
* @brief SDIO wait interrupt state
|
||||
@@ -134,7 +148,7 @@ typedef enum
|
||||
SDIO_WAIT_NO = 0x00000000,
|
||||
SDIO_WAIT_INT = 0x00000100,
|
||||
SDIO_WAIT_PEND = 0x00000200
|
||||
}SDIO_WAIT_T;
|
||||
} SDIO_WAIT_T;
|
||||
|
||||
/**
|
||||
* @brief SDIO CPSM state
|
||||
@@ -143,7 +157,7 @@ typedef enum
|
||||
{
|
||||
SDIO_CPSM_DISABLE = 0x00000000,
|
||||
SDIO_CPSM_ENABLE = 0x00000400
|
||||
}SDIO_CPSM_T;
|
||||
} SDIO_CPSM_T;
|
||||
|
||||
/**
|
||||
* @brief SDIO response registers
|
||||
@@ -154,7 +168,7 @@ typedef enum
|
||||
SDIO_RES2 = 0x00000004,
|
||||
SDIO_RES3 = 0x00000008,
|
||||
SDIO_RES4 = 0x0000000C
|
||||
}SDIO_RES_T;
|
||||
} SDIO_RES_T;
|
||||
|
||||
/**
|
||||
* @brief SDIO data block size
|
||||
@@ -176,16 +190,16 @@ typedef enum
|
||||
SDIO_DATA_BLOCKSIZE_496B = 0x000000C0,
|
||||
SDIO_DATA_BLOCKSIZE_8192B = 0x000000D0,
|
||||
SDIO_DATA_BLOCKSIZE_16384B = 0x000000E0
|
||||
}SDIO_DATA_BLOCKSIZE_T;
|
||||
} SDIO_DATA_BLOCKSIZE_T;
|
||||
|
||||
/**
|
||||
* @brief SDIO transfer direction
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SDIO_TRANSFER_DIR_TOCARD = 0x00000000,
|
||||
SDIO_TRANSFER_DIR_TOSDIO = 0x00000002
|
||||
}SDIO_TRANSFER_DIR_T;
|
||||
SDIO_TRANSFER_DIR_TO_CARD = 0x00000000,
|
||||
SDIO_TRANSFER_DIR_TO_SDIO = 0x00000002
|
||||
} SDIO_TRANSFER_DIR_T;
|
||||
|
||||
/**
|
||||
* @brief SDIO transfer type
|
||||
@@ -194,7 +208,7 @@ typedef enum
|
||||
{
|
||||
SDIO_TRANSFER_MODE_BLOCK = 0x00000000,
|
||||
SDIO_TRANSFER_MODE_STREAM = 0x00000004
|
||||
}SDIO_TRANSFER_MODE_T;
|
||||
} SDIO_TRANSFER_MODE_T;
|
||||
|
||||
/**
|
||||
* @brief SDIO DPSM state
|
||||
@@ -203,7 +217,7 @@ typedef enum
|
||||
{
|
||||
SDIO_DPSM_DISABLE = 0x00000000,
|
||||
SDIO_DPSM_ENABLE = 0x00000001
|
||||
}SDIO_DPSM_T;
|
||||
} SDIO_DPSM_T;
|
||||
|
||||
/**
|
||||
* @brief SDIO flag
|
||||
@@ -234,7 +248,7 @@ typedef enum
|
||||
SDIO_FLAG_RXDA = 0x00200000,
|
||||
SDIO_FLAG_SDIOINT = 0x00400000,
|
||||
SDIO_FLAG_ATAEND = 0x00800000
|
||||
}SDIO_FLAG_T;
|
||||
} SDIO_FLAG_T;
|
||||
|
||||
/**
|
||||
* @brief SDIO read wait mode
|
||||
@@ -243,7 +257,7 @@ typedef enum
|
||||
{
|
||||
SDIO_READ_WAIT_MODE_CLK = 0x00000001,
|
||||
SDIO_READ_WAIT_MODE_DATA2 = 0x00000000
|
||||
}SDIO_READ_WAIT_MODE_T;
|
||||
} SDIO_READ_WAIT_MODE_T;
|
||||
|
||||
/**@} end of group SDIO_Enumerations*/
|
||||
|
||||
@@ -255,52 +269,52 @@ typedef enum
|
||||
/** ------------ SDIO registers bit address in the alias region ----------- */
|
||||
#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
|
||||
|
||||
/* --- CLKCTRL Register ---*/
|
||||
/** --- CLKCTRL Register ---*/
|
||||
|
||||
/* Alias word address of CLKEN bit */
|
||||
/** Alias word address of CLKEN bit */
|
||||
#define CLKCTRL_OFFSET (SDIO_OFFSET + 0x04)
|
||||
#define CLKEN_BitNumber 0x08
|
||||
#define CLKCTRL_CLKEN_BB (PERIPH_BB_BASE + (CLKCTRL_OFFSET * 32) + (CLKEN_BitNumber * 4))
|
||||
|
||||
/* --- CMD Register ---*/
|
||||
/** --- CMD Register ---*/
|
||||
|
||||
/* Alias word address of SDIOSC bit */
|
||||
/** Alias word address of SDIOSC bit */
|
||||
#define CMD_OFFSET (SDIO_OFFSET + 0x0C)
|
||||
#define SDIOSC_BitNumber 0x0B
|
||||
#define CMD_SDIOSC_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSC_BitNumber * 4))
|
||||
|
||||
/* Alias word address of CMDCPEN bit */
|
||||
/** Alias word address of CMDCPEN bit */
|
||||
#define CMDCPEN_BitNumber 0x0C
|
||||
#define CMD_CMDCPEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (CMDCPEN_BitNumber * 4))
|
||||
|
||||
/* Alias word address of INTEN bit */
|
||||
/** Alias word address of INTEN bit */
|
||||
#define INTEN_BitNumber 0x0D
|
||||
#define CMD_INTEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (INTEN_BitNumber * 4))
|
||||
|
||||
/* Alias word address of ATACMD bit */
|
||||
/** Alias word address of ATACMD bit */
|
||||
#define ATACMD_BitNumber 0x0E
|
||||
#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
|
||||
|
||||
/* --- DCTRL Register ---*/
|
||||
/** --- DCTRL Register ---*/
|
||||
|
||||
/* Alias word address of DMAEN bit */
|
||||
/** Alias word address of DMAEN bit */
|
||||
#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
|
||||
#define DMAEN_BitNumber 0x03
|
||||
#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
|
||||
|
||||
/* Alias word address of RWSTR bit */
|
||||
/** Alias word address of RWSTR bit */
|
||||
#define RWSTR_BitNumber 0x08
|
||||
#define DCTRL_RWSTR_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTR_BitNumber * 4))
|
||||
|
||||
/* Alias word address of RWSTOP bit */
|
||||
/** Alias word address of RWSTOP bit */
|
||||
#define RWSTOP_BitNumber 0x09
|
||||
#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
|
||||
|
||||
/* Alias word address of RDWAIT bit */
|
||||
/** Alias word address of RDWAIT bit */
|
||||
#define RDWAIT_BitNumber 0x0A
|
||||
#define DCTRL_RDWAIT_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RDWAIT_BitNumber * 4))
|
||||
|
||||
/* Alias word address of SDIOF bit */
|
||||
/** Alias word address of SDIOF bit */
|
||||
#define SDIOF_BitNumber 0x0B
|
||||
#define DCTRL_SDIOF_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOF_BitNumber * 4))
|
||||
|
||||
@@ -318,10 +332,10 @@ typedef struct
|
||||
SDIO_CLOCK_EDGE_T clockEdge;
|
||||
SDIO_CLOCK_BYPASS_T clockBypass;
|
||||
SDIO_CLOCK_POWER_SAVE_T clockPowerSave;
|
||||
SDIO_BUSWIDE_T busWide;
|
||||
SDIO_BUS_WIDE_T busWide;
|
||||
SDIO_HARDWARE_FLOW_CONTROL_T hardwareFlowControl;
|
||||
uint8_t clockDiv;
|
||||
}SDIO_Config_T;
|
||||
} SDIO_Config_T;
|
||||
|
||||
/**
|
||||
* @brief SDIO CMD Config structure definition
|
||||
@@ -333,7 +347,7 @@ typedef struct
|
||||
SDIO_RESPONSE_T response;
|
||||
SDIO_WAIT_T wait;
|
||||
SDIO_CPSM_T CPSM;
|
||||
}SDIO_CMDConfig_T;
|
||||
} SDIO_CmdConfig_T;
|
||||
|
||||
/**
|
||||
* @brief SDIO Data Config structure definition
|
||||
@@ -346,7 +360,7 @@ typedef struct
|
||||
SDIO_TRANSFER_DIR_T transferDir;
|
||||
SDIO_TRANSFER_MODE_T transferMode;
|
||||
SDIO_DPSM_T DPSM;
|
||||
}SDIO_DataConfig_T;
|
||||
} SDIO_DataConfig_T;
|
||||
|
||||
/**@} end of group SDIO_Structure*/
|
||||
|
||||
@@ -357,8 +371,8 @@ typedef struct
|
||||
|
||||
/** SDIO reset and configuration */
|
||||
void SDIO_Reset(void);
|
||||
void SDIO_Config(SDIO_Config_T* sdioConfig);
|
||||
void SDIO_ConfigStructInit(SDIO_Config_T* sdioConfig);
|
||||
void SDIO_Config(SDIO_Config_T *sdioConfig);
|
||||
void SDIO_ConfigStructInit(SDIO_Config_T *sdioConfig);
|
||||
void SDIO_EnableClock(void);
|
||||
void SDIO_DisableClock(void);
|
||||
void SDIO_ConfigPowerState(SDIO_POWER_STATE_T powerState);
|
||||
@@ -369,14 +383,14 @@ void SDIO_EnableDMA(void);
|
||||
void SDIO_DisableDMA(void);
|
||||
|
||||
/** Command */
|
||||
void SDIO_TxCommand(SDIO_CMDConfig_T *cmdConfig);
|
||||
void SDIO_TxCommandStructInit(SDIO_CMDConfig_T* cmdconfig);
|
||||
void SDIO_TxCommand(SDIO_CmdConfig_T *cmdConfig);
|
||||
void SDIO_TxCommandStructInit(SDIO_CmdConfig_T *cmdconfig);
|
||||
uint8_t SDIO_ReadCommandResponse(void);
|
||||
uint32_t SDIO_ReadResponse(SDIO_RES_T res);
|
||||
|
||||
/** SDIO data configuration */
|
||||
void SDIO_ConfigData(SDIO_DataConfig_T* dataConfig);
|
||||
void SDIO_ConfigDataStructInit(SDIO_DataConfig_T* dataConfig);
|
||||
void SDIO_ConfigData(SDIO_DataConfig_T *dataConfig);
|
||||
void SDIO_ConfigDataStructInit(SDIO_DataConfig_T *dataConfig);
|
||||
uint32_t SDIO_ReadDataCounter(void);
|
||||
void SDIO_WriteData(uint32_t data);
|
||||
uint32_t SDIO_ReadData(void);
|
||||
|
||||
@@ -3,21 +3,35 @@
|
||||
*
|
||||
* @brief This file contains all the functions prototypes for the SPI firmware library
|
||||
*
|
||||
* @version V1.0.1
|
||||
* @version V1.0.2
|
||||
*
|
||||
* @date 2021-03-23
|
||||
* @date 2022-01-05
|
||||
*
|
||||
* @attention
|
||||
*
|
||||
* Copyright (C) 2020-2022 Geehy Semiconductor
|
||||
*
|
||||
* You may not use this file except in compliance with the
|
||||
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
|
||||
*
|
||||
* The program is only for reference, which is distributed in the hope
|
||||
* that it will be usefull and instructional for customers to develop
|
||||
* their software. Unless required by applicable law or agreed to in
|
||||
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
|
||||
* and limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __APM32F10X_SPI_H
|
||||
#define __APM32F10X_SPI_H
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
/** @addtogroup Peripherals_Library Standard Peripheral Library
|
||||
@{
|
||||
*/
|
||||
@@ -39,7 +53,7 @@ typedef enum
|
||||
SPI_DIRECTION_2LINES_RXONLY = 0x0400,
|
||||
SPI_DIRECTION_1LINE_RX = 0x8000,
|
||||
SPI_DIRECTION_1LINE_TX = 0xC000
|
||||
}SPI_DIRECTION_T;
|
||||
} SPI_DIRECTION_T;
|
||||
|
||||
/**
|
||||
* @brief SPI mode
|
||||
@@ -48,7 +62,7 @@ typedef enum
|
||||
{
|
||||
SPI_MODE_MASTER = 0x0104,
|
||||
SPI_MODE_SLAVE = 0x0000
|
||||
}SPI_MODE_T;
|
||||
} SPI_MODE_T;
|
||||
|
||||
/**
|
||||
* @brief SPI Data length
|
||||
@@ -57,7 +71,7 @@ typedef enum
|
||||
{
|
||||
SPI_DATA_LENGTH_16B = 0x0800,
|
||||
SPI_DATA_LENGTH_8B = 0x0000
|
||||
}SPI_DATA_LENGTH_T;
|
||||
} SPI_DATA_LENGTH_T;
|
||||
|
||||
/**
|
||||
* @brief SPI Clock Polarity
|
||||
@@ -66,7 +80,7 @@ typedef enum
|
||||
{
|
||||
SPI_CLKPOL_LOW = 0x0000,
|
||||
SPI_CLKPOL_HIGH = 0x0002
|
||||
}SPI_CLKPOL_T;
|
||||
} SPI_CLKPOL_T;
|
||||
|
||||
/**
|
||||
* @brief SPI Clock Phase
|
||||
@@ -75,7 +89,7 @@ typedef enum
|
||||
{
|
||||
SPI_CLKPHA_1EDGE = 0x0000,
|
||||
SPI_CLKPHA_2EDGE = 0x0001
|
||||
}SPI_CLKPHA_T;
|
||||
} SPI_CLKPHA_T;
|
||||
|
||||
/**
|
||||
* @brief SPI Slave Select management
|
||||
@@ -84,7 +98,7 @@ typedef enum
|
||||
{
|
||||
SPI_NSS_SOFT = 0x0200,
|
||||
SPI_NSS_HARD = 0x0000
|
||||
}SPI_NSS_T;
|
||||
} SPI_NSS_T;
|
||||
|
||||
/**
|
||||
* @brief SPI BaudRate Prescaler
|
||||
@@ -99,7 +113,7 @@ typedef enum
|
||||
SPI_BAUDRATE_DIV_64 = 0x0028,
|
||||
SPI_BAUDRATE_DIV_128 = 0x0030,
|
||||
SPI_BAUDRATE_DIV_256 = 0x0038,
|
||||
}SPI_BAUDRATE_DIV_T;
|
||||
} SPI_BAUDRATE_DIV_T;
|
||||
|
||||
/**
|
||||
* @brief SPI MSB LSB transmission
|
||||
@@ -108,7 +122,7 @@ typedef enum
|
||||
{
|
||||
SPI_FIRSTBIT_MSB = 0x0000,
|
||||
SPI_FIRSTBIT_LSB = 0x0080
|
||||
}SPI_FIRSTBIT_T;
|
||||
} SPI_FIRSTBIT_T;
|
||||
|
||||
/**
|
||||
* @brief I2S Mode
|
||||
@@ -119,7 +133,7 @@ typedef enum
|
||||
I2S_MODE_SLAVE_RX = 0x0100,
|
||||
I2S_MODE_MASTER_TX = 0x0200,
|
||||
I2S_MODE_MASTER_RX = 0x0300
|
||||
}I2S_MODE_T;
|
||||
} I2S_MODE_T;
|
||||
|
||||
/**
|
||||
* @brief I2S Standard
|
||||
@@ -131,7 +145,7 @@ typedef enum
|
||||
I2S_STANDARD_LSB = 0x0020,
|
||||
I2S_STANDARD_PCMSHORT = 0x0030,
|
||||
I2S_STANDARD_PCMLONG = 0x00B0
|
||||
}I2S_STANDARD_T;
|
||||
} I2S_STANDARD_T;
|
||||
|
||||
/**
|
||||
* @brief I2S data length
|
||||
@@ -151,7 +165,7 @@ typedef enum
|
||||
{
|
||||
I2S_MCLK_OUTPUT_DISABLE = 0x0000,
|
||||
I2S_MCLK_OUTPUT_ENABLE = 0x0200,
|
||||
}I2S_MCLK_OUTPUT_T;
|
||||
} I2S_MCLK_OUTPUT_T;
|
||||
|
||||
/**
|
||||
* @brief I2S Audio divider
|
||||
@@ -168,7 +182,7 @@ typedef enum
|
||||
I2S_AUDIO_DIV_11K = 11025,
|
||||
I2S_AUDIO_DIV_8K = 8000,
|
||||
I2S_AUDIO_DIV_DEFAULT = 2
|
||||
}I2S_AUDIO_DIV_T;
|
||||
} I2S_AUDIO_DIV_T;
|
||||
|
||||
/**
|
||||
* @brief I2S Clock Polarity
|
||||
@@ -177,7 +191,7 @@ typedef enum
|
||||
{
|
||||
I2S_CLKPOL_LOW = 0x0000,
|
||||
I2S_CLKPOL_HIGH = 0x0008
|
||||
}I2S_CLKPOL_T;
|
||||
} I2S_CLKPOL_T;
|
||||
|
||||
/**
|
||||
* @brief SPI Direction select
|
||||
@@ -186,7 +200,7 @@ typedef enum
|
||||
{
|
||||
SPI_DIRECTION_RX = 0xBFFF,
|
||||
SPI_DIRECTION_TX = 0x4000
|
||||
}SPI_DIRECTION_SELECT_T;
|
||||
} SPI_DIRECTION_SELECT_T;
|
||||
|
||||
/**
|
||||
* @brief SPI interrupts definition
|
||||
@@ -200,7 +214,7 @@ typedef enum
|
||||
SPI_INT_CRCE = 0x2010,
|
||||
SPI_INT_ME = 0x2020,
|
||||
I2S_INT_UDR = 0x2008
|
||||
}SPI_I2S_INT_T;
|
||||
} SPI_I2S_INT_T;
|
||||
|
||||
/**
|
||||
* @brief SPI flags definition
|
||||
@@ -215,7 +229,7 @@ typedef enum
|
||||
SPI_FLAG_ME = 0x0020,
|
||||
SPI_FLAG_OVR = 0x0040,
|
||||
SPI_FLAG_BSY = 0x0080
|
||||
}SPI_FLAG_T;
|
||||
} SPI_FLAG_T;
|
||||
|
||||
/**
|
||||
* @brief SPI I2S DMA requests
|
||||
@@ -224,7 +238,7 @@ typedef enum
|
||||
{
|
||||
SPI_I2S_DMA_REQ_TX = 0x0002,
|
||||
SPI_I2S_DMA_REQ_RX = 0x0001
|
||||
}SPI_I2S_DMA_REQ_T;
|
||||
} SPI_I2S_DMA_REQ_T;
|
||||
|
||||
/**@} end of group SPI_Enumerations*/
|
||||
|
||||
@@ -247,7 +261,7 @@ typedef struct
|
||||
SPI_DIRECTION_T direction;
|
||||
SPI_BAUDRATE_DIV_T baudrateDiv;
|
||||
uint16_t crcPolynomial;
|
||||
}SPI_Config_T;
|
||||
} SPI_Config_T;
|
||||
|
||||
/**
|
||||
* @brief I2S Config structure definition
|
||||
@@ -260,7 +274,7 @@ typedef struct
|
||||
I2S_MCLK_OUTPUT_T MCLKOutput;
|
||||
I2S_AUDIO_DIV_T audioDiv;
|
||||
I2S_CLKPOL_T polarity;
|
||||
}I2S_Config_T;
|
||||
} I2S_Config_T;
|
||||
|
||||
/**@} end of group SPI_Structure*/
|
||||
|
||||
@@ -269,44 +283,44 @@ typedef struct
|
||||
*/
|
||||
|
||||
/** Reset and Configuration */
|
||||
void SPI_I2S_Reset(SPI_T* spi);
|
||||
void SPI_Config(SPI_T* spi, SPI_Config_T* spiConfig);
|
||||
void I2S_Config(SPI_T* spi, I2S_Config_T* i2sConfig);
|
||||
void SPI_ConfigStructInit(SPI_Config_T* spiConfig);
|
||||
void I2S_ConfigStructInit(I2S_Config_T* i2sConfig);
|
||||
void SPI_Enable(SPI_T* spi);
|
||||
void SPI_Disable(SPI_T* spi);
|
||||
void I2S_Enable(SPI_T* spi);
|
||||
void I2S_Disable(SPI_T* spi);
|
||||
void SPI_I2S_Reset(SPI_T *spi);
|
||||
void SPI_Config(SPI_T *spi, SPI_Config_T *spiConfig);
|
||||
void I2S_Config(SPI_T *spi, I2S_Config_T *i2sConfig);
|
||||
void SPI_ConfigStructInit(SPI_Config_T *spiConfig);
|
||||
void I2S_ConfigStructInit(I2S_Config_T *i2sConfig);
|
||||
void SPI_Enable(SPI_T *spi);
|
||||
void SPI_Disable(SPI_T *spi);
|
||||
void I2S_Enable(SPI_T *spi);
|
||||
void I2S_Disable(SPI_T *spi);
|
||||
|
||||
void SPI_I2S_TxData(SPI_T* spi, uint16_t data);
|
||||
uint16_t SPI_I2S_RxData(SPI_T* spi);
|
||||
void SPI_SetSoftwareNSS(SPI_T* spi);
|
||||
void SPI_ResetSoftwareNSS(SPI_T* spi);
|
||||
void SPI_EnableSSOutput(SPI_T* spi);
|
||||
void SPI_DisableSSOutput(SPI_T* spi);
|
||||
void SPI_ConfigDataSize(SPI_T* spi, uint16_t dataSize);
|
||||
void SPI_I2S_TxData(SPI_T *spi, uint16_t data);
|
||||
uint16_t SPI_I2S_RxData(SPI_T *spi);
|
||||
void SPI_SetSoftwareNSS(SPI_T *spi);
|
||||
void SPI_ResetSoftwareNSS(SPI_T *spi);
|
||||
void SPI_EnableSSOutput(SPI_T *spi);
|
||||
void SPI_DisableSSOutput(SPI_T *spi);
|
||||
void SPI_ConfigDataSize(SPI_T *spi, SPI_DATA_LENGTH_T length);
|
||||
|
||||
/** DMA */
|
||||
void SPI_I2S_EnableDMA(SPI_T* spi, SPI_I2S_DMA_REQ_T dmaReq);
|
||||
void SPI_I2S_DisableDMA(SPI_T* spi, SPI_I2S_DMA_REQ_T dmaReq);
|
||||
void SPI_I2S_EnableDMA(SPI_T *spi, SPI_I2S_DMA_REQ_T dmaReq);
|
||||
void SPI_I2S_DisableDMA(SPI_T *spi, SPI_I2S_DMA_REQ_T dmaReq);
|
||||
|
||||
/** CRC */
|
||||
void SPI_TxCRC(SPI_T* spi);
|
||||
void SPI_EnableCRC(SPI_T* spi);
|
||||
void SPI_DisableCRC(SPI_T* spi);
|
||||
uint16_t SPI_ReadTxCRC(SPI_T* spi);
|
||||
uint16_t SPI_ReadRxCRC(SPI_T* spi);
|
||||
uint16_t SPI_ReadCRCPolynomial(SPI_T* spi);
|
||||
void SPI_ConfigBiDirectionalLine(SPI_T* spi, SPI_DIRECTION_SELECT_T direction);
|
||||
void SPI_TxCRC(SPI_T *spi);
|
||||
void SPI_EnableCRC(SPI_T *spi);
|
||||
void SPI_DisableCRC(SPI_T *spi);
|
||||
uint16_t SPI_ReadTxCRC(SPI_T *spi);
|
||||
uint16_t SPI_ReadRxCRC(SPI_T *spi);
|
||||
uint16_t SPI_ReadCRCPolynomial(SPI_T *spi);
|
||||
void SPI_ConfigBiDirectionalLine(SPI_T *spi, SPI_DIRECTION_SELECT_T direction);
|
||||
|
||||
/** Interrupts and flag */
|
||||
void SPI_I2S_EnableInterrupt(SPI_T* spi, SPI_I2S_INT_T interrupt);
|
||||
void SPI_I2S_DisableInterrupt(SPI_T* spi, SPI_I2S_INT_T interrupt);
|
||||
uint8_t SPI_I2S_ReadStatusFlag(SPI_T* spi, SPI_FLAG_T flag);
|
||||
void SPI_I2S_ClearStatusFlag(SPI_T* spi, SPI_FLAG_T flag);
|
||||
uint8_t SPI_I2S_ReadIntFlag(SPI_T* spi, SPI_I2S_INT_T flag);
|
||||
void SPI_I2S_ClearIntFlag(SPI_T* spi, SPI_I2S_INT_T flag);
|
||||
void SPI_I2S_EnableInterrupt(SPI_T *spi, SPI_I2S_INT_T interrupt);
|
||||
void SPI_I2S_DisableInterrupt(SPI_T *spi, SPI_I2S_INT_T interrupt);
|
||||
uint8_t SPI_I2S_ReadStatusFlag(SPI_T *spi, SPI_FLAG_T flag);
|
||||
void SPI_I2S_ClearStatusFlag(SPI_T *spi, SPI_FLAG_T flag);
|
||||
uint8_t SPI_I2S_ReadIntFlag(SPI_T *spi, SPI_I2S_INT_T flag);
|
||||
void SPI_I2S_ClearIntFlag(SPI_T *spi, SPI_I2S_INT_T flag);
|
||||
|
||||
/**@} end of group SPI_Fuctions*/
|
||||
/**@} end of group SPI_Driver*/
|
||||
|
||||
@@ -1,22 +1,36 @@
|
||||
/*!
|
||||
* @file apm32f10x_tmr.h
|
||||
* @file apm32f10x_tmr.h
|
||||
*
|
||||
* @brief This file contains all the functions prototypes for the TMR firmware library.
|
||||
* @brief This file contains all the functions prototypes for the TMR firmware library.
|
||||
*
|
||||
* @version V1.0.1
|
||||
* @version V1.0.2
|
||||
*
|
||||
* @date 2021-03-23
|
||||
* @date 2022-01-05
|
||||
*
|
||||
* @attention
|
||||
*
|
||||
* Copyright (C) 2020-2022 Geehy Semiconductor
|
||||
*
|
||||
* You may not use this file except in compliance with the
|
||||
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
|
||||
*
|
||||
* The program is only for reference, which is distributed in the hope
|
||||
* that it will be usefull and instructional for customers to develop
|
||||
* their software. Unless required by applicable law or agreed to in
|
||||
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
|
||||
* and limitations under the License.
|
||||
*/
|
||||
#ifndef __APM32F10X_TMR_H
|
||||
#define __APM32F10X_TMR_H
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
/** @addtogroup Peripherals_Library Standard Peripheral Library
|
||||
@{
|
||||
*/
|
||||
@@ -63,7 +77,7 @@ typedef enum
|
||||
TMR_OC_MODE_LOWLEVEL = 0x04,
|
||||
TMR_OC_MODE_HIGHLEVEL = 0x05,
|
||||
TMR_OC_MODE_PWM1 = 0x06,
|
||||
TMR_OC_MODE_PWM2 = 0x07,
|
||||
TMR_OC_MODE_PWM2 = 0x07
|
||||
} TMR_OC_MODE_T;
|
||||
|
||||
/**
|
||||
@@ -353,9 +367,9 @@ typedef enum
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TMR_PRESCALER_RELOAD_UPDATA,
|
||||
TMR_PRESCALER_RELOAD_IMMEDIATE
|
||||
} TMR_PRESCALER_RELOAD_T;
|
||||
TMR_PSC_RELOAD_UPDATE,
|
||||
TMR_PSC_RELOAD_IMMEDIATE
|
||||
} TMR_PSC_RELOAD_T;
|
||||
|
||||
/**
|
||||
* @brief TMR Encoder Mode
|
||||
@@ -444,7 +458,7 @@ typedef enum
|
||||
TMR_SLAVE_MODE_RESET = 0x04,
|
||||
TMR_SLAVE_MODE_GATED = 0x05,
|
||||
TMR_SLAVE_MODE_TRIGGER = 0x06,
|
||||
TMR_SLAVE_MODE_EXTERNALL = 0x07
|
||||
TMR_SLAVE_MODE_EXTERNAL1 = 0x07
|
||||
} TMR_SLAVE_MODE_T;
|
||||
|
||||
/**
|
||||
@@ -532,124 +546,124 @@ typedef struct
|
||||
*/
|
||||
|
||||
/** Reset and Configuration */
|
||||
void TMR_Reset(TMR_T* tmr);
|
||||
void TMR_ConfigTimeBase(TMR_T* tmr, TMR_BaseConfig_T *baseConfig);
|
||||
void TMR_ConfigOC1(TMR_T* tmr, TMR_OCConfig_T *OC1Config);
|
||||
void TMR_ConfigOC2(TMR_T* tmr, TMR_OCConfig_T *OC2Config);
|
||||
void TMR_ConfigOC3(TMR_T* tmr, TMR_OCConfig_T *OC3Config);
|
||||
void TMR_ConfigOC4(TMR_T* tmr, TMR_OCConfig_T *OC4Config);
|
||||
void TMR_ConfigIC(TMR_T* tmr, TMR_ICConfig_T *ICConfig);
|
||||
void TMR_ConfigBDT(TMR_T* tmr, TMR_BDTConfig_T *BDTConfig);
|
||||
void TMR_Reset(TMR_T *tmr);
|
||||
void TMR_ConfigTimeBase(TMR_T *tmr, TMR_BaseConfig_T *baseConfig);
|
||||
void TMR_ConfigOC1(TMR_T *tmr, TMR_OCConfig_T *OCConfig);
|
||||
void TMR_ConfigOC2(TMR_T *tmr, TMR_OCConfig_T *OCConfig);
|
||||
void TMR_ConfigOC3(TMR_T *tmr, TMR_OCConfig_T *OCConfig);
|
||||
void TMR_ConfigOC4(TMR_T *tmr, TMR_OCConfig_T *OCConfig);
|
||||
void TMR_ConfigIC(TMR_T *tmr, TMR_ICConfig_T *ICConfig);
|
||||
void TMR_ConfigBDT(TMR_T *tmr, TMR_BDTConfig_T *BDTConfig);
|
||||
void TMR_ConfigTimeBaseStructInit(TMR_BaseConfig_T *baseConfig);
|
||||
void TMR_ConfigOCStructInit(TMR_OCConfig_T *OCConfig);
|
||||
void TMR_ConfigICStructInit(TMR_ICConfig_T *ICConfig);
|
||||
void TMR_ConfigBDTStructInit( TMR_BDTConfig_T *BDTConfig);
|
||||
void TMR_Enable(TMR_T* tmr);
|
||||
void TMR_Disable(TMR_T* tmr);
|
||||
void TMR_ConfigBDTStructInit(TMR_BDTConfig_T *BDTConfig);
|
||||
void TMR_ConfigSinglePulseMode(TMR_T *tmr, TMR_SPM_T singlePulseMode);
|
||||
void TMR_ConfigClockDivision(TMR_T *tmr, TMR_CLOCK_DIV_T clockDivision);
|
||||
void TMR_Enable(TMR_T *tmr);
|
||||
void TMR_Disable(TMR_T *tmr);
|
||||
|
||||
/* PWM Configuration */
|
||||
void TMR_ConfigPWM(TMR_T* tmr, TMR_ICConfig_T *PWMConfig);
|
||||
void TMR_EnablePWMOutputs(TMR_T* tmr);
|
||||
void TMR_DisablePWMOutputs(TMR_T* tmr);
|
||||
/** PWM Configuration */
|
||||
void TMR_ConfigPWM(TMR_T *tmr, TMR_ICConfig_T *PWMConfig);
|
||||
void TMR_EnablePWMOutputs(TMR_T *tmr);
|
||||
void TMR_DisablePWMOutputs(TMR_T *tmr);
|
||||
|
||||
/** DMA */
|
||||
void TMR_ConfigDMA(TMR_T* tmr, TMR_DMA_BASE_T baseAddress, TMR_DMA_BURSTLENGTH_T burstLength);
|
||||
void TMR_EnableDMASoure(TMR_T* tmr, uint16_t dmaSource);
|
||||
void TMR_DisableDMASoure(TMR_T* tmr, uint16_t dmaSource);
|
||||
void TMR_ConfigDMA(TMR_T *tmr, TMR_DMA_BASE_T baseAddress, TMR_DMA_BURSTLENGTH_T burstLength);
|
||||
void TMR_EnableDMASoure(TMR_T *tmr, uint16_t dmaSource);
|
||||
void TMR_DisableDMASoure(TMR_T *tmr, uint16_t dmaSource);
|
||||
|
||||
/** Configuration */
|
||||
void TMR_ConfigInternalClock(TMR_T* tmr);
|
||||
void TMR_ConfigIntTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource);
|
||||
void TMR_ConfigTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource,
|
||||
TMR_IC_POLARITY_T ICpolarity, uint16_t ICfilter);
|
||||
void TMR_ConfigETRClockMode1(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler,
|
||||
void TMR_ConfigInternalClock(TMR_T *tmr);
|
||||
void TMR_ConfigIntTrigExternalClock(TMR_T *tmr, TMR_TRIGGER_SOURCE_T triggerSource);
|
||||
void TMR_ConfigTrigExternalClock(TMR_T *tmr, TMR_TRIGGER_SOURCE_T triggerSource,
|
||||
TMR_IC_POLARITY_T ICpolarity, uint16_t ICfilter);
|
||||
void TMR_ConfigETRClockMode1(TMR_T *tmr, TMR_EXTTRG_PSC_T prescaler,
|
||||
TMR_EXTTRG_POL_T polarity, uint16_t filter);
|
||||
void TMR_ConfigETRClockMode2(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler,
|
||||
void TMR_ConfigETRClockMode2(TMR_T *tmr, TMR_EXTTRG_PSC_T prescaler,
|
||||
TMR_EXTTRG_POL_T polarity, uint16_t filter);
|
||||
void TMR_ConfigETR(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler,
|
||||
void TMR_ConfigETR(TMR_T *tmr, TMR_EXTTRG_PSC_T prescaler,
|
||||
TMR_EXTTRG_POL_T polarity, uint16_t filter);
|
||||
void TMR_ConfigPrescaler(TMR_T* tmr, uint16_t prescaler, TMR_PRESCALER_RELOAD_T pscReloadMode);
|
||||
void TMR_ConfigCounterMode(TMR_T* tmr, TMR_COUNTER_MODE_T countMode);
|
||||
void TMR_SelectInputTrigger(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSouce);
|
||||
void TMR_ConfigEncodeInterface(TMR_T* tmr, TMR_ENCODER_MODE_T encodeMode, TMR_IC_POLARITY_T IC1Polarity,
|
||||
void TMR_ConfigPrescaler(TMR_T *tmr, uint16_t prescaler, TMR_PSC_RELOAD_T pscReloadMode);
|
||||
void TMR_ConfigCounterMode(TMR_T *tmr, TMR_COUNTER_MODE_T countMode);
|
||||
void TMR_SelectInputTrigger(TMR_T *tmr, TMR_TRIGGER_SOURCE_T triggerSouce);
|
||||
void TMR_ConfigEncodeInterface(TMR_T *tmr, TMR_ENCODER_MODE_T encodeMode, TMR_IC_POLARITY_T IC1Polarity,
|
||||
TMR_IC_POLARITY_T IC2Polarity);
|
||||
void TMR_ConfigForcedOC1(TMR_T* tmr,TMR_FORCED_ACTION_T forcesAction);
|
||||
void TMR_ConfigForcedOC2(TMR_T* tmr,TMR_FORCED_ACTION_T forcesAction);
|
||||
void TMR_ConfigForcedOC3(TMR_T* tmr,TMR_FORCED_ACTION_T forcesAction);
|
||||
void TMR_ConfigForcedOC4(TMR_T* tmr,TMR_FORCED_ACTION_T forcesAction);
|
||||
void TMR_EnableAUTOReload(TMR_T* tmr);
|
||||
void TMR_DisableAUTOReload(TMR_T* tmr);
|
||||
void TMR_EnableSelectCOM(TMR_T* tmr);
|
||||
void TMR_DisableSelectCOM(TMR_T* tmr);
|
||||
void TMR_EnableCCDMA(TMR_T* tmr);
|
||||
void TMR_DisableCCDMA(TMR_T* tmr);
|
||||
void TMR_EnableCCPreload(TMR_T* tmr);
|
||||
void TMR_DisableCCPreload(TMR_T* tmr);
|
||||
void TMR_ConfigOC1Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload);
|
||||
void TMR_ConfigOC2Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload);
|
||||
void TMR_ConfigOC3Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload);
|
||||
void TMR_ConfigOC4Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload);
|
||||
void TMR_ConfigOC1Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast);
|
||||
void TMR_ConfigOC2Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast);
|
||||
void TMR_ConfigOC3Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast);
|
||||
void TMR_ConfigOC4Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast);
|
||||
void TMR_ClearOC1Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear);
|
||||
void TMR_ClearOC2Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear);
|
||||
void TMR_ClearOC3Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear);
|
||||
void TMR_ClearOC4Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear);
|
||||
void TMR_ConfigOC1Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity);
|
||||
void TMR_ConfigOC1NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T OCNPolarity);
|
||||
void TMR_ConfigOC2Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity);
|
||||
void TMR_ConfigOC2NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T OCNPolarity);
|
||||
void TMR_ConfigOC3Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity);
|
||||
void TMR_ConfigOC3NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T OCNPolarity);
|
||||
void TMR_ConfigOC4Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity);
|
||||
void TMR_EnableCCxChannel(TMR_T* tmr,TMR_CHANNEL_T channel);
|
||||
void TMR_DisableCCxChannel(TMR_T* tmr,TMR_CHANNEL_T channel);
|
||||
void TMR_EnableCCxNChannel(TMR_T* tmr,TMR_CHANNEL_T channel);
|
||||
void TMR_DisableCCxNChannel(TMR_T* tmr,TMR_CHANNEL_T channel);
|
||||
void TMR_SelectOCxMode(TMR_T* tmr, TMR_CHANNEL_T channel, TMR_OC_MODE_T OCMode);
|
||||
void TMR_EnableNoUpdate(TMR_T* tmr);
|
||||
void TMR_DisableNoUpdate(TMR_T* tmr);
|
||||
void TMR_ConfigUPdateRequest(TMR_T* tmr, TMR_UPDATE_SOURCE_T updateSource);
|
||||
void TMR_EnableHallSensor(TMR_T* tmr);
|
||||
void TMR_DisableHallSensor(TMR_T* tmr);
|
||||
void TMR_SelectSinglePulseMode(TMR_T* tmr, TMR_SPM_T singlePulseMode);
|
||||
void TMR_SelectOutputTrigger(TMR_T* tmr, TMR_TRGO_SOURCE_T TRGOSource);
|
||||
void TMR_SelectSlaveMode(TMR_T* tmr, TMR_SLAVE_MODE_T slaveMode);
|
||||
void TMR_EnableMasterSlaveMode(TMR_T* tmr);
|
||||
void TMR_DisableMasterSlaveMode(TMR_T* tmr);
|
||||
void TMR_ConfigCounter(TMR_T* tmr, uint16_t counter);
|
||||
void TMR_ConfigAutoreload(TMR_T* tmr, uint16_t autoReload);
|
||||
void TMR_ConfigCompare1(TMR_T* tmr, uint16_t compare1);
|
||||
void TMR_ConfigCompare2(TMR_T* tmr, uint16_t compare2);
|
||||
void TMR_ConfigCompare3(TMR_T* tmr, uint16_t compare3);
|
||||
void TMR_ConfigCompare4(TMR_T* tmr, uint16_t compare4);
|
||||
void TMR_ConfigIC1Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler);
|
||||
void TMR_ConfigIC2Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler);
|
||||
void TMR_ConfigIC3Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler);
|
||||
void TMR_ConfigIC4Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler);
|
||||
void TMR_ConfigClockDivision(TMR_T* tmr, TMR_CLOCK_DIV_T clockDivision);
|
||||
uint16_t TMR_ReadCaputer1(TMR_T* tmr);
|
||||
uint16_t TMR_ReadCaputer2(TMR_T* tmr);
|
||||
uint16_t TMR_ReadCaputer3(TMR_T* tmr);
|
||||
uint16_t TMR_ReadCaputer4(TMR_T* tmr);
|
||||
uint16_t TMR_ReadCounter(TMR_T* tmr);
|
||||
uint16_t TMR_ReadPrescaler(TMR_T* tmr);
|
||||
void TMR_ConfigForcedOC1(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction);
|
||||
void TMR_ConfigForcedOC2(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction);
|
||||
void TMR_ConfigForcedOC3(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction);
|
||||
void TMR_ConfigForcedOC4(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction);
|
||||
void TMR_EnableAutoReload(TMR_T *tmr);
|
||||
void TMR_DisableAutoReload(TMR_T *tmr);
|
||||
void TMR_EnableSelectCOM(TMR_T *tmr);
|
||||
void TMR_DisableSelectCOM(TMR_T *tmr);
|
||||
void TMR_EnableCCDMA(TMR_T *tmr);
|
||||
void TMR_DisableCCDMA(TMR_T *tmr);
|
||||
void TMR_EnableCCPreload(TMR_T *tmr);
|
||||
void TMR_DisableCCPreload(TMR_T *tmr);
|
||||
void TMR_ConfigOC1Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload);
|
||||
void TMR_ConfigOC2Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload);
|
||||
void TMR_ConfigOC3Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload);
|
||||
void TMR_ConfigOC4Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload);
|
||||
void TMR_ConfigOC1Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast);
|
||||
void TMR_ConfigOC2Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast);
|
||||
void TMR_ConfigOC3Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast);
|
||||
void TMR_ConfigOC4Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast);
|
||||
void TMR_ClearOC1Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear);
|
||||
void TMR_ClearOC2Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear);
|
||||
void TMR_ClearOC3Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear);
|
||||
void TMR_ClearOC4Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear);
|
||||
void TMR_ConfigOC1Polarity(TMR_T *tmr, TMR_OC_POLARITY_T OCPolarity);
|
||||
void TMR_ConfigOC1NPolarity(TMR_T *tmr, TMR_OC_NPOLARITY_T OCNPolarity);
|
||||
void TMR_ConfigOC2Polarity(TMR_T *tmr, TMR_OC_POLARITY_T OCPolarity);
|
||||
void TMR_ConfigOC2NPolarity(TMR_T *tmr, TMR_OC_NPOLARITY_T OCNPolarity);
|
||||
void TMR_ConfigOC3Polarity(TMR_T *tmr, TMR_OC_POLARITY_T OCPolarity);
|
||||
void TMR_ConfigOC3NPolarity(TMR_T *tmr, TMR_OC_NPOLARITY_T OCNPolarity);
|
||||
void TMR_ConfigOC4Polarity(TMR_T *tmr, TMR_OC_POLARITY_T OCPolarity);
|
||||
void TMR_EnableCCxChannel(TMR_T *tmr, TMR_CHANNEL_T channel);
|
||||
void TMR_DisableCCxChannel(TMR_T *tmr, TMR_CHANNEL_T channel);
|
||||
void TMR_EnableCCxNChannel(TMR_T *tmr, TMR_CHANNEL_T channel);
|
||||
void TMR_DisableCCxNChannel(TMR_T *tmr, TMR_CHANNEL_T channel);
|
||||
void TMR_SelectOCxMode(TMR_T *tmr, TMR_CHANNEL_T channel, TMR_OC_MODE_T OCMode);
|
||||
void TMR_EnableUpdate(TMR_T *tmr);
|
||||
void TMR_DisableUpdate(TMR_T *tmr);
|
||||
void TMR_ConfigUpdateRequest(TMR_T *tmr, TMR_UPDATE_SOURCE_T updateSource);
|
||||
void TMR_EnableHallSensor(TMR_T *tmr);
|
||||
void TMR_DisableHallSensor(TMR_T *tmr);
|
||||
void TMR_SelectOutputTrigger(TMR_T *tmr, TMR_TRGO_SOURCE_T TRGOSource);
|
||||
void TMR_SelectSlaveMode(TMR_T *tmr, TMR_SLAVE_MODE_T slaveMode);
|
||||
void TMR_EnableMasterSlaveMode(TMR_T *tmr);
|
||||
void TMR_DisableMasterSlaveMode(TMR_T *tmr);
|
||||
void TMR_ConfigCounter(TMR_T *tmr, uint16_t counter);
|
||||
void TMR_ConfigAutoreload(TMR_T *tmr, uint16_t autoReload);
|
||||
void TMR_ConfigCompare1(TMR_T *tmr, uint16_t compare1);
|
||||
void TMR_ConfigCompare2(TMR_T *tmr, uint16_t compare2);
|
||||
void TMR_ConfigCompare3(TMR_T *tmr, uint16_t compare3);
|
||||
void TMR_ConfigCompare4(TMR_T *tmr, uint16_t compare4);
|
||||
void TMR_ConfigIC1Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler);
|
||||
void TMR_ConfigIC2Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler);
|
||||
void TMR_ConfigIC3Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler);
|
||||
void TMR_ConfigIC4Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler);
|
||||
uint16_t TMR_ReadCaputer1(TMR_T *tmr);
|
||||
uint16_t TMR_ReadCaputer2(TMR_T *tmr);
|
||||
uint16_t TMR_ReadCaputer3(TMR_T *tmr);
|
||||
uint16_t TMR_ReadCaputer4(TMR_T *tmr);
|
||||
uint16_t TMR_ReadCounter(TMR_T *tmr);
|
||||
uint16_t TMR_ReadPrescaler(TMR_T *tmr);
|
||||
|
||||
/** Interrupts and Event */
|
||||
void TMR_EnableInterrupt(TMR_T* tmr, uint16_t interrupt);
|
||||
void TMR_DisableInterrupt(TMR_T* tmr, uint16_t interrupt);
|
||||
void TMR_GenerateEvent(TMR_T* tmr,uint16_t eventSources);
|
||||
void TMR_EnableInterrupt(TMR_T *tmr, uint16_t interrupt);
|
||||
void TMR_DisableInterrupt(TMR_T *tmr, uint16_t interrupt);
|
||||
void TMR_GenerateEvent(TMR_T *tmr, uint16_t eventSources);
|
||||
|
||||
/** flags */
|
||||
uint16_t TMR_ReadStatusFlag(TMR_T* tmr, TMR_FLAG_T flag);
|
||||
void TMR_ClearStatusFlag(TMR_T* tmr, uint16_t flag);
|
||||
uint16_t TMR_ReadIntFlag(TMR_T* tmr, TMR_INT_T flag);
|
||||
void TMR_ClearIntFlag(TMR_T* tmr, uint16_t flag);
|
||||
uint16_t TMR_ReadStatusFlag(TMR_T *tmr, TMR_FLAG_T flag);
|
||||
void TMR_ClearStatusFlag(TMR_T *tmr, uint16_t flag);
|
||||
uint16_t TMR_ReadIntFlag(TMR_T *tmr, TMR_INT_T flag);
|
||||
void TMR_ClearIntFlag(TMR_T *tmr, uint16_t flag);
|
||||
|
||||
/**@} end of group TMR_Fuctions*/
|
||||
/**@} end of group TMR_Driver */
|
||||
/**@} end of group TMR_Driver*/
|
||||
/**@} end of group Peripherals_Library*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
@@ -1,23 +1,37 @@
|
||||
/*!
|
||||
* @file apm32f10x_usart.h
|
||||
* @file apm32f10x_usart.h
|
||||
*
|
||||
* @brief This file contains all the functions prototypes for the USART firmware library
|
||||
* @brief This file contains all the functions prototypes for the USART firmware library
|
||||
*
|
||||
* @version V1.0.1
|
||||
* @version V1.0.2
|
||||
*
|
||||
* @date 2021-03-23
|
||||
* @date 2022-01-05
|
||||
*
|
||||
* @attention
|
||||
*
|
||||
* Copyright (C) 2020-2022 Geehy Semiconductor
|
||||
*
|
||||
* You may not use this file except in compliance with the
|
||||
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
|
||||
*
|
||||
* The program is only for reference, which is distributed in the hope
|
||||
* that it will be usefull and instructional for customers to develop
|
||||
* their software. Unless required by applicable law or agreed to in
|
||||
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
|
||||
* and limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __APM32F10X_USART_H
|
||||
#define __APM32F10X_USART_H
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
/** @addtogroup Peripherals_Library Standard Peripheral Library
|
||||
@{
|
||||
*/
|
||||
@@ -226,64 +240,64 @@ typedef struct
|
||||
*/
|
||||
|
||||
/** USART Reset and Configuration */
|
||||
void USART_Reset(USART_T* usart);
|
||||
void USART_Config(USART_T* uart, USART_Config_T* usartConfig);
|
||||
void USART_ConfigStructInit(USART_Config_T* usartConfig);
|
||||
void USART_Address(USART_T* usart, uint8_t address);
|
||||
void USART_Enable(USART_T* usart);
|
||||
void USART_Disable(USART_T* usart);
|
||||
void USART_Reset(USART_T *usart);
|
||||
void USART_Config(USART_T *uart, USART_Config_T *usartConfig);
|
||||
void USART_ConfigStructInit(USART_Config_T *usartConfig);
|
||||
void USART_Address(USART_T *usart, uint8_t address);
|
||||
void USART_Enable(USART_T *usart);
|
||||
void USART_Disable(USART_T *usart);
|
||||
|
||||
/** Clock communication */
|
||||
void USART_ConfigClock(USART_T* usart, USART_ClockConfig_T* clockConfig);
|
||||
void USART_ConfigClockStructInit(USART_ClockConfig_T* clockConfig);
|
||||
void USART_ConfigClock(USART_T *usart, USART_ClockConfig_T *clockConfig);
|
||||
void USART_ConfigClockStructInit(USART_ClockConfig_T *clockConfig);
|
||||
|
||||
/** DMA mode */
|
||||
void USART_EnableDMA(USART_T* usart, USART_DMA_T dmaReq);
|
||||
void USART_DisableDMA(USART_T* usart, USART_DMA_T dmaReq);
|
||||
void USART_EnableDMA(USART_T *usart, USART_DMA_T dmaReq);
|
||||
void USART_DisableDMA(USART_T *usart, USART_DMA_T dmaReq);
|
||||
|
||||
/** Mute mode */
|
||||
void USART_ConfigWakeUp(USART_T* usart, USART_WAKEUP_T wakeup);
|
||||
void USART_EnableMuteMode(USART_T* usart);
|
||||
void USART_DisableMuteMode(USART_T* usart);
|
||||
void USART_ConfigWakeUp(USART_T *usart, USART_WAKEUP_T wakeup);
|
||||
void USART_EnableMuteMode(USART_T *usart);
|
||||
void USART_DisableMuteMode(USART_T *usart);
|
||||
|
||||
/** LIN mode */
|
||||
void USART_ConfigLINBreakDetectLength(USART_T* usart, USART_LBDL_T length);
|
||||
void USART_EnableLIN(USART_T* usart);
|
||||
void USART_DisableLIN(USART_T* usart);
|
||||
void USART_ConfigLINBreakDetectLength(USART_T *usart, USART_LBDL_T length);
|
||||
void USART_EnableLIN(USART_T *usart);
|
||||
void USART_DisableLIN(USART_T *usart);
|
||||
|
||||
/** Transmit and receive */
|
||||
void USART_EnableTx(USART_T* usart);
|
||||
void USART_DisableTx(USART_T* usart);
|
||||
void USART_EnableRx(USART_T* usart);
|
||||
void USART_DisableRx(USART_T* usart);
|
||||
void USART_TxData(USART_T* usart, uint16_t data);
|
||||
uint16_t USART_RxData(USART_T* usart);
|
||||
void USART_TxBreak(USART_T* usart);
|
||||
void USART_EnableTx(USART_T *usart);
|
||||
void USART_DisableTx(USART_T *usart);
|
||||
void USART_EnableRx(USART_T *usart);
|
||||
void USART_DisableRx(USART_T *usart);
|
||||
void USART_TxData(USART_T *usart, uint16_t data);
|
||||
uint16_t USART_RxData(USART_T *usart);
|
||||
void USART_TxBreak(USART_T *usart);
|
||||
|
||||
/** Smartcard mode */
|
||||
void USART_ConfigGuardTime(USART_T* usart, uint8_t guardTime);
|
||||
void USART_ConfigPrescaler(USART_T* usart, uint8_t div);
|
||||
void USART_EnableSmartCard(USART_T* usart);
|
||||
void USART_DisableSmartCard(USART_T* usart);
|
||||
void USART_EnableSmartCardNACK(USART_T* usart);
|
||||
void USART_DisableSmartCardNACK(USART_T* usart);
|
||||
void USART_ConfigGuardTime(USART_T *usart, uint8_t guardTime);
|
||||
void USART_ConfigPrescaler(USART_T *usart, uint8_t div);
|
||||
void USART_EnableSmartCard(USART_T *usart);
|
||||
void USART_DisableSmartCard(USART_T *usart);
|
||||
void USART_EnableSmartCardNACK(USART_T *usart);
|
||||
void USART_DisableSmartCardNACK(USART_T *usart);
|
||||
|
||||
/** Half-duplex mode */
|
||||
void USART_EnableHalfDuplex(USART_T* usart);
|
||||
void USART_DisableHalfDuplex(USART_T* usart);
|
||||
void USART_EnableHalfDuplex(USART_T *usart);
|
||||
void USART_DisableHalfDuplex(USART_T *usart);
|
||||
|
||||
/** IrDA mode */
|
||||
void USART_ConfigIrDA(USART_T* usart, USART_IRDALP_T IrDAMode);
|
||||
void USART_EnableIrDA(USART_T* usart);
|
||||
void USART_DisableIrDA(USART_T* usart);
|
||||
void USART_ConfigIrDA(USART_T *usart, USART_IRDALP_T IrDAMode);
|
||||
void USART_EnableIrDA(USART_T *usart);
|
||||
void USART_DisableIrDA(USART_T *usart);
|
||||
|
||||
/** Interrupt and flag */
|
||||
void USART_EnableInterrupt(USART_T* usart, USART_INT_T interrupt);
|
||||
void USART_DisableInterrupt(USART_T* usart, USART_INT_T interrupt);
|
||||
uint8_t USART_ReadStatusFlag(USART_T* usart, USART_FLAG_T flag);
|
||||
void USART_ClearStatusFlag(USART_T* usart, USART_FLAG_T flag);
|
||||
uint8_t USART_ReadIntFlag(USART_T* usart, USART_INT_T flag);
|
||||
void USART_ClearIntFlag(USART_T* usart, USART_INT_T flag);
|
||||
void USART_EnableInterrupt(USART_T *usart, USART_INT_T interrupt);
|
||||
void USART_DisableInterrupt(USART_T *usart, USART_INT_T interrupt);
|
||||
uint8_t USART_ReadStatusFlag(USART_T *usart, USART_FLAG_T flag);
|
||||
void USART_ClearStatusFlag(USART_T *usart, USART_FLAG_T flag);
|
||||
uint8_t USART_ReadIntFlag(USART_T *usart, USART_INT_T flag);
|
||||
void USART_ClearIntFlag(USART_T *usart, USART_INT_T flag);
|
||||
|
||||
/**@} end of group USART_Fuctions*/
|
||||
/**@} end of group USART_Driver*/
|
||||
|
||||
@@ -3,21 +3,35 @@
|
||||
*
|
||||
* @brief This file contains all the functions prototypes for the WWDT firmware library
|
||||
*
|
||||
* @version V1.0.1
|
||||
* @version V1.0.2
|
||||
*
|
||||
* @date 2021-03-23
|
||||
* @date 2022-01-05
|
||||
*
|
||||
* @attention
|
||||
*
|
||||
* Copyright (C) 2020-2022 Geehy Semiconductor
|
||||
*
|
||||
* You may not use this file except in compliance with the
|
||||
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
|
||||
*
|
||||
* The program is only for reference, which is distributed in the hope
|
||||
* that it will be usefull and instructional for customers to develop
|
||||
* their software. Unless required by applicable law or agreed to in
|
||||
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
|
||||
* and limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __APM32F10X_WWDT_H
|
||||
#define __APM32F10X_WWDT_H
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "apm32f10x.h"
|
||||
|
||||
/** @addtogroup Peripherals_Library Standard Peripheral Library
|
||||
@{
|
||||
*/
|
||||
@@ -39,7 +53,7 @@ typedef enum
|
||||
WWDT_TIME_BASE_2 = 0x00000080,
|
||||
WWDT_TIME_BASE_4 = 0x00000100,
|
||||
WWDT_TIME_BASE_8 = 0x00000180
|
||||
}WWDT_TIME_BASE_T;
|
||||
} WWDT_TIME_BASE_T;
|
||||
|
||||
/**@} end of group WWDT_Enumerations*/
|
||||
|
||||
@@ -68,7 +82,7 @@ uint8_t WWDT_ReadFlag(void);
|
||||
void WWDT_ClearFlag(void);
|
||||
|
||||
/**@} end of group WWDT_Fuctions*/
|
||||
/**@} end of group WWDT_Driver */
|
||||
/**@} end of group WWDT_Driver*/
|
||||
/**@} end of group Peripherals_Library*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,12 +1,26 @@
|
||||
/*!
|
||||
* @file apm32f10x_bakpr.c
|
||||
* @file apm32f10x_bakpr.c
|
||||
*
|
||||
* @brief This file provides all the BAKPR firmware functions.
|
||||
* @brief This file provides all the BAKPR firmware functions.
|
||||
*
|
||||
* @version V1.0.1
|
||||
* @version V1.0.2
|
||||
*
|
||||
* @date 2021-03-23
|
||||
* @date 2022-01-05
|
||||
*
|
||||
* @attention
|
||||
*
|
||||
* Copyright (C) 2020-2022 Geehy Semiconductor
|
||||
*
|
||||
* You may not use this file except in compliance with the
|
||||
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
|
||||
*
|
||||
* The program is only for reference, which is distributed in the hope
|
||||
* that it will be usefull and instructional for customers to develop
|
||||
* their software. Unless required by applicable law or agreed to in
|
||||
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
|
||||
* and limitations under the License.
|
||||
*/
|
||||
|
||||
#include "apm32f10x_bakpr.h"
|
||||
@@ -114,16 +128,19 @@ void BAKPR_DisableInterrupt(void)
|
||||
*/
|
||||
void BAKPR_ConfigRTCOutput(BAKPR_RTC_OUTPUT_SOURCE_T soure)
|
||||
{
|
||||
if(soure == BAKPR_RTC_OUTPUT_SOURCE_NONE)
|
||||
if (soure == BAKPR_RTC_OUTPUT_SOURCE_NONE)
|
||||
{
|
||||
BAKPR->CLKCAL = RESET;
|
||||
} else if(soure == BAKPR_RTC_OUTPUT_SOURCE_CALIBRATION_CLOCK)
|
||||
}
|
||||
else if (soure == BAKPR_RTC_OUTPUT_SOURCE_CALIBRATION_CLOCK)
|
||||
{
|
||||
BAKPR->CLKCAL_B.CALCOEN = BIT_SET;
|
||||
} else if(soure == BAKPR_RTC_OUTPUT_SOURCE_ALARM)
|
||||
}
|
||||
else if (soure == BAKPR_RTC_OUTPUT_SOURCE_ALARM)
|
||||
{
|
||||
BAKPR->CLKCAL_B.ASPOEN = BIT_SET;
|
||||
} else if(soure == BAKPR_RTC_OUTPUT_SOURCE_SECOND)
|
||||
}
|
||||
else if (soure == BAKPR_RTC_OUTPUT_SOURCE_SECOND)
|
||||
{
|
||||
BAKPR->CLKCAL_B.ASPOSEL = BIT_SET;
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,12 +1,26 @@
|
||||
/*!
|
||||
* @file apm32f10x_crc.c
|
||||
* @file apm32f10x_crc.c
|
||||
*
|
||||
* @brief This file provides all the CRC firmware functions
|
||||
* @brief This file provides all the CRC firmware functions
|
||||
*
|
||||
* @version V1.0.1
|
||||
* @version V1.0.2
|
||||
*
|
||||
* @date 2021-03-23
|
||||
* @date 2022-01-05
|
||||
*
|
||||
* @attention
|
||||
*
|
||||
* Copyright (C) 2020-2022 Geehy Semiconductor
|
||||
*
|
||||
* You may not use this file except in compliance with the
|
||||
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
|
||||
*
|
||||
* The program is only for reference, which is distributed in the hope
|
||||
* that it will be usefull and instructional for customers to develop
|
||||
* their software. Unless required by applicable law or agreed to in
|
||||
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
|
||||
* and limitations under the License.
|
||||
*/
|
||||
|
||||
#include "apm32f10x_crc.h"
|
||||
@@ -29,8 +43,6 @@
|
||||
* @param None
|
||||
*
|
||||
* @retval None
|
||||
*
|
||||
* @note
|
||||
*/
|
||||
void CRC_ResetDATA(void)
|
||||
{
|
||||
@@ -63,7 +75,7 @@ uint32_t CRC_CalculateCRC(uint32_t data)
|
||||
*/
|
||||
uint32_t CRC_CalculateBlockCRC(uint32_t *buf, uint32_t bufLen)
|
||||
{
|
||||
while(bufLen--)
|
||||
while (bufLen--)
|
||||
{
|
||||
CRC->DATA = *buf++;
|
||||
}
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user