From fb61c7960b67928c8736bbf46f0071032b5c8e66 Mon Sep 17 00:00:00 2001 From: stevetong459 <53069552+stevetong459@users.noreply.github.com> Date: Tue, 8 Mar 2022 12:03:06 +0800 Subject: [PATCH] =?UTF-8?q?=E6=9C=AC=E6=AC=A1PR=E6=B6=89=E5=8F=8A=E2=91=A0?= =?UTF-8?q?BSP=E9=A9=B1=E5=8A=A8=E6=96=B0=E5=A2=9E=E2=91=A1F103=E5=BA=93?= =?UTF-8?q?=E6=9B=B4=E6=96=B0=E2=91=A2GCC=E3=80=81IAR=E9=80=82=E9=85=8D?= =?UTF-8?q?=E5=8F=8AMDK=E6=9B=B4=E6=96=B0=E2=91=A3README=E6=96=87=E4=BB=B6?= =?UTF-8?q?=E5=8F=8A=E7=94=B1=E6=9B=B4=E6=96=B0=E9=A9=B1=E5=8A=A8=E5=BC=95?= =?UTF-8?q?=E8=B5=B7=E7=9A=84=E8=84=9A=E6=9C=AC=E6=94=B9=E5=8A=A8=E3=80=82?= =?UTF-8?q?=20(#5638)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * 本次提交包括①BSP驱动新增②F103库更新③GCC、IAR适配及MDK更新④README文件及由更新驱动引起的脚本改动。 详情如下： 一、BSP驱动新增 这是本次PR的主要目的，现新增了如下BSP驱动： ADC、DAC、RTC、PWM、HWTIMER、I2C、SPI和WDT等八个驱动文件。 二、F103库更新： 本次提交使用2022年3月初极海官网发布的最新F103库，主要增加了版权声明、USB驱动及其他代码调整。 三、编译器适配： 1、新增GCC编译支持，在ENV工具下编译能成功且输出的bin文件能够使开发板闪灯。 2、新增IAR工程支持。 3、由F103的SDK更新，MDK的工程也进行了相应更新。 四、其他 1、README文件做了修改，加入了scons编译后的jlink下载说明和官网链接。 2、Kconfig、SConscript脚本根据驱动更新做了修改。 * 格式化代码（AStyle + Formatting） * 增加BSP APM版权声明 * 在ci添加当前bsp的路径，以能够验证gcc能否正常编译 * 路径的“\”改为“/” --- .github/workflows/action.yml | 1 + bsp/Copyright_Notice.md | 27 + bsp/apm32/apm32f103xe-minibroard/README.md | 38 +- .../apm32f103xe-minibroard/board/Kconfig | 149 ++ .../apm32f103xe-minibroard/board/SConscript | 10 +- .../apm32f103xe-minibroard/board/board.c | 12 +- .../apm32f103xe-minibroard/board/board.h | 28 +- .../board/linker_scripts/link.icf | 28 + .../board/linker_scripts/link.lds | 141 + .../figures/JFlash_Leader_01.png | Bin 0 -> 47629 bytes .../figures/JFlash_Leader_02.png | Bin 0 -> 9973 bytes .../figures/JFlash_Leader_03.png | Bin 0 -> 3590 bytes .../figures/JFlash_Leader_04.png | Bin 0 -> 12434 bytes bsp/apm32/apm32f103xe-minibroard/project.ewp | 2346 +++++++++++++++++ bsp/apm32/apm32f103xe-minibroard/project.eww | 10 + .../apm32f103xe-minibroard/project.uvoptx | 805 ++++++ .../apm32f103xe-minibroard/project.uvprojx | 210 +- bsp/apm32/apm32f103xe-minibroard/template.ewp | 2114 +++++++++++++++ bsp/apm32/apm32f103xe-minibroard/template.eww | 10 + .../apm32f103xe-minibroard/template.uvoptx | 185 ++ .../apm32f103xe-minibroard/template.uvprojx | 5 +- .../inc/apm32f10x_adc.h | 140 +- .../inc/apm32f10x_bakpr.h | 24 +- .../inc/apm32f10x_can.h | 122 +- .../inc/apm32f10x_crc.h | 28 +- .../inc/apm32f10x_dac.h | 88 +- .../inc/apm32f10x_dbgmcu.h | 26 +- .../inc/apm32f10x_dma.h | 34 +- .../inc/apm32f10x_dmc.h | 78 +- .../inc/apm32f10x_eint.h | 36 +- .../inc/apm32f10x_emmc.h | 56 +- .../inc/apm32f10x_fmc.h | 30 +- .../inc/apm32f10x_gpio.h | 216 +- .../inc/apm32f10x_i2c.h | 120 +- .../inc/apm32f10x_iwdt.h | 34 +- .../inc/apm32f10x_misc.h | 54 +- .../inc/apm32f10x_pmu.h | 40 +- .../inc/apm32f10x_qspi.h | 72 +- .../inc/apm32f10x_rcm.h | 54 +- .../inc/apm32f10x_rtc.h | 26 +- .../inc/apm32f10x_sci2c.h | 46 +- .../inc/apm32f10x_sdio.h | 114 +- .../inc/apm32f10x_spi.h | 124 +- .../inc/apm32f10x_tmr.h | 236 +- .../inc/apm32f10x_usart.h | 106 +- .../inc/apm32f10x_wwdt.h | 28 +- .../src/apm32f10x_adc.c | 208 +- .../src/apm32f10x_bakpr.c | 33 +- .../src/apm32f10x_can.c | 292 +- .../src/apm32f10x_crc.c | 26 +- .../src/apm32f10x_dac.c | 64 +- .../src/apm32f10x_dbgmcu.c | 24 +- .../src/apm32f10x_dma.c | 87 +- .../src/apm32f10x_dmc.c | 79 +- .../src/apm32f10x_eint.c | 47 +- .../src/apm32f10x_emmc.c | 140 +- .../src/apm32f10x_fmc.c | 139 +- .../src/apm32f10x_gpio.c | 68 +- .../src/apm32f10x_i2c.c | 149 +- .../src/apm32f10x_iwdt.c | 23 +- .../src/apm32f10x_misc.c | 131 +- .../src/apm32f10x_pmu.c | 75 +- .../src/apm32f10x_qspi.c | 33 +- .../src/apm32f10x_rcm.c | 153 +- .../src/apm32f10x_rtc.c | 84 +- .../src/apm32f10x_sci2c.c | 66 +- .../src/apm32f10x_sdio.c | 112 +- .../src/apm32f10x_spi.c | 128 +- .../src/apm32f10x_tmr.c | 374 +-- .../src/apm32f10x_usart.c | 119 +- .../src/apm32f10x_wwdt.c | 22 +- .../CMSIS/Include/LICENSE.txt | 176 ++ .../CMSIS/Include/cmsis_armcc.h | 267 +- .../CMSIS/Include/cmsis_armclang.h | 1042 +++++--- .../CMSIS/Include/cmsis_armclang_ltm.h | 849 +++--- .../CMSIS/Include/cmsis_compiler.h | 326 ++- .../CMSIS/Include/cmsis_gcc.h | 2092 +++++++++++++++ .../CMSIS/Include/cmsis_iccarm.h | 941 +++++++ .../CMSIS/Include/cmsis_version.h | 4 +- .../CMSIS/Include/core_cm3.h | 786 +++--- .../Geehy/APM32F10x/Include/apm32f10x.h | 745 +++--- .../APM32F10x/Include/system_apm32f10x.h | 20 +- .../Source/ARM/startup_apm32f10x_hd.s | 583 ++-- .../Source/ARM/startup_apm32f10x_md.s | 495 ++-- .../Source/gcc/startup_apm32f10x_hd.s | 281 ++ .../Source/gcc/startup_apm32f10x_md.s | 246 ++ .../Source/iar/startup_apm32f10x_hd.s | 813 ++++++ .../Source/iar/startup_apm32f10x_md.s | 644 +++++ .../Geehy/APM32F10x/Source/system_apm32f10x.c | 347 +-- .../libraries/APM32F10x_Library/SConscript | 20 + .../Class/CDC/inc/usbd_class_cdc.h | 33 + .../Class/CDC/src/usbd_class_cdc.c | 71 + .../Class/HID/inc/usbd_class_hid.h | 37 + .../Class/HID/src/usbd_class_hid.c | 63 + .../Class/MSC/inc/usbd_class_msc.h | 37 + .../Core_Device/Class/MSC/inc/usbd_msc_bot.h | 106 + .../Core_Device/Class/MSC/inc/usbd_msc_scsi.h | 132 + .../Class/MSC/src/usbd_class_msc.c | 79 + .../Core_Device/Class/MSC/src/usbd_msc_bot.c | 242 ++ .../Core_Device/Class/MSC/src/usbd_msc_scsi.c | 701 +++++ .../Core_Device/Standard/inc/usbd_core.h | 312 +++ .../Core_Device/Standard/inc/usbd_init.h | 64 + .../Core_Device/Standard/inc/usbd_interrupt.h | 31 + .../Core_Device/Standard/inc/usbd_stdReq.h | 31 + .../Core_Device/Standard/src/usbd_core.c | 405 +++ .../Core_Device/Standard/src/usbd_init.c | 237 ++ .../Core_Device/Standard/src/usbd_interrupt.c | 349 +++ .../Core_Device/Standard/src/usbd_stdReq.c | 369 +++ .../Driver/inc/drv_usb_device.h} | 636 ++++- .../Driver/src/drv_usb_device.c} | 115 +- bsp/apm32/libraries/Drivers/SConscript | 24 + bsp/apm32/libraries/Drivers/drv_adc.c | 273 ++ bsp/apm32/libraries/Drivers/drv_common.c | 21 +- bsp/apm32/libraries/Drivers/drv_common.h | 4 +- bsp/apm32/libraries/Drivers/drv_dac.c | 184 ++ bsp/apm32/libraries/Drivers/drv_gpio.c | 2 +- bsp/apm32/libraries/Drivers/drv_gpio.h | 2 +- bsp/apm32/libraries/Drivers/drv_hwtimer.c | 402 +++ bsp/apm32/libraries/Drivers/drv_pwm.c | 484 ++++ bsp/apm32/libraries/Drivers/drv_rtc.c | 170 ++ bsp/apm32/libraries/Drivers/drv_soft_i2c.c | 244 ++ bsp/apm32/libraries/Drivers/drv_spi.c | 264 ++ bsp/apm32/libraries/Drivers/drv_spi.h | 22 + bsp/apm32/libraries/Drivers/drv_usart.c | 5 +- bsp/apm32/libraries/Drivers/drv_usart.h | 2 +- bsp/apm32/libraries/Drivers/drv_wdt.c | 150 ++ 126 files changed, 23083 insertions(+), 4624 deletions(-) create mode 100644 bsp/apm32/apm32f103xe-minibroard/board/linker_scripts/link.icf create mode 100644 bsp/apm32/apm32f103xe-minibroard/board/linker_scripts/link.lds create mode 100644 bsp/apm32/apm32f103xe-minibroard/figures/JFlash_Leader_01.png create mode 100644 bsp/apm32/apm32f103xe-minibroard/figures/JFlash_Leader_02.png create mode 100644 bsp/apm32/apm32f103xe-minibroard/figures/JFlash_Leader_03.png create mode 100644 bsp/apm32/apm32f103xe-minibroard/figures/JFlash_Leader_04.png create mode 100644 bsp/apm32/apm32f103xe-minibroard/project.ewp create mode 100644 bsp/apm32/apm32f103xe-minibroard/project.eww create mode 100644 bsp/apm32/apm32f103xe-minibroard/project.uvoptx create mode 100644 bsp/apm32/apm32f103xe-minibroard/template.ewp create mode 100644 bsp/apm32/apm32f103xe-minibroard/template.eww create mode 100644 bsp/apm32/apm32f103xe-minibroard/template.uvoptx create mode 100644 bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/LICENSE.txt create mode 100644 bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_gcc.h create mode 100644 bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_iccarm.h create mode 100644 bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/startup_apm32f10x_hd.s create mode 100644 bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/startup_apm32f10x_md.s create mode 100644 bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/iar/startup_apm32f10x_hd.s create mode 100644 bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/iar/startup_apm32f10x_md.s create mode 100644 bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/CDC/inc/usbd_class_cdc.h create mode 100644 bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/CDC/src/usbd_class_cdc.c create mode 100644 bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/HID/inc/usbd_class_hid.h create mode 100644 bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/HID/src/usbd_class_hid.c create mode 100644 bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/MSC/inc/usbd_class_msc.h create mode 100644 bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/MSC/inc/usbd_msc_bot.h create mode 100644 bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/MSC/inc/usbd_msc_scsi.h create mode 100644 bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/MSC/src/usbd_class_msc.c create mode 100644 bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/MSC/src/usbd_msc_bot.c create mode 100644 bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/MSC/src/usbd_msc_scsi.c create mode 100644 bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Standard/inc/usbd_core.h create mode 100644 bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Standard/inc/usbd_init.h create mode 100644 bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Standard/inc/usbd_interrupt.h create mode 100644 bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Standard/inc/usbd_stdReq.h create mode 100644 bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Standard/src/usbd_core.c create mode 100644 bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Standard/src/usbd_init.c create mode 100644 bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Standard/src/usbd_interrupt.c create mode 100644 bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Standard/src/usbd_stdReq.c rename bsp/apm32/libraries/APM32F10x_Library/{APM32F10x_StdPeriphDriver/inc/apm32f10x_usb.h => USB_Device_Lib/Driver/inc/drv_usb_device.h} (53%) rename bsp/apm32/libraries/APM32F10x_Library/{APM32F10x_StdPeriphDriver/src/apm32f10x_usb.c => USB_Device_Lib/Driver/src/drv_usb_device.c} (67%) create mode 100644 bsp/apm32/libraries/Drivers/drv_adc.c create mode 100644 bsp/apm32/libraries/Drivers/drv_dac.c create mode 100644 bsp/apm32/libraries/Drivers/drv_hwtimer.c create mode 100644 bsp/apm32/libraries/Drivers/drv_pwm.c create mode 100644 bsp/apm32/libraries/Drivers/drv_rtc.c create mode 100644 bsp/apm32/libraries/Drivers/drv_soft_i2c.c create mode 100644 bsp/apm32/libraries/Drivers/drv_spi.c create mode 100644 bsp/apm32/libraries/Drivers/drv_spi.h create mode 100644 bsp/apm32/libraries/Drivers/drv_wdt.c diff --git a/.github/workflows/action.yml b/.github/workflows/action.yml index 1184bc40f0..f98870e0d0 100644 --- a/.github/workflows/action.yml +++ b/.github/workflows/action.yml @@ -31,6 +31,7 @@ jobs: legs: - {RTT_BSP: "acm32f0x0-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "CME_M7", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "apm32/apm32f103xe-minibroard", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "apollo2", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "asm9260t", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "at91sam9260", RTT_TOOL_CHAIN: "sourcery-arm"} diff --git a/bsp/Copyright_Notice.md b/bsp/Copyright_Notice.md index ff730a9cb0..7a805d1771 100644 --- a/bsp/Copyright_Notice.md +++ b/bsp/Copyright_Notice.md @@ -20,6 +20,33 @@ Path: - bsp/acm32f0x0-nucleo/libraries +### apm32 + +bsp 列表： +- apm32f103xe-minibroard + +------ + +License: GEEHY SOFTWARE PACKAGE LICENSE + +Copyright: Copyright (C) 2020-2022 Geehy Semiconductor + +Path: + +- bsp\apm32\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver +- bsp\apm32\libraries\APM32F10x_Library\Device +- bsp\apm32\libraries\APM32F10x_Library\USB_Device_Lib + +------ + +License: bsd-new + +Copyright (c) 2009-2018 Arm Limited + +Path: + +- bsp\apm32\libraries\APM32F10x_Library\CMSIS\Include + ### apollo2 License: bsd-new diff --git a/bsp/apm32/apm32f103xe-minibroard/README.md b/bsp/apm32/apm32f103xe-minibroard/README.md index 63f3df1030..5284f30f92 100644 --- a/bsp/apm32/apm32f103xe-minibroard/README.md +++ b/bsp/apm32/apm32f103xe-minibroard/README.md @@ -17,17 +17,18 @@ APM32F103ZE MINI BOARD，采用标准JTAG/SWD调试接口，引出了全部的IO ![board](figures/APM32F103ZE.png) +- 有关开发板和芯片的详情可至极海官网查阅。[官网开发板链接 ](https://www.geehy.com/support/apm32?id=192) 该开发板常用 **板载资源** 如下： -- MCU：APM32F103C8T6，主频 96MHz，512KB FLASH ，128KB RAM +- MCU：APM32F103ZET6，主频 96MHz，512KB FLASH ，128KB RAM - 外部 RAM：无 - 外部 FLASH：无 - 常用外设 - LED：2个，（黄色，PE5/PE6） - 按键：2个，K1（兼具唤醒功能，PA0），K2（PC13） -- 常用接口：RS232转串口、、USB SLAVE +- 常用接口：RS232转串口、USB SLAVE - 调试接口：标准 JTAG/SWD @@ -42,6 +43,14 @@ APM32F103ZE MINI BOARD，采用标准JTAG/SWD调试接口，引出了全部的IO | **片上外设** | **支持情况** | **备注** | | GPIO | 支持 | PA0, PA1... PG15 ---> PIN: 0, 1...143 | | UART | 支持 | UART1/2 | +| ADC | 支持 | ADC1/2/3 | +| DAC | 支持 | DAC1 | +| RTC | 支持 | | +| TMR | 支持 | TMR1/2/3/4/5/6/7/8 | +| PWM | 支持 | TMR3 ->CH1/2 | +| I2C | 支持 | 软件I2C | +| SPI | 支持 | SPI1/2/3 | +| WDT | 支持 | IWDT | ## 使用说明 @@ -57,11 +66,28 @@ APM32F103ZE MINI BOARD，采用标准JTAG/SWD调试接口，引出了全部的IO 使用数据线连接开发板到 PC，打开电源开关。 #### 编译下载 +- 方式一：MDK -双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + 双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 > 工程默认配置使用 J-Link 仿真器下载程序，在通过 J-Link 连接开发板的基础上，点击下载按钮即可下载程序到开发板 +- 方式二：J-Flash下载 + + 通过ENV工具的scons指令或MDK编译出bin文件后，再使用J-Flash工具将bin文件下载至开发板即可，大致步骤如下： + +##### 1、建立J-Flash工程 + +![board](figures/JFlash_leader_01.png) + +##### 2、连接开发板 + +![board](figures/JFlash_leader_02.png) +##### 3、将bin文件拖至工程，起始地址设为0x8000000 +![board](figures/JFlash_leader_03.png) +##### 4、点击下载 +![board](figures/JFlash_leader_04.png) + #### 运行结果 下载程序成功之后，系统会自动运行，LED 闪烁 @@ -71,7 +97,7 @@ APM32F103ZE MINI BOARD，采用标准JTAG/SWD调试接口，引出了全部的IO ```bash \ | / - RT - Thread Operating System - / | \ 4.0.4 build Aug 20 2021 + / | \ 4.1.0 build Aug 20 2021 2006 - 2021 Copyright by rt-thread team msh > ``` @@ -81,4 +107,6 @@ msh > ## 联系人信息 --[abbbcc ](https://gitee.com/abbbcc) \ No newline at end of file +-[abbbcc ](https://gitee.com/abbbcc) + +-[stevetong459 ](https://github.com/stevetong459) diff --git a/bsp/apm32/apm32f103xe-minibroard/board/Kconfig b/bsp/apm32/apm32f103xe-minibroard/board/Kconfig index 983731fc10..2146256f92 100644 --- a/bsp/apm32/apm32f103xe-minibroard/board/Kconfig +++ b/bsp/apm32/apm32f103xe-minibroard/board/Kconfig @@ -24,6 +24,155 @@ menu "On-chip Peripheral Drivers" default y endif + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC + if BSP_USING_ADC + config BSP_USING_ADC1 + bool "Enable ADC1" + default n + config BSP_USING_ADC2 + bool "Enable ADC2" + default n + config BSP_USING_ADC3 + bool "Enable ADC3" + default n + endif + + menuconfig BSP_USING_DAC + bool "Enable DAC" + default n + select RT_USING_DAC + if BSP_USING_DAC + config BSP_USING_DAC1 + bool "Enable DAC1" + default n + endif + + menuconfig BSP_USING_ONCHIP_RTC + bool "Enable RTC" + select RT_USING_RTC + default n + if BSP_USING_ONCHIP_RTC + choice + prompt "Select clock source" + default BSP_RTC_USING_LSE + + config BSP_RTC_USING_LSE + bool "RTC USING LSE" + + config BSP_RTC_USING_LSI + bool "RTC USING LSI" + endchoice + endif + + menuconfig BSP_USING_I2C1 + bool "Enable I2C1 BUS (software simulation)" + default n + select RT_USING_I2C + select RT_USING_I2C_BITOPS + select RT_USING_PIN + if BSP_USING_I2C1 + config BSP_I2C1_SCL_PIN + int "i2c1 scl pin number" + range 0 63 + default 22 + config BSP_I2C1_SDA_PIN + int "I2C1 sda pin number" + range 0 63 + default 23 + endif + + menuconfig BSP_USING_SPI + bool "Enable SPI" + default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable SPI1" + default n + + config BSP_USING_SPI2 + bool "Enable SPI2" + default n + + config BSP_USING_SPI3 + bool "Enable SPI3" + default n + endif + + menuconfig BSP_USING_TMR + bool "Enable Timer" + default n + select RT_USING_HWTIMER + if BSP_USING_TMR + config BSP_USING_TMR1 + bool "Enable TMR1" + default n + + config BSP_USING_TMR2 + bool "Enable TMR2" + default n + + config BSP_USING_TMR3 + bool "Enable TMR3" + default n + + config BSP_USING_TMR4 + bool "Enable TMR4" + default n + + config BSP_USING_TMR5 + bool "Enable TMR5" + default n + + config BSP_USING_TMR6 + bool "Enable TMR6" + default n + + config BSP_USING_TMR7 + bool "Enable TMR7" + default n + + config BSP_USING_TMR8 + bool "Enable TMR8" + default n + endif + + menuconfig BSP_USING_PWM + bool "Enable PWM" + default n + select RT_USING_PWM + if BSP_USING_PWM + menuconfig BSP_USING_PWM3 + bool "Enable timer3 output pwm" + default n + if BSP_USING_PWM3 + config BSP_USING_PWM3_CH1 + bool "Enable PWM3 channel1" + default n + + config BSP_USING_PWM3_CH2 + bool "Enable PWM3 channel2" + default n + + config BSP_USING_PWM3_CH3 + bool "Enable PWM3 channel3" + default n + + config BSP_USING_PWM3_CH4 + bool "Enable PWM3 channel4" + default n + endif + endif + + config BSP_USING_WDT + bool "Enable Watchdog Timer" + select RT_USING_WDT + default n + endmenu endmenu diff --git a/bsp/apm32/apm32f103xe-minibroard/board/SConscript b/bsp/apm32/apm32f103xe-minibroard/board/SConscript index f453b68f6a..d0a821621f 100644 --- a/bsp/apm32/apm32f103xe-minibroard/board/SConscript +++ b/bsp/apm32/apm32f103xe-minibroard/board/SConscript @@ -16,9 +16,15 @@ path = [cwd] startup_path_prefix = SDK_LIB if rtconfig.CROSS_TOOL == 'keil': - src += [startup_path_prefix + '/APM32F10x_Library/Device/Geehy/APM32F10x/Source/ARM/startup_apm32f10x_hd.s'] + src += [startup_path_prefix + '/APM32F10x_Library/Device/Geehy/APM32F10x/Source/arm/startup_apm32f10x_hd.s'] + +if rtconfig.CROSS_TOOL == 'iar': + src += [startup_path_prefix + '/APM32F10x_Library/Device/Geehy/APM32F10x/Source/iar/startup_apm32f10x_hd.s'] + +if rtconfig.CROSS_TOOL == 'gcc': + src += [startup_path_prefix + '/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/startup_apm32f10x_hd.s'] # You can select chips from the list above -CPPDEFINES = ['APM32F103xE'] +CPPDEFINES = ['APM32F10X_HD'] group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) Return('group') diff --git a/bsp/apm32/apm32f103xe-minibroard/board/board.c b/bsp/apm32/apm32f103xe-minibroard/board/board.c index bec2c01cde..4fb464f3c2 100644 --- a/bsp/apm32/apm32f103xe-minibroard/board/board.c +++ b/bsp/apm32/apm32f103xe-minibroard/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -13,15 +13,15 @@ void apm32_usart_init(void) { GPIO_Config_T GPIO_ConfigStruct; - + #ifdef BSP_USING_UART1 RCM_EnableAPB2PeriphClock((RCM_APB2_PERIPH_T)(RCM_APB2_PERIPH_GPIOA | RCM_APB2_PERIPH_USART1)); - + GPIO_ConfigStruct.mode = GPIO_MODE_AF_PP; GPIO_ConfigStruct.pin = GPIO_PIN_9; GPIO_ConfigStruct.speed = GPIO_SPEED_50MHz; GPIO_Config(GPIOA, &GPIO_ConfigStruct); - + GPIO_ConfigStruct.mode = GPIO_MODE_IN_PU; GPIO_ConfigStruct.pin = GPIO_PIN_10; GPIO_ConfigStruct.speed = GPIO_SPEED_50MHz; @@ -31,12 +31,12 @@ void apm32_usart_init(void) #ifdef BSP_USING_UART2 RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIOA); RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_USART2); - + GPIO_ConfigStruct.mode = GPIO_MODE_AF_PP; GPIO_ConfigStruct.pin = GPIO_PIN_2; GPIO_ConfigStruct.speed = GPIO_SPEED_50MHz; GPIO_Config(GPIOA, &GPIO_ConfigStruct); - + GPIO_ConfigStruct.mode = GPIO_MODE_IN_PU; GPIO_ConfigStruct.pin = GPIO_PIN_3; GPIO_ConfigStruct.speed = GPIO_SPEED_50MHz; diff --git a/bsp/apm32/apm32f103xe-minibroard/board/board.h b/bsp/apm32/apm32f103xe-minibroard/board/board.h index b2f4773b26..83840ecc87 100644 --- a/bsp/apm32/apm32f103xe-minibroard/board/board.h +++ b/bsp/apm32/apm32f103xe-minibroard/board/board.h @@ -1,11 +1,12 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2020-08-20 Abbcc first version + * Date Author Notes + * 2020-08-20 Abbcc first version + * 2022-03-04 stevetong459 Add head file of new driver */ #ifndef __BOARD_H__ @@ -21,6 +22,27 @@ #include "apm32f10x_eint.h" #include "apm32f10x_usart.h" +#if defined(RT_USING_ADC) + #include "apm32f10x_adc.h" +#endif +#if defined(RT_USING_DAC) + #include "apm32f10x_dac.h" +#endif +#if defined(RT_USING_RTC) + #include "apm32f10x_rtc.h" + #include "apm32f10x_pmu.h" +#endif +#if defined(RT_USING_SPI) + #include "apm32f10x_spi.h" +#endif +#if defined(RT_USING_HWTIMER) || defined(RT_USING_PWM) + #include "apm32f10x_tmr.h" +#endif +#if defined(RT_USING_WDT) + #include "apm32f10x_iwdt.h" + #include "apm32f10x_wwdt.h" +#endif + #include "drv_common.h" #include "drv_gpio.h" diff --git a/bsp/apm32/apm32f103xe-minibroard/board/linker_scripts/link.icf b/bsp/apm32/apm32f103xe-minibroard/board/linker_scripts/link.icf new file mode 100644 index 0000000000..8a71ffd87c --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/board/linker_scripts/link.icf @@ -0,0 +1,28 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x0400; +define symbol __ICFEDIT_size_heap__ = 0x0000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, last block CSTACK}; diff --git a/bsp/apm32/apm32f103xe-minibroard/board/linker_scripts/link.lds b/bsp/apm32/apm32f103xe-minibroard/board/linker_scripts/link.lds new file mode 100644 index 0000000000..592dad353f --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/board/linker_scripts/link.lds @@ -0,0 +1,141 @@ +/* + * linker script for APM32F10x with GNU ld + */ + +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + CODE (rx) : ORIGIN = 0x08000000, LENGTH = 512k /* 512KB flash */ + DATA (rw) : ORIGIN = 0x20000000, LENGTH = 128k /* 128KB sram */ +} +ENTRY(Reset_Handler) +_system_stack_size = 0x200; + +SECTIONS +{ + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + . = ALIGN(4); + _etext = .; + } > CODE = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > CODE + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >DATA + + .stack : + { + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } >DATA + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > DATA + __bss_end = .; + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + 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$PROJ_DIR$\..\libraries\Drivers\drv_gpio.c + + + $PROJ_DIR$\..\libraries\Drivers\drv_usart.c + + + $PROJ_DIR$\..\libraries\Drivers\drv_common.c + + + + Finsh + + $PROJ_DIR$\..\..\..\components\finsh\shell.c + + + $PROJ_DIR$\..\..\..\components\finsh\msh.c + + + $PROJ_DIR$\..\..\..\components\finsh\cmd.c + + + + Kernel + + $PROJ_DIR$\..\..\..\src\scheduler.c + + + $PROJ_DIR$\..\..\..\src\mem.c + + + $PROJ_DIR$\..\..\..\src\components.c + + + $PROJ_DIR$\..\..\..\src\mempool.c + + + $PROJ_DIR$\..\..\..\src\kservice.c + + + $PROJ_DIR$\..\..\..\src\ipc.c + + + $PROJ_DIR$\..\..\..\src\clock.c + + + $PROJ_DIR$\..\..\..\src\object.c + + + $PROJ_DIR$\..\..\..\src\timer.c + + + $PROJ_DIR$\..\..\..\src\irq.c + + + $PROJ_DIR$\..\..\..\src\idle.c + + + $PROJ_DIR$\..\..\..\src\device.c + + + $PROJ_DIR$\..\..\..\src\thread.c + + + + Libraries + + $PROJ_DIR$\..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Source\system_apm32f10x.c + + + $PROJ_DIR$\..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_rcm.c + + + $PROJ_DIR$\..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_misc.c + + + $PROJ_DIR$\..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_usart.c + + + $PROJ_DIR$\..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_eint.c + + + $PROJ_DIR$\..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_gpio.c + + + + POSIX + + + utestcases + + diff --git a/bsp/apm32/apm32f103xe-minibroard/project.eww b/bsp/apm32/apm32f103xe-minibroard/project.eww new file mode 100644 index 0000000000..c2cb02eb1e --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\project.ewp + + + + + diff --git a/bsp/apm32/apm32f103xe-minibroard/project.uvoptx b/bsp/apm32/apm32f103xe-minibroard/project.uvoptx new file mode 100644 index 0000000000..a46a77a582 --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/project.uvoptx @@ -0,0 +1,805 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + JL2CM3 + -U59701291 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC1000 -FN1 -FF0APM32F10x_512.FLM -FS08000000 -FL080000 -FP0($$Device:APM32F103ZE$Flash\APM32F10x_512.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0APM32F10x_512 -FS08000000 -FL080000 -FP0($$Device:APM32F103ZE$Flash\APM32F10x_512.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Applications + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + applications\main.c + main.c + 0 + 0 + + + + + Compiler + 0 + 0 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\armlibc\libc_syms.c + libc_syms.c + 0 + 0 + + + 2 + 3 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\armlibc\syscalls.c + syscalls.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\armlibc\syscall_mem.c + syscall_mem.c + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\time.c + time.c + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\stdlib.c + stdlib.c + 0 + 0 + + + + + CPU + 0 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\backtrace.c + backtrace.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\showmem.c + showmem.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\div0.c + div0.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\cortex-m3\cpuport.c + cpuport.c + 0 + 0 + + + 3 + 11 + 2 + 0 + 0 + 0 + ..\..\..\libcpu\arm\cortex-m3\context_rvds.S + context_rvds.S + 0 + 0 + + + + + DeviceDrivers + 0 + 0 + 0 + 0 + + 4 + 12 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\misc\pin.c + pin.c + 0 + 0 + + + 4 + 13 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\serial\serial.c + serial.c + 0 + 0 + + + 4 + 14 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\ringbuffer.c + ringbuffer.c + 0 + 0 + + + 4 + 15 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\waitqueue.c + waitqueue.c + 0 + 0 + + + 4 + 16 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\workqueue.c + workqueue.c + 0 + 0 + + + 4 + 17 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\pipe.c + pipe.c + 0 + 0 + + + 4 + 18 + 1 + 0 + 0 + 0 + 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..\..\..\components\finsh\cmd.c + cmd.c + 0 + 0 + + + + + Kernel + 0 + 0 + 0 + 0 + + 7 + 29 + 1 + 0 + 0 + 0 + ..\..\..\src\object.c + object.c + 0 + 0 + + + 7 + 30 + 1 + 0 + 0 + 0 + ..\..\..\src\irq.c + irq.c + 0 + 0 + + + 7 + 31 + 1 + 0 + 0 + 0 + ..\..\..\src\thread.c + thread.c + 0 + 0 + + + 7 + 32 + 1 + 0 + 0 + 0 + ..\..\..\src\mempool.c + mempool.c + 0 + 0 + + + 7 + 33 + 1 + 0 + 0 + 0 + ..\..\..\src\timer.c + timer.c + 0 + 0 + + + 7 + 34 + 1 + 0 + 0 + 0 + ..\..\..\src\kservice.c + kservice.c + 0 + 0 + + + 7 + 35 + 1 + 0 + 0 + 0 + ..\..\..\src\device.c + device.c + 0 + 0 + + + 7 + 36 + 1 + 0 + 0 + 0 + ..\..\..\src\clock.c + clock.c + 0 + 0 + + + 7 + 37 + 1 + 0 + 0 + 0 + ..\..\..\src\scheduler.c + scheduler.c + 0 + 0 + + + 7 + 38 + 1 + 0 + 0 + 0 + ..\..\..\src\mem.c + mem.c + 0 + 0 + + + 7 + 39 + 1 + 0 + 0 + 0 + ..\..\..\src\components.c + components.c + 0 + 0 + + + 7 + 40 + 1 + 0 + 0 + 0 + ..\..\..\src\ipc.c + ipc.c + 0 + 0 + + + 7 + 41 + 1 + 0 + 0 + 0 + ..\..\..\src\idle.c + idle.c + 0 + 0 + + + + + Libraries + 0 + 0 + 0 + 0 + + 8 + 42 + 1 + 0 + 0 + 0 + ..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Source\system_apm32f10x.c + system_apm32f10x.c + 0 + 0 + + + 8 + 43 + 1 + 0 + 0 + 0 + ..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_rcm.c + apm32f10x_rcm.c + 0 + 0 + + + 8 + 44 + 1 + 0 + 0 + 0 + ..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_misc.c + apm32f10x_misc.c + 0 + 0 + + + 8 + 45 + 1 + 0 + 0 + 0 + ..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_usart.c + apm32f10x_usart.c + 0 + 0 + + + 8 + 46 + 1 + 0 + 0 + 0 + ..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_eint.c + apm32f10x_eint.c + 0 + 0 + + + 8 + 47 + 1 + 0 + 0 + 0 + ..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_gpio.c + apm32f10x_gpio.c + 0 + 0 + + + + diff --git a/bsp/apm32/apm32f103xe-minibroard/project.uvprojx b/bsp/apm32/apm32f103xe-minibroard/project.uvprojx index f0af5cb76c..f2f1468945 100644 --- a/bsp/apm32/apm32f103xe-minibroard/project.uvprojx +++ b/bsp/apm32/apm32f103xe-minibroard/project.uvprojx @@ -13,7 +13,7 @@ APM32F103ZE Geehy - Geehy.APM32F1xx_DFP.1.0.7 + Geehy.APM32F1xx_DFP.1.0.8 https://www.geehy.com/uploads/tool/ IRAM(0x20000000,0x00020000) IROM(0x08000000,0x00080000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE @@ -182,7 +182,6 @@ 0 0 0 - 0 0 0 8 @@ -334,9 +333,9 @@ 0 - USE_STDPERIPH_DRIVER, __RTTHREAD__, APM32F103xE, RT_USING_ARM_LIBC, __CLK_TCK=RT_TICK_PER_SECOND + USE_STDPERIPH_DRIVER, APM32F10X_HD, __RTTHREAD__, RT_USING_ARM_LIBC, __CLK_TCK=RT_TICK_PER_SECOND - applications;..\..\..\components\libc\compilers\common;..\..\..\components\libc\compilers\common\extension;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m3;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;..\libraries\Drivers;..\libraries\Drivers\config;..\..\..\components\finsh;.;..\..\..\include;..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Include;..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\inc;..\libraries\APM32F10x_Library\CMSIS\Include;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\posix\io\stdio;..\..\..\components\libc\posix\ipc;..\..\..\examples\utest\testcases\kernel + applications;..\..\..\components\libc\compilers\common;..\..\..\components\libc\compilers\common\nogcc;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m3;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;..\libraries\Drivers;..\libraries\Drivers\config;..\..\..\components\finsh;.;..\..\..\include;..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Include;..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\inc;..\libraries\APM32F10x_Library\CMSIS\Include;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\posix\ipc;..\..\..\examples\utest\testcases\kernel @@ -349,7 +348,7 @@ 0 0 0 - 4 + 0 @@ -391,9 +390,9 @@ Compiler - syscalls.c + libc_syms.c 1 - ..\..\..\components\libc\compilers\armlibc\syscalls.c + ..\..\..\components\libc\compilers\armlibc\libc_syms.c @@ -405,9 +404,9 @@ - stdlib.c + syscalls.c 1 - ..\..\..\components\libc\compilers\common\stdlib.c + ..\..\..\components\libc\compilers\armlibc\syscalls.c @@ -417,6 +416,13 @@ ..\..\..\components\libc\compilers\common\time.c + + + stdlib.c + 1 + ..\..\..\components\libc\compilers\common\stdlib.c + + CPU @@ -429,16 +435,16 @@ - div0.c + backtrace.c 1 - ..\..\..\libcpu\arm\common\div0.c + ..\..\..\libcpu\arm\common\backtrace.c - backtrace.c + div0.c 1 - ..\..\..\libcpu\arm\common\backtrace.c + ..\..\..\libcpu\arm\common\div0.c @@ -458,55 +464,6 @@ DeviceDrivers - - - completion.c - 1 - ..\..\..\components\drivers\ipc\completion.c - - - - - ringbuffer.c - 1 - ..\..\..\components\drivers\ipc\ringbuffer.c - - - - - waitqueue.c - 1 - ..\..\..\components\drivers\ipc\waitqueue.c - - - - - dataqueue.c - 1 - ..\..\..\components\drivers\ipc\dataqueue.c - - - - - pipe.c - 1 - ..\..\..\components\drivers\ipc\pipe.c - - - - - workqueue.c - 1 - ..\..\..\components\drivers\ipc\workqueue.c - - - - - ringblk_buf.c - 1 - ..\..\..\components\drivers\ipc\ringblk_buf.c - - pin.c @@ -521,21 +478,70 @@ ..\..\..\components\drivers\serial\serial.c + + + ringbuffer.c + 1 + ..\..\..\components\drivers\src\ringbuffer.c + + + + + pipe.c + 1 + ..\..\..\components\drivers\src\pipe.c + + + + + ringblk_buf.c + 1 + ..\..\..\components\drivers\src\ringblk_buf.c + + + + + workqueue.c + 1 + ..\..\..\components\drivers\src\workqueue.c + + + + + dataqueue.c + 1 + ..\..\..\components\drivers\src\dataqueue.c + + + + + waitqueue.c + 1 + ..\..\..\components\drivers\src\waitqueue.c + + + + + completion.c + 1 + ..\..\..\components\drivers\src\completion.c + + Drivers - startup_apm32f10x_hd.s - 2 - ..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Source\ARM\startup_apm32f10x_hd.s + board.c + 1 + board\board.c - board.c - 1 - board\board.c + startup_apm32f10x_hd.s + 2 + ..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Source\arm\startup_apm32f10x_hd.s @@ -588,16 +594,37 @@ Kernel - clock.c + thread.c 1 - ..\..\..\src\clock.c + ..\..\..\src\thread.c - kservice.c + mempool.c 1 - ..\..\..\src\kservice.c + ..\..\..\src\mempool.c + + + + + timer.c + 1 + ..\..\..\src\timer.c + + + + + object.c + 1 + ..\..\..\src\object.c + + + + + clock.c + 1 + ..\..\..\src\clock.c @@ -630,9 +657,16 @@ - mempool.c + kservice.c 1 - ..\..\..\src\mempool.c + ..\..\..\src\kservice.c + + + + + irq.c + 1 + ..\..\..\src\irq.c @@ -642,20 +676,6 @@ ..\..\..\src\components.c - - - thread.c - 1 - ..\..\..\src\thread.c - - - - - object.c - 1 - ..\..\..\src\object.c - - idle.c @@ -663,20 +683,6 @@ ..\..\..\src\idle.c - - - timer.c - 1 - ..\..\..\src\timer.c - - - - - irq.c - 1 - ..\..\..\src\irq.c - - Libraries diff --git a/bsp/apm32/apm32f103xe-minibroard/template.ewp b/bsp/apm32/apm32f103xe-minibroard/template.ewp new file mode 100644 index 0000000000..41627fa92c --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/template.ewp @@ -0,0 +1,2114 @@ + + + 3 + + rt-thread + + ARM + + 1 + + General + 3 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + JL2CM3 + -U59701291 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC1000 -FN1 -FF0APM32F10x_512.FLM -FS08000000 -FL080000 -FP0($$Device:APM32F103ZE$Flash\APM32F10x_512.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0APM32F10x_512 -FS08000000 -FL080000 -FP0($$Device:APM32F103ZE$Flash\APM32F10x_512.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Source Group 1 + 0 + 0 + 0 + 0 + + + diff --git a/bsp/apm32/apm32f103xe-minibroard/template.uvprojx b/bsp/apm32/apm32f103xe-minibroard/template.uvprojx index dee46dc63c..03ea186a2b 100644 --- a/bsp/apm32/apm32f103xe-minibroard/template.uvprojx +++ b/bsp/apm32/apm32f103xe-minibroard/template.uvprojx @@ -16,7 +16,7 @@ APM32F103ZE Geehy - Geehy.APM32F1xx_DFP.1.0.7 + Geehy.APM32F1xx_DFP.1.0.8 https://www.geehy.com/uploads/tool/ IRAM(0x20000000,0x00020000) IROM(0x08000000,0x00080000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE @@ -185,7 +185,6 @@ 0 0 0 - 0 0 0 8 @@ -352,7 +351,7 @@ 0 0 0 - 4 + 0 diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_adc.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_adc.h index 8117944933..66741681b0 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_adc.h +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_adc.h @@ -3,21 +3,35 @@ * * @brief This file contains all the functions prototypes for the ADC firmware library * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ #ifndef __APM32F10X_ADC_H #define __APM32F10X_ADC_H -#include "apm32f10x.h" - #ifdef __cplusplus - extern "C" { +extern "C" { #endif +#include "apm32f10x.h" + /** @addtogroup Peripherals_Library Standard Peripheral Library @{ */ @@ -62,7 +76,7 @@ typedef enum ADC_EXT_TRIG_CONV_None = ((uint32_t)0x000E0000), ADC_EXT_TRIG_CONV_TMR3_CC1 = ((uint32_t)0x00000000), - ADC_EXT_TRIG_CONV_TMR2_CC3 = ((uint32_t)0x00030000), + ADC_EXT_TRIG_CONV_TMR2_CC3 = ((uint32_t)0x00020000), ADC_EXT_TRIG_CONV_TMR8_CC1 = ((uint32_t)0x00060000), ADC_EXT_TRIG_CONV_TMR8_TRGO = ((uint32_t)0x00080000), ADC_EXT_TRIG_CONV_TMR5_CC1 = ((uint32_t)0x000A0000), @@ -110,15 +124,15 @@ typedef enum */ typedef enum { - ADC_SAMPLE_TIME_1_5 = ((uint8_t)0x00), - ADC_SAMPLE_TIME_7_5 = ((uint8_t)0x01), - ADC_SAMPLE_TIME_13_5 = ((uint8_t)0x02), - ADC_SAMPLE_TIME_28_5 = ((uint8_t)0x03), - ADC_SAMPLE_TIME_41_5 = ((uint8_t)0x04), - ADC_SAMPLE_TIME_55_5 = ((uint8_t)0x05), - ADC_SAMPLE_TIME_71_5 = ((uint8_t)0x06), - ADC_SAMPLE_TIME_239_5 = ((uint8_t)0x07) -} ADC_SAMPLE_TIME_T; + ADC_SAMPLETIME_1CYCLES5 = ((uint8_t)0x00), + ADC_SAMPLETIME_7CYCLES5 = ((uint8_t)0x01), + ADC_SAMPLETIME_13CYCLES5 = ((uint8_t)0x02), + ADC_SAMPLETIME_28CYCLES5 = ((uint8_t)0x03), + ADC_SAMPLETIME_41CYCLES5 = ((uint8_t)0x04), + ADC_SAMPLETIME_55CYCLES5 = ((uint8_t)0x05), + ADC_SAMPLETIME_71CYCLES5 = ((uint8_t)0x06), + ADC_SAMPLETIME_239CYCLES5 = ((uint8_t)0x07) +} ADC_SAMPLETIME_T; /** * @brief ADC external trigger sources for injected channels conversion @@ -246,80 +260,80 @@ typedef struct */ /** ADC reset and common configuration */ -void ADC_Reset(ADC_T* adc); -void ADC_Config(ADC_T* adc, ADC_Config_T* adcConfig); -void ADC_ConfigStructInit(ADC_Config_T* adcConfig); -void ADC_ConfigRegularChannel(ADC_T* adc, uint8_t channel,uint8_t rank, uint8_t sampleTime); -void ADC_Enable(ADC_T* adc); -void ADC_Disable(ADC_T* adc); +void ADC_Reset(ADC_T *adc); +void ADC_Config(ADC_T *adc, ADC_Config_T *adcConfig); +void ADC_ConfigStructInit(ADC_Config_T *adcConfig); +void ADC_ConfigRegularChannel(ADC_T *adc, uint8_t channel, uint8_t rank, uint8_t sampleTime); +void ADC_Enable(ADC_T *adc); +void ADC_Disable(ADC_T *adc); /** ADC for DMA */ -void ADC_EnableDMA(ADC_T* adc); -void ADC_DisableDMA(ADC_T* adc); +void ADC_EnableDMA(ADC_T *adc); +void ADC_DisableDMA(ADC_T *adc); /** ADC Calibration */ -void ADC_ResetCalibration(ADC_T* adc); -uint8_t ADC_ReadResetCalibrationStatus(ADC_T* adc); -void ADC_StartCalibration(ADC_T* adc); -uint8_t ADC_ReadCalibrationStartFlag(ADC_T* adc); +void ADC_ResetCalibration(ADC_T *adc); +uint8_t ADC_ReadResetCalibrationStatus(ADC_T *adc); +void ADC_StartCalibration(ADC_T *adc); +uint8_t ADC_ReadCalibrationStartFlag(ADC_T *adc); /** ADC software start conversion */ -void ADC_EnableSoftwareStartConv(ADC_T* adc); -void ADC_DisableSoftwareStartConv(ADC_T* adc); -uint8_t ADC_ReadSoftwareStartConvStatus(ADC_T* adc); +void ADC_EnableSoftwareStartConv(ADC_T *adc); +void ADC_DisableSoftwareStartConv(ADC_T *adc); +uint8_t ADC_ReadSoftwareStartConvStatus(ADC_T *adc); /** ADC Discontinuous mode */ -void ADC_ConfigDiscModeChannel(ADC_T* adc, uint8_t number); -void ADC_EnableDiscMode(ADC_T* adc); -void ADC_DisableDiscMode(ADC_T* adc); +void ADC_ConfigDiscMode(ADC_T *adc, uint8_t number); +void ADC_EnableDiscMode(ADC_T *adc); +void ADC_DisableDiscMode(ADC_T *adc); /** ADC External trigger conversion */ -void ADC_EnableExternalTrigConv(ADC_T* adc); -void ADC_DisableExternalTrigConv(ADC_T* adc); +void ADC_EnableExternalTrigConv(ADC_T *adc); +void ADC_DisableExternalTrigConv(ADC_T *adc); /** ADC Conversion result */ -uint16_t ADC_ReadConversionValue(ADC_T* adc); -uint32_t ADC_ReadDualModeConversionValue(ADC_T* adc); +uint16_t ADC_ReadConversionValue(ADC_T *adc); +uint32_t ADC_ReadDualModeConversionValue(ADC_T *adc); /** ADC Automatic injected group */ -void ADC_EnableInjectedConv(ADC_T* adc); -void ADC_DisableInjectedConv(ADC_T* adc); -void ADC_EnableInjectedDiscMode(ADC_T* adc); -void ADC_DisableInjectedDiscMode(ADC_T* adc); +void ADC_EnableAutoInjectedConv(ADC_T *adc); +void ADC_DisableAutoInjectedConv(ADC_T *adc); +void ADC_EnableInjectedDiscMode(ADC_T *adc); +void ADC_DisableInjectedDiscMode(ADC_T *adc); /** ADC External trigger for injected channels conversion */ -void ADC_ConfigExternalTrigInjectedConv(ADC_T* adc, ADC_EXT_TRIG_INJEC_CONV_T extTrigInjecConv); -void ADC_EnableExternalTrigInjectedConv(ADC_T* adc); -void ADC_DisableExternalTrigInjectedConv(ADC_T* adc); +void ADC_ConfigExternalTrigInjectedConv(ADC_T *adc, ADC_EXT_TRIG_INJEC_CONV_T extTrigInjecConv); +void ADC_EnableExternalTrigInjectedConv(ADC_T *adc); +void ADC_DisableExternalTrigInjectedConv(ADC_T *adc); /** ADC Start of the injected channels conversion */ -void ADC_EnableSoftwareStartInjectedConv(ADC_T* adc); -void ADC_DisableSoftwareStartInjectedConv(ADC_T* adc); -uint8_t ADC_ReadSoftwareStartInjectedConvStatus(ADC_T* adc); +void ADC_EnableSoftwareStartInjectedConv(ADC_T *adc); +void ADC_DisableSoftwareStartInjectedConv(ADC_T *adc); +uint8_t ADC_ReadSoftwareStartInjectedConvStatus(ADC_T *adc); /** ADC injected channel */ -void ADC_ConfigInjectedChannel(ADC_T* adc, uint8_t channel, uint8_t rank, uint8_t sampleTime); -void ADC_ConfigInjectedSequencerLength(ADC_T* adc, uint8_t length); -void ADC_ConfigInjectedOffset(ADC_T* adc, ADC_INJEC_CHANNEL_T channel, uint16_t offSet); -uint16_t ADC_ReadInjectedConversionValue(ADC_T* adc, ADC_INJEC_CHANNEL_T channel); +void ADC_ConfigInjectedChannel(ADC_T *adc, uint8_t channel, uint8_t rank, uint8_t sampleTime); +void ADC_ConfigInjectedSequencerLength(ADC_T *adc, uint8_t length); +void ADC_ConfigInjectedOffset(ADC_T *adc, ADC_INJEC_CHANNEL_T channel, uint16_t offSet); +uint16_t ADC_ReadInjectedConversionValue(ADC_T *adc, ADC_INJEC_CHANNEL_T channel); /** ADC analog watchdog */ -void ADC_EnableAnalogWatchdog(ADC_T* adc, uint32_t analogWatchdog); -void ADC_DisableAnalogWatchdog(ADC_T* adc); -void ADC_ConfigAnalogWatchdogThresholds(ADC_T* adc, uint16_t highThreshold, uint16_t lowThreshold); -void ADC_ConfigAnalogWatchdogSingleChannel(ADC_T* adc, uint8_t channel); +void ADC_EnableAnalogWatchdog(ADC_T *adc, uint32_t analogWatchdog); +void ADC_DisableAnalogWatchdog(ADC_T *adc); +void ADC_ConfigAnalogWatchdogThresholds(ADC_T *adc, uint16_t highThreshold, uint16_t lowThreshold); +void ADC_ConfigAnalogWatchdogSingleChannel(ADC_T *adc, uint8_t channel); /** ADC temperature sensor */ -void ADC_EnableTempSensorVrefint(ADC_T* adc); -void ADC_DisableTempSensorVrefint(ADC_T* adc); +void ADC_EnableTempSensorVrefint(ADC_T *adc); +void ADC_DisableTempSensorVrefint(ADC_T *adc); /** Interrupt and flag */ -void ADC_EnableInterrupt(ADC_T* adc, uint16_t interrupt); -void ADC_DisableInterrupt(ADC_T* adc, uint16_t interrupt); -uint8_t ADC_ReadStatusFlag(ADC_T* adc, ADC_FLAG_T flag); -void ADC_ClearStatusFlag(ADC_T* adc, uint8_t flag); -uint8_t ADC_ReadIntFlag(ADC_T* adc, ADC_INT_T interrupt); -void ADC_ClearIntFlag(ADC_T* adc, uint16_t interrupt); +void ADC_EnableInterrupt(ADC_T *adc, uint16_t interrupt); +void ADC_DisableInterrupt(ADC_T *adc, uint16_t interrupt); +uint8_t ADC_ReadStatusFlag(ADC_T *adc, ADC_FLAG_T flag); +void ADC_ClearStatusFlag(ADC_T *adc, uint8_t flag); +uint8_t ADC_ReadIntFlag(ADC_T *adc, ADC_INT_T flag); +void ADC_ClearIntFlag(ADC_T *adc, uint16_t flag); /**@} end of group ADC_Fuctions*/ /**@} end of group ADC_Driver*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_bakpr.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_bakpr.h index 84b12b4fea..ade398cee3 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_bakpr.h +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_bakpr.h @@ -3,21 +3,35 @@ * * @brief This file contains all the functions prototypes for the BAKPR firmware library. * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ #ifndef __APM32F10X_BAKPR_H #define __APM32F10X_BAKPR_H -#include "apm32f10x.h" - #ifdef __cplusplus extern "C" { #endif +#include "apm32f10x.h" + /** @addtogroup Peripherals_Library Standard Peripheral Library @{ */ @@ -125,7 +139,7 @@ uint8_t BAKPR_ReadIntFlag(void); void BAKPR_ClearIntFlag(void); /**@} end of group BAKPR_Fuctions*/ -/**@} end of group BAKPR_Driver */ +/**@} end of group BAKPR_Driver*/ /**@} end of group Peripherals_Library*/ #ifdef __cplusplus diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_can.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_can.h index 766d1918e4..dd49bd0773 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_can.h +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_can.h @@ -1,23 +1,37 @@ /*! - * @file apm32f10x_can.h + * @file apm32f10x_can.h * - * @brief This file contains all the functions prototypes for the CAN firmware library + * @brief This file contains all the functions prototypes for the CAN firmware library * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ #ifndef __APM32F10X_CAN_H #define __APM32F10X_CAN_H -#include "apm32f10x.h" - #ifdef __cplusplus extern "C" { #endif +#include "apm32f10x.h" + /** @addtogroup Peripherals_Library Standard Peripheral Library @{ */ @@ -35,10 +49,10 @@ extern "C" { */ typedef enum { - CAN_MODE_NORMAL = ((uint8_t)00), //!< normal mode - CAN_MODE_LOOPBACK = ((uint8_t)01), //!< loopback mode - CAN_MODE_SILENT = ((uint8_t)02), //!< silent mode - CAN_MODE_SILENT_LOOPBACK = ((uint8_t)03), //!< loopback combined with silent mode + CAN_MODE_NORMAL = ((uint8_t)0x00), //!< normal mode + CAN_MODE_LOOPBACK = ((uint8_t)0x01), //!< loopback mode + CAN_MODE_SILENT = ((uint8_t)0x02), //!< silent mode + CAN_MODE_SILENT_LOOPBACK = ((uint8_t)0x03) //!< loopback combined with silent mode } CAN_MODE_T; /** @@ -46,10 +60,10 @@ typedef enum */ typedef enum { - CAN_SJW_1 = ((uint8_t)00), //!< 1 time quantum - CAN_SJW_2 = ((uint8_t)01), //!< 2 time quantum - CAN_SJW_3 = ((uint8_t)02), //!< 3 time quantum - CAN_SJW_4 = ((uint8_t)03) //!< 4 time quantum + CAN_SJW_1 = ((uint8_t)0x00), //!< 1 time quantum + CAN_SJW_2 = ((uint8_t)0x01), //!< 2 time quantum + CAN_SJW_3 = ((uint8_t)0x02), //!< 3 time quantum + CAN_SJW_4 = ((uint8_t)0x03) //!< 4 time quantum } CAN_SJW_T; /** @@ -87,7 +101,7 @@ typedef enum CAN_TIME_SEGMENT2_5 = (uint8_t)0x04, //!< 5 time quanta CAN_TIME_SEGMENT2_6 = (uint8_t)0x05, //!< 6 time quanta CAN_TIME_SEGMENT2_7 = (uint8_t)0x06, //!< 7 time quanta - CAN_TIME_SEGMENT2_8 = (uint8_t)0x07, //!< 8 time quanta + CAN_TIME_SEGMENT2_8 = (uint8_t)0x07 //!< 8 time quanta } CAN_TIME_SEGMENT2_T; /** @@ -96,7 +110,7 @@ typedef enum typedef enum { CAN_FILTER_FIFO_0 = ((uint8_t)0x00), //!< filter FIFO 0 - CAN_FILTER_FIFO_1 = ((uint8_t)0x01), //!< filter FIFO 1 + CAN_FILTER_FIFO_1 = ((uint8_t)0x01) //!< filter FIFO 1 } CAN_FILTER_FIFO_T; /** @@ -104,8 +118,8 @@ typedef enum */ typedef enum { - CAN_FILTER_MODE_IDMASK = ((uint8_t)00), //!< identifier/mask mode - CAN_FILTER_MODE_IDLIST = ((uint8_t)01) //!< identifier list mode + CAN_FILTER_MODE_IDMASK = ((uint8_t)0x00),//!< identifier/mask mode + CAN_FILTER_MODE_IDLIST = ((uint8_t)0x01) //!< identifier list mode } CAN_FILTER_MODE_T; /** @@ -114,7 +128,7 @@ typedef enum typedef enum { CAN_FILTER_SCALE_16BIT = ((uint8_t)0x00), //!< Two 16-bit filters - CAN_FILTER_SCALE_32BIT = ((uint8_t)0x01), //!< One 32-bit filter + CAN_FILTER_SCALE_32BIT = ((uint8_t)0x01) //!< One 32-bit filter } CAN_FILTER_SCALE_T; /** @@ -142,7 +156,7 @@ typedef enum { CAN_TX_MAILBIX_0 = ((uint8_t)0x00), //!< Tx mailbox0 CAN_TX_MAILBIX_1 = ((uint8_t)0x01), //!< Tx mailbox1 - CAN_TX_MAILBIX_2 = ((uint8_t)0x02), //!< Tx mailbox2 + CAN_TX_MAILBIX_2 = ((uint8_t)0x02) //!< Tx mailbox2 } CAN_TX_MAILBIX_T; /** @@ -151,7 +165,7 @@ typedef enum typedef enum { CAN_RX_FIFO_0 = ((uint8_t)0x00), //!< receive FIFO 0 - CAN_RX_FIFO_1 = ((uint8_t)0x01), //!< receive FIFO 1 + CAN_RX_FIFO_1 = ((uint8_t)0x01) //!< receive FIFO 1 } CAN_RX_FIFO_T; /** @@ -159,9 +173,9 @@ typedef enum */ typedef enum { - CAN_OPERATING_MODE_INIT = ((uint8_t)00), //!< Initialization mode - CAN_OPERATING_MODE_NORMAL = ((uint8_t)01), //!< Normal mode - CAN_OPERATING_MODE_SLEEP = ((uint8_t)02), //!< sleep mode + CAN_OPERATING_MODE_INIT = ((uint8_t)0x00), //!< Initialization mode + CAN_OPERATING_MODE_NORMAL = ((uint8_t)0x01), //!< Normal mode + CAN_OPERATING_MODE_SLEEP = ((uint8_t)0x02) //!< sleep mode } CAN_OPERATING_MODE_T; /** @@ -223,7 +237,6 @@ typedef enum */ typedef struct { - uint8_t timeTrigComMode; //!< Enable or disable the time triggered communication mode. uint8_t autoBusOffManage; //!< Enable or disable the automatic bus-off management. uint8_t autoWakeUpMode; //!< Enable or disable the automatic wake-up mode. uint8_t nonAutoRetran; //!< Enable or disable the non-automatic retransmission mode. @@ -249,7 +262,7 @@ typedef struct CAN_RTXR_T remoteTxReq; uint8_t dataLengthCode;//!< Specifies the data length code. It can be 0 to 8. uint8_t data[8]; //!< Specifies the data to be transmitted. It can be 0 to 0xFF. -} CAN_TX_MESSAGE_T; +} CAN_TxMessage_T; /** * @brief CAN Rx message structure definition @@ -263,7 +276,7 @@ typedef struct uint8_t dataLengthCode; //!< Specifies the data length code. It can be 0 to 8. uint8_t data[8]; //!< Specifies the data to be transmitted. It can be 0 to 0xFF. uint8_t filterMatchIndex;//!< Specifies the filter match index. It can be 0 to 0xFF. -} CAN_RX_MESSAGE_T; +} CAN_RxMessage_T; /** * @brief CAN filter config structure definition @@ -279,7 +292,7 @@ typedef struct CAN_FILTER_FIFO_T filterFIFO; CAN_FILTER_MODE_T filterMode; CAN_FILTER_SCALE_T filterScale; -} CAN_FILTER_CONFIG_T; +} CAN_FilterConfig_T; /**@} end of group CAN_Structure*/ @@ -289,45 +302,44 @@ typedef struct */ /** CAN reset and configuration */ -void CAN_Reset(CAN_T* can); -uint8_t CAN_Config(CAN_T* can, CAN_Config_T* canConfig); -void CAN_ConfigFilter(CAN_T* can, CAN_FILTER_CONFIG_T* filterConfig); -void CAN_ConfigStructInit(CAN_Config_T* canConfig); -void CAN_EnableDBGFreeze(CAN_T* can); -void CAN_DisableDBGFreeze(CAN_T* can); -void CAN_EnableTTCComMode(CAN_T* can); -void CAN_DisableTTCComMode(CAN_T* can); +void CAN_Reset(CAN_T *can); +uint8_t CAN_Config(CAN_T *can, CAN_Config_T *canConfig); +void CAN_ConfigFilter(CAN_T *can, CAN_FilterConfig_T *filterConfig); +void CAN_ConfigStructInit(CAN_Config_T *canConfig); +void CAN_EnableDBGFreeze(CAN_T *can); +void CAN_DisableDBGFreeze(CAN_T *can); +void CAN_SlaveStartBank(CAN_T *can, uint8_t bankNum); /** CAN frames transmit */ -uint8_t CAN_TxMessage(CAN_T* can, CAN_TX_MESSAGE_T* TxMessage); -uint8_t CAN_TxMessageStatus(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox); -void CAN_CancelTxMailbox(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox); +uint8_t CAN_TxMessage(CAN_T *can, CAN_TxMessage_T *TxMessage); +uint8_t CAN_TxMessageStatus(CAN_T *can, CAN_TX_MAILBIX_T TxMailbox); +void CAN_CancelTxMailbox(CAN_T *can, CAN_TX_MAILBIX_T TxMailbox); /** CAN frames receive */ -void CAN_RxMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber, CAN_RX_MESSAGE_T* RxMessage); -void CAN_ReleaseFIFO(CAN_T* can, CAN_RX_FIFO_T FIFONumber); -uint8_t CAN_PendingMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber); +void CAN_RxMessage(CAN_T *can, CAN_RX_FIFO_T FIFONumber, CAN_RxMessage_T *RxMessage); +void CAN_ReleaseFIFO(CAN_T *can, CAN_RX_FIFO_T FIFONumber); +uint8_t CAN_PendingMessage(CAN_T *can, CAN_RX_FIFO_T FIFONumber); /** CAN operation modes */ -uint8_t CAN_OperatingMode(CAN_T* can, CAN_OPERATING_MODE_T operatingMode); -uint8_t CAN_SleepMode(CAN_T* can); -uint8_t CAN_WakeUpMode(CAN_T* can); +uint8_t CAN_OperatingMode(CAN_T *can, CAN_OPERATING_MODE_T operatingMode); +uint8_t CAN_SleepMode(CAN_T *can); +uint8_t CAN_WakeUpMode(CAN_T *can); /** CAN bus error management */ -uint8_t CAN_ReadLastErrorCode(CAN_T* can); -uint8_t CAN_ReadRxErrorCounter(CAN_T* can); -uint8_t CAN_ReadLSBTxErrorCounter(CAN_T* can); +uint8_t CAN_ReadLastErrorCode(CAN_T *can); +uint8_t CAN_ReadRxErrorCounter(CAN_T *can); +uint8_t CAN_ReadLSBTxErrorCounter(CAN_T *can); /** CAN interrupt and flag */ -void CAN_EnableInterrupt(CAN_T* can, uint32_t interrupt); -void CAN_DisableInterrupt(CAN_T* can, uint32_t interrupt); -uint8_t CAN_ReadStatusFlag(CAN_T* can, CAN_FLAG_T flag); -void CAN_ClearStatusFlag(CAN_T* can, CAN_FLAG_T flag); -uint8_t CAN_ReadIntFlag(CAN_T* can, CAN_INT_T flag); -void CAN_ClearIntFlag(CAN_T* can, CAN_INT_T flag); +void CAN_EnableInterrupt(CAN_T *can, uint32_t interrupt); +void CAN_DisableInterrupt(CAN_T *can, uint32_t interrupt); +uint8_t CAN_ReadStatusFlag(CAN_T *can, CAN_FLAG_T flag); +void CAN_ClearStatusFlag(CAN_T *can, CAN_FLAG_T flag); +uint8_t CAN_ReadIntFlag(CAN_T *can, CAN_INT_T flag); +void CAN_ClearIntFlag(CAN_T *can, CAN_INT_T flag); /**@} end of group CAN_Fuctions*/ -/**@} end of group CAN_Driver */ +/**@} end of group CAN_Driver*/ /**@} end of group Peripherals_Library*/ #ifdef __cplusplus diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_crc.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_crc.h index c3a0098aee..3c3f5272d9 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_crc.h +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_crc.h @@ -1,23 +1,37 @@ /*! - * @file apm32f10x_crc.h + * @file apm32f10x_crc.h * - * @brief This file contains all the functions prototypes for the CRC firmware library + * @brief This file contains all the functions prototypes for the CRC firmware library * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ #ifndef __APM32F10X_CRC_H #define __APM32F10X_CRC_H -#include "apm32f10x.h" - #ifdef __cplusplus extern "C" { #endif +#include "apm32f10x.h" + /** @addtogroup Peripherals_Library Standard Peripheral Library @{ */ @@ -41,7 +55,7 @@ void CRC_WriteIDRegister(uint8_t inData); uint8_t CRC_ReadIDRegister(void); /**@} end of group CRC_Fuctions*/ -/**@} end of group CRC_Driver */ +/**@} end of group CRC_Driver*/ /**@} end of group Peripherals_Library*/ #ifdef __cplusplus diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dac.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dac.h index 1fce07ebc1..be1adc048b 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dac.h +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dac.h @@ -3,21 +3,35 @@ * * @brief This file contains all the functions prototypes for the DAC firmware library * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ #ifndef __APM32F10X_DAC_H #define __APM32F10X_DAC_H -#include "apm32f10x.h" - #ifdef __cplusplus - extern "C" { +extern "C" { #endif +#include "apm32f10x.h" + /** @addtogroup Peripherals_Library Standard Peripheral Library @{ */ @@ -37,7 +51,7 @@ typedef enum { DAC_CHANNEL_1 = 0x00000000, DAC_CHANNEL_2 = 0x00000010 -}DAC_CHANNEL_T; +} DAC_CHANNEL_T; /** * @brief DAC trigger selection @@ -53,7 +67,7 @@ typedef enum DAC_TRIGGER_TMR4_TRGO = 0x0000002C, DAC_TRIGGER_EINT9 = 0x00000034, DAC_TRIGGER_SOFT = 0x0000003C -}DAC_TRIGGER_T; +} DAC_TRIGGER_T; /** * @brief DAC wave generation @@ -63,7 +77,7 @@ typedef enum DAC_WAVE_GENERATION_NONE = 0x00000000, DAC_WAVE_GENERATION_NOISE = 0x00000040, DAC_WAVE_GENERATION_TRIANGLE = 0x00000080 -}DAC_WAVE_GENERATION_T; +} DAC_WAVE_GENERATION_T; /** * @brief DAC channelx mask/amplitude selector @@ -71,31 +85,31 @@ typedef enum typedef enum { DAC_LFSR_MASK_BIT11_1 = 0x00000000, //!< Mask bit[11:1] of LFSR for noise wave generation - DAC_LFSR_MASK_BIT11_2 = 0x00001000, //!< Mask bit[11:2] of LFSR for noise wave generation - DAC_LFSR_MASK_BIT11_3 = 0x00002000, //!< Mask bit[11:3] of LFSR for noise wave generation - DAC_LFSR_MASK_BIT11_4 = 0x00003000, //!< Mask bit[11:4] of LFSR for noise wave generation - DAC_LFSR_MASK_BIT11_5 = 0x00004000, //!< Mask bit[11:5] of LFSR for noise wave generation - DAC_LFSR_MASK_BIT11_6 = 0x00005000, //!< Mask bit[11:6] of LFSR for noise wave generation - DAC_LFSR_MASK_BIT11_7 = 0x00006000, //!< Mask bit[11:7] of LFSR for noise wave generation - DAC_LFSR_MASK_BIT11_8 = 0x00007000, //!< Mask bit[11:8] of LFSR for noise wave generation - DAC_LFSR_MASK_BIT11_9 = 0x00008000, //!< Mask bit[11:9] of LFSR for noise wave generation - DAC_LFSR_MASK_BIT11_10 = 0x00009000, //!< Mask bit[11:10] of LFSR for noise wave generation - DAC_LFSR_MASK_BIT11 = 0x0000A000, //!< Mask bit11 of LFSR for noise wave generation - DAC_LFSR_MASK_NONE = 0x0000B000, //!< Mask none bit of LFSR for noise wave generation + DAC_LFSR_MASK_BIT11_2 = 0x00000100, //!< Mask bit[11:2] of LFSR for noise wave generation + DAC_LFSR_MASK_BIT11_3 = 0x00000200, //!< Mask bit[11:3] of LFSR for noise wave generation + DAC_LFSR_MASK_BIT11_4 = 0x00000300, //!< Mask bit[11:4] of LFSR for noise wave generation + DAC_LFSR_MASK_BIT11_5 = 0x00000400, //!< Mask bit[11:5] of LFSR for noise wave generation + DAC_LFSR_MASK_BIT11_6 = 0x00000500, //!< Mask bit[11:6] of LFSR for noise wave generation + DAC_LFSR_MASK_BIT11_7 = 0x00000600, //!< Mask bit[11:7] of LFSR for noise wave generation + DAC_LFSR_MASK_BIT11_8 = 0x00000700, //!< Mask bit[11:8] of LFSR for noise wave generation + DAC_LFSR_MASK_BIT11_9 = 0x00000800, //!< Mask bit[11:9] of LFSR for noise wave generation + DAC_LFSR_MASK_BIT11_10 = 0x00000900, //!< Mask bit[11:10] of LFSR for noise wave generation + DAC_LFSR_MASK_BIT11 = 0x00000A00, //!< Mask bit11 of LFSR for noise wave generation + DAC_LFSR_MASK_NONE = 0x00000B00, //!< Mask none bit of LFSR for noise wave generation DAC_TRIANGLE_AMPLITUDE_1 = 0x00000000, //!< Triangle amplitude equal to 1 - DAC_TRIANGLE_AMPLITUDE_3 = 0x00001000, //!< Triangle amplitude equal to 3 - DAC_TRIANGLE_AMPLITUDE_7 = 0x00002000, //!< Triangle amplitude equal to 7 - DAC_TRIANGLE_AMPLITUDE_15 = 0x00003000, //!< Triangle amplitude equal to 15 - DAC_TRIANGLE_AMPLITUDE_31 = 0x00004000, //!< Triangle amplitude equal to 31 - DAC_TRIANGLE_AMPLITUDE_63 = 0x00005000, //!< Triangle amplitude equal to 63 - DAC_TRIANGLE_AMPLITUDE_127 = 0x00006000, //!< Triangle amplitude equal to 127 - DAC_TRIANGLE_AMPLITUDE_255 = 0x00007000, //!< Triangle amplitude equal to 255 - DAC_TRIANGLE_AMPLITUDE_511 = 0x00008000, //!< Triangle amplitude equal to 511 - DAC_TRIANGLE_AMPLITUDE_1023 = 0x00009000, //!< Triangle amplitude equal to 1023 - DAC_TRIANGLE_AMPLITUDE_2047 = 0x0000A000, //!< Triangle amplitude equal to 2047 - DAC_TRIANGLE_AMPLITUDE_4095 = 0x0000B000 //!< Triangle amplitude equal to 4095 -}DAC_MASK_AMPLITUDE_SEL_T; + DAC_TRIANGLE_AMPLITUDE_3 = 0x00000100, //!< Triangle amplitude equal to 3 + DAC_TRIANGLE_AMPLITUDE_7 = 0x00000200, //!< Triangle amplitude equal to 7 + DAC_TRIANGLE_AMPLITUDE_15 = 0x00000300, //!< Triangle amplitude equal to 15 + DAC_TRIANGLE_AMPLITUDE_31 = 0x00000400, //!< Triangle amplitude equal to 31 + DAC_TRIANGLE_AMPLITUDE_63 = 0x00000500, //!< Triangle amplitude equal to 63 + DAC_TRIANGLE_AMPLITUDE_127 = 0x00000600, //!< Triangle amplitude equal to 127 + DAC_TRIANGLE_AMPLITUDE_255 = 0x00000700, //!< Triangle amplitude equal to 255 + DAC_TRIANGLE_AMPLITUDE_511 = 0x00000800, //!< Triangle amplitude equal to 511 + DAC_TRIANGLE_AMPLITUDE_1023 = 0x00000900, //!< Triangle amplitude equal to 1023 + DAC_TRIANGLE_AMPLITUDE_2047 = 0x00000A00, //!< Triangle amplitude equal to 2047 + DAC_TRIANGLE_AMPLITUDE_4095 = 0x00000B00 //!< Triangle amplitude equal to 4095 +} DAC_MASK_AMPLITUDE_SEL_T; /** * @brief DAC output buffer @@ -104,7 +118,7 @@ typedef enum { DAC_OUTPUT_BUFFER_ENBALE = 0x00000000, DAC_OUTPUT_BUFFER_DISABLE = 0x00000002 -}DAC_OUTPUT_BUFFER_T; +} DAC_OUTPUT_BUFFER_T; /** * @brief DAC data align @@ -114,7 +128,7 @@ typedef enum DAC_ALIGN_12BIT_R = 0x00000000, DAC_ALIGN_12BIT_L = 0x00000004, DAC_ALIGN_8BIT_R = 0x00000008 -}DAC_ALIGN_T; +} DAC_ALIGN_T; /**@} end of group DAC_Enumerations*/ @@ -132,7 +146,7 @@ typedef struct DAC_OUTPUT_BUFFER_T outputBuffer; DAC_WAVE_GENERATION_T waveGeneration; DAC_MASK_AMPLITUDE_SEL_T maskAmplitudeSelect; -}DAC_ConfigStruct_T; +} DAC_Config_T; /**@} end of group DAC_Structure*/ @@ -143,8 +157,8 @@ typedef struct /** DAC Reset and Configuration */ void DAC_Reset(void); -void DAC_Config(uint32_t channel, DAC_ConfigStruct_T* configStruct); -void DAC_ConfigStructInit(DAC_ConfigStruct_T* configStruct); +void DAC_Config(uint32_t channel, DAC_Config_T *dacConfig); +void DAC_ConfigStructInit(DAC_Config_T *dacConfig); void DAC_Enable(DAC_CHANNEL_T channel); void DAC_Disable(DAC_CHANNEL_T channel); @@ -171,7 +185,7 @@ void DAC_ConfigDualChannelData(DAC_ALIGN_T align, uint16_t data2, uint16_t data1 uint16_t DAC_ReadDataOutputValue(DAC_CHANNEL_T channel); /**@} end of group DAC_Fuctions*/ -/**@} end of group DAC_Driver */ +/**@} end of group DAC_Driver*/ /**@} end of group Peripherals_Library*/ #ifdef __cplusplus diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dbgmcu.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dbgmcu.h index 193f86ffba..9102cdabd3 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dbgmcu.h +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dbgmcu.h @@ -3,21 +3,35 @@ * * @brief This file contains all the functions prototypes for the DBUGMCU firmware library * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ #ifndef __APM32F10X_DBGMCU_H #define __APM32F10X_DBGMCU_H -#include "apm32f10x.h" - #ifdef __cplusplus - extern "C" { +extern "C" { #endif +#include "apm32f10x.h" + /** @addtogroup Peripherals_Library Standard Peripheral Library @{ */ @@ -73,7 +87,7 @@ void DBGMCU_Enable(uint32_t periph); void DBGMCU_Disable(uint32_t periph); /**@} end of group DBGMCU_Fuctions*/ -/**@} end of group DBGMCU_Driver */ +/**@} end of group DBGMCU_Driver*/ /**@} end of group Peripherals_Library*/ #ifdef __cplusplus diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dma.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dma.h index eb574afb73..af6335d4c7 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dma.h +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dma.h @@ -1,23 +1,37 @@ /*! - * @file apm32f10x_dma.h + * @file apm32f10x_dma.h * - * @brief This file contains all the functions prototypes for the DMA firmware library + * @brief This file contains all the functions prototypes for the DMA firmware library * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ #ifndef __APM32F10X_DMA_H #define __APM32F10X_DMA_H -#include "apm32f10x.h" - #ifdef __cplusplus extern "C" { #endif +#include "apm32f10x.h" + /** @addtogroup Peripherals_Library Standard Peripheral Library @{ */ @@ -173,7 +187,7 @@ typedef enum } DMA_FLAG_T; /** - * @brief DMA Flag + * @brief DMA Interrupt Flag */ typedef enum { @@ -262,8 +276,8 @@ typedef struct /** Reset and configuration */ void DMA_Reset(DMA_Channel_T *channel); -void DMA_Config(DMA_Channel_T* channel, DMA_Config_T* dmaConfig); -void DMA_ConfigStructInit( DMA_Config_T* dmaConfig); +void DMA_Config(DMA_Channel_T *channel, DMA_Config_T *dmaConfig); +void DMA_ConfigStructInit(DMA_Config_T *dmaConfig); void DMA_Enable(DMA_Channel_T *channel); void DMA_Disable(DMA_Channel_T *channel); @@ -280,7 +294,7 @@ uint8_t DMA_ReadIntFlag(DMA_INT_FLAG_T flag); void DMA_ClearIntFlag(uint32_t flag); /**@} end of group DMA_Fuctions*/ -/**@} end of group DMA_Driver */ +/**@} end of group DMA_Driver*/ /**@} end of group Peripherals_Library*/ #ifdef __cplusplus diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dmc.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dmc.h index 809e2663d7..32e3254ac6 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dmc.h +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dmc.h @@ -3,20 +3,35 @@ * * @brief This file contains all the prototypes,enumeration and macros for the DMC peripheral * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ + #ifndef __APM32F10X_DMC_H #define __APM32F10X_DMC_H -#include "apm32f10x.h" - #ifdef __cplusplus - extern "C" { +extern "C" { #endif +#include "apm32f10x.h" + /** @addtogroup Peripherals_Library Standard Peripheral Library @{ */ @@ -37,7 +52,7 @@ typedef enum { DMC_BANK_WIDTH_1, DMC_BANK_WIDTH_2 -}DMC_BANK_WIDTH_T; +} DMC_BANK_WIDTH_T; /** * @brief Row Address Width @@ -50,7 +65,7 @@ typedef enum DMC_ROW_WIDTH_14, DMC_ROW_WIDTH_15, DMC_ROW_WIDTH_16 -}DMC_ROW_WIDTH_T; +} DMC_ROW_WIDTH_T; /** * @brief Column Address Width @@ -65,7 +80,7 @@ typedef enum DMC_COL_WIDTH_13, DMC_COL_WIDTH_14, DMC_COL_WIDTH_15 -}DMC_COL_WIDTH_T; +} DMC_COL_WIDTH_T; /** * @brief CAS Latency Select @@ -76,7 +91,7 @@ typedef enum DMC_CAS_LATENCY_2, DMC_CAS_LATENCY_3, DMC_CAS_LATENCY_4 -}DMC_CAS_LATENCY_T; +} DMC_CAS_LATENCY_T; /** * @brief RAS Minimun Time Select @@ -99,7 +114,7 @@ typedef enum DMC_RAS_MINIMUM_14, DMC_RAS_MINIMUM_15, DMC_RAS_MINIMUM_16 -}DMC_RAS_MINIMUM_T; +} DMC_RAS_MINIMUM_T; /** * @brief RAS To CAS Delay Time Select @@ -114,7 +129,7 @@ typedef enum DMC_DELAY_TIME_6, DMC_DELAY_TIME_7, DMC_DELAY_TIME_8 -}DMC_DELAY_TIME_T; +} DMC_DELAY_TIME_T; /** * @brief Precharge Period Select @@ -129,10 +144,10 @@ typedef enum DMC_PRECHARGE_6, DMC_PRECHARGE_7, DMC_PRECHARGE_8 -}DMC_PRECHARGE_T; +} DMC_PRECHARGE_T; /** - * @brief Last Data Next Precharge For Write Time Select + * @brief Last Data Next Precharge For Write Time Select */ typedef enum { @@ -140,7 +155,7 @@ typedef enum DMC_NEXT_PRECHARGE_2, DMC_NEXT_PRECHARGE_3, DMC_NEXT_PRECHARGE_4 -}DMC_NEXT_PRECHARGE_T; +} DMC_NEXT_PRECHARGE_T; /** * @brief Auto-Refresh Period Select @@ -163,7 +178,7 @@ typedef enum DMC_AUTO_REFRESH_14, DMC_AUTO_REFRESH_15, DMC_AUTO_REFRESH_16, -}DMC_AUTO_REFRESH_T; +} DMC_AUTO_REFRESH_T; /** * @brief Active-to-active Command Period Select @@ -186,7 +201,7 @@ typedef enum DMC_ATA_CMD_14, DMC_ATA_CMD_15, DMC_ATA_CMD_16, -}DMC_ATA_CMD_T; +} DMC_ATA_CMD_T; /** * @brief Clock PHASE @@ -195,7 +210,7 @@ typedef enum { DMC_CLK_PHASE_NORMAL, DMC_CLK_PHASE_REVERSE -}DMC_CLK_PHASE_T; +} DMC_CLK_PHASE_T; /** * @brief DMC Memory Size @@ -216,10 +231,10 @@ typedef enum DMC_MEMORY_SIZE_64MB, DMC_MEMORY_SIZE_128MB, DMC_MEMORY_SIZE_256MB, -}DMC_MEMORY_SIZE_T; +} DMC_MEMORY_SIZE_T; /** - * @brief Open Banks Of Number + * @brief Open Banks Of Number */ typedef enum { @@ -239,7 +254,7 @@ typedef enum DMC_BANK_NUMBER_14, DMC_BANK_NUMBER_15, DMC_BANK_NUMBER_16, -}DMC_BANK_NUMBER_T; +} DMC_BANK_NUMBER_T; /** * @brief Full refresh type @@ -248,7 +263,7 @@ typedef enum { DMC_REFRESH_ROW_ONE, //!< Refresh one row DMC_REFRESH_ROW_ALL, //!< Refresh all row -}DMC_REFRESH_T; +} DMC_REFRESH_T; /** * @brief Precharge type @@ -257,8 +272,16 @@ typedef enum { DMC_PRECHARGE_IM, //!< Immediate precharge DMC_PRECHARGE_DELAY, //!< Delayed precharge -}DMC_PRECHARE_T; +} DMC_PRECHARE_T; +/** + * @brief WRAP Burst Type + */ +typedef enum +{ + DMC_WRAPB_4, + DMC_WRAPB_8, +} DMC_WRPB_T; /**@} end of group DMC_Enumerations*/ @@ -281,7 +304,7 @@ typedef struct uint32_t tCMD : 4; //!< DMC_ATA_CMD_T uint32_t tXSR : 9; //!< auto-refresh commands, can be 0x000 to 0x1FF uint16_t tRFP : 16; //!< Refresh period, can be 0x0000 to 0xFFFF -}DMC_TimingConfig_T; +} DMC_TimingConfig_T; /** * @brief Config struct definition @@ -294,7 +317,7 @@ typedef struct DMC_COL_WIDTH_T colWidth; //!< Number of col address bits DMC_CLK_PHASE_T clkPhase; //!< Clock phase DMC_TimingConfig_T timing; //!< Timing -}DMC_Config_T; +} DMC_Config_T; /**@} end of group DMC_Structure*/ @@ -303,7 +326,7 @@ typedef struct @{ */ - /** Enable / Disable */ +/** Enable / Disable */ void DMC_Enable(void); void DMC_Disable(void); void DMC_EnableInit(void); @@ -327,6 +350,10 @@ void DMC_ConfigRefreshPeriod(uint16_t period); void DMC_EixtSlefRefreshMode(void); void DMC_EnterSlefRefreshMode(void); +/** Accelerate Module */ +void DMC_EnableAccelerateModule(void); +void DMC_DisableAccelerateModule(void); + /** Config */ void DMC_ConfigOpenBank(DMC_BANK_NUMBER_T num); void DMC_EnableUpdateMode(void); @@ -336,6 +363,7 @@ void DMC_ConfigFullRefreshAfterSR(DMC_REFRESH_T refresh); void DMC_ConfigPrechargeType(DMC_PRECHARE_T precharge); void DMC_ConfigMemorySize(DMC_MEMORY_SIZE_T memorySize); void DMC_ConfigClockPhase(DMC_CLK_PHASE_T clkPhase); +void DMC_ConfigWRAPB(DMC_WRPB_T burst); /** read flag */ uint8_t DMC_ReadSelfRefreshStatus(void); diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_eint.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_eint.h index 23bedc9b02..9594405210 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_eint.h +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_eint.h @@ -1,23 +1,37 @@ /*! - * @file apm32f10x_eint.h + * @file apm32f10x_eint.h * - * @brief This file contains all the functions prototypes for the EINT firmware library + * @brief This file contains all the functions prototypes for the EINT firmware library * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ #ifndef __APM32F10X_EINT_H #define __APM32F10X_EINT_H -#include "apm32f10x.h" - #ifdef __cplusplus extern "C" { #endif +#include "apm32f10x.h" + /** @addtogroup Peripherals_Library Standard Peripheral Library @{ */ @@ -51,6 +65,7 @@ typedef enum typedef enum { + EINT_LINENONE = 0x00000, //! EINT_LINE_0 = 0x00001, //!< External interrupt line 0 EINT_LINE_1 = 0x00002, //!< External interrupt line 1 EINT_LINE_2 = 0x00004, //!< External interrupt line 2 @@ -99,7 +114,8 @@ typedef struct /** Reset and configuration */ void EINT_Reset(void); -void EINT_Config( EINT_Config_T* eintConfig); +void EINT_Config(EINT_Config_T *eintConfig); +void EINT_ConfigStructInit(EINT_Config_T *eintConfig); /** Interrupt and flag */ void EINT_SelectSWInterrupt(uint32_t line); @@ -109,11 +125,11 @@ uint8_t EINT_ReadIntFlag(EINT_LINE_T line); void EINT_ClearIntFlag(uint32_t line); /**@} end of group EINT_Fuctions*/ -/**@} end of group EINT_Driver */ +/**@} end of group EINT_Driver*/ /**@} end of group Peripherals_Library*/ -#ifdef __APM32F10X_cplusplus +#ifdef __cplusplus } #endif -#endif /* __EINT_H */ +#endif /* __APM32F10XEINT_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_emmc.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_emmc.h index 5b5c82e727..1c6d7ecc18 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_emmc.h +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_emmc.h @@ -1,23 +1,37 @@ /*! - * @file apm32f10x_emmc.h + * @file apm32f10x_emmc.h * - * @brief This file contains all the functions prototypes for the EMMC firmware library + * @brief This file contains all the functions prototypes for the EMMC firmware library * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ #ifndef __APM32F10X_EMMC_H #define __APM32F10X_EMMC_H -#include "apm32f10x.h" - #ifdef __cplusplus extern "C" { #endif +#include "apm32f10x.h" + /** @addtogroup Peripherals_Library Standard Peripheral Library @{ */ @@ -66,7 +80,7 @@ typedef enum typedef enum { EMMC_MEMORY_TYPE_SRAM = 0x00000000, - EMMC_MEMORY_TYPE_PARAM = 0x00000004, + EMMC_MEMORY_TYPE_PSRAM = 0x00000004, EMMC_MEMORY_TYPE_NOR = 0x00000008 } EMMC_MEMORY_TYPE_T; @@ -262,8 +276,8 @@ typedef struct EMMC_WAITE_SIGNAL_T waiteSignal; EMMC_EXTENDEN_MODE_T extendedMode; EMMC_WRITE_BURST_T writeBurst; - EMMC_NORSRAMTimingConfig_T* readWriteTimingStruct; - EMMC_NORSRAMTimingConfig_T* writeTimingStruct; + EMMC_NORSRAMTimingConfig_T *readWriteTimingStruct; + EMMC_NORSRAMTimingConfig_T *writeTimingStruct; } EMMC_NORSRAMConfig_T; /** @@ -289,8 +303,8 @@ typedef struct EMMC_ECC_PAGE_SIZE_BYTE_T ECCPageSize; uint32_t TCLRSetupTime; uint32_t TARSetupTime; - EMMC_NAND_PCCARDTimingConfig_T* commonSpaceTimingStruct; - EMMC_NAND_PCCARDTimingConfig_T* attributeSpaceTimingStruct; + EMMC_NAND_PCCARDTimingConfig_T *commonSpaceTimingStruct; + EMMC_NAND_PCCARDTimingConfig_T *attributeSpaceTimingStruct; } EMMC_NANDConfig_T; /** @@ -301,9 +315,9 @@ typedef struct EMMC_WAIT_FEATURE_T waitFeature; uint32_t TCLRSetupTime; uint32_t TARSetupTime; - EMMC_NAND_PCCARDTimingConfig_T* commonSpaceTimingStruct; - EMMC_NAND_PCCARDTimingConfig_T* attributeSpaceTimingStruct; - EMMC_NAND_PCCARDTimingConfig_T* IOSpaceTimingStruct; + EMMC_NAND_PCCARDTimingConfig_T *commonSpaceTimingStruct; + EMMC_NAND_PCCARDTimingConfig_T *attributeSpaceTimingStruct; + EMMC_NAND_PCCARDTimingConfig_T *IOSpaceTimingStruct; } EMMC_PCCARDConfig_T; /**@} end of group EMMC_Structure*/ @@ -318,12 +332,12 @@ void EMMC_ResetNAND(EMMC_BANK_NAND_T bank); void EMMC_ResetPCCard(void); /** EMMC Configuration */ -void EMMC_ConfigNORSRAM(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig); -void EMMC_ConfigNAND(EMMC_NANDConfig_T* emmcNANDConfig); -void EMMC_ConfigPCCard(EMMC_PCCARDConfig_T* emmcPCCardConfig); -void EMMC_ConfigNORSRAMStructInit(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig); -void EMMC_ConfigNANDStructInit(EMMC_NANDConfig_T* emmcNANDConfig); -void EMMC_ConfigPCCardStructInit(EMMC_PCCARDConfig_T* emmcPCCardConfig); +void EMMC_ConfigNORSRAM(EMMC_NORSRAMConfig_T *emmcNORSRAMConfig); +void EMMC_ConfigNAND(EMMC_NANDConfig_T *emmcNANDConfig); +void EMMC_ConfigPCCard(EMMC_PCCARDConfig_T *emmcPCCardConfig); +void EMMC_ConfigNORSRAMStructInit(EMMC_NORSRAMConfig_T *emmcNORSRAMConfig); +void EMMC_ConfigNANDStructInit(EMMC_NANDConfig_T *emmcNANDConfig); +void EMMC_ConfigPCCardStructInit(EMMC_PCCARDConfig_T *emmcPCCardConfig); /** EMMC bank control */ void EMMC_EnableNORSRAM(EMMC_BANK1_NORSRAM_T bank); @@ -345,7 +359,7 @@ uint8_t EMMC_ReadIntFlag(EMMC_BANK_NAND_T bank, EMMC_INT_T flag); void EMMC_ClearIntFlag(EMMC_BANK_NAND_T bank, uint32_t flag); /**@} end of group EMMC_Fuctions*/ -/**@} end of group EMMC_Driver */ +/**@} end of group EMMC_Driver*/ /**@} end of group Peripherals_Library*/ #ifdef __cplusplus diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_fmc.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_fmc.h index 5915185f6f..0043073ad6 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_fmc.h +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_fmc.h @@ -1,23 +1,37 @@ /*! - * @file apm32f10x_fmc.h + * @file apm32f10x_fmc.h * - * @brief This file contains all the functions prototypes for the FMC firmware library + * @brief This file contains all the functions prototypes for the FMC firmware library * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ #ifndef __APM32F10X_FMC_H #define __APM32F10X_FMC_H -#include "apm32f10x.h" - #ifdef __cplusplus extern "C" { #endif +#include "apm32f10x.h" + /** @addtogroup Peripherals_Library Standard Peripheral Library @{ */ @@ -224,7 +238,7 @@ FMC_STATUS_T FMC_ProgramOptionByteData(uint32_t address, uint8_t data); FMC_STATUS_T FMC_EnableWriteProtection(uint32_t page); FMC_STATUS_T FMC_EnableReadOutProtection(void); FMC_STATUS_T FMC_DisableReadOutProtection(void); -FMC_STATUS_T FMC_ConfigUserOptionByte(FMC_UserConfig_T* userConfig); +FMC_STATUS_T FMC_ConfigUserOptionByte(FMC_UserConfig_T *userConfig); uint32_t FMC_ReadUserOptionByte(void); uint32_t FMC_ReadOptionByteWriteProtection(void); uint8_t FMC_GetReadProtectionStatus(void); @@ -234,7 +248,7 @@ uint8_t FMC_ReadPrefetchBufferStatus(void); void FMC_EnableInterrupt(FMC_INT_T interrupt); void FMC_DisableInterrupt(FMC_INT_T interrupt); uint8_t FMC_ReadStatusFlag(FMC_FLAG_T flag); -void FMC_ClearStatusFlag(FMC_FLAG_T flag); +void FMC_ClearStatusFlag(uint32_t flag); /** Status management */ FMC_STATUS_T FMC_ReadStatus(void); diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_gpio.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_gpio.h index e78ac91b01..3c66a798e2 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_gpio.h +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_gpio.h @@ -1,23 +1,37 @@ /*! - * @file apm32f10x_gpio.h + * @file apm32f10x_gpio.h * - * @brief This file contains all the functions prototypes for the GPIO firmware library + * @brief This file contains all the functions prototypes for the GPIO firmware library * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ #ifndef __APM32F10X_GPIO_H #define __APM32F10X_GPIO_H -#include "apm32f10x.h" - #ifdef __cplusplus - extern "C" { +extern "C" { #endif +#include "apm32f10x.h" + /** @addtogroup Peripherals_Library Standard Peripheral Library @{ */ @@ -35,10 +49,10 @@ */ typedef enum { - GPIO_SPEED_10MHz = 1, - GPIO_SPEED_2MHz, - GPIO_SPEED_50MHz -}GPIO_SPEED_T; + GPIO_SPEED_10MHz = 1, + GPIO_SPEED_20MHz, + GPIO_SPEED_50MHz +} GPIO_SPEED_T; /** * @brief Configuration Mode enumeration @@ -53,7 +67,7 @@ typedef enum GPIO_MODE_OUT_OD = 0x84, //!< General purpose output Open-drain GPIO_MODE_AF_PP = 0x88, //!< Alternate function output Push-pull GPIO_MODE_AF_OD = 0x8C, //!< Alternate function output Open-drain -}GPIO_MODE_T; +} GPIO_MODE_T; /** * @brief Definition of the GPIO pins @@ -84,108 +98,108 @@ typedef enum */ typedef enum { - GPIO_NO_REMAP_SPI1 = 0x00000010, - GPIO_REMAP_SPI1 = 0x00000011, + GPIO_NO_REMAP_SPI1 = 0x00000010, + GPIO_REMAP_SPI1 = 0x00000011, - GPIO_NO_REMAP_I2C1 = 0x00000110, - GPIO_REMAP_I2C1 = 0x00000111, + GPIO_NO_REMAP_I2C1 = 0x00000110, + GPIO_REMAP_I2C1 = 0x00000111, - GPIO_NO_REMAP_USART1 = 0x00000210, - GPIO_REMAP_USART1 = 0x00000211, + GPIO_NO_REMAP_USART1 = 0x00000210, + GPIO_REMAP_USART1 = 0x00000211, - GPIO_NO_REMAP_USART2 = 0x00000310, - GPIO_REMAP_USART2 = 0x00000311, + GPIO_NO_REMAP_USART2 = 0x00000310, + GPIO_REMAP_USART2 = 0x00000311, - GPIO_NO_REMAP_USART3 = 0x00000430, - GPIO_PARTIAL_REMAP_USART3 = 0x00000431, - GPIO_FULL_REMAP_USART3 = 0x00000433, + GPIO_NO_REMAP_USART3 = 0x00000430, + GPIO_PARTIAL_REMAP_USART3 = 0x00000431, + GPIO_FULL_REMAP_USART3 = 0x00000433, - GPIO_NO_REMAP_TMR1 = 0x00000630, - GPIO_PARTIAL_REMAP_TMR1 = 0x00000631, - GPIO_FULL_REMAP_TMR1 = 0x00000633, + GPIO_NO_REMAP_TMR1 = 0x00000630, + GPIO_PARTIAL_REMAP_TMR1 = 0x00000631, + GPIO_FULL_REMAP_TMR1 = 0x00000633, - GPIO_NO_REMAP_TMR2 = 0x00000830, - GPIO_PARTIAL_REMAP1_TMR2 = 0x00000831, - GPIO_PARTIAL_REMAP2_TMR2 = 0x00000832, - GPIO_FULL_REMAP_TMR2 = 0x00000833, + GPIO_NO_REMAP_TMR2 = 0x00000830, + GPIO_PARTIAL_REMAP1_TMR2 = 0x00000831, + GPIO_PARTIAL_REMAP2_TMR2 = 0x00000832, + GPIO_FULL_REMAP_TMR2 = 0x00000833, - GPIO_NO_REMAP_TMR3 = 0x00000A30, - GPIO_PARTIAL_REMAP_TMR3 = 0x00000A32, - GPIO_FULL_REMAP_TMR3 = 0x00000A33, + GPIO_NO_REMAP_TMR3 = 0x00000A30, + GPIO_PARTIAL_REMAP_TMR3 = 0x00000A32, + GPIO_FULL_REMAP_TMR3 = 0x00000A33, - GPIO_NO_REMAP_TMR4 = 0x00000C10, - GPIO_REMAP_TMR4 = 0x00000C11, + GPIO_NO_REMAP_TMR4 = 0x00000C10, + GPIO_REMAP_TMR4 = 0x00000C11, - GPIO_NO_REMAP_CAN1 = 0x00000D30, - GPIO_REMAP1_CAN1 = 0x00000D32, - GPIO_REMAP2_CAN1 = 0x00000D33, + GPIO_NO_REMAP_CAN1 = 0x00000D30, + GPIO_REMAP1_CAN1 = 0x00000D32, + GPIO_REMAP2_CAN1 = 0x00000D33, - GPIO_NO_REMAP_PD01 = 0x00000F10, - GPIO_REMAP_PD01 = 0x00000F11, + GPIO_NO_REMAP_PD01 = 0x00000F10, + GPIO_REMAP_PD01 = 0x00000F11, - GPIO_NO_REMAP_TMR5CH4_LSI = 0x00001010, - GPIO_REMAP_TMR5CH4_LSI = 0x00001011, + GPIO_NO_REMAP_TMR5CH4_LSI = 0x00001010, + GPIO_REMAP_TMR5CH4_LSI = 0x00001011, - GPIO_NO_REMAP_ADC1_ETRGINJ = 0x00001110, - GPIO_REMAP_ADC1_ETRGINJ = 0x00001111, + GPIO_NO_REMAP_ADC1_ETRGINJ = 0x00001110, + GPIO_REMAP_ADC1_ETRGINJ = 0x00001111, - GPIO_NO_REMAP_ADC1_ETRGREG = 0x00001210, - GPIO_REMAP_ADC1_ETRGREG = 0x00001211, + GPIO_NO_REMAP_ADC1_ETRGREG = 0x00001210, + GPIO_REMAP_ADC1_ETRGREG = 0x00001211, - GPIO_NO_REMAP_ADC2_ETRGINJ = 0x00001310, - GPIO_REMAP_ADC2_ETRGINJ = 0x00001311, + GPIO_NO_REMAP_ADC2_ETRGINJ = 0x00001310, + GPIO_REMAP_ADC2_ETRGINJ = 0x00001311, - GPIO_NO_REMAP_ADC2_ETRGREG = 0x00001410, - GPIO_REMAP_ADC2_ETRGREG = 0x00001411, + GPIO_NO_REMAP_ADC2_ETRGREG = 0x00001410, + GPIO_REMAP_ADC2_ETRGREG = 0x00001411, - GPIO_NO_REMAP_CAN2 = 0x00001610, - GPIO_REMAP_CAN2 = 0x00001611, + GPIO_NO_REMAP_CAN2 = 0x00001610, + GPIO_REMAP_CAN2 = 0x00001611, - GPIO_NO_REMAP_SWJ = 0x00001870, - GPIO_REMAP_SWJ_NOJTRST = 0x00001871, - GPIO_REMAP_SWJ_JTAGDISABLE = 0x00001872, - GPIO_REMAP_SWJ_DISABLE = 0x00001874, + GPIO_NO_REMAP_SWJ = 0x00001870, + GPIO_REMAP_SWJ_NOJTRST = 0x00001871, + GPIO_REMAP_SWJ_JTAGDISABLE = 0x00001872, + GPIO_REMAP_SWJ_DISABLE = 0x00001874, - GPIO_NO_REMAP_EMMC_NADV = 0x00010A10, - GPIO_REMAP_EMMC_NADV = 0x00010A11, -}GPIO_REMAP_T; + GPIO_NO_REMAP_EMMC_NADV = 0x00010A10, + GPIO_REMAP_EMMC_NADV = 0x00010A11, +} GPIO_REMAP_T; /** * @brief gpio port source define */ typedef enum { - GPIO_PORT_SOURCE_A, - GPIO_PORT_SOURCE_B, - GPIO_PORT_SOURCE_C, - GPIO_PORT_SOURCE_D, - GPIO_PORT_SOURCE_E, - GPIO_PORT_SOURCE_F, - GPIO_PORT_SOURCE_G, -}GPIO_PORT_SOURCE_T; + GPIO_PORT_SOURCE_A, + GPIO_PORT_SOURCE_B, + GPIO_PORT_SOURCE_C, + GPIO_PORT_SOURCE_D, + GPIO_PORT_SOURCE_E, + GPIO_PORT_SOURCE_F, + GPIO_PORT_SOURCE_G, +} GPIO_PORT_SOURCE_T; /** * @brief gpio pin source define */ typedef enum { - GPIO_PIN_SOURCE_0, - GPIO_PIN_SOURCE_1, - GPIO_PIN_SOURCE_2, - GPIO_PIN_SOURCE_3, - GPIO_PIN_SOURCE_4, - GPIO_PIN_SOURCE_5, - GPIO_PIN_SOURCE_6, - GPIO_PIN_SOURCE_7, - GPIO_PIN_SOURCE_8, - GPIO_PIN_SOURCE_9, - GPIO_PIN_SOURCE_10, - GPIO_PIN_SOURCE_11, - GPIO_PIN_SOURCE_12, - GPIO_PIN_SOURCE_13, - GPIO_PIN_SOURCE_14, - GPIO_PIN_SOURCE_15, -}GPIO_PIN_SOURCE_T; + GPIO_PIN_SOURCE_0, + GPIO_PIN_SOURCE_1, + GPIO_PIN_SOURCE_2, + GPIO_PIN_SOURCE_3, + GPIO_PIN_SOURCE_4, + GPIO_PIN_SOURCE_5, + GPIO_PIN_SOURCE_6, + GPIO_PIN_SOURCE_7, + GPIO_PIN_SOURCE_8, + GPIO_PIN_SOURCE_9, + GPIO_PIN_SOURCE_10, + GPIO_PIN_SOURCE_11, + GPIO_PIN_SOURCE_12, + GPIO_PIN_SOURCE_13, + GPIO_PIN_SOURCE_14, + GPIO_PIN_SOURCE_15, +} GPIO_PIN_SOURCE_T; /**@} end of group GPIO_Enumerations*/ @@ -199,10 +213,10 @@ typedef enum */ typedef struct { - uint16_t pin; - GPIO_SPEED_T speed; - GPIO_MODE_T mode; -}GPIO_Config_T; + uint16_t pin; + GPIO_SPEED_T speed; + GPIO_MODE_T mode; +} GPIO_Config_T; /**@} end of group GPIO_Structure*/ @@ -211,25 +225,25 @@ typedef struct */ /** Reset and common Configuration */ -void GPIO_Reset(GPIO_T* port); +void GPIO_Reset(GPIO_T *port); void GPIO_AFIOReset(void); -void GPIO_Config(GPIO_T* port, GPIO_Config_T* gpioConfig); -void GPIO_StructInit(GPIO_Config_T* gpioConfig); +void GPIO_Config(GPIO_T *port, GPIO_Config_T *gpioConfig); +void GPIO_ConfigStructInit(GPIO_Config_T *gpioConfig); /** Read */ -uint8_t GPIO_ReadInputBit(GPIO_T* port, uint16_t pin); -uint16_t GPIO_ReadInputPort(GPIO_T* port); -uint8_t GPIO_ReadOutputBit(GPIO_T* port, uint16_t pin); -uint16_t GPIO_ReadOutputPort(GPIO_T* port); +uint8_t GPIO_ReadInputBit(GPIO_T *port, uint16_t pin); +uint16_t GPIO_ReadInputPort(GPIO_T *port); +uint8_t GPIO_ReadOutputBit(GPIO_T *port, uint16_t pin); +uint16_t GPIO_ReadOutputPort(GPIO_T *port); /** Write */ -void GPIO_SetBits(GPIO_T* port, uint16_t pin); -void GPIO_ResetBits(GPIO_T* port, uint16_t pin); -void GPIO_WriteOutputPort(GPIO_T* port, uint16_t portValue); -void GPIO_WriteBitValue(GPIO_T* port, uint16_t pin, uint8_t bitVal); +void GPIO_SetBit(GPIO_T *port, uint16_t pin); +void GPIO_ResetBit(GPIO_T *port, uint16_t pin); +void GPIO_WriteOutputPort(GPIO_T *port, uint16_t portValue); +void GPIO_WriteBitValue(GPIO_T *port, uint16_t pin, uint8_t bitVal); /** GPIO Configuration */ -void GPIO_ConfigPinLock(GPIO_T* port, uint16_t pin); +void GPIO_ConfigPinLock(GPIO_T *port, uint16_t pin); void GPIO_ConfigEventOutput(GPIO_PORT_SOURCE_T portSource, GPIO_PIN_SOURCE_T pinSource); void GPIO_EnableEventOutput(void); void GPIO_DisableEventOutput(void); @@ -237,7 +251,7 @@ void GPIO_ConfigPinRemap(GPIO_REMAP_T remap); void GPIO_ConfigEINTLine(GPIO_PORT_SOURCE_T portSource, GPIO_PIN_SOURCE_T pinSource); /**@} end of group GPIO_Fuctions*/ -/**@} end of group GPIO_Driver */ +/**@} end of group GPIO_Driver*/ /**@} end of group Peripherals_Library*/ #ifdef __cplusplus diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_i2c.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_i2c.h index 49c6537e11..aef9810509 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_i2c.h +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_i2c.h @@ -1,23 +1,37 @@ /*! - * @file apm32f10x_i2c.h + * @file apm32f10x_i2c.h * - * @brief This file contains all the functions prototypes for the I2C firmware library + * @brief This file contains all the functions prototypes for the I2C firmware library * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ #ifndef __APM32F10X_I2C_H #define __APM32F10X_I2C_H -#include "apm32f10x.h" - #ifdef __cplusplus extern "C" { #endif +#include "apm32f10x.h" + /** @addtogroup Peripherals_Library Standard Peripheral Library @{ */ @@ -269,59 +283,59 @@ typedef struct */ /** I2C reset and configuration */ -void I2C_Reset(I2C_T* i2c); -void I2C_Config(I2C_T* i2c, I2C_Config_T* i2cConfig); -void I2C_ConfigStructInit(I2C_Config_T* i2cConfig); -void I2C_Enable(I2C_T* i2c); -void I2C_Disable(I2C_T* i2c); -void I2C_EnableGenerateStart(I2C_T* i2c); -void I2C_DisableGenerateStart(I2C_T* i2c); -void I2C_EnableGenerateStop(I2C_T* i2c); -void I2C_DisableGenerateStop(I2C_T* i2c); -void I2C_EnableAcknowledge(I2C_T* i2c); -void I2C_DisableAcknowledge(I2C_T* i2c); -void I2C_ConfigOwnAddress2(I2C_T* i2c, uint8_t address); -void I2C_EnableDualAddress(I2C_T* i2c); -void I2C_DisableDualAddress(I2C_T* i2c); -void I2C_EnableGeneralCall(I2C_T* i2c); -void I2C_DisableGeneralCall(I2C_T* i2c); +void I2C_Reset(I2C_T *i2c); +void I2C_Config(I2C_T *i2c, I2C_Config_T *i2cConfig); +void I2C_ConfigStructInit(I2C_Config_T *i2cConfig); +void I2C_Enable(I2C_T *i2c); +void I2C_Disable(I2C_T *i2c); +void I2C_EnableGenerateStart(I2C_T *i2c); +void I2C_DisableGenerateStart(I2C_T *i2c); +void I2C_EnableGenerateStop(I2C_T *i2c); +void I2C_DisableGenerateStop(I2C_T *i2c); +void I2C_EnableAcknowledge(I2C_T *i2c); +void I2C_DisableAcknowledge(I2C_T *i2c); +void I2C_ConfigOwnAddress2(I2C_T *i2c, uint8_t address); +void I2C_EnableDualAddress(I2C_T *i2c); +void I2C_DisableDualAddress(I2C_T *i2c); +void I2C_EnableGeneralCall(I2C_T *i2c); +void I2C_DisableGeneralCall(I2C_T *i2c); /** Transmit Configuration */ -void I2C_TxData(I2C_T* i2c, uint8_t data); -uint8_t I2C_RxData(I2C_T* i2c); -void I2C_Tx7BitAddress(I2C_T* i2c, uint8_t address, I2C_DIRECTION_T direction); -uint16_t I2C_ReadRegister(I2C_T* i2c, I2C_REGISTER_T i2cRegister); -void I2C_EnableSoftwareReset(I2C_T* i2c); -void I2C_DisableSoftwareReset(I2C_T* i2c); -void I2C_ConfigNACKPosition(I2C_T* i2c, I2C_NACK_POSITION_T NACKPosition); -void I2C_ConfigSMBusAlert(I2C_T* i2c, I2C_SMBUSALER_T SMBusState); -void I2C_EnablePECTransmit(I2C_T* i2c); -void I2C_DisablePECTransmit(I2C_T* i2c); -void I2C_ConfigPECPosition(I2C_T* i2c, I2C_PEC_POSITION_T PECPosition); -void I2C_EnablePEC(I2C_T* i2c); -void I2C_DisablePEC(I2C_T* i2c); -uint8_t I2C_ReadPEC(I2C_T* i2c); -void I2C_EnableARP(I2C_T* i2c); -void I2C_DisableARP(I2C_T* i2c); -void I2C_EnableStretchClock(I2C_T* i2c); -void I2C_DisableStretchClock(I2C_T* i2c); -void I2C_ConfigFastModeDutyCycle(I2C_T* i2c, I2C_DUTYCYCLE_T dutyCycle); +void I2C_TxData(I2C_T *i2c, uint8_t data); +uint8_t I2C_RxData(I2C_T *i2c); +void I2C_Tx7BitAddress(I2C_T *i2c, uint8_t address, I2C_DIRECTION_T direction); +uint16_t I2C_ReadRegister(I2C_T *i2c, I2C_REGISTER_T i2cRegister); +void I2C_EnableSoftwareReset(I2C_T *i2c); +void I2C_DisableSoftwareReset(I2C_T *i2c); +void I2C_ConfigNACKPosition(I2C_T *i2c, I2C_NACK_POSITION_T NACKPosition); +void I2C_ConfigSMBusAlert(I2C_T *i2c, I2C_SMBUSALER_T SMBusState); +void I2C_EnablePECTransmit(I2C_T *i2c); +void I2C_DisablePECTransmit(I2C_T *i2c); +void I2C_ConfigPECPosition(I2C_T *i2c, I2C_PEC_POSITION_T PECPosition); +void I2C_EnablePEC(I2C_T *i2c); +void I2C_DisablePEC(I2C_T *i2c); +uint8_t I2C_ReadPEC(I2C_T *i2c); +void I2C_EnableARP(I2C_T *i2c); +void I2C_DisableARP(I2C_T *i2c); +void I2C_EnableStretchClock(I2C_T *i2c); +void I2C_DisableStretchClock(I2C_T *i2c); +void I2C_ConfigFastModeDutyCycle(I2C_T *i2c, I2C_DUTYCYCLE_T dutyCycle); /** DMA */ -void I2C_EnableDMA(I2C_T* i2c); -void I2C_DisableDMA(I2C_T* i2c); -void I2C_EnableDMALastTransfer(I2C_T* i2c); -void I2C_DisableDMALastTransfer(I2C_T* i2c); +void I2C_EnableDMA(I2C_T *i2c); +void I2C_DisableDMA(I2C_T *i2c); +void I2C_EnableDMALastTransfer(I2C_T *i2c); +void I2C_DisableDMALastTransfer(I2C_T *i2c); /** Interrupts and flags */ -void I2C_EnableInterrupt(I2C_T* i2c, uint16_t interrupt); -void I2C_DisableInterrupt(I2C_T* i2c, uint16_t interrupt); -uint8_t I2C_ReadEventStatus(I2C_T* i2c, I2C_EVENT_T i2cEvent); -uint32_t I2C_ReadLastEvent(I2C_T* i2c); -uint8_t I2C_ReadStatusFlag(I2C_T* i2c, I2C_FLAG_T flag); -void I2C_ClearStatusFlag(I2C_T* i2c, I2C_FLAG_T flag); -uint8_t I2C_ReadIntFlag(I2C_T* i2c, I2C_INT_FLAG_T flag); -void I2C_ClearIntFlag(I2C_T* i2c, I2C_INT_FLAG_T flag); +void I2C_EnableInterrupt(I2C_T *i2c, uint16_t interrupt); +void I2C_DisableInterrupt(I2C_T *i2c, uint16_t interrupt); +uint8_t I2C_ReadEventStatus(I2C_T *i2c, I2C_EVENT_T i2cEvent); +uint32_t I2C_ReadLastEvent(I2C_T *i2c); +uint8_t I2C_ReadStatusFlag(I2C_T *i2c, I2C_FLAG_T flag); +void I2C_ClearStatusFlag(I2C_T *i2c, I2C_FLAG_T flag); +uint8_t I2C_ReadIntFlag(I2C_T *i2c, I2C_INT_FLAG_T flag); +void I2C_ClearIntFlag(I2C_T *i2c, uint32_t flag); /**@} end of group I2C_Fuctions*/ /**@} end of group I2C_Driver*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_iwdt.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_iwdt.h index 45c2c34c4d..b169681d02 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_iwdt.h +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_iwdt.h @@ -3,21 +3,35 @@ * * @brief This file contains all the functions prototypes for the IWDT firmware library * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ #ifndef __APM32F10X_IWDT_H #define __APM32F10X_IWDT_H -#include "apm32f10x.h" - #ifdef __cplusplus - extern "C" { +extern "C" { #endif +#include "apm32f10x.h" + /** @addtogroup Peripherals_Library Standard Peripheral Library @{ */ @@ -37,7 +51,7 @@ typedef enum { IWDT_KEYWORD_RELOAD = 0xAAAA, IWDT_KEYWORD_ENABLE = 0xCCCC -}IWDT_KEYWORD_T; +} IWDT_KEYWORD_T; /** * @brief IWDT Write Access define @@ -46,7 +60,7 @@ typedef enum { IWDT_WRITEACCESS_ENABLE = 0x5555, IWDT_WRITEACCESS_DISABLE = 0x0000 -}IWDT_WRITEACCESS_T; +} IWDT_WRITEACCESS_T; /** * @brief IWDT Divider @@ -60,7 +74,7 @@ typedef enum IWDT_DIVIDER_64 = 0x04, IWDT_DIVIDER_128 = 0x05, IWDT_DIVIDER_256 = 0x06 -}IWDT_DIVIDER_T; +} IWDT_DIVIDER_T; /** * @brief IWDT Flag @@ -69,7 +83,7 @@ typedef enum { IWDT_FLAG_PSCU = BIT0, IWDT_FLAG_CNTU = BIT1 -}IWDT_FLAG_T; +} IWDT_FLAG_T; /**@} end of group IWDT_Enumerations*/ @@ -98,7 +112,7 @@ void IWDT_DisableWriteAccess(void); uint8_t IWDT_ReadStatusFlag(uint16_t flag); /**@} end of group IWDT_Fuctions*/ -/**@} end of group IWDT_Driver */ +/**@} end of group IWDT_Driver*/ /**@} end of group Peripherals_Library*/ #ifdef __cplusplus diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_misc.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_misc.h index fbc8171da0..3ef1cdea11 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_misc.h +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_misc.h @@ -1,24 +1,38 @@ /*! - * @file apm32f10x_misc.h + * @file apm32f10x_misc.h * - * @brief This file provides all the miscellaneous firmware functions. + * @brief This file provides all the miscellaneous firmware functions. * Include NVIC,SystemTick and Power management. * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ #ifndef __APM32F10X_MISC_H #define __APM32F10X_MISC_H -#include "apm32f10x.h" - #ifdef __cplusplus - extern "C" { +extern "C" { #endif +#include "apm32f10x.h" + /** @addtogroup Peripherals_Library Standard Peripheral Library @{ */ @@ -36,19 +50,19 @@ */ typedef enum { - NVIC_VECT_TAB_RAM = 0x20000000, - NVIC_VECT_TAB_FLASH = 0x08000000, -}NVIC_VECT_TAB_T; + NVIC_VECT_TAB_RAM = 0x20000000, + NVIC_VECT_TAB_FLASH = 0x08000000, +} NVIC_VECT_TAB_T; /** * @brief system low power mode */ typedef enum { - NVIC_LOWPOWER_SEVONPEND = 0x10, - NVIC_LOWPOWER_SLEEPDEEP = 0x04, - NVIC_LOWPOWER_SLEEPONEXIT = 0x02 -}NVIC_LOWPOWER_T; + NVIC_LOWPOWER_SEVONPEND = 0x10, + NVIC_LOWPOWER_SLEEPDEEP = 0x04, + NVIC_LOWPOWER_SLEEPONEXIT = 0x02 +} NVIC_LOWPOWER_T; /** * @brief nvic priority group @@ -60,16 +74,16 @@ typedef enum NVIC_PRIORITY_GROUP_2 = 0x500, //!< 2 bits for pre-emption priority,2 bits for subpriority NVIC_PRIORITY_GROUP_3 = 0x400, //!< 3 bits for pre-emption priority,1 bits for subpriority NVIC_PRIORITY_GROUP_4 = 0x300 //!< 4 bits for pre-emption priority,0 bits for subpriority -}NVIC_PRIORITY_GROUP_T; +} NVIC_PRIORITY_GROUP_T; /** * @brief SysTick Clock source */ typedef enum { - SYSTICK_CLK_SOURCE_HCLK_DIV8 = 0x00, - SYSTICK_CLK_SOURCE_HCLK = 0x01 -}SYSTICK_CLK_SOURCE_T; + SYSTICK_CLK_SOURCE_HCLK_DIV8 = 0x00, + SYSTICK_CLK_SOURCE_HCLK = 0x01 +} SYSTICK_CLK_SOURCE_T; /**@} end of group MISC_Enumerations*/ @@ -93,6 +107,10 @@ void NVIC_ResetystemLowPower(NVIC_LOWPOWER_T lowPowerMode); /** Systick */ void SysTick_ConfigCLKSource(SYSTICK_CLK_SOURCE_T clkSource); +/**@} end of group MISC_Fuctions*/ +/**@} end of group MISC_Driver*/ +/**@} end of group Peripherals_Library*/ + #ifdef __cplusplus } #endif diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_pmu.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_pmu.h index 873686a220..204bdafaf0 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_pmu.h +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_pmu.h @@ -1,23 +1,37 @@ /*! - * @file apm32f10x_pmu.h + * @file apm32f10x_pmu.h * - * @brief This file contains all the functions prototypes for the PMU firmware library. + * @brief This file contains all the functions prototypes for the PMU firmware library. * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ #ifndef __APM32F10X_PMU_H #define __APM32F10X_PMU_H -#include "apm32f10x.h" - #ifdef __cplusplus extern "C" { #endif +#include "apm32f10x.h" + /** @addtogroup Peripherals_Library Standard Peripheral Library @{ */ @@ -30,6 +44,9 @@ extern "C" { @{ */ +/** + * @brief PMU PVD detection level + */ typedef enum { PMU_PVD_LEVEL_2V2 = 0x00, //!< PVD detection level set to 2.2V @@ -42,18 +59,27 @@ typedef enum PMU_PVD_LEVEL_2V9 = 0x07, //!< PVD detection level set to 2.9V } PMU_PVD_LEVEL_T; +/** + * @brief PMU Regulator state in STOP mode + */ typedef enum { PMU_REGULATOR_ON = 0x00, PMU_REGULATOR_LOWPOWER = 0x01 } PMU_REGULATOR_T; +/** + * @brief PMU STOP mode entry + */ typedef enum { PMU_STOP_ENTRY_WFI = 0x01, PMU_STOP_ENTRY_WFE = 0x02 } PMU_STOP_ENTRY_T; +/** + * @brief PMU Flag + */ typedef enum { PMU_FLAG_WUE, @@ -87,7 +113,7 @@ uint8_t PMU_ReadStatusFlag(PMU_FLAG_T flag); void PMU_ClearStatusFlag(PMU_FLAG_T flag); /**@} end of group PMU_Fuctions*/ -/**@} end of group PMU_Driver */ +/**@} end of group PMU_Driver*/ /**@} end of group Peripherals_Library*/ #ifdef __cplusplus diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_qspi.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_qspi.h index 8a373eb326..592cfcbd63 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_qspi.h +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_qspi.h @@ -3,21 +3,35 @@ * * @brief This file contains all the prototypes,enumeration and macros for the QSPI peripheral * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ - + #ifndef __APM32F10X_QSPI_H #define __APM32F10X_QSPI_H -#include "apm32f10x.h" - #ifdef __cplusplus - extern "C" { +extern "C" { #endif +#include "apm32f10x.h" + /** @addtogroup Peripherals_Library Standard Peripheral Library @{ */ @@ -38,7 +52,7 @@ typedef enum QSPI_FRF_STANDARD, //!< Standard mode QSPI_FRF_DUAL, //!< Dual SPI QSPI_FRF_QUAD //!< QUAD SPI -}QSPI_FRF_T; +} QSPI_FRF_T; /** * @brief Transmission mode @@ -48,8 +62,8 @@ typedef enum QSPI_TRANS_MODE_TX_RX, //!< TX and RX mode QSPI_TRANS_MODE_TX, //!< TX mode only QSPI_TRANS_MODE_RX, //!< RX mode only - QSPI_TRANS_MODE_EEPROM_READ, //!< EEPROM read mode -}QSPI_TRANS_MODE_T; + QSPI_TRANS_MODE_EEPROM_READ //!< EEPROM read mode +} QSPI_TRANS_MODE_T; /** * @brief Clock polarity @@ -57,8 +71,8 @@ typedef enum typedef enum { QSPI_CLKPOL_LOW, - QSPI_CLKPOL_HIGH, -}QSPI_CLKPOL_T; + QSPI_CLKPOL_HIGH +} QSPI_CLKPOL_T; /** * @brief Clock phase @@ -67,7 +81,7 @@ typedef enum { QSPI_CLKPHA_1EDGE, QSPI_CLKPHA_2EDGE -}QSPI_CLKPHA_T; +} QSPI_CLKPHA_T; /** * @brief Data format size @@ -102,8 +116,8 @@ typedef enum QSPI_DFS_29BIT, QSPI_DFS_30BIT, QSPI_DFS_31BIT, - QSPI_DFS_32BIT, -}QSPI_DFS_T; + QSPI_DFS_32BIT +} QSPI_DFS_T; /** * @brief QSPI flag @@ -116,7 +130,7 @@ typedef enum QSPI_FLAG_RFNE = BIT3, //!< RX FIFO not empty flag QSPI_FLAG_RFF = BIT4, //!< RX FIFO full flag QSPI_FLAG_DCE = BIT6 //!< Data collision error -}QSPI_FLAG_T; +} QSPI_FLAG_T; /** * @brief QSPI interrupt source @@ -128,8 +142,8 @@ typedef enum QSPI_INT_RFU = BIT2, //!< RX FIFO underflow interrupt QSPI_INT_RFO = BIT3, //!< RX FIFO overflow interrupt QSPI_INT_RFF = BIT4, //!< RX FIFO full interrupt - QSPI_INT_MST = BIT5, //!< Master interrupt -}QSPI_INT_T; + QSPI_INT_MST = BIT5 //!< Master interrupt +} QSPI_INT_T; /** * @brief QSPI interrupt flag @@ -141,8 +155,8 @@ typedef enum QSPI_INT_FLAG_RFU = BIT2, //!< RX FIFO underflow interrupt flag QSPI_INT_FLAG_RFO = BIT3, //!< RX FIFO overflow interrupt flag QSPI_INT_FLAG_RFF = BIT4, //!< RX FIFO full interrupt flag - QSPI_INT_FLAG_MST = BIT5, //!< Master interrupt flag -}QSPI_INT_FLAG_T; + QSPI_INT_FLAG_MST = BIT5 //!< Master interrupt flag +} QSPI_INT_FLAG_T; /** * @brief Reception sample edge @@ -151,7 +165,7 @@ typedef enum { QSPI_RSE_RISING, QSPI_RSE_FALLING -}QSPI_RSE_T; +} QSPI_RSE_T; /** * @brief Instruction length @@ -161,8 +175,8 @@ typedef enum QSPI_INST_LEN_0, QSPI_INST_LEN_4BIT, QSPI_INST_LEN_8BIT, - QSPI_INST_LEN_16BIT, -}QSPI_INST_LEN_T; + QSPI_INST_LEN_16BIT +} QSPI_INST_LEN_T; /** * @brief QSPI address length @@ -184,8 +198,8 @@ typedef enum QSPI_ADDR_LEN_48BIT, QSPI_ADDR_LEN_52BIT, QSPI_ADDR_LEN_56BIT, - QSPI_ADDR_LEN_60BIT, -}QSPI_ADDR_LEN_T; + QSPI_ADDR_LEN_60BIT +} QSPI_ADDR_LEN_T; /** * @brief Instruction and address transmission mode @@ -194,8 +208,8 @@ typedef enum { QSPI_INST_ADDR_TYPE_STANDARD, QSPI_INST_TYPE_STANDARD, - QSPI_INST_ADDR_TYPE_FRF, -}QSPI_INST_ADDR_TYPE_T; + QSPI_INST_ADDR_TYPE_FRF +} QSPI_INST_ADDR_TYPE_T; /** * @brief Slave Select Toggle @@ -203,8 +217,8 @@ typedef enum typedef enum { QSPI_SST_DISABLE, - QSPI_SST_ENABLE, -}QSPI_SST_T; + QSPI_SST_ENABLE +} QSPI_SST_T; /**@} end of group QSPI_Enumerations*/ @@ -255,7 +269,7 @@ typedef struct QSPI_CLKPOL_T clockPolarity; //!< Clock polarity QSPI_CLKPHA_T clockPhase; //!< Clock phase QSPI_DFS_T dataFrameSize; //!< Data frame size -}QSPI_Config_T; +} QSPI_Config_T; /**@} end of group QSPI_Structure*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_rcm.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_rcm.h index 0d4ba102fa..10651ba794 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_rcm.h +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_rcm.h @@ -1,23 +1,37 @@ /*! - * @file apm32f10x_rcm.h + * @file apm32f10x_rcm.h * - * @brief This file contains all the functions prototypes for the RCM firmware library + * @brief This file contains all the functions prototypes for the RCM firmware library * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ #ifndef __APM32F10X_RCM_H #define __APM32F10X_RCM_H -#include "apm32f10x.h" - #ifdef __cplusplus extern "C" { #endif +#include "apm32f10x.h" + /** @addtogroup Peripherals_Library Standard Peripheral Library @{ */ @@ -35,9 +49,9 @@ extern "C" { */ typedef enum { - RCM_HSE_CLOSE, //!< CLOSE HSE - RCM_HSE_OPEN, //!< OPEN HSE - RCM_HSE_BYPASS, //!< HSE BYPASS + RCM_HSE_CLOSE, + RCM_HSE_OPEN, + RCM_HSE_BYPASS } RCM_HSE_T; /** @@ -59,7 +73,7 @@ typedef enum RCM_PLLMF_13, RCM_PLLMF_14, RCM_PLLMF_15, - RCM_PLLMF_16, + RCM_PLLMF_16 } RCM_PLLMF_T; /** @@ -85,7 +99,7 @@ typedef enum RCM_AHB_DIV_64, RCM_AHB_DIV_128, RCM_AHB_DIV_256, - RCM_AHB_DIV_512, + RCM_AHB_DIV_512 } RCM_AHB_DIV_T; /** @@ -117,7 +131,7 @@ typedef enum typedef enum { RCM_FPU_DIV_1, - RCM_FPU_DIV_2, + RCM_FPU_DIV_2 } RCM_FPU_DIV_T; /** @@ -128,7 +142,7 @@ typedef enum RCM_PCLK2_DIV_2, RCM_PCLK2_DIV_4, RCM_PCLK2_DIV_6, - RCM_PCLK2_DIV_8, + RCM_PCLK2_DIV_8 } RCM_PCLK2_DIV_T; /** @@ -160,7 +174,7 @@ typedef enum RCM_MCOCLK_SYSCLK, RCM_MCOCLK_HSI, RCM_MCOCLK_HSE, - RCM_MCOCLK_PLLCLK_DIV_2, + RCM_MCOCLK_PLLCLK_DIV_2 } RCM_MCOCLK_T; /** @@ -199,7 +213,7 @@ typedef enum RCM_AHB_PERIPH_QSPI = BIT5, RCM_AHB_PERIPH_CRC = BIT6, RCM_AHB_PERIPH_EMMC = BIT8, - RCM_AHB_PERIPH_SDIO = BIT10, + RCM_AHB_PERIPH_SDIO = BIT10 } RCM_AHB_PERIPH_T; /** @@ -221,7 +235,7 @@ typedef enum RCM_APB2_PERIPH_SPI1 = BIT12, RCM_APB2_PERIPH_TMR8 = BIT13, RCM_APB2_PERIPH_USART1 = BIT14, - RCM_APB2_PERIPH_ADC3 = BIT15, + RCM_APB2_PERIPH_ADC3 = BIT15 } RCM_APB2_PERIPH_T; /** @@ -249,7 +263,7 @@ typedef enum RCM_APB1_PERIPH_CAN2 = BIT26, RCM_APB1_PERIPH_BAKR = BIT27, RCM_APB1_PERIPH_PMU = BIT28, - RCM_APB1_PERIPH_DAC = BIT29, + RCM_APB1_PERIPH_DAC = BIT29 } RCM_APB1_PERIPH_T; /** @@ -267,7 +281,7 @@ typedef enum RCM_FLAG_SWRST = 0x21C, //!< Software reset flag RCM_FLAG_IWDTRST = 0x21D, //!< Independent watchdog reset flag RCM_FLAG_WWDTRST = 0x21E, //!< Window watchdog reset flag - RCM_FLAG_LPRRST = 0x21F, //!< Low-power reset flag + RCM_FLAG_LPRRST = 0x21F //!< Low-power reset flag } RCM_FLAG_T; /**@} end of group RCM_Enumerations*/ @@ -287,7 +301,7 @@ void RCM_ConfigHSE(RCM_HSE_T state); uint8_t RCM_WaitHSEReady(void); /** HSI clock */ -void RCM_SetHSITrim(uint8_t HSITrim); +void RCM_ConfigHSITrim(uint8_t HSITrim); void RCM_EnableHSI(void); void RCM_DisableHSI(void); @@ -325,7 +339,7 @@ void RCM_DisableRTCCLK(void); /** Reads the clock frequency */ uint32_t RCM_ReadSYSCLKFreq(void); uint32_t RCM_ReadHCLKFreq(void); -void RCM_ReadPCLKFreq(uint32_t* PCLK1, uint32_t* PCLK2); +void RCM_ReadPCLKFreq(uint32_t *PCLK1, uint32_t *PCLK2); uint32_t RCM_ReadADCCLKFreq(void); /** Enable or disable Periph Clock */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_rtc.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_rtc.h index 5e243794f6..6b5c37cf60 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_rtc.h +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_rtc.h @@ -1,23 +1,37 @@ /*! - * @file apm32f10x_rtc.h + * @file apm32f10x_rtc.h * - * @brief This file contains all the functions prototypes for the RTC firmware library + * @brief This file contains all the functions prototypes for the RTC firmware library * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ #ifndef __APM32F10X_RTC_H #define __APM32F10X_RTC_H -#include "apm32f10x.h" - #ifdef __cplusplus extern "C" { #endif +#include "apm32f10x.h" + /** @addtogroup Peripherals_Library Standard Peripheral Library @{ */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_sci2c.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_sci2c.h index fe6e1a6138..f4fa60f3ed 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_sci2c.h +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_sci2c.h @@ -3,21 +3,35 @@ * * @brief This file contains all the prototypes,enumeration and macros for the SCI2C(I2C3, I2C4) peripheral * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ #ifndef __APM32F10X_SCI2C_H #define __APM32F10X_SCI2C_H -#include "apm32f10x.h" - #ifdef __cplusplus - extern "C" { +extern "C" { #endif +#include "apm32f10x.h" + /** @addtogroup Peripherals_Library Standard Peripheral Library @{ */ @@ -38,7 +52,7 @@ typedef enum SCI2C_SPEED_STANDARD = 1, SCI2C_SPEED_FAST, SCI2C_SPEED_HIGH -}SCI2C_SPEED_T; +} SCI2C_SPEED_T; /** * @brief Address mode @@ -47,7 +61,7 @@ typedef enum { SCI2C_ADDR_MODE_7BIT, SCI2C_ADDR_MODE_10BIT -}SCI2C_ADDR_MODE_T; +} SCI2C_ADDR_MODE_T; /** * @brief SCI2C mode enumeration @@ -56,7 +70,7 @@ typedef enum { SCI2C_MODE_MASTER, SCI2C_MODE_SLAVE -}SCI2C_MODE_T; +} SCI2C_MODE_T; /** * @brief Restart enable or disable @@ -65,7 +79,7 @@ typedef enum { SCI2C_RESTART_DISABLE, SCI2C_RESTART_ENABLE -}SCI2C_RESTART_T; +} SCI2C_RESTART_T; /** * @brief Enable or disable generate stop condition @@ -74,7 +88,7 @@ typedef enum { SCI2C_STOP_DISABLE, SCI2C_STOP_ENABLE -}SCI2C_STOP_T; +} SCI2C_STOP_T; /** * @brief Data direction */ @@ -82,7 +96,7 @@ typedef enum { SCI2C_DATA_DIR_WRITE, SCI2C_DATA_DIR_READ, -}SCI2C_DATA_DIR_T; +} SCI2C_DATA_DIR_T; /** * @brief SCI2C interrupt @@ -104,7 +118,7 @@ typedef enum SCI2C_INT_RSTAD = BIT12, //!< Restart detect interrupt SCI2C_INT_MOH = BIT13, //!< Master on hold interrupt SCI2C_INT_ALL = BIT15 //!< All interrupt -}SCI2C_INT_T; +} SCI2C_INT_T; /** * @brief Flag enumeration @@ -121,7 +135,7 @@ typedef enum SCI2C_FLAG_I2CEN = BIT8 | BIT0, //!< I2C enable flag SCI2C_FLAG_SDWB = BIT8 | BIT1, //!< Slave disable while busy flag SCI2C_FLAG_SRDL = BIT8 | BIT2 //!< Slave receive data lost flag -}SCI2C_FLAG_T; +} SCI2C_FLAG_T; /** * @brief Tx abort source @@ -144,7 +158,7 @@ typedef enum SCI2C_TAS_SRI = BIT13, //!< Slave read done SCI2C_TAS_USRARB = BIT14, //!< User abort SCI2C_TAS_FLUCNT = BIT15 //!< Tx flush counter -}SCI2C_TAS_T; +} SCI2C_TAS_T; /** * @brief DMA Enable @@ -153,7 +167,7 @@ typedef enum { SCI2C_DMA_RX = BIT0, SCI2C_DMA_TX = BIT1, -}SCI2C_DMA_T; +} SCI2C_DMA_T; /**@} end of group SCI2C_Enumerations*/ @@ -213,7 +227,7 @@ typedef struct uint8_t txFifoThreshold; //!< Tx FIFO threshold SCI2C_RESTART_T restart; //!< Enable or disable restart SCI2C_ADDR_MODE_T addrMode; //!< Address mode. 7-bit or 10-bit mode. -}SCI2C_Config_T; +} SCI2C_Config_T; /**@} end of group SCI2C_Structure*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_sdio.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_sdio.h index cc29cc3c8f..98b83aa94c 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_sdio.h +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_sdio.h @@ -3,21 +3,35 @@ * * @brief This file contains all the functions prototypes for the SDIO firmware library * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ #ifndef __APM32F10X_SDIO_H #define __APM32F10X_SDIO_H -#include "apm32f10x.h" - #ifdef __cplusplus - extern "C" { +extern "C" { #endif +#include "apm32f10x.h" + /** @addtogroup Peripherals_Library Standard Peripheral Library @{ */ @@ -37,7 +51,7 @@ typedef enum { SDIO_CLOCK_EDGE_RISING = 0x00000000, SDIO_CLOCK_EDGE_FALLING = 0x00002000 -}SDIO_CLOCK_EDGE_T; +} SDIO_CLOCK_EDGE_T; /** * @brief SDIO clock bypass @@ -46,7 +60,7 @@ typedef enum { SDIO_CLOCK_BYPASS_DISABLE = 0x00000000, SDIO_CLOCK_BYPASS_ENABLE = 0x00000400 -}SDIO_CLOCK_BYPASS_T; +} SDIO_CLOCK_BYPASS_T; /** * @brief SDIO clock power save @@ -55,17 +69,17 @@ typedef enum { SDIO_CLOCK_POWER_SAVE_DISABLE = 0x00000000, SDIO_CLOCK_POWER_SAVE_ENABLE = 0x00000200 -}SDIO_CLOCK_POWER_SAVE_T; +} SDIO_CLOCK_POWER_SAVE_T; /** * @brief SDIO bus wide */ typedef enum { - SDIO_BUSWIDE_1B = 0x00000000, - SDIO_BUSWIDE_4B = 0x00000800, - SDIO_BUSWIDE_8B = 0x00001000 -}SDIO_BUSWIDE_T; + SDIO_BUS_WIDE_1B = 0x00000000, + SDIO_BUS_WIDE_4B = 0x00000800, + SDIO_BUS_WIDE_8B = 0x00001000 +} SDIO_BUS_WIDE_T; /** * @brief SDIO hardware flow control @@ -74,7 +88,7 @@ typedef enum { SDIO_HARDWARE_FLOW_CONTROL_DISABLE = 0x00000000, SDIO_HARDWARE_FLOW_CONTROL_ENABLE = 0x00004000 -}SDIO_HARDWARE_FLOW_CONTROL_T; +} SDIO_HARDWARE_FLOW_CONTROL_T; /** * @brief SDIO power state @@ -83,7 +97,7 @@ typedef enum { SDIO_POWER_STATE_OFF = 0x00000000, SDIO_POWER_STATE_ON = 0x00000003 -}SDIO_POWER_STATE_T; +} SDIO_POWER_STATE_T; /** * @brief SDIO interrupt sources @@ -114,7 +128,7 @@ typedef enum SDIO_INT_RXDA = 0x00200000, SDIO_INT_SDIOINT = 0x00400000, SDIO_INT_ATAEND = 0x00800000 -}SDIO_INT_T; +} SDIO_INT_T; /** * @brief SDIO response @@ -124,7 +138,7 @@ typedef enum SDIO_RESPONSE_NO = 0x00000000, SDIO_RESPONSE_SHORT = 0x00000040, SDIO_RESPONSE_LONG = 0x000000C0 -}SDIO_RESPONSE_T; +} SDIO_RESPONSE_T; /** * @brief SDIO wait interrupt state @@ -134,7 +148,7 @@ typedef enum SDIO_WAIT_NO = 0x00000000, SDIO_WAIT_INT = 0x00000100, SDIO_WAIT_PEND = 0x00000200 -}SDIO_WAIT_T; +} SDIO_WAIT_T; /** * @brief SDIO CPSM state @@ -143,7 +157,7 @@ typedef enum { SDIO_CPSM_DISABLE = 0x00000000, SDIO_CPSM_ENABLE = 0x00000400 -}SDIO_CPSM_T; +} SDIO_CPSM_T; /** * @brief SDIO response registers @@ -154,7 +168,7 @@ typedef enum SDIO_RES2 = 0x00000004, SDIO_RES3 = 0x00000008, SDIO_RES4 = 0x0000000C -}SDIO_RES_T; +} SDIO_RES_T; /** * @brief SDIO data block size @@ -176,16 +190,16 @@ typedef enum SDIO_DATA_BLOCKSIZE_496B = 0x000000C0, SDIO_DATA_BLOCKSIZE_8192B = 0x000000D0, SDIO_DATA_BLOCKSIZE_16384B = 0x000000E0 -}SDIO_DATA_BLOCKSIZE_T; +} SDIO_DATA_BLOCKSIZE_T; /** * @brief SDIO transfer direction */ typedef enum { - SDIO_TRANSFER_DIR_TOCARD = 0x00000000, - SDIO_TRANSFER_DIR_TOSDIO = 0x00000002 -}SDIO_TRANSFER_DIR_T; + SDIO_TRANSFER_DIR_TO_CARD = 0x00000000, + SDIO_TRANSFER_DIR_TO_SDIO = 0x00000002 +} SDIO_TRANSFER_DIR_T; /** * @brief SDIO transfer type @@ -194,7 +208,7 @@ typedef enum { SDIO_TRANSFER_MODE_BLOCK = 0x00000000, SDIO_TRANSFER_MODE_STREAM = 0x00000004 -}SDIO_TRANSFER_MODE_T; +} SDIO_TRANSFER_MODE_T; /** * @brief SDIO DPSM state @@ -203,7 +217,7 @@ typedef enum { SDIO_DPSM_DISABLE = 0x00000000, SDIO_DPSM_ENABLE = 0x00000001 -}SDIO_DPSM_T; +} SDIO_DPSM_T; /** * @brief SDIO flag @@ -234,7 +248,7 @@ typedef enum SDIO_FLAG_RXDA = 0x00200000, SDIO_FLAG_SDIOINT = 0x00400000, SDIO_FLAG_ATAEND = 0x00800000 -}SDIO_FLAG_T; +} SDIO_FLAG_T; /** * @brief SDIO read wait mode @@ -243,7 +257,7 @@ typedef enum { SDIO_READ_WAIT_MODE_CLK = 0x00000001, SDIO_READ_WAIT_MODE_DATA2 = 0x00000000 -}SDIO_READ_WAIT_MODE_T; +} SDIO_READ_WAIT_MODE_T; /**@} end of group SDIO_Enumerations*/ @@ -255,52 +269,52 @@ typedef enum /** ------------ SDIO registers bit address in the alias region ----------- */ #define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) -/* --- CLKCTRL Register ---*/ +/** --- CLKCTRL Register ---*/ -/* Alias word address of CLKEN bit */ +/** Alias word address of CLKEN bit */ #define CLKCTRL_OFFSET (SDIO_OFFSET + 0x04) #define CLKEN_BitNumber 0x08 #define CLKCTRL_CLKEN_BB (PERIPH_BB_BASE + (CLKCTRL_OFFSET * 32) + (CLKEN_BitNumber * 4)) -/* --- CMD Register ---*/ +/** --- CMD Register ---*/ -/* Alias word address of SDIOSC bit */ +/** Alias word address of SDIOSC bit */ #define CMD_OFFSET (SDIO_OFFSET + 0x0C) #define SDIOSC_BitNumber 0x0B #define CMD_SDIOSC_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSC_BitNumber * 4)) -/* Alias word address of CMDCPEN bit */ +/** Alias word address of CMDCPEN bit */ #define CMDCPEN_BitNumber 0x0C #define CMD_CMDCPEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (CMDCPEN_BitNumber * 4)) -/* Alias word address of INTEN bit */ +/** Alias word address of INTEN bit */ #define INTEN_BitNumber 0x0D #define CMD_INTEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (INTEN_BitNumber * 4)) -/* Alias word address of ATACMD bit */ +/** Alias word address of ATACMD bit */ #define ATACMD_BitNumber 0x0E #define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4)) -/* --- DCTRL Register ---*/ +/** --- DCTRL Register ---*/ -/* Alias word address of DMAEN bit */ +/** Alias word address of DMAEN bit */ #define DCTRL_OFFSET (SDIO_OFFSET + 0x2C) #define DMAEN_BitNumber 0x03 #define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4)) -/* Alias word address of RWSTR bit */ +/** Alias word address of RWSTR bit */ #define RWSTR_BitNumber 0x08 #define DCTRL_RWSTR_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTR_BitNumber * 4)) -/* Alias word address of RWSTOP bit */ +/** Alias word address of RWSTOP bit */ #define RWSTOP_BitNumber 0x09 #define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4)) -/* Alias word address of RDWAIT bit */ +/** Alias word address of RDWAIT bit */ #define RDWAIT_BitNumber 0x0A #define DCTRL_RDWAIT_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RDWAIT_BitNumber * 4)) -/* Alias word address of SDIOF bit */ +/** Alias word address of SDIOF bit */ #define SDIOF_BitNumber 0x0B #define DCTRL_SDIOF_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOF_BitNumber * 4)) @@ -318,10 +332,10 @@ typedef struct SDIO_CLOCK_EDGE_T clockEdge; SDIO_CLOCK_BYPASS_T clockBypass; SDIO_CLOCK_POWER_SAVE_T clockPowerSave; - SDIO_BUSWIDE_T busWide; + SDIO_BUS_WIDE_T busWide; SDIO_HARDWARE_FLOW_CONTROL_T hardwareFlowControl; uint8_t clockDiv; -}SDIO_Config_T; +} SDIO_Config_T; /** * @brief SDIO CMD Config structure definition @@ -333,7 +347,7 @@ typedef struct SDIO_RESPONSE_T response; SDIO_WAIT_T wait; SDIO_CPSM_T CPSM; -}SDIO_CMDConfig_T; +} SDIO_CmdConfig_T; /** * @brief SDIO Data Config structure definition @@ -346,7 +360,7 @@ typedef struct SDIO_TRANSFER_DIR_T transferDir; SDIO_TRANSFER_MODE_T transferMode; SDIO_DPSM_T DPSM; -}SDIO_DataConfig_T; +} SDIO_DataConfig_T; /**@} end of group SDIO_Structure*/ @@ -357,8 +371,8 @@ typedef struct /** SDIO reset and configuration */ void SDIO_Reset(void); -void SDIO_Config(SDIO_Config_T* sdioConfig); -void SDIO_ConfigStructInit(SDIO_Config_T* sdioConfig); +void SDIO_Config(SDIO_Config_T *sdioConfig); +void SDIO_ConfigStructInit(SDIO_Config_T *sdioConfig); void SDIO_EnableClock(void); void SDIO_DisableClock(void); void SDIO_ConfigPowerState(SDIO_POWER_STATE_T powerState); @@ -369,14 +383,14 @@ void SDIO_EnableDMA(void); void SDIO_DisableDMA(void); /** Command */ -void SDIO_TxCommand(SDIO_CMDConfig_T *cmdConfig); -void SDIO_TxCommandStructInit(SDIO_CMDConfig_T* cmdconfig); +void SDIO_TxCommand(SDIO_CmdConfig_T *cmdConfig); +void SDIO_TxCommandStructInit(SDIO_CmdConfig_T *cmdconfig); uint8_t SDIO_ReadCommandResponse(void); uint32_t SDIO_ReadResponse(SDIO_RES_T res); /** SDIO data configuration */ -void SDIO_ConfigData(SDIO_DataConfig_T* dataConfig); -void SDIO_ConfigDataStructInit(SDIO_DataConfig_T* dataConfig); +void SDIO_ConfigData(SDIO_DataConfig_T *dataConfig); +void SDIO_ConfigDataStructInit(SDIO_DataConfig_T *dataConfig); uint32_t SDIO_ReadDataCounter(void); void SDIO_WriteData(uint32_t data); uint32_t SDIO_ReadData(void); diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_spi.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_spi.h index 40e4afe7c0..2f2fbab65f 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_spi.h +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_spi.h @@ -3,21 +3,35 @@ * * @brief This file contains all the functions prototypes for the SPI firmware library * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ #ifndef __APM32F10X_SPI_H #define __APM32F10X_SPI_H -#include "apm32f10x.h" - #ifdef __cplusplus - extern "C" { +extern "C" { #endif +#include "apm32f10x.h" + /** @addtogroup Peripherals_Library Standard Peripheral Library @{ */ @@ -39,7 +53,7 @@ typedef enum SPI_DIRECTION_2LINES_RXONLY = 0x0400, SPI_DIRECTION_1LINE_RX = 0x8000, SPI_DIRECTION_1LINE_TX = 0xC000 -}SPI_DIRECTION_T; +} SPI_DIRECTION_T; /** * @brief SPI mode @@ -48,7 +62,7 @@ typedef enum { SPI_MODE_MASTER = 0x0104, SPI_MODE_SLAVE = 0x0000 -}SPI_MODE_T; +} SPI_MODE_T; /** * @brief SPI Data length @@ -57,7 +71,7 @@ typedef enum { SPI_DATA_LENGTH_16B = 0x0800, SPI_DATA_LENGTH_8B = 0x0000 -}SPI_DATA_LENGTH_T; +} SPI_DATA_LENGTH_T; /** * @brief SPI Clock Polarity @@ -66,7 +80,7 @@ typedef enum { SPI_CLKPOL_LOW = 0x0000, SPI_CLKPOL_HIGH = 0x0002 -}SPI_CLKPOL_T; +} SPI_CLKPOL_T; /** * @brief SPI Clock Phase @@ -75,7 +89,7 @@ typedef enum { SPI_CLKPHA_1EDGE = 0x0000, SPI_CLKPHA_2EDGE = 0x0001 -}SPI_CLKPHA_T; +} SPI_CLKPHA_T; /** * @brief SPI Slave Select management @@ -84,7 +98,7 @@ typedef enum { SPI_NSS_SOFT = 0x0200, SPI_NSS_HARD = 0x0000 -}SPI_NSS_T; +} SPI_NSS_T; /** * @brief SPI BaudRate Prescaler @@ -99,7 +113,7 @@ typedef enum SPI_BAUDRATE_DIV_64 = 0x0028, SPI_BAUDRATE_DIV_128 = 0x0030, SPI_BAUDRATE_DIV_256 = 0x0038, -}SPI_BAUDRATE_DIV_T; +} SPI_BAUDRATE_DIV_T; /** * @brief SPI MSB LSB transmission @@ -108,7 +122,7 @@ typedef enum { SPI_FIRSTBIT_MSB = 0x0000, SPI_FIRSTBIT_LSB = 0x0080 -}SPI_FIRSTBIT_T; +} SPI_FIRSTBIT_T; /** * @brief I2S Mode @@ -119,7 +133,7 @@ typedef enum I2S_MODE_SLAVE_RX = 0x0100, I2S_MODE_MASTER_TX = 0x0200, I2S_MODE_MASTER_RX = 0x0300 -}I2S_MODE_T; +} I2S_MODE_T; /** * @brief I2S Standard @@ -131,7 +145,7 @@ typedef enum I2S_STANDARD_LSB = 0x0020, I2S_STANDARD_PCMSHORT = 0x0030, I2S_STANDARD_PCMLONG = 0x00B0 -}I2S_STANDARD_T; +} I2S_STANDARD_T; /** * @brief I2S data length @@ -151,7 +165,7 @@ typedef enum { I2S_MCLK_OUTPUT_DISABLE = 0x0000, I2S_MCLK_OUTPUT_ENABLE = 0x0200, -}I2S_MCLK_OUTPUT_T; +} I2S_MCLK_OUTPUT_T; /** * @brief I2S Audio divider @@ -168,7 +182,7 @@ typedef enum I2S_AUDIO_DIV_11K = 11025, I2S_AUDIO_DIV_8K = 8000, I2S_AUDIO_DIV_DEFAULT = 2 -}I2S_AUDIO_DIV_T; +} I2S_AUDIO_DIV_T; /** * @brief I2S Clock Polarity @@ -177,7 +191,7 @@ typedef enum { I2S_CLKPOL_LOW = 0x0000, I2S_CLKPOL_HIGH = 0x0008 -}I2S_CLKPOL_T; +} I2S_CLKPOL_T; /** * @brief SPI Direction select @@ -186,7 +200,7 @@ typedef enum { SPI_DIRECTION_RX = 0xBFFF, SPI_DIRECTION_TX = 0x4000 -}SPI_DIRECTION_SELECT_T; +} SPI_DIRECTION_SELECT_T; /** * @brief SPI interrupts definition @@ -200,7 +214,7 @@ typedef enum SPI_INT_CRCE = 0x2010, SPI_INT_ME = 0x2020, I2S_INT_UDR = 0x2008 -}SPI_I2S_INT_T; +} SPI_I2S_INT_T; /** * @brief SPI flags definition @@ -215,7 +229,7 @@ typedef enum SPI_FLAG_ME = 0x0020, SPI_FLAG_OVR = 0x0040, SPI_FLAG_BSY = 0x0080 -}SPI_FLAG_T; +} SPI_FLAG_T; /** * @brief SPI I2S DMA requests @@ -224,7 +238,7 @@ typedef enum { SPI_I2S_DMA_REQ_TX = 0x0002, SPI_I2S_DMA_REQ_RX = 0x0001 -}SPI_I2S_DMA_REQ_T; +} SPI_I2S_DMA_REQ_T; /**@} end of group SPI_Enumerations*/ @@ -247,7 +261,7 @@ typedef struct SPI_DIRECTION_T direction; SPI_BAUDRATE_DIV_T baudrateDiv; uint16_t crcPolynomial; -}SPI_Config_T; +} SPI_Config_T; /** * @brief I2S Config structure definition @@ -260,7 +274,7 @@ typedef struct I2S_MCLK_OUTPUT_T MCLKOutput; I2S_AUDIO_DIV_T audioDiv; I2S_CLKPOL_T polarity; -}I2S_Config_T; +} I2S_Config_T; /**@} end of group SPI_Structure*/ @@ -269,44 +283,44 @@ typedef struct */ /** Reset and Configuration */ -void SPI_I2S_Reset(SPI_T* spi); -void SPI_Config(SPI_T* spi, SPI_Config_T* spiConfig); -void I2S_Config(SPI_T* spi, I2S_Config_T* i2sConfig); -void SPI_ConfigStructInit(SPI_Config_T* spiConfig); -void I2S_ConfigStructInit(I2S_Config_T* i2sConfig); -void SPI_Enable(SPI_T* spi); -void SPI_Disable(SPI_T* spi); -void I2S_Enable(SPI_T* spi); -void I2S_Disable(SPI_T* spi); +void SPI_I2S_Reset(SPI_T *spi); +void SPI_Config(SPI_T *spi, SPI_Config_T *spiConfig); +void I2S_Config(SPI_T *spi, I2S_Config_T *i2sConfig); +void SPI_ConfigStructInit(SPI_Config_T *spiConfig); +void I2S_ConfigStructInit(I2S_Config_T *i2sConfig); +void SPI_Enable(SPI_T *spi); +void SPI_Disable(SPI_T *spi); +void I2S_Enable(SPI_T *spi); +void I2S_Disable(SPI_T *spi); -void SPI_I2S_TxData(SPI_T* spi, uint16_t data); -uint16_t SPI_I2S_RxData(SPI_T* spi); -void SPI_SetSoftwareNSS(SPI_T* spi); -void SPI_ResetSoftwareNSS(SPI_T* spi); -void SPI_EnableSSOutput(SPI_T* spi); -void SPI_DisableSSOutput(SPI_T* spi); -void SPI_ConfigDataSize(SPI_T* spi, uint16_t dataSize); +void SPI_I2S_TxData(SPI_T *spi, uint16_t data); +uint16_t SPI_I2S_RxData(SPI_T *spi); +void SPI_SetSoftwareNSS(SPI_T *spi); +void SPI_ResetSoftwareNSS(SPI_T *spi); +void SPI_EnableSSOutput(SPI_T *spi); +void SPI_DisableSSOutput(SPI_T *spi); +void SPI_ConfigDataSize(SPI_T *spi, SPI_DATA_LENGTH_T length); /** DMA */ -void SPI_I2S_EnableDMA(SPI_T* spi, SPI_I2S_DMA_REQ_T dmaReq); -void SPI_I2S_DisableDMA(SPI_T* spi, SPI_I2S_DMA_REQ_T dmaReq); +void SPI_I2S_EnableDMA(SPI_T *spi, SPI_I2S_DMA_REQ_T dmaReq); +void SPI_I2S_DisableDMA(SPI_T *spi, SPI_I2S_DMA_REQ_T dmaReq); /** CRC */ -void SPI_TxCRC(SPI_T* spi); -void SPI_EnableCRC(SPI_T* spi); -void SPI_DisableCRC(SPI_T* spi); -uint16_t SPI_ReadTxCRC(SPI_T* spi); -uint16_t SPI_ReadRxCRC(SPI_T* spi); -uint16_t SPI_ReadCRCPolynomial(SPI_T* spi); -void SPI_ConfigBiDirectionalLine(SPI_T* spi, SPI_DIRECTION_SELECT_T direction); +void SPI_TxCRC(SPI_T *spi); +void SPI_EnableCRC(SPI_T *spi); +void SPI_DisableCRC(SPI_T *spi); +uint16_t SPI_ReadTxCRC(SPI_T *spi); +uint16_t SPI_ReadRxCRC(SPI_T *spi); +uint16_t SPI_ReadCRCPolynomial(SPI_T *spi); +void SPI_ConfigBiDirectionalLine(SPI_T *spi, SPI_DIRECTION_SELECT_T direction); /** Interrupts and flag */ -void SPI_I2S_EnableInterrupt(SPI_T* spi, SPI_I2S_INT_T interrupt); -void SPI_I2S_DisableInterrupt(SPI_T* spi, SPI_I2S_INT_T interrupt); -uint8_t SPI_I2S_ReadStatusFlag(SPI_T* spi, SPI_FLAG_T flag); -void SPI_I2S_ClearStatusFlag(SPI_T* spi, SPI_FLAG_T flag); -uint8_t SPI_I2S_ReadIntFlag(SPI_T* spi, SPI_I2S_INT_T flag); -void SPI_I2S_ClearIntFlag(SPI_T* spi, SPI_I2S_INT_T flag); +void SPI_I2S_EnableInterrupt(SPI_T *spi, SPI_I2S_INT_T interrupt); +void SPI_I2S_DisableInterrupt(SPI_T *spi, SPI_I2S_INT_T interrupt); +uint8_t SPI_I2S_ReadStatusFlag(SPI_T *spi, SPI_FLAG_T flag); +void SPI_I2S_ClearStatusFlag(SPI_T *spi, SPI_FLAG_T flag); +uint8_t SPI_I2S_ReadIntFlag(SPI_T *spi, SPI_I2S_INT_T flag); +void SPI_I2S_ClearIntFlag(SPI_T *spi, SPI_I2S_INT_T flag); /**@} end of group SPI_Fuctions*/ /**@} end of group SPI_Driver*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_tmr.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_tmr.h index 50313d7e08..292b9bc5ad 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_tmr.h +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_tmr.h @@ -1,22 +1,36 @@ /*! - * @file apm32f10x_tmr.h + * @file apm32f10x_tmr.h * - * @brief This file contains all the functions prototypes for the TMR firmware library. + * @brief This file contains all the functions prototypes for the TMR firmware library. * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ #ifndef __APM32F10X_TMR_H #define __APM32F10X_TMR_H -#include "apm32f10x.h" - #ifdef __cplusplus extern "C" { #endif +#include "apm32f10x.h" + /** @addtogroup Peripherals_Library Standard Peripheral Library @{ */ @@ -63,7 +77,7 @@ typedef enum TMR_OC_MODE_LOWLEVEL = 0x04, TMR_OC_MODE_HIGHLEVEL = 0x05, TMR_OC_MODE_PWM1 = 0x06, - TMR_OC_MODE_PWM2 = 0x07, + TMR_OC_MODE_PWM2 = 0x07 } TMR_OC_MODE_T; /** @@ -353,9 +367,9 @@ typedef enum */ typedef enum { - TMR_PRESCALER_RELOAD_UPDATA, - TMR_PRESCALER_RELOAD_IMMEDIATE -} TMR_PRESCALER_RELOAD_T; + TMR_PSC_RELOAD_UPDATE, + TMR_PSC_RELOAD_IMMEDIATE +} TMR_PSC_RELOAD_T; /** * @brief TMR Encoder Mode @@ -444,7 +458,7 @@ typedef enum TMR_SLAVE_MODE_RESET = 0x04, TMR_SLAVE_MODE_GATED = 0x05, TMR_SLAVE_MODE_TRIGGER = 0x06, - TMR_SLAVE_MODE_EXTERNALL = 0x07 + TMR_SLAVE_MODE_EXTERNAL1 = 0x07 } TMR_SLAVE_MODE_T; /** @@ -532,124 +546,124 @@ typedef struct */ /** Reset and Configuration */ -void TMR_Reset(TMR_T* tmr); -void TMR_ConfigTimeBase(TMR_T* tmr, TMR_BaseConfig_T *baseConfig); -void TMR_ConfigOC1(TMR_T* tmr, TMR_OCConfig_T *OC1Config); -void TMR_ConfigOC2(TMR_T* tmr, TMR_OCConfig_T *OC2Config); -void TMR_ConfigOC3(TMR_T* tmr, TMR_OCConfig_T *OC3Config); -void TMR_ConfigOC4(TMR_T* tmr, TMR_OCConfig_T *OC4Config); -void TMR_ConfigIC(TMR_T* tmr, TMR_ICConfig_T *ICConfig); -void TMR_ConfigBDT(TMR_T* tmr, TMR_BDTConfig_T *BDTConfig); +void TMR_Reset(TMR_T *tmr); +void TMR_ConfigTimeBase(TMR_T *tmr, TMR_BaseConfig_T *baseConfig); +void TMR_ConfigOC1(TMR_T *tmr, TMR_OCConfig_T *OCConfig); +void TMR_ConfigOC2(TMR_T *tmr, TMR_OCConfig_T *OCConfig); +void TMR_ConfigOC3(TMR_T *tmr, TMR_OCConfig_T *OCConfig); +void TMR_ConfigOC4(TMR_T *tmr, TMR_OCConfig_T *OCConfig); +void TMR_ConfigIC(TMR_T *tmr, TMR_ICConfig_T *ICConfig); +void TMR_ConfigBDT(TMR_T *tmr, TMR_BDTConfig_T *BDTConfig); void TMR_ConfigTimeBaseStructInit(TMR_BaseConfig_T *baseConfig); void TMR_ConfigOCStructInit(TMR_OCConfig_T *OCConfig); void TMR_ConfigICStructInit(TMR_ICConfig_T *ICConfig); -void TMR_ConfigBDTStructInit( TMR_BDTConfig_T *BDTConfig); -void TMR_Enable(TMR_T* tmr); -void TMR_Disable(TMR_T* tmr); +void TMR_ConfigBDTStructInit(TMR_BDTConfig_T *BDTConfig); +void TMR_ConfigSinglePulseMode(TMR_T *tmr, TMR_SPM_T singlePulseMode); +void TMR_ConfigClockDivision(TMR_T *tmr, TMR_CLOCK_DIV_T clockDivision); +void TMR_Enable(TMR_T *tmr); +void TMR_Disable(TMR_T *tmr); -/* PWM Configuration */ -void TMR_ConfigPWM(TMR_T* tmr, TMR_ICConfig_T *PWMConfig); -void TMR_EnablePWMOutputs(TMR_T* tmr); -void TMR_DisablePWMOutputs(TMR_T* tmr); +/** PWM Configuration */ +void TMR_ConfigPWM(TMR_T *tmr, TMR_ICConfig_T *PWMConfig); +void TMR_EnablePWMOutputs(TMR_T *tmr); +void TMR_DisablePWMOutputs(TMR_T *tmr); /** DMA */ -void TMR_ConfigDMA(TMR_T* tmr, TMR_DMA_BASE_T baseAddress, TMR_DMA_BURSTLENGTH_T burstLength); -void TMR_EnableDMASoure(TMR_T* tmr, uint16_t dmaSource); -void TMR_DisableDMASoure(TMR_T* tmr, uint16_t dmaSource); +void TMR_ConfigDMA(TMR_T *tmr, TMR_DMA_BASE_T baseAddress, TMR_DMA_BURSTLENGTH_T burstLength); +void TMR_EnableDMASoure(TMR_T *tmr, uint16_t dmaSource); +void TMR_DisableDMASoure(TMR_T *tmr, uint16_t dmaSource); /** Configuration */ -void TMR_ConfigInternalClock(TMR_T* tmr); -void TMR_ConfigIntTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource); -void TMR_ConfigTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource, - TMR_IC_POLARITY_T ICpolarity, uint16_t ICfilter); -void TMR_ConfigETRClockMode1(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler, +void TMR_ConfigInternalClock(TMR_T *tmr); +void TMR_ConfigIntTrigExternalClock(TMR_T *tmr, TMR_TRIGGER_SOURCE_T triggerSource); +void TMR_ConfigTrigExternalClock(TMR_T *tmr, TMR_TRIGGER_SOURCE_T triggerSource, + TMR_IC_POLARITY_T ICpolarity, uint16_t ICfilter); +void TMR_ConfigETRClockMode1(TMR_T *tmr, TMR_EXTTRG_PSC_T prescaler, TMR_EXTTRG_POL_T polarity, uint16_t filter); -void TMR_ConfigETRClockMode2(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler, +void TMR_ConfigETRClockMode2(TMR_T *tmr, TMR_EXTTRG_PSC_T prescaler, TMR_EXTTRG_POL_T polarity, uint16_t filter); -void TMR_ConfigETR(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler, +void TMR_ConfigETR(TMR_T *tmr, TMR_EXTTRG_PSC_T prescaler, TMR_EXTTRG_POL_T polarity, uint16_t filter); -void TMR_ConfigPrescaler(TMR_T* tmr, uint16_t prescaler, TMR_PRESCALER_RELOAD_T pscReloadMode); -void TMR_ConfigCounterMode(TMR_T* tmr, TMR_COUNTER_MODE_T countMode); -void TMR_SelectInputTrigger(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSouce); -void TMR_ConfigEncodeInterface(TMR_T* tmr, TMR_ENCODER_MODE_T encodeMode, TMR_IC_POLARITY_T IC1Polarity, +void TMR_ConfigPrescaler(TMR_T *tmr, uint16_t prescaler, TMR_PSC_RELOAD_T pscReloadMode); +void TMR_ConfigCounterMode(TMR_T *tmr, TMR_COUNTER_MODE_T countMode); +void TMR_SelectInputTrigger(TMR_T *tmr, TMR_TRIGGER_SOURCE_T triggerSouce); +void TMR_ConfigEncodeInterface(TMR_T *tmr, TMR_ENCODER_MODE_T encodeMode, TMR_IC_POLARITY_T IC1Polarity, TMR_IC_POLARITY_T IC2Polarity); -void TMR_ConfigForcedOC1(TMR_T* tmr,TMR_FORCED_ACTION_T forcesAction); -void TMR_ConfigForcedOC2(TMR_T* tmr,TMR_FORCED_ACTION_T forcesAction); -void TMR_ConfigForcedOC3(TMR_T* tmr,TMR_FORCED_ACTION_T forcesAction); -void TMR_ConfigForcedOC4(TMR_T* tmr,TMR_FORCED_ACTION_T forcesAction); -void TMR_EnableAUTOReload(TMR_T* tmr); -void TMR_DisableAUTOReload(TMR_T* tmr); -void TMR_EnableSelectCOM(TMR_T* tmr); -void TMR_DisableSelectCOM(TMR_T* tmr); -void TMR_EnableCCDMA(TMR_T* tmr); -void TMR_DisableCCDMA(TMR_T* tmr); -void TMR_EnableCCPreload(TMR_T* tmr); -void TMR_DisableCCPreload(TMR_T* tmr); -void TMR_ConfigOC1Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload); -void TMR_ConfigOC2Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload); -void TMR_ConfigOC3Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload); -void TMR_ConfigOC4Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload); -void TMR_ConfigOC1Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast); -void TMR_ConfigOC2Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast); -void TMR_ConfigOC3Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast); -void TMR_ConfigOC4Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast); -void TMR_ClearOC1Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear); -void TMR_ClearOC2Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear); -void TMR_ClearOC3Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear); -void TMR_ClearOC4Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear); -void TMR_ConfigOC1Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity); -void TMR_ConfigOC1NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T OCNPolarity); -void TMR_ConfigOC2Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity); -void TMR_ConfigOC2NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T OCNPolarity); -void TMR_ConfigOC3Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity); -void TMR_ConfigOC3NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T OCNPolarity); -void TMR_ConfigOC4Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity); -void TMR_EnableCCxChannel(TMR_T* tmr,TMR_CHANNEL_T channel); -void TMR_DisableCCxChannel(TMR_T* tmr,TMR_CHANNEL_T channel); -void TMR_EnableCCxNChannel(TMR_T* tmr,TMR_CHANNEL_T channel); -void TMR_DisableCCxNChannel(TMR_T* tmr,TMR_CHANNEL_T channel); -void TMR_SelectOCxMode(TMR_T* tmr, TMR_CHANNEL_T channel, TMR_OC_MODE_T OCMode); -void TMR_EnableNoUpdate(TMR_T* tmr); -void TMR_DisableNoUpdate(TMR_T* tmr); -void TMR_ConfigUPdateRequest(TMR_T* tmr, TMR_UPDATE_SOURCE_T updateSource); -void TMR_EnableHallSensor(TMR_T* tmr); -void TMR_DisableHallSensor(TMR_T* tmr); -void TMR_SelectSinglePulseMode(TMR_T* tmr, TMR_SPM_T singlePulseMode); -void TMR_SelectOutputTrigger(TMR_T* tmr, TMR_TRGO_SOURCE_T TRGOSource); -void TMR_SelectSlaveMode(TMR_T* tmr, TMR_SLAVE_MODE_T slaveMode); -void TMR_EnableMasterSlaveMode(TMR_T* tmr); -void TMR_DisableMasterSlaveMode(TMR_T* tmr); -void TMR_ConfigCounter(TMR_T* tmr, uint16_t counter); -void TMR_ConfigAutoreload(TMR_T* tmr, uint16_t autoReload); -void TMR_ConfigCompare1(TMR_T* tmr, uint16_t compare1); -void TMR_ConfigCompare2(TMR_T* tmr, uint16_t compare2); -void TMR_ConfigCompare3(TMR_T* tmr, uint16_t compare3); -void TMR_ConfigCompare4(TMR_T* tmr, uint16_t compare4); -void TMR_ConfigIC1Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler); -void TMR_ConfigIC2Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler); -void TMR_ConfigIC3Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler); -void TMR_ConfigIC4Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler); -void TMR_ConfigClockDivision(TMR_T* tmr, TMR_CLOCK_DIV_T clockDivision); -uint16_t TMR_ReadCaputer1(TMR_T* tmr); -uint16_t TMR_ReadCaputer2(TMR_T* tmr); -uint16_t TMR_ReadCaputer3(TMR_T* tmr); -uint16_t TMR_ReadCaputer4(TMR_T* tmr); -uint16_t TMR_ReadCounter(TMR_T* tmr); -uint16_t TMR_ReadPrescaler(TMR_T* tmr); +void TMR_ConfigForcedOC1(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction); +void TMR_ConfigForcedOC2(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction); +void TMR_ConfigForcedOC3(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction); +void TMR_ConfigForcedOC4(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction); +void TMR_EnableAutoReload(TMR_T *tmr); +void TMR_DisableAutoReload(TMR_T *tmr); +void TMR_EnableSelectCOM(TMR_T *tmr); +void TMR_DisableSelectCOM(TMR_T *tmr); +void TMR_EnableCCDMA(TMR_T *tmr); +void TMR_DisableCCDMA(TMR_T *tmr); +void TMR_EnableCCPreload(TMR_T *tmr); +void TMR_DisableCCPreload(TMR_T *tmr); +void TMR_ConfigOC1Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload); +void TMR_ConfigOC2Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload); +void TMR_ConfigOC3Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload); +void TMR_ConfigOC4Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload); +void TMR_ConfigOC1Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast); +void TMR_ConfigOC2Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast); +void TMR_ConfigOC3Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast); +void TMR_ConfigOC4Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast); +void TMR_ClearOC1Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear); +void TMR_ClearOC2Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear); +void TMR_ClearOC3Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear); +void TMR_ClearOC4Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear); +void TMR_ConfigOC1Polarity(TMR_T *tmr, TMR_OC_POLARITY_T OCPolarity); +void TMR_ConfigOC1NPolarity(TMR_T *tmr, TMR_OC_NPOLARITY_T OCNPolarity); +void TMR_ConfigOC2Polarity(TMR_T *tmr, TMR_OC_POLARITY_T OCPolarity); +void TMR_ConfigOC2NPolarity(TMR_T *tmr, TMR_OC_NPOLARITY_T OCNPolarity); +void TMR_ConfigOC3Polarity(TMR_T *tmr, TMR_OC_POLARITY_T OCPolarity); +void TMR_ConfigOC3NPolarity(TMR_T *tmr, TMR_OC_NPOLARITY_T OCNPolarity); +void TMR_ConfigOC4Polarity(TMR_T *tmr, TMR_OC_POLARITY_T OCPolarity); +void TMR_EnableCCxChannel(TMR_T *tmr, TMR_CHANNEL_T channel); +void TMR_DisableCCxChannel(TMR_T *tmr, TMR_CHANNEL_T channel); +void TMR_EnableCCxNChannel(TMR_T *tmr, TMR_CHANNEL_T channel); +void TMR_DisableCCxNChannel(TMR_T *tmr, TMR_CHANNEL_T channel); +void TMR_SelectOCxMode(TMR_T *tmr, TMR_CHANNEL_T channel, TMR_OC_MODE_T OCMode); +void TMR_EnableUpdate(TMR_T *tmr); +void TMR_DisableUpdate(TMR_T *tmr); +void TMR_ConfigUpdateRequest(TMR_T *tmr, TMR_UPDATE_SOURCE_T updateSource); +void TMR_EnableHallSensor(TMR_T *tmr); +void TMR_DisableHallSensor(TMR_T *tmr); +void TMR_SelectOutputTrigger(TMR_T *tmr, TMR_TRGO_SOURCE_T TRGOSource); +void TMR_SelectSlaveMode(TMR_T *tmr, TMR_SLAVE_MODE_T slaveMode); +void TMR_EnableMasterSlaveMode(TMR_T *tmr); +void TMR_DisableMasterSlaveMode(TMR_T *tmr); +void TMR_ConfigCounter(TMR_T *tmr, uint16_t counter); +void TMR_ConfigAutoreload(TMR_T *tmr, uint16_t autoReload); +void TMR_ConfigCompare1(TMR_T *tmr, uint16_t compare1); +void TMR_ConfigCompare2(TMR_T *tmr, uint16_t compare2); +void TMR_ConfigCompare3(TMR_T *tmr, uint16_t compare3); +void TMR_ConfigCompare4(TMR_T *tmr, uint16_t compare4); +void TMR_ConfigIC1Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler); +void TMR_ConfigIC2Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler); +void TMR_ConfigIC3Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler); +void TMR_ConfigIC4Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler); +uint16_t TMR_ReadCaputer1(TMR_T *tmr); +uint16_t TMR_ReadCaputer2(TMR_T *tmr); +uint16_t TMR_ReadCaputer3(TMR_T *tmr); +uint16_t TMR_ReadCaputer4(TMR_T *tmr); +uint16_t TMR_ReadCounter(TMR_T *tmr); +uint16_t TMR_ReadPrescaler(TMR_T *tmr); /** Interrupts and Event */ -void TMR_EnableInterrupt(TMR_T* tmr, uint16_t interrupt); -void TMR_DisableInterrupt(TMR_T* tmr, uint16_t interrupt); -void TMR_GenerateEvent(TMR_T* tmr,uint16_t eventSources); +void TMR_EnableInterrupt(TMR_T *tmr, uint16_t interrupt); +void TMR_DisableInterrupt(TMR_T *tmr, uint16_t interrupt); +void TMR_GenerateEvent(TMR_T *tmr, uint16_t eventSources); /** flags */ -uint16_t TMR_ReadStatusFlag(TMR_T* tmr, TMR_FLAG_T flag); -void TMR_ClearStatusFlag(TMR_T* tmr, uint16_t flag); -uint16_t TMR_ReadIntFlag(TMR_T* tmr, TMR_INT_T flag); -void TMR_ClearIntFlag(TMR_T* tmr, uint16_t flag); +uint16_t TMR_ReadStatusFlag(TMR_T *tmr, TMR_FLAG_T flag); +void TMR_ClearStatusFlag(TMR_T *tmr, uint16_t flag); +uint16_t TMR_ReadIntFlag(TMR_T *tmr, TMR_INT_T flag); +void TMR_ClearIntFlag(TMR_T *tmr, uint16_t flag); /**@} end of group TMR_Fuctions*/ -/**@} end of group TMR_Driver */ +/**@} end of group TMR_Driver*/ /**@} end of group Peripherals_Library*/ #ifdef __cplusplus diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_usart.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_usart.h index fb7880c1ee..1a4e6f8eed 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_usart.h +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_usart.h @@ -1,23 +1,37 @@ /*! - * @file apm32f10x_usart.h + * @file apm32f10x_usart.h * - * @brief This file contains all the functions prototypes for the USART firmware library + * @brief This file contains all the functions prototypes for the USART firmware library * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ #ifndef __APM32F10X_USART_H #define __APM32F10X_USART_H -#include "apm32f10x.h" - #ifdef __cplusplus extern "C" { #endif +#include "apm32f10x.h" + /** @addtogroup Peripherals_Library Standard Peripheral Library @{ */ @@ -226,64 +240,64 @@ typedef struct */ /** USART Reset and Configuration */ -void USART_Reset(USART_T* usart); -void USART_Config(USART_T* uart, USART_Config_T* usartConfig); -void USART_ConfigStructInit(USART_Config_T* usartConfig); -void USART_Address(USART_T* usart, uint8_t address); -void USART_Enable(USART_T* usart); -void USART_Disable(USART_T* usart); +void USART_Reset(USART_T *usart); +void USART_Config(USART_T *uart, USART_Config_T *usartConfig); +void USART_ConfigStructInit(USART_Config_T *usartConfig); +void USART_Address(USART_T *usart, uint8_t address); +void USART_Enable(USART_T *usart); +void USART_Disable(USART_T *usart); /** Clock communication */ -void USART_ConfigClock(USART_T* usart, USART_ClockConfig_T* clockConfig); -void USART_ConfigClockStructInit(USART_ClockConfig_T* clockConfig); +void USART_ConfigClock(USART_T *usart, USART_ClockConfig_T *clockConfig); +void USART_ConfigClockStructInit(USART_ClockConfig_T *clockConfig); /** DMA mode */ -void USART_EnableDMA(USART_T* usart, USART_DMA_T dmaReq); -void USART_DisableDMA(USART_T* usart, USART_DMA_T dmaReq); +void USART_EnableDMA(USART_T *usart, USART_DMA_T dmaReq); +void USART_DisableDMA(USART_T *usart, USART_DMA_T dmaReq); /** Mute mode */ -void USART_ConfigWakeUp(USART_T* usart, USART_WAKEUP_T wakeup); -void USART_EnableMuteMode(USART_T* usart); -void USART_DisableMuteMode(USART_T* usart); +void USART_ConfigWakeUp(USART_T *usart, USART_WAKEUP_T wakeup); +void USART_EnableMuteMode(USART_T *usart); +void USART_DisableMuteMode(USART_T *usart); /** LIN mode */ -void USART_ConfigLINBreakDetectLength(USART_T* usart, USART_LBDL_T length); -void USART_EnableLIN(USART_T* usart); -void USART_DisableLIN(USART_T* usart); +void USART_ConfigLINBreakDetectLength(USART_T *usart, USART_LBDL_T length); +void USART_EnableLIN(USART_T *usart); +void USART_DisableLIN(USART_T *usart); /** Transmit and receive */ -void USART_EnableTx(USART_T* usart); -void USART_DisableTx(USART_T* usart); -void USART_EnableRx(USART_T* usart); -void USART_DisableRx(USART_T* usart); -void USART_TxData(USART_T* usart, uint16_t data); -uint16_t USART_RxData(USART_T* usart); -void USART_TxBreak(USART_T* usart); +void USART_EnableTx(USART_T *usart); +void USART_DisableTx(USART_T *usart); +void USART_EnableRx(USART_T *usart); +void USART_DisableRx(USART_T *usart); +void USART_TxData(USART_T *usart, uint16_t data); +uint16_t USART_RxData(USART_T *usart); +void USART_TxBreak(USART_T *usart); /** Smartcard mode */ -void USART_ConfigGuardTime(USART_T* usart, uint8_t guardTime); -void USART_ConfigPrescaler(USART_T* usart, uint8_t div); -void USART_EnableSmartCard(USART_T* usart); -void USART_DisableSmartCard(USART_T* usart); -void USART_EnableSmartCardNACK(USART_T* usart); -void USART_DisableSmartCardNACK(USART_T* usart); +void USART_ConfigGuardTime(USART_T *usart, uint8_t guardTime); +void USART_ConfigPrescaler(USART_T *usart, uint8_t div); +void USART_EnableSmartCard(USART_T *usart); +void USART_DisableSmartCard(USART_T *usart); +void USART_EnableSmartCardNACK(USART_T *usart); +void USART_DisableSmartCardNACK(USART_T *usart); /** Half-duplex mode */ -void USART_EnableHalfDuplex(USART_T* usart); -void USART_DisableHalfDuplex(USART_T* usart); +void USART_EnableHalfDuplex(USART_T *usart); +void USART_DisableHalfDuplex(USART_T *usart); /** IrDA mode */ -void USART_ConfigIrDA(USART_T* usart, USART_IRDALP_T IrDAMode); -void USART_EnableIrDA(USART_T* usart); -void USART_DisableIrDA(USART_T* usart); +void USART_ConfigIrDA(USART_T *usart, USART_IRDALP_T IrDAMode); +void USART_EnableIrDA(USART_T *usart); +void USART_DisableIrDA(USART_T *usart); /** Interrupt and flag */ -void USART_EnableInterrupt(USART_T* usart, USART_INT_T interrupt); -void USART_DisableInterrupt(USART_T* usart, USART_INT_T interrupt); -uint8_t USART_ReadStatusFlag(USART_T* usart, USART_FLAG_T flag); -void USART_ClearStatusFlag(USART_T* usart, USART_FLAG_T flag); -uint8_t USART_ReadIntFlag(USART_T* usart, USART_INT_T flag); -void USART_ClearIntFlag(USART_T* usart, USART_INT_T flag); +void USART_EnableInterrupt(USART_T *usart, USART_INT_T interrupt); +void USART_DisableInterrupt(USART_T *usart, USART_INT_T interrupt); +uint8_t USART_ReadStatusFlag(USART_T *usart, USART_FLAG_T flag); +void USART_ClearStatusFlag(USART_T *usart, USART_FLAG_T flag); +uint8_t USART_ReadIntFlag(USART_T *usart, USART_INT_T flag); +void USART_ClearIntFlag(USART_T *usart, USART_INT_T flag); /**@} end of group USART_Fuctions*/ /**@} end of group USART_Driver*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_wwdt.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_wwdt.h index cb958d3dcb..842edc6007 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_wwdt.h +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_wwdt.h @@ -3,21 +3,35 @@ * * @brief This file contains all the functions prototypes for the WWDT firmware library * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ #ifndef __APM32F10X_WWDT_H #define __APM32F10X_WWDT_H -#include "apm32f10x.h" - #ifdef __cplusplus - extern "C" { +extern "C" { #endif +#include "apm32f10x.h" + /** @addtogroup Peripherals_Library Standard Peripheral Library @{ */ @@ -39,7 +53,7 @@ typedef enum WWDT_TIME_BASE_2 = 0x00000080, WWDT_TIME_BASE_4 = 0x00000100, WWDT_TIME_BASE_8 = 0x00000180 -}WWDT_TIME_BASE_T; +} WWDT_TIME_BASE_T; /**@} end of group WWDT_Enumerations*/ @@ -68,7 +82,7 @@ uint8_t WWDT_ReadFlag(void); void WWDT_ClearFlag(void); /**@} end of group WWDT_Fuctions*/ -/**@} end of group WWDT_Driver */ +/**@} end of group WWDT_Driver*/ /**@} end of group Peripherals_Library*/ #ifdef __cplusplus diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_adc.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_adc.c index c061ca94d4..0f7ef97b8b 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_adc.c +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_adc.c @@ -3,10 +3,24 @@ * * @brief This file provides all the ADC firmware functions * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ #include "apm32f10x_adc.h" @@ -25,22 +39,22 @@ */ /*! - * @brief Reset ADC peripheral registers to their default reset values. + * @brief Reset ADC peripheral registers to their default reset values. * - * @param adc: Select ADC peripheral. + * @param adc: Select ADC peripheral. * - * @retval None + * @retval None * - * @note adc can be ADC1, ADC2 or ADC3. + * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_Reset(ADC_T* adc) +void ADC_Reset(ADC_T *adc) { - if(adc == ADC1) + if (adc == ADC1) { RCM_EnableAPB2PeriphReset(RCM_APB2_PERIPH_ADC1); RCM_DisableAPB2PeriphReset(RCM_APB2_PERIPH_ADC1); } - else if(adc == ADC2) + else if (adc == ADC2) { RCM_EnableAPB2PeriphReset(RCM_APB2_PERIPH_ADC2); RCM_DisableAPB2PeriphReset(RCM_APB2_PERIPH_ADC2); @@ -63,7 +77,7 @@ void ADC_Reset(ADC_T* adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_Config(ADC_T* adc, ADC_Config_T* adcConfig) +void ADC_Config(ADC_T *adc, ADC_Config_T *adcConfig) { uint32_t reg; @@ -74,8 +88,10 @@ void ADC_Config(ADC_T* adc, ADC_Config_T* adcConfig) reg = adc->CTRL2; reg &= 0xFFF1F7FD; - reg |= (uint32_t)(adcConfig->dataAlign | adcConfig->externalTrigConv | - ((uint32_t)adcConfig->continuosConvMode << 1)); + reg |= (uint32_t)adcConfig->dataAlign | \ + (uint32_t)adcConfig->externalTrigConv | \ + ((uint32_t)adcConfig->continuosConvMode << 1); + adc->CTRL2 = reg; reg = adc->REGSEQ1; @@ -91,7 +107,7 @@ void ADC_Config(ADC_T* adc, ADC_Config_T* adcConfig) * * @retval None */ -void ADC_ConfigStructInit(ADC_Config_T* adcConfig) +void ADC_ConfigStructInit(ADC_Config_T *adcConfig) { adcConfig->mode = ADC_MODE_INDEPENDENT; adcConfig->scanConvMode = DISABLE; @@ -110,7 +126,7 @@ void ADC_ConfigStructInit(ADC_Config_T* adcConfig) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_Enable(ADC_T* adc) +void ADC_Enable(ADC_T *adc) { adc->CTRL2_B.ADCEN = BIT_SET; } @@ -124,7 +140,7 @@ void ADC_Enable(ADC_T* adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_Disable(ADC_T* adc) +void ADC_Disable(ADC_T *adc) { adc->CTRL2_B.ADCEN = BIT_RESET; } @@ -138,7 +154,7 @@ void ADC_Disable(ADC_T* adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_EnableDMA(ADC_T* adc) +void ADC_EnableDMA(ADC_T *adc) { adc->CTRL2_B.DMAEN = BIT_SET; } @@ -152,7 +168,7 @@ void ADC_EnableDMA(ADC_T* adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_DisableDMA(ADC_T* adc) +void ADC_DisableDMA(ADC_T *adc) { adc->CTRL2_B.DMAEN = BIT_RESET; } @@ -166,7 +182,7 @@ void ADC_DisableDMA(ADC_T* adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_ResetCalibration(ADC_T* adc) +void ADC_ResetCalibration(ADC_T *adc) { adc->CTRL2_B.CALRST = BIT_SET; } @@ -180,7 +196,7 @@ void ADC_ResetCalibration(ADC_T* adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -uint8_t ADC_ReadResetCalibrationStatus(ADC_T* adc) +uint8_t ADC_ReadResetCalibrationStatus(ADC_T *adc) { uint8_t ret; ret = (adc->CTRL2_B.CALRST) ? BIT_SET : BIT_RESET; @@ -196,7 +212,7 @@ uint8_t ADC_ReadResetCalibrationStatus(ADC_T* adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_StartCalibration(ADC_T* adc) +void ADC_StartCalibration(ADC_T *adc) { adc->CTRL2_B.CAL = BIT_SET; } @@ -210,7 +226,7 @@ void ADC_StartCalibration(ADC_T* adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -uint8_t ADC_ReadCalibrationStartFlag(ADC_T* adc) +uint8_t ADC_ReadCalibrationStartFlag(ADC_T *adc) { uint8_t ret; ret = (adc->CTRL2_B.CAL) ? BIT_SET : BIT_RESET; @@ -226,7 +242,7 @@ uint8_t ADC_ReadCalibrationStartFlag(ADC_T* adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_EnableSoftwareStartConv(ADC_T* adc) +void ADC_EnableSoftwareStartConv(ADC_T *adc) { adc->CTRL2 |= 0x00500000; } @@ -240,7 +256,7 @@ void ADC_EnableSoftwareStartConv(ADC_T* adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_DisableSoftwareStartConv(ADC_T* adc) +void ADC_DisableSoftwareStartConv(ADC_T *adc) { adc->CTRL2 &= 0xFFAFFFFF; } @@ -254,7 +270,7 @@ void ADC_DisableSoftwareStartConv(ADC_T* adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -uint8_t ADC_ReadSoftwareStartConvStatus(ADC_T* adc) +uint8_t ADC_ReadSoftwareStartConvStatus(ADC_T *adc) { uint8_t ret; ret = (adc->CTRL2_B.REGSWSC) ? BIT_SET : BIT_RESET; @@ -273,7 +289,7 @@ uint8_t ADC_ReadSoftwareStartConvStatus(ADC_T* adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_ConfigDiscModeChannel(ADC_T* adc, uint8_t number) +void ADC_ConfigDiscMode(ADC_T *adc, uint8_t number) { adc->CTRL1_B.DISCNUMCFG |= number - 1; } @@ -287,7 +303,7 @@ void ADC_ConfigDiscModeChannel(ADC_T* adc, uint8_t number) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_EnableDiscMode(ADC_T* adc) +void ADC_EnableDiscMode(ADC_T *adc) { adc->CTRL1_B.REGDISCEN = BIT_SET; } @@ -301,7 +317,7 @@ void ADC_EnableDiscMode(ADC_T* adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_DisableDiscMode(ADC_T* adc) +void ADC_DisableDiscMode(ADC_T *adc) { adc->CTRL1_B.REGDISCEN = BIT_RESET; } @@ -337,24 +353,24 @@ void ADC_DisableDiscMode(ADC_T* adc) * * @param sampleTime: the specified ADC channel SampleTime * The parameter can be one of following values: - * @arg ADC_SAMPLE_TIME_1_5: ADC 1.5 clock cycles - * @arg ADC_SAMPLE_TIME_7_5: ADC 7.5 clock cycles - * @arg ADC_SAMPLE_TIME_13_5: ADC 13.5 clock cycles - * @arg ADC_SAMPLE_TIME_28_5: ADC 28.5 clock cycles - * @arg ADC_SAMPLE_TIME_41_5: ADC 41.5 clock cycles - * @arg ADC_SAMPLE_TIME_55_5: ADC 55.5 clock cycles - * @arg ADC_SAMPLE_TIME_71_5: ADC 71.5 clock cycles - * @arg ADC_SAMPLE_TIME_239_5: ADC 239.5 clock cycles + * @arg ADC_SAMPLETIME_1CYCLES5: ADC 1.5 clock cycles + * @arg ADC_SAMPLETIME_7CYCLES5: ADC 7.5 clock cycles + * @arg ADC_SAMPLETIME_13CYCLES5: ADC 13.5 clock cycles + * @arg ADC_SAMPLETIME_28CYCLES5: ADC 28.5 clock cycles + * @arg ADC_SAMPLETIME_41CYCLES5: ADC 41.5 clock cycles + * @arg ADC_SAMPLETIME_55CYCLES5: ADC 55.5 clock cycles + * @arg ADC_SAMPLETIME_71CYCLES5: ADC 71.5 clock cycles + * @arg ADC_SAMPLETIME_239CYCLES5: ADC 239.5 clock cycles * * @retval None * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_ConfigRegularChannel(ADC_T* adc, uint8_t channel,uint8_t rank, uint8_t sampleTime) +void ADC_ConfigRegularChannel(ADC_T *adc, uint8_t channel, uint8_t rank, uint8_t sampleTime) { uint32_t temp1 = 0; uint32_t temp2 = 0; - if(channel > ADC_CHANNEL_9) + if (channel > ADC_CHANNEL_9) { temp1 = adc->SMPTIM1; temp2 = SMPCYCCFG_SET_SMPTIM1 << (3 * (channel - 10)); @@ -373,7 +389,7 @@ void ADC_ConfigRegularChannel(ADC_T* adc, uint8_t channel,uint8_t rank, uint8_t adc->SMPTIM2 = temp1; } - if(rank < 7) + if (rank < 7) { temp1 = adc->REGSEQ3; temp2 = REGSEQC_SET_REGSEQ3 << (5 * (rank - 1)); @@ -382,7 +398,7 @@ void ADC_ConfigRegularChannel(ADC_T* adc, uint8_t channel,uint8_t rank, uint8_t temp1 |= temp2; adc->REGSEQ3 = temp1; } - else if(rank < 13) + else if (rank < 13) { temp1 = adc->REGSEQ2; temp2 = REGSEQC_SET_REGSEQ2 << (5 * (rank - 7)); @@ -411,7 +427,7 @@ void ADC_ConfigRegularChannel(ADC_T* adc, uint8_t channel,uint8_t rank, uint8_t * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_EnableExternalTrigConv(ADC_T* adc) +void ADC_EnableExternalTrigConv(ADC_T *adc) { adc->CTRL2_B.REGEXTTRGEN = BIT_SET; } @@ -425,7 +441,7 @@ void ADC_EnableExternalTrigConv(ADC_T* adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_DisableExternalTrigConv(ADC_T* adc) +void ADC_DisableExternalTrigConv(ADC_T *adc) { adc->CTRL2_B.REGEXTTRGEN = BIT_RESET; } @@ -439,7 +455,7 @@ void ADC_DisableExternalTrigConv(ADC_T* adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -uint16_t ADC_ReadConversionValue(ADC_T* adc) +uint16_t ADC_ReadConversionValue(ADC_T *adc) { return (uint16_t) adc->REGDATA; } @@ -453,9 +469,9 @@ uint16_t ADC_ReadConversionValue(ADC_T* adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -uint32_t ADC_ReadDualModeConversionValue(ADC_T* adc) +uint32_t ADC_ReadDualModeConversionValue(ADC_T *adc) { - return (*(__IOM uint32_t *) RDG_ADDRESS); + return (*(__IOM uint32_t *) RDG_ADDRESS); } /*! @@ -467,7 +483,7 @@ uint32_t ADC_ReadDualModeConversionValue(ADC_T* adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_EnableInjectedConv(ADC_T* adc) +void ADC_EnableAutoInjectedConv(ADC_T *adc) { adc->CTRL1_B.INJGACEN = BIT_SET; } @@ -481,7 +497,7 @@ void ADC_EnableInjectedConv(ADC_T* adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_DisableInjectedConv(ADC_T* adc) +void ADC_DisableAutoInjectedConv(ADC_T *adc) { adc->CTRL1_B.INJGACEN = BIT_RESET; } @@ -495,7 +511,7 @@ void ADC_DisableInjectedConv(ADC_T* adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_EnableInjectedDiscMode(ADC_T* adc) +void ADC_EnableInjectedDiscMode(ADC_T *adc) { adc->CTRL1_B.INJDISCEN = BIT_SET; } @@ -509,7 +525,7 @@ void ADC_EnableInjectedDiscMode(ADC_T* adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_DisableInjectedDiscMode(ADC_T* adc) +void ADC_DisableInjectedDiscMode(ADC_T *adc) { adc->CTRL1_B.INJDISCEN = BIT_RESET; } @@ -542,7 +558,7 @@ void ADC_DisableInjectedDiscMode(ADC_T* adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_ConfigExternalTrigInjectedConv(ADC_T* adc, ADC_EXT_TRIG_INJEC_CONV_T extTrigInjecConv) +void ADC_ConfigExternalTrigInjectedConv(ADC_T *adc, ADC_EXT_TRIG_INJEC_CONV_T extTrigInjecConv) { adc->CTRL2_B.INJGEXTTRGSEL = RESET; adc->CTRL2_B.INJGEXTTRGSEL |= extTrigInjecConv; @@ -557,7 +573,7 @@ void ADC_ConfigExternalTrigInjectedConv(ADC_T* adc, ADC_EXT_TRIG_INJEC_CONV_T ex * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_EnableExternalTrigInjectedConv(ADC_T* adc) +void ADC_EnableExternalTrigInjectedConv(ADC_T *adc) { adc->CTRL2_B.INJEXTTRGEN = BIT_SET; } @@ -571,7 +587,7 @@ void ADC_EnableExternalTrigInjectedConv(ADC_T* adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_DisableExternalTrigInjectedConv(ADC_T* adc) +void ADC_DisableExternalTrigInjectedConv(ADC_T *adc) { adc->CTRL2_B.INJEXTTRGEN = BIT_RESET; } @@ -585,7 +601,7 @@ void ADC_DisableExternalTrigInjectedConv(ADC_T* adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_EnableSoftwareStartInjectedConv(ADC_T* adc) +void ADC_EnableSoftwareStartInjectedConv(ADC_T *adc) { adc->CTRL2_B.INJEXTTRGEN = BIT_SET; adc->CTRL2_B.INJSWSC = BIT_SET; @@ -600,7 +616,7 @@ void ADC_EnableSoftwareStartInjectedConv(ADC_T* adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_DisableSoftwareStartInjectedConv(ADC_T* adc) +void ADC_DisableSoftwareStartInjectedConv(ADC_T *adc) { adc->CTRL2_B.INJEXTTRGEN = BIT_RESET; adc->CTRL2_B.INJSWSC = BIT_RESET; @@ -615,7 +631,7 @@ void ADC_DisableSoftwareStartInjectedConv(ADC_T* adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -uint8_t ADC_ReadSoftwareStartInjectedConvStatus(ADC_T* adc) +uint8_t ADC_ReadSoftwareStartInjectedConvStatus(ADC_T *adc) { uint8_t ret; ret = (adc->CTRL2_B.INJSWSC) ? BIT_SET : BIT_RESET; @@ -653,20 +669,20 @@ uint8_t ADC_ReadSoftwareStartInjectedConvStatus(ADC_T* adc) * * @param sampleTime: the specified ADC channel SampleTime * The parameter can be one of following values: - * @arg ADC_SAMPLE_TIME_1_5: ADC 1.5 clock cycles - * @arg ADC_SAMPLE_TIME_7_5: ADC 7.5 clock cycles - * @arg ADC_SAMPLE_TIME_13_5: ADC 13.5 clock cycles - * @arg ADC_SAMPLE_TIME_28_5: ADC 28.5 clock cycles - * @arg ADC_SAMPLE_TIME_41_5: ADC 41.5 clock cycles - * @arg ADC_SAMPLE_TIME_55_5: ADC 55.5 clock cycles - * @arg ADC_SAMPLE_TIME_71_5: ADC 71.5 clock cycles - * @arg ADC_SAMPLE_TIME_239_5: ADC 239.5 clock cycles + * @arg ADC_SAMPLETIME_1CYCLES5: ADC 1.5 clock cycles + * @arg ADC_SAMPLETIME_7CYCLES5: ADC 7.5 clock cycles + * @arg ADC_SAMPLETIME_13CYCLES5: ADC 13.5 clock cycles + * @arg ADC_SAMPLETIME_28CYCLES5: ADC 28.5 clock cycles + * @arg ADC_SAMPLETIME_41CYCLES5: ADC 41.5 clock cycles + * @arg ADC_SAMPLETIME_55CYCLES5: ADC 55.5 clock cycles + * @arg ADC_SAMPLETIME_71CYCLES5: ADC 71.5 clock cycles + * @arg ADC_SAMPLETIME_239CYCLES5: ADC 239.5 clock cycles * * @retval None * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_ConfigInjectedChannel(ADC_T* adc, uint8_t channel, uint8_t rank, uint8_t sampleTime) +void ADC_ConfigInjectedChannel(ADC_T *adc, uint8_t channel, uint8_t rank, uint8_t sampleTime) { uint32_t temp1 = 0; uint32_t temp2 = 0; @@ -674,9 +690,9 @@ void ADC_ConfigInjectedChannel(ADC_T* adc, uint8_t channel, uint8_t rank, uint8_ if (channel > ADC_CHANNEL_9) { temp1 = adc->SMPTIM1; - temp2 = SMPCYCCFG_SET_SMPTIM1 << (3*(channel - 10)); + temp2 = SMPCYCCFG_SET_SMPTIM1 << (3 * (channel - 10)); temp1 &= ~temp2; - temp2 = (uint32_t)sampleTime << (3*(channel - 10)); + temp2 = (uint32_t)sampleTime << (3 * (channel - 10)); temp1 |= temp2; adc->SMPTIM1 = temp1; } @@ -690,7 +706,7 @@ void ADC_ConfigInjectedChannel(ADC_T* adc, uint8_t channel, uint8_t rank, uint8_ adc->SMPTIM2 = temp1; } temp1 = adc->INJSEQ; - temp3 = (temp1 & INJSEQ_SET_INJSEQLEN)>> 20; + temp3 = (temp1 & INJSEQ_SET_INJSEQLEN) >> 20; temp2 = INJSEQ_SET_INJSEQC << (5 * (uint8_t)((rank + 3) - (temp3 + 1))); temp1 &= ~temp2; temp2 = (uint32_t)channel << (5 * (uint8_t)((rank + 3) - (temp3 + 1))); @@ -710,7 +726,7 @@ void ADC_ConfigInjectedChannel(ADC_T* adc, uint8_t channel, uint8_t rank, uint8_ * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_ConfigInjectedSequencerLength(ADC_T* adc, uint8_t length) +void ADC_ConfigInjectedSequencerLength(ADC_T *adc, uint8_t length) { adc->INJSEQ_B.INJSEQLEN = RESET; adc->INJSEQ_B.INJSEQLEN |= length - 1; @@ -735,7 +751,7 @@ void ADC_ConfigInjectedSequencerLength(ADC_T* adc, uint8_t length) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_ConfigInjectedOffset(ADC_T* adc, ADC_INJEC_CHANNEL_T channel, uint16_t offSet) +void ADC_ConfigInjectedOffset(ADC_T *adc, ADC_INJEC_CHANNEL_T channel, uint16_t offSet) { __IOM uint32_t tmp = 0; @@ -761,14 +777,14 @@ void ADC_ConfigInjectedOffset(ADC_T* adc, ADC_INJEC_CHANNEL_T channel, uint16_t * * @note adc can be ADC1, ADC2 or ADC3. */ -uint16_t ADC_ReadInjectedConversionValue(ADC_T* adc, ADC_INJEC_CHANNEL_T channel) +uint16_t ADC_ReadInjectedConversionValue(ADC_T *adc, ADC_INJEC_CHANNEL_T channel) { - __IOM uint32_t temp = 0; + __IOM uint32_t temp = 0; - temp = (uint32_t)adc; - temp += channel + INJDATA_OFFSET; + temp = (uint32_t)adc; + temp += channel + INJDATA_OFFSET; - return (uint16_t) (*(__IOM uint32_t*) temp); + return (uint16_t)(*(__IOM uint32_t *) temp); } /*! @@ -790,7 +806,7 @@ uint16_t ADC_ReadInjectedConversionValue(ADC_T* adc, ADC_INJEC_CHANNEL_T channel * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_EnableAnalogWatchdog(ADC_T* adc, uint32_t analogWatchdog) +void ADC_EnableAnalogWatchdog(ADC_T *adc, uint32_t analogWatchdog) { adc->CTRL1 &= 0xFF3FFDFF; adc->CTRL1 |= analogWatchdog; @@ -805,7 +821,7 @@ void ADC_EnableAnalogWatchdog(ADC_T* adc, uint32_t analogWatchdog) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_DisableAnalogWatchdog(ADC_T* adc) +void ADC_DisableAnalogWatchdog(ADC_T *adc) { adc->CTRL1 &= 0xFF3FFDFF; } @@ -825,7 +841,7 @@ void ADC_DisableAnalogWatchdog(ADC_T* adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_ConfigAnalogWatchdogThresholds(ADC_T* adc, uint16_t highThreshold, uint16_t lowThreshold) +void ADC_ConfigAnalogWatchdogThresholds(ADC_T *adc, uint16_t highThreshold, uint16_t lowThreshold) { adc->AWDHT = highThreshold; adc->AWDLT = lowThreshold; @@ -861,7 +877,7 @@ void ADC_ConfigAnalogWatchdogThresholds(ADC_T* adc, uint16_t highThreshold, uint * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_ConfigAnalogWatchdogSingleChannel(ADC_T* adc, uint8_t channel) +void ADC_ConfigAnalogWatchdogSingleChannel(ADC_T *adc, uint8_t channel) { adc->CTRL1_B.AWDCHSEL = BIT_RESET; adc->CTRL1 |= channel; @@ -876,7 +892,7 @@ void ADC_ConfigAnalogWatchdogSingleChannel(ADC_T* adc, uint8_t channel) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_EnableTempSensorVrefint(ADC_T* adc) +void ADC_EnableTempSensorVrefint(ADC_T *adc) { adc->CTRL2_B.TSVREFEN = BIT_SET; } @@ -890,7 +906,7 @@ void ADC_EnableTempSensorVrefint(ADC_T* adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_DisableTempSensorVrefint(ADC_T* adc) +void ADC_DisableTempSensorVrefint(ADC_T *adc) { adc->CTRL2_B.TSVREFEN = BIT_RESET; } @@ -910,7 +926,7 @@ void ADC_DisableTempSensorVrefint(ADC_T* adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_EnableInterrupt(ADC_T* adc, uint16_t interrupt) +void ADC_EnableInterrupt(ADC_T *adc, uint16_t interrupt) { uint8_t mask; @@ -933,7 +949,7 @@ void ADC_EnableInterrupt(ADC_T* adc, uint16_t interrupt) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_DisableInterrupt(ADC_T* adc, uint16_t interrupt) +void ADC_DisableInterrupt(ADC_T *adc, uint16_t interrupt) { uint8_t mask; @@ -958,19 +974,9 @@ void ADC_DisableInterrupt(ADC_T* adc, uint16_t interrupt) * * @note adc can be ADC1, ADC2 or ADC3. */ -uint8_t ADC_ReadStatusFlag(ADC_T* adc, ADC_FLAG_T flag) +uint8_t ADC_ReadStatusFlag(ADC_T *adc, ADC_FLAG_T flag) { - uint8_t status = RESET; - - if ((adc->STS & flag) != (uint8_t)RESET) - { - status = SET; - } - else - { - status = RESET; - } - return status; + return (adc->STS & flag) ? SET : RESET; } /*! @@ -990,7 +996,7 @@ uint8_t ADC_ReadStatusFlag(ADC_T* adc, ADC_FLAG_T flag) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_ClearStatusFlag(ADC_T* adc, uint8_t flag) +void ADC_ClearStatusFlag(ADC_T *adc, uint8_t flag) { adc->STS = ~(uint32_t)flag; } @@ -1010,14 +1016,14 @@ void ADC_ClearStatusFlag(ADC_T* adc, uint8_t flag) * * @note adc can be ADC1, ADC2 or ADC3. */ -uint8_t ADC_ReadIntFlag(ADC_T* adc, ADC_INT_T interrupt) +uint8_t ADC_ReadIntFlag(ADC_T *adc, ADC_INT_T flag) { uint8_t bitStatus = RESET; uint32_t itmask = 0; uint32_t enableStatus = 0; - itmask = interrupt >> 8; - enableStatus = (adc->CTRL1 & (uint8_t)interrupt); + itmask = flag >> 8; + enableStatus = (adc->CTRL1 & (uint8_t)flag); if (((adc->STS & itmask) != (uint32_t)RESET) && enableStatus) { @@ -1045,12 +1051,12 @@ uint8_t ADC_ReadIntFlag(ADC_T* adc, ADC_INT_T interrupt) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_ClearIntFlag(ADC_T* adc, uint16_t interrupt) +void ADC_ClearIntFlag(ADC_T *adc, uint16_t flag) { - uint8_t mask = 0; + uint8_t mask = 0; - mask = (uint8_t)(interrupt >> 8); - adc->STS = ~(uint32_t)mask; + mask = (uint8_t)(flag >> 8); + adc->STS = ~(uint32_t)mask; } /**@} end of group ADC_Fuctions*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_bakpr.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_bakpr.c index a7bfad2fdb..d5c19a0e08 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_bakpr.c +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_bakpr.c @@ -1,12 +1,26 @@ /*! - * @file apm32f10x_bakpr.c + * @file apm32f10x_bakpr.c * - * @brief This file provides all the BAKPR firmware functions. + * @brief This file provides all the BAKPR firmware functions. * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ #include "apm32f10x_bakpr.h" @@ -114,16 +128,19 @@ void BAKPR_DisableInterrupt(void) */ void BAKPR_ConfigRTCOutput(BAKPR_RTC_OUTPUT_SOURCE_T soure) { - if(soure == BAKPR_RTC_OUTPUT_SOURCE_NONE) + if (soure == BAKPR_RTC_OUTPUT_SOURCE_NONE) { BAKPR->CLKCAL = RESET; - } else if(soure == BAKPR_RTC_OUTPUT_SOURCE_CALIBRATION_CLOCK) + } + else if (soure == BAKPR_RTC_OUTPUT_SOURCE_CALIBRATION_CLOCK) { BAKPR->CLKCAL_B.CALCOEN = BIT_SET; - } else if(soure == BAKPR_RTC_OUTPUT_SOURCE_ALARM) + } + else if (soure == BAKPR_RTC_OUTPUT_SOURCE_ALARM) { BAKPR->CLKCAL_B.ASPOEN = BIT_SET; - } else if(soure == BAKPR_RTC_OUTPUT_SOURCE_SECOND) + } + else if (soure == BAKPR_RTC_OUTPUT_SOURCE_SECOND) { BAKPR->CLKCAL_B.ASPOSEL = BIT_SET; } diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_can.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_can.c index 7efff90f9d..ed0ef63b81 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_can.c +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_can.c @@ -1,12 +1,26 @@ /*! - * @file apm32f10x_can.c + * @file apm32f10x_can.c * - * @brief This file provides all the CAN firmware functions + * @brief This file provides all the CAN firmware functions * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ #include "apm32f10x_can.h" @@ -33,7 +47,7 @@ * * @note CAN2 applies only to APM32F103xC device. */ -void CAN_Reset(CAN_T* can) +void CAN_Reset(CAN_T *can) { if (can == CAN1) { @@ -58,7 +72,7 @@ void CAN_Reset(CAN_T* can) * * @note CAN2 applies only to APM32F103xC device. */ -uint8_t CAN_Config(CAN_T* can, CAN_Config_T* canConfig) +uint8_t CAN_Config(CAN_T *can, CAN_Config_T *canConfig) { uint8_t initStatus = ERROR; uint32_t wait_ack = 0x00000000; @@ -69,27 +83,18 @@ uint8_t CAN_Config(CAN_T* can, CAN_Config_T* canConfig) can->MCTRL_B.INITREQ = BIT_SET; /** Wait the acknowledge */ - while(((can->MSTS_B.INITFLG) != BIT_SET) && (wait_ack != 0x0000FFFF)) + while (((can->MSTS_B.INITFLG) != BIT_SET) && (wait_ack != 0x0000FFFF)) { wait_ack++; } /** Check acknowledge */ - if(((can->MSTS_B.INITFLG) != BIT_SET)) + if (((can->MSTS_B.INITFLG) != BIT_SET)) { initStatus = ERROR; } else { - if(canConfig->timeTrigComMode == ENABLE) - { - can->MCTRL_B.TTCM = BIT_SET; - } - else - { - can->MCTRL_B.TTCM = BIT_RESET; - } - - if(canConfig->autoBusOffManage == ENABLE) + if (canConfig->autoBusOffManage == ENABLE) { can->MCTRL_B.ALBOFFM = BIT_SET; } @@ -98,7 +103,7 @@ uint8_t CAN_Config(CAN_T* can, CAN_Config_T* canConfig) can->MCTRL_B.ALBOFFM = BIT_RESET; } - if(canConfig->autoWakeUpMode == ENABLE) + if (canConfig->autoWakeUpMode == ENABLE) { can->MCTRL_B.AWUPCFG = BIT_SET; } @@ -107,7 +112,7 @@ uint8_t CAN_Config(CAN_T* can, CAN_Config_T* canConfig) can->MCTRL_B.AWUPCFG = BIT_RESET; } - if(canConfig->nonAutoRetran == ENABLE) + if (canConfig->nonAutoRetran == ENABLE) { can->MCTRL_B.ARTXMD = BIT_SET; } @@ -116,7 +121,7 @@ uint8_t CAN_Config(CAN_T* can, CAN_Config_T* canConfig) can->MCTRL_B.ARTXMD = BIT_RESET; } - if(canConfig->rxFIFOLockMode == ENABLE) + if (canConfig->rxFIFOLockMode == ENABLE) { can->MCTRL_B.RXFLOCK = BIT_SET; } @@ -125,7 +130,7 @@ uint8_t CAN_Config(CAN_T* can, CAN_Config_T* canConfig) can->MCTRL_B.RXFLOCK = BIT_RESET; } - if(canConfig->txFIFOPriority == ENABLE) + if (canConfig->txFIFOPriority == ENABLE) { can->MCTRL_B.TXFPCFG = BIT_SET; } @@ -147,12 +152,12 @@ uint8_t CAN_Config(CAN_T* can, CAN_Config_T* canConfig) wait_ack = 0; /** Wait the acknowledge */ - while(((can->MSTS_B.INITFLG) != BIT_RESET) && (wait_ack != 0x0000FFFF)) + while (((can->MSTS_B.INITFLG) != BIT_RESET) && (wait_ack != 0x0000FFFF)) { wait_ack++; } /** Check acknowledge */ - if(((can->MSTS_B.INITFLG) != BIT_RESET)) + if (((can->MSTS_B.INITFLG) != BIT_RESET)) { initStatus = ERROR; } @@ -169,20 +174,20 @@ uint8_t CAN_Config(CAN_T* can, CAN_Config_T* canConfig) * * @param can: Select the CAN peripheral which can be CAN1 or CAN2. * - * @param filterConfig :Point to a CAN_FILTER_CONFIG_T structure. + * @param filterConfig :Point to a CAN_FilterConfig_T structure. * * @retval None * * @note CAN2 applies only to APM32F103xC device. */ -void CAN_ConfigFilter(CAN_T* can, CAN_FILTER_CONFIG_T* filterConfig) +void CAN_ConfigFilter(CAN_T *can, CAN_FilterConfig_T *filterConfig) { can->FCTRL_B.FINITEN = BIT_SET; can->FACT &= ~(1 << filterConfig->filterNumber); /** Filter Scale */ - if(filterConfig->filterScale == CAN_FILTER_SCALE_16BIT) + if (filterConfig->filterScale == CAN_FILTER_SCALE_16BIT) { /** 16-bit scale for the filter */ can->FSCFG &= ~(1 << filterConfig->filterNumber); @@ -196,7 +201,7 @@ void CAN_ConfigFilter(CAN_T* can, CAN_FILTER_CONFIG_T* filterConfig) (0x0000FFFF & filterConfig->filterIdHigh); } - if(filterConfig->filterScale == CAN_FILTER_SCALE_32BIT) + if (filterConfig->filterScale == CAN_FILTER_SCALE_32BIT) { can->FSCFG |= (1 << filterConfig->filterNumber); @@ -210,7 +215,7 @@ void CAN_ConfigFilter(CAN_T* can, CAN_FILTER_CONFIG_T* filterConfig) } /** Filter Mode */ - if(filterConfig->filterMode == CAN_FILTER_MODE_IDMASK) + if (filterConfig->filterMode == CAN_FILTER_MODE_IDMASK) { can->FMCFG &= ~(1 << filterConfig->filterNumber); } @@ -220,17 +225,17 @@ void CAN_ConfigFilter(CAN_T* can, CAN_FILTER_CONFIG_T* filterConfig) } /** Filter FIFO assignment */ - if(filterConfig->filterFIFO == CAN_FILTER_FIFO_0) + if (filterConfig->filterFIFO == CAN_FILTER_FIFO_0) { can->FFASS &= ~(1 << filterConfig->filterNumber); } - if(filterConfig->filterFIFO == CAN_FILTER_FIFO_1) + if (filterConfig->filterFIFO == CAN_FILTER_FIFO_1) { can->FFASS |= (1 << filterConfig->filterNumber); } /** Filter activation */ - if(filterConfig->filterActivation == ENABLE) + if (filterConfig->filterActivation == ENABLE) { can->FACT |= (1 << filterConfig->filterNumber); } @@ -246,9 +251,8 @@ void CAN_ConfigFilter(CAN_T* can, CAN_FILTER_CONFIG_T* filterConfig) * * @note CAN2 applies only to APM32F103xC device. */ -void CAN_ConfigStructInit(CAN_Config_T* canConfig) +void CAN_ConfigStructInit(CAN_Config_T *canConfig) { - canConfig->timeTrigComMode = DISABLE; canConfig->autoBusOffManage = DISABLE; canConfig->autoWakeUpMode = DISABLE; canConfig->nonAutoRetran = DISABLE; @@ -270,7 +274,7 @@ void CAN_ConfigStructInit(CAN_Config_T* canConfig) * * @note CAN2 applies only to APM32F103xC device. */ -void CAN_EnableDBGFreeze(CAN_T* can) +void CAN_EnableDBGFreeze(CAN_T *can) { can->MCTRL_B.DBGFRZE = ENABLE; } @@ -284,45 +288,23 @@ void CAN_EnableDBGFreeze(CAN_T* can) * * @note CAN2 applies only to APM32F103xC device. */ -void CAN_DisableDBGFreeze(CAN_T* can) +void CAN_DisableDBGFreeze(CAN_T *can) { can->MCTRL_B.DBGFRZE = DISABLE; } /*! - * @brief Enables the CAN Time TriggerOperation communication mode. + * @brief Select the start bank filter for slave CAN. * - * @param can: Select the CAN peripheral. + * @param bankNum: the start slave bank filter from 1..27. * * @retval None - * - * @note CAN2 applies only to APM32F103xC device. */ -void CAN_EnableTTCComMode(CAN_T* can) +void CAN_SlaveStartBank(CAN_T *can, uint8_t bankNum) { - can->MCTRL_B.TTCM = ENABLE; - - can->sTxMailBox[0].TXDLEN_B.TXTS = BIT_SET; - can->sTxMailBox[1].TXDLEN_B.TXTS = BIT_SET; - can->sTxMailBox[2].TXDLEN_B.TXTS = BIT_SET; -} - -/*! - * @brief Disable the CAN Time TriggerOperation communication mode. - * - * @param can: Select the CAN peripheral. - * - * @retval None - * - * @note CAN2 applies only to APM32F103xC device. - */ -void CAN_DisableTTCComMode(CAN_T* can) -{ - can->MCTRL_B.TTCM = DISABLE; - - can->sTxMailBox[0].TXDLEN_B.TXTS = BIT_RESET; - can->sTxMailBox[1].TXDLEN_B.TXTS = BIT_RESET; - can->sTxMailBox[2].TXDLEN_B.TXTS = BIT_RESET; + can->FCTRL_B.FINITEN = SET; + can->FCTRL_B.CAN2BN = bankNum; + can->FCTRL_B.FINITEN = RESET; } /*! @@ -330,39 +312,41 @@ void CAN_DisableTTCComMode(CAN_T* can) * * @param can: Select the CAN peripheral. * - * @param TxMessage: pointer to a CAN_TX_MESSAGE_T structure. + * @param TxMessage: pointer to a CAN_TxMessage_T structure. * * @retval The number of the mailbox which is used for transmission or 3 if No mailbox is empty. * * @note CAN2 applies only to APM32F103xC device. */ -uint8_t CAN_TxMessage(CAN_T* can, CAN_TX_MESSAGE_T* TxMessage) +uint8_t CAN_TxMessage(CAN_T *can, CAN_TxMessage_T *TxMessage) { uint8_t transmit_milbox = 0; /** Select one empty transmit mailbox */ - if((can->TXSTS & 0x04000000) == 0x04000000) + if ((can->TXSTS & 0x04000000) == 0x04000000) { transmit_milbox = 0; } - else if((can->TXSTS & 0x08000000) == 0x08000000) + else if ((can->TXSTS & 0x08000000) == 0x08000000) { transmit_milbox = 1; } - else if((can->TXSTS & 0x10000000) == 0x10000000) + else if ((can->TXSTS & 0x10000000) == 0x10000000) { transmit_milbox = 2; - } else + } + else { return 3; //!< No mailbox is empty } /** Set up the Id */ can->sTxMailBox[transmit_milbox].TXMID &= 0x00000001; - if(TxMessage->typeID == CAN_TYPEID_STD) + if (TxMessage->typeID == CAN_TYPEID_STD) { can->sTxMailBox[transmit_milbox].TXMID |= (TxMessage->stdID << 21) | (TxMessage->remoteTxReq); - } else + } + else { can->sTxMailBox[transmit_milbox].TXMID |= (TxMessage->extID << 3) | (TxMessage->typeID) | (TxMessage->remoteTxReq); } @@ -396,45 +380,53 @@ uint8_t CAN_TxMessage(CAN_T* can, CAN_TX_MESSAGE_T* TxMessage) * * @note CAN2 applies only to APM32F103xC device. */ -uint8_t CAN_TxMessageStatus(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox) +uint8_t CAN_TxMessageStatus(CAN_T *can, CAN_TX_MAILBIX_T TxMailbox) { uint32_t state = 0; switch (TxMailbox) { - case (CAN_TX_MAILBIX_0): - state = can->TXSTS & (0x00000001 | 0x00000002 | 0x04000000); + case (CAN_TX_MAILBIX_0): + state = can->TXSTS & (0x00000001 | 0x00000002 | 0x04000000); break; - case (CAN_TX_MAILBIX_1): - state = can->TXSTS & (0x00000100 | 0x00000200 | 0x08000000); + case (CAN_TX_MAILBIX_1): + state = can->TXSTS & (0x00000100 | 0x00000200 | 0x08000000); break; - case (CAN_TX_MAILBIX_2): - state = can->TXSTS & (0x00010000 | 0x00020000 | 0x10000000); + case (CAN_TX_MAILBIX_2): + state = can->TXSTS & (0x00010000 | 0x00020000 | 0x10000000); break; - default: - state = 0; + default: + state = 0; break; } switch (state) { - /** transmit pending */ - case (0x0): state = 2; + /** Transmit pending */ + case (0x0): + state = 2; break; - /* transmit failed */ - case (0x00000001 | 0x04000000): state = 0; + /** Transmit failed */ + case (0x00000001 | 0x04000000): + state = 0; break; - case (0x00000100 | 0x08000000): state = 0; + case (0x00000100 | 0x08000000): + state = 0; break; - case (0x00010000 | 0x10000000): state = 0; + case (0x00010000 | 0x10000000): + state = 0; break; - /* transmit succeeded */ - case (0x00000001 | 0x00000002 | 0x04000000):state = 1; + /** Transmit succeeded */ + case (0x00000001 | 0x00000002 | 0x04000000): + state = 1; break; - case (0x00000100 | 0x00000200 | 0x08000000):state = 1; + case (0x00000100 | 0x00000200 | 0x08000000): + state = 1; break; - case (0x00010000 | 0x00020000 | 0x10000000):state = 1; + case (0x00010000 | 0x00020000 | 0x10000000): + state = 1; break; - default: state = 0; + default: + state = 0; break; } return (uint8_t) state; @@ -455,7 +447,7 @@ uint8_t CAN_TxMessageStatus(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox) * * @note CAN2 applies only to APM32F103xC device. */ -void CAN_CancelTxMailbox(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox) +void CAN_CancelTxMailbox(CAN_T *can, CAN_TX_MAILBIX_T TxMailbox) { switch (TxMailbox) { @@ -474,7 +466,7 @@ void CAN_CancelTxMailbox(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox) } /*! - * @brief Receives a message and save to a CAN_RX_MESSAGE_T structure. + * @brief Receives a message and save to a CAN_RxMessage_T structure. * * @param can: Select the CAN peripheral. * @@ -489,11 +481,11 @@ void CAN_CancelTxMailbox(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox) * * @note CAN2 applies only to APM32F103xC device. */ -void CAN_RxMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber, CAN_RX_MESSAGE_T* RxMessage) +void CAN_RxMessage(CAN_T *can, CAN_RX_FIFO_T FIFONumber, CAN_RxMessage_T *RxMessage) { - /* Get the Id */ + /** Get the Id */ RxMessage->typeID = ((uint8_t)0x04 & (can->sRxMailBox[FIFONumber].RXMID)); - if(RxMessage->typeID == CAN_TYPEID_STD) + if (RxMessage->typeID == CAN_TYPEID_STD) { RxMessage->stdID = (can->sRxMailBox[FIFONumber].RXMID >> 21) & 0x000007FF; } @@ -506,16 +498,16 @@ void CAN_RxMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber, CAN_RX_MESSAGE_T* RxMes RxMessage->dataLengthCode = can->sRxMailBox[FIFONumber].RXDLEN_B.DLCODE; RxMessage->filterMatchIndex = can->sRxMailBox[FIFONumber].RXDLEN_B.FMIDX; /** Get the data field */ - RxMessage->data[0] = can->sRxMailBox[FIFONumber].RXMDL_B.DATABYTE1; - RxMessage->data[1] = can->sRxMailBox[FIFONumber].RXMDL_B.DATABYTE2; - RxMessage->data[2] = can->sRxMailBox[FIFONumber].RXMDL_B.DATABYTE3; - RxMessage->data[3] = can->sRxMailBox[FIFONumber].RXMDL_B.DATABYTE4; - RxMessage->data[4] = can->sRxMailBox[FIFONumber].RXMDH_B.DATABYTE5; - RxMessage->data[5] = can->sRxMailBox[FIFONumber].RXMDH_B.DATABYTE6; - RxMessage->data[6] = can->sRxMailBox[FIFONumber].RXMDH_B.DATABYTE7; - RxMessage->data[7] = can->sRxMailBox[FIFONumber].RXMDH_B.DATABYTE8; + RxMessage->data[0] = can->sRxMailBox[FIFONumber].RXMDL_B.DATABYTE0; + RxMessage->data[1] = can->sRxMailBox[FIFONumber].RXMDL_B.DATABYTE1; + RxMessage->data[2] = can->sRxMailBox[FIFONumber].RXMDL_B.DATABYTE2; + RxMessage->data[3] = can->sRxMailBox[FIFONumber].RXMDL_B.DATABYTE3; + RxMessage->data[4] = can->sRxMailBox[FIFONumber].RXMDH_B.DATABYTE4; + RxMessage->data[5] = can->sRxMailBox[FIFONumber].RXMDH_B.DATABYTE5; + RxMessage->data[6] = can->sRxMailBox[FIFONumber].RXMDH_B.DATABYTE6; + RxMessage->data[7] = can->sRxMailBox[FIFONumber].RXMDH_B.DATABYTE7; - if(FIFONumber == CAN_RX_FIFO_0) + if (FIFONumber == CAN_RX_FIFO_0) { can->RXF0_B.RFOM0 = BIT_SET; } @@ -539,9 +531,9 @@ void CAN_RxMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber, CAN_RX_MESSAGE_T* RxMes * * @note CAN2 applies only to APM32F103xC device. */ -void CAN_ReleaseFIFO(CAN_T* can, CAN_RX_FIFO_T FIFONumber) +void CAN_ReleaseFIFO(CAN_T *can, CAN_RX_FIFO_T FIFONumber) { - if(FIFONumber == CAN_RX_FIFO_0) + if (FIFONumber == CAN_RX_FIFO_0) { can->RXF0_B.RFOM0 = BIT_SET; } @@ -565,9 +557,9 @@ void CAN_ReleaseFIFO(CAN_T* can, CAN_RX_FIFO_T FIFONumber) * * @note CAN2 applies only to APM32F103xC device. */ -uint8_t CAN_PendingMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber) +uint8_t CAN_PendingMessage(CAN_T *can, CAN_RX_FIFO_T FIFONumber) { - if(FIFONumber == CAN_RX_FIFO_0) + if (FIFONumber == CAN_RX_FIFO_0) { return can->RXF0 & 0x03; } @@ -594,53 +586,53 @@ uint8_t CAN_PendingMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber) * * @note CAN2 applies only to APM32F103xC device. */ -uint8_t CAN_OperatingMode(CAN_T* can, CAN_OPERATING_MODE_T operatingMode) +uint8_t CAN_OperatingMode(CAN_T *can, CAN_OPERATING_MODE_T operatingMode) { uint8_t states = 0; uint32_t time_out = 0x0000FFFF; - if(operatingMode == CAN_OPERATING_MODE_INIT) + if (operatingMode == CAN_OPERATING_MODE_INIT) { can->MCTRL_B.SLEEPREQ = BIT_RESET; can->MCTRL_B.INITREQ = BIT_SET; - while((can->MSTS_B.INITFLG != BIT_SET && can->MSTS_B.SLEEPFLG != BIT_RESET) && (time_out != 0)) + while ((can->MSTS_B.INITFLG != BIT_SET && can->MSTS_B.SLEEPFLG != BIT_RESET) && (time_out != 0)) { time_out --; } - if((can->MSTS_B.INITFLG == BIT_SET && can->MSTS_B.SLEEPFLG == BIT_RESET)) + if ((can->MSTS_B.INITFLG == BIT_SET && can->MSTS_B.SLEEPFLG == BIT_RESET)) { states = 1; } } - else if(operatingMode == CAN_OPERATING_MODE_NORMAL) + else if (operatingMode == CAN_OPERATING_MODE_NORMAL) { can->MCTRL_B.SLEEPREQ = BIT_RESET; can->MCTRL_B.INITREQ = BIT_RESET; time_out = 0x0000FFFF; - while((can->MSTS_B.INITFLG != BIT_RESET || can->MSTS_B.SLEEPFLG != BIT_RESET) && (time_out != 0)) + while ((can->MSTS_B.INITFLG != BIT_RESET || can->MSTS_B.SLEEPFLG != BIT_RESET) && (time_out != 0)) { time_out --; } - if((can->MSTS_B.INITFLG == BIT_RESET || can->MSTS_B.SLEEPFLG == BIT_RESET)) + if ((can->MSTS_B.INITFLG == BIT_RESET || can->MSTS_B.SLEEPFLG == BIT_RESET)) { states = 1; } } - else if(operatingMode == CAN_OPERATING_MODE_SLEEP) + else if (operatingMode == CAN_OPERATING_MODE_SLEEP) { can->MCTRL_B.SLEEPREQ = BIT_SET; can->MCTRL_B.INITREQ = BIT_RESET; time_out = 0x0000FFFF; - while((can->MSTS_B.INITFLG != BIT_RESET && can->MSTS_B.SLEEPFLG != BIT_SET) && (time_out != 0)) + while ((can->MSTS_B.INITFLG != BIT_RESET && can->MSTS_B.SLEEPFLG != BIT_SET) && (time_out != 0)) { time_out --; } - if((can->MSTS_B.INITFLG == BIT_RESET && can->MSTS_B.SLEEPFLG == BIT_SET)) + if ((can->MSTS_B.INITFLG == BIT_RESET && can->MSTS_B.SLEEPFLG == BIT_SET)) { states = 1; } @@ -659,12 +651,12 @@ uint8_t CAN_OperatingMode(CAN_T* can, CAN_OPERATING_MODE_T operatingMode) * * @note CAN2 applies only to APM32F103xC device. */ -uint8_t CAN_SleepMode(CAN_T* can) +uint8_t CAN_SleepMode(CAN_T *can) { can->MCTRL_B.SLEEPREQ = BIT_SET; can->MCTRL_B.INITREQ = BIT_RESET; - if((can->MSTS_B.INITFLG == BIT_RESET && can->MSTS_B.SLEEPFLG == BIT_SET)) + if ((can->MSTS_B.INITFLG == BIT_RESET && can->MSTS_B.SLEEPFLG == BIT_SET)) { return 1; } @@ -682,16 +674,16 @@ uint8_t CAN_SleepMode(CAN_T* can) * * @note CAN2 applies only to APM32F103xC device. */ -uint8_t CAN_WakeUpMode(CAN_T* can) +uint8_t CAN_WakeUpMode(CAN_T *can) { uint32_t time_out = 0x0000FFFF; can->MCTRL_B.SLEEPREQ = BIT_RESET; - while((can->MSTS_B.SLEEPFLG != BIT_RESET) && (time_out != 0)) + while ((can->MSTS_B.SLEEPFLG != BIT_RESET) && (time_out != 0)) { time_out --; } - if(can->MSTS_B.SLEEPFLG == BIT_RESET) + if (can->MSTS_B.SLEEPFLG == BIT_RESET) { return 1; } @@ -707,7 +699,7 @@ uint8_t CAN_WakeUpMode(CAN_T* can) * * @note CAN2 applies only to APM32F103xC device. */ -uint8_t CAN_ReadLastErrorCode(CAN_T* can) +uint8_t CAN_ReadLastErrorCode(CAN_T *can) { return can->ERRSTS_B.LERRC; } @@ -721,7 +713,7 @@ uint8_t CAN_ReadLastErrorCode(CAN_T* can) * * @note CAN2 applies only to APM32F103xC device. */ -uint8_t CAN_ReadRxErrorCounter(CAN_T* can) +uint8_t CAN_ReadRxErrorCounter(CAN_T *can) { return can->ERRSTS_B.RXERRCNT; } @@ -735,7 +727,7 @@ uint8_t CAN_ReadRxErrorCounter(CAN_T* can) * * @note CAN2 applies only to APM32F103xC device. */ -uint8_t CAN_ReadLSBTxErrorCounter(CAN_T* can) +uint8_t CAN_ReadLSBTxErrorCounter(CAN_T *can) { return can->ERRSTS_B.TXERRCNT; } @@ -766,7 +758,7 @@ uint8_t CAN_ReadLSBTxErrorCounter(CAN_T* can) * * @note CAN2 applies only to APM32F103xC device. */ -void CAN_EnableInterrupt(CAN_T* can, uint32_t interrupts) +void CAN_EnableInterrupt(CAN_T *can, uint32_t interrupts) { can->INTEN |= interrupts; } @@ -797,7 +789,7 @@ void CAN_EnableInterrupt(CAN_T* can, uint32_t interrupts) * * @note CAN2 applies only to APM32F103xC device. */ -void CAN_DisableInterrupt(CAN_T* can, uint32_t interrupts) +void CAN_DisableInterrupt(CAN_T *can, uint32_t interrupts) { can->INTEN &= ~interrupts; } @@ -829,13 +821,13 @@ void CAN_DisableInterrupt(CAN_T* can, uint32_t interrupts) * * @note CAN2 applies only to APM32F103xC device. */ -uint8_t CAN_ReadStatusFlag(CAN_T* can, CAN_FLAG_T flag) +uint8_t CAN_ReadStatusFlag(CAN_T *can, CAN_FLAG_T flag) { uint8_t status = 0; - if((flag & 0x00F00000) != RESET ) + if ((flag & 0x00F00000) != RESET) { - if((can->ERRSTS & (flag & 0x000FFFFF)) != RESET) + if ((can->ERRSTS & (flag & 0x000FFFFF)) != RESET) { status = SET; } @@ -844,9 +836,9 @@ uint8_t CAN_ReadStatusFlag(CAN_T* can, CAN_FLAG_T flag) status = RESET; } } - else if((flag & 0x01000000) != RESET ) + else if ((flag & 0x01000000) != RESET) { - if((can->MSTS & (flag & 0x000FFFFF)) != RESET ) + if ((can->MSTS & (flag & 0x000FFFFF)) != RESET) { status = SET; } @@ -855,9 +847,9 @@ uint8_t CAN_ReadStatusFlag(CAN_T* can, CAN_FLAG_T flag) status = RESET ; } } - else if((flag & 0x08000000) != RESET ) + else if ((flag & 0x08000000) != RESET) { - if((can->TXSTS & (flag & 0x000FFFFF)) != RESET ) + if ((can->TXSTS & (flag & 0x000FFFFF)) != RESET) { status = SET; } @@ -866,9 +858,9 @@ uint8_t CAN_ReadStatusFlag(CAN_T* can, CAN_FLAG_T flag) status = RESET; } } - else if((flag & 0x02000000) != RESET ) + else if ((flag & 0x02000000) != RESET) { - if((can->RXF0 & (flag & 0x000FFFFF)) != RESET ) + if ((can->RXF0 & (flag & 0x000FFFFF)) != RESET) { status = SET; } @@ -879,7 +871,7 @@ uint8_t CAN_ReadStatusFlag(CAN_T* can, CAN_FLAG_T flag) } else { - if((can->RXF1 & (flag & 0x000FFFFF)) != RESET) + if ((can->RXF1 & (flag & 0x000FFFFF)) != RESET) { status = SET; } @@ -913,27 +905,27 @@ uint8_t CAN_ReadStatusFlag(CAN_T* can, CAN_FLAG_T flag) * * @note CAN2 applies only to APM32F103xC device. */ -void CAN_ClearStatusFlag(CAN_T* can, CAN_FLAG_T flag) +void CAN_ClearStatusFlag(CAN_T *can, CAN_FLAG_T flag) { uint32_t flagtmp = 0; /** ERRSTS register */ - if(flag == 0x30F00070) + if (flag == 0x30F00070) { can->ERRSTS = RESET; } else { flagtmp = flag & 0x000FFFFF; - if((flag & 0x02000000) != RESET) + if ((flag & 0x02000000) != RESET) { can->RXF0 = flagtmp; } - else if((flag & 0x04000000) != RESET) + else if ((flag & 0x04000000) != RESET) { can->RXF1 = flagtmp; } - else if((flag & 0x08000000) != RESET) + else if ((flag & 0x08000000) != RESET) { can->TXSTS = flagtmp; } @@ -970,16 +962,18 @@ void CAN_ClearStatusFlag(CAN_T* can, CAN_FLAG_T flag) * * @note CAN2 applies only to APM32F103xC device. */ -uint8_t CAN_ReadIntFlag(CAN_T* can, CAN_INT_T flag) +uint8_t CAN_ReadIntFlag(CAN_T *can, CAN_INT_T flag) { uint8_t status = 0; - if((can->INTEN & flag) != RESET) + if ((can->INTEN & flag) != RESET) { switch (flag) { case CAN_INT_TXME: - status = can->TXSTS_B.REQCFLG0 | can->TXSTS_B.REQCFLG1 | can->TXSTS_B.REQCFLG2; + status = can->TXSTS_B.REQCFLG0; + status |= can->TXSTS_B.REQCFLG1; + status |= can->TXSTS_B.REQCFLG2; break; case CAN_INT_F0MP: status = can->RXF0_B.FMNUM0; @@ -1056,7 +1050,7 @@ uint8_t CAN_ReadIntFlag(CAN_T* can, CAN_INT_T flag) * * @note CAN2 applies only to APM32F103xC device. */ -void CAN_ClearIntFlag(CAN_T* can, CAN_INT_T flag) +void CAN_ClearIntFlag(CAN_T *can, CAN_INT_T flag) { switch (flag) { diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_crc.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_crc.c index fd0d7b28a6..fe208b5678 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_crc.c +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_crc.c @@ -1,12 +1,26 @@ /*! - * @file apm32f10x_crc.c + * @file apm32f10x_crc.c * - * @brief This file provides all the CRC firmware functions + * @brief This file provides all the CRC firmware functions * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ #include "apm32f10x_crc.h" @@ -29,8 +43,6 @@ * @param None * * @retval None - * - * @note */ void CRC_ResetDATA(void) { @@ -63,7 +75,7 @@ uint32_t CRC_CalculateCRC(uint32_t data) */ uint32_t CRC_CalculateBlockCRC(uint32_t *buf, uint32_t bufLen) { - while(bufLen--) + while (bufLen--) { CRC->DATA = *buf++; } diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dac.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dac.c index e66cd77463..fac9e9f135 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dac.c +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dac.c @@ -3,10 +3,24 @@ * * @brief This file provides all the DAC firmware functions * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ #include "apm32f10x_dac.h" @@ -38,18 +52,18 @@ void DAC_Reset(void) } /*! - * @brief Config the DAC peripheral according to the specified parameters in the configStruct + * @brief Config the DAC peripheral according to the specified parameters in the dacConfig * * @param channel: Select the DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1 : DAC channel 1 * @arg DAC_CHANNEL_2 : DAC channel 2 * - * @param configStruct: pointer to a DAC_ConfigStruct_T structure + * @param dacConfig: pointer to a DAC_Config_T structure * * @retval None */ -void DAC_Config(uint32_t channel, DAC_ConfigStruct_T* configStruct) +void DAC_Config(uint32_t channel, DAC_Config_T *dacConfig) { uint32_t tmp1 = 0, tmp2 = 0; @@ -57,29 +71,33 @@ void DAC_Config(uint32_t channel, DAC_ConfigStruct_T* configStruct) tmp1 &= ~(((uint32_t)0x00000FFE) << channel); - tmp2 = (configStruct->trigger | configStruct->waveGeneration | configStruct->maskAmplitudeSelect | configStruct->outputBuffer); + tmp2 = ((uint32_t)dacConfig->trigger | \ + (uint32_t)dacConfig->waveGeneration | \ + (uint32_t)dacConfig->maskAmplitudeSelect | \ + (uint32_t)dacConfig->outputBuffer); + tmp1 |= tmp2 << channel; DAC->CTRL = tmp1; } /*! - * @brief Fills each DAC_ConfigStruct_T member with its default value + * @brief Fills each DAC_Config_T member with its default value * - * @param configStruct: pointer to a DAC_ConfigStruct_T structure which will be initialized + * @param dacConfig: pointer to a DAC_Config_T structure which will be initialized * * @retval None */ -void DAC_ConfigStructInit(DAC_ConfigStruct_T* configStruct) +void DAC_ConfigStructInit(DAC_Config_T *dacConfig) { - /* Initialize the DAC_Trigger member */ - configStruct->trigger = DAC_TRIGGER_NONE; - /* Initialize the DAC_WaveGeneration member */ - configStruct->waveGeneration = DAC_WAVE_GENERATION_NONE; - /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */ - configStruct->maskAmplitudeSelect = DAC_LFSR_MASK_BIT11_1; - /* Initialize the DAC_OutputBuffer member */ - configStruct->outputBuffer = DAC_OUTPUT_BUFFER_ENBALE; + /** Initialize the DAC_Trigger member */ + dacConfig->trigger = DAC_TRIGGER_NONE; + /** Initialize the DAC_WaveGeneration member */ + dacConfig->waveGeneration = DAC_WAVE_GENERATION_NONE; + /** Initialize the DAC_LFSRUnmask_TriangleAmplitude member */ + dacConfig->maskAmplitudeSelect = DAC_LFSR_MASK_BIT11_1; + /** Initialize the DAC_OutputBuffer member */ + dacConfig->outputBuffer = DAC_OUTPUT_BUFFER_ENBALE; } /*! @@ -303,7 +321,7 @@ void DAC_ConfigChannel1Data(DAC_ALIGN_T align, uint16_t data) tmp = (uint32_t)DAC_BASE; tmp += 0x00000008 + align; - /* Set the DAC channel1 selected data holding register */ + /** Set the DAC channel1 selected data holding register */ *(__IO uint32_t *) tmp = data; } @@ -327,7 +345,7 @@ void DAC_ConfigChannel2Data(DAC_ALIGN_T align, uint16_t data) tmp = (uint32_t)DAC_BASE; tmp += 0x00000014 + align; - /* Set the DAC channel1 selected data holding register */ + /** Set the DAC channel1 selected data holding register */ *(__IO uint32_t *) tmp = data; } @@ -350,7 +368,7 @@ void DAC_ConfigDualChannelData(DAC_ALIGN_T align, uint16_t data2, uint16_t data1 { uint32_t data = 0, tmp = 0; - /* Calculate and set dual DAC data holding register value */ + /** Calculate and set dual DAC data holding register value */ if (align == DAC_ALIGN_8BIT_R) { data = ((uint32_t)data2 << 8) | data1; @@ -363,7 +381,7 @@ void DAC_ConfigDualChannelData(DAC_ALIGN_T align, uint16_t data2, uint16_t data1 tmp = (uint32_t)DAC_BASE; tmp += 0x00000020 + align; - /* Set the dual DAC selected data holding register */ + /** Set the dual DAC selected data holding register */ *(__IO uint32_t *)tmp = data; } @@ -384,8 +402,8 @@ uint16_t DAC_ReadDataOutputValue(DAC_CHANNEL_T channel) tmp = (uint32_t) DAC_BASE ; tmp += 0x0000002C + ((uint32_t)channel >> 2); - /* Returns the DAC channel data output register value */ - return (uint16_t) (*(__IO uint32_t*) tmp); + /** Returns the DAC channel data output register value */ + return (uint16_t)(*(__IO uint32_t *) tmp); } /**@} end of group DAC_Fuctions*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dbgmcu.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dbgmcu.c index 985f9f215d..3486aa8cfe 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dbgmcu.c +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dbgmcu.c @@ -3,10 +3,24 @@ * * @brief This file provides all the DEBUG firmware functions * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ #include "apm32f10x_dbgmcu.h" @@ -32,7 +46,7 @@ */ uint32_t DBGMCU_ReadDEVID(void) { - return(DBGMCU->IDCODE_B.EQR); + return (DBGMCU->IDCODE_B.EQR); } /*! @@ -44,7 +58,7 @@ uint32_t DBGMCU_ReadDEVID(void) */ uint32_t DBGMCU_ReadREVID(void) { - return(DBGMCU->IDCODE_B.WVR); + return (DBGMCU->IDCODE_B.WVR); } /*! @@ -128,5 +142,5 @@ void DBGMCU_Disable(uint32_t periph) } /**@} end of group DBGMCU_Fuctions*/ -/**@} end of group DBGMCU_Driver */ +/**@} end of group DBGMCU_Driver*/ /**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dma.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dma.c index 0df9c93fa7..fc302ad9a4 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dma.c +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dma.c @@ -1,12 +1,26 @@ /*! - * @file apm32f10x_dma.c + * @file apm32f10x_dma.c * - * @brief This file provides all the DMA firmware functions + * @brief This file provides all the DMA firmware functions * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ #include "apm32f10x_dma.h" @@ -40,51 +54,51 @@ void DMA_Reset(DMA_Channel_T *channel) channel->CHMADDR = 0; channel->CHPADDR = 0; - if(channel == DMA1_Channel1) + if (channel == DMA1_Channel1) { DMA1->INTFCLR |= 0xFFFFFFF0; } - else if(channel == DMA1_Channel2) + else if (channel == DMA1_Channel2) { DMA1->INTFCLR |= 0xFFFFFF0F; } - else if(channel == DMA1_Channel3) + else if (channel == DMA1_Channel3) { DMA1->INTFCLR |= 0xFFFFF0FF; } - else if(channel == DMA1_Channel4) + else if (channel == DMA1_Channel4) { DMA1->INTFCLR |= 0xFFFF0FFF; } - else if(channel == DMA1_Channel5) + else if (channel == DMA1_Channel5) { DMA1->INTFCLR |= 0xFFF0FFFF; } - else if(channel == DMA1_Channel6) + else if (channel == DMA1_Channel6) { DMA1->INTFCLR |= 0xFF0FFFFF; } - else if(channel == DMA1_Channel7) + else if (channel == DMA1_Channel7) { DMA1->INTFCLR |= 0xF0FFFFFF; } - else if(channel == DMA2_Channel1) + else if (channel == DMA2_Channel1) { DMA2->INTFCLR |= 0xFFFFFFF0; } - else if(channel == DMA2_Channel2) + else if (channel == DMA2_Channel2) { DMA2->INTFCLR |= 0xFFFFFF0F; } - else if(channel == DMA2_Channel3) + else if (channel == DMA2_Channel3) { DMA2->INTFCLR |= 0xFFFFF0FF; } - else if(channel == DMA2_Channel4) + else if (channel == DMA2_Channel4) { DMA2->INTFCLR |= 0xFFFF0FFF; } - else if(channel == DMA2_Channel5) + else if (channel == DMA2_Channel5) { DMA2->INTFCLR |= 0xFFF0FFFF; } @@ -101,7 +115,7 @@ void DMA_Reset(DMA_Channel_T *channel) * * @note DMA2 Channel only for APM32 High density devices. */ -void DMA_Config(DMA_Channel_T* channel, DMA_Config_T* dmaConfig) +void DMA_Config(DMA_Channel_T *channel, DMA_Config_T *dmaConfig) { channel->CHCFG_B.DIRCFG = dmaConfig->dir; channel->CHCFG_B.CIRMODE = dmaConfig->loopMode; @@ -124,7 +138,7 @@ void DMA_Config(DMA_Channel_T* channel, DMA_Config_T* dmaConfig) * * @retval None */ -void DMA_ConfigStructInit( DMA_Config_T* dmaConfig) +void DMA_ConfigStructInit(DMA_Config_T *dmaConfig) { dmaConfig->peripheralBaseAddr = 0; dmaConfig->memoryBaseAddr = 0; @@ -298,22 +312,24 @@ void DMA_DisableInterrupt(DMA_Channel_T *channel, uint32_t interrupt) */ uint8_t DMA_ReadStatusFlag(DMA_FLAG_T flag) { - if((flag & 0x10000000) != RESET ) + if ((flag & 0x10000000) != RESET) { - if((DMA2->INTSTS & flag ) != RESET ) + if ((DMA2->INTSTS & flag) != RESET) { return SET ; - } else + } + else { return RESET ; } } else { - if((DMA1->INTSTS & flag ) != RESET ) + if ((DMA1->INTSTS & flag) != RESET) { return SET ; - } else + } + else { return RESET ; } @@ -381,10 +397,11 @@ uint8_t DMA_ReadStatusFlag(DMA_FLAG_T flag) */ void DMA_ClearStatusFlag(uint32_t flag) { - if((flag & 0x10000000) != RESET) + if ((flag & 0x10000000) != RESET) { DMA2->INTFCLR = flag; - } else + } + else { DMA1->INTFCLR = flag; } @@ -451,21 +468,24 @@ void DMA_ClearStatusFlag(uint32_t flag) */ uint8_t DMA_ReadIntFlag(DMA_INT_FLAG_T flag) { - if((flag & 0x10000000) != RESET ) + if ((flag & 0x10000000) != RESET) { - if((DMA2->INTSTS & flag ) != RESET ) + if ((DMA2->INTSTS & flag) != RESET) { return SET ; - } else + } + else { return RESET ; } - } else + } + else { - if((DMA1->INTSTS & flag ) != RESET ) + if ((DMA1->INTSTS & flag) != RESET) { return SET ; - } else + } + else { return RESET ; } @@ -532,10 +552,11 @@ uint8_t DMA_ReadIntFlag(DMA_INT_FLAG_T flag) */ void DMA_ClearIntFlag(uint32_t flag) { - if((flag & 0x10000000) != RESET) + if ((flag & 0x10000000) != RESET) { DMA2->INTFCLR = flag; - } else + } + else { DMA1->INTFCLR = flag; } diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dmc.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dmc.c index 619550794f..290ab8d697 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dmc.c +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dmc.c @@ -3,11 +3,27 @@ * * @brief This file contains all the functions for the DMC controler peripheral * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ + +#ifdef APM32F10X_HD #include "apm32f10x_dmc.h" /** @addtogroup Peripherals_Library Standard Peripheral Library @@ -29,10 +45,10 @@ * * @retval None */ -void DMC_Config(DMC_Config_T * dmcConfig) +void DMC_Config(DMC_Config_T *dmcConfig) { DMC->SW_B.MCSW = 1; - while(!DMC->CTRL1_B.INIT); + while (!DMC->CTRL1_B.INIT); DMC->CFG_B.BAWCFG = dmcConfig->bankWidth; DMC->CFG_B.RAWCFG = dmcConfig->rowWidth; @@ -44,7 +60,7 @@ void DMC_Config(DMC_Config_T * dmcConfig) DMC_ConfigTiming(&dmcConfig->timing); DMC->CTRL1_B.MODESET = 1; - while(!DMC->CTRL1_B.MODESET); + while (!DMC->CTRL1_B.MODESET); DMC->CTRL2_B.RDDEN = 1; DMC->CTRL2_B.RDDCFG = 7; @@ -57,7 +73,7 @@ void DMC_Config(DMC_Config_T * dmcConfig) * * @retval None */ -void DMC_ConfigStructInit(DMC_Config_T * dmcConfig) +void DMC_ConfigStructInit(DMC_Config_T *dmcConfig) { dmcConfig->bankWidth = DMC_BANK_WIDTH_2; dmcConfig->clkPhase = DMC_CLK_PHASE_REVERSE; @@ -75,7 +91,7 @@ void DMC_ConfigStructInit(DMC_Config_T * dmcConfig) * * @retval None */ -void DMC_ConfigTiming(DMC_TimingConfig_T * timingConfig) +void DMC_ConfigTiming(DMC_TimingConfig_T *timingConfig) { DMC->TIM0_B.RASMINTSEL = timingConfig->tRAS; DMC->TIM0_B.DTIMSEL = timingConfig->tRCD; @@ -100,7 +116,7 @@ void DMC_ConfigTiming(DMC_TimingConfig_T * timingConfig) * * @retval None */ -void DMC_ConfigTimingStructInit(DMC_TimingConfig_T * timingConfig) +void DMC_ConfigTimingStructInit(DMC_TimingConfig_T *timingConfig) { timingConfig->latencyCAS = DMC_CAS_LATENCY_3; timingConfig->tARP = DMC_AUTO_REFRESH_10; @@ -267,6 +283,30 @@ void DMC_EnterSlefRefreshMode(void) DMC->CTRL1_B.SRMEN = 1; } +/*! + * @brief Enable Accelerate Module + * + * @param None + * + * @retval None + */ +void DMC_EnableAccelerateModule(void) +{ + DMC->CTRL2_B.BUFFEN = BIT_SET; +} + +/*! + * @brief Disable Accelerate Module + * + * @param None + * + * @retval None + */ +void DMC_DisableAccelerateModule(void) +{ + DMC->CTRL2_B.BUFFEN = BIT_RESET; +} + /*! * @brief Init DMC * @@ -396,14 +436,29 @@ void DMC_Disable(void) * @arg DMC_CLK_PHASE_REVERSE: Clock phase is reverse * * @retval None - * */ void DMC_ConfigClockPhase(DMC_CLK_PHASE_T clkPhase) { DMC->CTRL2_B.CPHACFG = clkPhase; } -/**@} end of group DMC_Fuctions*/ -/**@} end of group DMC_Driver */ -/**@} end of group Peripherals_Library*/ +/*! + * @brief Set DMC WRAP burst + * + * @param burst: WRAP burst Type Selection + * The parameter can be one of following values: + * @arg DMC_WRAPB_4: wrap4 burst transfer + * @arg DMC_WRAPB_8: wrap8 burst transfer + * + * @retval None + */ +void DMC_ConfigWRAPB(DMC_WRPB_T burst) +{ + DMC->CTRL2_B.WRPBSEL = burst; +} +#endif //defined APM32F10X_HD + +/**@} end of group DMC_Fuctions*/ +/**@} end of group DMC_Driver*/ +/**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_eint.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_eint.c index cc0eafe579..9b4c63aeac 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_eint.c +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_eint.c @@ -1,12 +1,26 @@ /*! - * @file apm32f10x_eint.c + * @file apm32f10x_eint.c * - * @brief This file provides all the EINT firmware functions + * @brief This file provides all the EINT firmware functions * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ #include "apm32f10x_eint.h" @@ -46,12 +60,12 @@ void EINT_Reset(void) * * @retval None */ -void EINT_Config(EINT_Config_T* eintConfig) +void EINT_Config(EINT_Config_T *eintConfig) { uint32_t temp = 0; temp = (uint32_t)EINT_BASE; - if(eintConfig->lineCmd != DISABLE) + if (eintConfig->lineCmd != DISABLE) { EINT->IMASK &= ~eintConfig->line; EINT->EMASK &= ~eintConfig->line; @@ -83,6 +97,21 @@ void EINT_Config(EINT_Config_T* eintConfig) } } +/*! + * @brief Fills each EINT_Config_T member with its reset value. + * + * @param eintConfig: pointer to a EINT_Config_T structure + * + * @retval None + */ +void EINT_ConfigStructInit(EINT_Config_T *eintConfig) +{ + eintConfig->line = EINT_LINENONE; + eintConfig->mode = EINT_MODE_INTERRUPT; + eintConfig->trigger = EINT_TRIGGER_FALLING; + eintConfig->lineCmd = DISABLE; +} + /*! * @brief Select Software interrupt on EINT line * @@ -108,7 +137,7 @@ uint8_t EINT_ReadStatusFlag(EINT_LINE_T line) { uint8_t status = RESET; - if((EINT->IPEND & line) != (uint32_t)RESET) + if ((EINT->IPEND & line) != (uint32_t)RESET) { status = SET; } @@ -147,7 +176,7 @@ uint8_t EINT_ReadIntFlag(EINT_LINE_T line) enablestatus = EINT->IMASK & line; - if((EINT->IPEND & line) != ((uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) + if ((EINT->IPEND & line) != ((uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) { status = SET; } @@ -172,5 +201,5 @@ void EINT_ClearIntFlag(uint32_t line) } /**@} end of group EINT_Fuctions*/ -/**@} end of group EINT_Driver */ +/**@} end of group EINT_Driver*/ /**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_emmc.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_emmc.c index 8d79d213d8..b27dd63d2b 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_emmc.c +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_emmc.c @@ -1,12 +1,26 @@ /*! - * @file apm32f10x_emmc.c + * @file apm32f10x_emmc.c * - * @brief This file provides all the EMMC firmware functions + * @brief This file provides all the EMMC firmware functions * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ #include "apm32f10x_emmc.h" @@ -39,7 +53,7 @@ void EMMC_ResetNORSRAM(EMMC_BANK1_NORSRAM_T bank) { /** EMMC_BANK1_NORSRAM_1 */ - if(bank == EMMC_BANK1_NORSRAM_1) + if (bank == EMMC_BANK1_NORSRAM_1) { EMMC_Bank1->SNCTRL_T[bank] = 0x000030DB; } @@ -64,7 +78,7 @@ void EMMC_ResetNORSRAM(EMMC_BANK1_NORSRAM_T bank) */ void EMMC_ResetNAND(EMMC_BANK_NAND_T bank) { - if(bank == EMMC_BANK2_NAND) + if (bank == EMMC_BANK2_NAND) { /** Set the EMMC_Bank2 registers to their reset values */ EMMC_Bank2->CTRL2 = 0x00000018; @@ -75,7 +89,7 @@ void EMMC_ResetNAND(EMMC_BANK_NAND_T bank) /** EMMC_BANK3_NAND */ else { - /* Set the EMMC_Bank3 registers to their reset values */ + /** Set the EMMC_Bank3 registers to their reset values */ EMMC_Bank3->CTRL3 = 0x00000018; EMMC_Bank3->STSINT3 = 0x00000040; EMMC_Bank3->CMSTIM3 = 0xFCFCFCFC; @@ -107,9 +121,9 @@ void EMMC_ResetPCCard(void) * * @retval None */ -void EMMC_ConfigNORSRAM(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig) +void EMMC_ConfigNORSRAM(EMMC_NORSRAMConfig_T *emmcNORSRAMConfig) { - /* Bank1 NOR/SRAM control register configuration */ + /** Bank1 NOR/SRAM control register configuration */ EMMC_Bank1->SNCTRL_T[emmcNORSRAMConfig->bank] = (uint32_t)emmcNORSRAMConfig->dataAddressMux | emmcNORSRAMConfig->memoryType | @@ -124,12 +138,12 @@ void EMMC_ConfigNORSRAM(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig) emmcNORSRAMConfig->extendedMode | emmcNORSRAMConfig->writeBurst; - if(emmcNORSRAMConfig->memoryType == EMMC_MEMORY_TYPE_NOR) + if (emmcNORSRAMConfig->memoryType == EMMC_MEMORY_TYPE_NOR) { EMMC_Bank1->SNCTRL_T[emmcNORSRAMConfig->bank] |= 0x00000040; } - /* Bank1 NOR/SRAM timing register configuration */ + /** Bank1 NOR/SRAM timing register configuration */ EMMC_Bank1->SNCTRL_T[emmcNORSRAMConfig->bank + 1] = (uint32_t)emmcNORSRAMConfig->readWriteTimingStruct->addressSetupTime | (emmcNORSRAMConfig->readWriteTimingStruct->addressHodeTime << 4) | @@ -139,8 +153,8 @@ void EMMC_ConfigNORSRAM(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig) (emmcNORSRAMConfig->readWriteTimingStruct->dataLatency << 24) | emmcNORSRAMConfig->readWriteTimingStruct->accessMode; - /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */ - if(emmcNORSRAMConfig->extendedMode == EMMC_EXTENDEN_MODE_ENABLE) + /** Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */ + if (emmcNORSRAMConfig->extendedMode == EMMC_EXTENDEN_MODE_ENABLE) { EMMC_Bank1E->WRTTIM[emmcNORSRAMConfig->bank] = (uint32_t)emmcNORSRAMConfig->writeTimingStruct->addressSetupTime | @@ -163,11 +177,11 @@ void EMMC_ConfigNORSRAM(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig) * * @retval None */ -void EMMC_ConfigNAND(EMMC_NANDConfig_T* emmcNANDConfig) +void EMMC_ConfigNAND(EMMC_NANDConfig_T *emmcNANDConfig) { uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; - /* Set the tmppcr value according to EMMC_NANDInitStruct parameters */ + /** Set the tmppcr value according to EMMC_NANDInitStruct parameters */ tmppcr = (uint32_t)emmcNANDConfig->waitFeature | 0x00000008 | emmcNANDConfig->memoryDataWidth | emmcNANDConfig->ECC | @@ -175,28 +189,28 @@ void EMMC_ConfigNAND(EMMC_NANDConfig_T* emmcNANDConfig) (emmcNANDConfig->TCLRSetupTime << 9) | (emmcNANDConfig->TARSetupTime << 13); - /* Set tmppmem value according to EMMC_CommonSpaceTimingStructure parameters */ + /** Set tmppmem value according to EMMC_CommonSpaceTimingStructure parameters */ tmppmem = (uint32_t)emmcNANDConfig->commonSpaceTimingStruct->setupTime | (emmcNANDConfig->commonSpaceTimingStruct->waitSetupTime << 8) | (emmcNANDConfig->commonSpaceTimingStruct->holdSetupTime << 16) | (emmcNANDConfig->commonSpaceTimingStruct->HiZSetupTime << 24); - /* Set tmppatt value according to EMMC_AttributeSpaceTimingStructure parameters */ + /** Set tmppatt value according to EMMC_AttributeSpaceTimingStructure parameters */ tmppatt = (uint32_t)emmcNANDConfig->attributeSpaceTimingStruct->setupTime | (emmcNANDConfig->attributeSpaceTimingStruct->waitSetupTime << 8) | (emmcNANDConfig->attributeSpaceTimingStruct->holdSetupTime << 16) | (emmcNANDConfig->attributeSpaceTimingStruct->HiZSetupTime << 24); - if(emmcNANDConfig->bank == EMMC_BANK2_NAND) + if (emmcNANDConfig->bank == EMMC_BANK2_NAND) { - /* EMMC_BANK2_NAND registers configuration */ + /** EMMC_BANK2_NAND registers configuration */ EMMC_Bank2->CTRL2 = tmppcr; EMMC_Bank2->CMSTIM2 = tmppmem; EMMC_Bank2->AMSTIM2 = tmppatt; } else { - /* EMMC_BANK3_NAND registers configuration */ + /** EMMC_BANK3_NAND registers configuration */ EMMC_Bank3->CTRL3 = tmppcr; EMMC_Bank3->CMSTIM3 = tmppmem; EMMC_Bank3->AMSTIM3 = tmppatt; @@ -211,30 +225,30 @@ void EMMC_ConfigNAND(EMMC_NANDConfig_T* emmcNANDConfig) * * @retval None */ -void EMMC_ConfigPCCard(EMMC_PCCARDConfig_T* emmcPCCardConfig) +void EMMC_ConfigPCCard(EMMC_PCCARDConfig_T *emmcPCCardConfig) { - /* Set the PCR4 register value according to EMMC_PCCARDInitStruct parameters */ + /** Set the PCR4 register value according to EMMC_PCCARDInitStruct parameters */ EMMC_Bank4->CTRL4 = (uint32_t)emmcPCCardConfig->waitFeature | EMMC_MEMORY_DATA_WIDTH_16BIT | - (emmcPCCardConfig->TCLRSetupTime << 9) | - (emmcPCCardConfig->TARSetupTime << 13); + (emmcPCCardConfig->TCLRSetupTime << 9) | + (emmcPCCardConfig->TARSetupTime << 13); - /* Set PMEM4 register value according to EMMC_CommonSpaceTimingStructure parameters */ + /** Set PMEM4 register value according to EMMC_CommonSpaceTimingStructure parameters */ EMMC_Bank4->CMSTIM4 = (uint32_t)emmcPCCardConfig->commonSpaceTimingStruct->setupTime | - (emmcPCCardConfig->commonSpaceTimingStruct->waitSetupTime << 8) | - (emmcPCCardConfig->commonSpaceTimingStruct->holdSetupTime << 16) | - (emmcPCCardConfig->commonSpaceTimingStruct->HiZSetupTime << 24); + (emmcPCCardConfig->commonSpaceTimingStruct->waitSetupTime << 8) | + (emmcPCCardConfig->commonSpaceTimingStruct->holdSetupTime << 16) | + (emmcPCCardConfig->commonSpaceTimingStruct->HiZSetupTime << 24); - /* Set PATT4 register value according to EMMC_AttributeSpaceTimingStructure parameters */ + /** Set PATT4 register value according to EMMC_AttributeSpaceTimingStructure parameters */ EMMC_Bank4->AMSTIM4 = (uint32_t)emmcPCCardConfig->attributeSpaceTimingStruct->setupTime | - (emmcPCCardConfig->attributeSpaceTimingStruct->waitSetupTime << 8) | - (emmcPCCardConfig->attributeSpaceTimingStruct->holdSetupTime << 16) | - (emmcPCCardConfig->attributeSpaceTimingStruct->HiZSetupTime << 24); + (emmcPCCardConfig->attributeSpaceTimingStruct->waitSetupTime << 8) | + (emmcPCCardConfig->attributeSpaceTimingStruct->holdSetupTime << 16) | + (emmcPCCardConfig->attributeSpaceTimingStruct->HiZSetupTime << 24); - /* Set PIO4 register value according to EMMC_IOSpaceTimingStructure parameters */ + /** Set PIO4 register value according to EMMC_IOSpaceTimingStructure parameters */ EMMC_Bank4->IOSTIM4 = (uint32_t)emmcPCCardConfig->IOSpaceTimingStruct->setupTime | - (emmcPCCardConfig->IOSpaceTimingStruct->waitSetupTime << 8) | - (emmcPCCardConfig->IOSpaceTimingStruct->holdSetupTime << 16) | - (emmcPCCardConfig->IOSpaceTimingStruct->HiZSetupTime << 24); + (emmcPCCardConfig->IOSpaceTimingStruct->waitSetupTime << 8) | + (emmcPCCardConfig->IOSpaceTimingStruct->holdSetupTime << 16) | + (emmcPCCardConfig->IOSpaceTimingStruct->HiZSetupTime << 24); } /*! @@ -244,9 +258,9 @@ void EMMC_ConfigPCCard(EMMC_PCCARDConfig_T* emmcPCCardConfig) * * @retval None */ -void EMMC_ConfigNORSRAMStructInit(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig) +void EMMC_ConfigNORSRAMStructInit(EMMC_NORSRAMConfig_T *emmcNORSRAMConfig) { - /* Reset NOR/SRAM Init structure parameters values */ + /** Reset NOR/SRAM Init structure parameters values */ emmcNORSRAMConfig->bank = EMMC_BANK1_NORSRAM_1; emmcNORSRAMConfig->dataAddressMux = EMMC_DATA_ADDRESS_MUX_ENABLE; emmcNORSRAMConfig->memoryType = EMMC_MEMORY_TYPE_SRAM; @@ -284,9 +298,9 @@ void EMMC_ConfigNORSRAMStructInit(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig) * * @retval None */ -void EMMC_ConfigNANDStructInit(EMMC_NANDConfig_T* emmcNANDConfig) +void EMMC_ConfigNANDStructInit(EMMC_NANDConfig_T *emmcNANDConfig) { - /* Reset NAND Init structure parameters values */ + /** Reset NAND Init structure parameters values */ emmcNANDConfig->bank = EMMC_BANK2_NAND; emmcNANDConfig->waitFeature = EMMC_WAIT_FEATURE_DISABLE; emmcNANDConfig->memoryDataWidth = EMMC_MEMORY_DATA_WIDTH_8BIT; @@ -311,9 +325,9 @@ void EMMC_ConfigNANDStructInit(EMMC_NANDConfig_T* emmcNANDConfig) * * @retval None */ -void EMMC_ConfigPCCardStructInit(EMMC_PCCARDConfig_T* emmcPCCardConfig) +void EMMC_ConfigPCCardStructInit(EMMC_PCCARDConfig_T *emmcPCCardConfig) { - /* Reset PCCARD Init structure parameters values */ + /** Reset PCCARD Init structure parameters values */ emmcPCCardConfig->waitFeature = EMMC_WAIT_FEATURE_DISABLE; emmcPCCardConfig->TCLRSetupTime = 0x0; emmcPCCardConfig->TARSetupTime = 0x0; @@ -377,7 +391,7 @@ void EMMC_DisableNORSRAM(EMMC_BANK1_NORSRAM_T bank) */ void EMMC_EnableNAND(EMMC_BANK_NAND_T bank) { - if(bank == EMMC_BANK2_NAND) + if (bank == EMMC_BANK2_NAND) { EMMC_Bank2->CTRL2_B.MBKEN = BIT_SET; } @@ -399,7 +413,7 @@ void EMMC_EnableNAND(EMMC_BANK_NAND_T bank) */ void EMMC_DisableNAND(EMMC_BANK_NAND_T bank) { - if(bank == EMMC_BANK2_NAND) + if (bank == EMMC_BANK2_NAND) { EMMC_Bank2->CTRL2_B.MBKEN = BIT_RESET; } @@ -445,7 +459,7 @@ void EMMC_DisablePCCARD(void) */ void EMMC_EnableNANDECC(EMMC_BANK_NAND_T bank) { - if(bank == EMMC_BANK2_NAND) + if (bank == EMMC_BANK2_NAND) { EMMC_Bank2->CTRL2 |= 0x00000040; } @@ -465,11 +479,10 @@ void EMMC_EnableNANDECC(EMMC_BANK_NAND_T bank) * * @retval None * - * @note */ void EMMC_DisableNANDECC(EMMC_BANK_NAND_T bank) { - if(bank == EMMC_BANK2_NAND) + if (bank == EMMC_BANK2_NAND) { EMMC_Bank2->CTRL2 &= 0x000FFFBF; } @@ -493,7 +506,7 @@ uint32_t EMMC_ReadECC(EMMC_BANK_NAND_T bank) { uint32_t eccval = 0x00000000; - if(bank == EMMC_BANK2_NAND) + if (bank == EMMC_BANK2_NAND) { eccval = EMMC_Bank2->ECCRS2; } @@ -523,11 +536,11 @@ uint32_t EMMC_ReadECC(EMMC_BANK_NAND_T bank) */ void EMMC_EnableInterrupt(EMMC_BANK_NAND_T bank, uint32_t interrupt) { - if(bank == EMMC_BANK2_NAND) + if (bank == EMMC_BANK2_NAND) { EMMC_Bank2->STSINT2 |= interrupt; } - else if(bank == EMMC_BANK3_NAND) + else if (bank == EMMC_BANK3_NAND) { EMMC_Bank3->STSINT3 |= interrupt; } @@ -556,11 +569,11 @@ void EMMC_EnableInterrupt(EMMC_BANK_NAND_T bank, uint32_t interrupt) */ void EMMC_DisableInterrupt(EMMC_BANK_NAND_T bank, uint32_t interrupt) { - if(bank == EMMC_BANK2_NAND) + if (bank == EMMC_BANK2_NAND) { EMMC_Bank2->STSINT2 &= ~interrupt; } - else if(bank == EMMC_BANK3_NAND) + else if (bank == EMMC_BANK3_NAND) { EMMC_Bank3->STSINT3 &= ~interrupt; } @@ -588,17 +601,16 @@ void EMMC_DisableInterrupt(EMMC_BANK_NAND_T bank, uint32_t interrupt) * * @retval SET or RESET * - * @note */ uint8_t EMMC_ReadStatusFlag(EMMC_BANK_NAND_T bank, EMMC_FLAG_T flag) { uint32_t tmpsr = 0x00000000; - if(bank == EMMC_BANK2_NAND) + if (bank == EMMC_BANK2_NAND) { tmpsr = EMMC_Bank2->STSINT2; } - else if(bank == EMMC_BANK3_NAND) + else if (bank == EMMC_BANK3_NAND) { tmpsr = EMMC_Bank3->STSINT3; } @@ -606,8 +618,8 @@ uint8_t EMMC_ReadStatusFlag(EMMC_BANK_NAND_T bank, EMMC_FLAG_T flag) { tmpsr = EMMC_Bank4->STSINT4; } - /* Get the flag status */ - if((tmpsr & flag) != RESET) + /** Get the flag status */ + if ((tmpsr & flag) != RESET) { return SET; } @@ -636,11 +648,11 @@ uint8_t EMMC_ReadStatusFlag(EMMC_BANK_NAND_T bank, EMMC_FLAG_T flag) */ void EMMC_ClearStatusFlag(EMMC_BANK_NAND_T bank, uint32_t flag) { - if(bank == EMMC_BANK2_NAND) + if (bank == EMMC_BANK2_NAND) { EMMC_Bank2->STSINT2 &= ~flag; } - else if(bank == EMMC_BANK3_NAND) + else if (bank == EMMC_BANK3_NAND) { EMMC_Bank3->STSINT3 &= ~flag; } @@ -671,11 +683,11 @@ uint8_t EMMC_ReadIntFlag(EMMC_BANK_NAND_T bank, EMMC_INT_T flag) { uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; - if(bank == EMMC_BANK2_NAND) + if (bank == EMMC_BANK2_NAND) { tmpsr = EMMC_Bank2->STSINT2; } - else if(bank == EMMC_BANK3_NAND) + else if (bank == EMMC_BANK3_NAND) { tmpsr = EMMC_Bank3->STSINT3; } @@ -687,7 +699,7 @@ uint8_t EMMC_ReadIntFlag(EMMC_BANK_NAND_T bank, EMMC_INT_T flag) itstatus = tmpsr & flag; itenable = tmpsr & (flag >> 3); - if((itstatus != RESET) && (itenable != RESET)) + if ((itstatus != RESET) && (itenable != RESET)) { return SET; } @@ -716,11 +728,11 @@ uint8_t EMMC_ReadIntFlag(EMMC_BANK_NAND_T bank, EMMC_INT_T flag) */ void EMMC_ClearIntFlag(EMMC_BANK_NAND_T bank, uint32_t flag) { - if(bank == EMMC_BANK2_NAND) + if (bank == EMMC_BANK2_NAND) { EMMC_Bank2->STSINT2 &= ~(flag >> 3); } - else if(bank == EMMC_BANK3_NAND) + else if (bank == EMMC_BANK3_NAND) { EMMC_Bank3->STSINT3 &= ~(flag >> 3); } diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_fmc.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_fmc.c index 63f8bf81ae..fc9c2670c6 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_fmc.c +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_fmc.c @@ -1,12 +1,26 @@ /*! - * @file apm32f10x_fmc.c + * @file apm32f10x_fmc.c * - * @brief This file provides all the FMC firmware functions + * @brief This file provides all the FMC firmware functions * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ #include "apm32f10x_fmc.h" @@ -126,7 +140,7 @@ FMC_STATUS_T FMC_ErasePage(uint32_t pageAddr) FMC_STATUS_T status = FMC_STATUS_COMPLETE; status = FMC_WaitForLastOperation(0x000B0000); - if(status == FMC_STATUS_COMPLETE) + if (status == FMC_STATUS_COMPLETE) { FMC->CTRL2_B.PAGEERA = BIT_SET; FMC->ADDR = pageAddr; @@ -154,7 +168,7 @@ FMC_STATUS_T FMC_EraseAllPage(void) FMC_STATUS_T status = FMC_STATUS_COMPLETE; status = FMC_WaitForLastOperation(0x000B0000); - if(status == FMC_STATUS_COMPLETE) + if (status == FMC_STATUS_COMPLETE) { FMC->CTRL2_B.MASSERA = BIT_SET; FMC->CTRL2_B.STA = BIT_SET; @@ -181,12 +195,12 @@ FMC_STATUS_T FMC_EraseOptionBytes(void) uint16_t rdtemp = 0x00A5; FMC_STATUS_T status = FMC_STATUS_COMPLETE; - if(FMC_GetReadProtectionStatus() != RESET) + if (FMC_GetReadProtectionStatus() != RESET) { rdtemp = 0x00; } status = FMC_WaitForLastOperation(0x000B0000); - if(status == FMC_STATUS_COMPLETE) + if (status == FMC_STATUS_COMPLETE) { FMC->OBKEY = 0x45670123; FMC->OBKEY = 0xCDEF89AB; @@ -196,18 +210,18 @@ FMC_STATUS_T FMC_EraseOptionBytes(void) status = FMC_WaitForLastOperation(0x000B0000); - if(status == FMC_STATUS_COMPLETE) + if (status == FMC_STATUS_COMPLETE) { FMC->CTRL2_B.OBE = BIT_RESET; FMC->CTRL2_B.OBP = BIT_SET; OB->RDP = rdtemp; status = FMC_WaitForLastOperation(0x000B0000); - if(status != FMC_STATUS_TIMEOUT) + if (status != FMC_STATUS_TIMEOUT) { FMC->CTRL2_B.OBP = BIT_RESET; } } - else if(status != FMC_STATUS_TIMEOUT) + else if (status != FMC_STATUS_TIMEOUT) { FMC->CTRL2_B.OBP = BIT_RESET; } @@ -233,13 +247,13 @@ FMC_STATUS_T FMC_ProgramWord(uint32_t address, uint32_t data) FMC_STATUS_T status = FMC_STATUS_COMPLETE; __IOM uint32_t temp = 0; - #ifdef APM32F10X_HD - __set_PRIMASK(1); - #endif +#ifdef APM32F10X_HD + __set_PRIMASK(1); +#endif status = FMC_WaitForLastOperation(0x000B0000); - if(status == FMC_STATUS_COMPLETE) + if (status == FMC_STATUS_COMPLETE) { FMC->CTRL2_B.PG = BIT_SET; @@ -247,11 +261,11 @@ FMC_STATUS_T FMC_ProgramWord(uint32_t address, uint32_t data) status = FMC_WaitForLastOperation(0x000B0000); - if(status == FMC_STATUS_COMPLETE) + if (status == FMC_STATUS_COMPLETE) { temp = address + 2; - *(__IOM uint16_t*) temp = data >> 16; + *(__IOM uint16_t *) temp = data >> 16; status = FMC_WaitForLastOperation(0x000B0000); FMC->CTRL2_B.PG = BIT_RESET; @@ -262,9 +276,9 @@ FMC_STATUS_T FMC_ProgramWord(uint32_t address, uint32_t data) } } - #ifdef APM32F10X_HD - __set_PRIMASK(0); - #endif +#ifdef APM32F10X_HD + __set_PRIMASK(0); +#endif return status; } @@ -286,13 +300,13 @@ FMC_STATUS_T FMC_ProgramHalfWord(uint32_t address, uint16_t data) { FMC_STATUS_T status = FMC_STATUS_COMPLETE; - #ifdef APM32F10X_HD - __set_PRIMASK(1); - #endif +#ifdef APM32F10X_HD + __set_PRIMASK(1); +#endif status = FMC_WaitForLastOperation(0x000B0000); - if(status == FMC_STATUS_COMPLETE) + if (status == FMC_STATUS_COMPLETE) { FMC->CTRL2_B.PG = BIT_SET; *(__IOM uint16_t *)address = data; @@ -300,9 +314,9 @@ FMC_STATUS_T FMC_ProgramHalfWord(uint32_t address, uint16_t data) FMC->CTRL2_B.PG = BIT_RESET; } - #ifdef APM32F10X_HD - __set_PRIMASK(0); - #endif +#ifdef APM32F10X_HD + __set_PRIMASK(0); +#endif return status; } @@ -326,7 +340,7 @@ FMC_STATUS_T FMC_ProgramOptionByteData(uint32_t address, uint8_t data) status = FMC_WaitForLastOperation(0x000B0000); - if(status == FMC_STATUS_COMPLETE) + if (status == FMC_STATUS_COMPLETE) { FMC->OBKEY = 0x45670123; FMC->OBKEY = 0xCDEF89AB; @@ -334,7 +348,7 @@ FMC_STATUS_T FMC_ProgramOptionByteData(uint32_t address, uint8_t data) FMC->CTRL2_B.OBP = BIT_SET; *(__IOM uint16_t *)address = data; status = FMC_WaitForLastOperation(0x000B0000); - if(status == FMC_STATUS_TIMEOUT) + if (status == FMC_STATUS_TIMEOUT) { FMC->CTRL2_B.OBP = BIT_RESET; } @@ -347,11 +361,11 @@ FMC_STATUS_T FMC_ProgramOptionByteData(uint32_t address, uint8_t data) * * @param page:the address of the pages to be write protection * This parameter can be any combination of the following values: - * for APM32F10X_LD + * for APM32F10X_LD ： * @arg FLASH_WRP_PAGE_0_3 to FLASH_WRP_PAGE_28_31 - * for APM32F10X_MD + * for APM32F10X_MD ： * @arg FLASH_WRP_PAGE_0_3 to FLASH_WRP_PAGE_124_127 - * for APM32F10X_HD + * for APM32F10X_HD ： * @arg FLASH_WRP_PAGE_0_1 to FLASH_WRP_PAGE_60_61 or FLASH_WRP_PAGE_62_127 * @arg FMC_WRP_PAGE_ALL * @@ -374,34 +388,34 @@ FMC_STATUS_T FMC_EnableWriteProtection(uint32_t page) status = FMC_WaitForLastOperation(0x000B0000); - if(status == FMC_STATUS_COMPLETE) + if (status == FMC_STATUS_COMPLETE) { FMC->OBKEY = 0x45670123; FMC->OBKEY = 0xCDEF89AB; FMC->CTRL2_B.OBP = BIT_SET; - if(WPP0_Data != 0xFF) + if (WPP0_Data != 0xFF) { OB->WRP0 = WPP0_Data; status = FMC_WaitForLastOperation(0x000B0000); } - if((status == FMC_STATUS_COMPLETE) && (WPP1_Data != 0xFF)) + if ((status == FMC_STATUS_COMPLETE) && (WPP1_Data != 0xFF)) { OB->WRP1 = WPP1_Data; status = FMC_WaitForLastOperation(0x000B0000); } - if((status == FMC_STATUS_COMPLETE) && (WPP2_Data != 0xFF)) + if ((status == FMC_STATUS_COMPLETE) && (WPP2_Data != 0xFF)) { OB->WRP2 = WPP2_Data; status = FMC_WaitForLastOperation(0x000B0000); } - if((status == FMC_STATUS_COMPLETE) && (WPP3_Data != 0xFF)) + if ((status == FMC_STATUS_COMPLETE) && (WPP3_Data != 0xFF)) { OB->WRP3 = WPP3_Data; status = FMC_WaitForLastOperation(0x000B0000); } - if(status != FMC_STATUS_TIMEOUT) + if (status != FMC_STATUS_TIMEOUT) { FMC->CTRL2_B.OBP = BIT_RESET; } @@ -426,7 +440,7 @@ FMC_STATUS_T FMC_EnableReadOutProtection(void) status = FMC_WaitForLastOperation(0x000B0000); - if(status == FMC_STATUS_COMPLETE) + if (status == FMC_STATUS_COMPLETE) { FMC->OBKEY = 0x45670123; FMC->OBKEY = 0xCDEF89AB; @@ -436,7 +450,7 @@ FMC_STATUS_T FMC_EnableReadOutProtection(void) status = FMC_WaitForLastOperation(0x000B0000); - if(status == FMC_STATUS_COMPLETE) + if (status == FMC_STATUS_COMPLETE) { FMC->CTRL2_B.OBE = BIT_RESET; FMC->CTRL2_B.OBP = BIT_SET; @@ -444,12 +458,12 @@ FMC_STATUS_T FMC_EnableReadOutProtection(void) status = FMC_WaitForLastOperation(0x000B0000); - if(status != FMC_STATUS_TIMEOUT) + if (status != FMC_STATUS_TIMEOUT) { FMC->CTRL2_B.OBP = BIT_RESET; } } - else if(status != FMC_STATUS_TIMEOUT) + else if (status != FMC_STATUS_TIMEOUT) { FMC->CTRL2_B.OBE = BIT_RESET; } @@ -474,7 +488,7 @@ FMC_STATUS_T FMC_DisableReadOutProtection(void) status = FMC_WaitForLastOperation(0x000B0000); - if(status == FMC_STATUS_COMPLETE) + if (status == FMC_STATUS_COMPLETE) { FMC->OBKEY = 0x45670123; FMC->OBKEY = 0xCDEF89AB; @@ -483,7 +497,7 @@ FMC_STATUS_T FMC_DisableReadOutProtection(void) status = FMC_WaitForLastOperation(0x000B0000); - if(status == FMC_STATUS_COMPLETE) + if (status == FMC_STATUS_COMPLETE) { FMC->CTRL2_B.OBE = BIT_RESET; FMC->CTRL2_B.OBP = BIT_SET; @@ -491,12 +505,12 @@ FMC_STATUS_T FMC_DisableReadOutProtection(void) status = FMC_WaitForLastOperation(0x000B0000); - if(status != FMC_STATUS_TIMEOUT) + if (status != FMC_STATUS_TIMEOUT) { FMC->CTRL2_B.OBP = BIT_RESET; } } - else if(status != FMC_STATUS_TIMEOUT) + else if (status != FMC_STATUS_TIMEOUT) { FMC->CTRL2_B.OBE = BIT_RESET; } @@ -515,7 +529,7 @@ FMC_STATUS_T FMC_DisableReadOutProtection(void) * @arg FMC_STATUS_COMPLETE * @arg FMC_STATUS_TIMEOUT */ -FMC_STATUS_T FMC_ConfigUserOptionByte(FMC_UserConfig_T* userConfig) +FMC_STATUS_T FMC_ConfigUserOptionByte(FMC_UserConfig_T *userConfig) { FMC_STATUS_T status = FMC_STATUS_COMPLETE; @@ -524,12 +538,14 @@ FMC_STATUS_T FMC_ConfigUserOptionByte(FMC_UserConfig_T* userConfig) status = FMC_WaitForLastOperation(0x000B0000); - if(status == FMC_STATUS_COMPLETE) + if (status == FMC_STATUS_COMPLETE) { FMC->CTRL2_B.OBP = BIT_SET; - OB->USER = userConfig->iwdtSet | userConfig->stopSet | userConfig->stdbySet | 0xF8; + OB->USER = (uint32_t)userConfig->iwdtSet | \ + (uint32_t)userConfig->stopSet | \ + (uint32_t)userConfig->stdbySet | 0xF8; status = FMC_WaitForLastOperation(0x000B0000); - if(status == FMC_STATUS_TIMEOUT) + if (status == FMC_STATUS_TIMEOUT) { FMC->CTRL2_B.OBP = BIT_RESET; } @@ -572,7 +588,7 @@ uint8_t FMC_GetReadProtectionStatus(void) { uint8_t flagstatus = RESET; - if(FMC->OBCS_B.READPROT != RESET) + if (FMC->OBCS_B.READPROT != RESET) { flagstatus = SET; } @@ -607,7 +623,7 @@ uint8_t FMC_ReadPrefetchBufferStatus(void) */ void FMC_EnableInterrupt(FMC_INT_T interrupt) { - if(interrupt == FMC_INT_ERR) + if (interrupt == FMC_INT_ERR) { FMC->CTRL2_B.ERRIE = ENABLE; } @@ -629,7 +645,7 @@ void FMC_EnableInterrupt(FMC_INT_T interrupt) */ void FMC_DisableInterrupt(FMC_INT_T interrupt) { - if(interrupt == FMC_INT_ERR) + if (interrupt == FMC_INT_ERR) { FMC->CTRL2_B.ERRIE = DISABLE; } @@ -654,11 +670,11 @@ void FMC_DisableInterrupt(FMC_INT_T interrupt) */ uint8_t FMC_ReadStatusFlag(FMC_FLAG_T flag) { - if(flag == FMC_FLAG_OBE) + if (flag == FMC_FLAG_OBE) { return FMC->OBCS_B.OBE; } - else if((FMC->STS & flag ) != RESET) + else if ((FMC->STS & flag) != RESET) { return SET; } @@ -676,9 +692,8 @@ uint8_t FMC_ReadStatusFlag(FMC_FLAG_T flag) * * @retval None * - * @note */ -void FMC_ClearStatusFlag(FMC_FLAG_T flag) +void FMC_ClearStatusFlag(uint32_t flag) { FMC->STS = flag; } @@ -698,15 +713,15 @@ FMC_STATUS_T FMC_ReadStatus(void) { FMC_STATUS_T status = FMC_STATUS_COMPLETE; - if(FMC->STS_B.BUSYF == BIT_SET) + if (FMC->STS_B.BUSYF == BIT_SET) { status = FMC_STATUS_BUSY; } - else if(FMC->STS_B.PEF == BIT_SET) + else if (FMC->STS_B.PEF == BIT_SET) { status = FMC_STATUS_ERROR_PG; } - else if(FMC->STS_B.WPEF == BIT_SET) + else if (FMC->STS_B.WPEF == BIT_SET) { status = FMC_STATUS_ERROR_WRP; } @@ -736,12 +751,12 @@ FMC_STATUS_T FMC_WaitForLastOperation(uint32_t timeOut) status = FMC_ReadStatus(); /** Wait for a Flash operation to complete or a TIMEOUT to occur */ - while((status == FMC_STATUS_BUSY) && (timeOut !=0)) + while ((status == FMC_STATUS_BUSY) && (timeOut != 0)) { status = FMC_ReadStatus(); timeOut--; } - if(timeOut == 0x00) + if (timeOut == 0x00) { status = FMC_STATUS_TIMEOUT; } diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_gpio.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_gpio.c index a3c1518eb5..e4399deb9e 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_gpio.c +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_gpio.c @@ -1,12 +1,26 @@ /*! - * @file apm32f10x_gpio.c + * @file apm32f10x_gpio.c * - * @brief This file provides all the GPIO firmware functions + * @brief This file provides all the GPIO firmware functions * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ #include "apm32f10x_gpio.h" @@ -32,7 +46,7 @@ * * @retval None */ -void GPIO_Reset(GPIO_T* port) +void GPIO_Reset(GPIO_T *port) { RCM_APB2_PERIPH_T APB2Periph; @@ -92,7 +106,7 @@ void GPIO_AFIOReset(void) * * @retval None */ -void GPIO_Config(GPIO_T* port, GPIO_Config_T* gpioConfig) +void GPIO_Config(GPIO_T *port, GPIO_Config_T *gpioConfig) { uint8_t i; uint32_t mode; @@ -167,10 +181,10 @@ void GPIO_Config(GPIO_T* port, GPIO_Config_T* gpioConfig) * * @retval None */ -void GPIO_StructInit(GPIO_Config_T* gpioConfig) +void GPIO_ConfigStructInit(GPIO_Config_T *gpioConfig) { gpioConfig->pin = GPIO_PIN_ALL; - gpioConfig->speed = GPIO_SPEED_2MHz; + gpioConfig->speed = GPIO_SPEED_20MHz; gpioConfig->mode = GPIO_MODE_IN_FLOATING; } @@ -185,7 +199,7 @@ void GPIO_StructInit(GPIO_Config_T* gpioConfig) * * @retval The input port pin value */ -uint8_t GPIO_ReadInputBit(GPIO_T* port, uint16_t pin) +uint8_t GPIO_ReadInputBit(GPIO_T *port, uint16_t pin) { uint8_t ret; @@ -202,7 +216,7 @@ uint8_t GPIO_ReadInputBit(GPIO_T* port, uint16_t pin) * * @retval GPIO input data port value */ -uint16_t GPIO_ReadInputPort(GPIO_T* port) +uint16_t GPIO_ReadInputPort(GPIO_T *port) { return ((uint16_t)port->IDATA); } @@ -218,7 +232,7 @@ uint16_t GPIO_ReadInputPort(GPIO_T* port) * * @retval The output port pin value */ -uint8_t GPIO_ReadOutputBit(GPIO_T* port, uint16_t pin) +uint8_t GPIO_ReadOutputBit(GPIO_T *port, uint16_t pin) { uint8_t ret; @@ -236,7 +250,7 @@ uint8_t GPIO_ReadOutputBit(GPIO_T* port, uint16_t pin) * * @retval output data port value */ -uint16_t GPIO_ReadOutputPort(GPIO_T* port) +uint16_t GPIO_ReadOutputPort(GPIO_T *port) { return ((uint16_t)port->ODATA); } @@ -252,7 +266,7 @@ uint16_t GPIO_ReadOutputPort(GPIO_T* port) * * @retval None */ -void GPIO_SetBits(GPIO_T* port, uint16_t pin) +void GPIO_SetBit(GPIO_T *port, uint16_t pin) { port->BSC = (uint32_t)pin; } @@ -268,7 +282,7 @@ void GPIO_SetBits(GPIO_T* port, uint16_t pin) * * @retval None */ -void GPIO_ResetBits(GPIO_T* port, uint16_t pin) +void GPIO_ResetBit(GPIO_T *port, uint16_t pin) { port->BC = (uint32_t)pin; } @@ -290,7 +304,7 @@ void GPIO_ResetBits(GPIO_T* port, uint16_t pin) * * @retval None */ -void GPIO_WriteBitValue(GPIO_T* port, uint16_t pin, uint8_t bitVal) +void GPIO_WriteBitValue(GPIO_T *port, uint16_t pin, uint8_t bitVal) { if (bitVal != BIT_RESET) { @@ -312,7 +326,7 @@ void GPIO_WriteBitValue(GPIO_T* port, uint16_t pin, uint8_t bitVal) * * @retval None */ -void GPIO_WriteOutputPort(GPIO_T* port, uint16_t portValue) +void GPIO_WriteOutputPort(GPIO_T *port, uint16_t portValue) { port->ODATA = (uint32_t)portValue; } @@ -328,20 +342,20 @@ void GPIO_WriteOutputPort(GPIO_T* port, uint16_t portValue) * * @retval None */ -void GPIO_ConfigPinLock(GPIO_T* port, uint16_t pin) +void GPIO_ConfigPinLock(GPIO_T *port, uint16_t pin) { uint32_t val = 0x00010000; val |= pin; - /* Set LCKK bit */ + /** Set LCKK bit */ port->LOCK = val ; - /* Reset LCKK bit */ + /** Reset LCKK bit */ port->LOCK = pin; - /* Set LCKK bit */ + /** Set LCKK bit */ port->LOCK = val; - /* Read LCKK bit*/ + /** Read LCKK bit*/ val = port->LOCK; - /* Read LCKK bit*/ + /** Read LCKK bit*/ val = port->LOCK; } @@ -457,7 +471,7 @@ void GPIO_ConfigPinRemap(GPIO_REMAP_T remap) regVal = AFIO->REMAP1; } - if(remap >> 8 == 0x18) + if (remap >> 8 == 0x18) { regVal &= 0xF0FFFFFF; AFIO->REMAP1 &= 0xF0FFFFFF; @@ -500,28 +514,28 @@ void GPIO_ConfigEINTLine(GPIO_PORT_SOURCE_T portSource, GPIO_PIN_SOURCE_T pinSou if (pinSource <= GPIO_PIN_SOURCE_3) { shift = pinSource << 2; - AFIO->EINTSEL1 &= (uint32_t )~(0x0f << shift); + AFIO->EINTSEL1 &= (uint32_t)~(0x0f << shift); AFIO->EINTSEL1 |= portSource << shift; } else if (pinSource <= GPIO_PIN_SOURCE_7) { shift = (pinSource - GPIO_PIN_SOURCE_4) << 2; - AFIO->EINTSEL2 &= (uint32_t )~(0x0f << shift); + AFIO->EINTSEL2 &= (uint32_t)~(0x0f << shift); AFIO->EINTSEL2 |= portSource << shift; } else if (pinSource <= GPIO_PIN_SOURCE_11) { shift = (pinSource - GPIO_PIN_SOURCE_8) << 2; - AFIO->EINTSEL3 &= (uint32_t )~(0x0f << shift); + AFIO->EINTSEL3 &= (uint32_t)~(0x0f << shift); AFIO->EINTSEL3 |= portSource << shift; } else if (pinSource <= GPIO_PIN_SOURCE_15) { shift = (pinSource - GPIO_PIN_SOURCE_12) << 2; - AFIO->EINTSEL4 &= (uint32_t )~(0x0f << shift); + AFIO->EINTSEL4 &= (uint32_t)~(0x0f << shift); AFIO->EINTSEL4 |= portSource << shift; } } diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_i2c.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_i2c.c index 319866723b..f03564c023 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_i2c.c +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_i2c.c @@ -1,12 +1,26 @@ /*! - * @file apm32f10x_i2c.c + * @file apm32f10x_i2c.c * - * @brief This file provides all the I2C firmware functions + * @brief This file provides all the I2C firmware functions * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ #include "apm32f10x_i2c.h" @@ -31,9 +45,9 @@ * * @retval None */ -void I2C_Reset(I2C_T* i2c) +void I2C_Reset(I2C_T *i2c) { - if(i2c == I2C1) + if (i2c == I2C1) { RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_I2C1); RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_I2C1); @@ -54,7 +68,7 @@ void I2C_Reset(I2C_T* i2c) * * @retval None */ -void I2C_Config(I2C_T* i2c, I2C_Config_T* i2cConfig) +void I2C_Config(I2C_T *i2c, I2C_Config_T *i2cConfig) { uint16_t tmpreg = 0, freqrange = 0; uint32_t PCLK1 = 8000000, PCLK2 = 0; @@ -65,15 +79,15 @@ void I2C_Config(I2C_T* i2c, I2C_Config_T* i2cConfig) /** I2C CTRL2 Configuration */ RCM_ReadPCLKFreq(&PCLK1, &PCLK2); freqrange = PCLK1 / 1000000; - i2c->CTRL2_B.CLKFCFG= freqrange; + i2c->CTRL2_B.CLKFCFG = freqrange; /** I2C CLKCTRL Configuration */ i2c->CTRL1_B.I2CEN = BIT_RESET; - if(i2cConfig->clockSpeed <= 100000) + if (i2cConfig->clockSpeed <= 100000) { result = (PCLK1 / (i2cConfig->clockSpeed << 1)); - if(result < 0x04) + if (result < 0x04) { result = 0x04; } @@ -83,7 +97,7 @@ void I2C_Config(I2C_T* i2c, I2C_Config_T* i2cConfig) /** Configure speed in fast mode */ else { - if(i2cConfig->dutyCycle == I2C_DUTYCYCLE_2) + if (i2cConfig->dutyCycle == I2C_DUTYCYCLE_2) { result = (PCLK1 / (i2cConfig->clockSpeed * 3)); } @@ -93,7 +107,7 @@ void I2C_Config(I2C_T* i2c, I2C_Config_T* i2cConfig) result |= I2C_DUTYCYCLE_16_9; } - if((result & 0x0FFF) == 0) + if ((result & 0x0FFF) == 0) { result |= 0x0001; } @@ -122,7 +136,7 @@ void I2C_Config(I2C_T* i2c, I2C_Config_T* i2cConfig) * * @retval None */ -void I2C_ConfigStructInit(I2C_Config_T* i2cConfig) +void I2C_ConfigStructInit(I2C_Config_T *i2cConfig) { i2cConfig->clockSpeed = 5000; i2cConfig->mode = I2C_MODE_I2C; @@ -139,7 +153,7 @@ void I2C_ConfigStructInit(I2C_Config_T* i2cConfig) * * @retval None */ -void I2C_Enable(I2C_T* i2c) +void I2C_Enable(I2C_T *i2c) { i2c->CTRL1_B.I2CEN = ENABLE; } @@ -151,7 +165,7 @@ void I2C_Enable(I2C_T* i2c) * * @retval None */ -void I2C_Disable(I2C_T* i2c) +void I2C_Disable(I2C_T *i2c) { i2c->CTRL1_B.I2CEN = DISABLE; } @@ -163,7 +177,7 @@ void I2C_Disable(I2C_T* i2c) * * @retval None */ -void I2C_EnableGenerateStart(I2C_T* i2c) +void I2C_EnableGenerateStart(I2C_T *i2c) { i2c->CTRL1_B.START = BIT_SET; } @@ -175,7 +189,7 @@ void I2C_EnableGenerateStart(I2C_T* i2c) * * @retval None */ -void I2C_DisableGenerateStart(I2C_T* i2c) +void I2C_DisableGenerateStart(I2C_T *i2c) { i2c->CTRL1_B.START = BIT_RESET; } @@ -187,7 +201,7 @@ void I2C_DisableGenerateStart(I2C_T* i2c) * * @retval None */ -void I2C_EnableGenerateStop(I2C_T* i2c) +void I2C_EnableGenerateStop(I2C_T *i2c) { i2c->CTRL1_B.STOP = BIT_SET; } @@ -199,7 +213,7 @@ void I2C_EnableGenerateStop(I2C_T* i2c) * * @retval None */ -void I2C_DisableGenerateStop(I2C_T* i2c) +void I2C_DisableGenerateStop(I2C_T *i2c) { i2c->CTRL1_B.STOP = BIT_RESET; } @@ -211,7 +225,7 @@ void I2C_DisableGenerateStop(I2C_T* i2c) * * @retval None */ -void I2C_EnableAcknowledge(I2C_T* i2c) +void I2C_EnableAcknowledge(I2C_T *i2c) { i2c->CTRL1_B.ACKEN = ENABLE; } @@ -223,7 +237,7 @@ void I2C_EnableAcknowledge(I2C_T* i2c) * * @retval None */ -void I2C_DisableAcknowledge(I2C_T* i2c) +void I2C_DisableAcknowledge(I2C_T *i2c) { i2c->CTRL1_B.ACKEN = DISABLE; } @@ -237,7 +251,7 @@ void I2C_DisableAcknowledge(I2C_T* i2c) * * @retval None */ -void I2C_ConfigOwnAddress2(I2C_T* i2c, uint8_t address) +void I2C_ConfigOwnAddress2(I2C_T *i2c, uint8_t address) { i2c->SADDR2_B.ADDR2 = address; } @@ -249,7 +263,7 @@ void I2C_ConfigOwnAddress2(I2C_T* i2c, uint8_t address) * * @retval None */ -void I2C_EnableDualAddress(I2C_T* i2c) +void I2C_EnableDualAddress(I2C_T *i2c) { i2c->SADDR2_B.ADDRNUM = ENABLE; } @@ -261,7 +275,7 @@ void I2C_EnableDualAddress(I2C_T* i2c) * * @retval None */ -void I2C_DisableDualAddress(I2C_T* i2c) +void I2C_DisableDualAddress(I2C_T *i2c) { i2c->SADDR2_B.ADDRNUM = DISABLE; } @@ -273,7 +287,7 @@ void I2C_DisableDualAddress(I2C_T* i2c) * * @retval None */ -void I2C_EnableGeneralCall(I2C_T* i2c) +void I2C_EnableGeneralCall(I2C_T *i2c) { i2c->CTRL1_B.SRBEN = ENABLE; } @@ -285,7 +299,7 @@ void I2C_EnableGeneralCall(I2C_T* i2c) * * @retval None */ -void I2C_DisableGeneralCall(I2C_T* i2c) +void I2C_DisableGeneralCall(I2C_T *i2c) { i2c->CTRL1_B.SRBEN = DISABLE; } @@ -299,7 +313,7 @@ void I2C_DisableGeneralCall(I2C_T* i2c) * * @retval None */ -void I2C_TxData(I2C_T* i2c, uint8_t data) +void I2C_TxData(I2C_T *i2c, uint8_t data) { i2c->DATA_B.DATA = data; } @@ -311,7 +325,7 @@ void I2C_TxData(I2C_T* i2c, uint8_t data) * * @retval received data */ -uint8_t I2C_RxData(I2C_T* i2c) +uint8_t I2C_RxData(I2C_T *i2c) { return i2c->DATA_B.DATA; } @@ -329,9 +343,9 @@ uint8_t I2C_RxData(I2C_T* i2c) * @arg I2C_DIRECTION_RX: Receiver mode * @retval None */ -void I2C_Tx7BitAddress(I2C_T* i2c, uint8_t address, I2C_DIRECTION_T direction) +void I2C_Tx7BitAddress(I2C_T *i2c, uint8_t address, I2C_DIRECTION_T direction) { - if(direction != I2C_DIRECTION_TX) + if (direction != I2C_DIRECTION_TX) { i2c->DATA_B.DATA = address | 0x0001; } @@ -361,7 +375,7 @@ void I2C_Tx7BitAddress(I2C_T* i2c, uint8_t address, I2C_DIRECTION_T direction) * * @retval The value of the read register */ -uint16_t I2C_ReadRegister(I2C_T* i2c, I2C_REGISTER_T i2cRegister) +uint16_t I2C_ReadRegister(I2C_T *i2c, I2C_REGISTER_T i2cRegister) { switch (i2cRegister) { @@ -397,7 +411,7 @@ uint16_t I2C_ReadRegister(I2C_T* i2c, I2C_REGISTER_T i2cRegister) * * @retval None */ -void I2C_EnableSoftwareReset(I2C_T* i2c) +void I2C_EnableSoftwareReset(I2C_T *i2c) { i2c->CTRL1_B.SWRST = ENABLE; } @@ -409,7 +423,7 @@ void I2C_EnableSoftwareReset(I2C_T* i2c) * * @retval None */ -void I2C_DisableSoftwareReset(I2C_T* i2c) +void I2C_DisableSoftwareReset(I2C_T *i2c) { i2c->CTRL1_B.SWRST = DISABLE; } @@ -423,9 +437,9 @@ void I2C_DisableSoftwareReset(I2C_T* i2c) * * @retval None */ -void I2C_ConfigNACKPosition(I2C_T* i2c, I2C_NACK_POSITION_T NACKPosition) +void I2C_ConfigNACKPosition(I2C_T *i2c, I2C_NACK_POSITION_T NACKPosition) { - if(NACKPosition == I2C_NACK_POSITION_NEXT) + if (NACKPosition == I2C_NACK_POSITION_NEXT) { i2c->CTRL1_B.ACKPOS = BIT_SET; } @@ -446,9 +460,9 @@ void I2C_ConfigNACKPosition(I2C_T* i2c, I2C_NACK_POSITION_T NACKPosition) * @arg I2C_SMBUSALER_HIGH: SMBus Alert pin high * @retval None */ -void I2C_ConfigSMBusAlert(I2C_T* i2c, I2C_SMBUSALER_T SMBusState) +void I2C_ConfigSMBusAlert(I2C_T *i2c, I2C_SMBUSALER_T SMBusState) { - if(SMBusState == I2C_SMBUSALER_LOW) + if (SMBusState == I2C_SMBUSALER_LOW) { i2c->CTRL1_B.ALERTEN = BIT_SET; } @@ -465,7 +479,7 @@ void I2C_ConfigSMBusAlert(I2C_T* i2c, I2C_SMBUSALER_T SMBusState) * * @retval None */ -void I2C_EnablePECTransmit(I2C_T* i2c) +void I2C_EnablePECTransmit(I2C_T *i2c) { i2c->CTRL1_B.PEC = BIT_SET; } @@ -477,7 +491,7 @@ void I2C_EnablePECTransmit(I2C_T* i2c) * * @retval None */ -void I2C_DisablePECTransmit(I2C_T* i2c) +void I2C_DisablePECTransmit(I2C_T *i2c) { i2c->CTRL1_B.PEC = BIT_RESET; } @@ -493,9 +507,9 @@ void I2C_DisablePECTransmit(I2C_T* i2c) * @arg I2C_PEC_POSITION_CURRENT: indicates that current byte is PEC * @retval None */ -void I2C_ConfigPECPosition(I2C_T* i2c, I2C_PEC_POSITION_T PECPosition) +void I2C_ConfigPECPosition(I2C_T *i2c, I2C_PEC_POSITION_T PECPosition) { - if(PECPosition == I2C_PEC_POSITION_NEXT) + if (PECPosition == I2C_PEC_POSITION_NEXT) { i2c->CTRL1_B.ACKPOS = BIT_SET; } @@ -512,7 +526,7 @@ void I2C_ConfigPECPosition(I2C_T* i2c, I2C_PEC_POSITION_T PECPosition) * * @retval None */ -void I2C_EnablePEC(I2C_T* i2c) +void I2C_EnablePEC(I2C_T *i2c) { i2c->CTRL1_B.PECEN = BIT_SET; } @@ -524,7 +538,7 @@ void I2C_EnablePEC(I2C_T* i2c) * * @retval None */ -void I2C_DisablePEC(I2C_T* i2c) +void I2C_DisablePEC(I2C_T *i2c) { i2c->CTRL1_B.PECEN = BIT_RESET; } @@ -536,7 +550,7 @@ void I2C_DisablePEC(I2C_T* i2c) * * @retval value of PEC */ -uint8_t I2C_ReadPEC(I2C_T* i2c) +uint8_t I2C_ReadPEC(I2C_T *i2c) { return i2c->STS2_B.PECVALUE; } @@ -548,7 +562,7 @@ uint8_t I2C_ReadPEC(I2C_T* i2c) * * @retval None */ -void I2C_EnableARP(I2C_T* i2c) +void I2C_EnableARP(I2C_T *i2c) { i2c->CTRL1_B.ARPEN = BIT_SET; } @@ -560,7 +574,7 @@ void I2C_EnableARP(I2C_T* i2c) * * @retval None */ -void I2C_DisableARP(I2C_T* i2c) +void I2C_DisableARP(I2C_T *i2c) { i2c->CTRL1_B.ARPEN = BIT_RESET; } @@ -572,7 +586,7 @@ void I2C_DisableARP(I2C_T* i2c) * * @retval None */ -void I2C_EnableStretchClock(I2C_T* i2c) +void I2C_EnableStretchClock(I2C_T *i2c) { i2c->CTRL1_B.CLKSTRETCHD = BIT_RESET; } @@ -584,7 +598,7 @@ void I2C_EnableStretchClock(I2C_T* i2c) * * @retval None */ -void I2C_DisableStretchClock(I2C_T* i2c) +void I2C_DisableStretchClock(I2C_T *i2c) { i2c->CTRL1_B.CLKSTRETCHD = BIT_SET; } @@ -600,9 +614,9 @@ void I2C_DisableStretchClock(I2C_T* i2c) * @arg I2C_DUTYCYCLE_2: I2C fast mode Tlow/Thigh = 2 * @retval None */ -void I2C_ConfigFastModeDutyCycle(I2C_T* i2c, I2C_DUTYCYCLE_T dutyCycle) +void I2C_ConfigFastModeDutyCycle(I2C_T *i2c, I2C_DUTYCYCLE_T dutyCycle) { - if(dutyCycle == I2C_DUTYCYCLE_16_9) + if (dutyCycle == I2C_DUTYCYCLE_16_9) { i2c->CLKCTRL_B.FDUTYCFG = BIT_SET; } @@ -619,7 +633,7 @@ void I2C_ConfigFastModeDutyCycle(I2C_T* i2c, I2C_DUTYCYCLE_T dutyCycle) * * @retval None */ -void I2C_EnableDMA(I2C_T* i2c) +void I2C_EnableDMA(I2C_T *i2c) { i2c->CTRL2_B.DMAEN = ENABLE; } @@ -631,7 +645,7 @@ void I2C_EnableDMA(I2C_T* i2c) * * @retval None */ -void I2C_DisableDMA(I2C_T* i2c) +void I2C_DisableDMA(I2C_T *i2c) { i2c->CTRL2_B.DMAEN = DISABLE; } @@ -643,7 +657,7 @@ void I2C_DisableDMA(I2C_T* i2c) * * @retval None */ -void I2C_EnableDMALastTransfer(I2C_T* i2c) +void I2C_EnableDMALastTransfer(I2C_T *i2c) { i2c->CTRL2_B.LTCFG = BIT_SET; } @@ -655,7 +669,7 @@ void I2C_EnableDMALastTransfer(I2C_T* i2c) * * @retval None */ -void I2C_DisableDMALastTransfer(I2C_T* i2c) +void I2C_DisableDMALastTransfer(I2C_T *i2c) { i2c->CTRL2_B.LTCFG = BIT_RESET; } @@ -673,7 +687,7 @@ void I2C_DisableDMALastTransfer(I2C_T* i2c) * * @retval None */ -void I2C_EnableInterrupt(I2C_T* i2c, uint16_t interrupt) +void I2C_EnableInterrupt(I2C_T *i2c, uint16_t interrupt) { i2c->CTRL2 |= interrupt; } @@ -691,7 +705,7 @@ void I2C_EnableInterrupt(I2C_T* i2c, uint16_t interrupt) * * @retval None */ -void I2C_DisableInterrupt(I2C_T* i2c, uint16_t interrupt) +void I2C_DisableInterrupt(I2C_T *i2c, uint16_t interrupt) { i2c->CTRL2 &= ~interrupt; } @@ -722,7 +736,7 @@ void I2C_DisableInterrupt(I2C_T* i2c, uint16_t interrupt) * * @retval Status: SUCCESS or ERROR */ -uint8_t I2C_ReadEventStatus(I2C_T* i2c, I2C_EVENT_T i2cEvent) +uint8_t I2C_ReadEventStatus(I2C_T *i2c, I2C_EVENT_T i2cEvent) { uint32_t lastevent = 0; uint32_t flag1 = 0, flag2 = 0; @@ -733,7 +747,7 @@ uint8_t I2C_ReadEventStatus(I2C_T* i2c, I2C_EVENT_T i2cEvent) lastevent = (flag1 | flag2) & 0x00FFFFFF; - if((lastevent & i2cEvent) == i2cEvent) + if ((lastevent & i2cEvent) == i2cEvent) { return SUCCESS; } @@ -747,7 +761,7 @@ uint8_t I2C_ReadEventStatus(I2C_T* i2c, I2C_EVENT_T i2cEvent) * * @retval The last event */ -uint32_t I2C_ReadLastEvent(I2C_T* i2c) +uint32_t I2C_ReadLastEvent(I2C_T *i2c) { uint32_t lastevent = 0; uint32_t flag1 = 0, flag2 = 0; @@ -792,7 +806,7 @@ uint32_t I2C_ReadLastEvent(I2C_T* i2c) * * @retval Status: flag SET or RESET */ -uint8_t I2C_ReadStatusFlag(I2C_T* i2c, I2C_FLAG_T flag) +uint8_t I2C_ReadStatusFlag(I2C_T *i2c, I2C_FLAG_T flag) { uint8_t status = 0; @@ -900,7 +914,7 @@ uint8_t I2C_ReadStatusFlag(I2C_T* i2c, I2C_FLAG_T flag) * a read operation to I2C_STS1 register (I2C_ReadStatusFlag()) * followed by a write operation to I2C_DATA register (I2C_TxData()). */ -void I2C_ClearStatusFlag(I2C_T* i2c, I2C_FLAG_T flag) +void I2C_ClearStatusFlag(I2C_T *i2c, I2C_FLAG_T flag) { switch (flag) { @@ -954,13 +968,13 @@ void I2C_ClearStatusFlag(I2C_T* i2c, I2C_FLAG_T flag) * * @retval Status: flag SET or RESET */ -uint8_t I2C_ReadIntFlag(I2C_T* i2c, I2C_INT_FLAG_T flag) +uint8_t I2C_ReadIntFlag(I2C_T *i2c, I2C_INT_FLAG_T flag) { uint32_t enablestatus = 0; enablestatus = ((flag & 0x07000000) >> 16) & (i2c->CTRL2); flag &= 0x00FFFFFF; - if(((i2c->STS1 & flag) != RESET) && enablestatus) + if (((i2c->STS1 & flag) != RESET) && enablestatus) { return SET; } @@ -973,7 +987,7 @@ uint8_t I2C_ReadIntFlag(I2C_T* i2c, I2C_INT_FLAG_T flag) * @param i2c: I2C selet 1 or 2 * * @param flag: specifies the I2C flag - * The parameter can be one of the following values: + * The parameter can be any combination of the following values: * @arg I2C_INT_FLAG_SMBALT: SMBus Alert flag * @arg I2C_INT_FLAG_TTE: Timeout or Tlow error flag * @arg I2C_INT_FLAG_PECE: PEC error in reception flag @@ -1000,12 +1014,9 @@ uint8_t I2C_ReadIntFlag(I2C_T* i2c, I2C_INT_FLAG_T flag) * a read operation to I2C_STS1 register (I2C_ReadIntFlag()) * followed by a write operation to I2C_DATA register (I2C_TxData()). */ -void I2C_ClearIntFlag(I2C_T* i2c, I2C_INT_FLAG_T flag) +void I2C_ClearIntFlag(I2C_T *i2c, uint32_t flag) { - uint32_t flagpos = 0; - - flagpos = flag & 0x00FFFFFF; - i2c->STS1 = ~flagpos; + i2c->STS1 = (uint16_t)~(flag & 0x00FFFFFF); } /**@} end of group I2C_Fuctions*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_iwdt.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_iwdt.c index a4a743749c..d3d64748a0 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_iwdt.c +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_iwdt.c @@ -3,10 +3,24 @@ * * @brief This file provides all the IWDT firmware functions * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ #include "apm32f10x_iwdt.h" @@ -113,13 +127,12 @@ void IWDT_ConfigDivider(uint8_t div) * * @retval status of IWDT_FLAG (SET or RESET) * - * @note */ uint8_t IWDT_ReadStatusFlag(uint16_t flag) { uint8_t bitStatus = RESET; - if((IWDT->STS & flag) != (uint32_t)RESET) + if ((IWDT->STS & flag) != (uint32_t)RESET) { bitStatus = SET; } @@ -131,5 +144,5 @@ uint8_t IWDT_ReadStatusFlag(uint16_t flag) } /**@} end of group IWDT_Fuctions*/ -/**@} end of group IWDT_Driver */ +/**@} end of group IWDT_Driver*/ /**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_misc.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_misc.c index 92b925b937..e642f786bd 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_misc.c +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_misc.c @@ -1,13 +1,27 @@ /*! - * @file apm32f10x_misc.c + * @file apm32f10x_misc.c * - * @brief This file provides all the miscellaneous firmware functions. + * @brief This file provides all the miscellaneous firmware functions. * Include NVIC,SystemTick and Power management. * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ #include "apm32f10x_misc.h" @@ -26,7 +40,7 @@ #define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) -/**@} end of group I2C_Macros*/ +/**@} end of group MISC_Macros*/ /** @addtogroup MISC_Fuctions Fuctions @@ -48,7 +62,7 @@ */ void NVIC_ConfigPriorityGroup(NVIC_PRIORITY_GROUP_T priorityGroup) { - SCB->AIRCR = AIRCR_VECTKEY_MASK | priorityGroup; + SCB->AIRCR = AIRCR_VECTKEY_MASK | priorityGroup; } /*! @@ -65,55 +79,55 @@ void NVIC_ConfigPriorityGroup(NVIC_PRIORITY_GROUP_T priorityGroup) */ void NVIC_EnableIRQRequest(IRQn_Type irq, uint8_t preemptionPriority, uint8_t subPriority) { - uint32_t tempPriority, tempPrePri, tempSubPri; - uint32_t priorityGrp; + uint32_t tempPriority, tempPrePri, tempSubPri; + uint32_t priorityGrp; - /** Get priority group */ - priorityGrp = (SCB->AIRCR) & (uint32_t)0x700U; + /** Get priority group */ + priorityGrp = (SCB->AIRCR) & (uint32_t)0x700U; - /** get pre-emption priority and subpriority */ - switch(priorityGrp) - { - case NVIC_PRIORITY_GROUP_0: - tempPrePri = 0; - tempSubPri = 4; - break; + /** get pre-emption priority and subpriority */ + switch (priorityGrp) + { + case NVIC_PRIORITY_GROUP_0: + tempPrePri = 0; + tempSubPri = 4; + break; - case NVIC_PRIORITY_GROUP_1: - tempPrePri = 1; - tempSubPri = 3; - break; + case NVIC_PRIORITY_GROUP_1: + tempPrePri = 1; + tempSubPri = 3; + break; - case NVIC_PRIORITY_GROUP_2: - tempPrePri = 2; - tempSubPri = 2; - break; + case NVIC_PRIORITY_GROUP_2: + tempPrePri = 2; + tempSubPri = 2; + break; - case NVIC_PRIORITY_GROUP_3: - tempPrePri = 3; - tempSubPri = 1; - break; + case NVIC_PRIORITY_GROUP_3: + tempPrePri = 3; + tempSubPri = 1; + break; - case NVIC_PRIORITY_GROUP_4: - tempPrePri = 4; - tempSubPri = 0; - break; + case NVIC_PRIORITY_GROUP_4: + tempPrePri = 4; + tempSubPri = 0; + break; - default: - NVIC_ConfigPriorityGroup(NVIC_PRIORITY_GROUP_0); - tempPrePri = 0; - tempSubPri = 4; - break; - } + default: + NVIC_ConfigPriorityGroup(NVIC_PRIORITY_GROUP_0); + tempPrePri = 0; + tempSubPri = 4; + break; + } - tempPrePri = 4 - tempPrePri; - tempSubPri = 4 - tempSubPri; - tempPriority = preemptionPriority << tempPrePri; - tempPriority |= subPriority & (0x0f >> tempSubPri); - tempPriority <<= 4; - NVIC->IP[irq] = (uint8_t)tempPriority; + tempPrePri = 4 - tempPrePri; + tempSubPri = 4 - tempSubPri; + tempPriority = preemptionPriority << tempPrePri; + tempPriority |= subPriority & (0x0f >> tempSubPri); + tempPriority <<= 4; + NVIC->IP[irq] = (uint8_t)tempPriority; - /* enable the selected IRQ */ + /** enable the selected IRQ */ NVIC->ISER[irq >> 0x05U] = (uint32_t)0x01U << (irq & (uint8_t)0x1FU); } @@ -126,7 +140,7 @@ void NVIC_EnableIRQRequest(IRQn_Type irq, uint8_t preemptionPriority, uint8_t su */ void NVIC_DisableIRQRequest(IRQn_Type irq) { - /* disable the selected IRQ.*/ + /** disable the selected IRQ.*/ NVIC->ICER[irq >> 0x05U] = (uint32_t)0x01U << (irq & (uint8_t)0x1FU); } @@ -160,10 +174,9 @@ void NVIC_ConfigVectorTable(NVIC_VECT_TAB_T vectTab, uint32_t offset) */ void NVIC_SetSystemLowPower(NVIC_LOWPOWER_T lowPowerMode) { - SCB->SCR |= lowPowerMode; + SCB->SCR |= lowPowerMode; } - /*! * @brief reset the state of the low power mode * @@ -177,7 +190,7 @@ void NVIC_SetSystemLowPower(NVIC_LOWPOWER_T lowPowerMode) */ void NVIC_ResetystemLowPower(NVIC_LOWPOWER_T lowPowerMode) { - SCB->SCR &= (uint32_t)(~(uint32_t)lowPowerMode); + SCB->SCR &= (uint32_t)(~(uint32_t)lowPowerMode); } /*! @@ -192,16 +205,16 @@ void NVIC_ResetystemLowPower(NVIC_LOWPOWER_T lowPowerMode) */ void SysTick_ConfigCLKSource(SYSTICK_CLK_SOURCE_T clkSource) { - if (clkSource == SYSTICK_CLK_SOURCE_HCLK) - { - SysTick->CTRL |= (uint32_t)BIT2; - } - else - { - SysTick->CTRL &= (uint32_t)(~BIT2); - } + if (clkSource == SYSTICK_CLK_SOURCE_HCLK) + { + SysTick->CTRL |= (uint32_t)BIT2; + } + else + { + SysTick->CTRL &= (uint32_t)(~BIT2); + } } /**@} end of group MISC_Fuctions*/ -/**@} end of group MISC_Driver */ +/**@} end of group MISC_Driver*/ /**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_pmu.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_pmu.c index 969b1a98d7..b32726e0df 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_pmu.c +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_pmu.c @@ -1,12 +1,26 @@ /*! - * @file apm32f10x_pmu.c + * @file apm32f10x_pmu.c * - * @brief This file provides all the PMU firmware functions. + * @brief This file provides all the PMU firmware functions. * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ #include "apm32f10x_pmu.h" @@ -33,8 +47,8 @@ */ void PMU_Reset(void) { - RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_PMU); - RCM_DisableAPB1PeriphClock(RCM_APB1_PERIPH_PMU); + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_PMU); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_PMU); } /*! @@ -88,7 +102,7 @@ void PMU_DisablePVD(void) /*! * @brief Configure a voltage threshold detected by a power supply voltage detector (PVD). * - * @param level : specifies the PVD detection level + * @param level：specifies the PVD detection level * This parameter can be one of the following values: * @arg PMU_PVD_LEVEL_2V2 : Config PVD detection level to 2.2V * @arg PMU_PVD_LEVEL_2V3 : Config PVD detection level to 2.3V @@ -104,9 +118,9 @@ void PMU_DisablePVD(void) void PMU_ConfigPVDLevel(PMU_PVD_LEVEL_T level) { - /* Clear PLS[7:5] bits */ + /** Clear PLS[7:5] bits */ PMU->CTRL_B.PLSEL = 0x0000; - /* Store the new value */ + /** Store the new value */ PMU->CTRL_B.PLSEL = level; } @@ -151,17 +165,20 @@ void PMU_DisableWakeUpPin(void) */ void PMU_EnterSTOPMode(PMU_REGULATOR_T regulator, PMU_STOP_ENTRY_T entry) { - /** Clear PLS and LPSM bits */ + /** Clear PDDSCFG and LPDSCFG bits */ PMU->CTRL_B.PDDSCFG = 0x00; PMU->CTRL_B.LPDSCFG = 0x00; - /** Set LPSM bit according to PWR_Regulator value */ - PMU->CTRL_B.PDDSCFG = regulator; + /** Set LPDSCFG bit according to regulator value */ + PMU->CTRL_B.LPDSCFG = regulator; + /** Set Cortex System Control Register */ + SCB->SCR |= (uint32_t)0x04; /** Select STOP mode entry*/ - if(entry == PMU_STOP_ENTRY_WFI) + if (entry == PMU_STOP_ENTRY_WFI) { /** Request Wait For Interrupt */ __WFI(); - } else + } + else { /** Request Wait For Event */ __WFE(); @@ -169,7 +186,6 @@ void PMU_EnterSTOPMode(PMU_REGULATOR_T regulator, PMU_STOP_ENTRY_T entry) /** Reset SLEEPDEEP bit of Cortex System Control Register */ SCB->SCR &= (uint32_t)~((uint32_t)0x04); - } /*! @@ -181,16 +197,16 @@ void PMU_EnterSTOPMode(PMU_REGULATOR_T regulator, PMU_STOP_ENTRY_T entry) */ void PMU_EnterSTANDBYMode(void) { - /* Clear Wake-up flag */ + /** Clear Wake-up flag */ PMU->CTRL_B.WUFLGCLR = BIT_SET; - /* Select STANDBY mode */ + /** Select STANDBY mode */ PMU->CTRL_B.PDDSCFG = BIT_SET; - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR |= (uint8_t )0x04; + /** Set Cortex System Control Register */ + SCB->SCR |= (uint32_t)0x04; #if defined ( __CC_ARM ) __force_stores(); #endif - /* Request Wait For Interrupt */ + /** Request Wait For Interrupt */ __WFI(); } @@ -198,7 +214,7 @@ void PMU_EnterSTANDBYMode(void) /*! * @brief Read the specified PWR flag is set or not. * - * @param flag : Reads the status of specifies the flag. + * @param flag：Reads the status of specifies the flag. * This parameter can be one of the following values: * @arg PMU_FLAG_WUE : Wake Up flag * @arg PMU_FLAG_SB : StandBy flag @@ -210,13 +226,15 @@ uint8_t PMU_ReadStatusFlag(PMU_FLAG_T flag) { uint8_t BitStatus = BIT_RESET; - if(flag == PMU_FLAG_WUE) + if (flag == PMU_FLAG_WUE) { BitStatus = PMU->CSTS_B.WUEFLG; - } else if(flag == PMU_FLAG_SB) + } + else if (flag == PMU_FLAG_SB) { BitStatus = PMU->CSTS_B.SBFLG; - } else if(flag == PMU_FLAG_PVDO) + } + else if (flag == PMU_FLAG_PVDO) { BitStatus = PMU->CSTS_B.PVDOFLG; } @@ -226,7 +244,7 @@ uint8_t PMU_ReadStatusFlag(PMU_FLAG_T flag) /*! * @brief Clears the PWR's pending flags. * - * @param flag : Clears the status of specifies the flag. + * @param flag：Clears the status of specifies the flag. * This parameter can be one of the following values: * @arg PMU_FLAG_WUE : Wake Up flag * @arg PMU_FLAG_SB : StandBy flag @@ -235,15 +253,16 @@ uint8_t PMU_ReadStatusFlag(PMU_FLAG_T flag) */ void PMU_ClearStatusFlag(PMU_FLAG_T flag) { - if(flag == PMU_FLAG_WUE) + if (flag == PMU_FLAG_WUE) { PMU->CTRL_B.WUFLGCLR = BIT_SET; - } else if(flag == PMU_FLAG_SB) + } + else if (flag == PMU_FLAG_SB) { PMU->CTRL_B.SBFLGCLR = BIT_SET; } } /**@} end of group PMU_Fuctions*/ -/**@} end of group PMU_Driver */ +/**@} end of group PMU_Driver*/ /**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_qspi.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_qspi.c index 5706b95e1a..2e3b694aa0 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_qspi.c +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_qspi.c @@ -3,12 +3,27 @@ * * @brief This file contains all the functions for the QSPI peripheral * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ +#if defined (APM32F10X_MD) || defined (APM32F10X_LD) #include "apm32f10x_qspi.h" /** @addtogroup Peripherals_Library Standard Peripheral Library @@ -58,7 +73,7 @@ void QSPI_Reset(void) * * @retval None */ -void QSPI_Config(QSPI_Config_T * qspiConfig) +void QSPI_Config(QSPI_Config_T *qspiConfig) { QSPI->CTRL1_B.CPHA = qspiConfig->clockPhase; QSPI->CTRL1_B.CPOL = qspiConfig->clockPolarity; @@ -67,7 +82,6 @@ void QSPI_Config(QSPI_Config_T * qspiConfig) QSPI->CTRL1_B.SSTEN = qspiConfig->selectSlaveToggle; QSPI->BR = qspiConfig->clockDiv; - } /*! @@ -571,24 +585,25 @@ void QSPI_ClearIntFlag(uint32_t flag) { volatile uint32_t dummy = 0; - if(flag & QSPI_INT_FLAG_TFO) + if (flag & QSPI_INT_FLAG_TFO) { dummy = QSPI->TFOIC; } - else if(flag & QSPI_INT_FLAG_RFO) + else if (flag & QSPI_INT_FLAG_RFO) { dummy = QSPI->RFOIC; } - else if(flag & QSPI_INT_FLAG_RFU) + else if (flag & QSPI_INT_FLAG_RFU) { dummy = QSPI->RFUIC; } - else if(flag & QSPI_INT_FLAG_MST) + else if (flag & QSPI_INT_FLAG_MST) { dummy = QSPI->MIC; } } +#endif //defined APM32F10X_MD/LD /**@} end of group QSPI_Fuctions*/ -/**@} end of group QSPI_Driver */ +/**@} end of group QSPI_Driver*/ /**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_rcm.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_rcm.c index a1d6205224..bf518d02ea 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_rcm.c +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_rcm.c @@ -1,12 +1,26 @@ /*! - * @file apm32f10x_rcm.c + * @file apm32f10x_rcm.c * - * @brief This file provides all the RCM firmware functions + * @brief This file provides all the RCM firmware functions * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ #include "apm32f10x_rcm.h" @@ -102,14 +116,14 @@ uint8_t RCM_WaitHSEReady(void) } /*! - * @brief Set HSI trimming value + * @brief Config HSI trimming value * * @param HSITrim: HSI trimming value * This parameter must be a number between 0 and 0x1F. * * @retval None */ -void RCM_SetHSITrim(uint8_t HSITrim) +void RCM_ConfigHSITrim(uint8_t HSITrim) { RCM->CTRL_B.HSITRIM = HSITrim; } @@ -145,10 +159,12 @@ void RCM_DisableHSI(void) * @brief Configures the External Low Speed oscillator (LSE) * * @param state : Specifies the new state of the LSE + * This parameter can be one of the following values: + * @arg RCM_LSE_CLOSE : Close the LSE + * @arg RCM_LSE_OPEN : Open the LSE + * @arg RCM_LSE_BYPASS : LSE bypass * * @retval None - * - * @note */ void RCM_ConfigLSE(RCM_LSE_T state) { @@ -172,8 +188,6 @@ void RCM_ConfigLSE(RCM_LSE_T state) * @param None * * @retval None - * - * @note */ void RCM_EnableLSI(void) { @@ -186,8 +200,6 @@ void RCM_EnableLSI(void) * @param None * * @retval None - * - * @note */ void RCM_DisableLSI(void) { @@ -273,14 +285,12 @@ void RCM_DisableCSS(void) * @param mcoClock: specifies the clock source to output * This parameter can be one of the following values: * @arg RCM_MCOCLK_NO_CLOCK : No clock selected. - * @arg RCM_MCOCLK_SYSCLK : HSI14 oscillator clock selected. - * @arg RCM_MCOCLK_HSI : LSI oscillator clock selected. - * @arg RCM_MCOCLK_HSE : LSE oscillator clock selected. - * @arg RCM_MCOCLK_PLLCLK_DIV_2 : System clock selected. + * @arg RCM_MCOCLK_SYSCLK : System clock selected. + * @arg RCM_MCOCLK_HSI : HSI oscillator clock selected. + * @arg RCM_MCOCLK_HSE : HSE oscillator clock selected. + * @arg RCM_MCOCLK_PLLCLK_DIV_2 : PLL clock divided by 2 selected. * * @retval None - * - * @note */ void RCM_ConfigMCO(RCM_MCOCLK_T mcoClock) { @@ -300,7 +310,7 @@ void RCM_ConfigMCO(RCM_MCOCLK_T mcoClock) */ void RCM_ConfigSYSCLK(RCM_SYSCLK_SEL_T sysClkSelect) { - RCM->CFG_B.SCLKSW = sysClkSelect; + RCM->CFG_B.SCLKSEL = sysClkSelect; } /*! @@ -312,11 +322,7 @@ void RCM_ConfigSYSCLK(RCM_SYSCLK_SEL_T sysClkSelect) */ RCM_SYSCLK_SEL_T RCM_ReadSYSCLKSource(void) { - RCM_SYSCLK_SEL_T sysClock; - - sysClock = (RCM_SYSCLK_SEL_T)RCM->CFG_B.SCLKSWSTS; - - return sysClock; + return (RCM_SYSCLK_SEL_T)RCM->CFG_B.SCLKSELSTS; } /*! @@ -335,8 +341,6 @@ RCM_SYSCLK_SEL_T RCM_ReadSYSCLKSource(void) * @arg RCM_AHB_DIV_512 : HCLK = SYSCLK / 512 * * @retval None - * - * @note */ void RCM_ConfigAHB(RCM_AHB_DIV_T AHBDiv) { @@ -482,47 +486,47 @@ uint32_t RCM_ReadSYSCLKFreq(void) uint32_t sysClock, pllMull, pllSource; /** get sys clock */ - sysClock = RCM->CFG_B.SCLKSW; + sysClock = RCM->CFG_B.SCLKSEL; switch (sysClock) { - /** sys clock is HSI */ - case RCM_SYSCLK_SEL_HSI: - sysClock = HSI_VALUE; - break; + /** sys clock is HSI */ + case RCM_SYSCLK_SEL_HSI: + sysClock = HSI_VALUE; + break; - /** sys clock is HSE */ - case RCM_SYSCLK_SEL_HSE: - sysClock = HSE_VALUE; - break; + /** sys clock is HSE */ + case RCM_SYSCLK_SEL_HSE: + sysClock = HSE_VALUE; + break; - /** sys clock is PLL */ - case RCM_SYSCLK_SEL_PLL: - pllMull = RCM->CFG_B.PLLMULCFG + 2; - pllSource = RCM->CFG_B.PLLSRCSEL; + /** sys clock is PLL */ + case RCM_SYSCLK_SEL_PLL: + pllMull = RCM->CFG_B.PLLMULCFG + 2; + pllSource = RCM->CFG_B.PLLSRCSEL; - /** PLL entry clock source is HSE */ - if (pllSource == BIT_SET) + /** PLL entry clock source is HSE */ + if (pllSource == BIT_SET) + { + sysClock = HSE_VALUE * pllMull; + + /** HSE clock divided by 2 */ + if (pllSource == RCM->CFG_B.PLLHSEPSC) { - sysClock = HSE_VALUE * pllMull; - - /** HSE clock divided by 2 */ - if (pllSource == RCM->CFG_B.PLLHSEPSC) - { - sysClock >>= 1; - } - } - /** PLL entry clock source is HSI/2 */ - else - { - sysClock = (HSI_VALUE >> 1) * pllMull; + sysClock >>= 1; } + } + /** PLL entry clock source is HSI/2 */ + else + { + sysClock = (HSI_VALUE >> 1) * pllMull; + } - break; + break; - default: - sysClock = HSI_VALUE; - break; + default: + sysClock = HSI_VALUE; + break; } return sysClock; @@ -557,7 +561,7 @@ uint32_t RCM_ReadHCLKFreq(void) * * @retval None */ -void RCM_ReadPCLKFreq(uint32_t* PCLK1, uint32_t* PCLK2) +void RCM_ReadPCLKFreq(uint32_t *PCLK1, uint32_t *PCLK2) { uint32_t hclk, divider; uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; @@ -897,7 +901,6 @@ void RCM_DisableAPB1PeriphReset(uint32_t APB1Periph) * * @retval None * - * @note */ void RCM_EnableBackupReset(void) { @@ -948,7 +951,7 @@ void RCM_EnableInterrupt(uint32_t interrupt) * @arg RCM_INT_HSIRDY : HSI ready interrupt * @arg RCM_INT_HSERDY : HSE ready interrupt * @arg RCM_INT_PLLRDY : PLL ready interrupt -RCM_DisableInterrupt(RCM_INT_LSIRDY) * + * * @retval None */ void RCM_DisableInterrupt(uint32_t interrupt) @@ -989,20 +992,20 @@ uint8_t RCM_ReadStatusFlag(RCM_FLAG_T flag) switch (reg) { - case 0: - reg = RCM->CTRL; - break; + case 0: + reg = RCM->CTRL; + break; - case 1: - reg = RCM->BDCTRL; - break; + case 1: + reg = RCM->BDCTRL; + break; - case 2: - reg = RCM->CSTS; - break; + case 2: + reg = RCM->CSTS; + break; - default: - break; + default: + break; } if (reg & bit) @@ -1032,7 +1035,7 @@ void RCM_ClearStatusFlag(void) /*! * @brief Reads the specified RCM interrupt Flag * - * @param flag : Reads specifies RCM interrupt flag. + * @param flag ：Reads specifies RCM interrupt flag. * This parameter can be one of the following values: * @arg RCM_INT_LSIRDY : LSI ready interrupt flag * @arg RCM_INT_LSERDY : LSE ready interrupt flag @@ -1045,11 +1048,7 @@ void RCM_ClearStatusFlag(void) */ uint8_t RCM_ReadIntFlag(RCM_INT_T flag) { - uint8_t ret; - - ret = (RCM->INT& flag) ? SET : RESET; - - return ret; + return (RCM->INT &flag) ? SET : RESET; } /*! diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_rtc.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_rtc.c index 71db57ceb7..14489aadc0 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_rtc.c +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_rtc.c @@ -1,12 +1,26 @@ /*! - * @file apm32f10x_rtc.c + * @file apm32f10x_rtc.c * - * @brief This file provides all the RTC firmware functions + * @brief This file provides all the RTC firmware functions * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ #include "apm32f10x_rtc.h" @@ -55,7 +69,10 @@ void RTC_DisableConfigMode(void) */ uint32_t RTC_ReadCounter(void) { - return (((RTC->CNTH_B.CNTH) << 16) | (RTC->CNTL_B.CNTL)); + uint32_t reg = 0; + reg = (RTC->CNTH_B.CNTH) << 16; + reg |= (RTC->CNTL_B.CNTL); + return (reg); } /*! @@ -112,7 +129,10 @@ void RTC_ConfigAlarm(uint32_t value) */ uint32_t RTC_ReadDivider(void) { - return ((RTC->PSCH_B.PSCH & 0x000F) << 16 ) | (RTC->PSCL_B.PSCL); + uint32_t reg = 0; + reg = (RTC->PSCH_B.PSCH & 0x000F) << 16; + reg |= (RTC->PSCL_B.PSCL); + return (reg); } /*! @@ -124,7 +144,7 @@ uint32_t RTC_ReadDivider(void) */ void RTC_WaitForLastTask(void) { - while(RTC->CSTS_B.OCFLG == BIT_RESET) + while (RTC->CSTS_B.OCFLG == BIT_RESET) { } } @@ -139,17 +159,17 @@ void RTC_WaitForLastTask(void) void RTC_WaitForSynchor(void) { RTC->CSTS_B.RSYNCFLG = BIT_RESET; - while(RTC->CSTS_B.RSYNCFLG == BIT_RESET) - { - } + while (RTC->CSTS_B.RSYNCFLG == BIT_RESET); } /*! * @brief Enable RTC interrupts. * - * @param interrupt: RTC interrupt - * - * @retval None + * @param interrupt: specifies the RTC interrupt sources to be enabled + * This parameter can be any combination of the following values: + * @arg RTC_INT_OVR : Overflow interrupt + * @arg RTC_INT_ALR : Alarm interrupt + * @arg RTC_INT_SEC : Second interrupt */ void RTC_EnableInterrupt(uint16_t interrupt) { @@ -159,31 +179,45 @@ void RTC_EnableInterrupt(uint16_t interrupt) /*! * @brief Disable RTC interrupts. * - * @param interrupt: RTC interrupt + * @param interrupt: specifies the RTC interrupt sources to be disabled + * This parameter can be any combination of the following values: + * @arg RTC_INT_OVR : Overflow interrupt + * @arg RTC_INT_ALR : Alarm interrupt + * @arg RTC_INT_SEC : Second interrupt * * @retval None */ void RTC_DisableInterrupt(uint16_t interrupt) { - RTC->CTRL &= (uint32_t )~interrupt; + RTC->CTRL &= (uint32_t)~interrupt; } /*! * @brief Read flag bit * - * @param flag: Flags to read + * @param flag: specifies the flag to check. + * This parameter can be one of the following values: + * @arg RTC_FLAG_OC : RTC Operation Complete flag + * @arg RTC_FLAG_RSYNC: Registers Synchronized flag + * @arg RTC_FLAG_OVR : Overflow flag + * @arg RTC_FLAG_ALR : Alarm flag + * @arg RTC_FLAG_SEC : Second flag * - * @retval flag bit + * @retval SET or RESET */ uint8_t RTC_ReadStatusFlag(RTC_FLAG_T flag) { - return (RTC->CSTS & flag) ? SET : RESET; + return (RTC->CSTS & flag) ? SET : RESET; } /*! * @brief Clear flag bit * - * @param flag: Flags to clear + * @param flag: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg RTC_FLAG_OVR : Overflow flag + * @arg RTC_FLAG_ALR : Alarm flag + * @arg RTC_FLAG_SEC : Second flag * * @retval None */ @@ -195,7 +229,11 @@ void RTC_ClearStatusFlag(uint16_t flag) /*! * @brief Read interrupt flag bit is set * - * @param flag:Flag bit to check + * @param flag: specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg RTC_INT_OVR : Overflow interrupt + * @arg RTC_INT_ALR : Alarm interrupt + * @arg RTC_INT_SEC : Second interrupt * * @retval None */ @@ -207,7 +245,11 @@ uint8_t RTC_ReadIntFlag(RTC_INT_T flag) /*! * @brief Clear RTC interrupt flag bit * - * @param flag: Clears the specified interrupt flag bit + * @param flag: specifies the flag to clear. + * This parameter can be one of the following values: + * @arg RTC_INT_OVR : Overflow interrupt + * @arg RTC_INT_ALR : Alarm interrupt + * @arg RTC_INT_SEC : Second interrupt * * @retval None */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_sci2c.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_sci2c.c index 4b5ea1276a..9c7f865592 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_sci2c.c +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_sci2c.c @@ -3,10 +3,24 @@ * * @brief This file contains all the functions for the SCI2C peripheral * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ #include "apm32f10x_sci2c.h" @@ -33,7 +47,7 @@ */ void SCI2C_Reset(SCI2C_T *i2c) { - if(i2c == I2C3) + if (i2c == I2C3) { RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_I2C1); RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_I2C1); @@ -64,7 +78,7 @@ void SCI2C_Config(SCI2C_T *i2c, SCI2C_Config_T *sci2cConfig) i2c->CTRL2_B.I2CEN = BIT_RESET; - if(sci2cConfig->mode == SCI2C_MODE_MASTER) + if (sci2cConfig->mode == SCI2C_MODE_MASTER) { i2c->CTRL1_B.MST = BIT_SET; i2c->CTRL1_B.SLADIS = BIT_SET; @@ -84,17 +98,17 @@ void SCI2C_Config(SCI2C_T *i2c, SCI2C_Config_T *sci2cConfig) i2c->CTRL1_B.SAM = sci2cConfig->addrMode; i2c->SLAADDR = sci2cConfig->slaveAddr; - if(sci2cConfig->speed == SCI2C_SPEED_STANDARD) + if (sci2cConfig->speed == SCI2C_SPEED_STANDARD) { i2c->SSCLC = sci2cConfig->clkLowPeriod; i2c->SSCHC = sci2cConfig->clkHighPeriod; } - else if(sci2cConfig->speed == SCI2C_SPEED_FAST) + else if (sci2cConfig->speed == SCI2C_SPEED_FAST) { i2c->FSCLC = sci2cConfig->clkLowPeriod; i2c->FSCHC = sci2cConfig->clkHighPeriod; } - else if(sci2cConfig->speed == SCI2C_SPEED_HIGH) + else if (sci2cConfig->speed == SCI2C_SPEED_HIGH) { i2c->HSCLC = sci2cConfig->clkLowPeriod; i2c->HSCHC = sci2cConfig->clkHighPeriod; @@ -145,7 +159,7 @@ uint8_t SCI2C_ReadStatusFlag(SCI2C_T *i2c, SCI2C_FLAG_T flag) { uint8_t ret = RESET; - if(flag & BIT8) + if (flag & BIT8) { ret = i2c->STS2 & flag ? SET : RESET; } @@ -214,47 +228,47 @@ void SCI2C_ClearIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag) { volatile uint32_t dummy = 0; - if(flag == SCI2C_INT_ALL) + if (flag == SCI2C_INT_ALL) { dummy = i2c->INTCLR; } - else if(flag == SCI2C_INT_RFU) + else if (flag == SCI2C_INT_RFU) { dummy = i2c->RFUIC; } - else if(flag == SCI2C_INT_RFO) + else if (flag == SCI2C_INT_RFO) { dummy = i2c->RFOIC; } - else if(flag == SCI2C_INT_TFO) + else if (flag == SCI2C_INT_TFO) { dummy = i2c->TFOIC; } - else if(flag == SCI2C_INT_RR) + else if (flag == SCI2C_INT_RR) { dummy = i2c->RRIC; } - else if(flag == SCI2C_INT_TA) + else if (flag == SCI2C_INT_TA) { dummy = i2c->TAIC; } - else if(flag == SCI2C_INT_RD) + else if (flag == SCI2C_INT_RD) { dummy = i2c->RDIC; } - else if(flag == SCI2C_INT_ACT) + else if (flag == SCI2C_INT_ACT) { dummy = i2c->AIC; } - else if(flag == SCI2C_INT_STPD) + else if (flag == SCI2C_INT_STPD) { dummy = i2c->STPDIC; } - else if(flag == SCI2C_INT_STAD) + else if (flag == SCI2C_INT_STAD) { dummy = i2c->STADIC; } - else if(flag == SCI2C_INT_GC) + else if (flag == SCI2C_INT_GC) { dummy = i2c->GCIC; } @@ -442,7 +456,7 @@ void SCI2C_ConfigSpeed(SCI2C_T *i2c, SCI2C_SPEED_T speed) * @arg SCI2C_ADDR_MODE_10BIT: 10-bit address mode. * * @param addr: Specifies the address. - + * * @retval None */ void SCI2C_ConfigMasterAddr(SCI2C_T *i2c, SCI2C_ADDR_MODE_T mode, uint16_t addr) @@ -462,7 +476,7 @@ void SCI2C_ConfigMasterAddr(SCI2C_T *i2c, SCI2C_ADDR_MODE_T mode, uint16_t addr) * @arg SCI2C_ADDR_MODE_10BIT: 10-bit address mode. * * @param addr: Specifies the address. - + * * @retval None */ void SCI2C_ConfigSlaveAddr(SCI2C_T *i2c, SCI2C_ADDR_MODE_T mode, uint16_t addr) @@ -570,7 +584,6 @@ void SCI2C_TxData(SCI2C_T *i2c, uint8_t data) * * @retval Received data * - * @note */ uint8_t SCI2C_RxData(SCI2C_T *i2c) { @@ -718,17 +731,17 @@ void SCI2C_BlockTxCmd(SCI2C_T *i2c, uint8_t enable) */ void SCI2C_ConfigClkPeriod(SCI2C_T *i2c, SCI2C_SPEED_T speed, uint16_t highPeriod, uint16_t lowPeriod) { - if(speed == SCI2C_SPEED_STANDARD) + if (speed == SCI2C_SPEED_STANDARD) { i2c->SSCLC = lowPeriod; i2c->SSCHC = highPeriod; } - else if(speed == SCI2C_SPEED_FAST) + else if (speed == SCI2C_SPEED_FAST) { i2c->FSCLC = lowPeriod; i2c->FSCHC = highPeriod; } - else if(speed == SCI2C_SPEED_HIGH) + else if (speed == SCI2C_SPEED_HIGH) { i2c->HSCLC = lowPeriod; i2c->HSCHC = highPeriod; @@ -882,7 +895,7 @@ void SCI2C_ConfigDMARxDataLevel(SCI2C_T *i2c, uint8_t cnt) */ void SCI2C_ConfigSpikeSuppressionLimit(SCI2C_T *i2c, SCI2C_SPEED_T speed, uint8_t limit) { - if(speed == SCI2C_SPEED_HIGH) + if (speed == SCI2C_SPEED_HIGH) { i2c->HSSSL = limit; } @@ -895,4 +908,3 @@ void SCI2C_ConfigSpikeSuppressionLimit(SCI2C_T *i2c, SCI2C_SPEED_T speed, uint8_ /**@} end of group SCI2C_Fuctions*/ /**@} end of group SCI2C_Driver*/ /**@} end of group Peripherals_Library*/ - diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_sdio.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_sdio.c index f79af54970..1a2d3a82be 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_sdio.c +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_sdio.c @@ -1,12 +1,26 @@ /*! - * @file apm32f10x_sdio.c + * @file apm32f10x_sdio.c * - * @brief This file provides all the SDIO firmware functions + * @brief This file provides all the SDIO firmware functions * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ #include "apm32f10x_sdio.h" @@ -51,7 +65,7 @@ void SDIO_Reset(void) * * @retval None */ -void SDIO_Config(SDIO_Config_T* sdioConfig) +void SDIO_Config(SDIO_Config_T *sdioConfig) { uint32_t tmp = 0; @@ -59,7 +73,7 @@ void SDIO_Config(SDIO_Config_T* sdioConfig) tmp &= 0xFFFF8100; tmp |= (sdioConfig->clockDiv | sdioConfig->clockPowerSave | sdioConfig->clockBypass | sdioConfig->busWide | - sdioConfig->clockEdge | sdioConfig->hardwareFlowControl); + sdioConfig->clockEdge | sdioConfig->hardwareFlowControl); SDIO->CLKCTRL = tmp; } @@ -71,14 +85,14 @@ void SDIO_Config(SDIO_Config_T* sdioConfig) * * @retval None */ -void SDIO_ConfigStructInit(SDIO_Config_T* sdioConfig) +void SDIO_ConfigStructInit(SDIO_Config_T *sdioConfig) { - sdioConfig->clockDiv = 0x00; - sdioConfig->clockEdge = SDIO_CLOCK_EDGE_RISING; - sdioConfig->clockBypass = SDIO_CLOCK_BYPASS_DISABLE; - sdioConfig->clockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE; - sdioConfig->busWide = SDIO_BUSWIDE_1B; - sdioConfig->hardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE; + sdioConfig->clockDiv = 0x00; + sdioConfig->clockEdge = SDIO_CLOCK_EDGE_RISING; + sdioConfig->clockBypass = SDIO_CLOCK_BYPASS_DISABLE; + sdioConfig->clockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE; + sdioConfig->busWide = SDIO_BUS_WIDE_1B; + sdioConfig->hardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE; } /*! @@ -161,13 +175,12 @@ void SDIO_DisableDMA(void) /*! * @brief Configs the SDIO Command and send the command * - * @param cmdConfig: pointer to a SDIO_CMDConfig_T structure + * @param cmdConfig: pointer to a SDIO_CmdConfig_T structure * * @retval None * - * @note */ -void SDIO_TxCommand(SDIO_CMDConfig_T *cmdConfig) +void SDIO_TxCommand(SDIO_CmdConfig_T *cmdConfig) { uint32_t tmpreg = 0; @@ -175,26 +188,25 @@ void SDIO_TxCommand(SDIO_CMDConfig_T *cmdConfig) tmpreg = SDIO->CMD; tmpreg &= 0xFFFFF800; tmpreg |= (uint32_t)cmdConfig->cmdIndex | cmdConfig->response - | cmdConfig->wait | cmdConfig->CPSM; + | cmdConfig->wait | cmdConfig->CPSM; SDIO->CMD = tmpreg; } /*! * @brief Fills each SDIO_CMD_ConfigStruct_T member with its default value * - * @param cmdConfig: pointer to a SDIO_CMDConfig_T structure + * @param cmdConfig: pointer to a SDIO_CmdConfig_T structure * * @retval None * - * @note */ -void SDIO_TxCommandStructInit(SDIO_CMDConfig_T* cmdConfig) +void SDIO_TxCommandStructInit(SDIO_CmdConfig_T *cmdConfig) { - cmdConfig->argument = 0x00; - cmdConfig->cmdIndex = 0x00; - cmdConfig->response = SDIO_RESPONSE_NO; - cmdConfig->wait = SDIO_WAIT_NO; - cmdConfig->CPSM = SDIO_CPSM_DISABLE; + cmdConfig->argument = 0x00; + cmdConfig->cmdIndex = 0x00; + cmdConfig->response = SDIO_RESPONSE_NO; + cmdConfig->wait = SDIO_WAIT_NO; + cmdConfig->CPSM = SDIO_CPSM_DISABLE; } /*! @@ -204,7 +216,6 @@ void SDIO_TxCommandStructInit(SDIO_CMDConfig_T* cmdConfig) * * @retval The command index of the last command response received * - * @note */ uint8_t SDIO_ReadCommandResponse(void) { @@ -225,11 +236,11 @@ uint8_t SDIO_ReadCommandResponse(void) */ uint32_t SDIO_ReadResponse(SDIO_RES_T res) { - __IO uint32_t tmp = 0; + __IO uint32_t tmp = 0; - tmp = ((uint32_t)(SDIO_BASE + 0x14)) + res; + tmp = ((uint32_t)(SDIO_BASE + 0x14)) + res; - return (*(__IO uint32_t *) tmp); + return (*(__IO uint32_t *) tmp); } /*! @@ -239,7 +250,7 @@ uint32_t SDIO_ReadResponse(SDIO_RES_T res) * * @retval None */ -void SDIO_ConfigData(SDIO_DataConfig_T* dataConfig) +void SDIO_ConfigData(SDIO_DataConfig_T *dataConfig) { uint32_t tmpreg = 0; @@ -252,7 +263,7 @@ void SDIO_ConfigData(SDIO_DataConfig_T* dataConfig) tmpreg &= 0xFFFFFF08; tmpreg |= (uint32_t)dataConfig->dataBlockSize | dataConfig->transferDir - | dataConfig->transferMode | dataConfig->DPSM; + | dataConfig->transferMode | dataConfig->DPSM; SDIO->DCTRL = tmpreg; } @@ -264,14 +275,14 @@ void SDIO_ConfigData(SDIO_DataConfig_T* dataConfig) * * @retval None */ -void SDIO_ConfigDataStructInit(SDIO_DataConfig_T* dataConfig) +void SDIO_ConfigDataStructInit(SDIO_DataConfig_T *dataConfig) { - dataConfig->dataTimeOut = 0xFFFFFFFF; - dataConfig->dataLength = 0x00; - dataConfig->dataBlockSize = SDIO_DATA_BLOCKSIZE_1B; - dataConfig->transferDir = SDIO_TRANSFER_DIR_TOCARD; - dataConfig->transferMode = SDIO_TRANSFER_MODE_BLOCK; - dataConfig->DPSM = SDIO_DPSM_DISABLE; + dataConfig->dataTimeOut = 0xFFFFFFFF; + dataConfig->dataLength = 0x00; + dataConfig->dataBlockSize = SDIO_DATA_BLOCKSIZE_1B; + dataConfig->transferDir = SDIO_TRANSFER_DIR_TO_CARD; + dataConfig->transferMode = SDIO_TRANSFER_MODE_BLOCK; + dataConfig->DPSM = SDIO_DPSM_DISABLE; } /*! @@ -289,7 +300,7 @@ uint32_t SDIO_ReadDataCounter(void) /*! * @brief Write the SDIO Data * - * @param Data : Write 32-bit data + * @param Data：Write 32-bit data * * @retval None */ @@ -380,11 +391,10 @@ void SDIO_DisableStartReadWait(void) * * @retval None * - * @note */ void SDIO_ConfigSDIOReadWaitMode(SDIO_READ_WAIT_MODE_T readWaitMode) { - *(__IO uint32_t *) DCTRL_RDWAIT_BB = readWaitMode; + *(__IO uint32_t *) DCTRL_RDWAIT_BB = readWaitMode; } /*! * @brief Enables SDIO SD I/O Mode Operation @@ -395,7 +405,7 @@ void SDIO_ConfigSDIOReadWaitMode(SDIO_READ_WAIT_MODE_T readWaitMode) */ void SDIO_EnableSDIO(void) { - *(__IO uint32_t *) DCTRL_SDIOF_BB = (uint32_t)SET; + *(__IO uint32_t *) DCTRL_SDIOF_BB = (uint32_t)SET; } /*! @@ -407,7 +417,7 @@ void SDIO_EnableSDIO(void) */ void SDIO_DisableSDIO(void) { - *(__IO uint32_t *) DCTRL_SDIOF_BB = (uint32_t)RESET; + *(__IO uint32_t *) DCTRL_SDIOF_BB = (uint32_t)RESET; } /*! @@ -612,17 +622,7 @@ void SDIO_DisableInterrupt(uint32_t interrupt) */ uint8_t SDIO_ReadStatusFlag(SDIO_FLAG_T flag) { - uint8_t bitstatus = RESET; - - if ((SDIO->STS & flag) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; + return (SDIO->STS & flag) ? SET : RESET; } /*! @@ -648,7 +648,7 @@ uint8_t SDIO_ReadStatusFlag(SDIO_FLAG_T flag) */ void SDIO_ClearStatusFlag(uint32_t flag) { - SDIO->ICF = flag; + SDIO->ICF = flag; } /*! @@ -722,7 +722,7 @@ uint8_t SDIO_ReadIntFlag(SDIO_INT_T flag) */ void SDIO_ClearIntFlag(uint32_t flag) { - SDIO->ICF = flag; + SDIO->ICF = flag; } /**@} end of group SDIO_Fuctions*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_spi.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_spi.c index 079685b148..1588cc17ab 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_spi.c +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_spi.c @@ -3,10 +3,24 @@ * * @brief This file provides all the SPI firmware functions * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ #include "apm32f10x_spi.h" @@ -31,19 +45,19 @@ * * @retval None */ -void SPI_I2S_Reset(SPI_T* spi) +void SPI_I2S_Reset(SPI_T *spi) { - if(spi == SPI1) + if (spi == SPI1) { RCM_EnableAPB2PeriphReset(RCM_APB2_PERIPH_SPI1); RCM_DisableAPB2PeriphReset(RCM_APB2_PERIPH_SPI1); } - else if(spi == SPI2) + else if (spi == SPI2) { RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_SPI2); RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_SPI2); } - else if(spi == SPI3) + else if (spi == SPI3) { RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_SPI3); RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_SPI3); @@ -59,13 +73,13 @@ void SPI_I2S_Reset(SPI_T* spi) * * @retval None */ -void SPI_Config(SPI_T* spi, SPI_Config_T* spiConfig) +void SPI_Config(SPI_T *spi, SPI_Config_T *spiConfig) { spi->CTRL1 &= 0x3040; spi->CTRL1 |= (uint16_t)((uint32_t)spiConfig->direction | spiConfig->mode | - spiConfig->length | spiConfig->polarity | - spiConfig->phase | spiConfig->nss | - spiConfig->baudrateDiv | spiConfig->firstBit); + spiConfig->length | spiConfig->polarity | + spiConfig->phase | spiConfig->nss | + spiConfig->baudrateDiv | spiConfig->firstBit); spi->CRCPOLY = spiConfig->crcPolynomial; } @@ -78,24 +92,24 @@ void SPI_Config(SPI_T* spi, SPI_Config_T* spiConfig) * * @retval None */ -void I2S_Config(SPI_T* spi, I2S_Config_T* i2sConfig) +void I2S_Config(SPI_T *spi, I2S_Config_T *i2sConfig) { uint16_t i2sDiv = 2, i2sOdd = 0, packetSize = 1; uint32_t tmp = 0; uint32_t sysClock = 0; - /* Clear MODESEL, I2SEN, I2SMOD, PFSSEL, I2SSSEL, CPOL, DATALEN and CHLEN bits */ + /** Clear MODESEL, I2SEN, I2SMOD, PFSSEL, I2SSSEL, CPOL, DATALEN and CHLEN bits */ spi->I2SCFG &= 0xF040; spi->I2SPSC = 0x0002; - if(i2sConfig->audioDiv == I2S_AUDIO_DIV_DEFAULT) + if (i2sConfig->audioDiv == I2S_AUDIO_DIV_DEFAULT) { spi->I2SPSC_B.ODDPSC = 0; spi->I2SPSC_B.I2SPSC = 2; } else { - if(i2sConfig->length == I2S_DATA_LENGHT_16B) + if (i2sConfig->length == I2S_DATA_LENGHT_16B) { packetSize = 1; } @@ -106,13 +120,13 @@ void I2S_Config(SPI_T* spi, I2S_Config_T* i2sConfig) sysClock = RCM_ReadSYSCLKFreq(); - if(i2sConfig->MCLKOutput == I2S_MCLK_OUTPUT_ENABLE) + if (i2sConfig->MCLKOutput == I2S_MCLK_OUTPUT_ENABLE) { tmp = (uint16_t)(((((sysClock / 256) * 10) / i2sConfig ->audioDiv)) + 5); } else { - tmp = (uint16_t)(((((sysClock / (32 * packetSize)) *10 ) / i2sConfig ->audioDiv )) + 5); + tmp = (uint16_t)(((((sysClock / (32 * packetSize)) * 10) / i2sConfig ->audioDiv)) + 5); } tmp = tmp / 10; @@ -130,7 +144,10 @@ void I2S_Config(SPI_T* spi, I2S_Config_T* i2sConfig) spi->I2SPSC_B.ODDPSC = i2sOdd; spi->I2SPSC |= i2sConfig->MCLKOutput; - spi->I2SCFG = i2sConfig->mode | i2sConfig->standard | i2sConfig->length | i2sConfig->polarity; + spi->I2SCFG = (uint32_t)i2sConfig->mode | \ + (uint32_t)i2sConfig->standard | \ + (uint32_t)i2sConfig->length | \ + (uint32_t)i2sConfig->polarity; /** select I2S mode */ spi->I2SCFG_B.MODESEL = BIT_SET; @@ -143,7 +160,7 @@ void I2S_Config(SPI_T* spi, I2S_Config_T* i2sConfig) * * @retval None */ -void SPI_ConfigStructInit(SPI_Config_T* spiConfig) +void SPI_ConfigStructInit(SPI_Config_T *spiConfig) { spiConfig->direction = SPI_DIRECTION_2LINES_FULLDUPLEX; spiConfig->mode = SPI_MODE_SLAVE; @@ -163,7 +180,7 @@ void SPI_ConfigStructInit(SPI_Config_T* spiConfig) * * @retval None */ -void I2S_ConfigStructInit(I2S_Config_T* i2sConfig) +void I2S_ConfigStructInit(I2S_Config_T *i2sConfig) { i2sConfig->mode = I2S_MODE_SLAVE_TX; i2sConfig->standard = I2S_STANDARD_PHILLIPS; @@ -179,7 +196,7 @@ void I2S_ConfigStructInit(I2S_Config_T* i2sConfig) * * @retval None */ -void SPI_Enable(SPI_T* spi) +void SPI_Enable(SPI_T *spi) { spi->CTRL1_B.SPIEN = BIT_SET; } @@ -191,7 +208,7 @@ void SPI_Enable(SPI_T* spi) * * @retval None */ -void SPI_Disable(SPI_T* spi) +void SPI_Disable(SPI_T *spi) { spi->CTRL1_B.SPIEN = BIT_RESET; } @@ -203,7 +220,7 @@ void SPI_Disable(SPI_T* spi) * * @retval None */ -void I2S_Enable(SPI_T* spi) +void I2S_Enable(SPI_T *spi) { spi->I2SCFG_B.I2SEN = BIT_SET; } @@ -215,7 +232,7 @@ void I2S_Enable(SPI_T* spi) * * @retval None */ -void I2S_Disable(SPI_T* spi) +void I2S_Disable(SPI_T *spi) { spi->I2SCFG_B.I2SEN = BIT_RESET; } @@ -231,9 +248,9 @@ void I2S_Disable(SPI_T* spi) * @arg SPI_I2S_DMA_REQ_RX: Rx buffer DMA transfer request * @retval None */ -void SPI_I2S_EnableDMA(SPI_T* spi, SPI_I2S_DMA_REQ_T dmaReq) +void SPI_I2S_EnableDMA(SPI_T *spi, SPI_I2S_DMA_REQ_T dmaReq) { - if(dmaReq == SPI_I2S_DMA_REQ_TX) + if (dmaReq == SPI_I2S_DMA_REQ_TX) { spi->CTRL2_B.TXDEN = ENABLE; } @@ -254,9 +271,9 @@ void SPI_I2S_EnableDMA(SPI_T* spi, SPI_I2S_DMA_REQ_T dmaReq) * @arg SPI_I2S_DMA_REQ_RX: Rx buffer DMA transfer request * @retval None */ -void SPI_I2S_DisableDMA(SPI_T* spi, SPI_I2S_DMA_REQ_T dmaReq) +void SPI_I2S_DisableDMA(SPI_T *spi, SPI_I2S_DMA_REQ_T dmaReq) { - if(dmaReq == SPI_I2S_DMA_REQ_TX) + if (dmaReq == SPI_I2S_DMA_REQ_TX) { spi->CTRL2_B.TXDEN = DISABLE; } @@ -275,7 +292,7 @@ void SPI_I2S_DisableDMA(SPI_T* spi, SPI_I2S_DMA_REQ_T dmaReq) * * @retval None */ -void SPI_I2S_TxData(SPI_T* spi, uint16_t data) +void SPI_I2S_TxData(SPI_T *spi, uint16_t data) { spi->DATA = data; } @@ -289,7 +306,7 @@ void SPI_I2S_TxData(SPI_T* spi, uint16_t data) * * @retval None */ -uint16_t SPI_I2S_RxData(SPI_T* spi) +uint16_t SPI_I2S_RxData(SPI_T *spi) { return spi->DATA; } @@ -301,7 +318,7 @@ uint16_t SPI_I2S_RxData(SPI_T* spi) * * @retval None */ -void SPI_SetSoftwareNSS(SPI_T* spi) +void SPI_SetSoftwareNSS(SPI_T *spi) { spi->CTRL1_B.ISSEL = BIT_SET; } @@ -313,7 +330,7 @@ void SPI_SetSoftwareNSS(SPI_T* spi) * * @retval None */ -void SPI_ResetSoftwareNSS(SPI_T* spi) +void SPI_ResetSoftwareNSS(SPI_T *spi) { spi->CTRL1_B.ISSEL = BIT_RESET; } @@ -325,7 +342,7 @@ void SPI_ResetSoftwareNSS(SPI_T* spi) * * @retval None */ -void SPI_EnableSSOutput(SPI_T* spi) +void SPI_EnableSSOutput(SPI_T *spi) { spi->CTRL2_B.SSOEN = BIT_SET; } @@ -337,7 +354,7 @@ void SPI_EnableSSOutput(SPI_T* spi) * * @retval None */ -void SPI_DisableSSOutput(SPI_T* spi) +void SPI_DisableSSOutput(SPI_T *spi) { spi->CTRL2_B.SSOEN = BIT_RESET; } @@ -347,11 +364,14 @@ void SPI_DisableSSOutput(SPI_T* spi) * * @param spi: The SPIx can be 1,2,3 * - * @param length: Select the SPI data Size + * @param length: specifies the SPI data size. + * This parameter can be one of the following values: + * @arg SPI_DATA_LENGTH_16B: Set data frame format to 16bit + * @arg SPI_DATA_LENGTH_8B : Set data frame format to 8bit * * @retval None */ -void SPI_ConfigDataSize(SPI_T* spi, uint16_t length) +void SPI_ConfigDataSize(SPI_T *spi, SPI_DATA_LENGTH_T length) { spi->CTRL1_B.DFLSEL = BIT_RESET; spi->CTRL1 |= length; @@ -364,9 +384,9 @@ void SPI_ConfigDataSize(SPI_T* spi, uint16_t length) * * @retval None */ -void SPI_TxCRC(SPI_T* spi) +void SPI_TxCRC(SPI_T *spi) { - spi->CTRL1_B.CECNXT = BIT_SET; + spi->CTRL1_B.CRCNXT = BIT_SET; } /*! @@ -376,7 +396,7 @@ void SPI_TxCRC(SPI_T* spi) * * @retval None */ -void SPI_EnableCRC(SPI_T* spi) +void SPI_EnableCRC(SPI_T *spi) { spi->CTRL1_B.CRCEN = BIT_SET; } @@ -387,7 +407,7 @@ void SPI_EnableCRC(SPI_T* spi) * @param spi: The SPIx can be 1,2,3 * */ -void SPI_DisableCRC(SPI_T* spi) +void SPI_DisableCRC(SPI_T *spi) { spi->CTRL1_B.CRCEN = BIT_RESET; } @@ -399,7 +419,7 @@ void SPI_DisableCRC(SPI_T* spi) * * @retval The SPI transmit CRC register value */ -uint16_t SPI_ReadTxCRC(SPI_T* spi) +uint16_t SPI_ReadTxCRC(SPI_T *spi) { return spi->TXCRC_B.TXCRC; } @@ -411,7 +431,7 @@ uint16_t SPI_ReadTxCRC(SPI_T* spi) * * @retval The SPI receive CRC register value */ -uint16_t SPI_ReadRxCRC(SPI_T* spi) +uint16_t SPI_ReadRxCRC(SPI_T *spi) { return spi->RXCRC_B.RXCRC; } @@ -423,7 +443,7 @@ uint16_t SPI_ReadRxCRC(SPI_T* spi) * * @retval The SPI CRC Polynomial register value */ -uint16_t SPI_ReadCRCPolynomial(SPI_T* spi) +uint16_t SPI_ReadCRCPolynomial(SPI_T *spi) { return spi->CRCPOLY_B.CRCPOLY; } @@ -439,9 +459,9 @@ uint16_t SPI_ReadCRCPolynomial(SPI_T* spi) * @arg SPI_DIRECTION_TX: Selects Tx transmission direction * @retval None */ -void SPI_ConfigBiDirectionalLine(SPI_T* spi, SPI_DIRECTION_SELECT_T direction) +void SPI_ConfigBiDirectionalLine(SPI_T *spi, SPI_DIRECTION_SELECT_T direction) { - if(direction == SPI_DIRECTION_TX) + if (direction == SPI_DIRECTION_TX) { spi->CTRL1 |= SPI_DIRECTION_TX; } @@ -463,9 +483,9 @@ void SPI_ConfigBiDirectionalLine(SPI_T* spi, SPI_DIRECTION_SELECT_T direction) * @arg SPI_I2S_INT_ERR: Error interrupt * @retval None */ -void SPI_I2S_EnableInterrupt(SPI_T* spi, SPI_I2S_INT_T interrupt) +void SPI_I2S_EnableInterrupt(SPI_T *spi, SPI_I2S_INT_T interrupt) { - spi->CTRL2 |= (interrupt >> 8); + spi->CTRL2 |= (interrupt >> 8); } /*! @@ -480,9 +500,9 @@ void SPI_I2S_EnableInterrupt(SPI_T* spi, SPI_I2S_INT_T interrupt) * @arg SPI_I2S_INT_ERR: Error interrupt * @retval None */ -void SPI_I2S_DisableInterrupt(SPI_T* spi, SPI_I2S_INT_T interrupt) +void SPI_I2S_DisableInterrupt(SPI_T *spi, SPI_I2S_INT_T interrupt) { - spi->CTRL2 &= ~(interrupt >> 8); + spi->CTRL2 &= ~(interrupt >> 8); } /*! @@ -503,9 +523,9 @@ void SPI_I2S_DisableInterrupt(SPI_T* spi, SPI_I2S_INT_T interrupt) * * @retval SET or RESET */ -uint8_t SPI_I2S_ReadStatusFlag(SPI_T* spi, SPI_FLAG_T flag) +uint8_t SPI_I2S_ReadStatusFlag(SPI_T *spi, SPI_FLAG_T flag) { - if((spi->STS & flag) != RESET) + if ((spi->STS & flag) != RESET) { return SET; } @@ -533,7 +553,7 @@ uint8_t SPI_I2S_ReadStatusFlag(SPI_T* spi, SPI_FLAG_T flag) * a read/write operation to SPI_STS register (SPI_I2S_ReadStatusFlag()) * followed by a write operation to SPI_CTRL1 register (SPI_Enable()). */ -void SPI_I2S_ClearStatusFlag(SPI_T* spi, SPI_FLAG_T flag) +void SPI_I2S_ClearStatusFlag(SPI_T *spi, SPI_FLAG_T flag) { spi->STS_B.CRCEFLG = BIT_RESET; } @@ -554,12 +574,12 @@ void SPI_I2S_ClearStatusFlag(SPI_T* spi, SPI_FLAG_T flag) * * @retval SET or RESET */ -uint8_t SPI_I2S_ReadIntFlag(SPI_T* spi, SPI_I2S_INT_T flag) +uint8_t SPI_I2S_ReadIntFlag(SPI_T *spi, SPI_I2S_INT_T flag) { uint32_t intEnable; uint32_t intStatus; - intEnable = (uint32_t)(spi->CTRL2 & (flag>>8)); + intEnable = (uint32_t)(spi->CTRL2 & (flag >> 8)); intStatus = (uint32_t)(spi->STS & flag); if (intEnable && intStatus) @@ -588,7 +608,7 @@ uint8_t SPI_I2S_ReadIntFlag(SPI_T* spi, SPI_I2S_INT_T flag) * a read/write operation to SPI_STS register (SPI_I2S_ReadIntFlag()) * followed by a write operation to SPI_CTRL1 register (SPI_Enable()). */ -void SPI_I2S_ClearIntFlag(SPI_T* spi, SPI_I2S_INT_T flag) +void SPI_I2S_ClearIntFlag(SPI_T *spi, SPI_I2S_INT_T flag) { spi->STS_B.CRCEFLG = BIT_RESET; } diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_tmr.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_tmr.c index 343cb19770..50a1449c36 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_tmr.c +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_tmr.c @@ -1,12 +1,26 @@ /*! - * @file apm32f10x_tmr.c + * @file apm32f10x_tmr.c * - * @brief This file provides all the TMR firmware functions. + * @brief This file provides all the TMR firmware functions. * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ #include "apm32f10x_tmr.h" @@ -24,10 +38,10 @@ @{ */ -static void TI1Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter); -static void TI2Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter); -static void TI3Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter); -static void TI4Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter); +static void TI1Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter); +static void TI2Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter); +static void TI3Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter); +static void TI4Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter); /*! * @brief Deinitializes the TMRx peripheral registers to their default reset values. @@ -36,9 +50,8 @@ static void TI4Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uin * * @retval None * - * @note */ -void TMR_Reset(TMR_T* tmr) +void TMR_Reset(TMR_T *tmr) { if (tmr == TMR1) { @@ -91,12 +104,12 @@ void TMR_Reset(TMR_T* tmr) * * @retval None */ -void TMR_ConfigTimeBase(TMR_T* tmr, TMR_BaseConfig_T* baseConfig) +void TMR_ConfigTimeBase(TMR_T *tmr, TMR_BaseConfig_T *baseConfig) { uint16_t temp; if ((tmr == TMR1) || (tmr == TMR8) || (tmr == TMR2) || (tmr == TMR3) || - (tmr == TMR4) || (tmr == TMR5)) + (tmr == TMR4) || (tmr == TMR5)) { temp = tmr->CTRL1; temp &= 0x038F; @@ -116,7 +129,7 @@ void TMR_ConfigTimeBase(TMR_T* tmr, TMR_BaseConfig_T* baseConfig) { tmr->REPCNT = baseConfig->repetitionCounter; } - tmr->CEG_B.BEG = 0x01; + tmr->CEG_B.UEG = 0x01; } /*! @@ -124,31 +137,31 @@ void TMR_ConfigTimeBase(TMR_T* tmr, TMR_BaseConfig_T* baseConfig) * * @param tmr: The TMRx can be 1 to 8 except 6 and 7 * - * @param OC1Config: Pointer to a TMR_OCConfig_T structure + * @param OCConfig: Pointer to a TMR_OCConfig_T structure * * @retval None */ -void TMR_ConfigOC1(TMR_T* tmr, TMR_OCConfig_T* OC1Config) +void TMR_ConfigOC1(TMR_T *tmr, TMR_OCConfig_T *OCConfig) { tmr->CCEN_B.CC1EN = BIT_RESET; tmr->CCM1_COMPARE_B.CC1SEL = BIT_RESET; - tmr->CCM1_COMPARE_B.OC1MOD = OC1Config->mode; + tmr->CCM1_COMPARE_B.OC1MOD = OCConfig->mode; - tmr->CCEN_B.CC1POL = OC1Config->polarity; - tmr->CCEN_B.CC1EN = OC1Config->outputState; + tmr->CCEN_B.CC1POL = OCConfig->polarity; + tmr->CCEN_B.CC1EN = OCConfig->outputState; if ((tmr == TMR1) || (tmr == TMR8)) { - tmr->CCEN_B.CC1NPOL = OC1Config->nPolarity; - tmr->CCEN_B.CC1NEN = OC1Config->outputNState; + tmr->CCEN_B.CC1NPOL = OCConfig->nPolarity; + tmr->CCEN_B.CC1NEN = OCConfig->outputNState; tmr->CTRL2_B.OC1OIS = BIT_RESET; tmr->CTRL2_B.OC1NOIS = BIT_RESET; - tmr->CTRL2_B.OC1OIS = OC1Config->idleState; - tmr->CTRL2_B.OC1NOIS = OC1Config->nIdleState; + tmr->CTRL2_B.OC1OIS = OCConfig->idleState; + tmr->CTRL2_B.OC1NOIS = OCConfig->nIdleState; } - tmr->CC1 = OC1Config->pulse; + tmr->CC1 = OCConfig->pulse; } /*! @@ -156,36 +169,36 @@ void TMR_ConfigOC1(TMR_T* tmr, TMR_OCConfig_T* OC1Config) * * @param tmr: The TMRx can be 1 to 8 except 6 and 7 * - * @param OC2Config: Pointer to a TMR_OCConfig_T structure + * @param OCConfig: Pointer to a TMR_OCConfig_T structure * * @retval None */ -void TMR_ConfigOC2(TMR_T* tmr, TMR_OCConfig_T* OC2Config) +void TMR_ConfigOC2(TMR_T *tmr, TMR_OCConfig_T *OCConfig) { tmr->CCEN_B.CC2EN = BIT_RESET; tmr->CCM1_COMPARE_B.OC2MOD = BIT_RESET; tmr->CCM1_COMPARE_B.CC2SEL = BIT_RESET; - tmr->CCM1_COMPARE_B.OC2MOD = OC2Config->mode; + tmr->CCM1_COMPARE_B.OC2MOD = OCConfig->mode; tmr->CCEN_B.CC2POL = BIT_RESET; - tmr->CCEN_B.CC2POL = OC2Config->polarity; - tmr->CCEN_B.CC2EN = OC2Config->outputState; + tmr->CCEN_B.CC2POL = OCConfig->polarity; + tmr->CCEN_B.CC2EN = OCConfig->outputState; if ((tmr == TMR1) || (tmr == TMR8)) { tmr->CCEN_B.CC2NPOL = BIT_RESET; - tmr->CCEN_B.CC2NPOL = OC2Config->nPolarity; + tmr->CCEN_B.CC2NPOL = OCConfig->nPolarity; tmr->CCEN_B.CC2NEN = BIT_RESET; - tmr->CCEN_B.CC2NEN = OC2Config->outputNState; + tmr->CCEN_B.CC2NEN = OCConfig->outputNState; tmr->CTRL2_B.OC2OIS = BIT_RESET; tmr->CTRL2_B.OC2NOIS = BIT_RESET; - tmr->CTRL2_B.OC2OIS = OC2Config->idleState; - tmr->CTRL2_B.OC2NOIS = OC2Config->nIdleState; + tmr->CTRL2_B.OC2OIS = OCConfig->idleState; + tmr->CTRL2_B.OC2NOIS = OCConfig->nIdleState; } - tmr->CC2 = OC2Config->pulse; + tmr->CC2 = OCConfig->pulse; } /*! @@ -193,35 +206,35 @@ void TMR_ConfigOC2(TMR_T* tmr, TMR_OCConfig_T* OC2Config) * * @param tmr: The TMRx can be 1 to 8 except 6 and 7 * - * @param OC3Config: Pointer to a TMR_OCConfig_T structure + * @param OCConfig: Pointer to a TMR_OCConfig_T structure * * @retval None */ -void TMR_ConfigOC3(TMR_T* tmr, TMR_OCConfig_T* OC3Config) +void TMR_ConfigOC3(TMR_T *tmr, TMR_OCConfig_T *OCConfig) { tmr->CCEN_B.CC3EN = BIT_RESET; - tmr->CCM2_COMPARE_B.OC3MODE = BIT_RESET; + tmr->CCM2_COMPARE_B.OC3MOD = BIT_RESET; tmr->CCM2_COMPARE_B.CC3SEL = BIT_RESET; - tmr->CCM2_COMPARE_B.OC3MODE = OC3Config->mode; + tmr->CCM2_COMPARE_B.OC3MOD = OCConfig->mode; tmr->CCEN_B.CC3POL = BIT_RESET; - tmr->CCEN_B.CC3POL = OC3Config->polarity; - tmr->CCEN_B.CC3EN = OC3Config->outputState; + tmr->CCEN_B.CC3POL = OCConfig->polarity; + tmr->CCEN_B.CC3EN = OCConfig->outputState; if ((tmr == TMR1) || (tmr == TMR8)) { tmr->CCEN_B.CC3NPOL = BIT_RESET; - tmr->CCEN_B.CC3NPOL = OC3Config->nPolarity; + tmr->CCEN_B.CC3NPOL = OCConfig->nPolarity; tmr->CCEN_B.CC3NEN = BIT_RESET; - tmr->CCEN_B.CC3NEN = OC3Config->outputNState; + tmr->CCEN_B.CC3NEN = OCConfig->outputNState; tmr->CTRL2_B.OC3OIS = BIT_RESET; tmr->CTRL2_B.OC3NOIS = BIT_RESET; - tmr->CTRL2_B.OC3OIS = OC3Config->idleState; - tmr->CTRL2_B.OC3NOIS = OC3Config->nIdleState; + tmr->CTRL2_B.OC3OIS = OCConfig->idleState; + tmr->CTRL2_B.OC3NOIS = OCConfig->nIdleState; } - tmr->CC3 = OC3Config->pulse; + tmr->CC3 = OCConfig->pulse; } /*! @@ -229,28 +242,28 @@ void TMR_ConfigOC3(TMR_T* tmr, TMR_OCConfig_T* OC3Config) * * @param tmr: The TMRx can be 1 to 8 except 6 and 7 * - * @param OC4Config: Pointer to a TMR_OCConfig_T structure + * @param OCConfig: Pointer to a TMR_OCConfig_T structure * * @retval None */ -void TMR_ConfigOC4(TMR_T* tmr, TMR_OCConfig_T* OC4Config) +void TMR_ConfigOC4(TMR_T *tmr, TMR_OCConfig_T *OCConfig) { tmr->CCEN_B.CC4EN = BIT_RESET; - tmr->CCM2_COMPARE_B.OC4MODE = BIT_RESET; + tmr->CCM2_COMPARE_B.OC4MOD = BIT_RESET; tmr->CCM2_COMPARE_B.CC4SEL = BIT_RESET; - tmr->CCM2_COMPARE_B.OC4MODE = OC4Config->mode; + tmr->CCM2_COMPARE_B.OC4MOD = OCConfig->mode; tmr->CCEN_B.CC4POL = BIT_RESET; - tmr->CCEN_B.CC4POL = OC4Config->polarity; - tmr->CCEN_B.CC4EN = OC4Config->outputState; + tmr->CCEN_B.CC4POL = OCConfig->polarity; + tmr->CCEN_B.CC4EN = OCConfig->outputState; if ((tmr == TMR1) || (tmr == TMR8)) { tmr->CTRL2_B.OC4OIS = BIT_RESET; - tmr->CTRL2_B.OC4OIS = OC4Config->idleState; + tmr->CTRL2_B.OC4OIS = OCConfig->idleState; } - tmr->CC4 = OC4Config->pulse; + tmr->CC4 = OCConfig->pulse; } /*! @@ -262,7 +275,7 @@ void TMR_ConfigOC4(TMR_T* tmr, TMR_OCConfig_T* OC4Config) * * @retval None */ -void TMR_ConfigIC(TMR_T* tmr, TMR_ICConfig_T* ICConfig) +void TMR_ConfigIC(TMR_T *tmr, TMR_ICConfig_T *ICConfig) { if (ICConfig->channel == TMR_CHANNEL_1) { @@ -295,15 +308,15 @@ void TMR_ConfigIC(TMR_T* tmr, TMR_ICConfig_T* ICConfig) * * @retval None */ -void TMR_ConfigBDT(TMR_T* tmr, TMR_BDTConfig_T* BDTConfig) +void TMR_ConfigBDT(TMR_T *tmr, TMR_BDTConfig_T *BDTConfig) { - tmr->BDT = (BDTConfig->IMOS)<<10 |\ - (BDTConfig->RMOS)<<11 |\ - (BDTConfig->lockLevel)<<8 |\ - (BDTConfig->deadTime) |\ - (BDTConfig->BRKState)<<12 |\ - (BDTConfig->BRKPolarity)<<13 |\ - (BDTConfig->automaticOutput)<<14; + tmr->BDT = (BDTConfig->IMOS) << 10 | \ + (BDTConfig->RMOS) << 11 | \ + (BDTConfig->lockLevel) << 8 | \ + (BDTConfig->deadTime) | \ + (BDTConfig->BRKState) << 12 | \ + (BDTConfig->BRKPolarity) << 13 | \ + (BDTConfig->automaticOutput) << 14; } /*! @@ -313,7 +326,7 @@ void TMR_ConfigBDT(TMR_T* tmr, TMR_BDTConfig_T* BDTConfig) * * @retval None */ -void TMR_ConfigTimeBaseStructInit(TMR_BaseConfig_T* baseConfig) +void TMR_ConfigTimeBaseStructInit(TMR_BaseConfig_T *baseConfig) { baseConfig->period = 0xFFFF; baseConfig->division = 0x0000; @@ -329,7 +342,7 @@ void TMR_ConfigTimeBaseStructInit(TMR_BaseConfig_T* baseConfig) * * @retval None */ -void TMR_ConfigOCStructInit(TMR_OCConfig_T* OCConfig) +void TMR_ConfigOCStructInit(TMR_OCConfig_T *OCConfig) { OCConfig->mode = TMR_OC_MODE_TMRING; OCConfig->outputState = TMR_OC_STATE_DISABLE; @@ -348,7 +361,7 @@ void TMR_ConfigOCStructInit(TMR_OCConfig_T* OCConfig) * * @retval None */ -void TMR_ConfigICStructInit(TMR_ICConfig_T* ICConfig) +void TMR_ConfigICStructInit(TMR_ICConfig_T *ICConfig) { ICConfig->channel = TMR_CHANNEL_1; ICConfig->polarity = TMR_IC_POLARITY_RISING; @@ -364,7 +377,7 @@ void TMR_ConfigICStructInit(TMR_ICConfig_T* ICConfig) * * @retval None */ -void TMR_ConfigBDTStructInit( TMR_BDTConfig_T* BDTConfig) +void TMR_ConfigBDTStructInit(TMR_BDTConfig_T *BDTConfig) { BDTConfig->RMOS = TMR_RMOS_STATE_DISABLE; BDTConfig->IMOS = TMR_IMOS_STATE_DISABLE; @@ -382,7 +395,7 @@ void TMR_ConfigBDTStructInit( TMR_BDTConfig_T* BDTConfig) * * @retval None */ -void TMR_Enable(TMR_T* tmr) +void TMR_Enable(TMR_T *tmr) { tmr->CTRL1_B.CNTEN = ENABLE; } @@ -394,7 +407,7 @@ void TMR_Enable(TMR_T* tmr) * * @retval None */ -void TMR_Disable(TMR_T* tmr) +void TMR_Disable(TMR_T *tmr) { tmr->CTRL1_B.CNTEN = DISABLE; } @@ -408,7 +421,7 @@ void TMR_Disable(TMR_T* tmr) * * @retval None */ -void TMR_ConfigPWM(TMR_T* tmr, TMR_ICConfig_T* PWMConfig) +void TMR_ConfigPWM(TMR_T *tmr, TMR_ICConfig_T *PWMConfig) { uint16_t icpolarity = TMR_IC_POLARITY_RISING; uint16_t icselection = TMR_IC_SELECTION_DIRECT_TI; @@ -454,7 +467,7 @@ void TMR_ConfigPWM(TMR_T* tmr, TMR_ICConfig_T* PWMConfig) * * @retval None */ -void TMR_EnablePWMOutputs(TMR_T* tmr) +void TMR_EnablePWMOutputs(TMR_T *tmr) { tmr->BDT_B.MOEN = ENABLE; } @@ -466,7 +479,7 @@ void TMR_EnablePWMOutputs(TMR_T* tmr) * * @retval None */ -void TMR_DisablePWMOutputs(TMR_T* tmr) +void TMR_DisablePWMOutputs(TMR_T *tmr) { tmr->BDT_B.MOEN = DISABLE; } @@ -482,9 +495,9 @@ void TMR_DisablePWMOutputs(TMR_T* tmr) * * @retval None */ -void TMR_ConfigDMA(TMR_T* tmr, TMR_DMA_BASE_T baseAddress, TMR_DMA_BURSTLENGTH_T burstLength) +void TMR_ConfigDMA(TMR_T *tmr, TMR_DMA_BASE_T baseAddress, TMR_DMA_BURSTLENGTH_T burstLength) { - tmr->DCTRL = baseAddress | burstLength; + tmr->DCTRL = (uint32_t)baseAddress | (uint32_t)burstLength; } /*! @@ -503,9 +516,8 @@ void TMR_ConfigDMA(TMR_T* tmr, TMR_DMA_BASE_T baseAddress, TMR_DMA_BURSTLENGTH_T * @arg TMR_DMA_SOURCE_TRG: TMR Trigger DMA souces * @retval None * - * @note */ -void TMR_EnableDMASoure(TMR_T* tmr, uint16_t dmaSource) +void TMR_EnableDMASoure(TMR_T *tmr, uint16_t dmaSource) { tmr->DIEN |= dmaSource; } @@ -526,9 +538,8 @@ void TMR_EnableDMASoure(TMR_T* tmr, uint16_t dmaSource) * @arg TMR_DMA_SOURCE_TRG: TMR Trigger DMA souces * @retval None * - * @note */ -void TMR_DisableDMASoure(TMR_T* tmr, uint16_t dmaSource) +void TMR_DisableDMASoure(TMR_T *tmr, uint16_t dmaSource) { tmr->DIEN &= ~dmaSource; } @@ -540,7 +551,7 @@ void TMR_DisableDMASoure(TMR_T* tmr, uint16_t dmaSource) * * @retval None */ -void TMR_ConfigInternalClock(TMR_T* tmr) +void TMR_ConfigInternalClock(TMR_T *tmr) { tmr->SMCTRL_B.SMFSEL = DISABLE; } @@ -558,7 +569,7 @@ void TMR_ConfigInternalClock(TMR_T* tmr) * @arg TMR_TRIGGER_SOURCE_ITR3: TMR Internal Trigger 3 * @retval None */ -void TMR_ConfigIntTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource) +void TMR_ConfigIntTrigExternalClock(TMR_T *tmr, TMR_TRIGGER_SOURCE_T triggerSource) { TMR_SelectInputTrigger(tmr, triggerSource); tmr->SMCTRL_B.SMFSEL = 0x07; @@ -584,8 +595,8 @@ void TMR_ConfigIntTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSour * * @retval None */ -void TMR_ConfigTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource, - TMR_IC_POLARITY_T ICpolarity, uint16_t ICfilter) +void TMR_ConfigTrigExternalClock(TMR_T *tmr, TMR_TRIGGER_SOURCE_T triggerSource, + TMR_IC_POLARITY_T ICpolarity, uint16_t ICfilter) { if (triggerSource == 0x06) { @@ -621,7 +632,7 @@ void TMR_ConfigTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource, * * @retval None */ -void TMR_ConfigETRClockMode1(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler, +void TMR_ConfigETRClockMode1(TMR_T *tmr, TMR_EXTTRG_PSC_T prescaler, TMR_EXTTRG_POL_T polarity, uint16_t filter) { TMR_ConfigETR(tmr, prescaler, polarity, filter); @@ -651,7 +662,7 @@ void TMR_ConfigETRClockMode1(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler, * * @retval None */ -void TMR_ConfigETRClockMode2(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler, +void TMR_ConfigETRClockMode2(TMR_T *tmr, TMR_EXTTRG_PSC_T prescaler, TMR_EXTTRG_POL_T polarity, uint16_t filter) { TMR_ConfigETR(tmr, prescaler, polarity, filter); @@ -678,7 +689,7 @@ void TMR_ConfigETRClockMode2(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler, * * @retval None */ -void TMR_ConfigETR(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler, +void TMR_ConfigETR(TMR_T *tmr, TMR_EXTTRG_PSC_T prescaler, TMR_EXTTRG_POL_T polarity, uint16_t filter) { tmr->SMCTRL &= 0x00FF; @@ -696,11 +707,11 @@ void TMR_ConfigETR(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler, * * @param pscReloadMode: specifies the TMR prescaler Reload mode * The parameter can be one of following values: - * @arg TMR_PRESCALER_RELOAD_UPDATA: The Prescaler is loaded at the update event - * @arg TMR_PRESCALER_RELOAD_IMMEDIATE: The Prescaler is loaded immediately + * @arg TMR_PSC_RELOAD_UPDATE: The Prescaler is loaded at the update event + * @arg TMR_PSC_RELOAD_IMMEDIATE: The Prescaler is loaded immediately * @retval None */ -void TMR_ConfigPrescaler(TMR_T* tmr, uint16_t prescaler, TMR_PRESCALER_RELOAD_T pscReloadMode) +void TMR_ConfigPrescaler(TMR_T *tmr, uint16_t prescaler, TMR_PSC_RELOAD_T pscReloadMode) { tmr->PSC = prescaler; tmr->CEG_B.UEG = pscReloadMode; @@ -720,7 +731,7 @@ void TMR_ConfigPrescaler(TMR_T* tmr, uint16_t prescaler, TMR_PRESCALER_RELOAD_T * @arg TMR_COUNTER_MODE_CENTERALIGNED3: Timer Center Aligned Mode3 * @retval None */ -void TMR_ConfigCounterMode(TMR_T* tmr, TMR_COUNTER_MODE_T countMode) +void TMR_ConfigCounterMode(TMR_T *tmr, TMR_COUNTER_MODE_T countMode) { tmr->CTRL1_B.CNTDIR = BIT_RESET; tmr->CTRL1_B.CAMSEL = BIT_RESET; @@ -745,7 +756,7 @@ void TMR_ConfigCounterMode(TMR_T* tmr, TMR_COUNTER_MODE_T countMode) * * @retval None */ -void TMR_SelectInputTrigger(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource) +void TMR_SelectInputTrigger(TMR_T *tmr, TMR_TRIGGER_SOURCE_T triggerSource) { tmr->SMCTRL_B.TRGSEL = BIT_RESET; tmr->SMCTRL_B.TRGSEL = triggerSource; @@ -774,7 +785,7 @@ void TMR_SelectInputTrigger(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource) * @arg TMR_IC_POLARITY_FALLING: TMR IC polarity falling * @retval None */ -void TMR_ConfigEncodeInterface(TMR_T* tmr, TMR_ENCODER_MODE_T encodeMode, TMR_IC_POLARITY_T IC1Polarity, +void TMR_ConfigEncodeInterface(TMR_T *tmr, TMR_ENCODER_MODE_T encodeMode, TMR_IC_POLARITY_T IC1Polarity, TMR_IC_POLARITY_T IC2Polarity) { tmr->SMCTRL_B.SMFSEL = BIT_RESET; @@ -801,7 +812,7 @@ void TMR_ConfigEncodeInterface(TMR_T* tmr, TMR_ENCODER_MODE_T encodeMode, TMR_IC * @arg TMR_FORCED_ACTION_INACTIVE: Force inactive level on OC1REF * @retval None */ -void TMR_ConfigForcedOC1(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction) +void TMR_ConfigForcedOC1(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction) { tmr->CCM1_COMPARE_B.OC1MOD = BIT_RESET; tmr->CCM1_COMPARE_B.OC1MOD = forcesAction; @@ -818,7 +829,7 @@ void TMR_ConfigForcedOC1(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction) * @arg TMR_FORCED_ACTION_INACTIVE: Force inactive level on OC1REF * @retval None */ -void TMR_ConfigForcedOC2(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction) +void TMR_ConfigForcedOC2(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction) { tmr->CCM1_COMPARE_B.OC2MOD = BIT_RESET; tmr->CCM1_COMPARE_B.OC2MOD = forcesAction; @@ -836,10 +847,10 @@ void TMR_ConfigForcedOC2(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction) * * @retval None */ -void TMR_ConfigForcedOC3(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction) +void TMR_ConfigForcedOC3(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction) { - tmr->CCM2_COMPARE_B.OC3MODE = BIT_RESET; - tmr->CCM2_COMPARE_B.OC3MODE = forcesAction; + tmr->CCM2_COMPARE_B.OC3MOD = BIT_RESET; + tmr->CCM2_COMPARE_B.OC3MOD = forcesAction; } /*! @@ -854,10 +865,10 @@ void TMR_ConfigForcedOC3(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction) * * @retval None */ -void TMR_ConfigForcedOC4(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction) +void TMR_ConfigForcedOC4(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction) { - tmr->CCM2_COMPARE_B.OC4MODE = BIT_RESET; - tmr->CCM2_COMPARE_B.OC4MODE = forcesAction; + tmr->CCM2_COMPARE_B.OC4MOD = BIT_RESET; + tmr->CCM2_COMPARE_B.OC4MOD = forcesAction; } /*! @@ -867,7 +878,7 @@ void TMR_ConfigForcedOC4(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction) * * @retval None */ -void TMR_EnableAUTOReload(TMR_T* tmr) +void TMR_EnableAutoReload(TMR_T *tmr) { tmr->CTRL1_B.ARPEN = ENABLE; } @@ -879,7 +890,7 @@ void TMR_EnableAUTOReload(TMR_T* tmr) * * @retval None */ -void TMR_DisableAUTOReload(TMR_T* tmr) +void TMR_DisableAutoReload(TMR_T *tmr) { tmr->CTRL1_B.ARPEN = DISABLE; } @@ -891,7 +902,7 @@ void TMR_DisableAUTOReload(TMR_T* tmr) * * @retval None */ -void TMR_EnableSelectCOM(TMR_T* tmr) +void TMR_EnableSelectCOM(TMR_T *tmr) { tmr->CTRL2_B.CCUSEL = ENABLE; } @@ -902,7 +913,7 @@ void TMR_EnableSelectCOM(TMR_T* tmr) * * @retval None */ -void TMR_DisableSelectCOM(TMR_T* tmr) +void TMR_DisableSelectCOM(TMR_T *tmr) { tmr->CTRL2_B.CCUSEL = DISABLE; } @@ -914,7 +925,7 @@ void TMR_DisableSelectCOM(TMR_T* tmr) * * @retval None */ -void TMR_EnableCCDMA(TMR_T* tmr) +void TMR_EnableCCDMA(TMR_T *tmr) { tmr->CTRL2_B.CCDSEL = ENABLE; } @@ -926,7 +937,7 @@ void TMR_EnableCCDMA(TMR_T* tmr) * * @retval None */ -void TMR_DisableCCDMA(TMR_T* tmr) +void TMR_DisableCCDMA(TMR_T *tmr) { tmr->CTRL2_B.CCDSEL = DISABLE; } @@ -938,7 +949,7 @@ void TMR_DisableCCDMA(TMR_T* tmr) * * @retval None */ -void TMR_EnableCCPreload(TMR_T* tmr) +void TMR_EnableCCPreload(TMR_T *tmr) { tmr->CTRL2_B.CCPEN = ENABLE; } @@ -950,7 +961,7 @@ void TMR_EnableCCPreload(TMR_T* tmr) * * @retval None */ -void TMR_DisableCCPreload(TMR_T* tmr) +void TMR_DisableCCPreload(TMR_T *tmr) { tmr->CTRL2_B.CCPEN = DISABLE; } @@ -966,7 +977,7 @@ void TMR_DisableCCPreload(TMR_T* tmr) * @arg TMR_OC_PRELOAD_ENABLE * @retval None */ -void TMR_ConfigOC1Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload) +void TMR_ConfigOC1Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload) { tmr->CCM1_COMPARE_B.OC1PEN = OCPreload; } @@ -982,7 +993,7 @@ void TMR_ConfigOC1Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload) * @arg TMR_OC_PRELOAD_ENABLE * @retval None */ -void TMR_ConfigOC2Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload) +void TMR_ConfigOC2Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload) { tmr->CCM1_COMPARE_B.OC2PEN = OCPreload; } @@ -998,7 +1009,7 @@ void TMR_ConfigOC2Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload) * @arg TMR_OC_PRELOAD_ENABLE * @retval None */ -void TMR_ConfigOC3Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload) +void TMR_ConfigOC3Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload) { tmr->CCM2_COMPARE_B.OC3PEN = OCPreload; } @@ -1014,7 +1025,7 @@ void TMR_ConfigOC3Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload) * @arg TMR_OC_PRELOAD_ENABLE * @retval Nonee */ -void TMR_ConfigOC4Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload) +void TMR_ConfigOC4Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload) { tmr->CCM2_COMPARE_B.OC4PEN = OCPreload; } @@ -1030,7 +1041,7 @@ void TMR_ConfigOC4Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload) * @arg TMR_OC_FAST_ENABLE * @retval None */ -void TMR_ConfigOC1Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast) +void TMR_ConfigOC1Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast) { tmr->CCM1_COMPARE_B.OC1FEN = OCFast; } @@ -1046,7 +1057,7 @@ void TMR_ConfigOC1Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast) * @arg TMR_OC_FAST_ENABLE * @retval None */ -void TMR_ConfigOC2Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast) +void TMR_ConfigOC2Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast) { tmr->CCM1_COMPARE_B.OC2FEN = OCFast; } @@ -1062,7 +1073,7 @@ void TMR_ConfigOC2Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast) * @arg TMR_OC_FAST_ENABLE * @retval None */ -void TMR_ConfigOC3Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast) +void TMR_ConfigOC3Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast) { tmr->CCM2_COMPARE_B.OC3FEN = OCFast; } @@ -1078,7 +1089,7 @@ void TMR_ConfigOC3Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast) * @arg TMR_OC_FAST_ENABLE * @retval None */ -void TMR_ConfigOC4Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast) +void TMR_ConfigOC4Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast) { tmr->CCM2_COMPARE_B.OC4FEN = OCFast; } @@ -1094,7 +1105,7 @@ void TMR_ConfigOC4Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast) * @arg TMR_OC_CLEAR_ENABLE * @retval None */ -void TMR_ClearOC1Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear) +void TMR_ClearOC1Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear) { tmr->CCM1_COMPARE_B.OC1CEN = OCClear; } @@ -1110,7 +1121,7 @@ void TMR_ClearOC1Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear) * @arg TMR_OC_CLEAR_ENABLE * @retval None */ -void TMR_ClearOC2Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear) +void TMR_ClearOC2Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear) { tmr->CCM1_COMPARE_B.OC2CEN = OCClear; } @@ -1126,7 +1137,7 @@ void TMR_ClearOC2Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear) * @arg TMR_OC_CLEAR_ENABLE * @retval None */ -void TMR_ClearOC3Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear) +void TMR_ClearOC3Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear) { tmr->CCM2_COMPARE_B.OC3CEN = OCClear; } @@ -1142,7 +1153,7 @@ void TMR_ClearOC3Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear) * @arg TMR_OC_CLEAR_ENABLE * @retval None */ -void TMR_ClearOC4Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear) +void TMR_ClearOC4Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear) { tmr->CCM2_COMPARE_B.OC4CEN = OCClear; } @@ -1158,7 +1169,7 @@ void TMR_ClearOC4Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear) * @arg TMR_OC_POLARITY_LOW: Output Compare active low * @retval Nonee */ -void TMR_ConfigOC1Polarity(TMR_T* tmr, TMR_OC_POLARITY_T polarity) +void TMR_ConfigOC1Polarity(TMR_T *tmr, TMR_OC_POLARITY_T polarity) { tmr->CCEN_B.CC1POL = polarity; } @@ -1174,7 +1185,7 @@ void TMR_ConfigOC1Polarity(TMR_T* tmr, TMR_OC_POLARITY_T polarity) * @arg TMR_OC_NPOLARITY_LOW: Output Compare active low * @retval None */ -void TMR_ConfigOC1NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T nPolarity) +void TMR_ConfigOC1NPolarity(TMR_T *tmr, TMR_OC_NPOLARITY_T nPolarity) { tmr->CCEN_B.CC1NPOL = nPolarity; } @@ -1190,7 +1201,7 @@ void TMR_ConfigOC1NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T nPolarity) * @arg TMR_OC_POLARITY_LOW: Output Compare active low * @retval None */ -void TMR_ConfigOC2Polarity(TMR_T* tmr, TMR_OC_POLARITY_T polarity) +void TMR_ConfigOC2Polarity(TMR_T *tmr, TMR_OC_POLARITY_T polarity) { tmr->CCEN_B.CC2POL = polarity; } @@ -1206,7 +1217,7 @@ void TMR_ConfigOC2Polarity(TMR_T* tmr, TMR_OC_POLARITY_T polarity) * @arg TMR_OC_NPOLARITY_LOW: Output Compare active low * @retval None */ -void TMR_ConfigOC2NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T nPolarity) +void TMR_ConfigOC2NPolarity(TMR_T *tmr, TMR_OC_NPOLARITY_T nPolarity) { tmr->CCEN_B.CC2NPOL = nPolarity; } @@ -1222,7 +1233,7 @@ void TMR_ConfigOC2NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T nPolarity) * @arg TMR_OC_POLARITY_LOW: Output Compare active low * @retval None */ -void TMR_ConfigOC3Polarity(TMR_T* tmr, TMR_OC_POLARITY_T polarity) +void TMR_ConfigOC3Polarity(TMR_T *tmr, TMR_OC_POLARITY_T polarity) { tmr->CCEN_B.CC3POL = polarity; } @@ -1238,7 +1249,7 @@ void TMR_ConfigOC3Polarity(TMR_T* tmr, TMR_OC_POLARITY_T polarity) * @arg TMR_OC_NPOLARITY_LOW: Output Compare active low * @retval None */ -void TMR_ConfigOC3NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T nPolarity) +void TMR_ConfigOC3NPolarity(TMR_T *tmr, TMR_OC_NPOLARITY_T nPolarity) { tmr->CCEN_B.CC3NPOL = nPolarity; } @@ -1254,7 +1265,7 @@ void TMR_ConfigOC3NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T nPolarity) * @arg TMR_OC_POLARITY_LOW: Output Compare active low * @retval None */ -void TMR_ConfigOC4Polarity(TMR_T* tmr, TMR_OC_POLARITY_T polarity) +void TMR_ConfigOC4Polarity(TMR_T *tmr, TMR_OC_POLARITY_T polarity) { tmr->CCEN_B.CC4POL = polarity; } @@ -1272,7 +1283,7 @@ void TMR_ConfigOC4Polarity(TMR_T* tmr, TMR_OC_POLARITY_T polarity) * @arg TMR_CHANNEL_4: Timer Channel 4 * @retval None */ -void TMR_EnableCCxChannel(TMR_T* tmr, TMR_CHANNEL_T channel) +void TMR_EnableCCxChannel(TMR_T *tmr, TMR_CHANNEL_T channel) { tmr->CCEN |= BIT_SET << channel; } @@ -1290,7 +1301,7 @@ void TMR_EnableCCxChannel(TMR_T* tmr, TMR_CHANNEL_T channel) * @arg TMR_CHANNEL_4: Timer Channel 4 * @retval None */ -void TMR_DisableCCxChannel(TMR_T* tmr, TMR_CHANNEL_T channel) +void TMR_DisableCCxChannel(TMR_T *tmr, TMR_CHANNEL_T channel) { tmr->CCEN &= BIT_RESET << channel; } @@ -1307,7 +1318,7 @@ void TMR_DisableCCxChannel(TMR_T* tmr, TMR_CHANNEL_T channel) * @arg TMR_CHANNEL_3: Timer Channel 3 * @retval None */ -void TMR_EnableCCxNChannel(TMR_T* tmr, TMR_CHANNEL_T channel) +void TMR_EnableCCxNChannel(TMR_T *tmr, TMR_CHANNEL_T channel) { tmr->CCEN |= 0x04 << channel; } @@ -1324,7 +1335,7 @@ void TMR_EnableCCxNChannel(TMR_T* tmr, TMR_CHANNEL_T channel) * @arg TMR_CHANNEL_3: Timer Channel 3 * @retval None */ -void TMR_DisableCCxNChannel(TMR_T* tmr, TMR_CHANNEL_T channel) +void TMR_DisableCCxNChannel(TMR_T *tmr, TMR_CHANNEL_T channel) { tmr->CCEN &= BIT_RESET << channel; } @@ -1353,7 +1364,7 @@ void TMR_DisableCCxNChannel(TMR_T* tmr, TMR_CHANNEL_T channel) * @arg TMR_OC_MODE_PWM2 * @retval None */ -void TMR_SelectOCxMode(TMR_T* tmr, TMR_CHANNEL_T channel, TMR_OC_MODE_T mode) +void TMR_SelectOCxMode(TMR_T *tmr, TMR_CHANNEL_T channel, TMR_OC_MODE_T mode) { tmr->CCEN &= BIT_RESET << channel; @@ -1367,11 +1378,11 @@ void TMR_SelectOCxMode(TMR_T* tmr, TMR_CHANNEL_T channel, TMR_OC_MODE_T mode) } else if (channel == TMR_CHANNEL_3) { - tmr->CCM2_COMPARE_B.OC3MODE = mode; + tmr->CCM2_COMPARE_B.OC3MOD = mode; } else if (channel == TMR_CHANNEL_4) { - tmr->CCM2_COMPARE_B.OC4MODE = mode; + tmr->CCM2_COMPARE_B.OC4MOD = mode; } } @@ -1382,9 +1393,9 @@ void TMR_SelectOCxMode(TMR_T* tmr, TMR_CHANNEL_T channel, TMR_OC_MODE_T mode) * * @retval None */ -void TMR_EnableNoUpdate(TMR_T* tmr) +void TMR_EnableUpdate(TMR_T *tmr) { - tmr->CTRL1_B.UD = ENABLE; + tmr->CTRL1_B.UD = DISABLE; } /*! @@ -1394,9 +1405,9 @@ void TMR_EnableNoUpdate(TMR_T* tmr) * * @retval None */ -void TMR_DisableNoUpdate(TMR_T* tmr) +void TMR_DisableUpdate(TMR_T *tmr) { - tmr->CTRL1_B.UD = DISABLE; + tmr->CTRL1_B.UD = ENABLE; } /*! @@ -1410,7 +1421,7 @@ void TMR_DisableNoUpdate(TMR_T* tmr) * @arg TMR_UPDATE_SOURCE_REGULAR * @retval None */ -void TMR_ConfigUPdateRequest(TMR_T* tmr, TMR_UPDATE_SOURCE_T updateSource) +void TMR_ConfigUpdateRequest(TMR_T *tmr, TMR_UPDATE_SOURCE_T updateSource) { if (updateSource != TMR_UPDATE_SOURCE_GLOBAL) { @@ -1429,7 +1440,7 @@ void TMR_ConfigUPdateRequest(TMR_T* tmr, TMR_UPDATE_SOURCE_T updateSource) * * @retval None */ -void TMR_EnableHallSensor(TMR_T* tmr) +void TMR_EnableHallSensor(TMR_T *tmr) { tmr->CTRL2_B.TI1SEL = ENABLE; } @@ -1441,13 +1452,13 @@ void TMR_EnableHallSensor(TMR_T* tmr) * * @retval None */ -void TMR_DisableHallSensor(TMR_T* tmr) +void TMR_DisableHallSensor(TMR_T *tmr) { tmr->CTRL2_B.TI1SEL = DISABLE; } /*! - * @brief Selects the Sing pulse Mode. + * @brief Config the Sing pulse Mode. * * @param tmr: The TMRx can be 1 to 8 * @@ -1457,7 +1468,7 @@ void TMR_DisableHallSensor(TMR_T* tmr) * @arg TMR_SPM_SINGLE * @retval None */ -void TMR_SelectSinglePulseMode(TMR_T* tmr, TMR_SPM_T singlePulseMode) +void TMR_ConfigSinglePulseMode(TMR_T *tmr, TMR_SPM_T singlePulseMode) { tmr->CTRL1_B.SPMEN = singlePulseMode; } @@ -1480,7 +1491,7 @@ void TMR_SelectSinglePulseMode(TMR_T* tmr, TMR_SPM_T singlePulseMode) * @arg TMR_TRGO_SOURCE_OC4REF * @retval None */ -void TMR_SelectOutputTrigger(TMR_T* tmr, TMR_TRGO_SOURCE_T TRGOSource) +void TMR_SelectOutputTrigger(TMR_T *tmr, TMR_TRGO_SOURCE_T TRGOSource) { tmr->CTRL2_B.MMSEL = TRGOSource; } @@ -1495,10 +1506,10 @@ void TMR_SelectOutputTrigger(TMR_T* tmr, TMR_TRGO_SOURCE_T TRGOSource) * @arg TMR_SLAVE_MODE_RESET * @arg TMR_SLAVE_MODE_GATED * @arg TMR_SLAVE_MODE_TRIGGER - * @arg TMR_SLAVE_MODE_EXTERNALL + * @arg TMR_SLAVE_MODE_EXTERNAL1 * @retval None */ -void TMR_SelectSlaveMode(TMR_T* tmr, TMR_SLAVE_MODE_T slaveMode) +void TMR_SelectSlaveMode(TMR_T *tmr, TMR_SLAVE_MODE_T slaveMode) { tmr->SMCTRL_B.SMFSEL = slaveMode; } @@ -1510,7 +1521,7 @@ void TMR_SelectSlaveMode(TMR_T* tmr, TMR_SLAVE_MODE_T slaveMode) * * @retval None */ -void TMR_EnableMasterSlaveMode(TMR_T* tmr) +void TMR_EnableMasterSlaveMode(TMR_T *tmr) { tmr->SMCTRL_B.MSMEN = ENABLE; } @@ -1522,7 +1533,7 @@ void TMR_EnableMasterSlaveMode(TMR_T* tmr) * * @retval None */ -void TMR_DisableMasterSlaveMode(TMR_T* tmr) +void TMR_DisableMasterSlaveMode(TMR_T *tmr) { tmr->SMCTRL_B.MSMEN = DISABLE; } @@ -1536,7 +1547,7 @@ void TMR_DisableMasterSlaveMode(TMR_T* tmr) * * @retval None */ -void TMR_ConfigCounter(TMR_T* tmr, uint16_t counter) +void TMR_ConfigCounter(TMR_T *tmr, uint16_t counter) { tmr->CNT = counter; } @@ -1550,7 +1561,7 @@ void TMR_ConfigCounter(TMR_T* tmr, uint16_t counter) * * @retval None */ -void TMR_ConfigAutoreload(TMR_T* tmr, uint16_t autoReload) +void TMR_ConfigAutoreload(TMR_T *tmr, uint16_t autoReload) { tmr->AUTORLD = autoReload; } @@ -1564,7 +1575,7 @@ void TMR_ConfigAutoreload(TMR_T* tmr, uint16_t autoReload) * * @retval None */ -void TMR_ConfigCompare1(TMR_T* tmr, uint16_t compare1) +void TMR_ConfigCompare1(TMR_T *tmr, uint16_t compare1) { tmr->CC1 = compare1; } @@ -1578,7 +1589,7 @@ void TMR_ConfigCompare1(TMR_T* tmr, uint16_t compare1) * * @retval None */ -void TMR_ConfigCompare2(TMR_T* tmr, uint16_t compare2) +void TMR_ConfigCompare2(TMR_T *tmr, uint16_t compare2) { tmr->CC2 = compare2; } @@ -1592,7 +1603,7 @@ void TMR_ConfigCompare2(TMR_T* tmr, uint16_t compare2) * * @retval None */ -void TMR_ConfigCompare3(TMR_T* tmr, uint16_t compare3) +void TMR_ConfigCompare3(TMR_T *tmr, uint16_t compare3) { tmr->CC3 = compare3; } @@ -1606,7 +1617,7 @@ void TMR_ConfigCompare3(TMR_T* tmr, uint16_t compare3) * * @retval None */ -void TMR_ConfigCompare4(TMR_T* tmr, uint16_t compare4) +void TMR_ConfigCompare4(TMR_T *tmr, uint16_t compare4) { tmr->CC4 = compare4; } @@ -1624,7 +1635,7 @@ void TMR_ConfigCompare4(TMR_T* tmr, uint16_t compare4) * @arg TMR_IC_PSC_8: capture is done once every 8 events * @retval None */ -void TMR_ConfigIC1Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler) +void TMR_ConfigIC1Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler) { tmr->CCM1_CAPTURE_B.IC1PSC = BIT_RESET; tmr->CCM1_CAPTURE_B.IC1PSC = prescaler; @@ -1642,7 +1653,7 @@ void TMR_ConfigIC1Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler) * @arg TMR_IC_PSC_8: capture is done once every 8 events * @retval None */ -void TMR_ConfigIC2Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler) +void TMR_ConfigIC2Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler) { tmr->CCM1_CAPTURE_B.IC2PSC = BIT_RESET; tmr->CCM1_CAPTURE_B.IC2PSC = prescaler; @@ -1661,7 +1672,7 @@ void TMR_ConfigIC2Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler) * @arg TMR_IC_PSC_8: capture is done once every 8 events * @retval None */ -void TMR_ConfigIC3Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler) +void TMR_ConfigIC3Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler) { tmr->CCM2_CAPTURE_B.IC3PSC = BIT_RESET; tmr->CCM2_CAPTURE_B.IC3PSC = prescaler; @@ -1680,7 +1691,7 @@ void TMR_ConfigIC3Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler) * @arg TMR_IC_PSC_8: capture is done once every 8 events * @retval None */ -void TMR_ConfigIC4Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler) +void TMR_ConfigIC4Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler) { tmr->CCM2_CAPTURE_B.IC4PSC = BIT_RESET; tmr->CCM2_CAPTURE_B.IC4PSC = prescaler; @@ -1698,7 +1709,7 @@ void TMR_ConfigIC4Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler) * @arg TMR_CLOCK_DIV_4: TDTS = 4*Tck_tim * @retval None */ -void TMR_ConfigClockDivision(TMR_T* tmr, TMR_CLOCK_DIV_T clockDivision) +void TMR_ConfigClockDivision(TMR_T *tmr, TMR_CLOCK_DIV_T clockDivision) { tmr->CTRL1_B.CLKDIV = clockDivision; } @@ -1710,7 +1721,7 @@ void TMR_ConfigClockDivision(TMR_T* tmr, TMR_CLOCK_DIV_T clockDivision) * * @retval Capture Compare 1 Register value. */ -uint16_t TMR_ReadCaputer1(TMR_T* tmr) +uint16_t TMR_ReadCaputer1(TMR_T *tmr) { return tmr->CC1; } @@ -1722,7 +1733,7 @@ uint16_t TMR_ReadCaputer1(TMR_T* tmr) * * @retval Capture Compare 2 Register value. */ -uint16_t TMR_ReadCaputer2(TMR_T* tmr) +uint16_t TMR_ReadCaputer2(TMR_T *tmr) { return tmr->CC2; } @@ -1734,7 +1745,7 @@ uint16_t TMR_ReadCaputer2(TMR_T* tmr) * * @retval Capture Compare 3 Register value. */ -uint16_t TMR_ReadCaputer3(TMR_T* tmr) +uint16_t TMR_ReadCaputer3(TMR_T *tmr) { return tmr->CC3; } @@ -1746,7 +1757,7 @@ uint16_t TMR_ReadCaputer3(TMR_T* tmr) * * @retval Capture Compare 4 Register value. */ -uint16_t TMR_ReadCaputer4(TMR_T* tmr) +uint16_t TMR_ReadCaputer4(TMR_T *tmr) { return tmr->CC4; } @@ -1758,7 +1769,7 @@ uint16_t TMR_ReadCaputer4(TMR_T* tmr) * * @retval Counter Register value. */ -uint16_t TMR_ReadCounter(TMR_T* tmr) +uint16_t TMR_ReadCounter(TMR_T *tmr) { return tmr->CNT; } @@ -1770,7 +1781,7 @@ uint16_t TMR_ReadCounter(TMR_T* tmr) * * @retval Prescaler Register value. */ -uint16_t TMR_ReadPrescaler(TMR_T* tmr) +uint16_t TMR_ReadPrescaler(TMR_T *tmr) { return tmr->PSC; } @@ -1794,7 +1805,7 @@ uint16_t TMR_ReadPrescaler(TMR_T* tmr) * * @note TMR6 and TMR7 can only generate an TMR_INT_UPDATE. */ -void TMR_EnableInterrupt(TMR_T* tmr, uint16_t interrupt) +void TMR_EnableInterrupt(TMR_T *tmr, uint16_t interrupt) { tmr->DIEN |= interrupt; } @@ -1818,7 +1829,7 @@ void TMR_EnableInterrupt(TMR_T* tmr, uint16_t interrupt) * * @note TMR6 and TMR7 can only generate an TMR_INT_UPDATE. */ -void TMR_DisableInterrupt(TMR_T* tmr, uint16_t interrupt) +void TMR_DisableInterrupt(TMR_T *tmr, uint16_t interrupt) { tmr->DIEN &= ~interrupt; } @@ -1842,7 +1853,7 @@ void TMR_DisableInterrupt(TMR_T* tmr, uint16_t interrupt) * * @note TMR6 and TMR7 can only generate an TMR_EVENT_UPDATE. */ -void TMR_GenerateEvent(TMR_T* tmr, uint16_t eventSources) +void TMR_GenerateEvent(TMR_T *tmr, uint16_t eventSources) { tmr->CEG = eventSources; } @@ -1870,16 +1881,9 @@ void TMR_GenerateEvent(TMR_T* tmr, uint16_t eventSources) * * @note TMR6 and TMR7 can only generate an TMR_FLAG_UPDATE. */ -uint16_t TMR_ReadStatusFlag(TMR_T* tmr, TMR_FLAG_T flag) +uint16_t TMR_ReadStatusFlag(TMR_T *tmr, TMR_FLAG_T flag) { - if ((tmr->STS & flag) != RESET) - { - return SET; - } - else - { - return RESET; - } + return (tmr->STS & flag) ? SET : RESET; } /*! @@ -1905,7 +1909,7 @@ uint16_t TMR_ReadStatusFlag(TMR_T* tmr, TMR_FLAG_T flag) * * @note TMR6 and TMR7 can only generate an TMR_FLAG_UPDATE. */ -void TMR_ClearStatusFlag(TMR_T* tmr, uint16_t flag) +void TMR_ClearStatusFlag(TMR_T *tmr, uint16_t flag) { tmr->STS = ~flag; } @@ -1929,9 +1933,9 @@ void TMR_ClearStatusFlag(TMR_T* tmr, uint16_t flag) * * @note TMR6 and TMR7 can only generate an TMR_INT_UPDATE. */ -uint16_t TMR_ReadIntFlag(TMR_T* tmr, TMR_INT_T flag) +uint16_t TMR_ReadIntFlag(TMR_T *tmr, TMR_INT_T flag) { - if (((tmr->STS & flag) != RESET ) && ((tmr->DIEN & flag) != RESET)) + if (((tmr->STS & flag) != RESET) && ((tmr->DIEN & flag) != RESET)) { return SET; } @@ -1960,7 +1964,7 @@ uint16_t TMR_ReadIntFlag(TMR_T* tmr, TMR_INT_T flag) * * @note TMR6 and TMR7 can only generate an TMR_INT_UPDATE. */ -void TMR_ClearIntFlag(TMR_T* tmr, uint16_t flag) +void TMR_ClearIntFlag(TMR_T *tmr, uint16_t flag) { tmr->STS = ~flag; } @@ -1978,7 +1982,7 @@ void TMR_ClearIntFlag(TMR_T* tmr, uint16_t flag) * * @retval None */ -static void TI1Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter) +static void TI1Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter) { uint16_t tmpchctrl = 0; @@ -1990,7 +1994,7 @@ static void TI1Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uin tmr->CCM1_CAPTURE_B.IC1F = ICfilter; if ((tmr == TMR1) || (tmr == TMR8) || (tmr == TMR2) || (tmr == TMR3) || - (tmr == TMR4) || (tmr == TMR5)) + (tmr == TMR4) || (tmr == TMR5)) { tmr->CCEN_B.CC1POL = BIT_RESET; tmr->CCEN_B.CC1EN = BIT_SET; @@ -2022,7 +2026,7 @@ static void TI1Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uin * * @retval None */ -static void TI2Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter) +static void TI2Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter) { uint16_t tmpchctrl = 0; @@ -2034,7 +2038,7 @@ static void TI2Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uin tmr->CCM1_CAPTURE_B.IC2F = ICfilter; if ((tmr == TMR1) || (tmr == TMR8) || (tmr == TMR2) || (tmr == TMR3) || - (tmr == TMR4) || (tmr == TMR5)) + (tmr == TMR4) || (tmr == TMR5)) { tmr->CCEN_B.CC2POL = BIT_RESET; tmr->CCEN_B.CC2EN = BIT_SET; @@ -2066,7 +2070,7 @@ static void TI2Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uin * * @retval None */ -static void TI3Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter) +static void TI3Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter) { uint16_t tmpchctrl = 0; @@ -2078,7 +2082,7 @@ static void TI3Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uin tmr->CCM2_CAPTURE_B.IC3F = ICfilter; if ((tmr == TMR1) || (tmr == TMR8) || (tmr == TMR2) || (tmr == TMR3) || - (tmr == TMR4) || (tmr == TMR5)) + (tmr == TMR4) || (tmr == TMR5)) { tmr->CCEN_B.CC3POL = BIT_RESET; tmr->CCEN_B.CC3EN = BIT_SET; @@ -2110,7 +2114,7 @@ static void TI3Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uin * * @retval None */ -static void TI4Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter) +static void TI4Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter) { uint16_t tmpchctrl = 0; diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_usart.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_usart.c index 23eb7fa355..081c50ce7a 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_usart.c +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_usart.c @@ -1,12 +1,26 @@ /*! - * @file apm32f10x_usart.c + * @file apm32f10x_usart.c * - * @brief This file provides all the USART firmware functions + * @brief This file provides all the USART firmware functions * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ #include "apm32f10x_usart.h" @@ -33,7 +47,7 @@ * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_Reset(USART_T* usart) +void USART_Reset(USART_T *usart) { if (USART1 == usart) { @@ -73,13 +87,15 @@ void USART_Reset(USART_T* usart) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_Config(USART_T* uart, USART_Config_T* usartConfig) +void USART_Config(USART_T *uart, USART_Config_T *usartConfig) { uint32_t temp, fCLK, intDiv, fractionalDiv; temp = uart->CTRL1; temp &= 0xE9F3; - temp |= usartConfig->mode | usartConfig->parity | usartConfig->wordLength; + temp |= (uint32_t)usartConfig->mode | \ + (uint32_t)usartConfig->parity | \ + (uint32_t)usartConfig->wordLength; uart->CTRL1 = temp; temp = uart->CTRL2; @@ -116,7 +132,7 @@ void USART_Config(USART_T* uart, USART_Config_T* usartConfig) * * @retval None */ -void USART_ConfigStructInit(USART_Config_T* usartConfig) +void USART_ConfigStructInit(USART_Config_T *usartConfig) { usartConfig->baudRate = 9600; usartConfig->wordLength = USART_WORD_LEN_8B; @@ -137,7 +153,7 @@ void USART_ConfigStructInit(USART_Config_T* usartConfig) * * @note The usart can be USART1, USART2, USART3 */ -void USART_ConfigClock(USART_T* usart, USART_ClockConfig_T* clockConfig) +void USART_ConfigClock(USART_T *usart, USART_ClockConfig_T *clockConfig) { usart->CTRL2_B.CLKEN = clockConfig->clock; usart->CTRL2_B.CPHA = clockConfig->phase; @@ -152,9 +168,8 @@ void USART_ConfigClock(USART_T* usart, USART_ClockConfig_T* clockConfig) * * @retval None * - * @note */ -void USART_ConfigClockStructInit(USART_ClockConfig_T* clockConfig) +void USART_ConfigClockStructInit(USART_ClockConfig_T *clockConfig) { clockConfig->clock = USART_CLKEN_DISABLE; clockConfig->phase = USART_CLKPHA_1EDGE; @@ -171,7 +186,7 @@ void USART_ConfigClockStructInit(USART_ClockConfig_T* clockConfig) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_Enable(USART_T* usart) +void USART_Enable(USART_T *usart) { usart->CTRL1_B.UEN = BIT_SET; } @@ -185,7 +200,7 @@ void USART_Enable(USART_T* usart) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_Disable(USART_T* usart) +void USART_Disable(USART_T *usart) { usart->CTRL1_B.UEN = BIT_RESET; } @@ -205,7 +220,7 @@ void USART_Disable(USART_T* usart) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_EnableDMA(USART_T* usart, USART_DMA_T dmaReq) +void USART_EnableDMA(USART_T *usart, USART_DMA_T dmaReq) { usart->CTRL3 |= dmaReq; } @@ -225,7 +240,7 @@ void USART_EnableDMA(USART_T* usart, USART_DMA_T dmaReq) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_DisableDMA(USART_T* usart, USART_DMA_T dmaReq) +void USART_DisableDMA(USART_T *usart, USART_DMA_T dmaReq) { usart->CTRL3 &= (uint32_t)~dmaReq; } @@ -241,7 +256,7 @@ void USART_DisableDMA(USART_T* usart, USART_DMA_T dmaReq) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_Address(USART_T* usart, uint8_t address) +void USART_Address(USART_T *usart, uint8_t address) { usart->CTRL2_B.ADDR = address; } @@ -260,7 +275,7 @@ void USART_Address(USART_T* usart, uint8_t address) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_ConfigWakeUp(USART_T* usart, USART_WAKEUP_T wakeup) +void USART_ConfigWakeUp(USART_T *usart, USART_WAKEUP_T wakeup) { usart->CTRL1_B.WUPMCFG = wakeup; } @@ -274,7 +289,7 @@ void USART_ConfigWakeUp(USART_T* usart, USART_WAKEUP_T wakeup) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_EnableMuteMode(USART_T* usart) +void USART_EnableMuteMode(USART_T *usart) { usart->CTRL1_B.RXMUTEEN = BIT_SET; } @@ -288,7 +303,7 @@ void USART_EnableMuteMode(USART_T* usart) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_DisableMuteMode(USART_T* usart) +void USART_DisableMuteMode(USART_T *usart) { usart->CTRL1_B.RXMUTEEN = BIT_RESET; } @@ -307,7 +322,7 @@ void USART_DisableMuteMode(USART_T* usart) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_ConfigLINBreakDetectLength(USART_T* usart, USART_LBDL_T length) +void USART_ConfigLINBreakDetectLength(USART_T *usart, USART_LBDL_T length) { usart->CTRL2_B.LBDLCFG = length; } @@ -321,7 +336,7 @@ void USART_ConfigLINBreakDetectLength(USART_T* usart, USART_LBDL_T length) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_EnableLIN(USART_T* usart) +void USART_EnableLIN(USART_T *usart) { usart->CTRL2_B.LINMEN = BIT_SET; } @@ -335,7 +350,7 @@ void USART_EnableLIN(USART_T* usart) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_DisableLIN(USART_T* usart) +void USART_DisableLIN(USART_T *usart) { usart->CTRL2_B.LINMEN = BIT_RESET; } @@ -349,7 +364,7 @@ void USART_DisableLIN(USART_T* usart) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_EnableTx(USART_T* usart) +void USART_EnableTx(USART_T *usart) { usart->CTRL1_B.TXEN = BIT_SET; } @@ -363,7 +378,7 @@ void USART_EnableTx(USART_T* usart) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_DisableTx(USART_T* usart) +void USART_DisableTx(USART_T *usart) { usart->CTRL1_B.TXEN = BIT_RESET; } @@ -377,7 +392,7 @@ void USART_DisableTx(USART_T* usart) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_EnableRx(USART_T* usart) +void USART_EnableRx(USART_T *usart) { usart->CTRL1_B.RXEN = BIT_SET; } @@ -391,7 +406,7 @@ void USART_EnableRx(USART_T* usart) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_DisableRx(USART_T* usart) +void USART_DisableRx(USART_T *usart) { usart->CTRL1_B.RXEN = BIT_RESET; } @@ -407,7 +422,7 @@ void USART_DisableRx(USART_T* usart) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_TxData(USART_T* usart, uint16_t data) +void USART_TxData(USART_T *usart, uint16_t data) { usart->DATA_B.DATA = data; } @@ -421,7 +436,7 @@ void USART_TxData(USART_T* usart, uint16_t data) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -uint16_t USART_RxData(USART_T* usart) +uint16_t USART_RxData(USART_T *usart) { return (uint16_t)(usart->DATA_B.DATA); } @@ -435,7 +450,7 @@ uint16_t USART_RxData(USART_T* usart) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_TxBreak(USART_T* usart) +void USART_TxBreak(USART_T *usart) { usart->CTRL1_B.TXBF = BIT_SET; } @@ -451,7 +466,7 @@ void USART_TxBreak(USART_T* usart) * * @note The usart can be USART1, USART2, USART3 */ -void USART_ConfigGuardTime(USART_T* usart, uint8_t guardTime) +void USART_ConfigGuardTime(USART_T *usart, uint8_t guardTime) { usart->GTPSC_B.GRDT = guardTime; } @@ -467,7 +482,7 @@ void USART_ConfigGuardTime(USART_T* usart, uint8_t guardTime) * * @note The usart can be USART1, USART2, USART3 */ -void USART_ConfigPrescaler(USART_T* usart, uint8_t div) +void USART_ConfigPrescaler(USART_T *usart, uint8_t div) { usart->GTPSC_B.PSC = div; } @@ -481,7 +496,7 @@ void USART_ConfigPrescaler(USART_T* usart, uint8_t div) * * @note The Smart Card mode is not available for UART4 and UART5 */ -void USART_EnableSmartCard(USART_T* usart) +void USART_EnableSmartCard(USART_T *usart) { usart->CTRL3_B.SCEN = BIT_SET; } @@ -495,7 +510,7 @@ void USART_EnableSmartCard(USART_T* usart) * * @note The Smart Card mode is not available for UART4 and UART5 */ -void USART_DisableSmartCard(USART_T* usart) +void USART_DisableSmartCard(USART_T *usart) { usart->CTRL3_B.SCEN = BIT_RESET; } @@ -509,7 +524,7 @@ void USART_DisableSmartCard(USART_T* usart) * * @note The Smart Card mode is not available for UART4 and UART5 */ -void USART_EnableSmartCardNACK(USART_T* usart) +void USART_EnableSmartCardNACK(USART_T *usart) { usart->CTRL3_B.SCNACKEN = BIT_SET; } @@ -523,7 +538,7 @@ void USART_EnableSmartCardNACK(USART_T* usart) * * @note The Smart Card mode is not available for UART4 and UART5 */ -void USART_DisableSmartCardNACK(USART_T* usart) +void USART_DisableSmartCardNACK(USART_T *usart) { usart->CTRL3_B.SCNACKEN = BIT_RESET; } @@ -537,7 +552,7 @@ void USART_DisableSmartCardNACK(USART_T* usart) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_EnableHalfDuplex(USART_T* usart) +void USART_EnableHalfDuplex(USART_T *usart) { usart->CTRL3_B.HDEN = BIT_SET; } @@ -551,7 +566,7 @@ void USART_EnableHalfDuplex(USART_T* usart) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_DisableHalfDuplex(USART_T* usart) +void USART_DisableHalfDuplex(USART_T *usart) { usart->CTRL3_B.HDEN = BIT_RESET; } @@ -569,7 +584,7 @@ void USART_DisableHalfDuplex(USART_T* usart) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_ConfigIrDA(USART_T* usart, USART_IRDALP_T IrDAMode) +void USART_ConfigIrDA(USART_T *usart, USART_IRDALP_T IrDAMode) { usart->CTRL3_B.IRLPEN = IrDAMode; } @@ -583,7 +598,7 @@ void USART_ConfigIrDA(USART_T* usart, USART_IRDALP_T IrDAMode) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_EnableIrDA(USART_T* usart) +void USART_EnableIrDA(USART_T *usart) { usart->CTRL3_B.IREN = BIT_SET; } @@ -597,7 +612,7 @@ void USART_EnableIrDA(USART_T* usart) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_DisableIrDA(USART_T* usart) +void USART_DisableIrDA(USART_T *usart) { usart->CTRL3_B.IREN = BIT_RESET; } @@ -622,23 +637,23 @@ void USART_DisableIrDA(USART_T* usart) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_EnableInterrupt(USART_T* usart, USART_INT_T interrupt) +void USART_EnableInterrupt(USART_T *usart, USART_INT_T interrupt) { uint32_t temp; temp = (uint32_t)(interrupt & 0xffff); - if (interrupt & 0X10000) + if (interrupt & 0x10000) { usart->CTRL1 |= temp; } - if (interrupt & 0X20000) + if (interrupt & 0x20000) { usart->CTRL2 |= temp; } - if (interrupt & 0X40000) + if (interrupt & 0x40000) { usart->CTRL3 |= temp; } @@ -664,23 +679,23 @@ void USART_EnableInterrupt(USART_T* usart, USART_INT_T interrupt) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_DisableInterrupt(USART_T* usart, USART_INT_T interrupt) +void USART_DisableInterrupt(USART_T *usart, USART_INT_T interrupt) { uint32_t temp; temp = (uint32_t)~(interrupt & 0xffff); - if (interrupt & 0X10000) + if (interrupt & 0x10000) { usart->CTRL1 &= temp; } - if (interrupt & 0X20000) + if (interrupt & 0x20000) { usart->CTRL2 &= temp; } - if (interrupt & 0X40000) + if (interrupt & 0x40000) { usart->CTRL3 &= temp; } @@ -708,7 +723,7 @@ void USART_DisableInterrupt(USART_T* usart, USART_INT_T interrupt) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -uint8_t USART_ReadStatusFlag(USART_T* usart, USART_FLAG_T flag) +uint8_t USART_ReadStatusFlag(USART_T *usart, USART_FLAG_T flag) { return (usart->STS & flag) ? SET : RESET; } @@ -729,7 +744,7 @@ uint8_t USART_ReadStatusFlag(USART_T* usart, USART_FLAG_T flag) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_ClearStatusFlag(USART_T* usart, USART_FLAG_T flag) +void USART_ClearStatusFlag(USART_T *usart, USART_FLAG_T flag) { usart->STS &= (uint32_t)~flag; } @@ -756,7 +771,7 @@ void USART_ClearStatusFlag(USART_T* usart, USART_FLAG_T flag) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -uint8_t USART_ReadIntFlag(USART_T* usart, USART_INT_T flag) +uint8_t USART_ReadIntFlag(USART_T *usart, USART_INT_T flag) { uint32_t itFlag, srFlag; @@ -801,7 +816,7 @@ uint8_t USART_ReadIntFlag(USART_T* usart, USART_INT_T flag) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_ClearIntFlag(USART_T* usart, USART_INT_T flag) +void USART_ClearIntFlag(USART_T *usart, USART_INT_T flag) { uint32_t srFlag; diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_wwdt.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_wwdt.c index 6e374cd5b4..e7a65ea69d 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_wwdt.c +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_wwdt.c @@ -3,10 +3,24 @@ * * @brief This file contains all the functions for the WWDT peripheral * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ #include "apm32f10x_wwdt.h" @@ -125,7 +139,7 @@ void WWDT_Enable(uint8_t counter) */ uint8_t WWDT_ReadFlag(void) { - return (uint8_t) (WWDT->STS); + return (uint8_t)(WWDT->STS); } /*! @@ -141,5 +155,5 @@ void WWDT_ClearFlag(void) } /**@} end of group WWDT_Fuctions*/ -/**@} end of group WWDT_Driver */ +/**@} end of group WWDT_Driver*/ /**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/LICENSE.txt b/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/LICENSE.txt new file mode 100644 index 0000000000..f0cd2d9ccf --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/LICENSE.txt @@ -0,0 +1,176 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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In no event and under no legal theory, + whether in tort (including negligence), contract, or otherwise, + unless required by applicable law (such as deliberate and grossly + negligent acts) or agreed to in writing, shall any Contributor be + liable to You for damages, including any direct, indirect, special, + incidental, or consequential damages of any character arising as a + result of this License or out of the use or inability to use the + Work (including but not limited to damages for loss of goodwill, + work stoppage, computer failure or malfunction, or any and all + other commercial damages or losses), even if such Contributor + has been advised of the possibility of such damages. + + 9. Accepting Warranty or Additional Liability. While redistributing + the Work or Derivative Works thereof, You may choose to offer, + and charge a fee for, acceptance of support, warranty, indemnity, + or other liability obligations and/or rights consistent with this + License. However, in accepting such obligations, You may act only + on Your own behalf and on Your sole responsibility, not on behalf + of any other Contributor, and only if You agree to indemnify, + defend, and hold each Contributor harmless for any liability + incurred by, or claims asserted against, such Contributor by reason + of your accepting any such warranty or additional liability. + + END OF TERMS AND CONDITIONS \ No newline at end of file diff --git a/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_armcc.h b/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_armcc.h index a19425d9fe..81ac0625f4 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_armcc.h +++ b/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_armcc.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file cmsis_armcc.h * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file - * @version V5.1.0 - * @date 08. May 2019 + * @version V5.0.4 + * @date 10. January 2018 ******************************************************************************/ /* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -27,107 +27,78 @@ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) - #error "Please use Arm Compiler Toolchain V4.0.677 or later!" + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" #endif /* CMSIS compiler control architecture macros */ #if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) - #define __ARM_ARCH_6M__ 1 +#define __ARM_ARCH_6M__ 1 #endif #if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) - #define __ARM_ARCH_7M__ 1 + #define __ARM_ARCH_7M__ 1 #endif #if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) - #define __ARM_ARCH_7EM__ 1 + #define __ARM_ARCH_7EM__ 1 #endif - /* __ARM_ARCH_8M_BASE__ not applicable */ - /* __ARM_ARCH_8M_MAIN__ not applicable */ +/* __ARM_ARCH_8M_BASE__ not applicable */ +/* __ARM_ARCH_8M_MAIN__ not applicable */ -/* CMSIS compiler control DSP macros */ -#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - #define __ARM_FEATURE_DSP 1 -#endif /* CMSIS compiler specific defines */ #ifndef __ASM - #define __ASM __asm + #define __ASM __asm #endif #ifndef __INLINE - #define __INLINE __inline + #define __INLINE __inline #endif #ifndef __STATIC_INLINE - #define __STATIC_INLINE static __inline + #define __STATIC_INLINE static __inline #endif #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE static __forceinline + #define __STATIC_FORCEINLINE static __forceinline #endif #ifndef __NO_RETURN - #define __NO_RETURN __declspec(noreturn) + #define __NO_RETURN __declspec(noreturn) #endif #ifndef __USED - #define __USED __attribute__((used)) + #define __USED __attribute__((used)) #endif #ifndef __WEAK - #define __WEAK __attribute__((weak)) + #define __WEAK __attribute__((weak)) #endif #ifndef __PACKED - #define __PACKED __attribute__((packed)) + #define __PACKED __attribute__((packed)) #endif #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT __packed struct + #define __PACKED_STRUCT __packed struct #endif #ifndef __PACKED_UNION - #define __PACKED_UNION __packed union + #define __PACKED_UNION __packed union #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ - #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) #endif #ifndef __UNALIGNED_UINT16_WRITE - #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) #endif #ifndef __UNALIGNED_UINT16_READ - #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) #endif #ifndef __UNALIGNED_UINT32_WRITE - #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) #endif #ifndef __UNALIGNED_UINT32_READ - #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) #endif #ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) + #define __ALIGNED(x) __attribute__((aligned(x))) #endif #ifndef __RESTRICT - #define __RESTRICT __restrict -#endif -#ifndef __COMPILER_BARRIER - #define __COMPILER_BARRIER() __memory_changed() -#endif - -/* ######################### Startup and Lowlevel Init ######################## */ - -#ifndef __PROGRAM_START -#define __PROGRAM_START __main -#endif - -#ifndef __INITIAL_SP -#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit -#endif - -#ifndef __STACK_LIMIT -#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base -#endif - -#ifndef __VECTOR_TABLE -#define __VECTOR_TABLE __Vectors -#endif - -#ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) + #define __RESTRICT __restrict #endif /* ########################### Core Function Access ########################### */ @@ -158,8 +129,8 @@ */ __STATIC_INLINE uint32_t __get_CONTROL(void) { - register uint32_t __regControl __ASM("control"); - return(__regControl); + register uint32_t __regControl __ASM("control"); + return (__regControl); } @@ -170,8 +141,8 @@ __STATIC_INLINE uint32_t __get_CONTROL(void) */ __STATIC_INLINE void __set_CONTROL(uint32_t control) { - register uint32_t __regControl __ASM("control"); - __regControl = control; + register uint32_t __regControl __ASM("control"); + __regControl = control; } @@ -182,8 +153,8 @@ __STATIC_INLINE void __set_CONTROL(uint32_t control) */ __STATIC_INLINE uint32_t __get_IPSR(void) { - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); + register uint32_t __regIPSR __ASM("ipsr"); + return (__regIPSR); } @@ -194,8 +165,8 @@ __STATIC_INLINE uint32_t __get_IPSR(void) */ __STATIC_INLINE uint32_t __get_APSR(void) { - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); + register uint32_t __regAPSR __ASM("apsr"); + return (__regAPSR); } @@ -206,8 +177,8 @@ __STATIC_INLINE uint32_t __get_APSR(void) */ __STATIC_INLINE uint32_t __get_xPSR(void) { - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); + register uint32_t __regXPSR __ASM("xpsr"); + return (__regXPSR); } @@ -218,8 +189,8 @@ __STATIC_INLINE uint32_t __get_xPSR(void) */ __STATIC_INLINE uint32_t __get_PSP(void) { - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); + register uint32_t __regProcessStackPointer __ASM("psp"); + return (__regProcessStackPointer); } @@ -230,8 +201,8 @@ __STATIC_INLINE uint32_t __get_PSP(void) */ __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) { - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; } @@ -242,8 +213,8 @@ __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) */ __STATIC_INLINE uint32_t __get_MSP(void) { - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); + register uint32_t __regMainStackPointer __ASM("msp"); + return (__regMainStackPointer); } @@ -254,8 +225,8 @@ __STATIC_INLINE uint32_t __get_MSP(void) */ __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) { - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; } @@ -266,8 +237,8 @@ __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) */ __STATIC_INLINE uint32_t __get_PRIMASK(void) { - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); + register uint32_t __regPriMask __ASM("primask"); + return (__regPriMask); } @@ -278,8 +249,8 @@ __STATIC_INLINE uint32_t __get_PRIMASK(void) */ __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) { - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); } @@ -309,8 +280,8 @@ __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) */ __STATIC_INLINE uint32_t __get_BASEPRI(void) { - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); + register uint32_t __regBasePri __ASM("basepri"); + return (__regBasePri); } @@ -321,8 +292,8 @@ __STATIC_INLINE uint32_t __get_BASEPRI(void) */ __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) { - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xFFU); + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); } @@ -334,8 +305,8 @@ __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) */ __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) { - register uint32_t __regBasePriMax __ASM("basepri_max"); - __regBasePriMax = (basePri & 0xFFU); + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); } @@ -346,8 +317,8 @@ __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) */ __STATIC_INLINE uint32_t __get_FAULTMASK(void) { - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); + register uint32_t __regFaultMask __ASM("faultmask"); + return (__regFaultMask); } @@ -358,8 +329,8 @@ __STATIC_INLINE uint32_t __get_FAULTMASK(void) */ __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) { - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1U); + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); } #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ @@ -375,10 +346,10 @@ __STATIC_INLINE uint32_t __get_FPSCR(void) { #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); + register uint32_t __regfpscr __ASM("fpscr"); + return (__regfpscr); #else - return(0U); + return (0U); #endif } @@ -392,10 +363,10 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) { #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); #else - (void)fpscr; + (void)fpscr; #endif } @@ -491,8 +462,8 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) #ifndef __NO_EMBEDDED_ASM __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) { - rev16 r0, r0 - bx lr + rev16 r0, r0 + bx lr } #endif @@ -506,8 +477,8 @@ __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(u #ifndef __NO_EMBEDDED_ASM __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) { - revsh r0, r0 - bx lr + revsh r0, r0 + bx lr } #endif @@ -540,22 +511,22 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(in */ #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - #define __RBIT __rbit +#define __RBIT __rbit #else __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) { - uint32_t result; - uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value != 0U; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ - return result; + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; } #endif @@ -579,9 +550,9 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) \return value of type uint8_t at (*ptr) */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) #else - #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") #endif @@ -592,9 +563,9 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) \return value of type uint16_t at (*ptr) */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) #else - #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") #endif @@ -605,9 +576,9 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) \return value of type uint32_t at (*ptr) */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) #else - #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") #endif @@ -620,9 +591,9 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) \return 1 Function failed */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXB(value, ptr) __strex(value, ptr) + #define __STREXB(value, ptr) __strex(value, ptr) #else - #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") #endif @@ -635,9 +606,9 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) \return 1 Function failed */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXH(value, ptr) __strex(value, ptr) + #define __STREXH(value, ptr) __strex(value, ptr) #else - #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") #endif @@ -650,9 +621,9 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) \return 1 Function failed */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXW(value, ptr) __strex(value, ptr) + #define __STREXW(value, ptr) __strex(value, ptr) #else - #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") #endif @@ -693,8 +664,8 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) #ifndef __NO_EMBEDDED_ASM __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) { - rrx r0, r0 - bx lr + rrx r0, r0 + bx lr } #endif @@ -764,20 +735,20 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3 */ __attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) { - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) + if ((sat >= 1U) && (sat <= 32U)) { - return max; + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } } - else if (val < min) - { - return min; - } - } - return val; + return val; } /** @@ -789,25 +760,25 @@ __attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint3 */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) { - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) + if (sat <= 31U) { - return max; + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; + return (uint32_t)val; } #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ -/**@}*/ /* end of group CMSIS_Core_InstructionInterface */ +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ /* ################### Compiler specific Intrinsics ########################### */ @@ -888,7 +859,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint ((int64_t)(ARG3) << 32U) ) >> 32U)) #endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ -/**@} end of group CMSIS_SIMD_intrinsics */ +/*@} end of group CMSIS_SIMD_intrinsics */ #endif /* __CMSIS_ARMCC_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_armclang.h b/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_armclang.h index ef919934c5..a25b249fe1 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_armclang.h +++ b/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_armclang.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file cmsis_armclang.h * @brief CMSIS compiler armclang (Arm Compiler 6) header file - * @version V5.2.0 - * @date 08. May 2019 + * @version V5.0.4 + * @date 10. January 2018 ******************************************************************************/ /* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -30,111 +30,90 @@ #pragma clang system_header /* treat file as system include file */ #ifndef __ARM_COMPAT_H -#include /* Compatibility header for Arm Compiler 5 intrinsics */ + #include /* Compatibility header for Arm Compiler 5 intrinsics */ #endif /* CMSIS compiler specific defines */ #ifndef __ASM - #define __ASM __asm + #define __ASM __asm #endif #ifndef __INLINE - #define __INLINE __inline + #define __INLINE __inline #endif #ifndef __STATIC_INLINE - #define __STATIC_INLINE static __inline + #define __STATIC_INLINE static __inline #endif #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline #endif #ifndef __NO_RETURN - #define __NO_RETURN __attribute__((__noreturn__)) + #define __NO_RETURN __attribute__((__noreturn__)) #endif #ifndef __USED - #define __USED __attribute__((used)) + #define __USED __attribute__((used)) #endif #ifndef __WEAK - #define __WEAK __attribute__((weak)) + #define __WEAK __attribute__((weak)) #endif #ifndef __PACKED - #define __PACKED __attribute__((packed, aligned(1))) + #define __PACKED __attribute__((packed, aligned(1))) #endif #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) #endif #ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #define __PACKED_UNION union __attribute__((packed, aligned(1))) #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +struct __attribute__((packed)) T_UINT32 +{ + uint32_t v; +}; +#pragma clang diagnostic pop +#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #endif #ifndef __UNALIGNED_UINT16_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; +#pragma clang diagnostic pop +#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT16_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +__PACKED_STRUCT T_UINT16_READ { uint16_t v; }; +#pragma clang diagnostic pop +#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #endif #ifndef __UNALIGNED_UINT32_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; +#pragma clang diagnostic pop +#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT32_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +__PACKED_STRUCT T_UINT32_READ { uint32_t v; }; +#pragma clang diagnostic pop +#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #endif #ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) + #define __ALIGNED(x) __attribute__((aligned(x))) #endif #ifndef __RESTRICT - #define __RESTRICT __restrict -#endif -#ifndef __COMPILER_BARRIER - #define __COMPILER_BARRIER() __ASM volatile("":::"memory") + #define __RESTRICT __restrict #endif -/* ######################### Startup and Lowlevel Init ######################## */ - -#ifndef __PROGRAM_START -#define __PROGRAM_START __main -#endif - -#ifndef __INITIAL_SP -#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit -#endif - -#ifndef __STACK_LIMIT -#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base -#endif - -#ifndef __VECTOR_TABLE -#define __VECTOR_TABLE __Vectors -#endif - -#ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) -#endif /* ########################### Core Function Access ########################### */ /** \ingroup CMSIS_Core_FunctionInterface @@ -165,10 +144,10 @@ */ __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) { - uint32_t result; + uint32_t result; - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, control" : "=r"(result)); + return (result); } @@ -180,10 +159,10 @@ __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) */ __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) { - uint32_t result; + uint32_t result; - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, control_ns" : "=r"(result)); + return (result); } #endif @@ -195,7 +174,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) */ __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) { - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ASM volatile("MSR control, %0" : : "r"(control) : "memory"); } @@ -207,7 +186,7 @@ __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) */ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) { - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ASM volatile("MSR control_ns, %0" : : "r"(control) : "memory"); } #endif @@ -219,10 +198,10 @@ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) */ __STATIC_FORCEINLINE uint32_t __get_IPSR(void) { - uint32_t result; + uint32_t result; - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, ipsr" : "=r"(result)); + return (result); } @@ -233,10 +212,10 @@ __STATIC_FORCEINLINE uint32_t __get_IPSR(void) */ __STATIC_FORCEINLINE uint32_t __get_APSR(void) { - uint32_t result; + uint32_t result; - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, apsr" : "=r"(result)); + return (result); } @@ -247,10 +226,10 @@ __STATIC_FORCEINLINE uint32_t __get_APSR(void) */ __STATIC_FORCEINLINE uint32_t __get_xPSR(void) { - uint32_t result; + uint32_t result; - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, xpsr" : "=r"(result)); + return (result); } @@ -261,10 +240,10 @@ __STATIC_FORCEINLINE uint32_t __get_xPSR(void) */ __STATIC_FORCEINLINE uint32_t __get_PSP(void) { - uint32_t result; + uint32_t result; - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, psp" : "=r"(result)); + return (result); } @@ -276,10 +255,10 @@ __STATIC_FORCEINLINE uint32_t __get_PSP(void) */ __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) { - uint32_t result; + uint32_t result; - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, psp_ns" : "=r"(result)); + return (result); } #endif @@ -291,7 +270,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) */ __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) { - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); + __ASM volatile("MSR psp, %0" : : "r"(topOfProcStack) :); } @@ -303,7 +282,7 @@ __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) */ __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) { - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); + __ASM volatile("MSR psp_ns, %0" : : "r"(topOfProcStack) :); } #endif @@ -315,10 +294,10 @@ __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) */ __STATIC_FORCEINLINE uint32_t __get_MSP(void) { - uint32_t result; + uint32_t result; - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, msp" : "=r"(result)); + return (result); } @@ -330,10 +309,10 @@ __STATIC_FORCEINLINE uint32_t __get_MSP(void) */ __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) { - uint32_t result; + uint32_t result; - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, msp_ns" : "=r"(result)); + return (result); } #endif @@ -345,7 +324,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) */ __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) { - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); + __ASM volatile("MSR msp, %0" : : "r"(topOfMainStack) :); } @@ -357,7 +336,7 @@ __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) */ __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) { - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); + __ASM volatile("MSR msp_ns, %0" : : "r"(topOfMainStack) :); } #endif @@ -370,10 +349,10 @@ __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) */ __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) { - uint32_t result; + uint32_t result; - __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, sp_ns" : "=r"(result)); + return (result); } @@ -384,7 +363,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) */ __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) { - __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); + __ASM volatile("MSR sp_ns, %0" : : "r"(topOfStack) :); } #endif @@ -396,10 +375,10 @@ __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) */ __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) { - uint32_t result; + uint32_t result; - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, primask" : "=r"(result)); + return (result); } @@ -411,10 +390,10 @@ __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) */ __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) { - uint32_t result; + uint32_t result; - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, primask_ns" : "=r"(result)); + return (result); } #endif @@ -426,7 +405,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) */ __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) { - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + __ASM volatile("MSR primask, %0" : : "r"(priMask) : "memory"); } @@ -438,7 +417,7 @@ __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) */ __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) { - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); + __ASM volatile("MSR primask_ns, %0" : : "r"(priMask) : "memory"); } #endif @@ -469,10 +448,10 @@ __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) */ __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) { - uint32_t result; + uint32_t result; - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, basepri" : "=r"(result)); + return (result); } @@ -484,10 +463,10 @@ __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) */ __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) { - uint32_t result; + uint32_t result; - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, basepri_ns" : "=r"(result)); + return (result); } #endif @@ -499,7 +478,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) */ __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) { - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); + __ASM volatile("MSR basepri, %0" : : "r"(basePri) : "memory"); } @@ -511,7 +490,7 @@ __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) */ __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) { - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); + __ASM volatile("MSR basepri_ns, %0" : : "r"(basePri) : "memory"); } #endif @@ -524,7 +503,7 @@ __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) */ __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) { - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); + __ASM volatile("MSR basepri_max, %0" : : "r"(basePri) : "memory"); } @@ -535,10 +514,10 @@ __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) */ __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) { - uint32_t result; + uint32_t result; - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, faultmask" : "=r"(result)); + return (result); } @@ -550,10 +529,10 @@ __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) */ __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) { - uint32_t result; + uint32_t result; - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, faultmask_ns" : "=r"(result)); + return (result); } #endif @@ -565,7 +544,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) */ __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) { - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); + __ASM volatile("MSR faultmask, %0" : : "r"(faultMask) : "memory"); } @@ -577,7 +556,7 @@ __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) */ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) { - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); + __ASM volatile("MSR faultmask_ns, %0" : : "r"(faultMask) : "memory"); } #endif @@ -603,11 +582,11 @@ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; + return 0U; #else - uint32_t result; - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return result; + uint32_t result; + __ASM volatile("MRS %0, psplim" : "=r"(result)); + return result; #endif } @@ -624,12 +603,12 @@ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; #else - uint32_t result; - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return result; + uint32_t result; + __ASM volatile("MRS %0, psplim_ns" : "=r"(result)); + return result; #endif } #endif @@ -648,10 +627,10 @@ __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; #else - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); + __ASM volatile("MSR psplim, %0" : : "r"(ProcStackPtrLimit)); #endif } @@ -669,10 +648,10 @@ __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; #else - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); + __ASM volatile("MSR psplim_ns, %0\n" : : "r"(ProcStackPtrLimit)); #endif } #endif @@ -690,12 +669,12 @@ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; #else - uint32_t result; - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - return result; + uint32_t result; + __ASM volatile("MRS %0, msplim" : "=r"(result)); + return result; #endif } @@ -712,12 +691,12 @@ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; #else - uint32_t result; - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return result; + uint32_t result; + __ASM volatile("MRS %0, msplim_ns" : "=r"(result)); + return result; #endif } #endif @@ -735,10 +714,10 @@ __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; #else - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); + __ASM volatile("MSR msplim, %0" : : "r"(MainStackPtrLimit)); #endif } @@ -755,10 +734,10 @@ __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; #else - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); + __ASM volatile("MSR msplim_ns, %0" : : "r"(MainStackPtrLimit)); #endif } #endif @@ -804,13 +783,11 @@ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) * For thumb1, use low register (r0-r7), specified by constraint "l" * Otherwise, use general registers, specified by constraint "r" */ #if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_RW_REG(r) "+l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) + #define __CMSIS_GCC_OUT_REG(r) "=l" (r) + #define __CMSIS_GCC_USE_REG(r) "l" (r) #else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_RW_REG(r) "+r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) + #define __CMSIS_GCC_OUT_REG(r) "=r" (r) + #define __CMSIS_GCC_USE_REG(r) "r" (r) #endif /** @@ -847,14 +824,14 @@ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ -#define __ISB() __builtin_arm_isb(0xF) +#define __ISB() __builtin_arm_isb(0xF); /** \brief Data Synchronization Barrier \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ -#define __DSB() __builtin_arm_dsb(0xF) +#define __DSB() __builtin_arm_dsb(0xF); /** @@ -862,7 +839,7 @@ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) \details Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ -#define __DMB() __builtin_arm_dmb(0xF) +#define __DMB() __builtin_arm_dmb(0xF); /** @@ -901,12 +878,12 @@ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) */ __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) { - op2 %= 32U; - if (op2 == 0U) - { - return op1; - } - return (op1 >> op2) | (op1 << (32U - op2)); + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); } @@ -934,23 +911,7 @@ __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) \param [in] value Value to count the leading zeros \return number of leading zeros in value */ -__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) -{ - /* Even though __builtin_clz produces a CLZ instruction on ARM, formally - __builtin_clz(0) is undefined behaviour, so handle this case specially. - This guarantees ARM-compatible results if happening to compile on a non-ARM - target, and ensures the compiler doesn't decide to activate any - optimisations using the logic "value was passed to __builtin_clz, so it - is non-zero". - ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a - single CLZ instruction. - */ - if (value == 0U) - { - return 32U; - } - return __builtin_clz(value); -} +#define __CLZ (uint8_t)__builtin_clz #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ @@ -1062,10 +1023,10 @@ __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) */ __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) { - uint32_t result; + uint32_t result; - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); + __ASM volatile("rrx %0, %1" : __CMSIS_GCC_OUT_REG(result) : __CMSIS_GCC_USE_REG(value)); + return (result); } @@ -1077,10 +1038,10 @@ __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) */ __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) { - uint32_t result; + uint32_t result; - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); /* Add explicit type cast here */ + __ASM volatile("ldrbt %0, %1" : "=r"(result) : "Q"(*ptr)); + return ((uint8_t) result); /* Add explicit type cast here */ } @@ -1092,10 +1053,10 @@ __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) */ __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) { - uint32_t result; + uint32_t result; - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); /* Add explicit type cast here */ + __ASM volatile("ldrht %0, %1" : "=r"(result) : "Q"(*ptr)); + return ((uint16_t) result); /* Add explicit type cast here */ } @@ -1107,10 +1068,10 @@ __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) */ __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) { - uint32_t result; + uint32_t result; - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); + __ASM volatile("ldrt %0, %1" : "=r"(result) : "Q"(*ptr)); + return (result); } @@ -1122,7 +1083,7 @@ __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) */ __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) { - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); + __ASM volatile("strbt %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value)); } @@ -1134,7 +1095,7 @@ __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) */ __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) { - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); + __ASM volatile("strht %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value)); } @@ -1146,7 +1107,7 @@ __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) */ __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) { - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); + __ASM volatile("strt %1, %0" : "=Q"(*ptr) : "r"(value)); } #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ @@ -1162,20 +1123,20 @@ __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) */ __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) { - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) + if ((sat >= 1U) && (sat <= 32U)) { - return max; + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } } - else if (val < min) - { - return min; - } - } - return val; + return val; } /** @@ -1187,19 +1148,19 @@ __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) */ __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) { - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) + if (sat <= 31U) { - return max; + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; + return (uint32_t)val; } #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ @@ -1217,10 +1178,10 @@ __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) */ __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) { - uint32_t result; + uint32_t result; - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); + __ASM volatile("ldab %0, %1" : "=r"(result) : "Q"(*ptr)); + return ((uint8_t) result); } @@ -1232,10 +1193,10 @@ __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) */ __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) { - uint32_t result; + uint32_t result; - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); + __ASM volatile("ldah %0, %1" : "=r"(result) : "Q"(*ptr)); + return ((uint16_t) result); } @@ -1247,10 +1208,10 @@ __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) */ __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) { - uint32_t result; + uint32_t result; - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); + __ASM volatile("lda %0, %1" : "=r"(result) : "Q"(*ptr)); + return (result); } @@ -1262,7 +1223,7 @@ __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) */ __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) { - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); + __ASM volatile("stlb %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value)); } @@ -1274,7 +1235,7 @@ __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) */ __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) { - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); + __ASM volatile("stlh %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value)); } @@ -1286,7 +1247,7 @@ __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) */ __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) { - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); + __ASM volatile("stl %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value)); } @@ -1352,7 +1313,7 @@ __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ -/**@}*/ /* end of group CMSIS_Core_InstructionInterface */ +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ /* ################### Compiler specific Intrinsics ########################### */ @@ -1363,65 +1324,536 @@ __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) -#define __SADD8 __builtin_arm_sadd8 -#define __QADD8 __builtin_arm_qadd8 -#define __SHADD8 __builtin_arm_shadd8 -#define __UADD8 __builtin_arm_uadd8 -#define __UQADD8 __builtin_arm_uqadd8 -#define __UHADD8 __builtin_arm_uhadd8 -#define __SSUB8 __builtin_arm_ssub8 -#define __QSUB8 __builtin_arm_qsub8 -#define __SHSUB8 __builtin_arm_shsub8 -#define __USUB8 __builtin_arm_usub8 -#define __UQSUB8 __builtin_arm_uqsub8 -#define __UHSUB8 __builtin_arm_uhsub8 -#define __SADD16 __builtin_arm_sadd16 -#define __QADD16 __builtin_arm_qadd16 -#define __SHADD16 __builtin_arm_shadd16 -#define __UADD16 __builtin_arm_uadd16 -#define __UQADD16 __builtin_arm_uqadd16 -#define __UHADD16 __builtin_arm_uhadd16 -#define __SSUB16 __builtin_arm_ssub16 -#define __QSUB16 __builtin_arm_qsub16 -#define __SHSUB16 __builtin_arm_shsub16 -#define __USUB16 __builtin_arm_usub16 -#define __UQSUB16 __builtin_arm_uqsub16 -#define __UHSUB16 __builtin_arm_uhsub16 -#define __SASX __builtin_arm_sasx -#define __QASX __builtin_arm_qasx -#define __SHASX __builtin_arm_shasx -#define __UASX __builtin_arm_uasx -#define __UQASX __builtin_arm_uqasx -#define __UHASX __builtin_arm_uhasx -#define __SSAX __builtin_arm_ssax -#define __QSAX __builtin_arm_qsax -#define __SHSAX __builtin_arm_shsax -#define __USAX __builtin_arm_usax -#define __UQSAX __builtin_arm_uqsax -#define __UHSAX __builtin_arm_uhsax -#define __USAD8 __builtin_arm_usad8 -#define __USADA8 __builtin_arm_usada8 -#define __SSAT16 __builtin_arm_ssat16 -#define __USAT16 __builtin_arm_usat16 -#define __UXTB16 __builtin_arm_uxtb16 -#define __UXTAB16 __builtin_arm_uxtab16 -#define __SXTB16 __builtin_arm_sxtb16 -#define __SXTAB16 __builtin_arm_sxtab16 -#define __SMUAD __builtin_arm_smuad -#define __SMUADX __builtin_arm_smuadx -#define __SMLAD __builtin_arm_smlad -#define __SMLADX __builtin_arm_smladx -#define __SMLALD __builtin_arm_smlald -#define __SMLALDX __builtin_arm_smlaldx -#define __SMUSD __builtin_arm_smusd -#define __SMUSDX __builtin_arm_smusdx -#define __SMLSD __builtin_arm_smlsd -#define __SMLSDX __builtin_arm_smlsdx -#define __SMLSLD __builtin_arm_smlsld -#define __SMLSLDX __builtin_arm_smlsldx -#define __SEL __builtin_arm_sel -#define __QADD __builtin_arm_qadd -#define __QSUB __builtin_arm_qsub +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("sadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("qadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("shadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uqadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uhadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("ssub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("qsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("shsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("usub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uqsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uhsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("sadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("qadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("shadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uqadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uhadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("ssub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("qsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("shsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("usub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uqsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uhsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("sasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("qasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("shasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uqasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uhasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("ssax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("qsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("shsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("usax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uqsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uhsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("usad8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile("usada8 %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); + return (result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile("uxtb16 %0, %1" : "=r"(result) : "r"(op1)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uxtab16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile("sxtb16 %0, %1" : "=r"(result) : "r"(op1)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("sxtab16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("smuad %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("smuadx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile("smlad %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile("smladx %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); + return (result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD(uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u + { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile("smlald %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]): "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); +#else /* Big endian */ + __ASM volatile("smlald %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]): "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); +#endif + + return (llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX(uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u + { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile("smlaldx %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]): "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); +#else /* Big endian */ + __ASM volatile("smlaldx %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]): "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); +#endif + + return (llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("smusd %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("smusdx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile("smlsd %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile("smlsdx %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); + return (result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD(uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u + { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile("smlsld %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]): "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); +#else /* Big endian */ + __ASM volatile("smlsld %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]): "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); +#endif + + return (llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX(uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u + { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile("smlsldx %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]): "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); +#else /* Big endian */ + __ASM volatile("smlsldx %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]): "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); +#endif + + return (llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("sel %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE int32_t __QADD(int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile("qadd %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE int32_t __QSUB(int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile("qsub %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) @@ -1429,16 +1861,16 @@ __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) -__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +__STATIC_FORCEINLINE int32_t __SMMLA(int32_t op1, int32_t op2, int32_t op3) { - int32_t result; + int32_t result; - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); + __ASM volatile("smmla %0, %1, %2, %3" : "=r"(result): "r"(op1), "r"(op2), "r"(op3)); + return (result); } #endif /* (__ARM_FEATURE_DSP == 1) */ -/**@} end of group CMSIS_SIMD_intrinsics */ +/*@} end of group CMSIS_SIMD_intrinsics */ #endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_armclang_ltm.h b/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_armclang_ltm.h index 356182c5f9..f80786e767 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_armclang_ltm.h +++ b/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_armclang_ltm.h @@ -30,110 +30,113 @@ #pragma clang system_header /* treat file as system include file */ #ifndef __ARM_COMPAT_H -#include /* Compatibility header for Arm Compiler 5 intrinsics */ + #include /* Compatibility header for Arm Compiler 5 intrinsics */ #endif /* CMSIS compiler specific defines */ #ifndef __ASM - #define __ASM __asm + #define __ASM __asm #endif #ifndef __INLINE - #define __INLINE __inline + #define __INLINE __inline #endif #ifndef __STATIC_INLINE - #define __STATIC_INLINE static __inline + #define __STATIC_INLINE static __inline #endif #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline #endif #ifndef __NO_RETURN - #define __NO_RETURN __attribute__((__noreturn__)) + #define __NO_RETURN __attribute__((__noreturn__)) #endif #ifndef __USED - #define __USED __attribute__((used)) + #define __USED __attribute__((used)) #endif #ifndef __WEAK - #define __WEAK __attribute__((weak)) + #define __WEAK __attribute__((weak)) #endif #ifndef __PACKED - #define __PACKED __attribute__((packed, aligned(1))) + #define __PACKED __attribute__((packed, aligned(1))) #endif #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) #endif #ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #define __PACKED_UNION union __attribute__((packed, aligned(1))) #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +struct __attribute__((packed)) T_UINT32 +{ + uint32_t v; +}; +#pragma clang diagnostic pop +#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #endif #ifndef __UNALIGNED_UINT16_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; +#pragma clang diagnostic pop +#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT16_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +__PACKED_STRUCT T_UINT16_READ { uint16_t v; }; +#pragma clang diagnostic pop +#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #endif #ifndef __UNALIGNED_UINT32_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; +#pragma clang diagnostic pop +#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT32_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +__PACKED_STRUCT T_UINT32_READ { uint32_t v; }; +#pragma clang diagnostic pop +#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #endif #ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) + #define __ALIGNED(x) __attribute__((aligned(x))) #endif #ifndef __RESTRICT - #define __RESTRICT __restrict + #define __RESTRICT __restrict #endif #ifndef __COMPILER_BARRIER - #define __COMPILER_BARRIER() __ASM volatile("":::"memory") + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") #endif /* ######################### Startup and Lowlevel Init ######################## */ #ifndef __PROGRAM_START -#define __PROGRAM_START __main + #define __PROGRAM_START __main #endif #ifndef __INITIAL_SP -#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit + #define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit #endif #ifndef __STACK_LIMIT -#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base + #define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base #endif #ifndef __VECTOR_TABLE -#define __VECTOR_TABLE __Vectors + #define __VECTOR_TABLE __Vectors #endif #ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) + #define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) #endif @@ -166,10 +169,10 @@ */ __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) { - uint32_t result; + uint32_t result; - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, control" : "=r"(result)); + return (result); } @@ -181,10 +184,10 @@ __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) */ __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) { - uint32_t result; + uint32_t result; - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, control_ns" : "=r"(result)); + return (result); } #endif @@ -196,7 +199,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) */ __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) { - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ASM volatile("MSR control, %0" : : "r"(control) : "memory"); } @@ -208,7 +211,7 @@ __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) */ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) { - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ASM volatile("MSR control_ns, %0" : : "r"(control) : "memory"); } #endif @@ -220,10 +223,10 @@ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) */ __STATIC_FORCEINLINE uint32_t __get_IPSR(void) { - uint32_t result; + uint32_t result; - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, ipsr" : "=r"(result)); + return (result); } @@ -234,10 +237,10 @@ __STATIC_FORCEINLINE uint32_t __get_IPSR(void) */ __STATIC_FORCEINLINE uint32_t __get_APSR(void) { - uint32_t result; + uint32_t result; - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, apsr" : "=r"(result)); + return (result); } @@ -248,10 +251,10 @@ __STATIC_FORCEINLINE uint32_t __get_APSR(void) */ __STATIC_FORCEINLINE uint32_t __get_xPSR(void) { - uint32_t result; + uint32_t result; - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, xpsr" : "=r"(result)); + return (result); } @@ -262,10 +265,10 @@ __STATIC_FORCEINLINE uint32_t __get_xPSR(void) */ __STATIC_FORCEINLINE uint32_t __get_PSP(void) { - uint32_t result; + uint32_t result; - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, psp" : "=r"(result)); + return (result); } @@ -277,10 +280,10 @@ __STATIC_FORCEINLINE uint32_t __get_PSP(void) */ __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) { - uint32_t result; + uint32_t result; - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, psp_ns" : "=r"(result)); + return (result); } #endif @@ -292,7 +295,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) */ __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) { - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); + __ASM volatile("MSR psp, %0" : : "r"(topOfProcStack) :); } @@ -304,7 +307,7 @@ __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) */ __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) { - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); + __ASM volatile("MSR psp_ns, %0" : : "r"(topOfProcStack) :); } #endif @@ -316,10 +319,10 @@ __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) */ __STATIC_FORCEINLINE uint32_t __get_MSP(void) { - uint32_t result; + uint32_t result; - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, msp" : "=r"(result)); + return (result); } @@ -331,10 +334,10 @@ __STATIC_FORCEINLINE uint32_t __get_MSP(void) */ __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) { - uint32_t result; + uint32_t result; - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, msp_ns" : "=r"(result)); + return (result); } #endif @@ -346,7 +349,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) */ __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) { - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); + __ASM volatile("MSR msp, %0" : : "r"(topOfMainStack) :); } @@ -358,7 +361,7 @@ __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) */ __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) { - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); + __ASM volatile("MSR msp_ns, %0" : : "r"(topOfMainStack) :); } #endif @@ -371,10 +374,10 @@ __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) */ __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) { - uint32_t result; + uint32_t result; - __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, sp_ns" : "=r"(result)); + return (result); } @@ -385,7 +388,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) */ __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) { - __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); + __ASM volatile("MSR sp_ns, %0" : : "r"(topOfStack) :); } #endif @@ -397,10 +400,10 @@ __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) */ __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) { - uint32_t result; + uint32_t result; - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, primask" : "=r"(result)); + return (result); } @@ -412,10 +415,10 @@ __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) */ __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) { - uint32_t result; + uint32_t result; - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, primask_ns" : "=r"(result)); + return (result); } #endif @@ -427,7 +430,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) */ __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) { - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + __ASM volatile("MSR primask, %0" : : "r"(priMask) : "memory"); } @@ -439,7 +442,7 @@ __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) */ __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) { - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); + __ASM volatile("MSR primask_ns, %0" : : "r"(priMask) : "memory"); } #endif @@ -470,10 +473,10 @@ __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) */ __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) { - uint32_t result; + uint32_t result; - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, basepri" : "=r"(result)); + return (result); } @@ -485,10 +488,10 @@ __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) */ __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) { - uint32_t result; + uint32_t result; - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, basepri_ns" : "=r"(result)); + return (result); } #endif @@ -500,7 +503,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) */ __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) { - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); + __ASM volatile("MSR basepri, %0" : : "r"(basePri) : "memory"); } @@ -512,7 +515,7 @@ __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) */ __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) { - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); + __ASM volatile("MSR basepri_ns, %0" : : "r"(basePri) : "memory"); } #endif @@ -525,7 +528,7 @@ __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) */ __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) { - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); + __ASM volatile("MSR basepri_max, %0" : : "r"(basePri) : "memory"); } @@ -536,10 +539,10 @@ __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) */ __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) { - uint32_t result; + uint32_t result; - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, faultmask" : "=r"(result)); + return (result); } @@ -551,10 +554,10 @@ __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) */ __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) { - uint32_t result; + uint32_t result; - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, faultmask_ns" : "=r"(result)); + return (result); } #endif @@ -566,7 +569,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) */ __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) { - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); + __ASM volatile("MSR faultmask, %0" : : "r"(faultMask) : "memory"); } @@ -578,7 +581,7 @@ __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) */ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) { - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); + __ASM volatile("MSR faultmask_ns, %0" : : "r"(faultMask) : "memory"); } #endif @@ -604,11 +607,11 @@ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; + return 0U; #else - uint32_t result; - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return result; + uint32_t result; + __ASM volatile("MRS %0, psplim" : "=r"(result)); + return result; #endif } @@ -625,12 +628,12 @@ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; #else - uint32_t result; - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return result; + uint32_t result; + __ASM volatile("MRS %0, psplim_ns" : "=r"(result)); + return result; #endif } #endif @@ -649,10 +652,10 @@ __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; #else - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); + __ASM volatile("MSR psplim, %0" : : "r"(ProcStackPtrLimit)); #endif } @@ -670,10 +673,10 @@ __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; #else - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); + __ASM volatile("MSR psplim_ns, %0\n" : : "r"(ProcStackPtrLimit)); #endif } #endif @@ -691,12 +694,12 @@ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; #else - uint32_t result; - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - return result; + uint32_t result; + __ASM volatile("MRS %0, msplim" : "=r"(result)); + return result; #endif } @@ -713,12 +716,12 @@ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; #else - uint32_t result; - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return result; + uint32_t result; + __ASM volatile("MRS %0, msplim_ns" : "=r"(result)); + return result; #endif } #endif @@ -736,10 +739,10 @@ __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; #else - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); + __ASM volatile("MSR msplim, %0" : : "r"(MainStackPtrLimit)); #endif } @@ -756,10 +759,10 @@ __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; #else - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); + __ASM volatile("MSR msplim_ns, %0" : : "r"(MainStackPtrLimit)); #endif } #endif @@ -805,11 +808,11 @@ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) * For thumb1, use low register (r0-r7), specified by constraint "l" * Otherwise, use general registers, specified by constraint "r" */ #if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) + #define __CMSIS_GCC_OUT_REG(r) "=l" (r) + #define __CMSIS_GCC_USE_REG(r) "l" (r) #else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) + #define __CMSIS_GCC_OUT_REG(r) "=r" (r) + #define __CMSIS_GCC_USE_REG(r) "r" (r) #endif /** @@ -900,12 +903,12 @@ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) */ __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) { - op2 %= 32U; - if (op2 == 0U) - { - return op1; - } - return (op1 >> op2) | (op1 << (32U - op2)); + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); } @@ -935,20 +938,20 @@ __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) */ __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) { - /* Even though __builtin_clz produces a CLZ instruction on ARM, formally - __builtin_clz(0) is undefined behaviour, so handle this case specially. - This guarantees ARM-compatible results if happening to compile on a non-ARM - target, and ensures the compiler doesn't decide to activate any - optimisations using the logic "value was passed to __builtin_clz, so it - is non-zero". - ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a - single CLZ instruction. - */ - if (value == 0U) - { - return 32U; - } - return __builtin_clz(value); + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); } @@ -1061,10 +1064,10 @@ __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) */ __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) { - uint32_t result; + uint32_t result; - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); + __ASM volatile("rrx %0, %1" : __CMSIS_GCC_OUT_REG(result) : __CMSIS_GCC_USE_REG(value)); + return (result); } @@ -1076,10 +1079,10 @@ __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) */ __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) { - uint32_t result; + uint32_t result; - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); /* Add explicit type cast here */ + __ASM volatile("ldrbt %0, %1" : "=r"(result) : "Q"(*ptr)); + return ((uint8_t) result); /* Add explicit type cast here */ } @@ -1091,10 +1094,10 @@ __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) */ __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) { - uint32_t result; + uint32_t result; - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); /* Add explicit type cast here */ + __ASM volatile("ldrht %0, %1" : "=r"(result) : "Q"(*ptr)); + return ((uint16_t) result); /* Add explicit type cast here */ } @@ -1106,10 +1109,10 @@ __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) */ __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) { - uint32_t result; + uint32_t result; - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); + __ASM volatile("ldrt %0, %1" : "=r"(result) : "Q"(*ptr)); + return (result); } @@ -1121,7 +1124,7 @@ __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) */ __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) { - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); + __ASM volatile("strbt %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value)); } @@ -1133,7 +1136,7 @@ __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) */ __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) { - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); + __ASM volatile("strht %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value)); } @@ -1145,7 +1148,7 @@ __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) */ __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) { - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); + __ASM volatile("strt %1, %0" : "=Q"(*ptr) : "r"(value)); } #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ @@ -1161,20 +1164,20 @@ __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) */ __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) { - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) + if ((sat >= 1U) && (sat <= 32U)) { - return max; + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } } - else if (val < min) - { - return min; - } - } - return val; + return val; } /** @@ -1186,19 +1189,19 @@ __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) */ __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) { - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) + if (sat <= 31U) { - return max; + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; + return (uint32_t)val; } #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ @@ -1216,10 +1219,10 @@ __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) */ __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) { - uint32_t result; + uint32_t result; - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); + __ASM volatile("ldab %0, %1" : "=r"(result) : "Q"(*ptr)); + return ((uint8_t) result); } @@ -1231,10 +1234,10 @@ __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) */ __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) { - uint32_t result; + uint32_t result; - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); + __ASM volatile("ldah %0, %1" : "=r"(result) : "Q"(*ptr)); + return ((uint16_t) result); } @@ -1246,10 +1249,10 @@ __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) */ __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) { - uint32_t result; + uint32_t result; - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); + __ASM volatile("lda %0, %1" : "=r"(result) : "Q"(*ptr)); + return (result); } @@ -1261,7 +1264,7 @@ __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) */ __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) { - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); + __ASM volatile("stlb %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value)); } @@ -1273,7 +1276,7 @@ __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) */ __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) { - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); + __ASM volatile("stlh %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value)); } @@ -1285,7 +1288,7 @@ __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) */ __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) { - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); + __ASM volatile("stl %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value)); } @@ -1364,308 +1367,308 @@ __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) __STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("sadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); } __STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("qadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); } __STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("shadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); } __STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("uadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); } __STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("uqadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); } __STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("uhadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); } __STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("ssub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); } __STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("qsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); } __STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("shsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); } __STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("usub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); } __STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("uqsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); } __STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("uhsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); } __STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("sadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); } __STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("qadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); } __STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("shadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); } __STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("uadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); } __STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("uqadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); } __STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("uhadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); } __STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("ssub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); } __STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("qsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); } __STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("shsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); } __STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("usub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); } __STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("uqsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); } __STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("uhsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); } __STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("sasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); } __STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("qasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); } __STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("shasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); } __STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("uasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); } __STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("uqasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); } __STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("uhasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); } __STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("ssax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); } __STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("qsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); } __STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("shsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); } __STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("usax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); } __STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("uqsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); } __STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("uhsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); } __STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("usad8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); } __STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) { - uint32_t result; + uint32_t result; - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); + __ASM volatile("usada8 %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); + return (result); } #define __SSAT16(ARG1,ARG2) \ @@ -1684,190 +1687,194 @@ __STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) __STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) { - uint32_t result; + uint32_t result; - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); + __ASM volatile("uxtb16 %0, %1" : "=r"(result) : "r"(op1)); + return (result); } __STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("uxtab16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); } __STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) { - uint32_t result; + uint32_t result; - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); + __ASM volatile("sxtb16 %0, %1" : "=r"(result) : "r"(op1)); + return (result); } __STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("sxtab16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); } -__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SMUAD(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("smuad %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); } -__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SMUADX(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("smuadx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); } -__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +__STATIC_FORCEINLINE uint32_t __SMLAD(uint32_t op1, uint32_t op2, uint32_t op3) { - uint32_t result; + uint32_t result; - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); + __ASM volatile("smlad %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); + return (result); } -__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +__STATIC_FORCEINLINE uint32_t __SMLADX(uint32_t op1, uint32_t op2, uint32_t op3) { - uint32_t result; + uint32_t result; - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); + __ASM volatile("smladx %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); + return (result); } -__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +__STATIC_FORCEINLINE uint64_t __SMLALD(uint32_t op1, uint32_t op2, uint64_t acc) { - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; + union llreg_u + { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); + __ASM volatile("smlald %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]): "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); #else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); + __ASM volatile("smlald %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]): "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); #endif - return(llr.w64); + return (llr.w64); } -__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +__STATIC_FORCEINLINE uint64_t __SMLALDX(uint32_t op1, uint32_t op2, uint64_t acc) { - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; + union llreg_u + { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); + __ASM volatile("smlaldx %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]): "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); #else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); + __ASM volatile("smlaldx %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]): "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); #endif - return(llr.w64); + return (llr.w64); } -__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SMUSD(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("smusd %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); } -__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SMUSDX(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("smusdx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); } -__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +__STATIC_FORCEINLINE uint32_t __SMLSD(uint32_t op1, uint32_t op2, uint32_t op3) { - uint32_t result; + uint32_t result; - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); + __ASM volatile("smlsd %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); + return (result); } -__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +__STATIC_FORCEINLINE uint32_t __SMLSDX(uint32_t op1, uint32_t op2, uint32_t op3) { - uint32_t result; + uint32_t result; - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); + __ASM volatile("smlsdx %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); + return (result); } -__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +__STATIC_FORCEINLINE uint64_t __SMLSLD(uint32_t op1, uint32_t op2, uint64_t acc) { - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; + union llreg_u + { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); + __ASM volatile("smlsld %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]): "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); #else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); + __ASM volatile("smlsld %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]): "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); #endif - return(llr.w64); + return (llr.w64); } -__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +__STATIC_FORCEINLINE uint64_t __SMLSLDX(uint32_t op1, uint32_t op2, uint64_t acc) { - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; + union llreg_u + { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); + __ASM volatile("smlsldx %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]): "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); #else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); + __ASM volatile("smlsldx %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]): "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); #endif - return(llr.w64); + return (llr.w64); } -__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SEL(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("sel %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); } -__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +__STATIC_FORCEINLINE int32_t __QADD(int32_t op1, int32_t op2) { - int32_t result; + int32_t result; - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("qadd %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); } -__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +__STATIC_FORCEINLINE int32_t __QSUB(int32_t op1, int32_t op2) { - int32_t result; + int32_t result; - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("qsub %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); } #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ @@ -1876,12 +1883,12 @@ __STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) -__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +__STATIC_FORCEINLINE int32_t __SMMLA(int32_t op1, int32_t op2, int32_t op3) { - int32_t result; + int32_t result; - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); + __ASM volatile("smmla %0, %1, %2, %3" : "=r"(result): "r"(op1), "r"(op2), "r"(op3)); + return (result); } #endif /* (__ARM_FEATURE_DSP == 1) */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_compiler.h b/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_compiler.h index adbf296f15..30d5800c0e 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_compiler.h +++ b/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_compiler.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file cmsis_compiler.h * @brief CMSIS compiler generic header file - * @version V5.1.0 - * @date 09. October 2018 + * @version V5.0.4 + * @date 10. January 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. @@ -31,251 +31,243 @@ * Arm Compiler 4/5 */ #if defined ( __CC_ARM ) - #include "cmsis_armcc.h" +#include "cmsis_armcc.h" /* - * Arm Compiler 6.6 LTM (armclang) + * Arm Compiler 6 (armclang) */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) - #include "cmsis_armclang_ltm.h" - - /* - * Arm Compiler above 6.10.1 (armclang) - */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) - #include "cmsis_armclang.h" +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#include "cmsis_armclang.h" /* * GNU Compiler */ #elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" +#include "cmsis_gcc.h" /* * IAR Compiler */ #elif defined ( __ICCARM__ ) - #include +#include /* * TI Arm Compiler */ #elif defined ( __TI_ARM__ ) - #include +#include - #ifndef __ASM +#ifndef __ASM #define __ASM __asm - #endif - #ifndef __INLINE +#endif +#ifndef __INLINE #define __INLINE inline - #endif - #ifndef __STATIC_INLINE +#endif +#ifndef __STATIC_INLINE #define __STATIC_INLINE static inline - #endif - #ifndef __STATIC_FORCEINLINE +#endif +#ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __STATIC_INLINE - #endif - #ifndef __NO_RETURN +#endif +#ifndef __NO_RETURN #define __NO_RETURN __attribute__((noreturn)) - #endif - #ifndef __USED +#endif +#ifndef __USED #define __USED __attribute__((used)) - #endif - #ifndef __WEAK +#endif +#ifndef __WEAK #define __WEAK __attribute__((weak)) - #endif - #ifndef __PACKED +#endif +#ifndef __PACKED #define __PACKED __attribute__((packed)) - #endif - #ifndef __PACKED_STRUCT +#endif +#ifndef __PACKED_STRUCT #define __PACKED_STRUCT struct __attribute__((packed)) - #endif - #ifndef __PACKED_UNION +#endif +#ifndef __PACKED_UNION #define __PACKED_UNION union __attribute__((packed)) - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ +struct __attribute__((packed)) T_UINT32 +{ + uint32_t v; +}; +#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE +__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; +#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ +__PACKED_STRUCT T_UINT16_READ { uint16_t v; }; +#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE +__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; +#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ +__PACKED_STRUCT T_UINT32_READ { uint32_t v; }; +#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED #define __ALIGNED(x) __attribute__((aligned(x))) - #endif - #ifndef __RESTRICT - #define __RESTRICT __restrict - #endif - #ifndef __COMPILER_BARRIER - #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. - #define __COMPILER_BARRIER() (void)0 - #endif +#endif +#ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT +#endif /* * TASKING Compiler */ #elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ - #ifndef __ASM +#ifndef __ASM #define __ASM __asm - #endif - #ifndef __INLINE +#endif +#ifndef __INLINE #define __INLINE inline - #endif - #ifndef __STATIC_INLINE +#endif +#ifndef __STATIC_INLINE #define __STATIC_INLINE static inline - #endif - #ifndef __STATIC_FORCEINLINE +#endif +#ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __STATIC_INLINE - #endif - #ifndef __NO_RETURN +#endif +#ifndef __NO_RETURN #define __NO_RETURN __attribute__((noreturn)) - #endif - #ifndef __USED +#endif +#ifndef __USED #define __USED __attribute__((used)) - #endif - #ifndef __WEAK +#endif +#ifndef __WEAK #define __WEAK __attribute__((weak)) - #endif - #ifndef __PACKED +#endif +#ifndef __PACKED #define __PACKED __packed__ - #endif - #ifndef __PACKED_STRUCT +#endif +#ifndef __PACKED_STRUCT #define __PACKED_STRUCT struct __packed__ - #endif - #ifndef __PACKED_UNION +#endif +#ifndef __PACKED_UNION #define __PACKED_UNION union __packed__ - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - struct __packed__ T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ +struct __packed__ T_UINT32 +{ + uint32_t v; +}; +#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE +__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; +#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ +__PACKED_STRUCT T_UINT16_READ { uint16_t v; }; +#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE +__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; +#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ +__PACKED_STRUCT T_UINT32_READ { uint32_t v; }; +#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED #define __ALIGNED(x) __align(x) - #endif - #ifndef __RESTRICT +#endif +#ifndef __RESTRICT #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. #define __RESTRICT - #endif - #ifndef __COMPILER_BARRIER - #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. - #define __COMPILER_BARRIER() (void)0 - #endif +#endif /* * COSMIC Compiler */ #elif defined ( __CSMC__ ) - #include +#include - #ifndef __ASM +#ifndef __ASM #define __ASM _asm - #endif - #ifndef __INLINE +#endif +#ifndef __INLINE #define __INLINE inline - #endif - #ifndef __STATIC_INLINE +#endif +#ifndef __STATIC_INLINE #define __STATIC_INLINE static inline - #endif - #ifndef __STATIC_FORCEINLINE +#endif +#ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __STATIC_INLINE - #endif - #ifndef __NO_RETURN +#endif +#ifndef __NO_RETURN // NO RETURN is automatically detected hence no warning here #define __NO_RETURN - #endif - #ifndef __USED +#endif +#ifndef __USED #warning No compiler specific solution for __USED. __USED is ignored. #define __USED - #endif - #ifndef __WEAK +#endif +#ifndef __WEAK #define __WEAK __weak - #endif - #ifndef __PACKED +#endif +#ifndef __PACKED #define __PACKED @packed - #endif - #ifndef __PACKED_STRUCT +#endif +#ifndef __PACKED_STRUCT #define __PACKED_STRUCT @packed struct - #endif - #ifndef __PACKED_UNION +#endif +#ifndef __PACKED_UNION #define __PACKED_UNION @packed union - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - @packed struct T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ +@packed struct T_UINT32 +{ + uint32_t v; +}; +#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE +__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; +#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ +__PACKED_STRUCT T_UINT16_READ { uint16_t v; }; +#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE +__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; +#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ +__PACKED_STRUCT T_UINT32_READ { uint32_t v; }; +#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. #define __ALIGNED(x) - #endif - #ifndef __RESTRICT +#endif +#ifndef __RESTRICT #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. #define __RESTRICT - #endif - #ifndef __COMPILER_BARRIER - #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. - #define __COMPILER_BARRIER() (void)0 - #endif +#endif #else - #error Unknown compiler. +#error Unknown compiler. #endif diff --git a/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_gcc.h b/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 0000000000..9c86a21ba3 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,2092 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.0.4 + * @date 09. April 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpacked" +#pragma GCC diagnostic ignored "-Wattributes" +struct __attribute__((packed)) T_UINT32 +{ + uint32_t v; +}; +#pragma GCC diagnostic pop +#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpacked" +#pragma GCC diagnostic ignored "-Wattributes" +__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; +#pragma GCC diagnostic pop +#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpacked" +#pragma GCC diagnostic ignored "-Wattributes" +__PACKED_STRUCT T_UINT16_READ { uint16_t v; }; +#pragma GCC diagnostic pop +#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpacked" +#pragma GCC diagnostic ignored "-Wattributes" +__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; +#pragma GCC diagnostic pop +#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpacked" +#pragma GCC diagnostic ignored "-Wattributes" +__PACKED_STRUCT T_UINT32_READ { uint32_t v; }; +#pragma GCC diagnostic pop +#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, control" : "=r"(result)); + return (result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, control_ns" : "=r"(result)); + return (result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile("MSR control, %0" : : "r"(control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile("MSR control_ns, %0" : : "r"(control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, ipsr" : "=r"(result)); + return (result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, apsr" : "=r"(result)); + return (result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, xpsr" : "=r"(result)); + return (result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, psp" : "=r"(result)); + return (result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, psp_ns" : "=r"(result)); + return (result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile("MSR psp, %0" : : "r"(topOfProcStack) :); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile("MSR psp_ns, %0" : : "r"(topOfProcStack) :); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, msp" : "=r"(result)); + return (result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, msp_ns" : "=r"(result)); + return (result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile("MSR msp, %0" : : "r"(topOfMainStack) :); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile("MSR msp_ns, %0" : : "r"(topOfMainStack) :); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, sp_ns" : "=r"(result)); + return (result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile("MSR sp_ns, %0" : : "r"(topOfStack) :); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, primask" : "=r"(result) :: "memory"); + return (result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, primask_ns" : "=r"(result) :: "memory"); + return (result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile("MSR primask, %0" : : "r"(priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile("MSR primask_ns, %0" : : "r"(priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, basepri" : "=r"(result)); + return (result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, basepri_ns" : "=r"(result)); + return (result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile("MSR basepri, %0" : : "r"(basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile("MSR basepri_ns, %0" : : "r"(basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile("MSR basepri_max, %0" : : "r"(basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, faultmask" : "=r"(result)); + return (result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, faultmask_ns" : "=r"(result)); + return (result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile("MSR faultmask, %0" : : "r"(faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile("MSR faultmask_ns, %0" : : "r"(faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile("MRS %0, psplim" : "=r"(result)); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile("MRS %0, psplim_ns" : "=r"(result)); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile("MSR psplim, %0" : : "r"(ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile("MSR psplim_ns, %0\n" : : "r"(ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile("MRS %0, msplim" : "=r"(result)); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile("MRS %0, msplim_ns" : "=r"(result)); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile("MSR msplim, %0" : : "r"(MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile("MSR msplim_ns, %0" : : "r"(MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile("VMRS %0, fpscr" : "=r"(result)); + return (result); +#endif +#else + return (0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile("VMSR fpscr, %0" : : "r"(fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) + #define __CMSIS_GCC_OUT_REG(r) "=l" (r) + #define __CMSIS_GCC_RW_REG(r) "+l" (r) + #define __CMSIS_GCC_USE_REG(r) "l" (r) +#else + #define __CMSIS_GCC_OUT_REG(r) "=r" (r) + #define __CMSIS_GCC_RW_REG(r) "+r" (r) + #define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile("isb 0xF"::: "memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile("dsb 0xF"::: "memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile("dmb 0xF"::: "memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile("rev %0, %1" : __CMSIS_GCC_OUT_REG(result) : __CMSIS_GCC_USE_REG(value)); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile("rev16 %0, %1" : __CMSIS_GCC_OUT_REG(result) : __CMSIS_GCC_USE_REG(value)); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile("revsh %0, %1" : __CMSIS_GCC_OUT_REG(result) : __CMSIS_GCC_USE_REG(value)); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile("rbit %0, %1" : "=r"(result) : "r"(value)); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile("ldrexb %0, %1" : "=r"(result) : "Q"(*addr)); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile("ldrexb %0, [%1]" : "=r"(result) : "r"(addr) : "memory"); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile("ldrexh %0, %1" : "=r"(result) : "Q"(*addr)); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile("ldrexh %0, [%1]" : "=r"(result) : "r"(addr) : "memory"); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile("ldrex %0, %1" : "=r"(result) : "Q"(*addr)); + return (result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile("strexb %0, %2, %1" : "=&r"(result), "=Q"(*addr) : "r"((uint32_t)value)); + return (result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile("strexh %0, %2, %1" : "=&r"(result), "=Q"(*addr) : "r"((uint32_t)value)); + return (result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile("strex %0, %2, %1" : "=&r"(result), "=Q"(*addr) : "r"(value)); + return (result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile("rrx %0, %1" : __CMSIS_GCC_OUT_REG(result) : __CMSIS_GCC_USE_REG(value)); + return (result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile("ldrbt %0, %1" : "=r"(result) : "Q"(*ptr)); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile("ldrbt %0, [%1]" : "=r"(result) : "r"(ptr) : "memory"); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile("ldrht %0, %1" : "=r"(result) : "Q"(*ptr)); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile("ldrht %0, [%1]" : "=r"(result) : "r"(ptr) : "memory"); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile("ldrt %0, %1" : "=r"(result) : "Q"(*ptr)); + return (result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile("strbt %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value)); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile("strht %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value)); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile("strt %1, %0" : "=Q"(*ptr) : "r"(value)); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile("ldab %0, %1" : "=r"(result) : "Q"(*ptr)); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile("ldah %0, %1" : "=r"(result) : "Q"(*ptr)); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile("lda %0, %1" : "=r"(result) : "Q"(*ptr)); + return (result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile("stlb %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value)); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile("stlh %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value)); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile("stl %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value)); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile("ldaexb %0, %1" : "=r"(result) : "Q"(*ptr)); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile("ldaexh %0, %1" : "=r"(result) : "Q"(*ptr)); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile("ldaex %0, %1" : "=r"(result) : "Q"(*ptr)); + return (result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile("stlexb %0, %2, %1" : "=&r"(result), "=Q"(*ptr) : "r"((uint32_t)value)); + return (result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile("stlexh %0, %2, %1" : "=&r"(result), "=Q"(*ptr) : "r"((uint32_t)value)); + return (result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile("stlex %0, %2, %1" : "=&r"(result), "=Q"(*ptr) : "r"((uint32_t)value)); + return (result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("sadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("qadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("shadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uqadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uhadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("ssub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("qsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("shsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("usub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uqsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uhsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("sadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("qadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("shadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uqadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uhadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("ssub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("qsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("shsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("usub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uqsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uhsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("sasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("qasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("shasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uqasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uhasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("ssax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("qsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("shsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("usax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uqsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uhsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("usad8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile("usada8 %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); + return (result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile("uxtb16 %0, %1" : "=r"(result) : "r"(op1)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uxtab16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile("sxtb16 %0, %1" : "=r"(result) : "r"(op1)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("sxtab16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("smuad %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("smuadx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile("smlad %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile("smladx %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); + return (result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD(uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u + { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile("smlald %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]): "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); +#else /* Big endian */ + __ASM volatile("smlald %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]): "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); +#endif + + return (llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX(uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u + { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile("smlaldx %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]): "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); +#else /* Big endian */ + __ASM volatile("smlaldx %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]): "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); +#endif + + return (llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("smusd %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("smusdx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile("smlsd %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile("smlsdx %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); + return (result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD(uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u + { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile("smlsld %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]): "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); +#else /* Big endian */ + __ASM volatile("smlsld %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]): "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); +#endif + + return (llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX(uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u + { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile("smlsldx %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]): "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); +#else /* Big endian */ + __ASM volatile("smlsldx %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]): "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); +#endif + + return (llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("sel %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE int32_t __QADD(int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile("qadd %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE int32_t __QSUB(int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile("qsub %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA(int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile("smmla %0, %1, %2, %3" : "=r"(result): "r"(op1), "r"(op2), "r"(op3)); + return (result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_iccarm.h b/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_iccarm.h new file mode 100644 index 0000000000..908caa52cf --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_iccarm.h @@ -0,0 +1,941 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.0.7 + * @date 19. June 2018 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2018 IAR Systems +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ + /* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t *)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t *)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t *)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t *)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 +{ + uint32_t v; +}; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + +#if defined(__CLZ) + #undef __CLZ +#endif +#if defined(__REVSH) + #undef __REVSH +#endif +#if defined(__RBIT) + #undef __RBIT +#endif +#if defined(__SSAT) + #undef __SSAT +#endif +#if defined(__USAT) + #undef __USAT +#endif + +#include "iccarm_builtin.h" + +#define __disable_fault_irq __iar_builtin_disable_fiq +#define __disable_irq __iar_builtin_disable_interrupt +#define __enable_fault_irq __iar_builtin_enable_fiq +#define __enable_irq __iar_builtin_enable_interrupt +#define __arm_rsr __iar_builtin_rsr +#define __arm_wsr __iar_builtin_wsr + + +#define __get_APSR() (__arm_rsr("APSR")) +#define __get_BASEPRI() (__arm_rsr("BASEPRI")) +#define __get_CONTROL() (__arm_rsr("CONTROL")) +#define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR() (__arm_rsr("FPSCR")) +#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) +#else +#define __get_FPSCR() ( 0 ) +#define __set_FPSCR(VALUE) ((void)VALUE) +#endif + +#define __get_IPSR() (__arm_rsr("IPSR")) +#define __get_MSP() (__arm_rsr("MSP")) +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) +// without main extensions, the non-secure MSPLIM is RAZ/WI +#define __get_MSPLIM() (0U) +#else +#define __get_MSPLIM() (__arm_rsr("MSPLIM")) +#endif +#define __get_PRIMASK() (__arm_rsr("PRIMASK")) +#define __get_PSP() (__arm_rsr("PSP")) + +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) +// without main extensions, the non-secure PSPLIM is RAZ/WI +#define __get_PSPLIM() (0U) +#else +#define __get_PSPLIM() (__arm_rsr("PSPLIM")) +#endif + +#define __get_xPSR() (__arm_rsr("xPSR")) + +#define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) +#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) +#define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) +#define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) +#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) +// without main extensions, the non-secure MSPLIM is RAZ/WI +#define __set_MSPLIM(VALUE) ((void)(VALUE)) +#else +#define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) +#endif +#define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) +#define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) +// without main extensions, the non-secure PSPLIM is RAZ/WI +#define __set_PSPLIM(VALUE) ((void)(VALUE)) +#else +#define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) +#endif + +#define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) +#define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) +#define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) +#define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) +#define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) +#define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) +#define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) +#define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) +#define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) +#define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) +#define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) +#define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) +#define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) +#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) +// without main extensions, the non-secure PSPLIM is RAZ/WI +#define __TZ_get_PSPLIM_NS() (0U) +#define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) +#else +#define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) +#define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) +#endif + +#define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) +#define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + +#define __NOP __iar_builtin_no_operation + +#define __CLZ __iar_builtin_CLZ +#define __CLREX __iar_builtin_CLREX + +#define __DMB __iar_builtin_DMB +#define __DSB __iar_builtin_DSB +#define __ISB __iar_builtin_ISB + +#define __LDREXB __iar_builtin_LDREXB +#define __LDREXH __iar_builtin_LDREXH +#define __LDREXW __iar_builtin_LDREX + +#define __RBIT __iar_builtin_RBIT +#define __REV __iar_builtin_REV +#define __REV16 __iar_builtin_REV16 + +__IAR_FT int16_t __REVSH(int16_t val) +{ + return (int16_t) __iar_builtin_REVSH(val); +} + +#define __ROR __iar_builtin_ROR +#define __RRX __iar_builtin_RRX + +#define __SEV __iar_builtin_SEV + +#if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT +#endif + +#define __STREXB __iar_builtin_STREXB +#define __STREXH __iar_builtin_STREXH +#define __STREXW __iar_builtin_STREX + +#if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT +#endif + +#define __WFE __iar_builtin_WFE +#define __WFI __iar_builtin_WFI + +#if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB +#endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active +#endif + + +#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) +#define __get_FPSCR __cmsis_iar_get_FPSR_not_active +#define __set_FPSCR __cmsis_iar_set_FPSR_not_active +#endif + +#ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! +#endif + +#include + +#if __IAR_M0_FAMILY +/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ +#undef __CLZ +#undef __SSAT +#undef __USAT +#undef __RBIT +#undef __get_APSR + +__STATIC_INLINE uint8_t __CLZ(uint32_t data) +{ + if (data == 0U) + { + return 32U; + } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; +} + +__STATIC_INLINE uint32_t __RBIT(uint32_t v) +{ + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); +} + +__STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t res; + __asm("MRS %0,APSR" : "=r"(res)); + return res; +} + +#endif + +#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) +#undef __get_FPSCR +#undef __set_FPSCR +#define __get_FPSCR() (0) +#define __set_FPSCR(VALUE) ((void)VALUE) +#endif + +#pragma diag_suppress=Pe940 +#pragma diag_suppress=Pe177 + +#define __enable_irq __enable_interrupt +#define __disable_irq __disable_interrupt +#define __NOP __no_operation + +#define __get_xPSR __get_PSR + +#if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + +__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) +{ + return __LDREX((unsigned long *)ptr); +} + +__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) +{ + return __STREX(value, (unsigned long *)ptr); +} +#endif + + +/* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ +#if (__CORTEX_M >= 0x03) + +__IAR_FT uint32_t __RRX(uint32_t value) +{ + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r"(value) : "cc"); + return (result); +} + +__IAR_FT void __set_BASEPRI_MAX(uint32_t value) +{ + __asm volatile("MSR BASEPRI_MAX,%0"::"r"(value)); +} + + +#define __enable_fault_irq __enable_fiq +#define __disable_fault_irq __disable_fiq + + +#endif /* (__CORTEX_M >= 0x03) */ + +__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << ((sizeof(op1) * 8) - op2)); +} + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +__IAR_FT uint32_t __get_MSPLIM(void) +{ + uint32_t res; +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; +#else + __asm volatile("MRS %0,MSPLIM" : "=r"(res)); +#endif + return res; +} + +__IAR_FT void __set_MSPLIM(uint32_t value) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; +#else + __asm volatile("MSR MSPLIM,%0" :: "r"(value)); +#endif +} + +__IAR_FT uint32_t __get_PSPLIM(void) +{ + uint32_t res; +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; +#else + __asm volatile("MRS %0,PSPLIM" : "=r"(res)); +#endif + return res; +} + +__IAR_FT void __set_PSPLIM(uint32_t value) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; +#else + __asm volatile("MSR PSPLIM,%0" :: "r"(value)); +#endif +} + +__IAR_FT uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r"(res)); + return res; +} + +__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) +{ + __asm volatile("MSR CONTROL_NS,%0" :: "r"(value)); +} + +__IAR_FT uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r"(res)); + return res; +} + +__IAR_FT void __TZ_set_PSP_NS(uint32_t value) +{ + __asm volatile("MSR PSP_NS,%0" :: "r"(value)); +} + +__IAR_FT uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r"(res)); + return res; +} + +__IAR_FT void __TZ_set_MSP_NS(uint32_t value) +{ + __asm volatile("MSR MSP_NS,%0" :: "r"(value)); +} + +__IAR_FT uint32_t __TZ_get_SP_NS(void) +{ + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r"(res)); + return res; +} +__IAR_FT void __TZ_set_SP_NS(uint32_t value) +{ + __asm volatile("MSR SP_NS,%0" :: "r"(value)); +} + +__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r"(res)); + return res; +} + +__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) +{ + __asm volatile("MSR PRIMASK_NS,%0" :: "r"(value)); +} + +__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r"(res)); + return res; +} + +__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) +{ + __asm volatile("MSR BASEPRI_NS,%0" :: "r"(value)); +} + +__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r"(res)); + return res; +} + +__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) +{ + __asm volatile("MSR FAULTMASK_NS,%0" :: "r"(value)); +} + +__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) +{ + uint32_t res; +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; +#else + __asm volatile("MRS %0,PSPLIM_NS" : "=r"(res)); +#endif + return res; +} + +__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; +#else + __asm volatile("MSR PSPLIM_NS,%0" :: "r"(value)); +#endif +} + +__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) +{ + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r"(res)); + return res; +} + +__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) +{ + __asm volatile("MSR MSPLIM_NS,%0" :: "r"(value)); +} + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY +__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + +__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) +{ + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r"(res) : "r"(addr) : "memory"); + return ((uint8_t)res); +} + +__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) +{ + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r"(res) : "r"(addr) : "memory"); + return ((uint16_t)res); +} + +__IAR_FT uint32_t __LDRT(volatile uint32_t *addr) +{ + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r"(res) : "r"(addr) : "memory"); + return res; +} + +__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) +{ + __ASM("STRBT %1, [%0]" : : "r"(addr), "r"((uint32_t)value) : "memory"); +} + +__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) +{ + __ASM("STRHT %1, [%0]" : : "r"(addr), "r"((uint32_t)value) : "memory"); +} + +__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) +{ + __ASM("STRT %1, [%0]" : : "r"(addr), "r"(value) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + +__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t res; + __ASM volatile("LDAB %0, [%1]" : "=r"(res) : "r"(ptr) : "memory"); + return ((uint8_t)res); +} + +__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t res; + __ASM volatile("LDAH %0, [%1]" : "=r"(res) : "r"(ptr) : "memory"); + return ((uint16_t)res); +} + +__IAR_FT uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t res; + __ASM volatile("LDA %0, [%1]" : "=r"(res) : "r"(ptr) : "memory"); + return res; +} + +__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile("STLB %1, [%0]" :: "r"(ptr), "r"(value) : "memory"); +} + +__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile("STLH %1, [%0]" :: "r"(ptr), "r"(value) : "memory"); +} + +__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile("STL %1, [%0]" :: "r"(ptr), "r"(value) : "memory"); +} + +__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t res; + __ASM volatile("LDAEXB %0, [%1]" : "=r"(res) : "r"(ptr) : "memory"); + return ((uint8_t)res); +} + +__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t res; + __ASM volatile("LDAEXH %0, [%1]" : "=r"(res) : "r"(ptr) : "memory"); + return ((uint16_t)res); +} + +__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t res; + __ASM volatile("LDAEX %0, [%1]" : "=r"(res) : "r"(ptr) : "memory"); + return res; +} + +__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t res; + __ASM volatile("STLEXB %0, %2, [%1]" : "=r"(res) : "r"(ptr), "r"(value) : "memory"); + return res; +} + +__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t res; + __ASM volatile("STLEXH %0, %2, [%1]" : "=r"(res) : "r"(ptr), "r"(value) : "memory"); + return res; +} + +__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t res; + __ASM volatile("STLEX %0, %2, [%1]" : "=r"(res) : "r"(ptr), "r"(value) : "memory"); + return res; +} + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_version.h b/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_version.h index 660f612aa3..f2fc98e765 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_version.h +++ b/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_version.h @@ -23,9 +23,9 @@ */ #if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ + #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ + #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CMSIS_VERSION_H diff --git a/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/core_cm3.h b/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/core_cm3.h index 8157ca782d..33a0b01e2d 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/core_cm3.h +++ b/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/core_cm3.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file core_cm3.h * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V5.1.0 - * @date 13. March 2019 + * @version V5.0.8 + * @date 04. June 2018 ******************************************************************************/ /* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -23,9 +23,9 @@ */ #if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ + #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ + #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM3_H_GENERIC @@ -34,7 +34,7 @@ #include #ifdef __cplusplus - extern "C" { +extern "C" { #endif /** @@ -76,39 +76,39 @@ #define __FPU_USED 0U #if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif +#if defined __TARGET_FPU_VFP +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_FP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif +#if defined __ARM_PCS_VFP +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif #elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif #elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif +#if defined __ARMVFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif #elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif +#if defined __TI_VFP_SUPPORT__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif #elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif +#if defined __FPU_VFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif #elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif +#if ( __CSMC__ & 0x400U) +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif #endif @@ -127,30 +127,30 @@ #define __CORE_CM3_H_DEPENDANT #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES - #ifndef __CM3_REV - #define __CM3_REV 0x0200U - #warning "__CM3_REV not defined in device header file; using default!" - #endif +#ifndef __CM3_REV +#define __CM3_REV 0x0200U +#warning "__CM3_REV not defined in device header file; using default!" +#endif - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0U +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 3U +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0U +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif #endif /* IO definitions (access restrictions to peripheral registers) */ @@ -162,9 +162,9 @@ \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ +#define __I volatile /*!< Defines 'read only' permissions */ #else - #define __I volatile const /*!< Defines 'read only' permissions */ +#define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ @@ -205,16 +205,16 @@ */ typedef union { - struct - { - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ + struct + { + uint32_t _reserved0: 27; /*!< bit: 0..26 Reserved */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ @@ -239,12 +239,12 @@ typedef union */ typedef union { - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ + struct + { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ @@ -257,21 +257,21 @@ typedef union */ typedef union { - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:1; /*!< bit: 9 Reserved */ - uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ - uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit */ - uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ + struct + { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1: 6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1: 8; /*!< bit: 16..23 Reserved */ + uint32_t T: 1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2: 2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ @@ -308,13 +308,13 @@ typedef union */ typedef union { - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ + struct + { + uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ @@ -339,19 +339,19 @@ typedef union */ typedef struct { - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RESERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ @@ -373,27 +373,27 @@ typedef struct */ typedef struct { - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ } SCB_Type; /* SCB CPUID Register Definitions */ @@ -654,12 +654,12 @@ typedef struct */ typedef struct { - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ #if defined (__CM3_REV) && (__CM3_REV >= 0x200U) - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ #else - uint32_t RESERVED1[1U]; + uint32_t RESERVED1[1U]; #endif } SCnSCB_Type; @@ -668,12 +668,6 @@ typedef struct #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /* Auxiliary Control Register Definitions */ -#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) -#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ -#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ - -#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ -#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ @@ -683,7 +677,6 @@ typedef struct #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ -#endif /*@} end of group CMSIS_SCnotSCB */ @@ -700,10 +693,10 @@ typedef struct */ typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ @@ -752,35 +745,38 @@ typedef struct */ typedef struct { - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[32U]; - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Trace Privilege Register Definitions */ @@ -815,6 +811,18 @@ typedef struct #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ @@ -840,29 +848,29 @@ typedef struct */ typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ } DWT_Type; /* DWT Control Register Definitions */ @@ -987,30 +995,30 @@ typedef struct */ typedef struct { - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ @@ -1047,13 +1055,13 @@ typedef struct /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ @@ -1076,13 +1084,13 @@ typedef struct /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ @@ -1149,17 +1157,17 @@ typedef struct */ typedef struct { - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ } MPU_Type; #define MPU_TYPE_RALIASES 4U @@ -1245,10 +1253,10 @@ typedef struct */ typedef struct { - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ @@ -1391,8 +1399,8 @@ typedef struct #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif /*@} */ @@ -1422,33 +1430,33 @@ typedef struct */ #ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE +#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" +#endif +#include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset +#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping +#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping +#define NVIC_EnableIRQ __NVIC_EnableIRQ +#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ +#define NVIC_DisableIRQ __NVIC_DisableIRQ +#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ +#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ +#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +#define NVIC_GetActive __NVIC_GetActive +#define NVIC_SetPriority __NVIC_SetPriority +#define NVIC_GetPriority __NVIC_GetPriority +#define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" +#endif +#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector +#define NVIC_SetVector __NVIC_SetVector +#define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 @@ -1471,15 +1479,15 @@ typedef struct */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB->AIRCR = reg_value; + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; } @@ -1490,7 +1498,7 @@ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } @@ -1502,12 +1510,10 @@ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } } @@ -1521,14 +1527,14 @@ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } + if ((int32_t)(IRQn) >= 0) + { + return ((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return (0U); + } } @@ -1540,12 +1546,12 @@ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } } @@ -1559,14 +1565,14 @@ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } + if ((int32_t)(IRQn) >= 0) + { + return ((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return (0U); + } } @@ -1578,10 +1584,10 @@ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } } @@ -1593,10 +1599,10 @@ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } } @@ -1610,14 +1616,14 @@ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } + if ((int32_t)(IRQn) >= 0) + { + return ((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return (0U); + } } @@ -1632,14 +1638,14 @@ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } } @@ -1655,14 +1661,14 @@ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } + if ((int32_t)(IRQn) >= 0) + { + return (((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return (((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS))); + } } @@ -1677,19 +1683,19 @@ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits)) - 1UL))) + ); } @@ -1704,17 +1710,17 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority) { - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority) & (uint32_t)((1UL << (SubPriorityBits)) - 1UL); } @@ -1729,9 +1735,8 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { - uint32_t vectors = (uint32_t )SCB->VTOR; - (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; - /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; } @@ -1745,8 +1750,8 @@ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { - uint32_t vectors = (uint32_t )SCB->VTOR; - return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } @@ -1756,17 +1761,17 @@ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { - __DSB(); /* Ensure all outstanding memory accesses included + __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ - for(;;) /* wait until reset */ - { - __NOP(); - } + for (;;) /* wait until reset */ + { + __NOP(); + } } /*@} end of CMSIS_Core_NVICFunctions */ @@ -1779,7 +1784,6 @@ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) #endif - /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface @@ -1829,18 +1833,18 @@ __STATIC_INLINE uint32_t SCB_GetFPUType(void) */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ } #endif @@ -1869,18 +1873,18 @@ extern volatile int32_t ITM_RxBuffer; /*!< External \param [in] ch Character to transmit. \returns Character to transmit. */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +__STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch) { - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL) != 0UL)) /* ITM Port #0 enabled */ { - __NOP(); + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); + return (ch); } @@ -1890,17 +1894,17 @@ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) \return Received character. \return -1 No character pending. */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) +__STATIC_INLINE int32_t ITM_ReceiveChar(void) { - int32_t ch = -1; /* no character available */ + int32_t ch = -1; /* no character available */ - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } - return (ch); + return (ch); } @@ -1910,17 +1914,17 @@ __STATIC_INLINE int32_t ITM_ReceiveChar (void) \return 0 No character available. \return 1 Character available. */ -__STATIC_INLINE int32_t ITM_CheckChar (void) +__STATIC_INLINE int32_t ITM_CheckChar(void) { - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } } /*@} end of CMSIS_core_DebugFunctions */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Include/apm32f10x.h b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Include/apm32f10x.h index f5edd39559..24e12575f6 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Include/apm32f10x.h +++ b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Include/apm32f10x.h @@ -1,21 +1,35 @@ /*! - * @file apm32f10x.h + * @file apm32f10x.h * - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. * - * @details This file contains all the peripheral register's definitions, bits definitions and memory mapping + * @details This file contains all the peripheral register's definitions, bits definitions and memory mapping * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ -#ifndef __APM32F10x_H -#define __APM32F10x_H +#ifndef __APM32F10X_H +#define __APM32F10X_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /*! @@ -31,11 +45,11 @@ * @brief Define Value of the External oscillator in Hz */ #ifndef HSE_VALUE - #define HSE_VALUE ((uint32_t)8000000) +#define HSE_VALUE ((uint32_t)8000000) #endif /** Time out for HSE start up */ -#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) +#define HSE_STARTUP_TIMEOUT ((uint16_t)0x05000) /** Value of the Internal oscillator in Hz */ #define HSI_VALUE ((uint32_t)8000000) @@ -45,7 +59,7 @@ */ #define __APM32F10X_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ #define __APM32F10X_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ -#define __APM32F10X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __APM32F10X_STDPERIPH_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ #define __APM32F10X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __APM32F10X_STDPERIPH_VERSION ( (__APM32F10X_STDPERIPH_VERSION_MAIN << 24)\ |(__APM32F10X_STDPERIPH_VERSION_SUB1 << 16)\ @@ -54,7 +68,7 @@ /** APM32 devices does not provide an MPU */ - #define __MPU_PRESENT 0 +#define __MPU_PRESENT 0 /** APM32 uses 4 Bits for the Priority Levels */ #define __NVIC_PRIO_BITS 4 /** Set to 1 if different SysTick Config is used */ @@ -66,143 +80,143 @@ */ typedef enum IRQn { -/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ -/****** APM32 specific Interrupt Numbers *********************************************************/ - WWDT_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EINT Line detection Interrupt */ - TAMPER_IRQn = 2, /*!< Tamper Interrupt */ - RTC_IRQn = 3, /*!< RTC global Interrupt */ - FMC_IRQn = 4, /*!< FMC global Interrupt */ - RCM_IRQn = 5, /*!< RCM global Interrupt */ - EINT0_IRQn = 6, /*!< EINT Line0 Interrupt */ - EINT1_IRQn = 7, /*!< EINT Line1 Interrupt */ - EINT2_IRQn = 8, /*!< EINT Line2 Interrupt */ - EINT3_IRQn = 9, /*!< EINT Line3 Interrupt */ - EINT4_IRQn = 10, /*!< EINT Line4 Interrupt */ - DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ - DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ - DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ - DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ - DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ - DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ - DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + /****** APM32 specific Interrupt Numbers *********************************************************/ + WWDT_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EINT Line detection Interrupt */ + TAMPER_IRQn = 2, /*!< Tamper Interrupt */ + RTC_IRQn = 3, /*!< RTC global Interrupt */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCM_IRQn = 5, /*!< RCM global Interrupt */ + EINT0_IRQn = 6, /*!< EINT Line0 Interrupt */ + EINT1_IRQn = 7, /*!< EINT Line1 Interrupt */ + EINT2_IRQn = 8, /*!< EINT Line2 Interrupt */ + EINT3_IRQn = 9, /*!< EINT Line3 Interrupt */ + EINT4_IRQn = 10, /*!< EINT Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ #if defined (APM32F10X_LD) - /** APM32F10X Low-density devices specific Interrupt Numbers */ - ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ - USBD1_HP_CAN1_TX_IRQn = 19, /*!< USB Device 1 High Priority or CAN1 TX Interrupts */ - USBD1_LP_CAN1_RX0_IRQn = 20, /*!< USB Device 1 Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EINT9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TMR1_BRK_IRQn = 24, /*!< TMR1 Break Interrupt */ - TMR1_UP_IRQn = 25, /*!< TMR1 Update Interrupt */ - TMR1_TRG_COM_IRQn = 26, /*!< TMR1 Trigger and Commutation Interrupt */ - TMR1_CC_IRQn = 27, /*!< TMR1 Capture Compare Interrupt */ - TMR2_IRQn = 28, /*!< TMR2 global Interrupt */ - TMR3_IRQn = 29, /*!< TMR3 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - EINT15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EINT Line Interrupt */ - USBDWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EINT Line Interrupt */ - FPU_IRQn = 43, /*!< FPU Global Interrupt */ - QSPI_IRQn = 44, /*!< QSPI Global Interrupt */ - USBD2_HP_IRQn = 45, /*!< USB Device 2 High Priority */ - USBD2_LP_IRQn = 46 /*!< USB Device 2 Low Priority */ + /** APM32F10X Low-density devices specific Interrupt Numbers */ + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USBD1_HP_CAN1_TX_IRQn = 19, /*!< USB Device 1 High Priority or CAN1 TX Interrupts */ + USBD1_LP_CAN1_RX0_IRQn = 20, /*!< USB Device 1 Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EINT9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TMR1_BRK_IRQn = 24, /*!< TMR1 Break Interrupt */ + TMR1_UP_IRQn = 25, /*!< TMR1 Update Interrupt */ + TMR1_TRG_COM_IRQn = 26, /*!< TMR1 Trigger and Commutation Interrupt */ + TMR1_CC_IRQn = 27, /*!< TMR1 Capture Compare Interrupt */ + TMR2_IRQn = 28, /*!< TMR2 global Interrupt */ + TMR3_IRQn = 29, /*!< TMR3 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + EINT15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EINT Line Interrupt */ + USBDWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EINT Line Interrupt */ + FPU_IRQn = 43, /*!< FPU Global Interrupt */ + QSPI_IRQn = 44, /*!< QSPI Global Interrupt */ + USBD2_HP_IRQn = 45, /*!< USB Device 2 High Priority */ + USBD2_LP_IRQn = 46 /*!< USB Device 2 Low Priority */ #elif defined (APM32F10X_MD) - /** APM32F10X Medium-density devices specific Interrupt Numbers */ - ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ - USBD1_HP_CAN1_TX_IRQn = 19, /*!< USB Device 1 High Priority or CAN1 TX Interrupts */ - USBD1_LP_CAN1_RX0_IRQn = 20, /*!< USB Device 1 Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EINT9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TMR1_BRK_IRQn = 24, /*!< TMR1 Break Interrupt */ - TMR1_UP_IRQn = 25, /*!< TMR1 Update Interrupt */ - TMR1_TRG_COM_IRQn = 26, /*!< TMR1 Trigger and Commutation Interrupt */ - TMR1_CC_IRQn = 27, /*!< TMR1 Capture Compare Interrupt */ - TMR2_IRQn = 28, /*!< TMR2 global Interrupt */ - TMR3_IRQn = 29, /*!< TMR3 global Interrupt */ - TMR4_IRQn = 30, /*!< TMR4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EINT15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EINT Line Interrupt */ - USBDWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EINT Line Interrupt */ - FPU_IRQn = 43, /*!< FPU Global Interrupt */ - QSPI_IRQn = 44, /*!< QSPI Global Interrupt */ - USBD2_HP_IRQn = 45, /*!< USB Device 2 High Priority */ - USBD2_LP_IRQn = 46 /*!< USB Device 2 Low Priority */ + /** APM32F10X Medium-density devices specific Interrupt Numbers */ + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USBD1_HP_CAN1_TX_IRQn = 19, /*!< USB Device 1 High Priority or CAN1 TX Interrupts */ + USBD1_LP_CAN1_RX0_IRQn = 20, /*!< USB Device 1 Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EINT9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TMR1_BRK_IRQn = 24, /*!< TMR1 Break Interrupt */ + TMR1_UP_IRQn = 25, /*!< TMR1 Update Interrupt */ + TMR1_TRG_COM_IRQn = 26, /*!< TMR1 Trigger and Commutation Interrupt */ + TMR1_CC_IRQn = 27, /*!< TMR1 Capture Compare Interrupt */ + TMR2_IRQn = 28, /*!< TMR2 global Interrupt */ + TMR3_IRQn = 29, /*!< TMR3 global Interrupt */ + TMR4_IRQn = 30, /*!< TMR4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EINT15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EINT Line Interrupt */ + USBDWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EINT Line Interrupt */ + FPU_IRQn = 43, /*!< FPU Global Interrupt */ + QSPI_IRQn = 44, /*!< QSPI Global Interrupt */ + USBD2_HP_IRQn = 45, /*!< USB Device 2 High Priority */ + USBD2_LP_IRQn = 46 /*!< USB Device 2 Low Priority */ #elif defined (APM32F10X_HD) - /** APM32F10X High-density devices specific Interrupt Numbers */ - ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ - USBD1_HP_CAN1_TX_IRQn = 19, /*!< USB Device 1 High Priority or CAN1 TX Interrupts */ - USBD1_LP_CAN1_RX0_IRQn = 20, /*!< USB Device 1 Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EINT9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TMR1_BRK_IRQn = 24, /*!< TMR1 Break Interrupt */ - TMR1_UP_IRQn = 25, /*!< TMR1 Update Interrupt */ - TMR1_TRG_COM_IRQn = 26, /*!< TMR1 Trigger and Commutation Interrupt */ - TMR1_CC_IRQn = 27, /*!< TMR1 Capture Compare Interrupt */ - TMR2_IRQn = 28, /*!< TMR2 global Interrupt */ - TMR3_IRQn = 29, /*!< TMR3 global Interrupt */ - TMR4_IRQn = 30, /*!< TMR4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EINT15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EINT Line Interrupt */ - USBDWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EINT Line Interrupt */ - TMR8_BRK_IRQn = 43, /*!< TMR8 Break Interrupt */ - TMR8_UP_IRQn = 44, /*!< TMR8 Update Interrupt */ - TMR8_TRG_COM_IRQn = 45, /*!< TMR8 Trigger and Commutation Interrupt */ - TMR8_CC_IRQn = 46, /*!< TMR8 Capture Compare Interrupt */ - ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ - EMMC_IRQn = 48, /*!< EMMC global Interrupt */ - SDIO_IRQn = 49, /*!< SDIO global Interrupt */ - TMR5_IRQn = 50, /*!< TMR5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TMR6_IRQn = 54, /*!< TMR6 global Interrupt */ - TMR7_IRQn = 55, /*!< TMR7 global Interrupt */ - DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ - DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ - DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ - DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ - USBD2_HP_CAN2_TX_IRQn = 61, /*!< USB Device 2 High Priority or CAN2 TX Interrupts */ - USBD2_LP_CAN2_RX0_IRQn = 62, /*!< USB Device 2 Low Priority or CAN2 RX0 Interrupts */ - CAN2_RX1_IRQn = 63, /*!< CAN2 RX1 Interrupts */ - CAN2_SCE_IRQn = 64, /*!< CAN2 SCE Interrupts */ + /** APM32F10X High-density devices specific Interrupt Numbers */ + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USBD1_HP_CAN1_TX_IRQn = 19, /*!< USB Device 1 High Priority or CAN1 TX Interrupts */ + USBD1_LP_CAN1_RX0_IRQn = 20, /*!< USB Device 1 Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EINT9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TMR1_BRK_IRQn = 24, /*!< TMR1 Break Interrupt */ + TMR1_UP_IRQn = 25, /*!< TMR1 Update Interrupt */ + TMR1_TRG_COM_IRQn = 26, /*!< TMR1 Trigger and Commutation Interrupt */ + TMR1_CC_IRQn = 27, /*!< TMR1 Capture Compare Interrupt */ + TMR2_IRQn = 28, /*!< TMR2 global Interrupt */ + TMR3_IRQn = 29, /*!< TMR3 global Interrupt */ + TMR4_IRQn = 30, /*!< TMR4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EINT15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EINT Line Interrupt */ + USBDWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EINT Line Interrupt */ + TMR8_BRK_IRQn = 43, /*!< TMR8 Break Interrupt */ + TMR8_UP_IRQn = 44, /*!< TMR8 Update Interrupt */ + TMR8_TRG_COM_IRQn = 45, /*!< TMR8 Trigger and Commutation Interrupt */ + TMR8_CC_IRQn = 46, /*!< TMR8 Capture Compare Interrupt */ + ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ + EMMC_IRQn = 48, /*!< EMMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TMR5_IRQn = 50, /*!< TMR5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TMR6_IRQn = 54, /*!< TMR6 global Interrupt */ + TMR7_IRQn = 55, /*!< TMR7 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ + USBD2_HP_CAN2_TX_IRQn = 61, /*!< USB Device 2 High Priority or CAN2 TX Interrupts */ + USBD2_LP_CAN2_RX0_IRQn = 62, /*!< USB Device 2 Low Priority or CAN2 RX0 Interrupts */ + CAN2_RX1_IRQn = 63, /*!< CAN2 RX1 Interrupts */ + CAN2_SCE_IRQn = 64, /*!< CAN2 SCE Interrupts */ #endif } IRQn_Type; @@ -248,13 +262,13 @@ typedef __I uint16_t vuc16; typedef __I uint8_t vuc8; #ifndef __IM - #define __IM __I +#define __IM __I #endif #ifndef __OM - #define __OM __O +#define __OM __O #endif #ifndef __IOM - #define __IOM __IO +#define __IOM __IO #endif enum {BIT_RESET, BIT_SET}; @@ -305,8 +319,8 @@ typedef struct struct { - __IOM uint32_t SCLKSW : 2; - __IM uint32_t SCLKSWSTS : 2; + __IOM uint32_t SCLKSEL : 2; + __IM uint32_t SCLKSELSTS : 2; __IOM uint32_t AHBPSC : 4; __IOM uint32_t APB1PSC : 3; __IOM uint32_t APB2PSC : 3; @@ -502,7 +516,7 @@ typedef struct /** Backup domain control register */ union - { + { __IOM uint32_t BDCTRL; struct @@ -2041,7 +2055,7 @@ typedef struct __OM uint32_t COMG : 1; __OM uint32_t TEG : 1; __OM uint32_t BEG : 1; - __OM uint32_t RESERVED : 24; + __IM uint32_t RESERVED : 24; } CEG_B; }; @@ -2090,12 +2104,12 @@ typedef struct __IOM uint32_t CC3SEL : 2; __IOM uint32_t OC3FEN : 1; __IOM uint32_t OC3PEN : 1; - __IOM uint32_t OC3MODE : 3; + __IOM uint32_t OC3MOD : 3; __IOM uint32_t OC3CEN : 1; __IOM uint32_t CC4SEL : 2; __IOM uint32_t OC4FEN : 1; __IOM uint32_t OC4PEN : 1; - __IOM uint32_t OC4MODE : 3; + __IOM uint32_t OC4MOD : 3; __IOM uint32_t OC4CEN : 1; __IM uint32_t RESERVED : 16; } CCM2_COMPARE_B; @@ -2455,10 +2469,7 @@ typedef struct struct { __IOM uint32_t DLCODE : 4; - __IM uint32_t RESERVED1 : 4; - __IOM uint32_t TXTS : 1; - __IM uint32_t RESERVED2 : 7; - __IOM uint32_t MTS : 16; + __IOM uint32_t RESERVED : 28; } TXDLEN_B; }; @@ -2519,9 +2530,9 @@ typedef struct struct { __IM uint32_t DLCODE : 4; - __IM uint32_t RESERVED : 4; + __IM uint32_t RESERVED1 : 4; __IM uint32_t FMIDX : 8; - __IM uint32_t MTS : 16; + __IM uint32_t RESERVED2 : 16; } RXDLEN_B; }; @@ -2532,10 +2543,10 @@ typedef struct struct { + __IM uint32_t DATABYTE0 : 8; __IM uint32_t DATABYTE1 : 8; __IM uint32_t DATABYTE2 : 8; __IM uint32_t DATABYTE3 : 8; - __IM uint32_t DATABYTE4 : 8; } RXMDL_B; }; @@ -2546,10 +2557,10 @@ typedef struct struct { + __IM uint32_t DATABYTE4 : 8; __IM uint32_t DATABYTE5 : 8; __IM uint32_t DATABYTE6 : 8; __IM uint32_t DATABYTE7 : 8; - __IM uint32_t DATABYTE8 : 8; } RXMDH_B; }; } CAN_RxMailBox_T; @@ -2601,7 +2612,7 @@ typedef struct } FBANK1_B; }; - /** @brief CAN Filter bank register 1 */ + /** @brief CAN Filter bank register 2 */ union { __IOM uint32_t FBANK2; @@ -2663,8 +2674,7 @@ typedef struct __IOM uint32_t ARTXMD : 1; __IOM uint32_t AWUPCFG : 1; __IOM uint32_t ALBOFFM : 1; - __IOM uint32_t TTCM : 1; - __IM uint32_t RESERVED1 : 7; + __IM uint32_t RESERVED1 : 8; __IOM uint32_t SWRST : 1; __IOM uint32_t DBGFRZE : 1; __IM uint32_t RESERVED2 : 15; @@ -2739,7 +2749,7 @@ typedef struct __IOM uint32_t FFULLFLG0 : 1; __IOM uint32_t FOVRFLG0 : 1; __IOM uint32_t RFOM0 : 1; - __IM uint32_t RESERVED2 : 26; + __IM uint32_t RESERVED1 : 26; } RXF0_B; }; @@ -2838,7 +2848,9 @@ typedef struct struct { __IOM uint32_t FINITEN : 1; - __IM uint32_t RESERVED : 31; + __IM uint32_t RESERVED : 7; + __IOM uint32_t CAN2BN : 6; + __IM uint32_t RESERVED1 : 18; } FCTRL_B; }; @@ -2863,7 +2875,21 @@ typedef struct __IOM uint32_t FMCFG11 : 1; __IOM uint32_t FMCFG12 : 1; __IOM uint32_t FMCFG13 : 1; - __IM uint32_t RESERVED : 18; + __IOM uint32_t FMCFG14 : 1; + __IOM uint32_t FMCFG15 : 1; + __IOM uint32_t FMCFG16 : 1; + __IOM uint32_t FMCFG17 : 1; + __IOM uint32_t FMCFG18 : 1; + __IOM uint32_t FMCFG19 : 1; + __IOM uint32_t FMCFG20 : 1; + __IOM uint32_t FMCFG21 : 1; + __IOM uint32_t FMCFG22 : 1; + __IOM uint32_t FMCFG23 : 1; + __IOM uint32_t FMCFG24 : 1; + __IOM uint32_t FMCFG25 : 1; + __IOM uint32_t FMCFG26 : 1; + __IOM uint32_t FMCFG27 : 1; + __IM uint32_t RESERVED : 4; } FMCFG_B; }; @@ -2890,8 +2916,22 @@ typedef struct __IOM uint32_t FSCFG11 : 1; __IOM uint32_t FSCFG12 : 1; __IOM uint32_t FSCFG13 : 1; - __IM uint32_t RESERVED : 18; - }FSCFG_B; + __IOM uint32_t FSCFG14 : 1; + __IOM uint32_t FSCFG15 : 1; + __IOM uint32_t FSCFG16 : 1; + __IOM uint32_t FSCFG17 : 1; + __IOM uint32_t FSCFG18 : 1; + __IOM uint32_t FSCFG19 : 1; + __IOM uint32_t FSCFG20 : 1; + __IOM uint32_t FSCFG21 : 1; + __IOM uint32_t FSCFG22 : 1; + __IOM uint32_t FSCFG23 : 1; + __IOM uint32_t FSCFG24 : 1; + __IOM uint32_t FSCFG25 : 1; + __IOM uint32_t FSCFG26 : 1; + __IOM uint32_t FSCFG27 : 1; + __IM uint32_t RESERVED : 4; + } FSCFG_B; }; __IM uint32_t RESERVED3; @@ -2917,7 +2957,21 @@ typedef struct __IOM uint32_t FFASS11 : 1; __IOM uint32_t FFASS12 : 1; __IOM uint32_t FFASS13 : 1; - __IM uint32_t RESERVED : 18; + __IOM uint32_t FFASS14 : 1; + __IOM uint32_t FFASS15 : 1; + __IOM uint32_t FFASS16 : 1; + __IOM uint32_t FFASS17 : 1; + __IOM uint32_t FFASS18 : 1; + __IOM uint32_t FFASS19 : 1; + __IOM uint32_t FFASS20 : 1; + __IOM uint32_t FFASS21 : 1; + __IOM uint32_t FFASS22 : 1; + __IOM uint32_t FFASS23 : 1; + __IOM uint32_t FFASS24 : 1; + __IOM uint32_t FFASS25 : 1; + __IOM uint32_t FFASS26 : 1; + __IOM uint32_t FFASS27 : 1; + __IM uint32_t RESERVED : 4; } FFASS_B; }; @@ -2944,13 +2998,27 @@ typedef struct __IOM uint32_t FACT11 : 1; __IOM uint32_t FACT12 : 1; __IOM uint32_t FACT13 : 1; - __IM uint32_t RESERVED : 18; + __IOM uint32_t FACT14 : 1; + __IOM uint32_t FACT15 : 1; + __IOM uint32_t FACT16 : 1; + __IOM uint32_t FACT17 : 1; + __IOM uint32_t FACT18 : 1; + __IOM uint32_t FACT19 : 1; + __IOM uint32_t FACT20 : 1; + __IOM uint32_t FACT21 : 1; + __IOM uint32_t FACT22 : 1; + __IOM uint32_t FACT23 : 1; + __IOM uint32_t FACT24 : 1; + __IOM uint32_t FACT25 : 1; + __IOM uint32_t FACT26 : 1; + __IOM uint32_t FACT27 : 1; + __IM uint32_t RESERVED : 4; } FACT_B; }; __IM uint32_t RESERVED5[8]; - CAN_FilterRegister_T sFilterRegister[14]; + CAN_FilterRegister_T sFilterRegister[28]; } CAN_T; @@ -3458,7 +3526,7 @@ typedef struct __IM uint32_t ADC2DATA : 16; } REGDATA_B; }; -}ADC_T; +} ADC_T; /** * @brief External Interrupt(EINT) @@ -3532,25 +3600,25 @@ typedef struct struct { - __IOM uint32_t PTEN0 : 1; - __IOM uint32_t PTEN1 : 1; - __IOM uint32_t PTEN2 : 1; - __IOM uint32_t PTEN3 : 1; - __IOM uint32_t PTEN4 : 1; - __IOM uint32_t PTEN5 : 1; - __IOM uint32_t PTEN6 : 1; - __IOM uint32_t PTEN7 : 1; - __IOM uint32_t PTEN8 : 1; - __IOM uint32_t PTEN9 : 1; - __IOM uint32_t PTEN10 : 1; - __IOM uint32_t PTEN11 : 1; - __IOM uint32_t PTEN12 : 1; - __IOM uint32_t PTEN13 : 1; - __IOM uint32_t PTEN14 : 1; - __IOM uint32_t PTEN15 : 1; - __IOM uint32_t PTEN16 : 1; - __IOM uint32_t PTEN17 : 1; - __IOM uint32_t PTEN18 : 1; + __IOM uint32_t RTEN0 : 1; + __IOM uint32_t RTEN1 : 1; + __IOM uint32_t RTEN2 : 1; + __IOM uint32_t RTEN3 : 1; + __IOM uint32_t RTEN4 : 1; + __IOM uint32_t RTEN5 : 1; + __IOM uint32_t RTEN6 : 1; + __IOM uint32_t RTEN7 : 1; + __IOM uint32_t RTEN8 : 1; + __IOM uint32_t RTEN9 : 1; + __IOM uint32_t RTEN10 : 1; + __IOM uint32_t RTEN11 : 1; + __IOM uint32_t RTEN12 : 1; + __IOM uint32_t RTEN13 : 1; + __IOM uint32_t RTEN14 : 1; + __IOM uint32_t RTEN15 : 1; + __IOM uint32_t RTEN16 : 1; + __IOM uint32_t RTEN17 : 1; + __IOM uint32_t RTEN18 : 1; __IM uint32_t RESERVED : 12; } RTEN_B; }; @@ -3644,7 +3712,7 @@ typedef struct __IM uint32_t RESERVED : 12; } IF_B; }; -}EINT_T; +} EINT_T; /** * @brief Independent watchdog(IWDT) @@ -3700,7 +3768,7 @@ typedef struct __IM uint32_t RESERVED : 30; } STS_B; }; -}IWDT_T; +} IWDT_T; /** * @brief Serial peripheral interface(SPI) @@ -3724,7 +3792,7 @@ typedef struct __IOM uint32_t SSEN : 1; __IOM uint32_t RXOMEN : 1; __IOM uint32_t DFLSEL : 1; - __IOM uint32_t CECNXT : 1; + __IOM uint32_t CRCNXT : 1; __IOM uint32_t CRCEN : 1; __IOM uint32_t BMOEN : 1; __IOM uint32_t BMEN : 1; @@ -3802,7 +3870,7 @@ typedef struct { __IM uint32_t RXCRC : 16; __IM uint32_t RESERVED : 16; - }RXCRC_B; + } RXCRC_B; }; /** Transmit CRC register */ @@ -3814,7 +3882,7 @@ typedef struct { __IM uint32_t TXCRC : 16; __IM uint32_t RESERVED : 16; - }TXCRC_B; + } TXCRC_B; }; /** Transmit I2S CTRL register */ @@ -3834,7 +3902,7 @@ typedef struct __IOM uint32_t I2SEN : 1; __IOM uint32_t MODESEL : 1; __IM uint32_t RESERVED2 : 20; - }I2SCFG_B; + } I2SCFG_B; }; /** Transmit I2S DIV register */ @@ -3848,9 +3916,9 @@ typedef struct __IOM uint32_t ODDPSC : 1; __IOM uint32_t MCIEN : 1; __IM uint32_t RESERVED1 : 22; - }I2SPSC_B; + } I2SPSC_B; }; -}SPI_T; +} SPI_T; /** * @brief Window watchdog (WWDT) @@ -3896,7 +3964,7 @@ typedef struct __IM uint32_t RESERVED : 31; } STS_B; }; -}WWDT_T; +} WWDT_T; /** * @brief Secure digital input/output interface (SDIO) @@ -4056,7 +4124,7 @@ typedef struct __IOM uint32_t DMAEN : 1; __IOM uint32_t DBSIZE : 4; __IOM uint32_t RWSTR : 1; - __IOM uint32_t PWSTOP : 1; + __IOM uint32_t RWSTOP : 1; __IOM uint32_t RDWAIT : 1; __IOM uint32_t SDIOF : 1; __IM uint32_t RESERVED : 20; @@ -4166,7 +4234,7 @@ typedef struct __IOM uint32_t RXDAVB : 1; __IOM uint32_t SDIOINTREC : 1; __IOM uint32_t ATACLPREC : 1; - __IM uint32_t RESERVEDIE : 8; + __IM uint32_t RESERVED : 8; } MASK_B; }; @@ -4196,7 +4264,7 @@ typedef struct __IOM uint32_t FIFODATA : 32; } FIFODATA_B; }; -}SDIO_T; +} SDIO_T; /** * @brief Digital to Analog Converter(DAC) @@ -4232,12 +4300,12 @@ typedef struct /** Software trigger register */ union { - __IOM uint32_t SWTRG; + __OM uint32_t SWTRG; struct { - __IOM uint32_t SWTRG1 : 1; - __IOM uint32_t SWTRG2 : 1; + __OM uint32_t SWTRG1 : 1; + __OM uint32_t SWTRG2 : 1; __IM uint32_t RESERVED : 30; } SWTRG_B; }; @@ -4279,13 +4347,13 @@ typedef struct } DH8R1_B; }; - /** Channel2 12-bit right-aligned register */ - union - { - __IOM uint32_t DH12R2; + /** Channel2 12-bit right-aligned register */ + union + { + __IOM uint32_t DH12R2; - struct - { + struct + { __IOM uint32_t DATA : 12; __IM uint32_t RESERVED : 20; } DH12R2_B; @@ -4301,7 +4369,7 @@ typedef struct __IM uint32_t RESERVED1 : 4; __IOM uint32_t DATA : 12; __IM uint32_t RESERVED2 : 16; - }DH12L2_B; + } DH12L2_B; }; /** Channel2 8-bit right-aligned register */ @@ -4351,8 +4419,8 @@ typedef struct struct { - __IOM uint32_t CH1DH : 8; - __IOM uint32_t CH2DH : 8; + __IOM uint32_t DATACH1 : 8; + __IOM uint32_t DATACH2 : 8; __IM uint32_t RESERVED : 16; } DH8RDUAL_B; }; @@ -4360,11 +4428,11 @@ typedef struct /** Channel1 data output register */ union { - __IOM uint32_t DATAOCH1; + __IM uint32_t DATAOCH1; struct { - __IOM uint32_t DATA : 12; + __IM uint32_t DATA : 12; __IM uint32_t RESERVED : 20; } DATAOCH1_B; }; @@ -4372,15 +4440,15 @@ typedef struct /** Channel2 data output register */ union { - __IOM uint32_t DATAOCH2; + __IM uint32_t DATAOCH2; struct { - __IOM uint32_t DATA : 12; + __IM uint32_t DATA : 12; __IM uint32_t RESERVED : 20; } DATAOCH2_B; }; -}DAC_T; +} DAC_T; /** * @brief EMMC Register @@ -4411,9 +4479,9 @@ typedef struct __IOM uint32_t CRAMPSIZECFG : 3; __IOM uint32_t WRBURSTEN : 1; __IOM uint32_t RESERVED2 : 12; - }CSCTRL_B; + } CSCTRL_B; }; -}SNCTRL_T; +} SNCTRL_T; typedef struct { @@ -4432,9 +4500,9 @@ typedef struct __IOM uint32_t DATALATCFG : 4; __IOM uint32_t ACCMODECFG : 2; __IM uint32_t RESERVED2 : 2; - }WRTTIM_T; + } WRTTIM_T; }; -}SNWCLK_T; +} SNWCLK_T; /** * @brief Flexible Static Memory Controller @@ -4475,7 +4543,7 @@ typedef struct __IOM uint32_t A2RDCFG : 4; __IOM uint32_t ECCPSCFG : 3; __IM uint32_t RESERVED3 : 12; - }CTRL2_B; + } CTRL2_B; }; /** FIFO status and interrupt register 2 */ @@ -4492,8 +4560,8 @@ typedef struct __IOM uint32_t IHLDEN : 1; __IOM uint32_t IFEDEN : 1; __IM uint32_t FEFLG : 1; - __IM uint32_t RESERVED :25; - }STSINT2_B; + __IM uint32_t RESERVED : 25; + } STSINT2_B; }; /** Common memory space timing register 2 */ union @@ -4506,7 +4574,7 @@ typedef struct __IOM uint32_t WAIT2 : 8; __IOM uint32_t HLD2 : 8; __IOM uint32_t HIZ2 : 8; - }CMSTIM2_B; + } CMSTIM2_B; }; /** Attribute memory space timing register 2 */ @@ -4520,7 +4588,7 @@ typedef struct __IOM uint32_t WAIT2 : 8; __IOM uint32_t HLD2 : 8; __IOM uint32_t HIZ2 : 8; - }AMSTIM2_B; + } AMSTIM2_B; }; __IOM uint32_t RESERVED; @@ -4535,7 +4603,7 @@ typedef struct __IM uint32_t ECCRS2 : 32; } ECCRS2_B; }; -}EMMC_Bank2_T; +} EMMC_Bank2_T; /** * @brief Flexible Static Memory Controller Bank 3 @@ -4560,7 +4628,7 @@ typedef struct __IOM uint32_t A2RDCFG : 4; __IOM uint32_t ECCPSCFG : 3; __IM uint32_t RESERVED3 : 12; - }CTRL3_B; + } CTRL3_B; }; /** FIFO status and interrupt register 3 */ @@ -4577,8 +4645,8 @@ typedef struct __IOM uint32_t IHLDEN : 1; __IOM uint32_t IFEDEN : 1; __IM uint32_t FEFLG : 1; - __IM uint32_t RESERVED :16; - }STSINT3_B; + __IM uint32_t RESERVED : 16; + } STSINT3_B; }; /** Common memory space timing register 3 */ @@ -4592,7 +4660,7 @@ typedef struct __IOM uint32_t WAIT3 : 8; __IOM uint32_t HLD3 : 8; __IOM uint32_t HIZ3 : 8; - }CMSTIM3_B; + } CMSTIM3_B; }; /** Attribute memory space timing register 3 */ @@ -4606,7 +4674,7 @@ typedef struct __IOM uint32_t WAIT3 : 8; __IOM uint32_t HLD3 : 8; __IOM uint32_t HIZ3 : 8; - }AMSTIM3_B; + } AMSTIM3_B; }; __IOM uint32_t RESERVED; @@ -4621,7 +4689,7 @@ typedef struct __IM uint32_t ECCRS3 : 32; } ECCRS3_B; }; -}EMMC_Bank3_T; +} EMMC_Bank3_T; /** * @brief Flexible Static Memory Controller Bank 4 @@ -4646,7 +4714,7 @@ typedef struct __IOM uint32_t A2RDCFG : 4; __IOM uint32_t ECCPSCFG : 3; __IM uint32_t RESERVED3 : 12; - }CTRL4_B; + } CTRL4_B; }; /** FIFO status and interrupt register 4 */ @@ -4663,8 +4731,8 @@ typedef struct __IOM uint32_t IHLDEN : 1; __IOM uint32_t IFEDEN : 1; __IM uint32_t FEFLG : 1; - __IM uint32_t RESERVED :16; - }STSINT4_B; + __IM uint32_t RESERVED : 16; + } STSINT4_B; }; /** Common memory space timing register 4 */ @@ -4678,7 +4746,7 @@ typedef struct __IOM uint32_t WAIT4 : 8; __IOM uint32_t HLD4 : 8; __IOM uint32_t HIZ4 : 8; - }CMSTIM4_B; + } CMSTIM4_B; }; /** Attribute memory space timing register 4 */ @@ -4692,7 +4760,7 @@ typedef struct __IOM uint32_t WAIT4 : 8; __IOM uint32_t HLD4 : 8; __IOM uint32_t HIZ4 : 8; - }AMSTIM4_B; + } AMSTIM4_B; }; /** I/O space timing register 4 */ @@ -4706,9 +4774,9 @@ typedef struct __IOM uint32_t WAIT4 : 8; __IOM uint32_t HLD4 : 8; __IOM uint32_t HIZ4 : 8; - }IOSTIM4_B; + } IOSTIM4_B; }; -}EMMC_Bank4_T; +} EMMC_Bank4_T; /** * @brief Queued serial peripheral interface(QSPI) @@ -4731,7 +4799,7 @@ typedef struct __IM uint32_t RESERVED3 : 7; __IOM uint32_t FRF : 2; __IM uint32_t RESERVED4 : 8; - }CTRL1_B; + } CTRL1_B; }; /** @brief Control register 2 */ @@ -4742,7 +4810,7 @@ typedef struct { __IOM uint32_t NDF : 16; __IM uint32_t RESERVED : 16; - }CTRL2_B; + } CTRL2_B; }; /** @brief QSPI Enable register */ @@ -4753,7 +4821,7 @@ typedef struct { __IOM uint32_t EN : 1; __IM uint32_t RESERVED : 31; - }SSIEN_B; + } SSIEN_B; }; __IM uint32_t RESERVED; @@ -4766,7 +4834,7 @@ typedef struct { __IOM uint32_t SLAEN : 1; __IM uint32_t RESERVED : 31; - }SLAEN_B; + } SLAEN_B; }; /** @brief Baudrate register */ @@ -4777,7 +4845,7 @@ typedef struct { __IOM uint32_t CLKDIV : 16; __IM uint32_t RESERVED : 16; - }BR_B; + } BR_B; }; /** @brief Transmission FIFO threshhold level register */ @@ -4790,7 +4858,7 @@ typedef struct __IM uint32_t RESERVED1 : 13; __IOM uint32_t TFTH : 3; __IM uint32_t RESERVED2 : 13; - }TFTL_B; + } TFTL_B; }; /** @brief Reception FIFO threshhold level register */ @@ -4801,7 +4869,7 @@ typedef struct { __IOM uint32_t RFT : 3; __IM uint32_t RESERVED : 29; - }RFTL_B; + } RFTL_B; }; /** @brief Transmission FIFO level register */ @@ -4812,7 +4880,7 @@ typedef struct { __IOM uint32_t TFL : 3; __IM uint32_t RESERVED : 29; - }TFL_B; + } TFL_B; }; /** @brief Reception FIFO level register */ @@ -4823,7 +4891,7 @@ typedef struct { __IOM uint32_t RFL : 3; __IM uint32_t RESERVED : 29; - }RFL_B; + } RFL_B; }; /** @brief Status register */ @@ -4840,7 +4908,7 @@ typedef struct __IM uint32_t RESERVED1 : 1; __IOM uint32_t DCEF : 1; __IM uint32_t RESERVED2 : 25; - }STS_B; + } STS_B; }; /** @brief Interrupt enable register */ @@ -4856,7 +4924,7 @@ typedef struct __IOM uint32_t RFFIE : 1; __IOM uint32_t MSTIE : 1; __IM uint32_t RESERVED : 26; - }INTEN_B; + } INTEN_B; }; /** @brief Interrupt status register */ @@ -4872,7 +4940,7 @@ typedef struct __IM uint32_t RFFIF : 1; __IM uint32_t MSTIF : 1; __IM uint32_t RESERVED : 26; - }ISTS_B; + } ISTS_B; }; /** @brief Raw interrupt register */ @@ -4888,7 +4956,7 @@ typedef struct __IM uint32_t RXFIR : 1; __IM uint32_t MSTIR : 1; __IM uint32_t RESERVED : 26; - }RIS_B; + } RIS_B; }; /** @brief Transmission FIFO overflow interrupt clear register */ @@ -4899,7 +4967,7 @@ typedef struct { __IM uint32_t TFOIC : 1; __IM uint32_t RESERVED : 31; - }TFOIC_B; + } TFOIC_B; }; /** @brief Reception FIFO overflow interrupt clear register */ @@ -4910,7 +4978,7 @@ typedef struct { __IM uint32_t RFOIC : 1; __IM uint32_t RESERVED : 31; - }RFOIC_B; + } RFOIC_B; }; /** @brief Reception FIFO underflow interrupt clear register */ @@ -4921,7 +4989,7 @@ typedef struct { __IM uint32_t RFUIC : 1; __IM uint32_t RESERVED : 31; - }RFUIC_B; + } RFUIC_B; }; /** @brief Master interrupt clear register */ @@ -4932,7 +5000,7 @@ typedef struct { __IM uint32_t MIC : 1; __IM uint32_t RESERVED : 31; - }MIC_B; + } MIC_B; }; /** @brief Interrupt clear register */ @@ -4943,7 +5011,7 @@ typedef struct { __IM uint32_t ICF : 1; __IM uint32_t RESERVED : 31; - }ICF_B; + } ICF_B; }; __IM uint32_t RESERVED1[5]; @@ -4955,7 +5023,7 @@ typedef struct struct { __IOM uint32_t DATA : 32; - }DATA_B; + } DATA_B; }; __IM uint32_t RESERVED2[35]; @@ -4970,7 +5038,7 @@ typedef struct __IM uint32_t RESERVED1 : 8; __IOM uint32_t RSE : 1; __IM uint32_t RESERVED2 : 15; - }RSD_B; + } RSD_B; }; /** @brief Reception sample register */ @@ -4988,7 +5056,7 @@ typedef struct __IM uint32_t RESERVED3 : 14; __IOM uint32_t CSEN : 1; __IM uint32_t RESERVED4 : 1; - }CTRL3_B; + } CTRL3_B; }; __IM uint32_t RESERVED3[66]; @@ -5001,9 +5069,9 @@ typedef struct { __IOM uint32_t IOSW : 1; __IM uint32_t RESERVED : 31; - }IOSW_B; + } IOSW_B; }; -}QSPI_T; +} QSPI_T; /** * @brief SEC Inter-integrated circuit (SCI2C) @@ -5027,7 +5095,7 @@ typedef struct __IOM uint32_t RFFIE : 1; __IOM uint32_t DSMA : 1; __IM uint32_t RESERVED2 : 21; - }CTRL1_B; + } CTRL1_B; }; /** @brief Master address register */ @@ -5041,7 +5109,7 @@ typedef struct __IOM uint32_t GCEN : 1; __IOM uint32_t MAM : 1; __IM uint32_t RESERVED : 19; - }TARADDR_B; + } TARADDR_B; }; /** @brief Slave address register */ @@ -5052,7 +5120,7 @@ typedef struct { __IOM uint32_t ADDR : 10; __IM uint32_t RESERVED : 22; - }SLAADDR_B; + } SLAADDR_B; }; /** @brief High speed master code register */ @@ -5063,7 +5131,7 @@ typedef struct { __IOM uint32_t HSMC : 4; __IM uint32_t RESERVED : 28; - }HSMC_B; + } HSMC_B; }; /** @brief Data register */ @@ -5076,7 +5144,7 @@ typedef struct __IOM uint32_t CMD : 1; __IOM uint32_t STOP : 1; __IM uint32_t RESERVED : 22; - }DATA_B; + } DATA_B; }; /** @brief Standard speed clock high counter register */ @@ -5087,7 +5155,7 @@ typedef struct { __IOM uint32_t CNT : 16; __IM uint32_t RESERVED : 16; - }SSCHC_B; + } SSCHC_B; }; /** @brief Standard speed clock low counter register */ @@ -5098,7 +5166,7 @@ typedef struct { __IOM uint32_t CNT : 16; __IM uint32_t RESERVED : 16; - }SSCLC_B; + } SSCLC_B; }; /** @brief Fast speed clock high counter register */ @@ -5109,7 +5177,7 @@ typedef struct { __IOM uint32_t CNT : 16; __IM uint32_t RESERVED : 16; - }FSCHC_B; + } FSCHC_B; }; /** @brief Fast speed clock low counter register */ @@ -5120,7 +5188,7 @@ typedef struct { __IOM uint32_t CNT : 16; __IM uint32_t RESERVED : 16; - }FSCLC_B; + } FSCLC_B; }; /** @brief High speed clock high counter */ @@ -5131,7 +5199,7 @@ typedef struct { __IOM uint32_t CNT : 16; __IM uint32_t RESERVED : 16; - }HSCHC_B; + } HSCHC_B; }; /** @brief High speed clock low counter register */ @@ -5142,7 +5210,7 @@ typedef struct { __IOM uint32_t CNT : 16; __IM uint32_t RESERVED : 16; - }HSCLC_B; + } HSCLC_B; }; /** @brief Interrupt status register */ @@ -5166,7 +5234,7 @@ typedef struct __IM uint32_t RSTADIF : 1; __IM uint32_t MOHIF : 1; __IM uint32_t RESERVED : 18; - }INTSTS_B; + } INTSTS_B; }; /** @brief Interrupt enable register */ @@ -5190,7 +5258,7 @@ typedef struct __IOM uint32_t RSTADIE : 1; __IOM uint32_t MOHIE : 1; __IM uint32_t RESERVED : 18; - }INTEN_B; + } INTEN_B; }; /** @brief Raw interrupt status register */ @@ -5213,7 +5281,7 @@ typedef struct __IM uint32_t GCIF : 1; __IM uint32_t RSTADIF : 1; __IM uint32_t RESERVED : 18; - }RIS_B; + } RIS_B; }; /** @brief Reception FIFO threshold register */ @@ -5224,7 +5292,7 @@ typedef struct { __IOM uint32_t RFT : 8; __IM uint32_t RESERVED : 24; - }RFT_B; + } RFT_B; }; /** @brief Transmission FIFO threshold register */ @@ -5235,7 +5303,7 @@ typedef struct { __IOM uint32_t TFT : 8; __IM uint32_t RESERVED : 24; - }TFT_B; + } TFT_B; }; /** @brief Interruption clear register */ @@ -5246,7 +5314,7 @@ typedef struct { __IM uint32_t INTCLR : 1; __IM uint32_t RESERVED : 31; - }INTCLR_B; + } INTCLR_B; }; /** @brief Reception FIFO underflow interruption clear register */ @@ -5257,7 +5325,7 @@ typedef struct { __IM uint32_t RFUIC : 1; __IM uint32_t RESERVED : 31; - }RFUIC_B; + } RFUIC_B; }; /** @brief Reception FIFO overflow interruption clear register */ @@ -5268,7 +5336,7 @@ typedef struct { __IM uint32_t RFOIC : 1; __IM uint32_t RESERVED : 31; - }RFOIC_B; + } RFOIC_B; }; /** @brief Transmission FIFO overflow interruption clear register */ @@ -5279,7 +5347,7 @@ typedef struct { __IM uint32_t TFOIC : 1; __IM uint32_t RESERVED : 31; - }TFOIC_B; + } TFOIC_B; }; /** @brief Reception request interruption clear register */ @@ -5290,7 +5358,7 @@ typedef struct { __IM uint32_t RRIC : 1; __IM uint32_t RESERVED : 31; - }RRIC_B; + } RRIC_B; }; /** @brief Transmission abort interruption clear register */ @@ -5301,7 +5369,7 @@ typedef struct { __IM uint32_t TAIC : 1; __IM uint32_t RESERVED : 31; - }TAIC_B; + } TAIC_B; }; /** @brief Receive done interruption clear register */ @@ -5312,7 +5380,7 @@ typedef struct { __IM uint32_t RDIC : 1; __IM uint32_t RESERVED : 31; - }RDIC_B; + } RDIC_B; }; /** @brief Activity interruption clear register */ @@ -5323,7 +5391,7 @@ typedef struct { __IM uint32_t AIC : 1; __IM uint32_t RESERVED : 31; - }AIC_B; + } AIC_B; }; /** @brief Stop detection interruption clear register */ @@ -5334,7 +5402,7 @@ typedef struct { __IM uint32_t STPDIC : 1; __IM uint32_t RESERVED : 31; - }STPDIC_B; + } STPDIC_B; }; /** @brief Start detection interruption clear register */ @@ -5345,7 +5413,7 @@ typedef struct { __IM uint32_t STADIC : 1; __IM uint32_t RESERVED : 31; - }STADIC_B; + } STADIC_B; }; /** @brief General call interruption clear register */ @@ -5356,7 +5424,7 @@ typedef struct { __IM uint32_t GCIC : 1; __IM uint32_t RESERVED : 31; - }GCIC_B; + } GCIC_B; }; /** @brief Control register 2 */ @@ -5369,7 +5437,7 @@ typedef struct __IOM uint32_t ABR : 1; __IOM uint32_t TCB : 1; __IM uint32_t RESERVED : 29; - }CTRL2_B; + } CTRL2_B; }; /** @brief Status register 1 */ @@ -5386,7 +5454,7 @@ typedef struct __IM uint32_t MAF : 1; __IM uint32_t SAF : 1; __IM uint32_t RESERVED : 24; - }STS1_B; + } STS1_B; }; /** @brief Transmission FIFO level */ @@ -5397,7 +5465,7 @@ typedef struct { __IOM uint32_t TFL : 4; __IM uint32_t RESERVED : 28; - }TFL_B; + } TFL_B; }; /** @brief Reception FIFO level */ @@ -5408,7 +5476,7 @@ typedef struct { __IOM uint32_t RFL : 4; __IM uint32_t RESERVED : 28; - }RFL_B; + } RFL_B; }; /** @brief SDA hold time length register */ @@ -5420,7 +5488,7 @@ typedef struct __IOM uint32_t TXHOLD : 16; __IOM uint32_t RXHOLD : 8; __IM uint32_t RESERVED : 8; - }SDAHOLD_B; + } SDAHOLD_B; }; /** @brief Transmission abort source register */ @@ -5446,7 +5514,7 @@ typedef struct __IM uint32_t USRARB : 1; __IM uint32_t FLUCNT : 1; __IM uint32_t RESERVED : 16; - }TAS_B; + } TAS_B; }; /** @brief Slave data NACK only register */ @@ -5457,7 +5525,7 @@ typedef struct { __IOM uint32_t NACK : 1; __IM uint32_t RESERVED : 31; - }SDNO_B; + } SDNO_B; }; /** @brief DMA control register */ @@ -5469,7 +5537,7 @@ typedef struct __IOM uint32_t RXEN : 1; __IOM uint32_t TXEN : 1; __IM uint32_t RESERVED : 30; - }DMACTRL_B; + } DMACTRL_B; }; /** @brief DMA transmission data level register */ @@ -5480,7 +5548,7 @@ typedef struct { __IOM uint32_t DTDL : 4; __IM uint32_t RESERVED : 28; - }DTDL_B; + } DTDL_B; }; /** @brief DMA teception data level register */ @@ -5491,7 +5559,7 @@ typedef struct { __IOM uint32_t DRDL : 4; __IM uint32_t RESERVED : 28; - }DRDL_B; + } DRDL_B; }; /** @brief SDA delay register */ @@ -5502,7 +5570,7 @@ typedef struct { __IOM uint32_t SDADLY : 8; __IM uint32_t RESERVED : 24; - }SDADLY_B; + } SDADLY_B; }; /** @brief Genernal call ACK register */ @@ -5513,7 +5581,7 @@ typedef struct { __IOM uint32_t GCA : 1; __IM uint32_t RESERVED : 31; - }GCA_B; + } GCA_B; }; /** @brief Status register 2 */ @@ -5526,7 +5594,7 @@ typedef struct __IM uint32_t SDWB : 1; __IM uint32_t SRDL : 1; __IM uint32_t RESERVED : 29; - }STS2_B; + } STS2_B; }; /** @brief Low speed spike suppression limit */ @@ -5537,7 +5605,7 @@ typedef struct { __IOM uint32_t LSSSL : 8; __IM uint32_t RESERVED : 24; - }LSSSL_B; + } LSSSL_B; }; /** @brief High speed spike suppression limit */ @@ -5548,7 +5616,7 @@ typedef struct { __IOM uint32_t HSSSL : 8; __IM uint32_t RESERVED : 24; - }HSSSL_B; + } HSSSL_B; }; uint32_t RESERVED[22]; @@ -5561,9 +5629,9 @@ typedef struct { __IOM uint32_t SW : 1; __IM uint32_t RESERVED : 31; - }SW_B; + } SW_B; }; -}SCI2C_T; +} SCI2C_T; /** * @brief Dynamic memory controler (DMC) @@ -5582,7 +5650,7 @@ typedef struct __IOM uint32_t CAWCFG : 4; __IOM uint32_t DWCFG : 2; __IM uint32_t RESERVED2 : 16; - }CFG_B; + } CFG_B; }; /** @brief Timing register 0 */ @@ -5601,7 +5669,7 @@ typedef struct __IOM uint32_t ATACP : 4; __IOM uint32_t ECASLSEL1 : 1; __IOM uint32_t EXSR1 : 5; - }TIM0_B; + } TIM0_B; }; /** @brief Timing register 1 */ @@ -5613,7 +5681,7 @@ typedef struct __IOM uint32_t STBTIM : 16; __IOM uint32_t ARNUMCFG : 4; __IM uint32_t RESERVED : 12; - }TIM1_B; + } TIM1_B; }; /** @brief Control register 1 */ @@ -5634,7 +5702,7 @@ typedef struct __IM uint32_t SRMFLG : 1; __IOM uint32_t BANKNUMCFG : 5; __IM uint32_t RESERVED2 : 15; - }CTRL1_B; + } CTRL1_B; }; /** @brief Refresh register */ @@ -5645,7 +5713,7 @@ typedef struct { __IOM uint32_t RCYCCFG : 16; __IM uint32_t RESERVED : 16; - }REF_B; + } REF_B; }; /** @brief Chip select register */ @@ -5657,7 +5725,7 @@ typedef struct __IM uint32_t RESERVED : 16; __IOM uint32_t BACHIPSEL : 16; - }CHIPSEL_B; + } CHIPSEL_B; }; __IM uint32_t RESERVED[15]; @@ -5671,7 +5739,7 @@ typedef struct __IOM uint32_t MSIZESEL : 5; __IOM uint32_t MTYPESEL : 3; __IM uint32_t RESERVED : 24; - }MASK_B; + } MASK_B; }; __IM uint32_t RESERVED1[234]; @@ -5684,7 +5752,7 @@ typedef struct { __IOM uint32_t MCSW : 1; __IM uint32_t RESERVED : 31; - }SW_B; + } SW_B; }; /** @brief Control register 2 */ @@ -5697,10 +5765,12 @@ typedef struct __IOM uint32_t RDDEN : 1; __IOM uint32_t RDDCFG : 3; __IOM uint32_t WPEN : 1; - __IM uint32_t RESERVED : 26; - }CTRL2_B; + __IOM uint32_t BUFFEN : 1; + __IOM uint32_t WRPBSEL : 1; + __IM uint32_t RESERVED : 24; + } CTRL2_B; }; -}DMC_T; +} DMC_T; /** * @brief Debug MCU(DBGMCU) @@ -5716,7 +5786,7 @@ typedef struct __IOM uint32_t EQR : 12; __IM uint32_t RESERVED : 4; __IOM uint32_t WVR : 16; - }IDCODE_B; + } IDCODE_B; }; /** @brief Control register */ @@ -5753,9 +5823,9 @@ typedef struct __IOM uint32_t TMR10_STS : 1; __IOM uint32_t TMR11_STS : 1; __IM uint32_t RESERVED3 : 1; - }CFG_B; + } CFG_B; }; -}DBGMCU_T; +} DBGMCU_T; /** * @brief USB Device controler(USBD) @@ -5777,13 +5847,13 @@ typedef union __IOM uint32_t RXDTOG : 1; __IOM uint32_t CTFR : 1; __IM uint32_t RESERVED : 16; - }EP_B; -}USB_EP_REG_T; + } EP_B; +} USBD_EP_REG_T; typedef struct { /** Endpoint */ - USB_EP_REG_T EP[8]; + USBD_EP_REG_T EP[8]; __IM uint32_t RESERVED[8]; @@ -5809,7 +5879,7 @@ typedef struct __IOM uint32_t PMAOUIEN : 1; __IOM uint32_t CTRIEN : 1; __IM uint32_t RESERVED2 : 16; - }CTRL_B; + } CTRL_B; }; /** @brief Interrupt status register */ @@ -5831,7 +5901,7 @@ typedef struct __IOM uint32_t PMOFLG : 1; __IOM uint32_t CTFLG : 1; __IM uint32_t RESERVED2 : 16; - }INTSTS_B; + } INTSTS_B; }; /** @brief Frame number register */ @@ -5847,7 +5917,7 @@ typedef struct __IM uint32_t RXDMSTS : 1; __IM uint32_t RXDPSTS : 1; __IM uint32_t RESERVED : 16; - }FRANUM_B; + } FRANUM_B; }; /** @brief Device address register */ @@ -5860,7 +5930,7 @@ typedef struct __IOM uint32_t ADDR : 7; __IOM uint32_t USBDEN : 1; __IM uint32_t RESERVED : 24; - }ADDR_B; + } ADDR_B; }; /** @brief Buffer table address register */ @@ -5873,7 +5943,7 @@ typedef struct __IM uint32_t RESERVED1 : 3; __IOM uint32_t BUFFTB : 13; __IM uint32_t RESERVED2 : 16; - }BUFFTB_B; + } BUFFTB_B; }; __IM uint32_t RESERVED1[43]; @@ -5887,9 +5957,9 @@ typedef struct { __IOM uint32_t SWITCH : 1; __IM uint32_t RESERVED : 31; - }SWITCH_B; + } SWITCH_B; }; -}USBD_T; +} USBD_T; /** FMC base address in the alias region */ #define FMC_BASE ((uint32_t)0x08000000) @@ -6096,11 +6166,12 @@ typedef struct #if defined (APM32F10X_MD) || defined (APM32F10X_LD) #define QSPI ((QSPI_T *)QSPI_BASE) -#elif defined (APM32F10X_HD) -#define DMC ((DMC_T *)DMC_BASE) +#endif +#if defined (APM32F10X_HD) +#define DMC ((DMC_T *)DMC_BASE) #endif -/* Define one bit mask */ +/** Define one bit mask */ #define BIT0 ((uint32_t)0x00000001) #define BIT1 ((uint32_t)0x00000002) #define BIT2 ((uint32_t)0x00000004) @@ -6153,6 +6224,6 @@ typedef struct } #endif -#endif /* __APM32F10x_H */ +#endif /* __APM32F10X_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Include/system_apm32f10x.h b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Include/system_apm32f10x.h index 2054757063..29a91b55f1 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Include/system_apm32f10x.h +++ b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Include/system_apm32f10x.h @@ -3,17 +3,31 @@ * * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ #ifndef __SYSTEM_APM32F10X_H #define __SYSTEM_APM32F10X_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif extern uint32_t SystemCoreClock; diff --git a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/ARM/startup_apm32f10x_hd.s b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/ARM/startup_apm32f10x_hd.s index d82311b15e..5be8ad078a 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/ARM/startup_apm32f10x_hd.s +++ b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/ARM/startup_apm32f10x_hd.s @@ -1,262 +1,367 @@ ;/*! -; * @file startup_apm32f10x_hd.s +; * @file startup_apm32f10x_hd.s ; * -; * @brief CMSIS Cortex-M3 based Core Device Startup File for Device startup_apm32f10x_hd +; * @brief CMSIS Cortex-M3 based Core Device Startup File for Device startup_apm32f10x_hd ; * -; * @version V1.0.1 +; * @version V1.0.2 ; * -; * @date 2021-03-23 +; * @date 2022-01-05 ; * +; * @attention +; * +; * Copyright (C) 2020-2022 Geehy Semiconductor +; * +; * You may not use this file except in compliance with the +; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). +; * +; * The program is only for reference, which is distributed in the hope +; * that it will be usefull and instructional for customers to develop +; * their software. Unless required by applicable law or agreed to in +; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT +; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. +; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions +; * and limitations under the License. ; */ -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; +; + Stack Configuration +; + Stack Size(in Bytes) < 0x0 - 0xFFFFFFFF: 8 > +; +< / h > Stack_Size EQU 0x00000400 - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp +AREA STACK, NOINIT, READWRITE, ALIGN = 3 + Stack_Mem SPACE Stack_Size + __initial_sp -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; + ; + Heap Configuration +; + Heap Size(in Bytes) < 0x0 - 0xFFFFFFFF: 8 > +; +< / h > Heap_Size EQU 0x00000200 - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit +AREA HEAP, NOINIT, READWRITE, ALIGN = 3 + __heap_base + Heap_Mem SPACE Heap_Size + __heap_limit - PRESERVE8 - THUMB + PRESERVE8 + THUMB -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size + ; +Vector Table Mapped to Address 0 at Reset +AREA RESET, DATA, READONLY +EXPORT __Vectors +EXPORT __Vectors_End +EXPORT __Vectors_Size -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler +__Vectors DCD __initial_sp ; +Top of Stack +DCD Reset_Handler ; +Reset Handler +DCD NMI_Handler ; +NMI Handler +DCD HardFault_Handler ; +Hard Fault Handler +DCD MemManage_Handler ; +MPU Fault Handler +DCD BusFault_Handler ; +Bus Fault Handler +DCD UsageFault_Handler ; +Usage Fault Handler +DCD 0 ; +Reserved +DCD 0 ; +Reserved +DCD 0 ; +Reserved +DCD 0 ; +Reserved +DCD SVC_Handler ; +SVCall Handler +DCD DebugMon_Handler ; +Debug Monitor Handler +DCD 0 ; +Reserved +DCD PendSV_Handler ; +PendSV Handler +DCD SysTick_Handler ; +SysTick Handler - ; External Interrupts - DCD WWDT_IRQHandler ; Window Watchdog - DCD PVD_IRQHandler ; PVD through EINT Line detect - DCD TAMPER_IRQHandler ; Tamper - DCD RTC_IRQHandler ; RTC - DCD FMC_IRQHandler ; Flash - DCD RCM_IRQHandler ; RCM - DCD EINT0_IRQHandler ; EINT Line 0 - DCD EINT1_IRQHandler ; EINT Line 1 - DCD EINT2_IRQHandler ; EINT Line 2 - DCD EINT3_IRQHandler ; EINT Line 3 - DCD EINT4_IRQHandler ; EINT Line 4 - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 - DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 - DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 - DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 - DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 - DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 - DCD ADC1_2_IRQHandler ; ADC1 & ADC2 - DCD USBD1_HP_CAN1_TX_IRQHandler ; USBD1 High Priority or CAN1 TX - DCD USBD1_LP_CAN1_RX0_IRQHandler ; USBD1 Low Priority or CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EINT9_5_IRQHandler ; EINT Line 9..5 - DCD TMR1_BRK_IRQHandler ; TMR1 Break - DCD TMR1_UP_IRQHandler ; TMR1 Update - DCD TMR1_TRG_COM_IRQHandler ; TMR1 Trigger and Commutation - DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare - DCD TMR2_IRQHandler ; TMR2 - DCD TMR3_IRQHandler ; TMR3 - DCD TMR4_IRQHandler ; TMR4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EINT15_10_IRQHandler ; EINT Line 15..10 - DCD RTCAlarm_IRQHandler ; RTC Alarm through EINT Line - DCD USBDWakeUp_IRQHandler ; USBD Wakeup from suspend - DCD TMR8_BRK_IRQHandler ; TMR8 Break - DCD TMR8_UP_IRQHandler ; TMR8 Update - DCD TMR8_TRG_COM_IRQHandler ; TMR8 Trigger and Commutation - DCD TMR8_CC_IRQHandler ; TMR8 Capture Compare - DCD ADC3_IRQHandler ; ADC3 - DCD EMMC_IRQHandler ; EMMC - DCD SDIO_IRQHandler ; SDIO - DCD TMR5_IRQHandler ; TMR5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TMR6_IRQHandler ; TMR6 - DCD TMR7_IRQHandler ; TMR7 - DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 - DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 - DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 - DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5 - DCD 0 ; Reserved - DCD USBD2_HP_CAN2_TX_IRQHandler ; USBD2 High Priority or CAN2 TX - DCD USBD2_LP_CAN2_RX0_IRQHandler ; USBD2 Low Priority or CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE +; +External Interrupts +DCD WWDT_IRQHandler ; +Window Watchdog +DCD PVD_IRQHandler ; +PVD through EINT Line detect +DCD TAMPER_IRQHandler ; +Tamper +DCD RTC_IRQHandler ; +RTC +DCD FLASH_IRQHandler ; +Flash +DCD RCM_IRQHandler ; +RCM +DCD EINT0_IRQHandler ; +EINT Line 0 +DCD EINT1_IRQHandler ; +EINT Line 1 +DCD EINT2_IRQHandler ; +EINT Line 2 +DCD EINT3_IRQHandler ; +EINT Line 3 +DCD EINT4_IRQHandler ; +EINT Line 4 +DCD DMA1_Channel1_IRQHandler ; +DMA1 Channel 1 +DCD DMA1_Channel2_IRQHandler ; +DMA1 Channel 2 +DCD DMA1_Channel3_IRQHandler ; +DMA1 Channel 3 +DCD DMA1_Channel4_IRQHandler ; +DMA1 Channel 4 +DCD DMA1_Channel5_IRQHandler ; +DMA1 Channel 5 +DCD DMA1_Channel6_IRQHandler ; +DMA1 Channel 6 +DCD DMA1_Channel7_IRQHandler ; +DMA1 Channel 7 +DCD ADC1_2_IRQHandler ; +ADC1 &ADC2 +DCD USBD1_HP_CAN1_TX_IRQHandler ; +USBD1 High Priority or CAN1 TX +DCD USBD1_LP_CAN1_RX0_IRQHandler ; +USBD1 Low Priority or CAN1 RX0 +DCD CAN1_RX1_IRQHandler ; +CAN1 RX1 +DCD CAN1_SCE_IRQHandler ; +CAN1 SCE +DCD EINT9_5_IRQHandler ; +EINT Line 9..5 +DCD TMR1_BRK_IRQHandler ; +TMR1 Break +DCD TMR1_UP_IRQHandler ; +TMR1 Update +DCD TMR1_TRG_COM_IRQHandler ; +TMR1 Trigger and Commutation +DCD TMR1_CC_IRQHandler ; +TMR1 Capture Compare +DCD TMR2_IRQHandler ; +TMR2 +DCD TMR3_IRQHandler ; +TMR3 +DCD TMR4_IRQHandler ; +TMR4 +DCD I2C1_EV_IRQHandler ; +I2C1 Event +DCD I2C1_ER_IRQHandler ; +I2C1 Error +DCD I2C2_EV_IRQHandler ; +I2C2 Event +DCD I2C2_ER_IRQHandler ; +I2C2 Error +DCD SPI1_IRQHandler ; +SPI1 +DCD SPI2_IRQHandler ; +SPI2 +DCD USART1_IRQHandler ; +USART1 +DCD USART2_IRQHandler ; +USART2 +DCD USART3_IRQHandler ; +USART3 +DCD EINT15_10_IRQHandler ; +EINT Line 15..10 +DCD RTCAlarm_IRQHandler ; +RTC Alarm through EINT Line +DCD USBDWakeUp_IRQHandler ; +USBD Wakeup from suspend +DCD TMR8_BRK_IRQHandler ; +TMR8 Break +DCD TMR8_UP_IRQHandler ; +TMR8 Update +DCD TMR8_TRG_COM_IRQHandler ; +TMR8 Trigger and Commutation +DCD TMR8_CC_IRQHandler ; +TMR8 Capture Compare +DCD ADC3_IRQHandler ; +ADC3 +DCD EMMC_IRQHandler ; +EMMC +DCD SDIO_IRQHandler ; +SDIO +DCD TMR5_IRQHandler ; +TMR5 +DCD SPI3_IRQHandler ; +SPI3 +DCD UART4_IRQHandler ; +UART4 +DCD UART5_IRQHandler ; +UART5 +DCD TMR6_IRQHandler ; +TMR6 +DCD TMR7_IRQHandler ; +TMR7 +DCD DMA2_Channel1_IRQHandler ; +DMA2 Channel1 +DCD DMA2_Channel2_IRQHandler ; +DMA2 Channel2 +DCD DMA2_Channel3_IRQHandler ; +DMA2 Channel3 +DCD DMA2_Channel4_5_IRQHandler ; +DMA2 Channel4 &Channel5 +DCD 0 ; +Reserved +DCD USBD2_HP_CAN2_TX_IRQHandler ; +USBD2 High Priority or CAN2 TX +DCD USBD2_LP_CAN2_RX0_IRQHandler ; +USBD2 Low Priority or CAN2 RX0 +DCD CAN2_RX1_IRQHandler ; +CAN2 RX1 +DCD CAN2_SCE_IRQHandler ; +CAN2 SCE __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors - AREA |.text|, CODE, READONLY +AREA | .text |, CODE, READONLY -; Reset handler +; +Reset handler Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP +EXPORT Reset_Handler [WEAK] +IMPORT __main +IMPORT SystemInit +LDR R0, = SystemInit + BLX R0 + LDR R0, = __main + BX R0 + ENDP -; Dummy Exception Handlers (infinite loops which can be modified) + ; +Dummy Exception Handlers(infinite loops which can be modified) NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP +EXPORT NMI_Handler [WEAK] +B . +ENDP HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP +PROC +EXPORT HardFault_Handler [WEAK] +B . +ENDP MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP +PROC +EXPORT MemManage_Handler [WEAK] +B . +ENDP BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP +PROC +EXPORT BusFault_Handler [WEAK] +B . +ENDP UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP +PROC +EXPORT UsageFault_Handler [WEAK] +B . +ENDP SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP +EXPORT SVC_Handler [WEAK] +B . +ENDP DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP +PROC +EXPORT DebugMon_Handler [WEAK] +B . +ENDP PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP +EXPORT PendSV_Handler [WEAK] +B . +ENDP SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP +EXPORT SysTick_Handler [WEAK] +B . +ENDP Default_Handler PROC - EXPORT WWDT_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMPER_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT RCM_IRQHandler [WEAK] - EXPORT EINT0_IRQHandler [WEAK] - EXPORT EINT1_IRQHandler [WEAK] - EXPORT EINT2_IRQHandler [WEAK] - EXPORT EINT3_IRQHandler [WEAK] - EXPORT EINT4_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_IRQHandler [WEAK] - EXPORT DMA1_Channel3_IRQHandler [WEAK] - EXPORT DMA1_Channel4_IRQHandler [WEAK] - EXPORT DMA1_Channel5_IRQHandler [WEAK] - EXPORT DMA1_Channel6_IRQHandler [WEAK] - EXPORT DMA1_Channel7_IRQHandler [WEAK] - EXPORT ADC1_2_IRQHandler [WEAK] - EXPORT USBD1_HP_CAN1_TX_IRQHandler [WEAK] - EXPORT USBD1_LP_CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EINT9_5_IRQHandler [WEAK] - EXPORT TMR1_BRK_IRQHandler [WEAK] - EXPORT TMR1_UP_IRQHandler [WEAK] - EXPORT TMR1_TRG_COM_IRQHandler [WEAK] - EXPORT TMR1_CC_IRQHandler [WEAK] - EXPORT TMR2_IRQHandler [WEAK] - EXPORT TMR3_IRQHandler [WEAK] - EXPORT TMR4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EINT15_10_IRQHandler [WEAK] - EXPORT RTCAlarm_IRQHandler [WEAK] - EXPORT USBDWakeUp_IRQHandler [WEAK] - EXPORT TMR8_BRK_IRQHandler [WEAK] - EXPORT TMR8_UP_IRQHandler [WEAK] - EXPORT TMR8_TRG_COM_IRQHandler [WEAK] - EXPORT TMR8_CC_IRQHandler [WEAK] - EXPORT ADC3_IRQHandler [WEAK] - EXPORT EMMC_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT TMR5_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT UART5_IRQHandler [WEAK] - EXPORT TMR6_IRQHandler [WEAK] - EXPORT TMR7_IRQHandler [WEAK] - EXPORT DMA2_Channel1_IRQHandler [WEAK] - EXPORT DMA2_Channel2_IRQHandler [WEAK] - EXPORT DMA2_Channel3_IRQHandler [WEAK] - EXPORT DMA2_Channel4_5_IRQHandler [WEAK] - EXPORT USBD2_HP_CAN2_TX_IRQHandler [WEAK] - EXPORT USBD2_LP_CAN2_RX0_IRQHandler [WEAK] - EXPORT CAN2_RX1_IRQHandler [WEAK] - EXPORT CAN2_SCE_IRQHandler [WEAK] +EXPORT WWDT_IRQHandler [WEAK] +EXPORT PVD_IRQHandler [WEAK] +EXPORT TAMPER_IRQHandler [WEAK] +EXPORT RTC_IRQHandler [WEAK] +EXPORT FLASH_IRQHandler [WEAK] +EXPORT RCM_IRQHandler [WEAK] +EXPORT EINT0_IRQHandler [WEAK] +EXPORT EINT1_IRQHandler [WEAK] +EXPORT EINT2_IRQHandler [WEAK] +EXPORT EINT3_IRQHandler [WEAK] +EXPORT EINT4_IRQHandler [WEAK] +EXPORT DMA1_Channel1_IRQHandler [WEAK] +EXPORT DMA1_Channel2_IRQHandler [WEAK] +EXPORT DMA1_Channel3_IRQHandler [WEAK] +EXPORT DMA1_Channel4_IRQHandler [WEAK] +EXPORT DMA1_Channel5_IRQHandler [WEAK] +EXPORT DMA1_Channel6_IRQHandler [WEAK] +EXPORT DMA1_Channel7_IRQHandler [WEAK] +EXPORT ADC1_2_IRQHandler [WEAK] +EXPORT USBD1_HP_CAN1_TX_IRQHandler [WEAK] +EXPORT USBD1_LP_CAN1_RX0_IRQHandler [WEAK] +EXPORT CAN1_RX1_IRQHandler [WEAK] +EXPORT CAN1_SCE_IRQHandler [WEAK] +EXPORT EINT9_5_IRQHandler [WEAK] +EXPORT TMR1_BRK_IRQHandler [WEAK] +EXPORT TMR1_UP_IRQHandler [WEAK] +EXPORT TMR1_TRG_COM_IRQHandler [WEAK] +EXPORT TMR1_CC_IRQHandler [WEAK] +EXPORT TMR2_IRQHandler [WEAK] +EXPORT TMR3_IRQHandler [WEAK] +EXPORT TMR4_IRQHandler [WEAK] +EXPORT I2C1_EV_IRQHandler [WEAK] +EXPORT I2C1_ER_IRQHandler [WEAK] +EXPORT I2C2_EV_IRQHandler [WEAK] +EXPORT I2C2_ER_IRQHandler [WEAK] +EXPORT SPI1_IRQHandler [WEAK] +EXPORT SPI2_IRQHandler [WEAK] +EXPORT USART1_IRQHandler [WEAK] +EXPORT USART2_IRQHandler [WEAK] +EXPORT USART3_IRQHandler [WEAK] +EXPORT EINT15_10_IRQHandler [WEAK] +EXPORT RTCAlarm_IRQHandler [WEAK] +EXPORT USBDWakeUp_IRQHandler [WEAK] +EXPORT TMR8_BRK_IRQHandler [WEAK] +EXPORT TMR8_UP_IRQHandler [WEAK] +EXPORT TMR8_TRG_COM_IRQHandler [WEAK] +EXPORT TMR8_CC_IRQHandler [WEAK] +EXPORT ADC3_IRQHandler [WEAK] +EXPORT EMMC_IRQHandler [WEAK] +EXPORT SDIO_IRQHandler [WEAK] +EXPORT TMR5_IRQHandler [WEAK] +EXPORT SPI3_IRQHandler [WEAK] +EXPORT UART4_IRQHandler [WEAK] +EXPORT UART5_IRQHandler [WEAK] +EXPORT TMR6_IRQHandler [WEAK] +EXPORT TMR7_IRQHandler [WEAK] +EXPORT DMA2_Channel1_IRQHandler [WEAK] +EXPORT DMA2_Channel2_IRQHandler [WEAK] +EXPORT DMA2_Channel3_IRQHandler [WEAK] +EXPORT DMA2_Channel4_5_IRQHandler [WEAK] +EXPORT USBD2_HP_CAN2_TX_IRQHandler [WEAK] +EXPORT USBD2_LP_CAN2_RX0_IRQHandler [WEAK] +EXPORT CAN2_RX1_IRQHandler [WEAK] +EXPORT CAN2_SCE_IRQHandler [WEAK] WWDT_IRQHandler PVD_IRQHandler TAMPER_IRQHandler RTC_IRQHandler -FMC_IRQHandler +FLASH_IRQHandler RCM_IRQHandler EINT0_IRQHandler EINT1_IRQHandler @@ -316,39 +421,45 @@ USBD2_HP_CAN2_TX_IRQHandler USBD2_LP_CAN2_RX0_IRQHandler CAN2_RX1_IRQHandler CAN2_SCE_IRQHandler - B . +B . - ENDP +ENDP - ALIGN +ALIGN -;******************************************************************************* -; User Stack and Heap initialization -;******************************************************************************* - IF :DEF:__MICROLIB +; +******************************************************************************* +; +User Stack and Heap initialization +; +******************************************************************************* +IF : +DEF: +__MICROLIB - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit +EXPORT __initial_sp +EXPORT __heap_base +EXPORT __heap_limit - ELSE +ELSE - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap +IMPORT __use_two_region_memory +EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem - LDR R1, = (Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR +LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR - ALIGN + ALIGN - ENDIF + ENDIF - END + END -;*******************************END OF FILE************************************ + ; +*******************************END OF FILE ************************************ diff --git a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/ARM/startup_apm32f10x_md.s b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/ARM/startup_apm32f10x_md.s index 95ea8f5f22..238be8397c 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/ARM/startup_apm32f10x_md.s +++ b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/ARM/startup_apm32f10x_md.s @@ -1,227 +1,314 @@ ;/*! -; * @file startup_apm32f10x_md.s +; * @file startup_apm32f10x_md.s ; * -; * @brief CMSIS Cortex-M3 based Core Device Startup File for Device startup_apm32f10x_md +; * @brief CMSIS Cortex-M3 based Core Device Startup File for Device startup_apm32f10x_md ; * -; * @version V1.0.1 +; * @version V1.0.2 ; * -; * @date 2021-03-23 +; * @date 2022-01-05 ; * +; * @attention +; * +; * Copyright (C) 2020-2022 Geehy Semiconductor +; * +; * You may not use this file except in compliance with the +; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). +; * +; * The program is only for reference, which is distributed in the hope +; * that it will be usefull and instructional for customers to develop +; * their software. Unless required by applicable law or agreed to in +; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT +; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. +; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions +; * and limitations under the License. ; */ -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; +; + Stack Configuration +; + Stack Size(in Bytes) < 0x0 - 0xFFFFFFFF: 8 > +; +< / h > Stack_Size EQU 0x00000400 - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp +AREA STACK, NOINIT, READWRITE, ALIGN = 3 + Stack_Mem SPACE Stack_Size + __initial_sp -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; + ; + Heap Configuration +; + Heap Size(in Bytes) < 0x0 - 0xFFFFFFFF: 8 > +; +< / h > Heap_Size EQU 0x00000200 - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit +AREA HEAP, NOINIT, READWRITE, ALIGN = 3 + __heap_base + Heap_Mem SPACE Heap_Size + __heap_limit - PRESERVE8 - THUMB + PRESERVE8 + THUMB -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size + ; +Vector Table Mapped to Address 0 at Reset +AREA RESET, DATA, READONLY +EXPORT __Vectors +EXPORT __Vectors_End +EXPORT __Vectors_Size -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler +__Vectors DCD __initial_sp ; +Top of Stack +DCD Reset_Handler ; +Reset Handler +DCD NMI_Handler ; +NMI Handler +DCD HardFault_Handler ; +Hard Fault Handler +DCD MemManage_Handler ; +MPU Fault Handler +DCD BusFault_Handler ; +Bus Fault Handler +DCD UsageFault_Handler ; +Usage Fault Handler +DCD 0 ; +Reserved +DCD 0 ; +Reserved +DCD 0 ; +Reserved +DCD 0 ; +Reserved +DCD SVC_Handler ; +SVCall Handler +DCD DebugMon_Handler ; +Debug Monitor Handler +DCD 0 ; +Reserved +DCD PendSV_Handler ; +PendSV Handler +DCD SysTick_Handler ; +SysTick Handler - ; External Interrupts - DCD WWDT_IRQHandler ; Window Watchdog - DCD PVD_IRQHandler ; PVD through EINT Line detect - DCD TAMPER_IRQHandler ; Tamper - DCD RTC_IRQHandler ; RTC - DCD FMC_IRQHandler ; Flash - DCD RCM_IRQHandler ; RCM - DCD EINT0_IRQHandler ; EINT Line 0 - DCD EINT1_IRQHandler ; EINT Line 1 - DCD EINT2_IRQHandler ; EINT Line 2 - DCD EINT3_IRQHandler ; EINT Line 3 - DCD EINT4_IRQHandler ; EINT Line 4 - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 - DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 - DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 - DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 - DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 - DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 - DCD ADC1_2_IRQHandler ; ADC1_2 - DCD USBD1_HP_CAN1_TX_IRQHandler ; USBD1 High Priority or CAN1 TX - DCD USBD1_LP_CAN1_RX0_IRQHandler ; USBD1 Low Priority or CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EINT9_5_IRQHandler ; EINT Line 9..5 - DCD TMR1_BRK_IRQHandler ; TMR1 Break - DCD TMR1_UP_IRQHandler ; TMR1 Update - DCD TMR1_TRG_COM_IRQHandler ; TMR1 Trigger and Commutation - DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare - DCD TMR2_IRQHandler ; TMR2 - DCD TMR3_IRQHandler ; TMR3 - DCD TMR4_IRQHandler ; TMR4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EINT15_10_IRQHandler ; EINT Line 15..10 - DCD RTCAlarm_IRQHandler ; RTC Alarm through EINT Line - DCD USBDWakeUp_IRQHandler ; USBD Wakeup from suspend - DCD FPU_IRQHandler ; FPU - DCD QSPI_IRQHandler ; QSPI - DCD USBD2_HP_IRQHandler ; USBD2 High Priority - DCD USBD2_LP_IRQHandler ; USBD2 Low Priority +; +External Interrupts +DCD WWDT_IRQHandler ; +Window Watchdog +DCD PVD_IRQHandler ; +PVD through EINT Line detect +DCD TAMPER_IRQHandler ; +Tamper +DCD RTC_IRQHandler ; +RTC +DCD FLASH_IRQHandler ; +Flash +DCD RCM_IRQHandler ; +RCM +DCD EINT0_IRQHandler ; +EINT Line 0 +DCD EINT1_IRQHandler ; +EINT Line 1 +DCD EINT2_IRQHandler ; +EINT Line 2 +DCD EINT3_IRQHandler ; +EINT Line 3 +DCD EINT4_IRQHandler ; +EINT Line 4 +DCD DMA1_Channel1_IRQHandler ; +DMA1 Channel 1 +DCD DMA1_Channel2_IRQHandler ; +DMA1 Channel 2 +DCD DMA1_Channel3_IRQHandler ; +DMA1 Channel 3 +DCD DMA1_Channel4_IRQHandler ; +DMA1 Channel 4 +DCD DMA1_Channel5_IRQHandler ; +DMA1 Channel 5 +DCD DMA1_Channel6_IRQHandler ; +DMA1 Channel 6 +DCD DMA1_Channel7_IRQHandler ; +DMA1 Channel 7 +DCD ADC1_2_IRQHandler ; +ADC1_2 +DCD USBD1_HP_CAN1_TX_IRQHandler ; +USBD1 High Priority or CAN1 TX +DCD USBD1_LP_CAN1_RX0_IRQHandler ; +USBD1 Low Priority or CAN1 RX0 +DCD CAN1_RX1_IRQHandler ; +CAN1 RX1 +DCD CAN1_SCE_IRQHandler ; +CAN1 SCE +DCD EINT9_5_IRQHandler ; +EINT Line 9..5 +DCD TMR1_BRK_IRQHandler ; +TMR1 Break +DCD TMR1_UP_IRQHandler ; +TMR1 Update +DCD TMR1_TRG_COM_IRQHandler ; +TMR1 Trigger and Commutation +DCD TMR1_CC_IRQHandler ; +TMR1 Capture Compare +DCD TMR2_IRQHandler ; +TMR2 +DCD TMR3_IRQHandler ; +TMR3 +DCD TMR4_IRQHandler ; +TMR4 +DCD I2C1_EV_IRQHandler ; +I2C1 Event +DCD I2C1_ER_IRQHandler ; +I2C1 Error +DCD I2C2_EV_IRQHandler ; +I2C2 Event +DCD I2C2_ER_IRQHandler ; +I2C2 Error +DCD SPI1_IRQHandler ; +SPI1 +DCD SPI2_IRQHandler ; +SPI2 +DCD USART1_IRQHandler ; +USART1 +DCD USART2_IRQHandler ; +USART2 +DCD USART3_IRQHandler ; +USART3 +DCD EINT15_10_IRQHandler ; +EINT Line 15..10 +DCD RTCAlarm_IRQHandler ; +RTC Alarm through EINT Line +DCD USBDWakeUp_IRQHandler ; +USBD Wakeup from suspend +DCD FPU_IRQHandler ; +FPU +DCD QSPI_IRQHandler ; +QSPI +DCD USBD2_HP_IRQHandler ; +USBD2 High Priority +DCD USBD2_LP_IRQHandler ; +USBD2 Low Priority __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors - AREA |.text|, CODE, READONLY +AREA | .text |, CODE, READONLY -; Reset handler +; +Reset handler Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP +EXPORT Reset_Handler [WEAK] +IMPORT __main +IMPORT SystemInit +LDR R0, = SystemInit + BLX R0 + LDR R0, = __main + BX R0 + ENDP -; Dummy Exception Handlers (infinite loops which can be modified) + ; +Dummy Exception Handlers(infinite loops which can be modified) NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP +EXPORT NMI_Handler [WEAK] +B . +ENDP HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP +PROC +EXPORT HardFault_Handler [WEAK] +B . +ENDP MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP +PROC +EXPORT MemManage_Handler [WEAK] +B . +ENDP BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP +PROC +EXPORT BusFault_Handler [WEAK] +B . +ENDP UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP +PROC +EXPORT UsageFault_Handler [WEAK] +B . +ENDP SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP +EXPORT SVC_Handler [WEAK] +B . +ENDP DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP +PROC +EXPORT DebugMon_Handler [WEAK] +B . +ENDP PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP +EXPORT PendSV_Handler [WEAK] +B . +ENDP SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP +EXPORT SysTick_Handler [WEAK] +B . +ENDP Default_Handler PROC - EXPORT WWDT_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMPER_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT RCM_IRQHandler [WEAK] - EXPORT EINT0_IRQHandler [WEAK] - EXPORT EINT1_IRQHandler [WEAK] - EXPORT EINT2_IRQHandler [WEAK] - EXPORT EINT3_IRQHandler [WEAK] - EXPORT EINT4_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_IRQHandler [WEAK] - EXPORT DMA1_Channel3_IRQHandler [WEAK] - EXPORT DMA1_Channel4_IRQHandler [WEAK] - EXPORT DMA1_Channel5_IRQHandler [WEAK] - EXPORT DMA1_Channel6_IRQHandler [WEAK] - EXPORT DMA1_Channel7_IRQHandler [WEAK] - EXPORT ADC1_2_IRQHandler [WEAK] - EXPORT USBD1_HP_CAN1_TX_IRQHandler [WEAK] - EXPORT USBD1_LP_CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EINT9_5_IRQHandler [WEAK] - EXPORT TMR1_BRK_IRQHandler [WEAK] - EXPORT TMR1_UP_IRQHandler [WEAK] - EXPORT TMR1_TRG_COM_IRQHandler [WEAK] - EXPORT TMR1_CC_IRQHandler [WEAK] - EXPORT TMR2_IRQHandler [WEAK] - EXPORT TMR3_IRQHandler [WEAK] - EXPORT TMR4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EINT15_10_IRQHandler [WEAK] - EXPORT RTCAlarm_IRQHandler [WEAK] - EXPORT USBDWakeUp_IRQHandler [WEAK] - EXPORT FPU_IRQHandler [WEAK] - EXPORT QSPI_IRQHandler [WEAK] - EXPORT USBD2_HP_IRQHandler [WEAK] - EXPORT USBD2_LP_IRQHandler [WEAK] +EXPORT WWDT_IRQHandler [WEAK] +EXPORT PVD_IRQHandler [WEAK] +EXPORT TAMPER_IRQHandler [WEAK] +EXPORT RTC_IRQHandler [WEAK] +EXPORT FLASH_IRQHandler [WEAK] +EXPORT RCM_IRQHandler [WEAK] +EXPORT EINT0_IRQHandler [WEAK] +EXPORT EINT1_IRQHandler [WEAK] +EXPORT EINT2_IRQHandler [WEAK] +EXPORT EINT3_IRQHandler [WEAK] +EXPORT EINT4_IRQHandler [WEAK] +EXPORT DMA1_Channel1_IRQHandler [WEAK] +EXPORT DMA1_Channel2_IRQHandler [WEAK] +EXPORT DMA1_Channel3_IRQHandler [WEAK] +EXPORT DMA1_Channel4_IRQHandler [WEAK] +EXPORT DMA1_Channel5_IRQHandler [WEAK] +EXPORT DMA1_Channel6_IRQHandler [WEAK] +EXPORT DMA1_Channel7_IRQHandler [WEAK] +EXPORT ADC1_2_IRQHandler [WEAK] +EXPORT USBD1_HP_CAN1_TX_IRQHandler [WEAK] +EXPORT USBD1_LP_CAN1_RX0_IRQHandler [WEAK] +EXPORT CAN1_RX1_IRQHandler [WEAK] +EXPORT CAN1_SCE_IRQHandler [WEAK] +EXPORT EINT9_5_IRQHandler [WEAK] +EXPORT TMR1_BRK_IRQHandler [WEAK] +EXPORT TMR1_UP_IRQHandler [WEAK] +EXPORT TMR1_TRG_COM_IRQHandler [WEAK] +EXPORT TMR1_CC_IRQHandler [WEAK] +EXPORT TMR2_IRQHandler [WEAK] +EXPORT TMR3_IRQHandler [WEAK] +EXPORT TMR4_IRQHandler [WEAK] +EXPORT I2C1_EV_IRQHandler [WEAK] +EXPORT I2C1_ER_IRQHandler [WEAK] +EXPORT I2C2_EV_IRQHandler [WEAK] +EXPORT I2C2_ER_IRQHandler [WEAK] +EXPORT SPI1_IRQHandler [WEAK] +EXPORT SPI2_IRQHandler [WEAK] +EXPORT USART1_IRQHandler [WEAK] +EXPORT USART2_IRQHandler [WEAK] +EXPORT USART3_IRQHandler [WEAK] +EXPORT EINT15_10_IRQHandler [WEAK] +EXPORT RTCAlarm_IRQHandler [WEAK] +EXPORT USBDWakeUp_IRQHandler [WEAK] +EXPORT FPU_IRQHandler [WEAK] +EXPORT QSPI_IRQHandler [WEAK] +EXPORT USBD2_HP_IRQHandler [WEAK] +EXPORT USBD2_LP_IRQHandler [WEAK] WWDT_IRQHandler PVD_IRQHandler TAMPER_IRQHandler RTC_IRQHandler -FMC_IRQHandler +FLASH_IRQHandler RCM_IRQHandler EINT0_IRQHandler EINT1_IRQHandler @@ -264,38 +351,44 @@ FPU_IRQHandler QSPI_IRQHandler USBD2_HP_IRQHandler USBD2_LP_IRQHandler - B . +B . - ENDP +ENDP - ALIGN +ALIGN -;******************************************************************************* -; User Stack and Heap initialization -;******************************************************************************* - IF :DEF:__MICROLIB +; +******************************************************************************* +; +User Stack and Heap initialization +; +******************************************************************************* +IF : +DEF: +__MICROLIB - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit +EXPORT __initial_sp +EXPORT __heap_base +EXPORT __heap_limit - ELSE +ELSE - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap +IMPORT __use_two_region_memory +EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem - LDR R1, = (Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR +LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR - ALIGN + ALIGN - ENDIF + ENDIF - END + END -;*******************************END OF FILE************************************ + ; +*******************************END OF FILE ************************************ diff --git a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/startup_apm32f10x_hd.s b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/startup_apm32f10x_hd.s new file mode 100644 index 0000000000..ad9c663676 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/startup_apm32f10x_hd.s @@ -0,0 +1,281 @@ +;/*! +; * @file startup_apm32f10x_hd.s +; * +; * @brief CMSIS Cortex-M3 based Core Device Startup File for Device startup_apm32f10x_hd +; * +; * @version V1.0.0 +; * +; * @date 2022-01-05 +; * +; * @attention +; * +; * Copyright (C) 2020-2022 Geehy Semiconductor +; * +; * You may not use this file except in compliance with the +; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). +; * +; * The program is only for reference, which is distributed in the hope +; * that it will be usefull and instructional for customers to develop +; * their software. Unless required by applicable law or agreed to in +; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT +; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. +; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions +; * and limitations under the License. +; */ + +.syntax unified +.cpu cortex - m3 +.fpu softvfp +.thumb + +.global g_pfnVectors +.global Default_Handler + +.section .isr_vector, "a", % progbits +.type g_pfnVectors, % object + +g_pfnVectors: +.word _estack // Top of Stack +.word Reset_Handler // Reset Handler +.word NMI_Handler // NMI Handler +.word HardFault_Handler // Hard Fault Handler +.word MemManage_Handler // MPU Fault Handler +.word BusFault_Handler // Bus Fault Handler +.word UsageFault_Handler // Usage Fault Handler +.word 0 // Reserved +.word 0 // Reserved +.word 0 // Reserved +.word 0 // Reserved +.word SVC_Handler // SVCall Handler +.word DebugMon_Handler // Debug Monitor Handler +.word 0 // Reserved +.word PendSV_Handler // PendSV Handler +.word SysTick_Handler // SysTick Handler + +// external interrupts handler +.word WWDT_IRQHandler // Window Watchdog +.word PVD_IRQHandler // PVD through EINT Line detect +.word TAMPER_IRQHandler // Tamper +.word RTC_IRQHandler // RTC +.word FLASH_IRQHandler // Flash +.word RCM_IRQHandler // RCM +.word EINT0_IRQHandler // EINT Line 0 +.word EINT1_IRQHandler // EINT Line 1 +.word EINT2_IRQHandler // EINT Line 2 +.word EINT3_IRQHandler // EINT Line 3 +.word EINT4_IRQHandler // EINT Line 4 +.word DMA1_Channel1_IRQHandler // DMA1 Channel 1 +.word DMA1_Channel2_IRQHandler // DMA1 Channel 2 +.word DMA1_Channel3_IRQHandler // DMA1 Channel 3 +.word DMA1_Channel4_IRQHandler // DMA1 Channel 4 +.word DMA1_Channel5_IRQHandler // DMA1 Channel 5 +.word DMA1_Channel6_IRQHandler // DMA1 Channel 6 +.word DMA1_Channel7_IRQHandler // DMA1 Channel 7 +.word ADC1_2_IRQHandler // ADC1 & ADC2 +.word USBD1_HP_CAN1_TX_IRQHandler // USBD1 High Priority or CAN1 TX +.word USBD1_LP_CAN1_RX0_IRQHandler // USBD1 Low Priority or CAN1 RX0 +.word CAN1_RX1_IRQHandler // CAN1 RX1 +.word CAN1_SCE_IRQHandler // CAN1 SCE +.word EINT9_5_IRQHandler // EINT Line 9..5 +.word TMR1_BRK_IRQHandler // TMR1 Break +.word TMR1_UP_IRQHandler // TMR1 Update +.word TMR1_TRG_COM_IRQHandler // TMR1 Trigger and Commutation +.word TMR1_CC_IRQHandler // TMR1 Capture Compare +.word TMR2_IRQHandler // TMR2 +.word TMR3_IRQHandler // TMR3 +.word TMR4_IRQHandler // TMR4 +.word I2C1_EV_IRQHandler // I2C1 Event +.word I2C1_ER_IRQHandler // I2C1 Error +.word I2C2_EV_IRQHandler // I2C2 Event +.word I2C2_ER_IRQHandler // I2C2 Error +.word SPI1_IRQHandler // SPI1 +.word SPI2_IRQHandler // SPI2 +.word USART1_IRQHandler // USART1 +.word USART2_IRQHandler // USART2 +.word USART3_IRQHandler // USART3 +.word EINT15_10_IRQHandler // EINT Line 15..10 +.word RTCAlarm_IRQHandler // RTC Alarm through EINT Line +.word USBDWakeUp_IRQHandler // USBD Wakeup from suspend +.word TMR8_BRK_IRQHandler // TMR8 Break +.word TMR8_UP_IRQHandler // TMR8 Update +.word TMR8_TRG_COM_IRQHandler // TMR8 Trigger and Commutation +.word TMR8_CC_IRQHandler // TMR8 Capture Compare +.word ADC3_IRQHandler // ADC3 +.word EMMC_IRQHandler // EMMC +.word SDIO_IRQHandler // SDIO +.word TMR5_IRQHandler // TMR5 +.word SPI3_IRQHandler // SPI3 +.word UART4_IRQHandler // UART4 +.word UART5_IRQHandler // UART5 +.word TMR6_IRQHandler // TMR6 +.word TMR7_IRQHandler // TMR7 +.word DMA2_Channel1_IRQHandler // DMA2 Channel1 +.word DMA2_Channel2_IRQHandler // DMA2 Channel2 +.word DMA2_Channel3_IRQHandler // DMA2 Channel3 +.word DMA2_Channel4_5_IRQHandler // DMA2 Channel4 & Channel5 +.word 0 // Reserved +.word USBD2_HP_CAN2_TX_IRQHandler // USBD2 High Priority or CAN2 TX +.word USBD2_LP_CAN2_RX0_IRQHandler // USBD2 Low Priority or CAN2 RX0 +.word CAN2_RX1_IRQHandler // CAN2 RX1 +.word CAN2_SCE_IRQHandler // CAN2 SCE + +.size g_pfnVectors, . - g_pfnVectors + +.section .text.Reset_Handler +.weak Reset_Handler +.type Reset_Handler, % function +Reset_Handler: +ldr r1, = _sidata + ldr r2, = _sdata + ldr r3, = _edata + + subs r3, r2 + ble fill_bss_start + + loop_copy_data: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt loop_copy_data + + fill_bss_start: + ldr r1, = __bss_start + ldr r2, = __bss_end + movs r0, 0 + subs r2, r1 + ble startup_enter + + loop_fill_bss: + subs r2, #4 + str r0, [r1, r2] + bgt loop_fill_bss + + startup_enter: + bl SystemInit + bl entry + + /* Exception Handlers */ + .weak NMI_Handler + .type NMI_Handler, % function + NMI_Handler: + b . + .size NMI_Handler, . - NMI_Handler + + .weak MemManage_Handler + .type MemManage_Handler, % function + MemManage_Handler: + b . + .size MemManage_Handler, . - MemManage_Handler + + .weak BusFault_Handler + .type BusFault_Handler, % function + BusFault_Handler: + b . + .size BusFault_Handler, . - BusFault_Handler + + .weak UsageFault_Handler + .type UsageFault_Handler, % function + UsageFault_Handler: + b . + .size UsageFault_Handler, . - UsageFault_Handler + + .weak SVC_Handler + .type SVC_Handler, % function + SVC_Handler: + b . + .size SVC_Handler, . - SVC_Handler + + .weak DebugMon_Handler + .type DebugMon_Handler, % function + DebugMon_Handler: + b . + .size DebugMon_Handler, . - DebugMon_Handler + + .weak PendSV_Handler + .type PendSV_Handler, % function + PendSV_Handler: + b . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, % function + SysTick_Handler: + b . + .size SysTick_Handler, . - SysTick_Handler + + /* IQR Handler */ + .section .text.Default_Handler, "ax", % progbits + .type Default_Handler, % function + Default_Handler: + b . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ WWDT_IRQHandler + IRQ PVD_IRQHandler + IRQ TAMPER_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCM_IRQHandler + IRQ EINT0_IRQHandler + IRQ EINT1_IRQHandler + IRQ EINT2_IRQHandler + IRQ EINT3_IRQHandler + IRQ EINT4_IRQHandler + IRQ DMA1_Channel1_IRQHandler + IRQ DMA1_Channel2_IRQHandler + IRQ DMA1_Channel3_IRQHandler + IRQ DMA1_Channel4_IRQHandler + IRQ DMA1_Channel5_IRQHandler + IRQ DMA1_Channel6_IRQHandler + IRQ DMA1_Channel7_IRQHandler + IRQ ADC1_2_IRQHandler + IRQ USBD1_HP_CAN1_TX_IRQHandler + IRQ USBD1_LP_CAN1_RX0_IRQHandler + IRQ CAN1_RX1_IRQHandler + IRQ CAN1_SCE_IRQHandler + IRQ EINT9_5_IRQHandler + IRQ TMR1_BRK_IRQHandler + IRQ TMR1_UP_IRQHandler + IRQ TMR1_TRG_COM_IRQHandler + IRQ TMR1_CC_IRQHandler + IRQ TMR2_IRQHandler + IRQ TMR3_IRQHandler + IRQ TMR4_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EINT15_10_IRQHandler + IRQ RTCAlarm_IRQHandler + IRQ USBDWakeUp_IRQHandler + IRQ TMR8_BRK_IRQHandler + IRQ TMR8_UP_IRQHandler + IRQ TMR8_TRG_COM_IRQHandler + IRQ TMR8_CC_IRQHandler + IRQ ADC3_IRQHandler + IRQ EMMC_IRQHandler + IRQ SDIO_IRQHandler + IRQ TMR5_IRQHandler + IRQ SPI3_IRQHandler + IRQ UART4_IRQHandler + IRQ UART5_IRQHandler + IRQ TMR6_IRQHandler + IRQ TMR7_IRQHandler + IRQ DMA2_Channel1_IRQHandler + IRQ DMA2_Channel2_IRQHandler + IRQ DMA2_Channel3_IRQHandler + IRQ DMA2_Channel4_5_IRQHandler + IRQ USBD2_HP_CAN2_TX_IRQHandler + IRQ USBD2_LP_CAN2_RX0_IRQHandler + IRQ CAN2_RX1_IRQHandler + IRQ CAN2_SCE_IRQHandler diff --git a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/startup_apm32f10x_md.s b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/startup_apm32f10x_md.s new file mode 100644 index 0000000000..8ff2dfc793 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/startup_apm32f10x_md.s @@ -0,0 +1,246 @@ +;/*! +; * @file startup_apm32f10x_hd.s +; * +; * @brief CMSIS Cortex-M3 based Core Device Startup File for Device startup_apm32f10x_hd +; * +; * @version V1.0.0 +; * +; * @date 2022-01-05 +; * +; * @attention +; * +; * Copyright (C) 2020-2022 Geehy Semiconductor +; * +; * You may not use this file except in compliance with the +; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). +; * +; * The program is only for reference, which is distributed in the hope +; * that it will be usefull and instructional for customers to develop +; * their software. Unless required by applicable law or agreed to in +; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT +; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. +; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions +; * and limitations under the License. +; */ + +.syntax unified +.cpu cortex - m3 +.fpu softvfp +.thumb + +.global g_pfnVectors +.global Default_Handler + +.section .isr_vector, "a", % progbits +.type g_pfnVectors, % object + +g_pfnVectors: +.word _estack // Top of Stack +.word Reset_Handler // Reset Handler +.word NMI_Handler // NMI Handler +.word HardFault_Handler // Hard Fault Handler +.word MemManage_Handler // MPU Fault Handler +.word BusFault_Handler // Bus Fault Handler +.word UsageFault_Handler // Usage Fault Handler +.word 0 // Reserved +.word 0 // Reserved +.word 0 // Reserved +.word 0 // Reserved +.word SVC_Handler // SVCall Handler +.word DebugMon_Handler // Debug Monitor Handler +.word 0 // Reserved +.word PendSV_Handler // PendSV Handler +.word SysTick_Handler // SysTick Handler + +// external interrupts handler +.word WWDT_IRQHandler // Window Watchdog +.word PVD_IRQHandler // PVD through EINT Line detect +.word TAMPER_IRQHandler // Tamper +.word RTC_IRQHandler // RTC +.word FLASH_IRQHandler // Flash +.word RCM_IRQHandler // RCM +.word EINT0_IRQHandler // EINT Line 0 +.word EINT1_IRQHandler // EINT Line 1 +.word EINT2_IRQHandler // EINT Line 2 +.word EINT3_IRQHandler // EINT Line 3 +.word EINT4_IRQHandler // EINT Line 4 +.word DMA1_Channel1_IRQHandler // DMA1 Channel 1 +.word DMA1_Channel2_IRQHandler // DMA1 Channel 2 +.word DMA1_Channel3_IRQHandler // DMA1 Channel 3 +.word DMA1_Channel4_IRQHandler // DMA1 Channel 4 +.word DMA1_Channel5_IRQHandler // DMA1 Channel 5 +.word DMA1_Channel6_IRQHandler // DMA1 Channel 6 +.word DMA1_Channel7_IRQHandler // DMA1 Channel 7 +.word ADC1_2_IRQHandler // ADC1_2 +.word USBD1_HP_CAN1_TX_IRQHandler // USBD1 High Priority or CAN1 TX +.word USBD1_LP_CAN1_RX0_IRQHandler // USBD1 Low Priority or CAN1 RX0 +.word CAN1_RX1_IRQHandler // CAN1 RX1 +.word CAN1_SCE_IRQHandler // CAN1 SCE +.word EINT9_5_IRQHandler // EINT Line 9..5 +.word TMR1_BRK_IRQHandler // TMR1 Break +.word TMR1_UP_IRQHandler // TMR1 Update +.word TMR1_TRG_COM_IRQHandler // TMR1 Trigger and Commutation +.word TMR1_CC_IRQHandler // TMR1 Capture Compare +.word TMR2_IRQHandler // TMR2 +.word TMR3_IRQHandler // TMR3 +.word TMR4_IRQHandler // TMR4 +.word I2C1_EV_IRQHandler // I2C1 Event +.word I2C1_ER_IRQHandler // I2C1 Error +.word I2C2_EV_IRQHandler // I2C2 Event +.word I2C2_ER_IRQHandler // I2C2 Error +.word SPI1_IRQHandler // SPI1 +.word SPI2_IRQHandler // SPI2 +.word USART1_IRQHandler // USART1 +.word USART2_IRQHandler // USART2 +.word USART3_IRQHandler // USART3 +.word EINT15_10_IRQHandler // EINT Line 15..10 +.word RTCAlarm_IRQHandler // RTC Alarm through EINT Line +.word USBDWakeUp_IRQHandler // USBD Wakeup from suspend +.word FPU_IRQHandler // FPU +.word QSPI_IRQHandler // QSPI +.word USBD2_HP_IRQHandler // USBD2 High Priority +.word USBD2_LP_IRQHandler // USBD2 Low Priority + +.size g_pfnVectors, . - g_pfnVectors + +.section .text.Reset_Handler +.weak Reset_Handler +.type Reset_Handler, % function +Reset_Handler: +ldr r1, = _sidata + ldr r2, = _sdata + ldr r3, = _edata + + subs r3, r2 + ble fill_bss_start + + loop_copy_data: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt loop_copy_data + + fill_bss_start: + ldr r1, = __bss_start + ldr r2, = __bss_end + movs r0, 0 + subs r2, r1 + ble startup_enter + + loop_fill_bss: + subs r2, #4 + str r0, [r1, r2] + bgt loop_fill_bss + + startup_enter: + bl SystemInit + bl entry + + /* Exception Handlers */ + .weak NMI_Handler + .type NMI_Handler, % function + NMI_Handler: + b . + .size NMI_Handler, . - NMI_Handler + + .weak MemManage_Handler + .type MemManage_Handler, % function + MemManage_Handler: + b . + .size MemManage_Handler, . - MemManage_Handler + + .weak BusFault_Handler + .type BusFault_Handler, % function + BusFault_Handler: + b . + .size BusFault_Handler, . - BusFault_Handler + + .weak UsageFault_Handler + .type UsageFault_Handler, % function + UsageFault_Handler: + b . + .size UsageFault_Handler, . - UsageFault_Handler + + .weak SVC_Handler + .type SVC_Handler, % function + SVC_Handler: + b . + .size SVC_Handler, . - SVC_Handler + + .weak DebugMon_Handler + .type DebugMon_Handler, % function + DebugMon_Handler: + b . + .size DebugMon_Handler, . - DebugMon_Handler + + .weak PendSV_Handler + .type PendSV_Handler, % function + PendSV_Handler: + b . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, % function + SysTick_Handler: + b . + .size SysTick_Handler, . - SysTick_Handler + + /* IQR Handler */ + .section .text.Default_Handler, "ax", % progbits + .type Default_Handler, % function + Default_Handler: + b . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ WWDT_IRQHandler + IRQ PVD_IRQHandler + IRQ TAMPER_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ RCM_IRQHandler + IRQ EINT0_IRQHandler + IRQ EINT1_IRQHandler + IRQ EINT2_IRQHandler + IRQ EINT3_IRQHandler + IRQ EINT4_IRQHandler + IRQ DMA1_Channel1_IRQHandler + IRQ DMA1_Channel2_IRQHandler + IRQ DMA1_Channel3_IRQHandler + IRQ DMA1_Channel4_IRQHandler + IRQ DMA1_Channel5_IRQHandler + IRQ DMA1_Channel6_IRQHandler + IRQ DMA1_Channel7_IRQHandler + IRQ ADC1_2_IRQHandler + IRQ USBD1_HP_CAN1_TX_IRQHandler + IRQ USBD1_LP_CAN1_RX0_IRQHandler + IRQ CAN1_RX1_IRQHandler + IRQ CAN1_SCE_IRQHandler + IRQ EINT9_5_IRQHandler + IRQ TMR1_BRK_IRQHandler + IRQ TMR1_UP_IRQHandler + IRQ TMR1_TRG_COM_IRQHandler + IRQ TMR1_CC_IRQHandler + IRQ TMR2_IRQHandler + IRQ TMR3_IRQHandler + IRQ TMR4_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ I2C2_EV_IRQHandler + IRQ I2C2_ER_IRQHandler + IRQ SPI1_IRQHandler + IRQ SPI2_IRQHandler + IRQ USART1_IRQHandler + IRQ USART2_IRQHandler + IRQ USART3_IRQHandler + IRQ EINT15_10_IRQHandler + IRQ RTCAlarm_IRQHandler + IRQ USBDWakeUp_IRQHandler + IRQ FPU_IRQHandler + IRQ QSPI_IRQHandler + IRQ USBD2_HP_IRQHandler + IRQ USBD2_LP_IRQHandler diff --git a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/iar/startup_apm32f10x_hd.s b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/iar/startup_apm32f10x_hd.s new file mode 100644 index 0000000000..672eab8977 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/iar/startup_apm32f10x_hd.s @@ -0,0 +1,813 @@ +;/*! +; * @file startup_apm32f10x_hd.s +; * +; * @brief CMSIS Cortex-M3 based Core Device Startup File for Device APM32F103 +; * +; * @version V1.0.0 +; * +; * @date 2022-01-05 +; * +; * @attention +; * +; * Copyright (C) 2020-2022 Geehy Semiconductor +; * +; * You may not use this file except in compliance with the +; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). +; * +; * The program is only for reference, which is distributed in the hope +; * that it will be usefull and instructional for customers to develop +; * their software. Unless required by applicable law or agreed to in +; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT +; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. +; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions +; * and limitations under the License. +; */ + +MODULE ? cstartup + +;; +Forward declaration of sections. +SECTION CSTACK: +DATA: +NOROOT(3) + +SECTION .intvec: +CODE: +NOROOT(2) + + +EXTERN __iar_program_start +EXTERN SystemInit +PUBLIC __vector_table + +DATA + +__vector_table +DCD sfe(CSTACK) +DCD Reset_Handler ; +Reset Handler +DCD NMI_Handler ; +NMI Handler +DCD HardFault_Handler ; +Hard Fault Handler +DCD MemManage_Handler ; +MPU Fault Handler +DCD BusFault_Handler ; +Bus Fault Handler +DCD UsageFault_Handler ; +Usage Fault Handler +DCD 0 ; +Reserved +DCD 0 ; +Reserved +DCD 0 ; +Reserved +DCD 0 ; +Reserved +DCD SVC_Handler ; +SVCall Handler +DCD DebugMon_Handler ; +Debug Monitor Handler +DCD 0 ; +Reserved +DCD PendSV_Handler ; +PendSV Handler +DCD SysTick_Handler ; +SysTick Handler + +; +External Interrupts +DCD WWDT_IRQHandler ; +Window Watchdog +DCD PVD_IRQHandler ; +PVD through EINT Line detect +DCD TAMPER_IRQHandler ; +Tamper +DCD RTC_IRQHandler ; +RTC +DCD FLASH_IRQHandler ; +Flash +DCD RCM_IRQHandler ; +RCM +DCD EINT0_IRQHandler ; +EINT Line 0 +DCD EINT1_IRQHandler ; +EINT Line 1 +DCD EINT2_IRQHandler ; +EINT Line 2 +DCD EINT3_IRQHandler ; +EINT Line 3 +DCD EINT4_IRQHandler ; +EINT Line 4 +DCD DMA1_Channel1_IRQHandler ; +DMA1 Channel 1 +DCD DMA1_Channel2_IRQHandler ; +DMA1 Channel 2 +DCD DMA1_Channel3_IRQHandler ; +DMA1 Channel 3 +DCD DMA1_Channel4_IRQHandler ; +DMA1 Channel 4 +DCD DMA1_Channel5_IRQHandler ; +DMA1 Channel 5 +DCD DMA1_Channel6_IRQHandler ; +DMA1 Channel 6 +DCD DMA1_Channel7_IRQHandler ; +DMA1 Channel 7 +DCD ADC1_2_IRQHandler ; +ADC1 &ADC2 +DCD USBD1_HP_CAN1_TX_IRQHandler ; +USBD1 High Priority or CAN1 TX +DCD USBD1_LP_CAN1_RX0_IRQHandler ; +USBD1 Low Priority or CAN1 RX0 +DCD CAN1_RX1_IRQHandler ; +CAN1 RX1 +DCD CAN1_SCE_IRQHandler ; +CAN1 SCE +DCD EINT9_5_IRQHandler ; +EINT Line 9..5 +DCD TMR1_BRK_IRQHandler ; +TMR1 Break +DCD TMR1_UP_IRQHandler ; +TMR1 Update +DCD TMR1_TRG_COM_IRQHandler ; +TMR1 Trigger and Commutation +DCD TMR1_CC_IRQHandler ; +TMR1 Capture Compare +DCD TMR2_IRQHandler ; +TMR2 +DCD TMR3_IRQHandler ; +TMR3 +DCD TMR4_IRQHandler ; +TMR4 +DCD I2C1_EV_IRQHandler ; +I2C1 Event +DCD I2C1_ER_IRQHandler ; +I2C1 Error +DCD I2C2_EV_IRQHandler ; +I2C2 Event +DCD I2C2_ER_IRQHandler ; +I2C2 Error +DCD SPI1_IRQHandler ; +SPI1 +DCD SPI2_IRQHandler ; +SPI2 +DCD USART1_IRQHandler ; +USART1 +DCD USART2_IRQHandler ; +USART2 +DCD USART3_IRQHandler ; +USART3 +DCD EINT15_10_IRQHandler ; +EINT Line 15..10 +DCD RTCAlarm_IRQHandler ; +RTC Alarm through EINT Line +DCD USBDWakeUp_IRQHandler ; +USBD Wakeup from suspend +DCD TMR8_BRK_IRQHandler ; +TMR8 Break +DCD TMR8_UP_IRQHandler ; +TMR8 Update +DCD TMR8_TRG_COM_IRQHandler ; +TMR8 Trigger and Commutation +DCD TMR8_CC_IRQHandler ; +TMR8 Capture Compare +DCD ADC3_IRQHandler ; +ADC3 +DCD EMMC_IRQHandler ; +EMMC +DCD SDIO_IRQHandler ; +SDIO +DCD TMR5_IRQHandler ; +TMR5 +DCD SPI3_IRQHandler ; +SPI3 +DCD UART4_IRQHandler ; +UART4 +DCD UART5_IRQHandler ; +UART5 +DCD TMR6_IRQHandler ; +TMR6 +DCD TMR7_IRQHandler ; +TMR7 +DCD DMA2_Channel1_IRQHandler ; +DMA2 Channel1 +DCD DMA2_Channel2_IRQHandler ; +DMA2 Channel2 +DCD DMA2_Channel3_IRQHandler ; +DMA2 Channel3 +DCD DMA2_Channel4_5_IRQHandler ; +DMA2 Channel4 &Channel5 +DCD 0 ; +Reserved +DCD USBD2_HP_CAN2_TX_IRQHandler ; +USBD2 High Priority or CAN2 TX +DCD USBD2_LP_CAN2_RX0_IRQHandler ; +USBD2 Low Priority or CAN2 RX0 +DCD CAN2_RX1_IRQHandler ; +CAN2 RX1 +DCD CAN2_SCE_IRQHandler ; +CAN2 SCE +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; +Default interrupt handlers. +;; +THUMB + +PUBWEAK Reset_Handler +SECTION .text: +CODE: +REORDER: +NOROOT(2) +Reset_Handler +LDR R0, = SystemInit + BLX R0 + LDR R0, = __iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDT_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + WWDT_IRQHandler + B WWDT_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMPER_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + TAMPER_IRQHandler + B TAMPER_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCM_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + RCM_IRQHandler + B RCM_IRQHandler + + PUBWEAK EINT0_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + EINT0_IRQHandler + B EINT0_IRQHandler + + PUBWEAK EINT1_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + EINT1_IRQHandler + B EINT1_IRQHandler + + PUBWEAK EINT2_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + EINT2_IRQHandler + B EINT2_IRQHandler + + PUBWEAK EINT3_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + EINT3_IRQHandler + B EINT3_IRQHandler + + PUBWEAK EINT4_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + EINT4_IRQHandler + B EINT4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_2_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + ADC1_2_IRQHandler + B ADC1_2_IRQHandler + + PUBWEAK USBD1_HP_CAN1_TX_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + USBD1_HP_CAN1_TX_IRQHandler + B USBD1_HP_CAN1_TX_IRQHandler + + PUBWEAK USBD1_LP_CAN1_RX0_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + USBD1_LP_CAN1_RX0_IRQHandler + B USBD1_LP_CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EINT9_5_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + EINT9_5_IRQHandler + B EINT9_5_IRQHandler + + PUBWEAK TMR1_BRK_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + TMR1_BRK_IRQHandler + B TMR1_BRK_IRQHandler + + PUBWEAK TMR1_UP_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + TMR1_UP_IRQHandler + B TMR1_UP_IRQHandler + + PUBWEAK TMR1_TRG_COM_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + TMR1_TRG_COM_IRQHandler + B TMR1_TRG_COM_IRQHandler + + PUBWEAK TMR1_CC_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + TMR1_CC_IRQHandler + B TMR1_CC_IRQHandler + + PUBWEAK TMR2_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + TMR2_IRQHandler + B TMR2_IRQHandler + + PUBWEAK TMR3_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + TMR3_IRQHandler + B TMR3_IRQHandler + + PUBWEAK TMR4_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + TMR4_IRQHandler + B TMR4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EINT15_10_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + EINT15_10_IRQHandler + B EINT15_10_IRQHandler + + PUBWEAK RTCAlarm_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + RTCAlarm_IRQHandler + B RTCAlarm_IRQHandler + + PUBWEAK USBDWakeUp_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + USBDWakeUp_IRQHandler + B USBDWakeUp_IRQHandler + + PUBWEAK TMR8_BRK_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + TMR8_BRK_IRQHandler + B TMR8_BRK_IRQHandler + + PUBWEAK TMR8_UP_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + TMR8_UP_IRQHandler + B TMR8_UP_IRQHandler + + PUBWEAK TMR8_TRG_COM_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + TMR8_TRG_COM_IRQHandler + B TMR8_TRG_COM_IRQHandler + + PUBWEAK TMR8_CC_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + TMR8_CC_IRQHandler + B TMR8_CC_IRQHandler + + PUBWEAK ADC3_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + ADC3_IRQHandler + B ADC3_IRQHandler + + PUBWEAK EMMC_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + EMMC_IRQHandler + B EMMC_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TMR5_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + TMR5_IRQHandler + B TMR5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TMR6_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + TMR6_IRQHandler + B TMR6_IRQHandler + + PUBWEAK TMR7_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + TMR7_IRQHandler + B TMR7_IRQHandler + + PUBWEAK DMA2_Channel1_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + DMA2_Channel1_IRQHandler + B DMA2_Channel1_IRQHandler + + PUBWEAK DMA2_Channel2_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + DMA2_Channel2_IRQHandler + B DMA2_Channel2_IRQHandler + + PUBWEAK DMA2_Channel3_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + DMA2_Channel3_IRQHandler + B DMA2_Channel3_IRQHandler + + PUBWEAK DMA2_Channel4_5_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + DMA2_Channel4_5_IRQHandler + B DMA2_Channel4_5_IRQHandler + + PUBWEAK USBD2_HP_CAN2_TX_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + USBD2_HP_CAN2_TX_IRQHandler + B USBD2_HP_CAN2_TX_IRQHandler + + PUBWEAK USBD2_LP_CAN2_RX0_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + USBD2_LP_CAN2_RX0_IRQHandler + B USBD2_LP_CAN2_RX0_IRQHandler + + PUBWEAK CAN2_RX1_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + CAN2_RX1_IRQHandler + B CAN2_RX1_IRQHandler + + PUBWEAK CAN2_SCE_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + CAN2_SCE_IRQHandler + B CAN2_SCE_IRQHandler + + END + diff --git a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/iar/startup_apm32f10x_md.s b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/iar/startup_apm32f10x_md.s new file mode 100644 index 0000000000..dee619770b --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/iar/startup_apm32f10x_md.s @@ -0,0 +1,644 @@ +;/*! +; * @file startup_apm32f10x_hd.s +; * +; * @brief CMSIS Cortex-M3 based Core Device Startup File for Device APM32F103 +; * +; * @version V1.0.0 +; * +; * @date 2022-01-05 +; * +; * @attention +; * +; * Copyright (C) 2020-2022 Geehy Semiconductor +; * +; * You may not use this file except in compliance with the +; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). +; * +; * The program is only for reference, which is distributed in the hope +; * that it will be usefull and instructional for customers to develop +; * their software. Unless required by applicable law or agreed to in +; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT +; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. +; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions +; * and limitations under the License. +; */ + +MODULE ? cstartup + +;; +Forward declaration of sections. +SECTION CSTACK: +DATA: +NOROOT(3) + +SECTION .intvec: +CODE: +NOROOT(2) + + +EXTERN __iar_program_start +EXTERN SystemInit +PUBLIC __vector_table + +DATA + +__vector_table +DCD sfe(CSTACK) +DCD Reset_Handler ; +Reset Handler +DCD NMI_Handler ; +NMI Handler +DCD HardFault_Handler ; +Hard Fault Handler +DCD MemManage_Handler ; +MPU Fault Handler +DCD BusFault_Handler ; +Bus Fault Handler +DCD UsageFault_Handler ; +Usage Fault Handler +DCD 0 ; +Reserved +DCD 0 ; +Reserved +DCD 0 ; +Reserved +DCD 0 ; +Reserved +DCD SVC_Handler ; +SVCall Handler +DCD DebugMon_Handler ; +Debug Monitor Handler +DCD 0 ; +Reserved +DCD PendSV_Handler ; +PendSV Handler +DCD SysTick_Handler ; +SysTick Handler + +; +External Interrupts +DCD WWDT_IRQHandler ; +Window Watchdog +DCD PVD_IRQHandler ; +PVD through EINT Line detect +DCD TAMPER_IRQHandler ; +Tamper +DCD RTC_IRQHandler ; +RTC +DCD FLASH_IRQHandler ; +Flash +DCD RCM_IRQHandler ; +RCM +DCD EINT0_IRQHandler ; +EINT Line 0 +DCD EINT1_IRQHandler ; +EINT Line 1 +DCD EINT2_IRQHandler ; +EINT Line 2 +DCD EINT3_IRQHandler ; +EINT Line 3 +DCD EINT4_IRQHandler ; +EINT Line 4 +DCD DMA1_Channel1_IRQHandler ; +DMA1 Channel 1 +DCD DMA1_Channel2_IRQHandler ; +DMA1 Channel 2 +DCD DMA1_Channel3_IRQHandler ; +DMA1 Channel 3 +DCD DMA1_Channel4_IRQHandler ; +DMA1 Channel 4 +DCD DMA1_Channel5_IRQHandler ; +DMA1 Channel 5 +DCD DMA1_Channel6_IRQHandler ; +DMA1 Channel 6 +DCD DMA1_Channel7_IRQHandler ; +DMA1 Channel 7 +DCD ADC1_2_IRQHandler ; +ADC1 &ADC2 +DCD USBD1_HP_CAN1_TX_IRQHandler ; +USBD1 High Priority or CAN1 TX +DCD USBD1_LP_CAN1_RX0_IRQHandler ; +USBD1 Low Priority or CAN1 RX0 +DCD CAN1_RX1_IRQHandler ; +CAN1 RX1 +DCD CAN1_SCE_IRQHandler ; +CAN1 SCE +DCD EINT9_5_IRQHandler ; +EINT Line 9..5 +DCD TMR1_BRK_IRQHandler ; +TMR1 Break +DCD TMR1_UP_IRQHandler ; +TMR1 Update +DCD TMR1_TRG_COM_IRQHandler ; +TMR1 Trigger and Commutation +DCD TMR1_CC_IRQHandler ; +TMR1 Capture Compare +DCD TMR2_IRQHandler ; +TMR2 +DCD TMR3_IRQHandler ; +TMR3 +DCD TMR4_IRQHandler ; +TMR4 +DCD I2C1_EV_IRQHandler ; +I2C1 Event +DCD I2C1_ER_IRQHandler ; +I2C1 Error +DCD I2C2_EV_IRQHandler ; +I2C2 Event +DCD I2C2_ER_IRQHandler ; +I2C2 Error +DCD SPI1_IRQHandler ; +SPI1 +DCD SPI2_IRQHandler ; +SPI2 +DCD USART1_IRQHandler ; +USART1 +DCD USART2_IRQHandler ; +USART2 +DCD USART3_IRQHandler ; +USART3 +DCD EINT15_10_IRQHandler ; +EINT Line 15..10 +DCD RTCAlarm_IRQHandler ; +RTC Alarm through EINT Line +DCD USBDWakeUp_IRQHandler ; +USBD Wakeup from suspend +DCD FPU_IRQHandler ; +FPU +DCD QSPI_IRQHandler ; +QSPI +DCD USBD2_HP_IRQHandler ; +USBD2 High Priority +DCD USBD2_LP_IRQHandler ; +USBD2 Low Priority +__Vectors_End + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; +Default interrupt handlers. +;; +THUMB + +PUBWEAK Reset_Handler +SECTION .text: +CODE: +REORDER: +NOROOT(2) +Reset_Handler +LDR R0, = SystemInit + BLX R0 + LDR R0, = __iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDT_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + WWDT_IRQHandler + B WWDT_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMPER_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + TAMPER_IRQHandler + B TAMPER_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCM_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + RCM_IRQHandler + B RCM_IRQHandler + + PUBWEAK EINT0_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + EINT0_IRQHandler + B EINT0_IRQHandler + + PUBWEAK EINT1_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + EINT1_IRQHandler + B EINT1_IRQHandler + + PUBWEAK EINT2_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + EINT2_IRQHandler + B EINT2_IRQHandler + + PUBWEAK EINT3_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + EINT3_IRQHandler + B EINT3_IRQHandler + + PUBWEAK EINT4_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + EINT4_IRQHandler + B EINT4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_2_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + ADC1_2_IRQHandler + B ADC1_2_IRQHandler + + PUBWEAK USBD1_HP_CAN1_TX_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + USBD1_HP_CAN1_TX_IRQHandler + B USBD1_HP_CAN1_TX_IRQHandler + + PUBWEAK USBD1_LP_CAN1_RX0_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + USBD1_LP_CAN1_RX0_IRQHandler + B USBD1_LP_CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EINT9_5_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + EINT9_5_IRQHandler + B EINT9_5_IRQHandler + + PUBWEAK TMR1_BRK_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + TMR1_BRK_IRQHandler + B TMR1_BRK_IRQHandler + + PUBWEAK TMR1_UP_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + TMR1_UP_IRQHandler + B TMR1_UP_IRQHandler + + PUBWEAK TMR1_TRG_COM_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + TMR1_TRG_COM_IRQHandler + B TMR1_TRG_COM_IRQHandler + + PUBWEAK TMR1_CC_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + TMR1_CC_IRQHandler + B TMR1_CC_IRQHandler + + PUBWEAK TMR2_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + TMR2_IRQHandler + B TMR2_IRQHandler + + PUBWEAK TMR3_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + TMR3_IRQHandler + B TMR3_IRQHandler + + PUBWEAK TMR4_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + TMR4_IRQHandler + B TMR4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EINT15_10_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + EINT15_10_IRQHandler + B EINT15_10_IRQHandler + + PUBWEAK RTCAlarm_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + RTCAlarm_IRQHandler + B RTCAlarm_IRQHandler + + PUBWEAK USBDWakeUp_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + USBDWakeUp_IRQHandler + B USBDWakeUp_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK QSPI_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + QSPI_IRQHandler + B QSPI_IRQHandler + + PUBWEAK USBD2_HP_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + USBD2_HP_IRQHandler + B USBD2_HP_IRQHandler + + PUBWEAK USBD2_LP_IRQHandler + SECTION .text: + CODE: + REORDER: + NOROOT(1) + USBD2_LP_IRQHandler + B USBD2_LP_IRQHandler + + + END + diff --git a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/system_apm32f10x.c b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/system_apm32f10x.c index aad3575613..2fae0cb90a 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/system_apm32f10x.c +++ b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/system_apm32f10x.c @@ -3,14 +3,33 @@ * * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File * - * @version V1.0.1 + * @version V1.0.2 * - * @date 2021-03-23 + * @date 2022-01-05 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ #include "apm32f10x.h" +/***************************************************************** + * If SYSCLK source is PLL,SystemCoreClock will contain the * + * HSE_VALUE or HSI_VALUE multiplied/divided by the PLL factors. * +******************************************************************/ + //#define SYSTEM_CLOCK_HSE HSE_VALUE //#define SYSTEM_CLOCK_24MHz (24000000) //#define SYSTEM_CLOCK_36MHz (36000000) @@ -20,42 +39,42 @@ //#define SYSTEM_CLOCK_96MHz (96000000) -/* #define VECT_TAB_SRAM */ +/** #define VECT_TAB_SRAM */ #define VECT_TAB_OFFSET 0x00 #ifdef SYSTEM_CLOCK_HSE -uint32_t SystemCoreClock = SYSTEM_CLOCK_HSE; + uint32_t SystemCoreClock = SYSTEM_CLOCK_HSE; #elif defined SYSTEM_CLOCK_24MHz -uint32_t SystemCoreClock = SYSTEM_CLOCK_24MHz; + uint32_t SystemCoreClock = SYSTEM_CLOCK_24MHz; #elif defined SYSTEM_CLOCK_36MHz -uint32_t SystemCoreClock = SYSTEM_CLOCK_36MHz; + uint32_t SystemCoreClock = SYSTEM_CLOCK_36MHz; #elif defined SYSTEM_CLOCK_48MHz -uint32_t SystemCoreClock = SYSTEM_CLOCK_48MHz; + uint32_t SystemCoreClock = SYSTEM_CLOCK_48MHz; #elif defined SYSTEM_CLOCK_56MHz -uint32_t SystemCoreClock = SYSTEM_CLOCK_56MHz; + uint32_t SystemCoreClock = SYSTEM_CLOCK_56MHz; #elif defined SYSTEM_CLOCK_72MHz -uint32_t SystemCoreClock = SYSTEM_CLOCK_72MHz; + uint32_t SystemCoreClock = SYSTEM_CLOCK_72MHz; #else -uint32_t SystemCoreClock = SYSTEM_CLOCK_96MHz; + uint32_t SystemCoreClock = SYSTEM_CLOCK_96MHz; #endif static void SystemClockConfig(void); #ifdef SYSTEM_CLOCK_HSE -static void SystemClockHSE(void); + static void SystemClockHSE(void); #elif defined SYSTEM_CLOCK_24MHz -static void SystemClock24M(void); + static void SystemClock24M(void); #elif defined SYSTEM_CLOCK_36MHz -static void SystemClock36M(void); + static void SystemClock36M(void); #elif defined SYSTEM_CLOCK_48MHz -static void SystemClock48M(void); + static void SystemClock48M(void); #elif defined SYSTEM_CLOCK_56MHz -static void SystemClock56M(void); + static void SystemClock56M(void); #elif defined SYSTEM_CLOCK_72MHz -static void SystemClock72M(void); + static void SystemClock72M(void); #elif defined SYSTEM_CLOCK_96MHz -static void SystemClock96M(void); + static void SystemClock96M(void); #endif /*! @@ -65,13 +84,12 @@ static void SystemClock96M(void); * * @retval None * - * @note */ -void SystemInit (void) +void SystemInit(void) { /** Set HSIEN bit */ RCM->CTRL_B.HSIEN = BIT_SET; - /** Reset SCLKSW, AHBPSC, APB1PSC, APB2PSC, ADCPSC and MCOSEL bits */ + /** Reset SCLKSEL, AHBPSC, APB1PSC, APB2PSC, ADCPSC and MCOSEL bits */ RCM->CFG &= (uint32_t)0xF8FF0000; /** Reset HSEEN, CSSEN and PLLEN bits */ RCM->CTRL &= (uint32_t)0xFEF6FFFF; @@ -99,52 +117,51 @@ void SystemInit (void) * * @retval None * - * @note */ -void SystemCoreClockUpdate (void) +void SystemCoreClockUpdate(void) { uint32_t sysClock, pllMull, pllSource, Prescaler; uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - sysClock = RCM->CFG_B.SCLKSWSTS; + sysClock = RCM->CFG_B.SCLKSELSTS; - switch(sysClock) + switch (sysClock) { - /** sys clock is HSI */ - case 0: - SystemCoreClock = HSI_VALUE; + /** sys clock is HSI */ + case 0: + SystemCoreClock = HSI_VALUE; break; - /** sys clock is HSE */ - case 1: - SystemCoreClock = HSE_VALUE; + /** sys clock is HSE */ + case 1: + SystemCoreClock = HSE_VALUE; break; - /** sys clock is PLL */ - case 2: - pllMull = RCM->CFG_B.PLLMULCFG + 2; - pllSource = RCM->CFG_B.PLLSRCSEL; + /** sys clock is PLL */ + case 2: + pllMull = RCM->CFG_B.PLLMULCFG + 2; + pllSource = RCM->CFG_B.PLLSRCSEL; - /** PLL entry clock source is HSE */ - if(pllSource == BIT_SET) + /** PLL entry clock source is HSE */ + if (pllSource == BIT_SET) + { + SystemCoreClock = HSE_VALUE * pllMull; + + /** HSE clock divided by 2 */ + if (pllSource == RCM->CFG_B.PLLHSEPSC) { - SystemCoreClock = HSE_VALUE * pllMull; - - /** HSE clock divided by 2 */ - if(pllSource == RCM->CFG_B.PLLHSEPSC) - { - SystemCoreClock >>= 1; - } + SystemCoreClock >>= 1; } - /** PLL entry clock source is HSI/2 */ - else - { - SystemCoreClock = (HSI_VALUE >> 1) * pllMull; - } - break; + } + /** PLL entry clock source is HSI/2 */ + else + { + SystemCoreClock = (HSI_VALUE >> 1) * pllMull; + } + break; - default: - SystemCoreClock = HSI_VALUE; + default: + SystemCoreClock = HSI_VALUE; break; } @@ -159,7 +176,6 @@ void SystemCoreClockUpdate (void) * * @retval None * - * @note */ static void SystemClockConfig(void) { @@ -188,41 +204,40 @@ static void SystemClockConfig(void) * * @retval None * - * @note */ static void SystemClockHSE(void) { __IO uint32_t i; - RCM->CTRL_B.HSEEN= BIT_SET; + RCM->CTRL_B.HSEEN = BIT_SET; - for(i = 0; i < HSE_STARTUP_TIMEOUT; i++) + for (i = 0; i < HSE_STARTUP_TIMEOUT; i++) { - if(RCM->CTRL_B.HSERDYFLG) + if (RCM->CTRL_B.HSERDYFLG) { break; } } - if(RCM->CTRL_B.HSERDYFLG) + if (RCM->CTRL_B.HSERDYFLG) { - /* Enable Prefetch Buffer */ + /** Enable Prefetch Buffer */ FMC->CTRL1_B.PBEN = BIT_SET; - /* Flash 0 wait state */ + /** Flash 0 wait state */ FMC->CTRL1_B.WS = 0; - /* HCLK = SYSCLK */ - RCM->CFG_B.AHBPSC= 0X00; - /* PCLK2 = HCLK */ - RCM->CFG_B.APB2PSC= 0; - /* PCLK1 = HCLK */ + /** HCLK = SYSCLK */ + RCM->CFG_B.AHBPSC = 0X00; + /** PCLK2 = HCLK */ + RCM->CFG_B.APB2PSC = 0; + /** PCLK1 = HCLK */ RCM->CFG_B.APB1PSC = 0; - /* Select HSE as system clock source */ - RCM->CFG_B.SCLKSW = 1; + /** Select HSE as system clock source */ + RCM->CFG_B.SCLKSEL = 1; /** Wait till HSE is used as system clock source */ - while(RCM->CFG_B.SCLKSWSTS!= 0x01); + while (RCM->CFG_B.SCLKSELSTS != 0x01); } } @@ -235,34 +250,33 @@ static void SystemClockHSE(void) * * @retval None * - * @note */ static void SystemClock24M(void) { __IO uint32_t i; - RCM->CTRL_B.HSEEN= BIT_SET; + RCM->CTRL_B.HSEEN = BIT_SET; - for(i = 0; i < HSE_STARTUP_TIMEOUT; i++) + for (i = 0; i < HSE_STARTUP_TIMEOUT; i++) { - if(RCM->CTRL_B.HSERDYFLG) + if (RCM->CTRL_B.HSERDYFLG) { break; } } - if(RCM->CTRL_B.HSERDYFLG) + if (RCM->CTRL_B.HSERDYFLG) { - /* Enable Prefetch Buffer */ + /** Enable Prefetch Buffer */ FMC->CTRL1_B.PBEN = BIT_SET; - /* Flash 0 wait state */ + /** Flash 0 wait state */ FMC->CTRL1_B.WS = 0; - /* HCLK = SYSCLK */ - RCM->CFG_B.AHBPSC= 0X00; - /* PCLK2 = HCLK */ - RCM->CFG_B.APB2PSC= 0; - /* PCLK1 = HCLK */ + /** HCLK = SYSCLK */ + RCM->CFG_B.AHBPSC = 0X00; + /** PCLK2 = HCLK */ + RCM->CFG_B.APB2PSC = 0; + /** PCLK1 = HCLK */ RCM->CFG_B.APB1PSC = 0; /** PLL: (HSE / 2) * 6 */ @@ -273,12 +287,12 @@ static void SystemClock24M(void) /** Enable PLL */ RCM->CTRL_B.PLLEN = 1; /** Wait PLL Ready */ - while(RCM->CTRL_B.PLLRDYFLG == BIT_RESET); + while (RCM->CTRL_B.PLLRDYFLG == BIT_RESET); - /* Select PLL as system clock source */ - RCM->CFG_B.SCLKSW = 2; - /* Wait till PLL is used as system clock source */ - while(RCM->CFG_B.SCLKSWSTS!= 0x02); + /** Select PLL as system clock source */ + RCM->CFG_B.SCLKSEL = 2; + /** Wait till PLL is used as system clock source */ + while (RCM->CFG_B.SCLKSELSTS != 0x02); } } @@ -290,34 +304,33 @@ static void SystemClock24M(void) * * @retval None * - * @note */ static void SystemClock36M(void) { __IO uint32_t i; - RCM->CTRL_B.HSEEN= BIT_SET; + RCM->CTRL_B.HSEEN = BIT_SET; - for(i = 0; i < HSE_STARTUP_TIMEOUT; i++) + for (i = 0; i < HSE_STARTUP_TIMEOUT; i++) { - if(RCM->CTRL_B.HSERDYFLG) + if (RCM->CTRL_B.HSERDYFLG) { break; } } - if(RCM->CTRL_B.HSERDYFLG) + if (RCM->CTRL_B.HSERDYFLG) { - /* Enable Prefetch Buffer */ + /** Enable Prefetch Buffer */ FMC->CTRL1_B.PBEN = BIT_SET; - /* Flash 1 wait state */ + /** Flash 1 wait state */ FMC->CTRL1_B.WS = 1; - /* HCLK = SYSCLK */ - RCM->CFG_B.AHBPSC= 0X00; - /* PCLK2 = HCLK */ - RCM->CFG_B.APB2PSC= 0; - /* PCLK1 = HCLK */ + /** HCLK = SYSCLK */ + RCM->CFG_B.AHBPSC = 0X00; + /** PCLK2 = HCLK */ + RCM->CFG_B.APB2PSC = 0; + /** PCLK1 = HCLK */ RCM->CFG_B.APB1PSC = 0; /** PLL: (HSE / 2) * 9 */ @@ -328,12 +341,12 @@ static void SystemClock36M(void) /** Enable PLL */ RCM->CTRL_B.PLLEN = 1; /** Wait PLL Ready */ - while(RCM->CTRL_B.PLLRDYFLG == BIT_RESET); + while (RCM->CTRL_B.PLLRDYFLG == BIT_RESET); - /* Select PLL as system clock source */ - RCM->CFG_B.SCLKSW = 2; - /* Wait till PLL is used as system clock source */ - while(RCM->CFG_B.SCLKSWSTS != 0x02); + /** Select PLL as system clock source */ + RCM->CFG_B.SCLKSEL = 2; + /** Wait till PLL is used as system clock source */ + while (RCM->CFG_B.SCLKSELSTS != 0x02); } } @@ -345,34 +358,33 @@ static void SystemClock36M(void) * * @retval None * - * @note */ static void SystemClock48M(void) { __IO uint32_t i; - RCM->CTRL_B.HSEEN= BIT_SET; + RCM->CTRL_B.HSEEN = BIT_SET; - for(i = 0; i < HSE_STARTUP_TIMEOUT; i++) + for (i = 0; i < HSE_STARTUP_TIMEOUT; i++) { - if(RCM->CTRL_B.HSERDYFLG) + if (RCM->CTRL_B.HSERDYFLG) { break; } } - if(RCM->CTRL_B.HSERDYFLG) + if (RCM->CTRL_B.HSERDYFLG) { - /* Enable Prefetch Buffer */ + /** Enable Prefetch Buffer */ FMC->CTRL1_B.PBEN = BIT_SET; - /* Flash 1 wait state */ + /** Flash 1 wait state */ FMC->CTRL1_B.WS = 1; - /* HCLK = SYSCLK */ - RCM->CFG_B.AHBPSC= 0X00; - /* PCLK2 = HCLK */ - RCM->CFG_B.APB2PSC= 0; - /* PCLK1 = HCLK / 2 */ + /** HCLK = SYSCLK */ + RCM->CFG_B.AHBPSC = 0X00; + /** PCLK2 = HCLK */ + RCM->CFG_B.APB2PSC = 0; + /** PCLK1 = HCLK / 2 */ RCM->CFG_B.APB1PSC = 4; /** PLL: HSE * 6 */ @@ -382,12 +394,12 @@ static void SystemClock48M(void) /** Enable PLL */ RCM->CTRL_B.PLLEN = 1; /** Wait PLL Ready */ - while(RCM->CTRL_B.PLLRDYFLG == BIT_RESET); + while (RCM->CTRL_B.PLLRDYFLG == BIT_RESET); - /* Select PLL as system clock source */ - RCM->CFG_B.SCLKSW = 2; - /* Wait till PLL is used as system clock source */ - while(RCM->CFG_B.SCLKSWSTS!= 0x02); + /** Select PLL as system clock source */ + RCM->CFG_B.SCLKSEL = 2; + /** Wait till PLL is used as system clock source */ + while (RCM->CFG_B.SCLKSELSTS != 0x02); } } @@ -399,34 +411,33 @@ static void SystemClock48M(void) * * @retval None * - * @note */ static void SystemClock56M(void) { __IO uint32_t i; - RCM->CTRL_B.HSEEN= BIT_SET; + RCM->CTRL_B.HSEEN = BIT_SET; - for(i = 0; i < HSE_STARTUP_TIMEOUT; i++) + for (i = 0; i < HSE_STARTUP_TIMEOUT; i++) { - if(RCM->CTRL_B.HSERDYFLG) + if (RCM->CTRL_B.HSERDYFLG) { break; } } - if(RCM->CTRL_B.HSERDYFLG) + if (RCM->CTRL_B.HSERDYFLG) { - /* Enable Prefetch Buffer */ + /** Enable Prefetch Buffer */ FMC->CTRL1_B.PBEN = BIT_SET; - /* Flash 2 wait state */ + /** Flash 2 wait state */ FMC->CTRL1_B.WS = 2; - /* HCLK = SYSCLK */ - RCM->CFG_B.AHBPSC= 0X00; - /* PCLK2 = HCLK */ - RCM->CFG_B.APB2PSC= 0; - /* PCLK1 = HCLK / 2 */ + /** HCLK = SYSCLK */ + RCM->CFG_B.AHBPSC = 0X00; + /** PCLK2 = HCLK */ + RCM->CFG_B.APB2PSC = 0; + /** PCLK1 = HCLK / 2 */ RCM->CFG_B.APB1PSC = 4; /** PLL: HSE * 7 */ @@ -436,12 +447,12 @@ static void SystemClock56M(void) /** Enable PLL */ RCM->CTRL_B.PLLEN = 1; /** Wait PLL Ready */ - while(RCM->CTRL_B.PLLRDYFLG == BIT_RESET); + while (RCM->CTRL_B.PLLRDYFLG == BIT_RESET); - /* Select PLL as system clock source */ - RCM->CFG_B.SCLKSW = 2; - /* Wait till PLL is used as system clock source */ - while(RCM->CFG_B.SCLKSWSTS!= 0x02); + /** Select PLL as system clock source */ + RCM->CFG_B.SCLKSEL = 2; + /** Wait till PLL is used as system clock source */ + while (RCM->CFG_B.SCLKSELSTS != 0x02); } } @@ -453,34 +464,33 @@ static void SystemClock56M(void) * * @retval None * - * @note */ static void SystemClock72M(void) { __IO uint32_t i; - RCM->CTRL_B.HSEEN= BIT_SET; + RCM->CTRL_B.HSEEN = BIT_SET; - for(i = 0; i < HSE_STARTUP_TIMEOUT; i++) + for (i = 0; i < HSE_STARTUP_TIMEOUT; i++) { - if(RCM->CTRL_B.HSERDYFLG) + if (RCM->CTRL_B.HSERDYFLG) { break; } } - if(RCM->CTRL_B.HSERDYFLG) + if (RCM->CTRL_B.HSERDYFLG) { - /* Enable Prefetch Buffer */ + /** Enable Prefetch Buffer */ FMC->CTRL1_B.PBEN = BIT_SET; - /* Flash 2 wait state */ + /** Flash 2 wait state */ FMC->CTRL1_B.WS = 2; - /* HCLK = SYSCLK */ - RCM->CFG_B.AHBPSC= 0X00; - /* PCLK2 = HCLK */ - RCM->CFG_B.APB2PSC= 0; - /* PCLK1 = HCLK / 2 */ + /** HCLK = SYSCLK */ + RCM->CFG_B.AHBPSC = 0X00; + /** PCLK2 = HCLK */ + RCM->CFG_B.APB2PSC = 0; + /** PCLK1 = HCLK / 2 */ RCM->CFG_B.APB1PSC = 4; /** PLL: HSE * 9 */ @@ -490,12 +500,12 @@ static void SystemClock72M(void) /** Enable PLL */ RCM->CTRL_B.PLLEN = 1; /** Wait PLL Ready */ - while(RCM->CTRL_B.PLLRDYFLG == BIT_RESET); + while (RCM->CTRL_B.PLLRDYFLG == BIT_RESET); - /* Select PLL as system clock source */ - RCM->CFG_B.SCLKSW = 2; - /* Wait till PLL is used as system clock source */ - while(RCM->CFG_B.SCLKSWSTS!= 0x02); + /** Select PLL as system clock source */ + RCM->CFG_B.SCLKSEL = 2; + /** Wait till PLL is used as system clock source */ + while (RCM->CFG_B.SCLKSELSTS != 0x02); } } @@ -508,34 +518,33 @@ static void SystemClock72M(void) * * @retval None * - * @note */ static void SystemClock96M(void) { __IO uint32_t i; - RCM->CTRL_B.HSEEN= BIT_SET; + RCM->CTRL_B.HSEEN = BIT_SET; - for(i = 0; i < HSE_STARTUP_TIMEOUT; i++) + for (i = 0; i < HSE_STARTUP_TIMEOUT; i++) { - if(RCM->CTRL_B.HSERDYFLG) + if (RCM->CTRL_B.HSERDYFLG) { break; } } - if(RCM->CTRL_B.HSERDYFLG) + if (RCM->CTRL_B.HSERDYFLG) { - /* Enable Prefetch Buffer */ + /** Enable Prefetch Buffer */ FMC->CTRL1_B.PBEN = BIT_SET; - /* Flash 3 wait state */ + /** Flash 3 wait state */ FMC->CTRL1_B.WS = 3; - /* HCLK = SYSCLK */ - RCM->CFG_B.AHBPSC= 0X00; - /* PCLK2 = HCLK */ - RCM->CFG_B.APB2PSC= 0; - /* PCLK1 = HCLK / 2 */ + /** HCLK = SYSCLK */ + RCM->CFG_B.AHBPSC = 0X00; + /** PCLK2 = HCLK */ + RCM->CFG_B.APB2PSC = 0; + /** PCLK1 = HCLK / 2 */ RCM->CFG_B.APB1PSC = 4; /** PLL: HSE * 12 */ @@ -545,12 +554,12 @@ static void SystemClock96M(void) /** Enable PLL */ RCM->CTRL_B.PLLEN = 1; /** Wait PLL Ready */ - while(RCM->CTRL_B.PLLRDYFLG == BIT_RESET); + while (RCM->CTRL_B.PLLRDYFLG == BIT_RESET); - /* Select PLL as system clock source */ - RCM->CFG_B.SCLKSW = 2; - /* Wait till PLL is used as system clock source */ - while(RCM->CFG_B.SCLKSWSTS!= 0x02); + /** Select PLL as system clock source */ + RCM->CFG_B.SCLKSEL = 2; + /** Wait till PLL is used as system clock source */ + while (RCM->CFG_B.SCLKSELSTS != 0x02); } } #endif diff --git a/bsp/apm32/libraries/APM32F10x_Library/SConscript b/bsp/apm32/libraries/APM32F10x_Library/SConscript index 84a2e5e2f6..a95e30d56a 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/SConscript +++ b/bsp/apm32/libraries/APM32F10x_Library/SConscript @@ -15,6 +15,26 @@ APM32F10x_StdPeriphDriver/src/apm32f10x_usart.c APM32F10x_StdPeriphDriver/src/apm32f10x_eint.c """) +if GetDepend(['RT_USING_ADC']): + src += ['APM32F10x_StdPeriphDriver/src/apm32f10x_adc.c'] + +if GetDepend(['RT_USING_DAC']): + src += ['APM32F10x_StdPeriphDriver/src/apm32f10x_dac.c'] + +if GetDepend(['RT_USING_RTC']): + src += ['APM32F10x_StdPeriphDriver/src/apm32f10x_rtc.c'] + src += ['APM32F10x_StdPeriphDriver/src/apm32f10x_pmu.c'] + +if GetDepend(['RT_USING_SPI']): + src += ['APM32F10x_StdPeriphDriver/src/apm32f10x_spi.c'] + +if GetDepend(['RT_USING_HWTIMER']) or GetDepend(['RT_USING_PWM']): + src += ['APM32F10x_StdPeriphDriver/src/apm32f10x_tmr.c'] + +if GetDepend(['RT_USING_WDT']): + src += ['APM32F10x_StdPeriphDriver/src/apm32f10x_wwdt.c'] + src += ['APM32F10x_StdPeriphDriver/src/apm32f10x_iwdt.c'] + path = [cwd + '/Device/Geehy/APM32F10x/Include', cwd + '/APM32F10x_StdPeriphDriver/inc', cwd + '/CMSIS/Include'] diff --git a/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/CDC/inc/usbd_class_cdc.h b/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/CDC/inc/usbd_class_cdc.h new file mode 100644 index 0000000000..0aebd68c42 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/CDC/inc/usbd_class_cdc.h @@ -0,0 +1,33 @@ +/*! + * @file usbd_class_cdc.h + * + * @brief CDC Class handler file head file + * + * @version V1.0.0 + * + * @date 2021-12-06 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +#ifndef __CDC_CLASS_ +#define __CDC_CLASS_ + +#include "usbd_core.h" + +void USBD_ClassHandler(USBD_DevReqData_T *reqData); + +#endif diff --git a/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/CDC/src/usbd_class_cdc.c b/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/CDC/src/usbd_class_cdc.c new file mode 100644 index 0000000000..ec54feeeda --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/CDC/src/usbd_class_cdc.c @@ -0,0 +1,71 @@ +/*! + * @file usbd_class_cdc.c + * + * @brief CDC Class handler file + * + * @version V1.0.0 + * + * @date 2021-12-06 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +#include "usbd_class_cdc.h" + +static uint8_t cmdBuf[8] = {0}; + +/*! + * @brief USB CDC Class request handler + * + * @param reqData : point to USBD_DevReqData_T structure + * + * @retval None + */ +void USBD_ClassHandler(USBD_DevReqData_T *reqData) +{ + uint16_t length = ((uint16_t)reqData->byte.wLength[1] << 8) | \ + reqData->byte.wLength[0] ; + + if (!length) + { + if (!reqData->byte.bmRequestType.bit.dir) + { + USBD_CtrlTxStatus(); + } + else + { + USBD_CtrlRxStatus(); + } + } + else + { + switch (reqData->byte.bRequest) + { + + case 0x20: + USBD_CtrlOutData(cmdBuf, length); + break; + case 0x21: + USBD_CtrlInData(cmdBuf, length); + break; + case 0x22: + USBD_CtrlOutData(cmdBuf, length); + break; + default: + break; + } + } +} diff --git a/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/HID/inc/usbd_class_hid.h b/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/HID/inc/usbd_class_hid.h new file mode 100644 index 0000000000..f1dc26c463 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/HID/inc/usbd_class_hid.h @@ -0,0 +1,37 @@ +/*! + * @file usbd_class_hid.h + * + * @brief HID Class handler file head file + * + * @version V1.0.0 + * + * @date 2021-12-06 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +#include "usbd_core.h" + +#define HID_CLASS_REQ_SET_PROTOCOL 0x0B +#define HID_CLASS_REQ_GET_PROTOCOL 0x03 + +#define HID_CLASS_REQ_SET_IDLE 0x0A +#define HID_CLASS_REQ_GET_IDLE 0x02 + +#define HID_CLASS_REQ_SET_REPORT 0x09 +#define HID_CLASS_REQ_GET_REPORT 0x01 + +void USBD_ClassHandler(USBD_DevReqData_T *reqData); diff --git a/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/HID/src/usbd_class_hid.c b/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/HID/src/usbd_class_hid.c new file mode 100644 index 0000000000..e81462c40c --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/HID/src/usbd_class_hid.c @@ -0,0 +1,63 @@ +/*! + * @file usbd_class_hid.c + * + * @brief HID Class handler file + * + * @version V1.0.0 + * + * @date 2021-12-06 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +#include "usbd_class_hid.h" + +static uint8_t s_hidIdleState; +static uint8_t s_hidProtocol; + +/*! + * @brief USB HID Class request handler + * + * @param reqData : point to USBD_DevReqData_T structure + * + * @retval None + */ +void USBD_ClassHandler(USBD_DevReqData_T *reqData) +{ + switch (reqData->byte.bRequest) + { + case HID_CLASS_REQ_SET_IDLE: + s_hidIdleState = reqData->byte.wValue[1]; + USBD_CtrlInData(NULL, 0); + break; + + case HID_CLASS_REQ_GET_IDLE: + USBD_CtrlInData(&s_hidIdleState, 1); + break; + + case HID_CLASS_REQ_SET_PROTOCOL: + s_hidProtocol = reqData->byte.wValue[0]; + USBD_CtrlInData(NULL, 0); + break; + + case HID_CLASS_REQ_GET_PROTOCOL: + USBD_CtrlInData(&s_hidProtocol, 1); + break; + + default: + break; + } +} diff --git a/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/MSC/inc/usbd_class_msc.h b/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/MSC/inc/usbd_class_msc.h new file mode 100644 index 0000000000..67cb3f293e --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/MSC/inc/usbd_class_msc.h @@ -0,0 +1,37 @@ +/*! + * @file usbd_class_msc.h + * + * @brief MSC Class handler file head file + * + * @version V1.0.0 + * + * @date 2021-12-06 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +#ifndef __USBD_CLASS_MSC +#define __USBD_CLASS_MSC + +#include "usbd_core.h" + + +#define BOT_GET_MAX_LUN 0xFE +#define BOT_RESET 0xFF + +void USBD_MSC_ClassHandler(USBD_DevReqData_T *reqData); + +#endif diff --git a/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/MSC/inc/usbd_msc_bot.h b/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/MSC/inc/usbd_msc_bot.h new file mode 100644 index 0000000000..b44f2f6e86 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/MSC/inc/usbd_msc_bot.h @@ -0,0 +1,106 @@ +/*! + * @file usbd_msc_bot.h + * + * @brief MSC BOT protocol core functions + * + * @version V1.0.0 + * + * @date 2021-12-25 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +#include "usbd_core.h" + +#ifndef __USBD_MSC_BOT_H +#define __USBD_MSC_BOT_H + +#define MSC_BOT_CBW_SIGNATURE (uint32_t)(0x43425355) +#define MSC_BOT_CBW_LENGTH 31 + +#define MSC_BOT_CSW_SIGNATURE (uint32_t)(0x53425355) +#define MSC_BOT_CSW_LENGTH 13 + +typedef enum +{ + BOT_STATE_IDLE, //!< Idle state + BOT_STATE_DATA_OUT, //!< Data Out state + BOT_STATE_DATA_IN, //!< Data In state + BOT_STATE_LAST_DATA_IN, //!< Last Data In Last + BOT_STATE_SEND_DATA //!< Send Immediate data +} BOT_STATE_T; + +typedef enum +{ + BOT_STATUS_NORMAL, + BOT_STATUS_RECOVERY, + BOT_STATUS_ERROR +} BOT_STATUS_T; + +typedef enum +{ + BOT_CSW_STATUS_CMD_OK, + BOT_CSW_STATUS_CMD_FAIL, + BOT_CSW_STATUS_PHASE_ERROR +} BOT_CSW_STATUS_T; + + +/** + * @brief Command Block Wrapper + */ +typedef struct +{ + uint32_t dSignature; + uint32_t dTag; + uint32_t dDataXferLen; + uint8_t bmFlags; + uint8_t bLUN; + uint8_t bCBLen; + uint8_t CB[16]; +} BOT_CBW_T; + +/** + * @brief Command Status Wrapper + */ +typedef struct +{ + uint32_t dSignature; + uint32_t dTag; + uint32_t dDataResidue; + uint8_t bStatus; +} BOT_CSW_T; + +typedef struct +{ + uint8_t state; + uint8_t status; + uint16_t dataLen; + BOT_CBW_T CBW; + BOT_CSW_T CSW; + uint8_t data[MSC_MEDIA_PACKET]; +} BOT_Info_T; + +extern BOT_Info_T g_BOTInfo; + +void USBD_MSC_BOT_Reset(void); +void USBD_MSC_BOT_Init(void); +void USBD_MSC_BOT_OutData(uint8_t ep); +void USBD_MSC_BOT_InData(uint8_t ep); +void USBD_MSC_BOT_TxCSW(uint8_t cswStatus); +void USBD_MSC_BOT_Stall(void); +void USBD_MSV_BOT_ClearFeatureHandler(void); + +#endif diff --git a/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/MSC/inc/usbd_msc_scsi.h b/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/MSC/inc/usbd_msc_scsi.h new file mode 100644 index 0000000000..9da491a7ce --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/MSC/inc/usbd_msc_scsi.h @@ -0,0 +1,132 @@ +/*! + * @file usbd_msc_scsi.h + * + * @brief MSC scsi + * + * @version V1.0.0 + * + * @date 2021-12-25 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +#include "usbd_core.h" +#ifndef __USBD_MSC_SCSI_H_ +#define __USBD_MSC_SCSI_H_ + +/** + * @brief SCSI function status + */ +enum +{ + SCSI_OK, + SCSI_FAIL +}; + +/** + * @brief SCSI Sense Key + */ +typedef enum +{ + SCSI_SKEY_NO_SENSE, + SCSI_SKEY_RECOVERED_ERROR, + SCSI_SKEY_NOT_READY, + SCSI_SKEY_MEDIUM_ERROR, + SCSI_SKEY_HARDWARE_ERROR, + SCSI_SKEY_ILLEGAL_REQUEST, + SCSI_SKEY_UNIT_ATTENTION, + SCSI_SKEY_DATA_PROTECT, + SCSI_SKEY_BLANK_CHECK, + SCSI_SKEY_VENDOR_SPECIFIC, + SCSI_SKEY_COPY_ABORTED, + SCSI_SKEY_ABORTED_COMMAND, + SCSI_SKEY_VOLUME_OVERFLOW = 13, + SCSI_SKEY_MISCOMPARE = 14 +} SCSI_SKEY_T; + +/** + * @brief SCSI Sense + */ +typedef struct +{ + uint8_t sensekey; + uint8_t ASC; + uint8_t ASCQ; +} SCSI_Sense_T; + + +#define SCSI_SENSE_LIST_NUMBER 4 +#define SCSI_INQUIRY_LENGTH 36 + +/** SCSI Commands */ +#define SCSI_CMD_FORMAT_UNIT ((uint8_t)0x04) +#define SCSI_CMD_INQUIRY ((uint8_t)0x12) +#define SCSI_CMD_MODE_SELECT_6 ((uint8_t)0x15) +#define SCSI_CMD_MODE_SELECT_10 ((uint8_t)0x55) +#define SCSI_CMD_MODE_SENSE_6 ((uint8_t)0x1A) +#define SCSI_CMD_MODE_SENSE_10 ((uint8_t)0x5A) +#define SCSI_CMD_ALLOW_MEDIUM_REMOVAL ((uint8_t)0x1E) +#define SCSI_CMD_READ_6 ((uint8_t)0x08) +#define SCSI_CMD_READ_10 ((uint8_t)0x28) +#define SCSI_CMD_READ_12 ((uint8_t)0xA8) +#define SCSI_CMD_READ_16 ((uint8_t)0x88) + +#define SCSI_CMD_READ_CAPACITY_10 ((uint8_t)0x25) +#define SCSI_CMD_READ_CAPACITY_16 ((uint8_t)0x9E) + +#define SCSI_CMD_REQUEST_SENSE ((uint8_t)0x03) +#define SCSI_CMD_START_STOP_UNIT ((uint8_t)0x1B) +#define SCSI_CMD_TEST_UNIT_READY ((uint8_t)0x00) +#define SCSI_CMD_WRITE6 ((uint8_t)0x0A) +#define SCSI_CMD_WRITE10 ((uint8_t)0x2A) +#define SCSI_CMD_WRITE12 ((uint8_t)0xAA) +#define SCSI_CMD_WRITE16 ((uint8_t)0x8A) + +#define SCSI_CMD_VERIFY_10 ((uint8_t)0x2F) +#define SCSI_CMD_VERIFY_12 ((uint8_t)0xAF) +#define SCSI_CMD_VERIFY_16 ((uint8_t)0x8F) + +#define SCSI_CMD_SEND_DIAGNOSTIC ((uint8_t)0x1D) +#define SCSI_CMD_READ_FORMAT_CAPACITIES ((uint8_t)0x23) + + +#define SCSI_ASC_INVALID_CDB 0x20 +#define SCSI_ASC_INVALID_FIELED_IN_COMMAND 0x24 +#define SCSI_ASC_PARAMETER_LIST_LENGTH_ERROR 0x1A +#define SCSI_ASC_INVALID_FIELD_IN_PARAMETER_LIST 0x26 +#define SCSI_ASC_ADDRESS_OUT_OF_RANGE 0x21 +#define SCSI_ASC_MEDIUM_NOT_PRESENT 0x3A +#define SCSI_ASC_MEDIUM_HAVE_CHANGED 0x28 +#define SCSI_ASC_WRITE_PROTECTED 0x27 +#define SCSI_ASC_UNRECOVERED_READ_ERROR 0x11 +#define SCSI_ASC_WRITE_FAULT 0x03 + +#define SCSI_READ_FORMAT_CAPACITY_DATA_LEN 0x0C +#define SCSI_READ_CAPACITY10_DATA_LEN 0x08 +#define SCSI_MODE_SENSE10_DATA_LEN 0x08 +#define SCSI_MODE_SENSE6_DATA_LEN 0x04 +#define SCSI_REQUEST_SENSE_DATA_LEN 0x12 +#define SCSI_STANDARD_INQUIRY_DATA_LEN 0x24 +#define SCSI_BLKVFY 0x04 + +extern SCSI_Sense_T g_scsiSense[SCSI_SENSE_LIST_NUMBER]; +extern uint8_t g_senseTxCnt; +extern uint8_t g_sensePutCnt; + +uint8_t SCSI_CmdHandler(uint8_t lun, uint8_t *cmd); +void SCSI_PutSenseCode(uint8_t lun, uint8_t sKey, uint8_t ASC, uint8_t ASCQ); + +#endif diff --git a/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/MSC/src/usbd_class_msc.c b/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/MSC/src/usbd_class_msc.c new file mode 100644 index 0000000000..09c3a83a77 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/MSC/src/usbd_class_msc.c @@ -0,0 +1,79 @@ +/*! + * @file usbd_class_msc.c + * + * @brief MSC Class file + * + * @version V1.0.0 + * + * @date 2021-12-06 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +#include "usbd_class_msc.h" +#include "usbd_msc_bot.h" + +static uint8_t s_mscMaxLen = 0; + +/*! + * @brief USB MSC Class request handler + * + * @param reqData : point to USBD_DevReqData_T structure + * + * @retval None + */ +void USBD_MSC_ClassHandler(USBD_DevReqData_T *reqData) +{ + uint16_t wValue = ((uint16_t)reqData->byte.wValue[1] << 8) | \ + reqData->byte.wValue[0]; + uint16_t wLength = ((uint16_t)reqData->byte.wLength[1] << 8) | \ + reqData->byte.wLength[0]; + + switch (reqData->byte.bRequest) + { + case BOT_GET_MAX_LUN : + if ((wValue == 0) && (wLength == 1) && \ + (reqData->byte.bmRequestType.bit.dir == 1)) + { + s_mscMaxLen = STORAGE_MAX_LUN - 1; + + USBD_CtrlInData(&s_mscMaxLen, 1); + } + else + { + USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_STALL, USBD_EP_STATUS_STALL); + } + break; + case BOT_RESET : + if ((wValue == 0) && (wLength == 0) && \ + (reqData->byte.bmRequestType.bit.dir == 0)) + { + USBD_CtrlInData(NULL, 0); + /** Reset */ + USBD_MSC_BOT_Reset(); + } + else + { + USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_STALL, USBD_EP_STATUS_STALL); + } + + break; + + default: + USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_STALL, USBD_EP_STATUS_STALL); + break; + } +} diff --git a/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/MSC/src/usbd_msc_bot.c b/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/MSC/src/usbd_msc_bot.c new file mode 100644 index 0000000000..436544e371 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/MSC/src/usbd_msc_bot.c @@ -0,0 +1,242 @@ +/*! + * @file usbd_msv_bot.c + * + * @brief MSC BOT protocol core functions + * + * @version V1.0.0 + * + * @date 2021-12-25 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +#include "usbd_msc_bot.h" +#include "usbd_core.h" +#include "usbd_storage_disk.h" +#include "usbd_msc_scsi.h" + +BOT_Info_T g_BOTInfo; + +static void USBD_MSC_BOT_DecodeCBW(void); +static void USBD_MSC_BOT_TxData(uint8_t *txBuf, uint16_t len); +static void USBD_MSC_BOT_Stall(void); + +/*! + * @brief BOT Process Reset. + * + * @param None + * + * @retval None + */ +void USBD_MSC_BOT_Reset(void) +{ + g_BOTInfo.state = BOT_STATE_IDLE; + g_BOTInfo.status = BOT_STATUS_RECOVERY; + + USBD_RxData(MSC_OUT_EP & 0x7f, (uint8_t *)&g_BOTInfo.CBW, MSC_BOT_CBW_LENGTH); +} + +/*! + * @brief BOT Process initialization. + * + * @param None + * + * @retval None + */ +void USBD_MSC_BOT_Init(void) +{ + g_BOTInfo.state = BOT_STATE_IDLE; + g_BOTInfo.status = BOT_STATUS_NORMAL; + + g_storageCallBack.Init(0); + + USBD_RxData(MSC_OUT_EP & 0x7f, (uint8_t *)&g_BOTInfo.CBW, MSC_BOT_CBW_LENGTH); +} + +/*! + * @brief Bulk OUT data handler. + * + * @param ep : OUT endpoint + * + * @retval None + */ +void USBD_MSC_BOT_OutData(uint8_t ep) +{ + if (g_BOTInfo.state == BOT_STATE_IDLE) + { + USBD_MSC_BOT_DecodeCBW(); + } + else if (g_BOTInfo.state == BOT_STATE_DATA_OUT) + { + if (SCSI_CmdHandler(g_BOTInfo.CBW.bLUN, g_BOTInfo.CBW.CB) != SCSI_OK) + { + USBD_MSC_BOT_TxCSW(BOT_CSW_STATUS_CMD_FAIL); + } + } +} + +/*! + * @brief Bulk IN data handler. + * + * @param ep : IN endpoint + * + * @retval None + */ +void USBD_MSC_BOT_InData(uint8_t ep) +{ + if (g_BOTInfo.state == BOT_STATE_DATA_IN) + { + if (SCSI_CmdHandler(g_BOTInfo.CBW.bLUN, g_BOTInfo.CBW.CB) != SCSI_OK) + { + USBD_MSC_BOT_TxCSW(BOT_CSW_STATUS_CMD_FAIL); + } + } + else if ((g_BOTInfo.state == BOT_STATE_SEND_DATA) || \ + (g_BOTInfo.state == BOT_STATE_LAST_DATA_IN)) + { + USBD_MSC_BOT_TxCSW(BOT_CSW_STATUS_CMD_OK); + } +} + +/*! + * @brief Decode CBW. + * + * @param None + * + * @retval None + */ +static void USBD_MSC_BOT_DecodeCBW(void) +{ + uint32_t xferCnt = g_usbDev.outBuf[MSC_OUT_EP & 0x7f].xferCnt; + + g_BOTInfo.CSW.dTag = g_BOTInfo.CBW.dTag; + g_BOTInfo.CSW.dDataResidue = g_BOTInfo.CBW.dDataXferLen; + + if ((xferCnt != MSC_BOT_CBW_LENGTH) || \ + (g_BOTInfo.CBW.dSignature != MSC_BOT_CBW_SIGNATURE) || \ + (g_BOTInfo.CBW.bLUN > 1) || (g_BOTInfo.CBW.bCBLen < 1) || \ + (g_BOTInfo.CBW.bCBLen > 16)) + { + SCSI_PutSenseCode(g_BOTInfo.CBW.bLUN, SCSI_SKEY_ILLEGAL_REQUEST, + SCSI_ASC_INVALID_CDB, 0); + + g_BOTInfo.status = BOT_STATUS_ERROR; + } + else + { + if (SCSI_CmdHandler(g_BOTInfo.CBW.bLUN, g_BOTInfo.CBW.CB) != SCSI_OK) + { + USBD_MSC_BOT_Stall(); + } + else if ((g_BOTInfo.state == BOT_STATE_IDLE) || \ + (g_BOTInfo.state == BOT_STATE_SEND_DATA)) + { + if (g_BOTInfo.dataLen) + { + USBD_MSC_BOT_TxData(g_BOTInfo.data, g_BOTInfo.dataLen); + } + else + { + USBD_MSC_BOT_TxCSW(BOT_CSW_STATUS_CMD_OK); + } + } + } +} + +/*! + * @brief MSC send data. + * + * @param txBuf : buffer to send + * + * @param len : buffer length + * + * @retval None + */ +static void USBD_MSC_BOT_TxData(uint8_t *txBuf, uint16_t len) +{ + len = USB_MIN(len, g_BOTInfo.CBW.dDataXferLen); + + g_BOTInfo.CSW.dDataResidue -= len; + g_BOTInfo.CSW.bStatus = BOT_CSW_STATUS_CMD_OK; + g_BOTInfo.state = BOT_STATE_SEND_DATA; + + USBD_TxData(MSC_IN_EP & 0x7f, txBuf, len); +} + +/*! + * @brief Send CSW. + * + * @param cswStatus : status of CSW + * + * @retval None + */ +void USBD_MSC_BOT_TxCSW(uint8_t cswStatus) +{ + g_BOTInfo.CSW.dSignature = MSC_BOT_CSW_SIGNATURE; + g_BOTInfo.CSW.bStatus = cswStatus; + g_BOTInfo.state = BOT_STATE_IDLE; + + USBD_TxData(MSC_IN_EP & 0x7f, (uint8_t *)&g_BOTInfo.CSW, + MSC_BOT_CSW_LENGTH); + + USBD_RxData(MSC_OUT_EP & 0x7f, (uint8_t *)&g_BOTInfo.CBW, + MSC_BOT_CBW_LENGTH); +} + +/*! + * @brief handler clearFeature in standard request. + * + * @param None + * + * @retval None + */ +void USBD_MSV_BOT_ClearFeatureHandler(void) +{ + if (g_BOTInfo.status == BOT_STATUS_ERROR) + { + USBD_SetEPTxStatus(MSC_IN_EP & 0x7f, USBD_EP_STATUS_NAK); + g_BOTInfo.status = BOT_STATUS_NORMAL; + } + else if (((g_usbDev.reqData.byte.wIndex[0] & 0x80) == 0x80) && \ + g_BOTInfo.status != BOT_STATUS_RECOVERY) + { + USBD_MSC_BOT_TxCSW(BOT_CSW_STATUS_CMD_FAIL); + } +} + +/*! + * @brief Stall MSC. + * + * @param None + * + * @retval None + */ +static void USBD_MSC_BOT_Stall(void) +{ + if ((g_BOTInfo.CBW.bmFlags == 0) && (g_BOTInfo.CBW.dDataXferLen != 0) && \ + (g_BOTInfo.status == BOT_STATUS_NORMAL)) + { + USBD_SetEPRxStatus(MSC_OUT_EP & 0x7f, USBD_EP_STATUS_STALL); + } + + USBD_SetEPTxStatus(MSC_IN_EP & 0x7f, USBD_EP_STATUS_STALL); + + if (g_BOTInfo.status == BOT_STATUS_ERROR) + { + USBD_RxData(MSC_OUT_EP & 0x7f, (uint8_t *)&g_BOTInfo.CBW, + MSC_BOT_CBW_LENGTH); + } +} diff --git a/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/MSC/src/usbd_msc_scsi.c b/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/MSC/src/usbd_msc_scsi.c new file mode 100644 index 0000000000..61fb46ac1c --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/MSC/src/usbd_msc_scsi.c @@ -0,0 +1,701 @@ +/*! + * @file usbd_msc_scsi.c + * + * @brief MSC scsi + * + * @version V1.0.0 + * + * @date 2021-12-25 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +#include "usbd_msc_bot.h" +#include "usbd_msc_scsi.h" +#include "usbd_storage_disk.h" + +SCSI_Sense_T g_scsiSenseCode[SCSI_SENSE_LIST_NUMBER]; +uint8_t g_senseTxCnt; +uint8_t g_sensePutCnt; + +static uint32_t s_blkSize; +static uint32_t s_blkNbr; + +static uint32_t s_blkAddr; +static uint32_t s_blkLen; + +/** USB Mass storage Page 0 Inquiry Data */ +static const uint8_t s_page00InquiryData[] = +{ + 0x00, + 0x00, + 0x00, + (7 - 4), + 0x00, + 0x80, + 0x83 +}; +/** USB Mass storage sense 6 Data */ +static const uint8_t s_modeSense6Data[] = +{ + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00 +}; +/** USB Mass storage sense 10 Data */ +static const uint8_t s_modeSense10Data[] = +{ + 0x00, + 0x06, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00 +}; + +static uint8_t SCSI_TestUnitReady(uint8_t lun); +static uint8_t SCSI_Inquiry(uint8_t lun, uint8_t *command); +static uint8_t SCSI_RequestSense(uint8_t lun, uint8_t *command); + +static uint8_t SCSI_ReadFormatCapacity(uint8_t lun, uint8_t *command); +static uint8_t SCSI_ReadCapacity10(uint8_t lun, uint8_t *command); +static uint8_t SCSI_Read10(uint8_t lun, uint8_t *command); +static uint8_t SCSI_Write10(uint8_t lun, uint8_t *command); +static uint8_t SCSI_Verify10(uint8_t lun, uint8_t *command); + +static uint8_t SCSI_StartStopUnit(void); +static uint8_t SCSI_ModeSense6(uint8_t lun, uint8_t *command); +static uint8_t SCSI_ModeSense10(uint8_t lun, uint8_t *command); + +static uint8_t SCSI_Read(uint8_t lun); +static uint8_t SCSI_Write(uint8_t lun); +static uint8_t SCSI_CheckAddress(uint8_t lun, uint32_t blkOffset, uint16_t blkNbr); + +/*! + * @brief SCSI command handler. + * + * @param lun: Logical unit number + * + * @param command: Command pointer + * + * @retval SCSI_OK or SCSI_FAILL + */ +uint8_t SCSI_CmdHandler(uint8_t lun, uint8_t *command) +{ + uint8_t ret = SCSI_OK; + + switch (command[0]) + { + case SCSI_CMD_TEST_UNIT_READY: + ret = SCSI_TestUnitReady(lun); + break; + + case SCSI_CMD_INQUIRY: + ret = SCSI_Inquiry(lun, command); + break; + + case SCSI_CMD_REQUEST_SENSE: + ret = SCSI_RequestSense(lun, command); + break; + + case SCSI_CMD_READ_FORMAT_CAPACITIES: + ret = SCSI_ReadFormatCapacity(lun, command); + break; + + case SCSI_CMD_READ_CAPACITY_10: + ret = SCSI_ReadCapacity10(lun, command); + break; + + case SCSI_CMD_READ_10: + ret = SCSI_Read10(lun, command); + break; + + case SCSI_CMD_WRITE10: + ret = SCSI_Write10(lun, command); + break; + + case SCSI_CMD_VERIFY_10: + ret = SCSI_Verify10(lun, command); + break; + case SCSI_CMD_ALLOW_MEDIUM_REMOVAL: + case SCSI_CMD_START_STOP_UNIT: + ret = SCSI_StartStopUnit(); + break; + + case SCSI_CMD_MODE_SENSE_6: + ret = SCSI_ModeSense6(lun, command); + break; + + case SCSI_CMD_MODE_SENSE_10: + ret = SCSI_ModeSense10(lun, command); + break; + + default: + SCSI_PutSenseCode(lun, SCSI_SKEY_ILLEGAL_REQUEST, + SCSI_ASC_INVALID_CDB, 0); + ret = SCSI_FAIL; + } + + return ret; +} + +/*! + * @brief Put the sense code to array. + * + * @param sKey: sense Key + * + * @param ASC: Additional Sense Code + * + * @param ASCQ: Additional Sense Code Qualifier + * + * @retval None + */ +void SCSI_PutSenseCode(uint8_t lun, uint8_t sKey, uint8_t ASC, uint8_t ASCQ) +{ + g_scsiSenseCode[g_sensePutCnt].sensekey = sKey; + g_scsiSenseCode[g_sensePutCnt].ASC = ASC; + g_scsiSenseCode[g_sensePutCnt].ASCQ = ASCQ; + + if ((++g_sensePutCnt) == SCSI_SENSE_LIST_NUMBER) + { + g_sensePutCnt = 0; + } +} + +/*! + * @brief SCSI Test Unit Ready handler. + * + * @param lun: Logical unit number + * + * @retval SCSI_OK or SCSI_FAILL + */ +static uint8_t SCSI_TestUnitReady(uint8_t lun) +{ + if (g_BOTInfo.CBW.dDataXferLen) + { + SCSI_PutSenseCode(g_BOTInfo.CBW.bLUN, SCSI_SKEY_ILLEGAL_REQUEST, + SCSI_ASC_INVALID_CDB, 0); + + return SCSI_FAIL; + } + else if (g_storageCallBack.CheckReady(lun) != SCSI_OK) + { + SCSI_PutSenseCode(lun, SCSI_SKEY_NOT_READY, + SCSI_ASC_MEDIUM_NOT_PRESENT, 0); + + return SCSI_FAIL; + } + else + { + g_BOTInfo.dataLen = 0; + return SCSI_OK; + } +} + +/*! + * @brief SCSI Inquiry handler. + * + * @param lun: Logical unit number + * + * @param command: command pointer + * + * @retval SCSI_OK or SCSI_FAILL + */ +static uint8_t SCSI_Inquiry(uint8_t lun, uint8_t *command) +{ + uint16_t i; + uint8_t *pInquiryData; + + if (command[1] & 0x01) + { + pInquiryData = (uint8_t *)s_page00InquiryData; + g_BOTInfo.dataLen = s_page00InquiryData[3] + 4; + } + else + { + pInquiryData = &g_storageCallBack.pInquiryData[lun * SCSI_INQUIRY_LENGTH]; + + g_BOTInfo.dataLen = USB_MIN((pInquiryData[4] + 5), command[4]); + } + + for (i = 0; i < g_BOTInfo.dataLen; i++) + { + g_BOTInfo.data[i] = pInquiryData[i]; + } + + return SCSI_OK; +} + +/*! + * @brief SCSI Request Sense handler. + * + * @param lun: Logical unit number + * + * @param command: command pointer + * + * @retval SCSI_OK or SCSI_FAILL + */ +static uint8_t SCSI_RequestSense(uint8_t lun, uint8_t *command) +{ + uint8_t i = 0; + + while (i < SCSI_REQUEST_SENSE_DATA_LEN) + { + g_BOTInfo.data[i++] = 0; + } + + g_BOTInfo.data[0] = 0x70; + g_BOTInfo.data[7] = SCSI_REQUEST_SENSE_DATA_LEN - 6; + + if (g_senseTxCnt != g_sensePutCnt) + { + g_BOTInfo.data[2] = g_scsiSenseCode[g_senseTxCnt].sensekey; + g_BOTInfo.data[12] = g_scsiSenseCode[g_senseTxCnt].ASC; + g_BOTInfo.data[13] = g_scsiSenseCode[g_senseTxCnt].ASCQ; + + if ((++g_senseTxCnt) == SCSI_SENSE_LIST_NUMBER) + { + g_senseTxCnt = 0; + } + } + + g_BOTInfo.dataLen = (SCSI_REQUEST_SENSE_DATA_LEN < command[4]) ? \ + SCSI_REQUEST_SENSE_DATA_LEN : command[4]; + + return SCSI_OK; +} + +/*! + * @brief SCSI Read Format Capacity handler. + * + * @param lun: Logical unit number + * + * @param command: command pointer + * + * @retval SCSI_OK or SCSI_FAILL + */ +static uint8_t SCSI_ReadFormatCapacity(uint8_t lun, uint8_t *command) +{ + uint16_t i = 0; + uint32_t blkSize; + uint32_t blkNbr; + + while (i < 12) + { + g_BOTInfo.data[i++] = 0; + } + + if (g_storageCallBack.ReadCapacity(lun, &blkNbr, &blkSize) != SCSI_OK) + { + SCSI_PutSenseCode(lun, SCSI_SKEY_NOT_READY, + SCSI_ASC_MEDIUM_NOT_PRESENT, 0); + + return SCSI_FAIL; + } + else + { + blkNbr--; + + g_BOTInfo.data[3] = 0x08; + g_BOTInfo.data[4] = (uint8_t)(blkNbr >> 24); + g_BOTInfo.data[5] = (uint8_t)(blkNbr >> 16); + g_BOTInfo.data[6] = (uint8_t)(blkNbr >> 8); + g_BOTInfo.data[7] = (uint8_t)(blkNbr); + g_BOTInfo.data[8] = 0x02; + g_BOTInfo.data[9] = (uint8_t)(blkSize >> 16); + g_BOTInfo.data[10] = (uint8_t)(blkSize >> 8); + g_BOTInfo.data[11] = (uint8_t)blkSize; + + g_BOTInfo.dataLen = 12; + + return SCSI_OK; + } +} + +/*! + * @brief SCSI Read Capacity10 handler. + * + * @param lun: Logical unit number + * + * @param command: command pointer + * + * @retval SCSI_OK or SCSI_FAILL + */ +static uint8_t SCSI_ReadCapacity10(uint8_t lun, uint8_t *command) +{ + if (g_storageCallBack.ReadCapacity(lun, &s_blkNbr, &s_blkSize) != SCSI_OK) + { + SCSI_PutSenseCode(lun, SCSI_SKEY_NOT_READY, + SCSI_ASC_MEDIUM_NOT_PRESENT, 0); + + return SCSI_FAIL; + } + else + { + g_BOTInfo.data[0] = (uint8_t)((s_blkNbr - 1) >> 24); + g_BOTInfo.data[1] = (uint8_t)((s_blkNbr - 1) >> 16); + g_BOTInfo.data[2] = (uint8_t)((s_blkNbr - 1) >> 8); + g_BOTInfo.data[3] = (uint8_t)(s_blkNbr - 1); + g_BOTInfo.data[4] = (uint8_t)(s_blkSize >> 24); + g_BOTInfo.data[5] = (uint8_t)(s_blkSize >> 16); + g_BOTInfo.data[6] = (uint8_t)(s_blkSize >> 8); + g_BOTInfo.data[7] = (uint8_t)(s_blkSize); + + g_BOTInfo.dataLen = 8; + + return SCSI_OK; + } +} + +/*! + * @brief SCSI Read10 handler. + * + * @param lun: Logical unit number + * + * @param command: command pointer + * + * @retval SCSI_OK or SCSI_FAILL + */ +static uint8_t SCSI_Read10(uint8_t lun, uint8_t *command) +{ + uint8_t ret = SCSI_OK; + + if (g_BOTInfo.state == BOT_STATE_IDLE) + { + if ((g_BOTInfo.CBW.bmFlags & 0x80) != 0x80) + { + SCSI_PutSenseCode(g_BOTInfo.CBW.bLUN, SCSI_SKEY_ILLEGAL_REQUEST, + SCSI_ASC_INVALID_CDB, 0); + + return SCSI_FAIL; + } + + if (g_storageCallBack.CheckReady(lun) != SCSI_OK) + { + SCSI_PutSenseCode(lun, SCSI_SKEY_NOT_READY, + SCSI_ASC_MEDIUM_NOT_PRESENT, 0); + + return SCSI_FAIL; + } + + s_blkAddr = ((uint32_t)command[2] << 24) | \ + ((uint32_t)command[3] << 16) | \ + ((uint32_t)command[4] << 8) | \ + (uint32_t)command[5]; + + s_blkLen = ((uint16_t)command[7] << 8 | (uint8_t)command[8]); + + if (SCSI_CheckAddress(lun, s_blkAddr, s_blkLen) != SCSI_OK) + { + return SCSI_FAIL; + } + + g_BOTInfo.state = BOT_STATE_DATA_IN; + s_blkAddr *= s_blkSize; + s_blkLen *= s_blkSize; + + if (g_BOTInfo.CBW.dDataXferLen != s_blkLen) + { + SCSI_PutSenseCode(g_BOTInfo.CBW.bLUN, SCSI_SKEY_ILLEGAL_REQUEST, + SCSI_ASC_INVALID_CDB, 0); + + return SCSI_FAIL; + } + + } + + g_BOTInfo.dataLen = MSC_MEDIA_PACKET; + + ret = SCSI_Read(lun); + + return ret; +} + +/*! + * @brief SCSI write10 handler. + * + * @param lun: Logical unit number + * + * @param command: command pointer + * + * @retval SCSI_OK or SCSI_FAILL + */ +static uint8_t SCSI_Write10(uint8_t lun, uint8_t *command) +{ + uint8_t ret = SCSI_OK; + uint32_t len; + + if (g_BOTInfo.state == BOT_STATE_IDLE) + { + if (g_BOTInfo.CBW.bmFlags & 0x80) + { + SCSI_PutSenseCode(g_BOTInfo.CBW.bLUN, SCSI_SKEY_ILLEGAL_REQUEST, + SCSI_ASC_INVALID_CDB, 0); + + return SCSI_FAIL; + } + + if (g_storageCallBack.CheckReady(lun) != SCSI_OK) + { + SCSI_PutSenseCode(lun, SCSI_SKEY_NOT_READY, + SCSI_ASC_MEDIUM_NOT_PRESENT, 0); + + return SCSI_FAIL; + } + + if (g_storageCallBack.CheckWPR(lun) != SCSI_OK) + { + SCSI_PutSenseCode(lun, SCSI_SKEY_NOT_READY, + SCSI_ASC_WRITE_PROTECTED, 0); + + return SCSI_FAIL; + } + + s_blkAddr = ((uint32_t)command[2] << 24) | \ + ((uint32_t)command[3] << 16) | \ + ((uint32_t)command[4] << 8) | \ + (uint32_t)command[5]; + + s_blkLen = ((uint16_t)command[7] << 8 | (uint8_t)command[8]); + + if (SCSI_CheckAddress(lun, s_blkAddr, s_blkLen) != SCSI_OK) + { + return SCSI_FAIL; + } + + s_blkAddr *= s_blkSize; + s_blkLen *= s_blkSize; + + if (g_BOTInfo.CBW.dDataXferLen != s_blkLen) + { + SCSI_PutSenseCode(g_BOTInfo.CBW.bLUN, SCSI_SKEY_ILLEGAL_REQUEST, + SCSI_ASC_INVALID_CDB, 0); + + return SCSI_FAIL; + } + + g_BOTInfo.state = BOT_STATE_DATA_OUT; + len = USB_MIN(s_blkLen, MSC_MEDIA_PACKET); + + USBD_RxData(MSC_OUT_EP & 0x7F, g_BOTInfo.data, len); + + } + else + { + ret = SCSI_Write(lun); + } + + return ret; +} + +/*! + * @brief SCSI Verify10 Handler. + * + * @param lun: Logical unit number + * + * @param command: command pointer + * + * @retval SCSI_OK or SCSI_FAILL + */ +static uint8_t SCSI_Verify10(uint8_t lun, uint8_t *command) +{ + if (command[1] & 0x02) + { + SCSI_PutSenseCode(lun, SCSI_SKEY_ILLEGAL_REQUEST, + SCSI_ASC_INVALID_FIELED_IN_COMMAND, 0); + + return SCSI_FAIL; + } + + s_blkAddr = ((uint32_t)command[2] << 24) | \ + ((uint32_t)command[3] << 16) | \ + ((uint32_t)command[4] << 8) | \ + (uint32_t)command[5]; + + s_blkLen = ((uint16_t)command[7] << 8 | (uint8_t)command[8]); + + if (SCSI_CheckAddress(lun, s_blkAddr, s_blkLen) != SCSI_OK) + { + return SCSI_FAIL; + } + + g_BOTInfo.dataLen = 0; + + return SCSI_OK; +} + +/*! + * @brief SCSI Start Stop Unit Handler. + * + * @param None + * + * @retval SCSI_OK or SCSI_FAILL + */ +static uint8_t SCSI_StartStopUnit(void) +{ + g_BOTInfo.dataLen = 0; + return SCSI_OK; +} + +/*! + * @brief SCSI Mode Sense6 Handler. + * + * @param lun: Logical unit number + * + * @param command: command pointer + * + * @retval SCSI_OK or SCSI_FAILL + */ +static uint8_t SCSI_ModeSense6(uint8_t lun, uint8_t *command) +{ + for (uint16_t i = 0; i < 8; i++) + { + g_BOTInfo.data[i] = s_modeSense6Data[i]; + } + + g_BOTInfo.dataLen = 8; + + return SCSI_OK; +} + +/*! + * @brief SCSI Mode Sense10 Handler. + * + * @param lun: Logical unit number + * + * @param command: command pointer + * + * @retval SCSI_OK or SCSI_FAILL + */ +static uint8_t SCSI_ModeSense10(uint8_t lun, uint8_t *command) +{ + for (uint16_t i = 0; i < 8; i++) + { + g_BOTInfo.data[i] = s_modeSense10Data[i]; + } + + g_BOTInfo.dataLen = 8; + + return SCSI_OK; +} + +/*! + * @brief SCSI Read Process. + * + * @param lun: Logical unit number + * + * @retval SCSI_OK or SCSI_FAILL + */ +static uint8_t SCSI_Read(uint8_t lun) +{ + uint32_t len = USB_MIN(MSC_MEDIA_PACKET, s_blkLen); + + if (g_storageCallBack.ReadData(len, g_BOTInfo.data, (s_blkAddr / s_blkSize), + (len / s_blkSize)) != SCSI_OK) + { + SCSI_PutSenseCode(lun, SCSI_SKEY_HARDWARE_ERROR, + SCSI_ASC_UNRECOVERED_READ_ERROR, 0); + + return SCSI_FAIL; + } + + USBD_TxData(MSC_IN_EP & 0x7F, g_BOTInfo.data, len); + + s_blkAddr += len; + s_blkLen -= len; + + g_BOTInfo.CSW.dDataResidue -= len; + + if (s_blkLen == 0) + { + g_BOTInfo.state = BOT_STATE_LAST_DATA_IN; + } + + return SCSI_OK; +} + +/*! + * @brief SCSI Write Process. + * + * @param lun: Logical unit number + * + * @retval SCSI_OK or SCSI_FAILL + */ +static uint8_t SCSI_Write(uint8_t lun) +{ + uint32_t len = USB_MIN(MSC_MEDIA_PACKET, s_blkLen); + + if (s_blkLen - len) + { + __NOP(); + } + if (g_storageCallBack.WriteData(lun, g_BOTInfo.data, s_blkAddr / s_blkSize, + len / s_blkSize) != SCSI_OK) + { + SCSI_PutSenseCode(lun, SCSI_SKEY_HARDWARE_ERROR, SCSI_ASC_WRITE_FAULT, 0); + + return SCSI_FAIL; + } + + s_blkAddr += len; + s_blkLen -= len; + + g_BOTInfo.CSW.dDataResidue -= len; + + if (s_blkLen) + { + len = USB_MIN(MSC_MEDIA_PACKET, s_blkLen); + + USBD_RxData(MSC_OUT_EP & 0x7f, g_BOTInfo.data, len); + } + else + { + USBD_MSC_BOT_TxCSW(BOT_CSW_STATUS_CMD_OK); + } + + return SCSI_OK; +} + +/*! + * @brief SCSI Check Address Range. + * + * @param lun: Logical unit number + * + * @param blkOffset: first block address + * + * @param blkNbr: number of block to be processed + * + * @retval SCSI_OK or SCSI_FAILL + */ +static uint8_t SCSI_CheckAddress(uint8_t lun, uint32_t blkOffset, uint16_t blkNbr) +{ + if (s_blkNbr < (blkNbr + blkOffset)) + { + SCSI_PutSenseCode(lun, SCSI_SKEY_ILLEGAL_REQUEST, + SCSI_ASC_ADDRESS_OUT_OF_RANGE, 0); + + return SCSI_FAIL; + } + + return SCSI_OK; +} diff --git a/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Standard/inc/usbd_core.h b/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Standard/inc/usbd_core.h new file mode 100644 index 0000000000..9dcbd79ccb --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Standard/inc/usbd_core.h @@ -0,0 +1,312 @@ +/*! + * @file usbd_core.h + * + * @brief USB protocol core handler head file + * + * @version V1.0.0 + * + * @date 2021-12-06 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +#ifndef __USBD_CORE_H_ +#define __USBD_CORE_H_ + +#include "drv_usb_device.h" + +/** Get minimum value */ +#define USB_MIN(a, b) (a >= b ? b : a) + +/** Get maximum value */ +#define USB_MAX(a, b) (a >= b ? a : b) + +/** + * @brief USB request type + */ +enum +{ + USBD_REQ_TYPE_STANDARD = 0, + USBD_REQ_TYPE_CLASS = 1, + USBD_REQ_TYPE_VENDOR = 2, + USBD_REQ_TYPE_RESERVED = 3 +}; + +/** + * @brief USB recipient + */ +enum +{ + USBD_RECIPIENT_DEVICE = 0, + USBD_RECIPIENT_INTERFACE = 1, + USBD_RECIPIENT_ENDPOINT = 2, + USBD_RECIPIENT_OTHER = 3, +}; + +/** + * @brief USB standard device requests + */ +enum +{ + USBD_GET_STATUS = 0, + USBD_CLEAR_FEATURE = 1, + USBD_SET_FEATURE = 3, + USBD_SET_ADDRESS = 5, + USBD_GET_DESCRIPTOR = 6, + USBD_SET_DESCRIPTOR = 7, + USBD_GET_CONFIGURATION = 8, + USBD_SET_CONFIGURATION = 9, + USBD_GET_INTERFACE = 10, + USBD_SET_INTERFACE = 11, + USBD_SYNCH_FRAME = 12, +}; + +/** + * @brief USB descriptor types + */ +enum +{ + USBD_DESC_DEVICE = 1, + USBD_DESC_CONFIGURATION = 2, + USBD_DESC_STRING = 3, + USBD_DESC_INTERFACE = 4, + USBD_DESC_ENDPOINT = 5, + USBD_DESC_DEVICE_QUALIFIER = 6, + USBD_DESC_OTHER_SPEED = 7, + USBD_INTERFACE_POWER = 8, +}; + +/** + * @brief USB standard feature + */ +enum +{ + USBD_FEATURE_ENDPOINT_HALT = 0, + USBD_FEATURE_REMOTE_WAKEUP = 1, + USBD_FEATURE_TEST_MODE = 2 +}; + +/** + * @brief USB internal state machine + */ +typedef enum +{ + USBD_CTRL_STATE_WAIT_SETUP, + USBD_CTRL_STATE_DATA_IN, + USBD_CTRL_STATE_DATA_OUT, + USBD_CTRL_STATE_WAIT_STATUS_IN, + USBD_CTRL_STATE_WAIT_STATUS_OUT, + USBD_CTRL_STATE_STALLED, +} USBD_CTRL_STATE_T; + +/** + * @brief USBD Endpoint type for USB protocol + */ +typedef enum +{ + USBD_EP_TYPE_CONTROL, + USBD_EP_TYPE_ISO, + USBD_EP_TYPE_BULK, + USBD_EP_TYPE_INTERRUPT +} USBD_EP_TYPE_T; + +/** + * @brief USB request type + */ +typedef union +{ + uint8_t byte; + + struct + { + uint8_t recipient : 5; + uint8_t type : 2; + uint8_t dir : 1; + } bit; +} USBD_REQ_TYPE_T; + +/** + * @brief USB device request data + */ +typedef struct +{ + union + { + uint8_t pack[8]; + + struct + { + USBD_REQ_TYPE_T bmRequestType; + uint8_t bRequest; + uint8_t wValue[2]; + uint8_t wIndex[2]; + uint8_t wLength[2]; + } byte; + }; +} USBD_DevReqData_T; + +/** + * @brief Descriptor structure + */ +typedef struct +{ + const uint8_t *pDesc; + uint8_t size; +} USBD_Descriptor_T; + +/** USB standard request callback handler */ +typedef void (*USBD_StdReqHandler_T)(void); + +/** USB request handler */ +typedef void (*USBD_ReqHandler_T)(USBD_DevReqData_T *); + +/** Ctrl Tx Status handler function define */ +typedef void (*USBD_CtrlTxStatusHandler_T)(void); + +/** Ctrl Rx Status handler function define */ +typedef void (*USBD_CtrlRxStatusHandler_T)(void); + +/** Endpoint handler */ +typedef void (*USBD_EPHandler_T)(uint8_t ep); + +/** Reset handler */ +typedef void (*USBD_ResetHandler_T)(void); + +/** Interrupt handler function define */ +typedef void (*USBD_InterruptHandler_T)(void); + +/** + * @brief USB Class Request handler + */ +typedef struct +{ + USBD_StdReqHandler_T getConfigurationHandler; + USBD_StdReqHandler_T getDescriptorHandler; + USBD_StdReqHandler_T getInterfaceHandler; + USBD_StdReqHandler_T getStatusHandler; + USBD_StdReqHandler_T setAddressHandler; + + USBD_StdReqHandler_T setConfigurationHandler; + USBD_StdReqHandler_T setDescriptorHandler; + USBD_StdReqHandler_T setFeatureHandler; + USBD_StdReqHandler_T setInterfaceHandler; + USBD_StdReqHandler_T clearFeatureHandler; +} USBD_StdReqCallback_T; + +/** + * @brief Control transfer buffer + */ +typedef struct +{ + uint8_t *pBuf; //!< Data buffer + uint32_t bufLen; //!< Length of the data buffer + uint8_t packNum; //!< Packet number of the data + uint8_t zeroPackFill; //!< Fill a zero pack for IN transfer or not + uint16_t maxPackSize; //!< Max pack size of this endpoint + uint32_t xferCnt; //!< Data count of one pack on from tansfer +} USBD_CtrlBuf_T; + +/** + * @brief USB init parameter + */ +typedef struct +{ + USBD_Descriptor_T *pDeviceDesc; //!< Device descriptor pointer + USBD_Descriptor_T *pConfigurationDesc; //!< Configuration descriptor pointer + USBD_Descriptor_T *pStringDesc; //!< String descriptor pointer + USBD_Descriptor_T *pQualifierDesc; //!< Device Qualifier descriptor pointer + USBD_Descriptor_T *pHidReportDesc; //!< HID report descriptor pointer + + + USBD_StdReqCallback_T *pStdReqCallback; + USBD_ReqHandler_T stdReqExceptionHandler; //!< Standard request exception handler + USBD_ReqHandler_T classReqHandler; //!< Class request handler + USBD_ReqHandler_T vendorReqHandler; //!< vendor request handler + + USBD_CtrlTxStatusHandler_T txStatusHandler; //!< Send IN status early handler + USBD_CtrlRxStatusHandler_T rxStatusHandler; //!< Receive OUT status early handler + + USBD_EPHandler_T outEpHandler; //!< OUT EP transfer done handler except EP0 + USBD_EPHandler_T inEpHandler; //!< IN EP transfer done handler except EP0 + USBD_ResetHandler_T resetHandler; //!< Reset handler + USBD_InterruptHandler_T intHandler; //!< Hadler the rest of interrupt. +} USBD_InitParam_T; + +/** + * @brief USB infomation + */ +typedef struct +{ + USBD_CTRL_STATE_T ctrlState; + + uint8_t curFeature; + uint8_t curInterface; + uint8_t curAlternateSetting; + uint8_t curConfiguration; + uint8_t configurationNum; + + /** Setup request data buffer */ + USBD_DevReqData_T reqData; + + /** Endpoint buffer management */ + USBD_CtrlBuf_T inBuf[USB_EP_MAX_NUM]; + USBD_CtrlBuf_T outBuf[USB_EP_MAX_NUM]; + + /** Descriptor pointer */ + USBD_Descriptor_T *pDeviceDesc; + USBD_Descriptor_T *pConfigurationDesc; + USBD_Descriptor_T *pStringDesc; + USBD_Descriptor_T *pQualifierDesc; + USBD_Descriptor_T *pHidReportDesc; + + /** Setup request callback handler */ + USBD_StdReqCallback_T *pStdReqCallback; + USBD_ReqHandler_T stdReqExceptionHandler; + USBD_ReqHandler_T classReqHandler; + USBD_ReqHandler_T vendorReqHandler; + + /** Control transfer status stage handler */ + USBD_CtrlTxStatusHandler_T txStatusHandler; + USBD_CtrlRxStatusHandler_T rxStatusHandler; + + /** Endpoint transfer done handler */ + USBD_EPHandler_T outEpHandler; + USBD_EPHandler_T inEpHandler; + + USBD_ResetHandler_T resetHandler; + USBD_InterruptHandler_T intHandler; +} USBD_Info_T; + +extern USBD_Info_T g_usbDev; + +/** control status function */ +#define USBD_CtrlTxStatus() USBD_CtrlInData(NULL, 0); +#define USBD_CtrlRxStatus() USBD_CtrlOutData(NULL, 0) + +/** Handler Endpoint 0 control transfer */ +void USBD_SetupProcess(void); +void USBD_CtrlInProcess(void); +void USBD_CtrlOutProcess(void); +void USBD_CtrlOutData(uint8_t *buf, uint32_t len); +void USBD_CtrlInData(uint8_t *buf, uint32_t len); + +/** Handler other Endpoint data transfer */ +void USBD_DataInProcess(USBD_EP_T ep); +void USBD_DataOutProcess(USBD_EP_T ep); +void USBD_TxData(uint8_t ep, uint8_t *buf, uint32_t len); +void USBD_RxData(uint8_t ep, uint8_t *buf, uint32_t len); + +#endif diff --git a/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Standard/inc/usbd_init.h b/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Standard/inc/usbd_init.h new file mode 100644 index 0000000000..10cfc459b1 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Standard/inc/usbd_init.h @@ -0,0 +1,64 @@ +/*! + * @file usbd_init.h + * + * @brief USB initialization management head file + * + * @version V1.0.0 + * + * @date 2021-12-06 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +#ifndef USBD_INIT_H_ +#define USBD_INIT_H_ + +#include "usbd_core.h" + +/** + * @brief Endpoint Configuration Info + */ +typedef struct +{ + USBD_EP_T epNum; //!< endpoint number + USBD_EP_TYPE_T epType; //!< endpoint type + uint8_t epKind; /** + * Which could be ENABLE or DISABLE, it is valid only for + * control and bulk Endpoint. The mean of ENABLE for them like : + * 1. Control endpoint : Only for OUT status which is zero data. + * 2. Bulk endpoint : Enable the double-buffer feature + */ + USBD_EP_STATUS_T epStatus; //!< Endpoint status + uint16_t epBufAddr; //!< buffer address for the endpoint + uint16_t maxPackSize; //!< max packet size for the endpoint +} USBD_EPConfig_T; + +/** USB init */ +void USBD_Init(USBD_InitParam_T *param); +void USBD_InitParamStructInit(USBD_InitParam_T *param); + +/** power */ +void USBD_PowerOn(void); +void USBD_PowerOff(void); + +/** Endpoint init */ +void USBD_OpenOutEP(USBD_EPConfig_T *epConfig); +void USBD_OpenInEP(USBD_EPConfig_T *epConfig); + +void USBD_CloseOutEP(USBD_EP_T ep); +void USBD_CloseInEP(USBD_EP_T ep); + +#endif diff --git a/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Standard/inc/usbd_interrupt.h b/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Standard/inc/usbd_interrupt.h new file mode 100644 index 0000000000..5cdf63be88 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Standard/inc/usbd_interrupt.h @@ -0,0 +1,31 @@ +/*! + * @file usbd_interrupt.h + * + * @brief USB interrupt service routine header file + * + * @version V1.0.0 + * + * @date 2021-12-06 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +#ifndef __USBD_INTERRUPT_H_ +#define __USBD_INTERRUPT_H_ + +#include "apm32f10x.h" + +#endif diff --git a/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Standard/inc/usbd_stdReq.h b/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Standard/inc/usbd_stdReq.h new file mode 100644 index 0000000000..c832060350 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Standard/inc/usbd_stdReq.h @@ -0,0 +1,31 @@ +/*! + * @file usbd_stdReq.h + * + * @brief USB standard request process head file + * + * @version V1.0.0 + * + * @date 2021-12-30 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +#ifndef __USBD_STDREQ_H_ +#define __USBD_STDREQ_H_ + +void USBD_StandardReqeust(void); + +#endif diff --git a/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Standard/src/usbd_core.c b/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Standard/src/usbd_core.c new file mode 100644 index 0000000000..653bf5b273 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Standard/src/usbd_core.c @@ -0,0 +1,405 @@ +/*! + * @file usbd_core.c + * + * @brief USB protocol core handler + * + * @version V1.0.0 + * + * @date 2021-12-06 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +#include "usbd_core.h" +#include "usbd_stdReq.h" + +/** USB information */ +USBD_Info_T g_usbDev; + +/*! + * @brief Endpoint 0 Setup process + * + * @param None + * + * @retval None + */ +void USBD_SetupProcess(void) +{ + uint8_t reqType; + uint8_t dataBuf[8]; + USBD_DevReqData_T *pReqData = &g_usbDev.reqData; + uint16_t xferLen = USBD_ReadEPRxCnt(USBD_EP_0); + + if (xferLen) + { + USBD_ReadDataFromEP(USBD_EP_0, (uint8_t *)dataBuf, xferLen); + } + else + { + return; + } + + pReqData->byte.bmRequestType.byte = dataBuf[0]; + pReqData->byte.bRequest = dataBuf[1]; + pReqData->byte.wValue[0] = dataBuf[2]; + pReqData->byte.wValue[1] = dataBuf[3]; + pReqData->byte.wIndex[0] = dataBuf[4]; + pReqData->byte.wIndex[1] = dataBuf[5]; + pReqData->byte.wLength[0] = dataBuf[6]; + pReqData->byte.wLength[1] = dataBuf[7]; + + reqType = pReqData->byte.bmRequestType.bit.type; + + if (reqType == USBD_REQ_TYPE_STANDARD) + { + USBD_StandardReqeust(); + } + else if (reqType == USBD_REQ_TYPE_CLASS) + { + if (g_usbDev.classReqHandler) + { + g_usbDev.classReqHandler(pReqData); + } + } + else if (reqType == USBD_REQ_TYPE_VENDOR) + { + if (g_usbDev.vendorReqHandler) + { + g_usbDev.vendorReqHandler(pReqData); + } + } + else + { + USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_STALL, USBD_EP_STATUS_STALL); + } +} + + +/*! + * @brief Endpoint 0 USB Control in process + * + * @param None + * + * @retval None + */ +void USBD_CtrlInProcess(void) +{ + uint32_t tmp; + + if (g_usbDev.ctrlState == USBD_CTRL_STATE_DATA_IN) + { + if (g_usbDev.inBuf[0].packNum) + { + tmp = USB_MIN(g_usbDev.inBuf[0].bufLen, g_usbDev.inBuf[0].maxPackSize); + + USBD_WriteDataToEP(USBD_EP_0, g_usbDev.inBuf[0].pBuf, tmp); + USBD_SetEPTxCnt(USBD_EP_0, tmp); + USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_VALID, USBD_EP_STATUS_NAK); + + g_usbDev.inBuf[0].pBuf += tmp; + g_usbDev.inBuf[0].bufLen -= tmp; + g_usbDev.inBuf[0].packNum--; + } + else + { + if (g_usbDev.inBuf[USBD_EP_0].zeroPackFill) + { + USBD_SetEPTxCnt(USBD_EP_0, 0); + USBD_SetEPTxStatus(USBD_EP_0, USBD_EP_STATUS_VALID); + g_usbDev.inBuf[USBD_EP_0].zeroPackFill = 0; + } + else + { + if (g_usbDev.rxStatusHandler) + { + g_usbDev.rxStatusHandler(); + } + + g_usbDev.ctrlState = USBD_CTRL_STATE_WAIT_STATUS_OUT; + USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_NAK, USBD_EP_STATUS_VALID); + } + + } + } + else if (g_usbDev.ctrlState == USBD_CTRL_STATE_WAIT_STATUS_IN) + { + if (g_usbDev.reqData.byte.bRequest == USBD_SET_ADDRESS) + { + USBD_SetDeviceAddr(g_usbDev.reqData.byte.wValue[0]); + } + } +} + +/*! + * @brief Endpoint 0 USB Control out process + * + * @param None + * + * @retval None + */ +void USBD_CtrlOutProcess(void) +{ + uint32_t len; + + if (g_usbDev.ctrlState == USBD_CTRL_STATE_DATA_OUT) + { + if (g_usbDev.outBuf[0].packNum) + { + len = USB_MIN(g_usbDev.outBuf[0].bufLen, g_usbDev.outBuf[0].maxPackSize); + + USBD_ReadDataFromEP(USBD_EP_0, g_usbDev.outBuf[0].pBuf, len); + + g_usbDev.outBuf[0].bufLen -= len; + g_usbDev.outBuf[0].pBuf += len; + g_usbDev.outBuf[0].packNum--; + + if (g_usbDev.outBuf[0].packNum) + { + USBD_CtrlOutData(g_usbDev.outBuf[0].pBuf, g_usbDev.outBuf[0].bufLen); + } + else + { + USBD_CtrlTxStatus(); + } + } + else + { + if (g_usbDev.txStatusHandler) + { + g_usbDev.txStatusHandler(); + } + + USBD_CtrlTxStatus(); + } + } +} + +/*! + * @brief Send data or status in control in transation + * + * @param buf: Buffer pointer + * + * @param len: Buffer length + * + * @retval None + */ +void USBD_CtrlInData(uint8_t *buf, uint32_t len) +{ + uint16_t maxPackSize = g_usbDev.inBuf[0].maxPackSize; + uint16_t reqLen = *(uint16_t *)g_usbDev.reqData.byte.wLength; + + if (len) + { + if ((len < reqLen) && ((len % maxPackSize) == 0)) + { + g_usbDev.inBuf[USBD_EP_0].zeroPackFill = 1; + } + + if (len >= g_usbDev.inBuf[0].maxPackSize) + { + /** Send a packet */ + USBD_WriteDataToEP(USBD_EP_0, buf, g_usbDev.inBuf[0].maxPackSize); + USBD_SetEPTxCnt(USBD_EP_0, g_usbDev.inBuf[0].maxPackSize); + USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_VALID, USBD_EP_STATUS_NAK); + + /** deal with buffer */ + g_usbDev.inBuf[0].bufLen = len - g_usbDev.inBuf[0].maxPackSize; + g_usbDev.inBuf[0].pBuf = buf + g_usbDev.inBuf[0].maxPackSize; + g_usbDev.inBuf[0].packNum = (g_usbDev.inBuf[0].bufLen + (maxPackSize - 1)) / maxPackSize; + + g_usbDev.ctrlState = USBD_CTRL_STATE_DATA_IN; + } + else + { + USBD_WriteDataToEP(USBD_EP_0, buf, len); + USBD_SetEPTxCnt(USBD_EP_0, len); + USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_VALID, USBD_EP_STATUS_NAK); + + g_usbDev.ctrlState = g_usbDev.reqData.byte.bmRequestType.bit.dir ? \ + USBD_CTRL_STATE_DATA_IN : \ + USBD_CTRL_STATE_WAIT_STATUS_IN; + } + } + else + { + USBD_SetEPTxCnt(USBD_EP_0, 0); + USBD_SetEPTxStatus(USBD_EP_0, USBD_EP_STATUS_VALID); + + g_usbDev.ctrlState = g_usbDev.reqData.byte.bmRequestType.bit.dir ? \ + USBD_CTRL_STATE_DATA_IN : \ + USBD_CTRL_STATE_WAIT_STATUS_IN; + } +} + +/*! + * @brief Read data or status in control out transation + * + * @param buf: Buffer pointer + * + * @param len: Buffer length + * + * @retval None + */ +void USBD_CtrlOutData(uint8_t *buf, uint32_t len) +{ + uint16_t maxPackSize = g_usbDev.outBuf[USBD_EP_0].maxPackSize; + + if (len) + { + g_usbDev.outBuf[USBD_EP_0].pBuf = buf; + g_usbDev.outBuf[USBD_EP_0].bufLen = len; + g_usbDev.outBuf[USBD_EP_0].packNum = (len + (maxPackSize - 1)) / maxPackSize; + + len = USB_MIN(g_usbDev.outBuf[0].bufLen, maxPackSize); + + USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_NAK, USBD_EP_STATUS_VALID); + + g_usbDev.ctrlState = USBD_CTRL_STATE_DATA_OUT; + } + else + { + g_usbDev.ctrlState = USBD_CTRL_STATE_WAIT_STATUS_OUT; + } + + USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_NAK, USBD_EP_STATUS_VALID); +} + +/*! + * @brief USB Data in process except endpoint 0 + * + * @param ep : endpoint Number except endpoint 0 + * + * @retval None + */ +void USBD_DataInProcess(USBD_EP_T ep) +{ + uint16_t len; + + if (g_usbDev.inBuf[ep].packNum) + { + len = g_usbDev.inBuf[ep].bufLen > g_usbDev.inBuf[ep].maxPackSize ? \ + g_usbDev.inBuf[ep].maxPackSize : g_usbDev.inBuf[ep].bufLen; + + + USBD_WriteDataToEP(ep, g_usbDev.inBuf[ep].pBuf, len); + USBD_SetEPTxCnt(ep, len); + USBD_SetEPTxStatus(ep, USBD_EP_STATUS_VALID); + + g_usbDev.inBuf[ep].pBuf += len; + g_usbDev.inBuf[ep].bufLen -= len; + g_usbDev.inBuf[ep].packNum--; + } + else + { + if (g_usbDev.inEpHandler) + { + g_usbDev.inEpHandler(ep); + } + } +} + +/*! + * @brief USB Data out process except endpoint 0 + * + * @param ep : endpoint Number except endpoint 0 + * + * @retval None + */ +void USBD_DataOutProcess(USBD_EP_T ep) +{ + if (g_usbDev.outBuf[ep].packNum) + { + g_usbDev.outBuf[ep].xferCnt = USBD_ReadEPRxCnt(ep); + + if ((g_usbDev.outBuf[ep].xferCnt != 0) && (g_usbDev.outBuf[ep].pBuf != NULL)) + { + USBD_ReadDataFromEP(ep, g_usbDev.outBuf[ep].pBuf, g_usbDev.outBuf[ep].xferCnt); + + g_usbDev.outBuf[ep].bufLen -= g_usbDev.outBuf[ep].xferCnt; + g_usbDev.outBuf[ep].pBuf += g_usbDev.outBuf[ep].xferCnt; + g_usbDev.outBuf[ep].packNum--; + } + if (g_usbDev.outBuf[ep].packNum) + { + USBD_SetEPRxStatus(ep, USBD_EP_STATUS_VALID); + } + } + + if (g_usbDev.outEpHandler && !g_usbDev.outBuf[ep].packNum) + { + g_usbDev.outEpHandler(ep); + } +} + +/*! + * @brief Transfer data to host(except endpoint 0) + * + * @param ep: Endpoint number except endpoint 0 + * + * @param buf: Buffer pointer + * + * @param len: Buffer length + * + * @retval None + */ +void USBD_TxData(uint8_t ep, uint8_t *buf, uint32_t len) +{ + uint16_t maxPackSize = g_usbDev.inBuf[ep].maxPackSize; + + if (len >= maxPackSize) + { + USBD_WriteDataToEP(ep, buf, maxPackSize); + USBD_SetEPTxCnt(ep, maxPackSize); + USBD_SetEPTxStatus(ep, USBD_EP_STATUS_VALID); + + g_usbDev.inBuf[ep].pBuf = buf + maxPackSize; + g_usbDev.inBuf[ep].bufLen = len - maxPackSize; + g_usbDev.inBuf[ep].packNum = (g_usbDev.inBuf[ep].bufLen + (maxPackSize - 1)) / maxPackSize; + } + else + { + USBD_WriteDataToEP(ep, buf, len); + USBD_SetEPTxCnt(ep, len); + USBD_SetEPTxStatus(ep, USBD_EP_STATUS_VALID); + + g_usbDev.inBuf[ep].packNum = 0; + g_usbDev.inBuf[ep].bufLen = 0; + } +} + +/*! + * @brief Receive data from host(except endpoint 0) + * + * @param ep: Endpoint number except endpoint 0 + * + * @param buf: Buffer pointer + * + * @param len: Buffer length + * + * @retval None + */ +void USBD_RxData(uint8_t ep, uint8_t *buf, uint32_t len) +{ + uint16_t maxPackSize = g_usbDev.outBuf[ep].maxPackSize; + + g_usbDev.outBuf[ep].pBuf = buf; + g_usbDev.outBuf[ep].bufLen = len; + g_usbDev.outBuf[ep].packNum = (len + (maxPackSize - 1)) / maxPackSize; + + USBD_SetEPRxCnt(ep, USB_MIN(len, maxPackSize)); + + USBD_SetEPRxStatus(ep, USBD_EP_STATUS_VALID); +} diff --git a/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Standard/src/usbd_init.c b/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Standard/src/usbd_init.c new file mode 100644 index 0000000000..08a217efd2 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Standard/src/usbd_init.c @@ -0,0 +1,237 @@ +/*! + * @file usbd_init.c + * + * @brief USB initialization management + * + * @version V1.0.0 + * + * @date 2021-12-06 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +#include "usbd_init.h" +#include "usb_bsp.h" + +static USBD_REG_EP_TYPE_T USBD_ConvertEPType(USBD_EP_TYPE_T epType); + +/*! + * @brief USB initialization + * + * @param param: Initialization parameter + * + * @retval None + */ +void USBD_Init(USBD_InitParam_T *param) +{ + g_usbDev.pDeviceDesc = param->pDeviceDesc; + g_usbDev.pConfigurationDesc = param->pConfigurationDesc; + g_usbDev.pStringDesc = param->pStringDesc; + g_usbDev.pQualifierDesc = param->pQualifierDesc; + g_usbDev.pHidReportDesc = param->pHidReportDesc; + + g_usbDev.pStdReqCallback = param->pStdReqCallback; + g_usbDev.classReqHandler = param->classReqHandler; + g_usbDev.vendorReqHandler = param->vendorReqHandler; + g_usbDev.stdReqExceptionHandler = param->stdReqExceptionHandler; + + g_usbDev.txStatusHandler = param->txStatusHandler; + g_usbDev.rxStatusHandler = param->rxStatusHandler; + + g_usbDev.inEpHandler = param->inEpHandler; + g_usbDev.outEpHandler = param->outEpHandler; + + g_usbDev.resetHandler = param->resetHandler; + g_usbDev.intHandler = param->intHandler; + + USBD_HardWareInit(); + +#ifndef APM32F0xx_USB +#if USB_SELECT == USB1 + USBD2_Disable(); +#else + USB2_Enable(); +#endif +#endif + + USBD_PowerOn(); +} + +/*! + * @brief Init parameter in param + * + * @param param: Initialization parameter + * + * @retval None + */ +void USBD_InitParamStructInit(USBD_InitParam_T *param) +{ + param->pStdReqCallback = NULL; + param->stdReqExceptionHandler = NULL; + param->classReqHandler = NULL; + param->vendorReqHandler = NULL; + + param->txStatusHandler = NULL; + param->rxStatusHandler = NULL; + + param->outEpHandler = NULL; + param->inEpHandler = NULL; + + param->resetHandler = NULL; + param->intHandler = NULL; +} + +/*! + * @brief USB Power on + * + * @param None + * + * @retval None + */ +void USBD_PowerOn(void) +{ + USBD_ResetPowerDown(); + + USBD_SetForceReset(); + USBD_ResetForceReset(); + + USBD_DisableInterrupt(USBD_INT_ALL); + USBD_ClearIntFlag(USBD_INT_ALL); + + USBD_EnableInterrupt(USB_INT_SOURCE); +} + +/*! + * @brief USB Power off + * + * @param None + * + * @retval None + */ +void USBD_PowerOff(void) +{ + USBD_DisableInterrupt(USBD_INT_ALL); + USBD_ClearIntFlag(USBD_INT_ALL); + + /** Power down and Force USB Reset */ + USBD_SetRegCTRL(0X03); +} + + +/*! + * @brief Open OUT endpoint. + * + * @param epConfig: Point to USBD_EPConfig_T structure + * + * @retval None + */ +void USBD_OpenOutEP(USBD_EPConfig_T *epConfig) +{ + g_usbDev.outBuf[epConfig->epNum].maxPackSize = epConfig->maxPackSize; + + USBD_SetEPType(epConfig->epNum, USBD_ConvertEPType(epConfig->epType)); + + if (epConfig->epKind) + { + USBD_SetEPKind(epConfig->epNum); + } + else + { + USBD_ResetEPKind(epConfig->epNum); + } + + USBD_SetEPRxAddr(epConfig->epNum, epConfig->epBufAddr); + USBD_SetEPRxCnt(epConfig->epNum, epConfig->maxPackSize); + USBD_SetEPRxStatus(epConfig->epNum, epConfig->epStatus); +} + +/*! + * @brief Open IN endpoint. + * + * @param epConfig: Point to USBD_EPConfig_T structure + * + * @retval None + */ +void USBD_OpenInEP(USBD_EPConfig_T *epConfig) +{ + g_usbDev.inBuf[epConfig->epNum].maxPackSize = epConfig->maxPackSize; + + USBD_SetEPType(epConfig->epNum, USBD_ConvertEPType(epConfig->epType)); + + if (epConfig->epKind) + { + USBD_SetEPKind(epConfig->epNum); + } + else + { + USBD_ResetEPKind(epConfig->epNum); + } + + USBD_SetEPTxAddr(epConfig->epNum, epConfig->epBufAddr); + USBD_SetEPTxStatus(epConfig->epNum, epConfig->epStatus); +} + +/*! + * @brief Close OUT endpoint. + * + * @param ep: OUT endpoint Number + * + * @retval None + */ +void USBD_CloseOutEP(USBD_EP_T ep) +{ + g_usbDev.outBuf[ep].maxPackSize = 0; + + USBD_SetEPRxStatus(ep, USBD_EP_STATUS_DISABLE); +} + +/*! + * @brief Close IN endpoint. + * + * @param ep: IN endpoint Number + * + * @retval None + */ +void USBD_CloseInEP(USBD_EP_T ep) +{ + g_usbDev.inBuf[ep].maxPackSize = 0; + + USBD_SetEPTxStatus(ep, USBD_EP_STATUS_DISABLE); +} + +/*! + * @brief Convert endpoint Type. + * + * @param epType: endpoint type + * + * @retval Value of USBD_REG_EP_TYPE_T + */ +static USBD_REG_EP_TYPE_T USBD_ConvertEPType(USBD_EP_TYPE_T epType) +{ + switch (epType) + { + case USBD_EP_TYPE_CONTROL : + return USBD_REG_EP_TYPE_CONTROL; + case USBD_EP_TYPE_ISO : + return USBD_REG_EP_TYPE_ISO; + case USBD_EP_TYPE_BULK : + return USBD_REG_EP_TYPE_BULK; + case USBD_EP_TYPE_INTERRUPT : + return USBD_REG_EP_TYPE_INTERRUPT; + default : + return USBD_REG_EP_TYPE_CONTROL; + } +} diff --git a/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Standard/src/usbd_interrupt.c b/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Standard/src/usbd_interrupt.c new file mode 100644 index 0000000000..fff3b7c473 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Standard/src/usbd_interrupt.c @@ -0,0 +1,349 @@ +/*! + * @file usbd_interrupt.c + * + * @brief USB interrupt service routine + * + * @version V1.0.0 + * + * @date 2021-12-06 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +#include "usbd_init.h" + +static void USBD_LowPriorityProc(void); + +static void USBD_ResetIsrHandler(void); +static void USBD_SuspendIsrHandler(void); +static void USBD_ResumeIsrHandler(void); + +/*! + * @brief USB interrupt service routine + * + * @param None + * + * @retval None + */ +#ifdef APM32F0xx_USB + void USB_IRQHandler(void) + +#else //!< APM32F10x_USB + #if USB_SELECT == USB1 + void USBD1_LP_CAN1_RX0_IRQHandler(void) + #else + void USB2_LP_IRQHandler(void) + #endif +#endif +{ +#if (USB_INT_SOURCE & USBD_INT_CTR) + if (USBD_ReadIntFlag(USBD_INT_CTR)) + { + USBD_LowPriorityProc(); + } +#endif + +#if (USB_INT_SOURCE & USBD_INT_RST) + if (USBD_ReadIntFlag(USBD_INT_RST)) + { + USBD_ClearIntFlag(USBD_INT_RST); + USBD_ResetIsrHandler(); + } +#endif + +#if USB_INT_SOURCE & USBD_INT_PMAOU + if (USB_ReadIntFlag(USB_INT_PMAOU)) + { + USB_ClearIntFlag(USB_INT_PMAOU); + } +#endif + +#if USB_INT_SOURCE & USBD_INT_ERR + + if (USB_ReadIntFlag(USB_INT_ERROR)) + { + USB_ClearIntFlag(USB_INT_ERROR); + } +#endif + +#if USB_INT_SOURCE & USBD_INT_WKUP + if (USBD_ReadIntFlag(USBD_INT_WKUP)) + { + USBD_ResumeIsrHandler(); + USBD_ClearIntFlag(USBD_INT_WKUP); + } +#endif + +#if USB_INT_SOURCE & USBD_INT_SUS + if (USBD_ReadIntFlag(USBD_INT_SUS)) + { + USBD_SuspendIsrHandler(); + USBD_ClearIntFlag(USBD_INT_SUS); + } +#endif + +#if USB_INT_SOURCE & USBD_INT_SOF + if (USB_ReadIntFlag(USB_INT_SOF)) + { + USB_ClearIntFlag(USB_INT_SOF); + } +#endif + +#if USB_INT_SOURCE & USBD_INT_ESOF + if (USB_ReadIntFlag(USB_INT_ESOF)) + { + USB_ClearIntFlag(USB_INT_ESOF); + } +#endif +} + +/*! + * @brief USB low priority process + * + * @param None + * + * @retval None + */ +static void USBD_LowPriorityProc(void) +{ + USBD_EP_T ep; + + while (USBD_ReadIntFlag(USBD_INT_CTR)) + { + ep = (USBD_EP_T)USBD_ReadEP(); + + /** Endpoint 0 */ + if (ep == 0) + { + USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_NAK, USBD_EP_STATUS_NAK); + + /** Control in */ + if (USBD_ReadDir() == 0) + { + USBD_ResetEPTxFlag(USBD_EP_0); + USBD_CtrlInProcess(); + } + else + { + /** Setup */ + if (USBD_ReadEPSetup(USBD_EP_0) == SET) + { + USBD_ResetEPRxFlag(USBD_EP_0); + USBD_SetupProcess(); + } + /** Control out */ + else + { + USBD_ResetEPRxFlag(USBD_EP_0); + USBD_CtrlOutProcess(); + } + } + } + /** Transfer Handler Except endpoint 0 */ + else + { + if (USBD_ReadEPRxFlag(ep)) + { + USBD_ResetEPRxFlag(ep); + USBD_DataOutProcess(ep); + } + + if (USBD_ReadEPTxFlag(ep)) + { + USBD_ResetEPTxFlag(ep); + USBD_DataInProcess(ep); + } + } + } +} + + +/*! + * @brief USB Device Reset + * + * @param None + * + * @retval None + */ +static void USBD_ResetIsrHandler(void) +{ + uint8_t i; + USBD_EPConfig_T epConfig; + + g_usbDev.configurationNum = USB_CONFIGURATION_NUM; + g_usbDev.curConfiguration = 0; + g_usbDev.curInterface = 0; + g_usbDev.curAlternateSetting = 0; + g_usbDev.curFeature = 0; + g_usbDev.ctrlState = USBD_CTRL_STATE_WAIT_SETUP; + + g_usbDev.inBuf[USBD_EP_0].maxPackSize = USB_EP0_PACKET_SIZE; + g_usbDev.outBuf[USBD_EP_0].maxPackSize = USB_EP0_PACKET_SIZE; + + USBD_SetBufferTable(USB_BUFFER_TABLE_ADDR); + + /** Endpoint 0 IN */ + epConfig.epNum = USBD_EP_0; + epConfig.epType = USBD_EP_TYPE_CONTROL; + epConfig.epKind = DISABLE; + epConfig.epBufAddr = USB_EP0_TX_ADDR; + epConfig.maxPackSize = g_usbDev.inBuf[USBD_EP_0].maxPackSize; + epConfig.epStatus = USBD_EP_STATUS_NAK; + USBD_OpenInEP(&epConfig); + + /** Endpoint 0 OUT */ + epConfig.epBufAddr = USB_EP0_RX_ADDR; + epConfig.maxPackSize = g_usbDev.outBuf[USBD_EP_0].maxPackSize; + epConfig.epStatus = USBD_EP_STATUS_VALID; + USBD_OpenOutEP(&epConfig); + + if (g_usbDev.resetHandler) + { + g_usbDev.resetHandler(); + } + + for (i = 0; i < USB_EP_MAX_NUM; i++) + { + USBD_SetEpAddr((USBD_EP_T)i, i); + } + + USBD_SetDeviceAddr(0); + USBD_Enable(); +} + +/*! + * @brief USB Suspend + * + * @param None + * + * @retval None + */ +static void USBD_SuspendIsrHandler(void) +{ + uint8_t i; + uint16_t bakEP[8]; +#if USB_LOW_POWER_SWITCH + uint32_t bakPwrCR; + uint32_t tmp; +#endif + + for (i = 0; i < 8; i++) + { + bakEP[i] = (uint16_t)USBD->EP[i].EP; + } + + USBD_EnableInterrupt(USBD_INT_RST); + + USBD_SetForceReset(); + USBD_ResetForceReset(); + + while (USBD_ReadIntFlag(USBD_INT_RST) == RESET); + + for (i = 0; i < 8; i++) + { + USBD->EP[i].EP = bakEP[i]; + } + + USBD_SetForceSuspend(); + +#if USB_LOW_POWER_SWITCH + USBD_SetLowerPowerMode(); + + bakPwrCR = PMU->CTRL; + tmp = PMU->CTRL; + tmp &= (uint32_t)0xfffffffc; + tmp |= PMU_REGULATOR_LOWPOWER; + PMU->CTRL = tmp; + + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + if (USBD_ReadIntFlag(USBD_INT_WKUP) == RESET) + { + __WFI(); + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); + } + else + { + USBD_ClearIntFlag(USBD_INT_WKUP); + USBD_ResetForceSuspend(); + PMU->CTRL = bakPwrCR; + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); + } +#endif +} + +/*! + * @brief Resume + * + * @param None + * + * @retval None + */ +static void USBD_ResumeIsrHandler(void) +{ +#if USB_LOW_POWER_SWITCH + USBD_ResetLowerPowerMode(); +#endif + + SystemInit(); + + USBD_SetRegCTRL(USB_INT_SOURCE); +} + +#ifndef APM32F0xx_USB +/*! + * @brief USB High priority process + * + * @param None + * + * @retval None + */ +static void USBD_HighPriorityProc(void) +{ + USBD_EP_T ep; + + while (USBD_ReadIntFlag(USBD_INT_CTR)) + { + USBD_ClearIntFlag(USBD_INT_CTR); + + ep = USBD_ReadEP(); + + if (USBD_ReadEPRxFlag(ep)) + { + USBD_ResetEPRxFlag(ep); + + g_usbDev.outEpHandler(ep); + } + + if (USBD_ReadEPTxFlag(ep)) + { + USBD_ResetEPTxFlag(ep); + + g_usbDev.inEpHandler(ep); + } + } +} + +#if USB_SELECT == USB1 + void USBD1_HP_CAN1_TX_IRQHandler(void) +#else + void USB2_HP_IRQHandler(void) +#endif +{ + USBD_HighPriorityProc(); +} + +#endif diff --git a/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Standard/src/usbd_stdReq.c b/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Standard/src/usbd_stdReq.c new file mode 100644 index 0000000000..98f50c3743 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Standard/src/usbd_stdReq.c @@ -0,0 +1,369 @@ +/*! + * @file usbd_stdReq.c + * + * @brief USB standard request process + * + * @version V1.0.0 + * + * @date 2021-12-30 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +#include "usbd_stdReq.h" +#include "usbd_core.h" +#include "usbd_descriptor.h" + +static uint8_t USBD_StandardGetConfiguration(void); +static uint8_t USBD_StandardGetDescriptor(void); +static uint8_t USBD_StandardGetInterface(void); +static uint8_t USBD_StandardGetStatus(void); + +static uint8_t USBD_StandardSetAddress(void); +static uint8_t USBD_StandardSetConfiguration(void); +static uint8_t USBD_StandardSetDescriptor(void); +static uint8_t USBD_StandardSetFeature(void); +static uint8_t USBD_StandardSetInterface(void); + +static uint8_t USBD_StandardClearFeature(void); + + +/*! + * @brief USB request standard request + * + * @param None + * + * @retval None + */ +void USBD_StandardReqeust(void) +{ + uint8_t result = 1; + + uint8_t bRequest = g_usbDev.reqData.byte.bRequest; + + switch (bRequest) + { + case USBD_GET_CONFIGURATION: + result = USBD_StandardGetConfiguration(); + break; + + case USBD_GET_DESCRIPTOR: + result = USBD_StandardGetDescriptor(); + break; + + case USBD_GET_INTERFACE: + result = USBD_StandardGetInterface(); + break; + + case USBD_GET_STATUS: + result = USBD_StandardGetStatus(); + break; + + case USBD_SET_ADDRESS: + result = USBD_StandardSetAddress(); + break; + + case USBD_SET_CONFIGURATION: + result = USBD_StandardSetConfiguration(); + break; + + case USBD_SET_DESCRIPTOR: + result = USBD_StandardSetDescriptor(); + break; + + case USBD_SET_FEATURE: + result = USBD_StandardSetFeature(); + break; + + case USBD_SET_INTERFACE: + result = USBD_StandardSetInterface(); + + break; + + case USBD_CLEAR_FEATURE: + result = USBD_StandardClearFeature(); + break; + + default: + + break; + } + + if (!result) + { + if (g_usbDev.stdReqExceptionHandler != NULL) + { + g_usbDev.stdReqExceptionHandler(&g_usbDev.reqData); + } + } +} + +/*! + * @brief Standard request get configuration + * + * @param None + * + * @retval ERROR: 0; SUCCESS : 1 + */ +static uint8_t USBD_StandardGetConfiguration(void) +{ + uint8_t recipient = g_usbDev.reqData.byte.bmRequestType.bit.recipient; + + if (recipient == USBD_RECIPIENT_DEVICE) + { + USBD_CtrlInData(&g_usbDev.curConfiguration, 1); + + if (g_usbDev.pStdReqCallback->getConfigurationHandler) + { + g_usbDev.pStdReqCallback->getConfigurationHandler(); + } + + + return SUCCESS; + } + + return ERROR; +} + +/*! + * @brief Standard request get descriptor + * + * @param None + * + * @retval ERROR: 0; SUCCESS : 1 + */ +static uint8_t USBD_StandardGetDescriptor(void) +{ + uint8_t ret = SUCCESS; + uint32_t len = 0; + uint8_t wValue0 = g_usbDev.reqData.byte.wValue[0]; + uint8_t wValue1 = g_usbDev.reqData.byte.wValue[1]; + + if (wValue1 == USBD_DESC_DEVICE) + { + len = USB_MIN(*(uint16_t *)g_usbDev.reqData.byte.wLength, g_usbDev.pDeviceDesc->size); + USBD_CtrlInData((uint8_t *)g_usbDev.pDeviceDesc->pDesc, len); + } + else if (wValue1 == USBD_DESC_CONFIGURATION) + { + len = USB_MIN(*(uint16_t *)g_usbDev.reqData.byte.wLength, g_usbDev.pConfigurationDesc->size); + USBD_CtrlInData((uint8_t *)g_usbDev.pConfigurationDesc->pDesc, len); + } + else if (wValue1 == USBD_DESC_STRING) + { + if (wValue0 < SRTING_DESC_NUM) + { + len = USB_MIN(*(uint16_t *)g_usbDev.reqData.byte.wLength, g_usbDev.pStringDesc[wValue0].size); + USBD_CtrlInData((uint8_t *)g_usbDev.pStringDesc[wValue0].pDesc, len); + } + else + { + ret = ERROR; + USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_STALL, USBD_EP_STATUS_STALL); + } + + } + else + { + ret = ERROR; + USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_STALL, USBD_EP_STATUS_STALL); + } + + return ret; +} + +/*! + * @brief Standard request get interface + * + * @param None + * + * @retval ERROR: 0; SUCCESS : 1 + */ +static uint8_t USBD_StandardGetInterface(void) +{ + + return ERROR; +} + +/*! + * @brief Standard request get status + * + * @param None + * + * @retval ERROR: 0; SUCCESS : 1 + */ +static uint8_t USBD_StandardGetStatus(void) +{ + uint8_t ret = 1; + + + uint8_t status[2] = {0, 0}; + + if ((g_usbDev.reqData.byte.bmRequestType.bit.recipient) == USBD_RECIPIENT_DEVICE) + { + if (g_usbDev.curFeature & (1 << 5)) + { + status[0] |= 0x02; + } + + if (g_usbDev.curFeature & (1 << 6)) + { + status[0] |= 0x01; + } + + USBD_CtrlInData(status, 2); + + + } + + else if ((g_usbDev.reqData.byte.bmRequestType.bit.recipient) == USBD_RECIPIENT_INTERFACE) + { + USBD_CtrlInData(status, 2); + + + } + + else if ((g_usbDev.reqData.byte.bmRequestType.bit.recipient) == USBD_RECIPIENT_ENDPOINT) + { + + if (g_usbDev.reqData.byte.wIndex[0] & 0x80) + { + if (USBD_ReadEPTxStatus(g_usbDev.reqData.byte.wIndex[0] & 0x0f) == USBD_EP_STATUS_STALL) + { + status[0] |= 0x01; + } + } + else + { + if (USBD_ReadEPRxStatus(g_usbDev.reqData.byte.wIndex[0] & 0x0f) == USBD_EP_STATUS_STALL) + { + status[0] |= 0x01; + } + + } + USBD_CtrlInData(status, 2); + + } + else + { + ret = 0; + } + + return ret; +} + +/*! + * @brief Standard request set address + * + * @param None + * + * @retval ERROR: 0; SUCCESS : 1 + */ +static uint8_t USBD_StandardSetAddress(void) +{ + USBD_DevReqData_T *reqData = &g_usbDev.reqData; + + if ((reqData->byte.wValue[0] < 127) && (reqData->byte.wValue[1] == 0) && + (reqData->byte.bmRequestType.bit.recipient == USBD_RECIPIENT_DEVICE)) + { + USBD_CtrlInData((void *)0, 0); + + return 1; + } + + return 0; +} + +/*! + * @brief Standard request set configuration + * + * @param None + * + * @retval ERROR: 0; SUCCESS : 1 + */ +static uint8_t USBD_StandardSetConfiguration(void) +{ + USBD_DevReqData_T *reqData = &g_usbDev.reqData; + + if ((reqData->byte.wValue[0] <= g_usbDev.configurationNum) && \ + (reqData->byte.bmRequestType.bit.recipient == USBD_RECIPIENT_DEVICE)) + { + g_usbDev.curConfiguration = reqData->byte.wValue[0]; + + if (g_usbDev.pStdReqCallback->setConfigurationHandler) + { + g_usbDev.pStdReqCallback->setConfigurationHandler(); + } + + USBD_CtrlInData((void *)0, 0); + + return 1; + } + + return 0; +} + +/*! + * @brief Standard request set descriptor + * + * @param None + * + * @retval 0: Failed; 1: Success + */ +static uint8_t USBD_StandardSetDescriptor(void) +{ + + return ERROR; +} + +/*! + * @brief Standard request set feature + * + * @param None + * + * @retval 0: Failed; 1: Success + */ +static uint8_t USBD_StandardSetFeature(void) +{ + uint8_t ret = 1; + + return ret; +} + +/*! + * @brief Standard request set interface + * + * @param None + * + * @retval 0: Failed; 1: Success + */ +static uint8_t USBD_StandardSetInterface(void) +{ + + return 0; +} + +/*! + * @brief Standard request clear feature + * + * @param None + * + * @retval 0: Failed; 1: Success + */ +static uint8_t USBD_StandardClearFeature(void) +{ + return 0; +} diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_usb.h b/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Driver/inc/drv_usb_device.h similarity index 53% rename from bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_usb.h rename to bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Driver/inc/drv_usb_device.h index 570c0e30a1..96aacf6fa9 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_usb.h +++ b/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Driver/inc/drv_usb_device.h @@ -1,22 +1,59 @@ /*! - * @file apm32f10x_usb.h + * @file drv_usb_device.h * * @brief This file contains all the prototypes,enumeration and macros for USBD peripheral * - * @version V1.0.1 + * @version V1.0.0 * - * @date 2021-03-23 + * @date 2021-12-06 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ -#ifndef __APM32F10X_USBD_H_ -#define __APM32F10X_USBD_H_ -#include "apm32f10x.h" +#ifndef __DRV_USB_DEVICE_H_ +#define __DRV_USB_DEVICE_H_ #ifdef __cplusplus extern "C" { #endif +#if defined(APM32F070xB) || defined(APM32F072x8) || defined(APM32F072xB) +#define APM32F0xx_USB +#else +#define APM32F10x_USB +#endif + +#ifdef APM32F0xx_USB +#include "apm32f0xx.h" +#include "apm32f0xx_pmu.h" +#include "apm32f0xx_eint.h" +#include "apm32f0xx_gpio.h" +#include "apm32f0xx_rcm.h" +#include "apm32f0xx_misc.h" +#include "usb_config.h" +#else +#include "apm32f10x.h" +#include "apm32f10x_pmu.h" +#include "apm32f10x_eint.h" +#include "apm32f10x_gpio.h" +#include "apm32f10x_rcm.h" +#include "apm32f10x_misc.h" +#include "usb_config.h" +#endif + /** @addtogroup Peripherals_Library Standard Peripheral Library @{ */ @@ -44,7 +81,7 @@ typedef enum USBD_EP_BIT_RXSTS = (uint32_t)(BIT12 | BIT13), USBD_EP_BIT_RXDTOG = (uint32_t)(BIT14), USBD_EP_BIT_CTFR = (uint32_t)(BIT15) -}USBD_EP_BIT_T; +} USBD_EP_BIT_T; /** * @brief Endpoint id @@ -59,7 +96,7 @@ typedef enum USBD_EP_5, USBD_EP_6, USBD_EP_7, -}USBD_EP_T; +} USBD_EP_T; /** * @brief Endpoint status @@ -70,18 +107,18 @@ typedef enum USBD_EP_STATUS_STALL = ((uint32_t)1), USBD_EP_STATUS_NAK = ((uint32_t)2), USBD_EP_STATUS_VALID = ((uint32_t)3), -}USBD_EP_STATUS_T; +} USBD_EP_STATUS_T; /** - * @brief USBD Endpoint type + * @brief USBD Endpoint type for register */ typedef enum { - USBD_EP_TYPE_BULK, - USBD_EP_TYPE_CONTROL, - USBD_EP_TYPE_ISO, - USBD_EP_TYPE_INTERRUPT -}USBD_EP_TYPE_T; + USBD_REG_EP_TYPE_BULK, + USBD_REG_EP_TYPE_CONTROL, + USBD_REG_EP_TYPE_ISO, + USBD_REG_EP_TYPE_INTERRUPT +} USBD_REG_EP_TYPE_T; /**@} end of group USBD_Enumerations*/ @@ -315,112 +352,6 @@ typedef enum */ #define USBD_ReadEPRxStatus(ep) ((USBD_EP_STATUS_T)(USBD->EP[ep].EP_B.RXSTS)) -/*! - * @brief Read EP Tx address pointer - * - * @param ep: EP number - * - * @retval EP Tx address pointer - */ -#define USBD_ReadEPTxAddrPointer(ep) (uint32_t *)((USBD->BUFFTB + ep * 8) * 2 + USBD_PMA_ADDR) - - -/*! - * @brief Read EP Tx count pointer - * - * @param ep: EP number - * - * @retval EP Tx count pointer - */ -#define USBD_ReadEPTxCntPointer(ep) (uint32_t *)((USBD->BUFFTB + ep * 8 + 2) * 2 + USBD_PMA_ADDR) - -/*! - * @brief Read EP Rx address pointer - * - * @param ep: EP number - * - * @retval EP Rx address pointer - */ -#define USBD_ReadEPRxAddrPointer(ep) (uint32_t *)((USBD->BUFFTB + ep * 8 + 4) * 2 + USBD_PMA_ADDR) - -/*! - * @brief Read EP Rx count pointer - * - * @param ep: EP number - * - * @retval EP Rx count pointer - */ -#define USBD_ReadEPRxCntPointer(ep) (uint32_t *)((USBD->BUFFTB + ep * 8 + 6) * 2 + USBD_PMA_ADDR) - -/*! - * @brief Set EP Tx addr - * - * @param ep: EP number - * - * @param addr: Tx addr - * - * @retval None - */ -#define USBD_SetEPTxAddr(ep, addr) (*USBD_ReadEPTxAddrPointer(ep) = (addr >> 1) << 1) - -/*! - * @brief Set EP Rx addr - * - * @param ep: EP number - * - * @param addr: Rx addr - * - * @retval None - */ -#define USBD_SetEPRxAddr(ep, addr) (*USBD_ReadEPRxAddrPointer(ep) = (addr >> 1) << 1) - -/*! - * @brief Read EP Tx addr - * - * @param ep: EP number - * - * @retval EP Tx addr - */ -#define USBD_ReadEPTxAddr(ep) ((uint16_t)*USBD_ReadEPTxAddrPointer(ep)) - -/*! - * @brief Read EP Rx addr - * - * @param ep: EP number - * - * @retval EP Rx addr - */ -#define USBD_ReadEPRxAddr(ep) ((uint16_t)*USBD_ReadEPRxAddrPointer(ep)) - -/*! - * @brief Set EP Rx Count - * - * @param ep: EP number - * - * @param cnt: Tx count - * - * @retval None - */ -#define USBD_SetEPTxCnt(ep, cnt) (*USBD_ReadEPTxCntPointer(ep) = cnt) - -/*! - * @brief Read EP Tx count - * - * @param ep: EP number - * - * @retval EP Tx count - */ -#define USBD_ReadEPTxCnt(ep) ((uint16_t)*USBD_ReadEPTxCntPointer(ep) & 0x3ff) - -/*! - * @brief Read EP Rx count - * - * @param ep: EP number - * - * @retval EP Rx count - */ -#define USBD_ReadEPRxCnt(ep) ((uint16_t)*USBD_ReadEPRxCntPointer(ep) & 0x3ff) - /*! * @brief Read SETUP field value in EP register * @@ -547,29 +478,458 @@ typedef enum */ #define USBD_ReadFRANUM() (USBD->FRANUM_B.FRANUM) -void USBD_SetEPType(USBD_EP_T ep, USBD_EP_TYPE_T type); +#ifdef APM32F0xx_USB +/*! + * @brief Read EP Tx address pointer + * + * @param ep: EP number + * + * @retval EP Tx address pointer + */ +#define USBD_ReadEPTxAddrPointer(ep) (uint16_t *)((USBD->BUFFTB + ep * 8) + USBD_PMA_ADDR) -void USBD_SetEPKind(USBD_EP_T ep); -void USBD_ResetEPKind(USBD_EP_T ep); +/*! + * @brief Read EP Tx count pointer + * + * @param ep: EP number + * + * @retval EP Tx count pointer + */ +#define USBD_ReadEPTxCntPointer(ep) (uint16_t *)((USBD->BUFFTB + ep * 8 + 2) + USBD_PMA_ADDR) -void USBD_ResetEPRxFlag(USBD_EP_T ep); -void USBD_ResetEPTxFlag(USBD_EP_T ep); +/*! + * @brief Read EP Rx address pointer + * + * @param ep: EP number + * + * @retval EP Rx address pointer + */ +#define USBD_ReadEPRxAddrPointer(ep) (uint16_t *)((USBD->BUFFTB + ep * 8 + 4) + USBD_PMA_ADDR) -void USBD_ToggleTx(USBD_EP_T ep); -void USBD_ToggleRx(USBD_EP_T ep); -void USBD_ResetTxToggle(USBD_EP_T ep); -void USBD_ResetRxToggle(USBD_EP_T ep); +/*! + * @brief Read EP Rx count pointer + * + * @param ep: EP number + * + * @retval EP Rx count pointer + */ +#define USBD_ReadEPRxCntPointer(ep) (uint16_t *)((USBD->BUFFTB + ep * 8 + 6) + USBD_PMA_ADDR) -void USBD_SetEpAddr(USBD_EP_T ep, uint8_t addr); +/*! + * @brief Set EP Tx addr + * + * @param ep: EP number + * + * @param addr: Tx addr + * + * @retval None + */ +#define USBD_SetEPTxAddr(ep, addr) (*USBD_ReadEPTxAddrPointer(ep) = (addr >> 1) << 1) -void USBD_SetEPTxStatus(USBD_EP_T ep, USBD_EP_STATUS_T status); -void USBD_SetEPRxStatus(USBD_EP_T ep, USBD_EP_STATUS_T status); -void USBD_SetEPRxTxStatus(USBD_EP_T ep, USBD_EP_STATUS_T txStatus, USBD_EP_STATUS_T rxStatus); +/*! + * @brief Set EP Rx addr + * + * @param ep: EP number + * + * @param addr: Rx addr + * + * @retval None + */ +#define USBD_SetEPRxAddr(ep, addr) (*USBD_ReadEPRxAddrPointer(ep) = (addr >> 1) << 1) -void USBD_SetEPRxCnt(USBD_EP_T ep, uint32_t cnt); +/*! + * @brief Read EP Tx addr + * + * @param ep: EP number + * + * @retval EP Tx addr + */ +#define USBD_ReadEPTxAddr(ep) ((uint16_t)*USBD_ReadEPTxAddrPointer(ep)) -void USBD_WriteDataToEP(USBD_EP_T ep, uint8_t *wBuf, uint32_t wLen); -void USBD_ReadDataFromEP(USBD_EP_T ep, uint8_t *rBuf, uint32_t rLen); +/*! + * @brief Read EP Rx addr + * + * @param ep: EP number + * + * @retval EP Rx addr + */ +#define USBD_ReadEPRxAddr(ep) ((uint16_t)*USBD_ReadEPRxAddrPointer(ep)) + +/*! + * @brief Read EP Tx Buffer Pointer + * + * @param ep: EP number + * + * @retval EP Tx Buffer Pointer + */ +#define USBD_ReadEPTxBufferPointer(ep) (uint16_t *)(USBD_ReadEPTxAddr(ep) + USBD_PMA_ADDR) + +/*! + * @brief Read EP Rx Buffer Pointer + * + * @param ep: EP number + * + * @retval EP Rx Buffer Pointer + */ +#define USBD_ReadEPRxBufferPointer(ep) (uint16_t *)(USBD_ReadEPRxAddr(ep) + USBD_PMA_ADDR) + +/*! + * @brief Set EP Tx Count + * + * @param ep: EP number + * + * @param cnt: Tx count + * + * @retval None + */ +#define USBD_SetEPTxCnt(ep, cnt) (*USBD_ReadEPTxCntPointer(ep) = cnt) + +/*! + * @brief Read EP Tx count + * + * @param ep: EP number + * + * @retval EP Tx count + */ +#define USBD_ReadEPTxCnt(ep) ((uint16_t)*USBD_ReadEPTxCntPointer(ep) & 0x3ff) + +/*! + * @brief Read EP Rx count + * + * @param ep: EP number + * + * @retval EP Rx count + */ +#define USBD_ReadEPRxCnt(ep) ((uint16_t)*USBD_ReadEPRxCntPointer(ep) & 0x3ff) + +/*! + * @brief Set BESL Value + * + * @param val: 4-bits BESL Value to be set + * + * @retval None + */ +#define USBD_SetBESL(val) (USBD->LPMCTRLSTS_B.BESL = val) + +/*! + * @brief Set bRemoteWakew Value + * + * @param val: 1-bit bRemoteWakew Value to be set + * + * @retval None + */ +#define USBD_SetRemoteWakeVal(val) (USBD->LPMCTRLSTS_B.REMWAKE = val) + +/*! + * @brief Enable LPM ACK + * + * @param None + * + * @retval None + */ +#define USBD_EnableAckLPM() (USBD->LPMCTRLSTS_B.LPMACKEN = 1) + +/*! + * @brief Disable LPM ACK + * + * @param None + * + * @retval None + */ +#define USBD_DisableAckLPM() (USBD->LPMCTRLSTS_B.LPMACKEN = 0) + +/*! + * @brief Disable LPM + * + * @param None + * + * @retval None + */ +#define USBD_EnableLPM() (USBD->LPMCTRLSTS_B.LPMEN = 1) + +/*! + * @brief Disable LPM + * + * @param None + * + * @retval None + */ +#define USBD_DisableLPM() (USBD->LPMCTRLSTS_B.LPMEN = 0) + +/*! + * @brief Enable Pull-up of DP line + * + * @param None + * + * @retval None + */ +#define USBD_EnablePullUpDP() (USBD->BCD_B.DPPUCTRL = 1) + +/*! + * @brief Disable Pull-up of DP line + * + * @param None + * + * @retval None + */ +#define USBD_DisablePullUpDP() (USBD->BCD_B.DPPUCTRL = 0) + +/*! + * @brief Read DM Pull-up Detection Status Flag + * + * @param None + * + * @retval DM Pull-up Detection Status Flag + */ +#define USBD_DMPullUpStatus() (USBD->BCD_B.DMPUDFLG) + +/*! + * @brief Read Secondary Detection Status Flag + * + * @param None + * + * @retval Secondary Detection Status Flag + */ +#define USBD_SDStatus() (USBD->BCD_B.SDFLG) + +/*! + * @brief Read Primary Detection Status Flag + * + * @param None + * + * @retval Primary Detection Status Flag + */ +#define USBD_PDStatus() (USBD->BCD_B.PDFLG) + +/*! + * @brief Read Data Contact Detection Status Flag + * + * @param None + * + * @retval Data Contact Detection Status Flag + */ +#define USBD_DCDStatus() (USBD->BCD_B.DCDFLG) + +/*! + * @brief Enable Secondary Detection Mode + * + * @param None + * + * @retval None + */ +#define USBD_EnableSDMode() (USBD->BCD_B.SDEN = 1) + +/*! + * @brief Disable Secondary Detection Mode + * + * @param None + * + * @retval None + */ +#define USBD_DisableSDMode() (USBD->BCD_B.SDEN = 0) + +/*! + * @brief Enable Primary Detection Mode + * + * @param None + * + * @retval None + */ +#define USBD_EnablePDMode() (USBD->BCD_B.PDEN = 1) + +/*! + * @brief Disable Primary Detection Mode + * + * @param None + * + * @retval None + */ +#define USBD_DisablePDMode() (USBD->BCD_B.PDEN = 0) + +/*! + * @brief Enable Data Contact Detection Mode + * + * @param None + * + * @retval None + */ +#define USBD_EnableDCDMode() (USBD->BCD_B.DCDEN = 1) + +/*! + * @brief Disable Data Contact Detection Mode + * + * @param None + * + * @retval None + */ +#define USBD_DisableDCDMode() (USBD->BCD_B.DCDEN = 0) + +/*! + * @brief Enable Battery Charging Detector + * + * @param None + * + * @retval None + */ +#define USBD_EnableBCD() (USBD->BCD_B.BCDEN = 1) + +/*! + * @brief Disable Battery Charging Detector + * + * @param None + * + * @retval None + */ +#define USBD_DisableBCD() (USBD->BCD_B.BCDEN = 0) + +#else //!< APM32F10x_USB +/*! + * @brief Read EP Tx address pointer + * + * @param ep: EP number + * + * @retval EP Tx address pointer + */ +#define USBD_ReadEPTxAddrPointer(ep) (uint16_t *)((USBD->BUFFTB + ep * 8) * 2 + USBD_PMA_ADDR) + +/*! + * @brief Read EP Tx count pointer + * + * @param ep: EP number + * + * @retval EP Tx count pointer + */ +#define USBD_ReadEPTxCntPointer(ep) (uint16_t *)((USBD->BUFFTB + ep * 8 + 2) * 2 + USBD_PMA_ADDR) + +/*! + * @brief Read EP Rx address pointer + * + * @param ep: EP number + * + * @retval EP Rx address pointer + */ +#define USBD_ReadEPRxAddrPointer(ep) (uint16_t *)((USBD->BUFFTB + ep * 8 + 4) * 2 + USBD_PMA_ADDR) + +/*! + * @brief Read EP Rx count pointer + * + * @param ep: EP number + * + * @retval EP Rx count pointer + */ +#define USBD_ReadEPRxCntPointer(ep) (uint16_t *)((USBD->BUFFTB + ep * 8 + 6) * 2 + USBD_PMA_ADDR) + +/*! + * @brief Set EP Tx addr + * + * @param ep: EP number + * + * @param addr: Tx addr + * + * @retval None + */ +#define USBD_SetEPTxAddr(ep, addr) (*USBD_ReadEPTxAddrPointer(ep) = (addr >> 1) << 1) + +/*! + * @brief Set EP Rx addr + * + * @param ep: EP number + * + * @param addr: Rx addr + * + * @retval None + */ +#define USBD_SetEPRxAddr(ep, addr) (*USBD_ReadEPRxAddrPointer(ep) = (addr >> 1) << 1) + +/*! + * @brief Read EP Tx addr + * + * @param ep: EP number + * + * @retval EP Tx addr + */ +#define USBD_ReadEPTxAddr(ep) ((uint16_t)*USBD_ReadEPTxAddrPointer(ep)) + +/*! + * @brief Read EP Rx addr + * + * @param ep: EP number + * + * @retval EP Rx addr + */ +#define USBD_ReadEPRxAddr(ep) ((uint16_t)*USBD_ReadEPRxAddrPointer(ep)) + +/*! + * @brief Read EP Tx Buffer Pointer + * + * @param ep: EP number + * + * @retval EP Tx Buffer Pointer + */ +#define USBD_ReadEPTxBufferPointer(ep) (uint32_t *)(((uint32_t)USBD_ReadEPTxAddr(ep) << 1) + USBD_PMA_ADDR) + +/*! + * @brief Read EP Rx Buffer Pointer + * + * @param ep: EP number + * + * @retval EP Rx Buffer Pointer + */ +#define USBD_ReadEPRxBufferPointer(ep) (uint32_t *)(((uint32_t)USBD_ReadEPRxAddr(ep) << 1) + USBD_PMA_ADDR) + +/*! + * @brief Set EP Tx Count + * + * @param ep: EP number + * + * @param cnt: Tx count + * + * @retval None + */ +#define USBD_SetEPTxCnt(ep, cnt) (*USBD_ReadEPTxCntPointer(ep) = cnt) + +/*! + * @brief Read EP Tx count + * + * @param ep: EP number + * + * @retval EP Tx count + */ +#define USBD_ReadEPTxCnt(ep) ((uint16_t)*USBD_ReadEPTxCntPointer(ep) & 0x3ff) + +/*! + * @brief Read EP Rx count + * + * @param ep: EP number + * + * @retval EP Rx count + */ +#define USBD_ReadEPRxCnt(ep) ((uint16_t)*USBD_ReadEPRxCntPointer(ep) & 0x3ff) + +#endif +void USBD_SetEPType(uint8_t ep, USBD_REG_EP_TYPE_T type); + +void USBD_SetEPKind(uint8_t ep); +void USBD_ResetEPKind(uint8_t ep); + +void USBD_ResetEPRxFlag(uint8_t ep); +void USBD_ResetEPTxFlag(uint8_t ep); + +void USBD_ToggleTx(uint8_t ep); +void USBD_ToggleRx(uint8_t ep); +void USBD_ResetTxToggle(uint8_t ep); +void USBD_ResetRxToggle(uint8_t ep); + +void USBD_SetEpAddr(uint8_t ep, uint8_t addr); + +void USBD_SetEPTxStatus(uint8_t ep, USBD_EP_STATUS_T status); +void USBD_SetEPRxStatus(uint8_t ep, USBD_EP_STATUS_T status); +void USBD_SetEPTxRxStatus(uint8_t ep, USBD_EP_STATUS_T txStatus, USBD_EP_STATUS_T rxStatus); + +void USBD_SetEPRxCnt(uint8_t ep, uint32_t cnt); + +void USBD_WriteDataToEP(uint8_t ep, uint8_t *wBuf, uint32_t wLen); +void USBD_ReadDataFromEP(uint8_t ep, uint8_t *rBuf, uint32_t rLen); /**@} end of group USBD_Fuctions*/ /**@} end of group USBD_Driver*/ @@ -579,4 +939,4 @@ void USBD_ReadDataFromEP(USBD_EP_T ep, uint8_t *rBuf, uint32_t rLen); } #endif -#endif /* __APM32F10X_USBD_H */ +#endif /* __DRV_USB_DEVICE_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_usb.c b/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Driver/src/drv_usb_device.c similarity index 67% rename from bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_usb.c rename to bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Driver/src/drv_usb_device.c index fb8fee5481..169d7024ac 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_usb.c +++ b/bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Driver/src/drv_usb_device.c @@ -1,15 +1,29 @@ /*! - * @file apm32f10x_usb.c + * @file drv_usb_device.c * * @brief This file contains all the functions for the USBD peripheral * - * @version V1.0.1 + * @version V1.0.0 * - * @date 2021-03-23 + * @date 2021-12-06 * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. */ -#include "apm32f10x_usb.h" +#include "drv_usb_device.h" /*! * @brief Set Endpoint type @@ -20,7 +34,7 @@ * * @retval None */ -void USBD_SetEPType(USBD_EP_T ep, USBD_EP_TYPE_T type) +void USBD_SetEPType(uint8_t ep, USBD_REG_EP_TYPE_T type) { __IOM uint32_t reg; @@ -40,7 +54,7 @@ void USBD_SetEPType(USBD_EP_T ep, USBD_EP_TYPE_T type) * * @retval None */ -void USBD_SetEPKind(USBD_EP_T ep) +void USBD_SetEPKind(uint8_t ep) { __IOM uint32_t reg; @@ -59,7 +73,7 @@ void USBD_SetEPKind(USBD_EP_T ep) * * @retval None */ -void USBD_ResetEPKind(USBD_EP_T ep) +void USBD_ResetEPKind(uint8_t ep) { __IOM uint32_t reg; @@ -79,7 +93,7 @@ void USBD_ResetEPKind(USBD_EP_T ep) * * @retval None */ -void USBD_ResetEPRxFlag(USBD_EP_T ep) +void USBD_ResetEPRxFlag(uint8_t ep) { __IOM uint32_t reg; @@ -98,7 +112,7 @@ void USBD_ResetEPRxFlag(USBD_EP_T ep) * * @retval None */ -void USBD_ResetEPTxFlag(USBD_EP_T ep) +void USBD_ResetEPTxFlag(uint8_t ep) { __IOM uint32_t reg; @@ -117,7 +131,7 @@ void USBD_ResetEPTxFlag(USBD_EP_T ep) * * @retval None */ -void USBD_ToggleTx(USBD_EP_T ep) +void USBD_ToggleTx(uint8_t ep) { __IOM uint32_t reg; @@ -136,7 +150,7 @@ void USBD_ToggleTx(USBD_EP_T ep) * * @retval None */ -void USBD_ToggleRx(USBD_EP_T ep) +void USBD_ToggleRx(uint8_t ep) { __IOM uint32_t reg; @@ -155,9 +169,9 @@ void USBD_ToggleRx(USBD_EP_T ep) * * @retval None */ -void USBD_ResetTxToggle(USBD_EP_T ep) +void USBD_ResetTxToggle(uint8_t ep) { - if(USBD->EP[ep].EP_B.TXDTOG) + if (USBD->EP[ep].EP_B.TXDTOG) { USBD_ToggleTx(ep); } @@ -170,9 +184,9 @@ void USBD_ResetTxToggle(USBD_EP_T ep) * * @retval None */ -void USBD_ResetRxToggle(USBD_EP_T ep) +void USBD_ResetRxToggle(uint8_t ep) { - if(USBD->EP[ep].EP_B.RXDTOG) + if (USBD->EP[ep].EP_B.RXDTOG) { USBD_ToggleRx(ep); } @@ -187,7 +201,7 @@ void USBD_ResetRxToggle(USBD_EP_T ep) * * @retval None */ -void USBD_SetEpAddr(USBD_EP_T ep, uint8_t addr) +void USBD_SetEpAddr(uint8_t ep, uint8_t addr) { __IOM uint32_t reg; @@ -209,7 +223,7 @@ void USBD_SetEpAddr(USBD_EP_T ep, uint8_t addr) * * @retval None */ -void USBD_SetEPTxStatus(USBD_EP_T ep, USBD_EP_STATUS_T status) +void USBD_SetEPTxStatus(uint8_t ep, USBD_EP_STATUS_T status) { __IOM uint32_t reg; @@ -218,7 +232,7 @@ void USBD_SetEPTxStatus(USBD_EP_T ep, USBD_EP_STATUS_T status) reg = USBD->EP[ep].EP; reg &= (uint32_t)(USBD_EP_MASK_DEFAULT | USBD_EP_BIT_TXSTS); - reg ^= (status & USBD_EP_BIT_TXSTS); + reg ^= ((uint32_t)status & (uint32_t)USBD_EP_BIT_TXSTS); USBD->EP[ep].EP = reg; } @@ -232,7 +246,7 @@ void USBD_SetEPTxStatus(USBD_EP_T ep, USBD_EP_STATUS_T status) * * @retval None */ -void USBD_SetEPRxStatus(USBD_EP_T ep, USBD_EP_STATUS_T status) +void USBD_SetEPRxStatus(uint8_t ep, USBD_EP_STATUS_T status) { __IOM uint32_t reg; uint32_t tmp; @@ -249,7 +263,7 @@ void USBD_SetEPRxStatus(USBD_EP_T ep, USBD_EP_STATUS_T status) /*! - * @brief Set EP Rx and Txstatus + * @brief Set EP Tx and Rx status * * @param ep: Endpoint number * @@ -257,7 +271,7 @@ void USBD_SetEPRxStatus(USBD_EP_T ep, USBD_EP_STATUS_T status) * * @retval None */ -void USBD_SetEPRxTxStatus(USBD_EP_T ep, USBD_EP_STATUS_T txStatus, USBD_EP_STATUS_T rxStatus) +void USBD_SetEPTxRxStatus(uint8_t ep, USBD_EP_STATUS_T txStatus, USBD_EP_STATUS_T rxStatus) { __IOM uint32_t reg; uint32_t tmp; @@ -284,18 +298,18 @@ void USBD_SetEPRxTxStatus(USBD_EP_T ep, USBD_EP_STATUS_T txStatus, USBD_EP_STATU * * @retval None */ -void USBD_SetEPRxCnt(USBD_EP_T ep, uint32_t cnt) +void USBD_SetEPRxCnt(uint8_t ep, uint32_t cnt) { - __IOM uint32_t *p; - __IOM uint32_t block = 0; + __IOM uint16_t *p; + __IOM uint16_t block = 0; p = USBD_ReadEPRxCntPointer(ep); - if(cnt > 62) + if (cnt > 62) { block = cnt >> 5; - if(!(cnt & 0x1f)) + if (!(cnt & 0x1f)) { block -= 1; } @@ -306,7 +320,7 @@ void USBD_SetEPRxCnt(USBD_EP_T ep, uint32_t cnt) { block = cnt >> 1; - if(cnt & 0x01) + if (cnt & 0x01) { block += 1; } @@ -326,23 +340,27 @@ void USBD_SetEPRxCnt(USBD_EP_T ep, uint32_t cnt) * * @retval None */ -void USBD_WriteDataToEP(USBD_EP_T ep, uint8_t *wBuf, uint32_t wLen) +void USBD_WriteDataToEP(uint8_t ep, uint8_t *wBuf, uint32_t wLen) { uint32_t i; - uint32_t *addrEP; +#ifdef APM32F0xx_USB + uint16_t *epAddr; + uint16_t tmp; +#else + uint32_t *epAddr; uint32_t tmp; +#endif wLen = (wLen + 1) >> 1; - addrEP = (uint32_t *)USBD_ReadEPTxAddr(ep); - addrEP = (uint32_t *)(((uint32_t)addrEP << 1) + USBD_PMA_ADDR); + epAddr = USBD_ReadEPTxBufferPointer(ep); - for(i = 0; i < wLen; i++) + for (i = 0; i < wLen; i++) { tmp = *wBuf++; tmp = ((*wBuf++) << 8) | tmp; - *addrEP++ = tmp; + *epAddr++ = tmp; } } @@ -357,22 +375,29 @@ void USBD_WriteDataToEP(USBD_EP_T ep, uint8_t *wBuf, uint32_t wLen) * * @retval None */ -void USBD_ReadDataFromEP(USBD_EP_T ep, uint8_t *rBuf, uint32_t rLen) +void USBD_ReadDataFromEP(uint8_t ep, uint8_t *rBuf, uint32_t rLen) { - uint32_t i; - uint32_t *addrEP; - uint32_t tmp; +#ifdef APM32F0xx_USB + uint16_t *epAddr; +#else + uint32_t *epAddr; +#endif + uint32_t i, tmp, cnt; - rLen = (rLen + 1) >> 1; + cnt = rLen >> 1; - addrEP = (uint32_t *)USBD_ReadEPRxAddr(ep); - addrEP = (uint32_t *)(((uint32_t)addrEP << 1) + USBD_PMA_ADDR); + epAddr = USBD_ReadEPRxBufferPointer(ep); - for(i = 0; i < rLen; i++) + for (i = 0; i < cnt; i++) { - tmp = *addrEP++; - *rBuf++ = tmp & 0XFF; - *rBuf++ = (tmp >> 8) & 0xff; + tmp = *epAddr++; + *rBuf++ = tmp & 0xFF; + *rBuf++ = (tmp >> 8) & 0xFF; + } + + if (rLen & 1) + { + tmp = *epAddr; + *rBuf = tmp & 0xFF; } } - diff --git a/bsp/apm32/libraries/Drivers/SConscript b/bsp/apm32/libraries/Drivers/SConscript index aa3dcad878..61cdb7ab9b 100644 --- a/bsp/apm32/libraries/Drivers/SConscript +++ b/bsp/apm32/libraries/Drivers/SConscript @@ -17,6 +17,30 @@ if GetDepend(['RT_USING_SERIAL']): else: src += ['drv_usart.c'] +if GetDepend(['RT_USING_ADC']): + src += ['drv_adc.c'] + +if GetDepend(['RT_USING_DAC']): + src += ['drv_dac.c'] + +if GetDepend('BSP_USING_ONCHIP_RTC'): + src += ['drv_rtc.c'] + +if GetDepend(['RT_USING_I2C']): + src += ['drv_soft_i2c.c'] + +if GetDepend(['RT_USING_SPI']): + src += ['drv_spi.c'] + +if GetDepend(['RT_USING_HWTIMER']): + src += ['drv_hwtimer.c'] + +if GetDepend(['RT_USING_PWM']): + src += ['drv_pwm.c'] + +if GetDepend(['RT_USING_WDT']): + src += ['drv_wdt.c'] + src += ['drv_common.c'] path = [cwd] diff --git a/bsp/apm32/libraries/Drivers/drv_adc.c b/bsp/apm32/libraries/Drivers/drv_adc.c new file mode 100644 index 0000000000..162f5afbdd --- /dev/null +++ b/bsp/apm32/libraries/Drivers/drv_adc.c @@ -0,0 +1,273 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-03-04 stevetong459 first version + */ + +#include + +#if defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2) || defined(BSP_USING_ADC3) + +#define LOG_TAG "drv.adc" +#define DBG_LVL DBG_INFO +#include + +#define DRV_ADC_CHANNEL_MAX_NUM 14 +#define DRV_ADC_TIME_OUT 0xFFF + +#define _ADC_GET_PORT(pin_num) ((GPIO_T *)(GPIOA_BASE + (0x400u * (((pin_num) >> 4) & 0xFu)))) +#define _ADC_GET_PIN(pin_num) ((uint16_t)(1u << ((pin_num) & 0xFu))) + +struct apm32_adc +{ + const char *name; + ADC_T *adc; + ADC_Config_T adc_config; + rt_base_t channel_pin[DRV_ADC_CHANNEL_MAX_NUM]; + struct rt_adc_device adc_dev; +}; + +static struct apm32_adc adc_config[] = +{ +#ifdef BSP_USING_ADC1 + { + "adc1", + ADC1, + { + ADC_MODE_INDEPENDENT, + DISABLE, + DISABLE, + ADC_EXT_TRIG_CONV_None, + ADC_DATA_ALIGN_RIGHT, + 1 + }, + { + GET_PIN(A, 0), GET_PIN(A, 1), GET_PIN(A, 2), GET_PIN(A, 3), GET_PIN(A, 4), + GET_PIN(A, 5), GET_PIN(A, 6), GET_PIN(A, 7), GET_PIN(B, 0), GET_PIN(B, 1), + GET_PIN(C, 0), GET_PIN(C, 1), GET_PIN(C, 2), GET_PIN(C, 3) + }, + RT_NULL + }, +#endif +#ifdef BSP_USING_ADC2 + { + "adc2", + ADC2, + { + ADC_MODE_INDEPENDENT, + DISABLE, + DISABLE, + ADC_EXT_TRIG_CONV_None, + ADC_DATA_ALIGN_RIGHT, + 1 + }, + { + GET_PIN(A, 0), GET_PIN(A, 1), GET_PIN(A, 2), GET_PIN(A, 3), GET_PIN(A, 4), + GET_PIN(A, 5), GET_PIN(A, 6), GET_PIN(A, 7), GET_PIN(B, 0), GET_PIN(B, 1), + GET_PIN(C, 0), GET_PIN(C, 1), GET_PIN(C, 2), GET_PIN(C, 3) + }, + RT_NULL + }, +#endif +#ifdef BSP_USING_ADC3 + { + "adc3", + ADC3, + { + ADC_MODE_INDEPENDENT, + DISABLE, + DISABLE, + ADC_EXT_TRIG_CONV_None, + ADC_DATA_ALIGN_RIGHT, + 1 + }, + { + GET_PIN(A, 0), GET_PIN(A, 1), GET_PIN(A, 2), GET_PIN(A, 3), GET_PIN(F, 6), + GET_PIN(F, 7), GET_PIN(F, 8), GET_PIN(F, 9), GET_PIN(F, 10) + }, + RT_NULL + }, +#endif +}; + +static rt_err_t _adc_channel_check(struct rt_adc_device *device, rt_uint32_t channel) +{ + struct apm32_adc *adc_cfg = ((struct apm32_adc *)device->parent.user_data); + + if (adc_cfg->adc == ADC3) + { + if (channel <= 8) + { + return RT_EOK; + } + } + else + { + if (channel <= 13) + { + return RT_EOK; + } + } + + LOG_E("channel %d of %s is not supported.", channel, adc_cfg->name); + return -RT_ERROR; +} + +static rt_err_t _adc_gpio_init(struct rt_adc_device *device, rt_uint32_t channel) +{ + struct apm32_adc *adc_cfg = ((struct apm32_adc *)device->parent.user_data); + GPIO_Config_T hw_gpio_config; + + if (_adc_channel_check(device, channel) != RT_EOK) + { + return -RT_ERROR; + } + + RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIOA << ((adc_cfg->channel_pin[channel] >> 4) & 0xFu)); + + hw_gpio_config.mode = GPIO_MODE_ANALOG; + hw_gpio_config.pin = _ADC_GET_PIN(adc_cfg->channel_pin[channel]); + GPIO_Config(_ADC_GET_PORT(adc_cfg->channel_pin[channel]), &hw_gpio_config); + + return RT_EOK; +} + +/** + * @brief This function will control the adc to enable or disable. + * + * @param device is a pointer to adc device. + * + * @param channel is the adc channel. + * + * @param enabled is the status to indicate enable or disable. + * + * @return RT_EOK indicates successful enable or disable adc, other value indicates failed. + */ +static rt_err_t _adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled) +{ + struct apm32_adc *adc_cfg = ((struct apm32_adc *)device->parent.user_data); + + RT_ASSERT(device != RT_NULL); + + if (enabled) + { + if (adc_cfg->adc == ADC1) + { + RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_ADC1); + } + else if (adc_cfg->adc == ADC2) + { + RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_ADC2); + } + else + { + RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_ADC3); + } + if (_adc_gpio_init(device, channel) != RT_EOK) + { + return -RT_ERROR; + } + + ADC_Config(adc_cfg->adc, &adc_cfg->adc_config); + + ADC_Enable(adc_cfg->adc); + } + else + { + ADC_Disable(adc_cfg->adc); + } + + return RT_EOK; +} + +/** + * @brief This function will get the adc conversion value. + * + * @param device is a pointer to adc device. + * + * @param channel is the adc channel. + * + * @param value is a pointer to the adc conversion value. + * + * @return RT_EOK indicates successful get adc value, other value indicates failed. + */ +static rt_err_t _adc_get_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value) +{ + struct apm32_adc *adc_cfg = ((struct apm32_adc *)device->parent.user_data); + volatile rt_uint32_t counter = 0; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(value != RT_NULL); + + if (_adc_channel_check(device, channel) != RT_EOK) + { + return -RT_ERROR; + } + ADC_ConfigRegularChannel(adc_cfg->adc, channel, 1, ADC_SAMPLETIME_13CYCLES5); + + ADC_StartCalibration(adc_cfg->adc); + /* Check the end of ADC calibration */ + while (ADC_ReadCalibrationStartFlag(adc_cfg->adc)) + { + if (++counter > DRV_ADC_TIME_OUT) + { + return RT_ETIMEOUT; + } + } + + ADC_EnableSoftwareStartConv(adc_cfg->adc); + + counter = 0; + while (!ADC_ReadStatusFlag(adc_cfg->adc, ADC_FLAG_EOC)) + { + if (++counter > DRV_ADC_TIME_OUT) + { + return RT_ETIMEOUT; + } + } + + *value = ADC_ReadConversionValue(adc_cfg->adc); + + return RT_EOK; +} + +static const struct rt_adc_ops _adc_ops = +{ + .enabled = _adc_enabled, + .convert = _adc_get_value, +}; + +/** + * @brief ADC initialization function. + * + * @return RT_EOK indicates successful initialization, other value indicates failed; + */ +static int rt_hw_adc_init(void) +{ + rt_err_t result = RT_EOK; + rt_size_t obj_num = sizeof(adc_config) / sizeof(struct apm32_adc); + rt_uint32_t i = 0; + + for (i = 0; i < obj_num; i++) + { + /* register ADC device */ + if (rt_hw_adc_register(&adc_config[i].adc_dev, adc_config[i].name, &_adc_ops, adc_config)) + { + LOG_D("%s init success", adc_config[i].name); + } + else + { + LOG_D("%s init failed", adc_config[i].name); + result = -RT_ERROR; + } + } + + return result; +} +INIT_BOARD_EXPORT(rt_hw_adc_init); + +#endif /* BSP_USING_ADCX */ diff --git a/bsp/apm32/libraries/Drivers/drv_common.c b/bsp/apm32/libraries/Drivers/drv_common.c index dd029321f8..f6caf333db 100644 --- a/bsp/apm32/libraries/Drivers/drv_common.c +++ b/bsp/apm32/libraries/Drivers/drv_common.c @@ -1,22 +1,23 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2020-08-20 Abbcc first version + * 2022-03-04 stevetong459 FINSH_FUNCTION_EXPORT_ALIAS change to MSH_CMD_EXPORT for reboot function. */ #include "drv_common.h" #include "board.h" #ifdef RT_USING_SERIAL -#ifdef RT_USING_SERIAL_V2 -#include "drv_usart_v2.h" -#else -#include "drv_usart.h" -#endif + #ifdef RT_USING_SERIAL_V2 + #include "drv_usart_v2.h" + #else + #include "drv_usart.h" + #endif #endif #ifdef RT_USING_FINSH @@ -25,17 +26,17 @@ static void reboot(uint8_t argc, char **argv) { rt_hw_cpu_reset(); } -FINSH_FUNCTION_EXPORT_ALIAS(reboot, __cmd_reboot, Reboot System); +MSH_CMD_EXPORT(reboot, Reboot System); #endif /* RT_USING_FINSH */ /* SysTick configuration */ void rt_hw_systick_init(void) { - SysTick_Config(RCM_ReadHCLKFreq()/RT_TICK_PER_SECOND); - + SysTick_Config(RCM_ReadHCLKFreq() / RT_TICK_PER_SECOND); + /* AHB clock selected as SysTick clock source. */ SysTick->CTRL |= 0x00000004U; - + NVIC_SetPriority(SysTick_IRQn, 0xFF); } diff --git a/bsp/apm32/libraries/Drivers/drv_common.h b/bsp/apm32/libraries/Drivers/drv_common.h index 5218b1189b..9e5dedddac 100644 --- a/bsp/apm32/libraries/Drivers/drv_common.h +++ b/bsp/apm32/libraries/Drivers/drv_common.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -14,7 +14,7 @@ #include #include #ifdef RT_USING_DEVICE -#include + #include #endif diff --git a/bsp/apm32/libraries/Drivers/drv_dac.c b/bsp/apm32/libraries/Drivers/drv_dac.c new file mode 100644 index 0000000000..6c49a47ea3 --- /dev/null +++ b/bsp/apm32/libraries/Drivers/drv_dac.c @@ -0,0 +1,184 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-03-04 stevetong459 first version + */ + +#include + +#if defined(BSP_USING_DAC1) + +#define LOG_TAG "drv.dac" +#define DBG_LVL DBG_INFO +#include + +struct apm32_dac +{ + const char *name; + DAC_T *dac; + DAC_Config_T dac_conf; + struct rt_dac_device dac_dev; +}; + +static struct apm32_dac dac_config[] = +{ +#if defined(BSP_USING_DAC1) + { + "dac1", + DAC, + { + DAC_TRIGGER_SOFT, + DAC_OUTPUT_BUFFER_DISABLE, + DAC_WAVE_GENERATION_NONE, + DAC_TRIANGLE_AMPLITUDE_4095, + }, + RT_NULL + } +#endif +}; + +/** + * @brief This function will enable dac. + * + * @param device is a pointer to dac device. + * + * @param channel is the dac channel. + * + * @return RT_EOK indicates successful enable dac, other value indicates failed. + */ +static rt_err_t _dac_enabled(struct rt_dac_device *device, rt_uint32_t channel) +{ + GPIO_Config_T GPIO_ConfigStruct; + struct apm32_dac *cfg = (struct apm32_dac *)device->parent.user_data; + + RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIOA); + GPIO_ConfigStruct.mode = GPIO_MODE_ANALOG; + + if (channel == 1) + { + GPIO_ConfigStruct.pin = GPIO_PIN_4; + GPIO_Config(GPIOA, &GPIO_ConfigStruct); + + DAC_Config(DAC_CHANNEL_1, &cfg->dac_conf); + DAC_Enable(DAC_CHANNEL_1); + } + else if (channel == 2) + { + GPIO_ConfigStruct.pin = GPIO_PIN_5; + GPIO_Config(GPIOA, &GPIO_ConfigStruct); + + DAC_Config(DAC_CHANNEL_2, &cfg->dac_conf); + DAC_Enable(DAC_CHANNEL_2); + } + else + { + LOG_E("dac channel must be 1 or 2."); + return -RT_ERROR; + } + + return RT_EOK; +} + +/** + * @brief This function will disable dac. + * + * @param device is a pointer to dac device. + * + * @param channel is the dac channel. + * + * @return RT_EOK indicates successful disable dac, other value indicates failed. + */ +static rt_err_t _dac_disabled(struct rt_dac_device *device, rt_uint32_t channel) +{ + if (channel == 1) + { + DAC_Disable(DAC_CHANNEL_1); + } + else if (channel == 2) + { + DAC_Disable(DAC_CHANNEL_2); + } + else + { + LOG_E("dac channel must be 1 or 2."); + return -RT_ERROR; + } + + return RT_EOK; +} + +/** + * @brief This function will set the vaule of dac. + * + * @param device is a pointer to dac device. + * + * @param channel is the dac channel. + * + * @param value is a pointer to dac value to be convert. + * + * @return RT_EOK indicates successful set dac value, other value indicates failed. + */ +static rt_err_t _dac_set_value(struct rt_dac_device *device, rt_uint32_t channel, rt_uint32_t *value) +{ + if (channel == 1) + { + DAC_ConfigChannel1Data(DAC_ALIGN_12BIT_R, *value); + DAC_EnableSoftwareTrigger(DAC_CHANNEL_1); + } + else if (channel == 2) + { + DAC_ConfigChannel2Data(DAC_ALIGN_12BIT_R, *value); + DAC_EnableSoftwareTrigger(DAC_CHANNEL_2); + } + else + { + LOG_E("dac channel must be 1 or 2."); + return -RT_ERROR; + } + + return RT_EOK; +} + +static const struct rt_dac_ops _dac_ops = +{ + .disabled = _dac_disabled, + .enabled = _dac_enabled, + .convert = _dac_set_value, +}; + +/** + * @brief DAC initialization function. + * + * @return RT_EOK indicates successful initialization, other value indicates failed; + */ +static int rt_hw_dac_init(void) +{ + rt_err_t result = RT_EOK; + rt_size_t obj_num = sizeof(dac_config) / sizeof(struct apm32_dac); + rt_uint32_t i = 0; + + RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_DAC); + + for (i = 0; i < obj_num; i++) + { + /* register dac device */ + if (rt_hw_dac_register(&dac_config[i].dac_dev, dac_config[i].name, &_dac_ops, dac_config) == RT_EOK) + { + LOG_D("%s init success", dac_config[i].name); + } + else + { + LOG_E("%s init failed", dac_config[i].name); + result = -RT_ERROR; + } + } + + return result; +} +INIT_DEVICE_EXPORT(rt_hw_dac_init); + +#endif /* BSP_USING_DACX */ diff --git a/bsp/apm32/libraries/Drivers/drv_gpio.c b/bsp/apm32/libraries/Drivers/drv_gpio.c index 7f8413d7fb..d45f2f71b3 100644 --- a/bsp/apm32/libraries/Drivers/drv_gpio.c +++ b/bsp/apm32/libraries/Drivers/drv_gpio.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/apm32/libraries/Drivers/drv_gpio.h b/bsp/apm32/libraries/Drivers/drv_gpio.h index 1da4fdb97b..6278d1924d 100644 --- a/bsp/apm32/libraries/Drivers/drv_gpio.h +++ b/bsp/apm32/libraries/Drivers/drv_gpio.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/apm32/libraries/Drivers/drv_hwtimer.c b/bsp/apm32/libraries/Drivers/drv_hwtimer.c new file mode 100644 index 0000000000..3cf7d1580b --- /dev/null +++ b/bsp/apm32/libraries/Drivers/drv_hwtimer.c @@ -0,0 +1,402 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-03-04 stevetong459 first version + */ + +#include + +#define LOG_TAG "drv.hwtimer" +#define DBG_LVL DBG_INFO +#include + +#ifdef RT_USING_HWTIMER + +static const struct rt_hwtimer_info _info = +{ + .maxfreq = 1000000, + .minfreq = 2000, + .maxcnt = 0xFFFF, + .cntmode = HWTIMER_CNTMODE_UP, +}; + +/* apm32 config class */ +struct apm32_timer +{ + char *name; + TMR_T *tmr; + IRQn_Type irqn; + rt_hwtimer_t device; +}; + +enum +{ +#ifdef BSP_USING_TMR1 + TMR1_INDEX, +#endif +#ifdef BSP_USING_TMR2 + TMR2_INDEX, +#endif +#ifdef BSP_USING_TMR3 + TMR3_INDEX, +#endif +#ifdef BSP_USING_TMR4 + TMR4_INDEX, +#endif +#ifdef BSP_USING_TMR5 + TMR5_INDEX, +#endif +#ifdef BSP_USING_TMR6 + TMR6_INDEX, +#endif +#ifdef BSP_USING_TMR7 + TMR7_INDEX, +#endif +#ifdef BSP_USING_TMR8 + TMR8_INDEX, +#endif +}; + +static struct apm32_timer tmr_config[] = +{ +#ifdef BSP_USING_TMR1 + { + "timer1", + TMR1, + TMR1_UP_IRQn, + }, +#endif +#ifdef BSP_USING_TMR2 + { + "timer2", + TMR2, + TMR2_IRQn, + }, +#endif +#ifdef BSP_USING_TMR3 + { + "timer3", + TMR3, + TMR3_IRQn, + }, +#endif +#ifdef BSP_USING_TMR4 + { + "timer4", + TMR4, + TMR4_IRQn, + }, +#endif +#ifdef BSP_USING_TMR5 + { + "timer5", + TMR5, + TMR5_IRQn, + }, +#endif +#ifdef BSP_USING_TMR6 + { + "timer6", + TMR6, + TMR6_IRQn, + }, +#endif +#ifdef BSP_USING_TMR7 + { + "timer7", + TMR7, + TMR7_IRQn, + }, +#endif +#ifdef BSP_USING_TMR8 + { + "timer8", + TMR8, + TMR8_UP_IRQn, + }, +#endif +}; + +static rt_uint32_t _hwtimer_clock_get(TMR_T *tmr) +{ + uint32_t pclk1; + + RCM_ReadPCLKFreq(&pclk1, NULL); + + return (rt_uint32_t)(pclk1 * ((RCM->CFG_B.APB1PSC != RCM_APB_DIV_1) ? 2 : 1)); +} + +static void _hwtimer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) +{ + TMR_BaseConfig_T base_config; + uint32_t prescaler = 0; + struct apm32_timer *timer_config; + + RT_ASSERT(timer != RT_NULL); + + if (state) + { + timer_config = (struct apm32_timer *)timer->parent.user_data; + if (timer_config->tmr == TMR1) + { + RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_TMR1); + } + else if (timer_config->tmr == TMR8) + { + RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_TMR8); + } + else if (timer_config->tmr == TMR2) + { + RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_TMR2); + } + else if (timer_config->tmr == TMR3) + { + RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_TMR3); + } + else if (timer_config->tmr == TMR4) + { + RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_TMR4); + } + else if (timer_config->tmr == TMR5) + { + RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_TMR5); + } + else if (timer_config->tmr == TMR6) + { + RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_TMR6); + } + else if (timer_config->tmr == TMR7) + { + RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_TMR7); + } + + prescaler = (uint32_t)(_hwtimer_clock_get(timer_config->tmr) / 10000) - 1; + + base_config.period = 10000 - 1; + base_config.division = prescaler; + base_config.clockDivision = TMR_CLOCK_DIV_1; + if (timer->info->cntmode == HWTIMER_CNTMODE_UP) + { + base_config.countMode = TMR_COUNTER_MODE_UP; + } + else + { + base_config.countMode = TMR_COUNTER_MODE_DOWN; + } + base_config.repetitionCounter = 0; + TMR_ConfigTimeBase(timer_config->tmr, &base_config); + + /* set the TIMx priority */ + NVIC_EnableIRQRequest(timer_config->irqn, 3, 0); + + /* clear update flag */ + TMR_ClearStatusFlag(timer_config->tmr, TMR_FLAG_UPDATE); + /* enable update request source */ + TMR_ConfigUpdateRequest(timer_config->tmr, TMR_UPDATE_SOURCE_REGULAR); + LOG_D("%s init success", timer_config->name); + } +} + +static rt_err_t _hwtimer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_t opmode) +{ + rt_err_t result = RT_EOK; + struct apm32_timer *timer_config = RT_NULL; + + RT_ASSERT(timer != RT_NULL); + + timer_config = (struct apm32_timer *)timer->parent.user_data; + + /* set timer_config counter */ + TMR_ConfigCounter(timer_config->tmr, 0); + /* set timer_config autoReload */ + TMR_ConfigAutoreload(timer_config->tmr, t - 1); + + if (opmode == HWTIMER_MODE_ONESHOT) + { + /* set timer to single mode */ + TMR_ConfigSinglePulseMode(timer_config->tmr, TMR_SPM_SINGLE); + } + else + { + TMR_ConfigSinglePulseMode(timer_config->tmr, TMR_SPM_REPETITIVE); + } + + TMR_EnableInterrupt(timer_config->tmr, TMR_INT_UPDATE); + + if (timer_config->tmr == TMR1 || timer_config->tmr == TMR8 || timer_config->tmr == TMR2 || + timer_config->tmr == TMR3 || timer_config->tmr == TMR4 || timer_config->tmr == TMR5) + { + if (timer_config->tmr->SMCTRL_B.SMFSEL != TMR_SLAVE_MODE_TRIGGER) + { + TMR_Enable(timer_config->tmr); + result = -RT_EOK; + } + } + else + { + TMR_Enable(timer_config->tmr); + result = -RT_EOK; + } + return result; +} + +static void _hwtimer_stop(rt_hwtimer_t *timer) +{ + struct apm32_timer *timer_config = RT_NULL; + RT_ASSERT(timer != RT_NULL); + timer_config = (struct apm32_timer *)timer->parent.user_data; + + TMR_DisableInterrupt(timer_config->tmr, TMR_INT_UPDATE); + TMR_Enable(timer_config->tmr); + TMR_ConfigCounter(timer_config->tmr, 0); +} + +static rt_err_t _hwtimer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) +{ + struct apm32_timer *timer_config = RT_NULL; + rt_err_t result = RT_EOK; + rt_uint32_t freq; + rt_uint16_t val; + + RT_ASSERT(timer != RT_NULL); + RT_ASSERT(arg != RT_NULL); + + timer_config = (struct apm32_timer *)timer->parent.user_data; + + switch (cmd) + { + case HWTIMER_CTRL_FREQ_SET: + /* set timer frequence */ + freq = *((rt_uint32_t *)arg); + + val = _hwtimer_clock_get(timer_config->tmr) / freq; + + TMR_ConfigPrescaler(timer_config->tmr, val - 1, TMR_PSC_RELOAD_IMMEDIATE); + break; + default: + result = -RT_ENOSYS; + break; + } + return result; +} + +static rt_uint32_t _hwtimer_counter_get(rt_hwtimer_t *timer) +{ + struct apm32_timer *timer_config = RT_NULL; + RT_ASSERT(timer != RT_NULL); + timer_config = (struct apm32_timer *)timer->parent.user_data; + + return timer_config->tmr->CNT; +} + +static const struct rt_hwtimer_ops _hwtimer_ops = +{ + .init = _hwtimer_init, + .start = _hwtimer_start, + .stop = _hwtimer_stop, + .count_get = _hwtimer_counter_get, + .control = _hwtimer_ctrl, +}; + +#ifdef BSP_USING_TMR1 +void TMR1_UP_IRQHandler(void) +{ + rt_interrupt_enter(); + rt_device_hwtimer_isr(&tmr_config[TMR1_INDEX].device); + TMR_ClearIntFlag(TMR1, TMR_INT_UPDATE); + rt_interrupt_leave(); +} +#endif +#ifdef BSP_USING_TMR2 +void TMR2_IRQHandler(void) +{ + rt_interrupt_enter(); + rt_device_hwtimer_isr(&tmr_config[TMR2_INDEX].device); + TMR_ClearIntFlag(TMR2, TMR_INT_UPDATE); + rt_interrupt_leave(); +} +#endif +#ifdef BSP_USING_TMR3 +void TMR3_IRQHandler(void) +{ + rt_interrupt_enter(); + rt_device_hwtimer_isr(&tmr_config[TMR3_INDEX].device); + TMR_ClearIntFlag(TMR3, TMR_INT_UPDATE); + rt_interrupt_leave(); +} +#endif +#ifdef BSP_USING_TMR4 +void TMR4_IRQHandler(void) +{ + rt_interrupt_enter(); + rt_device_hwtimer_isr(&tmr_config[TMR4_INDEX].device); + TMR_ClearIntFlag(TMR4, TMR_INT_UPDATE); + rt_interrupt_leave(); +} +#endif +#ifdef BSP_USING_TMR5 +void TMR5_IRQHandler(void) +{ + rt_interrupt_enter(); + rt_device_hwtimer_isr(&tmr_config[TMR5_INDEX].device); + TMR_ClearIntFlag(TMR5, TMR_INT_UPDATE); + rt_interrupt_leave(); +} +#endif +#ifdef BSP_USING_TMR6 +void TMR6_IRQHandler(void) +{ + rt_interrupt_enter(); + rt_device_hwtimer_isr(&tmr_config[TMR6_INDEX].device); + TMR_ClearIntFlag(TMR6, TMR_INT_UPDATE); + rt_interrupt_leave(); +} +#endif +#ifdef BSP_USING_TMR7 +void TMR7_IRQHandler(void) +{ + rt_interrupt_enter(); + rt_device_hwtimer_isr(&tmr_config[TMR7_INDEX].device); + TMR_ClearIntFlag(TMR7, TMR_INT_UPDATE); + rt_interrupt_leave(); +} +#endif +#ifdef BSP_USING_TMR8 +void TMR8_UP_IRQHandler(void) +{ + rt_interrupt_enter(); + rt_device_hwtimer_isr(&tmr_config[TMR8_INDEX].device); + TMR_ClearIntFlag(TMR8, TMR_INT_UPDATE); + rt_interrupt_leave(); +} +#endif + +static int rt_hw_hwtimer_init(void) +{ + int i = 0; + int result = RT_EOK; + + for (i = 0; i < sizeof(tmr_config) / sizeof(tmr_config[0]); i++) + { + tmr_config[i].device.info = &_info; + tmr_config[i].device.ops = &_hwtimer_ops; + if (rt_device_hwtimer_register(&tmr_config[i].device, tmr_config[i].name, &tmr_config[i]) == RT_EOK) + { + LOG_D("%s register success", tmr_config[i].name); + } + else + { + LOG_E("%s register failed", tmr_config[i].name); + result = -RT_ERROR; + } + } + + return result; +} +INIT_BOARD_EXPORT(rt_hw_hwtimer_init); + +#endif /* RT_USING_HWTIMER */ diff --git a/bsp/apm32/libraries/Drivers/drv_pwm.c b/bsp/apm32/libraries/Drivers/drv_pwm.c new file mode 100644 index 0000000000..5ddef39e42 --- /dev/null +++ b/bsp/apm32/libraries/Drivers/drv_pwm.c @@ -0,0 +1,484 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-03-04 stevetong459 first version + */ + +#include + +#ifdef RT_USING_PWM +#include + +#define LOG_TAG "drv.pwm" +#define DBG_LVL DBG_INFO +#include + +#define MAX_PERIOD 65535 +#define MIN_PERIOD 3 +#define MIN_PULSE 2 + +#define _PWM_GPIO_INIT(port_num, pin_num) \ +do \ +{ \ + RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIO##port_num); \ + gpio_config->pin = GPIO_PIN_##pin_num; \ + gpio_config->mode = GPIO_MODE_AF_PP; \ + gpio_config->speed = GPIO_SPEED_50MHz; \ + GPIO_Config(GPIO##port_num, gpio_config); \ +} while (0) + +enum +{ +#ifdef BSP_USING_PWM1 + PWM1_INDEX, +#endif +#ifdef BSP_USING_PWM2 + PWM2_INDEX, +#endif +#ifdef BSP_USING_PWM3 + PWM3_INDEX, +#endif +#ifdef BSP_USING_PWM4 + PWM4_INDEX, +#endif +#ifdef BSP_USING_PWM5 + PWM5_INDEX, +#endif +#ifdef BSP_USING_PWM8 + PWM8_INDEX, +#endif +}; + +struct apm32_pwm +{ + char *name; + TMR_T *tmr; + rt_uint8_t channel; + struct rt_device_pwm pwm_device; +}; + +static struct apm32_pwm pwm_config[] = +{ +#ifdef BSP_USING_PWM1 + { + "pwm1", + TMR1, + 0, + }, +#endif +#ifdef BSP_USING_PWM2 + { + "pwm2", + TMR2, + 0, + }, +#endif +#ifdef BSP_USING_PWM3 + { + "pwm3", + TMR3, + 0, + }, +#endif +#ifdef BSP_USING_PWM4 + { + "pwm4", + TMR4, + 0, + }, +#endif +#ifdef BSP_USING_PWM5 + { + "pwm5", + TMR5, + 0, + }, +#endif +#ifdef BSP_USING_PWM8 + { + "pwm8", + TMR8, + 0, + }, +#endif +}; + +static void _pwm_channel_init(GPIO_Config_T *gpio_config) +{ +#ifdef BSP_USING_PWM1_CH1 + pwm_config[PWM1_INDEX].channel |= 1 << 0; + _PWM_GPIO_INIT(A, 8); +#endif +#ifdef BSP_USING_PWM1_CH2 + pwm_config[PWM1_INDEX].channel |= 1 << 1; + _PWM_GPIO_INIT(A, 9); +#endif +#ifdef BSP_USING_PWM1_CH3 + pwm_config[PWM1_INDEX].channel |= 1 << 2; + _PWM_GPIO_INIT(A, 10); +#endif +#ifdef BSP_USING_PWM1_CH4 + pwm_config[PWM1_INDEX].channel |= 1 << 3; + _PWM_GPIO_INIT(A, 11); +#endif +#ifdef BSP_USING_PWM2_CH1 + pwm_config[PWM2_INDEX].channel |= 1 << 0; + _PWM_GPIO_INIT(A, 0); +#endif +#ifdef BSP_USING_PWM2_CH2 + pwm_config[PWM2_INDEX].channel |= 1 << 1; + _PWM_GPIO_INIT(A, 1); +#endif +#ifdef BSP_USING_PWM2_CH3 + pwm_config[PWM2_INDEX].channel |= 1 << 2; + _PWM_GPIO_INIT(A, 2); +#endif +#ifdef BSP_USING_PWM2_CH4 + pwm_config[PWM2_INDEX].channel |= 1 << 3; + _PWM_GPIO_INIT(A, 3); +#endif +#ifdef BSP_USING_PWM3_CH1 + pwm_config[PWM3_INDEX].channel |= 1 << 0; + GPIO_ConfigPinRemap(GPIO_FULL_REMAP_TMR3); + _PWM_GPIO_INIT(C, 6); +#endif +#ifdef BSP_USING_PWM3_CH2 + pwm_config[PWM3_INDEX].channel |= 1 << 1; + GPIO_ConfigPinRemap(GPIO_FULL_REMAP_TMR3); + _PWM_GPIO_INIT(C, 7); +#endif +#ifdef BSP_USING_PWM3_CH3 + pwm_config[PWM3_INDEX].channel |= 1 << 2; + GPIO_ConfigPinRemap(GPIO_FULL_REMAP_TMR3); + _PWM_GPIO_INIT(C, 8); +#endif +#ifdef BSP_USING_PWM3_CH4 + pwm_config[PWM3_INDEX].channel |= 1 << 3; + GPIO_ConfigPinRemap(GPIO_FULL_REMAP_TMR3); + _PWM_GPIO_INIT(C, 9); +#endif +#ifdef BSP_USING_PWM4_CH1 + pwm_config[PWM4_INDEX].channel |= 1 << 0; + _PWM_GPIO_INIT(B, 6); +#endif +#ifdef BSP_USING_PWM4_CH2 + pwm_config[PWM4_INDEX].channel |= 1 << 1; + _PWM_GPIO_INIT(B, 7); +#endif +#ifdef BSP_USING_PWM4_CH3 + pwm_config[PWM4_INDEX].channel |= 1 << 2; + _PWM_GPIO_INIT(B, 8); +#endif +#ifdef BSP_USING_PWM4_CH4 + pwm_config[PWM4_INDEX].channel |= 1 << 3; + _PWM_GPIO_INIT(B, 9); +#endif +#ifdef BSP_USING_PWM5_CH1 + pwm_config[PWM5_INDEX].channel |= 1 << 0; + _PWM_GPIO_INIT(A, 0); +#endif +#ifdef BSP_USING_PWM5_CH2 + pwm_config[PWM5_INDEX].channel |= 1 << 1; + _PWM_GPIO_INIT(A, 1); +#endif +#ifdef BSP_USING_PWM5_CH3 + pwm_config[PWM5_INDEX].channel |= 1 << 2; + _PWM_GPIO_INIT(A, 2); +#endif +#ifdef BSP_USING_PWM5_CH4 + pwm_config[PWM5_INDEX].channel |= 1 << 3; + _PWM_GPIO_INIT(A, 3); +#endif +#ifdef BSP_USING_PWM8_CH1 + pwm_config[PWM8_INDEX].channel |= 1 << 0; + _PWM_GPIO_INIT(C, 6); +#endif +#ifdef BSP_USING_PWM8_CH2 + pwm_config[PWM8_INDEX].channel |= 1 << 1; + _PWM_GPIO_INIT(C, 7); +#endif +#ifdef BSP_USING_PWM8_CH3 + pwm_config[PWM8_INDEX].channel |= 1 << 2; + _PWM_GPIO_INIT(C, 8); +#endif +#ifdef BSP_USING_PWM8_CH4 + pwm_config[PWM8_INDEX].channel |= 1 << 3; + _PWM_GPIO_INIT(C, 9); +#endif +} + +static rt_err_t _pwm_hw_init(struct apm32_pwm *device) +{ + rt_err_t result = RT_EOK; + TMR_T *tmr = RT_NULL; + TMR_BaseConfig_T base_config; + TMR_OCConfig_T oc_config; + + RT_ASSERT(device != RT_NULL); + + tmr = (TMR_T *)device->tmr; + + if (tmr == TMR1) + { + RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_TMR1); + } + else if (tmr == TMR8) + { + RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_TMR8); + } + else if (tmr == TMR2) + { + RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_TMR2); + } + else if (tmr == TMR3) + { + RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_TMR3); + } + else if (tmr == TMR4) + { + RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_TMR4); + } + else if (tmr == TMR5) + { + RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_TMR5); + } + + /* configure the tmrer to pwm mode */ + base_config.division = 0; + base_config.countMode = TMR_COUNTER_MODE_UP; + base_config.period = 0; + base_config.clockDivision = TMR_CLOCK_DIV_1; + TMR_ConfigTimeBase(tmr, &base_config); + + TMR_SelectOutputTrigger(tmr, TMR_TRGO_SOURCE_RESET); + TMR_DisableMasterSlaveMode(tmr); + + oc_config.mode = TMR_OC_MODE_PWM1; + oc_config.pulse = 0; + oc_config.polarity = TMR_OC_POLARITY_HIGH; + oc_config.nIdleState = TMR_OC_NIDLE_STATE_RESET; + oc_config.idleState = TMR_OC_IDLE_STATE_RESET; + oc_config.outputState = TMR_OC_STATE_ENABLE; + + /* config pwm channel */ + if (device->channel & 0x01) + { + TMR_ConfigOC1(tmr, &oc_config); + } + + if (device->channel & 0x02) + { + TMR_ConfigOC2(tmr, &oc_config); + } + + if (device->channel & 0x04) + { + TMR_ConfigOC3(tmr, &oc_config); + } + + if (device->channel & 0x08) + { + TMR_ConfigOC4(tmr, &oc_config); + } + + /* enable update request source */ + TMR_ConfigUpdateRequest(tmr, TMR_UPDATE_SOURCE_REGULAR); + + return result; +} + +static rt_uint32_t _pwm_timer_clock_get(TMR_T *tmr) +{ + uint32_t pclk1; + + RCM_ReadPCLKFreq(&pclk1, NULL); + + return (rt_uint32_t)(pclk1 * ((RCM->CFG_B.APB1PSC != RCM_APB_DIV_1) ? 2 : 1)); +} + +static rt_err_t _pwm_enable(TMR_T *tmr, struct rt_pwm_configuration *configuration, rt_bool_t enable) +{ + rt_uint32_t channel = (configuration->channel - 1) << 2; + + if (enable) + { + if (configuration->complementary) + { + TMR_EnableCCxNChannel(tmr, (TMR_CHANNEL_T)(0x01 << (channel & 0x1FU))); + } + else + { + TMR_EnableCCxChannel(tmr, (TMR_CHANNEL_T)(0x01 << (channel & 0x1FU))); + } + if (tmr == TMR1 || tmr == TMR8) + { + TMR_EnablePWMOutputs(tmr); + } + TMR_Enable(tmr); + } + else + { + if (configuration->complementary) + { + TMR_DisableCCxNChannel(tmr, (TMR_CHANNEL_T)(0x01 << (channel & 0x1FU))); + } + else + { + TMR_DisableCCxChannel(tmr, (TMR_CHANNEL_T)(0x01 << (channel & 0x1FU))); + } + if (tmr == TMR1 || tmr == TMR8) + { + TMR_DisablePWMOutputs(tmr); + } + TMR_Disable(tmr); + } + + return RT_EOK; +} + +static rt_err_t _pwm_get(TMR_T *tmr, struct rt_pwm_configuration *configuration) +{ + /* Converts the channel number to the channel number of library */ + rt_uint32_t channel = (configuration->channel - 1) << 2; + rt_uint64_t timer_clock; + rt_uint32_t timer_reload, timer_psc; + + timer_clock = _pwm_timer_clock_get(tmr); + + if (tmr->CTRL1_B.CLKDIV == TMR_CLOCK_DIV_2) + { + timer_clock <<= 1; + } + else if (tmr->CTRL1_B.CLKDIV == TMR_CLOCK_DIV_4) + { + timer_clock <<= 2; + } + + uint32_t temp; + temp = (uint32_t)tmr; + temp += (uint32_t)(0x34 + channel); + /* Convert nanosecond to frequency and duty cycle.*/ + timer_clock /= 1000000UL; + + timer_reload = tmr->AUTORLD; + timer_psc = tmr->PSC; + configuration->period = (timer_reload + 1) * (timer_psc + 1) * 1000UL / timer_clock; + configuration->pulse = ((*(__IO uint32_t *)temp) + 1) * (timer_psc + 1) * 1000UL / timer_clock; + + return RT_EOK; +} + +static rt_err_t _pwm_set(TMR_T *tmr, struct rt_pwm_configuration *configuration) +{ + rt_uint32_t period, pulse; + rt_uint64_t timer_clock, psc; + rt_uint32_t channel = 0x04 * (configuration->channel - 1); + uint32_t temp = (uint32_t)tmr; + + timer_clock = _pwm_timer_clock_get(tmr); + + /* Convert nanosecond to frequency and duty cycle. */ + timer_clock /= 1000000UL; + period = (unsigned long long)configuration->period * timer_clock / 1000ULL ; + psc = period / MAX_PERIOD + 1; + period = period / psc; + tmr->PSC = (uint16_t)(psc - 1); + + if (period < MIN_PERIOD) + { + period = MIN_PERIOD; + } + tmr->AUTORLD = (uint16_t)(period - 1); + + pulse = (unsigned long long)configuration->pulse * timer_clock / psc / 1000ULL; + if (pulse < MIN_PULSE) + { + pulse = MIN_PULSE; + } + else if (pulse > period) + { + pulse = period; + } + + temp += (uint32_t)(0x34 + channel); + *(__IO uint32_t *)temp = pulse - 1; + + tmr->CNT = 0; + + /* Update frequency value */ + TMR_GenerateEvent(tmr, TMR_EVENT_UPDATE); + + return RT_EOK; +} + +static rt_err_t _pwm_control(struct rt_device_pwm *device, int cmd, void *arg) +{ + struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg; + TMR_T *tmr = (TMR_T *)device->parent.user_data; + + switch (cmd) + { + case PWMN_CMD_ENABLE: + configuration->complementary = RT_TRUE; + case PWM_CMD_ENABLE: + return _pwm_enable(tmr, configuration, RT_TRUE); + case PWMN_CMD_DISABLE: + configuration->complementary = RT_FALSE; + case PWM_CMD_DISABLE: + return _pwm_enable(tmr, configuration, RT_FALSE); + case PWM_CMD_SET: + return _pwm_set(tmr, configuration); + case PWM_CMD_GET: + return _pwm_get(tmr, configuration); + default: + return RT_EINVAL; + } +} + +static const struct rt_pwm_ops _pwm_ops = +{ + _pwm_control +}; + +static int rt_hw_pwm_init(void) +{ + rt_uint32_t i = 0; + rt_err_t result = RT_EOK; + GPIO_Config_T gpio_config; + + _pwm_channel_init(&gpio_config); + + for (i = 0; i < sizeof(pwm_config) / sizeof(pwm_config[0]); i++) + { + /* pwm init */ + if (_pwm_hw_init(&pwm_config[i]) != RT_EOK) + { + LOG_E("%s init failed", pwm_config[i].name); + return -RT_ERROR; + } + else + { + LOG_D("%s init success", pwm_config[i].name); + + /* register pwm device */ + if (rt_device_pwm_register(&pwm_config[i].pwm_device, pwm_config[i].name, &_pwm_ops, pwm_config[i].tmr) == RT_EOK) + { + LOG_D("%s register success", pwm_config[i].name); + } + else + { + LOG_E("%s register failed", pwm_config[i].name); + result = -RT_ERROR; + } + } + } + + return result; +} +INIT_DEVICE_EXPORT(rt_hw_pwm_init); + +#endif /* RT_USING_PWM */ diff --git a/bsp/apm32/libraries/Drivers/drv_rtc.c b/bsp/apm32/libraries/Drivers/drv_rtc.c new file mode 100644 index 0000000000..5eee7d29ed --- /dev/null +++ b/bsp/apm32/libraries/Drivers/drv_rtc.c @@ -0,0 +1,170 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-03-04 stevetong459 first version + */ + +#include "board.h" +#include + +#ifdef BSP_USING_ONCHIP_RTC + +#define LOG_TAG "drv.rtc" +#define DBG_LVL DBG_INFO +#include + +#ifndef LSI_VALUE + #define LSI_VALUE ((uint32_t)40000) +#endif +#ifndef LSE_VALUE + #define LSE_VALUE ((uint32_t)32768) +#endif + +#define DRV_RTC_TIME_OUT 0xFFF + +static rt_rtc_dev_t apm32_rtc_dev; + +/** + * @brief This function will initialize the rtc on chip. + * + * @return RT_EOK indicates successful initialize, other value indicates failed; + */ +static rt_err_t _rtc_init(void) +{ + volatile rt_uint32_t counter = 0; + + /* Enable RTC Clock */ + RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_PMU | RCM_APB1_PERIPH_BAKR); + PMU_EnableBackupAccess(); + + /* Config RTC clock */ +#ifdef BSP_RTC_USING_LSI + RCM_EnableLSI(); + while (!RCM_ReadStatusFlag(RCM_FLAG_LSIRDY)) + { + if (++counter > DRV_RTC_TIME_OUT) + { + return RT_ETIMEOUT; + } + } + RCM_ConfigRTCCLK(RCM_RTCCLK_LSI); +#else + RCM_ConfigLSE(RCM_LSE_OPEN); + while (!RCM_ReadStatusFlag(RCM_FLAG_LSERDY)) + { + if (++counter > DRV_RTC_TIME_OUT) + { + return RT_ETIMEOUT; + } + } + RCM_ConfigRTCCLK(RCM_RTCCLK_LSE); +#endif + + RCM_EnableRTCCLK(); + + RTC_WaitForSynchor(); + + counter = 0; + while (!RTC_ReadStatusFlag(RTC_FLAG_OC)) + { + if (++counter > DRV_RTC_TIME_OUT) + { + return RT_ETIMEOUT; + } + } + + RTC_EnableConfigMode(); + + RTC_ClearStatusFlag(RTC_FLAG_OVR | RTC_FLAG_ALR | RTC_FLAG_SEC); + +#ifdef BSP_RTC_USING_LSI + RTC_ConfigPrescaler(LSI_VALUE - 1); +#else + RTC_ConfigPrescaler(LSE_VALUE - 1); +#endif + + return RT_EOK; +} + +/** + * @brief This function will initialize the rtc on chip. + * + * @return RT_EOK indicates successful initialize, other value indicates failed; + */ +static rt_err_t _rtc_get_secs(void *args) +{ + volatile rt_uint32_t counter = 0; + + while (!RTC_ReadStatusFlag(RTC_FLAG_OC)) + { + if (++counter > DRV_RTC_TIME_OUT) + { + return RT_ETIMEOUT; + } + } + + *(rt_uint32_t *) args = RTC_ReadCounter(); + + return RT_EOK; +} + +static rt_err_t _rtc_set_secs(void *args) +{ + volatile rt_uint32_t counter = 0; + + while (!RTC_ReadStatusFlag(RTC_FLAG_OC)) + { + if (++counter > DRV_RTC_TIME_OUT) + { + return RT_ETIMEOUT; + } + } + + RTC_ConfigCounter(*(rt_uint32_t *)args); + + return RT_EOK; +} + + +static const struct rt_rtc_ops _rtc_ops = +{ + _rtc_init, + _rtc_get_secs, + _rtc_set_secs, + RT_NULL, + RT_NULL, + RT_NULL, + RT_NULL, +}; + +/** + * @brief RTC initialization function. + * + * @return RT_EOK indicates successful initialization, other value indicates failed; + */ +static int rt_hw_rtc_init(void) +{ + rt_err_t result = RT_EOK; + + apm32_rtc_dev.ops = &_rtc_ops; + + if (rt_hw_rtc_register(&apm32_rtc_dev, "rtc", RT_DEVICE_FLAG_RDWR, RT_NULL) != RT_EOK) + { + LOG_E("rtc init failed"); + result = RT_ERROR; + } + else + { + LOG_D("rtc init success"); + } + + return result; +} + +INIT_DEVICE_EXPORT(rt_hw_rtc_init); + +#endif /* BSP_USING_ONCHIP_RTC */ diff --git a/bsp/apm32/libraries/Drivers/drv_soft_i2c.c b/bsp/apm32/libraries/Drivers/drv_soft_i2c.c new file mode 100644 index 0000000000..8911da89ad --- /dev/null +++ b/bsp/apm32/libraries/Drivers/drv_soft_i2c.c @@ -0,0 +1,244 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-03-04 stevetong459 first version + */ + +#include "board.h" +#include + +#ifdef RT_USING_I2C + +#define LOG_TAG "drv.i2c" +#define DBG_LVL DBG_INFO +#include + +#if !defined(BSP_USING_I2C1) && !defined(BSP_USING_I2C2) && !defined(BSP_USING_I2C3) && !defined(BSP_USING_I2C4) + #error "Please define at least one BSP_USING_I2Cx" +#endif + +/* apm32 i2c config class */ +struct apm32_soft_i2c_config +{ + rt_uint8_t scl_pin; + rt_uint8_t sda_pin; + const char *bus_name; +}; + +/* apm32 i2c dirver class */ +struct apm32_soft_i2c +{ + struct rt_i2c_bit_ops ops; + struct rt_i2c_bus_device i2c2_bus; +}; + +static const struct apm32_soft_i2c_config soft_i2c_config[] = +{ +#ifdef BSP_USING_I2C1 + { + BSP_I2C1_SCL_PIN, + BSP_I2C1_SDA_PIN, + "i2c1" + } +#endif +#ifdef BSP_USING_I2C2 + { + BSP_I2C2_SCL_PIN, + BSP_I2C2_SDA_PIN, + "i2c2" + } +#endif +#ifdef BSP_USING_I2C3 + { + BSP_I2C3_SCL_PIN, + BSP_I2C3_SDA_PIN, + "i2c3" + } +#endif +#ifdef BSP_USING_I2C4 + { + BSP_I2C4_SCL_PIN, + BSP_I2C4_SDA_PIN, + "i2c4" + } +#endif +}; + +static struct apm32_soft_i2c i2c_obj[sizeof(soft_i2c_config) / sizeof(soft_i2c_config[0])]; + +/** + * @brief This function will config gpio of soft i2c. + * + * @param i2c is a pointer to the object of soft i2c. + */ +static void _soft_i2c_gpio_init(struct apm32_soft_i2c *i2c) +{ + struct apm32_soft_i2c_config *cfg = (struct apm32_soft_i2c_config *)i2c->ops.data; + + rt_pin_mode(cfg->scl_pin, PIN_MODE_OUTPUT_OD); + rt_pin_mode(cfg->sda_pin, PIN_MODE_OUTPUT_OD); + + rt_pin_write(cfg->scl_pin, PIN_HIGH); + rt_pin_write(cfg->sda_pin, PIN_HIGH); +} + +/** + * @brief This function sets the sda pin. + * + * @param data is a pointer to the i2c config class. + * + * @param state is the level of sda pin. + */ +static void _soft_i2c_set_sda(void *data, rt_int32_t state) +{ + struct apm32_soft_i2c_config *cfg = (struct apm32_soft_i2c_config *)data; + + rt_pin_write(cfg->sda_pin, state ? PIN_HIGH : PIN_LOW); +} + +/** + * @brief This function sets the scl pin. + * + * @param data is a pointer to the i2c config class. + * + * @param state is the level of scl pin. + */ +static void _soft_i2c_set_scl(void *data, rt_int32_t state) +{ + struct apm32_soft_i2c_config *cfg = (struct apm32_soft_i2c_config *)data; + + rt_pin_write(cfg->scl_pin, state ? PIN_HIGH : PIN_LOW); +} + +/** + * @brief This function gets the sda pin state. + * + * @param data is a pointer to the i2c config class. + */ +static rt_int32_t _soft_i2c_get_sda(void *data) +{ + struct apm32_soft_i2c_config *cfg = (struct apm32_soft_i2c_config *)data; + return rt_pin_read(cfg->sda_pin); +} + +/** + * @brief This function gets the scl pin state. + * + * @param data is a pointer to the i2c config class. + */ +static rt_int32_t _soft_i2c_get_scl(void *data) +{ + struct apm32_soft_i2c_config *cfg = (struct apm32_soft_i2c_config *)data; + return rt_pin_read(cfg->scl_pin); +} + +/** + * @brief The time delay function in microseconds. + * + * @param us is the microseconds to delay. + */ +static void _soft_i2c_udelay(rt_uint32_t us) +{ + rt_uint32_t count_old = SysTick->VAL; + rt_uint32_t count_now; + rt_uint32_t count = 0; + rt_uint32_t reload = SysTick->LOAD; + rt_uint32_t count_pre_us = (reload * RT_TICK_PER_SECOND) / 1000000; + + while (count_pre_us * us > count) + { + count_now = SysTick->VAL; + if (count_now != count_old) + { + if (count_now < count_old) + { + count += count_old - count_now; + } + else + { + count += reload - count_now + count_old; + } + count_old = count_now; + } + } +} + +/** + * @brief This function will unlock i2c, if it is locked. + * + * @param cfg is a pointer to i2c config class. + * + * @return RT_EOK indicates successful unlock, other value indicates failed. + */ +static rt_err_t apm32_i2c_bus_unlock(const struct apm32_soft_i2c_config *cfg) +{ + rt_int32_t i = 0; + + if (PIN_LOW == rt_pin_read(cfg->sda_pin)) + { + while (i++ < 9) + { + rt_pin_write(cfg->scl_pin, PIN_HIGH); + _soft_i2c_udelay(100); + rt_pin_write(cfg->scl_pin, PIN_LOW); + _soft_i2c_udelay(100); + } + } + if (PIN_LOW == rt_pin_read(cfg->sda_pin)) + { + return -RT_ERROR; + } + + return RT_EOK; +} + +static const struct rt_i2c_bit_ops apm32_bit_ops_default = +{ + .data = RT_NULL, + .set_sda = _soft_i2c_set_sda, + .set_scl = _soft_i2c_set_scl, + .get_sda = _soft_i2c_get_sda, + .get_scl = _soft_i2c_get_scl, + .udelay = _soft_i2c_udelay, + .delay_us = 1, + .timeout = 100 +}; + +/** + * @brief I2C initialization function. + * + * @return RT_EOK indicates successful initialization, other value indicates failed; + */ +int rt_hw_i2c_init(void) +{ + rt_size_t obj_num = sizeof(i2c_obj) / sizeof(struct apm32_soft_i2c); + rt_err_t result; + + for (int i = 0; i < obj_num; i++) + { + i2c_obj[i].ops = apm32_bit_ops_default; + i2c_obj[i].ops.data = (void *)&soft_i2c_config[i]; + i2c_obj[i].i2c2_bus.priv = &i2c_obj[i].ops; + _soft_i2c_gpio_init(&i2c_obj[i]); + + result = rt_i2c_bit_add_bus(&i2c_obj[i].i2c2_bus, soft_i2c_config[i].bus_name); + + RT_ASSERT(result == RT_EOK); + + apm32_i2c_bus_unlock(&soft_i2c_config[i]); + + LOG_D("software simulation %s init done, pin scl: %s, pin sda: %s", + soft_i2c_config[i].bus_name, + soft_i2c_config[i].scl_pin_name, + soft_i2c_config[i].sda_pin_name); + } + + return RT_EOK; +} +INIT_BOARD_EXPORT(rt_hw_i2c_init); + +#endif /* RT_USING_I2C */ diff --git a/bsp/apm32/libraries/Drivers/drv_spi.c b/bsp/apm32/libraries/Drivers/drv_spi.c new file mode 100644 index 0000000000..db4dc734e0 --- /dev/null +++ b/bsp/apm32/libraries/Drivers/drv_spi.c @@ -0,0 +1,264 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-03-04 stevetong459 first version + */ + +#include "drv_spi.h" + +#define LOG_TAG "drv.spi" +#define DBG_LVL DBG_INFO +#include + +#if defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2) || defined(BSP_USING_SPI3) + +static rt_err_t _spi_configure(struct rt_spi_device *spi_drv, struct rt_spi_configuration *cfg) +{ + RT_ASSERT(spi_drv != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + SPI_Config_T hw_spi_config; + SPI_T *spi = (SPI_T *)spi_drv->bus->parent.user_data; + uint32_t hw_spi_apb_clock; +#if (DBG_LVL == DBG_LOG) + uint32_t hw_spi_sys_clock = RCM_ReadSYSCLKFreq(); +#endif + + hw_spi_config.mode = (cfg->mode & RT_SPI_SLAVE) ? SPI_MODE_SLAVE : SPI_MODE_MASTER; + hw_spi_config.direction = (cfg->mode & RT_SPI_3WIRE) ? SPI_DIRECTION_1LINE_RX : SPI_DIRECTION_2LINES_FULLDUPLEX; + hw_spi_config.phase = (cfg->mode & RT_SPI_CPHA) ? SPI_CLKPHA_2EDGE : SPI_CLKPHA_1EDGE; + hw_spi_config.polarity = (cfg->mode & RT_SPI_CPOL) ? SPI_CLKPOL_HIGH : SPI_CLKPOL_LOW; + hw_spi_config.nss = (cfg->mode & RT_SPI_NO_CS) ? SPI_NSS_HARD : SPI_NSS_SOFT; + hw_spi_config.firstBit = (cfg->mode & RT_SPI_MSB) ? SPI_FIRSTBIT_MSB : SPI_FIRSTBIT_LSB; + + if (cfg->data_width == 8) + { + hw_spi_config.length = SPI_DATA_LENGTH_8B; + } + else if (cfg->data_width == 16) + { + hw_spi_config.length = SPI_DATA_LENGTH_16B; + } + else + { + return RT_EIO; + } + + RCM_ReadPCLKFreq(NULL, &hw_spi_apb_clock); + + if (cfg->max_hz >= hw_spi_apb_clock / 2) + { + hw_spi_config.baudrateDiv = SPI_BAUDRATE_DIV_2; + } + else if (cfg->max_hz >= hw_spi_apb_clock / 4) + { + hw_spi_config.baudrateDiv = SPI_BAUDRATE_DIV_4; + } + else if (cfg->max_hz >= hw_spi_apb_clock / 8) + { + hw_spi_config.baudrateDiv = SPI_BAUDRATE_DIV_8; + } + else if (cfg->max_hz >= hw_spi_apb_clock / 16) + { + hw_spi_config.baudrateDiv = SPI_BAUDRATE_DIV_16; + } + else if (cfg->max_hz >= hw_spi_apb_clock / 32) + { + hw_spi_config.baudrateDiv = SPI_BAUDRATE_DIV_32; + } + else if (cfg->max_hz >= hw_spi_apb_clock / 64) + { + hw_spi_config.baudrateDiv = SPI_BAUDRATE_DIV_64; + } + else if (cfg->max_hz >= hw_spi_apb_clock / 128) + { + hw_spi_config.baudrateDiv = SPI_BAUDRATE_DIV_128; + } + else + { + /* min prescaler 256 */ + hw_spi_config.baudrateDiv = SPI_BAUDRATE_DIV_256; + } + + LOG_D("sys freq: %d, pclk2 freq: %d, SPI limiting freq: %d, BaudRatePrescaler: %d", + hw_spi_sys_clock, hw_spi_apb_clock, cfg->max_hz, hw_spi_config.baudrateDiv); + + SPI_Config(spi, &hw_spi_config); + SPI_Enable(spi); + + return RT_EOK; +} + +static rt_uint32_t _spi_xfer(struct rt_spi_device *device, struct rt_spi_message *message) +{ + RT_ASSERT(device != NULL); + RT_ASSERT(message != NULL); + + rt_base_t cs_pin = (rt_base_t)device->parent.user_data; + SPI_T *spi = (SPI_T *)device->bus->parent.user_data; + struct rt_spi_configuration *config = &device->config; + + /* take CS */ + if (message->cs_take) + { + rt_pin_write(cs_pin, PIN_LOW); + LOG_D("spi take cs\n"); + } + + if (config->data_width <= 8) + { + const rt_uint8_t *send_ptr = message->send_buf; + rt_uint8_t *recv_ptr = message->recv_buf; + rt_uint32_t size = message->length; + + LOG_D("spi poll transfer start: %d\n", size); + + while (size--) + { + rt_uint8_t data = 0xFF; + + if (send_ptr != RT_NULL) + { + data = *send_ptr++; + } + + /* Wait until the transmit buffer is empty */ + while (SPI_I2S_ReadStatusFlag(spi, SPI_FLAG_TXBE) == RESET); + + SPI_I2S_TxData(spi, data); + + /* Wait until a data is received */ + while (SPI_I2S_ReadStatusFlag(spi, SPI_FLAG_RXBNE) == RESET); + + data = SPI_I2S_RxData(spi); + + if (recv_ptr != RT_NULL) + { + *recv_ptr++ = data; + } + } + LOG_D("spi poll transfer finsh\n"); + } + else if (config->data_width <= 16) + { + const rt_uint16_t *send_ptr = message->send_buf; + rt_uint16_t *recv_ptr = message->recv_buf; + rt_uint32_t size = message->length; + + while (size--) + { + rt_uint16_t data = 0xFF; + + if (send_ptr != RT_NULL) + { + data = *send_ptr++; + } + + /*Wait until the transmit buffer is empty */ + while (SPI_I2S_ReadStatusFlag(spi, SPI_FLAG_TXBE) == RESET); + /* Send the byte */ + SPI_I2S_TxData(spi, data); + + /*Wait until a data is received */ + while (SPI_I2S_ReadStatusFlag(spi, SPI_FLAG_RXBNE) == RESET); + /* Get the received data */ + data = SPI_I2S_RxData(spi); + + if (recv_ptr != RT_NULL) + { + *recv_ptr++ = data; + } + } + } + + /* release CS */ + if (message->cs_release) + { + rt_pin_write(cs_pin, PIN_HIGH); + LOG_D("spi release cs\n"); + } + + return message->length; +}; + +static const struct rt_spi_ops _spi_ops = +{ + _spi_configure, + _spi_xfer +}; + +static int rt_hw_spi_init(void) +{ + int result = 0; + GPIO_Config_T gpio_config; + +#ifdef BSP_USING_SPI1 + static struct rt_spi_bus spi_bus1; + spi_bus1.parent.user_data = (void *)SPI1; + + result = rt_spi_bus_register(&spi_bus1, "spi1", &_spi_ops); + + RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIOA); + RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_SPI1); + + /* SPI1_SCK(PA5) SPI1_MOSI(PA7) */ + gpio_config.mode = GPIO_MODE_AF_PP; + gpio_config.speed = GPIO_SPEED_50MHz; + gpio_config.pin = (GPIO_PIN_5 | GPIO_PIN_7); + GPIO_Config(GPIOA, &gpio_config); + /* SPI1_MISO(PA6) */ + gpio_config.mode = GPIO_MODE_IN_FLOATING; + gpio_config.speed = GPIO_SPEED_50MHz; + gpio_config.pin = GPIO_PIN_6; + GPIO_Config(GPIOA, &gpio_config); +#endif + +#ifdef BSP_USING_SPI2 + static struct rt_spi_bus spi_bus2; + spi_bus2.parent.user_data = (void *)SPI2; + + result = rt_spi_bus_register(&spi_bus2, "spi2", &_spi_ops); + + RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIOB); + RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_SPI2); + + /* SPI2_SCK(PB13) SPI2_MOSI(PB15) */ + gpio_config.mode = GPIO_MODE_AF_PP; + gpio_config.speed = GPIO_SPEED_50MHz; + gpio_config.pin = (GPIO_PIN_13 | GPIO_PIN_15); + GPIO_Config(GPIOB, &gpio_config); + /* SPI2_MISO(PB14) */ + gpio_config.mode = GPIO_MODE_IN_FLOATING; + gpio_config.speed = GPIO_SPEED_50MHz; + gpio_config.pin = GPIO_PIN_14; + GPIO_Config(GPIOB, &gpio_config); +#endif + +#ifdef BSP_USING_SPI3 + static struct rt_spi_bus spi_bus3; + spi_bus3.parent.user_data = (void *)SPI3; + + result = rt_spi_bus_register(&spi_bus3, "spi3", &_spi_ops); + + RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIOB); + RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_SPI3); + + /* SPI3_SCK(PB3) SPI3_MOSI(PB5) */ + gpio_config.mode = GPIO_MODE_AF_PP; + gpio_config.speed = GPIO_SPEED_50MHz; + gpio_config.pin = (GPIO_PIN_3 | GPIO_PIN_5); + GPIO_Config(GPIOB, &gpio_config); + /* SPI3_MISO(PB4) */ + gpio_config.mode = GPIO_MODE_IN_FLOATING; + gpio_config.speed = GPIO_SPEED_50MHz; + gpio_config.pin = GPIO_PIN_4; + GPIO_Config(GPIOB, &gpio_config); +#endif + return result; +} +INIT_BOARD_EXPORT(rt_hw_spi_init); + +#endif /* RT_USING_SPI */ diff --git a/bsp/apm32/libraries/Drivers/drv_spi.h b/bsp/apm32/libraries/Drivers/drv_spi.h new file mode 100644 index 0000000000..e4591352f5 --- /dev/null +++ b/bsp/apm32/libraries/Drivers/drv_spi.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-03-04 stevetong459 first version + */ + +#ifndef __DRV_SPI_H__ +#define __DRV_SPI_H__ + +#include "board.h" + +struct apm32_spi_cs +{ + GPIO_T *GPIOx; + uint16_t GPIO_Pin; +}; + +#endif /*__DRV_SPI_H__ */ diff --git a/bsp/apm32/libraries/Drivers/drv_usart.c b/bsp/apm32/libraries/Drivers/drv_usart.c index c3141be55c..174bd8ebba 100644 --- a/bsp/apm32/libraries/Drivers/drv_usart.c +++ b/bsp/apm32/libraries/Drivers/drv_usart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -18,7 +18,6 @@ /* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */ #endif -/* stm32 config class */ struct apm32_usart { const char *name; @@ -204,7 +203,7 @@ static void usart_isr(struct rt_serial_device *serial) RT_ASSERT(usart != RT_NULL); - /* UART in mode Receiver -------------------------------------------------*/ + /* UART in mode Receiver */ if ((USART_ReadStatusFlag(usart->usartx, USART_FLAG_RXBNE) != RESET) && (USART_ReadIntFlag(usart->usartx, USART_INT_RXBNE) != RESET)) { diff --git a/bsp/apm32/libraries/Drivers/drv_usart.h b/bsp/apm32/libraries/Drivers/drv_usart.h index a9040cc14c..727772671a 100644 --- a/bsp/apm32/libraries/Drivers/drv_usart.h +++ b/bsp/apm32/libraries/Drivers/drv_usart.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/apm32/libraries/Drivers/drv_wdt.c b/bsp/apm32/libraries/Drivers/drv_wdt.c new file mode 100644 index 0000000000..829ba48ca5 --- /dev/null +++ b/bsp/apm32/libraries/Drivers/drv_wdt.c @@ -0,0 +1,150 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-03-04 stevetong459 first version + */ + +#include +#include + +#ifdef RT_USING_WDT + +#define DBG_TAG "drv.wdt" +#define DBG_LVL DBG_INFO +#include + +#ifndef LSI_VALUE + #define LSI_VALUE ((uint32_t)40000) +#endif + +#define DRV_WDT_TIME_OUT 0xFFFF + +typedef struct +{ + struct rt_watchdog_device wdt; + rt_uint32_t min_threshold; + rt_uint32_t max_threshold; + rt_uint32_t current_threshold; +} apm32_wdt_t; + +static apm32_wdt_t wdt_config; + +static rt_err_t _iwdt_init(rt_watchdog_t *wdt) +{ + rt_uint32_t counter = 0; + + RCM_EnableLSI(); + + while (!RCM_ReadStatusFlag(RCM_FLAG_LSIRDY)) + { + if (++counter > DRV_WDT_TIME_OUT) + { + LOG_E("LSI clock open failed."); + return -RT_ERROR; + } + } + + wdt_config.min_threshold = 1; + wdt_config.max_threshold = (0xfff << 8) / LSI_VALUE; + LOG_I("threshold section [%u, %d]", \ + wdt_config.min_threshold, + wdt_config.max_threshold); + + while (IWDT_ReadStatusFlag(IWDT_FLAG_PSCU)) + { + if (++counter > DRV_WDT_TIME_OUT) + { + LOG_E("watchdog prescaler init failed."); + return -RT_ERROR; + } + } + IWDT_EnableWriteAccess(); + IWDT_ConfigDivider(IWDT_DIVIDER_256); + IWDT_DisableWriteAccess(); + + return RT_EOK; +} + +/** + * @brief This function will control watchdog device. + * + * @param wdt is a pointer to i2c config class. + * + * @return RT_EOK indicates successful , other value indicates failed. + */ +static rt_err_t _iwdt_control(rt_watchdog_t *wdt, int cmd, void *arg) +{ + volatile rt_uint32_t param, counter = 0; + + switch (cmd) + { + case RT_DEVICE_CTRL_WDT_KEEPALIVE: + IWDT_Refresh(); + break; + case RT_DEVICE_CTRL_WDT_SET_TIMEOUT: + param = *(rt_uint32_t *) arg; + if ((param > wdt_config.max_threshold) || \ + (param < wdt_config.min_threshold)) + { + LOG_E("invalid param@%u.", param); + return -RT_ERROR; + } + else + { + wdt_config.current_threshold = param; + } + while (IWDT_ReadStatusFlag(IWDT_FLAG_CNTU)) + { + if (++counter > DRV_WDT_TIME_OUT) + { + LOG_E("Update watchdog reload value complete."); + return -RT_ERROR; + } + } + IWDT_Refresh(); + IWDT_EnableWriteAccess(); + IWDT_ConfigReload(param * LSI_VALUE >> 8); + IWDT_DisableWriteAccess(); + break; + case RT_DEVICE_CTRL_WDT_GET_TIMEOUT: + *(rt_uint32_t *)arg = wdt_config.current_threshold; + break; + case RT_DEVICE_CTRL_WDT_START: + IWDT_Enable(); + IWDT_Refresh(); + break; + default: + LOG_W("This command is not supported."); + return -RT_ERROR; + } + + return RT_EOK; +} + +static struct rt_watchdog_ops _wdt_ops = +{ + _iwdt_init, + _iwdt_control, +}; + +static int rt_hw_wdt_init(void) +{ + wdt_config.wdt.ops = &_wdt_ops; + /* register watchdog device */ + if (rt_hw_watchdog_register(&wdt_config.wdt, "wdt", \ + RT_DEVICE_FLAG_DEACTIVATE, RT_NULL) != RT_EOK) + { + LOG_E("wdt device register failed."); + return -RT_ERROR; + } + LOG_D("wdt device register success."); + + return RT_EOK; +} +INIT_BOARD_EXPORT(rt_hw_wdt_init); + +#endif