Mirrors_Framework/rt-thread
1
0
Fork 0
mirror of https://github.com/RT-Thread/rt-thread.git synced 2026-08-25 04:08:31 +08:00
Code Issues Actions 1 Packages Projects Releases Wiki Activity

bsp: nxp/mcxn947: Updated SDK to release v2.16.000

Browse Source 
Signed-off-by: Yilin Sun <imi415@imi.moe>
This commit is contained in:
Yilin Sun
2024-08-16 20:20:13 -04:00
committed by Meco Man
parent 0864456947
commit e6cf0bc97d
191 changed files with 52522 additions and 41105 deletions
Download Patch File Download Diff File Expand all files Collapse all files
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/MCXN947_cm33_core0.h
+9661 -15308
View File
File diff suppressed because it is too large Load Diff
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/MCXN947_cm33_core0_features.h
+296 -119
View File
File diff suppressed because it is too large Load Diff
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/MCXN947_cm33_core1.h
+9661 -15308
View File
File diff suppressed because it is too large Load Diff
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/MCXN947_cm33_core1_features.h
+296 -119
View File
File diff suppressed because it is too large Load Diff
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/arm/startup_MCXN947_cm33_core0.S
+74 -76
View File
@@ -2,15 +2,13 @@
/* @file: startup_MCXN947_cm33_core0.s */
/* @purpose: CMSIS Cortex-M33 Core Device Startup File */
/* MCXN947_cm33_core0 */
/* @version: 1.0 */
/* @date: 2022-10-1 */
/* @build: b230131 */
/* @version: 2.0 */
/* @date: 2023-2-1 */
/* @build: b240410 */
/* ------------------------------------------------------------------------- */
/* */
/* Copyright 1997-2016 Freescale Semiconductor, Inc. */
/* Copyright 2016-2023 NXP */
/* All rights reserved. */
/* */
/* Copyright 2016-2024 NXP */
/* SPDX-License-Identifier: BSD-3-Clause */
/*****************************************************************************/
/* Version: GCC for ARM Embedded Processors */
@@ -165,14 +163,14 @@ __Vectors:
.long FLEXPWM1_SUBMODULE1_IRQHandler /* FlexPWM1 Submodule 1 capture/compare/reload interrupt*/
.long FLEXPWM1_SUBMODULE2_IRQHandler /* FlexPWM1 Submodule 2 capture/compare/reload interrupt*/
.long FLEXPWM1_SUBMODULE3_IRQHandler /* FlexPWM1 Submodule 3 capture/compare/reload interrupt*/
.long ENC0_COMPARE_IRQHandler /* ENC0_Compare interrupt*/
.long ENC0_HOME_IRQHandler /* ENC0_Home interrupt*/
.long ENC0_WDG_SAB_IRQHandler /* ENC0_WDG_IRQ/SAB interrupt*/
.long ENC0_IDX_IRQHandler /* ENC0_IDX interrupt*/
.long ENC1_COMPARE_IRQHandler /* ENC1_Compare interrupt*/
.long ENC1_HOME_IRQHandler /* ENC1_Home interrupt*/
.long ENC1_WDG_SAB_IRQHandler /* ENC1_WDG_IRQ/SAB interrupt*/
.long ENC1_IDX_IRQHandler /* ENC1_IDX interrupt*/
.long QDC0_COMPARE_IRQHandler /* QDC0_Compare interrupt*/
.long QDC0_HOME_IRQHandler /* QDC0_Home interrupt*/
.long QDC0_WDG_SAB_IRQHandler /* QDC0_WDG_IRQ/SAB interrupt*/
.long QDC0_IDX_IRQHandler /* QDC0_IDX interrupt*/
.long QDC1_COMPARE_IRQHandler /* QDC1_Compare interrupt*/
.long QDC1_HOME_IRQHandler /* QDC1_Home interrupt*/
.long QDC1_WDG_SAB_IRQHandler /* QDC1_WDG_IRQ/SAB interrupt*/
.long QDC1_IDX_IRQHandler /* QDC1_IDX interrupt*/
.long ITRC0_IRQHandler /* Intrusion and Tamper Response Controller interrupt*/
.long BSP32_IRQHandler /* CoolFlux BSP32 interrupt*/
.long ELS_ERR_IRQHandler /* ELS error interrupt*/
@@ -191,8 +189,8 @@ __Vectors:
.long WUU_IRQHandler /* Wake Up Unit interrupt*/
.long PORT_EFT_IRQHandler /* PORT0~5 EFT interrupt*/
.long ETB0_IRQHandler /* ETB counter expires interrupt*/
.long SM3_IRQHandler /* Secure Generic Interface (SGI) SAFO interrupt */
.long TRNG0_IRQHandler /* True Random Number Generator interrupt*/
.long Reserved166_IRQHandler /* Reserved interrupt*/
.long Reserved167_IRQHandler /* Reserved interrupt*/
.long WWDT0_IRQHandler /* Windowed Watchdog Timer 0 interrupt*/
.long WWDT1_IRQHandler /* Windowed Watchdog Timer 1 interrupt*/
.long CMC0_IRQHandler /* Core Mode Controller interrupt*/
@@ -1399,75 +1397,75 @@ FLEXPWM1_SUBMODULE3_IRQHandler:
.align 1
.thumb_func
.weak ENC0_COMPARE_IRQHandler
.type ENC0_COMPARE_IRQHandler, %function
ENC0_COMPARE_IRQHandler:
ldr r0,=ENC0_COMPARE_DriverIRQHandler
.weak QDC0_COMPARE_IRQHandler
.type QDC0_COMPARE_IRQHandler, %function
QDC0_COMPARE_IRQHandler:
ldr r0,=QDC0_COMPARE_DriverIRQHandler
bx r0
.size ENC0_COMPARE_IRQHandler, . - ENC0_COMPARE_IRQHandler
.size QDC0_COMPARE_IRQHandler, . - QDC0_COMPARE_IRQHandler
.align 1
.thumb_func
.weak ENC0_HOME_IRQHandler
.type ENC0_HOME_IRQHandler, %function
ENC0_HOME_IRQHandler:
ldr r0,=ENC0_HOME_DriverIRQHandler
.weak QDC0_HOME_IRQHandler
.type QDC0_HOME_IRQHandler, %function
QDC0_HOME_IRQHandler:
ldr r0,=QDC0_HOME_DriverIRQHandler
bx r0
.size ENC0_HOME_IRQHandler, . - ENC0_HOME_IRQHandler
.size QDC0_HOME_IRQHandler, . - QDC0_HOME_IRQHandler
.align 1
.thumb_func
.weak ENC0_WDG_SAB_IRQHandler
.type ENC0_WDG_SAB_IRQHandler, %function
ENC0_WDG_SAB_IRQHandler:
ldr r0,=ENC0_WDG_SAB_DriverIRQHandler
.weak QDC0_WDG_SAB_IRQHandler
.type QDC0_WDG_SAB_IRQHandler, %function
QDC0_WDG_SAB_IRQHandler:
ldr r0,=QDC0_WDG_SAB_DriverIRQHandler
bx r0
.size ENC0_WDG_SAB_IRQHandler, . - ENC0_WDG_SAB_IRQHandler
.size QDC0_WDG_SAB_IRQHandler, . - QDC0_WDG_SAB_IRQHandler
.align 1
.thumb_func
.weak ENC0_IDX_IRQHandler
.type ENC0_IDX_IRQHandler, %function
ENC0_IDX_IRQHandler:
ldr r0,=ENC0_IDX_DriverIRQHandler
.weak QDC0_IDX_IRQHandler
.type QDC0_IDX_IRQHandler, %function
QDC0_IDX_IRQHandler:
ldr r0,=QDC0_IDX_DriverIRQHandler
bx r0
.size ENC0_IDX_IRQHandler, . - ENC0_IDX_IRQHandler
.size QDC0_IDX_IRQHandler, . - QDC0_IDX_IRQHandler
.align 1
.thumb_func
.weak ENC1_COMPARE_IRQHandler
.type ENC1_COMPARE_IRQHandler, %function
ENC1_COMPARE_IRQHandler:
ldr r0,=ENC1_COMPARE_DriverIRQHandler
.weak QDC1_COMPARE_IRQHandler
.type QDC1_COMPARE_IRQHandler, %function
QDC1_COMPARE_IRQHandler:
ldr r0,=QDC1_COMPARE_DriverIRQHandler
bx r0
.size ENC1_COMPARE_IRQHandler, . - ENC1_COMPARE_IRQHandler
.size QDC1_COMPARE_IRQHandler, . - QDC1_COMPARE_IRQHandler
.align 1
.thumb_func
.weak ENC1_HOME_IRQHandler
.type ENC1_HOME_IRQHandler, %function
ENC1_HOME_IRQHandler:
ldr r0,=ENC1_HOME_DriverIRQHandler
.weak QDC1_HOME_IRQHandler
.type QDC1_HOME_IRQHandler, %function
QDC1_HOME_IRQHandler:
ldr r0,=QDC1_HOME_DriverIRQHandler
bx r0
.size ENC1_HOME_IRQHandler, . - ENC1_HOME_IRQHandler
.size QDC1_HOME_IRQHandler, . - QDC1_HOME_IRQHandler
.align 1
.thumb_func
.weak ENC1_WDG_SAB_IRQHandler
.type ENC1_WDG_SAB_IRQHandler, %function
ENC1_WDG_SAB_IRQHandler:
ldr r0,=ENC1_WDG_SAB_DriverIRQHandler
.weak QDC1_WDG_SAB_IRQHandler
.type QDC1_WDG_SAB_IRQHandler, %function
QDC1_WDG_SAB_IRQHandler:
ldr r0,=QDC1_WDG_SAB_DriverIRQHandler
bx r0
.size ENC1_WDG_SAB_IRQHandler, . - ENC1_WDG_SAB_IRQHandler
.size QDC1_WDG_SAB_IRQHandler, . - QDC1_WDG_SAB_IRQHandler
.align 1
.thumb_func
.weak ENC1_IDX_IRQHandler
.type ENC1_IDX_IRQHandler, %function
ENC1_IDX_IRQHandler:
ldr r0,=ENC1_IDX_DriverIRQHandler
.weak QDC1_IDX_IRQHandler
.type QDC1_IDX_IRQHandler, %function
QDC1_IDX_IRQHandler:
ldr r0,=QDC1_IDX_DriverIRQHandler
bx r0
.size ENC1_IDX_IRQHandler, . - ENC1_IDX_IRQHandler
.size QDC1_IDX_IRQHandler, . - QDC1_IDX_IRQHandler
.align 1
.thumb_func
@@ -1633,21 +1631,21 @@ ETB0_IRQHandler:
.align 1
.thumb_func
.weak SM3_IRQHandler
.type SM3_IRQHandler, %function
SM3_IRQHandler:
ldr r0,=SM3_DriverIRQHandler
.weak Reserved166_IRQHandler
.type Reserved166_IRQHandler, %function
Reserved166_IRQHandler:
ldr r0,=Reserved166_DriverIRQHandler
bx r0
.size SM3_IRQHandler, . - SM3_IRQHandler
.size Reserved166_IRQHandler, . - Reserved166_IRQHandler
.align 1
.thumb_func
.weak TRNG0_IRQHandler
.type TRNG0_IRQHandler, %function
TRNG0_IRQHandler:
ldr r0,=TRNG0_DriverIRQHandler
.weak Reserved167_IRQHandler
.type Reserved167_IRQHandler, %function
Reserved167_IRQHandler:
ldr r0,=Reserved167_DriverIRQHandler
bx r0
.size TRNG0_IRQHandler, . - TRNG0_IRQHandler
.size Reserved167_IRQHandler, . - Reserved167_IRQHandler
.align 1
.thumb_func
@@ -1824,14 +1822,14 @@ CTI0_IRQHandler:
def_irq_handler FLEXPWM1_SUBMODULE1_DriverIRQHandler
def_irq_handler FLEXPWM1_SUBMODULE2_DriverIRQHandler
def_irq_handler FLEXPWM1_SUBMODULE3_DriverIRQHandler
def_irq_handler ENC0_COMPARE_DriverIRQHandler
def_irq_handler ENC0_HOME_DriverIRQHandler
def_irq_handler ENC0_WDG_SAB_DriverIRQHandler
def_irq_handler ENC0_IDX_DriverIRQHandler
def_irq_handler ENC1_COMPARE_DriverIRQHandler
def_irq_handler ENC1_HOME_DriverIRQHandler
def_irq_handler ENC1_WDG_SAB_DriverIRQHandler
def_irq_handler ENC1_IDX_DriverIRQHandler
def_irq_handler QDC0_COMPARE_DriverIRQHandler
def_irq_handler QDC0_HOME_DriverIRQHandler
def_irq_handler QDC0_WDG_SAB_DriverIRQHandler
def_irq_handler QDC0_IDX_DriverIRQHandler
def_irq_handler QDC1_COMPARE_DriverIRQHandler
def_irq_handler QDC1_HOME_DriverIRQHandler
def_irq_handler QDC1_WDG_SAB_DriverIRQHandler
def_irq_handler QDC1_IDX_DriverIRQHandler
def_irq_handler ITRC0_DriverIRQHandler
def_irq_handler BSP32_DriverIRQHandler
def_irq_handler ELS_ERR_DriverIRQHandler
@@ -1850,8 +1848,8 @@ CTI0_IRQHandler:
def_irq_handler WUU_DriverIRQHandler
def_irq_handler PORT_EFT_DriverIRQHandler
def_irq_handler ETB0_DriverIRQHandler
def_irq_handler SM3_DriverIRQHandler
def_irq_handler TRNG0_DriverIRQHandler
def_irq_handler Reserved166_DriverIRQHandler
def_irq_handler Reserved167_DriverIRQHandler
def_irq_handler WWDT0_DriverIRQHandler
def_irq_handler WWDT1_DriverIRQHandler
def_irq_handler CMC0_DriverIRQHandler
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/arm/startup_MCXN947_cm33_core1.S
+74 -76
View File
@@ -2,15 +2,13 @@
/* @file: startup_MCXN947_cm33_core1.s */
/* @purpose: CMSIS Cortex-M33 Core Device Startup File */
/* MCXN947_cm33_core1 */
/* @version: 1.0 */
/* @date: 2022-10-1 */
/* @build: b230131 */
/* @version: 2.0 */
/* @date: 2023-2-1 */
/* @build: b240410 */
/* ------------------------------------------------------------------------- */
/* */
/* Copyright 1997-2016 Freescale Semiconductor, Inc. */
/* Copyright 2016-2023 NXP */
/* All rights reserved. */
/* */
/* Copyright 2016-2024 NXP */
/* SPDX-License-Identifier: BSD-3-Clause */
/*****************************************************************************/
/* Version: GCC for ARM Embedded Processors */
@@ -165,14 +163,14 @@ __Vectors:
.long FLEXPWM1_SUBMODULE1_IRQHandler /* FlexPWM1 Submodule 1 capture/compare/reload interrupt*/
.long FLEXPWM1_SUBMODULE2_IRQHandler /* FlexPWM1 Submodule 2 capture/compare/reload interrupt*/
.long FLEXPWM1_SUBMODULE3_IRQHandler /* FlexPWM1 Submodule 3 capture/compare/reload interrupt*/
.long ENC0_COMPARE_IRQHandler /* ENC0_Compare interrupt*/
.long ENC0_HOME_IRQHandler /* ENC0_Home interrupt*/
.long ENC0_WDG_SAB_IRQHandler /* ENC0_WDG_IRQ/SAB interrupt*/
.long ENC0_IDX_IRQHandler /* ENC0_IDX interrupt*/
.long ENC1_COMPARE_IRQHandler /* ENC1_Compare interrupt*/
.long ENC1_HOME_IRQHandler /* ENC1_Home interrupt*/
.long ENC1_WDG_SAB_IRQHandler /* ENC1_WDG_IRQ/SAB interrupt*/
.long ENC1_IDX_IRQHandler /* ENC1_IDX interrupt*/
.long QDC0_COMPARE_IRQHandler /* QDC0_Compare interrupt*/
.long QDC0_HOME_IRQHandler /* QDC0_Home interrupt*/
.long QDC0_WDG_SAB_IRQHandler /* QDC0_WDG_IRQ/SAB interrupt*/
.long QDC0_IDX_IRQHandler /* QDC0_IDX interrupt*/
.long QDC1_COMPARE_IRQHandler /* QDC1_Compare interrupt*/
.long QDC1_HOME_IRQHandler /* QDC1_Home interrupt*/
.long QDC1_WDG_SAB_IRQHandler /* QDC1_WDG_IRQ/SAB interrupt*/
.long QDC1_IDX_IRQHandler /* QDC1_IDX interrupt*/
.long ITRC0_IRQHandler /* Intrusion and Tamper Response Controller interrupt*/
.long BSP32_IRQHandler /* CoolFlux BSP32 interrupt*/
.long ELS_ERR_IRQHandler /* ELS error interrupt*/
@@ -191,8 +189,8 @@ __Vectors:
.long WUU_IRQHandler /* Wake Up Unit interrupt*/
.long PORT_EFT_IRQHandler /* PORT0~5 EFT interrupt*/
.long ETB0_IRQHandler /* ETB counter expires interrupt*/
.long SM3_IRQHandler /* Secure Generic Interface (SGI) SAFO interrupt */
.long TRNG0_IRQHandler /* True Random Number Generator interrupt*/
.long Reserved166_IRQHandler /* Reserved interrupt*/
.long Reserved167_IRQHandler /* Reserved interrupt*/
.long WWDT0_IRQHandler /* Windowed Watchdog Timer 0 interrupt*/
.long WWDT1_IRQHandler /* Windowed Watchdog Timer 1 interrupt*/
.long CMC0_IRQHandler /* Core Mode Controller interrupt*/
@@ -1391,75 +1389,75 @@ FLEXPWM1_SUBMODULE3_IRQHandler:
.align 1
.thumb_func
.weak ENC0_COMPARE_IRQHandler
.type ENC0_COMPARE_IRQHandler, %function
ENC0_COMPARE_IRQHandler:
ldr r0,=ENC0_COMPARE_DriverIRQHandler
.weak QDC0_COMPARE_IRQHandler
.type QDC0_COMPARE_IRQHandler, %function
QDC0_COMPARE_IRQHandler:
ldr r0,=QDC0_COMPARE_DriverIRQHandler
bx r0
.size ENC0_COMPARE_IRQHandler, . - ENC0_COMPARE_IRQHandler
.size QDC0_COMPARE_IRQHandler, . - QDC0_COMPARE_IRQHandler
.align 1
.thumb_func
.weak ENC0_HOME_IRQHandler
.type ENC0_HOME_IRQHandler, %function
ENC0_HOME_IRQHandler:
ldr r0,=ENC0_HOME_DriverIRQHandler
.weak QDC0_HOME_IRQHandler
.type QDC0_HOME_IRQHandler, %function
QDC0_HOME_IRQHandler:
ldr r0,=QDC0_HOME_DriverIRQHandler
bx r0
.size ENC0_HOME_IRQHandler, . - ENC0_HOME_IRQHandler
.size QDC0_HOME_IRQHandler, . - QDC0_HOME_IRQHandler
.align 1
.thumb_func
.weak ENC0_WDG_SAB_IRQHandler
.type ENC0_WDG_SAB_IRQHandler, %function
ENC0_WDG_SAB_IRQHandler:
ldr r0,=ENC0_WDG_SAB_DriverIRQHandler
.weak QDC0_WDG_SAB_IRQHandler
.type QDC0_WDG_SAB_IRQHandler, %function
QDC0_WDG_SAB_IRQHandler:
ldr r0,=QDC0_WDG_SAB_DriverIRQHandler
bx r0
.size ENC0_WDG_SAB_IRQHandler, . - ENC0_WDG_SAB_IRQHandler
.size QDC0_WDG_SAB_IRQHandler, . - QDC0_WDG_SAB_IRQHandler
.align 1
.thumb_func
.weak ENC0_IDX_IRQHandler
.type ENC0_IDX_IRQHandler, %function
ENC0_IDX_IRQHandler:
ldr r0,=ENC0_IDX_DriverIRQHandler
.weak QDC0_IDX_IRQHandler
.type QDC0_IDX_IRQHandler, %function
QDC0_IDX_IRQHandler:
ldr r0,=QDC0_IDX_DriverIRQHandler
bx r0
.size ENC0_IDX_IRQHandler, . - ENC0_IDX_IRQHandler
.size QDC0_IDX_IRQHandler, . - QDC0_IDX_IRQHandler
.align 1
.thumb_func
.weak ENC1_COMPARE_IRQHandler
.type ENC1_COMPARE_IRQHandler, %function
ENC1_COMPARE_IRQHandler:
ldr r0,=ENC1_COMPARE_DriverIRQHandler
.weak QDC1_COMPARE_IRQHandler
.type QDC1_COMPARE_IRQHandler, %function
QDC1_COMPARE_IRQHandler:
ldr r0,=QDC1_COMPARE_DriverIRQHandler
bx r0
.size ENC1_COMPARE_IRQHandler, . - ENC1_COMPARE_IRQHandler
.size QDC1_COMPARE_IRQHandler, . - QDC1_COMPARE_IRQHandler
.align 1
.thumb_func
.weak ENC1_HOME_IRQHandler
.type ENC1_HOME_IRQHandler, %function
ENC1_HOME_IRQHandler:
ldr r0,=ENC1_HOME_DriverIRQHandler
.weak QDC1_HOME_IRQHandler
.type QDC1_HOME_IRQHandler, %function
QDC1_HOME_IRQHandler:
ldr r0,=QDC1_HOME_DriverIRQHandler
bx r0
.size ENC1_HOME_IRQHandler, . - ENC1_HOME_IRQHandler
.size QDC1_HOME_IRQHandler, . - QDC1_HOME_IRQHandler
.align 1
.thumb_func
.weak ENC1_WDG_SAB_IRQHandler
.type ENC1_WDG_SAB_IRQHandler, %function
ENC1_WDG_SAB_IRQHandler:
ldr r0,=ENC1_WDG_SAB_DriverIRQHandler
.weak QDC1_WDG_SAB_IRQHandler
.type QDC1_WDG_SAB_IRQHandler, %function
QDC1_WDG_SAB_IRQHandler:
ldr r0,=QDC1_WDG_SAB_DriverIRQHandler
bx r0
.size ENC1_WDG_SAB_IRQHandler, . - ENC1_WDG_SAB_IRQHandler
.size QDC1_WDG_SAB_IRQHandler, . - QDC1_WDG_SAB_IRQHandler
.align 1
.thumb_func
.weak ENC1_IDX_IRQHandler
.type ENC1_IDX_IRQHandler, %function
ENC1_IDX_IRQHandler:
ldr r0,=ENC1_IDX_DriverIRQHandler
.weak QDC1_IDX_IRQHandler
.type QDC1_IDX_IRQHandler, %function
QDC1_IDX_IRQHandler:
ldr r0,=QDC1_IDX_DriverIRQHandler
bx r0
.size ENC1_IDX_IRQHandler, . - ENC1_IDX_IRQHandler
.size QDC1_IDX_IRQHandler, . - QDC1_IDX_IRQHandler
.align 1
.thumb_func
@@ -1625,21 +1623,21 @@ ETB0_IRQHandler:
.align 1
.thumb_func
.weak SM3_IRQHandler
.type SM3_IRQHandler, %function
SM3_IRQHandler:
ldr r0,=SM3_DriverIRQHandler
.weak Reserved166_IRQHandler
.type Reserved166_IRQHandler, %function
Reserved166_IRQHandler:
ldr r0,=Reserved166_DriverIRQHandler
bx r0
.size SM3_IRQHandler, . - SM3_IRQHandler
.size Reserved166_IRQHandler, . - Reserved166_IRQHandler
.align 1
.thumb_func
.weak TRNG0_IRQHandler
.type TRNG0_IRQHandler, %function
TRNG0_IRQHandler:
ldr r0,=TRNG0_DriverIRQHandler
.weak Reserved167_IRQHandler
.type Reserved167_IRQHandler, %function
Reserved167_IRQHandler:
ldr r0,=Reserved167_DriverIRQHandler
bx r0
.size TRNG0_IRQHandler, . - TRNG0_IRQHandler
.size Reserved167_IRQHandler, . - Reserved167_IRQHandler
.align 1
.thumb_func
@@ -1816,14 +1814,14 @@ CTI0_IRQHandler:
def_irq_handler FLEXPWM1_SUBMODULE1_DriverIRQHandler
def_irq_handler FLEXPWM1_SUBMODULE2_DriverIRQHandler
def_irq_handler FLEXPWM1_SUBMODULE3_DriverIRQHandler
def_irq_handler ENC0_COMPARE_DriverIRQHandler
def_irq_handler ENC0_HOME_DriverIRQHandler
def_irq_handler ENC0_WDG_SAB_DriverIRQHandler
def_irq_handler ENC0_IDX_DriverIRQHandler
def_irq_handler ENC1_COMPARE_DriverIRQHandler
def_irq_handler ENC1_HOME_DriverIRQHandler
def_irq_handler ENC1_WDG_SAB_DriverIRQHandler
def_irq_handler ENC1_IDX_DriverIRQHandler
def_irq_handler QDC0_COMPARE_DriverIRQHandler
def_irq_handler QDC0_HOME_DriverIRQHandler
def_irq_handler QDC0_WDG_SAB_DriverIRQHandler
def_irq_handler QDC0_IDX_DriverIRQHandler
def_irq_handler QDC1_COMPARE_DriverIRQHandler
def_irq_handler QDC1_HOME_DriverIRQHandler
def_irq_handler QDC1_WDG_SAB_DriverIRQHandler
def_irq_handler QDC1_IDX_DriverIRQHandler
def_irq_handler ITRC0_DriverIRQHandler
def_irq_handler BSP32_DriverIRQHandler
def_irq_handler ELS_ERR_DriverIRQHandler
@@ -1842,8 +1840,8 @@ CTI0_IRQHandler:
def_irq_handler WUU_DriverIRQHandler
def_irq_handler PORT_EFT_DriverIRQHandler
def_irq_handler ETB0_DriverIRQHandler
def_irq_handler SM3_DriverIRQHandler
def_irq_handler TRNG0_DriverIRQHandler
def_irq_handler Reserved166_DriverIRQHandler
def_irq_handler Reserved167_DriverIRQHandler
def_irq_handler WWDT0_DriverIRQHandler
def_irq_handler WWDT1_DriverIRQHandler
def_irq_handler CMC0_DriverIRQHandler
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cache.c
+91 -82
View File
@@ -1,5 +1,5 @@
/*
* Copyright 2016-2021 NXP
* Copyright 2016-2021, 2023 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -205,7 +205,7 @@ void CACHE64_InvalidateCache(CACHE64_CTRL_Type *base)
* brief Invalidates cache by range.
*
* param address The physical address of cache.
* param size_byte size of the memory to be invalidated.
* param size_byte size of the memory to be invalidated, should be larger than 0.
* note Address and size should be aligned to "L1CODCACHE_LINESIZE_BYTE".
* The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if
* startAddr is not aligned. For the size_byte, application should make sure the
@@ -213,36 +213,39 @@ void CACHE64_InvalidateCache(CACHE64_CTRL_Type *base)
*/
void CACHE64_InvalidateCacheByRange(uint32_t address, uint32_t size_byte)
{
uint32_t endAddr = address + size_byte - 0x01U;
uint32_t pccReg = 0;
/* Align address to cache line size. */
uint32_t startAddr = address & ~((uint32_t)CACHE64_LINESIZE_BYTE - 1U);
uint32_t instance = CACHE64_GetInstanceByAddr(address);
uint32_t endLim;
CACHE64_CTRL_Type *base;
if (instance >= ARRAY_SIZE(s_cache64ctrlBases))
if (size_byte > 0UL)
{
return;
}
base = s_cache64ctrlBases[instance];
endLim = s_cache64PhymemBases[instance] + s_cache64PhymemSizes[instance] - 0x01U;
endAddr = endAddr > endLim ? endLim : endAddr;
uint32_t endAddr = address + size_byte - 0x01U;
uint32_t pccReg = 0;
/* Align address to cache line size. */
uint32_t startAddr = address & ~((uint32_t)CACHE64_LINESIZE_BYTE - 1U);
uint32_t instance = CACHE64_GetInstanceByAddr(address);
uint32_t endLim;
CACHE64_CTRL_Type *base;
/* Set the invalidate by line command and use the physical address. */
pccReg = (base->CLCR & ~CACHE64_CTRL_CLCR_LCMD_MASK) | CACHE64_CTRL_CLCR_LCMD(1) | CACHE64_CTRL_CLCR_LADSEL_MASK;
base->CLCR = pccReg;
while (startAddr < endAddr)
{
/* Set the address and initiate the command. */
base->CSAR = (startAddr & CACHE64_CTRL_CSAR_PHYADDR_MASK) | CACHE64_CTRL_CSAR_LGO_MASK;
/* Wait until the cache command completes. */
while ((base->CSAR & CACHE64_CTRL_CSAR_LGO_MASK) != 0x00U)
if (instance >= ARRAY_SIZE(s_cache64ctrlBases))
{
return;
}
base = s_cache64ctrlBases[instance];
endLim = s_cache64PhymemBases[instance] + s_cache64PhymemSizes[instance] - 0x01U;
endAddr = endAddr > endLim ? endLim : endAddr;
/* Set the invalidate by line command and use the physical address. */
pccReg = (base->CLCR & ~CACHE64_CTRL_CLCR_LCMD_MASK) | CACHE64_CTRL_CLCR_LCMD(1) | CACHE64_CTRL_CLCR_LADSEL_MASK;
base->CLCR = pccReg;
while (startAddr < endAddr)
{
/* Set the address and initiate the command. */
base->CSAR = (startAddr & CACHE64_CTRL_CSAR_PHYADDR_MASK) | CACHE64_CTRL_CSAR_LGO_MASK;
/* Wait until the cache command completes. */
while ((base->CSAR & CACHE64_CTRL_CSAR_LGO_MASK) != 0x00U)
{
}
startAddr += (uint32_t)CACHE64_LINESIZE_BYTE;
}
startAddr += (uint32_t)CACHE64_LINESIZE_BYTE;
}
}
@@ -268,7 +271,7 @@ void CACHE64_CleanCache(CACHE64_CTRL_Type *base)
* brief Cleans cache by range.
*
* param address The physical address of cache.
* param size_byte size of the memory to be cleaned.
* param size_byte size of the memory to be cleaned, should be larger than 0.
* note Address and size should be aligned to "CACHE64_LINESIZE_BYTE".
* The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if
* startAddr is not aligned. For the size_byte, application should make sure the
@@ -276,36 +279,39 @@ void CACHE64_CleanCache(CACHE64_CTRL_Type *base)
*/
void CACHE64_CleanCacheByRange(uint32_t address, uint32_t size_byte)
{
uint32_t endAddr = address + size_byte - 0x01U;
uint32_t pccReg = 0;
/* Align address to cache line size. */
uint32_t startAddr = address & ~((uint32_t)CACHE64_LINESIZE_BYTE - 1U);
uint32_t instance = CACHE64_GetInstanceByAddr(address);
uint32_t endLim;
CACHE64_CTRL_Type *base;
if (instance >= ARRAY_SIZE(s_cache64ctrlBases))
if (size_byte > 0UL)
{
return;
}
base = s_cache64ctrlBases[instance];
endLim = s_cache64PhymemBases[instance] + s_cache64PhymemSizes[instance] - 0x01U;
endAddr = endAddr > endLim ? endLim : endAddr;
uint32_t endAddr = address + size_byte - 0x01U;
uint32_t pccReg = 0;
/* Align address to cache line size. */
uint32_t startAddr = address & ~((uint32_t)CACHE64_LINESIZE_BYTE - 1U);
uint32_t instance = CACHE64_GetInstanceByAddr(address);
uint32_t endLim;
CACHE64_CTRL_Type *base;
/* Set the push by line command. */
pccReg = (base->CLCR & ~CACHE64_CTRL_CLCR_LCMD_MASK) | CACHE64_CTRL_CLCR_LCMD(2) | CACHE64_CTRL_CLCR_LADSEL_MASK;
base->CLCR = pccReg;
while (startAddr < endAddr)
{
/* Set the address and initiate the command. */
base->CSAR = (startAddr & CACHE64_CTRL_CSAR_PHYADDR_MASK) | CACHE64_CTRL_CSAR_LGO_MASK;
/* Wait until the cache command completes. */
while ((base->CSAR & CACHE64_CTRL_CSAR_LGO_MASK) != 0x00U)
if (instance >= ARRAY_SIZE(s_cache64ctrlBases))
{
return;
}
base = s_cache64ctrlBases[instance];
endLim = s_cache64PhymemBases[instance] + s_cache64PhymemSizes[instance] - 0x01U;
endAddr = endAddr > endLim ? endLim : endAddr;
/* Set the push by line command. */
pccReg = (base->CLCR & ~CACHE64_CTRL_CLCR_LCMD_MASK) | CACHE64_CTRL_CLCR_LCMD(2) | CACHE64_CTRL_CLCR_LADSEL_MASK;
base->CLCR = pccReg;
while (startAddr < endAddr)
{
/* Set the address and initiate the command. */
base->CSAR = (startAddr & CACHE64_CTRL_CSAR_PHYADDR_MASK) | CACHE64_CTRL_CSAR_LGO_MASK;
/* Wait until the cache command completes. */
while ((base->CSAR & CACHE64_CTRL_CSAR_LGO_MASK) != 0x00U)
{
}
startAddr += (uint32_t)CACHE64_LINESIZE_BYTE;
}
startAddr += (uint32_t)CACHE64_LINESIZE_BYTE;
}
}
@@ -333,7 +339,7 @@ void CACHE64_CleanInvalidateCache(CACHE64_CTRL_Type *base)
* brief Cleans and invalidate cache by range.
*
* param address The physical address of cache.
* param size_byte size of the memory to be Cleaned and Invalidated.
* param size_byte size of the memory to be Cleaned and Invalidated, should be larger than 0.
* note Address and size should be aligned to "CACHE64_LINESIZE_BYTE".
* The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if
* startAddr is not aligned. For the size_byte, application should make sure the
@@ -341,36 +347,39 @@ void CACHE64_CleanInvalidateCache(CACHE64_CTRL_Type *base)
*/
void CACHE64_CleanInvalidateCacheByRange(uint32_t address, uint32_t size_byte)
{
uint32_t endAddr = address + size_byte - 0x01U;
uint32_t pccReg = 0;
/* Align address to cache line size. */
uint32_t startAddr = address & ~((uint32_t)CACHE64_LINESIZE_BYTE - 1U);
uint32_t instance = CACHE64_GetInstanceByAddr(address);
uint32_t endLim;
CACHE64_CTRL_Type *base;
if (instance >= ARRAY_SIZE(s_cache64ctrlBases))
if (size_byte > 0UL)
{
return;
}
base = s_cache64ctrlBases[instance];
endLim = s_cache64PhymemBases[instance] + s_cache64PhymemSizes[instance] - 0x01U;
endAddr = endAddr > endLim ? endLim : endAddr;
uint32_t endAddr = address + size_byte - 0x01U;
uint32_t pccReg = 0;
/* Align address to cache line size. */
uint32_t startAddr = address & ~((uint32_t)CACHE64_LINESIZE_BYTE - 1U);
uint32_t instance = CACHE64_GetInstanceByAddr(address);
uint32_t endLim;
CACHE64_CTRL_Type *base;
/* Set the push by line command. */
pccReg = (base->CLCR & ~CACHE64_CTRL_CLCR_LCMD_MASK) | CACHE64_CTRL_CLCR_LCMD(3) | CACHE64_CTRL_CLCR_LADSEL_MASK;
base->CLCR = pccReg;
while (startAddr < endAddr)
{
/* Set the address and initiate the command. */
base->CSAR = (startAddr & CACHE64_CTRL_CSAR_PHYADDR_MASK) | CACHE64_CTRL_CSAR_LGO_MASK;
/* Wait until the cache command completes. */
while ((base->CSAR & CACHE64_CTRL_CSAR_LGO_MASK) != 0x00U)
if (instance >= ARRAY_SIZE(s_cache64ctrlBases))
{
return;
}
base = s_cache64ctrlBases[instance];
endLim = s_cache64PhymemBases[instance] + s_cache64PhymemSizes[instance] - 0x01U;
endAddr = endAddr > endLim ? endLim : endAddr;
/* Set the push by line command. */
pccReg = (base->CLCR & ~CACHE64_CTRL_CLCR_LCMD_MASK) | CACHE64_CTRL_CLCR_LCMD(3) | CACHE64_CTRL_CLCR_LADSEL_MASK;
base->CLCR = pccReg;
while (startAddr < endAddr)
{
/* Set the address and initiate the command. */
base->CSAR = (startAddr & CACHE64_CTRL_CSAR_PHYADDR_MASK) | CACHE64_CTRL_CSAR_LGO_MASK;
/* Wait until the cache command completes. */
while ((base->CSAR & CACHE64_CTRL_CSAR_LGO_MASK) != 0x00U)
{
}
startAddr += (uint32_t)CACHE64_LINESIZE_BYTE;
}
startAddr += (uint32_t)CACHE64_LINESIZE_BYTE;
}
}
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cache.h
+16 -16
View File
@@ -1,12 +1,12 @@
/*
* Copyright 2016-2021 NXP
* Copyright 2016-2021, 2023 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_CACHE_H_
#define _FSL_CACHE_H_
#ifndef FSL_CACHE_H_
#define FSL_CACHE_H_
#include "fsl_common.h"
@@ -20,10 +20,10 @@
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @{ */
/*! @brief cache driver version. */
#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 6))
/*@}*/
#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 7))
/*! @} */
/*! @brief cache line size. */
#define CACHE64_LINESIZE_BYTE (FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE)
@@ -138,7 +138,7 @@ void CACHE64_InvalidateCache(CACHE64_CTRL_Type *base);
* @brief Invalidates cache by range.
*
* @param address The physical address of cache.
* @param size_byte size of the memory to be invalidated.
* @param size_byte size of the memory to be invalidated, should be larger than 0.
* @note Address and size should be aligned to "CACHE64_LINESIZE_BYTE".
* The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if
* startAddr is not aligned. For the size_byte, application should make sure the
@@ -158,7 +158,7 @@ void CACHE64_CleanCache(CACHE64_CTRL_Type *base);
* @brief Cleans cache by range.
*
* @param address The physical address of cache.
* @param size_byte size of the memory to be cleaned.
* @param size_byte size of the memory to be cleaned, should be larger than 0.
* @note Address and size should be aligned to "CACHE64_LINESIZE_BYTE".
* The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if
* startAddr is not aligned. For the size_byte, application should make sure the
@@ -178,7 +178,7 @@ void CACHE64_CleanInvalidateCache(CACHE64_CTRL_Type *base);
* @brief Cleans and invalidate cache by range.
*
* @param address The physical address of cache.
* @param size_byte size of the memory to be Cleaned and Invalidated.
* @param size_byte size of the memory to be Cleaned and Invalidated, should be larger than 0.
* @note Address and size should be aligned to "CACHE64_LINESIZE_BYTE".
* The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if
* startAddr is not aligned. For the size_byte, application should make sure the
@@ -198,7 +198,7 @@ void CACHE64_CleanInvalidateCacheByRange(uint32_t address, uint32_t size_byte);
void CACHE64_EnableWriteBuffer(CACHE64_CTRL_Type *base, bool enable);
#endif
/*@}*/
/*! @} */
/*!
* @name Unified Cache Control for all caches
@@ -209,7 +209,7 @@ void CACHE64_EnableWriteBuffer(CACHE64_CTRL_Type *base, bool enable);
* @brief Invalidates instruction cache by range.
*
* @param address The physical address.
* @param size_byte size of the memory to be invalidated.
* @param size_byte size of the memory to be invalidated, should be larger than 0.
* @note Address and size should be aligned to CACHE64_LINESIZE_BYTE due to the cache operation unit
* FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line
* size if startAddr is not aligned. For the size_byte, application should make sure the
@@ -224,7 +224,7 @@ static inline void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte
* @brief Invalidates data cache by range.
*
* @param address The physical address.
* @param size_byte size of the memory to be invalidated.
* @param size_byte size of the memory to be invalidated, should be larger than 0.
* @note Address and size should be aligned to CACHE64_LINESIZE_BYTE due to the cache operation unit
* FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line
* size if startAddr is not aligned. For the size_byte, application should make sure the
@@ -239,7 +239,7 @@ static inline void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte
* @brief Clean data cache by range.
*
* @param address The physical address.
* @param size_byte size of the memory to be cleaned.
* @param size_byte size of the memory to be cleaned, should be larger than 0.
* @note Address and size should be aligned to CACHE64_LINESIZE_BYTE due to the cache operation unit
* FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line
* size if startAddr is not aligned. For the size_byte, application should make sure the
@@ -254,7 +254,7 @@ static inline void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte)
* @brief Cleans and Invalidates data cache by range.
*
* @param address The physical address.
* @param size_byte size of the memory to be Cleaned and Invalidated.
* @param size_byte size of the memory to be Cleaned and Invalidated, should be larger than 0.
* @note Address and size should be aligned to CACHE64_LINESIZE_BYTE due to the cache operation unit
* FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line
* size if startAddr is not aligned. For the size_byte, application should make sure the
@@ -265,7 +265,7 @@ static inline void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size
CACHE64_CleanInvalidateCacheByRange(address, size_byte);
}
/*@}*/
/*! @} */
#if defined(__cplusplus)
}
@@ -273,4 +273,4 @@ static inline void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size
/*! @}*/
#endif /* _FSL_CACHE_H_*/
#endif /* FSL_CACHE_H_*/
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cache_lpcac.h
+6 -6
View File
@@ -1,11 +1,11 @@
/*
* Copyright 2021-2022 NXP
* Copyright 2021-2023 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_CACHE_LPCAC_H_
#define _FSL_CACHE_LPCAC_H_
#ifndef FSL_CACHE_LPCAC_H_
#define FSL_CACHE_LPCAC_H_
#include "fsl_common.h"
@@ -21,7 +21,7 @@
/*! @name Driver version */
/*@{*/
/*! @brief cache driver version */
#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
#define FSL_CACHE_LPCAC_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
/*@}*/
/*******************************************************************************
* API
@@ -60,7 +60,7 @@ static inline void L1CACHE_DisableCodeCache(void)
*/
static inline void L1CACHE_InvalidateCodeCache(void)
{
SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK;
SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK;
}
/*!
@@ -181,4 +181,4 @@ static inline void L1CACHE_DisableXOMControl(void)
/*! @}*/
#endif /* _FSL_CACHE_LPCAC_H_*/
#endif /* FSL_CACHE_LPCAC_H_*/
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cdog.c
+55 -54
View File
@@ -24,6 +24,14 @@
static const IRQn_Type s_CdogIrqs[] = CDOG_IRQS;
#endif /* CDOG_IRQS */
#ifdef CDOG_CLOCKS
static const clock_ip_name_t s_CdogClocks[] = CDOG_CLOCKS;
#endif /* CDOG_CLOCKS */
#ifdef CDOG_BASE_PTRS
static const CDOG_Type* s_cdogBases[] = CDOG_BASE_PTRS;
#endif /* CDOG_BASE_PTRS */
/*******************************************************************************
* Prototypes
******************************************************************************/
@@ -31,50 +39,24 @@ static const IRQn_Type s_CdogIrqs[] = CDOG_IRQS;
/*******************************************************************************
* Code
******************************************************************************/
#if defined(CDOG)
/*!
* Weak implementation of CDOG IRQ, should be re-defined by user when using CDOG IRQ
*/
__WEAK void CDOG_DriverIRQHandler(void)
{
/* NVIC_DisableIRQ(CDOG_IRQn);
* CDOG_Stop(CDOG, s_start);
* CDOG->FLAGS = 0x0U;
* CDOG_Start(CDOG, 0xFFFFFFU, s_start);
* NVIC_EnableIRQ(CDOG_IRQn);
*/
}
#endif
#if defined(CDOG0)
/*!
* Weak implementation of CDOG0 IRQ, should be re-defined by user when using CDOG IRQ
*/
__WEAK void CDOG0_DriverIRQHandler(void)
static uint32_t CDOG_GetInstance(CDOG_Type *base)
{
/* NVIC_DisableIRQ(CDOG0_IRQn);
* CDOG_Stop(CDOG0, s_start);
* CDOG0->FLAGS = 0x0U;
* CDOG_Start(CDOG0, 0xFFFFFFU, s_start);
* NVIC_EnableIRQ(CDOG0_IRQn);
*/
}
#endif
#if defined(CDOG1)
/*!
* Weak implementation of CDOG1 IRQ, should be re-defined by user when using CDOG IRQ
*/
__WEAK void CDOG1_DriverIRQHandler(void)
{
/* NVIC_DisableIRQ(CDOG1_IRQn);
* CDOG_Stop(CDOG1, s_start);
* CDOG1->FLAGS = 0x0U;
* CDOG_Start(CDOG1, 0xFFFFFFU, s_start);
* NVIC_EnableIRQ(CDOG1_IRQn);
*/
}
#endif
uint32_t instance;
/* Find the instance index from base address mappings. */
for (instance = 0; instance < ARRAY_SIZE(s_cdogBases); instance++)
{
if (s_cdogBases[instance] == base)
{
break;
}
}
assert(instance < ARRAY_SIZE(s_cdogBases));
return instance;
}
/*!
* brief Sets the default configuration of CDOG
@@ -256,7 +238,13 @@ void CDOG_Sub256(CDOG_Type *base)
*/
void CDOG_Check(CDOG_Type *base, uint32_t check)
{
#if defined(FLS_FEATURE_CDOG_USE_RESTART)
base->RESTART = check;
#else
base->STOP = check;
base->RELOAD = base->RELOAD;
base->START= check;
#endif
}
/*!
@@ -295,7 +283,7 @@ status_t CDOG_Init(CDOG_Type *base, cdog_config_t *conf)
/* Ungate clock to CDOG engine and reset it */
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
#ifdef CDOG_CLOCKS
CLOCK_EnableClock(kCLOCK_Cdog);
CLOCK_EnableClock(s_CdogClocks[CDOG_GetInstance(base)]);
#endif /* CDOG_CLOCKS */
#endif /* !FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
@@ -322,6 +310,25 @@ status_t CDOG_Init(CDOG_Type *base, cdog_config_t *conf)
}
else
{
/* load default values for CDOG->CONTROL before flags clear */
#if defined(FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF) && (FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF > 0)
cdog_config_t default_conf;
/* Initialize CDOG */
CDOG_GetDefaultConfig(&default_conf);
/* Write default value to CDOG->CONTROL*/
base->CONTROL =
CDOG_CONTROL_TIMEOUT_CTRL(default_conf.timeout) | /* Action if the timeout event is triggered */
CDOG_CONTROL_MISCOMPARE_CTRL(default_conf.miscompare) | /* Action if the miscompare error event is triggered */
CDOG_CONTROL_SEQUENCE_CTRL(default_conf.sequence) | /* Action if the sequence error event is triggered */
CDOG_CONTROL_STATE_CTRL(default_conf.state) | /* Action if the state error event is triggered */
CDOG_CONTROL_ADDRESS_CTRL(default_conf.address) | /* Action if the address error event is triggered */
CDOG_CONTROL_IRQ_PAUSE(default_conf.irq_pause) | /* Pause running during interrupts setup */
CDOG_CONTROL_DEBUG_HALT_CTRL(default_conf.debug_halt) | /* Halt CDOG timer during debug */
CDOG_CONTROL_LOCK_CTRL(default_conf.lock) | RESERVED_CTRL_MASK; /* Lock control register, RESERVED */
#endif /* FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF */
base->FLAGS = CDOG_FLAGS_TO_FLAG(0U) | CDOG_FLAGS_MISCOM_FLAG(0U) | CDOG_FLAGS_SEQ_FLAG(0U) |
CDOG_FLAGS_CNT_FLAG(0U) | CDOG_FLAGS_STATE_FLAG(0U) | CDOG_FLAGS_ADDR_FLAG(0U) |
CDOG_FLAGS_POR_FLAG(0U);
@@ -338,11 +345,8 @@ status_t CDOG_Init(CDOG_Type *base, cdog_config_t *conf)
CDOG_CONTROL_LOCK_CTRL(conf->lock) | RESERVED_CTRL_MASK; /* Lock control register, RESERVED */
#if defined(CDOG_IRQS)
/* Enable peripheral IRQs, if defined in array */
for (uint32_t i = 0; i < ARRAY_SIZE(s_CdogIrqs); i++)
{
NVIC_EnableIRQ(s_CdogIrqs[i]);
}
/* Enable peripheral IRQ */
NVIC_EnableIRQ(s_CdogIrqs[CDOG_GetInstance(base)]);
#endif /* CDOG_IRQS */
return kStatus_Success;
@@ -358,11 +362,8 @@ status_t CDOG_Init(CDOG_Type *base, cdog_config_t *conf)
void CDOG_Deinit(CDOG_Type *base)
{
#if defined(CDOG_IRQS)
/* Enable peripheral IRQs, if defined in array */
for (uint32_t i = 0; i < ARRAY_SIZE(s_CdogIrqs); i++)
{
NVIC_DisableIRQ(s_CdogIrqs[i]);
}
/* Disable peripheral IRQ */
NVIC_DisableIRQ(s_CdogIrqs[CDOG_GetInstance(base)]);
#endif /* CDOG_IRQS */
#if !(defined(FSL_FEATURE_CDOG_HAS_NO_RESET) && FSL_FEATURE_CDOG_HAS_NO_RESET)
@@ -371,7 +372,7 @@ void CDOG_Deinit(CDOG_Type *base)
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
#ifdef CDOG_CLOCKS
CLOCK_DisableClock(kCLOCK_Cdog);
CLOCK_DisableClock(s_CdogClocks[CDOG_GetInstance(base)]);
#endif /* CDOG_CLOCKS */
#endif /* !FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cdog.h
+10 -18
View File
@@ -4,8 +4,8 @@
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_CDOG_H_
#define _FSL_CDOG_H_
#ifndef FSL_CDOG_H_
#define FSL_CDOG_H_
#include "fsl_common.h"
@@ -21,10 +21,13 @@
*******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief Defines CDOG driver version 2.1.2.
/*! @{ */
/*! @brief Defines CDOG driver version 2.1.3.
*
* Change log:
* - Version 2.1.3
* - Re-design multiple instance IRQs and Clocks
* - Add fix for RESTART command errata
* - Version 2.1.2
* - Support multiple IRQs
* - Fix default CONTROL values
@@ -39,8 +42,8 @@
* - Version 2.0.0
* - initial version
*/
#define FSL_CDOG_DRIVER_VERSION (MAKE_VERSION(2, 1, 2))
/*@}*/
#define FSL_CDOG_DRIVER_VERSION (MAKE_VERSION(2, 1, 3))
/*! @} */
typedef struct
{
@@ -139,17 +142,6 @@ typedef uint32_t secure_counter_t;
/*******************************************************************************
* API
*******************************************************************************/
#if defined(CDOG)
extern void CDOG_DriverIRQHandler(void);
#endif
#if defined(CDOG0)
extern void CDOG0_DriverIRQHandler(void);
#endif
#if defined(CDOG1)
extern void CDOG1_DriverIRQHandler(void);
#endif
#if defined(__cplusplus)
extern "C" {
@@ -334,4 +326,4 @@ uint32_t CDOG_ReadPersistent(CDOG_Type *base);
/*! @}*/ /* end of group cdog */
#endif /* _FSL_CDOG_H_ */
#endif /* FSL_CDOG_H_ */
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_clock.c
+223 -17
View File
@@ -1,5 +1,5 @@
/*
* Copyright 2022, NXP
* Copyright 2022-2023 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -207,6 +207,13 @@ status_t CLOCK_SetupExtClocking(uint32_t iFreq)
return (status_t)kStatus_SCG_Busy;
}
/* If sosc is used by PLL and PLL is used by system, return error. */
if ((((SCG0->APLLCTRL & SCG_APLLCTRL_SOURCE_MASK) == 0u) && ((SCG0->APLLCSR & SCG_APLLCSR_APLLSEL_MASK) != 0U)) ||
(((SCG0->SPLLCTRL & SCG_SPLLCTRL_SOURCE_MASK) == 0u) && ((SCG0->SPLLCSR & SCG_SPLLCSR_SPLLSEL_MASK) != 0U)))
{
return (status_t)kStatus_SCG_Busy;
}
/* If configure register is locked, return error. */
if ((SCG0->SOSCCSR & SCG_SOSCCSR_LK_MASK) != 0U)
{
@@ -238,6 +245,83 @@ status_t CLOCK_SetupExtClocking(uint32_t iFreq)
return kStatus_Success;
}
/**
* @brief Initialize the external reference clock to given frequency.
* @param iFreq : Desired frequency (must be equal to exact rate in Hz)
* @return returns success or fail status.
*/
status_t CLOCK_SetupExtRefClocking(uint32_t iFreq)
{
uint8_t range = 0U;
if ((iFreq >= 16000000U) && (iFreq < 20000000U))
{
range = 0U;
}
else if ((iFreq >= 20000000U) && (iFreq < 30000000U))
{
range = 1U;
}
else if ((iFreq >= 30000000U) && (iFreq < 50000000U))
{
range = 2U;
}
else if ((iFreq >= 50000000U) && (iFreq < 66000000U))
{
range = 3U;
}
else
{
return kStatus_InvalidArgument;
}
/* If clock is used by system, return error. */
if ((SCG0->SOSCCSR & SCG_SOSCCSR_SOSCSEL_MASK) != 0U)
{
return (status_t)kStatus_SCG_Busy;
}
/* If sosc is used by PLL and PLL is used by system, return error. */
if ((((SCG0->APLLCTRL & SCG_APLLCTRL_SOURCE_MASK) == 0u) && ((SCG0->APLLCSR & SCG_APLLCSR_APLLSEL_MASK) != 0U)) ||
(((SCG0->SPLLCTRL & SCG_SPLLCTRL_SOURCE_MASK) == 0u) && ((SCG0->SPLLCSR & SCG_SPLLCSR_SPLLSEL_MASK) != 0U)))
{
return (status_t)kStatus_SCG_Busy;
}
/* If configure register is locked, return error. */
if ((SCG0->SOSCCSR & SCG_SOSCCSR_LK_MASK) != 0U)
{
return kStatus_ReadOnly;
}
/* De-initializes the SCG SOSC */
SCG0->SOSCCSR = SCG_SOSCCSR_SOSCERR_MASK;
/* Enable LDO */
SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK;
/* Select SOSC source (external reference clock)*/
SCG0->SOSCCFG &= ~SCG_SOSCCFG_EREFS_MASK;
/*Configure SOSC range */
SCG0->SOSCCFG |= SCG_SOSCCFG_RANGE(range);
/* Unlock SOSCCSR */
SCG0->SOSCCSR &= ~SCG_SOSCCSR_LK_MASK;
/* Enable SOSC clock monitor and Enable SOSC */
SCG0->SOSCCSR |= (SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCEN_MASK);
/* Wait for SOSC clock to be valid. */
while ((SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) == 0U)
{
}
s_Ext_Clk_Freq = iFreq;
return kStatus_Success;
}
/**
* @brief Initialize the OSC 32K.
* @param id : OSC 32 kHz output clock to specified modules
@@ -250,8 +334,8 @@ status_t CLOCK_SetupOsc32KClocking(uint32_t id)
VBAT0->OSCCTLA =
(VBAT0->OSCCTLA & ~(VBAT_OSCCTLA_MODE_EN_MASK | VBAT_OSCCTLA_CAP_SEL_EN_MASK | VBAT_OSCCTLA_OSC_EN_MASK)) |
VBAT_OSCCTLA_MODE_EN(0x2) | VBAT_OSCCTLA_OSC_EN_MASK | VBAT_OSCCTLA_OSC_EN_MASK;
VBAT0->OSCCTLB = VBAT_OSCCTLB_INVERSE(0xDFF7E);
VBAT_OSCCTLA_MODE_EN(0x0) | VBAT_OSCCTLA_CAP_SEL_EN_MASK | VBAT_OSCCTLA_OSC_EN_MASK;
VBAT0->OSCCTLB = VBAT_OSCCTLB_INVERSE(0xFFF7E);
/* Wait for STATUSA[OSC_RDY] to set. */
while ((VBAT0->STATUSA & VBAT_STATUSA_OSC_RDY_MASK) == 0U)
{
@@ -309,11 +393,11 @@ status_t CLOCK_FROHFTrimConfig(firc_trim_config_t config)
if (kSCG_FircTrimNonUpdate == config.trimMode)
{
//SCG0->FIRCSTAT = SCG_FIRCSTAT_TRIMFINE(config.trimFine);
SCG0->FIRCSTAT = SCG_FIRCSTAT_TRIMFINE(config.trimFine);
}
/* Set trim mode. */
// SCG0->FIRCCSR = (uint32_t)config.trimMode;
SCG0->FIRCCSR = (uint32_t)config.trimMode;
if ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCERR_MASK) == SCG_FIRCCSR_FIRCERR_MASK)
{
@@ -444,6 +528,89 @@ void CLOCK_SetPll1MonitorMode(scg_pll1_monitor_mode_t mode)
SCG0->SPLLCSR = reg;
}
/*!
* @brief Set the additional number of wait-states added to account for the ratio of system clock period to flash access
* time during full speed power mode.
* @param system_freq_hz : Input frequency
* @param mode : Active run mode (voltage level).
* @return success or fail status
*/
status_t CLOCK_SetFLASHAccessCyclesForFreq(uint32_t system_freq_hz, run_mode_t mode)
{
uint32_t num_wait_states_added = 3UL; /* Default 3 additional wait states */
switch ((uint32_t)mode)
{
case (uint32_t)kMD_Mode:
{
if (system_freq_hz > 50000000U)
{
return kStatus_Fail;
}
if (system_freq_hz > 24000000U)
{
num_wait_states_added = 1U;
}
else
{
num_wait_states_added = 0U;
}
break;
}
case (uint32_t)kSD_Mode:
{
if (system_freq_hz > 100000000U)
{
return kStatus_Fail;
}
if (system_freq_hz > 64000000U)
{
num_wait_states_added = 2U;
}
else if (system_freq_hz > 36000000U)
{
num_wait_states_added = 1U;
}
else
{
num_wait_states_added = 0U;
}
break;
}
case (uint32_t)kOD_Mode:
{
if (system_freq_hz > 150000000U)
{
return kStatus_Fail;
}
if (system_freq_hz > 100000000U)
{
num_wait_states_added = 3U;
}
else if (system_freq_hz > 64000000U)
{
num_wait_states_added = 2U;
}
else if (system_freq_hz > 36000000U)
{
num_wait_states_added = 1U;
}
else
{
num_wait_states_added = 0U;
}
break;
}
default:
num_wait_states_added = 0U;
break;
}
/* additional wait-states are added */
FMU0->FCTRL = (FMU0->FCTRL & 0xFFFFFFF0UL) | (num_wait_states_added & 0xFUL);
return kStatus_Success;
}
/*!
* @brief Config 32k Crystal Oscillator.
*
@@ -677,11 +844,14 @@ uint32_t CLOCK_GetFreq(clock_name_t clockName)
switch (clockName)
{
case kCLOCK_MainClk:
freq = CLOCK_GetMainClkFreq();
break;
case kCLOCK_CoreSysClk:
freq = CLOCK_GetCoreSysClkFreq();
break;
case kCLOCK_BusClk:
freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U);
freq = CLOCK_GetCoreSysClkFreq();
break;
case kCLOCK_SystickClk0:
freq = CLOCK_GetSystickClkFreq(0U);
@@ -735,10 +905,10 @@ uint32_t CLOCK_GetFreq(clock_name_t clockName)
freq = CLOCK_GetOsc32KFreq((uint32_t)kCLOCK_Osc32kToMain);
break;
case kCLOCK_Pll0Out:
freq = CLOCK_GetPll1OutFreq();
freq = CLOCK_GetPll0OutFreq();
break;
case kCLOCK_Pll1Out:
freq = CLOCK_GetPll0OutFreq();
freq = CLOCK_GetPll1OutFreq();
break;
case kCLOCK_UsbPllOut:
// freq = CLOCK_GetPll0OutFreq();
@@ -1568,6 +1738,9 @@ uint32_t CLOCK_GetWdtClkFreq(uint32_t id)
case 2U:
freq = CLOCK_GetClk1MFreq();
break;
case 3U:
freq = CLOCK_GetClk1MFreq();
break;
default:
freq = 0U;
break;
@@ -2037,7 +2210,7 @@ pll_error_t CLOCK_SetPLL1Freq(const pll_setup_t *pSetup)
/* Unlock SPLLLOCK_CNFG register */
SCG0->TRIM_LOCK = 0x5a5a0001;
/* Configure lock time of APLL stable, value = 500μs/x+300, where x is the period of clk_ref (clk_in/N). */
/* Configure lock time of APLL stable, value = 500μs/x+300, where x is the period of clk_ref (clk_in/N). */
inRate = CLOCK_GetPLL1InClockRate();
prediv = findPll1PreDiv();
/* Adjust input clock */
@@ -2160,10 +2333,10 @@ static uint32_t CLOCK_GetOsc32KFreq(uint32_t id)
}
/* Get MAIN Clk */
/*! brief Return Frequency of Core System
* return Frequency of Core System
/*! @brief Return Frequency of main
* @return Frequency of the main
*/
uint32_t CLOCK_GetCoreSysClkFreq(void)
uint32_t CLOCK_GetMainClkFreq(void)
{
uint32_t freq = 0U;
@@ -2198,6 +2371,19 @@ uint32_t CLOCK_GetCoreSysClkFreq(void)
return freq;
}
/* Get cpu Clk */
/*! brief Return Frequency of Core System
* return Frequency of Core System
*/
uint32_t CLOCK_GetCoreSysClkFreq(void)
{
uint32_t freq = 0U;
freq = CLOCK_GetMainClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U);
return freq;
}
/* Get Systick Clk */
/*! brief Return Frequency of SystickClock
* return Frequency of Systick Clock
@@ -2209,7 +2395,7 @@ static uint32_t CLOCK_GetSystickClkFreq(uint32_t id)
switch ((id == 0U) ? SYSCON->SYSTICKCLKSEL0 : SYSCON->SYSTICKCLKSEL1)
{
case 0U:
freq = CLOCK_GetCoreSysClkFreq() / (((SYSCON->SYSTICKCLKDIV[id]) & 0xffU) + 1U);
freq = CLOCK_GetMainClkFreq() / (((SYSCON->SYSTICKCLKDIV[id]) & 0xffU) + 1U);
break;
case 1U:
freq = CLOCK_GetClk1MFreq();
@@ -2236,7 +2422,7 @@ static uint32_t CLOCK_GetClockOutClkFreq(void)
switch (SYSCON->CLKOUTSEL)
{
case 0U:
freq = CLOCK_GetCoreSysClkFreq();
freq = CLOCK_GetMainClkFreq();
break;
case 1U:
freq = CLOCK_GetPll0OutFreq();
@@ -2276,12 +2462,12 @@ static uint32_t CLOCK_GetLposcFreq(void)
switch ((RTC0->CTRL & RTC_CTRL_CLK_SEL_MASK) >> RTC_CTRL_CLK_SEL_SHIFT)
{
case 0U:
freq = CLOCK_GetClk16KFreq((uint32_t)kCLOCK_Clk16KToVbat);
break;
case 1U:
freq = CLOCK_GetOsc32KFreq((uint32_t)kCLOCK_Osc32kToVbat);
break;
case 2U:
freq = CLOCK_GetClk16KFreq((uint32_t)kCLOCK_Clk16KToVbat);
break;
default:
freq = 0U;
break;
@@ -2928,3 +3114,23 @@ bool CLOCK_EnableUsbhsClock(void)
}
return true;
}
/**
* @brief FIRC Auto Trim With SOF.
* @return returns success or fail status.
*/
status_t CLOCK_FIRCAutoTrimWithSOF(void)
{
/* System OSC Clock Monitor is disabled */
CLOCK_SetSysOscMonitorMode(kSCG_SysOscMonitorDisable);
firc_trim_config_t fircAutoTrimConfig = {
.trimMode = kSCG_FircTrimUpdate, /* FIRC trim is enabled and trim value update is enabled */
.trimSrc = kSCG_FircTrimSrcUsb0, /* Trim source is USB0 start of frame (1kHz) */
.trimDiv = 1U, /* Divided value */
.trimCoar = 0U, /* Trim value, see Reference Manual for more information */
.trimFine = 0U, /* Trim value, see Reference Manual for more information */
};
return CLOCK_FROHFTrimConfig(fircAutoTrimConfig);
}
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_clock.h
+641 -683
View File
File diff suppressed because it is too large Load Diff
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cmc.c
+44 -7
View File
@@ -1,5 +1,5 @@
/*
* Copyright 2022 NXP
* Copyright 2022-2024 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -107,6 +107,7 @@ void CMC_ConfigResetPin(CMC_Type *base, const cmc_reset_pin_config_t *config)
base->RPC = reg;
}
#if (defined(FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG) && FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG)
/*!
* brief Power off the selected system SRAM always.
*
@@ -119,10 +120,11 @@ void CMC_ConfigResetPin(CMC_Type *base, const cmc_reset_pin_config_t *config)
*/
void CMC_PowerOffSRAMAllMode(CMC_Type *base, uint32_t mask)
{
uint32_t reg = base->SRAMDIS[0];
uint32_t reg = base->SRAMDIS[0];
uint32_t maskToSet = mask & ((uint32_t)kCMC_AllSramArrays);
reg &= ~CMC_SRAMDIS_DIS_MASK;
reg |= CMC_SRAMDIS_DIS(mask);
reg &= ~((uint32_t)kCMC_AllSramArrays);
reg |= CMC_SRAMDIS_DIS(maskToSet);
base->SRAMDIS[0] = reg;
}
@@ -137,13 +139,36 @@ void CMC_PowerOffSRAMAllMode(CMC_Type *base, uint32_t mask)
*/
void CMC_PowerOffSRAMLowPowerOnly(CMC_Type *base, uint32_t mask)
{
uint32_t reg = base->SRAMRET[0];
uint32_t reg = base->SRAMRET[0];
uint32_t maskToSet = mask & ((uint32_t)kCMC_AllSramArrays);
reg &= ~CMC_SRAMRET_RET_MASK;
reg |= CMC_SRAMRET_RET(mask);
reg &= ~((uint32_t)kCMC_AllSramArrays);
reg |= CMC_SRAMRET_RET(maskToSet);
base->SRAMRET[0] = reg;
}
#endif /* FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG */
#if (defined(FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE) && FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE)
/*!
* brief Configs the low power mode of the on-chip flash memory.
*
* This function configs the low power mode of the on-chip flash memory.
*
* param base CMC peripheral base address.
* param doze true: Flash is disabled while core is sleeping
* false: No effect.
* param disable true: Flash memory is placed in low power state.
* false: No effect.
*/
void CMC_ConfigFlashMode(CMC_Type *base, bool doze, bool disable)
{
uint32_t reg = 0UL;
reg |= (disable ? CMC_FLASHCR_FLASHDIS(1U) : CMC_FLASHCR_FLASHDIS(0U)) |
(doze ? CMC_FLASHCR_FLASHDOZE(1U) : CMC_FLASHCR_FLASHDOZE(0U));
base->FLASHCR = reg;
}
#else
/*!
* brief Configs the low power mode of the on-chip flash memory.
*
@@ -169,6 +194,7 @@ void CMC_ConfigFlashMode(CMC_Type *base, bool wake, bool doze, bool disable)
(wake ? CMC_FLASHCR_FLASHWAKE(1U) : CMC_FLASHCR_FLASHWAKE(0U));
base->FLASHCR = reg;
}
#endif /* FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE */
/*!
* brief Prepares to enter stop modes.
@@ -233,8 +259,11 @@ void CMC_GlobalEnterLowPowerMode(CMC_Type *base, cmc_low_power_mode_t lowPowerMo
void CMC_EnterLowPowerMode(CMC_Type *base, const cmc_power_domain_config_t *config)
{
assert(config != NULL);
#if (CMC_PMCTRL_COUNT > 1U)
/* The WAKE domain must never be configured to a lower power mode compared with main power mode. */
assert(config->wake_domain <= config->main_domain);
#endif /* (CMC_PMCTRL_COUNT > 1U) */
if (config->clock_mode < kCMC_GateAllSystemClocksEnterLowPowerMode)
{
@@ -243,7 +272,9 @@ void CMC_EnterLowPowerMode(CMC_Type *base, const cmc_power_domain_config_t *conf
CMC_SetClockMode(base, config->clock_mode);
CMC_SetMAINPowerMode(base, kCMC_ActiveOrSleepMode);
#if (CMC_PMCTRL_COUNT > 1U)
CMC_SetWAKEPowerMode(base, kCMC_ActiveOrSleepMode);
#endif /* (CMC_PMCTRL_COUNT > 1U) */
/* Before executing WFI instruction read back the last register to
* ensure all registers writes have completed. */
@@ -258,16 +289,22 @@ void CMC_EnterLowPowerMode(CMC_Type *base, const cmc_power_domain_config_t *conf
/* Note: unlock the register if this API will be reinvoked later. */
CMC_SetClockMode(base, kCMC_GateAllSystemClocksEnterLowPowerMode);
CMC_SetMAINPowerMode(base, config->main_domain);
#if (CMC_PMCTRL_COUNT > 1U)
CMC_SetWAKEPowerMode(base, config->wake_domain);
#endif /* (CMC_PMCTRL_COUNT > 1U) */
/* Before execute WFI instruction read back the last register to
* ensure all registers writes have completed. */
#if (CMC_PMCTRL_COUNT > 1U)
if ((CMC_GetWAKEPowerMode(base) == config->wake_domain) && (CMC_GetMAINPowerMode(base) == config->main_domain))
{
#endif /* (CMC_PMCTRL_COUNT > 1U) */
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
__DSB();
__WFI();
__ISB();
#if (CMC_PMCTRL_COUNT > 1U)
}
#endif /* (CMC_PMCTRL_COUNT > 1U) */
}
}
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cmc.h
+100 -23
View File
@@ -1,11 +1,11 @@
/*
* Copyright 2022 NXP
* Copyright 2022-2024 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_CMC_H_
#define _FSL_CMC_H_
#ifndef FSL_CMC_H_
#define FSL_CMC_H_
#include "fsl_common.h"
/*!
@@ -17,8 +17,8 @@
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief CMC driver version 2.0.0. */
#define FSL_CMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
/*! @brief CMC driver version 2.2.2. */
#define FSL_CMC_DRIVER_VERSION (MAKE_VERSION(2, 2, 2))
/* @} */
/*!
@@ -34,6 +34,8 @@ enum _cmc_power_mode_protection
/*!
* @brief Wake up sources from the previous low power mode entry.
*
* @note #kCMC_WakeupFromUsbFs, #kCMC_WakeupFromITRC, #kCMC_WakeupFromCpu1 are not supported in MCXA family.
*/
enum _cmc_wakeup_sources
{
@@ -59,14 +61,25 @@ enum _cmc_system_reset_interrupt_enable
Reset interrupt enable. */
kCMC_WindowedWatchdog0ResetInterruptEnable = CMC_SRIE_WWDT0_MASK, /*!< Windowed Watchdog 0 reset
interrupt enable. */
kCMC_SoftwareResetInterruptEnable = CMC_SRIE_SW_MASK, /*!< Software Reset interrupt enable. */
kCMC_LockupResetInterruptEnable = CMC_SRIE_LOCKUP_MASK, /*!< Lockup Reset interrupt enable. */
kCMC_Cpu1ResetInterruptEnable = CMC_SRIE_CPU1_MASK, /*!< CPU1 Reset interrupt enable. */
kCMC_VBATResetInterruptEnable = CMC_SRIE_VBAT_MASK, /*!< VBAT reset interrupt enable. */
kCMC_SoftwareResetInterruptEnable = CMC_SRIE_SW_MASK, /*!< Software Reset interrupt enable. */
kCMC_LockupResetInterruptEnable = CMC_SRIE_LOCKUP_MASK, /*!< Lockup Reset interrupt enable. */
#if defined(CMC_SRIE_CPU1_MASK)
kCMC_Cpu1ResetInterruptEnable = CMC_SRIE_CPU1_MASK, /*!< CPU1 Reset interrupt enable. */
#endif /* CMC_SRIE_CPU1_MASK */
#if defined(CMC_SRIE_ADVC_MASK)
kCMC_AdvcResetInterruptEnable = CMC_SRIE_ADVC_MASK, /*!< ADVC Reset interrupt enable. */
#endif /* CMC_SRIE_ADVC_MASK */
#if defined(CMC_SRIE_VBAT_MASK)
kCMC_VBATResetInterruptEnable = CMC_SRIE_VBAT_MASK, /*!< VBAT reset interrupt enable. */
#endif /* CMC_SRIE_VBAT_MASK */
#if defined(CMC_SRIE_WWDT1_MASK)
kCMC_WindowedWatchdog1ResetInterruptEnable = CMC_SRIE_WWDT1_MASK, /*!< Windowed Watchdog 1 reset
interrupt enable. */
#endif /* CMC_SRIE_WWDT1_MASK */
kCMC_CodeWatchDog0ResetInterruptEnable = CMC_SRIE_CDOG0_MASK, /*!< Code watchdog 0 reset interrupt enable. */
#if defined(CMC_SRIE_CDOG1_MASK)
kCMC_CodeWatchDog1ResetInterruptEnable = CMC_SRIE_CDOG1_MASK, /*!< Code watchdog 1 reset interrupt enable. */
#endif /* CMC_SRIE_CDOG1_MASK */
};
/*!
@@ -81,13 +94,25 @@ enum _cmc_system_reset_interrupt_flag
kCMC_WindowedWatchdog0ResetInterruptFlag = CMC_SRIF_WWDT0_MASK, /*!< Windowned Watchdog 0 Reset interrupt flag. */
kCMC_SoftwareResetInterruptFlag = CMC_SRIF_SW_MASK, /*!< Software Reset interrupt flag. */
kCMC_LockupResetInterruptFlag = CMC_SRIF_LOCKUP_MASK, /*!< Lock up Reset interrupt flag. */
kCMC_Cpu1ResetInterruptFlag = CMC_SRIF_CPU1_MASK, /*!< CPU1 Reset interrupt flag. */
kCMC_VbatResetInterruptFlag = CMC_SRIF_VBAT_MASK, /*!< VBAT system reset interrupt flag. */
#if defined(CMC_SRIF_CPU1_MASK)
kCMC_Cpu1ResetInterruptFlag = CMC_SRIF_CPU1_MASK, /*!< CPU1 Reset interrupt flag. */
#endif /* CMC_SRIF_CPU1_MASK */
#if defined(CMC_SRIF_ADVC_MASK)
kCMC_AdvcResetInterruptFlag = CMC_SRIF_ADVC_MASK, /*!< ADVC Reset interrupt flag. */
#endif /* CMC_SRIF_ADVC_MASK */
#if defined(CMC_SRIF_VBAT_MASK)
kCMC_VbatResetInterruptFlag = CMC_SRIF_VBAT_MASK, /*!< VBAT system reset interrupt flag. */
#endif /* CMC_SRIF_VBAT_MASK */
#if defined(CMC_SRIF_WWDT1_MASK)
kCMC_WindowedWatchdog1ResetInterruptFlag = CMC_SRIF_WWDT1_MASK, /*!< Windowned Watchdog 1 Reset interrupt flag. */
kCMC_CodeWatchdog0ResetInterruptFlag = CMC_SRIF_CDOG0_MASK, /*!< Code watchdog0 reset interrupt flag. */
kCMC_CodeWatchdog1ResetInterruptFlag = CMC_SRIF_CDOG1_MASK, /*!< Code watchdog1 reset interrupt flag. */
#endif /* CMC_SRIF_WWDT1_MASK */
kCMC_CodeWatchdog0ResetInterruptFlag = CMC_SRIF_CDOG0_MASK, /*!< Code watchdog0 reset interrupt flag. */
#if defined(CMC_SRIF_CDOG1_MASK)
kCMC_CodeWatchdog1ResetInterruptFlag = CMC_SRIF_CDOG1_MASK, /*!< Code watchdog1 reset interrupt flag. */
#endif /* CMC_SRIF_CDOG1_MASK */
};
#if (defined(FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG) && FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG)
/*!
* @brief CMC System SRAM arrays low power mode enable enumeration.
*/
@@ -114,7 +139,13 @@ enum _cmc_system_sram_arrays
kCMC_PQ = 1UL << 27UL, /*!< Used to control PQ. */
kCMC_CAN0_CAN1_ENET_USB1 = 1UL << 28UL, /*!< Used to control CAN0, CAN1, ENET, USB1. */
kCMC_FlexSPI = 1UL << 29UL, /*!< Used to control FlexSPI. */
kCMC_AllSramArrays = (kCMC_RAMX0 | kCMC_RAMX1 | kCMC_RAMX2 | kCMC_RAMB | kCMC_RAMC0 | kCMC_RAMC1 | kCMC_RAMD0 |
kCMC_RAMD1 | kCMC_RAME0 | kCMC_RAME1 | kCMC_RAMF0 | kCMC_RAMF1 | kCMC_RAMG0_RAMG1 |
kCMC_RAMG2_RAMG3 | kCMC_RAMH0_RAMH1 | kCMC_LPCAC | kCMC_DMA0_DMA1_PKC | kCMC_USB0 | kCMC_PQ |
kCMC_CAN0_CAN1_ENET_USB1 | kCMC_FlexSPI), /*!< Mask of all System SRAM arrays. */
};
#endif /* FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG */
/*!
* @brief System reset sources enumeration.
@@ -137,14 +168,29 @@ enum _cmc_system_reset_sources
kCMC_WindowedWatchdog0Reset = CMC_SRS_WWDT0_MASK, /*!< The reset caused by the Windowed WatchDog 0 timeout. */
kCMC_SoftwareReset = CMC_SRS_SW_MASK, /*!< The reset caused by a software reset request. */
kCMC_LockUoReset = CMC_SRS_LOCKUP_MASK, /*!< The reset caused by the ARM core indication of a LOCKUP event. */
kCMC_Cpu1Reset = CMC_SRS_CPU1_MASK, /*!< The reset caused by a CPU1 system reset. */
kCMC_VbatReset = CMC_SRS_VBAT_MASK, /*!< The reset caused by a VBAT POR. */
#if defined(CMC_SRS_CPU1_MASK)
kCMC_Cpu1Reset = CMC_SRS_CPU1_MASK, /*!< The reset caused by a CPU1 system reset. */
#endif /* CMC_SRS_CPU1_MASK */
#if defined(CMC_SRS_ADVC_MASK)
kCMC_AdvcReset = CMC_SRS_ADVC_MASK, /*!< The reset caused by ADVC critical reset. */
#endif /* CMC_SRS_ADVC_MASK */
#if defined(CMC_SRS_VBAT_MASK)
kCMC_VbatReset = CMC_SRS_VBAT_MASK, /*!< The reset caused by a VBAT POR. */
#endif /* CMC_SRS_VBAT_MASK */
#if defined(CMC_SRS_WWDT1_MASK)
kCMC_WindowedWatchdog1Reset = CMC_SRS_WWDT1_MASK, /*!< The reset caused by the Windowed WatchDog 1 timeout. */
kCMC_CodeWatchDog0Reset = CMC_SRS_CDOG0_MASK, /*!< The reset caused by the code watchdog0 fault. */
kCMC_CodeWatchDog1Reset = CMC_SRS_CDOG1_MASK, /*!< The reset caused by the code watchdog1 fault. */
kCMC_JTAGSystemReset = CMC_SRS_JTAG_MASK, /*!< The reset caused by a JTAG system reset request. */
#endif /* CMC_SRS_WWDT1_MASK */
kCMC_CodeWatchDog0Reset = CMC_SRS_CDOG0_MASK, /*!< The reset caused by the code watchdog0 fault. */
#if defined(CMC_SRS_CDOG1_MASK)
kCMC_CodeWatchDog1Reset = CMC_SRS_CDOG1_MASK, /*!< The reset caused by the code watchdog1 fault. */
#endif /* CMC_SRS_CDOG1_MASK */
kCMC_JTAGSystemReset = CMC_SRS_JTAG_MASK, /*!< The reset caused by a JTAG system reset request. */
#if defined(CMC_SRS_SECVIO_MASK)
kCMC_SecurityViolationReset = CMC_SRS_SECVIO_MASK, /*!< The reset caused by a Security Violation logic. */
kCMC_TapmerReset = CMC_SRS_TAMPER_MASK, /*!< The reset caused by the tamper detection logic. */
#endif /* CMC_SRS_SECVIO_MASK */
#if defined(CMC_SRS_TAMPER_MASK)
kCMC_TapmerReset = CMC_SRS_TAMPER_MASK, /*!< The reset caused by the tamper detection logic. */
#endif /* CMC_SRS_TAMPER_MASK */
};
/*!
@@ -197,7 +243,9 @@ typedef struct _cmc_power_domain_config
{
cmc_clock_mode_t clock_mode; /*!< Clock mode for each power domain. */
cmc_low_power_mode_t main_domain; /*!< The low power mode of the MAIN power domain. */
#if (CMC_PMCTRL_COUNT > 1U)
cmc_low_power_mode_t wake_domain; /*!< The low power mode of the WAKE power domain. */
#endif /* (CMC_PMCTRL_COUNT > 1U) */
} cmc_power_domain_config_t;
/*******************************************************************************
@@ -335,8 +383,9 @@ static inline void CMC_ClearStickySystemResetStatus(CMC_Type *base, uint32_t mas
base->SSRS = mask;
}
#if (defined(FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG) && FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG)
/*!
* @brief Gets the number of reset sequences completed since the last WAKE Cold Reset.
* @brief Gets the number of reset sequences completed since the last Cold Reset.
*
* @param base CMC peripheral base address.
* @return The number of reset sequences.
@@ -345,6 +394,7 @@ static inline uint8_t CMC_GetResetCount(CMC_Type *base)
{
return (uint8_t)(base->RSTCNT & CMC_RSTCNT_COUNT_MASK);
}
#endif /* FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG */
/* @} */
@@ -422,6 +472,7 @@ static inline cmc_low_power_mode_t CMC_GetMAINPowerMode(CMC_Type *base)
return (cmc_low_power_mode_t)(uint32_t)(base->PMCTRL[0] & CMC_PMCTRL_LPMODE_MASK);
}
#if (CMC_PMCTRL_COUNT > 1U)
/*!
* @brief Configure entry into low power mode for the WAKE Power domain.
*
@@ -451,6 +502,7 @@ static inline cmc_low_power_mode_t CMC_GetWAKEPowerMode(CMC_Type *base)
{
return (cmc_low_power_mode_t)(uint32_t)(base->PMCTRL[1] & CMC_PMCTRL_LPMODE_MASK);
}
#endif /* CMC_PMCTRL_COUNT > 1U */
/* @} */
@@ -626,6 +678,7 @@ static inline void CMC_ForceBootConfiguration(CMC_Type *base, bool assert)
* @{
*/
#if (defined(FSL_FEATURE_MCX_CMC_HAS_BSR_REG) && FSL_FEATURE_MCX_CMC_HAS_BSR_REG)
/*!
* @brief Gets the status information written by the BootROM.
*
@@ -649,7 +702,9 @@ static inline void CMC_SetBootRomStatus(CMC_Type *base, uint32_t statValue)
{
base->BSR = CMC_BSR_STAT(statValue);
}
#endif /* FSL_FEATURE_MCX_CMC_HAS_BSR_REG */
#if (defined(FSL_FEATURE_MCX_CMC_HAS_BLR_REG) && FSL_FEATURE_MCX_CMC_HAS_BLR_REG)
/*!
* @brief Check if BootROM status and lock registers is writtable.
*
@@ -682,9 +737,11 @@ static inline void CMC_UnlockBootRomStatusWritten(CMC_Type *base)
{
base->BLR = CMC_BLR_LOCK(0x2U);
}
#endif /* FSL_FEATURE_MCX_CMC_HAS_BLR_REG */
/* @} */
#if (defined(FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG) && FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG)
/*!
* @name System SRAM Configuration.
* @{
@@ -693,10 +750,12 @@ static inline void CMC_UnlockBootRomStatusWritten(CMC_Type *base)
/*!
* @brief Power off the selected system SRAM always.
*
* This function power off the selected system SRAM always. The SRAM arrays should
* @note This function power off the selected system SRAM always. The SRAM arrays should
* not be accessed while they are shut down. SRAM array contents are not retained
* if they are powered off.
*
* @note Once invoked, the previous settings will be overwritten.
*
* @param base CMC peripheral base address.
* @param mask Bitmap of the SRAM arrays to be powered off all modes.
* See @ref _cmc_system_sram_arrays for details.
@@ -707,6 +766,8 @@ void CMC_PowerOffSRAMAllMode(CMC_Type *base, uint32_t mask);
/*!
* @brief Power on SRAM during all mode.
*
* @note Once invoked, the previous settings will be overwritten.
*
* @param base CMC peripheral base address.
* @param mask Bitmap of the SRAM arrays to be powered on all modes.
* See @ref _cmc_system_sram_arrays for details.
@@ -747,11 +808,27 @@ static inline void CMC_PowerOnSRAMLowPowerOnly(CMC_Type *base, uint32_t mask)
}
/* @} */
#endif /* FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG */
/*!
* @name Flash Low Power Mode configuration.
* @{
*/
#if (defined(FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE) && FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE)
/*!
* @brief Configs the low power mode of the on-chip flash memory.
*
* This function configs the low power mode of the on-chip flash memory.
*
* @param base CMC peripheral base address.
* @param doze true: Flash is disabled while core is sleeping
* false: No effect.
* @param disable true: Flash memory is placed in low power state.
* false: No effect.
*/
void CMC_ConfigFlashMode(CMC_Type *base, bool doze, bool disable);
#else
/*!
* @brief Configs the low power mode of the on-chip flash memory.
*
@@ -766,7 +843,7 @@ static inline void CMC_PowerOnSRAMLowPowerOnly(CMC_Type *base, uint32_t mask)
* false: No effect.
*/
void CMC_ConfigFlashMode(CMC_Type *base, bool wake, bool doze, bool disable);
#endif /* FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE */
/* @} */
/*!
@@ -849,4 +926,4 @@ void CMC_EnterLowPowerMode(CMC_Type *base, const cmc_power_domain_config_t *conf
#endif /* __cplusplus */
/*! @}*/
#endif /* _FSL_CMC_H_ */
#endif /* FSL_CMC_H_ */
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_common.h
+50 -23
View File
@@ -6,8 +6,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_COMMON_H_
#define _FSL_COMMON_H_
#ifndef FSL_COMMON_H_
#define FSL_COMMON_H_
#include <assert.h>
#include <stdbool.h>
@@ -57,12 +57,13 @@
#define MAKE_VERSION(major, minor, bugfix) (((major)*65536L) + ((minor)*256L) + (bugfix))
/*! @name Driver version */
/*@{*/
/*! @{ */
/*! @brief common driver version. */
#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))
/*@}*/
#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 4, 1))
/*! @} */
/* Debug console type definition. */
/*! @name Debug console type definition. */
/*! @{ */
#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */
#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console based on UART. */
#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console based on LPUART. */
@@ -74,6 +75,7 @@
#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console based on LPC_USART. */
#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console based on SWO. */
#define DEBUG_CONSOLE_DEVICE_TYPE_QSCI 10U /*!< Debug console based on QSCI. */
/*! @} */
/*! @brief Status group numbers. */
enum _status_groups
@@ -156,6 +158,9 @@ enum _status_groups
kStatusGroup_PUF = 105, /*!< Group number for PUF status codes. */
kStatusGroup_TOUCH_PANEL = 106, /*!< Group number for touch panel status codes */
kStatusGroup_VBAT = 107, /*!< Group number for VBAT status codes */
kStatusGroup_XSPI = 108, /*!< Group number for XSPI status codes */
kStatusGroup_PNGDEC = 109, /*!< Group number for PNGDEC status codes */
kStatusGroup_JPEGDEC = 110, /*!< Group number for JPEGDEC status codes */
kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */
kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */
@@ -166,6 +171,7 @@ enum _status_groups
kStatusGroup_HAL_PWM = 127, /*!< Group number for HAL PWM status codes. */
kStatusGroup_HAL_RNG = 128, /*!< Group number for HAL RNG status codes. */
kStatusGroup_HAL_I2S = 129, /*!< Group number for HAL I2S status codes. */
kStatusGroup_HAL_ADC_SENSOR = 130, /*!< Group number for HAL ADC SENSOR status codes. */
kStatusGroup_TIMERMANAGER = 135, /*!< Group number for TiMER MANAGER status codes. */
kStatusGroup_SERIALMANAGER = 136, /*!< Group number for SERIAL MANAGER status codes. */
kStatusGroup_LED = 137, /*!< Group number for LED status codes. */
@@ -188,15 +194,18 @@ enum _status_groups
kStatusGroup_LOG = 154, /*!< Group number for LOG status codes. */
kStatusGroup_I3CBUS = 155, /*!< Group number for I3CBUS status codes. */
kStatusGroup_QSCI = 156, /*!< Group number for QSCI status codes. */
kStatusGroup_SNT = 157, /*!< Group number for SNT status codes. */
kStatusGroup_ELEMU = 157, /*!< Group number for ELEMU status codes. */
kStatusGroup_QUEUEDSPI = 158, /*!< Group number for QSPI status codes. */
kStatusGroup_POWER_MANAGER = 159, /*!< Group number for POWER_MANAGER status codes. */
kStatusGroup_IPED = 160, /*!< Group number for IPED status codes. */
kStatusGroup_ELS_PKC = 161, /*!< Group number for ELS PKC status codes. */
kStatusGroup_HOSTIF = 162, /*!< Group number for HOSTIF status codes. */
kStatusGroup_CLIF = 163, /*!< Group number for CLIF status codes. */
kStatusGroup_BMA = 164, /*!< Group number for BMA status codes. */
kStatusGroup_NETC = 165, /*!< Group number for NETC status codes. */
kStatusGroup_CSS_PKC = 162, /*!< Group number for CSS PKC status codes. */
kStatusGroup_HOSTIF = 163, /*!< Group number for HOSTIF status codes. */
kStatusGroup_CLIF = 164, /*!< Group number for CLIF status codes. */
kStatusGroup_BMA = 165, /*!< Group number for BMA status codes. */
kStatusGroup_NETC = 166, /*!< Group number for NETC status codes. */
kStatusGroup_ELE = 167, /*!< Group number for ELE status codes. */
kStatusGroup_GLIKEY = 168, /*!< Group number for GLIKEY status codes. */
};
/*! \public
@@ -220,48 +229,66 @@ enum
/*! @brief Type used for all status and error return values. */
typedef int32_t status_t;
#ifdef __ZEPHYR__
#include <zephyr/sys/util.h>
#else
/*!
* @name Min/max macros
* @{
*/
#if !defined(MIN)
/*! Computes the minimum of \a a and \a b. */
#define MIN(a, b) (((a) < (b)) ? (a) : (b))
#endif
#if !defined(MAX)
/*! Computes the maximum of \a a and \a b. */
#define MAX(a, b) (((a) > (b)) ? (a) : (b))
#endif
/* @} */
/*! @} */
/*! @brief Computes the number of elements in an array. */
#if !defined(ARRAY_SIZE)
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
#endif
#endif /* __ZEPHYR__ */
/*! @name UINT16_MAX/UINT32_MAX value */
/* @{ */
/*! @{ */
#if !defined(UINT16_MAX)
/*! Max value of uint16_t type. */
#define UINT16_MAX ((uint16_t)-1)
#endif
#if !defined(UINT32_MAX)
/*! Max value of uint32_t type. */
#define UINT32_MAX ((uint32_t)-1)
#endif
/* @} */
/*! @} */
/*! @name Suppress fallthrough warning macro */
/* For switch case code block, if case section ends without "break;" statement, there wil be
fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc.
To suppress this warning, "SUPPRESS_FALL_THROUGH_WARNING();" need to be added at the end of each
case section which misses "break;"statement.
/*! Macro to get upper 32 bits of a 64-bit value */
#if !defined(UINT64_H)
#define UINT64_H(X) ((uint32_t)((((uint64_t) (X)) >> 32U) & 0x0FFFFFFFFULL))
#endif
/*! Macro to get lower 32 bits of a 64-bit value */
#if !defined(UINT64_L)
#define UINT64_L(X) ((uint32_t)(((uint64_t) (X)) & 0x0FFFFFFFFULL))
#endif
/*!
* @def SUPPRESS_FALL_THROUGH_WARNING()
*
* For switch case code block, if case section ends without "break;" statement, there wil be
* fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc.
* To suppress this warning, "SUPPRESS_FALL_THROUGH_WARNING();" need to be added at the end of each
* case section which misses "break;"statement.
*/
/* @{ */
#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
#define SUPPRESS_FALL_THROUGH_WARNING() __attribute__((fallthrough))
#else
#define SUPPRESS_FALL_THROUGH_WARNING()
#endif
/* @} */
/*******************************************************************************
* API
@@ -309,10 +336,10 @@ void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz);
#if (defined(__DSC__) && defined(__CW__))
#include "fsl_common_dsc.h"
#elif defined(__XCC__)
#elif defined(__XTENSA__)
#include "fsl_common_dsp.h"
#else
#include "fsl_common_arm.h"
#endif
#endif /* _FSL_COMMON_H_ */
#endif /* FSL_COMMON_H_ */
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_common_arm.c
+16 -8
View File
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
* Copyright 2016-2021 NXP
* Copyright 2016-2021, 2023 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -25,11 +25,11 @@ uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
extern uint32_t Image$$VECTOR_ROM$$Base[];
extern uint32_t Image$$VECTOR_RAM$$Base[];
extern uint32_t Image$$RW_m_data$$Base[];
extern uint32_t Image$$VECTOR_RAM$$ZI$$Limit[];
#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$VECTOR_RAM$$ZI$$Limit - (uint32_t)Image$$VECTOR_RAM$$Base))
#elif defined(__ICCARM__)
extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
extern uint32_t __VECTOR_TABLE[];
@@ -159,11 +159,11 @@ static void DelayLoop(uint32_t count)
{
__ASM volatile(" MOV X0, %0" : : "r"(count));
__ASM volatile(
"loop: \n"
"loop%=: \n"
" SUB X0, X0, #1 \n"
" CMP X0, #0 \n"
" BNE loop \n"
" BNE loop%= \n"
:
:
: "r0");
@@ -176,7 +176,7 @@ static void DelayLoop(uint32_t count)
{
__ASM volatile(" MOV R0, %0" : : "r"(count));
__ASM volatile(
"loop: \n"
"loop%=: \n"
#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
" SUB R0, R0, #1 \n"
#else
@@ -184,7 +184,7 @@ static void DelayLoop(uint32_t count)
#endif
" CMP R0, #0 \n"
" BNE loop \n"
" BNE loop%= \n"
:
:
: "r0");
@@ -232,13 +232,21 @@ void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz)
{
}
#else
#if defined(__CORTEX_Axx) && ((__CORTEX_Axx == 53) || (__CORTEX_Axx == 55))
/*
* Cortex-A53/A55 execution throughput:
* - SUB/CMP: 2 instructions per cycle
* - BNE: 1 instruction per cycle
* So, each loop takes 2 CPU cycles.
*/
count = count / 2U;
#elif (__CORTEX_M == 7)
/* Divide value may be different in various environment to ensure delay is precise.
* Every loop count includes three instructions, due to Cortex-M7 sometimes executes
* two instructions in one period, through test here set divide 1.5. Other M cores use
* divide 4. By the way, divide 1.5 or 4 could let the count lose precision, but it does
* not matter because other instructions outside while loop is enough to fill the time.
*/
#if (__CORTEX_M == 7)
count = count / 3U * 2U;
#else
count = count / 4U;
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_common_arm.h
+104 -33
View File
@@ -6,8 +6,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_COMMON_ARM_H_
#define _FSL_COMMON_ARM_H_
#ifndef FSL_COMMON_ARM_H_
#define FSL_COMMON_ARM_H_
/*
* For CMSIS pack RTE.
@@ -28,13 +28,7 @@
* These macros are used for atomic access, such as read-modify-write
* to the peripheral registers.
*
* - SDK_ATOMIC_LOCAL_ADD
* - SDK_ATOMIC_LOCAL_SET
* - SDK_ATOMIC_LOCAL_CLEAR
* - SDK_ATOMIC_LOCAL_TOGGLE
* - SDK_ATOMIC_LOCAL_CLEAR_AND_SET
*
* Take SDK_ATOMIC_LOCAL_CLEAR_AND_SET as an example: the parameter @c addr
* Take @ref SDK_ATOMIC_LOCAL_CLEAR_AND_SET as an example: the parameter @c addr
* means the address of the peripheral register or variable you want to modify
* atomically, the parameter @c clearBits is the bits to clear, the parameter
* @c setBits it the bits to set.
@@ -59,6 +53,27 @@
* @{
*/
/*!
* @def SDK_ATOMIC_LOCAL_ADD(addr, val)
* Add value \a val from the variable at address \a address.
*
* @def SDK_ATOMIC_LOCAL_SUB(addr, val)
* Subtract value \a val to the variable at address \a address.
*
* @def SDK_ATOMIC_LOCAL_SET(addr, bits)
* Set the bits specifiled by \a bits to the variable at address \a address.
*
* @def SDK_ATOMIC_LOCAL_CLEAR(addr, bits)
* Clear the bits specifiled by \a bits to the variable at address \a address.
*
* @def SDK_ATOMIC_LOCAL_TOGGLE(addr, bits)
* Toggle the bits specifiled by \a bits to the variable at address \a address.
*
* @def SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits)
* For the variable at address \a address, clear the bits specifiled by \a clearBits
* and set the bits specifiled by \a setBits.
*/
/* clang-format off */
#if ((defined(__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined(__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
@@ -220,6 +235,12 @@ static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uin
((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalAdd2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(val)) : \
_SDK_AtomicLocalAdd4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(val))))
#define SDK_ATOMIC_LOCAL_SUB(addr, val) \
((1UL == sizeof(*(addr))) ? \
_SDK_AtomicLocalSub1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(val)) : \
((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalSub2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(val)) : \
_SDK_AtomicLocalSub4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(val))))
#define SDK_ATOMIC_LOCAL_SET(addr, bits) \
((1UL == sizeof(*(addr))) ? \
_SDK_AtomicLocalSet1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \
@@ -255,7 +276,16 @@ static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uin
s_atomicOldInt = DisableGlobalIRQ(); \
*(addr) += (val); \
EnableGlobalIRQ(s_atomicOldInt); \
} while (0)
} while (false)
#define SDK_ATOMIC_LOCAL_SUB(addr, val) \
do \
{ \
uint32_t s_atomicOldInt; \
s_atomicOldInt = DisableGlobalIRQ(); \
*(addr) -= (val); \
EnableGlobalIRQ(s_atomicOldInt); \
} while (false)
#define SDK_ATOMIC_LOCAL_SET(addr, bits) \
do \
@@ -264,7 +294,7 @@ static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uin
s_atomicOldInt = DisableGlobalIRQ(); \
*(addr) |= (bits); \
EnableGlobalIRQ(s_atomicOldInt); \
} while (0)
} while (false)
#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits) \
do \
@@ -273,7 +303,7 @@ static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uin
s_atomicOldInt = DisableGlobalIRQ(); \
*(addr) &= ~(bits); \
EnableGlobalIRQ(s_atomicOldInt); \
} while (0)
} while (false)
#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) \
do \
@@ -282,7 +312,7 @@ static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uin
s_atomicOldInt = DisableGlobalIRQ(); \
*(addr) ^= (bits); \
EnableGlobalIRQ(s_atomicOldInt); \
} while (0)
} while (false)
#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \
do \
@@ -291,13 +321,13 @@ static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uin
s_atomicOldInt = DisableGlobalIRQ(); \
*(addr) = (*(addr) & ~(clearBits)) | (setBits); \
EnableGlobalIRQ(s_atomicOldInt); \
} while (0)
} while (false)
#endif
/* @} */
/*! @} */
/*! @name Timer utilities */
/* @{ */
/*! @{ */
/*! Macro to convert a microsecond period to raw count value */
#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)(((uint64_t)(us) * (clockFreqInHz)) / 1000000U)
/*! Macro to convert a raw count value to microsecond */
@@ -307,7 +337,7 @@ static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uin
#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)(ms) * (clockFreqInHz) / 1000U)
/*! Macro to convert a raw count value to millisecond */
#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count)*1000U / (clockFreqInHz))
/* @} */
/*! @} */
/*! @name ISR exit barrier
* @{
@@ -324,10 +354,10 @@ static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uin
#define SDK_ISR_EXIT_BARRIER
#endif
/* @} */
/*! @} */
/*! @name Alignment variable definition macros */
/* @{ */
/*! @{ */
#if (defined(__ICCARM__))
/*
* Workaround to disable MISRA C message suppress warnings for IAR compiler.
@@ -341,7 +371,7 @@ _Pragma("diag_suppress=Pm120")
#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
/*! Macro to define a variable with alignbytes alignment */
#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var
#elif defined(__GNUC__)
#elif defined(__GNUC__) || defined(DOXYGEN_OUTPUT)
/*! Macro to define a variable with alignbytes alignment */
#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
#else
@@ -360,15 +390,37 @@ _Pragma("diag_suppress=Pm120")
/*! Macro to change a value to a given size aligned value */
#define SDK_SIZEALIGN(var, alignbytes) \
((unsigned int)((var) + ((alignbytes)-1U)) & (unsigned int)(~(unsigned int)((alignbytes)-1U)))
/* @} */
/*! @} */
/*! @name Non-cacheable region definition macros */
/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or
* "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable
* variables, please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them,
/*!
* @name Non-cacheable region definition macros
*
* For initialized non-zero non-cacheable variables, please use "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or
* "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them. For zero-inited non-cacheable
* variables, please use "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them,
* these zero-inited variables will be initialized to zero in system startup.
*
* @note For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"
* in your projects to make sure the non-cacheable section variables will be initialized in system startup.
*
* @{
*/
/*!
* @def AT_NONCACHEABLE_SECTION(var)
* Define a variable \a var, and place it in non-cacheable section.
*
* @def AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes)
* Define a variable \a var, and place it in non-cacheable section, the start address
* of the variable is aligned to \a alignbytes.
*
* @def AT_NONCACHEABLE_SECTION_INIT(var)
* Define a variable \a var with initial value, and place it in non-cacheable section.
*
* @def AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes)
* Define a variable \a var with initial value, and place it in non-cacheable section,
* the start address of the variable is aligned to \a alignbytes.
*/
/* @{ */
#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && \
defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
@@ -394,7 +446,7 @@ _Pragma("diag_suppress=Pm120")
__attribute__((section(".bss.NonCacheable"))) __attribute__((aligned(alignbytes))) var
#endif
#elif (defined(__GNUC__))
#elif (defined(__GNUC__)) || defined(DOXYGEN_OUTPUT)
/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"
* in your projects to make sure the non-cacheable section variables will be initialized in system startup.
*/
@@ -417,12 +469,24 @@ _Pragma("diag_suppress=Pm120")
#endif
/* @} */
/*! @} */
/*!
* @name Time sensitive region
* @{
*/
/*!
* @def AT_QUICKACCESS_SECTION_CODE(func)
* Place function in a section which can be accessed quickly by core.
*
* @def AT_QUICKACCESS_SECTION_DATA(var)
* Place data in a section which can be accessed quickly by core.
*
* @def AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes)
* Place data in a section which can be accessed quickly by core, and the variable
* address is set to align with \a alignbytes.
*/
#if (defined(__ICCARM__))
#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess"
#define AT_QUICKACCESS_SECTION_DATA(var) var @"DataQuickAccess"
@@ -433,7 +497,7 @@ _Pragma("diag_suppress=Pm120")
#define AT_QUICKACCESS_SECTION_DATA(var) __attribute__((section("DataQuickAccess"))) var
#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \
__attribute__((section("DataQuickAccess"))) __attribute__((aligned(alignbytes))) var
#elif (defined(__GNUC__))
#elif (defined(__GNUC__)) || defined(DOXYGEN_OUTPUT)
#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func
#define AT_QUICKACCESS_SECTION_DATA(var) __attribute__((section("DataQuickAccess"))) var
#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \
@@ -441,18 +505,25 @@ _Pragma("diag_suppress=Pm120")
#else
#error Toolchain not supported.
#endif /* defined(__ICCARM__) */
/*! @} */
/*! @name Ram Function */
/*!
* @name Ram Function
* @{
*
* @def RAMFUNCTION_SECTION_CODE(func)
* Place function in ram.
*/
#if (defined(__ICCARM__))
#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction"
#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION))
#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
#elif (defined(__GNUC__))
#elif (defined(__GNUC__)) || defined(DOXYGEN_OUTPUT)
#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
#else
#error Toolchain not supported.
#endif /* defined(__ICCARM__) */
/* @} */
/*! @} */
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
void DefaultISR(void);
@@ -824,4 +895,4 @@ uint32_t MSDK_GetCpuCycleCount(void);
/*! @} */
#endif /* _FSL_COMMON_ARM_H_ */
#endif /* FSL_COMMON_ARM_H_ */
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_crc.c
+49
View File
@@ -40,6 +40,10 @@
/*< Default is resutl type is final checksum */
#endif /* CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT */
#if defined(CRC_RSTS)
#define CRC_RESETS_ARRAY CRC_RSTS
#endif
/*! @brief CRC type of transpose of read write data */
typedef enum _crc_transpose_type
{
@@ -65,9 +69,49 @@ typedef struct _crc_module_config
crc_bits_t crcBits; /*!< Selects 16- or 32- bit CRC protocol. */
} crc_module_config_t;
/*******************************************************************************
* Prototypes
******************************************************************************/
#if defined(CRC_RESETS_ARRAY)
/*!
* @brief Get instance number for CRC module.
*
* @param base CRC peripheral base address
*/
static uint32_t CRC_GetInstance(CRC_Type *base);
#endif
/*******************************************************************************
* Variables
******************************************************************************/
#if defined(CRC_RESETS_ARRAY)
static CRC_Type *const s_crcBases[] = CRC_BASE_PTRS;
/* Reset array */
static const reset_ip_name_t s_crcResets[] = CRC_RESETS_ARRAY;
#endif
/*******************************************************************************
* Code
******************************************************************************/
#if defined(CRC_RESETS_ARRAY)
static uint32_t CRC_GetInstance(CRC_Type *base)
{
uint32_t instance;
/* Find the instance index from base address mappings. */
for (instance = 0; instance < ARRAY_SIZE(s_crcBases); instance++)
{
if (s_crcBases[instance] == base)
{
break;
}
}
assert(instance < ARRAY_SIZE(s_crcBases));
return instance;
}
#endif
/*!
* @brief Returns transpose type for CRC protocol reflect in parameter.
@@ -191,6 +235,11 @@ void CRC_Init(CRC_Type *base, const crc_config_t *config)
/* ungate clock */
CLOCK_EnableClock(kCLOCK_Crc0);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
#if defined(CRC_RESETS_ARRAY)
RESET_ReleasePeripheralReset(s_crcResets[CRC_GetInstance(base)]);
#endif
/* configure CRC module and write the seed */
if (config->crcResult == kCrcFinalChecksum)
{
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_crc.h
+11 -8
View File
@@ -6,8 +6,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_CRC_H_
#define _FSL_CRC_H_
#ifndef FSL_CRC_H_
#define FSL_CRC_H_
#include "fsl_common.h"
@@ -21,13 +21,16 @@
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief CRC driver version. Version 2.0.3.
/*! @{ */
/*! @brief CRC driver version. Version 2.0.4.
*
* Current version: 2.0.3
* Current version: 2.0.4
*
* Change log:
*
* - Version 2.0.4
* - Release peripheral from reset if necessary in init function.
*
* - Version 2.0.3
* - Fix MISRA issues
*
@@ -37,8 +40,8 @@
* - Version 2.0.1
* - move DATA and DATALL macro definition from header file to source file
*/
#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 3))
/*@}*/
#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 4))
/*! @} */
#ifndef CRC_DRIVER_CUSTOM_DEFAULTS
/*! @brief Default configuration structure filled by CRC_GetDefaultConfig(). Use CRC16-CCIT-FALSE as defeault. */
@@ -175,4 +178,4 @@ uint16_t CRC_Get16bitResult(CRC_Type *base);
*@}
*/
#endif /* _FSL_CRC_H_ */
#endif /* FSL_CRC_H_ */
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_ctimer.c
+27
View File
@@ -575,3 +575,30 @@ void CTIMER4_DriverIRQHandler(void)
SDK_ISR_EXIT_BARRIER;
}
#endif
#if defined(CTIMER5)
void CTIMER5_DriverIRQHandler(void);
void CTIMER5_DriverIRQHandler(void)
{
CTIMER_GenericIRQHandler(5);
SDK_ISR_EXIT_BARRIER;
}
#endif
#if defined(CTIMER6)
void CTIMER6_DriverIRQHandler(void);
void CTIMER6_DriverIRQHandler(void)
{
CTIMER_GenericIRQHandler(6);
SDK_ISR_EXIT_BARRIER;
}
#endif
#if defined(CTIMER7)
void CTIMER7_DriverIRQHandler(void);
void CTIMER7_DriverIRQHandler(void)
{
CTIMER_GenericIRQHandler(7);
SDK_ISR_EXIT_BARRIER;
}
#endif
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_ctimer.h
+5 -5
View File
@@ -5,8 +5,8 @@
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_CTIMER_H_
#define _FSL_CTIMER_H_
#ifndef FSL_CTIMER_H_
#define FSL_CTIMER_H_
#include "fsl_common.h"
@@ -22,9 +22,9 @@
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @{ */
#define FSL_CTIMER_DRIVER_VERSION (MAKE_VERSION(2, 3, 1)) /*!< Version 2.3.1 */
/*@}*/
/*! @} */
/*! @brief List of Timer capture channels */
typedef enum _ctimer_capture_channel
@@ -679,4 +679,4 @@ static inline void CTIMER_SetShadowValue(CTIMER_Type *base, ctimer_match_t match
/*! @}*/
#endif /* _FSL_CTIMER_H_ */
#endif /* FSL_CTIMER_H_ */
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_dac.c
+18
View File
@@ -8,11 +8,20 @@
#include "fsl_dac.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.dac_1"
#endif
#if defined(DAC_RSTS)
#define DAC_RESETS_ARRAY DAC_RSTS
#elif defined(DAC_RSTS_N)
#define DAC_RESETS_ARRAY DAC_RSTS_N
#endif
/*******************************************************************************
* Prototypes
******************************************************************************/
@@ -34,6 +43,11 @@ static LPDAC_Type *const s_dacBases[] = LPDAC_BASE_PTRS;
static const clock_ip_name_t s_dacClocks[] = LPDAC_CLOCKS;
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
#if defined(DAC_RESETS_ARRAY)
/* Reset array */
static const reset_ip_name_t s_dacResets[] = DAC_RESETS_ARRAY;
#endif
/*******************************************************************************
* Code
******************************************************************************/
@@ -74,6 +88,10 @@ void DAC_Init(LPDAC_Type *base, const dac_config_t *config)
CLOCK_EnableClock(s_dacClocks[DAC_GetInstance(base)]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
#if defined(DAC_RESETS_ARRAY)
RESET_ReleasePeripheralReset(s_dacResets[DAC_GetInstance(base)]);
#endif
/* Reset the logic. */
DAC_SetReset(base, kDAC_ResetLogic);
DAC_ClearReset(base, kDAC_ResetLogic);
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_dac.h
+12 -12
View File
@@ -6,8 +6,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_DAC_H_
#define _FSL_DAC_H_
#ifndef FSL_DAC_H_
#define FSL_DAC_H_
#include "fsl_common.h"
@@ -23,10 +23,10 @@
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief DAC driver version 2.1.1. */
#define FSL_DAC_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
/*@}*/
/*! @{ */
/*! @brief DAC driver version 2.1.2. */
#define FSL_DAC_DRIVER_VERSION (MAKE_VERSION(2, 1, 2))
/*! @} */
/*!
* @brief DAC reset control.
@@ -293,7 +293,7 @@ static inline void DAC_Enable(LPDAC_Type *base, bool enable)
}
}
/* @} */
/*! @} */
/*!
* @name Interrupts
@@ -322,7 +322,7 @@ static inline void DAC_DisableInterrupts(LPDAC_Type *base, uint32_t mask)
base->IER &= ~mask;
}
/* @} */
/*! @} */
/*!
* @name DMA control
@@ -348,7 +348,7 @@ static inline void DAC_EnableDMA(LPDAC_Type *base, uint32_t mask, bool enable)
}
}
/* @} */
/*! @} */
/*!
* @name Status flags
@@ -377,7 +377,7 @@ static inline void DAC_ClearStatusFlags(LPDAC_Type *base, uint32_t flags)
base->FSR = flags;
}
/* @} */
/*! @} */
/*!
* @name Functional feature
@@ -430,7 +430,7 @@ static inline void DAC_DoSoftwareTriggerFIFO(LPDAC_Type *base)
base->TCR = LPDAC_TCR_SWTRG_MASK;
}
/* @} */
/*! @} */
#if defined(__cplusplus)
}
@@ -439,4 +439,4 @@ static inline void DAC_DoSoftwareTriggerFIFO(LPDAC_Type *base)
/*!
* @}
*/
#endif /* _FSL_DAC12_H_ */
#endif /* FSL_DAC12_H_ */
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_dac14.h
+13 -13
View File
@@ -5,8 +5,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_DAC14_H_
#define _FSL_DAC14_H_
#ifndef FSL_DAC14_H_
#define FSL_DAC14_H_
#include "fsl_common.h"
@@ -22,10 +22,10 @@
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @{ */
/*! @brief DAC14 driver version 2.0.0. */
#define FSL_DAC14_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
/*@}*/
/*! @} */
/*!
* @brief DAC14 interrupts enumeration.
@@ -209,7 +209,7 @@ static inline void DAC14_AbortPeriodTriggerConvSequence(HPDAC_Type *base)
{
base->GCR &= ~HPDAC_GCR_PTGEN_MASK;
}
/* @} */
/*! @} */
/*!
* @name DAC Control Interface
@@ -233,7 +233,7 @@ static inline void DAC14_Enable(HPDAC_Type *base, bool enable)
base->GCR &= ~HPDAC_GCR_DACEN_MASK;
}
}
/* @} */
/*! @} */
/*!
* @name Swing Back Mode Control Interface
@@ -256,7 +256,7 @@ static inline void DAC14_EnableSwingBackMode(HPDAC_Type *base, bool enable)
base->GCR &= ~HPDAC_GCR_SWMD_MASK;
}
}
/* @} */
/*! @} */
/*!
* @name FIFO Mode Control Interface
@@ -279,7 +279,7 @@ static inline void DAC14_EnableFIFOMode(HPDAC_Type *base, bool enable)
base->GCR &= ~HPDAC_GCR_FIFOEN_MASK;
}
}
/* @} */
/*! @} */
/*!
* @name Interrupts
@@ -306,7 +306,7 @@ static inline void DAC14_DisableInterrupts(HPDAC_Type *base, uint32_t mask)
{
base->IER &= ~mask;
}
/* @} */
/*! @} */
/*!
* @name DMA Control Interface
@@ -330,7 +330,7 @@ static inline void DAC14_EnableDMA(HPDAC_Type *base, uint32_t mask, bool enable)
base->DER &= ~mask;
}
}
/* @} */
/*! @} */
/*!
* @name Status
@@ -357,7 +357,7 @@ static inline void DAC14_ClearStatusFlags(HPDAC_Type *base, uint32_t flags)
{
base->FSR = flags;
}
/* @} */
/*! @} */
/*!
* @name Functional Feature
@@ -407,7 +407,7 @@ static inline void DAC14_DoSoftwareTrigger(HPDAC_Type *base)
{
base->TCR = HPDAC_TCR_SWTRG_MASK;
}
/* @} */
/*! @} */
#if defined(__cplusplus)
}
@@ -416,4 +416,4 @@ static inline void DAC14_DoSoftwareTrigger(HPDAC_Type *base)
/*!
* @}
*/
#endif /* _FSL_DAC14_H_ */
#endif /* FSL_DAC14_H_ */
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_edma.c
+1021 -339
View File
File diff suppressed because it is too large Load Diff
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_edma.h
+536 -127
View File
File diff suppressed because it is too large Load Diff
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_edma_core.h
+288 -151
View File
@@ -4,8 +4,8 @@
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_EDMA_CORE_H_
#define _FSL_EDMA_CORE_H_
#ifndef FSL_EDMA_CORE_H_
#define FSL_EDMA_CORE_H_
#include "fsl_edma_soc.h"
@@ -17,163 +17,209 @@
/*******************************************************************************
* Definitions
******************************************************************************/
#if defined(FSL_EDMA_SOC_IP_DMA3) && defined(FSL_EDMA_SOC_IP_DMA4) && FSL_EDMA_SOC_IP_DMA3 && FSL_EDMA_SOC_IP_DMA4
#define DMA_CSR_INTMAJOR_MASK DMA_TCD_CSR_INTMAJOR_MASK
#define DMA_CSR_INTHALF_MASK DMA_TCD_CSR_INTHALF_MASK
#define DMA_CSR_DREQ_MASK DMA_TCD_CSR_DREQ_MASK
#define DMA_CSR_ESG_MASK DMA_TCD_CSR_ESG_MASK
#define DMA_CSR_START_MASK DMA_TCD_CSR_START_MASK
#define DMA_CITER_ELINKNO_CITER_MASK DMA_TCD_CITER_ELINKNO_CITER_MASK
#define DMA_BITER_ELINKNO_BITER_MASK DMA_TCD_BITER_ELINKNO_BITER_MASK
#define DMA_CITER_ELINKNO_CITER_SHIFT DMA_TCD_CITER_ELINKNO_CITER_SHIFT
#define DMA_CITER_ELINKYES_CITER_MASK DMA_TCD_CITER_ELINKYES_CITER_MASK
#define DMA_CITER_ELINKYES_CITER_SHIFT DMA_TCD_CITER_ELINKYES_CITER_SHIFT
#define DMA_ATTR_SMOD_MASK DMA_TCD_ATTR_SMOD_MASK
#define DMA_ATTR_DMOD_MASK DMA_TCD_ATTR_DMOD_MASK
#define DMA_CITER_ELINKNO_ELINK_MASK DMA_TCD_CITER_ELINKNO_ELINK_MASK
#define DMA_CSR_MAJORELINK_MASK DMA_TCD_CSR_MAJORELINK_MASK
#define DMA_BITER_ELINKYES_ELINK_MASK DMA_TCD_BITER_ELINKYES_ELINK_MASK
#define DMA_CITER_ELINKYES_ELINK_MASK DMA_TCD_CITER_ELINKYES_ELINK_MASK
#define DMA_CSR_MAJORLINKCH_MASK DMA_TCD_CSR_MAJORLINKCH_MASK
#define DMA_BITER_ELINKYES_LINKCH_MASK DMA_TCD_BITER_ELINKYES_LINKCH_MASK
#define DMA_CITER_ELINKYES_LINKCH_MASK DMA_TCD_CITER_ELINKYES_LINKCH_MASK
#define DMA_NBYTES_MLOFFYES_MLOFF_MASK DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK
#define DMA_NBYTES_MLOFFYES_DMLOE_MASK DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK
#define DMA_NBYTES_MLOFFYES_SMLOE_MASK DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK
#define DMA_NBYTES_MLOFFNO_NBYTES_MASK DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK
#define DMA_ATTR_DMOD(x) DMA_TCD_ATTR_DMOD(x)
#define DMA_ATTR_SMOD(X) DMA_TCD_ATTR_SMOD(X)
#define DMA_BITER_ELINKYES_LINKCH(x) DMA_TCD_BITER_ELINKYES_LINKCH(x)
#define DMA_CITER_ELINKYES_LINKCH(x) DMA_TCD_CITER_ELINKYES_LINKCH(x)
#define DMA_NBYTES_MLOFFYES_MLOFF(x) DMA_TCD_NBYTES_MLOFFYES_MLOFF(x)
#define DMA_NBYTES_MLOFFYES_DMLOE(x) DMA_TCD_NBYTES_MLOFFYES_DMLOE(x)
#define DMA_NBYTES_MLOFFYES_SMLOE(x) DMA_TCD_NBYTES_MLOFFYES_SMLOE(x)
#define DMA_NBYTES_MLOFFNO_NBYTES(x) DMA_TCD_NBYTES_MLOFFNO_NBYTES(x)
#define DMA_NBYTES_MLOFFYES_NBYTES(x) DMA_TCD_NBYTES_MLOFFYES_NBYTES(x)
#define DMA_ATTR_DSIZE(x) DMA_TCD_ATTR_DSIZE(x)
#define DMA_ATTR_SSIZE(x) DMA_TCD_ATTR_SSIZE(x)
#define DMA_CSR_DREQ(x) DMA_TCD_CSR_DREQ(x)
#define DMA_CSR_MAJORLINKCH(x) DMA_TCD_CSR_MAJORLINKCH(x)
#define DMA_CH_MATTR_WCACHE(x) DMA4_CH_MATTR_WCACHE(x)
#define DMA_CH_MATTR_RCACHE(x) DMA4_CH_MATTR_RCACHE(x)
#define DMA_CH_CSR_SIGNEXT_MASK DMA4_CH_CSR_SIGNEXT_MASK
#define DMA_CH_CSR_SIGNEXT_SHIFT DMA4_CH_CSR_SIGNEXT_SHIFT
#define DMA_CH_CSR_SWAP_MASK DMA4_CH_CSR_SWAP_MASK
#define DMA_CH_CSR_SWAP_SHIFT DMA4_CH_CSR_SWAP_SHIFT
#define DMA_CH_SBR_INSTR_MASK DMA4_CH_SBR_INSTR_MASK
#define DMA_CH_SBR_INSTR_SHIFT DMA4_CH_SBR_INSTR_SHIFT
#define DMA_CH_MUX_SOURCE(x) DMA4_CH_MUX_SRC(x)
#elif defined(FSL_EDMA_SOC_IP_DMA3) && FSL_EDMA_SOC_IP_DMA3 && \
(!defined(FSL_EDMA_SOC_IP_DMA4) || (defined(FSL_EDMA_SOC_IP_DMA4) && !FSL_EDMA_SOC_IP_DMA4))
#define DMA_CSR_INTMAJOR_MASK DMA_TCD_CSR_INTMAJOR_MASK
#define DMA_CSR_INTHALF_MASK DMA_TCD_CSR_INTHALF_MASK
#define DMA_CSR_DREQ_MASK DMA_TCD_CSR_DREQ_MASK
#define DMA_CSR_ESG_MASK DMA_TCD_CSR_ESG_MASK
#define DMA_CSR_START_MASK DMA_TCD_CSR_START_MASK
#define DMA_CITER_ELINKNO_CITER_MASK DMA_TCD_CITER_ELINKNO_CITER_MASK
#define DMA_BITER_ELINKNO_BITER_MASK DMA_TCD_BITER_ELINKNO_BITER_MASK
#define DMA_CITER_ELINKNO_CITER_SHIFT DMA_TCD_CITER_ELINKNO_CITER_SHIFT
#define DMA_CITER_ELINKYES_CITER_MASK DMA_TCD_CITER_ELINKYES_CITER_MASK
#define DMA_CITER_ELINKYES_CITER_SHIFT DMA_TCD_CITER_ELINKYES_CITER_SHIFT
#define DMA_ATTR_SMOD_MASK DMA_TCD_ATTR_SMOD_MASK
#define DMA_ATTR_DMOD_MASK DMA_TCD_ATTR_DMOD_MASK
#define DMA_CITER_ELINKNO_ELINK_MASK DMA_TCD_CITER_ELINKNO_ELINK_MASK
#define DMA_CSR_MAJORELINK_MASK DMA_TCD_CSR_MAJORELINK_MASK
#define DMA_BITER_ELINKYES_ELINK_MASK DMA_TCD_BITER_ELINKYES_ELINK_MASK
#define DMA_CITER_ELINKYES_ELINK_MASK DMA_TCD_CITER_ELINKYES_ELINK_MASK
#define DMA_CSR_MAJORLINKCH_MASK DMA_TCD_CSR_MAJORLINKCH_MASK
#define DMA_BITER_ELINKYES_LINKCH_MASK DMA_TCD_BITER_ELINKYES_LINKCH_MASK
#define DMA_CITER_ELINKYES_LINKCH_MASK DMA_TCD_CITER_ELINKYES_LINKCH_MASK
#define DMA_NBYTES_MLOFFYES_MLOFF_MASK DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK
#define DMA_NBYTES_MLOFFYES_DMLOE_MASK DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK
#define DMA_NBYTES_MLOFFYES_SMLOE_MASK DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK
#define DMA_ATTR_DMOD(x) DMA_TCD_ATTR_DMOD(x)
#define DMA_ATTR_SMOD(X) DMA_TCD_ATTR_SMOD(X)
#define DMA_BITER_ELINKYES_LINKCH(x) DMA_TCD_BITER_ELINKYES_LINKCH(x)
#define DMA_CITER_ELINKYES_LINKCH(x) DMA_TCD_CITER_ELINKYES_LINKCH(x)
#define DMA_NBYTES_MLOFFYES_MLOFF(x) DMA_TCD_NBYTES_MLOFFYES_MLOFF(x)
#define DMA_NBYTES_MLOFFYES_DMLOE(x) DMA_TCD_NBYTES_MLOFFYES_DMLOE(x)
#define DMA_NBYTES_MLOFFYES_SMLOE(x) DMA_TCD_NBYTES_MLOFFYES_SMLOE(x)
#define DMA_NBYTES_MLOFFNO_NBYTES(x) DMA_TCD_NBYTES_MLOFFNO_NBYTES(x)
#define DMA_NBYTES_MLOFFYES_NBYTES(x) DMA_TCD_NBYTES_MLOFFYES_NBYTES(x)
#define DMA_ATTR_DSIZE(x) DMA_TCD_ATTR_DSIZE(x)
#define DMA_ATTR_SSIZE(x) DMA_TCD_ATTR_SSIZE(x)
#define DMA_CSR_DREQ(x) DMA_TCD_CSR_DREQ(x)
#define DMA_CSR_MAJORLINKCH(x) DMA_TCD_CSR_MAJORLINKCH(x)
#define DMA_CH_MUX_SOURCE(x) DMA_CH_MUX_SRC(x)
#elif defined(FSL_EDMA_SOC_IP_DMA4) && FSL_EDMA_SOC_IP_DMA4 && \
(!defined(FSL_EDMA_SOC_IP_DMA3) || (defined(FSL_EDMA_SOC_IP_DMA3) && !FSL_EDMA_SOC_IP_DMA3))
#define DMA_CSR_INTMAJOR_MASK DMA4_CSR_INTMAJOR_MASK
#define DMA_CSR_INTHALF_MASK DMA4_CSR_INTHALF_MASK
#define DMA_CSR_DREQ_MASK DMA4_CSR_DREQ_MASK
#define DMA_CSR_ESG_MASK DMA4_CSR_ESG_MASK
#define DMA_CSR_START_MASK DMA4_CSR_START_MASK
#define DMA_CITER_ELINKNO_CITER_MASK DMA4_CITER_ELINKNO_CITER_MASK
#define DMA_BITER_ELINKNO_BITER_MASK DMA4_BITER_ELINKNO_BITER_MASK
#define DMA_CITER_ELINKNO_CITER_SHIFT DMA4_CITER_ELINKNO_CITER_SHIFT
#define DMA_CITER_ELINKYES_CITER_MASK DMA4_CITER_ELINKYES_CITER_MASK
#define DMA_CITER_ELINKYES_CITER_SHIFT DMA4_CITER_ELINKYES_CITER_SHIFT
#define DMA_ATTR_SMOD_MASK DMA4_ATTR_SMOD_MASK
#define DMA_ATTR_DMOD_MASK DMA4_ATTR_DMOD_MASK
#define DMA_CITER_ELINKNO_ELINK_MASK DMA4_CITER_ELINKNO_ELINK_MASK
#define DMA_CSR_MAJORELINK_MASK DMA4_CSR_MAJORELINK_MASK
#define DMA_BITER_ELINKYES_ELINK_MASK DMA4_BITER_ELINKYES_ELINK_MASK
#define DMA_CITER_ELINKYES_ELINK_MASK DMA4_CITER_ELINKYES_ELINK_MASK
#define DMA_CSR_MAJORLINKCH_MASK DMA4_CSR_MAJORLINKCH_MASK
#define DMA_BITER_ELINKYES_LINKCH_MASK DMA4_BITER_ELINKYES_LINKCH_MASK
#define DMA_CITER_ELINKYES_LINKCH_MASK DMA4_CITER_ELINKYES_LINKCH_MASK
#define DMA_NBYTES_MLOFFYES_MLOFF_MASK DMA4_NBYTES_MLOFFYES_MLOFF_MASK
#define DMA_NBYTES_MLOFFYES_DMLOE_MASK DMA4_NBYTES_MLOFFYES_DMLOE_MASK
#define DMA_NBYTES_MLOFFYES_SMLOE_MASK DMA4_NBYTES_MLOFFYES_SMLOE_MASK
#define DMA_ATTR_DMOD(x) DMA4_ATTR_DMOD(x)
#define DMA_ATTR_SMOD(X) DMA4_ATTR_SMOD(X)
#define DMA_BITER_ELINKYES_LINKCH(x) DMA4_BITER_ELINKYES_LINKCH(x)
#define DMA_CITER_ELINKYES_LINKCH(x) DMA4_CITER_ELINKYES_LINKCH(x)
#define DMA_NBYTES_MLOFFYES_MLOFF(x) DMA4_NBYTES_MLOFFYES_MLOFF(x)
#define DMA_NBYTES_MLOFFYES_DMLOE(x) DMA4_NBYTES_MLOFFYES_DMLOE(x)
#define DMA_NBYTES_MLOFFYES_SMLOE(x) DMA4_NBYTES_MLOFFYES_SMLOE(x)
#define DMA_NBYTES_MLOFFNO_NBYTES(x) DMA4_NBYTES_MLOFFNO_NBYTES(x)
#define DMA_NBYTES_MLOFFYES_NBYTES(x) DMA4_NBYTES_MLOFFYES_NBYTES(x)
#define DMA_ATTR_DSIZE(x) DMA4_ATTR_DSIZE(x)
#define DMA_ATTR_SSIZE(x) DMA4_ATTR_SSIZE(x)
#define DMA_CSR_DREQ(x) DMA4_CSR_DREQ(x)
#define DMA_CSR_MAJORLINKCH(x) DMA4_CSR_MAJORLINKCH(x)
#define DMA_CH_MATTR_WCACHE(x) DMA4_CH_MATTR_WCACHE(x)
#define DMA_CH_MATTR_RCACHE(x) DMA4_CH_MATTR_RCACHE(x)
#define DMA_CH_CSR_SIGNEXT_MASK DMA4_CH_CSR_SIGNEXT_MASK
#define DMA_CH_CSR_SIGNEXT_SHIFT DMA4_CH_CSR_SIGNEXT_SHIFT
#define DMA_CH_CSR_SWAP_MASK DMA4_CH_CSR_SWAP_MASK
#define DMA_CH_CSR_SWAP_SHIFT DMA4_CH_CSR_SWAP_SHIFT
#define DMA_CH_SBR_INSTR_MASK DMA4_CH_SBR_INSTR_MASK
#define DMA_CH_SBR_INSTR_SHIFT DMA4_CH_SBR_INSTR_SHIFT
#define DMA_CH_MUX_SOURCE(x) DMA4_CH_MUX_SRC(x)
#define DMA_CH_CSR_DONE_MASK DMA4_CH_CSR_DONE_MASK
#define DMA_CH_CSR_ERQ_MASK DMA4_CH_CSR_ERQ_MASK
#elif defined(FSL_EDMA_SOC_IP_EDMA) && FSL_EDMA_SOC_IP_EDMA
/*! intentional empty */
#define DMA_CSR_INTMAJOR_MASK (0x2U)
#define DMA_CSR_INTHALF_MASK (0x4U)
#define DMA_CSR_DREQ_MASK (0x8U)
#define DMA_CSR_ESG_MASK (0x10U)
#define DMA_CSR_BWC_MASK (0xC000U)
#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << (14U))) & (0xC000U))
#define DMA_CSR_START_MASK (0x1U)
#define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)
#define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)
#define DMA_CITER_ELINKNO_CITER_SHIFT (0U)
#define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)
#define DMA_CITER_ELINKYES_CITER_SHIFT (0U)
#define DMA_ATTR_SMOD_MASK (0xF800U)
#define DMA_ATTR_DMOD_MASK (0xF8U)
#define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)
#define DMA_CSR_MAJORELINK_MASK (0x20U)
#define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)
#define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)
#define DMA_CSR_MAJORLINKCH_MASK (0x1F00U)
#define DMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U)
#define DMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U)
#define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)
#define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)
#define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)
#define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)
#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << (3U))) & (0xF8U))
#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << (11U))) & (0xF800U))
#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << (9U))) & (0x3E00U))
#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << (9U))) & (0x3E00U))
#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << (10U))) & (0x3FFFFC00U))
#define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << (30U))) & (0x40000000U))
#define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << (31U))) & (0x80000000U))
#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << (0U))) & (0x3FFFFFFFU))
#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << (0U))) & (0x3FFU))
#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << (0U))) & (0x7U))
#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << (8U))) & (0x700U))
#define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << (3U))) & (0x8U))
#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << (8U))) & (0x1F00U))
#define DMA_CH_MATTR_WCACHE(x) (((uint16_t)(((uint16_t)(x)) << (4U))) & (0xF0U))
#define DMA_CH_MATTR_RCACHE(x) (((uint16_t)(((uint16_t)(x)) << (0U))) & (0xFU))
#define DMA_CH_CSR_SIGNEXT_MASK (0x3F0000U)
#define DMA_CH_CSR_SIGNEXT_SHIFT (16U)
#define DMA_CH_CSR_SWAP_MASK (0xF000U)
#define DMA_CH_CSR_SWAP_SHIFT (12U)
#define DMA_CH_SBR_INSTR_MASK (0x2000U)
#define DMA_CH_SBR_INSTR_SHIFT (13U)
#define DMA_CH_MUX_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << (0U))) & (0xFFU))
/*! @brief DMA error flag */
#if defined(FSL_EDMA_SOC_IP_EDMA) && FSL_EDMA_SOC_IP_EDMA
#define DMA_ERR_DBE_FLAG DMA_ES_DBE_MASK
#define DMA_ERR_SBE_FLAG DMA_ES_SBE_MASK
#define DMA_ERR_SGE_FLAG DMA_ES_SGE_MASK
#define DMA_ERR_NCE_FLAG DMA_ES_NCE_MASK
#define DMA_ERR_DOE_FLAG DMA_ES_DOE_MASK
#define DMA_ERR_DAE_FLAG DMA_ES_DAE_MASK
#define DMA_ERR_SOE_FLAG DMA_ES_SOE_MASK
#define DMA_ERR_SAE_FLAG DMA_ES_SAE_MASK
#define DMA_ERR_ERRCHAN_FLAG DMA_ES_ERRCHN_MASK
#define DMA_ERR_CPE_FLAG DMA_ES_CPE_MASK
#define DMA_ERR_ECX_FLAG DMA_ES_ECX_MASK
#if defined(FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT) && (FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 1)
#define DMA_ERR_GPE_FLAG DMA_ES_GPE_MASK
#endif
#define DMA_ERR_FLAG DMA_ES_VLD_MASK
/*! @brief get/clear DONE status*/
#define DMA_CLEAR_DONE_STATUS(base, channel) (EDMA_BASE(base)->CDNE = (uint8_t)channel)
#define DMA_GET_DONE_STATUS(base, channel) \
((EDMA_TCD_BASE(base, channel)->CSR & DMA_CSR_DONE_MASK) >> DMA_CSR_DONE_SHIFT)
/*! @brief enable/disable error interrupt*/
#define DMA_ENABLE_ERROR_INT(base, channel) (base->EEI |= ((uint32_t)0x1U << channel))
#define DMA_DISABLE_ERROR_INT(base, channel) (base->EEI &= (~((uint32_t)0x1U << channel)))
/*! @brief get/clear error status*/
#define DMA_GET_ERROR_STATUS(base, channel) (((uint32_t)EDMA_BASE(base)->ERR >> channel) & 0x1U)
#define DMA_CLEAR_ERROR_STATUS(base, channel) ((uint32_t)EDMA_BASE(base)->CERR = (uint8_t)channel)
/*! @brief get/clear int status*/
#define DMA_GET_INT_STATUS(base, channel) ((((uint32_t)EDMA_BASE(base)->INT >> channel) & 0x1U))
#define DMA_CLEAR_INT_STATUS(base, channel) ((uint32_t)EDMA_BASE(base)->CINT = (uint8_t)channel)
#else
#define DMA_ERR_DBE_FLAG DMA_MP_ES_DBE_MASK
#define DMA_ERR_SBE_FLAG DMA_MP_ES_SBE_MASK
#define DMA_ERR_SGE_FLAG DMA_MP_ES_SGE_MASK
#define DMA_ERR_NCE_FLAG DMA_MP_ES_NCE_MASK
#define DMA_ERR_DOE_FLAG DMA_MP_ES_DOE_MASK
#define DMA_ERR_DAE_FLAG DMA_MP_ES_DAE_MASK
#define DMA_ERR_SOE_FLAG DMA_MP_ES_SOE_MASK
#define DMA_ERR_SAE_FLAG DMA_MP_ES_SAE_MASK
#define DMA_ERR_ERRCHAN_FLAG DMA_MP_ES_ERRCHN_MASK
#define DMA_ERR_ECX_FLAG DMA_MP_ES_ECX_MASK
#define DMA_ERR_FLAG DMA_MP_ES_VLD_MASK
/*! @brief get/clear DONE bit*/
#define DMA_CLEAR_DONE_STATUS(base, channel) (EDMA_CHANNEL_BASE(base, channel)->CH_CSR |= DMA_CH_CSR_DONE_MASK)
#define DMA_GET_DONE_STATUS(base, channel) \
((EDMA_CHANNEL_BASE(base, channel)->CH_CSR & DMA_CH_CSR_DONE_MASK) >> DMA_CH_CSR_DONE_SHIFT)
/*! @brief enable/disable error interupt*/
#define DMA_ENABLE_ERROR_INT(base, channel) (EDMA_CHANNEL_BASE(base, channel)->CH_CSR |= DMA_CH_CSR_EEI_MASK)
#define DMA_DISABLE_ERROR_INT(base, channel) (EDMA_CHANNEL_BASE(base, channel)->CH_CSR &= ~DMA_CH_CSR_EEI_MASK)
/*! @brief get/clear error status*/
#define DMA_CLEAR_ERROR_STATUS(base, channel) (EDMA_CHANNEL_BASE(base, channel)->CH_ES |= DMA_CH_ES_ERR_MASK)
#define DMA_GET_ERROR_STATUS(base, channel) \
(((uint32_t)EDMA_CHANNEL_BASE(base, channel)->CH_ES >> DMA_CH_ES_ERR_SHIFT) & 0x1U)
/*! @brief get/clear INT status*/
#define DMA_CLEAR_INT_STATUS(base, channel) (EDMA_CHANNEL_BASE(base, channel)->CH_INT = DMA_CH_INT_INT_MASK)
#define DMA_GET_INT_STATUS(base, channel) ((((uint32_t)EDMA_CHANNEL_BASE(base, channel)->CH_INT) & 0x1U))
#endif /*FSL_EDMA_SOC_IP_EDMA*/
/*! @brief enable/dsiable MAJOR/HALF INT*/
#define DMA_ENABLE_MAJOR_INT(base, channel) \
(EDMA_TCD_CSR(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) |= DMA_CSR_INTMAJOR_MASK)
#define DMA_ENABLE_HALF_INT(base, channel) \
(EDMA_TCD_CSR(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) |= DMA_CSR_INTHALF_MASK)
#define DMA_DISABLE_MAJOR_INT(base, channel) \
(EDMA_TCD_CSR(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) &= ~(uint16_t)DMA_CSR_INTMAJOR_MASK)
#define DMA_DISABLE_HALF_INT(base, channel) \
(EDMA_TCD_CSR(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) &= ~(uint16_t)DMA_CSR_INTHALF_MASK)
/*!@brief EDMA tcd align size */
#define EDMA_TCD_ALIGN_SIZE (32U)
/*!@brief edma core channel struture definition */
typedef struct _edma_core_mp
{
__IO uint32_t MP_CSR; /**< Channel Control and Status, array offset: 0x10000, array step: 0x10000 */
__IO uint32_t MP_ES; /**< Channel Error Status, array offset: 0x10004, array step: 0x10000 */
union
{
struct
{
__IO uint32_t MP_INT_LOW; /**< Channel Control and Status, array offset: 0x10008, array step: 0x10000 */
__I uint32_t MP_INT_HIGH; /**< Channel Control and Status, array offset: 0x1000C, array step: 0x10000 */
__I uint32_t MP_HRS_LOW; /**< Channel Control and Status, array offset: 0x10010, array step: 0x10000 */
__I uint32_t MP_HRS_HIGH; /**< Channel Control and Status, array offset: 0x10014, array step: 0x10000 */
uint8_t RESERVED_0[8];
__IO uint32_t MP_STOPCH; /**< Channel Control and Status, array offset: 0x10020, array step: 0x10000 */
uint8_t RESERVED_1[12];
__I uint32_t MP_SSR_LOW; /**< Channel Control and Status, array offset: 0x10030, array step: 0x10000 */
__I uint32_t MP_SSR_HIGH; /**< Channel Control and Status, array offset: 0x10034, array step: 0x10000 */
uint8_t RESERVED_2[200];
__IO uint32_t CH_GRPRI[64]; /**< Channel Control and Status, array offset: 0x10100, array step: 0x10000 */
__IO uint32_t CH_MUX[64]; /**< Channel Control and Status, array offset: 0x10200, array step: 0x10000 */
uint8_t RESERVED_3[256];
__IO uint32_t CH_PROT[64]; /**< Channel Control and Status, array offset: 0x10400, array step: 0x10000 */
} EDMA5_REG;
} MP_REGS;
} edma_core_mp_t;
/*!@brief edma core channel struture definition */
typedef struct _edma_core_channel
{
__IO uint32_t CH_CSR; /**< Channel Control and Status, array offset: 0x10000, array step: 0x10000 */
__IO uint32_t CH_ES; /**< Channel Error Status, array offset: 0x10004, array step: 0x10000 */
__IO uint32_t CH_INT; /**< Channel Interrupt Status, array offset: 0x10008, array step: 0x10000 */
__IO uint32_t CH_SBR; /**< Channel System Bus, array offset: 0x1000C, array step: 0x10000 */
__IO uint32_t CH_PRI; /**< Channel Priority, array offset: 0x10010, array step: 0x10000 */
__IO uint32_t CH_MUX; /**< Channel Multiplexor Configuration, array offset: 0x10014, array step: 0x10000 */
__IO uint16_t CH_MATTR; /**< Memory Attributes Register, array offset: 0x10018, array step: 0x8000 */
__IO uint32_t CH_CSR; /**< Channel Control and Status, array offset: 0x10000, array step: 0x10000 */
__IO uint32_t CH_ES; /**< Channel Error Status, array offset: 0x10004, array step: 0x10000 */
__IO uint32_t CH_INT; /**< Channel Interrupt Status, array offset: 0x10008, array step: 0x10000 */
__IO uint32_t CH_SBR; /**< Channel System Bus, array offset: 0x1000C, array step: 0x10000 */
__IO uint32_t CH_PRI; /**< Channel Priority, array offset: 0x10010, array step: 0x10000 */
union
{
struct
{
__IO uint8_t RESERVED_1[4];
__IO uint32_t CH_MATTR; /**< Memory Attributes Register, array offset: 0x10018, array step: 0x8000 */
} EDMA5_REG;
struct
{
__IO uint32_t CH_MUX; /**< Channel Multiplexor Configuration, array offset: 0x10014, array step: 0x10000 */
__IO uint16_t CH_MATTR; /**< Memory Attributes Register, array offset: 0x10018, array step: 0x8000 */
} EDMA4_REG;
} CH_REGS;
} edma_core_channel_t;
/*!@brief edma core TCD struture definition */
typedef struct _edma_core_tcd
/*! @brief eDMA tcd flag type */
typedef enum _edma_tcd_type
{
kEDMA_EDMA4Flag = 0x0U, /*!< Data access for eDMA4 transfers. */
kEDMA_EDMA5Flag = 0x1U, /*!< Instruction access for eDMA4 transfers. */
} edma_tcd_type_t;
/*!@brief edma5 core TCD struture definition */
typedef struct _edma5_core_tcd
{
__IO uint32_t SADDR; /*!< SADDR register, used to save source address */
__IO uint32_t SADDR_HIGH; /*!< SADDR HIGH register, used to save source address */
__IO uint16_t SOFF; /*!< SOFF register, save offset bytes every transfer */
__IO uint16_t ATTR; /*!< ATTR register, source/destination transfer size and modulo */
__IO uint32_t NBYTES; /*!< Nbytes register, minor loop length in bytes */
__IO uint32_t SLAST; /*!< SLAST register */
__IO uint32_t SLAST_SDA_HIGH; /*!< SLAST SDA HIGH register */
__IO uint32_t DADDR; /*!< DADDR register, used for destination address */
__IO uint32_t DADDR_HIGH; /*!< DADDR HIGH register, used for destination address */
__IO uint32_t DLAST_SGA; /*!< DLASTSGA register, next tcd address used in scatter-gather mode */
__IO uint32_t DLAST_SGA_HIGH; /*!< DLASTSGA HIGH register, next tcd address used in scatter-gather mode */
__IO uint16_t DOFF; /*!< DOFF register, used for destination offset */
__IO uint16_t CITER; /*!< CITER register, current minor loop numbers, for unfinished minor loop.*/
__IO uint16_t CSR; /*!< CSR register, for TCD control status */
__IO uint16_t BITER; /*!< BITER register, begin minor loop count. */
uint8_t RESERVED[16]; /*!< Aligned 64 bytes */
} edma5_core_tcd_t;
/*!@brief edma4 core TCD struture definition */
typedef struct _edma4_core_tcd
{
__IO uint32_t SADDR; /*!< SADDR register, used to save source address */
__IO uint16_t SOFF; /*!< SOFF register, save offset bytes every transfer */
@@ -186,6 +232,18 @@ typedef struct _edma_core_tcd
__IO uint32_t DLAST_SGA; /*!< DLASTSGA register, next tcd address used in scatter-gather mode */
__IO uint16_t CSR; /*!< CSR register, for TCD control status */
__IO uint16_t BITER; /*!< BITER register, begin minor loop count. */
} edma4_core_tcd_t;
/*!@brief edma core TCD struture definition */
typedef struct _edma_core_tcd
{
union
{
edma4_core_tcd_t edma4_tcd;
#if defined FSL_EDMA_SOC_IP_DMA5 && FSL_EDMA_SOC_IP_DMA5
edma5_core_tcd_t edma5_tcd;
#endif /* FSL_EDMA_SOC_IP_DMA5 */
} TCD_REGS;
} edma_core_tcd_t;
/*!@brief EDMA typedef */
@@ -195,12 +253,91 @@ typedef void EDMA_Type;
/*!@brief EDMA base address convert macro */
#define EDMA_BASE(base)
#define EDMA_CHANNEL_BASE(base, channel) \
((edma_core_channel_t *)((uint32_t)base + EDMA_CHANNEL_OFFSET + channel * EDMA_CHANNEL_ARRAY_STEP(base)))
#define EDMA_TCD_BASE(base, channel) \
((edma_core_tcd_t *)((uint32_t)base + EDMA_CHANNEL_OFFSET + channel * EDMA_CHANNEL_ARRAY_STEP(base) + 0x20U))
#define EDMA_MP_BASE(base) ((edma_core_mp_t *)((uint32_t)base))
#define EDMA_CHANNEL_BASE(base, channel) \
((edma_core_channel_t *)((uint32_t)(uint32_t *)(base) + EDMA_CHANNEL_OFFSET + \
(channel)*EDMA_CHANNEL_ARRAY_STEP(base)))
#define EDMA_TCD_BASE(base, channel) \
((edma_core_tcd_t *)((uint32_t)(uint32_t *)(base) + EDMA_CHANNEL_OFFSET + \
(channel)*EDMA_CHANNEL_ARRAY_STEP(base) + 0x20U))
#define EDMA_MP_BASE(base) ((edma_core_mp_t *)((uint32_t)(uint32_t *)(base)))
/*!@brief EDMA TCD type macro */
#if defined FSL_FEATURE_EDMA_TCD_TYPEn
#define EDMA_TCD_TYPE(x) FSL_FEATURE_EDMA_TCD_TYPEn(x)
#else
#define EDMA_TCD_TYPE(x) (0)
#endif
#if defined FSL_EDMA_SOC_IP_DMA5 && FSL_EDMA_SOC_IP_DMA5
/*!@brief EDMA TCD address convert macro */
#define EDMA_TCD_SADDR(tcd, flag) \
(*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->SADDR)) : \
(&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->SADDR))))
#define EDMA_TCD_SOFF(tcd, flag) \
(*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->SOFF)) : \
(&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->SOFF))))
#define EDMA_TCD_ATTR(tcd, flag) \
(*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->ATTR)) : \
(&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->ATTR))))
#define EDMA_TCD_NBYTES(tcd, flag) \
(*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->NBYTES)) : \
(&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->NBYTES))))
#define EDMA_TCD_SLAST(tcd, flag) \
(*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->SLAST)) : \
(&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->SLAST))))
#define EDMA_TCD_DADDR(tcd, flag) \
(*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->DADDR)) : \
(&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->DADDR))))
#define EDMA_TCD_DOFF(tcd, flag) \
(*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->DOFF)) : \
(&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->DOFF))))
#define EDMA_TCD_CITER(tcd, flag) \
(*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->CITER)) : \
(&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->CITER))))
#define EDMA_TCD_DLAST_SGA(tcd, flag) \
(*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? \
(&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->DLAST_SGA)) : \
(&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->DLAST_SGA))))
#define EDMA_TCD_CSR(tcd, flag) \
(*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->CSR)) : \
(&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->CSR))))
#define EDMA_TCD_BITER(tcd, flag) \
(*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->BITER)) : \
(&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->BITER))))
#else
/*!@brief EDMA TCD address convert macro */
#define EDMA_TCD_SADDR(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->SADDR)
#define EDMA_TCD_SOFF(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->SOFF)
#define EDMA_TCD_ATTR(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->ATTR)
#define EDMA_TCD_NBYTES(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->NBYTES)
#define EDMA_TCD_SLAST(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->SLAST)
#define EDMA_TCD_DADDR(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->DADDR)
#define EDMA_TCD_DOFF(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->DOFF)
#define EDMA_TCD_CITER(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->CITER)
#define EDMA_TCD_DLAST_SGA(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->DLAST_SGA)
#define EDMA_TCD_CSR(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->CSR)
#define EDMA_TCD_BITER(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->BITER)
#endif /* FSL_EDMA_SOC_IP_DMA5 */
/*******************************************************************************
* API
******************************************************************************/
@@ -217,4 +354,4 @@ extern "C" {
* @}
*/
#endif /* _FSL_EDMA_CORE_H_ */
#endif /* FSL_EDMA_CORE_H_ */
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_edma_soc.h
-145
View File
@@ -45,151 +45,6 @@
} \
}
/*!@brief dma request source */
typedef enum _dma_request_source
{
kDmaRequestDisabled = 0U, /**< DSisabled*/
kDmaRequestMuxFlexSpi0Rx = 1 | 0x100U, /**< FlexSPI0 Receive event */
kDmaRequestMuxFlexSpi0Tx = 2 | 0x100U, /**< FlexSPI0 Transmit event */
kDmaRequestMuxPinInt0 = 3 | 0x100U, /**< PinInt0 */
kDmaRequestMuxPinInt1 = 4 | 0x100U, /**< PinInt1 */
kDmaRequestMuxPinInt2 = 5 | 0x100U, /**< PinInt2 */
kDmaRequestMuxPinInt3 = 6 | 0x100U, /**< PinInt3 */
kDmaRequestMuxCtimer0M0 = 7 | 0x100U, /**< Ctimer0_M0 */
kDmaRequestMuxCtimer0M1 = 8 | 0x100U, /**< Ctimer0_M1 */
kDmaRequestMuxCtimer1M0 = 9 | 0x100U, /**< Ctimer1_M0 */
kDmaRequestMuxCtimer1M1 = 10 | 0x100U, /**< Ctimer1_M1 */
kDmaRequestMuxCtimer2M0 = 11 | 0x100U, /**< Ctimer2_M0 */
kDmaRequestMuxCtimer2M1 = 12 | 0x100U, /**< Ctimer2_M1 */
kDmaRequestMuxCtimer3M0 = 13 | 0x100U, /**< Ctimer3_M0 */
kDmaRequestMuxCtimer3M1 = 14 | 0x100U, /**< Ctimer3_M1 */
kDmaRequestMuxCtimer4M0 = 15 | 0x100U, /**< Ctimer4_M0 */
kDmaRequestMuxCtimer5M1 = 16 | 0x100U, /**< Ctimer4_M1 */
kDmaRequestMuxWuu0 = 17 | 0x100U, /**< Wake up event */
kDmaRequestMuxMicfil0FifoRequest = 18 | 0x100U, /**< MICFIL0 FIFO_request */
kDmaRequestMuxSct0Dma0 = 19 | 0x100U, /**< SCT0 DMA0 */
kDmaRequestMuxSct0Dma1 = 20 | 0x100U, /**< SCT0 DMA1 */
kDmaRequestMuxAdc0FifoARequest = 21 | 0x100U, /**< ADC0 FIFO A request */
kDmaRequestMuxAdc0FifoBRequest = 22 | 0x100U, /**< ADC0 FIFO B request */
kDmaRequestMuxAdc1FifoARequest = 23 | 0x100U, /**< ADC1 FIFO A request */
kDmaRequestMuxAdc1FifoBRequest = 24 | 0x100U, /**< ADC1 FIFO B request */
kDmaRequestMuxDac0FifoRequest = 25 | 0x100U, /**< DAC0 FIFO_request */
kDmaRequestMuxDac1FifoRequest = 26 | 0x100U, /**< DAC1 FIFO_request */
kDmaRequestMuxHpDac0FifoRequest = 27 | 0x100U, /**< HP DAC0 FIFO_request */
kDmaRequestMuxHsCmp0DmaRequest = 28 | 0x100U, /**< HS CMP0 DMA_request */
kDmaRequestMuxHsCmp1DmaRequest = 29 | 0x100U, /**< HS CMP0 DMA_request */
kDmaRequestMuxHsCmp2DmaRequest = 30 | 0x100U, /**< HS CMP0 DMA_request */
kDmaRequestMuxEvtg0Out0A = 31 | 0x100U, /**< EVTG0 OUT0A */
kDmaRequestMuxEvtg0Out0B = 32 | 0x100U, /**< EVTG0 OUT0B */
kDmaRequestMuxEvtg0Out1A = 33 | 0x100U, /**< EVTG0 OUT1A */
kDmaRequestMuxEvtg0Out1B = 34 | 0x100U, /**< EVTG0 OUT1B */
kDmaRequestMuxEvtg0Out2A = 35 | 0x100U, /**< EVTG0 OUT2A */
kDmaRequestMuxEvtg0Out2B = 36 | 0x100U, /**< EVTG0 OUT2B */
kDmaRequestMuxEvtg0Out3A = 37 | 0x100U, /**< EVTG0 OUT3A */
kDmaRequestMuxEvtg0Out3B = 38 | 0x100U, /**< EVTG0 OUT3B */
kDmaRequestMuxFlexPwm0ReqCapt0 = 39 | 0x100U, /**< FlexPWM0 Req_capt0 */
kDmaRequestMuxFlexPwm0ReqCapt1 = 40 | 0x100U, /**< FlexPWM0 Req_capt1 */
kDmaRequestMuxFlexPwm0ReqCapt2 = 41 | 0x100U, /**< FlexPWM0 Req_capt2 */
kDmaRequestMuxFlexPwm0ReqCapt3 = 42 | 0x100U, /**< FlexPWM0 Req_capt3 */
kDmaRequestMuxFlexPwm0ReqVal0 = 43 | 0x100U, /**< FlexPWM0 Req_val0 */
kDmaRequestMuxFlexPwm0ReqVal1 = 44 | 0x100U, /**< FlexPWM0 Req_val1 */
kDmaRequestMuxFlexPwm0ReqVal2 = 45 | 0x100U, /**< FlexPWM0 Req_val2 */
kDmaRequestMuxFlexPwm0ReqVal3 = 46 | 0x100U, /**< FlexPWM0 Req_val3 */
kDmaRequestMuxFlexPwm1ReqCapt0 = 47 | 0x100U, /**< FlexPWM1 Req_capt0 */
kDmaRequestMuxFlexPwm1ReqCapt1 = 48 | 0x100U, /**< FlexPWM1 Req_capt1 */
kDmaRequestMuxFlexPwm1ReqCapt2 = 49 | 0x100U, /**< FlexPWM1 Req_capt2 */
kDmaRequestMuxFlexPwm1ReqCapt3 = 50 | 0x100U, /**< FlexPWM1 Req_capt3 */
kDmaRequestMuxFlexPwm1ReqVal0 = 51 | 0x100U, /**< FlexPWM1 Req_val0 */
kDmaRequestMuxFlexPwm1ReqVal1 = 52 | 0x100U, /**< FlexPWM1 Req_val1 */
kDmaRequestMuxFlexPwm1ReqVal2 = 53 | 0x100U, /**< FlexPWM1 Req_val2 */
kDmaRequestMuxFlexPwm1ReqVal3 = 54 | 0x100U, /**< FlexPWM1 Req_val3 */
kDmaRequestMuxItrc0TmprOut0 = 55 | 0x100U, /**< ITRC0 TMPR_OUT0 */
kDmaRequestMuxItrc0TmprOut1 = 56 | 0x100U, /**< ITRC0 TMPR_OUT1 */
kDmaRequestMuxLptmr0 = 57 | 0x100U, /**< LPTMR0 Counter match event */
kDmaRequestMuxLptmr1 = 58 | 0x100U, /**< LPTMR1 Counter match event */
kDmaRequestMuxFlexCan0DmaRequest = 59 | 0x100U, /**< FlexCAN0 DMA request */
kDmaRequestMuxFlexCan1DmaRequest = 60 | 0x100U, /**< FlexCAN1 DMA request */
kDmaRequestMuxFlexIO0ShiftRegister0Request = 61 | 0x100U, /**< FlexIO0 Shift Register 0 request */
kDmaRequestMuxFlexIO0ShiftRegister1Request = 62 | 0x100U, /**< FlexIO0 Shift Register 1 request */
kDmaRequestMuxFlexIO0ShiftRegister2Request = 63 | 0x100U, /**< FlexIO0 Shift Register 2 request */
kDmaRequestMuxFlexIO0ShiftRegister3Request = 64 | 0x100U, /**< FlexIO0 Shift Register 3 request */
kDmaRequestMuxFlexIO0ShiftRegister4Request = 65 | 0x100U, /**< FlexIO0 Shift Register 4 request */
kDmaRequestMuxFlexIO0ShiftRegister5Request = 66 | 0x100U, /**< FlexIO0 Shift Register 5 request */
kDmaRequestMuxFlexIO0ShiftRegister6Request = 67 | 0x100U, /**< FlexIO0 Shift Register 6 request */
kDmaRequestMuxFlexIO0ShiftRegister7Request = 68 | 0x100U, /**< FlexIO0 Shift Register 7 request */
kDmaRequestMuxLpFlexcomm0Rx = 69 | 0x100U, /**< LP_FLEXCOMM0 Receive request */
kDmaRequestMuxLpFlexcomm0Tx = 70 | 0x100U, /**< LP_FLEXCOMM0 Transmit request */
kDmaRequestMuxLpFlexcomm1Rx = 71 | 0x100U, /**< LP_FLEXCOMM1 Receive request */
kDmaRequestMuxLpFlexcomm1Tx = 72 | 0x100U, /**< LP_FLEXCOMM1 Transmit request */
kDmaRequestMuxLpFlexcomm2Rx = 73 | 0x100U, /**< LP_FLEXCOMM2 Receive request */
kDmaRequestMuxLpFlexcomm2Tx = 74 | 0x100U, /**< LP_FLEXCOMM2 Transmit request */
kDmaRequestMuxLpFlexcomm3Rx = 75 | 0x100U, /**< LP_FLEXCOMM3 Receive request */
kDmaRequestMuxLpFlexcomm3Tx = 76 | 0x100U, /**< LP_FLEXCOMM3 Transmit request */
kDmaRequestMuxLpFlexcomm4Rx = 77 | 0x100U, /**< LP_FLEXCOMM4 Receive request */
kDmaRequestMuxLpFlexcomm4Tx = 78 | 0x100U, /**< LP_FLEXCOMM4 Transmit request */
kDmaRequestMuxLpFlexcomm5Rx = 79 | 0x100U, /**< LP_FLEXCOMM5 Receive request */
kDmaRequestMuxLpFlexcomm5Tx = 80 | 0x100U, /**< LP_FLEXCOMM5 Transmit request */
kDmaRequestMuxLpFlexcomm6Rx = 81 | 0x100U, /**< LP_FLEXCOMM6 Receive request */
kDmaRequestMuxLpFlexcomm6Tx = 82 | 0x100U, /**< LP_FLEXCOMM6 Transmit request */
kDmaRequestMuxLpFlexcomm7Rx = 83 | 0x100U, /**< LP_FLEXCOMM7 Receive request */
kDmaRequestMuxLpFlexcomm7Tx = 84 | 0x100U, /**< LP_FLEXCOMM7 Transmit request */
kDmaRequestMuxLpFlexcomm8Rx = 85 | 0x100U, /**< LP_FLEXCOMM8 Receive request */
kDmaRequestMuxLpFlexcomm8Tx = 86 | 0x100U, /**< LP_FLEXCOMM8 Transmit request */
kDmaRequestMuxLpFlexcomm9Rx = 87 | 0x100U, /**< LP_FLEXCOMM9 Receive request */
kDmaRequestMuxLpFlexcomm9Tx = 88 | 0x100U, /**< LP_FLEXCOMM9 Transmit request */
kDmaRequestMuxESpi0Ch0 = 89 | 0x100U, /**< eSPI0 channel 0 */
kDmaRequestMuxESpi0Ch1 = 90 | 0x100U, /**< eSPI0 channel 1 */
kDmaRequestMuxEmvSim0Rx = 91 | 0x100U, /**< EMVSIM0 Receive request */
kDmaRequestMuxEmvSim0Tx = 92 | 0x100U, /**< EMVSIM0 Transmit request */
kDmaRequestMuxEmvSim1Rx = 93 | 0x100U, /**< EMVSIM1 Receive request */
kDmaRequestMuxEmvSim1Tx = 94 | 0x100U, /**< EMVSIM1 Transmit request */
kDmaRequestMuxI3c0Rx = 95 | 0x100U, /**< I3C0 Receive request */
kDmaRequestMuxI3c0Tx = 96 | 0x100U, /**< I3C0 Transmit request */
kDmaRequestMuxI3c1Rx = 97 | 0x100U, /**< I3C0 Receive request */
kDmaRequestMuxI3c1Tx = 98 | 0x100U, /**< I3C0 Transmit request */
kDmaRequestMuxSai0Rx = 99 | 0x100U, /**< SAI0 Receive request */
kDmaRequestMuxSai0Tx = 100 | 0x100U, /**< SAI0 Receive request */
kDmaRequestMuxSai1Rx = 101 | 0x100U, /**< SAI1 Receive request */
kDmaRequestMuxSai1Tx = 102 | 0x100U, /**< SAI1 Receive request */
kDmaRequestMuxSinc0IpdReqSincAlt0 = 103 | 0x100U, /**< SINC0 ipd_req_sinc[0] or ipd_req_alt [0] */
kDmaRequestMuxSinc0IpdReqSincAlt1 = 104 | 0x100U, /**< SINC0 ipd_req_sinc[1] or ipd_req_alt [1] */
kDmaRequestMuxSinc0IpdReqSincAlt2 = 105 | 0x100U, /**< SINC0 ipd_req_sinc[2] or ipd_req_alt [2] */
kDmaRequestMuxSinc0IpdReqSincAlt3 = 106 | 0x100U, /**< SINC0 ipd_req_sinc[3] or ipd_req_alt [3] */
kDmaRequestMuxSinc0IpdReqSincAlt4 = 107 | 0x100U, /**< SINC0 ipd_req_sinc[4] or ipd_req_alt [4] */
kDmaRequestMuxGpio0PinEventRequest0 = 108 | 0x100U, /**< GPIO0 Pin event request 0 */
kDmaRequestMuxGpio0PinEventRequest1 = 109 | 0x100U, /**< GPIO0 Pin event request 1 */
kDmaRequestMuxGpio1PinEventRequest0 = 110 | 0x100U, /**< GPIO1 Pin event request 0 */
kDmaRequestMuxGpio1PinEventRequest1 = 111 | 0x100U, /**< GPIO1 Pin event request 1 */
kDmaRequestMuxGpio2PinEventRequest0 = 112 | 0x100U, /**< GPIO2 Pin event request 0 */
kDmaRequestMuxGpio2PinEventRequest1 = 113 | 0x100U, /**< GPIO2 Pin event request 1 */
kDmaRequestMuxGpio3PinEventRequest0 = 114 | 0x100U, /**< GPIO3 Pin event request 0 */
kDmaRequestMuxGpio3PinEventRequest1 = 115 | 0x100U, /**< GPIO3 Pin event request 1 */
kDmaRequestMuxGpio4PinEventRequest0 = 116 | 0x100U, /**< GPIO4 Pin event request 0 */
kDmaRequestMuxGpio4PinEventRequest1 = 117 | 0x100U, /**< GPIO4 Pin event request 1 */
kDmaRequestMuxGpio5PinEventRequest0 = 118 | 0x100U, /**< GPIO5 Pin event request 0 */
kDmaRequestMuxGpio5PinEventRequest1 = 119 | 0x100U, /**< GPIO5 Pin event request 1 */
kDmaRequestMuxTsi0EndOfScan = 120 | 0x100U, /**< TSI0 End of Scan */
kDmaRequestMuxTsi0OutOfRange = 121 | 0x100U, /**< TSI0 Out of Range */
} dma_request_source_t;
/*!< Verify dma base and request source */
#define EDMA_CHANNEL_HAS_REQUEST_SOURCE(base, source) ((source)&0x100U)
#define FSL_FEATURE_EDMA_MODULE_CHANNEL(base) (16U)
#define FSL_FEATURE_EDMA_MODULE_MAX_CHANNEL (16)
#define FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION (1)
#define FSL_FEATURE_EDMA_HAS_CONTINUOUS_LINK_MODE (0)
#define FSL_FEATURE_EDMA_MODULE_COUNT (2)
#define FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG (1)
#define FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE (0)
#define FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE (0)
#define FSL_FEATURE_EDMA_HAS_CHANNEL_MEMRORY_ATTRIBUTE (0)
#define FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION (0)
#define FSL_FEATURE_EDMA_MODULE_SUPPORT_MATTR(base) (0U)
#define FSL_FEATURE_EDMA_MODULE_SUPPORT_SIGN_EXTENSION(base) (0U)
#define FSL_FEATURE_EDMA_MODULE_SUPPORT_SWAP(base) (0U)
#define FSL_FEATURE_EDMA_MODULE_SUPPORT_INSTR(base) (0U)
/*!@brief EDMA base address convert macro */
#define EDMA_CHANNEL_OFFSET 0x1000U
#define EDMA_CHANNEL_ARRAY_STEP(base) (0x1000U)
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_eim.c
+98 -68
View File
@@ -82,44 +82,52 @@ void EIM_Deinit(EIM_Type *base)
void EIM_InjectCheckBitError(EIM_Type *base, eim_memory_channel_t channel, uint8_t mask)
{
switch (channel)
switch ((uint8_t)channel)
{
case kEIM_MemoryChannelRAMX:
case 0U:
base->EICHD0_WORD0 = EIM_EICHD0_WORD0_CHKBIT_MASK(mask);
break;
case kEIM_MemoryChannelRAMA:
#ifdef EIM_EICHEN_EICH1EN_MASK
case 1U:
base->EICHD1_WORD0 = EIM_EICHD1_WORD0_CHKBIT_MASK(mask);
break;
#endif
case kEIM_MemoryChannelRAMB:
#ifdef EIM_EICHEN_EICH2EN_MASK
case 2U:
base->EICHD2_WORD0 = EIM_EICHD2_WORD0_CHKBIT_MASK(mask);
break;
case kEIM_MemoryChannelRAMC:
#endif
#ifdef EIM_EICHEN_EICH3EN_MASK
case 3U:
base->EICHD3_WORD0 = EIM_EICHD3_WORD0_CHKBIT_MASK(mask);
break;
case kEIM_MemoryChannelRAMD:
#endif
#ifdef EIM_EICHEN_EICH4EN_MASK
case 4U:
base->EICHD4_WORD0 = EIM_EICHD4_WORD0_CHKBIT_MASK(mask);
break;
case kEIM_MemoryChannelRAME:
#endif
#ifdef EIM_EICHEN_EICH5EN_MASK
case 5U:
base->EICHD5_WORD0 = EIM_EICHD5_WORD0_CHKBIT_MASK(mask);
break;
case kEIM_MemoryChannelRAMF:
#endif
#ifdef EIM_EICHEN_EICH6EN_MASK
case 6U:
base->EICHD6_WORD0 = EIM_EICHD6_WORD0_CHKBIT_MASK(mask);
break;
case kEIM_MemoryChannelLPCACRAM:
#endif
#ifdef EIM_EICHEN_EICH7EN_MASK
case 7U:
base->EICHD7_WORD0 = EIM_EICHD7_WORD0_CHKBIT_MASK(mask);
break;
case kEIM_MemoryChannelPKCRAM:
#endif
#ifdef EIM_EICHEN_EICH8EN_MASK
case 8U:
base->EICHD8_WORD0 = EIM_EICHD8_WORD0_CHKBIT_MASK(mask);
break;
#endif
default:
assert(NULL);
break;
@@ -130,53 +138,60 @@ uint8_t EIM_GetCheckBitMask(EIM_Type *base, eim_memory_channel_t channel)
{
uint8_t mask = 0x00U;
switch (channel)
switch ((uint8_t)channel)
{
case kEIM_MemoryChannelRAMX:
case 0U:
mask = (uint8_t)((base->EICHD0_WORD0 & EIM_EICHD0_WORD0_CHKBIT_MASK_MASK) >>
EIM_EICHD0_WORD0_CHKBIT_MASK_SHIFT);
break;
case kEIM_MemoryChannelRAMA:
#ifdef EIM_EICHEN_EICH1EN_MASK
case 1U:
mask = (uint8_t)((base->EICHD1_WORD0 & EIM_EICHD1_WORD0_CHKBIT_MASK_MASK) >>
EIM_EICHD1_WORD0_CHKBIT_MASK_SHIFT);
break;
case kEIM_MemoryChannelRAMB:
#endif
#ifdef EIM_EICHEN_EICH2EN_MASK
case 2U:
mask = (uint8_t)((base->EICHD2_WORD0 & EIM_EICHD2_WORD0_CHKBIT_MASK_MASK) >>
EIM_EICHD2_WORD0_CHKBIT_MASK_SHIFT);
break;
case kEIM_MemoryChannelRAMC:
#endif
#ifdef EIM_EICHEN_EICH3EN_MASK
case 3U:
mask = (uint8_t)((base->EICHD3_WORD0 & EIM_EICHD3_WORD0_CHKBIT_MASK_MASK) >>
EIM_EICHD3_WORD0_CHKBIT_MASK_SHIFT);
break;
case kEIM_MemoryChannelRAMD:
#endif
#ifdef EIM_EICHEN_EICH4EN_MASK
case 4U:
mask = (uint8_t)((base->EICHD4_WORD0 & EIM_EICHD4_WORD0_CHKBIT_MASK_MASK) >>
EIM_EICHD4_WORD0_CHKBIT_MASK_SHIFT);
break;
case kEIM_MemoryChannelRAME:
#endif
#ifdef EIM_EICHEN_EICH5EN_MASK
case 5U:
mask = (uint8_t)((base->EICHD5_WORD0 & EIM_EICHD5_WORD0_CHKBIT_MASK_MASK) >>
EIM_EICHD5_WORD0_CHKBIT_MASK_SHIFT);
break;
case kEIM_MemoryChannelRAMF:
#endif
#ifdef EIM_EICHEN_EICH6EN_MASK
case 6U:
mask = (uint8_t)((base->EICHD6_WORD0 & EIM_EICHD6_WORD0_CHKBIT_MASK_MASK) >>
EIM_EICHD6_WORD0_CHKBIT_MASK_SHIFT);
break;
case kEIM_MemoryChannelLPCACRAM:
#endif
#ifdef EIM_EICHEN_EICH7EN_MASK
case 7U:
mask = (uint8_t)((base->EICHD7_WORD0 & EIM_EICHD7_WORD0_CHKBIT_MASK_MASK) >>
EIM_EICHD7_WORD0_CHKBIT_MASK_SHIFT);
break;
case kEIM_MemoryChannelPKCRAM:
#endif
#ifdef EIM_EICHEN_EICH8EN_MASK
case 8U:
mask = (uint8_t)((base->EICHD8_WORD0 & EIM_EICHD8_WORD0_CHKBIT_MASK_MASK) >>
EIM_EICHD8_WORD0_CHKBIT_MASK_SHIFT);
break;
#endif
default:
assert(NULL);
break;
@@ -187,44 +202,51 @@ uint8_t EIM_GetCheckBitMask(EIM_Type *base, eim_memory_channel_t channel)
void EIM_InjectDataBitError(EIM_Type *base, eim_memory_channel_t channel, uint8_t mask)
{
switch (channel)
switch ((uint8_t)channel)
{
case kEIM_MemoryChannelRAMX:
case 0U:
base->EICHD0_WORD1 = mask;
break;
case kEIM_MemoryChannelRAMA:
#ifdef EIM_EICHEN_EICH1EN_MASK
case 1U:
base->EICHD1_WORD1 = mask;
break;
case kEIM_MemoryChannelRAMB:
#endif
#ifdef EIM_EICHEN_EICH2EN_MASK
case 2U:
base->EICHD2_WORD1 = mask;
break;
#endif
#ifdef EIM_EICHEN_EICH3EN_MASK
case kEIM_MemoryChannelRAMC:
base->EICHD3_WORD1 = mask;
break;
#endif
#ifdef EIM_EICHEN_EICH4EN_MASK
case kEIM_MemoryChannelRAMD:
base->EICHD4_WORD1 = mask;
break;
#endif
#ifdef EIM_EICHEN_EICH5EN_MASK
case kEIM_MemoryChannelRAME:
base->EICHD5_WORD1 = mask;
break;
#endif
#ifdef EIM_EICHEN_EICH6EN_MASK
case kEIM_MemoryChannelRAMF:
base->EICHD6_WORD1 = mask;
break;
#endif
#ifdef EIM_EICHEN_EICH7EN_MASK
case kEIM_MemoryChannelLPCACRAM:
base->EICHD7_WORD1 = mask;
break;
#endif
#ifdef EIM_EICHEN_EICH8EN_MASK
case kEIM_MemoryChannelPKCRAM:
base->EICHD8_WORD1 = mask;
break;
#endif
default:
assert(NULL);
break;
@@ -235,44 +257,52 @@ uint32_t EIM_GetDataBitMask(EIM_Type *base, eim_memory_channel_t channel)
{
uint32_t mask = 0x00U;
switch (channel)
switch ((uint8_t)channel)
{
case kEIM_MemoryChannelRAMX:
case 0U:
mask = (base->EICHD0_WORD0 & EIM_EICHD0_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT;
break;
case kEIM_MemoryChannelRAMA:
#ifdef EIM_EICHEN_EICH1EN_MASK
case 1U:
mask = (base->EICHD1_WORD0 & EIM_EICHD1_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD1_WORD1_B0_3DATA_MASK_SHIFT;
break;
case kEIM_MemoryChannelRAMB:
#endif
#ifdef EIM_EICHEN_EICH2EN_MASK
case 2U:
mask = (base->EICHD2_WORD0 & EIM_EICHD2_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD2_WORD1_B0_3DATA_MASK_SHIFT;
break;
case kEIM_MemoryChannelRAMC:
#endif
#ifdef EIM_EICHEN_EICH3EN_MASK
case 3U:
mask = (base->EICHD3_WORD0 & EIM_EICHD3_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD3_WORD1_B0_3DATA_MASK_SHIFT;
break;
case kEIM_MemoryChannelRAMD:
#endif
#ifdef EIM_EICHEN_EICH4EN_MASK
case 4U:
mask = (base->EICHD4_WORD0 & EIM_EICHD4_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD4_WORD1_B0_3DATA_MASK_SHIFT;
break;
case kEIM_MemoryChannelRAME:
#endif
#ifdef EIM_EICHEN_EICH5EN_MASK
case 5U:
mask = (base->EICHD5_WORD0 & EIM_EICHD5_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD5_WORD1_B0_3DATA_MASK_SHIFT;
break;
case kEIM_MemoryChannelRAMF:
#endif
#ifdef EIM_EICHEN_EICH6EN_MASK
case 6U:
mask = (base->EICHD6_WORD0 & EIM_EICHD6_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD6_WORD1_B0_3DATA_MASK_SHIFT;
break;
case kEIM_MemoryChannelLPCACRAM:
#endif
#ifdef EIM_EICHEN_EICH7EN_MASK
case 7U:
mask = (base->EICHD7_WORD0 & EIM_EICHD7_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD7_WORD1_B0_3DATA_MASK_SHIFT;
break;
case kEIM_MemoryChannelPKCRAM:
#endif
#ifdef EIM_EICHEN_EICH8EN_MASK
case 8U:
mask = (base->EICHD8_WORD1 & EIM_EICHD8_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD8_WORD1_B0_3DATA_MASK_SHIFT;
break;
#endif
default:
assert(NULL);
break;
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_eim.h
+6 -6
View File
@@ -6,8 +6,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_EIM_H_
#define _FSL_EIM_H_
#ifndef FSL_EIM_H_
#define FSL_EIM_H_
#include "fsl_common.h"
@@ -21,10 +21,10 @@
*****************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @{ */
/*! @brief Driver version. */
#define FSL_ERM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 0U))
/*@}*/
#define FSL_ERM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 1U))
/*! @} */
/*******************************************************************************
* APIs
@@ -47,7 +47,7 @@ void EIM_Init(EIM_Type *base);
*/
void EIM_Deinit(EIM_Type *base);
/* @} */
/*! @} */
/*!
* @name functional
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_enc.c
-625
View File
File diff suppressed because it is too large Load Diff
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_enet.c
+261 -30
View File
@@ -1,9 +1,10 @@
/*
* Copyright 2022 NXP
* Copyright 2022-2024 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <math.h>
#include "fsl_enet.h"
/*******************************************************************************
@@ -41,7 +42,7 @@
#define ENET_HEAD_AVBTYPE_OFFSET (16)
/*! @brief Binary rollover mode count convert */
#define ENET_BINARY_ROLLOVER_SCALE(x) (uint32_t)((uint64_t)(x)*46566U / 100000U)
#define ENET_BINARY_ROLLOVER_SCALE(x) (uint32_t)((uint64_t)(x) * 46566U / 100000U)
/*******************************************************************************
* Prototypes
@@ -302,7 +303,8 @@ static void ENET_SetMacControl(ENET_Type *base, const enet_config_t *config, uin
/* Set the speed and duplex. */
reg = ENET_MAC_CONFIGURATION_ECRSFD_MASK | ENET_MAC_CONFIGURATION_PS_MASK |
ENET_MAC_CONFIGURATION_DM(config->miiDuplex) | ENET_MAC_CONFIGURATION_FES(config->miiSpeed) |
ENET_MAC_CONFIGURATION_S2KP(!((config->specialControl & (uint16_t)kENET_8023AS2KPacket) == 0U));
ENET_MAC_CONFIGURATION_S2KP((config->specialControl & (uint16_t)kENET_8023AS2KPacket) != 0U) |
ENET_MAC_CONFIGURATION_IPC((config->specialControl & (uint16_t)kENET_RxChecksumOffloadEnable) != 0U);
if (config->miiDuplex == kENET_MiiHalfDuplex)
{
reg |= ENET_MAC_CONFIGURATION_IPG(ENET_HALFDUPLEX_DEFAULTIPG);
@@ -751,7 +753,7 @@ void ENET_EnableInterrupts(ENET_Type *base, uint32_t mask)
base->DMA_CH[index].DMA_CHX_INT_EN = interrupt;
}
}
interrupt = interrupt >> ENET_MACINT_ENUM_OFFSET;
interrupt = mask >> ENET_MACINT_ENUM_OFFSET;
if (interrupt != 0U)
{
/* MAC interrupt */
@@ -829,7 +831,7 @@ void ENET_DisableInterrupts(ENET_Type *base, uint32_t mask)
base->DMA_CH[index].DMA_CHX_INT_EN &= ~interrupt;
}
}
interrupt = interrupt >> ENET_MACINT_ENUM_OFFSET;
interrupt = mask >> ENET_MACINT_ENUM_OFFSET;
if (interrupt != 0U)
{
/* MAC interrupt */
@@ -867,6 +869,8 @@ void ENET_CreateHandler(ENET_Type *base,
uint8_t count = 0;
uint8_t rxIntEnable = 0;
enet_buffer_config_t *buffConfig = bufferConfig;
uint32_t txFifoSize;
uint32_t pbl;
/* Store transfer parameters in handle pointer. */
(void)memset(handle, 0, sizeof(enet_handle_t));
@@ -901,10 +905,24 @@ void ENET_CreateHandler(ENET_Type *base,
/* Check if the Rx interrrupt is enabled. */
rxIntEnable |= (uint8_t)(uint32_t)(base->DMA_CH[count].DMA_CHX_INT_EN & ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK);
/* Calculate the reserved space for Tx in certain cases. */
if (0U != (base->MTL_QUEUE[count].MTL_TXQX_OP_MODE & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_MASK))
{
pbl = (base->DMA_CH[count].DMA_CHX_TX_CTRL & ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_MASK) >>
ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_SHIFT;
pbl = ((base->DMA_CH[count].DMA_CHX_CTRL & ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_MASK) != 0U) ? (8U * pbl) : pbl;
txFifoSize = (uint32_t)pow((double)2,
(double)(uint32_t)(((base->MAC_HW_FEAT[1] & ENET_MAC_HW_FEAT_TXFIFOSIZE_MASK) >>
ENET_MAC_HW_FEAT_TXFIFOSIZE_SHIFT) +
7U));
handle->txLenLimitation[count] = txFifoSize - (pbl + 6U) * (32U / 8U);
}
buffConfig++;
}
handle->rxintEnable = (rxIntEnable != 0U) ? true : false;
handle->rxintEnable = (rxIntEnable != 0U);
/* Save the handle pointer in the global variables. */
s_ENETHandle[ENET_GetInstance(base)] = handle;
@@ -1135,6 +1153,127 @@ void ENET_EnterPowerDown(ENET_Type *base, uint32_t *wakeFilter)
base->MAC_CONFIGURATION |= ENET_MAC_CONFIGURATION_RE_MASK;
}
/*!
* brief Set VLAN control.
*
* param base ENET peripheral base address.
* param control VLAN control configuration.
*/
status_t ENET_SetVlanCtrl(ENET_Type *base, enet_vlan_ctrl_t *control)
{
uint32_t vl = (((uint32_t)control->rxVlanTag.pcp) << 13U) | (((uint32_t)control->rxVlanTag.dei) << 12U) |
(uint32_t)control->rxVlanTag.vid;
uint32_t vlanCtrl;
if ((control->innerVlanFilterMatch) && (!control->doubleVlanEnable))
{
return kStatus_Fail;
}
vlanCtrl = ENET_MAC_VLAN_TAG_CTRL_VL(vl) | ENET_MAC_VLAN_TAG_CTRL_ETV(control->vidComparison) |
ENET_MAC_VLAN_TAG_CTRL_VTIM(control->vlanInverseMatch) |
ENET_MAC_VLAN_TAG_CTRL_ESVL(control->svlanEnable) |
ENET_MAC_VLAN_TAG_CTRL_DOVLTC(control->disableVlanTypeCheck) |
ENET_MAC_VLAN_TAG_CTRL_EVLS(control->rxOuterVlanStrip) |
ENET_MAC_VLAN_TAG_CTRL_EIVLS(control->rxInnerVlanStrip) |
ENET_MAC_VLAN_TAG_CTRL_EDVLP(control->doubleVlanEnable) |
ENET_MAC_VLAN_TAG_CTRL_ERIVLT(control->innerVlanFilterMatch) |
ENET_MAC_VLAN_TAG_CTRL_EVLRXS(control->outerTagInRxStatus) |
ENET_MAC_VLAN_TAG_CTRL_EIVLRXS(control->innerTagInRxStatus);
if (control->rxVlanTag.tpid == kENET_StanSvlan)
{
vlanCtrl |= ENET_MAC_VLAN_TAG_CTRL_ERSVLM_MASK;
}
base->MAC_VLAN_TAG_CTRL = vlanCtrl;
return kStatus_Success;
}
/*!
* brief Set Tx outer VLAN configuration.
*
* param base ENET peripheral base address.
* param config Tx VLAN operation configuration.
* param channel The channel to apply this configuration.
*/
status_t ENET_SetTxOuterVlan(ENET_Type *base, enet_vlan_tx_config_t *config, enet_vlan_tx_channel_t channel)
{
uint32_t vlt =
(((uint32_t)config->tag.pcp) << 13U) | (((uint32_t)config->tag.dei) << 12U) | (uint32_t)config->tag.vid;
uint32_t vlanConfig = ENET_MAC_VLAN_INCL_VLTI(config->txDescVlan) | ENET_MAC_VLAN_INCL_CSVL(config->tag.tpid) |
ENET_MAC_VLAN_INCL_VLC(config->ops) | ENET_MAC_VLAN_INCL_VLT(vlt);
if ((config->tag.tpid == kENET_StanSvlan) && ((base->MAC_VLAN_TAG_CTRL & ENET_MAC_VLAN_TAG_CTRL_ESVL_MASK) == 0U))
{
return kStatus_Fail;
}
if (config->ops != kENET_NoOps)
{
vlanConfig |= ENET_MAC_VLAN_INCL_VLP(1);
}
if (channel != kENET_VlanTagAllChannels)
{
while ((base->MAC_VLAN_INCL & ENET_MAC_VLAN_INCL_BUSY_MASK) != 0U)
{
}
/* Clear and status ans reset the power down. */
base->MAC_VLAN_INCL |=
ENET_MAC_VLAN_INCL_CBTI_MASK | ENET_MAC_VLAN_INCL_RDWR_MASK | ENET_MAC_VLAN_INCL_ADDR(channel) | vlanConfig;
while ((base->MAC_VLAN_INCL & ENET_MAC_VLAN_INCL_BUSY_MASK) != 0U)
{
}
/* Clear set channel bits. */
base->MAC_VLAN_INCL &= ~(ENET_MAC_VLAN_INCL_RDWR_MASK | ENET_MAC_VLAN_INCL_CBTI_MASK);
}
else
{
base->MAC_VLAN_INCL = vlanConfig;
}
return kStatus_Success;
}
/*!
* brief Set Tx inner VLAN configuration.
*
* param base ENET peripheral base address.
* param config Tx VLAN operation configuration.
*/
status_t ENET_SetTxInnerVlan(ENET_Type *base, enet_vlan_tx_config_t *config)
{
uint32_t vlt =
(((uint32_t)config->tag.pcp) << 13U) | (((uint32_t)config->tag.dei) << 12U) | (uint32_t)config->tag.vid;
uint32_t vlanConfig = ENET_MAC_INNER_VLAN_INCL_VLTI(config->txDescVlan) |
ENET_MAC_INNER_VLAN_INCL_CSVL(config->tag.tpid) | ENET_MAC_INNER_VLAN_INCL_VLC(config->ops) |
ENET_MAC_INNER_VLAN_INCL_VLT(vlt);
/* S-VLAN should be enabled first. */
if ((config->tag.tpid == kENET_StanSvlan) && ((base->MAC_VLAN_TAG_CTRL & ENET_MAC_VLAN_TAG_CTRL_ESVL_MASK) == 0U))
{
return kStatus_Fail;
}
/* Double VLAN should be enabled first for inner VLAN. */
if ((base->MAC_VLAN_TAG_CTRL & ENET_MAC_VLAN_TAG_CTRL_EDVLP_MASK) == 0U)
{
return kStatus_Fail;
}
if (config->ops != kENET_NoOps)
{
vlanConfig |= ENET_MAC_INNER_VLAN_INCL_VLP(1);
}
base->MAC_INNER_VLAN_INCL = vlanConfig;
return kStatus_Success;
}
/*!
* brief Gets the size of the read frame.
* This function gets a received frame size from the ENET buffer descriptors.
@@ -1551,7 +1690,6 @@ void ENET_RxBufferFreeAll(ENET_Type *base, enet_handle_t *handle)
static inline void ENET_GetRxFrameErr(enet_rx_bd_struct_t *rxDesc, enet_rx_frame_error_t *rxFrameError)
{
uint32_t rdes3 = rxDesc->rdes3;
union _frame_error
{
uint32_t data;
@@ -1559,9 +1697,8 @@ static inline void ENET_GetRxFrameErr(enet_rx_bd_struct_t *rxDesc, enet_rx_frame
};
union _frame_error error;
(void)memset((void *)&error.frameError, 0, sizeof(enet_rx_frame_error_t));
error.data = ENET_FRAME_RX_ERROR_BITS(rdes3);
error.data = ENET_FRAME_RX_ERROR_BITS(rxDesc->rdes3);
*rxFrameError = error.frameError;
}
static void ENET_DropFrame(ENET_Type *base, enet_handle_t *handle, uint8_t channel)
@@ -1573,23 +1710,29 @@ static void ENET_DropFrame(ENET_Type *base, enet_handle_t *handle, uint8_t chann
bool tsAvailable = false;
uint32_t buff1Addr = 0;
uint32_t buff2Addr = 0;
uint32_t rdes1;
#endif /* ENET_PTP1588FEATURE_REQUIRED */
uint32_t rdes3;
/* Not check DMA ownership here, assume there's at least one valid frame left in BD ring */
do
{
/* Update the BD to idle status. */
rxDesc = &rxBdRing->rxBdBase[rxBdRing->rxGenIdx];
#ifdef ENET_PTP1588FEATURE_REQUIRED
rdes1 = rxDesc->rdes1;
#endif
rdes3 = rxDesc->rdes3;
ENET_UpdateRxDescriptor(rxDesc, NULL, NULL, handle->rxintEnable, handle->doubleBuffEnable);
rxBdRing->rxGenIdx = ENET_IncreaseIndex(rxBdRing->rxGenIdx, rxBdRing->rxRingLen);
/* Find the last buffer descriptor for the frame. */
if ((rxDesc->rdes3 & ENET_RXDESCRIP_WR_LD_MASK) != 0U)
if ((rdes3 & ENET_RXDESCRIP_WR_LD_MASK) != 0U)
{
#ifdef ENET_PTP1588FEATURE_REQUIRED
if ((rxDesc->rdes3 & ENET_RXDESCRIP_WR_RS1V_MASK) != 0U)
if ((rdes3 & ENET_RXDESCRIP_WR_RS1V_MASK) != 0U)
{
if ((rxDesc->rdes1 & ENET_RXDESCRIP_WR_PTPTSA_MASK) != 0U)
if ((rdes1 & ENET_RXDESCRIP_WR_PTPTSA_MASK) != 0U)
{
tsAvailable = true;
}
@@ -1631,10 +1774,7 @@ static void ENET_DropFrame(ENET_Type *base, enet_handle_t *handle, uint8_t chann
* this function, driver will allocate new buffers for the BDs whose buffers have been taken by application.
* note This function will drop current frame and update related BDs as available for DMA if new buffers allocating
* fails. Application must provide a memory pool including at least BD number + 1 buffers(+2 if enable double buffer)
* to make this function work normally. If user calls this function in Rx interrupt handler, be careful that this
* function makes Rx BD ready with allocating new buffer(normal) or updating current BD(out of memory). If there's
* always new Rx frame input, Rx interrupt will be triggered forever. Application need to disable Rx interrupt according
* to specific design in this case.
* to make this function work normally.
*
* param base ENET peripheral base address.
* param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init.
@@ -1739,17 +1879,16 @@ status_t ENET_GetRxFrame(ENET_Type *base, enet_handle_t *handle, enet_rx_frame_s
if (rxFrame->totLen - offset > (uint16_t)rxBdRing->rxBuffSizeAlign)
{
/* Here must be double buffer. */
assert(handle->doubleBuffEnable);
buff1Len = (uint16_t)rxBdRing->rxBuffSizeAlign;
if (handle->doubleBuffEnable)
{
buff2Len = rxFrame->totLen - offset - (uint16_t)rxBdRing->rxBuffSizeAlign - ENET_FCS_LEN;
}
buff2Len = rxFrame->totLen - offset - (uint16_t)rxBdRing->rxBuffSizeAlign;
}
else
{
buff1Len = rxFrame->totLen - offset - ENET_FCS_LEN;
buff1Len = rxFrame->totLen - offset;
}
rxFrame->totLen -= ENET_FCS_LEN;
}
else
{
@@ -1896,7 +2035,7 @@ status_t ENET_GetRxFrame(ENET_Type *base, enet_handle_t *handle, enet_rx_frame_s
/* Free the incomplete frame buffers. */
while (index-- != 0U)
{
handle->rxBuffFree(base, &rxFrame->rxBuffArray[index].buffer, handle->userData, channel);
handle->rxBuffFree(base, rxFrame->rxBuffArray[index].buffer, handle->userData, channel);
}
/* Update all left BDs of this frame from current index. */
@@ -1907,6 +2046,27 @@ status_t ENET_GetRxFrame(ENET_Type *base, enet_handle_t *handle, enet_rx_frame_s
}
} while (!isLastBuff);
/* Remove 4 bytes FCS. */
if (result == kStatus_Success)
{
/* Find the last 4 bytes in the linked buffers and remove these FCS data. */
buff1Len = rxFrame->rxBuffArray[--index].length;
if (buff1Len > ENET_FCS_LEN)
{
rxFrame->rxBuffArray[index].length -= ENET_FCS_LEN;
}
else
{
rxFrame->rxBuffArray[index].length = 0;
handle->rxBuffFree(base, rxFrame->rxBuffArray[index].buffer, handle->userData, channel);
if (buff1Len < ENET_FCS_LEN)
{
rxFrame->rxBuffArray[--index].length -= (ENET_FCS_LEN - buff1Len);
}
}
rxFrame->totLen -= ENET_FCS_LEN;
}
return result;
}
@@ -1977,6 +2137,58 @@ void ENET_SetupTxDescriptor(enet_tx_bd_struct_t *txDesc,
txDesc->tdes3 = control;
}
/*!
* brief Configure a given Tx descriptor.
* This function is a low level functional API to setup or prepare
* a given Tx descriptor.
*
* param txDesc The given Tx descriptor.
* param config The Tx descriptor configuration.
*
* note This must be called after all the ENET initilization.
* And should be called when the ENET receive/transmit is required.
* Transmit buffers are 'zero-copy' buffers, so the buffer must remain in
* memory until the packet has been fully transmitted. The buffers
* should be free or requeued in the transmit interrupt irq handler.
*/
static void ENET_ConfigTxDescriptor(enet_tx_bd_struct_t *txDesc, enet_tx_bd_config_struct_t *config)
{
uint32_t control = ENET_TXDESCRIP_RD_BL1(config->bytes1) | ENET_TXDESCRIP_RD_BL2(config->bytes2);
enet_tx_offload_t txOffloadMode = kENET_TxOffloadDisable;
if ((config->flag == kENET_FirstFlagOnly) || (config->flag == kENET_FirstLastFlag))
{
if (config->tsEnable)
{
control |= ENET_TXDESCRIP_RD_TTSE_MASK;
}
else
{
control &= ~ENET_TXDESCRIP_RD_TTSE_MASK;
}
txOffloadMode = config->txOffloadOps;
}
if (config->intEnable)
{
control |= ENET_TXDESCRIP_RD_IOC_MASK;
}
else
{
control &= ~ENET_TXDESCRIP_RD_IOC_MASK;
}
/* Preare the descriptor for transmit. */
txDesc->tdes0 = (uint32_t)(uint32_t *)config->buffer1;
txDesc->tdes1 = (uint32_t)(uint32_t *)config->buffer2;
txDesc->tdes2 = control;
control = ENET_TXDESCRIP_RD_SLOT(config->slotNum) | ENET_TXDESCRIP_RD_FL(config->framelen) |
ENET_TXDESCRIP_RD_CIC(txOffloadMode) | ENET_TXDESCRIP_RD_LDFD(config->flag) | ENET_TXDESCRIP_RD_OWN_MASK;
txDesc->tdes3 = control;
}
/*!
* brief Reclaim Tx descriptors.
* This function is used to update the Tx descriptor status and
@@ -2090,6 +2302,15 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, enet_tx_frame_st
return kStatus_ENET_TxFrameOverLen;
}
/* Check Tx FIFO whether can store enough frame data. */
if (0U != handle->txLenLimitation[channel])
{
if (frameLen > handle->txLenLimitation[channel])
{
return kStatus_ENET_TxFrameOverLen;
}
}
/* Check whether the available BD number is enough for Tx data buffer. */
if (txFrame->txBuffNum > (((uint32_t)txBdRing->txRingLen - (uint32_t)txBdRing->txDescUsed) * 2U))
{
@@ -2116,22 +2337,32 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, enet_tx_frame_st
descFlag = (leftBuffNum > 2U) ? kENET_MiddleFlag : kENET_LastFlagOnly;
}
enet_tx_bd_config_struct_t txDescConfig = {0};
txDescConfig.framelen = frameLen;
txDescConfig.intEnable = (bool)txFrame->txConfig.intEnable;
txDescConfig.tsEnable = (bool)txFrame->txConfig.tsEnable;
txDescConfig.txOffloadOps = txFrame->txConfig.txOffloadOps;
txDescConfig.flag = descFlag;
txDescConfig.slotNum = txFrame->txConfig.slotNum;
/* Fill the descriptor. */
txDescConfig.buffer1 = txBuff[index].buffer;
txDescConfig.bytes1 = txBuff[index].length;
if (leftBuffNum < 2U)
{
ENET_SetupTxDescriptor(txDesc, txBuff[index].buffer, txBuff[index].length, NULL, 0, frameLen,
(bool)txFrame->txConfig.intEnable, (bool)txFrame->txConfig.tsEnable, descFlag,
txFrame->txConfig.slotNum);
txDescConfig.buffer2 = NULL;
txDescConfig.bytes2 = 0;
leftBuffNum--;
}
else
{
ENET_SetupTxDescriptor(txDesc, txBuff[index].buffer, txBuff[index].length, txBuff[index + 1U].buffer,
txBuff[index + 1U].length, frameLen, (bool)txFrame->txConfig.intEnable,
(bool)txFrame->txConfig.tsEnable, descFlag, txFrame->txConfig.slotNum);
txDescConfig.buffer2 = txBuff[index + 1U].buffer;
txDescConfig.bytes2 = txBuff[index + 1U].length;
index += 2U;
leftBuffNum -= 2U;
}
ENET_ConfigTxDescriptor(txDesc, &txDescConfig);
/* Increase the index. */
txBdRing->txGenIdx = ENET_IncreaseIndex(txBdRing->txGenIdx, txBdRing->txRingLen);
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_enet.h
+141 -26
View File
@@ -1,10 +1,10 @@
/*
* Copyright 2022 NXP
* Copyright 2022-2024 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_ENET_H_
#define _FSL_ENET_H_
#ifndef FSL_ENET_H_
#define FSL_ENET_H_
#include "fsl_common.h"
@@ -20,7 +20,7 @@
/*! @name Driver version */
/*@{*/
/*! @brief Defines the driver version. */
#define FSL_ENET_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
#define FSL_ENET_DRIVER_VERSION (MAKE_VERSION(2, 1, 3))
/*@}*/
/*! @name Control and status region bit masks of the receive buffer descriptor. */
@@ -58,19 +58,19 @@
/*! @brief Defines for read format. */
#define ENET_TXDESCRIP_RD_BL1_MASK (0x3fffU)
#define ENET_TXDESCRIP_RD_BL2_MASK (ENET_TXDESCRIP_RD_BL1_MASK << 16)
#define ENET_TXDESCRIP_RD_BL1(n) ((uint32_t)(n)&ENET_TXDESCRIP_RD_BL1_MASK)
#define ENET_TXDESCRIP_RD_BL2(n) (((uint32_t)(n)&ENET_TXDESCRIP_RD_BL1_MASK) << 16)
#define ENET_TXDESCRIP_RD_BL1(n) ((uint32_t)(n) & ENET_TXDESCRIP_RD_BL1_MASK)
#define ENET_TXDESCRIP_RD_BL2(n) (((uint32_t)(n) & ENET_TXDESCRIP_RD_BL1_MASK) << 16)
#define ENET_TXDESCRIP_RD_TTSE_MASK (1UL << 30)
#define ENET_TXDESCRIP_RD_IOC_MASK (1UL << 31)
#define ENET_TXDESCRIP_RD_FL_MASK (0x7FFFU)
#define ENET_TXDESCRIP_RD_FL(n) ((uint32_t)(n)&ENET_TXDESCRIP_RD_FL_MASK)
#define ENET_TXDESCRIP_RD_CIC(n) (((uint32_t)(n)&0x3U) << 16)
#define ENET_TXDESCRIP_RD_FL(n) ((uint32_t)(n) & ENET_TXDESCRIP_RD_FL_MASK)
#define ENET_TXDESCRIP_RD_CIC(n) (((uint32_t)(n) & 0x3U) << 16)
#define ENET_TXDESCRIP_RD_TSE_MASK (1UL << 18)
#define ENET_TXDESCRIP_RD_SLOT(n) (((uint32_t)(n)&0x0fU) << 19)
#define ENET_TXDESCRIP_RD_SAIC(n) (((uint32_t)(n)&0x07U) << 23)
#define ENET_TXDESCRIP_RD_CPC(n) (((uint32_t)(n)&0x03U) << 26)
#define ENET_TXDESCRIP_RD_LDFD(n) (((uint32_t)(n)&0x03U) << 28)
#define ENET_TXDESCRIP_RD_SLOT(n) (((uint32_t)(n) & 0x0fU) << 19)
#define ENET_TXDESCRIP_RD_SAIC(n) (((uint32_t)(n) & 0x07U) << 23)
#define ENET_TXDESCRIP_RD_CPC(n) (((uint32_t)(n) & 0x03U) << 26)
#define ENET_TXDESCRIP_RD_LDFD(n) (((uint32_t)(n) & 0x03U) << 28)
#define ENET_TXDESCRIP_RD_LD_MASK (1UL << 28)
#define ENET_TXDESCRIP_RD_FD_MASK (1UL << 29)
#define ENET_TXDESCRIP_RD_CTXT_MASK (1UL << 30)
@@ -198,11 +198,12 @@ typedef enum _enet_special_config
/**************************MTL************************************/
kENET_StoreAndForward = 0x0002U, /*!< The Rx/Tx store and forward enable. */
/***********************MAC****************************************/
kENET_PromiscuousEnable = 0x0004U, /*!< The promiscuous enabled. */
kENET_FlowControlEnable = 0x0008U, /*!< The flow control enabled. */
kENET_BroadCastRxDisable = 0x0010U, /*!< The broadcast disabled. */
kENET_MulticastAllEnable = 0x0020U, /*!< All multicast are passed. */
kENET_8023AS2KPacket = 0x0040U /*!< 8023as support for 2K packets. */
kENET_PromiscuousEnable = 0x0004U, /*!< The promiscuous enabled. */
kENET_FlowControlEnable = 0x0008U, /*!< The flow control enabled. */
kENET_BroadCastRxDisable = 0x0010U, /*!< The broadcast disabled. */
kENET_MulticastAllEnable = 0x0020U, /*!< All multicast are passed. */
kENET_8023AS2KPacket = 0x0040U, /*!< 8023as support for 2K packets. */
kENET_RxChecksumOffloadEnable = 0x0080U, /*!< The Rx checksum offload enabled. */
} enet_special_config_t;
/*! @brief List of DMA interrupts supported by the ENET interrupt. This
@@ -282,6 +283,48 @@ typedef enum _enet_ptp_event_type
kENET_PtpGnrlPort = 320U /*!< PTP general port number. */
} enet_ptp_event_type_t;
/*! @brief Define the Tx checksum offload options. */
typedef enum _enet_tx_offload
{
kENET_TxOffloadDisable = 0U, /*!< Disable Tx checksum offload. */
kENET_TxOffloadIPHeader = 1U, /*!< Enable IP header checksum calculation and insertion. */
kENET_TxOffloadIPHeaderPlusPayload = 2U, /*!< Enable IP header and payload checksum calculation and insertion. */
kENET_TxOffloadAll = 3U, /*!< Enable IP header, payload and pseudo header checksum calculation and insertion. */
} enet_tx_offload_t;
/*! @brief Ethernet VLAN Tag protocol identifiers. */
typedef enum _enet_vlan_tpid
{
kENET_StanCvlan = 0x0U, /*!< C-VLAN 0x8100. */
kENET_StanSvlan, /*!< S-VLAN 0x88A8. */
} enet_vlan_tpid_t;
/*! @brief Ethernet VLAN operations. */
typedef enum _enet_vlan_ops
{
kENET_NoOps = 0x0U, /*!< Not do anything. */
kENET_VlanRemove, /*!< Remove VLAN Tag. */
kENET_VlanInsert, /*!< Insert VLAN Tag. */
kENET_VlanReplace, /*!< Replace VLAN Tag. */
} enet_vlan_ops_t;
/*! @brief Ethernet VLAN strip setting. */
typedef enum _enet_vlan_strip
{
kENET_VlanNotStrip = 0x0U, /*!< Not strip frame. */
kENET_VlanFilterPassStrip, /*!< Strip if VLAN filter passes. */
kENET_VlanFilterFailStrip, /*!< Strip if VLAN filter fails. */
kENET_VlanAlwaysStrip, /*!< Always strip. */
} enet_vlan_strip_t;
/*! @brief Ethernet VLAN Tx channels. */
typedef enum _enet_vlan_tx_channel
{
kENET_VlanTagAllChannels = 0xFFU, /*!< VLAN tag is inserted for every packets transmitted by the MAC. */
kENET_VlanTagChannel0 = 0x0U, /*!< VLAN tag is inserted for the frames transmitted by channel 0. */
kENET_VlanTagChannel1, /*!< VLAN tag is inserted for the frames transmitted by channel 1. */
} enet_vlan_tx_channel_t;
/*! @brief Defines the receive descriptor structure
* It has the read-format and write-back format structures. They both
* have the same size with different region definition. So we define
@@ -314,6 +357,21 @@ typedef struct _enet_tx_bd_struct
__IO uint32_t tdes3; /*!< Transmit descriptor 3 */
} enet_tx_bd_struct_t;
/*! @brief Defines the Tx BD configuration structure. */
typedef struct _enet_tx_bd_config_struct
{
void *buffer1; /*!< The first buffer address in the descriptor. */
uint32_t bytes1; /*!< The bytes in the fist buffer. */
void *buffer2; /*!< The second buffer address in the descriptor. */
uint32_t bytes2; /*!< The bytes in the second buffer. */
uint32_t framelen; /*!< The length of the frame to be transmitted. */
bool intEnable; /*!< Interrupt enable flag. */
bool tsEnable; /*!< The timestamp enable. */
enet_tx_offload_t txOffloadOps; /*!< The Tx checksum offload option, only vaild for Queue 0. */
enet_desc_flag_t flag; /*!< The flag of this tx desciriptor, see "enet_qos_desc_flag". */
uint8_t slotNum; /*!< The slot number used for AV mode only. */
} enet_tx_bd_config_struct_t;
#ifdef ENET_PTP1588FEATURE_REQUIRED
/*! @brief Defines the ENET PTP configuration structure. */
typedef struct _enet_ptp_config
@@ -322,7 +380,7 @@ typedef struct _enet_ptp_config
bool ptp1588V2Enable; /*!< ptp 1588 version 2 is used. */
enet_ts_rollover_type_t tsRollover; /*!< 1588 time nanosecond rollover. */
} enet_ptp_config_t;
#endif /* ENET_PTP1588FEATURE_REQUIRED */
#endif /* ENET_PTP1588FEATURE_REQUIRED */
/*! @brief Defines the ENET PTP time stamp structure. */
typedef struct _enet_ptp_time
@@ -472,6 +530,7 @@ struct _enet_handle
enet_tx_dirty_ring_t txDirtyRing[ENET_RING_NUM_MAX]; /*!< Transmit dirty buffers addresses. */
uint32_t *rxBufferStartAddr[ENET_RING_NUM_MAX]; /*!< The Init-Rx buffers used for reinit corrupted BD due to
write-back operation. */
uint32_t txLenLimitation[ENET_RING_NUM_MAX]; /*!< Tx frame length limitation. */
enet_callback_t callback; /*!< Callback function. */
void *userData; /*!< Callback function parameter.*/
enet_rx_alloc_callback_t rxBuffAlloc; /*!< Callback to alloc memory, must be provided for zero-copy Rx. */
@@ -513,9 +572,10 @@ typedef struct _enet_rx_frame_struct
typedef struct _enet_tx_config_struct
{
uint8_t intEnable : 1; /*!< Enable interrupt every time one BD is completed. */
uint8_t tsEnable : 1; /*!< Transmit timestamp enable. */
uint8_t slotNum : 4; /*!< Slot number control bits in AV mode. */
uint8_t intEnable : 1; /*!< Enable interrupt every time one BD is completed. */
uint8_t tsEnable : 1; /*!< Transmit timestamp enable. */
uint8_t slotNum : 4; /*!< Slot number control bits in AV mode. */
enet_tx_offload_t txOffloadOps; /*!< Tx checksum offload option. */
} enet_tx_config_struct_t;
typedef struct _enet_tx_frame_struct
@@ -526,6 +586,39 @@ typedef struct _enet_tx_frame_struct
void *context; /*!< Driver reclaims and gives it in Tx over callback. */
} enet_tx_frame_struct_t;
/*! @brief Ethernet VLAN Tag. */
typedef struct _enet_vlan_tag
{
enet_vlan_tpid_t tpid; /*!< VLAN TPID. */
uint16_t pcp : 3; /*!< VLAN Priority. */
uint16_t dei : 1; /*!< Drop Eligible indicator. */
uint16_t vid : 12; /*!< VLAN Identifier. */
} enet_vlan_tag_t;
/*! @brief Ethernet VLAN configuration for Tx. */
typedef struct _enet_vlan_tx_config
{
bool txDescVlan; /*!< Use VLAN configuration in Tx descriptor. */
enet_vlan_tag_t tag; /*!< VLAN Tag. */
enet_vlan_ops_t ops; /*!< VLAN operations. */
} enet_vlan_tx_config_t;
/*! @brief Ethernet VLAN control. */
typedef struct _enet_vlan_ctrl
{
bool svlanEnable : 1; /*!< The MAC transmitter and receiver consider the S-VLAN packets. */
bool vlanInverseMatch : 1; /*!< True: Marks frames without matching as match, False: Marks matched frames. */
bool vidComparison : 1; /*!< Only takes VLAN VID as match. */
bool disableVlanTypeCheck : 1; /*!< Not check C-VLAN and S-VLAN. */
bool doubleVlanEnable : 1; /*!< Enable the inner VLAN operations. */
bool innerVlanFilterMatch : 1; /*!< Takes Inner VLAN as match. */
bool outerTagInRxStatus : 1; /*!< Set outer VLAN in Rx Status. */
bool innerTagInRxStatus : 1; /*!< Set inner VLAN in Rx Status. */
enet_vlan_tag_t rxVlanTag; /*!< VLAN tag for Rx match. */
enet_vlan_strip_t rxOuterVlanStrip; /*!< Outer VLAN Rx strip operation. */
enet_vlan_strip_t rxInnerVlanStrip; /*!< Inner VLAN Rx strip operation. */
} enet_vlan_ctrl_t;
/* Typedef for interrupt handler. */
typedef void (*enet_isr_t)(ENET_Type *base, enet_handle_t *handle);
@@ -853,6 +946,31 @@ static inline void ENET_ExitPowerDown(ENET_Type *base)
base->MAC_CONFIGURATION |= ENET_MAC_CONFIGURATION_TE_MASK;
}
/*!
* @brief Set VLAN control.
*
* @param base ENET peripheral base address.
* @param control VLAN control configuration.
*/
status_t ENET_SetVlanCtrl(ENET_Type *base, enet_vlan_ctrl_t *control);
/*!
* @brief Set Tx outer VLAN configuration.
*
* @param base ENET peripheral base address.
* @param config Tx VLAN operation configuration.
* @param channel The channel to apply this configuration.
*/
status_t ENET_SetTxOuterVlan(ENET_Type *base, enet_vlan_tx_config_t *config, enet_vlan_tx_channel_t channel);
/*!
* @brief Set Tx inner VLAN configuration.
*
* @param base ENET peripheral base address.
* @param config Tx VLAN operation configuration.
*/
status_t ENET_SetTxInnerVlan(ENET_Type *base, enet_vlan_tx_config_t *config);
/* @} */
/*!
@@ -1169,10 +1287,7 @@ status_t ENET_ReadFrame(ENET_Type *base,
* this function, driver will allocate new buffers for the BDs whose buffers have been taken by application.
* @note This function will drop current frame and update related BDs as available for DMA if new buffers allocating
* fails. Application must provide a memory pool including at least BD number + 1 buffers(+2 if enable double buffer)
* to make this function work normally. If user calls this function in Rx interrupt handler, be careful that this
* function makes Rx BD ready with allocating new buffer(normal) or updating current BD(out of memory). If there's
* always new Rx frame input, Rx interrupt will be triggered forever. Application need to disable Rx interrupt according
* to specific design in this case.
* to make this function work normally.
*
* @param base ENET peripheral base address.
* @param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init.
@@ -1302,4 +1417,4 @@ void ENET_Ptp1588GetTimer(ENET_Type *base, uint64_t *second, uint32_t *nanosecon
/*! @}*/
#endif /* _FSL_ENET_H_ */
#endif /* FSL_ENET_H_ */
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_erm.c
+113 -109
View File
@@ -65,9 +65,13 @@ void ERM_Init(ERM_Type *base)
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
base->CR0 = 0x00U;
#ifdef ERM_CR1_ENCIE8_MASK
base->CR1 = 0x00U;
#endif
base->SR0 = 0xFFFFFFFFU;
#ifdef ERM_SR1_SBC8_MASK
base->SR1 = 0xFFFFFFFFU;
#endif
}
/*!
@@ -86,66 +90,41 @@ uint32_t ERM_GetMemoryErrorAddr(ERM_Type *base, erm_memory_channel_t channel)
{
uint32_t absoluteErrorAddress = 0x00U;
switch (channel)
switch ((uint8_t)channel)
{
case kERM_MemoryChannelRAMX:
/* Total RAMX size: 96KB
RAMX0: 32KB(0x04000000 ~ 0x04007FFF)
RAMX1: 32KB(0x04008000 ~ 0x0400FFFF)
RAMX2: 32KB(0x04100000 ~ 0x04017FFF)
*/
case 0U:
absoluteErrorAddress = base->EAR0;
break;
case kERM_MemoryChannelRAMA:
/* Total RAMA size: 32KB
RAMA0: 8KB(0x20000000 ~ 0x20001FFF)
RAMA1: 8KB(0x20002000 ~ 0x20003FFF)
RAMA2: 8KB(0x20004000 ~ 0x20005FFF)
RAMA3: 8KB(0x20006000 ~ 0x20007FFF)
*/
#ifdef ERM_EAR1_EAR_MASK
case 1U:
absoluteErrorAddress = base->EAR1;
break;
case kERM_MemoryChannelRAMB:
/* Total RAMB size: 32KB
RAMB0: 32KB(0x20008000 ~ 0x2000FFFF)
*/
#endif
#ifdef ERM_EAR2_EAR_MASK
case 2U:
absoluteErrorAddress = base->EAR2;
break;
case kERM_MemoryChannelRAMC:
/* Total RAMC size: 64KB
RAMC0: 32KB(0x20010000 ~ 0x20017FFF)
RAMC0: 32KB(0x20018000 ~ 0x2001FFFF)
*/
#endif
#ifdef ERM_EAR3_EAR_MASK
case 3U:
absoluteErrorAddress = base->EAR3;
break;
case kERM_MemoryChannelRAMD:
/* Total RAMD size: 64KB
RAMD0: 32KB(0x20020000 ~ 0x20027FFF)
RAMD0: 32KB(0x20028000 ~ 0x2002FFFF)
*/
#endif
#ifdef ERM_EAR4_EAR_MASK
case 4U:
absoluteErrorAddress = base->EAR4;
break;
case kERM_MemoryChannelRAME:
/* Total RAME size: 64KB
RAME0: 32KB(0x20030000 ~ 0x20037FFF)
RAME0: 32KB(0x20038000 ~ 0x2003FFFF)
*/
#endif
#ifdef ERM_EAR5_EAR_MASK
case 5U:
absoluteErrorAddress = base->EAR5;
break;
case kERM_MemoryChannelRAMF:
/* Total RAMF size: 64KB
RAMF0: 32KB(0x20040000 ~ 0x20047FFF)
RAMF0: 32KB(0x20048000 ~ 0x2004FFFF)
*/
#endif
#ifdef ERM_EAR6_EAR_MASK
case 6U:
absoluteErrorAddress = base->EAR6;
break;
#endif
default:
assert(NULL);
break;
@@ -158,48 +137,56 @@ uint32_t ERM_GetSyndrome(ERM_Type *base, erm_memory_channel_t channel)
{
uint32_t syndrome = 0x00U;
switch (channel)
switch ((uint8_t)channel)
{
case kERM_MemoryChannelRAMX:
case 0U:
syndrome = (base->SYN0 & ERM_SYN0_SYNDROME_MASK) >> ERM_SYN0_SYNDROME_SHIFT;
break;
case kERM_MemoryChannelRAMA:
#ifdef ERM_SYN1_SYNDROME_MASK
case 1U:
syndrome = (base->SYN1 & ERM_SYN1_SYNDROME_MASK) >> ERM_SYN1_SYNDROME_SHIFT;
break;
case kERM_MemoryChannelRAMB:
#endif
#ifdef ERM_SYN2_SYNDROME_MASK
case 2U:
syndrome = (base->SYN2 & ERM_SYN2_SYNDROME_MASK) >> ERM_SYN2_SYNDROME_SHIFT;
break;
case kERM_MemoryChannelRAMC:
#endif
#ifdef ERM_SYN3_SYNDROME_MASK
case 3U:
syndrome = (base->SYN3 & ERM_SYN3_SYNDROME_MASK) >> ERM_SYN3_SYNDROME_SHIFT;
break;
case kERM_MemoryChannelRAMD:
#endif
#ifdef ERM_SYN4_SYNDROME_MASK
case 4U:
syndrome = (base->SYN4 & ERM_SYN4_SYNDROME_MASK) >> ERM_SYN4_SYNDROME_SHIFT;
break;
case kERM_MemoryChannelRAME:
#endif
#ifdef ERM_SYN5_SYNDROME_MASK
case 5U:
syndrome = (base->SYN5 & ERM_SYN5_SYNDROME_MASK) >> ERM_SYN5_SYNDROME_SHIFT;
break;
case kERM_MemoryChannelRAMF:
#endif
#ifdef ERM_SYN6_SYNDROME_MASK
case 6U:
syndrome = (base->SYN6 & ERM_SYN6_SYNDROME_MASK) >> ERM_SYN6_SYNDROME_SHIFT;
break;
case kERM_MemoryChannelLPCACRAM:
assert(NULL);
#endif
#ifdef ERM_SYN7_SYNDROME_MASK
case 7U:
syndrome = (base->SYN7 & ERM_SYN6_SYNDROME_MASK) >> ERM_SYN7_SYNDROME_SHIFT;
break;
case kERM_MemoryChannelPKCRAM:
#endif
#ifdef ERM_SYN8_SYNDROME_MASK
case 8U:
syndrome = (base->SYN8 & ERM_SYN8_SYNDROME_MASK) >> ERM_SYN8_SYNDROME_SHIFT;
break;
case kERM_MemoryChannelFLASH:
assert(NULL);
#endif
#ifdef ERM_SYN9_SYNDROME_MASK
case 8U:
syndrome = (base->SYN9 & ERM_SYN9_SYNDROME_MASK) >> ERM_SYN9_SYNDROME_SHIFT;
break;
#endif
default:
assert(NULL);
break;
@@ -212,48 +199,56 @@ uint32_t ERM_GetErrorCount(ERM_Type *base, erm_memory_channel_t channel)
{
uint32_t count = 0x00U;
switch (channel)
switch ((uint8_t)channel)
{
case kERM_MemoryChannelRAMX:
case 0U:
count = (base->CORR_ERR_CNT0 & ERM_CORR_ERR_CNT0_COUNT_MASK) >> ERM_CORR_ERR_CNT0_COUNT_SHIFT;
break;
case kERM_MemoryChannelRAMA:
#ifdef ERM_CORR_ERR_CNT1_COUNT_MASK
case 1U:
count = (base->CORR_ERR_CNT1 & ERM_CORR_ERR_CNT1_COUNT_MASK) >> ERM_CORR_ERR_CNT1_COUNT_SHIFT;
break;
case kERM_MemoryChannelRAMB:
#endif
#ifdef ERM_CORR_ERR_CNT2_COUNT_MASK
case 2U:
count = (base->CORR_ERR_CNT2 & ERM_CORR_ERR_CNT2_COUNT_MASK) >> ERM_CORR_ERR_CNT2_COUNT_SHIFT;
break;
case kERM_MemoryChannelRAMC:
#endif
#ifdef ERM_CORR_ERR_CNT3_COUNT_MASK
case 3U:
count = (base->CORR_ERR_CNT3 & ERM_CORR_ERR_CNT3_COUNT_MASK) >> ERM_CORR_ERR_CNT3_COUNT_SHIFT;
break;
case kERM_MemoryChannelRAMD:
#endif
#ifdef ERM_CORR_ERR_CNT4_COUNT_MASK
case 4U:
count = (base->CORR_ERR_CNT4 & ERM_CORR_ERR_CNT4_COUNT_MASK) >> ERM_CORR_ERR_CNT4_COUNT_SHIFT;
break;
case kERM_MemoryChannelRAME:
#endif
#ifdef ERM_CORR_ERR_CNT5_COUNT_MASK
case 5U:
count = (base->CORR_ERR_CNT5 & ERM_CORR_ERR_CNT5_COUNT_MASK) >> ERM_CORR_ERR_CNT5_COUNT_SHIFT;
break;
case kERM_MemoryChannelRAMF:
#endif
#ifdef ERM_CORR_ERR_CNT6_COUNT_MASK
case 6U:
count = (base->CORR_ERR_CNT6 & ERM_CORR_ERR_CNT6_COUNT_MASK) >> ERM_CORR_ERR_CNT6_COUNT_SHIFT;
break;
case kERM_MemoryChannelLPCACRAM:
#endif
#ifdef ERM_CORR_ERR_CNT7_COUNT_MASK
case 7U:
count = (base->CORR_ERR_CNT7 & ERM_CORR_ERR_CNT7_COUNT_MASK) >> ERM_CORR_ERR_CNT7_COUNT_SHIFT;
break;
case kERM_MemoryChannelPKCRAM:
#endif
#ifdef ERM_CORR_ERR_CNT8_COUNT_MASK
case 8U:
count = (base->CORR_ERR_CNT8 & ERM_CORR_ERR_CNT8_COUNT_MASK) >> ERM_CORR_ERR_CNT8_COUNT_SHIFT;
break;
case kERM_MemoryChannelFLASH:
#endif
#ifdef ERM_CORR_ERR_CNT9_COUNT_MASK
case 9U:
count = (base->CORR_ERR_CNT9 & ERM_CORR_ERR_CNT9_COUNT_MASK) >> ERM_CORR_ERR_CNT9_COUNT_SHIFT;
break;
#endif
default:
assert(NULL);
break;
@@ -264,48 +259,57 @@ uint32_t ERM_GetErrorCount(ERM_Type *base, erm_memory_channel_t channel)
void ERM_ResetErrorCount(ERM_Type *base, erm_memory_channel_t channel)
{
switch (channel)
switch ((uint8_t)channel)
{
case kERM_MemoryChannelRAMX:
case 0U:
base->CORR_ERR_CNT0 = 0x00U;
break;
case kERM_MemoryChannelRAMA:
#ifdef ERM_CORR_ERR_CNT1_COUNT_MASK
case 1U:
base->CORR_ERR_CNT1 = 0x00U;
break;
case kERM_MemoryChannelRAMB:
#endif
#ifdef ERM_CORR_ERR_CNT2_COUNT_MASK
case 2U:
base->CORR_ERR_CNT2 = 0x00U;
break;
case kERM_MemoryChannelRAMC:
#endif
#ifdef ERM_CORR_ERR_CNT3_COUNT_MASK
case 3U:
base->CORR_ERR_CNT3 = 0x00U;
break;
case kERM_MemoryChannelRAMD:
#endif
#ifdef ERM_CORR_ERR_CNT4_COUNT_MASK
case 4U:
base->CORR_ERR_CNT4 = 0x00U;
break;
case kERM_MemoryChannelRAME:
#endif
#ifdef ERM_CORR_ERR_CNT5_COUNT_MASK
case 5U:
base->CORR_ERR_CNT5 = 0x00U;
break;
case kERM_MemoryChannelRAMF:
#endif
#ifdef ERM_CORR_ERR_CNT6_COUNT_MASK
case 6U:
base->CORR_ERR_CNT6 = 0x00U;
break;
case kERM_MemoryChannelLPCACRAM:
#endif
#ifdef ERM_CORR_ERR_CNT6_COUNT_MASK
case 7U:
base->CORR_ERR_CNT7 = 0x00U;
break;
case kERM_MemoryChannelPKCRAM:
#endif
#ifdef ERM_CORR_ERR_CNT8_COUNT_MASK
case 8U:
base->CORR_ERR_CNT8 = 0x00U;
break;
case kERM_MemoryChannelFLASH:
#endif
#ifdef ERM_CORR_ERR_CNT9_COUNT_MASK
case 9U:
base->CORR_ERR_CNT9 = 0x00U;
break;
#endif
default:
assert(NULL);
break;
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_erm.h
+19 -7
View File
@@ -6,8 +6,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_ERM_H_
#define _FSL_ERM_H_
#ifndef FSL_ERM_H_
#define FSL_ERM_H_
#include "fsl_common.h"
@@ -21,10 +21,10 @@
*****************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @{ */
/*! @brief Driver version. */
#define FSL_ERM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 0U))
/*@}*/
#define FSL_ERM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 1U))
/*! @} */
/*!
* @brief ERM interrupt configuration structure, default settings all disabled, _erm_interrupt_enable.
@@ -78,7 +78,7 @@ void ERM_Init(ERM_Type *base);
*/
void ERM_Deinit(ERM_Type *base);
/* @} */
/*! @} */
/*!
* @name Interrupt
@@ -101,12 +101,14 @@ static inline void ERM_EnableInterrupts(ERM_Type *base, erm_memory_channel_t cha
base->CR0 =
(temp & ~(0x0CUL << ((0x07U - (uint32_t)channel) * 4U))) | (mask << ((0x07U - (uint32_t)channel) * 4U));
}
#ifdef ERM_CR1_ESCIE8_MASK
else
{
temp = base->CR1;
base->CR1 = (temp & ~(0x0CUL << ((0x07U + 0x08U - (uint32_t)channel) * 4U))) |
(mask << ((0x07U + 0x08U - (uint32_t)channel) * 4U));
}
#endif
}
/*!
@@ -123,10 +125,12 @@ static inline void ERM_DisableInterrupts(ERM_Type *base, erm_memory_channel_t ch
{
base->CR0 &= ~(mask << ((0x07U - (uint32_t)channel) * 4U));
}
#ifdef ERM_CR1_ESCIE8_MASK
else
{
base->CR1 &= ~(mask << ((0x07U + 0x08U - (uint32_t)channel) * 4U));
}
#endif
}
/*!
@@ -141,10 +145,16 @@ static inline uint32_t ERM_GetInterruptStatus(ERM_Type *base, erm_memory_channel
{
return ((base->SR0 & (uint32_t)kERM_AllIntsFlag) >> (0x07U - (uint32_t)channel) * 4U);
}
#ifdef ERM_SR1_SBC8_MASK
else
{
return ((base->SR1 & (uint32_t)kERM_AllIntsFlag) >> ((0x07U + 0x08U - (uint32_t)channel) * 4U));
}
#else
{
return 0;
}
#endif
}
/*!
@@ -159,13 +169,15 @@ static inline void ERM_ClearInterruptStatus(ERM_Type *base, erm_memory_channel_t
{
base->SR0 = mask << ((0x07U - (uint32_t)channel) * 4U);
}
#ifdef ERM_SR1_SBC8_MASK
else
{
base->SR1 = mask << ((0x07U + 0x08U - (uint32_t)channel) * 4U);
}
#endif
}
/* @} */
/*! @} */
/*!
* @name functional
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_evtg.h
+22 -22
View File
@@ -5,8 +5,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_EVTG_H_
#define _FSL_EVTG_H_
#ifndef FSL_EVTG_H_
#define FSL_EVTG_H_
#include "fsl_common.h"
@@ -20,10 +20,10 @@
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @{ */
/*! @brief EVTG driver version. */
#define FSL_EVTG_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1. */
/*@}*/
/*! @} */
/*! @brief EVTG instance index. */
typedef enum _evtg_index
@@ -247,7 +247,7 @@ static inline void EVTG_ForceFlipflopInitOutput(EVTG_Type *base,
evtg_index_t evtgIndex,
evtg_flipflop_init_output_t flipflopInitOutputValue)
{
base->EVTG_INST[(uint8_t)evtgIndex].EVTG_CTRL &= (~EVTG_EVTG_INST_EVTG_CTRL_FF_INIT_MASK);
base->EVTG_INST[(uint8_t)evtgIndex].EVTG_CTRL &= (~(uint16_t)EVTG_EVTG_INST_EVTG_CTRL_FF_INIT_MASK);
base->EVTG_INST[(uint8_t)evtgIndex].EVTG_CTRL |=
EVTG_EVTG_INST_EVTG_CTRL_FF_INIT((uint16_t)flipflopInitOutputValue);
/* INIT_EN bit should be set after FF_INIT is set. */
@@ -284,20 +284,20 @@ static inline void EVTG_SetProductTermInput(EVTG_Type *base,
if ((productTerm == kEVTG_ProductTerm0) || (productTerm == kEVTG_ProductTerm1))
{
base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI0_BFT01 &=
(~(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U))));
(uint16_t)(~(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U))));
base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI0_BFT01 |=
(((uint16_t)(((uint16_t)(input))
<< ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U)))) &
(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U))));
((((uint16_t)(input)) << ((3U - ((uint8_t)inputIndex)) * 2U +
(((3U - (uint8_t)productTerm) % 2U) * 8U))) &
(uint16_t)(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U))));
}
else
{
base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI0_BFT23 &=
(~(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U))));
(uint16_t)(~(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U))));
base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI0_BFT23 |=
(((uint16_t)(((uint16_t)(input))
<< ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U)))) &
(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U))));
((((uint16_t)(input)) << ((3U - ((uint8_t)inputIndex)) * 2U +
(((3U - (uint8_t)productTerm) % 2U) * 8U))) &
(uint16_t)(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U))));
}
}
else if (kEVTG_AOI1 == aoiIndex)
@@ -305,20 +305,20 @@ static inline void EVTG_SetProductTermInput(EVTG_Type *base,
if ((productTerm == kEVTG_ProductTerm0) || (productTerm == kEVTG_ProductTerm1))
{
base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI1_BFT01 &=
(~(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U))));
(uint16_t)(~(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U))));
base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI1_BFT01 |=
(((uint16_t)(((uint16_t)(input))
<< ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U)))) &
(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U))));
((((uint16_t)(input)) << ((3U - ((uint8_t)inputIndex)) * 2U +
(((3U - (uint8_t)productTerm) % 2U) * 8U))) &
(uint16_t)(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U))));
}
else
{
base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI1_BFT23 &=
(~(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U))));
(uint16_t)(~(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U))));
base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI1_BFT23 |=
(((uint16_t)(((uint16_t)(input))
<< ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U)))) &
(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U))));
((((uint16_t)(input)) << ((3U - ((uint8_t)inputIndex)) * 2U +
(((3U - (uint8_t)productTerm) % 2U) * 8U))) &
(uint16_t)(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U))));
}
}
else
@@ -352,4 +352,4 @@ void EVTG_ConfigAOIProductTerm(EVTG_Type *base,
/*! @} */
#endif /* _FSL_EVTG_H_ */
#endif /* FSL_EVTG_H_ */
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_ewm.h
+7 -7
View File
@@ -5,8 +5,8 @@
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_EWM_H_
#define _FSL_EWM_H_
#ifndef FSL_EWM_H_
#define FSL_EWM_H_
#include "fsl_common.h"
@@ -20,10 +20,10 @@
*******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @{ */
/*! @brief EWM driver version 2.0.3. */
#define FSL_EWM_DRIVER_VERSION (MAKE_VERSION(2, 0, 3))
/*@}*/
/*! @} */
/*! @brief Describes EWM clock source. */
#if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT
@@ -141,7 +141,7 @@ void EWM_Deinit(EWM_Type *base);
*/
void EWM_GetDefaultConfig(ewm_config_t *config);
/* @} */
/*! @} */
/*!
* @name EWM functional Operation
@@ -207,7 +207,7 @@ static inline uint32_t EWM_GetStatusFlags(EWM_Type *base)
*/
void EWM_Refresh(EWM_Type *base);
/*@}*/
/*! @} */
#if defined(__cplusplus)
}
@@ -215,4 +215,4 @@ void EWM_Refresh(EWM_Type *base);
/*! @}*/
#endif /* _FSL_EWM_H_ */
#endif /* FSL_EWM_H_ */
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexcan.c
+584 -270
View File
File diff suppressed because it is too large Load Diff
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexcan.h
+135 -16
View File
@@ -1,12 +1,12 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2022 NXP
* Copyright 2016-2023 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_FLEXCAN_H_
#define _FSL_FLEXCAN_H_
#ifndef FSL_FLEXCAN_H_
#define FSL_FLEXCAN_H_
#include "fsl_common.h"
@@ -20,10 +20,10 @@
*****************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @{ */
/*! @brief FlexCAN driver version. */
#define FSL_FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 9, 2))
/*@}*/
#define FSL_FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 11, 6))
/*! @} */
#if !(defined(FLEXCAN_WAIT_TIMEOUT) && FLEXCAN_WAIT_TIMEOUT)
/* Define to 1000 means keep waiting 1000 times until the flag is assert/deassert. */
@@ -231,7 +231,7 @@
#endif
/*! @brief FlexCAN Enhanced Rx FIFO base address helper macro. */
#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
#define E_RX_FIFO(base) ((uint32_t)(base) + 0x2000U)
#define E_RX_FIFO(base) ((uintptr_t)(base) + 0x2000U)
#else
#define FLEXCAN_MEMORY_ENHANCED_RX_FIFO_INIT_FLAG (0U)
#endif
@@ -339,7 +339,7 @@ enum _flexcan_fd_frame_length
kFLEXCAN_12BperFrame, /*!< Frame contains 12 valid data bytes. */
kFLEXCAN_16BperFrame, /*!< Frame contains 16 valid data bytes. */
kFLEXCAN_20BperFrame, /*!< Frame contains 20 valid data bytes. */
kFLEXCAN_24Bperrame, /*!< Frame contains 24 valid data bytes. */
kFLEXCAN_24BperFrame, /*!< Frame contains 24 valid data bytes. */
kFLEXCAN_32BperFrame, /*!< Frame contains 32 valid data bytes. */
kFLEXCAN_48BperFrame, /*!< Frame contains 48 valid data bytes. */
kFLEXCAN_64BperFrame, /*!< Frame contains 64 valid data bytes. */
@@ -1025,6 +1025,22 @@ extern "C" {
* @{
*/
#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
/*!
* @brief Determine whether the FlexCAN instance support CAN FD mode at run time.
*
* @note Use this API only if different soc parts share the SOC part name macro define. Otherwise, a different SOC part
* name can be used to determine at compile time whether the FlexCAN instance supports CAN FD mode or not.
* If need use this API to determine if CAN FD mode is supported, the FLEXCAN_Init function needs to be
* executed first, and then call this API and use the return to value determines whether to supports CAN FD mode,
* if return true, continue calling FLEXCAN_FDInit to enable CAN FD mode.
*
* @param base FlexCAN peripheral base address.
* @return return TRUE if instance support CAN FD mode, FALSE if instance only support classic CAN (2.0) mode.
*/
bool FLEXCAN_IsInstanceHasFDMode(CAN_Type *base);
#endif
/*!
* @brief Enter FlexCAN Freeze Mode.
*
@@ -1185,7 +1201,7 @@ void FLEXCAN_Deinit(CAN_Type *base);
*/
void FLEXCAN_GetDefaultConfig(flexcan_config_t *pConfig);
/* @} */
/*! @} */
/*!
* @name Configuration.
@@ -1394,7 +1410,7 @@ void FLEXCAN_SetEnhancedRxFifoConfig(CAN_Type *base, const flexcan_enhanced_rx_f
*/
void FLEXCAN_SetPNConfig(CAN_Type *base, const flexcan_pn_config_t *pConfig);
#endif
/* @} */
/*! @} */
/*!
* @name Status
@@ -1518,6 +1534,29 @@ static inline uint32_t FLEXCAN_GetMbStatusFlags(CAN_Type *base, uint32_t mask)
#endif
}
#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB)
/*!
* @brief Gets the FlexCAN High 64 Message Buffer interrupt flags.
*
* Valid only if the number of available MBs exceeds 64.
*
* @param base FlexCAN peripheral base address.
* @param mask The ORed FlexCAN Message Buffer mask.
* @return The status of given Message Buffers.
*/
static inline uint64_t FLEXCAN_GetHigh64MbStatusFlags(CAN_Type *base, uint64_t mask)
{
uint64_t tempflag = 0U;
#if defined(CAN_IFLAG3_BUF95TO64_MASK)
tempflag |= (uint64_t)base->IFLAG3;
#endif
#if defined(CAN_IFLAG4_BUF127TO96_MASK)
tempflag |= (uint64_t)base->IFLAG4;
#endif
return (tempflag & mask);
}
#endif
/*!
* @brief Clears the FlexCAN Message Buffer interrupt flags.
*
@@ -1540,6 +1579,26 @@ static inline void FLEXCAN_ClearMbStatusFlags(CAN_Type *base, uint32_t mask)
#endif
}
#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB)
/*!
* @brief Clears the FlexCAN High 64 Message Buffer interrupt flags.
*
* Valid only if the number of available MBs exceeds 64.
*
* @param base FlexCAN peripheral base address.
* @param mask The ORed FlexCAN Message Buffer mask.
*/
static inline void FLEXCAN_ClearHigh64MbStatusFlags(CAN_Type *base, uint64_t mask)
{
#if defined(CAN_IFLAG3_BUF95TO64_MASK)
base->IFLAG3 = (uint32_t)(mask & 0xFFFFFFFFU);
#endif
#if defined(CAN_IFLAG4_BUF127TO96_MASK)
base->IFLAG4 = (uint32_t)(mask >> 32U);
#endif
}
#endif
#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
/*!
* @brief Gets the FlexCAN Memory Error Report registers status.
@@ -1582,7 +1641,7 @@ static inline uint32_t FLEXCAN_GetEnhancedFifoDataCount(CAN_Type *base)
return (base->ERFSR & CAN_ERFSR_ERFEL_MASK);
}
#endif
/* @} */
/*! @} */
/*!
* @name Interrupts
@@ -1606,6 +1665,8 @@ static inline void FLEXCAN_EnableInterrupts(CAN_Type *base, uint64_t mask)
static inline void FLEXCAN_EnableInterrupts(CAN_Type *base, uint32_t mask)
#endif
{
uint32_t primask = DisableGlobalIRQ();
/* Solve Self Wake Up interrupt. */
base->MCR |= (uint32_t)(mask & (uint32_t)kFLEXCAN_WakeUpInterruptEnable);
@@ -1636,6 +1697,8 @@ static inline void FLEXCAN_EnableInterrupts(CAN_Type *base, uint32_t mask)
base->CTRL1 |=
(uint32_t)(mask & ((uint32_t)kFLEXCAN_BusOffInterruptEnable | (uint32_t)kFLEXCAN_ErrorInterruptEnable |
(uint32_t)kFLEXCAN_RxWarningInterruptEnable | (uint32_t)kFLEXCAN_TxWarningInterruptEnable));
EnableGlobalIRQ(primask);
}
/*!
@@ -1654,6 +1717,8 @@ static inline void FLEXCAN_DisableInterrupts(CAN_Type *base, uint64_t mask)
static inline void FLEXCAN_DisableInterrupts(CAN_Type *base, uint32_t mask)
#endif
{
uint32_t primask = DisableGlobalIRQ();
/* Solve Wake Up Interrupt. */
base->MCR &= ~(uint32_t)(mask & (uint32_t)kFLEXCAN_WakeUpInterruptEnable);
@@ -1684,6 +1749,8 @@ static inline void FLEXCAN_DisableInterrupts(CAN_Type *base, uint32_t mask)
base->CTRL1 &=
~(uint32_t)(mask & ((uint32_t)kFLEXCAN_BusOffInterruptEnable | (uint32_t)kFLEXCAN_ErrorInterruptEnable |
(uint32_t)kFLEXCAN_RxWarningInterruptEnable | (uint32_t)kFLEXCAN_TxWarningInterruptEnable));
EnableGlobalIRQ(primask);
}
/*!
@@ -1700,14 +1767,40 @@ static inline void FLEXCAN_EnableMbInterrupts(CAN_Type *base, uint64_t mask)
static inline void FLEXCAN_EnableMbInterrupts(CAN_Type *base, uint32_t mask)
#endif
{
uint32_t primask = DisableGlobalIRQ();
#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
base->IMASK1 |= (uint32_t)(mask & 0xFFFFFFFFU);
base->IMASK2 |= (uint32_t)(mask >> 32);
#else
base->IMASK1 |= mask;
#endif
EnableGlobalIRQ(primask);
}
#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB)
/*!
* @brief Enables FlexCAN high 64 Message Buffer interrupts.
*
* Valid only if the number of available MBs exceeds 64.
*
* @param base FlexCAN peripheral base address.
* @param mask The ORed FlexCAN Message Buffer mask.
*/
static inline void FLEXCAN_EnableHigh64MbInterrupts(CAN_Type *base, uint64_t mask)
{
uint32_t primask = DisableGlobalIRQ();
#if defined(CAN_IMASK3_BUF95TO64M_MASK)
base->IMASK3 |= (uint32_t)(mask & 0xFFFFFFFFU);
#endif
#if defined(CAN_IMASK4_BUF127TO96_MASK)
base->IMASK4 |= (uint32_t)(mask >> 32U);
#endif
EnableGlobalIRQ(primask);
}
#endif
/*!
* @brief Disables FlexCAN Message Buffer interrupts.
*
@@ -1722,15 +1815,41 @@ static inline void FLEXCAN_DisableMbInterrupts(CAN_Type *base, uint64_t mask)
static inline void FLEXCAN_DisableMbInterrupts(CAN_Type *base, uint32_t mask)
#endif
{
uint32_t primask = DisableGlobalIRQ();
#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
base->IMASK1 &= ~((uint32_t)(mask & 0xFFFFFFFFU));
base->IMASK2 &= ~((uint32_t)(mask >> 32));
#else
base->IMASK1 &= ~mask;
#endif
EnableGlobalIRQ(primask);
}
/* @} */
#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB)
/*!
* @brief Disables FlexCAN high 64 Message Buffer interrupts.
*
* Valid only if the number of available MBs exceeds 64.
*
* @param base FlexCAN peripheral base address.
* @param mask The ORed FlexCAN Message Buffer mask.
*/
static inline void FLEXCAN_DisableHigh64MbInterrupts(CAN_Type *base, uint64_t mask)
{
uint32_t primask = DisableGlobalIRQ();
#if defined(CAN_IMASK3_BUF95TO64M_MASK)
base->IMASK3 &= ~((uint32_t)(mask & 0xFFFFFFFFU));
#endif
#if defined(CAN_IMASK4_BUF127TO96_MASK)
base->IMASK4 &= ~((uint32_t)(mask >> 32U));
#endif
EnableGlobalIRQ(primask);
}
#endif
/*! @} */
#if (defined(FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) && FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA)
/*!
@@ -1761,7 +1880,7 @@ static inline uintptr_t FLEXCAN_GetRxFifoHeadAddr(CAN_Type *base)
return (uintptr_t) & (base->MB[0].CS);
}
/* @} */
/*! @} */
#endif /* FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA */
/*!
@@ -1907,7 +2026,7 @@ status_t FLEXCAN_ReadEnhancedRxFifo(CAN_Type *base, flexcan_fd_frame_t *pRxFrame
*/
status_t FLEXCAN_ReadPNWakeUpMB(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame);
#endif
/* @} */
/*! @} */
/*!
* @name Transactional
@@ -2230,7 +2349,7 @@ void FLEXCAN_TransferAbortReceiveEnhancedFifo(CAN_Type *base, flexcan_handle_t *
*/
void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle);
/* @} */
/*! @} */
#if defined(__cplusplus)
}
@@ -2238,4 +2357,4 @@ void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle);
/*! @}*/
#endif /* _FSL_FLEXCAN_H_ */
#endif /* FSL_FLEXCAN_H_ */
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexcan_edma.c
+381
View File
@@ -0,0 +1,381 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_flexcan_edma.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.flexcan_edma"
#endif
/*<! Structure definition for flexcan_edma_private_handle_t. The structure is private. */
typedef struct _flexcan_edma_private_handle
{
CAN_Type *base;
flexcan_edma_handle_t *handle;
} flexcan_edma_private_handle_t;
/* FlexCAN EDMA transfer handle. */
enum _flexcan_edma_tansfer_state
{
KFLEXCAN_RxFifoIdle = 0U, /* Rx Fifo idle. */
KFLEXCAN_RxFifoBusy = 1U, /* Rx Fifo busy. */
};
/*******************************************************************************
* Variables
******************************************************************************/
/* Array of FlexCAN peripheral base address. */
static CAN_Type *const s_flexcanBases[] = CAN_BASE_PTRS;
/* Private handle only used for internally. */
static flexcan_edma_private_handle_t s_flexcanEdmaPrivateHandle[ARRAY_SIZE(s_flexcanBases)];
/*******************************************************************************
* Prototypes
******************************************************************************/
/*!
* @brief FlexCAN EDMA receive finished callback function.
*
* This function is called when FlexCAN Rx FIFO EDMA receive finished.
* It disables the FlexCAN Rx FIFO EDMA request and sends
* @ref kStatus_FLEXCAN_RxFifoIdle to FlexCAN EDMA callback.
*
* @param handle The EDMA handle.
* @param param Callback function parameter.
*/
static void FLEXCAN_ReceiveFifoEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds);
/*******************************************************************************
* Code
******************************************************************************/
static void FLEXCAN_ReceiveFifoEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds)
{
handle = handle;
tcds = tcds;
#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
flexcan_fd_frame_t *framefd;
uint32_t idHitIndex;
#endif
flexcan_edma_private_handle_t *flexcanPrivateHandle = (flexcan_edma_private_handle_t *)param;
/*
* $Branch Coverage Justification$
* (!transferDone) not covered. Unable to simulate DMA transfer error.
*/
if (transferDone)
{
#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
if (0U != (flexcanPrivateHandle->base->ERFCR & CAN_ERFCR_ERFEN_MASK))
{
framefd = flexcanPrivateHandle->handle->framefd;
for (uint32_t i = 0; i < flexcanPrivateHandle->handle->frameNum; i++)
{
/* Enhanced Rx FIFO ID HIT offset is changed dynamically according to data length code (DLC) . */
idHitIndex = (DLC_LENGTH_DECODE(framefd->length) + 3U) / 4U;
framefd->idhit = framefd->dataWord[idHitIndex];
/* Clear the unused frame data. */
for (uint32_t j = idHitIndex; j < 16U; j++)
{
framefd->dataWord[j] = 0x0U;
}
framefd++;
}
}
#endif
/* Disable transfer. */
FLEXCAN_TransferAbortReceiveFifoEDMA(flexcanPrivateHandle->base, flexcanPrivateHandle->handle);
if (NULL != flexcanPrivateHandle->handle->callback)
{
flexcanPrivateHandle->handle->callback(flexcanPrivateHandle->base, flexcanPrivateHandle->handle,
kStatus_FLEXCAN_RxFifoIdle, flexcanPrivateHandle->handle->userData);
}
}
}
/*!
* brief Initializes the FlexCAN handle, which is used in transactional functions.
*
* param base FlexCAN peripheral base address.
* param handle Pointer to flexcan_edma_handle_t structure.
* param callback The callback function.
* param userData The parameter of the callback function.
* param rxFifoEdmaHandle User-requested DMA handle for Rx FIFO DMA transfer.
*/
void FLEXCAN_TransferCreateHandleEDMA(CAN_Type *base,
flexcan_edma_handle_t *handle,
flexcan_edma_transfer_callback_t callback,
void *userData,
edma_handle_t *rxFifoEdmaHandle)
{
assert(NULL != handle);
uint32_t instance = FLEXCAN_GetInstance(base);
s_flexcanEdmaPrivateHandle[instance].base = base;
s_flexcanEdmaPrivateHandle[instance].handle = handle;
(void)memset(handle, 0, sizeof(flexcan_edma_handle_t));
handle->rxFifoState = (uint8_t)KFLEXCAN_RxFifoIdle;
handle->rxFifoEdmaHandle = rxFifoEdmaHandle;
/* Register Callback. */
handle->callback = callback;
handle->userData = userData;
/* Configure Legacy/Enhanced Rx FIFO DMA callback. */
EDMA_SetCallback(handle->rxFifoEdmaHandle, FLEXCAN_ReceiveFifoEDMACallback, &s_flexcanEdmaPrivateHandle[instance]);
}
/*!
* brief Prepares the eDMA transfer configuration for FLEXCAN Legacy RX FIFO.
*
* This function prepares the eDMA transfer configuration structure according to FLEXCAN Legacy RX FIFO.
*
* param base FlexCAN peripheral base address.
* param pFifoXfer FlexCAN Rx FIFO EDMA transfer structure, see #flexcan_fifo_transfer_t.
* param pEdmaConfig The user configuration structure of type edma_transfer_t.
*
*/
void FLEXCAN_PrepareTransfConfiguration(CAN_Type *base,
flexcan_fifo_transfer_t *pFifoXfer,
edma_transfer_config_t *pEdmaConfig)
{
assert(NULL != pFifoXfer);
assert(NULL != pFifoXfer->frame);
assert(NULL != pEdmaConfig);
flexcan_frame_t *fifoAddr = (flexcan_frame_t *)FLEXCAN_GetRxFifoHeadAddr(base);
#if (defined(FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER)
EDMA_PrepareTransfer(pEdmaConfig, (void *)fifoAddr, sizeof(flexcan_frame_t), (void *)pFifoXfer->frame,
sizeof(uint32_t), sizeof(flexcan_frame_t), sizeof(flexcan_frame_t) * pFifoXfer->frameNum,
kEDMA_PeripheralToMemory);
#else
/* The Data Size of FLEXCAN Legacy RX FIFO output port is 16 Bytes, but lots of chips not support 16Bytes width DMA
* transfer. These chips always support 4Byte width memory transfer, so we need prepare Memory to Memory mode by 4
* Bytes width mode.
*/
EDMA_PrepareTransfer(pEdmaConfig, (void *)fifoAddr, 4U, (void *)pFifoXfer->frame, sizeof(uint32_t),
sizeof(flexcan_frame_t), sizeof(flexcan_frame_t) * pFifoXfer->frameNum, kEDMA_MemoryToMemory);
#endif
}
/*!
* brief Start Transfer Data from the FLEXCAN Legacy Rx FIFO using eDMA.
*
* This function to Update edma transfer confiugration and Start eDMA transfer
*
* param base FlexCAN peripheral base address.
* param handle Pointer to flexcan_edma_handle_t structure.
* param pEdmaConfig The user configuration structure of type edma_transfer_t.
* retval kStatus_Success if succeed, others failed.
* retval kStatus_FLEXCAN_RxFifoBusy Previous transfer ongoing.
*/
status_t FLEXCAN_StartTransferDatafromRxFIFO(CAN_Type *base,
flexcan_edma_handle_t *handle,
edma_transfer_config_t *pEdmaConfig)
{
assert(NULL != handle->rxFifoEdmaHandle);
assert(NULL != pEdmaConfig);
status_t status;
/* If previous Rx FIFO receive not finished. */
if ((uint8_t)KFLEXCAN_RxFifoBusy == handle->rxFifoState)
{
status = kStatus_FLEXCAN_RxFifoBusy;
}
else
{
handle->rxFifoState = (uint8_t)KFLEXCAN_RxFifoBusy;
/* Enable FlexCAN Rx FIFO EDMA. */
FLEXCAN_EnableRxFifoDMA(base, true);
/* Submit configuration. */
(void)EDMA_SubmitTransfer(handle->rxFifoEdmaHandle, (const edma_transfer_config_t *)pEdmaConfig);
EDMA_SetModulo(handle->rxFifoEdmaHandle->base, handle->rxFifoEdmaHandle->channel, kEDMA_Modulo16bytes,
kEDMA_ModuloDisable);
/* Start transfer. */
EDMA_StartTransfer(handle->rxFifoEdmaHandle);
status = kStatus_Success;
}
return status;
}
/*!
* brief Receives the CAN Messages from the Legacy Rx FIFO using eDMA.
*
* This function receives the CAN Message using eDMA. This is a non-blocking function, which returns
* right away. After the CAN Message is received, the receive callback function is called.
*
* param base FlexCAN peripheral base address.
* param handle Pointer to flexcan_edma_handle_t structure.
* param pFifoXfer FlexCAN Rx FIFO EDMA transfer structure, see #flexcan_fifo_transfer_t.
* retval kStatus_Success if succeed, others failed.
* retval kStatus_FLEXCAN_RxFifoBusy Previous transfer ongoing.
*/
status_t FLEXCAN_TransferReceiveFifoEDMA(CAN_Type *base,
flexcan_edma_handle_t *handle,
flexcan_fifo_transfer_t *pFifoXfer)
{
assert(NULL != handle->rxFifoEdmaHandle);
assert(NULL != pFifoXfer->frame);
edma_transfer_config_t dmaXferConfig = {0};
status_t status;
handle->frameNum = pFifoXfer->frameNum;
/* Prepare transfer. */
FLEXCAN_PrepareTransfConfiguration(base, pFifoXfer, &dmaXferConfig);
/* Submit configuration and start edma transfer. */
status = FLEXCAN_StartTransferDatafromRxFIFO(base, handle, &dmaXferConfig);
return status;
}
/*!
* brief Gets the Legacy Rx Fifo transfer status during a interrupt non-blocking receive.
*
* param base FlexCAN peripheral base address.
* param handle FlexCAN handle pointer.
* param count Number of CAN messages receive so far by the non-blocking transaction.
* retval kStatus_InvalidArgument count is Invalid.
* retval kStatus_Success Successfully return the count.
*/
status_t FLEXCAN_TransferGetReceiveFifoCountEMDA(CAN_Type *base, flexcan_edma_handle_t *handle, size_t *count)
{
assert(NULL != handle);
status_t result = kStatus_Success;
if (handle->rxFifoState == (uint32_t)KFLEXCAN_RxFifoIdle)
{
result = kStatus_NoTransferInProgress;
}
else
{
*count = handle->frameNum -
EDMA_GetRemainingMajorLoopCount(handle->rxFifoEdmaHandle->base, handle->rxFifoEdmaHandle->channel);
}
return result;
}
/*!
* brief Aborts the receive Legacy/Enhanced Rx FIFO process which used eDMA.
*
* This function aborts the receive Legacy/Enhanced Rx FIFO process which used eDMA.
*
* param base FlexCAN peripheral base address.
* param handle Pointer to flexcan_edma_handle_t structure.
*/
void FLEXCAN_TransferAbortReceiveFifoEDMA(CAN_Type *base, flexcan_edma_handle_t *handle)
{
assert(NULL != handle->rxFifoEdmaHandle);
/* Stop transfer. */
EDMA_AbortTransfer(handle->rxFifoEdmaHandle);
handle->rxFifoState = (uint8_t)KFLEXCAN_RxFifoIdle;
#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
handle->framefd = NULL;
#endif
handle->frameNum = 0U;
/* Disable FlexCAN Legacy/Enhanced Rx FIFO EDMA. */
FLEXCAN_EnableRxFifoDMA(base, false);
}
#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
/*!
* brief Receives the CAN FD Message from the Enhanced Rx FIFO using eDMA.
*
* This function receives the CAN FD Message using eDMA. This is a non-blocking function, which returns
* right away. After the CAN Message is received, the receive callback function is called.
*
* param base FlexCAN peripheral base address.
* param handle Pointer to flexcan_edma_handle_t structure.
* param pFifoXfer FlexCAN Rx FIFO EDMA transfer structure, see #flexcan_fifo_transfer_t.
* retval kStatus_Success if succeed, others failed.
* retval kStatus_FLEXCAN_RxFifoBusy Previous transfer ongoing.
* retval kStatus_InvalidArgument The watermark configuration is invalid, the watermark need be set to
1 to do successfully EDMA transfer with this API.
*/
status_t FLEXCAN_TransferReceiveEnhancedFifoEDMA(CAN_Type *base,
flexcan_edma_handle_t *handle,
flexcan_fifo_transfer_t *pFifoXfer)
{
assert(NULL != handle->rxFifoEdmaHandle);
assert(NULL != pFifoXfer->framefd);
edma_transfer_config_t dmaXferConfig;
edma_minor_offset_config_t dmaMinorOffsetConfig;
status_t status;
flexcan_fd_frame_t *fifoAddr = (flexcan_fd_frame_t *)E_RX_FIFO(base);
uint32_t perReadWords = ((base->ERFCR & CAN_ERFCR_DMALW_MASK) >> CAN_ERFCR_DMALW_SHIFT) + 1U;
uint32_t watermark = ((base->ERFCR & CAN_ERFCR_ERFWM_MASK) >> CAN_ERFCR_ERFWM_SHIFT) + 1U;
/* If previous Rx FIFO receive not finished. */
if ((uint8_t)KFLEXCAN_RxFifoBusy == handle->rxFifoState)
{
status = kStatus_FLEXCAN_RxFifoBusy;
}
else
{
handle->frameNum = pFifoXfer->frameNum;
handle->framefd = pFifoXfer->framefd;
/*!< To reduce the complexity of DMA software configuration, need to set watermark to 1 to make that each DMA
request read once Rx FIFO. Because a DMA transfer cannot be dynamically changed, Number of words read per
transfer (ERFCR[DMALW] + 1) should be programmed so that the Enhanced Rx FIFO element can store the largest
CAN message present on the CAN bus. */
if ((watermark != 1U) || ((sizeof(uint32_t) * perReadWords) != sizeof(flexcan_fd_frame_t)))
{
return kStatus_InvalidArgument;
}
/* Prepare transfer. */
EDMA_PrepareTransfer(
&dmaXferConfig, (void *)fifoAddr, sizeof(uint32_t), (void *)pFifoXfer->framefd, sizeof(uint32_t),
sizeof(uint32_t) * perReadWords, /* minor loop bytes : 4* perReadWords */
sizeof(uint32_t) * perReadWords * handle->frameNum, /* major loop counts : handle->frameNum */
kEDMA_MemoryToMemory);
/* Submit configuration. */
(void)EDMA_SubmitTransfer(handle->rxFifoEdmaHandle, &dmaXferConfig);
dmaMinorOffsetConfig.enableDestMinorOffset = false;
dmaMinorOffsetConfig.enableSrcMinorOffset = true;
dmaMinorOffsetConfig.minorOffset = 128U - sizeof(uint32_t) * perReadWords;
EDMA_SetMinorOffsetConfig(handle->rxFifoEdmaHandle->base, handle->rxFifoEdmaHandle->channel,
&dmaMinorOffsetConfig);
EDMA_SetModulo(handle->rxFifoEdmaHandle->base, handle->rxFifoEdmaHandle->channel, kEDMA_Modulo128bytes,
kEDMA_ModuloDisable);
handle->rxFifoState = (uint8_t)KFLEXCAN_RxFifoBusy;
/* Enable FlexCAN Rx FIFO EDMA. */
FLEXCAN_EnableRxFifoDMA(base, true);
/* Start transfer. */
EDMA_StartTransfer(handle->rxFifoEdmaHandle);
status = kStatus_Success;
}
return status;
}
#endif
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexcan_edma.h
+188
View File
@@ -0,0 +1,188 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2023 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef FSL_FLEXCAN_EDMA_H_
#define FSL_FLEXCAN_EDMA_H_
#include "fsl_flexcan.h"
#include "fsl_edma.h"
/*!
* @addtogroup flexcan_edma_driver
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @name Driver version */
/*! @{ */
/*! @brief FlexCAN EDMA driver version. */
#define FSL_FLEXCAN_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 11, 3))
/*! @} */
/* Forward declaration of the handle typedef. */
typedef struct _flexcan_edma_handle flexcan_edma_handle_t;
/*! @brief FlexCAN transfer callback function. */
typedef void (*flexcan_edma_transfer_callback_t)(CAN_Type *base,
flexcan_edma_handle_t *handle,
status_t status,
void *userData);
/*!
* @brief FlexCAN eDMA handle
*/
struct _flexcan_edma_handle
{
flexcan_edma_transfer_callback_t callback; /*!< Callback function. */
void *userData; /*!< FlexCAN callback function parameter.*/
edma_handle_t *rxFifoEdmaHandle; /*!< The EDMA handler for Rx FIFO. */
volatile uint8_t rxFifoState; /*!< Rx FIFO transfer state. */
size_t frameNum; /*!< The number of messages that need to be received. */
#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
flexcan_fd_frame_t *framefd; /*!< Point to the buffer of CAN Message to be received from Enhanced Rx FIFO. */
#endif
};
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @name eDMA transactional
* @{
*/
/*!
* @brief Initializes the FlexCAN handle, which is used in transactional functions.
*
* @param base FlexCAN peripheral base address.
* @param handle Pointer to flexcan_edma_handle_t structure.
* @param callback The callback function.
* @param userData The parameter of the callback function.
* @param rxFifoEdmaHandle User-requested DMA handle for Rx FIFO DMA transfer.
*/
void FLEXCAN_TransferCreateHandleEDMA(CAN_Type *base,
flexcan_edma_handle_t *handle,
flexcan_edma_transfer_callback_t callback,
void *userData,
edma_handle_t *rxFifoEdmaHandle);
/*!
* @brief Prepares the eDMA transfer configuration for FLEXCAN Legacy RX FIFO.
*
* This function prepares the eDMA transfer configuration structure according to FLEXCAN Legacy RX FIFO.
*
* @param base FlexCAN peripheral base address.
* @param pFifoXfer FlexCAN Rx FIFO EDMA transfer structure, see #flexcan_fifo_transfer_t.
* @param pEdmaConfig The user configuration structure of type edma_transfer_t.
*
*/
void FLEXCAN_PrepareTransfConfiguration(CAN_Type *base,
flexcan_fifo_transfer_t *pFifoXfer,
edma_transfer_config_t *pEdmaConfig);
/*!
* @brief Start Transfer Data from the FLEXCAN Legacy Rx FIFO using eDMA.
*
* This function to Update edma transfer confiugration and Start eDMA transfer
*
* @param base FlexCAN peripheral base address.
* @param handle Pointer to flexcan_edma_handle_t structure.
* @param pEdmaConfig The user configuration structure of type edma_transfer_t.
* @retval kStatus_Success if succeed, others failed.
* @retval kStatus_FLEXCAN_RxFifoBusy Previous transfer ongoing.
*/
status_t FLEXCAN_StartTransferDatafromRxFIFO(CAN_Type *base,
flexcan_edma_handle_t *handle,
edma_transfer_config_t *pEdmaConfig);
/*!
* @brief Receives the CAN Message from the Legacy Rx FIFO using eDMA.
*
* This function receives the CAN Message using eDMA. This is a non-blocking function, which returns
* right away. After the CAN Message is received, the receive callback function is called.
*
* @param base FlexCAN peripheral base address.
* @param handle Pointer to flexcan_edma_handle_t structure.
* @param pFifoXfer FlexCAN Rx FIFO EDMA transfer structure, see #flexcan_fifo_transfer_t.
* @retval kStatus_Success if succeed, others failed.
* @retval kStatus_FLEXCAN_RxFifoBusy Previous transfer ongoing.
*/
status_t FLEXCAN_TransferReceiveFifoEDMA(CAN_Type *base,
flexcan_edma_handle_t *handle,
flexcan_fifo_transfer_t *pFifoXfer);
/*!
* @brief Gets the Legacy Rx Fifo transfer status during a interrupt non-blocking receive.
*
* @param base FlexCAN peripheral base address.
* @param handle FlexCAN handle pointer.
* @param count Number of CAN messages receive so far by the non-blocking transaction.
* @retval kStatus_InvalidArgument count is Invalid.
* @retval kStatus_Success Successfully return the count.
*/
status_t FLEXCAN_TransferGetReceiveFifoCountEMDA(CAN_Type *base, flexcan_edma_handle_t *handle, size_t *count);
/*!
* @brief Aborts the receive Legacy/Enhanced Rx FIFO process which used eDMA.
*
* This function aborts the receive Legacy/Enhanced Rx FIFO process which used eDMA.
*
* @param base FlexCAN peripheral base address.
* @param handle Pointer to flexcan_edma_handle_t structure.
*/
void FLEXCAN_TransferAbortReceiveFifoEDMA(CAN_Type *base, flexcan_edma_handle_t *handle);
#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
/*!
* @brief Receives the CAN FD Message from the Enhanced Rx FIFO using eDMA.
*
* This function receives the CAN FD Message using eDMA. This is a non-blocking function, which returns
* right away. After the CAN Message is received, the receive callback function is called.
*
* @param base FlexCAN peripheral base address.
* @param handle Pointer to flexcan_edma_handle_t structure.
* @param pFifoXfer FlexCAN Rx FIFO EDMA transfer structure, see #flexcan_fifo_transfer_t.
* @retval kStatus_Success if succeed, others failed.
* @retval kStatus_FLEXCAN_RxFifoBusy Previous transfer ongoing.
*/
status_t FLEXCAN_TransferReceiveEnhancedFifoEDMA(CAN_Type *base,
flexcan_edma_handle_t *handle,
flexcan_fifo_transfer_t *pFifoXfer);
/*!
* @brief Gets the Enhanced Rx Fifo transfer status during a interrupt non-blocking receive.
*
* @param base FlexCAN peripheral base address.
* @param handle FlexCAN handle pointer.
* @param count Number of CAN messages receive so far by the non-blocking transaction.
* @retval kStatus_InvalidArgument count is Invalid.
* @retval kStatus_Success Successfully return the count.
*/
static inline status_t FLEXCAN_TransferGetReceiveEnhancedFifoCountEMDA(CAN_Type *base,
flexcan_edma_handle_t *handle,
size_t *count)
{
return FLEXCAN_TransferGetReceiveFifoCountEMDA(base, handle, count);
}
#endif
/*! @} */
#if defined(__cplusplus)
}
#endif
/*! @}*/
#endif /* FSL_FLEXCAN_EDMA_H_ */
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio.c
+78
View File
@@ -20,6 +20,12 @@
/*< @brief user configurable flexio handle count. */
#define FLEXIO_HANDLE_COUNT 2
#if defined(FLEXIO_RSTS)
#define FLEXIO_RESETS_ARRAY FLEXIO_RSTS
#elif defined(FLEXIO_RSTS_N)
#define FLEXIO_RESETS_ARRAY FLEXIO_RSTS_N
#endif
/*******************************************************************************
* Variables
******************************************************************************/
@@ -43,6 +49,11 @@ static flexio_isr_t s_flexioIsr[FLEXIO_HANDLE_COUNT];
/* FlexIO common IRQ Handler. */
static void FLEXIO_CommonIRQHandler(void);
#if defined(FLEXIO_RESETS_ARRAY)
/* Reset array */
static const reset_ip_name_t s_flexioResets[] = FLEXIO_RESETS_ARRAY;
#endif
/*******************************************************************************
* Codes
******************************************************************************/
@@ -96,6 +107,10 @@ void FLEXIO_Init(FLEXIO_Type *base, const flexio_config_t *userConfig)
CLOCK_EnableClock(s_flexioClocks[FLEXIO_GetInstance(base)]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
#if defined(FLEXIO_RESETS_ARRAY)
RESET_ReleasePeripheralReset(s_flexioResets[FLEXIO_GetInstance(base)]);
#endif
FLEXIO_Reset(base);
ctrlReg = base->CTRL;
@@ -396,6 +411,69 @@ static void FLEXIO_CommonIRQHandler(void)
SDK_ISR_EXIT_BARRIER;
}
#if defined(FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER) && FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER
/*!
* brief Configure a FLEXIO pin used by the board.
*
* To Config the FLEXIO PIN, define a pin configuration, as either input or output, in the user file.
* Then, call the FLEXIO_SetPinConfig() function.
*
* This is an example to define an input pin or an output pin configuration.
* code
* Define a digital input pin configuration,
* flexio_gpio_config_t config =
* {
* kFLEXIO_DigitalInput,
* 0U,
* kFLEXIO_FlagRisingEdgeEnable | kFLEXIO_InputInterruptEnable,
* }
* Define a digital output pin configuration,
* flexio_gpio_config_t config =
* {
* kFLEXIO_DigitalOutput,
* 0U,
* 0U
* }
* endcode
* param base FlexIO peripheral base address
* param pin FLEXIO pin number.
* param config FLEXIO pin configuration pointer.
*/
void FLEXIO_SetPinConfig(FLEXIO_Type *base, uint32_t pin, flexio_gpio_config_t *config)
{
assert(NULL != config);
IRQn_Type flexio_irqs[] = FLEXIO_IRQS;
if (config->pinDirection == kFLEXIO_DigitalInput)
{
base->PINOUTE &= ~(1UL << pin);
if (0U != (config->inputConfig & (uint8_t)kFLEXIO_InputInterruptEnable))
{
base->PINIEN = 1UL << pin;
/* Clear pending NVIC IRQ before enable NVIC IRQ. */
NVIC_ClearPendingIRQ(flexio_irqs[FLEXIO_GetInstance(base)]);
/* Enable interrupt in NVIC. */
(void)EnableIRQ(flexio_irqs[FLEXIO_GetInstance(base)]);
}
if (0U != (config->inputConfig & (uint8_t)kFLEXIO_FlagRisingEdgeEnable))
{
base->PINREN = 1UL << pin;
}
if (0U != (config->inputConfig & (uint8_t)kFLEXIO_FlagFallingEdgeEnable))
{
base->PINFEN = 1UL << pin;
}
}
else
{
FLEXIO_EnablePinOutput(base, pin);
FLEXIO_PinWrite(base, pin, config->outputLogic);
}
}
#endif /*FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER*/
void FLEXIO_DriverIRQHandler(void);
void FLEXIO_DriverIRQHandler(void)
{
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio.h
+194 -12
View File
@@ -5,8 +5,8 @@
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_FLEXIO_H_
#define _FSL_FLEXIO_H_
#ifndef FSL_FLEXIO_H_
#define FSL_FLEXIO_H_
#include "fsl_common.h"
@@ -20,10 +20,10 @@
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @{ */
/*! @brief FlexIO driver version. */
#define FSL_FLEXIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
/*@}*/
#define FSL_FLEXIO_DRIVER_VERSION (MAKE_VERSION(2, 2, 2))
/*! @} */
/*! @brief Calculate FlexIO timer trigger.*/
#define FLEXIO_TIMER_TRIGGER_SEL_PININPUT(x) ((uint32_t)(x) << 1U)
@@ -294,6 +294,38 @@ typedef struct _flexio_shifter_config
flexio_shifter_start_bit_t shifterStart; /*!< Shifter START bit. */
} flexio_shifter_config_t;
#if defined(FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER) && FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER
/*! @brief FLEXIO gpio direction definition */
typedef enum _flexio_gpio_direction
{
kFLEXIO_DigitalInput = 0U, /*!< Set current pin as digital input*/
kFLEXIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/
} flexio_gpio_direction_t;
/*! @brief FLEXIO gpio input config */
typedef enum _flexio_pin_input_config
{
kFLEXIO_InputInterruptDisabled = 0x0U, /*!< Interrupt request is disabled. */
kFLEXIO_InputInterruptEnable = 0x1U, /*!< Interrupt request is enable. */
kFLEXIO_FlagRisingEdgeEnable = 0x2U, /*!< Input pin flag on rising edge. */
kFLEXIO_FlagFallingEdgeEnable = 0x4U, /*!< Input pin flag on falling edge. */
} flexio_pin_input_config_t;
/*!
* @brief The FLEXIO pin configuration structure.
*
* Each pin can only be configured as either an output pin or an input pin at a time.
* If configured as an input pin, use inputConfig param.
* If configured as an output pin, use outputLogic.
*/
typedef struct _flexio_gpio_config
{
flexio_gpio_direction_t pinDirection; /*!< FLEXIO pin direction, input or output */
uint8_t outputLogic; /*!< Set a default output logic, which has no use in input */
uint8_t inputConfig; /*!< Set an input config */
} flexio_gpio_config_t;
#endif /*FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER*/
/*! @brief typedef for FlexIO simulated driver interrupt handler.*/
typedef void (*flexio_isr_t)(void *base, void *handle);
@@ -370,7 +402,7 @@ void FLEXIO_Deinit(FLEXIO_Type *base);
*/
uint32_t FLEXIO_GetInstance(FLEXIO_Type *base);
/* @} */
/*! @} */
/*!
* @name FlexIO Basic Operation
@@ -490,6 +522,7 @@ void FLEXIO_SetTimerConfig(FLEXIO_Type *base, uint8_t index, const flexio_timer_
* @brief This function set the value of the prescaler on flexio channels
*
* @param base Pointer to the FlexIO simulated peripheral type.
* @param index Timer index
* @param clocksource Set clock value
*/
static inline void FLEXIO_SetClockMode(FLEXIO_Type *base, uint8_t index, flexio_timer_decrement_source_t clocksource)
@@ -503,7 +536,7 @@ static inline void FLEXIO_SetClockMode(FLEXIO_Type *base, uint8_t index, flexio_
base->TIMCFG[index] = reg;
}
/* @} */
/*! @} */
/*!
* @name FlexIO Interrupt Operation
@@ -588,7 +621,7 @@ static inline void FLEXIO_DisableTimerStatusInterrupts(FLEXIO_Type *base, uint32
base->TIMIEN &= ~mask;
}
/* @} */
/*! @} */
/*!
* @name FlexIO Status Operation
@@ -667,7 +700,7 @@ static inline void FLEXIO_ClearTimerStatusFlags(FLEXIO_Type *base, uint32_t mask
base->TIMSTAT = mask;
}
/* @} */
/*! @} */
/*!
* @name FlexIO DMA Operation
@@ -725,11 +758,160 @@ status_t FLEXIO_RegisterHandleIRQ(void *base, void *handle, flexio_isr_t isr);
* @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range.
*/
status_t FLEXIO_UnregisterHandleIRQ(void *base);
/* @} */
/*! @} */
#if defined(FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER) && FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER
/*!
* @brief Configure a FLEXIO pin used by the board.
*
* To Config the FLEXIO PIN, define a pin configuration, as either input or output, in the user file.
* Then, call the FLEXIO_SetPinConfig() function.
*
* This is an example to define an input pin or an output pin configuration.
* @code
* Define a digital input pin configuration,
* flexio_gpio_config_t config =
* {
* kFLEXIO_DigitalInput,
* 0U,
* kFLEXIO_FlagRisingEdgeEnable | kFLEXIO_InputInterruptEnable,
* }
* Define a digital output pin configuration,
* flexio_gpio_config_t config =
* {
* kFLEXIO_DigitalOutput,
* 0U,
* 0U
* }
* @endcode
* @param base FlexIO peripheral base address
* @param pin FLEXIO pin number.
* @param config FLEXIO pin configuration pointer.
*/
void FLEXIO_SetPinConfig(FLEXIO_Type *base, uint32_t pin, flexio_gpio_config_t *config);
/*!
* @name GPIO Output Operations
* @{
*/
/*!
* @brief Sets the output level of the multiple FLEXIO pins to the logic 0.
*
* @param base FlexIO peripheral base address
* @param mask FLEXIO pin number mask
*/
static inline void FLEXIO_ClearPortOutput(FLEXIO_Type *base, uint32_t mask)
{
base->PINOUTCLR = mask;
}
/*!
* @brief Sets the output level of the multiple FLEXIO pins to the logic 1.
*
* @param base FlexIO peripheral base address
* @param mask FLEXIO pin number mask
*/
static inline void FLEXIO_SetPortOutput(FLEXIO_Type *base, uint32_t mask)
{
base->PINOUTSET = mask;
}
/*!
* @brief Reverses the current output logic of the multiple FLEXIO pins.
*
* @param base FlexIO peripheral base address
* @param mask FLEXIO pin number mask
*/
static inline void FLEXIO_TogglePortOutput(FLEXIO_Type *base, uint32_t mask)
{
base->PINOUTTOG = mask;
}
/*!
* @brief Sets the output level of the FLEXIO pins to the logic 1 or 0.
*
* @param base FlexIO peripheral base address
* @param pin FLEXIO pin number.
* @param output FLEXIO pin output logic level.
* - 0: corresponding pin output low-logic level.
* - 1: corresponding pin output high-logic level.
*/
static inline void FLEXIO_PinWrite(FLEXIO_Type *base, uint32_t pin, uint8_t output)
{
if (output == 0U)
{
FLEXIO_ClearPortOutput(base, 1UL << pin);
}
else
{
FLEXIO_SetPortOutput(base, 1UL << pin);
}
}
/*!
* @brief Enables the FLEXIO output pin function.
*
* @param base FlexIO peripheral base address
* @param pin FLEXIO pin number.
*/
static inline void FLEXIO_EnablePinOutput(FLEXIO_Type *base, uint32_t pin)
{
base->PINOUTE |= (1UL << pin);
}
/*! @} */
/*!
* @name FLEXIO PIN Input Operations
* @{
*/
/*!
* @brief Reads the current input value of the FLEXIO pin.
*
* @param base FlexIO peripheral base address
* @param pin FLEXIO pin number.
* @retval FLEXIO port input value
* - 0: corresponding pin input low-logic level.
* - 1: corresponding pin input high-logic level.
*/
static inline uint32_t FLEXIO_PinRead(FLEXIO_Type *base, uint32_t pin)
{
return (((base->PIN) >> pin) & 0x01U);
}
/*!
* @brief Gets the FLEXIO input pin status.
*
* @param base FlexIO peripheral base address
* @param pin FLEXIO pin number.
* @retval FLEXIO port input status
* - 0: corresponding pin input capture no status.
* - 1: corresponding pin input capture rising or falling edge.
*/
static inline uint32_t FLEXIO_GetPinStatus(FLEXIO_Type *base, uint32_t pin)
{
return (((base->PINSTAT) >> pin) & 0x01U);
}
/*!
* @brief Clears the multiple FLEXIO input pins status.
*
* @param base FlexIO peripheral base address
* @param mask FLEXIO pin number mask
*/
static inline void FLEXIO_ClearPortStatus(FLEXIO_Type *base, uint32_t mask)
{
base->PINSTAT = mask;
}
/*! @} */
#endif /*FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER*/
#if defined(__cplusplus)
}
#endif /*_cplusplus*/
/*@}*/
/*! @} */
#endif /*_FSL_FLEXIO_H_*/
#endif /*FSL_FLEXIO_H_*/
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_i2c_master.h
+11 -11
View File
@@ -5,8 +5,8 @@
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_FLEXIO_I2C_MASTER_H_
#define _FSL_FLEXIO_I2C_MASTER_H_
#ifndef FSL_FLEXIO_I2C_MASTER_H_
#define FSL_FLEXIO_I2C_MASTER_H_
#include "fsl_common.h"
#include "fsl_flexio.h"
@@ -21,9 +21,9 @@
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @{ */
#define FSL_FLEXIO_I2C_MASTER_DRIVER_VERSION (MAKE_VERSION(2, 5, 0))
/*@}*/
/*! @} */
/*! @brief Retry times for waiting flag. */
#ifndef I2C_RETRY_TIMES
@@ -207,7 +207,7 @@ static inline void FLEXIO_I2C_MasterEnable(FLEXIO_I2C_Type *base, bool enable)
}
}
/* @} */
/*! @} */
/*!
* @name Status
@@ -235,7 +235,7 @@ uint32_t FLEXIO_I2C_MasterGetStatusFlags(FLEXIO_I2C_Type *base);
void FLEXIO_I2C_MasterClearStatusFlags(FLEXIO_I2C_Type *base, uint32_t mask);
/*@}*/
/*! @} */
/*!
* @name Interrupts
@@ -260,7 +260,7 @@ void FLEXIO_I2C_MasterEnableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask);
*/
void FLEXIO_I2C_MasterDisableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask);
/*@}*/
/*! @} */
/*!
* @name Bus Operations
@@ -402,7 +402,7 @@ status_t FLEXIO_I2C_MasterReadBlocking(FLEXIO_I2C_Type *base, uint8_t *rxBuff, u
* @return status of status_t.
*/
status_t FLEXIO_I2C_MasterTransferBlocking(FLEXIO_I2C_Type *base, flexio_i2c_master_transfer_t *xfer);
/*@}*/
/*! @} */
/*Transactional APIs*/
@@ -475,11 +475,11 @@ void FLEXIO_I2C_MasterTransferAbort(FLEXIO_I2C_Type *base, flexio_i2c_master_han
*/
void FLEXIO_I2C_MasterTransferHandleIRQ(void *i2cType, void *i2cHandle);
/*@}*/
/*! @} */
#if defined(__cplusplus)
}
#endif /*_cplusplus*/
/*@}*/
/*! @} */
#endif /*_FSL_FLEXIO_I2C_MASTER_H_*/
#endif /*FSL_FLEXIO_I2C_MASTER_H_*/
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_mculcd.c
+65 -42
View File
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2021, 2022 NXP
* Copyright 2016-2023 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -117,7 +117,7 @@ void FLEXIO_MCULCD_GetDefaultConfig(flexio_mculcd_config_t *config)
* brief Set desired baud rate.
*
* param base Pointer to the FLEXIO_MCULCD_Type structure.
* param baudRate_Bps Desired baud rate.
* param baudRate_Bps Desired baud rate in bit-per-second for all data lines combined.
* param srcClock_Hz FLEXIO clock frequency in Hz.
* retval kStatus_Success Set successfully.
* retval kStatus_InvalidArgument Could not set the baud rate.
@@ -125,12 +125,13 @@ void FLEXIO_MCULCD_GetDefaultConfig(flexio_mculcd_config_t *config)
status_t FLEXIO_MCULCD_SetBaudRate(FLEXIO_MCULCD_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
{
uint32_t baudRateDiv;
uint32_t baudRatePerDataLine;
uint32_t timerCompare;
status_t status;
uint8_t baudRatio;
baudRatio = (FLEXIO_MCULCD_DATA_BUS_WIDTH == 16) ? 2 : 1;
baudRateDiv = (srcClock_Hz + 1) / (baudRate_Bps * baudRatio);
baudRatePerDataLine = baudRate_Bps / (uint32_t)FLEXIO_MCULCD_DATA_BUS_WIDTH;
baudRateDiv = (srcClock_Hz + baudRatePerDataLine) / (baudRatePerDataLine * 2U);
if ((0U == baudRateDiv) || (baudRateDiv > (FLEXIO_BAUDRATE_DIV_MASK + 1U)))
{
@@ -138,6 +139,8 @@ status_t FLEXIO_MCULCD_SetBaudRate(FLEXIO_MCULCD_Type *base, uint32_t baudRate_B
}
else
{
baudRateDiv--;
timerCompare = base->flexioBase->TIMCMP[base->timerIndex];
timerCompare = (timerCompare & ~FLEXIO_BAUDRATE_DIV_MASK) | baudRateDiv;
@@ -296,7 +299,7 @@ uint32_t FLEXIO_MCULCD_ReadData(FLEXIO_MCULCD_Type *base)
}
/*!
* brief Configures the FLEXIO MCULCD to multiple beats write mode.
* brief Configures the FLEXIO MCULCD to single beats write mode.
*
* At the begining multiple beats write operation, the FLEXIO MCULCD is configured to
* multiple beats write mode using this function. After write operation, the configuration
@@ -315,7 +318,7 @@ void FLEXIO_MCULCD_SetSingleBeatWriteConfig(FLEXIO_MCULCD_Type *base)
*/
uint32_t timerCompare;
uint32_t tempValue;
uint32_t timerControl;
/* Enable the TX Shifter output. */
base->flexioBase->SHIFTCFG[base->txShifterStartIndex] =
@@ -343,27 +346,23 @@ void FLEXIO_MCULCD_SetSingleBeatWriteConfig(FLEXIO_MCULCD_Type *base)
FLEXIO_TIMCFG_TIMENA(kFLEXIO_TimerEnableOnTriggerHigh) | FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitDisabled) |
FLEXIO_TIMCFG_TSTART(kFLEXIO_TimerStartBitDisabled);
/* FlexIO bug workaround, see RM register description. */
/* When initially configure the timer pin as output, the pin may be driven low causing glitch on bus.
Configure the pin as bidirection output first then perform a subsequent write to change to output to avoid the
issue. */
timerControl = FLEXIO_TIMCTL_TRGSEL(FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->txShifterStartIndex)) |
FLEXIO_TIMCTL_TRGPOL(kFLEXIO_TimerTriggerPolarityActiveLow) |
FLEXIO_TIMCTL_TRGSRC(kFLEXIO_TimerTriggerSourceInternal) |
FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigBidirectionOutputData) |
FLEXIO_TIMCTL_PINSEL(base->ENWRPinIndex) | FLEXIO_TIMCTL_PINPOL(kFLEXIO_PinActiveLow) |
FLEXIO_TIMCTL_TIMOD(kFLEXIO_TimerModeDual8BitBaudBit);
tempValue =
base->flexioBase->TIMCTL[base->timerIndex] =
FLEXIO_TIMCTL_TRGSEL(FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->txShifterStartIndex)) |
FLEXIO_TIMCTL_TRGPOL(kFLEXIO_TimerTriggerPolarityActiveLow) |
FLEXIO_TIMCTL_TRGSRC(kFLEXIO_TimerTriggerSourceInternal) | FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigBidirectionOutputData) |
FLEXIO_TIMCTL_TRGSRC(kFLEXIO_TimerTriggerSourceInternal) | FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigOutput) |
FLEXIO_TIMCTL_PINSEL(base->ENWRPinIndex) | FLEXIO_TIMCTL_PINPOL(kFLEXIO_PinActiveLow) |
FLEXIO_TIMCTL_TIMOD(kFLEXIO_TimerModeDual8BitBaudBit);
base->flexioBase->TIMCTL[base->timerIndex] = tempValue;
tempValue &= ~(FLEXIO_TIMCTL_PINCFG_MASK);
tempValue |= FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigOutput);
base->flexioBase->TIMCTL[base->timerIndex] = tempValue;
base->flexioBase->TIMCTL[base->timerIndex] = timerControl;
timerControl = (timerControl & ~FLEXIO_TIMCTL_PINCFG_MASK) | FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigOutput);
base->flexioBase->TIMCTL[base->timerIndex] = timerControl;
}
/*!
* brief Clear the FLEXIO MCULCD multiple beats write mode configuration.
* brief Clear the FLEXIO MCULCD single beats write mode configuration.
*
* Clear the write configuration set by ref FLEXIO_MCULCD_SetSingleBeatWriteConfig.
*
@@ -374,12 +373,10 @@ void FLEXIO_MCULCD_SetSingleBeatWriteConfig(FLEXIO_MCULCD_Type *base)
void FLEXIO_MCULCD_ClearSingleBeatWriteConfig(FLEXIO_MCULCD_Type *base)
{
/* Disable the timer. */
uint32_t tempValue = base->flexioBase->TIMCTL[base->timerIndex];
tempValue &= ~(FLEXIO_TIMCTL_PINCFG_MASK);
tempValue |= FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigBidirectionOutputData);
base->flexioBase->TIMCTL[base->timerIndex] = tempValue;
/* Set to bidirection output first then set to disable to avoid glitch on bus. */
base->flexioBase->TIMCTL[base->timerIndex] =
(base->flexioBase->TIMCTL[base->timerIndex] & ~FLEXIO_TIMCTL_PINCFG_MASK) |
FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigBidirectionOutputData);
base->flexioBase->TIMCTL[base->timerIndex] = 0U;
base->flexioBase->TIMCFG[base->timerIndex] = 0U;
/* Clear the timer flag. */
@@ -392,7 +389,7 @@ void FLEXIO_MCULCD_ClearSingleBeatWriteConfig(FLEXIO_MCULCD_Type *base)
}
/*!
* brief Configures the FLEXIO MCULCD to multiple beats read mode.
* brief Configures the FLEXIO MCULCD to single beats read mode.
*
* At the begining or multiple beats read operation, the FLEXIO MCULCD is configured
* to multiple beats read mode using this function. After read operation, the configuration
@@ -461,7 +458,7 @@ void FLEXIO_MCULCD_SetSingleBeatReadConfig(FLEXIO_MCULCD_Type *base)
}
/*!
* brief Clear the FLEXIO MCULCD multiple beats read mode configuration.
* brief Clear the FLEXIO MCULCD single beats read mode configuration.
*
* Clear the read configuration set by ref FLEXIO_MCULCD_SetSingleBeatReadConfig.
*
@@ -472,6 +469,10 @@ void FLEXIO_MCULCD_SetSingleBeatReadConfig(FLEXIO_MCULCD_Type *base)
void FLEXIO_MCULCD_ClearSingleBeatReadConfig(FLEXIO_MCULCD_Type *base)
{
/* Disable the timer. */
/* Set to bidirection output first then set to disable to avoid glitch on bus. */
base->flexioBase->TIMCTL[base->timerIndex] =
(base->flexioBase->TIMCTL[base->timerIndex] & ~FLEXIO_TIMCTL_PINCFG_MASK) |
FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigBidirectionOutputData);
base->flexioBase->TIMCTL[base->timerIndex] = 0U;
base->flexioBase->TIMCFG[base->timerIndex] = 0U;
/* Clear the timer flag. */
@@ -503,6 +504,7 @@ void FLEXIO_MCULCD_SetMultiBeatsWriteConfig(FLEXIO_MCULCD_Type *base)
*/
uint32_t timerCompare;
uint32_t timerControl;
uint8_t beats;
uint8_t i;
@@ -548,12 +550,19 @@ void FLEXIO_MCULCD_SetMultiBeatsWriteConfig(FLEXIO_MCULCD_Type *base)
FLEXIO_TIMCFG_TIMENA(kFLEXIO_TimerEnableOnTriggerHigh) | FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitDisabled) |
FLEXIO_TIMCFG_TSTART(kFLEXIO_TimerStartBitDisabled);
base->flexioBase->TIMCTL[base->timerIndex] =
FLEXIO_TIMCTL_TRGSEL(FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->txShifterEndIndex)) |
FLEXIO_TIMCTL_TRGPOL(kFLEXIO_TimerTriggerPolarityActiveLow) |
FLEXIO_TIMCTL_TRGSRC(kFLEXIO_TimerTriggerSourceInternal) | FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigOutput) |
FLEXIO_TIMCTL_PINSEL(base->ENWRPinIndex) | FLEXIO_TIMCTL_PINPOL(kFLEXIO_PinActiveLow) |
FLEXIO_TIMCTL_TIMOD(kFLEXIO_TimerModeDual8BitBaudBit);
/* When initially configure the timer pin as output, the pin may be driven low causing glitch on bus.
Configure the pin as bidirection output first then perform a subsequent write to change to output to avoid the
issue. */
timerControl = FLEXIO_TIMCTL_TRGSEL(FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->txShifterEndIndex)) |
FLEXIO_TIMCTL_TRGPOL(kFLEXIO_TimerTriggerPolarityActiveLow) |
FLEXIO_TIMCTL_TRGSRC(kFLEXIO_TimerTriggerSourceInternal) |
FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigBidirectionOutputData) |
FLEXIO_TIMCTL_PINSEL(base->ENWRPinIndex) | FLEXIO_TIMCTL_PINPOL(kFLEXIO_PinActiveLow) |
FLEXIO_TIMCTL_TIMOD(kFLEXIO_TimerModeDual8BitBaudBit);
base->flexioBase->TIMCTL[base->timerIndex] = timerControl;
timerControl = (timerControl & ~FLEXIO_TIMCTL_PINCFG_MASK) | FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigOutput);
base->flexioBase->TIMCTL[base->timerIndex] = timerControl;
}
/*!
@@ -571,6 +580,10 @@ void FLEXIO_MCULCD_ClearMultiBeatsWriteConfig(FLEXIO_MCULCD_Type *base)
uint32_t statusFlags = 0U;
/* Disable the timer. */
/* Set to bidirection output first then set to disable to avoid glitch on bus. */
base->flexioBase->TIMCTL[base->timerIndex] =
(base->flexioBase->TIMCTL[base->timerIndex] & ~FLEXIO_TIMCTL_PINCFG_MASK) |
FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigBidirectionOutputData);
base->flexioBase->TIMCTL[base->timerIndex] = 0U;
base->flexioBase->TIMCFG[base->timerIndex] = 0U;
/* Clear the timer flag. */
@@ -688,6 +701,10 @@ void FLEXIO_MCULCD_ClearMultiBeatsReadConfig(FLEXIO_MCULCD_Type *base)
uint32_t statusFlags = 0U;
/* Disable the timer. */
/* Set to bidirection output first then set to disable to avoid glitch on bus. */
base->flexioBase->TIMCTL[base->timerIndex] =
(base->flexioBase->TIMCTL[base->timerIndex] & ~FLEXIO_TIMCTL_PINCFG_MASK) |
FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigBidirectionOutputData);
base->flexioBase->TIMCTL[base->timerIndex] = 0U;
base->flexioBase->TIMCFG[base->timerIndex] = 0U;
/* Clear the timer flag. */
@@ -975,7 +992,10 @@ void FLEXIO_MCULCD_TransferBlocking(FLEXIO_MCULCD_Type *base, flexio_mculcd_tran
{
FLEXIO_MCULCD_StartTransfer(base);
FLEXIO_MCULCD_WriteCommandBlocking(base, xfer->command);
if (!xfer->dataOnly)
{
FLEXIO_MCULCD_WriteCommandBlocking(base, xfer->command);
}
if (xfer->dataSize > 0U)
{
@@ -1076,8 +1096,11 @@ status_t FLEXIO_MCULCD_TransferNonBlocking(FLEXIO_MCULCD_Type *base,
/* Assert the nCS. */
FLEXIO_MCULCD_StartTransfer(base);
/* Send the command. */
FLEXIO_MCULCD_WriteCommandBlocking(base, xfer->command);
if (!xfer->dataOnly)
{
/* Send the command. */
FLEXIO_MCULCD_WriteCommandBlocking(base, xfer->command);
}
/* If transfer count is 0 (only to send command), return directly. */
if (0U == xfer->dataSize)
@@ -1308,4 +1331,4 @@ void FLEXIO_MCULCD_TransferHandleIRQ(void *base, void *handle)
statusFlags = FLEXIO_MCULCD_GetStatusFlags(flexioLcdMcuBase);
}
}
}
}
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_mculcd.h
+18 -17
View File
@@ -1,13 +1,13 @@
/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2021, 2022 NXP
* Copyright 2016-2023 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_FLEXIO_MCULCD_H_
#define _FSL_FLEXIO_MCULCD_H_
#ifndef FSL_FLEXIO_MCULCD_H_
#define FSL_FLEXIO_MCULCD_H_
#include "fsl_common.h"
#include "fsl_flexio.h"
@@ -22,10 +22,10 @@
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @{ */
/*! @brief FlexIO MCULCD driver version. */
#define FSL_FLEXIO_MCULCD_DRIVER_VERSION (MAKE_VERSION(2, 0, 7))
/*@}*/
#define FSL_FLEXIO_MCULCD_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
/*! @} */
#ifndef FLEXIO_MCULCD_WAIT_COMPLETE_TIME
/*!
@@ -129,7 +129,7 @@ typedef struct _flexio_mculcd_config
bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers,
fast access requires the FlexIO clock to be at least
twice the frequency of the bus clock. */
uint32_t baudRate_Bps; /*!< Baud rate in Bps. */
uint32_t baudRate_Bps; /*!< Baud rate in bit-per-second for all data lines combined. */
} flexio_mculcd_config_t;
/*! @brief Transfer mode.*/
@@ -144,11 +144,12 @@ typedef enum _flexio_mculcd_transfer_mode
typedef struct _flexio_mculcd_transfer
{
uint32_t command; /*!< Command to send. */
flexio_mculcd_transfer_mode_t mode; /*!< Transfer mode. */
uint32_t dataAddrOrSameValue; /*!< When sending the same value for many times,
this is the value to send. When writing or reading array,
this is the address of the data array. */
size_t dataSize; /*!< How many bytes to transfer. */
flexio_mculcd_transfer_mode_t mode; /*!< Transfer mode. */
bool dataOnly; /*!< Send data only when tx without the command. */
} flexio_mculcd_transfer_t;
/*! @brief typedef for flexio_mculcd_handle_t in advance. */
@@ -229,7 +230,7 @@ void FLEXIO_MCULCD_Deinit(FLEXIO_MCULCD_Type *base);
*/
void FLEXIO_MCULCD_GetDefaultConfig(flexio_mculcd_config_t *config);
/*@}*/
/*! @} */
/*!
* @name Status
@@ -257,7 +258,7 @@ uint32_t FLEXIO_MCULCD_GetStatusFlags(FLEXIO_MCULCD_Type *base);
*/
void FLEXIO_MCULCD_ClearStatusFlags(FLEXIO_MCULCD_Type *base, uint32_t mask);
/*@}*/
/*! @} */
/*!
* @name Interrupts
@@ -286,7 +287,7 @@ void FLEXIO_MCULCD_EnableInterrupts(FLEXIO_MCULCD_Type *base, uint32_t mask);
*/
void FLEXIO_MCULCD_DisableInterrupts(FLEXIO_MCULCD_Type *base, uint32_t mask);
/*@}*/
/*! @} */
/*!
* @name DMA Control
@@ -343,7 +344,7 @@ static inline uint32_t FLEXIO_MCULCD_GetRxDataRegisterAddress(FLEXIO_MCULCD_Type
return (uint32_t) & (base->flexioBase->SHIFTBUF[base->rxShifterStartIndex]);
}
/*@}*/
/*! @} */
/*!
* @name Bus Operations
@@ -354,7 +355,7 @@ static inline uint32_t FLEXIO_MCULCD_GetRxDataRegisterAddress(FLEXIO_MCULCD_Type
* @brief Set desired baud rate.
*
* @param base Pointer to the FLEXIO_MCULCD_Type structure.
* @param baudRate_Bps Desired baud rate.
* @param baudRate_Bps Desired baud rate in bit-per-second for all data lines combined.
* @param srcClock_Hz FLEXIO clock frequency in Hz.
* @retval kStatus_Success Set successfully.
* @retval kStatus_InvalidArgument Could not set the baud rate.
@@ -602,7 +603,7 @@ void FLEXIO_MCULCD_WriteSameValueBlocking(FLEXIO_MCULCD_Type *base, uint32_t sam
* @param xfer pointer to flexio_mculcd_transfer_t structure.
*/
void FLEXIO_MCULCD_TransferBlocking(FLEXIO_MCULCD_Type *base, flexio_mculcd_transfer_t *xfer);
/*@}*/
/*! @} */
/*!
* @name Transactional
@@ -675,11 +676,11 @@ status_t FLEXIO_MCULCD_TransferGetCount(FLEXIO_MCULCD_Type *base, flexio_mculcd_
*/
void FLEXIO_MCULCD_TransferHandleIRQ(void *base, void *handle);
/*@}*/
/*! @} */
#if defined(__cplusplus)
}
#endif /*_cplusplus*/
/*@}*/
/*! @} */
#endif /*_FSL_FLEXIO_MCULCD_H_*/
#endif /*FSL_FLEXIO_MCULCD_H_*/
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_mculcd_edma.c
+7 -99
View File
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2019 NXP
* Copyright 2016-2019,2023 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -460,8 +460,12 @@ status_t FLEXIO_MCULCD_TransferEDMA(FLEXIO_MCULCD_Type *base,
/* Setup DMA to transfer data. */
/* Assert the nCS. */
FLEXIO_MCULCD_StartTransfer(base);
/* Send the command. */
FLEXIO_MCULCD_WriteCommandBlocking(base, xfer->command);
if (!xfer->dataOnly)
{
/* Send the command. */
FLEXIO_MCULCD_WriteCommandBlocking(base, xfer->command);
}
/* Setup the DMA configuration. */
FLEXIO_MCULCD_EDMAConfig(base, handle);
@@ -494,102 +498,6 @@ status_t FLEXIO_MCULCD_TransferEDMA(FLEXIO_MCULCD_Type *base,
return kStatus_Success;
}
/*!
* brief Performs a non-blocking FlexIO MCULCD data write using eDMA.
*
* This function returns immediately after transfer initiates. To check whether
* the transfer is completed, user could:
* 1. Use the transfer completed callback;
* 2. Polling function ref FLEXIO_MCULCD_GetTransferCountEDMA
*
* param base pointer to FLEXIO_MCULCD_Type structure.
* param handle pointer to flexio_mculcd_edma_handle_t structure to store the
* transfer state.
* param data Pointer to data.
* param size Size(in bytes) of the data
* retval kStatus_Success Successfully start a transfer.
* retval kStatus_InvalidArgument Input argument is invalid.
* retval kStatus_FLEXIO_MCULCD_Busy FlexIO MCULCD is not idle, it is running another
* transfer.
*/
status_t FLEXIO_MCULCD_WriteDataEDMA(FLEXIO_MCULCD_Type *base,
flexio_mculcd_edma_handle_t *handle,
const void *data, size_t size)
{
assert(NULL != handle);
assert(NULL != data);
/*
* The data transfer mechanism:
*
* Read:
* Assume the data length is Lr = (n1 * minorLoopBytes + n2), where
* n2 < minorLoopBytes.
* If (n1 <= 1), then all data are sent using blocking method.
* If (n1 > 1), then the beginning ((n1-1) * minorLoopBytes) are read
* using DMA, the left (minorLoopBytes + n2) are read using blocking method.
*
* Write:
* Assume the data length is Lw = (n1 * minorLoopBytes + n2), where
* n2 < minorLoopBytes.
* If (n1 = 0), then all data are sent using blocking method.
* If (n1 >= 1), then the beginning (n1 * minorLoopBytes) are sent
* using DMA, the left n2 are sent using blocking method.
*/
/* Check if the device is busy. */
if ((uint32_t)kFLEXIO_MCULCD_StateIdle != handle->state)
{
return kStatus_FLEXIO_MCULCD_Busy;
}
/* Set the state in handle. */
handle->minorLoopBytes = handle->txShifterNum * 4UL;
handle->state = (uint32_t)kFLEXIO_MCULCD_StateWriteArray;
/*
* For TX, if data is less than one minor loop, then use polling method.
* For RX, if data is less than two minor loop, then use polling method.
*/
if (size < handle->minorLoopBytes)
{
FLEXIO_MCULCD_WriteDataArrayBlocking(base, data, size);
handle->state = (uint32_t)kFLEXIO_MCULCD_StateIdle;
/* Callback to inform upper layer. */
if (NULL != handle->completionCallback)
{
handle->completionCallback(base, handle, kStatus_FLEXIO_MCULCD_Idle, handle->userData);
}
}
else
{
handle->dataCount = size;
handle->remainingCount = size;
handle->dataAddrOrSameValue = (uint32_t)data;
/* Setup DMA to transfer data. */
/* Assert the nCS. */
FLEXIO_MCULCD_StartTransfer(base);
/* Setup the DMA configuration. */
FLEXIO_MCULCD_EDMAConfig(base, handle);
/* Start the transfer. */
/* For 6800, de-assert the RDWR pin. */
if (kFLEXIO_MCULCD_6800 == base->busType)
{
base->setRDWRPin(false);
}
FLEXIO_MCULCD_SetMultiBeatsWriteConfig(base);
FLEXIO_MCULCD_EnableTxDMA(base, true);
EDMA_StartTransfer(handle->txDmaHandle);
}
return kStatus_Success;
}
/*!
* brief Aborts a FlexIO MCULCD transfer using eDMA.
*
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_mculcd_edma.h
+7 -28
View File
@@ -1,13 +1,13 @@
/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2020 NXP
* Copyright 2016-2020,2023 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_FLEXIO_MCULCD_EDMA_H_
#define _FSL_FLEXIO_MCULCD_EDMA_H_
#ifndef FSL_FLEXIO_MCULCD_EDMA_H_
#define FSL_FLEXIO_MCULCD_EDMA_H_
#include "fsl_edma.h"
#include "fsl_flexio_mculcd.h"
@@ -21,10 +21,10 @@
* Definitions
******************************************************************************/
/*@{*/
/*! @{ */
/*! @brief FlexIO MCULCD EDMA driver version. */
#define FSL_FLEXIO_MCULCD_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 4))
/*@}*/
#define FSL_FLEXIO_MCULCD_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 5))
/*! @} */
/*! @brief typedef for flexio_mculcd_edma_handle_t in advance. */
typedef struct _flexio_mculcd_edma_handle flexio_mculcd_edma_handle_t;
@@ -119,27 +119,6 @@ status_t FLEXIO_MCULCD_TransferCreateHandleEDMA(FLEXIO_MCULCD_Type *base,
status_t FLEXIO_MCULCD_TransferEDMA(FLEXIO_MCULCD_Type *base,
flexio_mculcd_edma_handle_t *handle,
flexio_mculcd_transfer_t *xfer);
/*!
* brief Performs a non-blocking FlexIO MCULCD data write using eDMA.
*
* This function returns immediately after transfer initiates. To check whether
* the transfer is completed, user could:
* 1. Use the transfer completed callback;
* 2. Polling function ref FLEXIO_MCULCD_GetTransferCountEDMA
*
* param base pointer to FLEXIO_MCULCD_Type structure.
* param handle pointer to flexio_mculcd_edma_handle_t structure to store the
* transfer state.
* param data Pointer to data.
* param size Size(in bytes) of the data
* retval kStatus_Success Successfully start a transfer.
* retval kStatus_InvalidArgument Input argument is invalid.
* retval kStatus_FLEXIO_MCULCD_Busy FlexIO MCULCD is not idle, it is running another
* transfer.
*/
status_t FLEXIO_MCULCD_WriteDataEDMA(FLEXIO_MCULCD_Type *base,
flexio_mculcd_edma_handle_t *handle,
const void *data, size_t size);
/*!
* @brief Aborts a FlexIO MCULCD transfer using eDMA.
@@ -171,4 +150,4 @@ status_t FLEXIO_MCULCD_TransferGetCountEDMA(FLEXIO_MCULCD_Type *base,
/*!
* @}
*/
#endif /* _FSL_FLEXIO_MCULCD_EDMA_H_ */
#endif /* FSL_FLEXIO_MCULCD_EDMA_H_ */
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_mculcd_smartdma.c
+407
View File
@@ -0,0 +1,407 @@
/*
* Copyright 2019-2021,2023 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_flexio_mculcd_smartdma.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.flexio_mculcd_smartdma"
#endif
#define FLEXIO_MCULCD_SMARTDMA_TX_START_SHIFTER 0U
#define FLEXIO_MCULCD_SMARTDMA_TX_END_SHIFTER 7U
#define FLEXIO_MCULCD_SMARTDMA_TX_SHIFTER_NUM \
(FLEXIO_MCULCD_SMARTDMA_TX_END_SHIFTER - FLEXIO_MCULCD_SMARTDMA_TX_START_SHIFTER + 1)
enum _MCULCD_transfer_state
{
kFLEXIO_MCULCD_StateIdle, /*!< No transfer in progress. */
kFLEXIO_MCULCD_StateReadArray, /*!< Reading array in progress. */
kFLEXIO_MCULCD_StateWriteArray, /*!< Writing array in progress. */
kFLEXIO_MCULCD_StateWriteSameValue, /*!< Writing the same value in progress.
*/
};
/*******************************************************************************
* Prototypes
******************************************************************************/
/*!
* @brief Get the TX chunk size.
*
* The SMARTDMA TX transfer memory must be 4Byte aligned, the transfer size must
* be multiple of 64Byte. So the transfer data is devided in to three part:
* part1 + part2 + part3.
* The part2 is transfered using SMARTDMA, it should be 4Byte aligned, multiple
* of 64Byte.
* The part1 and part3 are transfered using blocking method, each of them is
* less than 64Byte, and total of them is less than (64 + 4) bytes.
*
* This function gets the size of each part.
*
* @param totalLen The total TX size in byte.
* @param startAddr The start address of the TX data.
* @param part1Len Length of the part 1 in byte.
* @param part2Len Length of the part 2 in byte.
* @param part3Len Length of the part 3 in byte.
*/
static void FLEXIO_MCULCD_SMARTDMA_GetTxChunkLen(
uint32_t totalLen, uint32_t startAddr, uint32_t *part1Len, uint32_t *part2Len, uint32_t *part3Len);
/*!
* @brief Convert RGB565 to RGB888.
*
* @param rgb565 Input RGB565.
* @param pixelCount Pixel count.
* @param rgb888 Output RGB888.
*/
static void FLEXIO_MCULCD_RGB656ToRGB888(const uint16_t *rgb565, uint32_t pixelCount, uint8_t *rgb888);
/*!
* @brief Callback function registered to SMARTDMA driver.
*/
static void FLEXIO_MCULCD_SMARTDMA_Callback(void *param);
/*******************************************************************************
* Variables
******************************************************************************/
/*******************************************************************************
* Code
******************************************************************************/
static void FLEXIO_MCULCD_SMARTDMA_GetTxChunkLen(
uint32_t totalLen, uint32_t startAddr, uint32_t *part1Len, uint32_t *part2Len, uint32_t *part3Len)
{
if (totalLen < FLEXIO_MCULCD_SMARTDMA_TX_LEN_ALIGN)
{
*part1Len = totalLen;
*part2Len = 0;
*part3Len = 0;
}
else
{
*part3Len = (startAddr + totalLen) & (FLEXIO_MCULCD_SMARTDMA_TX_ADDR_ALIGN - 1U);
*part2Len = ((uint32_t)(totalLen - *part3Len)) & (~(FLEXIO_MCULCD_SMARTDMA_TX_LEN_ALIGN - 1U));
if (FLEXIO_MCULCD_SMARTDMA_TX_LEN_ALIGN > *part2Len)
{
*part1Len = totalLen;
*part2Len = 0;
*part3Len = 0;
}
else
{
*part1Len = totalLen - *part2Len - *part3Len;
}
}
}
static void FLEXIO_MCULCD_RGB656ToRGB888(const uint16_t *rgb565, uint32_t pixelCount, uint8_t *rgb888)
{
while ((pixelCount--) != 0U)
{
*rgb888 = (uint8_t)(((*rgb565) & 0x001FU) << 3U);
rgb888++;
*rgb888 = (uint8_t)(((*rgb565) & 0x07E0U) >> 3U);
rgb888++;
*rgb888 = (uint8_t)(((*rgb565) & 0xF800U) >> 8U);
rgb888++;
rgb565++;
}
}
/*!
* brief Initializes the FLEXO MCULCD master SMARTDMA handle.
*
* This function initializes the FLEXO MCULCD master SMARTDMA handle which can be
* used for other FLEXO MCULCD transactional APIs. For a specified FLEXO MCULCD
* instance, call this API once to get the initialized handle.
*
* param base Pointer to FLEXIO_MCULCD_Type structure.
* param handle Pointer to flexio_mculcd_smartdma_handle_t structure to store the
* transfer state.
* param config Pointer to the configuration.
* param callback MCULCD transfer complete callback, NULL means no callback.
* param userData callback function parameter.
* retval kStatus_Success Successfully create the handle.
*/
status_t FLEXIO_MCULCD_TransferCreateHandleSMARTDMA(FLEXIO_MCULCD_Type *base,
flexio_mculcd_smartdma_handle_t *handle,
const flexio_mculcd_smartdma_config_t *config,
flexio_mculcd_smartdma_transfer_callback_t callback,
void *userData)
{
assert(handle != NULL);
/* The SMARTDMA firmware only support TX using shifter 0 to shifter 7 */
if (base->txShifterStartIndex != FLEXIO_MCULCD_SMARTDMA_TX_START_SHIFTER)
{
return kStatus_InvalidArgument;
}
if (base->txShifterEndIndex != FLEXIO_MCULCD_SMARTDMA_TX_END_SHIFTER)
{
return kStatus_InvalidArgument;
}
/* Zero the handle. */
(void)memset(handle, 0, sizeof(*handle));
if (NULL == config)
{
handle->smartdmaApi = (uint8_t)kSMARTDMA_FlexIO_DMA;
}
else
{
if (config->inputPixelFormat == config->outputPixelFormat)
{
handle->smartdmaApi = (uint8_t)kSMARTDMA_FlexIO_DMA;
}
else if (((config->inputPixelFormat == kFLEXIO_MCULCD_RGB565) &&
(config->outputPixelFormat == kFLEXIO_MCULCD_RGB888)) ||
((config->inputPixelFormat == kFLEXIO_MCULCD_BGR565) &&
(config->outputPixelFormat == kFLEXIO_MCULCD_BGR888)))
{
handle->smartdmaApi = (uint8_t)kSMARTDMA_FlexIO_DMA_RGB565To888;
handle->needColorConvert = true;
}
else
{
return kStatus_InvalidArgument;
}
}
/* Initialize the state. */
handle->state = (uint32_t)kFLEXIO_MCULCD_StateIdle;
/* Register callback and userData. */
handle->completionCallback = callback;
handle->userData = userData;
handle->base = base;
SMARTDMA_InstallFirmware(SMARTDMA_DISPLAY_MEM_ADDR, s_smartdmaDisplayFirmware, SMARTDMA_DISPLAY_FIRMWARE_SIZE);
SMARTDMA_InstallCallback(FLEXIO_MCULCD_SMARTDMA_Callback, handle);
/* The shifter interrupt is used by the SMARTDMA. */
FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, (1UL << FLEXIO_MCULCD_SMARTDMA_TX_END_SHIFTER));
#if (defined(SMARTDMA_USE_FLEXIO_SHIFTER_DMA) && SMARTDMA_USE_FLEXIO_SHIFTER_DMA)
FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1UL, true);
#endif
return kStatus_Success;
}
/*!
* brief Performs a non-blocking FlexIO MCULCD transfer using SMARTDMA.
*
* This function returns immediately after transfer initiates. Use the callback
* function to check whether the transfer is completed.
*
* param base pointer to FLEXIO_MCULCD_Type structure.
* param handle pointer to flexio_mculcd_smartdma_handle_t structure to store the
* transfer state.
* param xfer Pointer to FlexIO MCULCD transfer structure.
* retval kStatus_Success Successfully start a transfer.
* retval kStatus_InvalidArgument Input argument is invalid.
* retval kStatus_FLEXIO_MCULCD_Busy FlexIO MCULCD is not idle, it is running another
* transfer.
*/
status_t FLEXIO_MCULCD_TransferSMARTDMA(FLEXIO_MCULCD_Type *base,
flexio_mculcd_smartdma_handle_t *handle,
flexio_mculcd_transfer_t *xfer)
{
assert(handle != NULL);
assert(xfer != NULL);
uint32_t part1Len, part2Len, part3Len;
/* Check if the device is busy. */
if ((uint32_t)kFLEXIO_MCULCD_StateIdle != handle->state)
{
return kStatus_FLEXIO_MCULCD_Busy;
}
/* Only support write array. */
if (kFLEXIO_MCULCD_WriteArray != xfer->mode)
{
return kStatus_InvalidArgument;
}
FLEXIO_MCULCD_SMARTDMA_GetTxChunkLen(xfer->dataSize, xfer->dataAddrOrSameValue, &part1Len, &part2Len, &part3Len);
handle->state = (uint32_t)kFLEXIO_MCULCD_StateWriteArray;
/* Start transfer. */
handle->remainingCount = xfer->dataSize;
handle->dataCount = xfer->dataSize;
handle->dataAddrOrSameValue = xfer->dataAddrOrSameValue;
/* Assert the nCS. */
FLEXIO_MCULCD_StartTransfer(base);
if (!xfer->dataOnly)
{
/* Send the command. */
FLEXIO_MCULCD_WriteCommandBlocking(base, xfer->command);
}
if (part1Len > 0U)
{
if (handle->needColorConvert)
{
FLEXIO_MCULCD_RGB656ToRGB888((uint16_t *)xfer->dataAddrOrSameValue, part1Len >> 1U,
handle->blockingXferBuffer);
FLEXIO_MCULCD_WriteDataArrayBlocking(base, handle->blockingXferBuffer, (part1Len >> 1U) * 3U);
}
else
{
FLEXIO_MCULCD_WriteDataArrayBlocking(base, (void *)(uint8_t *)xfer->dataAddrOrSameValue, (size_t)part1Len);
}
handle->remainingCount -= part1Len;
handle->dataAddrOrSameValue += part1Len;
}
if (0U == part2Len)
{
/* In this case, all data are sent out as part 1. Only notify upper layer here. */
FLEXIO_MCULCD_StopTransfer(base);
handle->state = (uint32_t)kFLEXIO_MCULCD_StateIdle;
/* Callback to inform upper layer. */
if (NULL != handle->completionCallback)
{
handle->completionCallback(base, handle, kStatus_FLEXIO_MCULCD_Idle, handle->userData);
}
}
else
{
/* For 6800, de-assert the RDWR pin. */
if (kFLEXIO_MCULCD_6800 == base->busType)
{
base->setRDWRPin(false);
}
FLEXIO_MCULCD_SetMultiBeatsWriteConfig(base);
/* Save the part 3 information. */
handle->dataCountUsingEzh = part2Len;
handle->dataAddrOrSameValue += part2Len;
/* The part 3 is transfered using blocking method in ISR, convert the color
to save time in ISR. */
if ((0U != part3Len) && (handle->needColorConvert))
{
FLEXIO_MCULCD_RGB656ToRGB888((uint16_t *)xfer->dataAddrOrSameValue, part3Len >> 1U,
handle->blockingXferBuffer);
}
handle->smartdmaParam.p_buffer = (uint32_t *)(xfer->dataAddrOrSameValue + part1Len);
handle->smartdmaParam.buffersize = part2Len;
handle->smartdmaParam.smartdma_stack = handle->smartdmaStack;
SMARTDMA_Reset();
SMARTDMA_Boot(handle->smartdmaApi, &(handle->smartdmaParam), 0);
}
return kStatus_Success;
}
/*!
* brief Aborts a FlexIO MCULCD transfer using SMARTDMA.
*
* param base pointer to FLEXIO_MCULCD_Type structure.
* param handle FlexIO MCULCD SMARTDMA handle pointer.
*/
void FLEXIO_MCULCD_TransferAbortSMARTDMA(FLEXIO_MCULCD_Type *base, flexio_mculcd_smartdma_handle_t *handle)
{
assert(handle != NULL);
SMARTDMA_Reset();
/* Set the handle state. */
handle->state = (uint32_t)kFLEXIO_MCULCD_StateIdle;
handle->dataCount = 0;
}
/*!
* brief Gets the remaining bytes for FlexIO MCULCD SMARTDMA transfer.
*
* param base pointer to FLEXIO_MCULCD_Type structure.
* param handle FlexIO MCULCD SMARTDMA handle pointer.
* param count Number of count transferred so far by the SMARTDMA transaction.
* retval kStatus_Success Get the transferred count Successfully.
* retval kStatus_NoTransferInProgress No transfer in process.
*/
status_t FLEXIO_MCULCD_TransferGetCountSMARTDMA(FLEXIO_MCULCD_Type *base,
flexio_mculcd_smartdma_handle_t *handle,
size_t *count)
{
assert(handle != NULL);
assert(count != NULL);
uint32_t state = handle->state;
if ((uint32_t)kFLEXIO_MCULCD_StateIdle == state)
{
return kStatus_NoTransferInProgress;
}
else
{
*count = handle->dataCount - handle->remainingCount;
}
return kStatus_Success;
}
static void FLEXIO_MCULCD_SMARTDMA_Callback(void *param)
{
flexio_mculcd_smartdma_handle_t *flexioMculcdSmartDmaHandle = (flexio_mculcd_smartdma_handle_t *)param;
FLEXIO_MCULCD_Type *flexioLcdMcuBase = flexioMculcdSmartDmaHandle->base;
FLEXIO_MCULCD_WaitTransmitComplete();
/* Disable the TX shifter and the timer. */
FLEXIO_MCULCD_ClearMultiBeatsWriteConfig(flexioLcdMcuBase);
flexioMculcdSmartDmaHandle->remainingCount -= flexioMculcdSmartDmaHandle->dataCountUsingEzh;
/* Send the part 3 */
if (0U != flexioMculcdSmartDmaHandle->remainingCount)
{
if (flexioMculcdSmartDmaHandle->needColorConvert)
{
FLEXIO_MCULCD_WriteDataArrayBlocking(flexioLcdMcuBase, flexioMculcdSmartDmaHandle->blockingXferBuffer,
(flexioMculcdSmartDmaHandle->remainingCount >> 1U) * 3U);
}
else
{
FLEXIO_MCULCD_WriteDataArrayBlocking(flexioLcdMcuBase,
(void *)(uint8_t *)flexioMculcdSmartDmaHandle->dataAddrOrSameValue,
flexioMculcdSmartDmaHandle->remainingCount);
}
}
flexioMculcdSmartDmaHandle->remainingCount = 0;
FLEXIO_MCULCD_StopTransfer(flexioLcdMcuBase);
flexioMculcdSmartDmaHandle->state = (uint32_t)kFLEXIO_MCULCD_StateIdle;
/* Callback to inform upper layer. */
if (NULL != flexioMculcdSmartDmaHandle->completionCallback)
{
flexioMculcdSmartDmaHandle->completionCallback(flexioLcdMcuBase, flexioMculcdSmartDmaHandle,
kStatus_FLEXIO_MCULCD_Idle,
flexioMculcdSmartDmaHandle->userData);
}
}

Some files were not shown because too many files have changed in this diff Show More