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bsp: nxp/mcxn947: Updated SDK to release v2.16.000

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Signed-off-by: Yilin Sun <imi415@imi.moe>
This commit is contained in:
Yilin Sun authored and Meco Man committed 2024-08-16 20:20:13 -04:00
1 parent 0864456947
commit e6cf0bc97d
191 files changed
+52522 -41105
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bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/MCXN947_cm33_core0.h
+9661 -15308
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bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/MCXN947_cm33_core0_features.h
+296 -119
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bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/MCXN947_cm33_core1.h
+9661 -15308
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bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/MCXN947_cm33_core1_features.h
+296 -119
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bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/arm/startup_MCXN947_cm33_core0.S
+74 -76
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bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/arm/startup_MCXN947_cm33_core1.S
+74 -76
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bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cache.c
+91 -82
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bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cache.h
+16 -16
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@@ -1,12 +1,12 @@
/*
* Copyright 2016-2021 NXP
* Copyright 2016-2021, 2023 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_CACHE_H_
#define _FSL_CACHE_H_
#ifndef FSL_CACHE_H_
#define FSL_CACHE_H_
#include "fsl_common.h"
@@ -20,10 +20,10 @@
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @{ */
/*! @brief cache driver version. */
#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 6))
/*@}*/
#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 7))
/*! @} */
/*! @brief cache line size. */
#define CACHE64_LINESIZE_BYTE (FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE)
@@ -138,7 +138,7 @@ void CACHE64_InvalidateCache(CACHE64_CTRL_Type *base);
* @brief Invalidates cache by range.
*
* @param address The physical address of cache.
* @param size_byte size of the memory to be invalidated.
* @param size_byte size of the memory to be invalidated, should be larger than 0.
* @note Address and size should be aligned to "CACHE64_LINESIZE_BYTE".
* The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if
* startAddr is not aligned. For the size_byte, application should make sure the
@@ -158,7 +158,7 @@ void CACHE64_CleanCache(CACHE64_CTRL_Type *base);
* @brief Cleans cache by range.
*
* @param address The physical address of cache.
* @param size_byte size of the memory to be cleaned.
* @param size_byte size of the memory to be cleaned, should be larger than 0.
* @note Address and size should be aligned to "CACHE64_LINESIZE_BYTE".
* The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if
* startAddr is not aligned. For the size_byte, application should make sure the
@@ -178,7 +178,7 @@ void CACHE64_CleanInvalidateCache(CACHE64_CTRL_Type *base);
* @brief Cleans and invalidate cache by range.
*
* @param address The physical address of cache.
* @param size_byte size of the memory to be Cleaned and Invalidated.
* @param size_byte size of the memory to be Cleaned and Invalidated, should be larger than 0.
* @note Address and size should be aligned to "CACHE64_LINESIZE_BYTE".
* The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if
* startAddr is not aligned. For the size_byte, application should make sure the
@@ -198,7 +198,7 @@ void CACHE64_CleanInvalidateCacheByRange(uint32_t address, uint32_t size_byte);
void CACHE64_EnableWriteBuffer(CACHE64_CTRL_Type *base, bool enable);
#endif
/*@}*/
/*! @} */
/*!
* @name Unified Cache Control for all caches
@@ -209,7 +209,7 @@ void CACHE64_EnableWriteBuffer(CACHE64_CTRL_Type *base, bool enable);
* @brief Invalidates instruction cache by range.
*
* @param address The physical address.
* @param size_byte size of the memory to be invalidated.
* @param size_byte size of the memory to be invalidated, should be larger than 0.
* @note Address and size should be aligned to CACHE64_LINESIZE_BYTE due to the cache operation unit
* FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line
* size if startAddr is not aligned. For the size_byte, application should make sure the
@@ -224,7 +224,7 @@ static inline void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte
* @brief Invalidates data cache by range.
*
* @param address The physical address.
* @param size_byte size of the memory to be invalidated.
* @param size_byte size of the memory to be invalidated, should be larger than 0.
* @note Address and size should be aligned to CACHE64_LINESIZE_BYTE due to the cache operation unit
* FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line
* size if startAddr is not aligned. For the size_byte, application should make sure the
@@ -239,7 +239,7 @@ static inline void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte
* @brief Clean data cache by range.
*
* @param address The physical address.
* @param size_byte size of the memory to be cleaned.
* @param size_byte size of the memory to be cleaned, should be larger than 0.
* @note Address and size should be aligned to CACHE64_LINESIZE_BYTE due to the cache operation unit
* FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line
* size if startAddr is not aligned. For the size_byte, application should make sure the
@@ -254,7 +254,7 @@ static inline void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte)
* @brief Cleans and Invalidates data cache by range.
*
* @param address The physical address.
* @param size_byte size of the memory to be Cleaned and Invalidated.
* @param size_byte size of the memory to be Cleaned and Invalidated, should be larger than 0.
* @note Address and size should be aligned to CACHE64_LINESIZE_BYTE due to the cache operation unit
* FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line
* size if startAddr is not aligned. For the size_byte, application should make sure the
@@ -265,7 +265,7 @@ static inline void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size
CACHE64_CleanInvalidateCacheByRange(address, size_byte);
}
/*@}*/
/*! @} */
#if defined(__cplusplus)
}
@@ -273,4 +273,4 @@ static inline void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size
/*! @}*/
#endif /* _FSL_CACHE_H_*/
#endif /* FSL_CACHE_H_*/
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cache_lpcac.h
+6 -6
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@@ -1,11 +1,11 @@
/*
* Copyright 2021-2022 NXP
* Copyright 2021-2023 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_CACHE_LPCAC_H_
#define _FSL_CACHE_LPCAC_H_
#ifndef FSL_CACHE_LPCAC_H_
#define FSL_CACHE_LPCAC_H_
#include "fsl_common.h"
@@ -21,7 +21,7 @@
/*! @name Driver version */
/*@{*/
/*! @brief cache driver version */
#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
#define FSL_CACHE_LPCAC_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
/*@}*/
/*******************************************************************************
* API
@@ -60,7 +60,7 @@ static inline void L1CACHE_DisableCodeCache(void)
*/
static inline void L1CACHE_InvalidateCodeCache(void)
{
SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK;
SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK;
}
/*!
@@ -181,4 +181,4 @@ static inline void L1CACHE_DisableXOMControl(void)
/*! @}*/
#endif /* _FSL_CACHE_LPCAC_H_*/
#endif /* FSL_CACHE_LPCAC_H_*/
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cdog.c
+55 -54
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@@ -24,6 +24,14 @@
static const IRQn_Type s_CdogIrqs[] = CDOG_IRQS;
#endif /* CDOG_IRQS */
#ifdef CDOG_CLOCKS
static const clock_ip_name_t s_CdogClocks[] = CDOG_CLOCKS;
#endif /* CDOG_CLOCKS */
#ifdef CDOG_BASE_PTRS
static const CDOG_Type* s_cdogBases[] = CDOG_BASE_PTRS;
#endif /* CDOG_BASE_PTRS */
/*******************************************************************************
* Prototypes
******************************************************************************/
@@ -31,50 +39,24 @@ static const IRQn_Type s_CdogIrqs[] = CDOG_IRQS;
/*******************************************************************************
* Code
******************************************************************************/
#if defined(CDOG)
/*!
* Weak implementation of CDOG IRQ, should be re-defined by user when using CDOG IRQ
*/
__WEAK void CDOG_DriverIRQHandler(void)
{
/* NVIC_DisableIRQ(CDOG_IRQn);
* CDOG_Stop(CDOG, s_start);
* CDOG->FLAGS = 0x0U;
* CDOG_Start(CDOG, 0xFFFFFFU, s_start);
* NVIC_EnableIRQ(CDOG_IRQn);
*/
}
#endif
#if defined(CDOG0)
/*!
* Weak implementation of CDOG0 IRQ, should be re-defined by user when using CDOG IRQ
*/
__WEAK void CDOG0_DriverIRQHandler(void)
static uint32_t CDOG_GetInstance(CDOG_Type *base)
{
/* NVIC_DisableIRQ(CDOG0_IRQn);
* CDOG_Stop(CDOG0, s_start);
* CDOG0->FLAGS = 0x0U;
* CDOG_Start(CDOG0, 0xFFFFFFU, s_start);
* NVIC_EnableIRQ(CDOG0_IRQn);
*/
}
#endif
#if defined(CDOG1)
/*!
* Weak implementation of CDOG1 IRQ, should be re-defined by user when using CDOG IRQ
*/
__WEAK void CDOG1_DriverIRQHandler(void)
{
/* NVIC_DisableIRQ(CDOG1_IRQn);
* CDOG_Stop(CDOG1, s_start);
* CDOG1->FLAGS = 0x0U;
* CDOG_Start(CDOG1, 0xFFFFFFU, s_start);
* NVIC_EnableIRQ(CDOG1_IRQn);
*/
}
#endif
uint32_t instance;
/* Find the instance index from base address mappings. */
for (instance = 0; instance < ARRAY_SIZE(s_cdogBases); instance++)
{
if (s_cdogBases[instance] == base)
{
break;
}
}
assert(instance < ARRAY_SIZE(s_cdogBases));
return instance;
}
/*!
* brief Sets the default configuration of CDOG
@@ -256,7 +238,13 @@ void CDOG_Sub256(CDOG_Type *base)
*/
void CDOG_Check(CDOG_Type *base, uint32_t check)
{
#if defined(FLS_FEATURE_CDOG_USE_RESTART)
base->RESTART = check;
#else
base->STOP = check;
base->RELOAD = base->RELOAD;
base->START= check;
#endif
}
/*!
@@ -295,7 +283,7 @@ status_t CDOG_Init(CDOG_Type *base, cdog_config_t *conf)
/* Ungate clock to CDOG engine and reset it */
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
#ifdef CDOG_CLOCKS
CLOCK_EnableClock(kCLOCK_Cdog);
CLOCK_EnableClock(s_CdogClocks[CDOG_GetInstance(base)]);
#endif /* CDOG_CLOCKS */
#endif /* !FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
@@ -322,6 +310,25 @@ status_t CDOG_Init(CDOG_Type *base, cdog_config_t *conf)
}
else
{
/* load default values for CDOG->CONTROL before flags clear */
#if defined(FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF) && (FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF > 0)
cdog_config_t default_conf;
/* Initialize CDOG */
CDOG_GetDefaultConfig(&default_conf);
/* Write default value to CDOG->CONTROL*/
base->CONTROL =
CDOG_CONTROL_TIMEOUT_CTRL(default_conf.timeout) | /* Action if the timeout event is triggered */
CDOG_CONTROL_MISCOMPARE_CTRL(default_conf.miscompare) | /* Action if the miscompare error event is triggered */
CDOG_CONTROL_SEQUENCE_CTRL(default_conf.sequence) | /* Action if the sequence error event is triggered */
CDOG_CONTROL_STATE_CTRL(default_conf.state) | /* Action if the state error event is triggered */
CDOG_CONTROL_ADDRESS_CTRL(default_conf.address) | /* Action if the address error event is triggered */
CDOG_CONTROL_IRQ_PAUSE(default_conf.irq_pause) | /* Pause running during interrupts setup */
CDOG_CONTROL_DEBUG_HALT_CTRL(default_conf.debug_halt) | /* Halt CDOG timer during debug */
CDOG_CONTROL_LOCK_CTRL(default_conf.lock) | RESERVED_CTRL_MASK; /* Lock control register, RESERVED */
#endif /* FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF */
base->FLAGS = CDOG_FLAGS_TO_FLAG(0U) | CDOG_FLAGS_MISCOM_FLAG(0U) | CDOG_FLAGS_SEQ_FLAG(0U) |
CDOG_FLAGS_CNT_FLAG(0U) | CDOG_FLAGS_STATE_FLAG(0U) | CDOG_FLAGS_ADDR_FLAG(0U) |
CDOG_FLAGS_POR_FLAG(0U);
@@ -338,11 +345,8 @@ status_t CDOG_Init(CDOG_Type *base, cdog_config_t *conf)
CDOG_CONTROL_LOCK_CTRL(conf->lock) | RESERVED_CTRL_MASK; /* Lock control register, RESERVED */
#if defined(CDOG_IRQS)
/* Enable peripheral IRQs, if defined in array */
for (uint32_t i = 0; i < ARRAY_SIZE(s_CdogIrqs); i++)
{
NVIC_EnableIRQ(s_CdogIrqs[i]);
}
/* Enable peripheral IRQ */
NVIC_EnableIRQ(s_CdogIrqs[CDOG_GetInstance(base)]);
#endif /* CDOG_IRQS */
return kStatus_Success;
@@ -358,11 +362,8 @@ status_t CDOG_Init(CDOG_Type *base, cdog_config_t *conf)
void CDOG_Deinit(CDOG_Type *base)
{
#if defined(CDOG_IRQS)
/* Enable peripheral IRQs, if defined in array */
for (uint32_t i = 0; i < ARRAY_SIZE(s_CdogIrqs); i++)
{
NVIC_DisableIRQ(s_CdogIrqs[i]);
}
/* Disable peripheral IRQ */
NVIC_DisableIRQ(s_CdogIrqs[CDOG_GetInstance(base)]);
#endif /* CDOG_IRQS */
#if !(defined(FSL_FEATURE_CDOG_HAS_NO_RESET) && FSL_FEATURE_CDOG_HAS_NO_RESET)
@@ -371,7 +372,7 @@ void CDOG_Deinit(CDOG_Type *base)
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
#ifdef CDOG_CLOCKS
CLOCK_DisableClock(kCLOCK_Cdog);
CLOCK_DisableClock(s_CdogClocks[CDOG_GetInstance(base)]);
#endif /* CDOG_CLOCKS */
#endif /* !FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cdog.h
+10 -18
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@@ -4,8 +4,8 @@
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_CDOG_H_
#define _FSL_CDOG_H_
#ifndef FSL_CDOG_H_
#define FSL_CDOG_H_
#include "fsl_common.h"
@@ -21,10 +21,13 @@
*******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief Defines CDOG driver version 2.1.2.
/*! @{ */
/*! @brief Defines CDOG driver version 2.1.3.
*
* Change log:
* - Version 2.1.3
* - Re-design multiple instance IRQs and Clocks
* - Add fix for RESTART command errata
* - Version 2.1.2
* - Support multiple IRQs
* - Fix default CONTROL values
@@ -39,8 +42,8 @@
* - Version 2.0.0
* - initial version
*/
#define FSL_CDOG_DRIVER_VERSION (MAKE_VERSION(2, 1, 2))
/*@}*/
#define FSL_CDOG_DRIVER_VERSION (MAKE_VERSION(2, 1, 3))
/*! @} */
typedef struct
{
@@ -139,17 +142,6 @@ typedef uint32_t secure_counter_t;
/*******************************************************************************
* API
*******************************************************************************/
#if defined(CDOG)
extern void CDOG_DriverIRQHandler(void);
#endif
#if defined(CDOG0)
extern void CDOG0_DriverIRQHandler(void);
#endif
#if defined(CDOG1)
extern void CDOG1_DriverIRQHandler(void);
#endif
#if defined(__cplusplus)
extern "C" {
@@ -334,4 +326,4 @@ uint32_t CDOG_ReadPersistent(CDOG_Type *base);
/*! @}*/ /* end of group cdog */
#endif /* _FSL_CDOG_H_ */
#endif /* FSL_CDOG_H_ */
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_clock.c
+223 -17
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bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_clock.h
+641 -683
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bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cmc.c
+44 -7
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@@ -1,5 +1,5 @@
/*
* Copyright 2022 NXP
* Copyright 2022-2024 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -107,6 +107,7 @@ void CMC_ConfigResetPin(CMC_Type *base, const cmc_reset_pin_config_t *config)
base->RPC = reg;
}
#if (defined(FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG) && FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG)
/*!
* brief Power off the selected system SRAM always.
*
@@ -119,10 +120,11 @@ void CMC_ConfigResetPin(CMC_Type *base, const cmc_reset_pin_config_t *config)
*/
void CMC_PowerOffSRAMAllMode(CMC_Type *base, uint32_t mask)
{
uint32_t reg = base->SRAMDIS[0];
uint32_t reg = base->SRAMDIS[0];
uint32_t maskToSet = mask & ((uint32_t)kCMC_AllSramArrays);
reg &= ~CMC_SRAMDIS_DIS_MASK;
reg |= CMC_SRAMDIS_DIS(mask);
reg &= ~((uint32_t)kCMC_AllSramArrays);
reg |= CMC_SRAMDIS_DIS(maskToSet);
base->SRAMDIS[0] = reg;
}
@@ -137,13 +139,36 @@ void CMC_PowerOffSRAMAllMode(CMC_Type *base, uint32_t mask)
*/
void CMC_PowerOffSRAMLowPowerOnly(CMC_Type *base, uint32_t mask)
{
uint32_t reg = base->SRAMRET[0];
uint32_t reg = base->SRAMRET[0];
uint32_t maskToSet = mask & ((uint32_t)kCMC_AllSramArrays);
reg &= ~CMC_SRAMRET_RET_MASK;
reg |= CMC_SRAMRET_RET(mask);
reg &= ~((uint32_t)kCMC_AllSramArrays);
reg |= CMC_SRAMRET_RET(maskToSet);
base->SRAMRET[0] = reg;
}
#endif /* FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG */
#if (defined(FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE) && FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE)
/*!
* brief Configs the low power mode of the on-chip flash memory.
*
* This function configs the low power mode of the on-chip flash memory.
*
* param base CMC peripheral base address.
* param doze true: Flash is disabled while core is sleeping
* false: No effect.
* param disable true: Flash memory is placed in low power state.
* false: No effect.
*/
void CMC_ConfigFlashMode(CMC_Type *base, bool doze, bool disable)
{
uint32_t reg = 0UL;
reg |= (disable ? CMC_FLASHCR_FLASHDIS(1U) : CMC_FLASHCR_FLASHDIS(0U)) |
(doze ? CMC_FLASHCR_FLASHDOZE(1U) : CMC_FLASHCR_FLASHDOZE(0U));
base->FLASHCR = reg;
}
#else
/*!
* brief Configs the low power mode of the on-chip flash memory.
*
@@ -169,6 +194,7 @@ void CMC_ConfigFlashMode(CMC_Type *base, bool wake, bool doze, bool disable)
(wake ? CMC_FLASHCR_FLASHWAKE(1U) : CMC_FLASHCR_FLASHWAKE(0U));
base->FLASHCR = reg;
}
#endif /* FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE */
/*!
* brief Prepares to enter stop modes.
@@ -233,8 +259,11 @@ void CMC_GlobalEnterLowPowerMode(CMC_Type *base, cmc_low_power_mode_t lowPowerMo
void CMC_EnterLowPowerMode(CMC_Type *base, const cmc_power_domain_config_t *config)
{
assert(config != NULL);
#if (CMC_PMCTRL_COUNT > 1U)
/* The WAKE domain must never be configured to a lower power mode compared with main power mode. */
assert(config->wake_domain <= config->main_domain);
#endif /* (CMC_PMCTRL_COUNT > 1U) */
if (config->clock_mode < kCMC_GateAllSystemClocksEnterLowPowerMode)
{
@@ -243,7 +272,9 @@ void CMC_EnterLowPowerMode(CMC_Type *base, const cmc_power_domain_config_t *conf
CMC_SetClockMode(base, config->clock_mode);
CMC_SetMAINPowerMode(base, kCMC_ActiveOrSleepMode);
#if (CMC_PMCTRL_COUNT > 1U)
CMC_SetWAKEPowerMode(base, kCMC_ActiveOrSleepMode);
#endif /* (CMC_PMCTRL_COUNT > 1U) */
/* Before executing WFI instruction read back the last register to
* ensure all registers writes have completed. */
@@ -258,16 +289,22 @@ void CMC_EnterLowPowerMode(CMC_Type *base, const cmc_power_domain_config_t *conf
/* Note: unlock the register if this API will be reinvoked later. */
CMC_SetClockMode(base, kCMC_GateAllSystemClocksEnterLowPowerMode);
CMC_SetMAINPowerMode(base, config->main_domain);
#if (CMC_PMCTRL_COUNT > 1U)
CMC_SetWAKEPowerMode(base, config->wake_domain);
#endif /* (CMC_PMCTRL_COUNT > 1U) */
/* Before execute WFI instruction read back the last register to
* ensure all registers writes have completed. */
#if (CMC_PMCTRL_COUNT > 1U)
if ((CMC_GetWAKEPowerMode(base) == config->wake_domain) && (CMC_GetMAINPowerMode(base) == config->main_domain))
{
#endif /* (CMC_PMCTRL_COUNT > 1U) */
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
__DSB();
__WFI();
__ISB();
#if (CMC_PMCTRL_COUNT > 1U)
}
#endif /* (CMC_PMCTRL_COUNT > 1U) */
}
}
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cmc.h
+100 -23
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bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_common.h
+50 -23
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@@ -6,8 +6,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_COMMON_H_
#define _FSL_COMMON_H_
#ifndef FSL_COMMON_H_
#define FSL_COMMON_H_
#include <assert.h>
#include <stdbool.h>
@@ -57,12 +57,13 @@
#define MAKE_VERSION(major, minor, bugfix) (((major)*65536L) + ((minor)*256L) + (bugfix))
/*! @name Driver version */
/*@{*/
/*! @{ */
/*! @brief common driver version. */
#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))
/*@}*/
#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 4, 1))
/*! @} */
/* Debug console type definition. */
/*! @name Debug console type definition. */
/*! @{ */
#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */
#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console based on UART. */
#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console based on LPUART. */
@@ -74,6 +75,7 @@
#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console based on LPC_USART. */
#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console based on SWO. */
#define DEBUG_CONSOLE_DEVICE_TYPE_QSCI 10U /*!< Debug console based on QSCI. */
/*! @} */
/*! @brief Status group numbers. */
enum _status_groups
@@ -156,6 +158,9 @@ enum _status_groups
kStatusGroup_PUF = 105, /*!< Group number for PUF status codes. */
kStatusGroup_TOUCH_PANEL = 106, /*!< Group number for touch panel status codes */
kStatusGroup_VBAT = 107, /*!< Group number for VBAT status codes */
kStatusGroup_XSPI = 108, /*!< Group number for XSPI status codes */
kStatusGroup_PNGDEC = 109, /*!< Group number for PNGDEC status codes */
kStatusGroup_JPEGDEC = 110, /*!< Group number for JPEGDEC status codes */
kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */
kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */
@@ -166,6 +171,7 @@ enum _status_groups
kStatusGroup_HAL_PWM = 127, /*!< Group number for HAL PWM status codes. */
kStatusGroup_HAL_RNG = 128, /*!< Group number for HAL RNG status codes. */
kStatusGroup_HAL_I2S = 129, /*!< Group number for HAL I2S status codes. */
kStatusGroup_HAL_ADC_SENSOR = 130, /*!< Group number for HAL ADC SENSOR status codes. */
kStatusGroup_TIMERMANAGER = 135, /*!< Group number for TiMER MANAGER status codes. */
kStatusGroup_SERIALMANAGER = 136, /*!< Group number for SERIAL MANAGER status codes. */
kStatusGroup_LED = 137, /*!< Group number for LED status codes. */
@@ -188,15 +194,18 @@ enum _status_groups
kStatusGroup_LOG = 154, /*!< Group number for LOG status codes. */
kStatusGroup_I3CBUS = 155, /*!< Group number for I3CBUS status codes. */
kStatusGroup_QSCI = 156, /*!< Group number for QSCI status codes. */
kStatusGroup_SNT = 157, /*!< Group number for SNT status codes. */
kStatusGroup_ELEMU = 157, /*!< Group number for ELEMU status codes. */
kStatusGroup_QUEUEDSPI = 158, /*!< Group number for QSPI status codes. */
kStatusGroup_POWER_MANAGER = 159, /*!< Group number for POWER_MANAGER status codes. */
kStatusGroup_IPED = 160, /*!< Group number for IPED status codes. */
kStatusGroup_ELS_PKC = 161, /*!< Group number for ELS PKC status codes. */
kStatusGroup_HOSTIF = 162, /*!< Group number for HOSTIF status codes. */
kStatusGroup_CLIF = 163, /*!< Group number for CLIF status codes. */
kStatusGroup_BMA = 164, /*!< Group number for BMA status codes. */
kStatusGroup_NETC = 165, /*!< Group number for NETC status codes. */
kStatusGroup_CSS_PKC = 162, /*!< Group number for CSS PKC status codes. */
kStatusGroup_HOSTIF = 163, /*!< Group number for HOSTIF status codes. */
kStatusGroup_CLIF = 164, /*!< Group number for CLIF status codes. */
kStatusGroup_BMA = 165, /*!< Group number for BMA status codes. */
kStatusGroup_NETC = 166, /*!< Group number for NETC status codes. */
kStatusGroup_ELE = 167, /*!< Group number for ELE status codes. */
kStatusGroup_GLIKEY = 168, /*!< Group number for GLIKEY status codes. */
};
/*! \public
@@ -220,48 +229,66 @@ enum
/*! @brief Type used for all status and error return values. */
typedef int32_t status_t;
#ifdef __ZEPHYR__
#include <zephyr/sys/util.h>
#else
/*!
* @name Min/max macros
* @{
*/
#if !defined(MIN)
/*! Computes the minimum of \a a and \a b. */
#define MIN(a, b) (((a) < (b)) ? (a) : (b))
#endif
#if !defined(MAX)
/*! Computes the maximum of \a a and \a b. */
#define MAX(a, b) (((a) > (b)) ? (a) : (b))
#endif
/* @} */
/*! @} */
/*! @brief Computes the number of elements in an array. */
#if !defined(ARRAY_SIZE)
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
#endif
#endif /* __ZEPHYR__ */
/*! @name UINT16_MAX/UINT32_MAX value */
/* @{ */
/*! @{ */
#if !defined(UINT16_MAX)
/*! Max value of uint16_t type. */
#define UINT16_MAX ((uint16_t)-1)
#endif
#if !defined(UINT32_MAX)
/*! Max value of uint32_t type. */
#define UINT32_MAX ((uint32_t)-1)
#endif
/* @} */
/*! @} */
/*! @name Suppress fallthrough warning macro */
/* For switch case code block, if case section ends without "break;" statement, there wil be
fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc.
To suppress this warning, "SUPPRESS_FALL_THROUGH_WARNING();" need to be added at the end of each
case section which misses "break;"statement.
/*! Macro to get upper 32 bits of a 64-bit value */
#if !defined(UINT64_H)
#define UINT64_H(X) ((uint32_t)((((uint64_t) (X)) >> 32U) & 0x0FFFFFFFFULL))
#endif
/*! Macro to get lower 32 bits of a 64-bit value */
#if !defined(UINT64_L)
#define UINT64_L(X) ((uint32_t)(((uint64_t) (X)) & 0x0FFFFFFFFULL))
#endif
/*!
* @def SUPPRESS_FALL_THROUGH_WARNING()
*
* For switch case code block, if case section ends without "break;" statement, there wil be
* fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc.
* To suppress this warning, "SUPPRESS_FALL_THROUGH_WARNING();" need to be added at the end of each
* case section which misses "break;"statement.
*/
/* @{ */
#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
#define SUPPRESS_FALL_THROUGH_WARNING() __attribute__((fallthrough))
#else
#define SUPPRESS_FALL_THROUGH_WARNING()
#endif
/* @} */
/*******************************************************************************
* API
@@ -309,10 +336,10 @@ void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz);
#if (defined(__DSC__) && defined(__CW__))
#include "fsl_common_dsc.h"
#elif defined(__XCC__)
#elif defined(__XTENSA__)
#include "fsl_common_dsp.h"
#else
#include "fsl_common_arm.h"
#endif
#endif /* _FSL_COMMON_H_ */
#endif /* FSL_COMMON_H_ */
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_common_arm.c
+16 -8
View File
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
* Copyright 2016-2021 NXP
* Copyright 2016-2021, 2023 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -25,11 +25,11 @@ uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
extern uint32_t Image$$VECTOR_ROM$$Base[];
extern uint32_t Image$$VECTOR_RAM$$Base[];
extern uint32_t Image$$RW_m_data$$Base[];
extern uint32_t Image$$VECTOR_RAM$$ZI$$Limit[];
#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$VECTOR_RAM$$ZI$$Limit - (uint32_t)Image$$VECTOR_RAM$$Base))
#elif defined(__ICCARM__)
extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
extern uint32_t __VECTOR_TABLE[];
@@ -159,11 +159,11 @@ static void DelayLoop(uint32_t count)
{
__ASM volatile(" MOV X0, %0" : : "r"(count));
__ASM volatile(
"loop: \n"
"loop%=: \n"
" SUB X0, X0, #1 \n"
" CMP X0, #0 \n"
" BNE loop \n"
" BNE loop%= \n"
:
:
: "r0");
@@ -176,7 +176,7 @@ static void DelayLoop(uint32_t count)
{
__ASM volatile(" MOV R0, %0" : : "r"(count));
__ASM volatile(
"loop: \n"
"loop%=: \n"
#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
" SUB R0, R0, #1 \n"
#else
@@ -184,7 +184,7 @@ static void DelayLoop(uint32_t count)
#endif
" CMP R0, #0 \n"
" BNE loop \n"
" BNE loop%= \n"
:
:
: "r0");
@@ -232,13 +232,21 @@ void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz)
{
}
#else
#if defined(__CORTEX_Axx) && ((__CORTEX_Axx == 53) || (__CORTEX_Axx == 55))
/*
* Cortex-A53/A55 execution throughput:
* - SUB/CMP: 2 instructions per cycle
* - BNE: 1 instruction per cycle
* So, each loop takes 2 CPU cycles.
*/
count = count / 2U;
#elif (__CORTEX_M == 7)
/* Divide value may be different in various environment to ensure delay is precise.
* Every loop count includes three instructions, due to Cortex-M7 sometimes executes
* two instructions in one period, through test here set divide 1.5. Other M cores use
* divide 4. By the way, divide 1.5 or 4 could let the count lose precision, but it does
* not matter because other instructions outside while loop is enough to fill the time.
*/
#if (__CORTEX_M == 7)
count = count / 3U * 2U;
#else
count = count / 4U;
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_common_arm.h
+104 -33
View File
File diff suppressed because it is too large. Load diff
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_crc.c
+49
View File
@@ -40,6 +40,10 @@
/*< Default is resutl type is final checksum */
#endif /* CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT */
#if defined(CRC_RSTS)
#define CRC_RESETS_ARRAY CRC_RSTS
#endif
/*! @brief CRC type of transpose of read write data */
typedef enum _crc_transpose_type
{
@@ -65,9 +69,49 @@ typedef struct _crc_module_config
crc_bits_t crcBits; /*!< Selects 16- or 32- bit CRC protocol. */
} crc_module_config_t;
/*******************************************************************************
* Prototypes
******************************************************************************/
#if defined(CRC_RESETS_ARRAY)
/*!
* @brief Get instance number for CRC module.
*
* @param base CRC peripheral base address
*/
static uint32_t CRC_GetInstance(CRC_Type *base);
#endif
/*******************************************************************************
* Variables
******************************************************************************/
#if defined(CRC_RESETS_ARRAY)
static CRC_Type *const s_crcBases[] = CRC_BASE_PTRS;
/* Reset array */
static const reset_ip_name_t s_crcResets[] = CRC_RESETS_ARRAY;
#endif
/*******************************************************************************
* Code
******************************************************************************/
#if defined(CRC_RESETS_ARRAY)
static uint32_t CRC_GetInstance(CRC_Type *base)
{
uint32_t instance;
/* Find the instance index from base address mappings. */
for (instance = 0; instance < ARRAY_SIZE(s_crcBases); instance++)
{
if (s_crcBases[instance] == base)
{
break;
}
}
assert(instance < ARRAY_SIZE(s_crcBases));
return instance;
}
#endif
/*!
* @brief Returns transpose type for CRC protocol reflect in parameter.
@@ -191,6 +235,11 @@ void CRC_Init(CRC_Type *base, const crc_config_t *config)
/* ungate clock */
CLOCK_EnableClock(kCLOCK_Crc0);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
#if defined(CRC_RESETS_ARRAY)
RESET_ReleasePeripheralReset(s_crcResets[CRC_GetInstance(base)]);
#endif
/* configure CRC module and write the seed */
if (config->crcResult == kCrcFinalChecksum)
{
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_crc.h
+11 -8
View File
@@ -6,8 +6,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_CRC_H_
#define _FSL_CRC_H_
#ifndef FSL_CRC_H_
#define FSL_CRC_H_
#include "fsl_common.h"
@@ -21,13 +21,16 @@
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief CRC driver version. Version 2.0.3.
/*! @{ */
/*! @brief CRC driver version. Version 2.0.4.
*
* Current version: 2.0.3
* Current version: 2.0.4
*
* Change log:
*
* - Version 2.0.4
* - Release peripheral from reset if necessary in init function.
*
* - Version 2.0.3
* - Fix MISRA issues
*
@@ -37,8 +40,8 @@
* - Version 2.0.1
* - move DATA and DATALL macro definition from header file to source file
*/
#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 3))
/*@}*/
#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 4))
/*! @} */
#ifndef CRC_DRIVER_CUSTOM_DEFAULTS
/*! @brief Default configuration structure filled by CRC_GetDefaultConfig(). Use CRC16-CCIT-FALSE as defeault. */
@@ -175,4 +178,4 @@ uint16_t CRC_Get16bitResult(CRC_Type *base);
*@}
*/
#endif /* _FSL_CRC_H_ */
#endif /* FSL_CRC_H_ */
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_ctimer.c
+27
View File
@@ -575,3 +575,30 @@ void CTIMER4_DriverIRQHandler(void)
SDK_ISR_EXIT_BARRIER;
}
#endif
#if defined(CTIMER5)
void CTIMER5_DriverIRQHandler(void);
void CTIMER5_DriverIRQHandler(void)
{
CTIMER_GenericIRQHandler(5);
SDK_ISR_EXIT_BARRIER;
}
#endif
#if defined(CTIMER6)
void CTIMER6_DriverIRQHandler(void);
void CTIMER6_DriverIRQHandler(void)
{
CTIMER_GenericIRQHandler(6);
SDK_ISR_EXIT_BARRIER;
}
#endif
#if defined(CTIMER7)
void CTIMER7_DriverIRQHandler(void);
void CTIMER7_DriverIRQHandler(void)
{
CTIMER_GenericIRQHandler(7);
SDK_ISR_EXIT_BARRIER;
}
#endif
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_ctimer.h
+5 -5
View File
@@ -5,8 +5,8 @@
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_CTIMER_H_
#define _FSL_CTIMER_H_
#ifndef FSL_CTIMER_H_
#define FSL_CTIMER_H_
#include "fsl_common.h"
@@ -22,9 +22,9 @@
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @{ */
#define FSL_CTIMER_DRIVER_VERSION (MAKE_VERSION(2, 3, 1)) /*!< Version 2.3.1 */
/*@}*/
/*! @} */
/*! @brief List of Timer capture channels */
typedef enum _ctimer_capture_channel
@@ -679,4 +679,4 @@ static inline void CTIMER_SetShadowValue(CTIMER_Type *base, ctimer_match_t match
/*! @}*/
#endif /* _FSL_CTIMER_H_ */
#endif /* FSL_CTIMER_H_ */
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_dac.c
+18
View File
@@ -8,11 +8,20 @@
#include "fsl_dac.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.dac_1"
#endif
#if defined(DAC_RSTS)
#define DAC_RESETS_ARRAY DAC_RSTS
#elif defined(DAC_RSTS_N)
#define DAC_RESETS_ARRAY DAC_RSTS_N
#endif
/*******************************************************************************
* Prototypes
******************************************************************************/
@@ -34,6 +43,11 @@ static LPDAC_Type *const s_dacBases[] = LPDAC_BASE_PTRS;
static const clock_ip_name_t s_dacClocks[] = LPDAC_CLOCKS;
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
#if defined(DAC_RESETS_ARRAY)
/* Reset array */
static const reset_ip_name_t s_dacResets[] = DAC_RESETS_ARRAY;
#endif
/*******************************************************************************
* Code
******************************************************************************/
@@ -74,6 +88,10 @@ void DAC_Init(LPDAC_Type *base, const dac_config_t *config)
CLOCK_EnableClock(s_dacClocks[DAC_GetInstance(base)]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
#if defined(DAC_RESETS_ARRAY)
RESET_ReleasePeripheralReset(s_dacResets[DAC_GetInstance(base)]);
#endif
/* Reset the logic. */
DAC_SetReset(base, kDAC_ResetLogic);
DAC_ClearReset(base, kDAC_ResetLogic);
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_dac.h
+12 -12
View File
@@ -6,8 +6,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_DAC_H_
#define _FSL_DAC_H_
#ifndef FSL_DAC_H_
#define FSL_DAC_H_
#include "fsl_common.h"
@@ -23,10 +23,10 @@
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief DAC driver version 2.1.1. */
#define FSL_DAC_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
/*@}*/
/*! @{ */
/*! @brief DAC driver version 2.1.2. */
#define FSL_DAC_DRIVER_VERSION (MAKE_VERSION(2, 1, 2))
/*! @} */
/*!
* @brief DAC reset control.
@@ -293,7 +293,7 @@ static inline void DAC_Enable(LPDAC_Type *base, bool enable)
}
}
/* @} */
/*! @} */
/*!
* @name Interrupts
@@ -322,7 +322,7 @@ static inline void DAC_DisableInterrupts(LPDAC_Type *base, uint32_t mask)
base->IER &= ~mask;
}
/* @} */
/*! @} */
/*!
* @name DMA control
@@ -348,7 +348,7 @@ static inline void DAC_EnableDMA(LPDAC_Type *base, uint32_t mask, bool enable)
}
}
/* @} */
/*! @} */
/*!
* @name Status flags
@@ -377,7 +377,7 @@ static inline void DAC_ClearStatusFlags(LPDAC_Type *base, uint32_t flags)
base->FSR = flags;
}
/* @} */
/*! @} */
/*!
* @name Functional feature
@@ -430,7 +430,7 @@ static inline void DAC_DoSoftwareTriggerFIFO(LPDAC_Type *base)
base->TCR = LPDAC_TCR_SWTRG_MASK;
}
/* @} */
/*! @} */
#if defined(__cplusplus)
}
@@ -439,4 +439,4 @@ static inline void DAC_DoSoftwareTriggerFIFO(LPDAC_Type *base)
/*!
* @}
*/
#endif /* _FSL_DAC12_H_ */
#endif /* FSL_DAC12_H_ */
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_dac14.h
+13 -13
View File
@@ -5,8 +5,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_DAC14_H_
#define _FSL_DAC14_H_
#ifndef FSL_DAC14_H_
#define FSL_DAC14_H_
#include "fsl_common.h"
@@ -22,10 +22,10 @@
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @{ */
/*! @brief DAC14 driver version 2.0.0. */
#define FSL_DAC14_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
/*@}*/
/*! @} */
/*!
* @brief DAC14 interrupts enumeration.
@@ -209,7 +209,7 @@ static inline void DAC14_AbortPeriodTriggerConvSequence(HPDAC_Type *base)
{
base->GCR &= ~HPDAC_GCR_PTGEN_MASK;
}
/* @} */
/*! @} */
/*!
* @name DAC Control Interface
@@ -233,7 +233,7 @@ static inline void DAC14_Enable(HPDAC_Type *base, bool enable)
base->GCR &= ~HPDAC_GCR_DACEN_MASK;
}
}
/* @} */
/*! @} */
/*!
* @name Swing Back Mode Control Interface
@@ -256,7 +256,7 @@ static inline void DAC14_EnableSwingBackMode(HPDAC_Type *base, bool enable)
base->GCR &= ~HPDAC_GCR_SWMD_MASK;
}
}
/* @} */
/*! @} */
/*!
* @name FIFO Mode Control Interface
@@ -279,7 +279,7 @@ static inline void DAC14_EnableFIFOMode(HPDAC_Type *base, bool enable)
base->GCR &= ~HPDAC_GCR_FIFOEN_MASK;
}
}
/* @} */
/*! @} */
/*!
* @name Interrupts
@@ -306,7 +306,7 @@ static inline void DAC14_DisableInterrupts(HPDAC_Type *base, uint32_t mask)
{
base->IER &= ~mask;
}
/* @} */
/*! @} */
/*!
* @name DMA Control Interface
@@ -330,7 +330,7 @@ static inline void DAC14_EnableDMA(HPDAC_Type *base, uint32_t mask, bool enable)
base->DER &= ~mask;
}
}
/* @} */
/*! @} */
/*!
* @name Status
@@ -357,7 +357,7 @@ static inline void DAC14_ClearStatusFlags(HPDAC_Type *base, uint32_t flags)
{
base->FSR = flags;
}
/* @} */
/*! @} */
/*!
* @name Functional Feature
@@ -407,7 +407,7 @@ static inline void DAC14_DoSoftwareTrigger(HPDAC_Type *base)
{
base->TCR = HPDAC_TCR_SWTRG_MASK;
}
/* @} */
/*! @} */
#if defined(__cplusplus)
}
@@ -416,4 +416,4 @@ static inline void DAC14_DoSoftwareTrigger(HPDAC_Type *base)
/*!
* @}
*/
#endif /* _FSL_DAC14_H_ */
#endif /* FSL_DAC14_H_ */
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_edma.c
+1021 -339
View File
File diff suppressed because it is too large. Load diff
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_edma.h
+536 -127
View File
File diff suppressed because it is too large. Load diff
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_edma_core.h
+288 -151
View File
File diff suppressed because it is too large. Load diff
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_edma_soc.h
-145
View File
@@ -45,151 +45,6 @@
} \
}
/*!@brief dma request source */
typedef enum _dma_request_source
{
kDmaRequestDisabled = 0U, /**< DSisabled*/
kDmaRequestMuxFlexSpi0Rx = 1 | 0x100U, /**< FlexSPI0 Receive event */
kDmaRequestMuxFlexSpi0Tx = 2 | 0x100U, /**< FlexSPI0 Transmit event */
kDmaRequestMuxPinInt0 = 3 | 0x100U, /**< PinInt0 */
kDmaRequestMuxPinInt1 = 4 | 0x100U, /**< PinInt1 */
kDmaRequestMuxPinInt2 = 5 | 0x100U, /**< PinInt2 */
kDmaRequestMuxPinInt3 = 6 | 0x100U, /**< PinInt3 */
kDmaRequestMuxCtimer0M0 = 7 | 0x100U, /**< Ctimer0_M0 */
kDmaRequestMuxCtimer0M1 = 8 | 0x100U, /**< Ctimer0_M1 */
kDmaRequestMuxCtimer1M0 = 9 | 0x100U, /**< Ctimer1_M0 */
kDmaRequestMuxCtimer1M1 = 10 | 0x100U, /**< Ctimer1_M1 */
kDmaRequestMuxCtimer2M0 = 11 | 0x100U, /**< Ctimer2_M0 */
kDmaRequestMuxCtimer2M1 = 12 | 0x100U, /**< Ctimer2_M1 */
kDmaRequestMuxCtimer3M0 = 13 | 0x100U, /**< Ctimer3_M0 */
kDmaRequestMuxCtimer3M1 = 14 | 0x100U, /**< Ctimer3_M1 */
kDmaRequestMuxCtimer4M0 = 15 | 0x100U, /**< Ctimer4_M0 */
kDmaRequestMuxCtimer5M1 = 16 | 0x100U, /**< Ctimer4_M1 */
kDmaRequestMuxWuu0 = 17 | 0x100U, /**< Wake up event */
kDmaRequestMuxMicfil0FifoRequest = 18 | 0x100U, /**< MICFIL0 FIFO_request */
kDmaRequestMuxSct0Dma0 = 19 | 0x100U, /**< SCT0 DMA0 */
kDmaRequestMuxSct0Dma1 = 20 | 0x100U, /**< SCT0 DMA1 */
kDmaRequestMuxAdc0FifoARequest = 21 | 0x100U, /**< ADC0 FIFO A request */
kDmaRequestMuxAdc0FifoBRequest = 22 | 0x100U, /**< ADC0 FIFO B request */
kDmaRequestMuxAdc1FifoARequest = 23 | 0x100U, /**< ADC1 FIFO A request */
kDmaRequestMuxAdc1FifoBRequest = 24 | 0x100U, /**< ADC1 FIFO B request */
kDmaRequestMuxDac0FifoRequest = 25 | 0x100U, /**< DAC0 FIFO_request */
kDmaRequestMuxDac1FifoRequest = 26 | 0x100U, /**< DAC1 FIFO_request */
kDmaRequestMuxHpDac0FifoRequest = 27 | 0x100U, /**< HP DAC0 FIFO_request */
kDmaRequestMuxHsCmp0DmaRequest = 28 | 0x100U, /**< HS CMP0 DMA_request */
kDmaRequestMuxHsCmp1DmaRequest = 29 | 0x100U, /**< HS CMP0 DMA_request */
kDmaRequestMuxHsCmp2DmaRequest = 30 | 0x100U, /**< HS CMP0 DMA_request */
kDmaRequestMuxEvtg0Out0A = 31 | 0x100U, /**< EVTG0 OUT0A */
kDmaRequestMuxEvtg0Out0B = 32 | 0x100U, /**< EVTG0 OUT0B */
kDmaRequestMuxEvtg0Out1A = 33 | 0x100U, /**< EVTG0 OUT1A */
kDmaRequestMuxEvtg0Out1B = 34 | 0x100U, /**< EVTG0 OUT1B */
kDmaRequestMuxEvtg0Out2A = 35 | 0x100U, /**< EVTG0 OUT2A */
kDmaRequestMuxEvtg0Out2B = 36 | 0x100U, /**< EVTG0 OUT2B */
kDmaRequestMuxEvtg0Out3A = 37 | 0x100U, /**< EVTG0 OUT3A */
kDmaRequestMuxEvtg0Out3B = 38 | 0x100U, /**< EVTG0 OUT3B */
kDmaRequestMuxFlexPwm0ReqCapt0 = 39 | 0x100U, /**< FlexPWM0 Req_capt0 */
kDmaRequestMuxFlexPwm0ReqCapt1 = 40 | 0x100U, /**< FlexPWM0 Req_capt1 */
kDmaRequestMuxFlexPwm0ReqCapt2 = 41 | 0x100U, /**< FlexPWM0 Req_capt2 */
kDmaRequestMuxFlexPwm0ReqCapt3 = 42 | 0x100U, /**< FlexPWM0 Req_capt3 */
kDmaRequestMuxFlexPwm0ReqVal0 = 43 | 0x100U, /**< FlexPWM0 Req_val0 */
kDmaRequestMuxFlexPwm0ReqVal1 = 44 | 0x100U, /**< FlexPWM0 Req_val1 */
kDmaRequestMuxFlexPwm0ReqVal2 = 45 | 0x100U, /**< FlexPWM0 Req_val2 */
kDmaRequestMuxFlexPwm0ReqVal3 = 46 | 0x100U, /**< FlexPWM0 Req_val3 */
kDmaRequestMuxFlexPwm1ReqCapt0 = 47 | 0x100U, /**< FlexPWM1 Req_capt0 */
kDmaRequestMuxFlexPwm1ReqCapt1 = 48 | 0x100U, /**< FlexPWM1 Req_capt1 */
kDmaRequestMuxFlexPwm1ReqCapt2 = 49 | 0x100U, /**< FlexPWM1 Req_capt2 */
kDmaRequestMuxFlexPwm1ReqCapt3 = 50 | 0x100U, /**< FlexPWM1 Req_capt3 */
kDmaRequestMuxFlexPwm1ReqVal0 = 51 | 0x100U, /**< FlexPWM1 Req_val0 */
kDmaRequestMuxFlexPwm1ReqVal1 = 52 | 0x100U, /**< FlexPWM1 Req_val1 */
kDmaRequestMuxFlexPwm1ReqVal2 = 53 | 0x100U, /**< FlexPWM1 Req_val2 */
kDmaRequestMuxFlexPwm1ReqVal3 = 54 | 0x100U, /**< FlexPWM1 Req_val3 */
kDmaRequestMuxItrc0TmprOut0 = 55 | 0x100U, /**< ITRC0 TMPR_OUT0 */
kDmaRequestMuxItrc0TmprOut1 = 56 | 0x100U, /**< ITRC0 TMPR_OUT1 */
kDmaRequestMuxLptmr0 = 57 | 0x100U, /**< LPTMR0 Counter match event */
kDmaRequestMuxLptmr1 = 58 | 0x100U, /**< LPTMR1 Counter match event */
kDmaRequestMuxFlexCan0DmaRequest = 59 | 0x100U, /**< FlexCAN0 DMA request */
kDmaRequestMuxFlexCan1DmaRequest = 60 | 0x100U, /**< FlexCAN1 DMA request */
kDmaRequestMuxFlexIO0ShiftRegister0Request = 61 | 0x100U, /**< FlexIO0 Shift Register 0 request */
kDmaRequestMuxFlexIO0ShiftRegister1Request = 62 | 0x100U, /**< FlexIO0 Shift Register 1 request */
kDmaRequestMuxFlexIO0ShiftRegister2Request = 63 | 0x100U, /**< FlexIO0 Shift Register 2 request */
kDmaRequestMuxFlexIO0ShiftRegister3Request = 64 | 0x100U, /**< FlexIO0 Shift Register 3 request */
kDmaRequestMuxFlexIO0ShiftRegister4Request = 65 | 0x100U, /**< FlexIO0 Shift Register 4 request */
kDmaRequestMuxFlexIO0ShiftRegister5Request = 66 | 0x100U, /**< FlexIO0 Shift Register 5 request */
kDmaRequestMuxFlexIO0ShiftRegister6Request = 67 | 0x100U, /**< FlexIO0 Shift Register 6 request */
kDmaRequestMuxFlexIO0ShiftRegister7Request = 68 | 0x100U, /**< FlexIO0 Shift Register 7 request */
kDmaRequestMuxLpFlexcomm0Rx = 69 | 0x100U, /**< LP_FLEXCOMM0 Receive request */
kDmaRequestMuxLpFlexcomm0Tx = 70 | 0x100U, /**< LP_FLEXCOMM0 Transmit request */
kDmaRequestMuxLpFlexcomm1Rx = 71 | 0x100U, /**< LP_FLEXCOMM1 Receive request */
kDmaRequestMuxLpFlexcomm1Tx = 72 | 0x100U, /**< LP_FLEXCOMM1 Transmit request */
kDmaRequestMuxLpFlexcomm2Rx = 73 | 0x100U, /**< LP_FLEXCOMM2 Receive request */
kDmaRequestMuxLpFlexcomm2Tx = 74 | 0x100U, /**< LP_FLEXCOMM2 Transmit request */
kDmaRequestMuxLpFlexcomm3Rx = 75 | 0x100U, /**< LP_FLEXCOMM3 Receive request */
kDmaRequestMuxLpFlexcomm3Tx = 76 | 0x100U, /**< LP_FLEXCOMM3 Transmit request */
kDmaRequestMuxLpFlexcomm4Rx = 77 | 0x100U, /**< LP_FLEXCOMM4 Receive request */
kDmaRequestMuxLpFlexcomm4Tx = 78 | 0x100U, /**< LP_FLEXCOMM4 Transmit request */
kDmaRequestMuxLpFlexcomm5Rx = 79 | 0x100U, /**< LP_FLEXCOMM5 Receive request */
kDmaRequestMuxLpFlexcomm5Tx = 80 | 0x100U, /**< LP_FLEXCOMM5 Transmit request */
kDmaRequestMuxLpFlexcomm6Rx = 81 | 0x100U, /**< LP_FLEXCOMM6 Receive request */
kDmaRequestMuxLpFlexcomm6Tx = 82 | 0x100U, /**< LP_FLEXCOMM6 Transmit request */
kDmaRequestMuxLpFlexcomm7Rx = 83 | 0x100U, /**< LP_FLEXCOMM7 Receive request */
kDmaRequestMuxLpFlexcomm7Tx = 84 | 0x100U, /**< LP_FLEXCOMM7 Transmit request */
kDmaRequestMuxLpFlexcomm8Rx = 85 | 0x100U, /**< LP_FLEXCOMM8 Receive request */
kDmaRequestMuxLpFlexcomm8Tx = 86 | 0x100U, /**< LP_FLEXCOMM8 Transmit request */
kDmaRequestMuxLpFlexcomm9Rx = 87 | 0x100U, /**< LP_FLEXCOMM9 Receive request */
kDmaRequestMuxLpFlexcomm9Tx = 88 | 0x100U, /**< LP_FLEXCOMM9 Transmit request */
kDmaRequestMuxESpi0Ch0 = 89 | 0x100U, /**< eSPI0 channel 0 */
kDmaRequestMuxESpi0Ch1 = 90 | 0x100U, /**< eSPI0 channel 1 */
kDmaRequestMuxEmvSim0Rx = 91 | 0x100U, /**< EMVSIM0 Receive request */
kDmaRequestMuxEmvSim0Tx = 92 | 0x100U, /**< EMVSIM0 Transmit request */
kDmaRequestMuxEmvSim1Rx = 93 | 0x100U, /**< EMVSIM1 Receive request */
kDmaRequestMuxEmvSim1Tx = 94 | 0x100U, /**< EMVSIM1 Transmit request */
kDmaRequestMuxI3c0Rx = 95 | 0x100U, /**< I3C0 Receive request */
kDmaRequestMuxI3c0Tx = 96 | 0x100U, /**< I3C0 Transmit request */
kDmaRequestMuxI3c1Rx = 97 | 0x100U, /**< I3C0 Receive request */
kDmaRequestMuxI3c1Tx = 98 | 0x100U, /**< I3C0 Transmit request */
kDmaRequestMuxSai0Rx = 99 | 0x100U, /**< SAI0 Receive request */
kDmaRequestMuxSai0Tx = 100 | 0x100U, /**< SAI0 Receive request */
kDmaRequestMuxSai1Rx = 101 | 0x100U, /**< SAI1 Receive request */
kDmaRequestMuxSai1Tx = 102 | 0x100U, /**< SAI1 Receive request */
kDmaRequestMuxSinc0IpdReqSincAlt0 = 103 | 0x100U, /**< SINC0 ipd_req_sinc[0] or ipd_req_alt [0] */
kDmaRequestMuxSinc0IpdReqSincAlt1 = 104 | 0x100U, /**< SINC0 ipd_req_sinc[1] or ipd_req_alt [1] */
kDmaRequestMuxSinc0IpdReqSincAlt2 = 105 | 0x100U, /**< SINC0 ipd_req_sinc[2] or ipd_req_alt [2] */
kDmaRequestMuxSinc0IpdReqSincAlt3 = 106 | 0x100U, /**< SINC0 ipd_req_sinc[3] or ipd_req_alt [3] */
kDmaRequestMuxSinc0IpdReqSincAlt4 = 107 | 0x100U, /**< SINC0 ipd_req_sinc[4] or ipd_req_alt [4] */
kDmaRequestMuxGpio0PinEventRequest0 = 108 | 0x100U, /**< GPIO0 Pin event request 0 */
kDmaRequestMuxGpio0PinEventRequest1 = 109 | 0x100U, /**< GPIO0 Pin event request 1 */
kDmaRequestMuxGpio1PinEventRequest0 = 110 | 0x100U, /**< GPIO1 Pin event request 0 */
kDmaRequestMuxGpio1PinEventRequest1 = 111 | 0x100U, /**< GPIO1 Pin event request 1 */
kDmaRequestMuxGpio2PinEventRequest0 = 112 | 0x100U, /**< GPIO2 Pin event request 0 */
kDmaRequestMuxGpio2PinEventRequest1 = 113 | 0x100U, /**< GPIO2 Pin event request 1 */
kDmaRequestMuxGpio3PinEventRequest0 = 114 | 0x100U, /**< GPIO3 Pin event request 0 */
kDmaRequestMuxGpio3PinEventRequest1 = 115 | 0x100U, /**< GPIO3 Pin event request 1 */
kDmaRequestMuxGpio4PinEventRequest0 = 116 | 0x100U, /**< GPIO4 Pin event request 0 */
kDmaRequestMuxGpio4PinEventRequest1 = 117 | 0x100U, /**< GPIO4 Pin event request 1 */
kDmaRequestMuxGpio5PinEventRequest0 = 118 | 0x100U, /**< GPIO5 Pin event request 0 */
kDmaRequestMuxGpio5PinEventRequest1 = 119 | 0x100U, /**< GPIO5 Pin event request 1 */
kDmaRequestMuxTsi0EndOfScan = 120 | 0x100U, /**< TSI0 End of Scan */
kDmaRequestMuxTsi0OutOfRange = 121 | 0x100U, /**< TSI0 Out of Range */
} dma_request_source_t;
/*!< Verify dma base and request source */
#define EDMA_CHANNEL_HAS_REQUEST_SOURCE(base, source) ((source)&0x100U)
#define FSL_FEATURE_EDMA_MODULE_CHANNEL(base) (16U)
#define FSL_FEATURE_EDMA_MODULE_MAX_CHANNEL (16)
#define FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION (1)
#define FSL_FEATURE_EDMA_HAS_CONTINUOUS_LINK_MODE (0)
#define FSL_FEATURE_EDMA_MODULE_COUNT (2)
#define FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG (1)
#define FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE (0)
#define FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE (0)
#define FSL_FEATURE_EDMA_HAS_CHANNEL_MEMRORY_ATTRIBUTE (0)
#define FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION (0)
#define FSL_FEATURE_EDMA_MODULE_SUPPORT_MATTR(base) (0U)
#define FSL_FEATURE_EDMA_MODULE_SUPPORT_SIGN_EXTENSION(base) (0U)
#define FSL_FEATURE_EDMA_MODULE_SUPPORT_SWAP(base) (0U)
#define FSL_FEATURE_EDMA_MODULE_SUPPORT_INSTR(base) (0U)
/*!@brief EDMA base address convert macro */
#define EDMA_CHANNEL_OFFSET 0x1000U
#define EDMA_CHANNEL_ARRAY_STEP(base) (0x1000U)
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_eim.c
+98 -68
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bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_eim.h
+6 -6
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@@ -6,8 +6,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_EIM_H_
#define _FSL_EIM_H_
#ifndef FSL_EIM_H_
#define FSL_EIM_H_
#include "fsl_common.h"
@@ -21,10 +21,10 @@
*****************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @{ */
/*! @brief Driver version. */
#define FSL_ERM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 0U))
/*@}*/
#define FSL_ERM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 1U))
/*! @} */
/*******************************************************************************
* APIs
@@ -47,7 +47,7 @@ void EIM_Init(EIM_Type *base);
*/
void EIM_Deinit(EIM_Type *base);
/* @} */
/*! @} */
/*!
* @name functional
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_enc.c
-625
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bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_enet.c
+261 -30
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bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_enet.h
+141 -26
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bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_erm.c
+113 -109
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bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_erm.h
+19 -7
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@@ -6,8 +6,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_ERM_H_
#define _FSL_ERM_H_
#ifndef FSL_ERM_H_
#define FSL_ERM_H_
#include "fsl_common.h"
@@ -21,10 +21,10 @@
*****************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @{ */
/*! @brief Driver version. */
#define FSL_ERM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 0U))
/*@}*/
#define FSL_ERM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 1U))
/*! @} */
/*!
* @brief ERM interrupt configuration structure, default settings all disabled, _erm_interrupt_enable.
@@ -78,7 +78,7 @@ void ERM_Init(ERM_Type *base);
*/
void ERM_Deinit(ERM_Type *base);
/* @} */
/*! @} */
/*!
* @name Interrupt
@@ -101,12 +101,14 @@ static inline void ERM_EnableInterrupts(ERM_Type *base, erm_memory_channel_t cha
base->CR0 =
(temp & ~(0x0CUL << ((0x07U - (uint32_t)channel) * 4U))) | (mask << ((0x07U - (uint32_t)channel) * 4U));
}
#ifdef ERM_CR1_ESCIE8_MASK
else
{
temp = base->CR1;
base->CR1 = (temp & ~(0x0CUL << ((0x07U + 0x08U - (uint32_t)channel) * 4U))) |
(mask << ((0x07U + 0x08U - (uint32_t)channel) * 4U));
}
#endif
}
/*!
@@ -123,10 +125,12 @@ static inline void ERM_DisableInterrupts(ERM_Type *base, erm_memory_channel_t ch
{
base->CR0 &= ~(mask << ((0x07U - (uint32_t)channel) * 4U));
}
#ifdef ERM_CR1_ESCIE8_MASK
else
{
base->CR1 &= ~(mask << ((0x07U + 0x08U - (uint32_t)channel) * 4U));
}
#endif
}
/*!
@@ -141,10 +145,16 @@ static inline uint32_t ERM_GetInterruptStatus(ERM_Type *base, erm_memory_channel
{
return ((base->SR0 & (uint32_t)kERM_AllIntsFlag) >> (0x07U - (uint32_t)channel) * 4U);
}
#ifdef ERM_SR1_SBC8_MASK
else
{
return ((base->SR1 & (uint32_t)kERM_AllIntsFlag) >> ((0x07U + 0x08U - (uint32_t)channel) * 4U));
}
#else
{
return 0;
}
#endif
}
/*!
@@ -159,13 +169,15 @@ static inline void ERM_ClearInterruptStatus(ERM_Type *base, erm_memory_channel_t
{
base->SR0 = mask << ((0x07U - (uint32_t)channel) * 4U);
}
#ifdef ERM_SR1_SBC8_MASK
else
{
base->SR1 = mask << ((0x07U + 0x08U - (uint32_t)channel) * 4U);
}
#endif
}
/* @} */
/*! @} */
/*!
* @name functional
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_evtg.h
+22 -22
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@@ -5,8 +5,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_EVTG_H_
#define _FSL_EVTG_H_
#ifndef FSL_EVTG_H_
#define FSL_EVTG_H_
#include "fsl_common.h"
@@ -20,10 +20,10 @@
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @{ */
/*! @brief EVTG driver version. */
#define FSL_EVTG_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1. */
/*@}*/
/*! @} */
/*! @brief EVTG instance index. */
typedef enum _evtg_index
@@ -247,7 +247,7 @@ static inline void EVTG_ForceFlipflopInitOutput(EVTG_Type *base,
evtg_index_t evtgIndex,
evtg_flipflop_init_output_t flipflopInitOutputValue)
{
base->EVTG_INST[(uint8_t)evtgIndex].EVTG_CTRL &= (~EVTG_EVTG_INST_EVTG_CTRL_FF_INIT_MASK);
base->EVTG_INST[(uint8_t)evtgIndex].EVTG_CTRL &= (~(uint16_t)EVTG_EVTG_INST_EVTG_CTRL_FF_INIT_MASK);
base->EVTG_INST[(uint8_t)evtgIndex].EVTG_CTRL |=
EVTG_EVTG_INST_EVTG_CTRL_FF_INIT((uint16_t)flipflopInitOutputValue);
/* INIT_EN bit should be set after FF_INIT is set. */
@@ -284,20 +284,20 @@ static inline void EVTG_SetProductTermInput(EVTG_Type *base,
if ((productTerm == kEVTG_ProductTerm0) || (productTerm == kEVTG_ProductTerm1))
{
base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI0_BFT01 &=
(~(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U))));
(uint16_t)(~(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U))));
base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI0_BFT01 |=
(((uint16_t)(((uint16_t)(input))
<< ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U)))) &
(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U))));
((((uint16_t)(input)) << ((3U - ((uint8_t)inputIndex)) * 2U +
(((3U - (uint8_t)productTerm) % 2U) * 8U))) &
(uint16_t)(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U))));
}
else
{
base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI0_BFT23 &=
(~(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U))));
(uint16_t)(~(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U))));
base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI0_BFT23 |=
(((uint16_t)(((uint16_t)(input))
<< ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U)))) &
(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U))));
((((uint16_t)(input)) << ((3U - ((uint8_t)inputIndex)) * 2U +
(((3U - (uint8_t)productTerm) % 2U) * 8U))) &
(uint16_t)(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U))));
}
}
else if (kEVTG_AOI1 == aoiIndex)
@@ -305,20 +305,20 @@ static inline void EVTG_SetProductTermInput(EVTG_Type *base,
if ((productTerm == kEVTG_ProductTerm0) || (productTerm == kEVTG_ProductTerm1))
{
base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI1_BFT01 &=
(~(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U))));
(uint16_t)(~(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U))));
base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI1_BFT01 |=
(((uint16_t)(((uint16_t)(input))
<< ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U)))) &
(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U))));
((((uint16_t)(input)) << ((3U - ((uint8_t)inputIndex)) * 2U +
(((3U - (uint8_t)productTerm) % 2U) * 8U))) &
(uint16_t)(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U))));
}
else
{
base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI1_BFT23 &=
(~(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U))));
(uint16_t)(~(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U))));
base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI1_BFT23 |=
(((uint16_t)(((uint16_t)(input))
<< ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U)))) &
(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U))));
((((uint16_t)(input)) << ((3U - ((uint8_t)inputIndex)) * 2U +
(((3U - (uint8_t)productTerm) % 2U) * 8U))) &
(uint16_t)(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U))));
}
}
else
@@ -352,4 +352,4 @@ void EVTG_ConfigAOIProductTerm(EVTG_Type *base,
/*! @} */
#endif /* _FSL_EVTG_H_ */
#endif /* FSL_EVTG_H_ */
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_ewm.h
+7 -7
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@@ -5,8 +5,8 @@
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_EWM_H_
#define _FSL_EWM_H_
#ifndef FSL_EWM_H_
#define FSL_EWM_H_
#include "fsl_common.h"
@@ -20,10 +20,10 @@
*******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @{ */
/*! @brief EWM driver version 2.0.3. */
#define FSL_EWM_DRIVER_VERSION (MAKE_VERSION(2, 0, 3))
/*@}*/
/*! @} */
/*! @brief Describes EWM clock source. */
#if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT
@@ -141,7 +141,7 @@ void EWM_Deinit(EWM_Type *base);
*/
void EWM_GetDefaultConfig(ewm_config_t *config);
/* @} */
/*! @} */
/*!
* @name EWM functional Operation
@@ -207,7 +207,7 @@ static inline uint32_t EWM_GetStatusFlags(EWM_Type *base)
*/
void EWM_Refresh(EWM_Type *base);
/*@}*/
/*! @} */
#if defined(__cplusplus)
}
@@ -215,4 +215,4 @@ void EWM_Refresh(EWM_Type *base);
/*! @}*/
#endif /* _FSL_EWM_H_ */
#endif /* FSL_EWM_H_ */
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexcan.c
+584 -270
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bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexcan.h
+135 -16
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bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexcan_edma.c
+381
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bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexcan_edma.h
+188
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@@ -0,0 +1,188 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2023 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef FSL_FLEXCAN_EDMA_H_
#define FSL_FLEXCAN_EDMA_H_
#include "fsl_flexcan.h"
#include "fsl_edma.h"
/*!
* @addtogroup flexcan_edma_driver
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @name Driver version */
/*! @{ */
/*! @brief FlexCAN EDMA driver version. */
#define FSL_FLEXCAN_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 11, 3))
/*! @} */
/* Forward declaration of the handle typedef. */
typedef struct _flexcan_edma_handle flexcan_edma_handle_t;
/*! @brief FlexCAN transfer callback function. */
typedef void (*flexcan_edma_transfer_callback_t)(CAN_Type *base,
flexcan_edma_handle_t *handle,
status_t status,
void *userData);
/*!
* @brief FlexCAN eDMA handle
*/
struct _flexcan_edma_handle
{
flexcan_edma_transfer_callback_t callback; /*!< Callback function. */
void *userData; /*!< FlexCAN callback function parameter.*/
edma_handle_t *rxFifoEdmaHandle; /*!< The EDMA handler for Rx FIFO. */
volatile uint8_t rxFifoState; /*!< Rx FIFO transfer state. */
size_t frameNum; /*!< The number of messages that need to be received. */
#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
flexcan_fd_frame_t *framefd; /*!< Point to the buffer of CAN Message to be received from Enhanced Rx FIFO. */
#endif
};
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @name eDMA transactional
* @{
*/
/*!
* @brief Initializes the FlexCAN handle, which is used in transactional functions.
*
* @param base FlexCAN peripheral base address.
* @param handle Pointer to flexcan_edma_handle_t structure.
* @param callback The callback function.
* @param userData The parameter of the callback function.
* @param rxFifoEdmaHandle User-requested DMA handle for Rx FIFO DMA transfer.
*/
void FLEXCAN_TransferCreateHandleEDMA(CAN_Type *base,
flexcan_edma_handle_t *handle,
flexcan_edma_transfer_callback_t callback,
void *userData,
edma_handle_t *rxFifoEdmaHandle);
/*!
* @brief Prepares the eDMA transfer configuration for FLEXCAN Legacy RX FIFO.
*
* This function prepares the eDMA transfer configuration structure according to FLEXCAN Legacy RX FIFO.
*
* @param base FlexCAN peripheral base address.
* @param pFifoXfer FlexCAN Rx FIFO EDMA transfer structure, see #flexcan_fifo_transfer_t.
* @param pEdmaConfig The user configuration structure of type edma_transfer_t.
*
*/
void FLEXCAN_PrepareTransfConfiguration(CAN_Type *base,
flexcan_fifo_transfer_t *pFifoXfer,
edma_transfer_config_t *pEdmaConfig);
/*!
* @brief Start Transfer Data from the FLEXCAN Legacy Rx FIFO using eDMA.
*
* This function to Update edma transfer confiugration and Start eDMA transfer
*
* @param base FlexCAN peripheral base address.
* @param handle Pointer to flexcan_edma_handle_t structure.
* @param pEdmaConfig The user configuration structure of type edma_transfer_t.
* @retval kStatus_Success if succeed, others failed.
* @retval kStatus_FLEXCAN_RxFifoBusy Previous transfer ongoing.
*/
status_t FLEXCAN_StartTransferDatafromRxFIFO(CAN_Type *base,
flexcan_edma_handle_t *handle,
edma_transfer_config_t *pEdmaConfig);
/*!
* @brief Receives the CAN Message from the Legacy Rx FIFO using eDMA.
*
* This function receives the CAN Message using eDMA. This is a non-blocking function, which returns
* right away. After the CAN Message is received, the receive callback function is called.
*
* @param base FlexCAN peripheral base address.
* @param handle Pointer to flexcan_edma_handle_t structure.
* @param pFifoXfer FlexCAN Rx FIFO EDMA transfer structure, see #flexcan_fifo_transfer_t.
* @retval kStatus_Success if succeed, others failed.
* @retval kStatus_FLEXCAN_RxFifoBusy Previous transfer ongoing.
*/
status_t FLEXCAN_TransferReceiveFifoEDMA(CAN_Type *base,
flexcan_edma_handle_t *handle,
flexcan_fifo_transfer_t *pFifoXfer);
/*!
* @brief Gets the Legacy Rx Fifo transfer status during a interrupt non-blocking receive.
*
* @param base FlexCAN peripheral base address.
* @param handle FlexCAN handle pointer.
* @param count Number of CAN messages receive so far by the non-blocking transaction.
* @retval kStatus_InvalidArgument count is Invalid.
* @retval kStatus_Success Successfully return the count.
*/
status_t FLEXCAN_TransferGetReceiveFifoCountEMDA(CAN_Type *base, flexcan_edma_handle_t *handle, size_t *count);
/*!
* @brief Aborts the receive Legacy/Enhanced Rx FIFO process which used eDMA.
*
* This function aborts the receive Legacy/Enhanced Rx FIFO process which used eDMA.
*
* @param base FlexCAN peripheral base address.
* @param handle Pointer to flexcan_edma_handle_t structure.
*/
void FLEXCAN_TransferAbortReceiveFifoEDMA(CAN_Type *base, flexcan_edma_handle_t *handle);
#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
/*!
* @brief Receives the CAN FD Message from the Enhanced Rx FIFO using eDMA.
*
* This function receives the CAN FD Message using eDMA. This is a non-blocking function, which returns
* right away. After the CAN Message is received, the receive callback function is called.
*
* @param base FlexCAN peripheral base address.
* @param handle Pointer to flexcan_edma_handle_t structure.
* @param pFifoXfer FlexCAN Rx FIFO EDMA transfer structure, see #flexcan_fifo_transfer_t.
* @retval kStatus_Success if succeed, others failed.
* @retval kStatus_FLEXCAN_RxFifoBusy Previous transfer ongoing.
*/
status_t FLEXCAN_TransferReceiveEnhancedFifoEDMA(CAN_Type *base,
flexcan_edma_handle_t *handle,
flexcan_fifo_transfer_t *pFifoXfer);
/*!
* @brief Gets the Enhanced Rx Fifo transfer status during a interrupt non-blocking receive.
*
* @param base FlexCAN peripheral base address.
* @param handle FlexCAN handle pointer.
* @param count Number of CAN messages receive so far by the non-blocking transaction.
* @retval kStatus_InvalidArgument count is Invalid.
* @retval kStatus_Success Successfully return the count.
*/
static inline status_t FLEXCAN_TransferGetReceiveEnhancedFifoCountEMDA(CAN_Type *base,
flexcan_edma_handle_t *handle,
size_t *count)
{
return FLEXCAN_TransferGetReceiveFifoCountEMDA(base, handle, count);
}
#endif
/*! @} */
#if defined(__cplusplus)
}
#endif
/*! @}*/
#endif /* FSL_FLEXCAN_EDMA_H_ */
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio.c
+78
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@@ -20,6 +20,12 @@
/*< @brief user configurable flexio handle count. */
#define FLEXIO_HANDLE_COUNT 2
#if defined(FLEXIO_RSTS)
#define FLEXIO_RESETS_ARRAY FLEXIO_RSTS
#elif defined(FLEXIO_RSTS_N)
#define FLEXIO_RESETS_ARRAY FLEXIO_RSTS_N
#endif
/*******************************************************************************
* Variables
******************************************************************************/
@@ -43,6 +49,11 @@ static flexio_isr_t s_flexioIsr[FLEXIO_HANDLE_COUNT];
/* FlexIO common IRQ Handler. */
static void FLEXIO_CommonIRQHandler(void);
#if defined(FLEXIO_RESETS_ARRAY)
/* Reset array */
static const reset_ip_name_t s_flexioResets[] = FLEXIO_RESETS_ARRAY;
#endif
/*******************************************************************************
* Codes
******************************************************************************/
@@ -96,6 +107,10 @@ void FLEXIO_Init(FLEXIO_Type *base, const flexio_config_t *userConfig)
CLOCK_EnableClock(s_flexioClocks[FLEXIO_GetInstance(base)]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
#if defined(FLEXIO_RESETS_ARRAY)
RESET_ReleasePeripheralReset(s_flexioResets[FLEXIO_GetInstance(base)]);
#endif
FLEXIO_Reset(base);
ctrlReg = base->CTRL;
@@ -396,6 +411,69 @@ static void FLEXIO_CommonIRQHandler(void)
SDK_ISR_EXIT_BARRIER;
}
#if defined(FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER) && FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER
/*!
* brief Configure a FLEXIO pin used by the board.
*
* To Config the FLEXIO PIN, define a pin configuration, as either input or output, in the user file.
* Then, call the FLEXIO_SetPinConfig() function.
*
* This is an example to define an input pin or an output pin configuration.
* code
* Define a digital input pin configuration,
* flexio_gpio_config_t config =
* {
* kFLEXIO_DigitalInput,
* 0U,
* kFLEXIO_FlagRisingEdgeEnable | kFLEXIO_InputInterruptEnable,
* }
* Define a digital output pin configuration,
* flexio_gpio_config_t config =
* {
* kFLEXIO_DigitalOutput,
* 0U,
* 0U
* }
* endcode
* param base FlexIO peripheral base address
* param pin FLEXIO pin number.
* param config FLEXIO pin configuration pointer.
*/
void FLEXIO_SetPinConfig(FLEXIO_Type *base, uint32_t pin, flexio_gpio_config_t *config)
{
assert(NULL != config);
IRQn_Type flexio_irqs[] = FLEXIO_IRQS;
if (config->pinDirection == kFLEXIO_DigitalInput)
{
base->PINOUTE &= ~(1UL << pin);
if (0U != (config->inputConfig & (uint8_t)kFLEXIO_InputInterruptEnable))
{
base->PINIEN = 1UL << pin;
/* Clear pending NVIC IRQ before enable NVIC IRQ. */
NVIC_ClearPendingIRQ(flexio_irqs[FLEXIO_GetInstance(base)]);
/* Enable interrupt in NVIC. */
(void)EnableIRQ(flexio_irqs[FLEXIO_GetInstance(base)]);
}
if (0U != (config->inputConfig & (uint8_t)kFLEXIO_FlagRisingEdgeEnable))
{
base->PINREN = 1UL << pin;
}
if (0U != (config->inputConfig & (uint8_t)kFLEXIO_FlagFallingEdgeEnable))
{
base->PINFEN = 1UL << pin;
}
}
else
{
FLEXIO_EnablePinOutput(base, pin);
FLEXIO_PinWrite(base, pin, config->outputLogic);
}
}
#endif /*FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER*/
void FLEXIO_DriverIRQHandler(void);
void FLEXIO_DriverIRQHandler(void)
{
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio.h
+194 -12
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File diff suppressed because it is too large. Load diff
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_i2c_master.h
+11 -11
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@@ -5,8 +5,8 @@
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_FLEXIO_I2C_MASTER_H_
#define _FSL_FLEXIO_I2C_MASTER_H_
#ifndef FSL_FLEXIO_I2C_MASTER_H_
#define FSL_FLEXIO_I2C_MASTER_H_
#include "fsl_common.h"
#include "fsl_flexio.h"
@@ -21,9 +21,9 @@
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @{ */
#define FSL_FLEXIO_I2C_MASTER_DRIVER_VERSION (MAKE_VERSION(2, 5, 0))
/*@}*/
/*! @} */
/*! @brief Retry times for waiting flag. */
#ifndef I2C_RETRY_TIMES
@@ -207,7 +207,7 @@ static inline void FLEXIO_I2C_MasterEnable(FLEXIO_I2C_Type *base, bool enable)
}
}
/* @} */
/*! @} */
/*!
* @name Status
@@ -235,7 +235,7 @@ uint32_t FLEXIO_I2C_MasterGetStatusFlags(FLEXIO_I2C_Type *base);
void FLEXIO_I2C_MasterClearStatusFlags(FLEXIO_I2C_Type *base, uint32_t mask);
/*@}*/
/*! @} */
/*!
* @name Interrupts
@@ -260,7 +260,7 @@ void FLEXIO_I2C_MasterEnableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask);
*/
void FLEXIO_I2C_MasterDisableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask);
/*@}*/
/*! @} */
/*!
* @name Bus Operations
@@ -402,7 +402,7 @@ status_t FLEXIO_I2C_MasterReadBlocking(FLEXIO_I2C_Type *base, uint8_t *rxBuff, u
* @return status of status_t.
*/
status_t FLEXIO_I2C_MasterTransferBlocking(FLEXIO_I2C_Type *base, flexio_i2c_master_transfer_t *xfer);
/*@}*/
/*! @} */
/*Transactional APIs*/
@@ -475,11 +475,11 @@ void FLEXIO_I2C_MasterTransferAbort(FLEXIO_I2C_Type *base, flexio_i2c_master_han
*/
void FLEXIO_I2C_MasterTransferHandleIRQ(void *i2cType, void *i2cHandle);
/*@}*/
/*! @} */
#if defined(__cplusplus)
}
#endif /*_cplusplus*/
/*@}*/
/*! @} */
#endif /*_FSL_FLEXIO_I2C_MASTER_H_*/
#endif /*FSL_FLEXIO_I2C_MASTER_H_*/
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_mculcd.c
+65 -42
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File diff suppressed because it is too large. Load diff
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_mculcd.h
+18 -17
View File
@@ -1,13 +1,13 @@
/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2021, 2022 NXP
* Copyright 2016-2023 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_FLEXIO_MCULCD_H_
#define _FSL_FLEXIO_MCULCD_H_
#ifndef FSL_FLEXIO_MCULCD_H_
#define FSL_FLEXIO_MCULCD_H_
#include "fsl_common.h"
#include "fsl_flexio.h"
@@ -22,10 +22,10 @@
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @{ */
/*! @brief FlexIO MCULCD driver version. */
#define FSL_FLEXIO_MCULCD_DRIVER_VERSION (MAKE_VERSION(2, 0, 7))
/*@}*/
#define FSL_FLEXIO_MCULCD_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
/*! @} */
#ifndef FLEXIO_MCULCD_WAIT_COMPLETE_TIME
/*!
@@ -129,7 +129,7 @@ typedef struct _flexio_mculcd_config
bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers,
fast access requires the FlexIO clock to be at least
twice the frequency of the bus clock. */
uint32_t baudRate_Bps; /*!< Baud rate in Bps. */
uint32_t baudRate_Bps; /*!< Baud rate in bit-per-second for all data lines combined. */
} flexio_mculcd_config_t;
/*! @brief Transfer mode.*/
@@ -144,11 +144,12 @@ typedef enum _flexio_mculcd_transfer_mode
typedef struct _flexio_mculcd_transfer
{
uint32_t command; /*!< Command to send. */
flexio_mculcd_transfer_mode_t mode; /*!< Transfer mode. */
uint32_t dataAddrOrSameValue; /*!< When sending the same value for many times,
this is the value to send. When writing or reading array,
this is the address of the data array. */
size_t dataSize; /*!< How many bytes to transfer. */
flexio_mculcd_transfer_mode_t mode; /*!< Transfer mode. */
bool dataOnly; /*!< Send data only when tx without the command. */
} flexio_mculcd_transfer_t;
/*! @brief typedef for flexio_mculcd_handle_t in advance. */
@@ -229,7 +230,7 @@ void FLEXIO_MCULCD_Deinit(FLEXIO_MCULCD_Type *base);
*/
void FLEXIO_MCULCD_GetDefaultConfig(flexio_mculcd_config_t *config);
/*@}*/
/*! @} */
/*!
* @name Status
@@ -257,7 +258,7 @@ uint32_t FLEXIO_MCULCD_GetStatusFlags(FLEXIO_MCULCD_Type *base);
*/
void FLEXIO_MCULCD_ClearStatusFlags(FLEXIO_MCULCD_Type *base, uint32_t mask);
/*@}*/
/*! @} */
/*!
* @name Interrupts
@@ -286,7 +287,7 @@ void FLEXIO_MCULCD_EnableInterrupts(FLEXIO_MCULCD_Type *base, uint32_t mask);
*/
void FLEXIO_MCULCD_DisableInterrupts(FLEXIO_MCULCD_Type *base, uint32_t mask);
/*@}*/
/*! @} */
/*!
* @name DMA Control
@@ -343,7 +344,7 @@ static inline uint32_t FLEXIO_MCULCD_GetRxDataRegisterAddress(FLEXIO_MCULCD_Type
return (uint32_t) & (base->flexioBase->SHIFTBUF[base->rxShifterStartIndex]);
}
/*@}*/
/*! @} */
/*!
* @name Bus Operations
@@ -354,7 +355,7 @@ static inline uint32_t FLEXIO_MCULCD_GetRxDataRegisterAddress(FLEXIO_MCULCD_Type
* @brief Set desired baud rate.
*
* @param base Pointer to the FLEXIO_MCULCD_Type structure.
* @param baudRate_Bps Desired baud rate.
* @param baudRate_Bps Desired baud rate in bit-per-second for all data lines combined.
* @param srcClock_Hz FLEXIO clock frequency in Hz.
* @retval kStatus_Success Set successfully.
* @retval kStatus_InvalidArgument Could not set the baud rate.
@@ -602,7 +603,7 @@ void FLEXIO_MCULCD_WriteSameValueBlocking(FLEXIO_MCULCD_Type *base, uint32_t sam
* @param xfer pointer to flexio_mculcd_transfer_t structure.
*/
void FLEXIO_MCULCD_TransferBlocking(FLEXIO_MCULCD_Type *base, flexio_mculcd_transfer_t *xfer);
/*@}*/
/*! @} */
/*!
* @name Transactional
@@ -675,11 +676,11 @@ status_t FLEXIO_MCULCD_TransferGetCount(FLEXIO_MCULCD_Type *base, flexio_mculcd_
*/
void FLEXIO_MCULCD_TransferHandleIRQ(void *base, void *handle);
/*@}*/
/*! @} */
#if defined(__cplusplus)
}
#endif /*_cplusplus*/
/*@}*/
/*! @} */
#endif /*_FSL_FLEXIO_MCULCD_H_*/
#endif /*FSL_FLEXIO_MCULCD_H_*/
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_mculcd_edma.c
+7 -99
View File
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2019 NXP
* Copyright 2016-2019,2023 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -460,8 +460,12 @@ status_t FLEXIO_MCULCD_TransferEDMA(FLEXIO_MCULCD_Type *base,
/* Setup DMA to transfer data. */
/* Assert the nCS. */
FLEXIO_MCULCD_StartTransfer(base);
/* Send the command. */
FLEXIO_MCULCD_WriteCommandBlocking(base, xfer->command);
if (!xfer->dataOnly)
{
/* Send the command. */
FLEXIO_MCULCD_WriteCommandBlocking(base, xfer->command);
}
/* Setup the DMA configuration. */
FLEXIO_MCULCD_EDMAConfig(base, handle);
@@ -494,102 +498,6 @@ status_t FLEXIO_MCULCD_TransferEDMA(FLEXIO_MCULCD_Type *base,
return kStatus_Success;
}
/*!
* brief Performs a non-blocking FlexIO MCULCD data write using eDMA.
*
* This function returns immediately after transfer initiates. To check whether
* the transfer is completed, user could:
* 1. Use the transfer completed callback;
* 2. Polling function ref FLEXIO_MCULCD_GetTransferCountEDMA
*
* param base pointer to FLEXIO_MCULCD_Type structure.
* param handle pointer to flexio_mculcd_edma_handle_t structure to store the
* transfer state.
* param data Pointer to data.
* param size Size(in bytes) of the data
* retval kStatus_Success Successfully start a transfer.
* retval kStatus_InvalidArgument Input argument is invalid.
* retval kStatus_FLEXIO_MCULCD_Busy FlexIO MCULCD is not idle, it is running another
* transfer.
*/
status_t FLEXIO_MCULCD_WriteDataEDMA(FLEXIO_MCULCD_Type *base,
flexio_mculcd_edma_handle_t *handle,
const void *data, size_t size)
{
assert(NULL != handle);
assert(NULL != data);
/*
* The data transfer mechanism:
*
* Read:
* Assume the data length is Lr = (n1 * minorLoopBytes + n2), where
* n2 < minorLoopBytes.
* If (n1 <= 1), then all data are sent using blocking method.
* If (n1 > 1), then the beginning ((n1-1) * minorLoopBytes) are read
* using DMA, the left (minorLoopBytes + n2) are read using blocking method.
*
* Write:
* Assume the data length is Lw = (n1 * minorLoopBytes + n2), where
* n2 < minorLoopBytes.
* If (n1 = 0), then all data are sent using blocking method.
* If (n1 >= 1), then the beginning (n1 * minorLoopBytes) are sent
* using DMA, the left n2 are sent using blocking method.
*/
/* Check if the device is busy. */
if ((uint32_t)kFLEXIO_MCULCD_StateIdle != handle->state)
{
return kStatus_FLEXIO_MCULCD_Busy;
}
/* Set the state in handle. */
handle->minorLoopBytes = handle->txShifterNum * 4UL;
handle->state = (uint32_t)kFLEXIO_MCULCD_StateWriteArray;
/*
* For TX, if data is less than one minor loop, then use polling method.
* For RX, if data is less than two minor loop, then use polling method.
*/
if (size < handle->minorLoopBytes)
{
FLEXIO_MCULCD_WriteDataArrayBlocking(base, data, size);
handle->state = (uint32_t)kFLEXIO_MCULCD_StateIdle;
/* Callback to inform upper layer. */
if (NULL != handle->completionCallback)
{
handle->completionCallback(base, handle, kStatus_FLEXIO_MCULCD_Idle, handle->userData);
}
}
else
{
handle->dataCount = size;
handle->remainingCount = size;
handle->dataAddrOrSameValue = (uint32_t)data;
/* Setup DMA to transfer data. */
/* Assert the nCS. */
FLEXIO_MCULCD_StartTransfer(base);
/* Setup the DMA configuration. */
FLEXIO_MCULCD_EDMAConfig(base, handle);
/* Start the transfer. */
/* For 6800, de-assert the RDWR pin. */
if (kFLEXIO_MCULCD_6800 == base->busType)
{
base->setRDWRPin(false);
}
FLEXIO_MCULCD_SetMultiBeatsWriteConfig(base);
FLEXIO_MCULCD_EnableTxDMA(base, true);
EDMA_StartTransfer(handle->txDmaHandle);
}
return kStatus_Success;
}
/*!
* brief Aborts a FlexIO MCULCD transfer using eDMA.
*
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_mculcd_edma.h
+7 -28
View File
@@ -1,13 +1,13 @@
/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2020 NXP
* Copyright 2016-2020,2023 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_FLEXIO_MCULCD_EDMA_H_
#define _FSL_FLEXIO_MCULCD_EDMA_H_
#ifndef FSL_FLEXIO_MCULCD_EDMA_H_
#define FSL_FLEXIO_MCULCD_EDMA_H_
#include "fsl_edma.h"
#include "fsl_flexio_mculcd.h"
@@ -21,10 +21,10 @@
* Definitions
******************************************************************************/
/*@{*/
/*! @{ */
/*! @brief FlexIO MCULCD EDMA driver version. */
#define FSL_FLEXIO_MCULCD_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 4))
/*@}*/
#define FSL_FLEXIO_MCULCD_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 5))
/*! @} */
/*! @brief typedef for flexio_mculcd_edma_handle_t in advance. */
typedef struct _flexio_mculcd_edma_handle flexio_mculcd_edma_handle_t;
@@ -119,27 +119,6 @@ status_t FLEXIO_MCULCD_TransferCreateHandleEDMA(FLEXIO_MCULCD_Type *base,
status_t FLEXIO_MCULCD_TransferEDMA(FLEXIO_MCULCD_Type *base,
flexio_mculcd_edma_handle_t *handle,
flexio_mculcd_transfer_t *xfer);
/*!
* brief Performs a non-blocking FlexIO MCULCD data write using eDMA.
*
* This function returns immediately after transfer initiates. To check whether
* the transfer is completed, user could:
* 1. Use the transfer completed callback;
* 2. Polling function ref FLEXIO_MCULCD_GetTransferCountEDMA
*
* param base pointer to FLEXIO_MCULCD_Type structure.
* param handle pointer to flexio_mculcd_edma_handle_t structure to store the
* transfer state.
* param data Pointer to data.
* param size Size(in bytes) of the data
* retval kStatus_Success Successfully start a transfer.
* retval kStatus_InvalidArgument Input argument is invalid.
* retval kStatus_FLEXIO_MCULCD_Busy FlexIO MCULCD is not idle, it is running another
* transfer.
*/
status_t FLEXIO_MCULCD_WriteDataEDMA(FLEXIO_MCULCD_Type *base,
flexio_mculcd_edma_handle_t *handle,
const void *data, size_t size);
/*!
* @brief Aborts a FlexIO MCULCD transfer using eDMA.
@@ -171,4 +150,4 @@ status_t FLEXIO_MCULCD_TransferGetCountEDMA(FLEXIO_MCULCD_Type *base,
/*!
* @}
*/
#endif /* _FSL_FLEXIO_MCULCD_EDMA_H_ */
#endif /* FSL_FLEXIO_MCULCD_EDMA_H_ */
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_mculcd_smartdma.c
+407
View File
File diff suppressed because it is too large. Load diff
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_mculcd_smartdma.h
+158
View File
@@ -0,0 +1,158 @@
/*
* Copyright 2019,2021,2023 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef FSL_FLEXIO_MCULCD_SMARTDMA_H_
#define FSL_FLEXIO_MCULCD_SMARTDMA_H_
#include "fsl_smartdma.h"
#include "fsl_flexio_mculcd.h"
/*!
* @addtogroup flexio_smartdma_mculcd
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*@{*/
/*! @brief FlexIO MCULCD SMARTDMA driver version. */
#define FSL_FLEXIO_MCULCD_SMARTDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 4))
/*@}*/
/*! @brief SMARTDMA transfer size should be multiple of 64 bytes. */
#define FLEXIO_MCULCD_SMARTDMA_TX_LEN_ALIGN 64U
/*! @brief SMARTDMA transfer memory address should be 4 byte aligned. */
#define FLEXIO_MCULCD_SMARTDMA_TX_ADDR_ALIGN 4U
/*! @brief typedef for flexio_mculcd_smartdma_handle_t in advance. */
typedef struct _flexio_mculcd_smartdma_handle flexio_mculcd_smartdma_handle_t;
/*! @brief FlexIO MCULCD master callback for transfer complete.
*
* When transfer finished, the callback function is called and returns the
* @p status as kStatus_FLEXIO_MCULCD_Idle.
*/
typedef void (*flexio_mculcd_smartdma_transfer_callback_t)(FLEXIO_MCULCD_Type *base,
flexio_mculcd_smartdma_handle_t *handle,
status_t status,
void *userData);
/*! @brief FlexIO MCULCD SMARTDMA transfer handle, users should not touch the
* content of the handle.*/
struct _flexio_mculcd_smartdma_handle
{
FLEXIO_MCULCD_Type *base; /*!< Pointer to the FLEXIO_MCULCD_Type. */
size_t dataCount; /*!< Total count to be transferred. */
uint32_t dataAddrOrSameValue; /*!< When sending the same value for many times,
this is the value to send. When writing or reading array,
this is the address of the data array. */
size_t dataCountUsingEzh; /*!< Data transfered using SMARTDMA. */
volatile size_t remainingCount; /*!< Remaining count to transfer. */
volatile uint32_t state; /*!< FlexIO MCULCD driver internal state. */
uint8_t smartdmaApi; /*!< The SMARTDMA API used during transfer. */
bool needColorConvert; /*!< Need color convert or not. */
uint8_t blockingXferBuffer[FLEXIO_MCULCD_SMARTDMA_TX_LEN_ALIGN * 3 /
2]; /*!< Used for blocking method color space convet. */
flexio_mculcd_smartdma_transfer_callback_t completionCallback; /*!< Callback for MCULCD SMARTDMA transfer */
void *userData; /*!< User Data for MCULCD SMARTDMA callback */
smartdma_flexio_mculcd_param_t smartdmaParam; /*!< SMARTDMA function parameters. */
uint32_t smartdmaStack[1]; /*!< SMARTDMA function stack. */
};
/*! @brief FlexIO MCULCD SMARTDMA configuration. */
typedef struct _flexio_mculcd_smartdma_config
{
flexio_mculcd_pixel_format_t inputPixelFormat; /*!< The pixel format in the frame buffer. */
flexio_mculcd_pixel_format_t outputPixelFormat; /*!< The pixel format on the 8080/68k bus. */
} flexio_mculcd_smartdma_config_t;
/*******************************************************************************
* APIs
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @name SMARTDMA Transactional
* @{
*/
/*!
* @brief Initializes the FLEXO MCULCD master SMARTDMA handle.
*
* This function initializes the FLEXO MCULCD master SMARTDMA handle which can be
* used for other FLEXO MCULCD transactional APIs. For a specified FLEXO MCULCD
* instance, call this API once to get the initialized handle.
*
* @param base Pointer to FLEXIO_MCULCD_Type structure.
* @param handle Pointer to flexio_mculcd_smartdma_handle_t structure to store the
* transfer state.
* @param config Pointer to the configuration.
* @param callback MCULCD transfer complete callback, NULL means no callback.
* @param userData callback function parameter.
* @retval kStatus_Success Successfully create the handle.
*/
status_t FLEXIO_MCULCD_TransferCreateHandleSMARTDMA(FLEXIO_MCULCD_Type *base,
flexio_mculcd_smartdma_handle_t *handle,
const flexio_mculcd_smartdma_config_t *config,
flexio_mculcd_smartdma_transfer_callback_t callback,
void *userData);
/*!
* @brief Performs a non-blocking FlexIO MCULCD transfer using SMARTDMA.
*
* This function returns immediately after transfer initiates. Use the callback
* function to check whether the transfer is completed.
*
* @param base pointer to FLEXIO_MCULCD_Type structure.
* @param handle pointer to flexio_mculcd_smartdma_handle_t structure to store the
* transfer state.
* @param xfer Pointer to FlexIO MCULCD transfer structure.
* @retval kStatus_Success Successfully start a transfer.
* @retval kStatus_InvalidArgument Input argument is invalid.
* @retval kStatus_FLEXIO_MCULCD_Busy FlexIO MCULCD is not idle, it is running another
* transfer.
*/
status_t FLEXIO_MCULCD_TransferSMARTDMA(FLEXIO_MCULCD_Type *base,
flexio_mculcd_smartdma_handle_t *handle,
flexio_mculcd_transfer_t *xfer);
/*!
* @brief Aborts a FlexIO MCULCD transfer using SMARTDMA.
*
* @param base pointer to FLEXIO_MCULCD_Type structure.
* @param handle FlexIO MCULCD SMARTDMA handle pointer.
*/
void FLEXIO_MCULCD_TransferAbortSMARTDMA(FLEXIO_MCULCD_Type *base, flexio_mculcd_smartdma_handle_t *handle);
/*!
* @brief Gets the remaining bytes for FlexIO MCULCD SMARTDMA transfer.
*
* @param base pointer to FLEXIO_MCULCD_Type structure.
* @param handle FlexIO MCULCD SMARTDMA handle pointer.
* @param count Number of count transferred so far by the SMARTDMA transaction.
* @retval kStatus_Success Get the transferred count Successfully.
* @retval kStatus_NoTransferInProgress No transfer in process.
*/
status_t FLEXIO_MCULCD_TransferGetCountSMARTDMA(FLEXIO_MCULCD_Type *base,
flexio_mculcd_smartdma_handle_t *handle,
size_t *count);
/*! @} */
#if defined(__cplusplus)
}
#endif
/*!
* @}
*/
#endif /* FSL_FLEXIO_MCULCD_SMARTDMA_H_ */
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_spi.c
+14 -2
View File
@@ -1229,7 +1229,12 @@ status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base,
/* Enable transmit and receive interrupt to handle rx. */
FLEXIO_SPI_EnableInterrupts(base, (uint32_t)kFLEXIO_SPI_RxFullInterruptEnable);
if ((xfer->flags & (uint8_t)kFLEXIO_SPI_csContinuous) != 0U)
{
FLEXIO_SPI_EnableInterrupts(base, (uint32_t)kFLEXIO_SPI_TxEmptyInterruptEnable);
}
return kStatus_Success;
}
@@ -1307,8 +1312,15 @@ void FLEXIO_SPI_MasterTransferHandleIRQ(void *spiType, void *spiHandle)
base = (FLEXIO_SPI_Type *)spiType;
status = FLEXIO_SPI_GetStatusFlags(base);
/* Receive interrupt. */
if ((status & (uint32_t)kFLEXIO_SPI_RxBufferFullFlag) == 0U)
{
FLEXIO_SPI_TransferSendTransaction(base, handle);
return;
}
/* Handle rx. */
if (((status & (uint32_t)kFLEXIO_SPI_RxBufferFullFlag) != 0U) && (handle->rxRemainingBytes != 0U))
if (handle->rxRemainingBytes != 0U)
{
FLEXIO_SPI_TransferReceiveTransaction(base, handle);
}
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_spi.h
+16 -17
View File
@@ -6,8 +6,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_FLEXIO_SPI_H_
#define _FSL_FLEXIO_SPI_H_
#ifndef FSL_FLEXIO_SPI_H_
#define FSL_FLEXIO_SPI_H_
#include "fsl_common.h"
#include "fsl_flexio.h"
@@ -22,14 +22,14 @@
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @{ */
/*! @brief FlexIO SPI driver version. */
#define FSL_FLEXIO_SPI_DRIVER_VERSION (MAKE_VERSION(2, 3, 0))
/*@}*/
#define FSL_FLEXIO_SPI_DRIVER_VERSION (MAKE_VERSION(2, 3, 4))
/*! @} */
#ifndef FLEXIO_SPI_DUMMYDATA
/*! @brief FlexIO SPI dummy transfer data, the data is sent while txData is NULL. */
#define FLEXIO_SPI_DUMMYDATA (0xFFFFFFFFU)
#define FLEXIO_SPI_DUMMYDATA (0x00U)
#endif
/*! @brief Retry times for waiting flag. */
@@ -152,7 +152,7 @@ typedef struct _flexio_spi_slave_config
/*! @brief Define FlexIO SPI transfer structure. */
typedef struct _flexio_spi_transfer
{
uint8_t *txData; /*!< Send buffer. */
const uint8_t *txData; /*!< Send buffer. */
uint8_t *rxData; /*!< Receive buffer. */
size_t dataSize; /*!< Transfer bytes. */
uint8_t flags; /*!< FlexIO SPI control flag, MSB first or LSB first. */
@@ -179,7 +179,7 @@ typedef void (*flexio_spi_slave_transfer_callback_t)(FLEXIO_SPI_Type *base,
/*! @brief Define FlexIO SPI handle structure. */
struct _flexio_spi_master_handle
{
uint8_t *txData; /*!< Transfer buffer. */
const uint8_t *txData; /*!< Transfer buffer. */
uint8_t *rxData; /*!< Receive buffer. */
size_t transferSize; /*!< Total bytes to be transferred. */
volatile size_t txRemainingBytes; /*!< Send data remaining in bytes. */
@@ -323,7 +323,7 @@ void FLEXIO_SPI_SlaveDeinit(FLEXIO_SPI_Type *base);
*/
void FLEXIO_SPI_SlaveGetDefaultConfig(flexio_spi_slave_config_t *slaveConfig);
/*@}*/
/*! @} */
/*!
* @name Status
@@ -353,7 +353,7 @@ uint32_t FLEXIO_SPI_GetStatusFlags(FLEXIO_SPI_Type *base);
void FLEXIO_SPI_ClearStatusFlags(FLEXIO_SPI_Type *base, uint32_t mask);
/*@}*/
/*! @} */
/*!
* @name Interrupts
@@ -384,7 +384,7 @@ void FLEXIO_SPI_EnableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask);
*/
void FLEXIO_SPI_DisableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask);
/*@}*/
/*! @} */
/*!
* @name DMA Control
@@ -447,7 +447,7 @@ static inline uint32_t FLEXIO_SPI_GetRxDataRegisterAddress(FLEXIO_SPI_Type *base
}
}
/*@}*/
/*! @} */
/*!
* @name Bus Operations
@@ -548,7 +548,6 @@ status_t FLEXIO_SPI_WriteBlocking(FLEXIO_SPI_Type *base,
* @param direction Shift direction of MSB first or LSB first.
* @param buffer The buffer to store the received bytes.
* @param size The number of data bytes to be received.
* @param direction Shift direction of MSB first or LSB first.
* @retval kStatus_Success Successfully create the handle.
* @retval kStatus_FLEXIO_SPI_Timeout The transfer timed out and was aborted.
*/
@@ -575,7 +574,7 @@ status_t FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_tra
* @param base Pointer to the FLEXIO_SPI_Type structure.
*/
void FLEXIO_SPI_FlushShifters(FLEXIO_SPI_Type *base);
/*@}*/
/*! @} */
/*Transactional APIs*/
@@ -709,11 +708,11 @@ static inline status_t FLEXIO_SPI_SlaveTransferGetCount(FLEXIO_SPI_Type *base,
*/
void FLEXIO_SPI_SlaveTransferHandleIRQ(void *spiType, void *spiHandle);
/*@}*/
/*! @} */
#if defined(__cplusplus)
}
#endif /*_cplusplus*/
/*@}*/
/*! @} */
#endif /*_FSL_FLEXIO_SPI_H_*/
#endif /*FSL_FLEXIO_SPI_H_*/
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_spi_edma.h
+4 -4
View File
@@ -5,8 +5,8 @@
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_FLEXIO_SPI_EDMA_H_
#define _FSL_FLEXIO_SPI_EDMA_H_
#ifndef FSL_FLEXIO_SPI_EDMA_H_
#define FSL_FLEXIO_SPI_EDMA_H_
#include "fsl_flexio_spi.h"
#include "fsl_edma.h"
@@ -21,10 +21,10 @@
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @{ */
/*! @brief FlexIO SPI EDMA driver version. */
#define FSL_FLEXIO_SPI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 3, 0))
/*@}*/
/*! @} */
/*! @brief typedef for flexio_spi_master_edma_handle_t in advance. */
typedef struct _flexio_spi_master_edma_handle flexio_spi_master_edma_handle_t;
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_uart.c
+14
View File
@@ -1007,3 +1007,17 @@ void FLEXIO_UART_TransferHandleIRQ(void *uartType, void *uartHandle)
}
}
}
/*!
* brief Flush tx/rx shifters.
*
* param base Pointer to the FLEXIO_UART_Type structure.
*/
void FLEXIO_UART_FlushShifters(FLEXIO_UART_Type *base)
{
/* Disable then re-enable to flush the tx shifter. */
base->flexioBase->SHIFTCTL[base->shifterIndex[0]] &= ~FLEXIO_SHIFTCTL_SMOD_MASK;
base->flexioBase->SHIFTCTL[base->shifterIndex[0]] |= FLEXIO_SHIFTCTL_SMOD(kFLEXIO_ShifterModeTransmit);
/* Read to flush the rx shifter. */
(void)base->flexioBase->SHIFTBUF[base->shifterIndex[1]];
}
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_uart.h
+20 -13
View File
@@ -6,8 +6,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_FLEXIO_UART_H_
#define _FSL_FLEXIO_UART_H_
#ifndef FSL_FLEXIO_UART_H_
#define FSL_FLEXIO_UART_H_
#include "fsl_common.h"
#include "fsl_flexio.h"
@@ -22,10 +22,10 @@
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @{ */
/*! @brief FlexIO UART driver version. */
#define FSL_FLEXIO_UART_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))
/*@}*/
#define FSL_FLEXIO_UART_DRIVER_VERSION (MAKE_VERSION(2, 5, 0))
/*! @} */
/*! @brief Retry times for waiting flag. */
#ifndef UART_RETRY_TIMES
@@ -208,7 +208,7 @@ void FLEXIO_UART_Deinit(FLEXIO_UART_Type *base);
*/
void FLEXIO_UART_GetDefaultConfig(flexio_uart_config_t *userConfig);
/* @} */
/*! @} */
/*!
* @name Status
@@ -237,7 +237,7 @@ uint32_t FLEXIO_UART_GetStatusFlags(FLEXIO_UART_Type *base);
void FLEXIO_UART_ClearStatusFlags(FLEXIO_UART_Type *base, uint32_t mask);
/* @} */
/*! @} */
/*!
* @name Interrupts
@@ -264,7 +264,7 @@ void FLEXIO_UART_EnableInterrupts(FLEXIO_UART_Type *base, uint32_t mask);
*/
void FLEXIO_UART_DisableInterrupts(FLEXIO_UART_Type *base, uint32_t mask);
/* @} */
/*! @} */
/*!
* @name DMA Control
@@ -323,7 +323,7 @@ static inline void FLEXIO_UART_EnableRxDMA(FLEXIO_UART_Type *base, bool enable)
FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1UL << base->shifterIndex[1], enable);
}
/* @} */
/*! @} */
/*!
* @name Bus Operations
@@ -399,7 +399,7 @@ status_t FLEXIO_UART_WriteBlocking(FLEXIO_UART_Type *base, const uint8_t *txData
*/
status_t FLEXIO_UART_ReadBlocking(FLEXIO_UART_Type *base, uint8_t *rxData, size_t rxSize);
/* @} */
/*! @} */
/*!
* @name Transactional
@@ -571,11 +571,18 @@ status_t FLEXIO_UART_TransferGetReceiveCount(FLEXIO_UART_Type *base, flexio_uart
*/
void FLEXIO_UART_TransferHandleIRQ(void *uartType, void *uartHandle);
/*@}*/
/*!
* @brief Flush tx/rx shifters.
*
* @param base Pointer to the FLEXIO_UART_Type structure.
*/
void FLEXIO_UART_FlushShifters(FLEXIO_UART_Type *base);
/*! @} */
#if defined(__cplusplus)
}
#endif /*_cplusplus*/
/*@}*/
/*! @} */
#endif /*_FSL_FLEXIO_UART_H_*/
#endif /*FSL_FLEXIO_UART_H_*/
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_uart_edma.h
+6 -6
View File
@@ -5,8 +5,8 @@
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_FLEXIO_UART_EDMA_H_
#define _FSL_FLEXIO_UART_EDMA_H_
#ifndef FSL_FLEXIO_UART_EDMA_H_
#define FSL_FLEXIO_UART_EDMA_H_
#include "fsl_flexio_uart.h"
#include "fsl_edma.h"
@@ -21,10 +21,10 @@
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @{ */
/*! @brief FlexIO UART EDMA driver version. */
#define FSL_FLEXIO_UART_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 4, 1))
/*@}*/
/*! @} */
/* Forward declaration of the handle typedef. */
typedef struct _flexio_uart_edma_handle flexio_uart_edma_handle_t;
@@ -167,7 +167,7 @@ status_t FLEXIO_UART_TransferGetReceiveCountEDMA(FLEXIO_UART_Type *base,
flexio_uart_edma_handle_t *handle,
size_t *count);
/*@}*/
/*! @} */
#if defined(__cplusplus)
}
@@ -175,4 +175,4 @@ status_t FLEXIO_UART_TransferGetReceiveCountEDMA(FLEXIO_UART_Type *base,
/*! @}*/
#endif /* _FSL_UART_EDMA_H_ */
#endif /* FSL_UART_EDMA_H_ */
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexspi.c
+27 -19
View File
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2022 NXP
* Copyright 2016-2022, 2023 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -118,7 +118,7 @@ static flexspi_isr_t s_flexspiIsr;
static void FLEXSPI_Memset(void *src, uint8_t value, size_t length)
{
assert(src != NULL);
uint8_t *p = src;
uint8_t *p = (uint8_t *)src;
for (uint32_t i = 0U; i < length; i++)
{
@@ -192,6 +192,9 @@ static uint32_t FLEXSPI_CalculateDll(FLEXSPI_Type *base, flexspi_device_config_t
/* DLLEN = 1, SLVDLYTARGET = 0xF, */
flexspiDllValue = FLEXSPI_DLLCR_DLLEN(1) | FLEXSPI_DLLCR_SLVDLYTARGET(0x0F);
#endif
#if (defined(FSL_FEATURE_FLEXSPI_HAS_REFPHASEGAP) && FSL_FEATURE_FLEXSPI_HAS_REFPHASEGAP)
flexspiDllValue |= FLEXSPI_DLLCR_REFPHASEGAP(2U);
#endif /* FSL_FEATURE_FLEXSPI_HAS_REFPHASEGAP */
}
else
{
@@ -235,10 +238,6 @@ status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status)
/* Clear the flags. */
FLEXSPI_ClearInterruptStatusFlags(base, status);
/* Reset fifos. These flags clear automatically. */
base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK;
base->IPRXFCR |= FLEXSPI_IPRXFCR_CLRIPRXF_MASK;
}
return result;
@@ -712,7 +711,7 @@ status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint8_t *buffer, size_t size)
}
/* Push a watermark level data into IP TX FIFO. */
base->INTR |= (uint32_t)kFLEXSPI_IpTxFifoWatermarkEmptyFlag;
base->INTR = (uint32_t)kFLEXSPI_IpTxFifoWatermarkEmptyFlag;
}
return result;
@@ -819,7 +818,7 @@ status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint8_t *buffer, size_t size)
}
/* Pop out a watermark level datas from IP RX FIFO. */
base->INTR |= (uint32_t)kFLEXSPI_IpRxFifoWatermarkAvailableFlag;
base->INTR = (uint32_t)kFLEXSPI_IpRxFifoWatermarkAvailableFlag;
}
return result;
@@ -843,8 +842,8 @@ status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer)
base->FLSHCR2[xfer->port] |= FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK;
/* Clear former pending status before start this transfer. */
base->INTR |= FLEXSPI_INTR_AHBCMDERR_MASK | FLEXSPI_INTR_IPCMDERR_MASK | FLEXSPI_INTR_AHBCMDGE_MASK |
FLEXSPI_INTR_IPCMDGE_MASK;
base->INTR = FLEXSPI_INTR_AHBCMDERR_MASK | FLEXSPI_INTR_IPCMDERR_MASK | FLEXSPI_INTR_AHBCMDGE_MASK |
FLEXSPI_INTR_IPCMDGE_MASK | FLEXSPI_INTR_IPCMDDONE_MASK;
/* Configure base address. */
base->IPCR0 = xfer->deviceAddress;
@@ -880,12 +879,13 @@ status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer)
/* Empty else. */
}
/* Wait for bus to be idle before changing flash configuration. */
while (!FLEXSPI_GetBusIdleStatus(base))
/* Wait until the IP command execution finishes */
while (0UL == (base->INTR & FLEXSPI_INTR_IPCMDDONE_MASK))
{
}
if (xfer->cmdType == kFLEXSPI_Command)
/* Unless there is an error status already set, capture the latest one */
if (result == kStatus_Success)
{
result = FLEXSPI_CheckAndClearError(base, base->INTR);
}
@@ -966,8 +966,8 @@ status_t FLEXSPI_TransferNonBlocking(FLEXSPI_Type *base, flexspi_handle_t *handl
base->FLSHCR2[xfer->port] |= FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK;
/* Clear former pending status before start this transfer. */
base->INTR |= FLEXSPI_INTR_AHBCMDERR_MASK | FLEXSPI_INTR_IPCMDERR_MASK | FLEXSPI_INTR_AHBCMDGE_MASK |
FLEXSPI_INTR_IPCMDGE_MASK;
base->INTR = FLEXSPI_INTR_AHBCMDERR_MASK | FLEXSPI_INTR_IPCMDERR_MASK | FLEXSPI_INTR_AHBCMDGE_MASK |
FLEXSPI_INTR_IPCMDGE_MASK | FLEXSPI_INTR_IPCMDDONE_MASK;
/* Configure base address. */
base->IPCR0 = xfer->deviceAddress;
@@ -1067,7 +1067,7 @@ void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle)
uint32_t intEnableStatus;
uint32_t txWatermark;
uint32_t rxWatermark;
uint8_t i = 0;
uint32_t i = 0;
status = base->INTR;
intEnableStatus = base->INTEN;
@@ -1130,12 +1130,12 @@ void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle)
handle->dataSize = 0;
}
/* Pop out a watermark level data from IP RX FIFO. */
base->INTR |= (uint32_t)kFLEXSPI_IpRxFifoWatermarkAvailableFlag;
base->INTR = (uint32_t)kFLEXSPI_IpRxFifoWatermarkAvailableFlag;
}
if (0U != (status & (uint32_t)kFLEXSPI_IpCommandExecutionDoneFlag))
{
base->INTR |= (uint32_t)kFLEXSPI_IpCommandExecutionDoneFlag;
base->INTR = (uint32_t)kFLEXSPI_IpCommandExecutionDoneFlag;
FLEXSPI_TransferAbort(base, handle);
@@ -1192,7 +1192,7 @@ void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle)
}
/* Push a watermark level data into IP TX FIFO. */
base->INTR |= (uint32_t)kFLEXSPI_IpTxFifoWatermarkEmptyFlag;
base->INTR = (uint32_t)kFLEXSPI_IpTxFifoWatermarkEmptyFlag;
}
}
else
@@ -1233,6 +1233,14 @@ void FLEXSPI1_DriverIRQHandler(void)
SDK_ISR_EXIT_BARRIER;
}
#endif
#if defined(FLEXSPI2)
void FLEXSPI2_DriverIRQHandler(void);
void FLEXSPI2_DriverIRQHandler(void)
{
s_flexspiIsr(FLEXSPI2, s_flexspiHandle[2]);
SDK_ISR_EXIT_BARRIER;
}
#endif
#if defined(LSIO__FLEXSPI0)
void LSIO_OCTASPI0_INT_DriverIRQHandler(void);
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexspi.h
+36 -18
View File
@@ -1,13 +1,13 @@
/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2022 NXP
* Copyright 2016-2023 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __FSL_FLEXSPI_H_
#define __FSL_FLEXSPI_H_
#ifndef FSL_FLEXSPI_H_
#define FSL_FLEXSPI_H_
#include <stddef.h>
#include "fsl_device_registers.h"
@@ -23,10 +23,10 @@
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @{ */
/*! @brief FLEXSPI driver version. */
#define FSL_FLEXSPI_DRIVER_VERSION (MAKE_VERSION(2, 5, 0))
/*@}*/
#define FSL_FLEXSPI_DRIVER_VERSION (MAKE_VERSION(2, 6, 0))
/*! @} */
#define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(0)
@@ -242,8 +242,10 @@ typedef struct _flexspi_config
#if defined(FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF) && FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF
bool rxSampleClockDiff; /*!< Sample Clock source or source_b selection for Flash Reading. */
#endif
bool enableSckBDiffOpt; /*!< Enable/disable SCKB pad use as SCKA differential clock
output, when enable, Port B flash access is not available. */
#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT)
bool enableSckBDiffOpt; /*!< Enable/disable SCKB pad use as SCKA differential clock
output, when enable, Port B flash access is not available. */
#endif
bool enableSameConfigForAll; /*!< Enable/disable same configuration for all connected devices
when enabled, same configuration in FLASHA1CRx is applied to all. */
uint16_t seqTimeoutCycle; /*!< Timeout wait cycle for command sequence execution,
@@ -452,7 +454,7 @@ static inline void FLEXSPI_Enable(FLEXSPI_Type *base, bool enable)
}
}
/* @} */
/*! @} */
/*!
* @name Interrupts
@@ -480,10 +482,10 @@ static inline void FLEXSPI_DisableInterrupts(FLEXSPI_Type *base, uint32_t mask)
base->INTEN &= ~mask;
}
/* @} */
/*! @} */
/*! @name DMA control */
/*@{*/
/*! @{ */
/*!
* @brief Enables or disables FLEXSPI IP Tx FIFO DMA requests.
@@ -543,10 +545,10 @@ static inline uint32_t FLEXSPI_GetRxFifoAddress(FLEXSPI_Type *base)
return (uint32_t)&base->RFDR[0];
}
/*@}*/
/*! @} */
/*! @name FIFO control */
/*@{*/
/*! @{ */
/*! @brief Clears the FLEXSPI IP FIFO logic.
*
@@ -587,7 +589,7 @@ static inline void FLEXSPI_GetFifoCounts(FLEXSPI_Type *base, size_t *txCount, si
}
}
/*@}*/
/*! @} */
/*!
* @name Status
@@ -612,7 +614,7 @@ static inline uint32_t FLEXSPI_GetInterruptStatusFlags(FLEXSPI_Type *base)
*/
static inline void FLEXSPI_ClearInterruptStatusFlags(FLEXSPI_Type *base, uint32_t mask)
{
base->INTR |= mask;
base->INTR = mask;
}
#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN)) && (FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN))
@@ -685,7 +687,7 @@ static inline bool FLEXSPI_GetBusIdleStatus(FLEXSPI_Type *base)
{
return (0U != (base->STS0 & FLEXSPI_STS0_ARBIDLE_MASK)) && (0U != (base->STS0 & FLEXSPI_STS0_SEQIDLE_MASK));
}
/*@}*/
/*! @} */
/*!
* @name Bus Operations
@@ -737,6 +739,22 @@ static inline void FLEXSPI_EnableAHBParallelMode(FLEXSPI_Type *base, bool enable
}
#endif
#if (defined(FSL_FEATURE_FLEXSPI_HAS_AHBCR_AFLASHBASE_BIT) && FSL_FEATURE_FLEXSPI_HAS_AHBCR_AFLASHBASE_BIT)
/*!
* @brief Set AHB Memory-Mapped Flash base address.
*
* @note The length of base address may be different for differnt instance, please refer to the reference manual.
* @note This function should be called when FLEXSPI is in stop mode.
*
* @param base FLEXSPI peripheral base address.
* @param address AHB Memory-Mapped Flash base address.
*/
static inline void FLEXSPI_SetAHBFlashBaseAddress(FLEXSPI_Type *base, uint8_t address)
{
base->AHBCR = (base->AHBCR & (~FLEXSPI_AHBCR_AFLASHBASE_MASK)) | FLEXSPI_AHBCR_AFLASHBASE(address);
}
#endif /* (defined(FSL_FEATURE_FLEXSPI_HAS_AHBCR_AFLASHBASE_BIT) && FSL_FEATURE_FLEXSPI_HAS_AHBCR_AFLASHBASE_BIT) */
/*! @brief Updates the LUT table.
*
* @param base FLEXSPI peripheral base address.
@@ -879,6 +897,6 @@ void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle);
#if defined(__cplusplus)
}
#endif /*_cplusplus. */
/*@}*/
/*! @} */
#endif /* __FSL_FLEXSPI_H_ */
#endif /* FSL_FLEXSPI_H_ */
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexspi_edma.c
+2 -2
View File
@@ -1,5 +1,5 @@
/*
* Copyright 2021-2022 NXP
* Copyright 2021-2023 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -288,7 +288,7 @@ status_t FLEXSPI_TransferEDMA(FLEXSPI_Type *base, flexspi_edma_handle_t *handle,
/* Submit transfer. */
(void)EDMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig);
EDMA_SetModulo(handle->txDmaHandle->base, handle->txDmaHandle->channel, (edma_modulo_t)power,
EDMA_SetModulo(handle->rxDmaHandle->base, handle->rxDmaHandle->channel, (edma_modulo_t)power,
kEDMA_ModuloDisable);
EDMA_SetCallback(handle->rxDmaHandle, FLEXSPI_TransferEDMACallback, &s_edmaPrivateHandle[instance]);
EDMA_StartTransfer(handle->rxDmaHandle);
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexspi_edma.h
+9 -9
View File
@@ -1,12 +1,12 @@
/*
* Copyright 2021-2022 NXP
* Copyright 2021-2023 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_FLEXSPI_EDMA_H_
#define _FSL_FLEXSPI_EDMA_H_
#ifndef FSL_FLEXSPI_EDMA_H_
#define FSL_FLEXSPI_EDMA_H_
#include "fsl_flexspi.h"
#include "fsl_edma.h"
@@ -21,10 +21,10 @@
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @{ */
/*! @brief FLEXSPI EDMA driver. */
#define FSL_FLEXSPI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
/*@}*/
#define FSL_FLEXSPI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
/*! @} */
typedef struct _flexspi_edma_handle flexspi_edma_handle_t;
@@ -135,12 +135,12 @@ void FLEXSPI_TransferAbortEDMA(FLEXSPI_Type *base, flexspi_edma_handle_t *handle
*/
status_t FLEXSPI_TransferGetTransferCountEDMA(FLEXSPI_Type *base, flexspi_edma_handle_t *handle, size_t *count);
/* @} */
/*! @} */
#if defined(__cplusplus)
}
#endif
/* @} */
/*! @} */
#endif /* _FSL_FLEXSPI_EDMA_H_ */
#endif /* FSL_FLEXSPI_EDMA_H_ */
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_freqme.c
+14 -2
View File
@@ -15,6 +15,10 @@
#define FSL_COMPONENT_ID "platform.drivers.lpc_freqme"
#endif
#if defined(FREQME_RSTS_N)
#define FREQME_RESETS_ARRAY FREQME_RSTS_N
#endif
/*******************************************************************************
* Prototypes
******************************************************************************/
@@ -31,6 +35,10 @@ static FREQME_Type *const s_freqmeBases[] = FREQME_BASE_PTRS;
static const clock_ip_name_t s_freqmeClocks[] = FREQME_CLOCKS;
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
#if defined(FREQME_RESETS_ARRAY)
/* Reset array */
static const reset_ip_name_t s_freqmeResets[] = FREQME_RESETS_ARRAY;
#endif
/*******************************************************************************
* Code
******************************************************************************/
@@ -69,12 +77,16 @@ void FREQME_Init(FREQME_Type *base, const freq_measure_config_t *config)
CLOCK_EnableClock(s_freqmeClocks[FREQME_GetInstance(base)]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
#if defined(FREQME_RESETS_ARRAY)
RESET_ReleasePeripheralReset(s_freqmeResets[FREQME_GetInstance(base)]);
#endif
if (config->startMeasurement)
{
tmp32 |= FREQME_CTRL_W_MEASURE_IN_PROGRESS_MASK;
}
tmp32 |=
FREQME_CTRL_W_CONTINUOUS_MODE_EN(config->enableContinuousMode) | FREQME_CTRL_W_PULSE_MODE(config->operateMode);
tmp32 |= FREQME_CTRL_W_CONTINUOUS_MODE_EN(config->enableContinuousMode) |
FREQME_CTRL_W_PULSE_MODE(config->operateMode);
if (config->operateMode == kFREQME_FreqMeasurementMode)
{
tmp32 |= FREQME_CTRL_W_REF_SCALE(config->operateModeAttribute.refClkScaleFactor);
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_freqme.h
+17 -16
View File
@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_FREQME_
#define _FSL_FREQME_
#ifndef FSL_FREQME_H_
#define FSL_FREQME_H_
#include "fsl_common.h"
@@ -19,10 +19,10 @@
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief FREQME driver version 2.0.0. */
#define FSL_FREQME_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
/*@}*/
/*! @{ */
/*! @brief FREQME driver version 2.1.2. */
#define FSL_FREQME_DRIVER_VERSION (MAKE_VERSION(2, 1, 2))
/*! @} */
/*!
* @brief The enumeration of interrupt status flags.
@@ -51,10 +51,10 @@ enum _freqme_interrupt_status_flags
*/
enum _freqme_interrupt_enable
{
kFREQME_UnderflowInterruptEnable = FREQME_CTRL_W_LT_MIN_INT_EN_MASK, /*!< Enable interrupt when the result is
less than minimum value. */
kFREQME_OverflowInterruptEnable = FREQME_CTRL_W_GT_MAX_INT_EN_MASK, /*!< Enable interrupt when the result is
greater than maximum value. */
kFREQME_UnderflowInterruptEnable = FREQME_CTRL_W_LT_MIN_INT_EN_MASK, /*!< Enable interrupt when the result is
less than minimum value. */
kFREQME_OverflowInterruptEnable = FREQME_CTRL_W_GT_MAX_INT_EN_MASK, /*!< Enable interrupt when the result is
greater than maximum value. */
kFREQME_ReadyInterruptEnable = FREQME_CTRL_W_RESULT_READY_INT_EN_MASK, /*!< Enable interrupt when a
measurement completes and the result
is ready. */
@@ -223,8 +223,8 @@ static inline void FREQME_SetOperateMode(FREQME_Type *base, freqme_operate_mode_
uint32_t tmp32;
tmp32 = base->CTRLSTAT;
tmp32 &= ~(FREQME_CTRLSTAT_LT_MIN_STAT_MASK | FREQME_CTRLSTAT_PULSE_MODE_MASK | FREQME_CTRLSTAT_GT_MAX_STAT_MASK |
FREQME_CTRLSTAT_RESULT_READY_STAT_MASK);
tmp32 &= ~(FREQME_CTRLSTAT_LT_MIN_STAT_MASK | FREQME_CTRLSTAT_PULSE_MODE_MASK |
FREQME_CTRLSTAT_GT_MAX_STAT_MASK | FREQME_CTRLSTAT_RESULT_READY_STAT_MASK);
if (operateMode == kFREOME_PulseWidthMeasurementMode)
{
tmp32 |= FREQME_CTRL_W_PULSE_MODE_MASK;
@@ -243,6 +243,7 @@ static inline void FREQME_SetOperateMode(FREQME_Type *base, freqme_operate_mode_
static inline bool FREQME_CheckOperateMode(FREQME_Type *base)
{
return (bool)((base->CTRLSTAT & FREQME_CTRLSTAT_PULSE_MODE_MASK) != 0UL);
}
/*!
@@ -275,7 +276,7 @@ static inline void FREQME_SetMaxExpectedValue(FREQME_Type *base, uint32_t maxVal
*/
/*!
* @brief Calculate the frequency of selected target clock。
* @brief Calculate the frequency of selected target clock。
*
* @note The formula: Ftarget = (RESULT - 2) * Freference / 2 ^ REF_SCALE.
*
@@ -317,8 +318,8 @@ static inline void FREQME_SetPulsePolarity(FREQME_Type *base, freqme_pulse_polar
uint32_t tmp32;
tmp32 = base->CTRLSTAT;
tmp32 &= ~(FREQME_CTRLSTAT_LT_MIN_STAT_MASK | FREQME_CTRLSTAT_PULSE_POL_MASK | FREQME_CTRLSTAT_GT_MAX_STAT_MASK |
FREQME_CTRLSTAT_RESULT_READY_STAT_MASK);
tmp32 &= ~(FREQME_CTRLSTAT_LT_MIN_STAT_MASK | FREQME_CTRLSTAT_PULSE_POL_MASK |
FREQME_CTRLSTAT_GT_MAX_STAT_MASK | FREQME_CTRLSTAT_RESULT_READY_STAT_MASK);
if (pulsePolarity != kFREQME_PulseHighPeriod)
{
@@ -437,4 +438,4 @@ static inline void FREQME_DisableInterrupts(FREQME_Type *base, uint32_t masks)
/*!
* @}
*/
#endif /* __FSL_FREQME_H__ */
#endif /* FSL_FREQME_H_ */
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_gdet.c
+1 -1
View File
@@ -141,7 +141,7 @@ status_t GDET_ReconfigureVoltageMode(GDET_Type *base, gdet_core_voltage_t voltag
uint32_t tmp0 = 0;
status_t status = kStatus_Fail;
if (voltage != (kGDET_MidVoltage || kGDET_NormalVoltage || kGDET_OverDriveVoltage))
if ((voltage != kGDET_MidVoltage) && (voltage != kGDET_NormalVoltage) && (voltage != kGDET_OverDriveVoltage))
{
return kStatus_InvalidArgument;
}
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_gdet.h
+12 -12
View File
@@ -4,8 +4,8 @@
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_GDET_H_
#define _FSL_GDET_H_
#ifndef FSL_GDET_H_
#define FSL_GDET_H_
#include "fsl_common.h"
@@ -21,7 +21,7 @@
*******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @{ */
/*! @brief Defines GDET driver version 2.0.0.
*
* Change log:
@@ -29,7 +29,7 @@
* - initial version
*/
#define FSL_GDET_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
/*@}*/
/*! @} */
/*!
* @brief GDET Core Voltage.
@@ -37,12 +37,12 @@
* These constants are used to define core voltage argument to be used with
* GDET_ReconfigureVoltageMode().
*/
typedef enum _gdet_core_voltage
{
kGDET_MidVoltage = 0U, /*!< Mid Voltage (1.0V) */
kGDET_NormalVoltage = 1U, /*!< Normal Voltage (1.1V) */
kGDET_OverDriveVoltage = 2U, /*!< Over Drive Voltage (1.2V) */
} gdet_core_voltage_t;
typedef uint32_t gdet_core_voltage_t;
#define kGDET_MidVoltage ((gdet_core_voltage_t)0x0u) /*!< Mid Voltage (1.0V) */
#define kGDET_NormalVoltage ((gdet_core_voltage_t)0x1u) /*!< Normal Voltage (1.1V) */
#define kGDET_OverDriveVoltage ((gdet_core_voltage_t)0x2u) /*!< Over Drive Voltage (1.2V) */
/*******************************************************************************
* API
*******************************************************************************/
@@ -109,8 +109,8 @@ status_t GDET_ReconfigureVoltageMode(GDET_Type *base, gdet_core_voltage_t voltag
#if defined(__cplusplus)
}
#endif /* __cplusplus */
#endif /* __cplusplus */
/*! @}*/ /* end of group gdet */
#endif /* _FSL_GDET_H_ */
#endif /* FSL_GDET_H_ */
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_gpio.c
+39 -10
View File
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2019 NXP
* Copyright 2016-2019, 2023 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -8,18 +8,30 @@
#include "fsl_gpio.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.gpio"
#endif
#if defined(GPIO_RSTS)
#define GPIO_RESETS_ARRAY GPIO_RSTS
#endif
/*******************************************************************************
* Variables
******************************************************************************/
#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
defined(FSL_FEATURE_SOC_PORT_COUNT)
static PORT_Type *const s_portBases[] = PORT_BASE_PTRS;
static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS;
#else
#if defined(GPIO_RESETS_ARRAY)
static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS;
#endif
#endif
#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT
@@ -35,10 +47,16 @@ static const clock_ip_name_t s_fgpioClockName[] = FGPIO_CLOCKS;
#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */
#if defined(GPIO_RESETS_ARRAY)
/* Reset array */
static const reset_ip_name_t s_gpioResets[] = GPIO_RESETS_ARRAY;
#endif
/*******************************************************************************
* Prototypes
******************************************************************************/
#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
defined(FSL_FEATURE_SOC_PORT_COUNT)
/*!
* @brief Gets the GPIO instance according to the GPIO base
*
@@ -50,7 +68,8 @@ static uint32_t GPIO_GetInstance(GPIO_Type *base);
/*******************************************************************************
* Code
******************************************************************************/
#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
defined(FSL_FEATURE_SOC_PORT_COUNT) || defined(GPIO_RESETS_ARRAY)
static uint32_t GPIO_GetInstance(GPIO_Type *base)
{
uint32_t instance;
@@ -99,6 +118,10 @@ void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config
{
assert(NULL != config);
#if defined(GPIO_RESETS_ARRAY)
RESET_ReleasePeripheralReset(s_gpioResets[GPIO_GetInstance(base)]);
#endif
if (config->pinDirection == kGPIO_DigitalInput)
{
base->PDDR &= GPIO_FIT_REG(~(1UL << pin));
@@ -119,7 +142,8 @@ void GPIO_GetVersionInfo(GPIO_Type *base, gpio_version_info_t *info)
}
#endif /* FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER */
#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
defined(FSL_FEATURE_SOC_PORT_COUNT)
/*!
* brief Reads the GPIO port interrupt status flag.
*
@@ -183,7 +207,8 @@ uint8_t GPIO_PinGetInterruptFlag(GPIO_Type *base, uint32_t pin)
}
#endif /* FSL_FEATURE_PORT_HAS_NO_INTERRUPT */
#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
defined(FSL_FEATURE_SOC_PORT_COUNT)
/*!
* brief Clears multiple GPIO pin interrupt status flags.
*
@@ -262,13 +287,15 @@ void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribut
/*******************************************************************************
* Variables
******************************************************************************/
#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
defined(FSL_FEATURE_SOC_PORT_COUNT)
static FGPIO_Type *const s_fgpioBases[] = FGPIO_BASE_PTRS;
#endif
/*******************************************************************************
* Prototypes
******************************************************************************/
#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
defined(FSL_FEATURE_SOC_PORT_COUNT)
/*!
* @brief Gets the FGPIO instance according to the GPIO base
*
@@ -280,7 +307,8 @@ static uint32_t FGPIO_GetInstance(FGPIO_Type *base);
/*******************************************************************************
* Code
******************************************************************************/
#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
defined(FSL_FEATURE_SOC_PORT_COUNT)
static uint32_t FGPIO_GetInstance(FGPIO_Type *base)
{
uint32_t instance;
@@ -356,7 +384,8 @@ void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *conf
base->PDDR |= (1UL << pin);
}
}
#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
defined(FSL_FEATURE_SOC_PORT_COUNT)
/*!
* brief Reads the FGPIO port interrupt status flag.
*
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_gpio.h
+31 -28
View File
@@ -1,13 +1,13 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2021 NXP
* Copyright 2016-2023 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_GPIO_H_
#define _FSL_GPIO_H_
#ifndef FSL_GPIO_H_
#define FSL_GPIO_H_
#include "fsl_common.h"
@@ -21,10 +21,10 @@
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @{ */
/*! @brief GPIO driver version. */
#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 7, 1))
/*@}*/
#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 7, 3))
/*! @} */
#if defined(FSL_FEATURE_GPIO_REGISTERS_WIDTH) && (FSL_FEATURE_GPIO_REGISTERS_WIDTH == 8U)
#define GPIO_FIT_REG(value) \
@@ -79,7 +79,8 @@ typedef struct _gpio_pin_config
uint8_t outputLogic; /*!< Set a default output logic, which has no use in input */
} gpio_pin_config_t;
#if (defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
#if (defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) || \
!(defined(FSL_FEATURE_SOC_PORT_COUNT))
/*! @brief Configures the interrupt generation condition. */
typedef enum _gpio_interrupt_config
{
@@ -104,8 +105,8 @@ typedef enum _gpio_interrupt_config
/*! @brief Configures the selection of interrupt/DMA request/trigger output. */
typedef enum _gpio_interrupt_selection
{
kGPIO_InterruptOutput0 = 0x0U, /*!< Interrupt/DMA request/trigger output 0. */
kGPIO_InterruptOutput1 = 0x1U, /*!< Interrupt/DMA request/trigger output 1. */
kGPIO_InterruptOutput0 = 0x0U, /*!< Interrupt/DMA request/trigger output 0. */
kGPIO_InterruptOutput1 = 0x1U, /*!< Interrupt/DMA request/trigger output 1. */
} gpio_interrupt_selection_t;
#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT */
@@ -146,7 +147,7 @@ extern "C" {
*/
/*! @name GPIO Configuration */
/*@{*/
/*! @{ */
/*!
* @brief Initializes a GPIO pin used by the board.
@@ -311,10 +312,10 @@ static inline void GPIO_PortInputDisable(GPIO_Type *base, uint32_t mask)
}
#endif /* FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL */
/*@}*/
/*! @} */
/*! @name GPIO Output Operations */
/*@{*/
/*! @{ */
/*!
* @brief Sets the output level of the multiple GPIO pins to the logic 1 or 0.
@@ -393,10 +394,10 @@ static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t mask)
#endif
}
/*@}*/
/*! @} */
/*! @name GPIO Input Operations */
/*@{*/
/*! @{ */
/*!
* @brief Reads the current input value of the GPIO port.
@@ -412,11 +413,12 @@ static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t pin)
return (((uint32_t)(base->PDIR) >> pin) & 0x01UL);
}
/*@}*/
/*! @} */
/*! @name GPIO Interrupt */
/*@{*/
#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
/*! @{ */
#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
defined(FSL_FEATURE_SOC_PORT_COUNT)
/*!
* @brief Reads the GPIO port interrupt status flag.
*
@@ -602,7 +604,7 @@ static inline void GPIO_SetMultipleInterruptPinsConfig(GPIO_Type *base, uint32_t
void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribute);
#endif
/*@}*/
/*! @} */
/*! @} */
/*!
@@ -621,7 +623,7 @@ void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribut
#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT
/*! @name FGPIO Configuration */
/*@{*/
/*! @{ */
#if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL
/*!
@@ -662,10 +664,10 @@ void FGPIO_PortInit(FGPIO_Type *base);
*/
void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config);
/*@}*/
/*! @} */
/*! @name FGPIO Output Operations */
/*@{*/
/*! @{ */
/*!
* @brief Sets the output level of the multiple FGPIO pins to the logic 1 or 0.
@@ -720,10 +722,10 @@ static inline void FGPIO_PortToggle(FGPIO_Type *base, uint32_t mask)
{
base->PTOR = mask;
}
/*@}*/
/*! @} */
/*! @name FGPIO Input Operations */
/*@{*/
/*! @{ */
/*!
* @brief Reads the current input value of the FGPIO port.
@@ -738,11 +740,12 @@ static inline uint32_t FGPIO_PinRead(FGPIO_Type *base, uint32_t pin)
{
return (((base->PDIR) >> pin) & 0x01U);
}
/*@}*/
/*! @} */
/*! @name FGPIO Interrupt */
/*@{*/
#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
/*! @{ */
#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
defined(FSL_FEATURE_SOC_PORT_COUNT)
/*!
* @brief Reads the FGPIO port interrupt status flag.
@@ -781,7 +784,7 @@ void FGPIO_PortClearInterruptFlags(FGPIO_Type *base, uint32_t mask);
void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attribute);
#endif /* FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER */
/*@}*/
/*! @} */
#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */
@@ -793,4 +796,4 @@ void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attrib
* @}
*/
#endif /* _FSL_GPIO_H_*/
#endif /* FSL_GPIO_H_*/
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_i3c.c
+418 -139
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bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_i3c.h
+135 -66
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bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_i3c_edma.c
+1057
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bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_i3c_edma.h
+279
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bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_inputmux.c
+61 -6
View File
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2021 NXP
* Copyright 2016-2021, 2023 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -17,12 +17,57 @@
#define FSL_COMPONENT_ID "platform.drivers.inputmux"
#endif
#if defined(INPUTMUX_RSTS)
#define INPUTMUX_RESETS_ARRAY INPUTMUX_RSTS
#endif
/*******************************************************************************
* Prototypes
******************************************************************************/
#if defined(INPUTMUX_RESETS_ARRAY)
/*!
* @brief Get instance number for INPUTMUX module.
*
* @param base INPUTMUX peripheral base address
*/
static uint32_t INPUTMUX_GetInstance(INPUTMUX_Type *base);
#endif
/*******************************************************************************
* Variables
******************************************************************************/
#if defined(INPUTMUX_RESETS_ARRAY)
/*! @brief Pointers to INPUTMUX bases for each instance. */
static INPUTMUX_Type *const s_inputmuxBases[] = INPUTMUX_BASE_PTRS;
/* Reset array */
static const reset_ip_name_t s_inputmuxResets[] = INPUTMUX_RESETS_ARRAY;
#endif
/*******************************************************************************
* Code
******************************************************************************/
#if defined(INPUTMUX_RESETS_ARRAY)
static uint32_t INPUTMUX_GetInstance(INPUTMUX_Type *base)
{
uint32_t instance;
/* Find the instance index from base address mappings. */
for (instance = 0; instance < ARRAY_SIZE(s_inputmuxBases); instance++)
{
if (s_inputmuxBases[instance] == base)
{
break;
}
}
assert(instance < ARRAY_SIZE(s_inputmuxBases));
return instance;
}
#endif
/*!
* brief Initialize INPUTMUX peripheral.
* brief Initialize INPUTMUX peripheral.
* This function enables the INPUTMUX clock.
*
@@ -42,16 +87,26 @@ void INPUTMUX_Init(INPUTMUX_Type *base)
CLOCK_EnableClock(kCLOCK_InputMux);
#endif /* FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE */
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
#if defined(INPUTMUX_RESETS_ARRAY)
RESET_ReleasePeripheralReset(s_inputmuxResets[INPUTMUX_GetInstance(base)]);
#endif
}
/*!
* brief Attaches a signal
*
* This function gates the INPUTPMUX clock.
* This function attaches multiplexed signals from INPUTMUX to target signals.
* For example, to attach GPIO PORT0 Pin 5 to PINT peripheral, do the following:
* code
* INPUTMUX_AttachSignal(INPUTMUX, 2, kINPUTMUX_GpioPort0Pin5ToPintsel);
* endcode
* In this example, INTMUX has 8 registers for PINT, PINT_SEL0~PINT_SEL7.
* With parameter p index specified as 2, this function configures register PINT_SEL2.
*
* param base Base address of the INPUTMUX peripheral.
* param index Destination peripheral to attach the signal to.
* param connection Selects connection.
* param index The serial number of destination register in the group of INPUTMUX registers with same name.
* param connection Applies signal from source signals collection to target signal.
*
* retval None.
*/
@@ -116,7 +171,7 @@ void INPUTMUX_EnableSignal(INPUTMUX_Type *base, inputmux_signal_t signal, bool e
#endif
/*!
* brief Deinitialize INPUTMUX peripheral.
* brief Deinitialize INPUTMUX peripheral.
* This function disables the INPUTMUX clock.
*
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_inputmux.h
+19 -13
View File
@@ -1,13 +1,13 @@
/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2021 NXP
* Copyright 2016-2021, 2023 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_INPUTMUX_H_
#define _FSL_INPUTMUX_H_
#ifndef FSL_INPUTMUX_H_
#define FSL_INPUTMUX_H_
#include "fsl_inputmux_connections.h"
#include "fsl_common.h"
@@ -25,10 +25,10 @@
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @{ */
/*! @brief Group interrupt driver version for SDK */
#define FSL_INPUTMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 5))
/*@}*/
#define FSL_INPUTMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 7))
/*! @} */
/*******************************************************************************
* API
@@ -39,7 +39,7 @@ extern "C" {
#endif
/*!
* @brief Initialize INPUTMUX peripheral.
* @brief Initialize INPUTMUX peripheral.
* This function enables the INPUTMUX clock.
*
@@ -52,11 +52,17 @@ void INPUTMUX_Init(INPUTMUX_Type *base);
/*!
* @brief Attaches a signal
*
* This function gates the INPUTPMUX clock.
* This function attaches multiplexed signals from INPUTMUX to target signals.
* For example, to attach GPIO PORT0 Pin 5 to PINT peripheral, do the following:
* @code
* INPUTMUX_AttachSignal(INPUTMUX, 2, kINPUTMUX_GpioPort0Pin5ToPintsel);
* @endcode
* In this example, INTMUX has 8 registers for PINT, PINT_SEL0~PINT_SEL7.
* With parameter @p index specified as 2, this function configures register PINT_SEL2.
*
* @param base Base address of the INPUTMUX peripheral.
* @param index Destination peripheral to attach the signal to.
* @param connection Selects connection.
* @param index The serial number of destination register in the group of INPUTMUX registers with same name.
* @param connection Applies signal from source signals collection to target signal.
*
* @retval None.
*/
@@ -78,7 +84,7 @@ void INPUTMUX_EnableSignal(INPUTMUX_Type *base, inputmux_signal_t signal, bool e
#endif
/*!
* @brief Deinitialize INPUTMUX peripheral.
* @brief Deinitialize INPUTMUX peripheral.
* This function disables the INPUTMUX clock.
*
@@ -92,6 +98,6 @@ void INPUTMUX_Deinit(INPUTMUX_Type *base);
}
#endif
/*@}*/
/*! @} */
#endif /* _FSL_INPUTMUX_H_ */
#endif /* FSL_INPUTMUX_H_ */
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_inputmux_connections.h
+751 -745
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bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_intm.h
+5 -5
View File
@@ -5,8 +5,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_INTM_H_
#define _FSL_INTM_H_
#ifndef FSL_INTM_H_
#define FSL_INTM_H_
#include "fsl_common.h"
@@ -20,10 +20,10 @@
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @{ */
/*! @brief INTM driver version. */
#define FSL_INTM_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
/*@}*/
/*! @} */
/*! @brief Interrupt monitors. */
typedef enum _intm_monitor
@@ -204,4 +204,4 @@ static inline bool INTM_GetStatusFlags(INTM_Type *base, intm_monitor_t intms)
}
/*! @} */
#endif /* _FSL_INTM_H_*/
#endif /* FSL_INTM_H_*/
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_irtc.c
+94 -5
View File
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2019 NXP
* Copyright 2016-2019, 2023 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -21,6 +21,22 @@
#define YEAR_RANGE_START (1984U) /* Valid values for year range from -128 to 127; 2112 - 128 */
#define YEAR_RANGE_END (2239U) /* Valid values for year range from -128 to 127; 2112 + 127 */
#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) || \
(defined(FSL_FEATURE_RTC_HAS_RESET) && FSL_FEATURE_RTC_HAS_RESET)
/*! @brief Array to map IRTC instance number to base pointer. */
static RTC_Type *const kIrtcBases[] = RTC_BASE_PTRS;
#endif
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/*! @brief Array to map IRTC instance number to clock gate enum. */
static clock_ip_name_t const kIrtcClocks[] = RTC_CLOCKS;
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
#if defined(FSL_FEATURE_RTC_HAS_RESET) && FSL_FEATURE_RTC_HAS_RESET
/*! @brief Pointers to IRTC resets for each instance. */
static const reset_ip_name_t kIrtcResets[] = RTC_RSTS;
#endif
/*******************************************************************************
* Prototypes
******************************************************************************/
@@ -33,6 +49,18 @@
*/
static bool IRTC_CheckDatetimeFormat(const irtc_datetime_t *datetime);
#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) || \
(defined(FSL_FEATURE_RTC_HAS_RESET) && FSL_FEATURE_RTC_HAS_RESET)
/*!
* @brief Returns an instance number given a base address.
*
* @param base The IRTC peripheral base address.
* @return IRTC instance number starting from 0. If cannot the base address is
* not a valid address, this function returns -1.
*/
static int32_t IRTC_GetInstance(RTC_Type *base);
#endif
/*******************************************************************************
* Code
******************************************************************************/
@@ -70,6 +98,29 @@ static bool IRTC_CheckDatetimeFormat(const irtc_datetime_t *datetime)
return fgRet;
}
#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) || \
(defined(FSL_FEATURE_RTC_HAS_RESET) && FSL_FEATURE_RTC_HAS_RESET)
static int32_t IRTC_GetInstance(RTC_Type *base)
{
int32_t instance;
for (instance = 0; instance < (int32_t)ARRAY_SIZE(kIrtcBases); ++instance)
{
if (kIrtcBases[instance] == base)
{
break;
}
}
if (instance >= (int32_t)ARRAY_SIZE(kIrtcBases))
{
instance = -1;
}
return instance;
}
#endif
/*!
* brief Ungates the IRTC clock and configures the peripheral for basic operation.
*
@@ -90,12 +141,21 @@ status_t IRTC_Init(RTC_Type *base, const irtc_config_t *config)
uint16_t reg;
status_t status = kStatus_Success;
#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) || \
(defined(FSL_FEATURE_RTC_HAS_RESET) && FSL_FEATURE_RTC_HAS_RESET)
int32_t instance = IRTC_GetInstance(base);
if (instance < 0)
{
return kStatus_InvalidArgument;
}
#endif
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
CLOCK_EnableClock(kCLOCK_Rtc0);
CLOCK_EnableClock(kIrtcClocks[instance]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
#if defined(FSL_FEATURE_RTC_HAS_RESET) && FSL_FEATURE_RTC_HAS_RESET
RESET_PeripheralReset(kRTC_RST_SHIFT_RSTn);
RESET_ReleasePeripheralReset(kIrtcResets[instance]);
#endif
/* Unlock to allow register write operation */
@@ -123,7 +183,7 @@ status_t IRTC_Init(RTC_Type *base, const irtc_config_t *config)
#endif
#if defined(FSL_FEATURE_RTC_HAS_CLOCK_SELECT) && FSL_FEATURE_RTC_HAS_CLOCK_SELECT
(uint16_t)RTC_CTRL_CLK_SEL_MASK |
#endif
#endif
#if defined(FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT_DISABLE) && FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT_DISABLE
(uint16_t)RTC_CTRL_CLKO_DIS_MASK |
#endif
@@ -149,6 +209,26 @@ status_t IRTC_Init(RTC_Type *base, const irtc_config_t *config)
return status;
}
/*
* brief Gate the IRTC clock
*
* param base IRTC peripheral base address
*/
status_t IRTC_Deinit(RTC_Type *base)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
int32_t instance = IRTC_GetInstance(base);
if (instance < 0)
{
return kStatus_InvalidArgument;
}
CLOCK_DisableClock(kIrtcClocks[instance]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
return kStatus_Success;
}
/*!
* brief Fill in the IRTC config struct with the default settings
*
@@ -172,7 +252,7 @@ void IRTC_GetDefaultConfig(irtc_config_t *config)
config->wakeupSelect = true;
#endif
#if !defined(FSL_FEATURE_RTC_HAS_NO_SAMPLING_CLOCKS) || (!FSL_FEATURE_RTC_HAS_NO_SAMPLING_CLOCKS)
#if !defined(FSL_FEATURE_RTC_HAS_NO_TIMER_STB_MASK) || (!FSL_FEATURE_RTC_HAS_NO_TIMER_STB_MASK)
/* Sampling clock are not gated when in standby mode */
config->timerStdMask = false;
#endif
@@ -191,6 +271,7 @@ void IRTC_GetDefaultConfig(irtc_config_t *config)
#endif
}
#if !(defined(FSL_FEATURE_RTC_IS_SLAVE) && (FSL_FEATURE_RTC_IS_SLAVE != 0U))
/*!
* brief Sets the IRTC date and time according to the given time structure.
*
@@ -239,6 +320,7 @@ status_t IRTC_SetDatetime(RTC_Type *base, const irtc_datetime_t *datetime)
return status;
}
#endif /* FSL_FEATURE_RTC_IS_SLAVE */
/*!
* brief Gets the IRTC time and stores it in the given time structure.
@@ -395,6 +477,7 @@ status_t IRTC_SetWriteProtection(RTC_Type *base, bool lock)
return status;
}
#if !(defined(FSL_FEATURE_RTC_IS_SLAVE) && (FSL_FEATURE_RTC_IS_SLAVE != 0U))
/*!
* brief Sets the IRTC daylight savings start and stop date and time.
*
@@ -423,6 +506,7 @@ void IRTC_SetDaylightTime(RTC_Type *base, const irtc_daylight_time_t *datetime)
/* Enable daylight saving time */
base->CTRL |= RTC_CTRL_DST_EN_MASK;
}
#endif /* FSL_FEATURE_RTC_IS_SLAVE */
/*!
* brief Gets the IRTC daylight savings time and stores it in the given time structure.
@@ -452,6 +536,7 @@ void IRTC_GetDaylightTime(RTC_Type *base, irtc_daylight_time_t *datetime)
datetime->endHour = (uint8_t)((temp & RTC_DST_HOUR_DST_END_HOUR_MASK) >> RTC_DST_HOUR_DST_END_HOUR_SHIFT);
}
#if !(defined(FSL_FEATURE_RTC_IS_SLAVE) && (FSL_FEATURE_RTC_IS_SLAVE != 0U))
/*!
* brief Enables the coarse compensation and sets the value in the IRTC compensation register.
*
@@ -497,6 +582,7 @@ void IRTC_SetFineCompensation(RTC_Type *base, uint8_t integralValue, uint8_t fra
/* Enable fine compensation */
base->CTRL |= (RTC_CTRL_COMP_EN_MASK | RTC_CTRL_FINEEN_MASK);
}
#endif /* FSL_FEATURE_RTC_IS_SLAVE */
#if !defined(FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE) || (!FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE)
@@ -676,6 +762,8 @@ void IRTC_ConfigClockOut(RTC_Type *base, irtc_clockout_sel_t clkOut)
ctrlVal &= (uint16_t)(~RTC_CTRL_CLKOUT_MASK);
ctrlVal |= RTC_CTRL_CLKOUT((uint16_t)clkOut);
#if !(defined(FSL_FEATURE_RTC_IS_SLAVE) && (FSL_FEATURE_RTC_IS_SLAVE != 0U))
if (clkOut == kIRTC_ClkoutCoarse1Hz)
{
ctrlVal |= RTC_CTRL_COMP_EN_MASK;
@@ -688,6 +776,7 @@ void IRTC_ConfigClockOut(RTC_Type *base, irtc_clockout_sel_t clkOut)
{
/* empty else */
}
#endif /* FSL_FEATURE_RTC_IS_SLAVE */
base->CTRL = ctrlVal;
}
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_irtc.h
+40 -24
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bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_itrc.h
+11 -9
View File
@@ -4,8 +4,8 @@
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_ITRC_H_
#define _FSL_ITRC_H_
#ifndef FSL_ITRC_H_
#define FSL_ITRC_H_
#include "fsl_common.h"
@@ -21,10 +21,12 @@
*******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief Defines ITRC driver version 2.2.0.
/*! @{ */
/*! @brief Defines ITRC driver version 2.3.0.
*
* Change log:
* - Version 2.3.0
* - Update names of kITRC_SwEvent1/2 to kITRC_SwEvent0/1 to align with RM
* - Version 2.2.0
* - Update driver to new version and input events
* - Version 2.1.0
@@ -32,8 +34,8 @@
* - Version 2.0.0
* - initial version
*/
#define FSL_ITRC_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
/*@}*/
#define FSL_ITRC_DRIVER_VERSION (MAKE_VERSION(2, 3, 0))
/*! @} */
typedef enum _itrc_input_signals
{
@@ -59,8 +61,8 @@ typedef enum _itrc_input_signals
#if defined(ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN13_SELn_MASK)
kITRC_Freqme = 13u,
#endif /* ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN13_SELn_MASK */
kITRC_SwEvent1 = 14u,
kITRC_SwEvent2 = 15u,
kITRC_SwEvent0 = 14u,
kITRC_SwEvent1 = 15u,
#if defined(ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN16_SELn_MASK)
kITRC_VddSysLow = 16u,
#endif /* ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN16_SELn_MASK */
@@ -317,4 +319,4 @@ void ITRC_Deinit(ITRC_Type *base);
/*! @}*/ /* end of group itrc */
#endif /* _FSL_ITRC_H_ */
#endif /* FSL_ITRC_H_ */
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpadc.c
+364 -95
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bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpadc.h
+597 -138
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bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpcmp.c
+145 -12
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bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpcmp.h
+324 -43
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bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpflexcomm.c
+26 -9
View File
@@ -32,6 +32,11 @@ typedef union pvoid_to_u32
/*! @brief check whether lpflexcomm supports peripheral type */
static bool LP_FLEXCOMM_PeripheralIsPresent(LP_FLEXCOMM_Type *base, LP_FLEXCOMM_PERIPH_T periph);
/*! @brief Changes LP_FLEXCOMM mode. */
static status_t LP_FLEXCOMM_SetPeriph(uint32_t instance, LP_FLEXCOMM_PERIPH_T periph, int lock);
/*! @brief Common LPFLEXCOMM IRQhandle. */
static void LP_FLEXCOMM_CommonIRQHandler(uint32_t instance);
/*******************************************************************************
* Variables
******************************************************************************/
@@ -39,6 +44,9 @@ static bool LP_FLEXCOMM_PeripheralIsPresent(LP_FLEXCOMM_Type *base, LP_FLEXCOMM_
/*! @brief Array to map LP_FLEXCOMM instance number to base address. */
static const uint32_t s_lpflexcommBaseAddrs[] = LP_FLEXCOMM_BASE_ADDRS;
/*! @brief Array to map LP_FLEXCOMM instance PTRS. */
static LP_FLEXCOMM_Type *const s_lpflexcommBase[] = LP_FLEXCOMM_BASE_PTRS;
/*! @brief Pointers to real IRQ handlers installed by drivers for each instance. */
static lpflexcomm_irq_handler_t s_lpflexcommIrqHandler[LP_FLEXCOMM_PERIPH_LPI2C + 1][ARRAY_SIZE(s_lpflexcommBaseAddrs)];
@@ -57,7 +65,6 @@ static const clock_ip_name_t s_lpflexcommClocks[] = LP_FLEXCOMM_CLOCKS;
/*! @brief Pointers to LP_FLEXCOMM resets for each instance. */
static const reset_ip_name_t s_lpflexcommResets[] = LP_FLEXCOMM_RSTS;
#endif
/*******************************************************************************
* Code
******************************************************************************/
@@ -83,10 +90,20 @@ static bool LP_FLEXCOMM_PeripheralIsPresent(LP_FLEXCOMM_Type *base, LP_FLEXCOMM_
}
}
/*! @brief Returns for LP_FLEXCOMM base address. */
uint32_t LP_FLEXCOMM_GetBaseAddress(uint32_t instance)
{
if(instance < (uint32_t)ARRAY_SIZE(s_lpflexcommBaseAddrs))
{
return s_lpflexcommBaseAddrs[instance];
}
return 0U;
}
/*! brief Returns for LP_FLEXCOMM interrupt source,see #_lpflexcomm_interrupt_flag. */
uint32_t LP_FLEXCOMM_GetInterruptStatus(uint32_t instance)
{
LP_FLEXCOMM_Type *base = (LP_FLEXCOMM_Type *)s_lpflexcommBaseAddrs[instance];
LP_FLEXCOMM_Type *base = s_lpflexcommBase[instance];
return base->ISTAT;
}
@@ -114,8 +131,7 @@ uint32_t LP_FLEXCOMM_GetInstance(void *base)
static status_t LP_FLEXCOMM_SetPeriph(uint32_t instance, LP_FLEXCOMM_PERIPH_T periph, int lock)
{
assert(periph <= LP_FLEXCOMM_PERIPH_LPI2CAndLPUART);
assert(instance < (uint32_t)ARRAY_SIZE(s_lpflexcommBaseAddrs));
LP_FLEXCOMM_Type *base = (LP_FLEXCOMM_Type *)s_lpflexcommBaseAddrs[instance];
LP_FLEXCOMM_Type *base = s_lpflexcommBase[instance];
/* Check whether peripheral type is present */
if (!LP_FLEXCOMM_PeripheralIsPresent(base, periph))
@@ -146,15 +162,15 @@ static status_t LP_FLEXCOMM_SetPeriph(uint32_t instance, LP_FLEXCOMM_PERIPH_T pe
/*! brief Initializes LP_FLEXCOMM and selects peripheral mode according to the second parameter. */
status_t LP_FLEXCOMM_Init(uint32_t instance, LP_FLEXCOMM_PERIPH_T periph)
{
assert(instance < (uint32_t)ARRAY_SIZE(s_lpflexcommBaseAddrs));
assert(instance < (uint32_t)ARRAY_SIZE(s_lpflexcommBase));
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Enable the peripheral clock */
CLOCK_EnableClock(s_lpflexcommClocks[instance]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
#if !(defined(FSL_FEATURE_LP_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_LP_FLEXCOMM_HAS_NO_RESET)
/* Reset the LP_FLEXCOMM module */
RESET_PeripheralReset(s_lpflexcommResets[instance]);
/* Reset the LP_FLEXCOMM module before configuring it.*/
RESET_ClearPeripheralReset(s_lpflexcommResets[instance]);
#endif
/* Set the LP_FLEXCOMM to given peripheral */
return LP_FLEXCOMM_SetPeriph(instance, periph, 0);
@@ -163,11 +179,12 @@ status_t LP_FLEXCOMM_Init(uint32_t instance, LP_FLEXCOMM_PERIPH_T periph)
/*! brief Deinitializes LP_FLEXCOMM. */
void LP_FLEXCOMM_Deinit(uint32_t instance)
{
assert(instance < (uint32_t)ARRAY_SIZE(s_lpflexcommBaseAddrs));
assert(instance < (uint32_t)ARRAY_SIZE(s_lpflexcommBase));
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Disable the peripheral clock */
CLOCK_DisableClock(s_lpflexcommClocks[instance]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
RESET_SetPeripheralReset(s_lpflexcommResets[instance]);
}
/*! brief Sets IRQ handler for given LP_FLEXCOMM module. It is used by drivers register IRQ handler according to
@@ -177,7 +194,7 @@ void LP_FLEXCOMM_SetIRQHandler(uint32_t instance,
void *lpflexcommHandle,
LP_FLEXCOMM_PERIPH_T periph)
{
assert(instance < (uint32_t)ARRAY_SIZE(s_lpflexcommBaseAddrs));
assert(instance < (uint32_t)ARRAY_SIZE(s_lpflexcommBase));
/* Clear handler first to avoid execution of the handler with wrong handle */
s_lpflexcommIrqHandler[periph][instance] = NULL;
s_lpflexcommHandle[periph][instance] = lpflexcommHandle;
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpflexcomm.h
+10 -7
View File
@@ -4,8 +4,8 @@
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_LP_FLEXCOMM_H_
#define _FSL_LP_FLEXCOMM_H_
#ifndef FSL_LP_FLEXCOMM_H_
#define FSL_LP_FLEXCOMM_H_
#include "fsl_common.h"
@@ -15,10 +15,10 @@
*/
/*! @name Driver version */
/*@{*/
/*! @{ */
/*! @brief FlexCOMM driver version. */
#define FSL_LP_FLEXCOMM_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
/*@}*/
#define FSL_LP_FLEXCOMM_DRIVER_VERSION (MAKE_VERSION(2, 2, 1))
/*! @} */
/*! @brief LP_FLEXCOMM peripheral modes. */
typedef enum
@@ -60,6 +60,9 @@ extern "C" {
/*! @brief Returns instance number for LP_FLEXCOMM module with given base address. */
uint32_t LP_FLEXCOMM_GetInstance(void *base);
/*! @brief Returns for LP_FLEXCOMM base address. */
uint32_t LP_FLEXCOMM_GetBaseAddress(uint32_t instance);
/*! brief Returns for LP_FLEXCOMM interrupt source,see #_lpflexcomm_interrupt_flag. */
uint32_t LP_FLEXCOMM_GetInterruptStatus(uint32_t instance);
@@ -80,6 +83,6 @@ void LP_FLEXCOMM_SetIRQHandler(uint32_t instance,
}
#endif
/*@}*/
/*! @} */
#endif /* _FSL_LP_FLEXCOMM_H_*/
#endif /* FSL_LP_FLEXCOMM_H_*/
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpi2c.c
+202 -33
View File
File diff suppressed because it is too large. Load diff
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpi2c.h
+46 -38
View File
File diff suppressed because it is too large. Load diff
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpi2c_edma.c
+32 -6
View File
@@ -41,9 +41,6 @@ enum _lpi2c_transfer_states
kWaitForCompletionState,
};
/*! @brief Typedef for interrupt handler. */
typedef void (*lpi2c_isr_t)(LPI2C_Type *base, void *handle);
/*!
* @brief Used for conversion from `lpflexcomm_irq_handler_t` to `lpi2c_master_isr_t`
*/
@@ -126,7 +123,6 @@ void LPI2C_MasterCreateEDMAHandle(LPI2C_Type *base,
/* Look up instance number */
uint32_t instance = LPI2C_GetInstance(base);
lpi2c_to_lpflexcomm_edma_t handler;
/* Clear out the handle. */
(void)memset(handle, 0, sizeof(*handle));
@@ -139,9 +135,21 @@ void LPI2C_MasterCreateEDMAHandle(LPI2C_Type *base,
handle->rx = rxDmaHandle;
handle->tx = (FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base) > 0) ? txDmaHandle : rxDmaHandle;
handler.lpi2c_master_handler = LPI2C_MasterTransferEdmaHandleIRQ;
if (LP_FLEXCOMM_GetBaseAddress(instance) != 0U)
{
lpi2c_to_lpflexcomm_edma_t handler;
handler.lpi2c_master_handler = LPI2C_MasterTransferEdmaHandleIRQ;
LP_FLEXCOMM_SetIRQHandler(instance, handler.lpflexcomm_handler, handle, LP_FLEXCOMM_PERIPH_LPI2C);
LP_FLEXCOMM_SetIRQHandler(instance, handler.lpflexcomm_handler, handle, LP_FLEXCOMM_PERIPH_LPI2C);
}
else
{
/* Save the handle in global variables to support the double weak mechanism. */
s_lpi2cMasterHandle[instance] = handle;
/* Set LPI2C_MasterTransferEdmaHandleIRQ as LPI2C DMA IRQ handler */
s_lpi2cMasterIsr = LPI2C_MasterTransferEdmaHandleIRQ;
}
/* Enable interrupt in NVIC. */
(void)EnableIRQ(kLpi2cIrqs[instance]);
@@ -330,10 +338,17 @@ status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base,
if (commandCount != 0U)
{
#if defined FSL_EDMA_DRIVER_EDMA4 && FSL_EDMA_DRIVER_EDMA4
/* Create a software TCD, which will be chained after the commands. */
EDMA_TcdResetExt(handle->tx->base, tcd);
EDMA_TcdSetTransferConfigExt(handle->tx->base, tcd, &transferConfig, NULL);
EDMA_TcdEnableInterruptsExt(handle->tx->base, tcd, (uint32_t)kEDMA_MajorInterruptEnable);
#else
/* Create a software TCD, which will be chained after the commands. */
EDMA_TcdReset(tcd);
EDMA_TcdSetTransferConfig(tcd, &transferConfig, NULL);
EDMA_TcdEnableInterrupts(tcd, (uint32_t)kEDMA_MajorInterruptEnable);
#endif
linkTcd = tcd;
}
else
@@ -371,9 +386,15 @@ status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base,
enabling rx dma and disabling tx dma, which will be chained onto the commands transfer,
and create another software TCD of transfering data and chain it onto the last TCD.
Notice that in this situation assume tx/rx uses same channel */
#if defined FSL_EDMA_DRIVER_EDMA4 && FSL_EDMA_DRIVER_EDMA4
EDMA_TcdResetExt(handle->rx->base, tcd);
EDMA_TcdSetTransferConfigExt(handle->rx->base, tcd, &transferConfig, NULL);
EDMA_TcdEnableInterruptsExt(handle->rx->base, tcd, (uint32_t)kEDMA_MajorInterruptEnable);
#else
EDMA_TcdReset(tcd);
EDMA_TcdSetTransferConfig(tcd, &transferConfig, NULL);
EDMA_TcdEnableInterrupts(tcd, (uint32_t)kEDMA_MajorInterruptEnable);
#endif
transferConfig.srcAddr = (uint32_t)&lpi2c_edma_RecSetting;
transferConfig.destAddr = (uint32_t) & (base->MDER);
@@ -386,8 +407,13 @@ status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base,
edma_tcd_t *tcdSetRxClearTxDMA = (edma_tcd_t *)((uint32_t)(&handle->tcds[2]) & (~ALIGN_32_MASK));
#if defined FSL_EDMA_DRIVER_EDMA4 && FSL_EDMA_DRIVER_EDMA4
EDMA_TcdResetExt(handle->rx->base, tcdSetRxClearTxDMA);
EDMA_TcdSetTransferConfigExt(handle->rx->base, tcdSetRxClearTxDMA, &transferConfig, tcd);
#else
EDMA_TcdReset(tcdSetRxClearTxDMA);
EDMA_TcdSetTransferConfig(tcdSetRxClearTxDMA, &transferConfig, tcd);
#endif
linkTcd = tcdSetRxClearTxDMA;
}
}
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpi2c_edma.h
+8 -8
View File
@@ -5,8 +5,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_LPI2C_EDMA_H_
#define _FSL_LPI2C_EDMA_H_
#ifndef FSL_LPI2C_EDMA_H_
#define FSL_LPI2C_EDMA_H_
#include "fsl_lpi2c.h"
#include "fsl_edma.h"
@@ -16,10 +16,10 @@
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @{ */
/*! @brief LPI2C EDMA driver version. */
#define FSL_LPI2C_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
/*@}*/
#define FSL_LPI2C_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
/*! @} */
/*!
* @addtogroup lpi2c_master_edma_driver
@@ -80,7 +80,7 @@ extern "C" {
*/
/*! @name Master DMA */
/*@{*/
/*! @{ */
/*!
* @brief Create a new handle for the LPI2C master DMA APIs.
@@ -147,7 +147,7 @@ status_t LPI2C_MasterTransferGetCountEDMA(LPI2C_Type *base, lpi2c_master_edma_ha
*/
status_t LPI2C_MasterTransferAbortEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle);
/*@}*/
/*! @} */
/*! @} */
@@ -155,4 +155,4 @@ status_t LPI2C_MasterTransferAbortEDMA(LPI2C_Type *base, lpi2c_master_edma_handl
}
#endif
#endif /* _FSL_LPI2C_EDMA_H_ */
#endif /* FSL_LPI2C_EDMA_H_ */
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpi2c_freertos.c
+1 -1
View File
@@ -15,7 +15,7 @@
static void LPI2C_RTOS_Callback(LPI2C_Type *base, lpi2c_master_handle_t *drv_handle, status_t status, void *userData)
{
lpi2c_rtos_handle_t *handle = (lpi2c_rtos_handle_t *)userData;
BaseType_t reschedule;
BaseType_t reschedule = pdFALSE;
handle->async_status = status;
(void)xSemaphoreGiveFromISR(handle->semaphore, &reschedule);
portYIELD_FROM_ISR(reschedule);
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpi2c_freertos.h
+2 -2
View File
@@ -25,8 +25,8 @@
/*! @name Driver version */
/*@{*/
/*! @brief LPI2C FreeRTOS driver version 2.0.8. */
#define FSL_LPI2C_FREERTOS_DRIVER_VERSION (MAKE_VERSION(1, 0, 0))
/*! @brief LPI2C FreeRTOS driver version 2.0.0. */
#define FSL_LPI2C_FREERTOS_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
/*@}*/
/*! @brief LPI2C FreeRTOS handle */
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpspi.c
+168 -43
View File
File diff suppressed because it is too large. Load diff
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpspi.h
+17 -25
View File
@@ -5,8 +5,8 @@
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_LPSPI_H_
#define _FSL_LPSPI_H_
#ifndef FSL_LPSPI_H_
#define FSL_LPSPI_H_
#include "fsl_common.h"
#include "fsl_lpflexcomm.h"
@@ -21,10 +21,10 @@
*********************************************************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @{ */
/*! @brief LPSPI driver version. */
#define FSL_LPSPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
/*@}*/
#define FSL_LPSPI_DRIVER_VERSION (MAKE_VERSION(2, 2, 6))
/*! @} */
#ifndef LPSPI_DUMMY_DATA
/*! @brief LPSPI dummy data if no Tx data.*/
@@ -180,10 +180,11 @@ typedef enum _lpspi_data_out_config
kLpspiDataOutTristate = 1U /*!< Data out is tristated when chip select is de-asserted */
} lpspi_data_out_config_t;
/*! @brief LPSPI cs function configuration. */
typedef enum _lpspi_pcs_function_config
{
kLPSPI_PcsAsCs = 0U,
kLPSPI_PcsAsData = 1U,
kLPSPI_PcsAsCs = 0U, /*!< PCS pin select as cs function */
kLPSPI_PcsAsData = 1U, /*!< PCS pin select as date function */
} lpspi_pcs_function_config_t;
/*! @brief LPSPI transfer width configuration. */
@@ -206,7 +207,7 @@ typedef enum _lpspi_delay_type
#define LPSPI_MASTER_PCS_MASK (0xF0U) /*!< LPSPI master PCS shift macro , internal used. */
#define LPSPI_MASTER_WIDTH_SHIFT (16U) /*!< LPSPI master width shift macro, internal used */
#define LPSPI_MASTER_WIDTH_MASK (0x30000U) /*!< LPSPI master width shift macro, internal used */
#define LPSPI_MASTER_WIDTH_MASK (0x30000U) /*!< LPSPI master width shift mask, internal used */
/*! @brief Use this enumeration for LPSPI master transfer configFlags. */
enum _lpspi_transfer_config_flag_for_master
@@ -219,7 +220,7 @@ enum _lpspi_transfer_config_flag_for_master
kLPSPI_MasterWidth1 = 0U << LPSPI_MASTER_WIDTH_SHIFT, /*!< LPSPI master transfer 1bit */
kLPSPI_MasterWidth2 = 1U << LPSPI_MASTER_WIDTH_SHIFT, /*!< LPSPI master transfer 2bit */
kLPSPI_MasterWidth4 = 2U << LPSPI_MASTER_WIDTH_SHIFT, /*!< LPSPI master transfer 4bit */
kLPSPI_MasterPcsContinuous = 1U << 20, /*!< Is PCS signal continuous */
kLPSPI_MasterByteSwap =
@@ -240,9 +241,6 @@ enum _lpspi_transfer_config_flag_for_master
#define LPSPI_SLAVE_PCS_SHIFT (4U) /*!< LPSPI slave PCS shift macro , internal used. */
#define LPSPI_SLAVE_PCS_MASK (0xF0U) /*!< LPSPI slave PCS shift macro , internal used. */
#define LPSPI_SLAVE_WIDTH_SHIFT (16U) /*!< LPSPI slave width shift macro, internal used */
#define LPSPI_SLAVE_WIDTH_MASK (0x30000U) /*!< LPSPI slave width shift macro, internal used */
/*! @brief Use this enumeration for LPSPI slave transfer configFlags. */
enum _lpspi_transfer_config_flag_for_slave
{
@@ -251,10 +249,6 @@ enum _lpspi_transfer_config_flag_for_slave
kLPSPI_SlavePcs2 = 2U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS2 signal */
kLPSPI_SlavePcs3 = 3U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS3 signal */
kLPSPI_SlaveWidth1 = 0U << LPSPI_SLAVE_WIDTH_SHIFT, /*!< LPSPI slave transfer 1bit */
kLPSPI_SlaveWidth2 = 1U << LPSPI_SLAVE_WIDTH_SHIFT, /*!< LPSPI slave transfer 2bit */
kLPSPI_SlaveWidth4 = 2U << LPSPI_SLAVE_WIDTH_SHIFT, /*!< LPSPI slave transfer 4bit */
kLPSPI_SlaveByteSwap =
1U << 22 /*!< Is slave swap the byte.
* For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set
@@ -299,8 +293,8 @@ typedef struct _lpspi_master_config
lpspi_pin_config_t pinCfg; /*!< Configures which pins are used for input and output data
*during single bit transfers.*/
lpspi_pcs_function_config_t pcsFunc;
lpspi_pcs_function_config_t pcsFunc; /*!< Configures cs pins function.*/
lpspi_data_out_config_t dataOutConfig; /*!< Configures if the output data is tristated
* between accesses (LPSPI_PCS is negated). */
@@ -322,8 +316,6 @@ typedef struct _lpspi_slave_config
lpspi_pin_config_t pinCfg; /*!< Configures which pins are used for input and output data
*during single bit transfers.*/
lpspi_pcs_function_config_t pcsFunc;
lpspi_data_out_config_t dataOutConfig; /*!< Configures if the output data is tristated
* between accesses (LPSPI_PCS is negated). */
} lpspi_slave_config_t;
@@ -367,7 +359,7 @@ typedef void (*lpspi_slave_transfer_callback_t)(LPSPI_Type *base,
/*! @brief LPSPI master/slave transfer structure.*/
typedef struct _lpspi_transfer
{
uint8_t *txData; /*!< Send buffer. */
const uint8_t *txData; /*!< Send buffer. */
uint8_t *rxData; /*!< Receive buffer. */
volatile size_t dataSize; /*!< Transfer bytes. */
@@ -393,7 +385,7 @@ struct _lpspi_master_handle
volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR. */
volatile uint8_t bytesEachRead; /*!< Bytes for each read RDR. */
uint8_t *volatile txData; /*!< Send buffer. */
const uint8_t *volatile txData; /*!< Send buffer. */
uint8_t *volatile rxData; /*!< Receive buffer. */
volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/
volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/
@@ -423,7 +415,7 @@ struct _lpspi_slave_handle
volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR. */
volatile uint8_t bytesEachRead; /*!< Bytes for each read RDR. */
uint8_t *volatile txData; /*!< Send buffer. */
const uint8_t *volatile txData; /*!< Send buffer. */
uint8_t *volatile rxData; /*!< Receive buffer. */
volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/
@@ -1165,7 +1157,7 @@ void LPSPI_SlaveTransferAbort(LPSPI_Type *base, lpspi_slave_handle_t *handle);
*
* This function processes the LPSPI transmit and receives an IRQ.
*
* @param base LPSPI instance.
* @param instance LPSPI instance index.
* @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state.
*/
void LPSPI_SlaveTransferHandleIRQ(uint32_t instance, lpspi_slave_handle_t *handle);
@@ -1180,4 +1172,4 @@ void LPSPI_SlaveTransferHandleIRQ(uint32_t instance, lpspi_slave_handle_t *handl
/*! @}*/
#endif /*_FSL_LPSPI_H_*/
#endif /*FSL_LPSPI_H_*/
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpspi_edma.c
+139 -51
View File
File diff suppressed because it is too large. Load diff
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpspi_edma.h
+48 -8
View File
@@ -5,8 +5,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_LPSPI_EDMA_H_
#define _FSL_LPSPI_EDMA_H_
#ifndef FSL_LPSPI_EDMA_H_
#define FSL_LPSPI_EDMA_H_
#include "fsl_lpspi.h"
#include "fsl_edma.h"
@@ -20,10 +20,10 @@
* Definitions
**********************************************************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @{ */
/*! @brief LPSPI EDMA driver version. */
#define FSL_LPSPI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
/*@}*/
#define FSL_LPSPI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
/*! @} */
/*!
* @brief Forward declaration of the _lpspi_master_edma_handle typedefs.
@@ -77,7 +77,7 @@ struct _lpspi_master_edma_handle
volatile uint8_t bytesLastRead; /*!< Bytes for last read RDR. */
volatile bool isThereExtraRxBytes; /*!< Is there extra RX byte. */
uint8_t *volatile txData; /*!< Send buffer. */
const uint8_t *volatile txData; /*!< Send buffer. */
uint8_t *volatile rxData; /*!< Receive buffer. */
volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/
volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/
@@ -122,7 +122,7 @@ struct _lpspi_slave_edma_handle
uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */
uint8_t *volatile txData; /*!< Send buffer. */
const uint8_t *volatile txData; /*!< Send buffer. */
uint8_t *volatile rxData; /*!< Receive buffer. */
volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/
volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/
@@ -202,6 +202,46 @@ void LPSPI_MasterTransferCreateHandleEDMA(LPSPI_Type *base,
*/
status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, lpspi_transfer_t *transfer);
/*!
* @brief LPSPI master config transfer parameter while using eDMA.
*
* This function is preparing to transfer data using eDMA, work with LPSPI_MasterTransferEDMALite.
*
* @param base LPSPI peripheral base address.
* @param handle pointer to lpspi_master_edma_handle_t structure which stores the transfer state.
* @param configFlags transfer configuration flags. @ref _lpspi_transfer_config_flag_for_master.
* @return Indicates whether LPSPI master transfer was successful or not.
* @retval kStatus_Success Execution successfully.
* @retval kStatus_LPSPI_Busy The LPSPI device is busy.
*/
status_t LPSPI_MasterTransferPrepareEDMALite(LPSPI_Type *base,
lpspi_master_edma_handle_t *handle,
uint32_t configFlags);
/*!
* @brief LPSPI master transfer data using eDMA without configs.
*
* This function transfers data using eDMA. This is a non-blocking function, which returns right away. When all data
* is transferred, the callback function is called.
*
* Note:
* This API is only for transfer through DMA without configuration.
* Before calling this API, you must call LPSPI_MasterTransferPrepareEDMALite to configure it once.
* The transfer data size should be an integer multiple of bytesPerFrame if bytesPerFrame is less than or equal to 4.
* For bytesPerFrame greater than 4:
* The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4.
* Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.
*
* @param base LPSPI peripheral base address.
* @param handle pointer to lpspi_master_edma_handle_t structure which stores the transfer state.
* @param transfer pointer to lpspi_transfer_t structure, config field is not uesed.
* @return Indicates whether LPSPI master transfer was successful or not.
* @retval kStatus_Success Execution successfully.
* @retval kStatus_LPSPI_Busy The LPSPI device is busy.
* @retval kStatus_InvalidArgument The transfer structure is invalid.
*/
status_t LPSPI_MasterTransferEDMALite(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, lpspi_transfer_t *transfer);
/*!
* @brief LPSPI master aborts a transfer which is using eDMA.
*
@@ -298,4 +338,4 @@ status_t LPSPI_SlaveTransferGetCountEDMA(LPSPI_Type *base, lpspi_slave_edma_hand
/*! @}*/
#endif /*_FSL_LPSPI_EDMA_H_*/
#endif /*FSL_LPSPI_EDMA_H_*/
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpspi_freertos.c
+1 -1
View File
@@ -15,7 +15,7 @@
static void LPSPI_RTOS_Callback(LPSPI_Type *base, lpspi_master_handle_t *drv_handle, status_t status, void *userData)
{
lpspi_rtos_handle_t *handle = (lpspi_rtos_handle_t *)userData;
BaseType_t reschedule;
BaseType_t reschedule = pdFALSE;
handle->async_status = status;
(void)xSemaphoreGiveFromISR(handle->event, &reschedule);
portYIELD_FROM_ISR(reschedule);
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpspi_freertos.h
+2 -2
View File
@@ -25,8 +25,8 @@
/*! @name Driver version */
/*@{*/
/*! @brief LPSPI FreeRTOS driver version 2.1.0. */
#define FSL_LPSPI_FREERTOS_DRIVER_VERSION (MAKE_VERSION(1, 0, 0))
/*! @brief LPSPI FreeRTOS driver version 2.0.0. */
#define FSL_LPSPI_FREERTOS_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
/*@}*/
/*! @brief LPSPI FreeRTOS handle */
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lptmr.c
+12 -2
View File
@@ -165,9 +165,19 @@ void LPTMR_GetDefaultConfig(lptmr_config_t *config)
#if !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT) && \
FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT)
config->prescalerClockSource = kLPTMR_PrescalerClock_1;
#else
#elif !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT) && \
FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT)
config->prescalerClockSource = kLPTMR_PrescalerClock_0;
#endif /* FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT */
#elif !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT) && \
FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT)
config->prescalerClockSource = kLPTMR_PrescalerClock_2;
#elif !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT) && \
FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT)
config->prescalerClockSource = kLPTMR_PrescalerClock_3;
#else
#error No valid source
#endif
/* Divide the prescaler clock by 2 */
config->value = kLPTMR_Prescale_Glitch_0;
}
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lptmr.h
+17 -7
View File
@@ -1,12 +1,12 @@
/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* Copyright 2016-2017, 2023 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_LPTMR_H_
#define _FSL_LPTMR_H_
#ifndef FSL_LPTMR_H_
#define FSL_LPTMR_H_
#include "fsl_common.h"
@@ -20,9 +20,10 @@
******************************************************************************/
/*! @name Driver version */
/*@{*/
#define FSL_LPTMR_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) /*!< Version 2.1.1 */
/*@}*/
/*! @{ */
/*! Driver Version */
#define FSL_LPTMR_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
/*! @} */
/*! @brief LPTMR pin selection used in pulse counter mode.*/
typedef enum _lptmr_pin_select
@@ -74,12 +75,21 @@ typedef enum _lptmr_prescaler_glitch_value
*/
typedef enum _lptmr_prescaler_clock_select
{
#if !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT) && \
FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT)
kLPTMR_PrescalerClock_0 = 0x0U, /*!< Prescaler/glitch filter clock 0 selected. */
#endif
#if !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT) && \
FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT)
kLPTMR_PrescalerClock_1 = 0x1U, /*!< Prescaler/glitch filter clock 1 selected. */
#endif /* FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT */
#if !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT) && \
FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT)
kLPTMR_PrescalerClock_2 = 0x2U, /*!< Prescaler/glitch filter clock 2 selected. */
#endif
#if !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT) && \
FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT)
kLPTMR_PrescalerClock_3 = 0x3U, /*!< Prescaler/glitch filter clock 3 selected. */
@@ -371,4 +381,4 @@ static inline void LPTMR_StopTimer(LPTMR_Type *base)
/*! @}*/
#endif /* _FSL_LPTMR_H_ */
#endif /* FSL_LPTMR_H_ */
bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpuart.c
+364 -32
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bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpuart.h
+118 -58
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